arm64: dts: Import devicetree sources for FP4
Change-Id: I0014ac226ae8b6a494ab53ee20f451d2cd057685
diff --git a/.gitignore b/.gitignore
index b0ea5a7..53929af 100644
--- a/.gitignore
+++ b/.gitignore
@@ -136,8 +136,5 @@
# fetched Android config fragments
kernel/configs/android-*.cfg
-# vendor device tree directories
-arch/arm64/boot/dts/vendor/
-
# Tech package directories
techpack/
diff --git a/arch/arm64/boot/dts/vendor b/arch/arm64/boot/dts/vendor
deleted file mode 120000
index c51d85f..0000000
--- a/arch/arm64/boot/dts/vendor
+++ /dev/null
@@ -1 +0,0 @@
-../../../../../../vendor/qcom/proprietary/devicetree-4.19
\ No newline at end of file
diff --git a/arch/arm64/boot/dts/vendor/Makefile b/arch/arm64/boot/dts/vendor/Makefile
new file mode 100755
index 0000000..855132a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/Makefile
@@ -0,0 +1,5 @@
+vendor := $(srctree)/$(src)
+
+ifneq "$(wildcard $(vendor)/qcom)" ""
+ subdir-y += qcom
+endif
diff --git a/arch/arm64/boot/dts/vendor/qcom/Makefile b/arch/arm64/boot/dts/vendor/qcom/Makefile
new file mode 100755
index 0000000..c811cf3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/Makefile
@@ -0,0 +1,410 @@
+ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
+ dtbo-$(CONFIG_ARCH_KONA) += \
+ kona-cdp-overlay.dtbo \
+ kona-cdp-lcd-overlay.dtbo \
+ kona-cdp-lcd-tron-overlay.dtbo \
+ kona-mtp-overlay.dtbo \
+ kona-mtp-ws-overlay.dtbo \
+ kona-sa-mtp-overlay.dtbo \
+ kona-xr-overlay.dtbo \
+ kona-rumi-overlay.dtbo \
+ kona-qrd-overlay.dtbo \
+ kona-xrfusion-overlay.dtbo \
+ kona-xrfusion-ult-overlay.dtbo \
+ kona-arglass-overlay.dtbo \
+ kona-hdk-overlay.dtbo
+
+kona-cdp-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+kona-cdp-lcd-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+kona-cdp-lcd-tron-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+kona-mtp-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+kona-mtp-ws-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+kona-sa-mtp-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+kona-xr-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+kona-rumi-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+kona-qrd-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+kona-xrfusion-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+kona-xrfusion-ult-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+kona-arglass-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+kona-hdk-overlay.dtbo-base := kona.dtb kona-v2.dtb kona-v2.1.dtb
+else
+dtb-$(CONFIG_ARCH_KONA) += kona-rumi.dtb \
+ kona-mtp.dtb \
+ kona-mtp-ws.dtb \
+ kona-mtp-sa.dtb \
+ kona-xr.dtb \
+ kona-xrfusion.dtb \
+ kona-xrfusion-ult.dtb \
+ kona-arglass.dtb \
+ kona-cdp.dtb \
+ kona-cdp-lcd.dtb \
+ kona-cdp-lcd-tron.dtb \
+ kona-qrd.dtb \
+ kona-v2-rumi.dtb \
+ kona-v2-mtp.dtb \
+ kona-v2-mtp-ws.dtb \
+ kona-v2-mtp-sa.dtb \
+ kona-v2-cdp.dtb \
+ kona-v2-qrd.dtb \
+ kona-v2-xrfusion.dtb \
+ kona-v2-xrfusion-ult.dtb \
+ kona-v2-arglass.dtb \
+ kona-hdk.dtb \
+ kona-v2.1-mtp.dtb \
+ kona-v2.1-mtp-ws.dtb \
+ kona-v2.1-mtp-sa.dtb \
+ kona-v2.1-cdp.dtb \
+ kona-v2.1-qrd.dtb \
+ kona-v2.1-hdk.dtb \
+ kona-v2.1-xrfusion.dtb \
+ kona-v2.1-xrfusion-ult.dtb \
+ kona-v2.1-arglass.dtb \
+ qrb5165-iot-rb5.dtb \
+ qrb5165n-iot-rb5.dtb \
+ kona-v2.1-iot-rb5.dtb
+endif
+
+ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
+dtbo-$(CONFIG_ARCH_LITO) += lito-rumi-overlay.dtbo \
+ lito-mtp-overlay.dtbo \
+ lito-v2-mtp-overlay.dtbo \
+ lito-cdp-overlay.dtbo \
+ lito-v2-cdp-overlay.dtbo \
+ lito-atp-overlay.dtbo \
+ lito-v2-atp-overlay.dtbo \
+ lito-v2-atp-lcd-overlay.dtbo \
+ lito-qrd-overlay.dtbo \
+ lito-v2-qrd-overlay.dtbo \
+ litomagnus-mtp-overlay.dtbo \
+ litomagnus-cdp-overlay.dtbo \
+ orchid-mtp-overlay.dtbo \
+ orchid-cdp-overlay.dtbo
+
+lito-rumi-overlay.dtbo-base := lito.dtb lito-v2.dtb
+lito-mtp-overlay.dtbo-base := lito.dtb
+lito-v2-mtp-overlay.dtbo-base := lito-v2.dtb
+lito-cdp-overlay.dtbo-base := lito.dtb
+lito-v2-cdp-overlay.dtbo-base := lito-v2.dtb
+lito-atp-overlay.dtbo-base := lito.dtb
+lito-v2-atp-overlay.dtbo-base := lito-v2.dtb
+lito-v2-atp-lcd-overlay.dtbo-base := lito-v2.dtb
+lito-qrd-overlay.dtbo-base := lito.dtb
+lito-v2-qrd-overlay.dtbo-base := lito-v2.dtb
+litomagnus-mtp-overlay.dtbo-base := litomagnus.dtb
+litomagnus-cdp-overlay.dtbo-base := litomagnus.dtb
+orchid-mtp-overlay.dtbo-base := orchid.dtb
+orchid-cdp-overlay.dtbo-base := orchid.dtb
+else
+dtb-$(CONFIG_ARCH_LITO) += lito-rumi.dtb \
+ lito-mtp.dtb \
+ lito-cdp.dtb \
+ lito-atp.dtb \
+ lito-qrd.dtb \
+ lito-v2-mtp.dtb \
+ lito-v2-cdp.dtb \
+ lito-v2-atp.dtb \
+ lito-v2-atp-lcd.dtb \
+ lito-v2-qrd.dtb \
+ litomagnus-mtp.dtb \
+ litomagnus-cdp.dtb \
+ orchid-mtp.dtb \
+ orchid-cdp.dtb
+endif
+
+ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
+dtbo-$(CONFIG_ARCH_LAGOON) += \
+ lagoon-rumi-overlay.dtbo \
+ lagoon-mtp-overlay.dtbo \
+ lagoon-mtp-usbc-overlay.dtbo \
+ lagoon-cdp-overlay.dtbo \
+ lagoon-atp-overlay.dtbo \
+ lagoon-qrd-overlay.dtbo \
+ lagoon-mtp-overlay_n10.dtbo \
+ lagoon-mtp-overlay_fp4.dtbo
+lagoon-rumi-overlay.dtbo-base := lagoon.dtb
+lagoon-mtp-overlay.dtbo-base := lagoon.dtb
+lagoon-mtp-usbc-overlay.dtbo-base := lagoon.dtb
+lagoon-cdp-overlay.dtbo-base := lagoon.dtb
+lagoon-atp-overlay.dtbo-base := lagoon.dtb
+lagoon-qrd-overlay.dtbo-base := lagoon.dtb
+lagoon-mtp-overlay_n10.dtbo-base := lagoon.dtb
+lagoon-mtp-overlay_fp4.dtbo-base := lagoon.dtb
+else
+dtb-$(CONFIG_ARCH_LAGOON) += \
+ lagoon-rumi.dtb \
+ lagoon-mtp.dtb \
+ lagoon-mtp-usbc.dtb \
+ lagoon-cdp.dtb \
+ lagoon-atp.dtb \
+ lagoon-qrd.dtb
+endif
+
+ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
+ dtbo-$(CONFIG_ARCH_BENGAL) += \
+ bengal-rumi-overlay.dtbo \
+ bengal-qrd-overlay.dtbo \
+ bengal-idp-overlay.dtbo \
+ bengal-idp-nopmi-overlay.dtbo \
+ bengal-idp-usbc-overlay.dtbo \
+ bengalp-idp-overlay.dtbo \
+ bengal-idp-1gb-overlay.dtbo \
+ bengal-idp-2gb-overlay.dtbo \
+ bengal-idp-usbc-1gb-overlay.dtbo \
+ bengal-idp-usbc-2gb-overlay.dtbo \
+ bengal-iot-idp-overlay.dtbo \
+ bengalp-iot-idp-overlay.dtbo \
+ bengal-iot-idp-2gb-overlay.dtbo \
+ bengal-iot-idp-usbc-2gb-overlay.dtbo \
+ bengal-iot-idp-usbc-overlay.dtbo \
+ bengalp-iot-idp-2gb-overlay.dtbo \
+ bengalp-iot-idp-usbc-2gb-overlay.dtbo \
+ bengalp-iot-idp-usbc-overlay.dtbo
+
+bengal-rumi-overlay.dtbo-base := bengal.dtb
+bengal-qrd-overlay.dtbo-base := bengal.dtb
+bengal-idp-overlay.dtbo-base := bengal.dtb
+bengal-idp-nopmi-overlay.dtbo-base := bengal.dtb
+bengal-idp-usbc-overlay.dtbo-base := bengal.dtb
+bengalp-idp-overlay.dtbo-base := bengalp.dtb
+bengal-idp-1gb-overlay.dtbo-base := bengal-1gb.dtb
+bengal-idp-2gb-overlay.dtbo-base := bengal-2gb.dtb
+bengal-idp-usbc-1gb-overlay.dtbo-base := bengal-1gb.dtb
+bengal-idp-usbc-2gb-overlay.dtbo-base := bengal-2gb.dtb
+bengal-iot-idp-overlay.dtbo-base := bengal-iot.dtb
+bengalp-iot-idp-overlay.dtbo-base := bengalp-iot.dtb
+bengal-iot-idp-2gb-overlay.dtbo-base := bengal-iot-2gb.dtb
+bengal-iot-idp-usbc-2gb-overlay.dtbo-base := bengal-iot-2gb.dtb
+bengal-iot-idp-usbc-overlay.dtbo-base := bengal-iot.dtb
+bengalp-iot-idp-2gb-overlay.dtbo-base := bengalp-iot-2gb.dtb
+bengalp-iot-idp-usbc-2gb-overlay.dtbo-base := bengalp-iot-2gb.dtb
+bengalp-iot-idp-usbc-overlay.dtbo-base := bengalp-iot.dtb
+else
+dtb-$(CONFIG_ARCH_BENGAL) += bengal-rumi.dtb \
+ bengal-qrd.dtb \
+ bengal-idp.dtb \
+ bengal-idp-nopmi.dtb \
+ bengal-idp-usbc.dtb \
+ bengalp-idp.dtb \
+ bengal-idp-1gb.dtb \
+ bengal-idp-2gb.dtb \
+ bengal-idp-usbc-1gb.dtb \
+ bengal-idp-usbc-2gb.dtb \
+ bengal-iot-idp.dtb \
+ bengalp-iot-idp.dtb \
+ bengal-iot-idp-2gb.dtb \
+ bengal-iot-idp-usbc-2gb.dtb \
+ bengal-iot-idp-usbc.dtb \
+ bengalp-iot-idp-2gb.dtb \
+ bengalp-iot-idp-usbc-2gb.dtb \
+ bengalp-iot-idp-usbc.dtb \
+ bengalp-iot-idp-2gb.dtb
+endif
+
+ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
+ dtbo-$(CONFIG_ARCH_SCUBA) += \
+ scuba-rumi-overlay.dtbo \
+ scuba-idp-overlay.dtbo \
+ scuba-idp-usbc-overlay.dtbo \
+ scuba-qrd-eldo-overlay.dtbo \
+ scuba-qrd-non-eldo-overlay.dtbo \
+ scuba-iot-idp-overlay.dtbo \
+ scuba-iot-idp-usbc-overlay.dtbo \
+ scuba-iot-qrd-eldo-overlay.dtbo \
+ scuba-iot-qrd-non-eldo-overlay.dtbo
+
+scuba-rumi-overlay.dtbo-base := scuba.dtb scubap.dtb scuba-2gb.dtb
+scuba-idp-overlay.dtbo-base := scuba.dtb scubap.dtb scuba-2gb.dtb
+scuba-qrd-eldo-overlay.dtbo-base := scuba.dtb scubap.dtb scuba-2gb.dtb
+scuba-qrd-non-eldo-overlay.dtbo-base := scuba.dtb scubap.dtb scuba-2gb.dtb
+scuba-idp-usbc-overlay.dtbo-base := scuba.dtb scubap.dtb scuba-2gb.dtb
+scuba-iot-idp-overlay.dtbo-base := scuba-iot.dtb scuba-iot-2gb.dtb scubap-iot.dtb scubap-iot-idp.dtb scubap-iot-idp-2gb.dtb
+scuba-iot-qrd-eldo-overlay.dtbo-base := scuba-iot.dtb scubap-iot.dtb scuba-iot-2gb.dtb
+scuba-iot-qrd-non-eldo-overlay.dtbo-base := scuba-iot.dtb scubap-iot.dtb scuba-iot-2gb.dtb
+scuba-iot-idp-usbc-overlay.dtbo-base := scuba-iot.dtb scubap-iot.dtb scuba-iot-2gb.dtb
+else
+dtb-$(CONFIG_ARCH_SCUBA) += scuba-rumi.dtb \
+ scuba-idp.dtb \
+ scuba-idp-usbc.dtb \
+ scuba-qrd-eldo.dtb \
+ scuba-qrd-non-eldo.dtb \
+ scubap-idp.dtb \
+ scubap-idp-2gb.dtb \
+ scuba-idp-2gb.dtb \
+ scuba-idp-usbc-2gb.dtb \
+ scuba-iot-idp.dtb \
+ scuba-iot-idp-usbc.dtb \
+ scubap-iot-idp.dtb \
+ scuba-iot-qrd-eldo.dtb \
+ scuba-iot-qrd-non-eldo.dtb \
+ scubap-iot-idp-2gb.dtb \
+ scuba-iot-idp-2gb.dtb \
+ scuba-iot-idp-usbc-2gb.dtb
+endif
+
+ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
+ dtbo-$(CONFIG_ARCH_KHAJE) += \
+ khaje-idp-overlay.dtbo \
+ khaje-qrd-overlay.dtbo \
+ khaje-qrd-hvdcp3p5-overlay.dtbo \
+ khaje-qrd-nowcd9375-overlay.dtbo \
+ khaje-idp-nopmi-overlay.dtbo \
+ khaje-idp-usbc-overlay.dtbo \
+ khaje-idp-pm8010-overlay.dtbo \
+ khaje-qrd-nopmi-overlay.dtbo \
+ khaje-idps-display-90hz-overlay.dtbo \
+ khaje-atp-overlay.dtbo
+
+khaje-idp-overlay.dtbo-base := khaje.dtb
+khaje-qrd-overlay.dtbo-base := khaje.dtb
+khaje-qrd-hvdcp3p5-overlay.dtbo-base := khaje.dtb
+khaje-qrd-nowcd9375-overlay.dtbo-base := khaje.dtb
+khaje-idp-nopmi-overlay.dtbo-base := khaje.dtb
+khaje-idp-usbc-overlay.dtbo-base := khaje.dtb
+khaje-idp-pm8010-overlay.dtbo-base := khaje.dtb
+khaje-qrd-nopmi-overlay.dtbo-base := khaje.dtb
+khaje-idps-display-90hz-overlay.dtbo-base := khaje.dtb
+khaje-atp-overlay.dtbo-base := khaje.dtb
+else
+dtb-$(CONFIG_ARCH_KHAJE) += khaje-idp.dtb \
+ khaje-qrd.dtb \
+ khaje-qrd-hvdcp3p5.dtb \
+ khaje-qrd-nowcd9375.dtb \
+ khaje-idp-nopmi.dtb \
+ khaje-idp-usbc.dtb \
+ khaje-idp-pm8010.dtb \
+ khaje-qrd-nopmi.dtb \
+ khaje-idps-display-90hz.dtb \
+ khaje-atp.dtb
+endif
+
+ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
+ dtbo-$(CONFIG_ARCH_SDM660) += \
+ sdm660-mtp-external-codec-overlay.dtbo \
+ sdm660-mtp-internal-codec-overlay.dtbo \
+ sdm660-cdp-external-codec-overlay.dtbo \
+ sdm660-cdp-internal-codec-overlay.dtbo \
+ sdm660-qrd-external-codec-overlay.dtbo \
+ sdm660-rcm-external-codec-overlay.dtbo \
+ sdm660-rcm-internal-codec-overlay.dtbo \
+ sda660-mtp-external-codec-overlay.dtbo \
+ sda660-cdp-external-codec-overlay.dtbo \
+ sda660-rcm-external-codec-overlay.dtbo
+
+sdm660-mtp-external-codec-overlay.dtbo-base := sdm660-pm660l.dtb
+
+sdm660-mtp-internal-codec-overlay.dtbo-base := sdm660-pm660l.dtb
+
+sdm660-cdp-external-codec-overlay.dtbo-base := sdm660-pm660l.dtb
+
+sdm660-cdp-internal-codec-overlay.dtbo-base := sdm660-pm660l.dtb
+
+sdm660-qrd-external-codec-overlay.dtbo-base := sdm660-pm660l.dtb
+
+sdm660-rcm-external-codec-overlay.dtbo-base := sdm660-pm660l.dtb
+
+sdm660-rcm-internal-codec-overlay.dtbo-base := sdm660-pm660l.dtb
+
+sda660-mtp-external-codec-overlay.dtbo-base := sda660-pm660l.dtb
+
+sda660-cdp-external-codec-overlay.dtbo-base := sda660-pm660l.dtb
+
+sda660-rcm-external-codec-overlay.dtbo-base := sda660-pm660l.dtb
+else
+dtb-$(CONFIG_ARCH_SDM660) += sdm660-sim.dtb \
+sdm660-internal-codec-cdp.dtb \
+ sdm660-internal-codec-mtp.dtb \
+ sdm660-internal-codec-rcm.dtb \
+ sdm660-cdp.dtb \
+ sdm660-mtp.dtb \
+ sdm660-qrd.dtb \
+ sdm660-rcm.dtb \
+ sdm660-pm660a-cdp.dtb \
+ sdm660-pm660a-mtp.dtb \
+ sdm660-pm660a-qrd.dtb \
+ sdm660-pm660a-rcm.dtb \
+ sdm660-internal-codec-pm660a-cdp.dtb \
+ sdm660-internal-codec-pm660a-mtp.dtb \
+ sdm660-internal-codec-pm660a-rcm.dtb \
+ sdm660-pm660a-sim.dtb \
+ sda660-cdp.dtb \
+ sda660-mtp.dtb \
+ sda660-rcm.dtb \
+ sda660-pm660a-cdp.dtb \
+ sda660-pm660a-mtp.dtb \
+ sda660-pm660a-rcm.dtb \
+ sda660-pm660a-qrd-hdk.dtb \
+ sdm660-headset-jacktype-no-cdp.dtb \
+ sdm660-headset-jacktype-no-rcm.dtb \
+ sdm660-pm660a-headset-jacktype-no-cdp.dtb \
+ sdm660-pm660a-headset-jacktype-no-rcm.dtb \
+ sdm660-usbc-audio-mtp.dtb \
+ sdm660-usbc-audio-rcm.dtb
+endif
+
+ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y)
+
+dtbo-$(CONFIG_ARCH_SDM439) += sdm439-mtp-overlay.dtbo \
+ sdm439-cdp-overlay.dtbo \
+ sdm439-qrd-overlay.dtbo \
+ sdm439-external-codec-mtp-overlay.dtbo \
+ sdm439-rcm-overlay.dtbo
+
+dtbo-$(CONFIG_ARCH_SDM429) += sdm429-mtp-overlay.dtbo \
+ sdm429-cdp-overlay.dtbo \
+ sdm429-qrd-overlay.dtbo
+
+dtbo-$(CONFIG_ARCH_QM215) +=qm215-qrd-overlay.dtbo \
+ qcm2150-qrd-overlay.dtbo \
+ qm215-qrd-smb1360-overlay.dtbo
+
+sdm439-mtp-overlay.dtbo-base := sdm439.dtb \
+ sda439.dtb \
+ msm8937-interposer-sdm439.dtb
+
+sdm439-cdp-overlay.dtbo-base := sdm439.dtb \
+ sda439.dtb \
+ msm8937-interposer-sdm439.dtb
+
+sdm439-qrd-overlay.dtbo-base := sdm439.dtb \
+ msm8937-interposer-sdm439.dtb
+
+sdm439-external-codec-mtp-overlay.dtbo-base := sdm439.dtb
+sdm439-rcm-overlay.dtbo-base := sdm439.dtb
+
+
+sdm429-mtp-overlay.dtbo-base := sdm429.dtb \
+ sda429.dtb \
+ msm8937-interposer-sdm429.dtb
+
+sdm429-cdp-overlay.dtbo-base := sdm429.dtb \
+ sda429.dtb \
+ msm8937-interposer-sdm429.dtb
+
+sdm429-qrd-overlay.dtbo-base := sdm429.dtb \
+ msm8937-interposer-sdm429.dtb
+
+qm215-qrd-overlay.dtbo-base := qm215.dtb
+qcm2150-qrd-overlay.dtbo-base := qcm2150.dtb
+qm215-qrd-smb1360-overlay.dtbo-base := qm215.dtb
+else
+dtb-$(CONFIG_ARCH_SDM439) += sdm439-mtp.dtb \
+ sdm439-cdp.dtb \
+ sdm439-qrd.dtb \
+ sda439-mtp.dtb \
+ sda439-cdp.dtb \
+ sdm439-external-codec-mtp.dtb \
+ sdm439-rcm.dtb
+dtb-$(CONFIG_ARCH_QM215) += qm215-qrd.dtb \
+ qcm2150-qrd.dtb \
+ qm215-qrd-smb1360.dtb
+
+dtb-$(CONFIG_ARCH_SDM429) += sdm429-mtp.dtb \
+ sdm429-cdp.dtb \
+ sdm429-qrd.dtb \
+ sda429-mtp.dtb \
+ sda429-cdp.dtb
+endif
+
+always := $(dtb-y)
+subdir-y := $(dts-dirs)
+clean-files := *.dtb *.dtbo
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-1gb.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-1gb.dts
new file mode 100755
index 0000000..e21f686
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-1gb.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "bengal-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Bengal 1Gb DDR HD+ SoC";
+ compatible = "qcom,bengal";
+ qcom,board-id = <0 0x303>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-2gb.dts
new file mode 100755
index 0000000..b4c7dda
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-2gb.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "bengal-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Bengal 2Gb DDR HD+ SoC";
+ compatible = "qcom,bengal";
+ qcom,board-id = <0 0x403>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-audio-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-audio-overlay.dtsi
new file mode 100755
index 0000000..29025c6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-audio-overlay.dtsi
@@ -0,0 +1,343 @@
+#include <dt-bindings/clock/qcom,audio-ext-clk.h>
+#include <dt-bindings/sound/qcom,bolero-clk-rsc.h>
+#include <dt-bindings/sound/audio-codec-port-types.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&bolero {
+ qcom,num-macros = <3>;
+ qcom,bolero-version = <5>;
+ bolero-clk-rsc-mngr {
+ compatible = "qcom,bolero-clk-rsc-mngr";
+ qcom,fs-gen-sequence = <0x3000 0x1>,
+ <0x3004 0x1>, <0x3080 0x2>;
+ qcom,rx_mclk_mode_muxsel = <0x0a5640d8>;
+ qcom,va_mclk_mode_muxsel = <0x0a7a0000>;
+ clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
+ "va_core_clk", "va_npl_clk";
+ clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
+ <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
+ <&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
+ };
+
+ tx_macro: tx-macro@a620000 {
+ compatible = "qcom,tx-macro";
+ reg = <0xa620000 0x0>;
+ clock-names = "tx_core_clk", "tx_npl_clk";
+ clocks = <&clock_audio_tx_1 0>,
+ <&clock_audio_tx_2 0>;
+ qcom,tx-dmic-sample-rate = <2400000>;
+ qcom,is-used-swr-gpio = <0>;
+ };
+
+ rx_macro: rx-macro@a600000 {
+ compatible = "qcom,rx-macro";
+ reg = <0xa600000 0x0>;
+ clock-names = "rx_core_clk", "rx_npl_clk";
+ clocks = <&clock_audio_rx_1 0>,
+ <&clock_audio_rx_2 0>;
+ qcom,rx-swr-gpios = <&rx_swr_gpios>;
+ qcom,rx_mclk_mode_muxsel = <0x0a5640d8>;
+ qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ swr1: rx_swr_master {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+ qcom,swr_master_id = <2>;
+ qcom,swrm-hctl-reg = <0x0a6a9098>;
+ qcom,mipi-sdw-block-packing-mode = <1>;
+ swrm-io-base = <0xa610000 0x0>;
+ interrupts = <0 297 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq";
+ qcom,swr-num-ports = <5>;
+ qcom,swr-port-mapping = <1 HPH_L 0x1>,
+ <1 HPH_R 0x2>, <2 CLSH 0x1>,
+ <3 COMP_L 0x1>, <3 COMP_R 0x2>,
+ <4 LO 0x1>, <5 DSD_L 0x1>,
+ <5 DSD_R 0x2>;
+ qcom,swr-num-dev = <1>;
+ qcom,disable-div2-clk-switch = <1>;
+ qcom,swr-clock-stop-mode0 = <1>;
+ wcd937x_rx_slave: wcd937x-rx-slave {
+ compatible = "qcom,wcd937x-slave";
+ reg = <0x0A 0x01170224>;
+ };
+ };
+ };
+
+ va_macro: va-macro@a730000 {
+ compatible = "qcom,va-macro";
+ reg = <0xa730000 0x0>;
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+ qcom,va-dmic-sample-rate = <600000>;
+ qcom,va-clk-mux-select = <1>;
+ qcom,va-island-mode-muxsel = <0x0a7a0000>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ qcom,is-used-swr-gpio = <1>;
+ qcom,va-swr-gpios = <&va_swr_gpios>;
+ swr0: va_swr_master {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+ qcom,swr_master_id = <3>;
+ qcom,swrm-hctl-reg = <0x0a7ec100>;
+ qcom,mipi-sdw-block-packing-mode = <1>;
+ swrm-io-base = <0xa740000 0x0>;
+ interrupts =
+ <0 296 IRQ_TYPE_LEVEL_HIGH>,
+ <0 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq", "swr_wake_irq";
+ qcom,swr-wakeup-required = <1>;
+ qcom,swr-num-ports = <3>;
+ qcom,swr-port-mapping = <1 ADC1 0x1>, <1 ADC2 0x2>,
+ <1 ADC3 0x4>, <1 ADC4 0x8>,
+ <2 DMIC0 0x1>, <2 DMIC1 0x2>,
+ <2 DMIC2 0x4>, <2 DMIC3 0x8>,
+ <3 DMIC4 0x1>, <3 DMIC5 0x2>,
+ <3 DMIC6 0x4>, <3 DMIC7 0x8>;
+ qcom,swr-num-dev = <1>;
+ qcom,swr-clock-stop-mode0 = <1>;
+ qcom,swr-mstr-irq-wakeup-capable = <1>;
+ wcd937x_tx_slave: wcd937x-tx-slave {
+ compatible = "qcom,wcd937x-slave";
+ reg = <0x0A 0x01170223>;
+ };
+ };
+ };
+
+ wcd937x_codec: wcd937x-codec {
+ compatible = "qcom,wcd937x-codec";
+ qcom,split-codec = <1>;
+ qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
+ <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
+ <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
+ <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
+ <4 DSD_R 0x2 0 DSD_R>;
+ qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
+ <1 ADC2 0x1 0 DMIC0>, <1 ADC3 0x2 0 DMIC1>,
+ <2 DMIC0 0x1 0 DMIC4>, <2 DMIC1 0x2 0 DMIC5>,
+ <2 MBHC 0x4 0 DMIC6>, <3 DMIC2 0x1 0 DMIC4>,
+ <3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>,
+ <3 DMIC5 0x8 0 DMIC7>;
+
+ qcom,wcd-rst-gpio-node = <&wcd937x_rst_gpio>;
+ qcom,rx-slave = <&wcd937x_rx_slave>;
+ qcom,tx-slave = <&wcd937x_tx_slave>;
+
+ cdc-vdd-rxtx-supply = <&L9A>;
+ qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-rxtx-current = <10000>;
+
+ cdc-vddpx-supply = <&L9A>;
+ qcom,cdc-vddpx-voltage = <1800000 1800000>;
+ qcom,cdc-vddpx-current = <20000>;
+
+ cdc-vdd-buck-supply = <&L14A>;
+ qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-buck-current = <650000>;
+
+ qcom,cdc-micbias1-mv = <1800>;
+ qcom,cdc-micbias2-mv = <1800>;
+ qcom,cdc-micbias3-mv = <1800>;
+
+ qcom,cdc-static-supplies = "cdc-vdd-rxtx",
+ "cdc-vddpx";
+ qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
+ };
+
+};
+
+&bengal_snd {
+ qcom,model = "bengal-idp-snd-card";
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
+ qcom,wcn-btfm = <1>;
+ qcom,va-bolero-codec = <1>;
+ qcom,rxtx-bolero-codec = <1>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic4",
+ "TX DMIC0", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic0",
+ "TX DMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic1",
+ "TX DMIC2", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic2",
+ "TX DMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic3",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "SpkrMono WSA_IN", "AUX",
+ "TX SWR_MIC0", "ADC1_OUTPUT",
+ "TX SWR_MIC4", "ADC2_OUTPUT",
+ "TX SWR_MIC5", "ADC3_OUTPUT",
+ "TX SWR_MIC8", "DMIC1_OUTPUT",
+ "TX SWR_MIC9", "DMIC2_OUTPUT",
+ "TX SWR_MIC8", "DMIC3_OUTPUT",
+ "TX SWR_MIC9", "DMIC4_OUTPUT",
+ "TX SWR_MIC10", "DMIC5_OUTPUT",
+ "TX SWR_MIC11", "DMIC6_OUTPUT",
+ "TX SWR_MIC0", "VA_TX_SWR_CLK",
+ "TX SWR_MIC1", "VA_TX_SWR_CLK",
+ "TX SWR_MIC2", "VA_TX_SWR_CLK",
+ "TX SWR_MIC3", "VA_TX_SWR_CLK",
+ "TX SWR_MIC4", "VA_TX_SWR_CLK",
+ "TX SWR_MIC5", "VA_TX_SWR_CLK",
+ "TX SWR_MIC6", "VA_TX_SWR_CLK",
+ "TX SWR_MIC7", "VA_TX_SWR_CLK",
+ "TX SWR_MIC8", "VA_TX_SWR_CLK",
+ "TX SWR_MIC9", "VA_TX_SWR_CLK",
+ "TX SWR_MIC10", "VA_TX_SWR_CLK",
+ "TX SWR_MIC11", "VA_TX_SWR_CLK",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "TX_AIF1 CAP", "VA_TX_SWR_CLK",
+ "TX_AIF2 CAP", "VA_TX_SWR_CLK",
+ "TX_AIF3 CAP", "VA_TX_SWR_CLK",
+ "VA DMIC0", "VA MIC BIAS1",
+ "VA DMIC1", "VA MIC BIAS1",
+ "VA DMIC2", "VA MIC BIAS3",
+ "VA DMIC3", "VA MIC BIAS3",
+ "VA MIC BIAS1", "Digital Mic0",
+ "VA MIC BIAS1", "Digital Mic1",
+ "VA MIC BIAS3", "Digital Mic2",
+ "VA MIC BIAS3", "Digital Mic3",
+ "VA SWR_MIC0", "ADC1_OUTPUT",
+ "VA SWR_MIC4", "ADC2_OUTPUT",
+ "VA SWR_MIC5", "ADC3_OUTPUT",
+ "VA SWR_MIC8", "DMIC1_OUTPUT",
+ "VA SWR_MIC9", "DMIC2_OUTPUT",
+ "VA SWR_MIC8", "DMIC3_OUTPUT",
+ "VA SWR_MIC9", "DMIC4_OUTPUT",
+ "VA SWR_MIC10", "DMIC5_OUTPUT",
+ "VA SWR_MIC11", "DMIC6_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
+ qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
+
+ nvmem-cells = <&adsp_variant>;
+ nvmem-cell-names = "adsp_variant";
+
+ asoc-codec = <&stub_codec>, <&bolero>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec";
+ qcom,wsa-max-devs = <1>;
+ qcom,wsa-devs = <&wsa881x_i2c_e>;
+ qcom,wsa-aux-dev-prefix = "SpkrMono";
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&wcd937x_codec>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&bolero>,
+ <&lpi_tlmm>;
+};
+
+&qupv3_se1_i2c {
+ wsa881x_i2c_e: wsa881x-i2c-codec@e {
+ compatible = "qcom,wsa881x-i2c-codec";
+ reg = <0x0e>;
+ clock-names = "wsa_mclk";
+ clocks = <&wsa881x_analog_clk 0>;
+ qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>;
+ qcom,wsa-analog-reset-gpio = <&wsa881x_analog_reset_gpio>;
+ };
+
+ wsa881x_i2c_44: wsa881x-i2c-codec@44 {
+ compatible = "qcom,wsa881x-i2c-codec";
+ reg = <0x044>;
+ };
+};
+
+&soc {
+ wcd937x_rst_gpio: msm_cdc_pinctrl@92 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wcd937x_reset_active>;
+ pinctrl-1 = <&wcd937x_reset_sleep>;
+ };
+
+ wsa881x_analog_reset_gpio: msm_cdc_pinctrl@106 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ pinctrl-1 = <&spkr_1_sd_n_sleep>;
+ };
+
+ wsa881x_analog_clk: wsa_ana_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
+ qcom,codec-lpass-ext-clk-freq = <9600000>;
+ qcom,codec-lpass-clk-id = <0x301>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_rx_1: rx_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
+ qcom,codec-lpass-ext-clk-freq = <22579200>;
+ qcom,codec-lpass-clk-id = <0x30E>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_rx_2: rx_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>;
+ qcom,codec-lpass-ext-clk-freq = <22579200>;
+ qcom,codec-lpass-clk-id = <0x30F>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_tx_1: tx_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30C>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_tx_2: tx_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30D>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_va_1: va_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30B>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_va_2: va_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_8>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x310>;
+ #clock-cells = <1>;
+ };
+};
+
+&va_cdc_dma_0_tx {
+ qcom,msm-dai-is-island-supported = <1>;
+};
+
+&adsp_loader {
+ nvmem-cells = <&adsp_variant>;
+ nvmem-cell-names = "adsp_variant";
+ adsp-fw-names = "adsp2";
+ adsp-fw-bit-values = <0x1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-audio.dtsi
new file mode 100755
index 0000000..0bffa0e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-audio.dtsi
@@ -0,0 +1,185 @@
+#include <dt-bindings/clock/qcom,audio-ext-clk.h>
+#include "msm-audio-lpass.dtsi"
+
+&msm_audio_ion {
+ iommus = <&apps_smmu 0x01c1 0x0>;
+ qcom,smmu-sid-mask = /bits/ 64 <0xf>;
+};
+
+&audio_apr {
+ q6core: qcom,q6core-audio {
+ compatible = "qcom,q6core-audio";
+
+ lpass_audio_hw_vote: vote_lpass_audio_hw {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_AUDIO_HW_VOTE>;
+ #clock-cells = <1>;
+ };
+ };
+};
+
+#include "bengal-lpi.dtsi"
+
+&q6core {
+ cdc_dmic01_gpios: cdc_dmic01_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
+ pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ cdc_dmic23_gpios: cdc_dmic23_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
+ pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ rx_swr_gpios: rx_swr_clk_data_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
+ &rx_swr_data1_active>;
+ pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
+ &rx_swr_data1_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ va_swr_gpios: va_swr_clk_data_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active
+ &tx_swr_data2_active>;
+ pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep
+ &tx_swr_data2_sleep>;
+ qcom,lpi-gpios;
+ qcom,chip-wakeup-reg = <0x003ca04c>;
+ qcom,chip-wakeup-maskbit = <0>;
+ qcom,chip-wakeup-default-val = <0x1>;
+ };
+
+ wsa881x_analog_clk_gpio: msm_cdc_pinctrl@18 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wsa_mclk_active>;
+ pinctrl-1 = <&wsa_mclk_sleep>;
+ qcom,lpi-gpios;
+ };
+};
+
+&q6core {
+ bolero: bolero-cdc {
+ compatible = "qcom,bolero-codec";
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+
+ bolero-clk-rsc-mngr {
+ compatible = "qcom,bolero-clk-rsc-mngr";
+ };
+
+ va_macro: va-macro@a730000 {
+ swr0: va_swr_master {
+ };
+ };
+
+ rx_macro: rx-macro@a600000 {
+ swr1: rx_swr_master {
+ };
+ };
+ };
+};
+
+&q6core {
+ bengal_snd: sound {
+ compatible = "qcom,bengal-asoc-snd";
+ qcom,mi2s-audio-intf = <0>;
+ qcom,auxpcm-audio-intf = <0>;
+ qcom,tdm-audio-intf = <0>;
+ qcom,wcn-btfm = <1>;
+ qcom,afe-rxtx-lb = <0>;
+
+ asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
+ <&loopback>, <&compress>, <&hostless>,
+ <&afe>, <&lsm>, <&routing>, <&compr>,
+ <&pcm_noirq>;
+ asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
+ "msm-pcm-dsp.2", "msm-voip-dsp",
+ "msm-pcm-voice", "msm-pcm-loopback",
+ "msm-compress-dsp", "msm-pcm-hostless",
+ "msm-pcm-afe", "msm-lsm-client",
+ "msm-pcm-routing", "msm-compr-dsp",
+ "msm-pcm-dsp-noirq";
+ asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>,
+ <&dai_mi2s2>, <&dai_mi2s3>,
+ <&dai_pri_auxpcm>,
+ <&dai_sec_auxpcm>, <&dai_tert_auxpcm>,
+ <&dai_quat_auxpcm>,
+ <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>,
+ <&afe_proxy_tx>, <&incall_record_rx>,
+ <&incall_record_tx>, <&incall_music_rx>,
+ <&incall_music_2_rx>,
+ <&proxy_rx>, <&proxy_tx>,
+ <&usb_audio_rx>, <&usb_audio_tx>,
+ <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>,
+ <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>,
+ <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>,
+ <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>,
+ <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>,
+ <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>,
+ <&va_cdc_dma_2_tx>,
+ <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>,
+ <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>,
+ <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>,
+ <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>,
+ <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>,
+ <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>,
+ <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>,
+ <&afe_loopback_tx>;
+ asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",
+ "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",
+ "msm-dai-q6-auxpcm.1",
+ "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3",
+ "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224",
+ "msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
+ "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
+ "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
+ "msm-dai-q6-dev.32770",
+ "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195",
+ "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673",
+ "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399",
+ "msm-dai-q6-dev.16401",
+ "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865",
+ "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881",
+ "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897",
+ "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913",
+ "msm-dai-cdc-dma-dev.45089",
+ "msm-dai-cdc-dma-dev.45091",
+ "msm-dai-cdc-dma-dev.45093",
+ "msm-dai-cdc-dma-dev.45104",
+ "msm-dai-cdc-dma-dev.45105",
+ "msm-dai-cdc-dma-dev.45106",
+ "msm-dai-cdc-dma-dev.45107",
+ "msm-dai-cdc-dma-dev.45108",
+ "msm-dai-cdc-dma-dev.45109",
+ "msm-dai-cdc-dma-dev.45110",
+ "msm-dai-cdc-dma-dev.45111",
+ "msm-dai-cdc-dma-dev.45112",
+ "msm-dai-cdc-dma-dev.45113",
+ "msm-dai-cdc-dma-dev.45114",
+ "msm-dai-cdc-dma-dev.45115",
+ "msm-dai-cdc-dma-dev.45116",
+ "msm-dai-cdc-dma-dev.45118",
+ "msm-dai-q6-dev.24577";
+ fsa4480-i2c-handle = <&fsa4480>;
+ };
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ fsa4480: fsa4480@42 {
+ compatible = "qcom,fsa4480-i2c";
+ reg = <0x42>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-bus.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-bus.dtsi
new file mode 100755
index 0000000..1932f9d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-bus.dtsi
@@ -0,0 +1,1081 @@
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+
+&soc {
+ ad_hoc_bus: ad-hoc-bus {
+ compatible = "qcom,msm-bus-device";
+ reg = <0x1880000 0x60200>,
+ <0x4480000 0x80000>,
+ <0x1900000 0x8200>,
+ <0x1880000 0x60200>,
+ <0x1880000 0x60200>,
+ <0x1880000 0x60200>,
+ <0x1880000 0x60200>;
+ reg-names = "sys_noc-base", "bimc-base", "config_noc-base",
+ "qup_virt-base", "fab-gpu_vert-base",
+ "mmnrt_virt-base", "mmrt_virt-base";
+
+ /*Buses*/
+
+ fab_bimc: fab-bimc {
+ cell-id = <MSM_BUS_FAB_BIMC>;
+ label = "fab-bimc";
+ qcom,fab-dev;
+ qcom,base-name = "bimc-base";
+ qcom,bus-type = <2>;
+ qcom,util-fact = <153>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc BIMC_MSMBUS_CLK>,
+ <&rpmcc BIMC_MSMBUS_A_CLK>;
+ };
+
+ fab_config_noc: fab-config_noc {
+ cell-id = <MSM_BUS_FAB_CONFIG_NOC>;
+ label = "fab-config_noc";
+ qcom,fab-dev;
+ qcom,base-name = "config_noc-base";
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc CNOC_MSMBUS_CLK>,
+ <&rpmcc CNOC_MSMBUS_A_CLK>;
+ };
+
+ fab_qup_virt: fab-qup_virt {
+ cell-id = <MSM_BUS_FAB_QUP_VIRT>;
+ label = "fab-qup_virt";
+ qcom,fab-dev;
+ qcom,base-name = "qup_virt-base";
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc RPM_SMD_QUP_CLK>,
+ <&rpmcc RPM_SMD_QUP_A_CLK>;
+ };
+
+ fab_sys_noc: fab-sys_noc {
+ cell-id = <MSM_BUS_FAB_SYS_NOC>;
+ label = "fab-sys_noc";
+ qcom,fab-dev;
+ qcom,base-name = "sys_noc-base";
+ qcom,bus-type = <3>;
+ qcom,base-offset = <0x15000>;
+ qcom,qos-off = <0x1000>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc SNOC_MSMBUS_CLK>,
+ <&rpmcc SNOC_MSMBUS_A_CLK>;
+ };
+
+ fab_gpu_vert: fab-gpu_vert {
+ cell-id = <MSM_BUS_FAB_GPU_VIRT>;
+ label = "fab-gpu_vert";
+ qcom,vert-dev;
+ qcom,base-name = "fab-gpu_vert-base";
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ };
+
+ fab_mmnrt_virt: fab-mmnrt_virt {
+ cell-id = <MSM_BUS_FAB_MMNRT_VIRT>;
+ label = "fab-mmnrt_virt";
+ qcom,fab-dev;
+ qcom,base-name = "mmnrt_virt-base";
+ qcom,bus-type = <3>;
+ qcom,base-offset = <0x15000>;
+ qcom,qos-off = <0x1000>;
+ qcom,util-fact = <142>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc CPP_MMNRT_MSMBUS_CLK>,
+ <&rpmcc CPP_MMNRT_MSMBUS_A_CLK>;
+ };
+
+ fab_mmrt_virt: fab-mmrt_virt {
+ cell-id = <MSM_BUS_FAB_MMRT_VIRT>;
+ label = "fab-mmrt_virt";
+ qcom,fab-dev;
+ qcom,base-name = "mmrt_virt-base";
+ qcom,bus-type = <3>;
+ qcom,base-offset = <0x15000>;
+ qcom,qos-off = <0x1000>;
+ qcom,util-fact = <139>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc MDP_MMRT_MSMBUS_CLK>,
+ <&rpmcc MDP_MMRT_MSMBUS_A_CLK>;
+ };
+
+ /*Masters*/
+
+ mas_apps_proc: mas-apps-proc {
+ cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
+ label = "mas-apps-proc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,prio-lvl = <0>;
+ qcom,prio-rd = <0>;
+ qcom,prio-wr = <0>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_APPSS_PROC>;
+ };
+
+ mas_snoc_bimc_rt: mas-snoc-bimc-rt {
+ cell-id = <MSM_BUS_MASTER_SNOC_BIMC_RT>;
+ label = "mas-snoc-bimc-rt";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_ebi>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_RT>;
+ };
+
+ mas_snoc_bimc_nrt: mas-snoc-bimc-nrt {
+ cell-id = <MSM_BUS_MASTER_SNOC_BIMC_NRT>;
+ label = "mas-snoc-bimc-nrt";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <3>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_ebi>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_NRT>;
+ };
+
+ mas_snoc_bimc: mas-snoc-bimc {
+ cell-id = <MSM_BUS_SNOC_BIMC_MAS>;
+ label = "mas-snoc-bimc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <6>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_ebi>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC>;
+ };
+
+ mas_gpu_cdsp_bimc: mas-gpu-cdsp-bimc {
+ cell-id = <MSM_BUS_MASTER_GPU_CDSP_PROC>;
+ label = "mas-gpu-cdsp-bimc";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_GPU_CDSP_PROC>;
+ };
+
+ mas_tcu_0: mas-tcu-0 {
+ cell-id = <MSM_BUS_MASTER_TCU_0>;
+ label = "mas-tcu-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <4>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,prio-lvl = <6>;
+ qcom,prio-rd = <6>;
+ qcom,prio-wr = <6>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_TCU_0>;
+ };
+
+ mas_snoc_cnoc: mas-snoc-cnoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_MAS>;
+ label = "mas-snoc-cnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_qhs_tlmm_south
+ &slv_qhs_camera_rt_throttle_cfg
+ &slv_qhs_cdsp_throttle_cfg
+ &slv_srvc_cnoc &slv_qhs_sdc2
+ &slv_qhs_sdc1
+ &slv_qhs_qm_cfg &slv_qhs_tlmm_east
+ &slv_qhs_bimc_cfg &slv_qhs_usb3
+ &slv_qhs_qm_mpu_cfg
+ &slv_qhs_camera_nrt_throttle_cfg
+ &slv_qhs_tlmm_west &slv_qhs_qdss_cfg
+ &slv_qhs_pdm &slv_qhs_ipa_cfg
+ &slv_qhs_display_throttle_cfg &slv_qhs_tcsr
+ &slv_qhs_mesg_ram
+ &slv_qhs_pmic_arb
+ &slv_qhs_lpass
+ &slv_qhs_disp_ss_cfg
+ &slv_qhs_venus_cfg
+ &slv_qhs_gpu_cfg
+ &slv_qhs_imem_cfg &slv_snoc_cfg
+ &slv_qhs_ufs_mem_cfg
+ &slv_qhs_venus_throttle_cfg
+ &slv_qhs_prng
+ &slv_qhs_vsense_ctrl_cfg
+ &slv_qhs_crypto0_cfg &slv_qhs_pimem_cfg
+ &slv_qhs_qup0
+ &slv_qhs_camera_ss_cfg &slv_qhs_clk_ctl>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_CNOC>;
+ };
+
+ mas_xm_dap: mas-xm-dap {
+ cell-id = <MSM_BUS_MASTER_QDSS_DAP>;
+ label = "mas-xm-dap";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_qhs_tlmm_south
+ &slv_qhs_camera_rt_throttle_cfg
+ &slv_qhs_cdsp_throttle_cfg
+ &slv_srvc_cnoc &slv_qhs_sdc2
+ &slv_qhs_sdc1
+ &slv_qhs_qm_cfg &slv_qhs_tlmm_east
+ &slv_qhs_bimc_cfg &slv_qhs_usb3
+ &slv_qhs_qm_mpu_cfg
+ &slv_qhs_camera_nrt_throttle_cfg
+ &slv_qhs_tlmm_west &slv_qhs_qdss_cfg
+ &slv_qhs_pdm &slv_qhs_ipa_cfg
+ &slv_qhs_display_throttle_cfg &slv_qhs_tcsr
+ &slv_qhs_mesg_ram
+ &slv_qhs_pmic_arb
+ &slv_qhs_lpass
+ &slv_qhs_disp_ss_cfg
+ &slv_qhs_venus_cfg
+ &slv_qhs_gpu_cfg
+ &slv_qhs_imem_cfg &slv_snoc_cfg
+ &slv_qhs_ufs_mem_cfg
+ &slv_qhs_venus_throttle_cfg
+ &slv_qhs_prng
+ &slv_qhs_vsense_ctrl_cfg
+ &slv_qhs_crypto0_cfg &slv_qhs_pimem_cfg
+ &slv_qhs_qup0
+ &slv_qhs_camera_ss_cfg &slv_qhs_clk_ctl>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_DAP>;
+ };
+
+ mas_crypto_c0: mas-crypto-c0 {
+ cell-id = <MSM_BUS_MASTER_CRYPTO_CORE0>;
+ label = "mas-crypto-c0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <22>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ clock-names = "node_clk", "node_a_clk";
+ clocks = <&rpmcc CRYPTO_MSMBUS_SNOC_PERIPH_CLK>,
+ <&rpmcc CRYPTO_MSMBUS_SNOC_PERIPH_A_CLK>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO_CORE0>;
+ };
+
+ mas_qup_core_master_0: mas-qup-core-master-0 {
+ cell-id = <MSM_BUS_MASTER_QUP_CORE_0>;
+ label = "mas-qup-core-master-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qup_core_slave_0>;
+ qcom,bus-dev = <&fab_qup_virt>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QUP_CORE_0>;
+ };
+
+ mas_snoc_cfg: mas-snoc-cfg {
+ cell-id = <MSM_BUS_MASTER_SNOC_CFG>;
+ label = "mas-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_srvc_snoc>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_CFG>;
+ };
+
+ mas_qhm_tic: mas-qhm-tic {
+ cell-id = <MSM_BUS_MASTER_TIC>;
+ label = "mas-qhm-tic";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_qxs_pimem &slv_qxs_imem
+ &slv_qhs_apss &slv_snoc_bimc &slv_snoc_cnoc
+ &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_TIC>;
+ };
+
+ mas_anoc_snoc: mas-anoc-snoc {
+ cell-id = <MSM_BUS_MASTER_ANOC_SNOC>;
+ label = "mas-anoc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qxs_pimem &slv_qxs_imem
+ &slv_qhs_apss &slv_snoc_bimc
+ &slv_snoc_cnoc &slv_xs_sys_tcu_cfg
+ &slv_xs_qdss_stm>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_A0NOC_SNOC>;
+ };
+
+ mas_qnm_camera_nrt: mas-qnm-camera-nrt {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_SF>;
+ label = "mas-qnm-camera-nrt";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <4>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_snoc_bimc_nrt>;
+ qcom,prio = <3>;
+ qcom,bus-dev = <&fab_mmnrt_virt>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CAMNOC_SF>;
+ };
+
+ mas_qnm_camera_rt: mas-qnm-camera-rt {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_HF>;
+ label = "mas-qnm-camera-rt";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <10>;
+ qcom,qos-mode = "fixed";
+ qcom,forwarding;
+ qcom,connections = <&slv_snoc_bimc_rt>;
+ qcom,prio = <2>;
+ qcom,bus-dev = <&fab_mmrt_virt>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CAMNOC_HF>;
+ };
+
+ mas_bimc_snoc: mas-bimc-snoc {
+ cell-id = <MSM_BUS_BIMC_SNOC_MAS>;
+ label = "mas-bimc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qxs_pimem &slv_qxs_imem
+ &slv_qhs_apss &slv_snoc_cnoc
+ &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BIMC_SNOC>;
+ };
+
+ mas_qxm_mdp0: mas-qxm-mdp0 {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT0>;
+ label = "mas-qxm-mdp0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <5>;
+ qcom,qos-mode = "fixed";
+ qcom,prio = <2>;
+ qcom,forwarding;
+ qcom,connections = <&slv_snoc_bimc_rt>;
+ qcom,bus-dev = <&fab_mmrt_virt>;
+ qcom,mas-rpm-id = <ICBID_MASTER_MDP0>;
+ };
+
+ mas_qxm_pimem: mas-qxm-pimem {
+ cell-id = <MSM_BUS_MASTER_PIMEM>;
+ label = "mas-qxm-pimem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <20>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_qxs_imem &slv_snoc_bimc>;
+ qcom,prio = <2>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PIMEM>;
+ };
+
+ mas_qxm_venus0: mas-qxm-venus0 {
+ cell-id = <MSM_BUS_MASTER_VIDEO_P0>;
+ label = "mas-qxm-venus0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <9>;
+ qcom,qos-mode = "fixed";
+ qcom,prio = <3>;
+ qcom,forwarding;
+ qcom,connections = <&slv_snoc_bimc_nrt>;
+ qcom,bus-dev = <&fab_mmnrt_virt>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VIDEO_P0>;
+ };
+
+ mas_qxm_venus_cpu: mas-qxm-venus-cpu {
+ cell-id = <MSM_BUS_MASTER_VIDEO_PROC>;
+ label = "mas-qxm-venus-cpu";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <13>;
+ qcom,qos-mode = "fixed";
+ qcom,prio = <4>;
+ qcom,forwarding;
+ qcom,connections = <&slv_snoc_bimc_nrt>;
+ qcom,bus-dev = <&fab_mmnrt_virt>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VIDEO_PROC>;
+ };
+
+ mas_qhm_qdss_bam: mas-qhm-qdss-bam {
+ cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
+ label = "mas-qhm-qdss-bam";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAM>;
+ };
+
+ mas_qhm_qup0: mas-qhm-qup0 {
+ cell-id = <MSM_BUS_MASTER_QUP_0>;
+ label = "mas-qhm-qup0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ clock-names = "node_clk", "node_a_clk";
+ clocks = <&rpmcc QUP0_MSMBUS_SNOC_PERIPH_CLK>,
+ <&rpmcc QUP0_MSMBUS_SNOC_PERIPH_A_CLK>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QUP_0>;
+ };
+
+ mas_qxm_ipa: mas-qxm-ipa {
+ cell-id = <MSM_BUS_MASTER_IPA>;
+ label = "mas-qxm-ipa";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <3>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_IPA>;
+ };
+
+ mas_xm_qdss_etr: mas-xm-qdss-etr {
+ cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
+ label = "mas-xm-qdss-etr";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <12>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>;
+ };
+
+ mas_xm_sdc1: mas-xm-sdc1 {
+ cell-id = <MSM_BUS_MASTER_SDCC_1>;
+ label = "mas-xm-sdc1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <17>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ clock-names = "node_clk", "node_a_clk";
+ clocks = <&rpmcc SDC1_MSMBUS_SNOC_PERIPH_CLK>,
+ <&rpmcc SDC1_MSMBUS_SNOC_PERIPH_A_CLK>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SDCC_1>;
+ };
+
+ mas_xm_sdc2: mas-xm-sdc2 {
+ cell-id = <MSM_BUS_MASTER_SDCC_2>;
+ label = "mas-xm-sdc2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <23>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ clock-names = "node_clk", "node_a_clk";
+ clocks = <&rpmcc SDC2_MSMBUS_SNOC_PERIPH_CLK>,
+ <&rpmcc SDC2_MSMBUS_SNOC_PERIPH_A_CLK>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SDCC_2>;
+ };
+
+ mas_xm_ufs_mem: mas-xm-ufs-mem {
+ cell-id = <MSM_BUS_MASTER_UFS_MEM>;
+ label = "mas-xm-ufs-mem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <25>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ clock-names = "node_clk", "node_a_clk";
+ clocks = <&rpmcc RPM_SMD_SNOC_LPASS_CLK>,
+ <&rpmcc RPM_SMD_SNOC_LPASS_A_CLK>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_UFS_MEM>;
+ };
+
+ mas_xm_usb3_0: mas-xm-usb3-0 {
+ cell-id = <MSM_BUS_MASTER_USB3>;
+ label = "mas-xm-usb3-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <24>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_USB3_0>;
+ };
+
+ mas_qnm_gpu_qos: mas-qnm-gpu-qos {
+ cell-id = <MSM_BUS_MASTER_GRAPHICS_3D_PORT1>;
+ label = "mas-qnm-gpu-qos";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <16>;
+ qcom,qos-mode = "fixed";
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,prio = <0>;
+ qcom,mas-rpm-id = <ICBID_MASTER_GFX3D>;
+ };
+
+ mas_qnm_gpu: mas-qnm-gpu {
+ cell-id = <MSM_BUS_MASTER_GRAPHICS_3D>;
+ label = "mas-qnm-gpu";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_gpu_cdsp_bimc>;
+ qcom,bus-dev = <&fab_gpu_vert>;
+ qcom,mas-rpm-id = <ICBID_MASTER_GFX3D>;
+ };
+
+ /*Slaves*/
+
+ slv_ebi:slv-ebi {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ label = "slv-ebi";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_EBI1>;
+ };
+
+ slv_bimc_snoc:slv-bimc-snoc {
+ cell-id = <MSM_BUS_BIMC_SNOC_SLV>;
+ label = "slv-bimc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,connections = <&mas_bimc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_SNOC>;
+ };
+
+ slv_qhs_bimc_cfg:slv-qhs-bimc-cfg {
+ cell-id = <MSM_BUS_SLAVE_BIMC_CFG>;
+ label = "slv-qhs-bimc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_CFG>;
+ };
+
+ slv_qhs_camera_nrt_throttle_cfg:slv-qhs-camera-nrt-throtle-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_NRT_THROTTLE_CFG>;
+ label = "slv-qhs-camera-nrt-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_NRT_THROTTLE_CFG>;
+ };
+
+ slv_qhs_camera_rt_throttle_cfg:slv-qhs-camera-rt-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_RT_THROTTLE_CFG>;
+ label = "slv-qhs-camera-rt-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_RT_THROTTLE_CFG>;
+ };
+
+ slv_qhs_camera_ss_cfg:slv-qhs-camera-ss-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_CFG>;
+ label = "slv-qhs-camera-ss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_CFG>;
+ };
+
+ slv_qhs_cdsp_throttle_cfg:slv-qhs-cdsp-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_CDSP_THROTTLE_CFG>;
+ label = "slv-qhs-cdsp-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CDSP_THROTTLE_CFG>;
+ };
+
+ slv_qhs_clk_ctl:slv-qhs-clk-ctl {
+ cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
+ label = "slv-qhs-clk-ctl";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CLK_CTL>;
+ };
+
+ slv_qhs_crypto0_cfg:slv-qhs-crypto0-cfg {
+ cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>;
+ label = "slv-qhs-crypto0-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CRYPTO_0_CFG>;
+ };
+
+ slv_qhs_disp_ss_cfg:slv-qhs-disp-ss-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_CFG>;
+ label = "slv-qhs-disp-ss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_CFG>;
+ };
+
+ slv_qhs_display_throttle_cfg:slv-qhs-display-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG>;
+ label = "slv-qhs-display-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_THROTTLE_CFG>;
+ };
+
+ slv_qhs_gpu_cfg:slv-qhs-gpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_GPU_CFG>;
+ label = "slv-qhs-gpu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GPU_CFG>;
+ };
+
+ slv_qhs_imem_cfg:slv-qhs-imem-cfg {
+ cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
+ label = "slv-qhs-imem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IMEM_CFG>;
+ };
+
+ slv_qhs_ipa_cfg:slv-qhs-ipa-cfg {
+ cell-id = <MSM_BUS_SLAVE_IPA_CFG>;
+ label = "slv-qhs-ipa-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IPA_CFG>;
+ };
+
+ slv_qhs_lpass:slv-qhs-lpass {
+ cell-id = <MSM_BUS_SLAVE_LPASS>;
+ label = "slv-qhs-lpass";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_LPASS>;
+ };
+
+ slv_qhs_mesg_ram:slv-qhs-mesg-ram {
+ cell-id = <MSM_BUS_SLAVE_MESSAGE_RAM>;
+ label = "slv-qhs-mesg-ram";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MESSAGE_RAM>;
+ };
+
+ slv_qhs_pdm:slv-qhs-pdm {
+ cell-id = <MSM_BUS_SLAVE_PDM>;
+ label = "slv-qhs-pdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PDM>;
+ };
+
+ slv_qhs_pimem_cfg:slv-qhs-pimem-cfg {
+ cell-id = <MSM_BUS_SLAVE_PIMEM_CFG>;
+ label = "slv-qhs-pimem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PIMEM_CFG>;
+ };
+
+ slv_qhs_pmic_arb:slv-qhs-pmic-arb {
+ cell-id = <MSM_BUS_SLAVE_PMIC_ARB>;
+ label = "slv-qhs-pmic-arb";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PMIC_ARB>;
+ };
+
+ slv_qhs_prng:slv-qhs-prng {
+ cell-id = <MSM_BUS_SLAVE_PRNG>;
+ label = "slv-qhs-prng";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>;
+ };
+
+ slv_qhs_qdss_cfg:slv-qhs-qdss-cfg {
+ cell-id = <MSM_BUS_SLAVE_QDSS_CFG>;
+ label = "slv-qhs-qdss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_CFG>;
+ };
+
+ slv_qhs_qm_cfg:slv-qhs-qm-cfg {
+ cell-id = <MSM_BUS_SLAVE_QM_CFG>;
+ label = "slv-qhs-qm-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QM_CFG>;
+ };
+
+ slv_qhs_qm_mpu_cfg:slv-qhs-qm-mpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_QM_MPU_CFG>;
+ label = "slv-qhs-qm-mpu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QM_MPU_CFG>;
+ };
+
+ slv_qhs_qup0:slv-qhs-qup0 {
+ cell-id = <MSM_BUS_SLAVE_QUP_0>;
+ label = "slv-qhs-qup0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QUP_0>;
+ };
+
+ slv_qhs_sdc1:slv-qhs-sdc1 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_1>;
+ label = "slv-qhs-sdc1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_1>;
+ };
+
+ slv_qhs_sdc2:slv-qhs-sdc2 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_2>;
+ label = "slv-qhs-sdc2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_2>;
+ };
+
+ slv_snoc_cfg:slv-snoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
+ label = "slv-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_snoc_cfg>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CFG>;
+ };
+
+ slv_qhs_tcsr:slv-qhs-tcsr {
+ cell-id = <MSM_BUS_SLAVE_TCSR>;
+ label = "slv-qhs-tcsr";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>;
+ };
+
+ slv_qhs_tlmm_east:slv-qhs-tlmm-east {
+ cell-id = <MSM_BUS_SLAVE_TLMM_EAST>;
+ label = "slv-qhs-tlmm-east";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TLMM_EAST>;
+ };
+
+ slv_qhs_tlmm_south:slv-qhs-tlmm-south {
+ cell-id = <MSM_BUS_SLAVE_TLMM_SOUTH>;
+ label = "slv-qhs-tlmm-south";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TLMM_SOUTH>;
+ };
+
+ slv_qhs_tlmm_west:slv-qhs-tlmm-west {
+ cell-id = <MSM_BUS_SLAVE_TLMM_WEST>;
+ label = "slv-qhs-tlmm-west";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TLMM_WEST>;
+ };
+
+ slv_qhs_ufs_mem_cfg:slv-qhs-ufs-mem-cfg {
+ cell-id = <MSM_BUS_SLAVE_UFS_MEM_CFG>;
+ label = "slv-qhs-ufs-mem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_UFS_MEM_CFG>;
+ };
+
+ slv_qhs_usb3:slv-qhs-usb3 {
+ cell-id = <MSM_BUS_SLAVE_USB3>;
+ label = "slv-qhs-usb3";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_USB3>;
+ };
+
+ slv_qhs_venus_cfg:slv-qhs-venus-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_CFG>;
+ label = "slv-qhs-venus-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_CFG>;
+ };
+
+ slv_qhs_venus_throttle_cfg:slv-qhs-venus-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_THROTTLE_CFG>;
+ label = "slv-qhs-venus-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_THROTTLE_CFG>;
+ };
+
+ slv_qhs_vsense_ctrl_cfg:slv-qhs-vsense-ctrl-cfg {
+ cell-id = <MSM_BUS_SLAVE_VSENSE_CTRL_CFG>;
+ label = "slv-qhs-vsense-ctrl-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VSENSE_CTRL_CFG>;
+ };
+
+ slv_srvc_cnoc:slv-srvc-cnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_CNOC>;
+ label = "slv-srvc-cnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_CNOC>;
+ };
+
+ slv_qup_core_slave_0:slv-qup-core-slave-0 {
+ cell-id = <MSM_BUS_SLAVE_QUP_CORE_0>;
+ label = "slv-qup-core-slave-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_qup_virt>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QUP_CORE_0>;
+ };
+
+ slv_qhs_apss:slv-qhs-apss {
+ cell-id = <MSM_BUS_SLAVE_APPSS>;
+ label = "slv-qhs-apss";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_APPSS>;
+ };
+
+ slv_snoc_bimc_nrt:slv-snoc-bimc-nrt {
+ cell-id = <MSM_BUS_SLAVE_SNOC_BIMC_NRT>;
+ label = "slv-snoc-bimc-nrt";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mmnrt_virt>;
+ qcom,connections = <&mas_snoc_bimc_nrt>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_NRT>;
+ };
+
+ slv_snoc_bimc_rt:slv-snoc-bimc-rt {
+ cell-id = <MSM_BUS_SLAVE_SNOC_BIMC_RT>;
+ label = "slv-snoc-bimc-rt";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mmrt_virt>;
+ qcom,connections = <&mas_snoc_bimc_rt>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_RT>;
+ };
+
+ slv_snoc_cnoc:slv-snoc-cnoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_SLV>;
+ label = "slv-snoc-cnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <8>;
+ qcom,qos-mode = "fixed";
+ qcom,prio = <2>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,connections = <&mas_snoc_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CNOC>;
+ };
+
+ slv_qxs_imem:slv-qxs-imem {
+ cell-id = <MSM_BUS_SLAVE_OCIMEM>;
+ label = "slv-qxs-imem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IMEM>;
+ };
+
+ slv_qxs_pimem:slv-qxs-pimem {
+ cell-id = <MSM_BUS_SLAVE_PIMEM>;
+ label = "slv-qxs-pimem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PIMEM>;
+ };
+
+ slv_snoc_bimc:slv-snoc-bimc {
+ cell-id = <MSM_BUS_SNOC_BIMC_SLV>;
+ label = "slv-snoc-bimc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,connections = <&mas_snoc_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC>;
+ };
+
+ slv_srvc_snoc:slv-srvc-snoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_SNOC>;
+ label = "slv-srvc-snoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_SNOC>;
+ };
+
+ slv_xs_qdss_stm:slv-xs-qdss-stm {
+ cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
+ label = "slv-xs-qdss-stm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>;
+ };
+
+ slv_xs_sys_tcu_cfg:slv-xs-sys-tcu-cfg {
+ cell-id = <MSM_BUS_SLAVE_TCU>;
+ label = "slv-xs-sys-tcu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TCU>;
+ };
+
+ slv_anoc_snoc:slv-anoc-snoc {
+ cell-id = <MSM_BUS_SLAVE_ANOC_SNOC>;
+ label = "slv-anoc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,connections = <&mas_anoc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_A0NOC_SNOC>;
+ };
+
+ slv_gpu_cdsp_bimc:slv-gpu-cdsp-bimc {
+ cell-id = <MSM_BUS_SLAVE_GPU_CDSP_BIMC>;
+ label = "slv-gpu-cdsp-bimc";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gpu_vert>;
+ qcom,connections = <&mas_gpu_cdsp_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GPU_CDSP_BIMC>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-coresight.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-coresight.dtsi
new file mode 100755
index 0000000..5bd4d1d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-coresight.dtsi
@@ -0,0 +1,1767 @@
+&soc {
+ hwevent {
+ compatible = "qcom,coresight-hwevent";
+
+ coresight-name = "coresight-hwevent";
+ coresight-csr = <&csr>;
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ apss_tgu: tgu@9900000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b999>;
+ reg = <0x09900000 0x1000>;
+ reg-names = "tgu-base";
+ tgu-steps = <3>;
+ tgu-conditions = <4>;
+ tgu-regs = <8>;
+ tgu-timer-counters = <8>;
+ interrupts = <0 53 1>, <0 54 1>, <0 55 1>, <0 56 1>;
+ coresight-name = "coresight-tgu-apss";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ csr: csr@8001000 {
+ compatible = "qcom,coresight-csr";
+ reg = <0x8001000 0x1000>;
+ reg-names = "csr-base";
+
+ coresight-name = "coresight-csr";
+ qcom,usb-bam-support;
+ qcom,hwctrl-set-support;
+ qcom,set-byte-cntr-support;
+
+ qcom,blk-size = <1>;
+ };
+
+ swao_csr: csr@8a03000 {
+ compatible = "qcom,coresight-csr";
+ reg = <0x8a03000 0x1000>;
+ reg-names = "csr-base";
+
+ coresight-name = "coresight-swao-csr";
+
+ qcom,timestamp-support;
+ qcom,aodbg-csr-support;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,blk-size = <1>;
+ };
+
+ stm: stm@8002000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb962>;
+
+ reg = <0x8002000 0x1000>,
+ <0xe280000 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ coresight-name = "coresight-stm";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ nvmem-cells = <&stm_debug_fuse>;
+ nvmem-cell-names = "debug_fuse";
+
+ port {
+ stm_out_funnel_in0: endpoint {
+ remote-endpoint = <&funnel_in0_in_stm>;
+ };
+ };
+
+ };
+
+ tpdm_center: tpdm@8b58000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8b58000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-center";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_dl_ct_out_tpda0: endpoint {
+ remote-endpoint =
+ <&tpda0_in_tpdm_dl_ct>;
+ };
+ };
+ };
+
+ tpdm_gpu: tpdm@8940000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8940000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-gpu";
+ status = "disabled";
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_gpu_out_funnel_gpu: endpoint {
+ remote-endpoint =
+ <&funnel_gpu_in_tpdm_gpu>;
+ };
+ };
+ };
+
+ modem_rfxe: modem_rfxe {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-modem-rfxe";
+ qcom,dummy-source;
+
+ port {
+ modem_rxfe_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_modem_rxfe>;
+ };
+ };
+ };
+
+ audio_etm0: audio_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+ coresight-name = "coresight-audio-etm0";
+
+ qcom,inst-id = <5>;
+
+ port {
+ audio_etm0_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_audio_etm0>;
+ };
+ };
+ };
+
+ snoc: snoc {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-snoc";
+ qcom,dummy-source;
+
+ port {
+ snoc_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_snoc>;
+ };
+ };
+ };
+
+ tpdm_lpass: tpdm@8a26000 {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-tpdm-lpass";
+ qcom,dummy-source;
+
+ port {
+ tpdm_lpass_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_tpdm_lpass>;
+ };
+ };
+ };
+
+ tpdm_turing: tpdm@8860000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8860000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-turing";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_turing_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_tpdm_turing>;
+ };
+ };
+ };
+
+ turing_etm0: turing_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+ coresight-name = "coresight-turing-etm0";
+
+ qcom,inst-id = <13>;
+
+ port {
+ turing_etm0_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_turing_etm0>;
+ };
+ };
+ };
+
+ tpdm_vsense: tpdm@8840000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8840000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-vsense";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_vsense_out_tpda7: endpoint {
+ remote-endpoint =
+ <&tpda7_in_tpdm_vsense>;
+ };
+ };
+ };
+
+ tpdm_dcc: tpdm@8870000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8870000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dcc";
+
+ qcom,hw-enable-check;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_dcc_out_tpda8: endpoint {
+ remote-endpoint =
+ <&tpda8_in_tpdm_dcc>;
+ };
+ };
+ };
+
+ tpdm_prng: tpdm@884c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x884c000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-prng";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_prng_out_tpda10: endpoint {
+ remote-endpoint =
+ <&tpda10_in_tpdm_prng>;
+ };
+ };
+ };
+
+ tpdm_qm: tpdm@89d0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x89d0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-qm";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_qm_out_tpda12: endpoint {
+ remote-endpoint =
+ <&tpda12_in_tpdm_qm>;
+ };
+ };
+ };
+
+ tpdm_west: tpdm@8a58000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8a58000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-west";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_west_out_tpda13: endpoint {
+ remote-endpoint =
+ <&tpda13_in_tpdm_west>;
+ };
+ };
+ };
+
+ tpdm_pimem: tpdm@8850000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8850000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-pimem";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_pimem_out_tpda15: endpoint {
+ remote-endpoint =
+ <&tpda15_in_tpdm_pimem>;
+ };
+ };
+ };
+
+ tpdm_mapss: tpdm@8a01000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8a01000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-mapss";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_mapss_out_tpda_mapss: endpoint {
+ remote-endpoint =
+ <&tpda_mapss_in_tpdm_mapss>;
+ };
+ };
+ };
+
+ tpdm_wcss: tpdm@899c000 {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-tpdm-wcss";
+ qcom,dummy-source;
+
+ port {
+ tpdm_wcss_silver_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_tpdm_wcss_silver>;
+ };
+ };
+ };
+
+ modem_etm0: modem_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+ coresight-name = "coresight-modem-etm0";
+
+ qcom,inst-id = <2>;
+
+ port {
+ modem_etm0_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_modem_etm0>;
+ };
+ };
+ };
+
+ etm0: etm@9040000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x9040000 0x1000>;
+ cpu = <&CPU0>;
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm0_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_etm0>;
+ };
+ };
+ };
+
+ etm1: etm@9140000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x9140000 0x1000>;
+ cpu = <&CPU1>;
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm1";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm1_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_etm1>;
+ };
+ };
+ };
+
+ etm2: etm@9240000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x9240000 0x1000>;
+ cpu = <&CPU2>;
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm2";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm2_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_etm2>;
+ };
+ };
+ };
+
+ etm3: etm@9340000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x9340000 0x1000>;
+ cpu = <&CPU3>;
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm3";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm3_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_etm3>;
+ };
+ };
+ };
+
+ etm4: etm@9440000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x9440000 0x1000>;
+ cpu = <&CPU4>;
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm4";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm4_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_etm4>;
+ };
+ };
+ };
+
+ etm5: etm@9540000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x9540000 0x1000>;
+ cpu = <&CPU5>;
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm5";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm5_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_etm5>;
+ };
+ };
+ };
+
+ etm6: etm@9640000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x9640000 0x1000>;
+ cpu = <&CPU6>;
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm6";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm6_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_etm6>;
+ };
+ };
+ };
+
+ etm7: etm@9740000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x9740000 0x1000>;
+ cpu = <&CPU7>;
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm7";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm7_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_etm7>;
+ };
+ };
+ };
+
+ tpdm_actpm: tpd@9830000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x9830000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-actpm";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_actpm_out_tpda_actpm: endpoint {
+ remote-endpoint =
+ <&tpda_actpm_in_tpdm_actpm>;
+ };
+ };
+ };
+
+ tpdm_llm_silver: tpdm@98a0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x98a0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-llm-silver";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_llm_silver_out_tpda_llm_silver: endpoint {
+ remote-endpoint =
+ <&tpda_llm_silver_in_tpdm_llm_silver>;
+ };
+ };
+ };
+
+ tpdm_apss: tpdm@9860000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x9860000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-apss";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_apss_out_tpda_apss: endpoint {
+ remote-endpoint =
+ <&tpda_apss_in_tpdm_apss>;
+ };
+ };
+ };
+
+ funnel_apss0: funnel@9800000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x9800000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-apss0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_apss0_out_funnel_apss1: endpoint {
+ remote-endpoint =
+ <&funnel_apss1_in_funnel_apss0>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_apss0_in_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm0_out_funnel_apss0>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_apss0_in_etm1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm1_out_funnel_apss0>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ funnel_apss0_in_etm2: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm2_out_funnel_apss0>;
+ };
+ };
+
+ port@4 {
+ reg = <3>;
+ funnel_apss0_in_etm3: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm3_out_funnel_apss0>;
+ };
+ };
+
+ port@5 {
+ reg = <4>;
+ funnel_apss0_in_etm4: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm4_out_funnel_apss0>;
+ };
+ };
+
+ port@6 {
+ reg = <5>;
+ funnel_apss0_in_etm5: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm5_out_funnel_apss0>;
+ };
+ };
+
+ port@7 {
+ reg = <6>;
+ funnel_apss0_in_etm6: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm6_out_funnel_apss0>;
+ };
+ };
+
+ port@8 {
+ reg = <7>;
+ funnel_apss0_in_etm7: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm7_out_funnel_apss0>;
+ };
+ };
+
+ };
+ };
+
+ tpda_actpm: tpda@9832000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x9832000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-actpm";
+
+ qcom,tpda-atid = <77>;
+ qcom,cmb-elem-size = <0 32>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_actpm_out_funnel_apss1: endpoint {
+ remote-endpoint =
+ <&funnel_apss1_in_tpda_actpm>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_actpm_in_tpdm_actpm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_actpm_out_tpda_actpm>;
+ };
+ };
+ };
+ };
+
+ tpda_apss: tpda@9862000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x9862000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-apss";
+
+
+ qcom,tpda-atid = <66>;
+ qcom,dsb-elem-size = <0 32>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_apss_out_funnel_apss1: endpoint {
+ remote-endpoint =
+ <&funnel_apss1_in_tpda_apss>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_apss_in_tpdm_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_apss_out_tpda_apss>;
+ };
+ };
+ };
+ };
+
+
+ tpda_llm_silver: tpda@98c0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x98c0000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-llm-silver";
+
+ qcom,tpda-atid = <72>;
+ qcom,cmb-elem-size = <0 32>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_llm_silver_out_funnel_apss1: endpoint {
+ remote-endpoint =
+ <&funnel_apss1_in_tpda_llm_silver>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_llm_silver_in_tpdm_llm_silver: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_llm_silver_out_tpda_llm_silver>;
+ };
+ };
+ };
+ };
+
+
+ funnel_apss1: funnel@9810000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x9810000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-apss1";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_apss1_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_funnel_apss1>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_apss1_in_funnel_apss0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_apss0_out_funnel_apss1>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_apss1_in_tpda_actpm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_actpm_out_funnel_apss1>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_apss1_in_tpda_llm_silver: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_llm_silver_out_funnel_apss1>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ funnel_apss1_in_tpda_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_apss_out_funnel_apss1>;
+ };
+ };
+
+ };
+ };
+
+ tpda_mapss: tpda@8a04000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x8a04000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-mapss";
+
+ qcom,tpda-atid = <76>;
+ qcom,cmb-elem-size = <0 32>;
+ qcom,dsb-elem-size = <0 32>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_mapss_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_tpda_mapss>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_mapss_in_tpdm_mapss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_mapss_out_tpda_mapss>;
+ };
+ };
+ };
+ };
+
+ funnel_gpu: funnel@8944000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x8944000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-gpu";
+ status = "disabled";
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_gpu_out_tpda1: endpoint {
+ remote-endpoint =
+ <&tpda1_in_funnel_gpu>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_gpu_in_tpdm_gpu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_gpu_out_funnel_gpu>;
+ };
+ };
+
+ };
+ };
+
+ funnel_turing: funnel@8861000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x8861000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-turing";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_turing_out_tpda5: endpoint {
+ remote-endpoint =
+ <&tpda5_in_funnel_turing>;
+ source = <&tpdm_turing>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_turing_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_funnel_turing>;
+ source = <&turing_etm0>;
+ };
+ };
+
+ port@2 {
+ reg = <0>;
+ funnel_turing_in_tpdm_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_turing_out_funnel_turing>;
+ };
+ };
+
+ port@3 {
+ reg = <1>;
+ funnel_turing_in_turing_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&turing_etm0_out_funnel_turing>;
+ };
+ };
+
+ };
+ };
+
+ tpda: tpda@8004000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x8004000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda";
+
+ qcom,tpda-atid = <65>;
+ qcom,dsb-elem-size = <0 32>,
+ <1 32>,
+ <5 32>,
+ <12 32>,
+ <13 32>,
+ <15 32>;
+ qcom,cmb-elem-size = <7 32>,
+ <8 32>,
+ <10 32>,
+ <15 64>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_tpda>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda0_in_tpdm_dl_ct: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dl_ct_out_tpda0>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ tpda1_in_funnel_gpu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_gpu_out_tpda1>;
+ };
+ };
+
+ port@3 {
+ reg = <5>;
+ tpda5_in_funnel_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_turing_out_tpda5>;
+ };
+ };
+
+ port@4 {
+ reg = <7>;
+ tpda7_in_tpdm_vsense: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_vsense_out_tpda7>;
+ };
+ };
+
+ port@5 {
+ reg = <8>;
+ tpda8_in_tpdm_dcc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dcc_out_tpda8>;
+ };
+ };
+
+ port@6 {
+ reg = <10>;
+ tpda10_in_tpdm_prng: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_prng_out_tpda10>;
+ };
+ };
+
+ port@7 {
+ reg = <12>;
+ tpda12_in_tpdm_qm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_qm_out_tpda12>;
+ };
+ };
+
+ port@8 {
+ reg = <13>;
+ tpda13_in_tpdm_west: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_west_out_tpda13>;
+ };
+ };
+
+ port@9 {
+ reg = <15>;
+ tpda15_in_tpdm_pimem: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_pimem_out_tpda15>;
+ };
+ };
+
+ };
+ };
+
+ funnel_qatb: funnel@8005000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x8005000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-qatb";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_qatb_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_funnel_qatb>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_qatb_in_tpda: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_out_funnel_qatb>;
+ };
+ };
+
+ port@2 {
+ reg = <6>;
+ funnel_qatb_in_funnel_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_turing_out_funnel_qatb>;
+ };
+ };
+
+ port@3 {
+ reg = <5>;
+ funnel_qatb_in_tpdm_lpass: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_lpass_out_funnel_qatb>;
+ };
+ };
+
+ port@4 {
+ reg = <5>;
+ funnel_qatb_in_audio_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&audio_etm0_out_funnel_qatb>;
+ };
+ };
+ };
+ };
+
+ funnel_in0: funnel@8041000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x8041000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-in0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_in0_out_funnel_merg: endpoint {
+ remote-endpoint =
+ <&funnel_merg_in_funnel_in0>;
+ };
+ };
+
+ port@1 {
+ reg = <5>;
+ funnel_in0_in_snoc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&snoc_out_funnel_in0>;
+ };
+ };
+
+ port@2 {
+ reg = <6>;
+ funnel_in0_in_funnel_qatb: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_qatb_out_funnel_in0>;
+ };
+ };
+
+ port@3 {
+ reg = <7>;
+ funnel_in0_in_stm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&stm_out_funnel_in0>;
+ };
+ };
+
+ };
+ };
+
+ funnel_in1: funnel@8042000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x8042000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-in1";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_in1_out_funnel_merg: endpoint {
+ remote-endpoint =
+ <&funnel_merg_in_funnel_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_in1_in_tpda_mapss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_mapss_out_funnel_in1>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_in1_in_modem_rxfe: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&modem_rxfe_out_funnel_in1>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_in1_in_tpdm_wcss_silver: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_wcss_silver_out_funnel_in1>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ funnel_in1_in_modem_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&modem_etm0_out_funnel_in1>;
+ };
+ };
+
+ port@5 {
+ reg = <6>;
+ funnel_in1_in_funnel_apss1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_apss1_out_funnel_in1>;
+ };
+ };
+
+ };
+ };
+
+ funnel_merg: funnel@8045000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x8045000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-merg";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_merg_out_tmc_etf: endpoint {
+ remote-endpoint =
+ <&tmc_etf_in_funnel_merg>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_merg_in_funnel_in0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_in0_out_funnel_merg>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_merg_in_funnel_in1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_in1_out_funnel_merg>;
+ };
+ };
+
+ };
+ };
+
+ tmc_etf: tmc@8047000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+ reg = <0x8047000 0x1000>;
+ reg-names = "tmc-base";
+
+ coresight-name = "coresight-tmc-etf";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ coresight-ctis = <&cti0>;
+ coresight-csr = <&csr>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tmc_etf_out_replicator_qdss: endpoint {
+ remote-endpoint =
+ <&replicator_qdss_in_tmc_etf>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tmc_etf_in_funnel_merg: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_merg_out_tmc_etf>;
+ };
+ };
+
+ };
+ };
+
+ replicator_qdss: replicator@8046000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x8046000 0x1000>;
+ reg-names = "replicator-base";
+
+ coresight-name = "coresight-replicator-qdss";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ replicator_qdss_out_tmc_etr: endpoint {
+ remote-endpoint =
+ <&tmc_etr_in_replicator_qdss>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ replicator_qdss_in_tmc_etf: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tmc_etf_out_replicator_qdss>;
+ };
+ };
+
+ };
+ };
+
+ tmc_etr: tmc@8048000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+ reg = <0x8048000 0x1000>,
+ <0x8064000 0x15000>;
+ reg-names = "tmc-base","bam-base";
+
+ coresight-name = "coresight-tmc-etr";
+
+
+ iommus = <&apps_smmu 0x0180 0>,
+ <&apps_smmu 0x0160 0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ arm,buffer-size = <0x400000>;
+ arm,scatter-gather;
+
+ coresight-ctis = <&cti0>;
+ coresight-csr = <&csr>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ interrupts = <GIC_SPI 429 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "byte-cntr-irq";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tmc_etr_in_replicator_qdss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&replicator_qdss_out_tmc_etr>;
+ };
+ };
+
+ };
+ };
+
+ cti_cortex_M3: cti@8B30000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8B30000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cortex_M3";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_apss_cti0: cti@98E0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x98E0000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss-cti0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_apss_cti1: cti@98F0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x98F0000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss-cti1";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_wcss_cti0: cti@89A4000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x89A4000 0x1000>;
+ reg-names = "cti-base";
+ status = "disabled";
+ coresight-name = "coresight-cti-wcss-cti0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_wcss_cti1: cti@89A5000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x89A5000 0x1000>;
+ reg-names = "cti-base";
+ status = "disabled";
+ coresight-name = "coresight-cti-wcss-cti1";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_wcss_cti2: cti@89A6000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x89A6000 0x1000>;
+ reg-names = "cti-base";
+ status = "disabled";
+ coresight-name = "coresight-cti-wcss-cti2";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_lpass_q6: cti@8A21000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8A21000 0x1000>;
+ reg-names = "cti-base";
+
+ status = "disabled";
+ coresight-name = "coresight-cti-lpass-q6";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_turing_q6: cti@8867000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8867000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-turing-q6";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_mss_q6: cti@8833000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8833000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-mss-q6";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_isdb_gpu: cti@8941000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8941000 0x1000>;
+ reg-names = "cti-base";
+ status = "disabled";
+ coresight-name = "coresight-cti-isdb-gpu";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_mapss: cti@8A02000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8A02000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-mapss";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct_cti0: cti@8B59000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8B59000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct-cti0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct_cti1: cti@8B5A000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8B5A000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct-cti1";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct_cti2: cti@8B5B000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8B5B000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct-cti2";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct_cti3: cti@8B5C000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8B5C000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct-cti3";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0: cti@8010000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8010000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1: cti@8011000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8011000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti1";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti10: cti@801a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x801a000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti10";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti11: cti@801b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x801b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti11";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti12: cti@801c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x801c000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti12";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti13: cti@801d000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x801d000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti13";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti14: cti@801e000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x801e000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti14";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti15: cti@801f000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x801f000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti15";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2: cti@8012000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8012000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti2";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti3: cti@8013000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8013000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti3";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti4: cti@8014000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8014000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti4";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti5: cti@8015000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8015000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti5";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti6: cti@8016000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8016000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti6";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti7: cti@8017000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8017000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti7";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti8: cti@8018000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8018000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti8";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti9: cti@8019000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8019000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti9";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-gdsc.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-gdsc.dtsi
new file mode 100755
index 0000000..16c1a0a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-gdsc.dtsi
@@ -0,0 +1,115 @@
+&soc {
+ /* GDSCs in GCC */
+ gcc_camss_top_gdsc: qcom,gdsc@1458004 {
+ compatible = "qcom,gdsc";
+ reg = <0x1458004 0x4>;
+ regulator-name = "gcc_camss_top_gdsc";
+ status = "disabled";
+ };
+
+ gcc_ufs_phy_gdsc: qcom,gdsc@1445004 {
+ compatible = "qcom,gdsc";
+ reg = <0x1445004 0x4>;
+ regulator-name = "gcc_ufs_phy_gdsc";
+ status = "disabled";
+ };
+
+ gcc_usb30_prim_gdsc: qcom,gdsc@141a004 {
+ compatible = "qcom,gdsc";
+ reg = <0x141a004 0x4>;
+ regulator-name = "gcc_usb30_prim_gdsc";
+ status = "disabled";
+ };
+
+ gcc_vcodec0_gdsc: qcom,gdsc@1458098 {
+ compatible = "qcom,gdsc";
+ reg = <0x1458098 0x4>;
+ regulator-name = "gcc_vcodec0_gdsc";
+ status = "disabled";
+ };
+
+ gcc_venus_gdsc: qcom,gdsc@145807c {
+ compatible = "qcom,gdsc";
+ reg = <0x145807c 0x4>;
+ regulator-name = "gcc_venus_gdsc";
+ status = "disabled";
+ };
+
+ hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 {
+ compatible = "qcom,gdsc";
+ reg = <0x147d060 0x4>;
+ regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";
+ qcom,no-status-check-on-disable;
+ status = "disabled";
+ };
+
+ hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@147d07c {
+ compatible = "qcom,gdsc";
+ reg = <0x147d07c 0x4>;
+ regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";
+ qcom,no-status-check-on-disable;
+ status = "disabled";
+ };
+
+ hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 {
+ compatible = "qcom,gdsc";
+ reg = <0x147d074 0x4>;
+ regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc";
+ qcom,no-status-check-on-disable;
+ status = "disabled";
+ };
+
+ hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 {
+ compatible = "qcom,gdsc";
+ reg = <0x147d078 0x4>;
+ regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc";
+ qcom,no-status-check-on-disable;
+ status = "disabled";
+ };
+
+ /* GDSCs in DISPCC */
+ mdss_core_gdsc: qcom,gdsc@5f03000 {
+ compatible = "qcom,gdsc";
+ reg = <0x5f03000 0x4>;
+ regulator-name = "mdss_core_gdsc";
+ proxy-supply = <&mdss_core_gdsc>;
+ qcom,proxy-consumer-enable;
+ status = "disabled";
+ };
+
+ /* GDSCs in GPUCC */
+ gpu_gx_domain_addr: syscon@5991508 {
+ compatible = "syscon";
+ reg = <0x5991508 0x4>;
+ };
+
+ gpu_cx_hw_ctrl: syscon@5991540 {
+ compatible = "syscon";
+ reg = <0x5991540 0x4>;
+ };
+
+ gpu_gx_sw_reset: syscon@5991008 {
+ compatible = "syscon";
+ reg = <0x5991008 0x4>;
+ };
+
+ gpu_cx_gdsc: qcom,gdsc@599106c {
+ compatible = "qcom,gdsc";
+ reg = <0x599106c 0x4>;
+ regulator-name = "gpu_cx_gdsc";
+ hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ qcom,clk-dis-wait-val = <8>;
+ status = "disabled";
+ };
+
+ gpu_gx_gdsc: qcom,gdsc@599100c {
+ compatible = "qcom,gdsc";
+ reg = <0x599100c 0x4>;
+ regulator-name = "gpu_gx_gdsc";
+ sw-reset = <&gpu_gx_sw_reset>;
+ domain-addr = <&gpu_gx_domain_addr>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-gpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-gpu.dtsi
new file mode 100755
index 0000000..b108207
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-gpu.dtsi
@@ -0,0 +1,651 @@
+&soc {
+ pil_gpu: qcom,kgsl-hyp {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <13>;
+ qcom,firmware-name = "a610_zap";
+ qcom,mas-crypto = <&mas_crypto_c0>;
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-980000000 {
+ opp-hz = /bits/ 64 <980000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+
+ opp-950000000 {
+ opp-hz = /bits/ 64 <950000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ opp-820000000 {
+ opp-hz = /bits/ 64 <820000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-745000000 {
+ opp-hz = /bits/ 64 <745000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-465000000 {
+ opp-hz = /bits/ 64 <465000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+
+ msm_bus: qcom,kgsl-busmon {
+ label = "kgsl-busmon";
+ compatible = "qcom,kgsl-busmon";
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
+ gpu_bw_tbl: gpu-bw-tbl {
+ compatible = "operating-points-v2";
+
+ opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */
+
+ opp-100 { opp-hz = /bits/ 64 < 762 >; }; /* 1.100 MHz */
+
+ opp-200 { opp-hz = /bits/ 64 < 1525 >; }; /* 2.200 MHz */
+
+ opp-300 { opp-hz = /bits/ 64 < 2288 >; }; /* 3.300 MHz */
+
+ opp-451 { opp-hz = /bits/ 64 < 3440 >; }; /* 4.451 MHz */
+
+ opp-547 { opp-hz = /bits/ 64 < 4173 >; }; /* 5.547 MHz */
+
+ opp-681 { opp-hz = /bits/ 64 < 5195 >; }; /* 6.681 MHz */
+
+ opp-768 { opp-hz = /bits/ 64 < 5859 >; }; /* 7.768 MHz */
+
+ opp-1017 { opp-hz = /bits/ 64 < 7759 >; }; /* 8.1017 MHz */
+
+ opp-1353 { opp-hz = /bits/ 64 < 10322 >; }; /* 9.1353 MHz */
+
+ opp-1555 { opp-hz = /bits/ 64 < 11863 >; }; /* 10.1555 MHz */
+
+ opp-1804 { opp-hz = /bits/ 64 < 13763 >; }; /* 11.1804 MHz */
+ };
+
+ gpubw: qcom,gpubw {
+ compatible = "qcom,devbw";
+ governor = "bw_vbif";
+ qcom,src-dst-ports = <26 512>;
+ operating-points-v2 = <&gpu_bw_tbl>;
+ };
+
+ msm_gpu: qcom,kgsl-3d0@5900000 {
+ label = "kgsl-3d0";
+ compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
+ status = "ok";
+
+ reg = <0x5900000 0x90000>,
+ <0x5961000 0x800>;
+ reg-names = "kgsl_3d0_reg_memory", "cx_dbgc";
+
+ interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+
+ qcom,id = <0>;
+ qcom,chipid = <0x06010000>;
+
+ qcom,initial-pwrlevel = <6>;
+ qcom,idle-timeout = <80>;
+
+ qcom,ubwc-mode = <1>;
+ qcom,min-access-length = <64>;
+ qcom,highest-bank-bit = <14>;
+
+ /* size in bytes */
+ qcom,snapshot-size = <1048576>;
+
+ /* base addr, size */
+ qcom,gpu-qdss-stm = <0xe1c0000 0x40000>;
+ #cooling-cells = <2>;
+
+ clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_BIMC_GPU_AXI_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&rpmcc RPM_SMD_QDSS_CLK>;
+
+ clock-names = "core_clk", "rbbmtimer_clk", "iface_clk",
+ "ahb_clk", "mem_clk", "gmu_clk",
+ "smmu_vote", "apb_pclk";
+
+ /* Bus Scale Settings */
+ qcom,gpubw-dev = <&gpubw>;
+ qcom,bus-control;
+ qcom,msm-bus,name = "grp3d";
+ qcom,msm-bus,num-cases = <12>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <26 512 0 0>,
+ <26 512 0 800000>, /* 1 bus=100 (LOW SVS) */
+ <26 512 0 1600000>, /* 2 bus=200 (LOW SVS) */
+ <26 512 0 2400000>, /* 3 bus=300 (LOW SVS) */
+ <26 512 0 3608000>, /* 4 bus=451 (LOW SVS) */
+ <26 512 0 4376000>, /* 5 bus=547 (LOW SVS) */
+ <26 512 0 5448000>, /* 6 bus=681 (SVS) */
+ <26 512 0 6144000>, /* 7 bus=768 (SVS) */
+ <26 512 0 8136000>, /* 8 bus=1017 (SVS_L1) */
+ <26 512 0 10824000>, /* 9 bus=1353 (NOM) */
+ <26 512 0 12440000>, /* 10 bus=1555 (NOM) */
+ <26 512 0 14432000>; /* 11 bus=1804 (TURBO) */
+
+ /* GDSC regulator names */
+ regulator-names = "vddcx", "vdd";
+ /* GDSC oxili regulators */
+ vddcx-supply = <&gpu_cx_gdsc>;
+ vdd-supply = <&gpu_gx_gdsc>;
+
+ /* CPU latency parameter */
+ qcom,pm-qos-active-latency = <422>;
+ qcom,pm-qos-wakeup-latency = <422>;
+
+ /* Enable context aware freq. scaling */
+ qcom,enable-ca-jump;
+ /* Context aware jump busy penalty in us */
+ qcom,ca-busy-penalty = <12000>;
+ /* Context aware jump target power level */
+ qcom,ca-target-pwrlevel = <5>;
+
+ nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
+ nvmem-cell-names = "speed_bin", "gaming_bin";
+
+ qcom,gpu-cx-ipeak {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,gpu-cx-ipeak";
+
+ qcom,gpu-cx-ipeak@0 {
+ qcom,gpu-cx-ipeak = <&cx_ipeak_lm 10>;
+ qcom,gpu-cx-ipeak-freq = <950000000>;
+ };
+
+ qcom,gpu-cx-ipeak@1 {
+ qcom,gpu-cx-ipeak = <&cx_ipeak_lm 1>;
+ qcom,gpu-cx-ipeak-freq = <900000000>;
+ };
+ };
+
+ /* GPU Mempools */
+ qcom,gpu-mempools {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,gpu-mempools";
+
+ /* 4K Page Pool configuration */
+ qcom,gpu-mempool@0 {
+ reg = <0>;
+ qcom,mempool-page-size = <4096>;
+ qcom,mempool-allocate;
+ };
+ /* 8K Page Pool configuration */
+ qcom,gpu-mempool@1 {
+ reg = <1>;
+ qcom,mempool-page-size = <8192>;
+ qcom,mempool-allocate;
+ };
+ /* 64K Page Pool configuration */
+ qcom,gpu-mempool@2 {
+ reg = <2>;
+ qcom,mempool-page-size = <65536>;
+ qcom,mempool-reserved = <256>;
+ };
+ /* 1M Page Pool configuration */
+ qcom,gpu-mempool@3 {
+ reg = <3>;
+ qcom,mempool-page-size = <1048576>;
+ qcom,mempool-reserved = <32>;
+ };
+ };
+
+ /* GPU Mempool configuration for low memory SKUs */
+ qcom,gpu-mempools-lowmem {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,gpu-mempools-lowmem";
+
+ /* 4K Page Pool configuration */
+ qcom,gpu-mempool@0 {
+ reg = <0>;
+ qcom,mempool-page-size = <4096>;
+ qcom,mempool-allocate;
+ };
+ /* 8K Page Pool configuration */
+ qcom,gpu-mempool@1 {
+ reg = <1>;
+ qcom,mempool-page-size = <8192>;
+ qcom,mempool-allocate;
+ };
+ /* 64K Page Pool configuration */
+ qcom,gpu-mempool@2 {
+ reg = <2>;
+ qcom,mempool-page-size = <65536>;
+ qcom,mempool-allocate;
+ qcom,mempool-max-pages = <256>;
+ };
+ /* 1M Page Pool configuration */
+ qcom,gpu-mempool@3 {
+ reg = <3>;
+ qcom,mempool-page-size = <1048576>;
+ qcom,mempool-allocate;
+ qcom,mempool-max-pages = <32>;
+ };
+ };
+
+ /*
+ * Speed-bin zero is default speed bin.
+ * For rest of the speed bins, speed-bin value
+ * is calculated as FMAX/4.8 MHz round up to zero
+ * decimal places plus two margin to account for
+ * clock jitters.
+ */
+ qcom,gpu-pwrlevel-bins {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "qcom,gpu-pwrlevel-bins";
+
+ qcom,gpu-pwrlevels-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <0>;
+
+ qcom,initial-pwrlevel = <6>;
+ qcom,ca-target-pwrlevel = <5>;
+
+ /* TURBO_L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <980000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <900000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* NOM_L1 */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <820000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <745000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <600000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <9>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <320000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <206>;
+
+ qcom,initial-pwrlevel = <6>;
+ qcom,ca-target-pwrlevel = <5>;
+
+ /* TURBO_L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <980000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <900000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* NOM_L1 */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <820000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <745000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <600000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <9>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <320000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <200>;
+
+ qcom,initial-pwrlevel = <6>;
+ qcom,ca-target-pwrlevel = <5>;
+
+ /* TURBO_L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <950000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <900000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* NOM_L1 */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <820000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <745000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <600000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <9>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <320000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <157>;
+
+ qcom,initial-pwrlevel = <3>;
+ qcom,ca-target-pwrlevel = <2>;
+
+ /* NOM */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <745000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <11>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <600000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <320000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <127>;
+
+ qcom,initial-pwrlevel = <2>;
+ qcom,ca-target-pwrlevel = <1>;
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <600000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <11>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <9>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <320000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ };
+ };
+
+ kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 {
+ compatible = "qcom,kgsl-smmu-v2";
+
+ reg = <0x59a0000 0x10000>;
+ qcom,protect = <0xa0000 0x10000>;
+
+ clocks = <&gcc GCC_BIMC_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+
+ clock-names = "mem_clk", "mem_iface_clk", "smmu_vote";
+
+ qcom,retention;
+ qcom,hyp_secure_alloc;
+
+ gfx3d_user: gfx3d_user {
+ compatible = "qcom,smmu-kgsl-cb";
+ label = "gfx3d_user";
+ iommus = <&kgsl_smmu 0 1>;
+ qcom,iommu-dma = "disabled";
+ qcom,gpu-offset = <0xa8000>;
+ };
+
+ gfx3d_secure: gfx3d_secure {
+ compatible = "qcom,smmu-kgsl-cb";
+ label = "gfx3d_secure";
+ iommus = <&kgsl_smmu 2 0>;
+ qcom,iommu-dma = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-1gb-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-1gb-overlay.dts
new file mode 100755
index 0000000..f614df1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-1gb-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengal-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL IDP 1Gb DDR HD+";
+ compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp";
+ qcom,msm-id = <417 0x10000>, <444 0x10000>;
+ qcom,board-id = <34 0x303>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-1gb.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-1gb.dts
new file mode 100755
index 0000000..d272c7b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-1gb.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "bengal-low-ram.dtsi"
+#include "bengal-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL IDP 1Gb DDR HD+";
+ compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp";
+ qcom,board-id = <34 0x303>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-2gb-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-2gb-overlay.dts
new file mode 100755
index 0000000..962305e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-2gb-overlay.dts
@@ -0,0 +1,40 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengal-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL IDP 2Gb DDR HD+";
+ compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp";
+ qcom,msm-id = <417 0x10000>, <444 0x10000>;
+ qcom,board-id = <34 0x403>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_nt36525_truly_video>;
+};
+
+&qupv3_se2_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="novatek,NVT-ts";
+
+ novatek@62 {
+ compatible = "novatek,NVT-ts";
+ reg = <0x62>;
+ status = "ok";
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+
+ novatek,reset-gpio = <&tlmm 71 0x00>;
+ novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+ panel = <&dsi_nt36525_truly_video>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-2gb.dts
new file mode 100755
index 0000000..fd12308
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-2gb.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+#include "bengal-low-ram.dtsi"
+#include "bengal-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL IDP 2Gb DDR HD+";
+ compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp";
+ qcom,board-id = <34 0x403>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_nt36525_truly_video>;
+};
+
+&qupv3_se2_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="novatek,NVT-ts";
+
+ novatek@62 {
+ compatible = "novatek,NVT-ts";
+ reg = <0x62>;
+ status = "ok";
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+
+ novatek,reset-gpio = <&tlmm 71 0x00>;
+ novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+ panel = <&dsi_nt36525_truly_video>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-low-ram.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-low-ram.dtsi
new file mode 100755
index 0000000..f045653
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-low-ram.dtsi
@@ -0,0 +1,2 @@
+#include "bengal-idp.dtsi"
+#include "bengal-idp-pmi632.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi-overlay.dts
new file mode 100755
index 0000000..1bb7fc9
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengal-idp-nopmi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL IDP nopmi";
+ compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp";
+ qcom,msm-id = <417 0x10000>, <444 0x10000>;
+ qcom,board-id = <34 0>;
+ qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi.dts
new file mode 100755
index 0000000..a9f8f46
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "bengal.dtsi"
+#include "bengal-idp-nopmi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL IDP nopmi";
+ compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp";
+ qcom,board-id = <34 0>;
+ qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi.dtsi
new file mode 100755
index 0000000..6f000af
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-nopmi.dtsi
@@ -0,0 +1,53 @@
+#include "bengal-idp.dtsi"
+
+&led_flash_rear {
+ /delete-property/ flash-source;
+ /delete-property/ torch-source;
+ /delete-property/ switch-source;
+};
+
+&led_flash_rear_aux {
+ /delete-property/ flash-source;
+ /delete-property/ torch-source;
+ /delete-property/ switch-source;
+};
+
+&led_flash_rear_aux2 {
+ /delete-property/ flash-source;
+ /delete-property/ torch-source;
+ /delete-property/ switch-source;
+};
+
+&sde_dsi {
+ /delete-property/ lab-supply;
+ /delete-property/ ibb-supply;
+};
+
+&dsi_td4330_truly_v2_video {
+ /delete-property/ qcom,esd-check-enabled;
+};
+
+&dsi_td4330_truly_v2_cmd {
+ /delete-property/ qcom,esd-check-enabled;
+};
+
+&qupv3_se2_i2c {
+ synaptics_tcm@20 {
+ status = "disabled";
+ };
+
+ novatek@62 {
+ status = "disabled";
+ };
+
+ focaltech@38 {
+ status = "disabled";
+ };
+};
+
+&usb0 {
+ /delete-property/ extcon;
+ dwc3@4e00000 {
+ dr_mode = "peripheral";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-overlay.dts
new file mode 100755
index 0000000..31af8ab
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengal-idp.dtsi"
+#include "bengal-idp-pmi632.dtsi"
+#include "bengal-thermal-pmi632-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL IDP";
+ compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp";
+ qcom,msm-id = <417 0x10000>, <444 0x10000>;
+ qcom,board-id = <34 0>;
+ qcom,pmic-id = <0x2D 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-pmi632.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-pmi632.dtsi
new file mode 100755
index 0000000..ac778bd
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-pmi632.dtsi
@@ -0,0 +1,64 @@
+#include "bengal-pmi632.dtsi"
+
+&pmi632_qg {
+ qcom,battery-data = <&mtp_batterydata>;
+ qcom,qg-iterm-ma = <100>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,qg-use-s7-ocv;
+};
+
+&pmi632_charger {
+ qcom,battery-data = <&mtp_batterydata>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,sw-jeita-enable;
+ qcom,step-charging-enable;
+ qcom,hvdcp2-max-icl-ua = <2000000>;
+ /* SMB1355 only */
+ qcom,sec-charger-config = <2>;
+ dpdm-supply = <&qusb_phy0>;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ qcom,auto-recharge-soc = <98>;
+ qcom,flash-disable-soc = <10>;
+ qcom,hw-die-temp-mitigation;
+ qcom,hw-connector-mitigation;
+ qcom,connector-internal-pull-kohm = <100>;
+ qcom,float-option = <1>;
+ qcom,thermal-mitigation = <3000000 2500000
+ 2000000 1500000 1000000 500000>;
+};
+
+&usb0 {
+ extcon = <&pmi632_charger>, <&eud>;
+};
+
+&smb1355 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_int_default>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <105 IRQ_TYPE_LEVEL_LOW>;
+ status = "ok";
+};
+
+&smb1355_charger {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_en_default &pmi632_sense_default &pmi632_ctm_default>;
+ qcom,parallel-mode = <1>;
+ qcom,disable-ctm;
+ qcom,hw-die-temp-mitigation;
+ status = "ok";
+};
+
+&dsi_td4330_truly_v2_video {
+ qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+ qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>;
+};
+
+&dsi_nt36525_truly_video {
+ qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-1gb-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-1gb-overlay.dts
new file mode 100755
index 0000000..91c3725
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-1gb-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengal-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL IDP AATC 1Gb DDR";
+ compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp";
+ qcom,msm-id = <417 0x10000>, <444 0x10000>;
+ qcom,board-id = <34 0x301>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-1gb.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-1gb.dts
new file mode 100755
index 0000000..95ebbd0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-1gb.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "bengal-low-ram.dtsi"
+#include "bengal-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL IDP AATC 1Gb DDR";
+ compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp";
+ qcom,board-id = <34 0x301>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-2gb-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-2gb-overlay.dts
new file mode 100755
index 0000000..4b5b228
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-2gb-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengal-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL IDP AATC 2Gb DDR";
+ compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp";
+ qcom,msm-id = <417 0x10000>, <444 0x10000>;
+ qcom,board-id = <34 0x401>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-2gb.dts
new file mode 100755
index 0000000..d35e02c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-2gb.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "bengal-low-ram.dtsi"
+#include "bengal-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL IDP AATC 2Gb DDR";
+ compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp";
+ qcom,board-id = <34 0x401>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-overlay.dts
new file mode 100755
index 0000000..53da1e4
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc-overlay.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengal-idp.dtsi"
+#include "bengal-idp-pmi632.dtsi"
+#include "bengal-idp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL IDP USBC Audio";
+ compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp";
+ qcom,msm-id = <417 0x10000>, <444 0x10000>;
+ qcom,board-id = <34 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc.dts
new file mode 100755
index 0000000..a0ae3f5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+#include "bengal.dtsi"
+#include "bengal-idp.dtsi"
+#include "bengal-idp-pmi632.dtsi"
+#include "bengal-idp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL IDP USBC Audio";
+ compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp";
+ qcom,board-id = <34 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc.dtsi
new file mode 100755
index 0000000..704385e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp-usbc.dtsi
@@ -0,0 +1,5 @@
+&bengal_snd {
+ qcom,msm-mbhc-usbc-audio-supported = <1>;
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-idp.dts
new file mode 100755
index 0000000..1ad45c7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+#include "bengal.dtsi"
+#include "bengal-idp.dtsi"
+#include "bengal-thermal-pmi632-overlay.dtsi"
+#include "bengal-idp-pmi632.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL IDP";
+ compatible = "qcom,bengal-idp", "qcom,bengal", "qcom,idp";
+ qcom,board-id = <34 0>;
+ qcom,pmic-id = <0x2D 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-idp.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-idp.dtsi
new file mode 100755
index 0000000..160eb3c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-idp.dtsi
@@ -0,0 +1,361 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/input.h>
+#include "bengal-audio-overlay.dtsi"
+#include "bengal-thermal-overlay.dtsi"
+#include "bengal-sde-display.dtsi"
+#include "camera/bengal-camera-sensor-idp.dtsi"
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #include "smb1355.dtsi"
+};
+
+&qupv3_se4_2uart {
+ status = "ok";
+};
+
+&pm6125_vadc {
+ pinctrl-0 = <&camera_therm_default &emmc_therm_default &rf_pa1_therm_default>;
+
+ rf_pa1_therm {
+ reg = <ADC_GPIO4_PU2>;
+ label = "rf_pa1_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm6125_adc_tm {
+ io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>,
+ <&pm6125_vadc ADC_AMUX_THM2_PU2>,
+ <&pm6125_vadc ADC_XO_THERM_PU2>,
+ <&pm6125_vadc ADC_GPIO4_PU2>;
+
+ rf_pa1_therm {
+ reg = <ADC_GPIO4_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&thermal_zones {
+ rf-pa1-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm6125_adc_tm ADC_GPIO4_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&pm6125_gpios {
+
+ rf_pa1_therm {
+ rf_pa1_therm_default: rf_pa1_therm_default {
+ pins = "gpio7";
+ bias-high-impedance;
+ };
+ };
+
+ key_vol_up {
+ key_vol_up_default: key_vol_up_default {
+ pins = "gpio5";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+ };
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ linux,can-disable;
+ debounce-interval = <15>;
+ gpio-key,wakeup;
+ };
+ };
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 70 0x00>;
+ qcom,nq-ven = <&tlmm 69 0x00>;
+ qcom,nq-firm = <&tlmm 31 0x00>;
+ qcom,nq-clkreq = <&tlmm 86 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <70 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&tlmm {
+ smb_int_default: smb_int_default {
+ mux {
+ pins = "gpio105";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio105";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+};
+
+&sdhc_1 {
+ vdd-supply = <&L24A>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L11A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&L22A>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L5A>;
+ qcom,vdd-io-voltage-level = <1800000 2960000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ vdd-io-bias-supply = <&L7A>;
+ qcom,vdd-io-bias-voltage-level = <1256000 1256000>;
+ qcom,vdd-io-bias-current-level = <0 6000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v3-660";
+
+ vdda-phy-supply = <&L4A>; /* 0.9v */
+ vdda-pll-supply = <&L12A>; /* 1.8v */
+ vdda-phy-max-microamp = <51400>;
+ vdda-pll-max-microamp = <14200>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&L24A>;
+ vcc-voltage-level = <2950000 2960000>;
+ vccq2-supply = <&L11A>;
+ vcc-max-microamp = <600000>;
+ vccq2-max-microamp = <600000>;
+ vccq2-pwr-collapse-sup;
+
+ qcom,vddp-ref-clk-supply = <&L18A>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vddp-ref-clk-min-uV = <1232000>;
+ qcom,vddp-ref-clk-max-uV = <1232000>;
+
+ status = "ok";
+};
+
+&pm6125_pwm {
+ status = "ok";
+};
+
+&dsi_td4330_truly_v2_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm6125_pwm 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm6125_pwm 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 81 0>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_nt36525_truly_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm6125_pwm 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_r66451_amoled_hd_90hz_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+ qcom,platform-en-gpio = <&tlmm 83 0>;
+};
+
+&dsi_r66451_amoled_hd_90hz_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 81 0>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+ qcom,platform-en-gpio = <&tlmm 83 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_td4330_truly_v2_video>;
+};
+
+&tlmm {
+ touch_vdd_default: touch_vdd_default {
+ mux {
+ pins = "gpio84";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio84";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ output-high;
+ };
+ };
+};
+
+&soc {
+ touch_vdd: touch_vdd {
+ compatible = "regulator-fixed";
+ regulator-name = "touch_vdd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ pinctrl-names = "default";
+ pinctrl-0 = <&touch_vdd_default>;
+ };
+};
+
+&qupv3_se2_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="synaptics,tcm-i2c";
+
+ synaptics_tcm@20 {
+ compatible = "synaptics,tcm-i2c";
+ reg = <0x20>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+ synaptics,irq-gpio = <&tlmm 80 0x2008>;
+ synaptics,irq-on-state = <0>;
+ synaptics,reset-gpio = <&tlmm 71 0x00>;
+ synaptics,reset-on-state = <0>;
+ synaptics,reset-active-ms = <20>;
+ synaptics,reset-delay-ms = <200>;
+ synaptics,power-delay-ms = <200>;
+ synaptics,ubl-i2c-addr = <0x20>;
+ synaptics,extend_report;
+ synaptics,firmware-name = "synaptics_firmware_k.img";
+
+ panel = <&dsi_td4330_truly_v2_video &dsi_td4330_truly_v2_cmd>;
+ };
+
+ novatek@62 {
+ compatible = "novatek,NVT-ts";
+ reg = <0x62>;
+ status = "ok";
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+
+ novatek,reset-gpio = <&tlmm 71 0x00>;
+ novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+ panel = <&dsi_nt36525_truly_video>;
+ };
+
+ focaltech@38 {
+ compatible = "focaltech,fts_ts";
+ reg = <0x38>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ focaltech,reset-gpio = <&tlmm 71 0x00>;
+ focaltech,irq-gpio = <&tlmm 80 0x2008>;
+ focaltech,max-touch-number = <5>;
+ focaltech,display-coords = <0 0 1080 2340>;
+
+ vdd-supply = <&touch_vdd>;
+
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+
+ panel = <&dsi_r66451_amoled_hd_90hz_video
+ &dsi_r66451_amoled_hd_90hz_cmd>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-ion.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-ion.dtsi
new file mode 100755
index 0000000..b1e71e3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-ion.dtsi
@@ -0,0 +1,50 @@
+&soc {
+ qcom,ion {
+ compatible = "qcom,msm-ion";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ system_heap: qcom,ion-heap@25 {
+ reg = <25>;
+ qcom,ion-heap-type = "SYSTEM";
+ };
+
+ system_secure_heap: qcom,ion-heap@9 {
+ reg = <9>;
+ qcom,ion-heap-type = "SYSTEM_SECURE";
+ };
+
+ qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */
+ reg = <10>;
+ memory-region = <&secure_display_memory>;
+ qcom,ion-heap-type = "HYP_CMA";
+ };
+
+ qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */
+ reg = <14>;
+ qcom,ion-heap-type = "SECURE_CARVEOUT";
+ cdsp {
+ memory-region = <&cdsp_sec_mem>;
+ token = <0x20000000>;
+ };
+ };
+
+ qcom,ion-heap@26 { /* USER CONTIG HEAP */
+ reg = <26>;
+ memory-region = <&user_contig_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@27 { /* QSEECOM HEAP */
+ reg = <27>;
+ memory-region = <&qseecom_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@19 { /* QSEECOM HEAP */
+ reg = <19>;
+ memory-region = <&qseecom_ta_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-2gb.dts
new file mode 100755
index 0000000..cc6fe36
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-2gb.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "bengal-iot-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL-IOT 2Gb DDR HD+ SoC";
+ compatible = "qcom,bengal-iot";
+ qcom,board-id = <0 0x403>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-2gb-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-2gb-overlay.dts
new file mode 100755
index 0000000..8ba5934
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-2gb-overlay.dts
@@ -0,0 +1,40 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengal-iot-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL-IOT IDP 2Gb DDR HD+";
+ compatible = "qcom,bengal-iot-idp", "qcom,bengal-iot", "qcom,idp";
+ qcom,msm-id = <469 0x10000>;
+ qcom,board-id = <34 0x403>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_nt36525_truly_video>;
+};
+
+&qupv3_se2_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="novatek,NVT-ts";
+
+ novatek@62 {
+ compatible = "novatek,NVT-ts";
+ reg = <0x62>;
+ status = "ok";
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+
+ novatek,reset-gpio = <&tlmm 71 0x00>;
+ novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+ panel = <&dsi_nt36525_truly_video>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-2gb.dts
new file mode 100755
index 0000000..50b6b22
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-2gb.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+#include "bengal-iot-low-ram.dtsi"
+#include "bengal-iot-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL-IOT IDP 2Gb DDR HD+";
+ compatible = "qcom,bengal-iot-idp", "qcom,bengal-iot", "qcom,idp";
+ qcom,board-id = <34 0x403>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_nt36525_truly_video>;
+};
+
+&qupv3_se2_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="novatek,NVT-ts";
+
+ novatek@62 {
+ compatible = "novatek,NVT-ts";
+ reg = <0x62>;
+ status = "ok";
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+
+ novatek,reset-gpio = <&tlmm 71 0x00>;
+ novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+ panel = <&dsi_nt36525_truly_video>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-low-ram.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-low-ram.dtsi
new file mode 100755
index 0000000..f76fdf0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-low-ram.dtsi
@@ -0,0 +1 @@
+#include "bengal-iot-idp.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-overlay.dts
new file mode 100755
index 0000000..3afec6e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengal-iot-idp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL-IOT IDP Overlay";
+ compatible = "qcom,bengal-iot-idp", "qcom,bengal-iot", "qcom,idp";
+ qcom,msm-id = <469 0x10000>;
+ qcom,board-id = <34 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc-2gb-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc-2gb-overlay.dts
new file mode 100755
index 0000000..cde5443
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc-2gb-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengal-iot-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL-IOT IDP AATC 2Gb DDR";
+ compatible = "qcom,bengal-iot-idp", "qcom,bengal-iot", "qcom,idp";
+ qcom,msm-id = <469 0x10000>;
+ qcom,board-id = <34 0x401>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc-2gb.dts
new file mode 100755
index 0000000..37ca939
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc-2gb.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "bengal-iot-low-ram.dtsi"
+#include "bengal-iot-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL-IOT IDP AATC 2Gb DDR";
+ compatible = "qcom,bengal-iot-idp", "qcom,bengal-iot", "qcom,idp";
+ qcom,board-id = <34 0x401>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc-overlay.dts
new file mode 100755
index 0000000..a57774fa
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengal-iot-idp.dtsi"
+#include "bengal-iot-idp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL-IOT IDP USBC Audio";
+ compatible = "qcom,bengal-iot-idp", "qcom,bengal-iot", "qcom,idp";
+ qcom,msm-id = <469 0x10000>;
+ qcom,board-id = <34 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc.dts
new file mode 100755
index 0000000..1d9a563
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "bengal-iot.dtsi"
+#include "bengal-iot-idp.dtsi"
+#include "bengal-iot-idp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL-IOT IDP USBC Audio";
+ compatible = "qcom,bengal-iot-idp", "qcom,bengal-iot", "qcom,idp";
+ qcom,board-id = <34 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc.dtsi
new file mode 100755
index 0000000..704385e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp-usbc.dtsi
@@ -0,0 +1,5 @@
+&bengal_snd {
+ qcom,msm-mbhc-usbc-audio-supported = <1>;
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp.dts
new file mode 100755
index 0000000..6457f123
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "bengal-iot.dtsi"
+#include "bengal-iot-idp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL-IOT IDP";
+ compatible = "qcom,bengal-iot-idp", "qcom,bengal-iot", "qcom,idp";
+ qcom,board-id = <34 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp.dtsi
new file mode 100755
index 0000000..f045653
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-idp.dtsi
@@ -0,0 +1,2 @@
+#include "bengal-idp.dtsi"
+#include "bengal-idp-pmi632.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot-low-ram.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-low-ram.dtsi
new file mode 100755
index 0000000..ab4a6ae
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot-low-ram.dtsi
@@ -0,0 +1,148 @@
+#include "bengal-iot.dtsi"
+/ {
+};
+
+/delete-node/ &hyp_mem;
+/delete-node/ &xbl_aop_mem;
+/delete-node/ &sec_apps_mem;
+/delete-node/ &smem_mem;
+/delete-node/ &removed_mem;
+/delete-node/ &pil_modem_mem;
+/delete-node/ &pil_video_mem;
+/delete-node/ &wlan_msa_mem;
+/delete-node/ &pil_cdsp_mem;
+/delete-node/ &pil_adsp_mem;
+/delete-node/ &pil_ipa_fw_mem;
+/delete-node/ &pil_ipa_gsi_mem;
+/delete-node/ &pil_gpu_mem;
+/delete-node/ &cdsp_sec_mem;
+
+/delete-node/ &user_contig_mem;
+/delete-node/ &qseecom_mem;
+/delete-node/ &qseecom_ta_mem;
+
+/delete-node/ &secure_display_memory;
+
+/delete-node/ &disp_rdump_memory;
+
+&reserved_memory {
+ hyp_mem: hyp_region@45700000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45700000 0x0 0x600000>;
+ };
+
+ xbl_aop_mem: xbl_aop_region@45e00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45e00000 0x0 0x100000>;
+ };
+
+ sec_apps_mem: sec_apps_region@45fff000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45fff000 0x0 0x1000>;
+ };
+
+ smem_mem: smem_region@46000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x46000000 0x0 0x200000>;
+ };
+
+ pil_modem_mem: modem_region@4ab00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x4ab00000 0x0 0x6900000>;
+ };
+
+ pil_video_mem: pil_video_region@51400000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51400000 0x0 0x500000>;
+ };
+
+ wlan_msa_mem: wlan_msa_region@51900000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51900000 0x0 0x100000>;
+ };
+
+ pil_cdsp_mem: cdsp_regions@51a00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51a00000 0x0 0x800000>;
+ };
+
+ pil_adsp_mem: pil_adsp_region@52200000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x52200000 0x0 0x1c00000>;
+ };
+
+ pil_ipa_fw_mem: ipa_fw_region@53e00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x53e00000 0x0 0x10000>;
+ };
+
+ pil_ipa_gsi_mem: ipa_gsi_region@53e10000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x53e10000 0x0 0x5000>;
+ };
+
+ pil_gpu_mem: gpu_region@53e15000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x53e15000 0x0 0x2000>;
+ };
+
+ tz_stat_mem: tz_stat_region@60000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x60000000 0x0 0x100000>;
+ };
+
+ removed_mem: removed_region@60100000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x60100000 0x0 0x2200000>;
+ };
+
+ qseecom_mem: qseecom_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ qseecom_ta_mem: qseecom_ta_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x400000>;
+ };
+
+ linux,cma {
+ size = <0x0 0x1000000>;
+ };
+};
+
+&soc {
+ qcom,ion {
+ /delete-node/ qcom,ion-heap@14;
+ /delete-node/ qcom,ion-heap@10;
+ /delete-node/ qcom,ion-heap@26;
+ };
+
+ qcom_seecom: qseecom@61800000 {
+ reg = <0x61800000 0xb00000>;
+ };
+
+ qcom_smcinvoke: smcinvoke@61800000 {
+ reg = <0x61800000 0xb00000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-iot.dts
new file mode 100755
index 0000000..2a5be79
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "bengal-iot.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL-IOT SoC";
+ compatible = "qcom,bengal-iot";
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-iot.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-iot.dtsi
new file mode 100755
index 0000000..794b85b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-iot.dtsi
@@ -0,0 +1,9 @@
+#include "bengal.dtsi"
+#include "bengal-pmi632.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL-IOT";
+ compatible = "qcom,bengal-iot";
+ qcom,msm-id = <469 0x0>;
+ qcom,msm-name = "BENGAL-IOT";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-low-ram.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-low-ram.dtsi
new file mode 100755
index 0000000..05c53c5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-low-ram.dtsi
@@ -0,0 +1,149 @@
+#include "bengal.dtsi"
+#include "bengal-pmi632.dtsi"
+/ {
+};
+
+/delete-node/ &hyp_mem;
+/delete-node/ &xbl_aop_mem;
+/delete-node/ &sec_apps_mem;
+/delete-node/ &smem_mem;
+/delete-node/ &removed_mem;
+/delete-node/ &pil_modem_mem;
+/delete-node/ &pil_video_mem;
+/delete-node/ &wlan_msa_mem;
+/delete-node/ &pil_cdsp_mem;
+/delete-node/ &pil_adsp_mem;
+/delete-node/ &pil_ipa_fw_mem;
+/delete-node/ &pil_ipa_gsi_mem;
+/delete-node/ &pil_gpu_mem;
+/delete-node/ &cdsp_sec_mem;
+
+/delete-node/ &user_contig_mem;
+/delete-node/ &qseecom_mem;
+/delete-node/ &qseecom_ta_mem;
+
+/delete-node/ &secure_display_memory;
+
+/delete-node/ &disp_rdump_memory;
+
+&reserved_memory {
+ hyp_mem: hyp_region@45700000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45700000 0x0 0x600000>;
+ };
+
+ xbl_aop_mem: xbl_aop_region@45e00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45e00000 0x0 0x100000>;
+ };
+
+ sec_apps_mem: sec_apps_region@45fff000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45fff000 0x0 0x1000>;
+ };
+
+ smem_mem: smem_region@46000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x46000000 0x0 0x200000>;
+ };
+
+ pil_modem_mem: modem_region@4ab00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x4ab00000 0x0 0x6900000>;
+ };
+
+ pil_video_mem: pil_video_region@51400000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51400000 0x0 0x500000>;
+ };
+
+ wlan_msa_mem: wlan_msa_region@51900000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51900000 0x0 0x100000>;
+ };
+
+ pil_cdsp_mem: cdsp_regions@51a00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51a00000 0x0 0x800000>;
+ };
+
+ pil_adsp_mem: pil_adsp_region@52200000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x52200000 0x0 0x1c00000>;
+ };
+
+ pil_ipa_fw_mem: ipa_fw_region@53e00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x53e00000 0x0 0x10000>;
+ };
+
+ pil_ipa_gsi_mem: ipa_gsi_region@53e10000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x53e10000 0x0 0x5000>;
+ };
+
+ pil_gpu_mem: gpu_region@53e15000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x53e15000 0x0 0x2000>;
+ };
+
+ tz_stat_mem: tz_stat_region@60000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x60000000 0x0 0x100000>;
+ };
+
+ removed_mem: removed_region@60100000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x60100000 0x0 0x2200000>;
+ };
+
+ qseecom_mem: qseecom_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ qseecom_ta_mem: qseecom_ta_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x400000>;
+ };
+
+ linux,cma {
+ size = <0x0 0x1000000>;
+ };
+};
+
+&soc {
+ qcom,ion {
+ /delete-node/ qcom,ion-heap@14;
+ /delete-node/ qcom,ion-heap@10;
+ /delete-node/ qcom,ion-heap@26;
+ };
+
+ qcom_seecom: qseecom@61800000 {
+ reg = <0x61800000 0xb00000>;
+ };
+
+ qcom_smcinvoke: smcinvoke@61800000 {
+ reg = <0x61800000 0xb00000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-lpi.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-lpi.dtsi
new file mode 100755
index 0000000..4bcd1af
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-lpi.dtsi
@@ -0,0 +1,1957 @@
+&q6core {
+ lpi_tlmm: lpi_pinctrl@ac40000 {
+ compatible = "qcom,lpi-pinctrl";
+ reg = <0xa7c0000 0x0>;
+ qcom,slew-reg = <0xa95a000 0x0>;
+ qcom,num-gpios = <19>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
+ <0x00002000>, <0x00003000>,
+ <0x00004000>, <0x00005000>,
+ <0x00006000>, <0x00007000>,
+ <0x00008000>, <0x00009000>,
+ <0x0000A000>, <0x0000B000>,
+ <0x0000C000>, <0x0000D000>,
+ <0x0000E000>, <0x0000F000>,
+ <0x00010000>, <0x00011000>,
+ <0x00012000>;
+ qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>,
+ <0x00000004>, <0x00000008>,
+ <0x0000000A>, <0x0000000C>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000014>;
+
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+
+ quat_mi2s_sck {
+ quat_mi2s_sck_sleep: quat_mi2s_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sck_active: quat_mi2s_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_ws {
+ quat_mi2s_ws_sleep: quat_mi2s_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_ws_active: quat_mi2s_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd0 {
+ quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd0_active: quat_mi2s_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd1 {
+ quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd1_active: quat_mi2s_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd2 {
+ quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd2_active: quat_mi2s_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd3 {
+ quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd3_active: quat_mi2s_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sck {
+ lpi_i2s1_sck_sleep: lpi_i2s1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sck_active: lpi_i2s1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_ws {
+ lpi_i2s1_ws_sleep: lpi_i2s1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_ws_active: lpi_i2s1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sd0 {
+ lpi_i2s1_sd0_sleep: lpi_i2s1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sd0_active: lpi_i2s1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sd1 {
+ lpi_i2s1_sd1_sleep: lpi_i2s1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sd1_active: lpi_i2s1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sck {
+ lpi_i2s2_sck_sleep: lpi_i2s2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sck_active: lpi_i2s2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_ws {
+ lpi_i2s2_ws_sleep: lpi_i2s2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_ws_active: lpi_i2s2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sd0 {
+ lpi_i2s2_sd0_sleep: lpi_i2s2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sd0_active: lpi_i2s2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sd1 {
+ lpi_i2s2_sd1_sleep: lpi_i2s2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sd1_active: lpi_i2s2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s3_sck {
+ lpi_i2s3_sck_sleep: lpi_i2s3_sck_sleep {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s3_sck_active: lpi_i2s3_sck_active {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s3_ws {
+ lpi_i2s3_ws_sleep: lpi_i2s3_ws_sleep {
+ mux {
+ pins = "gpio15";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio15";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s3_ws_active: lpi_i2s3_ws_active {
+ mux {
+ pins = "gpio15";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio15";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s3_sd0 {
+ lpi_i2s3_sd0_sleep: lpi_i2s3_sd0_sleep {
+ mux {
+ pins = "gpio16";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s3_sd0_active: lpi_i2s3_sd0_active {
+ mux {
+ pins = "gpio16";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s3_sd1 {
+ lpi_i2s3_sd1_sleep: lpi_i2s3_sd1_sleep {
+ mux {
+ pins = "gpio17";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s3_sd1_active: lpi_i2s3_sd1_active {
+ mux {
+ pins = "gpio17";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sck {
+ quat_tdm_sck_sleep: quat_tdm_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sck_active: quat_tdm_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_ws {
+ quat_tdm_ws_sleep: quat_tdm_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_ws_active: quat_tdm_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd0 {
+ quat_tdm_sd0_sleep: quat_tdm_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd0_active: quat_tdm_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd1 {
+ quat_tdm_sd1_sleep: quat_tdm_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd1_active: quat_tdm_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd2 {
+ quat_tdm_sd2_sleep: quat_tdm_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd2_active: quat_tdm_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd3 {
+ quat_tdm_sd3_sleep: quat_tdm_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd3_active: quat_tdm_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sck {
+ lpi_tdm1_sck_sleep: lpi_tdm1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sck_active: lpi_tdm1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_ws {
+ lpi_tdm1_ws_sleep: lpi_tdm1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_ws_active: lpi_tdm1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sd0 {
+ lpi_tdm1_sd0_sleep: lpi_tdm1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sd0_active: lpi_tdm1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sd1 {
+ lpi_tdm1_sd1_sleep: lpi_tdm1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sd1_active: lpi_tdm1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sck {
+ lpi_tdm2_sck_sleep: lpi_tdm2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sck_active: lpi_tdm2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_ws {
+ lpi_tdm2_ws_sleep: lpi_tdm2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_ws_active: lpi_tdm2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sd0 {
+ lpi_tdm2_sd0_sleep: lpi_tdm2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sd0_active: lpi_tdm2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sd1 {
+ lpi_tdm2_sd1_sleep: lpi_tdm2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sd1_active: lpi_tdm2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm3_sck {
+ lpi_tdm3_sck_sleep: lpi_tdm3_sck_sleep {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm3_sck_active: lpi_tdm3_sck_active {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm3_ws {
+ lpi_tdm3_ws_sleep: lpi_tdm3_ws_sleep {
+ mux {
+ pins = "gpio15";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio15";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm3_ws_active: lpi_tdm3_ws_active {
+ mux {
+ pins = "gpio15";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio15";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm3_sd0 {
+ lpi_tdm3_sd0_sleep: lpi_tdm3_sd0_sleep {
+ mux {
+ pins = "gpio16";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm3_sd0_active: lpi_tdm3_sd0_active {
+ mux {
+ pins = "gpio16";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm3_sd1 {
+ lpi_tdm3_sd1_sleep: lpi_tdm3_sd1_sleep {
+ mux {
+ pins = "gpio17";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm3_sd1_active: lpi_tdm3_sd1_active {
+ mux {
+ pins = "gpio17";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sck {
+ quat_aux_sck_sleep: quat_aux_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sck_active: quat_aux_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_ws {
+ quat_aux_ws_sleep: quat_aux_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_ws_active: quat_aux_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd0 {
+ quat_aux_sd0_sleep: quat_aux_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd0_active: quat_aux_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd1 {
+ quat_aux_sd1_sleep: quat_aux_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd1_active: quat_aux_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd2 {
+ quat_aux_sd2_sleep: quat_aux_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd2_active: quat_aux_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd3 {
+ quat_aux_sd3_sleep: quat_aux_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd3_active: quat_aux_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sck {
+ lpi_aux1_sck_sleep: lpi_aux1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sck_active: lpi_aux1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_ws {
+ lpi_aux1_ws_sleep: lpi_aux1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_ws_active: lpi_aux1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sd0 {
+ lpi_aux1_sd0_sleep: lpi_aux1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sd0_active: lpi_aux1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sd1 {
+ lpi_aux1_sd1_sleep: lpi_aux1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sd1_active: lpi_aux1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sck {
+ lpi_aux2_sck_sleep: lpi_aux2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sck_active: lpi_aux2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_ws {
+ lpi_aux2_ws_sleep: lpi_aux2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_ws_active: lpi_aux2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sd0 {
+ lpi_aux2_sd0_sleep: lpi_aux2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sd0_active: lpi_aux2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sd1 {
+ lpi_aux2_sd1_sleep: lpi_aux2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sd1_active: lpi_aux2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux3_sck {
+ lpi_aux3_sck_sleep: lpi_aux3_sck_sleep {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux3_sck_active: lpi_aux3_sck_active {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux3_ws {
+ lpi_aux3_ws_sleep: lpi_aux3_ws_sleep {
+ mux {
+ pins = "gpio15";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio15";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux3_ws_active: lpi_aux3_ws_active {
+ mux {
+ pins = "gpio15";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio15";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux3_sd0 {
+ lpi_aux3_sd0_sleep: lpi_aux3_sd0_sleep {
+ mux {
+ pins = "gpio16";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux3_sd0_active: lpi_aux3_sd0_active {
+ mux {
+ pins = "gpio16";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux3_sd1 {
+ lpi_aux3_sd1_sleep: lpi_aux3_sd1_sleep {
+ mux {
+ pins = "gpio17";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux3_sd1_active: lpi_aux3_sd1_active {
+ mux {
+ pins = "gpio17";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ tx_swr_clk_sleep: tx_swr_clk_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func1";
+ input-enable;
+ bias-pull-down;
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <10>;
+ };
+ };
+
+ tx_swr_clk_active: tx_swr_clk_active {
+ mux {
+ pins = "gpio0";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-disable;
+ };
+ };
+
+ tx_swr_data1_sleep: tx_swr_data1_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <10>;
+ input-enable;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_data1_active: tx_swr_data1_active {
+ mux {
+ pins = "gpio1";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_data2_sleep: tx_swr_data2_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <10>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ tx_swr_data2_active: tx_swr_data2_active {
+ mux {
+ pins = "gpio2";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_clk_sleep: rx_swr_clk_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <10>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_clk_active: rx_swr_clk_active {
+ mux {
+ pins = "gpio3";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-disable;
+ };
+ };
+
+ rx_swr_data_sleep: rx_swr_data_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <10>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_data_active: rx_swr_data_active {
+ mux {
+ pins = "gpio4";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_data1_sleep: rx_swr_data1_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <10>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_data1_active: rx_swr_data1_active {
+ mux {
+ pins = "gpio5";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ cdc_dmic01_clk_active: dmic01_clk_active {
+ mux {
+ pins = "gpio6";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic01_clk_sleep: dmic01_clk_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic01_data_active: dmic01_data_active {
+ mux {
+ pins = "gpio7";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic01_data_sleep: dmic01_data_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ cdc_dmic23_clk_active: dmic23_clk_active {
+ mux {
+ pins = "gpio8";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic23_clk_sleep: dmic23_clk_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic23_data_active: dmic23_data_active {
+ mux {
+ pins = "gpio9";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic23_data_sleep: dmic23_data_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ wsa_mclk_sleep: wsa_mclk_sleep {
+ mux {
+ pins = "gpio18";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio18";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ };
+ };
+
+ wsa_mclk_active: wsa_mclk_active {
+ mux {
+ pins = "gpio18";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio18";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-pinctrl.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-pinctrl.dtsi
new file mode 100755
index 0000000..b322d1a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-pinctrl.dtsi
@@ -0,0 +1,1197 @@
+&soc {
+ tlmm: pinctrl@400000 {
+ compatible = "qcom,bengal-pinctrl";
+ reg = <0x400000 0xc00000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ wakeup-parent = <&wakegpio>;
+ irqdomain-map = <0 0 &wakegpio 84 0>,
+ <3 0 &wakegpio 75 0>,
+ <4 0 &wakegpio 16 0>,
+ <6 0 &wakegpio 59 0>,
+ <8 0 &wakegpio 63 0>,
+ <11 0 &wakegpio 17 0>,
+ <13 0 &wakegpio 18 0>,
+ <14 0 &wakegpio 51 0>,
+ <17 0 &wakegpio 20 0>,
+ <18 0 &wakegpio 52 0>,
+ <19 0 &wakegpio 53 0>,
+ <24 0 &wakegpio 6 0>,
+ <25 0 &wakegpio 71 0>,
+ <27 0 &wakegpio 73 0>,
+ <28 0 &wakegpio 41 0>,
+ <31 0 &wakegpio 27 0>,
+ <32 0 &wakegpio 54 0>,
+ <33 0 &wakegpio 55 0>,
+ <34 0 &wakegpio 56 0>,
+ <35 0 &wakegpio 57 0>,
+ <36 0 &wakegpio 58 0>,
+ <39 0 &wakegpio 28 0>,
+ <46 0 &wakegpio 29 0>,
+ <62 0 &wakegpio 60 0>,
+ <63 0 &wakegpio 61 0>,
+ <64 0 &wakegpio 62 0>,
+ <65 0 &wakegpio 30 0>,
+ <66 0 &wakegpio 31 0>,
+ <67 0 &wakegpio 32 0>,
+ <69 0 &wakegpio 33 0>,
+ <70 0 &wakegpio 34 0>,
+ <72 0 &wakegpio 72 0>,
+ <75 0 &wakegpio 35 0>,
+ <79 0 &wakegpio 36 0>,
+ <80 0 &wakegpio 21 0>,
+ <81 0 &wakegpio 38 0>,
+ <83 0 &wakegpio 9 0>,
+ <84 0 &wakegpio 39 0>,
+ <85 0 &wakegpio 40 0>,
+ <86 0 &wakegpio 19 0>,
+ <87 0 &wakegpio 42 0>,
+ <88 0 &wakegpio 43 0>,
+ <89 0 &wakegpio 45 0>,
+ <91 0 &wakegpio 74 0>,
+ <93 0 &wakegpio 46 0>,
+ <94 0 &wakegpio 47 0>,
+ <95 0 &wakegpio 48 0>,
+ <96 0 &wakegpio 49 0>,
+ <97 0 &wakegpio 50 0>,
+ <99 0 &wakegpio 64 0>, /* LPI_GPIO 7 */
+ <102 0 &wakegpio 65 0>, /* LPI_GPIO 10 */
+ <103 0 &wakegpio 66 0>, /* LPI_GPIO 11 */
+ <104 0 &wakegpio 67 0>, /* LPI_GPIO 12 */
+ <105 0 &wakegpio 69 0>, /* LPI_GPIO 17 */
+ <106 0 &wakegpio 14 0>, /* LPI_GPIO 16 */
+ <107 0 &wakegpio 7 0>, /* LPI_GPIO 17 */
+ <109 0 &wakegpio 37 0>, /* LPI_GPIO 19 */
+ <112 0 &wakegpio 25 0>; /* LPI_GPIO 24 */
+ irqdomain-map-pass-thru = <0 0xff>;
+ irqdomain-map-mask = <0xff 0>;
+
+ ufs_dev_reset_assert: ufs_dev_reset_assert {
+ config {
+ pins = "ufs_reset";
+ bias-pull-down; /* default: pull down */
+ /*
+ * UFS_RESET driver strengths are having
+ * different values/steps compared to typical
+ * GPIO drive strengths.
+ *
+ * Following table clarifies:
+ *
+ * HDRV value | UFS_RESET | Typical GPIO
+ * (dec) | (mA) | (mA)
+ * 0 | 0.8 | 2
+ * 1 | 1.55 | 4
+ * 2 | 2.35 | 6
+ * 3 | 3.1 | 8
+ * 4 | 3.9 | 10
+ * 5 | 4.65 | 12
+ * 6 | 5.4 | 14
+ * 7 | 6.15 | 16
+ *
+ * POR value for UFS_RESET HDRV is 3 which means
+ * 3.1mA and we want to use that. Hence just
+ * specify 8mA to "drive-strength" binding and
+ * that should result into writing 3 to HDRV
+ * field.
+ */
+ drive-strength = <8>; /* default: 3.1 mA */
+ output-low; /* active low reset */
+ };
+ };
+
+ ufs_dev_reset_deassert: ufs_dev_reset_deassert {
+ config {
+ pins = "ufs_reset";
+ bias-pull-down; /* default: pull down */
+ /*
+ * default: 3.1 mA
+ * check comments under ufs_dev_reset_assert
+ */
+ drive-strength = <8>;
+ output-high; /* active low reset */
+ };
+ };
+
+ /* SDC pin type */
+ sdc1_clk_on: sdc1_clk_on {
+ config {
+ pins = "sdc1_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc1_clk_off: sdc1_clk_off {
+ config {
+ pins = "sdc1_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_cmd_on: sdc1_cmd_on {
+ config {
+ pins = "sdc1_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc1_cmd_off: sdc1_cmd_off {
+ config {
+ pins = "sdc1_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_data_on: sdc1_data_on {
+ config {
+ pins = "sdc1_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc1_data_off: sdc1_data_off {
+ config {
+ pins = "sdc1_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_rclk_on: sdc1_rclk_on {
+ config {
+ pins = "sdc1_rclk";
+ bias-pull-down; /* pull down */
+ };
+ };
+
+ sdc1_rclk_off: sdc1_rclk_off {
+ config {
+ pins = "sdc1_rclk";
+ bias-pull-down; /* pull down */
+ };
+ };
+
+ sdc2_clk_on: sdc2_clk_on {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_clk_off: sdc2_clk_off {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_cmd_on: sdc2_cmd_on {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_cmd_off: sdc2_cmd_off {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_data_on: sdc2_data_on {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_data_off: sdc2_data_off {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_cd_on: cd_on {
+ mux {
+ pins = "gpio88";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio88";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_cd_off: cd_off {
+ mux {
+ pins = "gpio88";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio88";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ tb_trig1_on: tb_trig1_on {
+ mux {
+ pins = "gpio19";
+ function = "SDC1_TB";
+ };
+
+ config {
+ pins = "gpio19";
+ bias-pull-up; /* PULL UP */
+ drive-strength = <8>; /* 8 MA */
+ input-enable;
+ };
+ };
+
+ /* WSA speaker reset pin1 */
+ spkr_1_sd_n {
+ spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+ mux {
+ pins = "gpio106";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio106";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_1_sd_n_active: spkr_1_sd_n_active {
+ mux {
+ pins = "gpio106";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio106";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ wcd937x_reset_active: wcd937x_reset_active {
+ mux {
+ pins = "gpio92";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio92";
+ drive-strength = <16>;
+ output-high;
+ };
+ };
+
+ wcd937x_reset_sleep: wcd937x_reset_sleep {
+ mux {
+ pins = "gpio92";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio92";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ qupv3_se4_2uart_pins: qupv3_se4_2uart_pins {
+ qupv3_se4_2uart_active: qupv3_se4_2uart_active {
+ mux {
+ pins = "gpio12", "gpio13";
+ function = "qup4";
+ };
+
+ config {
+ pins = "gpio12", "gpio13";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep {
+ mux {
+ pins = "gpio12", "gpio13";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio12", "gpio13";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ qupv3_se3_4uart_pins: qupv3_se3_4uart_pins {
+ qupv3_se3_default_ctsrtsrx:
+ qupv3_se3_default_ctsrtsrx {
+ mux {
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8", "gpio9", "gpio11";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ qupv3_se3_default_tx:
+ qupv3_se3_default_tx {
+ mux {
+ pins = "gpio10";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se3_ctsrx: qupv3_se3_ctsrx {
+ mux {
+ pins = "gpio8", "gpio11";
+ function = "qup3";
+ };
+
+ config {
+ pins = "gpio8", "gpio11";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se3_rts: qupv3_se3_rts {
+ mux {
+ pins = "gpio9";
+ function = "qup3";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ qupv3_se3_tx: qupv3_se3_tx {
+ mux {
+ pins = "gpio10";
+ function = "qup3";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
+ qupv3_se0_i2c_active: qupv3_se0_i2c_active {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "qup0";
+ };
+
+ config {
+ pins = "gpio0", "gpio1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio0", "gpio1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
+ qupv3_se1_i2c_active: qupv3_se1_i2c_active {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "qup1";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ nfc {
+ nfc_int_active: nfc_int_active {
+ /* active state */
+ mux {
+ /* GPIO 70 NFC Read Interrupt */
+ pins = "gpio70";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio70";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_int_suspend: nfc_int_suspend {
+ /* sleep state */
+ mux {
+ /* GPIO 70 NFC Read Interrupt */
+ pins = "gpio70";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio70";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_enable_active: nfc_enable_active {
+ /* active state */
+ mux {
+ /* 69: Enable 31: Firmware */
+ pins = "gpio69", "gpio31";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio69", "gpio31";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_enable_suspend: nfc_enable_suspend {
+ /* sleep state */
+ mux {
+ /* 69: Enable 31: Firmware */
+ pins = "gpio69", "gpio31";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio69", "gpio31";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable;
+ };
+ };
+
+ nfc_clk_req_active: nfc_clk_req_active {
+ /* active state */
+ mux {
+ /* GPIO 86: NFC CLOCK REQUEST */
+ pins = "gpio86";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio86";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_clk_req_suspend: nfc_clk_req_suspend {
+ /* sleep state */
+ mux {
+ /* GPIO 86: NFC CLOCK REQUEST */
+ pins = "gpio86";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio86";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable;
+ };
+ };
+ };
+
+
+ qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
+ qupv3_se2_i2c_active: qupv3_se2_i2c_active {
+ mux {
+ pins = "gpio6", "gpio7";
+ function = "qup2";
+ };
+
+ config {
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
+ mux {
+ pins = "gpio6", "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ qupv3_se0_spi_pins: qupv3_se0_spi_pins {
+ qupv3_se0_spi_active: qupv3_se0_spi_active {
+ mux {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ function = "qup0";
+ };
+
+ config {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
+ mux {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se1_spi_pins: qupv3_se1_spi_pins {
+ qupv3_se1_spi_active: qupv3_se1_spi_active {
+ mux {
+ pins = "gpio4", "gpio5",
+ "gpio69", "gpio70";
+ function = "qup1";
+ };
+
+ config {
+ pins = "gpio4", "gpio5",
+ "gpio69", "gpio70";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
+ mux {
+ pins = "gpio4", "gpio5",
+ "gpio69", "gpio70";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio4", "gpio5",
+ "gpio69", "gpio70";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se5_spi_pins: qupv3_se5_spi_pins {
+ qupv3_se5_spi_active: qupv3_se5_spi_active {
+ mux {
+ pins = "gpio14", "gpio15",
+ "gpio16", "gpio17";
+ function = "qup5";
+ };
+
+ config {
+ pins = "gpio14", "gpio15",
+ "gpio16", "gpio17";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
+ mux {
+ pins = "gpio14", "gpio15",
+ "gpio16", "gpio17";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio14", "gpio15",
+ "gpio16", "gpio17";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ cci0_suspend: cci0_suspend {
+ mux {
+ /* CLK, DATA*/
+ pins = "gpio23", "gpio22";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio23", "gpio22";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci0_active: cci0_active {
+ mux {
+ /* CLK, DATA*/
+ pins = "gpio23", "gpio22";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio23", "gpio22";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci1_suspend: cci1_suspend {
+ mux {
+ /* CLK, DATA*/
+ pins = "gpio30", "gpio29";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio30", "gpio29";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci1_active: cci1_active {
+ mux {
+ /* CLK, DATA*/
+ pins = "gpio30", "gpio29";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio30", "gpio29";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk0_active: cam_sensor_mclk0_active {
+ /* MCLK 0*/
+ mux {
+ pins = "gpio20";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio20";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
+ /* MCLK 0*/
+ mux {
+ pins = "gpio20";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio20";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk1_active: cam_sensor_mclk1_active {
+ /* MCLK 1*/
+ mux {
+ pins = "gpio21";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio21";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
+ /* MCLK 1*/
+ mux {
+ pins = "gpio21";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio21";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk2_active: cam_sensor_mclk2_active {
+ /* MCLK 2*/
+ mux {
+ pins = "gpio27";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio27";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
+ /* MCLK 2*/
+ mux {
+ pins = "gpio27";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio27";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk3_active: cam_sensor_mclk3_active {
+ /* MCLK 3*/
+ mux {
+ pins = "gpio28";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio28";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend {
+ /* MCLK 3*/
+ mux {
+ pins = "gpio28";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio28";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear0_reset_active: cam_sensor_rear0_reset_active {
+ /* RESET0 */
+ mux {
+ pins = "gpio18";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio18";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear0_reset_suspend: cam_sensor_rear0_reset_suspend {
+ /* RESET0 */
+ mux {
+ pins = "gpio18";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio18";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_rear1_reset_active: cam_sensor_rear1_reset_active {
+ /* RESET1 */
+ mux {
+ pins = "gpio19";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio19";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear1_reset_suspend: cam_sensor_rear1_reset_suspend {
+ /* RESET1 */
+ mux {
+ pins = "gpio19";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio19";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_rear2_reset_active: cam_sensor_rear2_reset_active {
+ /* RESET2 */
+ mux {
+ pins = "gpio65";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio65";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear2_reset_suspend: cam_sensor_rear2_reset_suspend {
+ /* RESET2 */
+ mux {
+ pins = "gpio65";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio65";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_front0_reset_active: cam_sensor_front0_reset_active {
+ /* RESET0 */
+ mux {
+ pins = "gpio24";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio24";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_front0_reset_suspend: cam_sensor_front0_reset_suspend {
+ /* RESET0 */
+ mux {
+ pins = "gpio24";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio24";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_csi_mux_oe_active: cam_sensor_csi_mux_oe_active {
+ /*CSIMUX_OE*/
+ mux {
+ pins = "gpio66";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio66";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_csi_mux_oe_suspend: cam_sensor_csi_mux_oe_suspend {
+ /* CSIMUX_OE */
+ mux {
+ pins = "gpio66";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio66";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_csi_mux_sel_active: cam_sensor_csi_mux_sel_active {
+ /*CSIMUX_SEL*/
+ mux {
+ pins = "gpio67";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio67";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_csi_mux_sel_suspend: cam_sensor_csi_mux_sel_suspend {
+ /* CSIMUX_SEL */
+ mux {
+ pins = "gpio67";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio67";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ pmx_sde: pmx_sde {
+ sde_dsi_active: sde_dsi_active {
+ mux {
+ pins = "gpio82";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio82";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ };
+ };
+
+ sde_dsi_suspend: sde_dsi_suspend {
+ mux {
+ pins = "gpio82";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio82";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_sde_te {
+ sde_te_active: sde_te_active {
+ mux {
+ pins = "gpio81";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio81";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ sde_te_suspend: sde_te_suspend {
+ mux {
+ pins = "gpio81";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio81";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_int_active {
+ ts_int_active: ts_int_active {
+ mux {
+ pins = "gpio80";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio80";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_int_suspend {
+ ts_int_suspend: ts_int_suspend {
+ mux {
+ pins = "gpio80";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio80";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_reset_active {
+ ts_reset_active: ts_reset_active {
+ mux {
+ pins = "gpio71";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio71";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_reset_suspend {
+ ts_reset_suspend: ts_reset_suspend {
+ mux {
+ pins = "gpio71";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio71";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_release {
+ ts_release: ts_release {
+ mux {
+ pins = "gpio80", "gpio71";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio80", "gpio71";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pm8008_active: pm8008_active {
+ mux {
+ pins = "gpio26";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio26";
+ bias-pull-up;
+ output-high;
+ drive-strength = <2>;
+ };
+ };
+
+ pm8008_interrupt: pm8008_interrupt {
+ mux {
+ pins = "gpio25";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio25";
+ bias-disable;
+ input-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-pm.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-pm.dtsi
new file mode 100755
index 0000000..059d29f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-pm.dtsi
@@ -0,0 +1,192 @@
+&soc {
+ qcom,lpm-levels {
+ compatible = "qcom,lpm-levels";
+ qcom,use-psci;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,pm-cluster@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "system";
+ qcom,spm-device-names = "cci";
+ qcom,psci-mode-shift = <8>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cluster-level@0 {
+ reg = <0>;
+ label = "system-wfi";
+ qcom,psci-mode = <0x0>;
+ qcom,entry-latency-us = <640>;
+ qcom,exit-latency-us = <1654>;
+ qcom,min-residency-us = <2294>;
+ };
+
+ qcom,pm-cluster-level@1 { /* E3 */
+ reg = <1>;
+ label = "system-pc";
+ qcom,psci-mode = <0x3>;
+ qcom,entry-latency-us = <10831>;
+ qcom,exit-latency-us = <4506>;
+ qcom,min-residency-us = <15338>;
+ qcom,min-child-idx = <2>;
+ qcom,notify-rpm;
+ qcom,is-reset;
+ };
+
+ qcom,pm-cluster@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "pwr";
+ qcom,spm-device-names = "l2";
+ qcom,psci-mode-shift = <4>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cluster-level@0 { /* D1 */
+ reg = <0>;
+ label = "pwr-l2-wfi";
+ qcom,psci-mode = <0x1>;
+ qcom,entry-latency-us = <38>;
+ qcom,exit-latency-us = <51>;
+ qcom,min-residency-us = <89>;
+ };
+
+ qcom,pm-cluster-level@1 { /* D3G */
+ reg = <1>;
+ label = "pwr-l2-gdhs";
+ qcom,psci-mode = <0x2>;
+ qcom,entry-latency-us = <360>;
+ qcom,exit-latency-us = <421>;
+ qcom,min-residency-us = <782>;
+ qcom,min-child-idx = <1>;
+ };
+
+ qcom,pm-cluster-level@2 { /* D3 */
+ reg = <2>;
+ label = "pwr-l2-pc";
+ qcom,psci-mode = <0x4>;
+ qcom,entry-latency-us = <800>;
+ qcom,exit-latency-us = <2118>;
+ qcom,min-residency-us = <7376>;
+ qcom,min-child-idx = <1>;
+ qcom,is-reset;
+ };
+
+ qcom,pm-cpu {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+ qcom,disable-ipi-prediction;
+ qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ qcom,pm-cpu-level@0 { /* C1 */
+ reg = <0>;
+ label = "wfi";
+ qcom,psci-cpu-mode = <0x1>;
+ qcom,entry-latency-us = <49>;
+ qcom,exit-latency-us = <42>;
+ qcom,min-residency-us = <91>;
+ };
+
+ qcom,pm-cpu-level@1 { /* C3 */
+ reg = <1>;
+ label = "pc";
+ qcom,psci-cpu-mode = <0x3>;
+ qcom,entry-latency-us = <290>;
+ qcom,exit-latency-us = <376>;
+ qcom,min-residency-us = <1182>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+ };
+ };
+
+ qcom,pm-cluster@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "perf";
+ qcom,spm-device-names = "l2";
+ qcom,psci-mode-shift = <4>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cluster-level@0 { /* D1 */
+ reg = <0>;
+ label = "perf-l2-wfi";
+ qcom,psci-mode = <0x1>;
+ qcom,entry-latency-us = <38>;
+ qcom,exit-latency-us = <51>;
+ qcom,min-residency-us = <89>;
+ };
+
+ qcom,pm-cluster-level@1 { /* D3G*/
+ reg = <1>;
+ label = "perf-l2-gdhs";
+ qcom,psci-mode = <2>;
+ qcom,entry-latency-us = <314>;
+ qcom,exit-latency-us = <345>;
+ qcom,min-residency-us = <660>;
+ qcom,min-child-idx = <1>;
+ };
+
+ qcom,pm-cluster-level@2 { /* D3 */
+ reg = <2>;
+ label = "perf-l2-pc";
+ qcom,psci-mode = <0x4>;
+ qcom,entry-latency-us = <640>;
+ qcom,exit-latency-us = <1654>;
+ qcom,min-residency-us = <8094>;
+ qcom,min-child-idx = <1>;
+ qcom,is-reset;
+ };
+
+ qcom,pm-cpu {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+ qcom,disable-ipi-prediction;
+ qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>;
+
+ qcom,pm-cpu-level@0 { /* C1 */
+ reg = <0>;
+ label = "wfi";
+ qcom,psci-cpu-mode = <0x1>;
+ qcom,entry-latency-us = <29>;
+ qcom,exit-latency-us = <39>;
+ qcom,min-residency-us = <68>;
+ };
+
+ qcom,pm-cpu-level@1 { /* C3 */
+ reg = <1>;
+ label = "pc";
+ qcom,psci-cpu-mode = <0x3>;
+ qcom,entry-latency-us = <297>;
+ qcom,exit-latency-us = <324>;
+ qcom,min-residency-us = <1110>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+ };
+ };
+ };
+ };
+
+ qcom,rpm-stats@4600000 {
+ compatible = "qcom,rpm-stats";
+ reg = <0x04600000 0x1000>,
+ <0x04690014 0x4>;
+ reg-names = "phys_addr_base", "offset_addr";
+ qcom,sleep-stats-version = <2>;
+ };
+
+ qcom,rpm-master-stats@45f0150 {
+ compatible = "qcom,rpm-master-stats";
+ reg = <0x45f0150 0x5000>;
+ qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ";
+ qcom,master-stats-version = <2>;
+ qcom,master-offset = <4096>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-pmi632.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-pmi632.dtsi
new file mode 100755
index 0000000..caa724a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-pmi632.dtsi
@@ -0,0 +1,138 @@
+#include "pmi632.dtsi"
+
+&soc {
+ mtp_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "qg-batterydata-alium-3600mah.dtsi"
+ };
+};
+
+&pmi632_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&conn_therm_default &skin_therm_default>;
+
+ conn_therm {
+ reg = <ADC_GPIO1_PU2>;
+ label = "conn_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_therm {
+ reg = <ADC_GPIO2_PU2>;
+ label = "skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pmi632_gpios {
+ conn_therm {
+ conn_therm_default: conn_therm_default {
+ pins = "gpio1";
+ bias-high-impedance;
+ };
+ };
+
+ skin_therm {
+ skin_therm_default: skin_therm_default {
+ pins = "gpio3";
+ bias-high-impedance;
+ };
+ };
+};
+
+&pmi632_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ io-channels = <&pmi632_vadc ADC_GPIO2_PU2>;
+
+ /* Channel nodes */
+ skin_therm {
+ reg = <ADC_GPIO2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pmi632_gpios {
+ smb_en {
+ smb_en_default: smb_en_default {
+ pins = "gpio2";
+ function = "func1";
+ output-enable;
+ };
+ };
+
+ pmi632_sense {
+ /* GPIO 7 and 8 are external-sense pins for PMI632 */
+ pmi632_sense_default: pmi632_sense_default {
+ pins = "gpio7", "gpio8";
+ bias-high-impedance; /* disable the GPIO */
+ bias-disable; /* no-pull */
+ };
+ };
+
+ pmi632_ctm {
+ /* Disable GPIO1 for h/w base mitigation */
+ pmi632_ctm_default: pmi632_ctm_default {
+ pins = "gpio1";
+ bias-high-impedance; /* disable the GPIO */
+ bias-disable; /* no-pull */
+ };
+ };
+};
+
+&pmi632_gpios {
+ disp_pins {
+ disp_pins_default: disp_pins_default {
+ pins = "gpio6";
+ function = "func1";
+ qcom,drive-strength = <2>;
+ power-source = <0>;
+ bias-disable;
+ output-low;
+ };
+ };
+};
+
+&thermal_zones {
+ chg-skin-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pmi632_adc_tm ADC_GPIO2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ quiet-therm-step {
+ cooling-maps {
+ batt_cdev1 {
+ cooling-device = <&pmi632_charger 2 2>;
+ };
+
+ batt_cdev2 {
+ cooling-device = <&pmi632_charger 4 4>;
+ };
+
+ batt_cdev3 {
+ cooling-device = <&pmi632_charger 6 6>;
+ };
+
+ batt_cdev4 {
+ cooling-device = <&pmi632_charger 7 7>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-nopmi.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-nopmi.dtsi
new file mode 100755
index 0000000..413bac3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-nopmi.dtsi
@@ -0,0 +1,24 @@
+#include "bengal-qrd.dtsi"
+
+&led_flash_rear {
+ /delete-property/ flash-source;
+ /delete-property/ torch-source;
+ /delete-property/ switch-source;
+};
+
+&led_flash_rear_aux {
+ /delete-property/ flash-source;
+ /delete-property/ torch-source;
+ /delete-property/ switch-source;
+};
+
+&led_flash_rear_aux2 {
+ /delete-property/ flash-source;
+ /delete-property/ torch-source;
+ /delete-property/ switch-source;
+};
+
+&sde_dsi {
+ /delete-property/ lab-supply;
+ /delete-property/ ibb-supply;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-overlay.dts
new file mode 100755
index 0000000..3d020cf
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "bengal-qrd.dtsi"
+#include "bengal-qrd-pmi632.dtsi"
+#include "bengal-thermal-pmi632-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Bengal QRD";
+ compatible = "qcom,bengal-qrd", "qcom,bengal", "qcom,qrd";
+ qcom,board-id = <0x1000B 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-pmi632.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-pmi632.dtsi
new file mode 100755
index 0000000..706b1f9
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd-pmi632.dtsi
@@ -0,0 +1,94 @@
+#include "bengal-pmi632.dtsi"
+
+&soc {
+ qrd_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "qg-batterydata-atl466271_3300mAh.dtsi"
+ };
+};
+
+&pmi632_qg {
+ qcom,battery-data = <&qrd_batterydata>;
+ qcom,qg-iterm-ma = <100>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,qg-use-s7-ocv;
+};
+
+&pmi632_charger {
+ qcom,battery-data = <&qrd_batterydata>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,sw-jeita-enable;
+ qcom,step-charging-enable;
+ /* SMB1355 only */
+ qcom,sec-charger-config = <2>;
+ qcom,hvdcp2-max-icl-ua = <2000000>;
+ dpdm-supply = <&qusb_phy0>;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ qcom,auto-recharge-soc = <98>;
+ qcom,flash-disable-soc = <10>;
+ qcom,hw-die-temp-mitigation;
+ qcom,hw-connector-mitigation;
+ qcom,connector-internal-pull-kohm = <100>;
+ qcom,float-option = <1>;
+ qcom,thermal-mitigation = <4200000 3500000 3000000
+ 2500000 2000000 1500000 1000000 500000>;
+};
+
+&pmi632_gpios {
+ smb_en {
+ smb_en_default: smb_en_default {
+ pins = "gpio2";
+ function = "func1";
+ output-enable;
+ };
+ };
+
+ pmi632_sense {
+ /* GPIO 7 and 8 are external-sense pins for PMI632 */
+ pmi632_sense_default: pmi632_sense_default {
+ pins = "gpio7", "gpio8";
+ bias-high-impedance; /* disable the GPIO */
+ bias-disable; /* no-pull */
+ };
+ };
+
+ pmi632_ctm {
+ /* Disable GPIO1 for h/w base mitigation */
+ pmi632_ctm_default: pmi632_ctm_default {
+ pins = "gpio1";
+ bias-high-impedance; /* disable the GPIO */
+ bias-disable; /* no-pull */
+ };
+ };
+};
+
+&usb0 {
+ extcon = <&pmi632_charger>, <&eud>;
+};
+
+&smb1355 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_int_default>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <105 IRQ_TYPE_LEVEL_LOW>;
+ status = "ok";
+};
+
+&smb1355_charger {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_en_default &pmi632_sense_default &pmi632_ctm_default>;
+ qcom,parallel-mode = <1>;
+ qcom,disable-ctm;
+ qcom,hw-die-temp-mitigation;
+ status = "ok";
+};
+
+&dsi_td4330_truly_v2_video {
+ qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+ qcom,platform-bklight-en-gpio = <&pmi632_gpios 6 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd.dts
new file mode 100755
index 0000000..bb52608
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+#include "bengal.dtsi"
+#include "bengal-qrd.dtsi"
+#include "bengal-qrd-pmi632.dtsi"
+#include "bengal-thermal-pmi632-overlay.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Bengal QRD";
+ compatible = "qcom,bengal-qrd", "qcom,bengal", "qcom,qrd";
+ qcom,board-id = <0x1000B 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd.dtsi
new file mode 100755
index 0000000..2f45758
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-qrd.dtsi
@@ -0,0 +1,349 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/input.h>
+#include "bengal-thermal-overlay.dtsi"
+#include "bengal-audio-overlay.dtsi"
+#include "bengal-sde-display.dtsi"
+#include "camera/bengal-camera-sensor-qrd.dtsi"
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #include "smb1355.dtsi"
+};
+
+&pm6125_gpios {
+ key_vol_up {
+ key_vol_up_default: key_vol_up_default {
+ pins = "gpio5";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+ };
+};
+
+&qusb_phy0 {
+ qcom,qusb-phy-init-seq = <0xf8 0x80
+ 0xb3 0x84
+ 0x81 0x88
+ 0xc7 0x8c
+ 0x30 0x08
+ 0x79 0x0c
+ 0x21 0x10
+ 0x14 0x9c
+ 0x80 0x04
+ 0x9f 0x1c
+ 0x00 0x18>;
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ linux,can-disable;
+ debounce-interval = <15>;
+ gpio-key,wakeup;
+ };
+ };
+};
+
+&bengal_snd {
+ qcom,model = "bengal-qrd-snd-card";
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
+ qcom,wcn-btfm = <1>;
+ qcom,ext-disp-audio-rx = <0>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic4",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "SpkrMono WSA_IN", "AUX",
+ "TX SWR_MIC0", "ADC1_OUTPUT",
+ "TX SWR_MIC4", "ADC2_OUTPUT",
+ "TX SWR_MIC5", "ADC3_OUTPUT",
+ "TX SWR_MIC0", "VA_TX_SWR_CLK",
+ "TX SWR_MIC1", "VA_TX_SWR_CLK",
+ "TX SWR_MIC2", "VA_TX_SWR_CLK",
+ "TX SWR_MIC3", "VA_TX_SWR_CLK",
+ "TX SWR_MIC4", "VA_TX_SWR_CLK",
+ "TX SWR_MIC5", "VA_TX_SWR_CLK",
+ "TX SWR_MIC6", "VA_TX_SWR_CLK",
+ "TX SWR_MIC7", "VA_TX_SWR_CLK",
+ "TX SWR_MIC8", "VA_TX_SWR_CLK",
+ "TX SWR_MIC9", "VA_TX_SWR_CLK",
+ "TX SWR_MIC10", "VA_TX_SWR_CLK",
+ "TX SWR_MIC11", "VA_TX_SWR_CLK",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "TX_AIF1 CAP", "VA_TX_SWR_CLK",
+ "TX_AIF2 CAP", "VA_TX_SWR_CLK",
+ "TX_AIF3 CAP", "VA_TX_SWR_CLK",
+ "VA SWR_MIC0", "ADC1_OUTPUT",
+ "VA SWR_MIC4", "ADC2_OUTPUT",
+ "VA SWR_MIC5", "ADC3_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ asoc-codec = <&stub_codec>, <&bolero>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec";
+ qcom,wsa-max-devs = <1>;
+ qcom,wsa-devs = <&wsa881x_i2c_e>;
+ qcom,wsa-aux-dev-prefix = "SpkrMono";
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&wcd937x_codec>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&bolero>,
+ <&lpi_tlmm>;
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 70 0x00>;
+ qcom,nq-ven = <&tlmm 69 0x00>;
+ qcom,nq-firm = <&tlmm 31 0x00>;
+ qcom,nq-clkreq = <&tlmm 86 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <70 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&sdhc_1 {
+ vdd-supply = <&L24A>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L11A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&L22A>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L5A>;
+ qcom,vdd-io-voltage-level = <1800000 2960000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ vdd-io-bias-supply = <&L7A>;
+ qcom,vdd-io-bias-voltage-level = <1256000 1256000>;
+ qcom,vdd-io-bias-current-level = <0 6000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&tlmm {
+ smb_int_default: smb_int_default {
+ mux {
+ pins = "gpio105";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio105";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v3-660";
+
+ vdda-phy-supply = <&L4A>; /* 0.9v */
+ vdda-pll-supply = <&L12A>; /* 1.8v */
+ vdda-phy-max-microamp = <51400>;
+ vdda-pll-max-microamp = <14200>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&L24A>;
+ vcc-voltage-level = <2950000 2960000>;
+ vccq2-supply = <&L11A>;
+ vcc-max-microamp = <600000>;
+ vccq2-max-microamp = <600000>;
+ vccq2-pwr-collapse-sup;
+
+ qcom,vddp-ref-clk-supply = <&L18A>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vddp-ref-clk-min-uV = <1232000>;
+ qcom,vddp-ref-clk-max-uV = <1232000>;
+
+ status = "ok";
+};
+
+&pm6125_pwm {
+ status = "ok";
+};
+
+&dsi_td4330_truly_v2_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm6125_pwm 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm6125_pwm 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 81 0>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_td4330_truly_v2_video>;
+};
+
+&qupv3_se2_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="synaptics,tcm-i2c";
+
+ synaptics_tcm@20 {
+ compatible = "synaptics,tcm-i2c";
+ reg = <0x20>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+ synaptics,irq-gpio = <&tlmm 80 0x2008>;
+ synaptics,irq-on-state = <0>;
+ synaptics,reset-gpio = <&tlmm 71 0x00>;
+ synaptics,reset-on-state = <0>;
+ synaptics,reset-active-ms = <20>;
+ synaptics,reset-delay-ms = <200>;
+ synaptics,power-delay-ms = <200>;
+ synaptics,ubl-i2c-addr = <0x20>;
+ synaptics,extend_report;
+ synaptics,firmware-name = "synaptics_firmware_k.img";
+
+ panel = <&dsi_td4330_truly_v2_video &dsi_td4330_truly_v2_cmd>;
+ };
+};
+
+&thermal_zones {
+ quiet-therm-step {
+ status = "ok";
+ };
+};
+
+&tlmm {
+ fpc_reset_int: fpc_reset_int {
+ fpc_reset_low: reset_low {
+ mux {
+ pins = "gpio104";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio104";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ fpc_reset_high: reset_high {
+ mux {
+ pins = "gpio104";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio104";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ fpc_int_low: int_low {
+ mux {
+ pins = "gpio97";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio97";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+ };
+ };
+};
+
+&soc {
+ fingerprint: fpc1020 {
+ compatible = "fpc,fpc1020";
+ interrupt-parent = <&tlmm>;
+ interrupts = <97 0>;
+ fpc,gpio_rst = <&tlmm 104 0>;
+ fpc,gpio_irq = <&tlmm 97 0>;
+ fpc,enable-on-boot;
+ pinctrl-names = "fpc1020_reset_reset",
+ "fpc1020_reset_active",
+ "fpc1020_irq_active";
+ pinctrl-0 = <&fpc_reset_low>;
+ pinctrl-1 = <&fpc_reset_high>;
+ pinctrl-2 = <&fpc_int_low>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-qupv3.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-qupv3.dtsi
new file mode 100755
index 0000000..c050d4b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-qupv3.dtsi
@@ -0,0 +1,214 @@
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ /* QUPv3_0 wrapper instance */
+ qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {
+ compatible = "qcom,qupv3-geni-se";
+ reg = <0x4ac0000 0x2000>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-bus-ids =
+ <MSM_BUS_MASTER_QUP_CORE_0 MSM_BUS_SLAVE_QUP_CORE_0>,
+ <MSM_BUS_MASTER_QUP_0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,vote-for-bw;
+ iommus = <&apps_smmu 0xe3 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+ qcom,iommu-dma = "fastmap";
+ };
+
+ /* GPI Instance */
+ gpi_dma0: qcom,gpi-dma@4a00000 {
+ compatible = "qcom,gpi-dma";
+ #dma-cells = <5>;
+ reg = <0x4a00000 0x60000>;
+ reg-names = "gpi-top";
+ interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,max-num-gpii = <10>;
+ qcom,gpii-mask = <0xf>;
+ qcom,ev-factor = <2>;
+ iommus = <&apps_smmu 0xf6 0x0>;
+ qcom,gpi-ee-offset = <0x10000>;
+ qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+ status = "ok";
+ };
+
+ /* Debug UART Instance */
+ qupv3_se4_2uart: qcom,qup_uart@4a90000 {
+ compatible = "qcom,msm-geni-console";
+ reg = <0x4a90000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se4_2uart_active>;
+ pinctrl-1 = <&qupv3_se4_2uart_sleep>;
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ /* HS UART Instance */
+ qupv3_se3_4uart: qcom,qup_uart@4a8c000 {
+ compatible = "qcom,msm-geni-serial-hs";
+ reg = <0x4a8c000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "active", "sleep";
+ pinctrl-0 = <&qupv3_se3_default_ctsrtsrx>,
+ <&qupv3_se3_default_tx>;
+ pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,
+ <&qupv3_se3_tx>;
+ pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,
+ <&qupv3_se3_tx>;
+ interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 11 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,wrapper-core = <&qupv3_0>;
+ qcom,wakeup-byte = <0xFD>;
+ status = "disabled";
+ };
+
+ /* I2C Instance */
+ qupv3_se0_i2c: i2c@4a80000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x4a80000 0x4000>;
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 0 3 64 0>,
+ <&gpi_dma0 1 0 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se0_i2c_active>;
+ pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ /* I2C Instance */
+ qupv3_se1_i2c: i2c@4a84000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x4a84000 0x4000>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 1 3 64 0>,
+ <&gpi_dma0 1 1 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se1_i2c_active>;
+ pinctrl-1 = <&qupv3_se1_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ /* I2C Instance */
+ qupv3_se2_i2c: i2c@4a88000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x4a88000 0x4000>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 2 3 64 0>,
+ <&gpi_dma0 1 2 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se2_i2c_active>;
+ pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ /* SPI Instance */
+ qupv3_se0_spi: spi@4a80000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4a80000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se0_spi_active>;
+ pinctrl-1 = <&qupv3_se0_spi_sleep>;
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 0 1 64 0>,
+ <&gpi_dma0 1 0 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ /* SPI Instance */
+ qupv3_se1_spi: spi@4a84000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4a84000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se1_spi_active>;
+ pinctrl-1 = <&qupv3_se1_spi_sleep>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 1 1 64 0>,
+ <&gpi_dma0 1 1 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ /* SPI Instance */
+ qupv3_se5_spi: spi@4a94000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x4a94000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se5_spi_active>;
+ pinctrl-1 = <&qupv3_se5_spi_sleep>;
+ interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 5 1 64 0>,
+ <&gpi_dma0 1 5 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-regulator.dtsi
new file mode 100755
index 0000000..ba3ca19
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-regulator.dtsi
@@ -0,0 +1,394 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+
+&rpm_bus {
+ /* PM6125 S3/S4 - VDD_CX supply */
+ rpm-regulator-smpa3 {
+ status = "okay";
+ VDD_CX_LEVEL:
+ VDD_GFX_LEVEL:
+ VDD_MSS_LEVEL:
+ S3A_LEVEL: pm6125_s3_level: regulator-s3-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_s3_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ VDD_CX_FLOOR_LEVEL:
+ VDD_MSS_FLOOR_LEVEL:
+ S3A_FLOOR_LEVEL:
+ pm6125_s3_floor_level: regulator-s3-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_s3_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+
+ VDD_CX_LEVEL_AO:
+ VDD_MSS_LEVEL_AO:
+ S3A_LEVEL_AO: pm6125_s3_level_ao: regulator-s3-level-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_s3_level_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ cx_cdev: cx-cdev-lvl {
+ compatible = "qcom,regulator-cooling-device";
+ regulator-cdev-supply = <&VDD_CX_FLOOR_LEVEL>;
+ regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NOM
+ RPM_SMD_REGULATOR_LEVEL_NONE>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ /* PM6125 S5 - VDD_MX/WCSS_MX supply */
+ rpm-regulator-smpa5 {
+ status = "okay";
+ VDD_MX_LEVEL:
+ S5A_LEVEL: pm6125_s5_level: regulator-s5-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_s5_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ VDD_MX_FLOOR_LEVEL:
+ S5A_FLOOR_LEVEL:
+ pm6125_s5_floor_level: regulator-s5-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_s5_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+
+ VDD_MX_LEVEL_AO:
+ S5A_LEVEL_AO: pm6125_s5_level_ao: regulator-s5-level-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_s5_level_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ mx_cdev: mx-cdev-lvl {
+ compatible = "qcom,regulator-cooling-device";
+ regulator-cdev-supply = <&VDD_MX_LEVEL>;
+ regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NOM
+ RPM_SMD_REGULATOR_LEVEL_NONE>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ rpm-regulator-smpa6 {
+ status = "okay";
+ S6A: pm6125_s6: regulator-s6 {
+ regulator-min-microvolt = <304000>;
+ regulator-max-microvolt = <1456000>;
+ qcom,init-voltage = <304000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpa7 {
+ status = "okay";
+ S7A: pm6125_s7: regulator-s7 {
+ regulator-min-microvolt = <1280000>;
+ regulator-max-microvolt = <2080000>;
+ qcom,init-voltage = <1280000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpa8 {
+ status = "okay";
+ S8A: pm6125_s8: regulator-s8 {
+ regulator-min-microvolt = <1064000>;
+ regulator-max-microvolt = <1304000>;
+ qcom,init-voltage = <1064000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa1 {
+ status = "okay";
+ L1A: pm6125_l1: regulator-l1 {
+ regulator-min-microvolt = <952000>;
+ regulator-max-microvolt = <1152000>;
+ qcom,init-voltage = <952000>;
+ status = "okay";
+ };
+ };
+
+ /* VDD_LPI_MX supply */
+ rpm-regulator-ldoa2 {
+ status = "okay";
+ qcom,resource-name = "rwlm";
+ qcom,resource-id = <0>;
+ L2A_LEVEL: pm6125_l2_level: regulator-l2-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l2_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+ };
+
+ /* VDD_LPI_CX supply */
+ rpm-regulator-ldoa3 {
+ status = "okay";
+ qcom,resource-name = "rwlc";
+ qcom,resource-id = <0>;
+ L3A_LEVEL: pm6125_l3_level: regulator-l3-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l3_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ };
+
+ rpm-regulator-ldoa4 {
+ status = "okay";
+ L4A: pm6125_l4: regulator-l4 {
+ regulator-min-microvolt = <488000>;
+ regulator-max-microvolt = <1000000>;
+ qcom,init-voltage = <488000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa5 {
+ status = "okay";
+ L5A: pm6125_l5: regulator-l5 {
+ regulator-min-microvolt = <1648000>;
+ regulator-max-microvolt = <3056000>;
+ qcom,init-voltage = <1648000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa6 {
+ status = "okay";
+ L6A: pm6125_l6: regulator-l6 {
+ regulator-min-microvolt = <576000>;
+ regulator-max-microvolt = <656000>;
+ qcom,init-voltage = <576000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa7 {
+ status = "okay";
+ L7A: pm6125_l7: regulator-l7 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1304000>;
+ qcom,init-voltage = <1200000>;
+ status = "okay";
+ };
+ };
+
+ /* WCSS_CX */
+ rpm-regulator-ldoa8 {
+ status = "okay";
+ L8A: pm6125_l8: regulator-l8 {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <728000>;
+ qcom,init-voltage = <400000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa9 {
+ status = "okay";
+ L9A: pm6125_l9: regulator-l9 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa10 {
+ status = "okay";
+ L10A: pm6125_l10: regulator-l10 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1904000>;
+ qcom,init-voltage = <1704000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa11 {
+ status = "okay";
+ L11A: pm6125_l11: regulator-l11 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1952000>;
+ qcom,init-voltage = <1704000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa12 {
+ status = "okay";
+ L12A: pm6125_l12: regulator-l12 {
+ regulator-min-microvolt = <1624000>;
+ regulator-max-microvolt = <1984000>;
+ qcom,init-voltage = <1624000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa13 {
+ status = "okay";
+ L13A: pm6125_l13: regulator-l13 {
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <1952000>;
+ qcom,init-voltage = <1504000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa14 {
+ status = "okay";
+ L14A: pm6125_l14: regulator-l14 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1904000>;
+ qcom,init-voltage = <1704000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa15 {
+ status = "okay";
+ L15A: pm6125_l15: regulator-l15 {
+ regulator-min-microvolt = <2920000>;
+ regulator-max-microvolt = <3232000>;
+ qcom,init-voltage = <2920000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa16 {
+ status = "okay";
+ L16A: pm6125_l16: regulator-l16 {
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1904000>;
+ qcom,init-voltage = <1704000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa17 {
+ status = "okay";
+ L17A: pm6125_l17: regulator-l17 {
+ regulator-min-microvolt = <1152000>;
+ regulator-max-microvolt = <1384000>;
+ qcom,init-voltage = <1152000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa18 {
+ status = "okay";
+ L18A: pm6125_l18: regulator-l18 {
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1312000>;
+ qcom,init-voltage = <1104000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa19 {
+ status = "okay";
+ L19A: pm6125_l19: regulator-l19 {
+ regulator-min-microvolt = <1624000>;
+ regulator-max-microvolt = <3304000>;
+ qcom,init-voltage = <1624000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa20 {
+ status = "okay";
+ L20A: pm6125_l20: regulator-l20 {
+ regulator-min-microvolt = <1624000>;
+ regulator-max-microvolt = <3304000>;
+ qcom,init-voltage = <1624000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa21 {
+ status = "okay";
+ L21A: pm6125_l21: regulator-l21 {
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3600000>;
+ qcom,init-voltage = <2400000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa22 {
+ status = "okay";
+ L22A: pm6125_l22: regulator-l22 {
+ regulator-min-microvolt = <2952000>;
+ regulator-max-microvolt = <3304000>;
+ qcom,init-voltage = <2952000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa23 {
+ status = "okay";
+ L23A: pm6125_l23: regulator-l23 {
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3400000>;
+ qcom,init-voltage = <3200000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa24 {
+ status = "okay";
+ L24A: pm6125_l24: regulator-l24 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3600000>;
+ qcom,init-voltage = <2704000>;
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-rumi-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-rumi-overlay.dts
new file mode 100755
index 0000000..8440ce0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-rumi-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengal-pmi632.dtsi"
+#include "bengal-rumi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Bengal RUMI";
+ compatible = "qcom,bengal-rumi", "qcom,bengal", "qcom,rumi";
+ qcom,msm-id = <417 0x10000>;
+ qcom,board-id = <15 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-rumi.dts b/arch/arm64/boot/dts/vendor/qcom/bengal-rumi.dts
new file mode 100755
index 0000000..f2efdfa
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-rumi.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/memreserve/ 0x90000000 0x00000100;
+
+#include "bengal.dtsi"
+#include "bengal-pmi632.dtsi"
+#include "bengal-rumi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Bengal RUMI";
+ compatible = "qcom,bengal-rumi", "qcom,bengal", "qcom,rumi";
+ qcom,board-id = <15 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-rumi.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-rumi.dtsi
new file mode 100755
index 0000000..236d76f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-rumi.dtsi
@@ -0,0 +1,230 @@
+&soc {
+ usb_emu_phy: usb_emu_phy@4f20000 {
+ compatible = "qcom,usb-emu-phy";
+ reg = <0x04f20000 0x9500>,
+ <0x04ef8800 0x100>;
+ reg-names = "base", "qscratch_base";
+
+
+ qcom,emu-init-seq = <0xffff 0x4
+ 0xfff0 0x4
+ 0x100000 0x20
+ 0x0 0x20
+ 0x101f0 0x20
+ 0x100000 0x3c
+ 0x0 0x3c
+ 0x10060 0x3c
+ 0x0 0x4>;
+ };
+
+ timer {
+ clock-frequency = <500000>;
+ };
+
+ timer@f120000 {
+ clock-frequency = <500000>;
+ };
+
+ wdog: qcom,wdt@f017000 {
+ status = "disabled";
+ };
+
+ bi_tcxo: bi_tcxo {
+ compatible = "fixed-factor-clock";
+ clocks = <&xo_board>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ #clock-cells = <0>;
+ };
+
+ bi_tcxo_ao: bi_tcxo_ao {
+ compatible = "fixed-factor-clock";
+ clocks = <&xo_board>;
+ clock-mult = <1>;
+ clock-div = <1>;
+ #clock-cells = <0>;
+ };
+
+ qmi-tmd-devices {
+ status = "disabled";
+ };
+};
+
+&qupv3_se1_i2c {
+ status = "disabled";
+};
+
+&rpm_bus {
+ rpm-standalone;
+ /delete-node/ rpm-regulator-smpa3;
+ /delete-node/ rpm-regulator-smpa5;
+ /delete-node/ rpm-regulator-smpa6;
+ /delete-node/ rpm-regulator-smpa7;
+ /delete-node/ rpm-regulator-smpa8;
+ /delete-node/ rpm-regulator-ldoa1;
+ /delete-node/ rpm-regulator-ldoa2;
+ /delete-node/ rpm-regulator-ldoa3;
+ /delete-node/ rpm-regulator-ldoa4;
+ /delete-node/ rpm-regulator-ldoa5;
+ /delete-node/ rpm-regulator-ldoa6;
+ /delete-node/ rpm-regulator-ldoa7;
+ /delete-node/ rpm-regulator-ldoa8;
+ /delete-node/ rpm-regulator-ldoa9;
+ /delete-node/ rpm-regulator-ldoa10;
+ /delete-node/ rpm-regulator-ldoa11;
+ /delete-node/ rpm-regulator-ldoa12;
+ /delete-node/ rpm-regulator-ldoa13;
+ /delete-node/ rpm-regulator-ldoa14;
+ /delete-node/ rpm-regulator-ldoa15;
+ /delete-node/ rpm-regulator-ldoa16;
+ /delete-node/ rpm-regulator-ldoa17;
+ /delete-node/ rpm-regulator-ldoa18;
+ /delete-node/ rpm-regulator-ldoa19;
+ /delete-node/ rpm-regulator-ldoa20;
+ /delete-node/ rpm-regulator-ldoa21;
+ /delete-node/ rpm-regulator-ldoa22;
+ /delete-node/ rpm-regulator-ldoa23;
+ /delete-node/ rpm-regulator-ldoa24;
+};
+
+&tsens0 {
+ status = "disabled";
+};
+
+&bcl_sensor {
+ status = "disabled";
+};
+
+&bcl_soc {
+ status = "disabled";
+};
+
+&lmh_cpu_vdd {
+ status = "disabled";
+};
+
+&cxip_cdev {
+ status = "disabled";
+};
+
+&lmh_dcvs0 {
+ status = "disabled";
+};
+
+&lmh_dcvs1 {
+ status = "disabled";
+};
+
+&thermal_zones {
+ /delete-node/ mapss-lowf;
+ /delete-node/ camera-lowf;
+ /delete-node/ pmi632-ibat-lvl0;
+ /delete-node/ pmi632-ibat-lvl1;
+ /delete-node/ pmi632-vbat-lvl0;
+ /delete-node/ pmi632-vbat-lvl1;
+ /delete-node/ pmi632-vbat-lvl2;
+ /delete-node/ pmi632-bcl-lvl0;
+ /delete-node/ pmi632-bcl-lvl1;
+ /delete-node/ pmi632-bcl-lvl2;
+};
+
+ #include "bengal-stub-regulator.dtsi"
+
+&sdhc_1 {
+ vdd-supply = <&L24A>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L11A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000>;
+ qcom,bus-speed-mode = "DDR_1p8v";
+
+ /delete-property/qcom,devfreq,freq-table;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&L22A>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L5A>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50";
+
+ /delete-property/qcom,devfreq,freq-table;
+
+ status = "ok";
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qrbtc-sdm845";
+
+ vdda-phy-supply = <&L4A>; /* 0.9v */
+ vdda-pll-supply = <&L12A>; /* 1.8v */
+ vdda-phy-max-microamp = <51400>;
+ vdda-pll-max-microamp = <14200>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ limit-tx-hs-gear = <1>;
+ limit-rx-hs-gear = <1>;
+ scsi-cmd-timeout = <300000>;
+
+ vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&L24A>;
+ vccq2-supply = <&L11A>;
+ vcc-max-microamp = <600000>;
+ vccq2-max-microamp = <600000>;
+
+ qcom,vddp-ref-clk-supply = <&L18A>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vddp-ref-clk-min-uV = <1232000>;
+ qcom,vddp-ref-clk-max-uV = <1232000>;
+
+ qcom,disable-lpm;
+ status = "ok";
+};
+
+&usb0 {
+ dpdm-supply = <&usb_nop_phy>;
+ dwc3@4e00000 {
+ usb-phy = <&usb_emu_phy>, <&usb_nop_phy>;
+ maximum-speed = "high-speed";
+ dr_mode = "peripheral";
+ };
+};
+
+&rpmcc {
+ compatible = "qcom,dummycc";
+ clock-output-names = "rpmcc_clocks";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
+
+&debugcc {
+ compatible = "qcom,dummycc";
+ clock-output-names = "debugcc_clocks";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-sde-display.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-sde-display.dtsi
new file mode 100755
index 0000000..b6d7337
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-sde-display.dtsi
@@ -0,0 +1,276 @@
+#include "dsi-panel-td4330-truly-v2-singlemipi-fhd-cmd.dtsi"
+#include "dsi-panel-td4330-truly-v2-singlemipi-fhd-vid.dtsi"
+#include "dsi-panel-nt36525-truly-hd-plus-vid.dtsi"
+#include "dsi-panel-r66451-hd-plus-90hz-video.dtsi"
+#include "dsi-panel-r66451-hd-plus-90hz-cmd.dtsi"
+#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
+
+&soc {
+ dsi_panel_pwr_supply: dsi_panel_pwr_supply {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "lab";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@2 {
+ reg = <2>;
+ qcom,supply-name = "ibb";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+ };
+
+ dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+ };
+
+ dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "vdda-3p3";
+ qcom,supply-min-voltage = <3000000>;
+ qcom,supply-max-voltage = <3000000>;
+ qcom,supply-enable-load = <13200>;
+ qcom,supply-disable-load = <80>;
+ };
+ };
+
+ sde_dsi: qcom,dsi-display-primary {
+ compatible = "qcom,dsi-display";
+ label = "primary";
+ qcom,dsi-ctrl = <&mdss_dsi0>;
+ qcom,dsi-phy = <&mdss_dsi_phy0>;
+
+ clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>,
+ <&mdss_dsi0_pll PIX0_MUX_CLK>,
+ <&mdss_dsi0_pll BYTE0_SRC_CLK>,
+ <&mdss_dsi0_pll PIX0_SRC_CLK>,
+ <&mdss_dsi0_pll SHADOW_BYTE0_SRC_CLK>,
+ <&mdss_dsi0_pll SHADOW_PIX0_SRC_CLK>;
+ clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+ pinctrl-names = "panel_active", "panel_suspend";
+ pinctrl-0 = <&sde_dsi_active &sde_te_active>;
+ pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
+
+ qcom,platform-te-gpio = <&tlmm 81 0>;
+ qcom,panel-te-source = <0>;
+
+ vddio-supply = <&L9A>;
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+ qcom,mdp = <&mdss_mdp>;
+
+ qcom,dsi-default-panel =
+ <&dsi_td4330_truly_v2_video>;
+ };
+
+ sde_wb: qcom,wb-display@0 {
+ status = "disabled";
+ compatible = "qcom,wb-display";
+ cell-index = <0>;
+ label = "wb_display";
+ };
+
+ msm_notifier: qcom,msm_notifier@0 {
+ compatible = "qcom,msm-notifier";
+ panel = <&dsi_r66451_amoled_hd_90hz_video
+ &dsi_r66451_amoled_hd_90hz_cmd>;
+ };
+};
+
+&mdss_mdp {
+ connectors = <&sde_dsi>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+ qcom,mdss-dsi-t-clk-post = <0x0e>;
+ qcom,mdss-dsi-t-clk-pre = <0x36>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x1c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x1c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-dyn-clk-enable;
+ qcom,dsi-dyn-clk-list =
+ <944315056 928576464 932511112 936445760 940380400>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings =
+ [26 20 09 0B 06 02 04 a0
+ 26 20 09 0B 06 02 04 a0
+ 26 20 09 0B 06 02 04 a0
+ 26 20 09 0B 06 02 04 a0
+ 26 1F 09 0B 06 02 04 a0];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <40 40 40 40 40 40>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings =
+ [25 20 09 0A 06 03 04 a0
+ 25 20 09 0A 06 03 04 a0
+ 25 20 09 0A 06 03 04 a0
+ 25 20 09 0A 06 03 04 a0
+ 25 1F 09 0A 06 03 04 a0];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_td4330_truly_v2_video {
+ qcom,mdss-dsi-t-clk-post = <0x0e>;
+ qcom,mdss-dsi-t-clk-pre = <0x35>;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x1c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x1c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-supported-dfps-list = <60 55 48>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update =
+ "dfps_immediate_porch_mode_vfp";
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+ qcom,dsi-dyn-clk-enable;
+ qcom,dsi-dyn-clk-list =
+ <976190400 988392784 984325320 980257864>;
+ qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings =
+ [25 20 09 0A 06 03 04 a0
+ 25 20 09 0A 06 03 04 a0
+ 25 20 09 0A 06 03 04 a0
+ 25 20 09 0A 06 03 04 a0
+ 25 1F 09 0A 06 03 04 a0];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings =
+ [26 20 09 0B 06 02 04 a0
+ 26 20 09 0B 06 02 04 a0
+ 26 20 09 0B 06 02 04 a0
+ 26 20 09 0B 06 02 04 a0
+ 26 1F 09 0B 06 02 04 a0];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_nt36525_truly_video {
+ qcom,mdss-dsi-t-clk-post = <0x0a>;
+ qcom,mdss-dsi-t-clk-pre = <0x21>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings =
+ [1F 1B 05 06 03 02 04 a0
+ 1F 1B 05 06 03 02 04 a0
+ 1F 1B 05 06 03 02 04 a0
+ 1F 1B 05 06 03 02 04 a0
+ 1F 10 04 06 03 02 04 a0];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_r66451_amoled_hd_90hz_video {
+ qcom,mdss-dsi-t-clk-post = <0x0c>;
+ qcom,mdss-dsi-t-clk-pre = <0x2a>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings =
+ [22 1E 07 08 04 02 04 a0
+ 22 1E 07 08 04 02 04 a0
+ 22 1E 07 08 04 02 04 a0
+ 22 1E 07 08 04 02 04 a0
+ 22 17 06 07 04 02 04 a0];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_r66451_amoled_hd_90hz_cmd {
+ qcom,mdss-dsi-t-clk-post = <0x0c>;
+ qcom,mdss-dsi-t-clk-pre = <0x2a>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings =
+ [22 1E 07 08 04 02 04 a0
+ 22 1E 07 08 04 02 04 a0
+ 22 1E 07 08 04 02 04 a0
+ 22 1E 07 08 04 02 04 a0
+ 22 17 06 07 04 02 04 a0];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-sde-pll.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-sde-pll.dtsi
new file mode 100755
index 0000000..72e4bc6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-sde-pll.dtsi
@@ -0,0 +1,32 @@
+&soc {
+ mdss_dsi0_pll: qcom,mdss_dsi0_pll {
+ compatible = "qcom,mdss_dsi_pll_14nm";
+ label = "MDSS DSI 0 PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+ reg = <0x5e94400 0x588>,
+ <0x5f03000 0x8>,
+ <0x5e94200 0x100>;
+ reg-names = "pll_base", "gdsc_base",
+ "dynamic_pll_base";
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ memory-region = <&dfps_data_memory>;
+ gdsc-supply = <&mdss_core_gdsc>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-sde.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-sde.dtsi
new file mode 100755
index 0000000..e94c58e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-sde.dtsi
@@ -0,0 +1,417 @@
+#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
+
+&soc {
+ mdss_mdp: qcom,mdss_mdp {
+ compatible = "qcom,sde-kms";
+ reg = <0x5e00000 0x8f030>,
+ <0x5eb0000 0x2008>,
+ <0x5e8f000 0x02c>,
+ <0xc125ba4 0x20>;
+
+ reg-names = "mdp_phys",
+ "vbif_phys",
+ "sid_phys",
+ "sde_imem_phys";
+
+ clocks =
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_THROTTLE_CORE_CLK>,
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>;
+ clock-names = "gcc_iface", "gcc_bus", "throttle_clk",
+ "div_clk",
+ "iface_clk", "core_clk", "vsync_clk",
+ "lut_clk", "rot_clk";
+ clock-rate = <0 0 0 0 0 256000000 19200000 192000000 192000000>;
+ clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000
+ 307000000>;
+
+ sde-vdd-supply = <&mdss_core_gdsc>;
+
+ /* interrupt config */
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #power-domain-cells = <0>;
+
+ /* hw blocks */
+ qcom,sde-off = <0x1000>;
+ qcom,sde-len = <0x494>;
+
+ qcom,sde-ctl-off = <0x2000>;
+ qcom,sde-ctl-size = <0x1dc>;
+ qcom,sde-ctl-display-pref = "primary";
+
+ qcom,sde-mixer-off = <0x45000>;
+ qcom,sde-mixer-size = <0x320>;
+ qcom,sde-mixer-display-pref = "primary";
+
+ qcom,sde-dspp-top-off = <0x1300>;
+ qcom,sde-dspp-top-size = <0x80>;
+ qcom,sde-dspp-off = <0x55000>;
+ qcom,sde-dspp-size = <0xfe4>;
+
+ qcom,sde-intf-off = <0x0 0x6b800>;
+ qcom,sde-intf-size = <0x2b8>;
+ qcom,sde-intf-type = "none", "dsi";
+
+ qcom,sde-pp-off = <0x71000>;
+ qcom,sde-pp-size = <0xd4>;
+
+ qcom,sde-dither-off = <0x30e0>;
+ qcom,sde-dither-version = <0x00010000>;
+ qcom,sde-dither-size = <0x20>;
+
+ qcom,sde-sspp-type = "vig", "dma";
+
+ qcom,sde-sspp-off = <0x5000 0x25000>;
+ qcom,sde-sspp-src-size = <0x1f8>;
+
+ qcom,sde-sspp-xin-id = <0 1>;
+ qcom,sde-sspp-excl-rect = <1 1>;
+ qcom,sde-sspp-smart-dma-priority = <2 1>;
+ qcom,sde-smart-dma-rev = "smart_dma_v2p5";
+
+ qcom,sde-mixer-pair-mask = <0>;
+
+ qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
+ 0xb0 0xc8 0xe0 0xf8 0x110>;
+
+ qcom,sde-mixer-stage-base-layer;
+
+ qcom,sde-max-per-pipe-bw-kbps = <2600000 2600000>;
+
+ qcom,sde-max-per-pipe-bw-high-kbps = <2600000 2600000>;
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+ qcom,sde-sspp-clk-ctrl =
+ <0x2ac 0>, <0x2ac 8>;
+ qcom,sde-sspp-csc-off = <0x1a00>;
+ qcom,sde-csc-type = "csc-10bit";
+ qcom,sde-qseed-type = "qseedv3lite";
+ qcom,sde-sspp-qseed-off = <0xa00>;
+ qcom,sde-mixer-linewidth = <2048>;
+ qcom,sde-sspp-linewidth = <2160>;
+ qcom,sde-mixer-blendstages = <0x4>;
+ qcom,sde-highest-bank-bit = <0x1>;
+ qcom,sde-ubwc-version = <0x100>;
+ qcom,sde-ubwc-swizzle = <0x7>;
+ qcom,sde-ubwc-static = <0x11F>;
+ qcom,sde-panic-per-pipe;
+ qcom,sde-has-cdp;
+
+ qcom,sde-has-dim-layer;
+ qcom,sde-has-idle-pc;
+
+ qcom,sde-max-bw-low-kbps = <3100000>;
+ qcom,sde-max-bw-high-kbps = <4000000>;
+ qcom,sde-min-core-ib-kbps = <2400000>;
+ qcom,sde-min-llcc-ib-kbps = <800000>;
+ qcom,sde-min-dram-ib-kbps = <800000>;
+ qcom,sde-dram-channels = <1>;
+ qcom,sde-num-nrt-paths = <0>;
+
+ qcom,sde-vbif-off = <0>;
+ qcom,sde-vbif-size = <0x2008>;
+ qcom,sde-vbif-id = <0>;
+ qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
+
+ qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
+ qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
+
+ /*Pending macrotile & macrotile-qseed has the same configs */
+
+ qcom,sde-danger-lut = <0x000000ff 0x0000ffff
+ 0x00000000 0x00000000 0x0000ffff>;
+
+ qcom,sde-safe-lut-linear = <0 0xfff0>;
+ qcom,sde-safe-lut-macrotile = <0 0xff00>;
+ /* same as safe-lut-macrotile */
+ qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>;
+ qcom,sde-safe-lut-nrt = <0 0xffff>;
+
+ qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;
+ qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;
+ qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;
+ qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;
+
+ qcom,sde-cdp-setting = <1 1>, <1 0>;
+
+ qcom,sde-qos-cpu-mask = <0x3>;
+ qcom,sde-qos-cpu-dma-latency = <300>;
+
+ qcom,sde-secure-sid-mask = <0x0000421>;
+ qcom,sde-num-mnoc-ports = <1>;
+ qcom,sde-axi-bus-width = <16>;
+
+ qcom,sde-sspp-vig-blocks {
+ qcom,sde-vig-csc-off = <0x1a00>;
+ qcom,sde-vig-qseed-off = <0xa00>;
+ qcom,sde-vig-qseed-size = <0xa0>;
+ qcom,sde-vig-inverse-pma;
+ };
+
+ qcom,sde-dspp-blocks {
+ qcom,sde-dspp-igc = <0x0 0x00030001>;
+ qcom,sde-dspp-hsic = <0x800 0x00010007>;
+ qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+ qcom,sde-dspp-hist = <0x800 0x00010007>;
+ qcom,sde-dspp-sixzone= <0x900 0x00010007>;
+ qcom,sde-dspp-vlut = <0xa00 0x00010008>;
+ qcom,sde-dspp-pcc = <0x1700 0x00040000>;
+ qcom,sde-dspp-gc = <0x17c0 0x00010008>;
+ qcom,sde-dspp-dither = <0x82c 0x00010007>;
+ };
+
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "sde-vdd";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
+ compatible = "qcom,smmu_sde_unsec";
+ iommus = <&apps_smmu 0x420 0x2>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-earlymap; /* for cont-splash */
+ };
+
+ smmu_sde_sec: qcom,smmu_sde_sec_cb {
+ compatible = "qcom,smmu_sde_sec";
+ iommus = <&apps_smmu 0x421 0x0>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xa>;
+ };
+
+ /* data and reg bus scale settings */
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "mdss_sde";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>,
+ <22 512 0 4800000>,
+ <22 512 0 4800000>;
+ };
+
+ qcom,sde-reg-bus {
+ qcom,msm-bus,name = "mdss_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 150000>,
+ <1 590 0 300000>;
+ };
+
+ qcom,sde-limits {
+ qcom,sde-linewidth-limits {
+ qcom,sde-limit-name = "sspp_linewidth_usecases";
+ qcom,sde-limit-cases = "vig", "dma", "scale";
+ qcom,sde-limit-ids= <0x1 0x2 0x4>;
+ qcom,sde-limit-values = <0x1 4096>,
+ <0x5 2560>,
+ <0x2 2160>;
+ };
+
+ qcom,sde-bw-limits {
+ qcom,sde-limit-name = "sde_bwlimit_usecases";
+ qcom,sde-limit-cases = "per_vig_pipe",
+ "per_dma_pipe",
+ "total_max_bw",
+ "camera_concurrency";
+ qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>;
+ qcom,sde-limit-values = <0x1 2600000>,
+ <0x9 2600000>,
+ <0x2 2600000>,
+ <0xa 2600000>,
+ <0x4 4000000>,
+ <0xc 3100000>;
+ };
+ };
+ };
+
+ mdss_rotator: qcom,mdss_rotator {
+ compatible = "qcom,sde_rotator";
+ reg = <0x5e00000 0xac000>,
+ <0x5eb0000 0x2008>;
+ reg-names = "mdp_phys",
+ "rot_vbif_phys";
+
+ #list-cells = <1>;
+
+ qcom,mdss-rot-mode = <1>;
+
+ /* Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_rotator";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>,
+ <22 512 0 6400000>,
+ <22 512 0 6400000>;
+
+ rot-vdd-supply = <&mdss_core_gdsc>;
+ qcom,supply-names = "rot-vdd";
+
+ clocks =
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>;
+ clock-names = "gcc_iface",
+ "iface_clk", "rot_clk";
+
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <2 0>;
+
+ power-domains = <&mdss_mdp>;
+ /*Offline rotator RT setting */
+ qcom,mdss-rot-parent = <&mdss_mdp 0>;
+ qcom,mdss-rot-xin-id = <10 11>;
+
+ /* Offline rotator QoS setting */
+ qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
+ qcom,mdss-rot-cdp-setting = <1 1>;
+ qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
+ qcom,mdss-rot-danger-lut = <0x0 0x0>;
+ qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
+
+ qcom,mdss-default-ot-rd-limit = <32>;
+ qcom,mdss-default-ot-wr-limit = <32>;
+
+ qcom,mdss-sbuf-headroom = <20>;
+
+ /* reg bus scale settings */
+ rot_reg: qcom,rot-reg-bus {
+ qcom,msm-bus,name = "mdss_rot_reg";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>;
+ };
+
+ smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
+ compatible = "qcom,smmu_sde_rot_unsec";
+ iommus = <&apps_smmu 0x43C 0x0>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ };
+
+ smmu_rot_sec: qcom,smmu_rot_sec_cb {
+ compatible = "qcom,smmu_sde_rot_sec";
+ iommus = <&apps_smmu 0x43D 0x0>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xa>;
+ };
+ };
+
+ mdss_dsi0: qcom,mdss_dsi0_ctrl {
+ compatible = "qcom,dsi-ctrl-hw-v2.4";
+ label = "dsi-ctrl-0";
+ cell-index = <0>;
+ frame-threshold-time-us = <1000>;
+ reg = <0x5e94000 0x400>,
+ <0x5f08000 0x4>;
+ reg-names = "dsi_ctrl", "disp_cc_base";
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <4 0>;
+ vdda-1p2-supply = <&L18A>;
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>;
+ clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+ "pixel_clk", "pixel_clk_rcg",
+ "esc_clk";
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1232000>;
+ qcom,supply-max-voltage = <1232000>;
+ qcom,supply-enable-load = <21800>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi_phy0: qcom,mdss_dsi_phy0 {
+ compatible = "qcom,dsi-phy-v2.0";
+ label = "dsi-phy-0";
+ cell-index = <0>;
+ reg = <0x5e94400 0x588>,
+ <0x5e01400 0x100>,
+ <0x5e94200 0x100>;
+ reg-names = "dsi_phy", "phy_clamp_base",
+ "dyn_refresh_base";
+ vdda-0p9-supply = <&VDD_MX_LEVEL>;
+ qcom,platform-strength-ctrl = [ff 06
+ ff 06
+ ff 06
+ ff 06
+ ff 00];
+ qcom,platform-lane-config = [00 00 10 0f
+ 00 00 10 0f
+ 00 00 10 0f
+ 00 00 10 0f
+ 00 00 10 8f];
+ qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+ qcom,panel-allow-phy-poweroff;
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage =
+ <RPM_SMD_REGULATOR_LEVEL_NOM>;
+ qcom,supply-max-voltage =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR>;
+ qcom,supply-off-min-voltage =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-stub-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-stub-regulator.dtsi
new file mode 100755
index 0000000..f0698e7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-stub-regulator.dtsi
@@ -0,0 +1,263 @@
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+
+&soc {
+ S1A: pm6125_s1: regulator-pm6125-s1 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_s1";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <465000>;
+ regulator-max-microvolt = <1155000>;
+ };
+
+ VDD_CX_LEVEL:
+ S3A_LEVEL: pm6125_s3_level: regulator-pm6125-s3-level {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_s3_level";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ VDD_CX_LEVEL_AO:
+ S3A_LEVEL_AO: pm6125_s3_level_ao: regulator-pm6125-s3-level-ao {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_s3_level_ao";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ VDD_MX_LEVEL:
+ S5A_LEVEL: pm6125_s5_level: regulator-pm6125-s5-level {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_s5_level";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ VDD_MX_LEVEL_AO:
+ S5A_LEVEL_AO: pm6125_s5_level_ao: regulator-pm6125-s5-level-ao {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_s5_level_ao";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ S6A: pm6125_s6: regulator-pm6125-s6 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_s6";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1450000>;
+ };
+
+ S7A: pm6125_s7: regulator-pm6125-s7 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_s7";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1270000>;
+ regulator-max-microvolt = <3369999>;
+ };
+
+ S8A: pm6125_s8: regulator-pm6125-s8 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_s8";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1060000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ L1A: pm6125_l1: regulator-pm6125-l1 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l1";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ L2A_LEVEL: pm6125_l2_level: regulator-pm6125-l2-level {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l2_level";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ L3A_LEVEL: pm6125_l3_level: regulator-pm6125-l3-level {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l3_level";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ L4A: pm6125_l4: regulator-pm6125-l4 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l4";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <488000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ L5A: pm6125_l5: regulator-pm6125-l5 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l5";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3050000>;
+ };
+
+ L6A: pm6125_l6: regulator-pm6125-l6 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l6";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <570000>;
+ regulator-max-microvolt = <650000>;
+ };
+
+ L7A: pm6125_l7: regulator-pm6125-l7 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l7";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ L8A: pm6125_l8: regulator-pm6125-l8 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l8";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <728000>;
+ };
+
+ L9A: pm6125_l9: regulator-pm6125-l9 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l9";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ L10A: pm6125_l10: regulator-pm6125-l10 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l10";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ };
+
+ L11A: pm6125_l11: regulator-pm6125-l11 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l11";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1950000>;
+ };
+
+ L12A: pm6125_l12: regulator-pm6125-l12 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l12";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ };
+
+ L13A: pm6125_l13: regulator-pm6125-l13 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l13";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3100000>;
+ };
+
+ L14A: pm6125_l14: regulator-pm6125-l14 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l14";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ };
+
+ L15A: pm6125_l15: regulator-pm6125-l15 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l15";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <2300000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ L16A: pm6125_l16: regulator-pm6125-l16 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l16";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ };
+
+ L17A: pm6125_l17: regulator-pm6125-l17 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l17";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1380000>;
+ };
+
+ L18A: pm6125_l18: regulator-pm6125-l18 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l18";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1312500>;
+ };
+
+ L19A: pm6125_l19: regulator-pm6125-l19 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l19";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ L20A: pm6125_l20: regulator-pm6125-l20 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l20";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ L21A: pm6125_l21: regulator-pm6125-l21 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l21";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ L22A: pm6125_l22: regulator-pm6125-l22 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l22";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ L23A: pm6125_l23: regulator-pm6125-l23 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l23";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ L24A: pm6125_l24: regulator-pm6125-l24 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6125_l24";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3600000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-thermal-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-thermal-overlay.dtsi
new file mode 100755
index 0000000..cea18dc
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-thermal-overlay.dtsi
@@ -0,0 +1,60 @@
+#include <dt-bindings/thermal/thermal.h>
+
+&thermal_zones {
+ pm6125-tz {
+ cooling-maps {
+ trip0_cpu0 {
+ trip = <&pm6125_trip0>;
+ cooling-device =
+ <&CPU0 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ trip0_cpu4 {
+ trip = <&pm6125_trip0>;
+ cooling-device =
+ <&CPU4 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ trip1_cpu1 {
+ trip = <&pm6125_trip1>;
+ cooling-device = <&cpu1_isolate 1 1>;
+ };
+
+ trip1_cpu2 {
+ trip = <&pm6125_trip1>;
+ cooling-device = <&cpu2_isolate 1 1>;
+ };
+
+ trip1_cpu3 {
+ trip = <&pm6125_trip1>;
+ cooling-device = <&cpu3_isolate 1 1>;
+ };
+
+ trip1_cpu4 {
+ trip = <&pm6125_trip1>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+
+ trip1_cpu5 {
+ trip = <&pm6125_trip1>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+
+ trip1_cpu6 {
+ trip = <&pm6125_trip1>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ trip1_cpu7 {
+ trip = <&pm6125_trip1>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+};
+
+&mdss_mdp {
+ #cooling-cells = <2>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-thermal-pmi632-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-thermal-pmi632-overlay.dtsi
new file mode 100755
index 0000000..6771046
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-thermal-pmi632-overlay.dtsi
@@ -0,0 +1,109 @@
+#include <dt-bindings/thermal/thermal.h>
+
+&thermal_zones {
+ pmi632-tz {
+ cooling-maps {
+ trip0_bat {
+ trip = <&pmi632_trip0>;
+ cooling-device =
+ <&pmi632_charger (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ trip1_bat {
+ trip = <&pmi632_trip1>;
+ cooling-device =
+ <&pmi632_charger THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+
+ pmi632-bcl-lvl0 {
+ cooling-maps {
+ cpu0_cdev {
+ trip = <&bcl_lvl0>;
+ cooling-device =
+ <&CPU0 (THERMAL_MAX_LIMIT-5)
+ (THERMAL_MAX_LIMIT-5)>;
+ };
+
+ cpu4_cdev {
+ trip = <&bcl_lvl0>;
+ cooling-device =
+ <&CPU4 (THERMAL_MAX_LIMIT-5)
+ (THERMAL_MAX_LIMIT-5)>;
+ };
+ };
+ };
+
+ pmi632-bcl-lvl1 {
+ cooling-maps {
+ cpu0_cdev {
+ trip = <&bcl_lvl1>;
+ cooling-device =
+ <&CPU0 (THERMAL_MAX_LIMIT-4)
+ (THERMAL_MAX_LIMIT-4)>;
+ };
+
+ cpu4_cdev {
+ trip = <&bcl_lvl1>;
+ cooling-device =
+ <&CPU4 (THERMAL_MAX_LIMIT-4)
+ (THERMAL_MAX_LIMIT-4)>;
+ };
+
+ cpu6_cdev {
+ trip = <&bcl_lvl1>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ cpu7_cdev {
+ trip = <&bcl_lvl1>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pmi632-bcl-lvl2 {
+ cooling-maps {
+ cpu4_cdev {
+ trip = <&bcl_lvl2>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+
+ cpu5_cdev {
+ trip = <&bcl_lvl2>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+ };
+ };
+
+ soc {
+ cooling-maps {
+ soc_cpu0 {
+ trip = <&pmi632_low_soc>;
+ cooling-device =
+ <&CPU0 (THERMAL_MAX_LIMIT-4)
+ (THERMAL_MAX_LIMIT-4)>;
+ };
+
+ soc_cpu4 {
+ trip = <&pmi632_low_soc>;
+ cooling-device =
+ <&CPU4 (THERMAL_MAX_LIMIT-4)
+ (THERMAL_MAX_LIMIT-4)>;
+ };
+
+ soc_cpu6 {
+ trip = <&pmi632_low_soc>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ soc_cpu7 {
+ trip = <&pmi632_low_soc>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-thermal.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-thermal.dtsi
new file mode 100755
index 0000000..0cc49b1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-thermal.dtsi
@@ -0,0 +1,1235 @@
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/thermal/qmi_thermal.h>
+
+&cpufreq_hw {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ lmh_dcvs0: qcom,limits-dcvs@f521000 {
+ compatible = "qcom,msm-hw-limits";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,affinity = <0>;
+ reg = <0xf550800 0x1000>,
+ <0xf521000 0x1000>;
+ qcom,no-cooling-device-register;
+ #thermal-sensor-cells = <0>;
+ };
+
+ lmh_dcvs1: qcom,limits-dcvs@f523000 {
+ compatible = "qcom,msm-hw-limits";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,affinity = <1>;
+ reg = <0xf550800 0x1000>,
+ <0xf523000 0x1000>;
+ qcom,no-cooling-device-register;
+ #thermal-sensor-cells = <0>;
+ };
+
+ qcom,cpu-isolation {
+ compatible = "qcom,cpu-isolate";
+ cpu0_isolate: cpu0-isolate {
+ qcom,cpu = <&CPU0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1_isolate: cpu1-isolate {
+ qcom,cpu = <&CPU1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2_isolate: cpu2-isolate {
+ qcom,cpu = <&CPU2>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3_isolate: cpu3-isolate {
+ qcom,cpu = <&CPU3>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4_isolate: cpu4-isolate {
+ qcom,cpu = <&CPU4>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5_isolate: cpu5-isolate {
+ qcom,cpu = <&CPU5>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6_isolate: cpu6-isolate {
+ qcom,cpu = <&CPU6>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7_isolate: cpu7-isolate {
+ qcom,cpu = <&CPU7>;
+ #cooling-cells = <2>;
+ };
+ };
+};
+
+&soc {
+ qmi-tmd-devices {
+ compatible = "qcom,qmi-cooling-devices";
+
+ modem {
+ qcom,instance-id = <QMI_MODEM_INST_ID>;
+
+ modem_pa: modem_pa {
+ qcom,qmi-dev-name = "pa";
+ #cooling-cells = <2>;
+ };
+
+ modem_proc: modem_proc {
+ qcom,qmi-dev-name = "modem";
+ #cooling-cells = <2>;
+ };
+
+ modem_current: modem_current {
+ qcom,qmi-dev-name = "modem_current";
+ #cooling-cells = <2>;
+ };
+
+ modem_skin: modem_skin {
+ qcom,qmi-dev-name = "modem_skin";
+ #cooling-cells = <2>;
+ };
+
+ modem_vdd: modem_vdd {
+ qcom,qmi-dev-name = "cpuv_restriction_cold";
+ #cooling-cells = <2>;
+ };
+
+ modem_wlan: modem_wlan {
+ qcom,qmi-dev-name = "wlan";
+ #cooling-cells = <2>;
+ };
+ };
+
+ cdsp {
+ qcom,instance-id = <QMI_CDSP_INST_ID>;
+
+ cdsp_sw: cdsp {
+ qcom,qmi-dev-name = "cdsp_sw";
+ #cooling-cells = <2>;
+ };
+
+ cdsp_hw: hvx {
+ qcom,qmi-dev-name = "cdsp_hw";
+ #cooling-cells = <2>;
+ };
+ };
+
+ adsp {
+ qcom,instance-id = <QMI_ADSP_INST_ID>;
+
+ adsp_vdd: adsp_vdd {
+ qcom,qmi-dev-name = "cpuv_restriction_cold";
+ #cooling-cells = <2>;
+ };
+ };
+ };
+
+ lmh_cpu_vdd: qcom,lmh-cpu-vdd@f550800 {
+ compatible = "qcom,lmh-cpu-vdd";
+ reg = <0xf550800 0x1000>;
+ #cooling-cells = <2>;
+ };
+
+ cxip_cdev: cxip-cdev@3ed000 {
+ compatible = "qcom,cxip-lm-cooling-device";
+ reg = <0x3ed000 0xc00c>;
+ qcom,thermal-client-offset = <0x8000>;
+ /* 4th and 5th offsets to bypass VICTIM1 */
+ qcom,bypass-client-list = <0x1004 0x4004 0x6004 0xc004 0xc008>;
+ #cooling-cells = <2>;
+ };
+};
+
+&thermal_zones {
+ mapss-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 0>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cdsp-hvx-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 1>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ wlan-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 3>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ video-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 4>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 5>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 6>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 7>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 8>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 9>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 10>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 11>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 12>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 13>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ display-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 14>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpu-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 15>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm6125_adc_tm ADC_XO_THERM_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ active-config1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa-therm0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm6125_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ quiet-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm6125_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm6125_adc_tm_iio ADC_GPIO1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ emmc-ufs-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm6125_adc_tm_iio ADC_GPIO2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpu-step {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 15>;
+ wake-capable-sensor;
+ trips {
+ gpu_step_trip: gpu-trip {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ gpu_cx_mon: gpu-cx-mon {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ gpu_cdev {
+ trip = <&gpu_step_trip>;
+ cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+
+ gpu-cx-cdev0 {
+ trip = <&gpu_cx_mon>;
+ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ gpu-cx-cdev1 {
+ trip = <&gpu_cx_mon>;
+ cooling-device = <&modem_proc 3 3>;
+ };
+
+ gpu-cx-cdev2 {
+ trip = <&gpu_cx_mon>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ gpu-cx-cdev3 {
+ trip = <&gpu_cx_mon>;
+ cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+
+ hepta-cpu-max-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+
+ trips {
+ silver-trip {
+ temperature = <120000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 10>;
+ wake-capable-sensor;
+
+ trips {
+ cpu4_5_config: cpu-4-5-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu4_cdev {
+ trip = <&cpu4_5_config>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+
+ cpu5_cdev {
+ trip = <&cpu4_5_config>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+ };
+ };
+
+ cpuss-1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 11>;
+ wake-capable-sensor;
+
+ trips {
+ cpu6_7_config: cpu-6-7-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu6_cdev {
+ trip = <&cpu6_7_config>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ cpu7_cdev {
+ trip = <&cpu6_7_config>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ cpuss-2-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 12>;
+ wake-capable-sensor;
+
+ trips {
+ silv_cpus_config: silv-cpus-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_cdev {
+ trip = <&silv_cpus_config>;
+ cooling-device = <&cpu0_isolate 1 1>;
+ };
+
+ cpu1_cdev {
+ trip = <&silv_cpus_config>;
+ cooling-device = <&cpu1_isolate 1 1>;
+ };
+
+ cpu2_cdev {
+ trip = <&silv_cpus_config>;
+ cooling-device = <&cpu2_isolate 1 1>;
+ };
+
+ cpu3_cdev {
+ trip = <&silv_cpus_config>;
+ cooling-device = <&cpu3_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 6>;
+ wake-capable-sensor;
+
+ trips {
+ cpu4_config: cpu4-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu4_cdev {
+ trip = <&cpu4_config>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 7>;
+ wake-capable-sensor;
+
+ trips {
+ cpu5_config: cpu5-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu5_cdev {
+ trip = <&cpu5_config>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-2-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 8>;
+ wake-capable-sensor;
+
+ trips {
+ cpu6_config: cpu6-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu6_cdev {
+ trip = <&cpu6_config>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-3-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 9>;
+ wake-capable-sensor;
+
+ trips {
+ cpu7_config: cpu7-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu7_cdev {
+ trip = <&cpu7_config>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ cdsp-hvx-step {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 1>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+
+ trips {
+ cdsp_trip0: cdsp-trip0 {
+ temperature = <95000>;
+ hysteresis = <20000>;
+ type = "passive";
+ };
+
+ cdsp_trip1: cdsp-trip1 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ cdsp_cx_mon: cdsp-cx-mon {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cxip-cdev {
+ trip = <&cdsp_trip0>;
+ cooling-device = <&cxip_cdev 1 1>;
+ };
+
+ cdsp-cdev0 {
+ trip = <&cdsp_trip1>;
+ cooling-device = <&cdsp_sw THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+
+ cdsp-cx-cdev0 {
+ trip = <&cdsp_cx_mon>;
+ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ cdsp-cx-cdev1 {
+ trip = <&cdsp_cx_mon>;
+ cooling-device = <&modem_proc 3 3>;
+ };
+
+ cdsp-cx-cdev2 {
+ trip = <&cdsp_cx_mon>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ cdsp-cx-cdev3 {
+ trip = <&cdsp_cx_mon>;
+ cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+
+ mdm-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 13>;
+ wake-capable-sensor;
+ trips {
+ mdm0_cx_mon: mdm0-cx-mon {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ mdm0-cx-cdev0 {
+ trip = <&mdm0_cx_mon>;
+ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ mdm0-cx-cdev1 {
+ trip = <&mdm0_cx_mon>;
+ cooling-device = <&modem_proc 3 3>;
+ };
+
+ mdm0-cx-cdev2 {
+ trip = <&mdm0_cx_mon>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ mdm0-cx-cdev3 {
+ trip = <&mdm0_cx_mon>;
+ cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+
+ mdm-1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 5>;
+ wake-capable-sensor;
+ trips {
+ mdm1_cx_mon: mdm1-cx-mon {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ mdm1-cx-cdev0 {
+ trip = <&mdm1_cx_mon>;
+ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ mdm1-cx-cdev1 {
+ trip = <&mdm1_cx_mon>;
+ cooling-device = <&modem_proc 3 3>;
+ };
+
+ mdm1-cx-cdev2 {
+ trip = <&mdm1_cx_mon>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ mdm1-cx-cdev3 {
+ trip = <&mdm1_cx_mon>;
+ cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+
+ mapss-lowc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&tsens0 0>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ mapss_cap_trip: mapss-cap-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ lmh_cpu_cdev {
+ trip = <&mapss_cap_trip>;
+ cooling-device = <&lmh_cpu_vdd 1 1>;
+ };
+ };
+ };
+
+ mapss-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 0>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ mapss_trip: mapss-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cx_vdd_cdev {
+ trip = <&mapss_trip>;
+ cooling-device = <&cx_cdev 0 0>;
+ };
+
+ mx_vdd_cdev {
+ trip = <&mapss_trip>;
+ cooling-device = <&mx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&mapss_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+
+ adsp_vdd_cdev {
+ trip = <&mapss_trip>;
+ cooling-device = <&adsp_vdd 0 0>;
+ };
+ };
+ };
+
+ camera-lowc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&tsens0 3>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ camera_cap_trip: camera-cap-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ lmh_cpu_cdev {
+ trip = <&camera_cap_trip>;
+ cooling-device = <&lmh_cpu_vdd 1 1>;
+ };
+ };
+ };
+
+ camera-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 3>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ camera_trip: camera-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cx_vdd_cdev {
+ trip = <&camera_trip>;
+ cooling-device = <&cx_cdev 0 0>;
+ };
+
+ mx_vdd_cdev {
+ trip = <&camera_trip>;
+ cooling-device = <&mx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&camera_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+
+ adsp_vdd_cdev {
+ trip = <&camera_trip>;
+ cooling-device = <&adsp_vdd 0 0>;
+ };
+ };
+ };
+
+ quiet-therm-step {
+ polling-delay-passive = <2000>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm6125_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ status = "disabled";
+
+ trips {
+ skin_batt_trip0: batt-trip0 {
+ temperature = <39000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ skin_modem_trip0: modem-trip0 {
+ temperature = <40000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ skin_gold_trip: gold-trip {
+ temperature = <40000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ skin_batt_trip1: batt-trip1 {
+ temperature = <41000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ skin_silver_trip: silver-trip {
+ temperature = <41000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ skin_modem_trip1: modem-trip1 {
+ temperature = <42000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ skin_modem_trip2: modem-trip2 {
+ temperature = <43000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ skin_batt_trip2: batt-trip2 {
+ temperature = <43000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ skin_gpu_trip: gpu-trip {
+ temperature = <43000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ skin_batt_trip3: batt-trip3 {
+ temperature = <45000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ skin_modem_trip3: modem-trip3 {
+ temperature = <50000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ skin_hvx_trip: hvx-trip {
+ temperature = <52000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ gold_cdev {
+ trip = <&skin_gold_trip>;
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-4)>;
+ };
+
+ silver_cdev {
+ trip = <&skin_silver_trip>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-5)>;
+ };
+
+ gpu_cdev {
+ trip = <&skin_gpu_trip>;
+ cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+
+ hvx_cdev {
+ trip = <&skin_hvx_trip>;
+ cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ mdm_cdev0 {
+ trip = <&skin_modem_trip0>;
+ cooling-device = <&modem_proc 1 1>;
+ };
+
+ mdm_cdev1 {
+ trip = <&skin_modem_trip1>;
+ cooling-device = <&modem_pa 1 1>;
+ };
+
+ mdm_cdev2 {
+ trip = <&skin_modem_trip2>;
+ cooling-device = <&modem_pa 2 2>;
+ };
+
+ mdm_cdev3 {
+ trip = <&skin_modem_trip3>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ mdm_cdev4 {
+ trip = <&skin_modem_trip3>;
+ cooling-device = <&modem_proc 3 3>;
+ };
+
+ batt_cdev1 {
+ trip = <&skin_batt_trip0>;
+ };
+
+ batt_cdev2 {
+ trip = <&skin_batt_trip1>;
+ };
+
+ batt_cdev3 {
+ trip = <&skin_batt_trip2>;
+ };
+
+ batt_cdev4 {
+ trip = <&skin_batt_trip3>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-usb.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-usb.dtsi
new file mode 100755
index 0000000..f3f2d38
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-usb.dtsi
@@ -0,0 +1,322 @@
+#include <dt-bindings/clock/qcom,gcc-bengal.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/phy/qcom,usb3-11nm-qmp-combo.h>
+
+&soc {
+ /* Primary USB port related controller */
+ usb0: ssusb@4e00000 {
+ compatible = "qcom,dwc-usb3-msm";
+ reg = <0x4e00000 0x100000>;
+ reg-names = "core_base";
+
+ iommus = <&apps_smmu 0x120 0x0>;
+ qcom,iommu-dma = "atomic";
+ qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq";
+
+ clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+ clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+ "xo", "sleep_clk", "utmi_clk";
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+ reset-names = "core_reset";
+
+ USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
+ dpdm-supply = <&qusb_phy0>;
+
+ qcom,core-clk-rate = <133333333>;
+ qcom,core-clk-rate-hs = <66666667>;
+ qcom,num-gsi-evt-buffs = <0x3>;
+ qcom,gsi-reg-offset =
+ <0x0fc /* GSI_GENERAL_CFG */
+ 0x110 /* GSI_DBL_ADDR_L */
+ 0x120 /* GSI_DBL_ADDR_H */
+ 0x130 /* GSI_RING_BASE_ADDR_L */
+ 0x144 /* GSI_RING_BASE_ADDR_H */
+ 0x1a4>; /* GSI_IF_STS */
+ qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
+ qcom,gsi-disable-io-coherency;
+
+ qcom,msm-bus,name = "usb0";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ /* suspend vote */
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>,
+
+ /* nominal vote */
+ <MSM_BUS_MASTER_USB3
+ MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+ /* svs vote */
+ <MSM_BUS_MASTER_USB3
+ MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+ /* min vote */
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 1 1>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 1 1>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 1 1>;
+
+ dwc3@4e00000 {
+ compatible = "snps,dwc3";
+ reg = <0x4e00000 0xcd00>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ usb-phy = <&qusb_phy0>, <&usb_qmp_phy>;
+ tx-fifo-resize;
+ linux,sysdev_is_parent;
+ snps,disable-clk-gating;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3-u1u2-disable;
+ snps,usb3_lpm_capable;
+ usb-core-id = <0>;
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+
+ qcom,usbbam@0x04f04000 {
+ compatible = "qcom,usb-bam-msm";
+ reg = <0x04f04000 0x17000>;
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+
+ qcom,usb-bam-fifo-baseaddr = <0xc121000>;
+ qcom,usb-bam-num-pipes = <4>;
+ qcom,disable-clk-gating;
+ qcom,usb-bam-override-threshold = <0x4001>;
+ qcom,usb-bam-max-mbps-highspeed = <400>;
+ qcom,usb-bam-max-mbps-superspeed = <3600>;
+ qcom,reset-bam-on-connect;
+
+ qcom,pipe0 {
+ label = "ssusb-qdss-in-0";
+ qcom,usb-bam-mem-type = <2>;
+ qcom,dir = <1>;
+ qcom,pipe-num = <0>;
+ qcom,peer-bam = <0>;
+ qcom,peer-bam-physical-address = <0x08064000>;
+ qcom,src-bam-pipe-index = <0>;
+ qcom,dst-bam-pipe-index = <0>;
+ qcom,data-fifo-offset = <0x0>;
+ qcom,data-fifo-size = <0x1800>;
+ qcom,descriptor-fifo-offset = <0x1800>;
+ qcom,descriptor-fifo-size = <0x800>;
+ };
+ };
+ };
+
+ /* Primary USB port related High Speed PHY */
+ qusb_phy0: qusb@1613000 {
+ compatible = "qcom,qusb2phy";
+ reg = <0x01613000 0x180>,
+ <0x003cb250 0x4>,
+ <0x01b40258 0x4>,
+ <0x01612000 0x4>;
+ reg-names = "qusb_phy_base",
+ "tcsr_clamp_dig_n_1p8",
+ "tune2_efuse_addr",
+ "eud_enable_reg";
+
+ vdd-supply = <&pm6125_l4>;
+ vdda18-supply = <&pm6125_l12>;
+ vdda33-supply = <&pm6125_l15>;
+ qcom,vdd-voltage-level = <0 925000 970000>;
+ qcom,tune2-efuse-bit-pos = <25>;
+ qcom,tune2-efuse-num-bits = <4>;
+ qcom,qusb-phy-init-seq = <0xf8 0x80
+ 0xb3 0x84
+ 0x81 0x88
+ 0xc0 0x8c
+ 0x30 0x08
+ 0x79 0x0c
+ 0x21 0x10
+ 0x14 0x9c
+ 0x80 0x04
+ 0x9f 0x1c
+ 0x00 0x18>;
+ phy_type = "utmi";
+ qcom,phy-clk-scheme = "cmos";
+ qcom,major-rev = <1>;
+
+ clocks = <&rpmcc CXO_SMD_OTG_CLK>,
+ <&gcc GCC_AHB2PHY_USB_CLK>;
+ clock-names = "ref_clk_src", "cfg_ahb_clk";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ reset-names = "phy_reset";
+ };
+
+ /* Primary USB port related QMP USB PHY */
+ usb_qmp_phy: ssphy@1615000 {
+ compatible = "qcom,usb-ssphy-qmp-usb3-or-dp";
+ reg = <0x01615000 0x1000>,
+ <0x03cb244 0x4>;
+ reg-names = "qmp_phy_base",
+ "vls_clamp_reg";
+
+ vdd-supply = <&pm6125_l4>;
+ core-supply = <&pm6125_l12>;
+ qcom,vdd-voltage-level = <0 925000 970000>;
+ qcom,core-voltage-level = <0 1800000 1800000>;
+ qcom,qmp-phy-init-seq =
+ /* <reg_offset, value, delay> */
+ <USB3PHY_QSERDES_COM_SYSCLK_EN_SEL 0x14 0x00
+ USB3PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x08 0x00
+ USB3PHY_QSERDES_COM_CLK_SELECT 0x30 0x00
+ USB3PHY_QSERDES_COM_SYS_CLK_CTRL 0x06 0x00
+ USB3PHY_QSERDES_COM_RESETSM_CNTRL 0x00 0x00
+ USB3PHY_QSERDES_COM_RESETSM_CNTRL2 0x08 0x00
+ USB3PHY_QSERDES_COM_BG_TRIM 0x0f 0x00
+ USB3PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x01 0x00
+ USB3PHY_QSERDES_COM_HSCLK_SEL 0x00 0x00
+ USB3PHY_QSERDES_COM_DEC_START_MODE0 0x82 0x00
+ USB3PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x55 0x00
+ USB3PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x55 0x00
+ USB3PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x03 0x00
+ USB3PHY_QSERDES_COM_CP_CTRL_MODE0 0x0b 0x00
+ USB3PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0x00
+ USB3PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x28 0x00
+ USB3PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x80 0x00
+ USB3PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00 0x00
+ USB3PHY_QSERDES_COM_CORECLK_DIV 0x0a 0x00
+ USB3PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x15 0x00
+ USB3PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0x00
+ USB3PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00 0x00
+ USB3PHY_QSERDES_COM_LOCK_CMP_EN 0x00 0x00
+ USB3PHY_QSERDES_COM_CORE_CLK_EN 0x00 0x00
+ USB3PHY_QSERDES_COM_LOCK_CMP_CFG 0x00 0x00
+ USB3PHY_QSERDES_COM_VCO_TUNE_MAP 0x00 0x00
+ USB3PHY_QSERDES_COM_BG_TIMER 0x0a 0x00
+ USB3PHY_QSERDES_COM_SSC_EN_CENTER 0x01 0x00
+ USB3PHY_QSERDES_COM_SSC_PER1 0x31 0x00
+ USB3PHY_QSERDES_COM_SSC_PER2 0x01 0x00
+ USB3PHY_QSERDES_COM_SSC_ADJ_PER1 0x00 0x00
+ USB3PHY_QSERDES_COM_SSC_ADJ_PER2 0x00 0x00
+ USB3PHY_QSERDES_COM_SSC_STEP_SIZE1 0xde 0x00
+ USB3PHY_QSERDES_COM_SSC_STEP_SIZE2 0x07 0x00
+ USB3PHY_QSERDES_COM_PLL_IVCO 0x0f 0x00
+ USB3PHY_QSERDES_COM_CMN_CONFIG 0x06 0x00
+ USB3PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x80 0x00
+ USB3PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x01 0x00
+ USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x0b 0x00
+ USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x0b 0x00
+ USB3PHY_QSERDES_RXA_UCDR_PI_CONTROLS 0x00 0x00
+ USB3PHY_QSERDES_RXB_UCDR_PI_CONTROLS 0x00 0x00
+ USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0x00 0x00
+ USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0x00 0x00
+ USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x00 0x00
+ USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x00 0x00
+ USB3PHY_QSERDES_RXA_UCDR_FO_GAIN 0x0a 0x00
+ USB3PHY_QSERDES_RXB_UCDR_FO_GAIN 0x0a 0x00
+ USB3PHY_QSERDES_RXA_UCDR_SO_GAIN 0x06 0x00
+ USB3PHY_QSERDES_RXB_UCDR_SO_GAIN 0x06 0x00
+ USB3PHY_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x75 0x00
+ USB3PHY_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x75 0x00
+ USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x02 0x00
+ USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x02 0x00
+ USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4e 0x00
+ USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4e 0x00
+ USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x18 0x00
+ USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18 0x00
+ USB3PHY_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0x00
+ USB3PHY_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0x00
+ USB3PHY_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0x00
+ USB3PHY_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0x00
+ USB3PHY_QSERDES_RXA_VGA_CAL_CNTRL2 0x0a 0x00
+ USB3PHY_QSERDES_RXB_VGA_CAL_CNTRL2 0x0a 0x00
+ USB3PHY_QSERDES_RXA_SIGDET_CNTRL 0x03 0x00
+ USB3PHY_QSERDES_RXB_SIGDET_CNTRL 0x03 0x00
+ USB3PHY_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x16 0x00
+ USB3PHY_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x16 0x00
+ USB3PHY_QSERDES_RXA_SIGDET_ENABLES 0x00 0x00
+ USB3PHY_QSERDES_RXB_SIGDET_ENABLES 0x00 0x00
+ USB3PHY_QSERDES_RXA_RX_MODE_00 0x00 0x00
+ USB3PHY_QSERDES_RXB_RX_MODE_00 0x00 0x00
+ USB3PHY_QSERDES_TXA_HIGHZ_DRVR_EN 0x10 0x00
+ USB3PHY_QSERDES_TXB_HIGHZ_DRVR_EN 0x10 0x00
+ USB3PHY_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0x00
+ USB3PHY_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0x00
+ USB3PHY_QSERDES_TXA_LANE_MODE_1 0xc6 0x00
+ USB3PHY_QSERDES_TXB_LANE_MODE_1 0xc6 0x00
+ USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x00 0x00
+ USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x00 0x00
+ USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x00 0x00
+ USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x00 0x00
+ USB3PHY_PCS_TXMGN_V0 0x9f 0x00
+ USB3PHY_PCS_TXDEEMPH_M6DB_V0 0x17 0x00
+ USB3PHY_PCS_TXDEEMPH_M3P5DB_V0 0x0f 0x00
+ USB3PHY_PCS_FLL_CNTRL2 0x83 0x00
+ USB3PHY_PCS_FLL_CNTRL1 0x02 0x00
+ USB3PHY_PCS_FLL_CNT_VAL_L 0x09 0x00
+ USB3PHY_PCS_FLL_CNT_VAL_H_TOL 0xa2 0x00
+ USB3PHY_PCS_FLL_MAN_CODE 0x85 0x00
+ USB3PHY_PCS_LOCK_DETECT_CONFIG1 0xd1 0x00
+ USB3PHY_PCS_LOCK_DETECT_CONFIG2 0x1f 0x00
+ USB3PHY_PCS_LOCK_DETECT_CONFIG3 0x47 0x00
+ USB3PHY_PCS_RXEQTRAINING_WAIT_TIME 0x75 0x00
+ USB3PHY_PCS_RXEQTRAINING_RUN_TIME 0x13 0x00
+ USB3PHY_PCS_LFPS_TX_ECSTART_EQTLOCK 0x86 0x00
+ USB3PHY_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x04 0x00
+ USB3PHY_PCS_TSYNC_RSYNC_TIME 0x44 0x00
+ USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0x00
+ USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0x00
+ USB3PHY_PCS_RCVR_DTCT_DLY_U3_L 0x40 0x00
+ USB3PHY_PCS_RCVR_DTCT_DLY_U3_H 0x00 0x00
+ USB3PHY_PCS_RX_SIGDET_LVL 0x88 0x00
+ 0xffffffff 0xffffffff 0x00>;
+
+ qcom,qmp-phy-reg-offset =
+ <0xd74 /* USB3_PHY_PCS_STATUS */
+ 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */
+ 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */
+ 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */
+ 0xc00 /* USB3_PHY_SW_RESET */
+ 0xc08 /* USB3_PHY_START */
+ 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&rpmcc CXO_SMD_OTG_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_AHB2PHY_USB_CLK>;
+
+ clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
+ "ref_clk", "cfg_ahb_clk";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
+ <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
+ reset-names = "phy_reset", "phy_phy_reset";
+ };
+
+ usb_nop_phy: usb_nop_phy {
+ compatible = "usb-nop-xceiv";
+ };
+
+ usb_audio_qmi_dev {
+ compatible = "qcom,usb-audio-qmi-dev";
+ iommus = <&apps_smmu 0x1cf 0x0>;
+ qcom,iommu-dma = "disabled";
+ qcom,usb-audio-stream-id = <0xf>;
+ qcom,usb-audio-intr-num = <2>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal-vidc.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal-vidc.dtsi
new file mode 100755
index 0000000..5a97a53
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal-vidc.dtsi
@@ -0,0 +1,110 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ msm_vidc: qcom,vidc@5a00000 {
+ compatible = "qcom,msm-vidc", "qcom,bengal-vidc";
+ status = "ok";
+ reg = <0x5a00000 0x200000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+
+ /* Supply */
+ venus-supply = <&gcc_venus_gdsc>;
+ venus-core0-supply = <&gcc_vcodec0_gdsc>;
+
+ /* Clocks */
+ clock-names = "core_clk", "iface_clk", "bus_clk",
+ "core0_clk", "core0_bus_clk", "throttle_clk";
+ clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>,
+ <&gcc GCC_VIDEO_AHB_CLK>,
+ <&gcc GCC_VENUS_CTL_AXI_CLK>,
+ <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>,
+ <&gcc GCC_VCODEC0_AXI_CLK>,
+ <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>;
+ qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk",
+ "core0_clk", "core0_bus_clk", "throttle_clk";
+ qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0 0x0>;
+ qcom,allowed-clock-rates = <133330000 240000000 300000000
+ 384000000>;
+
+ /* Buses */
+ bus_cnoc {
+ compatible = "qcom,msm-vidc,bus";
+ label = "cnoc";
+ qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <1000 1000>;
+ };
+
+ venus_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "vidc-ar50-ddr";
+ qcom,bus-range-kbps = <1000 6500000>;
+ };
+
+ arm9_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-arm9-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <1000 1000>;
+ };
+
+ /* MMUs */
+ non_secure_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_ns";
+ iommus =
+ <&apps_smmu 0x860 0x00>,
+ <&apps_smmu 0x880 0x00>;
+ qcom,iommu-dma-addr-pool = <0x70800000 0x6f800000>;
+ qcom,iommu-faults = "non-fatal";
+ buffer-types = <0xfff>;
+ virtual-addr-pool = <0x70800000 0x6f800000>;
+ };
+
+ secure_bitstream_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_bitstream";
+ iommus =
+ <&apps_smmu 0x861 0x04>;
+ qcom,iommu-dma-addr-pool = <0x4b000000 0x25800000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
+ buffer-types = <0x241>;
+ virtual-addr-pool = <0x4b000000 0x25800000>;
+ qcom,secure-context-bank;
+ };
+
+ secure_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_pixel";
+ iommus =
+ <&apps_smmu 0x863 0x0>;
+ qcom,iommu-dma-addr-pool = <0x25800000 0x25800000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
+ buffer-types = <0x106>;
+ virtual-addr-pool = <0x25800000 0x25800000>;
+ qcom,secure-context-bank;
+ };
+
+ secure_non_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_non_pixel";
+ iommus =
+ <&apps_smmu 0x804 0xE0>;
+ qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
+ buffer-types = <0x480>;
+ virtual-addr-pool = <0x1000000 0x24800000>;
+ qcom,secure-context-bank;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal.dts b/arch/arm64/boot/dts/vendor/qcom/bengal.dts
new file mode 100755
index 0000000..9ae4867
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "bengal.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Bengal SoC";
+ compatible = "qcom,bengal";
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengal.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengal.dtsi
new file mode 100755
index 0000000..519586a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengal.dtsi
@@ -0,0 +1,2897 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,dispcc-bengal.h>
+#include <dt-bindings/clock/qcom,gcc-bengal.h>
+#include <dt-bindings/clock/qcom,gpucc-bengal.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
+#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
+
+#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
+ opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
+ opp-supported-hw = <ddrtype>;}
+
+#define DDR_TYPE_LPDDR3 5
+#define DDR_TYPE_LPDDR4X 7
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGAL";
+ compatible = "qcom,bengal";
+ qcom,msm-id = <417 0x10000>, <444 0x10000>;
+ interrupt-parent = <&wakegic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+ mem-offline {
+ compatible = "qcom,mem-offline";
+ offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
+ <0x1 0xc0000000 0x0 0x80000000>,
+ <0x2 0xc0000000 0x1 0x40000000>;
+ granule = <512>;
+ };
+
+ aliases {
+ sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
+ sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
+ swr0 = &swr0;
+ swr1 = &swr1;
+ ufshc1 = &ufshc_mem; /* Embedded UFS slot */
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ #cooling-cells = <2>;
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ };
+
+ L1_I_0: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_0: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x1>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+ L1_I_1: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_1: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x2>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+ L1_I_2: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_2: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x3>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+ L1_I_3: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_3: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ next-level-cache = <&L2_1>;
+ qcom,freq-domain = <&cpufreq_hw 1 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+ #cooling-cells = <2>;
+ L2_1: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ };
+
+ L1_I_100: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_100: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x101>;
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ qcom,freq-domain = <&cpufreq_hw 1 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+
+ L1_I_101: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_101: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x102>;
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ qcom,freq-domain = <&cpufreq_hw 1 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+
+ L1_I_102: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_102: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x103>;
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ qcom,freq-domain = <&cpufreq_hw 1 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+
+ L1_I_103: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_103: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ firmware: firmware {
+ android {
+ compatible = "android,firmware";
+ vbmeta {
+ compatible="android,vbmeta";
+ parts = "vbmeta,boot,system,vendor,dtbo,recovery";
+ };
+
+ fstab {
+ compatible = "android,fstab";
+ vendor {
+ compatible = "android,vendor";
+ dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,discard";
+ fsmgr_flags = "wait,slotselect,avb";
+ status = "ok";
+ };
+ };
+ };
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: hyp_region@45700000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45700000 0x0 0x600000>;
+ };
+
+ xbl_aop_mem: xbl_aop_region@45e00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45e00000 0x0 0x140000>;
+ };
+
+ sec_apps_mem: sec_apps_region@45fff000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45fff000 0x0 0x1000>;
+ };
+
+ smem_mem: smem_region@46000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x46000000 0x0 0x200000>;
+ };
+
+ removed_mem: removed_region@60000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x60000000 0x0 0x3900000>;
+ };
+
+ pil_modem_mem: modem_region@4ab00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x4ab00000 0x0 0x6900000>;
+ };
+
+ pil_video_mem: pil_video_region@51400000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51400000 0x0 0x500000>;
+ };
+
+ wlan_msa_mem: wlan_msa_region@51900000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51900000 0x0 0x100000>;
+ };
+
+ pil_cdsp_mem: cdsp_regions@51a00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51a00000 0x0 0x1e00000>;
+ };
+
+ pil_adsp_mem: pil_adsp_region@53800000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x53800000 0x0 0x1e00000>;
+ };
+
+ pil_ipa_fw_mem: ipa_fw_region@55600000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x55600000 0x0 0x10000>;
+ };
+
+ pil_ipa_gsi_mem: ipa_gsi_region@55610000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x55610000 0x0 0x5000>;
+ };
+
+ pil_gpu_mem: gpu_region@55615000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x55615000 0x0 0x2000>;
+ };
+
+ user_contig_mem: user_contig_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ qseecom_mem: qseecom_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1400000>;
+ };
+
+ qseecom_ta_mem: qseecom_ta_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ cdsp_sec_mem: cdsp_sec_regions@46200000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x46200000 0x0 0x1e00000>;
+ };
+
+ secure_display_memory: secure_display_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x00000000 0 0xffffffff>;
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x5c00000>;
+ };
+
+ cont_splash_memory: cont_splash_region@5c000000 {
+ reg = <0x0 0x5c000000 0x0 0x00f00000>;
+ label = "cont_splash_region";
+ };
+
+ disp_rdump_memory: disp_rdump_region@5c000000 {
+ reg = <0x0 0x5c000000 0x0 0x00f00000>;
+ label = "disp_rdump_region";
+ };
+
+ dfps_data_memory: dfps_data_region@5cf00000 {
+ reg = <0x0 0x5cf00000 0x0 0x0100000>;
+ label = "dfps_data_region";
+ };
+
+ adsp_mem: adsp_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x00000000 0 0xffffffff>;
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x800000>;
+ };
+
+ dump_mem: mem_dump_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ size = <0 0x800000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+
+ chosen {
+ bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
+ };
+
+ soc: soc { };
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ intc: interrupt-controller@f200000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ reg = <0xf200000 0x10000>, /* GICD */
+ <0xf300000 0x100000>; /* GICR * 8 */
+ interrupts = <1 9 4>;
+ };
+
+ jtag_mm0: jtagmm@9040000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9040000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU0>;
+ };
+
+ jtag_mm1: jtagmm@9140000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9140000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU1>;
+ };
+
+ jtag_mm2: jtagmm@9240000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9240000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU2>;
+ };
+
+ jtag_mm3: jtagmm@9340000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9340000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU3>;
+ };
+
+ jtag_mm4: jtagmm@9440000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9440000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU4>;
+ };
+
+ jtag_mm5: jtagmm@9540000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9540000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU5>;
+ };
+
+ jtag_mm6: jtagmm@9640000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9640000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU6>;
+ };
+
+ jtag_mm7: jtagmm@9740000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9740000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU7>;
+ };
+
+ qcom,memshare {
+ compatible = "qcom,memshare";
+
+ qcom,client_1 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x0>;
+ qcom,client-id = <0>;
+ qcom,allocate-boot-time;
+ label = "modem";
+ };
+
+ qcom,client_2 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x0>;
+ qcom,client-id = <2>;
+ label = "modem";
+ };
+
+ mem_client_3_size: qcom,client_3 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x500000>;
+ qcom,client-id = <1>;
+ qcom,allocate-on-request;
+ label = "modem";
+ };
+ };
+
+ slim_aud: slim@a5c0000 {
+ cell-index = <1>;
+ compatible = "qcom,slim-ngd";
+ reg = <0xa5c0000 0x2c000>,
+ <0xa584000 0x20000>, <0xa66e000 0x2000>;
+ reg-names = "slimbus_physical",
+ "slimbus_bam_physical", "slimbus_lpass_mem";
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "slimbus_irq", "slimbus_bam_irq";
+ qcom,apps-ch-pipes = <0x0>;
+ qcom,ea-pc = <0x360>;
+ status = "ok";
+
+ /* Slimbus Slave DT for WCN3990 */
+ btfmslim_codec: wcn3990 {
+ compatible = "qcom,btfmslim_slave";
+ elemental-addr = [00 01 20 02 17 02];
+ qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
+ qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
+ };
+ };
+
+ wakegic: wake-gic {
+ compatible = "qcom,mpm-gic-bengal", "qcom,mpm-gic";
+ interrupts-extended = <&wakegic GIC_SPI 197
+ IRQ_TYPE_EDGE_RISING>;
+ reg = <0x45f01b8 0x1000>,
+ <0xf011008 0x4>; /* MSM_APCS_GCC_BASE 4K */
+ reg-names = "vmpm", "ipc";
+ qcom,num-mpm-irqs = <96>;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <3>;
+ };
+
+ wakegpio: wake-gpio {
+ compatible = "qcom,mpm-gpio";
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <2>;
+ };
+
+ bluetooth: bt_wcn3990 {
+ compatible = "qca,wcn3990";
+ qca,bt-sw-ctrl-gpio = <&tlmm 87 0>; /* SW_CTRL */
+ qca,bt-vdd-io-supply = <&L9A>; /* IO */
+ qca,bt-vdd-core-supply = <&L17A>; /* RFA */
+ qca,bt-vdd-pa-supply = <&L23A>; /* CH0 */
+ qca,bt-vdd-xtal-supply = <&L16A>; /* XO */
+
+ qca,bt-vdd-io-voltage-level = <1700000 1900000>;
+ qca,bt-vdd-core-voltage-level = <1304000 1304000>;
+ qca,bt-vdd-pa-voltage-level = <3000000 3312000>;
+ qca,bt-vdd-xtal-voltage-level = <1700000 1900000>;
+
+ qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 1 0xf08>,
+ <1 2 0xf08>,
+ <1 3 0xf08>,
+ <1 0 0xf08>;
+ clock-frequency = <19200000>;
+ };
+
+ dcc: dcc_v2@1be2000 {
+ compatible = "qcom,dcc-v2";
+ reg = <0x1be2000 0x1000>,
+ <0x1bee000 0x2000>;
+ reg-names = "dcc-base", "dcc-ram-base";
+ dcc-ram-offset = <0x2000>;
+ };
+
+ timer@f120000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xf120000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@f121000 {
+ frame-number = <0>;
+ interrupts = <0 8 0x4>,
+ <0 7 0x4>;
+ reg = <0xf121000 0x1000>,
+ <0xf122000 0x1000>;
+ };
+
+ frame@f123000 {
+ frame-number = <1>;
+ interrupts = <0 9 0x4>;
+ reg = <0xf123000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f124000 {
+ frame-number = <2>;
+ interrupts = <0 10 0x4>;
+ reg = <0xf124000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f125000 {
+ frame-number = <3>;
+ interrupts = <0 11 0x4>;
+ reg = <0xf125000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f126000 {
+ frame-number = <4>;
+ interrupts = <0 12 0x4>;
+ reg = <0xf126000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f127000 {
+ frame-number = <5>;
+ interrupts = <0 13 0x4>;
+ reg = <0xf127000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f128000 {
+ frame-number = <6>;
+ interrupts = <0 14 0x4>;
+ reg = <0xf128000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ arm64_cpu_erp {
+ compatible = "arm,arm64-cpu-erp";
+ interrupt-names = "pri-dbe-irq",
+ "sec-dbe-irq",
+ "pri-ext-irq",
+ "sec-ext-irq";
+ interrupts = <0 43 4>,
+ <0 44 4>,
+ <0 41 4>,
+ <0 42 4>;
+ poll-delay-ms = <5000>;
+ };
+
+ l2cache_pmu {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "qcom,l2cache-pmu";
+ ranges;
+
+ cluster0@f111000 {
+ cluster-id = <0>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf111000 0x1000>;
+ };
+
+ cluster1@f011000 {
+ cluster-id = <1>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf011000 0x1000>;
+ };
+ };
+
+ qcom,msm-imem@c125000 {
+ compatible = "qcom,msm-imem";
+ reg = <0xc125000 0x1000>;
+ ranges = <0x0 0xc125000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mem_dump_table@10 {
+ compatible = "qcom,msm-imem-mem_dump_table";
+ reg = <0x10 0x8>;
+ };
+
+ restart_reason@65c {
+ compatible = "qcom,msm-imem-restart_reason";
+ reg = <0x65c 0x4>;
+ };
+
+ dload_type@1c {
+ compatible = "qcom,msm-imem-dload-type";
+ reg = <0x1c 0x4>;
+ };
+
+ boot_stats@6b0 {
+ compatible = "qcom,msm-imem-boot_stats";
+ reg = <0x6b0 0x20>;
+ };
+
+ kaslr_offset@6d0 {
+ compatible = "qcom,msm-imem-kaslr_offset";
+ reg = <0x6d0 0xc>;
+ };
+
+ pil@94c {
+ compatible = "qcom,msm-imem-pil";
+ reg = <0x94c 0xc8>;
+ };
+
+ diag_dload@c8 {
+ compatible = "qcom,msm-imem-diag-dload";
+ reg = <0xc8 0xc8>;
+ };
+ };
+
+ restart@440b000 {
+ compatible = "qcom,pshold";
+ reg = <0x440b000 0x4>,
+ <0x03d3000 0x4>;
+ reg-names = "pshold-base", "tcsr-boot-misc-detect";
+ };
+
+ qcom_seecom: qseecom@61800000 {
+ compatible = "qcom,qseecom";
+ reg = <0x61800000 0x2100000>;
+ reg-names = "secapp-region";
+ memory-region = <&qseecom_mem>;
+ qcom,hlos-num-ce-hw-instances = <1>;
+ qcom,hlos-ce-hw-instance = <0>;
+ qcom,qsee-ce-hw-instance = <0>;
+ qcom,disk-encrypt-pipe-pair = <2>;
+ qcom,support-fde;
+ qcom,fde-key-size;
+ qcom,appsbl-qseecom-support;
+ qcom,commonlib64-loaded-by-uefi;
+ qcom,msm-bus,name = "qseecom-noc";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 0 0>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 200000 400000>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 300000 800000>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 400000 1000000>;
+ clock-names =
+ "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks =
+ <&rpmcc QSEECOM_CE1_CLK>,
+ <&rpmcc QSEECOM_CE1_CLK>,
+ <&rpmcc QSEECOM_CE1_CLK>,
+ <&rpmcc QSEECOM_CE1_CLK>;
+ qcom,ce-opp-freq = <192000000>;
+ qcom,qsee-reentrancy-support = <2>;
+ };
+
+ qcom_smcinvoke: smcinvoke@61800000 {
+ compatible = "qcom,smcinvoke";
+ reg = <0x61800000 0x2100000>;
+ reg-names = "secapp-region";
+ };
+
+ qcom_rng: qrng@1b53000 {
+ compatible = "qcom,msm-rng";
+ reg = <0x1b53000 0x1000>;
+ qcom,msm-rng-iface-clk;
+ qcom,no-qrng-config;
+ qcom,msm-bus,name = "msm-rng-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_PRNG 0 0>, /* No vote */
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_PRNG 0 300000>; /* 75 MHz */
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "iface_clk";
+ };
+
+ qcom_tzlog: tz-log@c125720 {
+ compatible = "qcom,tz-log";
+ reg = <0xc125720 0x3000>;
+ qcom,hyplog-enabled;
+ hyplog-address-offset = <0x410>;
+ hyplog-size-offset = <0x414>;
+ };
+
+ qcom_cedev: qcedev@1b20000 {
+ compatible = "qcom,qcedev";
+ reg = <0x1b20000 0x20000>,
+ <0x1b04000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <3>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,ce-hw-shared;
+ qcom,bam-ee = <0>;
+ qcom,msm-bus,name = "qcedev-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 0 0>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 393600 393600>;
+ clock-names =
+ "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks =
+ <&rpmcc QCEDEV_CE1_CLK>,
+ <&rpmcc QCEDEV_CE1_CLK>,
+ <&rpmcc QCEDEV_CE1_CLK>,
+ <&rpmcc QCEDEV_CE1_CLK>;
+ qcom,ce-opp-freq = <192000000>;
+ qcom,smmu-s1-enable;
+ iommus = <&apps_smmu 0x0086 0x0011>,
+ <&apps_smmu 0x0096 0x0011>;
+ qcom,iommu-dma = "atomic";
+
+ qcom_cedev_ns_cb {
+ compatible = "qcom,qcedev,context-bank";
+ label = "ns_context";
+ iommus = <&apps_smmu 0x92 0>,
+ <&apps_smmu 0x98 0x1>,
+ <&apps_smmu 0x9F 0>;
+ qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>;
+ };
+
+ qcom_cedev_s_cb {
+ compatible = "qcom,qcedev,context-bank";
+ label = "secure_context";
+ iommus = <&apps_smmu 0x93 0>,
+ <&apps_smmu 0x9C 0x1>,
+ <&apps_smmu 0x9E 0>;
+ qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>;
+ qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
+ qcom,secure-context-bank;
+ };
+ };
+
+ qcom_crypto: qcrypto@1b20000 {
+ compatible = "qcom,qcrypto";
+ reg = <0x1b20000 0x20000>,
+ <0x1b04000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <2>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,bam-ee = <0>;
+ qcom,ce-hw-shared;
+ qcom,clk-mgmt-sus-res;
+ qcom,msm-bus,name = "qcrypto-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST
+ 0 0>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST
+ 393600 393600>;
+ clock-names =
+ "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks =
+ <&rpmcc QCRYPTO_CE1_CLK>,
+ <&rpmcc QCRYPTO_CE1_CLK>,
+ <&rpmcc QCRYPTO_CE1_CLK>,
+ <&rpmcc QCRYPTO_CE1_CLK>;
+ qcom,use-sw-aes-cbc-ecb-ctr-algo;
+ qcom,use-sw-aes-xts-algo;
+ qcom,use-sw-aes-ccm-algo;
+ qcom,use-sw-ahash-algo;
+ qcom,use-sw-aead-algo;
+ qcom,use-sw-hmac-algo;
+ qcom,smmu-s1-enable;
+ iommus = <&apps_smmu 0x0084 0x0011>,
+ <&apps_smmu 0x0094 0x0011>;
+ qcom,iommu-dma = "atomic";
+ };
+
+ qcom,mpm2-sleep-counter@4403000 {
+ compatible = "qcom,mpm2-sleep-counter";
+ reg = <0x4403000 0x1000>;
+ clock-frequency = <32768>;
+ };
+
+ qcom,msm-rtb {
+ compatible = "qcom,msm-rtb";
+ qcom,rtb-size = <0x100000>;
+ };
+
+ cpu_pmu: cpu-pmu {
+ compatible = "arm,armv8-pmuv3";
+ qcom,irq-is-percpu;
+ interrupts = <1 6 4>;
+ };
+
+ eud: qcom,msm-eud@1610000 {
+ compatible = "qcom,msm-eud";
+ interrupt-names = "eud_irq";
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x1610000 0x2000>,
+ <0x1612000 0x1000>,
+ <0x3E5018 0x4>;
+ reg-names = "eud_base", "eud_mode_mgr2",
+ "eud_tcsr_check_reg";
+ qcom,secure-eud-en;
+ qcom,eud-tcsr-check-enable;
+ qcom,eud-clock-vote-req;
+ clocks = <&gcc GCC_AHB2PHY_USB_CLK>;
+ clock-names = "eud_ahb2phy_clk";
+ status = "ok";
+ };
+
+ qcom,msm-gladiator-v2@f100000 {
+ compatible = "qcom,msm-gladiator-v2";
+ reg = <0xf100000 0xdc00>;
+ reg-names = "gladiator_base";
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "atb_clk";
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ };
+
+ wdog: qcom,wdt@f017000 {
+ compatible = "qcom,msm-watchdog";
+ reg = <0xf017000 0x1000>;
+ reg-names = "wdt-base";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bark-time = <11000>;
+ qcom,pet-time = <9360>;
+ qcom,ipi-ping;
+ qcom,wakeup-enable;
+ };
+
+ rpm_bus: qcom,rpm-smd {
+ compatible = "qcom,rpm-smd";
+ rpm-channel-name = "rpm_requests";
+ interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+ rpm-channel-type = <15>; /* SMD_APPS_RPM */
+ };
+
+ qcom,chd_silver {
+ compatible = "qcom,core-hang-detect";
+ label = "silver";
+ qcom,threshold-arr = <0x0f1880b0 0x0f1980b0
+ 0x0f1a80b0 0x0f1b80b0>;
+ qcom,config-arr = <0x0f1880b8 0x0f1980b8
+ 0x0f1a80b8 0x0f1b80b8>;
+ };
+
+ qcom,chd_gold {
+ compatible = "qcom,core-hang-detect";
+ label = "gold";
+ qcom,threshold-arr = <0x0f0880b0 0x0f0980b0
+ 0x0f0a80b0 0x0f0b80b0>;
+ qcom,config-arr = <0x0f0880b8 0x0f0980b8
+ 0x0f0a80b8 0x0f0b80b8>;
+ };
+
+ qcom,ghd {
+ compatible = "qcom,gladiator-hang-detect";
+ qcom,threshold-arr = <0x0f1d141c 0x0f1d1420
+ 0x0f1d1424 0x0f1d1428
+ 0x0f1d142c 0x0f1d1430>;
+ qcom,config-reg = <0x0f1d1434>;
+ };
+
+ qcom,lpass@ab00000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0xab00000 0x00100>;
+
+ vdd_lpi_cx-supply = <&L3A_LEVEL>;
+ qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx";
+ qcom,vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ vdd_lpi_mx-supply = <&L2A_LEVEL>;
+ qcom,vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+
+ clocks = <&rpmcc CXO_SMD_PIL_LPASS_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+ qcom,mas-crypto = <&mas_crypto_c0>;
+
+ qcom,pas-id = <1>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <423>;
+ qcom,minidump-id = <5>;
+ qcom,sysmon-id = <1>;
+ qcom,ssctl-instance-id = <0x14>;
+ qcom,firmware-name = "adsp";
+ memory-region = <&pil_adsp_mem>;
+ qcom,complete-ramdump;
+ qcom,minidump-as-elf32;
+
+ /* Inputs from lpass */
+ interrupts-extended = <&intc 0 282 1>,
+ <&adsp_smp2p_in 0 0>,
+ <&adsp_smp2p_in 2 0>,
+ <&adsp_smp2p_in 1 0>,
+ <&adsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack";
+
+ /* Outputs to lpass */
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+ };
+
+ qcom,turing@b300000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0xb300000 0x100000>;
+
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,proxy-reg-names = "vdd_cx";
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+
+ clocks = <&rpmcc CXO_SMD_PIL_CDSP_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+ qcom,mas-crypto = <&mas_crypto_c0>;
+
+ qcom,pas-id = <18>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <601>;
+ qcom,minidump-id = <7>;
+ qcom,sysmon-id = <7>;
+ qcom,ssctl-instance-id = <0x17>;
+ qcom,firmware-name = "cdsp";
+ memory-region = <&pil_cdsp_mem>;
+ qcom,complete-ramdump;
+ qcom,minidump-as-elf32;
+
+ /* Inputs from turing */
+ interrupts-extended = <&intc 0 265 1>,
+ <&cdsp_smp2p_in 0 0>,
+ <&cdsp_smp2p_in 2 0>,
+ <&cdsp_smp2p_in 1 0>,
+ <&cdsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack";
+
+ /* Outputs to turing */
+ qcom,smem-states = <&cdsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+ };
+
+ mem_dump {
+ compatible = "qcom,mem-dump";
+ memory-region = <&dump_mem>;
+
+ c0_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x0>;
+ };
+
+ c1_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x1>;
+ };
+
+ c2_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x2>;
+ };
+
+ c3_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x3>;
+ };
+
+ c100_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x4>;
+ };
+
+ c101_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x5>;
+ };
+
+ c102_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x6>;
+ };
+
+ c103_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x7>;
+ };
+
+ c_scandump {
+ qcom,dump-size = <0x40000>;
+ qcom,dump-id = <0xeb>;
+ };
+
+ l1_icache0 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x60>;
+ };
+
+ l1_icache1 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x61>;
+ };
+
+ l1_icache2 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x62>;
+ };
+
+ l1_icache3 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x63>;
+ };
+
+ l1_icache100 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x64>;
+ };
+
+ l1_icache101 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x65>;
+ };
+
+ l1_icache102 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x66>;
+ };
+
+ l1_icache103 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x67>;
+ };
+
+ l1_dcache0 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x80>;
+ };
+
+ l1_dcache1 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x81>;
+ };
+
+ l1_dcache2 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x82>;
+ };
+
+ l1_dcache3 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x83>;
+ };
+
+ l1_dcache100 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x84>;
+ };
+
+ l1_dcache101 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x85>;
+ };
+
+ l1_dcache102 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x86>;
+ };
+
+ l1_dcache103 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x87>;
+ };
+
+ l2_tlb0 {
+ qcom,dump-size = <0x2000>;
+ qcom,dump-id = <0x120>;
+ };
+
+ l2_tlb1 {
+ qcom,dump-size = <0x2000>;
+ qcom,dump-id = <0x121>;
+ };
+
+ l2_tlb2 {
+ qcom,dump-size = <0x2000>;
+ qcom,dump-id = <0x122>;
+ };
+
+ l2_tlb3 {
+ qcom,dump-size = <0x2000>;
+ qcom,dump-id = <0x123>;
+ };
+
+ l2_tlb100 {
+ qcom,dump-size = <0x4800>;
+ qcom,dump-id = <0x124>;
+ };
+
+ l2_tlb101 {
+ qcom,dump-size = <0x4800>;
+ qcom,dump-id = <0x125>;
+ };
+
+ l2_tlb102 {
+ qcom,dump-size = <0x4800>;
+ qcom,dump-id = <0x126>;
+ };
+
+ l2_tlb103 {
+ qcom,dump-size = <0x4800>;
+ qcom,dump-id = <0x127>;
+ };
+
+ rpm_sw {
+ qcom,dump-size = <0x28000>;
+ qcom,dump-id = <0xea>;
+ };
+
+ pmic {
+ qcom,dump-size = <0x40000>;
+ qcom,dump-id = <0xe4>;
+ };
+
+ fcm {
+ qcom,dump-size = <0x8400>;
+ qcom,dump-id = <0xee>;
+ };
+
+ tmc_etf {
+ qcom,dump-size = <0x8000>;
+ qcom,dump-id = <0xf0>;
+ };
+
+ etr_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x100>;
+ };
+
+ etf_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x101>;
+ };
+
+ misc_data {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xe8>;
+ };
+ };
+
+ sdhc_1: sdhci@4744000 {
+ compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe";
+ reg = <0x4744000 0x1000>, <0x4745000 0x1000>,
+ <0x4748000 0x8000>;
+ reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";
+
+ interrupts-extended = <&intc GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 19 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "hc_irq", "pwr_irq", "tb_trig_irq";
+
+ qcom,bus-width = <8>;
+ qcom,large-address-bus;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
+ 192000000 384000000>;
+ qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+
+ qcom,devfreq,freq-table = <50000000 200000000>;
+
+ qcom,scaling-lower-bus-speed-mode = "DDR52";
+
+ qcom,msm-bus,name = "sdhc1";
+ qcom,msm-bus,num-cases = <9>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <78 512 0 0>, <1 606 0 0>,
+ /* 400 KB/s*/
+ <78 512 1046 1600>,
+ <1 606 1600 1600>,
+ /* 20 MB/s */
+ <78 512 20480 80000>,
+ <1 606 80000 80000>,
+ /* 25 MB/s */
+ <78 512 25600 250000>,
+ <1 606 50000 133320>,
+ /* 50 MB/s */
+ <78 512 51200 250000>,
+ <1 606 65000 133320>,
+ /* 100 MB/s */
+ <78 512 102400 250000>,
+ <1 606 65000 133320>,
+ /* 200 MB/s */
+ <78 512 204800 800000>,
+ <1 606 200000 300000>,
+ /* 400 MB/s */
+ <78 512 204800 800000>,
+ <1 606 200000 300000>,
+ /* Max. bandwidth */
+ <78 512 1338562 4096000>,
+ <1 606 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100750000 200000000 400000000 4294967295>;
+
+ /* PM QoS */
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <26 26>;
+ qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
+ qcom,pm-qos-cmdq-latency-us = <26 26>, <26 26>;
+ qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>;
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface_clk", "core_clk", "ice_core_clk";
+
+ qcom,ice-clk-rates = <300000000 100000000>;
+
+ /* Add support for gcc hw reset */
+ resets = <&gcc GCC_SDCC1_BCR>;
+ reset-names = "core_reset";
+
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040850>;
+
+ qcom,nonremovable;
+ status = "disabled";
+ };
+
+ sdhc_2: sdhci@4784000 {
+ compatible = "qcom,sdhci-msm-v5";
+ reg = <0x4784000 0x1000>;
+ reg-names = "hc_mem";
+
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <4>;
+ qcom,large-address-bus;
+
+ qcom,clk-rates = <400000 20000000 25000000
+ 50000000 100000000 202000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
+ "SDR104";
+
+ qcom,devfreq,freq-table = <50000000 202000000>;
+
+ qcom,msm-bus,name = "sdhc2";
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <81 512 0 0>, <1 608 0 0>,
+ /* 400 KB/s*/
+ <81 512 1046 3200>,
+ <1 608 1600 1600>,
+ /* 20 MB/s */
+ <81 512 52286 250000>,
+ <1 608 80000 133320>,
+ /* 25 MB/s */
+ <81 512 65360 250000>,
+ <1 608 100000 133320>,
+ /* 50 MB/s */
+ <81 512 130718 250000>,
+ <1 608 133320 133320>,
+ /* 100 MB/s */
+ <81 512 261438 250000>,
+ <1 608 150000 133320>,
+ /* 200 MB/s */
+ <81 512 261438 800000>,
+ <1 608 300000 300000>,
+ /* Max. bandwidth */
+ <81 512 1338562 4096000>,
+ <1 608 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100750000 200000000 4294967295>;
+
+ /* PM QoS */
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <26 26>;
+ qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
+ qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>;
+
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>;
+ clock-names = "iface_clk", "core_clk";
+
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>;
+
+ status = "disabled";
+ };
+
+ ufsphy_mem: ufsphy_mem@4807000 {
+ reg = <0x4807000 0xdb8>; /* PHY regs */
+ reg-names = "phy_mem";
+ #phy-cells = <0>;
+
+ lanes-per-direction = <1>;
+
+ clock-names = "ref_clk_src",
+ "ref_clk",
+ "ref_aux_clk";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_UFS_CLKREF_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+ status = "disabled";
+ };
+
+ ufshc_mem: ufshc@4804000 {
+ compatible = "qcom,ufshc";
+ reg = <0x4804000 0x3000>, <0x4810000 0x8000>;
+ reg-names = "ufs_mem", "ufs_ice";
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufsphy_mem>;
+ phy-names = "ufsphy";
+
+ lanes-per-direction = <1>;
+ dev-ref-clk-freq = <0>; /* 19.2 MHz */
+ spm-level = <5>;
+
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "core_clk_ice",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk";
+ clocks =
+ <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
+ freq-table-hz =
+ <50000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <37500000 150000000>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ qcom,msm-bus,name = "ufshc_mem";
+ qcom,msm-bus,num-cases = <12>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /*
+ * During HS G3 UFS runs at nominal voltage corner, vote
+ * higher bandwidth to push other buses in the data path
+ * to run at nominal to achieve max throughput.
+ * 4GBps pushes BIMC to run at nominal.
+ * 200MBps pushes CNOC to run at nominal.
+ * Vote for half of this bandwidth for HS G3 1-lane.
+ * For max bandwidth, vote high enough to push the buses
+ * to run in turbo voltage corner.
+ */
+ <123 512 0 0>, <1 757 0 0>, /* No vote */
+ <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */
+ <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */
+ <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */
+ <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */
+ <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */
+ <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */
+ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */
+ <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */
+ <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */
+ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */
+ <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
+
+ qcom,bus-vector-names = "MIN",
+ "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
+ "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
+ "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
+ "MAX";
+
+ /* PM QoS */
+ qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
+ qcom,pm-qos-cpu-group-latency-us = <26 26>;
+ qcom,pm-qos-default-cpu = <0>;
+
+ pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
+ pinctrl-0 = <&ufs_dev_reset_assert>;
+ pinctrl-1 = <&ufs_dev_reset_deassert>;
+
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "core_reset";
+ non-removable;
+
+ status = "disabled";
+ };
+
+ thermal_zones: thermal-zones {};
+
+ tsens0:tsens@c222000 {
+ compatible = "qcom,tsens24xx";
+ reg = <0x04410000 0x8>,
+ <0x04411000 0x1ff>;
+ reg-names = "tsens_srot_physical",
+ "tsens_tm_physical";
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tsens-upper-lower", "tsens-critical";
+ tsens-reinit-wa;
+ #thermal-sensor-cells = <1>;
+ };
+
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ clock-output-names = "xo_board";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ clock-output-names = "sleep_clk";
+ #clock-cells = <0>;
+ };
+ };
+
+ rpmcc: qcom,rpmcc {
+ compatible = "qcom,rpmcc-bengal";
+ #clock-cells = <1>;
+ };
+
+ qcom,rmtfs_sharedmem@0 {
+ compatible = "qcom,sharedmem-uio";
+ reg = <0x0 0x200000>;
+ reg-names = "rmtfs";
+ qcom,client-id = <0x00000001>;
+ qcom,guard-memory;
+ qcom,vm-nav-path;
+ };
+
+ gcc: qcom,gcc@1400000 {
+ compatible = "qcom,bengal-gcc", "syscon";
+ reg = <0x1400000 0x1f0000>;
+ reg-names = "cc_base";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ dispcc: qcom,dispcc@5f00000 {
+ compatible = "qcom,bengal-dispcc", "syscon";
+ reg = <0x05f00000 0x20000>;
+ reg-names = "cc_base";
+ clock-names = "cfg_ahb_clk";
+ clocks = <&gcc GCC_DISP_AHB_CLK>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gpucc: qcom,gpucc@5990000 {
+ compatible = "qcom,bengal-gpucc", "syscon";
+ reg = <0x5990000 0x9000>;
+ reg-names = "cc_base";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mccc_debug: syscon@447d200 {
+ compatible = "syscon";
+ reg = <0x447d200 0x100>;
+ };
+
+ cpucc_debug: syscon@f11101c {
+ compatible = "syscon";
+ reg = <0xf11101c 0x4>;
+ };
+
+ debugcc: qcom,cc-debug {
+ compatible = "qcom,bengal-debugcc";
+ qcom,gcc = <&gcc>;
+ qcom,dispcc = <&dispcc>;
+ qcom,gpucc = <&gpucc>;
+ qcom,mccc = <&mccc_debug>;
+ qcom,cpucc = <&cpucc_debug>;
+ clock-names = "xo_clk_src";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ #clock-cells = <1>;
+ };
+
+ cpufreq_hw: qcom,cpufreq-hw {
+ compatible = "qcom,cpufreq-hw";
+ reg = <0xf521000 0x1000>, <0xf523000 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+ qcom,no-accumulative-counter;
+ qcom,max-lut-entries = <12>;
+ #freq-domain-cells = <2>;
+ };
+
+ tcsr_mutex_block: syscon@00340000 {
+ compatible = "syscon";
+ reg = <0x340000 0x20000>;
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_block 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ smem: qcom,smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ rpm_msg_ram: memory@045f0000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x45f0000 0x7000>;
+ };
+
+ apcs_glb: mailbox@0f111000 {
+ compatible = "qcom,bengal-apcs-hmss-global";
+ reg = <0xF111000 0x1000>;
+
+ #mbox-cells = <1>;
+ };
+
+ qcom,msm-cdsp-loader {
+ compatible = "qcom,cdsp-loader";
+ qcom,proc-img-to-load = "cdsp";
+ };
+
+ qcom,msm-adsprpc-mem {
+ compatible = "qcom,msm-adsprpc-mem-region";
+ memory-region = <&adsp_mem>;
+ restrict-access;
+ };
+
+ qcom,msm_fastrpc {
+ compatible = "qcom,msm-fastrpc-compute";
+ qcom,rpc-latency-us = <611>;
+ qcom,adsp-remoteheap-vmid = <22 37>;
+ qcom,fastrpc-adsp-audio-pdr;
+ qcom,fastrpc-adsp-sensors-pdr;
+
+ qcom,msm_fastrpc_compute_cb1 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x0C01 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb2 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x0C02 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb3 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x0C03 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb4 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x0C04 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb5 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x0C05 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb6 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x0C06 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb9 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ qcom,secure-context-bank;
+ iommus = <&apps_smmu 0x0C09 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb10 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C3 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb11 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C4 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb12 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C5 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb13 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C6 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb14 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C7 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ };
+
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ qcom,rpm_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_adsp>,
+ <&glink_cdsp>;
+ };
+
+ };
+
+ qcom,glink {
+ compatible = "qcom,glink";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ glink_modem: modem {
+ qcom,remote-pid = <1>;
+ transport = "smem";
+ mboxes = <&apcs_glb 12>;
+ mbox-names = "mpss_smem";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
+
+ label = "modem";
+ qcom,glink-label = "mpss";
+
+ qcom,modem_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,low-latency;
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,modem_ds {
+ qcom,glink-channels = "DS";
+ qcom,intents = <0x4000 2>;
+ };
+
+ qcom,modem_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_adsp>,
+ <&glink_cdsp>;
+ };
+ };
+
+ glink_adsp: adsp {
+ qcom,remote-pid = <2>;
+ transport = "smem";
+ mboxes = <&apcs_glb 8>;
+ mbox-names = "adsp_smem";
+ interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
+
+ label = "adsp";
+ qcom,glink-label = "lpass";
+
+ qcom,adsp_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,low-latency;
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,apr_tal_rpmsg {
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,intents = <0x200 20>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,adsp_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_cdsp>;
+ };
+ };
+
+ glink_cdsp: cdsp {
+ qcom,remote-pid = <5>;
+ transport = "smem";
+ mboxes = <&apcs_glb 28>;
+ mbox-names = "cdsp_smem";
+ interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>;
+
+ label = "cdsp";
+ qcom,glink-label = "cdsp";
+
+ qcom,cdsp_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,msm_cdsprm_rpmsg {
+ compatible = "qcom,msm-cdsprm-rpmsg";
+ qcom,glink-channels = "cdsprmglink-apps-dsp";
+ qcom,intents = <0x20 12>;
+
+ msm_cdsp_rm: qcom,msm_cdsp_rm {
+ compatible = "qcom,msm-cdsp-rm";
+ qcom,qos-latency-us = <100>;
+ qcom,qos-maxhold-ms = <20>;
+ };
+ };
+
+ qcom,cdsp_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_adsp>;
+ };
+ };
+ };
+
+ qcom,glinkpkt {
+ compatible = "qcom,glinkpkt";
+
+ qcom,glinkpkt-at-mdm0 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DS";
+ qcom,glinkpkt-dev-name = "at_mdm0";
+ };
+
+ qcom,glinkpkt-apr-apps2 {
+ qcom,glinkpkt-edge = "adsp";
+ qcom,glinkpkt-ch-name = "apr_apps2";
+ qcom,glinkpkt-dev-name = "apr_apps2";
+ };
+
+ qcom,glinkpkt-data40-cntl {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA40_CNTL";
+ qcom,glinkpkt-dev-name = "smdcntl8";
+ };
+
+ qcom,glinkpkt-data1 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA1";
+ qcom,glinkpkt-dev-name = "smd7";
+ };
+
+ qcom,glinkpkt-data4 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA4";
+ qcom,glinkpkt-dev-name = "smd8";
+ };
+
+ qcom,glinkpkt-data11 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA11";
+ qcom,glinkpkt-dev-name = "smd11";
+ };
+ };
+
+ qcom,smp2p_sleepstate {
+ compatible = "qcom,smp2p-sleepstate";
+ qcom,smem-states = <&sleepstate_smp2p_out 0>;
+ interrupt-parent = <&sleepstate_smp2p_in>;
+ interrupts = <0 0>;
+ interrupt-names = "smp2p-sleepstate-in";
+ };
+
+ qcom,smp2p-modem {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 14>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ /* ipa - inbound entry from mss */
+ smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
+ qcom,entry-name = "wlan";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ };
+
+ qcom,smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 10>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
+ qcom,entry-name = "rdbg";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
+ qcom,entry-name = "rdbg";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sleepstate_smp2p_out: sleepstate-out {
+ qcom,entry-name = "sleepstate";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ sleepstate_smp2p_in: qcom,sleepstate-in {
+ qcom,entry-name = "sleepstate_see";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 30>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
+ qcom,entry-name = "rdbg";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
+ qcom,entry-name = "rdbg";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,sps {
+ compatible = "qcom,msm-sps-4k";
+ qcom,pipe-attr-ee;
+ };
+
+ qfprom: qfprom@1b40000 {
+ compatible = "qcom,qfprom";
+ reg = <0x1b40000 0x7000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ read-only;
+ ranges;
+
+ stm_debug_fuse: stm@20f0 {
+ reg = <0x20f0 0x4>;
+ };
+
+ feat_conf5: feat_conf5@6018 {
+ reg = <0x6018 0x4>;
+ };
+
+ feat_conf10: feat_conf10@602c {
+ reg = <0x602c 0x4>;
+ };
+
+ adsp_variant: adsp_variant@6011 {
+ reg = <0x6011 0x1>;
+ bits = <3 1>;
+ };
+
+ gpu_speed_bin: gpu_speed_bin@6006 {
+ reg = <0x6006 0x2>;
+ bits = <5 8>;
+ };
+
+ gpu_gaming_bin: gpu_gaming_bin@602d {
+ reg = <0x602d 0x1>;
+ bits = <5 1>;
+ };
+ };
+
+ spmi_bus: qcom,spmi@1c40000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x1c40000 0x1100>,
+ <0x1e00000 0x2000000>,
+ <0x3e00000 0x100000>,
+ <0x3f00000 0xa0000>,
+ <0x1c0a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
+ icnss: qcom,icnss@C800000 {
+ compatible = "qcom,icnss";
+ reg = <0xC800000 0x800000>,
+ <0xb0000000 0x10000>;
+ reg-names = "membase", "smmu_iova_ipa";
+ iommus = <&apps_smmu 0x1A0 0x1>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
+ <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
+ <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
+ <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH /* CE10 */ >,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH /* CE11 */ >;
+ qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
+ qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
+ qcom,iommu-dma = "fastmap";
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ qcom,iommu-geometry = <0xa0000000 0x10010000>;
+ vdd-cx-mx-supply = <&L8A>;
+ vdd-1.8-xo-supply = <&L16A>;
+ vdd-1.3-rfa-supply = <&L17A>;
+ vdd-3.3-ch0-supply = <&L23A>;
+ qcom,vdd-cx-mx-config = <640000 640000>;
+ qcom,vdd-3.3-ch0-config = <3000000 3312000>;
+ qcom,smp2p_map_wlan_1_in {
+ interrupts-extended = <&smp2p_wlan_1_in 0 0>,
+ <&smp2p_wlan_1_in 1 0>;
+ interrupt-names = "qcom,smp2p-force-fatal-error",
+ "qcom,smp2p-early-crash-ind";
+ };
+ };
+
+ qcom,venus@5ab0000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x5ab0000 0x20000>;
+
+ vdd-supply = <&gcc_venus_gdsc>;
+ qcom,proxy-reg-names = "vdd";
+
+ clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>,
+ <&gcc GCC_VENUS_CTL_AXI_CLK>,
+ <&gcc GCC_VIDEO_AHB_CLK>,
+ <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>;
+ clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk";
+ qcom,proxy-clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk";
+ qcom,mas-crypto = <&mas_crypto_c0>;
+
+ qcom,core-freq = <240000000>;
+ qcom,ahb-freq = <240000000>;
+
+ qcom,pas-id = <9>;
+ qcom,msm-bus,name = "pil-venus";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <63 512 0 0>,
+ <63 512 0 304000>;
+ qcom,proxy-timeout-ms = <100>;
+ qcom,firmware-name = "venus";
+ memory-region = <&pil_video_mem>;
+ };
+
+ cx_ipeak_lm: cx_ipeak@3ed000 {
+ compatible = "qcom,cx-ipeak-v2";
+ reg = <0x3ed000 0xe008>;
+ };
+
+ pil_modem: qcom,mss@6080000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x6080000 0x100>;
+
+ clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+ qcom,mas-crypto = <&mas_crypto_c0>;
+
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+ qcom,proxy-reg-names = "vdd_cx";
+
+ qcom,firmware-name = "modem";
+ memory-region = <&pil_modem_mem>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,sysmon-id = <0>;
+ qcom,ssctl-instance-id = <0x12>;
+ qcom,pas-id = <4>;
+ qcom,smem-id = <421>;
+ qcom,minidump-id = <3>;
+ qcom,aux-minidump-ids = <4>;
+ qcom,complete-ramdump;
+ qcom,sequential-fw-load;
+
+ qcom,msm-bus,name = "pil-modem";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0 0 8171520>;
+
+ /* Inputs from mss */
+ interrupts-extended = <&intc 0 307 1>,
+ <&modem_smp2p_in 0 0>,
+ <&modem_smp2p_in 2 0>,
+ <&modem_smp2p_in 1 0>,
+ <&modem_smp2p_in 3 0>,
+ <&modem_smp2p_in 7 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack",
+ "qcom,shutdown-ack";
+
+ /* Outputs to mss */
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+ };
+
+ ddr_bw_opp_table: ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY_DDR( 200, 8, 0xA0); /* 1525 MB/s */
+ BW_OPP_ENTRY_DDR( 300, 8, 0xA0); /* 2288 MB/s */
+ BW_OPP_ENTRY_DDR( 451, 8, 0xA0); /* 3440 MB/s */
+ BW_OPP_ENTRY_DDR( 547, 8, 0xA0); /* 4173 MB/s */
+ BW_OPP_ENTRY_DDR( 681, 8, 0xA0); /* 5195 MB/s */
+ BW_OPP_ENTRY_DDR( 768, 8, 0xA0); /* 5859 MB/s */
+ BW_OPP_ENTRY_DDR( 931, 8, 0x20); /* 7102 MB/s */
+ BW_OPP_ENTRY_DDR(1017, 8, 0x80); /* 7759 MB/s */
+ BW_OPP_ENTRY_DDR(1353, 8, 0x80); /*10322 MB/s */
+ BW_OPP_ENTRY_DDR(1555, 8, 0x80); /*11863 MB/s */
+ BW_OPP_ENTRY_DDR(1804, 8, 0x80); /*13763 MB/s */
+ };
+
+ suspendable_ddr4_bw_opp_table: suspendable-ddr4-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY_DDR( 0, 8, 0xA0); /* 0 MB/s */
+ BW_OPP_ENTRY_DDR( 200, 8, 0xA0); /* 1525 MB/s */
+ BW_OPP_ENTRY_DDR( 300, 8, 0xA0); /* 2288 MB/s */
+ BW_OPP_ENTRY_DDR( 451, 8, 0xA0); /* 3440 MB/s */
+ BW_OPP_ENTRY_DDR( 547, 8, 0xA0); /* 4173 MB/s */
+ BW_OPP_ENTRY_DDR( 681, 8, 0xA0); /* 5195 MB/s */
+ BW_OPP_ENTRY_DDR( 768, 8, 0xA0); /* 5859 MB/s */
+ BW_OPP_ENTRY_DDR( 931, 8, 0x20); /* 7102 MB/s */
+ BW_OPP_ENTRY_DDR(1017, 8, 0x80); /* 7759 MB/s */
+ BW_OPP_ENTRY_DDR(1353, 8, 0x80); /*10322 MB/s */
+ BW_OPP_ENTRY_DDR(1555, 8, 0x80); /*11863 MB/s */
+ BW_OPP_ENTRY_DDR(1804, 8, 0x80); /*13763 MB/s */
+ };
+
+ cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@01b8e200 {
+ compatible = "qcom,bimc-bwmon4";
+ reg = <0x01b8e300 0x100>, <0x01b8e200 0x100>;
+ reg-names = "base", "global_base";
+ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&cpu_cpu_ddr_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,target-dev = <&cpu0_cpu_ddr_lat>;
+ qcom,cachemiss-ev = <0x17>;
+ qcom,stall-cycle-ev = <0xE7>;
+ ddr3-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR3>;
+ qcom,core-dev-table =
+ < 864000 MHZ_TO_MBPS(200, 8) >,
+ < 1305600 MHZ_TO_MBPS(451, 8) >,
+ < 1804800 MHZ_TO_MBPS(768, 8) >;
+ };
+
+ ddr4-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
+ qcom,core-dev-table =
+ < 864000 MHZ_TO_MBPS( 300, 8) >,
+ < 1305600 MHZ_TO_MBPS( 547, 8) >,
+ < 1420000 MHZ_TO_MBPS( 768, 8) >,
+ < 1804800 MHZ_TO_MBPS(1017, 8) >;
+ };
+ };
+
+ cpu0_computemon: qcom,cpu0-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
+ ddr3-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR3>;
+ qcom,core-dev-table =
+ < 614400 MHZ_TO_MBPS( 200, 8) >,
+ < 1305600 MHZ_TO_MBPS( 451, 8) >,
+ < 1804800 MHZ_TO_MBPS( 768, 8) >;
+ };
+
+ ddr4-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
+ qcom,core-dev-table =
+ < 614400 MHZ_TO_MBPS( 300, 8) >,
+ < 1017600 MHZ_TO_MBPS( 451, 8) >,
+ < 1420000 MHZ_TO_MBPS( 547, 8) >,
+ < 1804800 MHZ_TO_MBPS( 768, 8) >;
+ };
+ };
+ };
+
+ cpu4_cpu_ddr_lat: qcom,cpu4-cpu-ddr-lat {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+
+ cpu4_cpu_ddr_latmon: qcom,cpu4-cpu-ddr-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+ qcom,target-dev = <&cpu4_cpu_ddr_lat>;
+ qcom,cachemiss-ev = <0x17>;
+ qcom,stall-cycle-ev = <0x24>;
+ ddr3-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR3>;
+ qcom,core-dev-table =
+ < 1056000 MHZ_TO_MBPS(200, 8) >,
+ < 1401600 MHZ_TO_MBPS(451, 8) >,
+ < 1804800 MHZ_TO_MBPS(768, 8) >,
+ < 2016000 MHZ_TO_MBPS(931, 8) >;
+ };
+
+ ddr4-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
+ qcom,core-dev-table =
+ < 902400 MHZ_TO_MBPS( 451, 8) >,
+ < 1401600 MHZ_TO_MBPS(1017, 8) >,
+ < 1804800 MHZ_TO_MBPS(1555, 8) >,
+ < 2016000 MHZ_TO_MBPS(1804, 8) >;
+ };
+ };
+
+ cpu4_computemon: qcom,cpu4-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+ qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
+ ddr3-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR3>;
+ qcom,core-dev-table =
+ < 652800 MHZ_TO_MBPS( 200, 8) >,
+ < 1056000 MHZ_TO_MBPS( 451, 8) >,
+ < 1401600 MHZ_TO_MBPS( 547, 8) >,
+ < 1536000 MHZ_TO_MBPS( 768, 8) >,
+ < 2016000 MHZ_TO_MBPS( 931, 8) >;
+ };
+
+ ddr4-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
+ qcom,core-dev-table =
+ < 902400 MHZ_TO_MBPS( 300, 8) >,
+ < 1056000 MHZ_TO_MBPS( 547, 8) >,
+ < 1401680 MHZ_TO_MBPS( 768, 8) >,
+ < 1804800 MHZ_TO_MBPS(1017, 8) >,
+ < 2016000 MHZ_TO_MBPS(1804, 8) >;
+ };
+ };
+ };
+
+ qcom,msm_gsi {
+ compatible = "qcom,msm_gsi";
+ };
+
+ qcom,rmnet-ipa {
+ compatible = "qcom,rmnet-ipa3";
+ qcom,rmnet-ipa-ssr;
+ qcom,ipa-platform-type-msm;
+ qcom,ipa-advertise-sg-support;
+ qcom,ipa-napi-enable;
+ };
+
+ ipa_hw: qcom,ipa@0x5800000 {
+ compatible = "qcom,ipa";
+ reg = <0x5800000 0x34000>,
+ <0x5804000 0x28000>;
+ reg-names = "ipa-base", "gsi-base";
+ interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ipa-irq", "gsi-irq";
+ qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */
+ qcom,ipa-hw-mode = <0>;
+ qcom,platform-type = <1>; /* MSM platform */
+ qcom,ee = <0>;
+ qcom,use-ipa-tethering-bridge;
+ qcom,modem-cfg-emb-pipe-flt;
+ qcom,ipa-wdi2;
+ qcom,ipa-wdi2_over_gsi;
+ qcom,ipa-endp-delay-wa;
+ qcom,ipa-fltrt-not-hashable;
+ qcom,use-64-bit-dma-mask;
+ qcom,arm-smmu;
+ qcom,smmu-fast-map;
+ qcom,use-ipa-pm;
+ qcom,skip-ieob-mask-wa;
+ clocks = <&rpmcc RPM_SMD_IPA_CLK>;
+ clock-names = "core_clk";
+ qcom,msm-bus,name = "ipa";
+ qcom,msm-bus,num-cases = <5>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+ /* SVS2 */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 465000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 68570>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 30>,
+ /* SVS */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 2000000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 267461>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 109890>,
+ /* NOMINAL */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 4000000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 712961>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 491520>,
+ /* TURBO */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 5598900>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 1436481>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 491520>;
+ qcom,bus-vector-names =
+ "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
+ qcom,throughput-threshold = <310 600 1000>;
+ qcom,scaling-exceptions = <>;
+
+ /* smp2p information */
+ qcom,smp2p_map_ipa_1_out {
+ compatible = "qcom,smp2p-map-ipa-1-out";
+ qcom,smem-states = <&smp2p_ipa_1_out 0>;
+ qcom,smem-state-names = "ipa-smp2p-out";
+ };
+
+ qcom,smp2p_map_ipa_1_in {
+ compatible = "qcom,smp2p-map-ipa-1-in";
+ interrupts-extended = <&smp2p_ipa_1_in 0 0>;
+ interrupt-names = "ipa-smp2p-in";
+ };
+ };
+
+ ipa_smmu_ap: ipa_smmu_ap {
+ compatible = "qcom,ipa-smmu-ap-cb";
+ iommus = <&apps_smmu 0x0140 0x0>;
+ qcom,iommu-dma-addr-pool = <0x10000000 0x30000000>;
+ /* modem tables in IMEM */
+ qcom,iommu-dma = "fastmap";
+ qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>;
+ qcom,iommu-geometry = <0 0xB0000000>;
+ };
+
+ ipa_smmu_wlan: ipa_smmu_wlan {
+ compatible = "qcom,ipa-smmu-wlan-cb";
+ iommus = <&apps_smmu 0x0141 0x0>;
+ /* ipa-uc ram */
+ qcom,iommu-dma = "atomic";
+ };
+
+ ipa_smmu_uc: ipa_smmu_uc {
+ compatible = "qcom,ipa-smmu-uc-cb";
+ iommus = <&apps_smmu 0x0142 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40400000 0x1fc00000>;
+ };
+
+ qcom,ipa_fws {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <0xf>;
+ qcom,firmware-name = "ipa_fws";
+ qcom,pil-force-shutdown;
+ memory-region = <&pil_ipa_fw_mem>;
+ };
+
+ qcom,demux {
+ compatible = "qcom,demux";
+ };
+};
+
+#include "bengal-gdsc.dtsi"
+#include "bengal-usb.dtsi"
+#include "bengal-ion.dtsi"
+#include "bengal-coresight.dtsi"
+#include "bengal-bus.dtsi"
+#include "bengal-vidc.dtsi"
+#include "pm6125.dtsi"
+
+&gcc_camss_top_gdsc {
+ status = "ok";
+};
+
+&gcc_ufs_phy_gdsc {
+ status = "ok";
+};
+
+&gcc_usb30_prim_gdsc {
+ status = "ok";
+};
+
+&gcc_vcodec0_gdsc {
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&gcc_venus_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_turing_mmu_tbu1_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_turing_mmu_tbu0_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {
+ status = "ok";
+};
+
+&mdss_core_gdsc {
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&gpu_cx_gdsc {
+ parent-supply = <&VDD_CX_LEVEL>;
+ status = "ok";
+};
+
+&gpu_gx_gdsc {
+ parent-supply = <&VDD_CX_LEVEL>;
+ status = "ok";
+};
+
+#include "msm-arm-smmu-bengal.dtsi"
+#include "pm6125-rpm-regulator.dtsi"
+#include "bengal-regulator.dtsi"
+#include "bengal-pm.dtsi"
+#include "bengal-pinctrl.dtsi"
+#include "bengal-qupv3.dtsi"
+#include "bengal-gpu.dtsi"
+#include "bengal-audio.dtsi"
+#include "bengal-sde-pll.dtsi"
+#include "bengal-sde.dtsi"
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #include "pm8008.dtsi"
+};
+
+&pm8008_8 {
+ /* PM8008 IRQ STAT */
+ interrupt-parent = <&tlmm>;
+ interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm8008_active &pm8008_interrupt>;
+};
+
+&pm8008_regulators {
+ vdd_l1_l2-supply = <&S6A>;
+};
+
+&L1P {
+ regulator-max-microvolt = <1200000>;
+ qcom,min-dropout-voltage = <100000>;
+};
+
+&L2P {
+ regulator-max-microvolt = <1056000>;
+ qcom,min-dropout-voltage = <100000>;
+};
+
+&L3P {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+};
+
+&L4P {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+};
+
+&L5P {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+};
+
+&L6P {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+};
+
+&L7P {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+};
+
+&qupv3_se4_2uart {
+ status = "ok";
+};
+
+&qupv3_se3_4uart {
+ status = "ok";
+};
+
+&pm6125_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&camera_therm_default &emmc_therm_default>;
+
+ pa_therm0 {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "pa_therm0";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ quiet_therm {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "quiet_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ camera_flash_therm {
+ reg = <ADC_GPIO1_PU2>;
+ label = "camera_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ emmc_ufs_therm {
+ reg = <ADC_GPIO2_PU2>;
+ label = "emmc_ufs_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm6125_gpios {
+ camera_therm {
+ camera_therm_default: camera_therm_default {
+ pins = "gpio3";
+ bias-high-impedance;
+ };
+ };
+
+ emmc_therm {
+ emmc_therm_default: emmc_therm_default {
+ pins = "gpio4";
+ bias-high-impedance;
+ };
+ };
+
+};
+
+&spmi_bus {
+ qcom,pm6125@0 {
+ pm6125_adc_tm_iio: adc_tm@3400 {
+ compatible = "qcom,adc-tm5-iio";
+ reg = <0x3400 0x100>;
+ #thermal-sensor-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ io-channels = <&pm6125_vadc ADC_GPIO1_PU2>,
+ <&pm6125_vadc ADC_GPIO2_PU2>;
+
+ camera_flash_therm {
+ reg = <ADC_GPIO1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ emmc_ufs_therm {
+ reg = <ADC_GPIO2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+ };
+ };
+};
+
+&pm6125_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>,
+ <&pm6125_vadc ADC_AMUX_THM2_PU2>,
+ <&pm6125_vadc ADC_XO_THERM_PU2>;
+
+ /* Channel nodes */
+ pa_therm0 {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ quiet_therm {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ xo_therm {
+ reg = <ADC_XO_THERM_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&msm_vidc {
+ qcom,cx-ipeak-data = <&cx_ipeak_lm 6>;
+ qcom,clock-freq-threshold = <300000000>;
+};
+
+#include "bengal-thermal.dtsi"
+#include "camera/bengal-camera.dtsi"
+#include "msm-rdbg.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-idp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp-idp-overlay.dts
new file mode 100755
index 0000000..b01175e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-idp-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengal-idp.dtsi"
+#include "bengal-idp-pmi632.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGALP IDP";
+ compatible = "qcom,bengalp-idp", "qcom,bengalp", "qcom,idp";
+ qcom,msm-id = <445 0x10000>, <420 0x10000>;
+ qcom,board-id = <34 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-idp.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp-idp.dts
new file mode 100755
index 0000000..db8a15b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-idp.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "bengalp.dtsi"
+#include "bengal-idp.dtsi"
+#include "bengal-idp-pmi632.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGALP IDP";
+ compatible = "qcom,bengalp-idp", "qcom,bengalp", "qcom,idp";
+ qcom,board-id = <34 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-2gb.dts
new file mode 100755
index 0000000..26bd558
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-2gb.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "bengalp-iot-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGALP-IOT 2Gb DDR HD+ SoC";
+ compatible = "qcom,bengalp-iot";
+ qcom,board-id = <0 0x403>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-2gb-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-2gb-overlay.dts
new file mode 100755
index 0000000..3761014
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-2gb-overlay.dts
@@ -0,0 +1,40 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengalp-iot-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGALP-IOT IDP 2Gb DDR HD+";
+ compatible = "qcom,bengalp-iot-idp", "qcom,bengalp-iot", "qcom,idp";
+ qcom,msm-id = <470 0x10000>;
+ qcom,board-id = <34 0x403>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_nt36525_truly_video>;
+};
+
+&qupv3_se2_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="novatek,NVT-ts";
+
+ novatek@62 {
+ compatible = "novatek,NVT-ts";
+ reg = <0x62>;
+ status = "ok";
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+
+ novatek,reset-gpio = <&tlmm 71 0x00>;
+ novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+ panel = <&dsi_nt36525_truly_video>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-2gb.dts
new file mode 100755
index 0000000..966ca966
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-2gb.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+#include "bengalp-iot-low-ram.dtsi"
+#include "bengalp-iot-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGALP-IOT IDP 2Gb DDR HD+";
+ compatible = "qcom,bengalp-iot-idp", "qcom,bengalp-iot", "qcom,idp";
+ qcom,board-id = <34 0x403>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_nt36525_truly_video>;
+};
+
+&qupv3_se2_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="novatek,NVT-ts";
+
+ novatek@62 {
+ compatible = "novatek,NVT-ts";
+ reg = <0x62>;
+ status = "ok";
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+
+ novatek,reset-gpio = <&tlmm 71 0x00>;
+ novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+ panel = <&dsi_nt36525_truly_video>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-low-ram.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-low-ram.dtsi
new file mode 100755
index 0000000..9a3cdc7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-low-ram.dtsi
@@ -0,0 +1 @@
+#include "bengalp-iot-idp.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-overlay.dts
new file mode 100755
index 0000000..dc0e382
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengalp-iot-idp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGALP-IOT IDP Overlay";
+ compatible = "qcom,bengalp-iot-idp", "qcom,bengalp-iot", "qcom,idp";
+ qcom,msm-id = <470 0x10000>;
+ qcom,board-id = <34 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc-2gb-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc-2gb-overlay.dts
new file mode 100755
index 0000000..0bd85a2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc-2gb-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengalp-iot-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGALP-IOT IDP AATC 2Gb DDR";
+ compatible = "qcom,bengalp-iot-idp", "qcom,bengalp-iot", "qcom,idp";
+ qcom,msm-id = <470 0x10000>;
+ qcom,board-id = <34 0x401>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc-2gb.dts
new file mode 100755
index 0000000..217daa8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc-2gb.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "bengalp-iot-low-ram.dtsi"
+#include "bengalp-iot-idp-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGALP-IOT IDP AATC 2Gb DDR";
+ compatible = "qcom,bengalp-iot-idp", "qcom,bengalp-iot", "qcom,idp";
+ qcom,board-id = <34 0x401>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc-overlay.dts
new file mode 100755
index 0000000..ecec206
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "bengalp-iot-idp.dtsi"
+#include "bengalp-iot-idp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGALP-IOT IDP USBC Audio";
+ compatible = "qcom,bengalp-iot-idp", "qcom,bengalp-iot", "qcom,idp";
+ qcom,msm-id = <470 0x10000>;
+ qcom,board-id = <34 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc.dts
new file mode 100755
index 0000000..091a668
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "bengalp-iot.dtsi"
+#include "bengalp-iot-idp.dtsi"
+#include "bengalp-iot-idp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGALP-IOT IDP USBC Audio";
+ compatible = "qcom,bengalp-iot-idp", "qcom,bengalp-iot", "qcom,idp";
+ qcom,board-id = <34 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc.dtsi
new file mode 100755
index 0000000..704385e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp-usbc.dtsi
@@ -0,0 +1,5 @@
+&bengal_snd {
+ qcom,msm-mbhc-usbc-audio-supported = <1>;
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp.dts
new file mode 100755
index 0000000..4299025
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "bengalp-iot.dtsi"
+#include "bengalp-iot-idp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGALP-IOT IDP";
+ compatible = "qcom,bengalp-iot-idp", "qcom,bengalp-iot", "qcom,idp";
+ qcom,board-id = <34 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp.dtsi
new file mode 100755
index 0000000..f045653
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-idp.dtsi
@@ -0,0 +1,2 @@
+#include "bengal-idp.dtsi"
+#include "bengal-idp-pmi632.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-low-ram.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-low-ram.dtsi
new file mode 100755
index 0000000..7451dc1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot-low-ram.dtsi
@@ -0,0 +1,148 @@
+#include "bengalp-iot.dtsi"
+/ {
+};
+
+/delete-node/ &hyp_mem;
+/delete-node/ &xbl_aop_mem;
+/delete-node/ &sec_apps_mem;
+/delete-node/ &smem_mem;
+/delete-node/ &removed_mem;
+/delete-node/ &pil_modem_mem;
+/delete-node/ &pil_video_mem;
+/delete-node/ &wlan_msa_mem;
+/delete-node/ &pil_cdsp_mem;
+/delete-node/ &pil_adsp_mem;
+/delete-node/ &pil_ipa_fw_mem;
+/delete-node/ &pil_ipa_gsi_mem;
+/delete-node/ &pil_gpu_mem;
+/delete-node/ &cdsp_sec_mem;
+
+/delete-node/ &user_contig_mem;
+/delete-node/ &qseecom_mem;
+/delete-node/ &qseecom_ta_mem;
+
+/delete-node/ &secure_display_memory;
+
+/delete-node/ &disp_rdump_memory;
+
+&reserved_memory {
+ hyp_mem: hyp_region@45700000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45700000 0x0 0x600000>;
+ };
+
+ xbl_aop_mem: xbl_aop_region@45e00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45e00000 0x0 0x100000>;
+ };
+
+ sec_apps_mem: sec_apps_region@45fff000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45fff000 0x0 0x1000>;
+ };
+
+ smem_mem: smem_region@46000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x46000000 0x0 0x200000>;
+ };
+
+ pil_modem_mem: modem_region@4ab00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x4ab00000 0x0 0x6900000>;
+ };
+
+ pil_video_mem: pil_video_region@51400000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51400000 0x0 0x500000>;
+ };
+
+ wlan_msa_mem: wlan_msa_region@51900000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51900000 0x0 0x100000>;
+ };
+
+ pil_cdsp_mem: cdsp_regions@51a00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51a00000 0x0 0x800000>;
+ };
+
+ pil_adsp_mem: pil_adsp_region@52200000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x52200000 0x0 0x1c00000>;
+ };
+
+ pil_ipa_fw_mem: ipa_fw_region@53e00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x53e00000 0x0 0x10000>;
+ };
+
+ pil_ipa_gsi_mem: ipa_gsi_region@53e10000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x53e10000 0x0 0x5000>;
+ };
+
+ pil_gpu_mem: gpu_region@53e15000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x53e15000 0x0 0x2000>;
+ };
+
+ tz_stat_mem: tz_stat_region@60000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x60000000 0x0 0x100000>;
+ };
+
+ removed_mem: removed_region@60100000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x60100000 0x0 0x2200000>;
+ };
+
+ qseecom_mem: qseecom_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ qseecom_ta_mem: qseecom_ta_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x400000>;
+ };
+
+ linux,cma {
+ size = <0x0 0x1000000>;
+ };
+};
+
+&soc {
+ qcom,ion {
+ /delete-node/ qcom,ion-heap@14;
+ /delete-node/ qcom,ion-heap@10;
+ /delete-node/ qcom,ion-heap@26;
+ };
+
+ qcom_seecom: qseecom@61800000 {
+ reg = <0x61800000 0xb00000>;
+ };
+
+ qcom_smcinvoke: smcinvoke@61800000 {
+ reg = <0x61800000 0xb00000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot.dts
new file mode 100755
index 0000000..b035dd2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "bengalp-iot.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGALP-IOT SoC";
+ compatible = "qcom,bengalp-iot";
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp-iot.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot.dtsi
new file mode 100755
index 0000000..8a9fa89
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp-iot.dtsi
@@ -0,0 +1,19 @@
+#include "bengal.dtsi"
+#include "bengal-pmi632.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. BENGALP-IOT";
+ compatible = "qcom,bengalp-iot";
+ qcom,msm-id = <470 0x0>;
+ qcom,msm-name = "BENGALP-IOT";
+};
+
+&soc {
+ qcom,rmnet-ipa {
+ status = "disabled";
+ };
+};
+
+&ipa_hw {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp.dts b/arch/arm64/boot/dts/vendor/qcom/bengalp.dts
new file mode 100755
index 0000000..a4bc2ac
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "bengalp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Bengalp SoC";
+ compatible = "qcom,bengalp";
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/bengalp.dtsi b/arch/arm64/boot/dts/vendor/qcom/bengalp.dtsi
new file mode 100755
index 0000000..f9a2c11
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/bengalp.dtsi
@@ -0,0 +1,19 @@
+/dts-v1/;
+
+#include "bengal.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Bengalp SoC";
+ compatible = "qcom,bengalp";
+ qcom,msm-id = <445 0x10000>, <420 0x10000>;
+};
+
+&soc {
+ qcom,rmnet-ipa {
+ status = "disabled";
+ };
+};
+
+&ipa_hw {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera-sensor-idp.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera-sensor-idp.dtsi
new file mode 100755
index 0000000..65ac199
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera-sensor-idp.dtsi
@@ -0,0 +1,393 @@
+#include <dt-bindings/clock/qcom,gcc-bengal.h>
+&soc {
+ led_flash_rear: qcom,camera-flash@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pmi632_flash0 &pmi632_flash1>;
+ torch-source = <&pmi632_torch0 &pmi632_torch1>;
+ switch-source = <&pmi632_switch0 &pmi632_switch0>;
+ status = "ok";
+ };
+
+ led_flash_rear_aux: qcom,camera-flash@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pmi632_flash0 &pmi632_flash1>;
+ torch-source = <&pmi632_torch0 &pmi632_torch1>;
+ switch-source = <&pmi632_switch0 &pmi632_switch0>;
+ status = "ok";
+ };
+
+ led_flash_rear_aux2: qcom,camera-flash@2 {
+ cell-index = <2>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pmi632_flash0 &pmi632_flash1>;
+ torch-source = <&pmi632_torch0 &pmi632_torch1>;
+ switch-source = <&pmi632_switch0 &pmi632_switch0>;
+ status = "ok";
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator0 {
+ cell-index = <0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ actuator_rear_aux: qcom,actuator1 {
+ cell-index = <1>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ eeprom_rear: qcom,eeprom0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_vaf-supply = <&L5P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear0_reset_suspend>;
+ gpios = <&tlmm 20 0>,
+ <&tlmm 18 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom1 {
+ cell-index = <1>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_vaf-supply = <&L5P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_rear1_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_rear1_reset_suspend>;
+ gpios = <&tlmm 19 0>,
+ <&tlmm 21 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ eeprom_front: qcom,eeprom2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_front0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_front0_reset_suspend>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 24 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rear_aux2: qcom,eeprom3 {
+ cell-index = <3>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_rear2_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_rear2_reset_suspend>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 65 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ /* Rear*/
+ qcom,cam-sensor0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear>;
+ led-flash-src = <&led_flash_rear>;
+ eeprom-src = <&eeprom_rear>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1050000 0>;
+ rgltr-max-voltage = <1800000 2800000 1050000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear0_reset_suspend>;
+ gpios = <&tlmm 20 0>,
+ <&tlmm 18 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ /*Rear Aux*/
+ qcom,cam-sensor1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear_aux>;
+ led-flash-src = <&led_flash_rear_aux>;
+ eeprom-src = <&eeprom_rear_aux>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_rear1_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_rear1_reset_suspend>;
+ gpios = <&tlmm 19 0>,
+ <&tlmm 21 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ /*Front*/
+ qcom,cam-sensor2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_front0_reset_active
+ &cam_sensor_csi_mux_oe_active
+ &cam_sensor_csi_mux_sel_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_front0_reset_suspend
+ &cam_sensor_csi_mux_oe_suspend
+ &cam_sensor_csi_mux_sel_suspend>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 24 0>,
+ <&tlmm 66 0>,
+ <&tlmm 67 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /*Rear Aux2*/
+ qcom,cam-sensor3 {
+ cell-index = <3>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_rear_aux2>;
+ eeprom-src = <&eeprom_rear_aux2>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_rear2_reset_active
+ &cam_sensor_csi_mux_oe_active
+ &cam_sensor_csi_mux_sel_active>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_rear2_reset_suspend
+ &cam_sensor_csi_mux_oe_suspend
+ &cam_sensor_csi_mux_sel_suspend>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 65 0>,
+ <&tlmm 66 0>,
+ <&tlmm 67 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera-sensor-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera-sensor-qrd.dtsi
new file mode 100755
index 0000000..a4c9347
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera-sensor-qrd.dtsi
@@ -0,0 +1,403 @@
+#include <dt-bindings/clock/qcom,gcc-bengal.h>
+&soc {
+ led_flash_rear: qcom,camera-flash@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pmi632_flash0 &pmi632_flash1>;
+ torch-source = <&pmi632_torch0 &pmi632_torch1>;
+ switch-source = <&pmi632_switch0 &pmi632_switch0>;
+ status = "ok";
+ };
+
+ led_flash_rear_aux: qcom,camera-flash@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pmi632_flash0 &pmi632_flash1>;
+ torch-source = <&pmi632_torch0 &pmi632_torch1>;
+ switch-source = <&pmi632_switch0 &pmi632_switch0>;
+ status = "ok";
+ };
+
+ led_flash_rear_aux2: qcom,camera-flash@2 {
+ cell-index = <2>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pmi632_flash0 &pmi632_flash1>;
+ torch-source = <&pmi632_torch0 &pmi632_torch1>;
+ switch-source = <&pmi632_switch0 &pmi632_switch0>;
+ status = "ok";
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator0 {
+ cell-index = <0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ actuator_rear_aux: qcom,actuator1 {
+ cell-index = <1>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ eeprom_rear: qcom,eeprom0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_vaf-supply = <&L5P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear0_reset_suspend>;
+ gpios = <&tlmm 20 0>,
+ <&tlmm 18 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom1 {
+ cell-index = <1>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_vaf-supply = <&L5P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_rear1_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_rear1_reset_suspend>;
+ gpios = <&tlmm 21 0>,
+ <&tlmm 19 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ eeprom_front: qcom,eeprom2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_front0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_front0_reset_suspend>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 24 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rear_aux2: qcom,eeprom3 {
+ cell-index = <3>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_rear2_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_rear2_reset_suspend>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 65 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ /* Rear*/
+ qcom,cam-sensor0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear>;
+ led-flash-src = <&led_flash_rear>;
+ eeprom-src = <&eeprom_rear>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_vaf-supply = <&L5P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear0_reset_suspend>;
+ gpios = <&tlmm 20 0>,
+ <&tlmm 18 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ /*Rear Aux*/
+ qcom,cam-sensor1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear_aux>;
+ led-flash-src = <&led_flash_rear_aux>;
+ eeprom-src = <&eeprom_rear_aux>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_vaf-supply = <&L5P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_rear1_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_rear1_reset_suspend>;
+ gpios = <&tlmm 21 0>,
+ <&tlmm 19 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ /*Front*/
+ qcom,cam-sensor2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_front0_reset_active
+ &cam_sensor_csi_mux_oe_active
+ &cam_sensor_csi_mux_sel_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_front0_reset_suspend
+ &cam_sensor_csi_mux_oe_suspend
+ &cam_sensor_csi_mux_sel_suspend>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 24 0>,
+ <&tlmm 66 0>,
+ <&tlmm 67 0>;
+ gpio-reset = <1>;
+ gpio-custom1 = <2>;
+ gpio-custom2 = <3>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_CSIMUX_OE0",
+ "CAM_CSIMUX_SEL0";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /*Rear Aux2*/
+ qcom,cam-sensor3 {
+ cell-index = <3>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_rear_aux2>;
+ eeprom-src = <&eeprom_rear_aux2>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_rear2_reset_active
+ &cam_sensor_csi_mux_oe_active
+ &cam_sensor_csi_mux_sel_active>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_rear2_reset_suspend
+ &cam_sensor_csi_mux_oe_suspend
+ &cam_sensor_csi_mux_sel_suspend>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 65 0>,
+ <&tlmm 66 0>,
+ <&tlmm 67 0>;
+ gpio-reset = <1>;
+ gpio-custom1 = <2>;
+ gpio-custom2 = <3>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3",
+ "CAM_CSIMUX_OE1",
+ "CAM_CSIMUX_SEL1";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera.dtsi
new file mode 100755
index 0000000..23c6041
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/bengal-camera.dtsi
@@ -0,0 +1,870 @@
+#include <dt-bindings/msm/msm-camera.h>
+
+&soc {
+ qcom,cam-req-mgr {
+ compatible = "qcom,cam-req-mgr";
+ status = "ok";
+ };
+
+ cam_csiphy0: qcom,csiphy0 {
+ cell-index = <0>;
+ compatible = "qcom,csiphy-v2.0", "qcom,csiphy";
+ reg = <0x05C52000 0x1000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x52000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr";
+ gdscr-supply = <&gcc_camss_top_gdsc>;
+ csi-vdd-voltage = <1200000>;
+ mipi-csi-vdd-supply = <&L18A>;
+ clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_CPHY_0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy0_clk",
+ "csi0phytimer_clk_src",
+ "csi0phytimer_clk";
+ src-clock-name = "csi0phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ clock-rates =
+ <19200000 0 19200000 0>,
+ <341330000 0 200000000 0>,
+ <341330000 0 200000000 0>,
+ <384000000 0 268800000 0>;
+ status = "ok";
+ };
+
+ cam_csiphy1: qcom,csiphy1 {
+ cell-index = <1>;
+ compatible = "qcom,csiphy-v2.0", "qcom,csiphy";
+ reg = <0x05C53000 0x1000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x53000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr";
+ gdscr-supply = <&gcc_camss_top_gdsc>;
+ csi-vdd-voltage = <1200000>;
+ mipi-csi-vdd-supply = <&L18A>;
+ clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_CPHY_1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy1_clk",
+ "csi1phytimer_clk_src",
+ "csi1phytimer_clk";
+ src-clock-name = "csi1phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ clock-rates =
+ <19200000 0 19200000 0>,
+ <341330000 0 200000000 0>,
+ <341330000 0 200000000 0>,
+ <384000000 0 268800000 0>;
+ status = "ok";
+ };
+
+ cam_csiphy2: qcom,csiphy2 {
+ cell-index = <2>;
+ compatible = "qcom,csiphy-v2.0", "qcom,csiphy";
+ reg = <0x05C54000 0x1000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x54000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr";
+ gdscr-supply = <&gcc_camss_top_gdsc>;
+ csi-vdd-voltage = <1200000>;
+ mipi-csi-vdd-supply = <&L18A>;
+ clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_CPHY_2_CLK>,
+ <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy2_clk",
+ "csi2phytimer_clk_src",
+ "csi2phytimer_clk";
+ src-clock-name = "csi2phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ clock-rates =
+ <19200000 0 19200000 0>,
+ <341330000 0 200000000 0>,
+ <341330000 0 200000000 0>,
+ <384000000 0 268800000 0>;
+ status = "ok";
+ };
+
+ cam_cci0: qcom,cci0 {
+ cell-index = <0>;
+ compatible = "qcom,cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x05C1B000 0x1000>;
+ reg-names = "cci";
+ reg-cam-base = <0x1B000>;
+ interrupt-names = "cci";
+ interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
+ status = "ok";
+ gdscr-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "gdscr";
+ clocks = <&gcc GCC_CAMSS_CCI_0_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK_SRC>;
+ clock-names = "cci_0_clk",
+ "cci_0_clk_src";
+ src-clock-name = "cci_0_clk_src";
+ clock-cntl-level = "svs";
+ clock-rates = <0 37500000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cci0_active &cci1_active>;
+ pinctrl-1 = <&cci0_suspend &cci1_suspend>;
+ gpios = <&tlmm 22 0>,
+ <&tlmm 23 0>,
+ <&tlmm 29 0>,
+ <&tlmm 30 0>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 1 1 1>;
+ gpio-req-tbl-label = "CCI_I2C_DATA0",
+ "CCI_I2C_CLK0",
+ "CCI_I2C_DATA1",
+ "CCI_I2C_CLK1";
+
+ i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
+ hw-thigh = <201>;
+ hw-tlow = <174>;
+ hw-tsu-sto = <204>;
+ hw-tsu-sta = <231>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <162>;
+ hw-tbuf = <227>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_custom_cci0: qcom,i2c_custom_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <1>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
+ hw-thigh = <16>;
+ hw-tlow = <22>;
+ hw-tsu-sto = <17>;
+ hw-tsu-sta = <18>;
+ hw-thd-dat = <16>;
+ hw-thd-sta = <15>;
+ hw-tbuf = <24>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <3>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+ };
+
+ qcom,cam_smmu {
+ compatible = "qcom,msm-cam-smmu";
+ status = "ok";
+
+ msm_cam_smmu_tfe {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x400 0x000>,
+ <&apps_smmu 0x401 0x000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ label = "tfe";
+ tfe_iova_mem_map: iova-mem-map {
+ /* IO region is approximately 3.4 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_ope {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x820 0x000>,
+ <&apps_smmu 0x821 0x020>,
+ <&apps_smmu 0x840 0x000>,
+ <&apps_smmu 0x841 0x000>;
+ qcom,iommu-faults = "non-fatal";
+ multiple-client-devices;
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ label = "ope", "ope-cdm0";
+ ope_iova_mem_map: iova-mem-map {
+ /* IO region is approximately 3.4 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_cpas_cdm {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x800 0x000>,
+ <&apps_smmu 0x801 0x020>;
+ label = "cpas-cdm0";
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ cpas_cdm_iova_mem_map: iova-mem-map {
+ iova-mem-region-io {
+ /* IO region is approximately 3.4 GB */
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_secure {
+ compatible = "qcom,msm-cam-smmu-cb";
+ label = "cam-secure";
+ qcom,secure-cb;
+ };
+
+ };
+
+ qcom,cam-cpas@5c11000 {
+ cell-index = <0>;
+ compatible = "qcom,cam-cpas";
+ label = "cpas";
+ arch-compat = "cpas_top";
+ status = "ok";
+ reg-names = "cam_cpas_top", "cam_camnoc";
+ reg = <0x5c11000 0x1000>,
+ <0x5c13000 0x4000>;
+ reg-cam-base = <0x11000 0x13000>;
+ interrupt-names = "cpas_camnoc";
+ interrupts = <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>;
+ camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "gcc_camss_ahb_clk",
+ "gcc_camss_top_ahb_clk",
+ "gcc_camss_top_ahb_clk_src",
+ "gcc_camss_axi_clk",
+ "gcc_camss_axi_clk_src";
+ clocks =
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>,
+ <&gcc GCC_CAMSS_AXI_CLK>,
+ <&gcc GCC_CAMSS_AXI_CLK_SRC>;
+ src-clock-name = "gcc_camss_axi_clk_src";
+ clock-rates =
+ <0 0 0 0 0>,
+ <0 80000000 80000000 19200000 19200000>,
+ <0 80000000 80000000 150000000 150000000>,
+ <0 80000000 80000000 200000000 200000000>,
+ <0 80000000 80000000 300000000 300000000>,
+ <0 80000000 80000000 300000000 300000000>,
+ <0 80000000 80000000 300000000 300000000>;
+ clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs",
+ "svs_l1", "nominal", "turbo";
+ control-camnoc-axi-clk;
+ camnoc-bus-width = <32>;
+ camnoc-axi-clk-bw-margin-perc = <20>;
+ qcom,msm-bus,name = "cam_ahb"; /*Need to verify*/
+ qcom,msm-bus,num-cases = <7>; /*Need to verify*/
+ qcom,msm-bus,num-paths = <1>; /*Need to verify*/
+ qcom,msm-bus,vectors-KBps = /*Need to verify*/
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 76800>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 76800>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 300000>;
+ vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
+ RPMH_REGULATOR_LEVEL_MIN_SVS
+ RPMH_REGULATOR_LEVEL_LOW_SVS
+ RPMH_REGULATOR_LEVEL_SVS
+ RPMH_REGULATOR_LEVEL_SVS_L1
+ RPMH_REGULATOR_LEVEL_NOM
+ RPMH_REGULATOR_LEVEL_NOM_L1
+ RPMH_REGULATOR_LEVEL_NOM_L2
+ RPMH_REGULATOR_LEVEL_TURBO
+ RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ vdd-corner-ahb-mapping = "suspend", "minsvs",
+ "lowsvs", "svs", "svs_l1",
+ "nominal", "nominal", "nominal",
+ "turbo", "turbo";
+ client-id-based;
+ client-names =
+ "csiphy0", "csiphy1", "csiphy2", "cci0",
+ "csid0", "csid1", "csid2", "tfe0",
+ "tfe1", "tfe2", "ope0", "cam-cdm-intf0",
+ "cpas-cdm0", "ope-cdm0", "tpg0", "tpg1";
+
+ camera-bus-nodes {
+ level2-nodes {
+ level-index = <2>;
+ level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum {
+ cell-index = <0>;
+ node-name = "level2-rt0-rd-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_hf_0";
+ ib-bw-voting-needed;
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_hf_0_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_HF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_HF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+ };
+
+ level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum {
+ cell-index = <1>;
+ node-name = "level2-nrt0-rd-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_sf_0";
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_sf_0_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_SF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_SF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+ };
+ };
+
+ level1-nodes {
+ level-index = <1>;
+ camnoc-max-needed;
+ level1_rt0_wr: level1-rt0-wr {
+ cell-index = <2>;
+ node-name = "level1-rt0-wr";
+ parent-node = <&level2_rt0_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
+ };
+
+ level1_nrt0_rd_wr: level1-nrt0-rd-wr {
+ cell-index = <3>;
+ node-name = "level1-nrt0-rd-wr";
+ parent-node = <&level2_nrt0_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
+ };
+ };
+
+ level0-nodes {
+ level-index = <0>;
+ ope0_all_wr: ope0-all-wr {
+ cell-index = <4>;
+ node-name = "ope0-all-wr";
+ client-name = "ope0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level1_nrt0_rd_wr>;
+ };
+
+ ope0_all_rd: ope0-all-rd {
+ cell-index = <5>;
+ node-name = "ope0-all-rd";
+ client-name = "ope0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_rd_wr>;
+ };
+
+ tfe0_all_wr: tfe0-all-wr {
+ cell-index = <6>;
+ node-name = "tfe0-all-wr";
+ client-name = "tfe0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3
+ CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS>;
+ parent-node = <&level1_rt0_wr>;
+ };
+
+ tfe1_all_wr: tfe1-all-wr {
+ cell-index = <7>;
+ node-name = "tfe1-all-wr";
+ client-name = "tfe1";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3
+ CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS>;
+ parent-node = <&level1_rt0_wr>;
+ };
+
+ tfe2_all_wr: tfe2-all-wr {
+ cell-index = <8>;
+ node-name = "tfe2-all-wr";
+ client-name = "tfe2";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3
+ CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS>;
+ parent-node = <&level1_rt0_wr>;
+ };
+
+ cpas_cdm0_all_rd: cpas-cdm0-all-rd {
+ cell-index = <9>;
+ node-name = "cpas-cdm0-all-rd";
+ client-name = "cpas-cdm0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_rd_wr>;
+ };
+
+ ope_cdm0_all_rd: ope-cdm0-all-rd {
+ cell-index = <10>;
+ node-name = "ope-cdm0-all-rd";
+ client-name = "ope-cdm0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_rd_wr>;
+ };
+ };
+ };
+ };
+
+ qcom,cam-cdm-intf {
+ compatible = "qcom,cam-cdm-intf";
+ cell-index = <0>;
+ label = "cam-cdm-intf";
+ num-hw-cdm = <2>;
+ cdm-client-names = "vfe";
+ status = "ok";
+ };
+
+ cam_cpas_cdm: qcom,cpas-cdm0@5c23000 {
+ cell-index = <0>;
+ compatible = "qcom,cam-cpas-cdm2_0";
+ label = "cpas-cdm";
+ reg = <0x5c23000 0x400>;
+ reg-names = "cpas-cdm0";
+ reg-cam-base = <0x23000>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "cpas-cdm0";
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names = "cam_cc_cpas_top_ahb_clk";
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>;
+ clock-rates = <0>;
+ clock-cntl-level = "svs";
+ cdm-client-names = "tfe0", "tfe1", "tfe2";
+ config-fifo;
+ fifo-depths = <64 64 64 64>;
+ status = "ok";
+ };
+
+ cam_ope_cdm: qcom,ope-cdm0@5c42000 {
+ cell-index = <0>;
+ compatible = "qcom,cam-ope-cdm2_0";
+ label = "ope-cdm";
+ reg = <0x5c42000 0x400>;
+ reg-names = "ope-cdm0";
+ reg-cam-base = <0x42000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ope-cdm0";
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "ope_ahb_clk",
+ "ope_clk_src",
+ "ope_clk";
+ clocks =
+ <&gcc GCC_CAMSS_OPE_AHB_CLK>,
+ <&gcc GCC_CAMSS_OPE_CLK_SRC>,
+ <&gcc GCC_CAMSS_OPE_CLK>;
+ clock-rates = <0 0 0>,
+ <0 0 0>,
+ <0 0 0>,
+ <0 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ cdm-client-names = "ope";
+ config-fifo;
+ fifo-depths = <64 64 64 64>;
+ status = "ok";
+ };
+
+ qcom,cam-isp {
+ compatible = "qcom,cam-isp";
+ arch-compat = "tfe";
+ status = "ok";
+ };
+
+ cam_tfe_csid0: qcom,tfe_csid0@5c6e000 {
+ cell-index = <0>;
+ compatible = "qcom,csid530";
+ reg-names = "csid", "top", "camnoc";
+ reg = <0x5c6e000 0x5000>,
+ <0x5c11000 0x1000>,
+ <0x5c13000 0x4000>;
+ reg-cam-base = <0x6e000 0x11000 0x13000>;
+ interrupt-names = "csid0";
+ interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_csid_clk_src",
+ "tfe_csid_clk",
+ "cphy_rx_clk_src",
+ "tfe_cphy_rx_clk",
+ "tfe_clk_src",
+ "tfe_clk",
+ "tfe_axi_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
+ <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CLK>,
+ <&gcc GCC_CAMSS_AXI_CLK>;
+ clock-rates =
+ <240000000 240000000 0 240000000 256000000 256000000 150000000>,
+ <384000000 384000000 0 341333333 460800000 460800000 200000000>,
+ <426400000 426400000 0 384000000 576000000 576000000 300000000>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_tfe0: qcom,tfe0@5c6e000 {
+ cell-index = <0>;
+ compatible = "qcom,tfe530";
+ reg-names = "tfe0";
+ reg = <0x5c6e000 0x5000>;
+ reg-cam-base = <0x6e000>;
+ interrupt-names = "tfe0";
+ interrupts = <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_clk_src",
+ "tfe_clk",
+ "tfe_axi_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CLK>,
+ <&gcc GCC_CAMSS_AXI_CLK>;
+ clock-rates =
+ <256000000 256000000 150000000>,
+ <460800000 460800000 200000000>,
+ <576000000 576000000 300000000>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_tfe_csid1: qcom,tfe_csid1@5c75000 {
+ cell-index = <1>;
+ compatible = "qcom,csid530";
+ reg-names = "csid", "top", "camnoc";
+ reg = <0x5c75000 0x5000>,
+ <0x5c11000 0x1000>,
+ <0x5c13000 0x4000>;
+ reg-cam-base = <0x75000 0x11000 0x13000>;
+ interrupt-names = "csid1";
+ interrupts = <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_csid_clk_src",
+ "tfe_csid_clk",
+ "cphy_rx_clk_src",
+ "tfe_cphy_rx_clk",
+ "tfe_clk_src",
+ "tfe_clk",
+ "tfe_axi_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
+ <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CLK>,
+ <&gcc GCC_CAMSS_AXI_CLK>;
+ clock-rates =
+ <240000000 240000000 0 240000000 256000000 256000000 150000000>,
+ <384000000 384000000 0 341333333 460800000 460800000 200000000>,
+ <426400000 426400000 0 384000000 576000000 576000000 300000000>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_tfe1: qcom,tfe1@5c75000 {
+ cell-index = <1>;
+ compatible = "qcom,tfe530";
+ reg-names = "tfe1";
+ reg = <0x5c75000 0x5000>;
+ reg-cam-base = <0x75000>;
+ interrupt-names = "tfe1";
+ interrupts = <0 213 0>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_clk_src",
+ "tfe_clk",
+ "tfe_axi_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CLK>,
+ <&gcc GCC_CAMSS_AXI_CLK>;
+ clock-rates =
+ <256000000 256000000 150000000>,
+ <460800000 460800000 200000000>,
+ <576000000 576000000 300000000>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_tfe_csid2: qcom,tfe_csid2@5c7c000 {
+ cell-index = <2>;
+ compatible = "qcom,csid530";
+ reg-names = "csid", "top", "camnoc";
+ reg = <0x5c7c000 0x5000>,
+ <0x5c11000 0x1000>,
+ <0x5c13000 0x4000>;
+ reg-cam-base = <0x7c000 0x11000 0x13000>;
+ interrupt-names = "csid2";
+ interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_csid_clk_src",
+ "tfe_csid_clk",
+ "cphy_rx_clk_src",
+ "tfe_cphy_rx_clk",
+ "tfe_clk_src",
+ "tfe_clk",
+ "tfe_axi_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_2_CSID_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_2_CSID_CLK>,
+ <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_2_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_TFE_2_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_2_CLK>,
+ <&gcc GCC_CAMSS_AXI_CLK>;
+ clock-rates =
+ <240000000 240000000 0 240000000 256000000 256000000 150000000>,
+ <384000000 384000000 0 341333333 460800000 460800000 200000000>,
+ <426400000 426400000 0 384000000 576000000 576000000 300000000>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_tfe2: qcom,tfe2@5c7c000 {
+ cell-index = <2>;
+ compatible = "qcom,tfe530";
+ reg-names = "tfe2";
+ reg = <0x5c7c000 0x5000>;
+ reg-cam-base = <0x7c000>;
+ interrupt-names = "tfe2";
+ interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_clk_src",
+ "tfe_clk",
+ "tfe_axi_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_2_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_2_CLK>,
+ <&gcc GCC_CAMSS_AXI_CLK>;
+ clock-rates =
+ <256000000 256000000 150000000>,
+ <460800000 460800000 200000000>,
+ <576000000 576000000 300000000>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_tfe_tpg0: qcom,tpg0@5c66000 {
+ cell-index = <0>;
+ compatible = "qcom,tpgv1";
+ reg-names = "tpg0", "top";
+ reg = <0x5c66000 0x400>,
+ <0x5c11000 0x1000>;
+ reg-cam-base = <0x66000 0x11000>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "cphy_rx_clk_src",
+ "tfe_0_cphy_rx_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>;
+ clock-rates =
+ <240000000 240000000>,
+ <341333333 341333333>,
+ <384000000 384000000>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "cphy_rx_clk_src";
+ clock-control-debugfs = "false";
+ status = "ok";
+ };
+
+ cam_tfe_tpg1: qcom,tpg0@5c68000 {
+ cell-index = <1>;
+ compatible = "qcom,tpgv1";
+ reg-names = "tpg0", "top";
+ reg = <0x5c68000 0x400>,
+ <0x5c11000 0x1000>;
+ reg-cam-base = <0x68000 0x11000>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "cphy_rx_clk_src",
+ "tfe_1_cphy_rx_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>;
+ clock-rates =
+ <240000000 240000000>,
+ <341333333 341333333>,
+ <384000000 384000000>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "cphy_rx_clk_src";
+ clock-control-debugfs = "false";
+ status = "ok";
+ };
+
+ qcom,cam-ope {
+ compatible = "qcom,cam-ope";
+ compat-hw-name = "qcom,ope";
+ num-ope = <1>;
+ status = "ok";
+ };
+
+ ope: qcom,ope@0x5c42000 {
+ cell-index = <0>;
+ compatible = "qcom,ope";
+ reg =
+ <0x5c42000 0x400>,
+ <0x5c42400 0x200>,
+ <0x5c42600 0x200>,
+ <0x5c42800 0x4400>,
+ <0x5c46c00 0x190>,
+ <0x5c46d90 0x1270>;
+ reg-names =
+ "ope_cdm",
+ "ope_top",
+ "ope_qos",
+ "ope_pp",
+ "ope_bus_rd",
+ "ope_bus_wr";
+ reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ope";
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "ope_ahb_clk",
+ "ope_clk_src",
+ "ope_clk";
+ clocks =
+ <&gcc GCC_CAMSS_OPE_AHB_CLK>,
+ <&gcc GCC_CAMSS_OPE_CLK_SRC>,
+ <&gcc GCC_CAMSS_OPE_CLK>;
+ clock-rates =
+ <171428571 200000000 200000000>,
+ <171428571 266600000 266600000>,
+ <240000000 465000000 465000000>,
+ <240000000 580000000 580000000>;
+ clock-cntl-level = "svs", "svs_l1", "nominal", "turbo";
+ src-clock-name = "ope_clk_src";
+ status = "ok";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/khaje-camera-sensor-idp.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/khaje-camera-sensor-idp.dtsi
new file mode 100755
index 0000000..fe31ddf
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/khaje-camera-sensor-idp.dtsi
@@ -0,0 +1,433 @@
+#include <dt-bindings/clock/qcom,gcc-khaje.h>
+#include <dt-bindings/msm/msm-camera.h>
+
+&soc {
+ cam_res_mgr_label: qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator0 {
+ cell-index = <0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ actuator_rear_aux: qcom,actuator1 {
+ cell-index = <1>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ eeprom_rear: qcom,eeprom0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_vaf-supply = <&L5P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear0_reset_suspend>;
+ gpios = <&tlmm 20 0>,
+ <&tlmm 18 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom1 {
+ cell-index = <1>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_vaf-supply = <&L5P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_rear1_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_rear1_reset_suspend>;
+ gpios = <&tlmm 21 0>,
+ <&tlmm 19 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ eeprom_front: qcom,eeprom2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_front0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_front0_reset_suspend>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 24 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rear_aux2: qcom,eeprom3 {
+ cell-index = <3>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_rear2_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_rear2_reset_suspend>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 65 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ led_flash_rear: qcom,camera-flash@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ cci-master = <1>;
+ flash-type = <CAM_FLASH_TYPE_I2C>;
+ cam_vio-supply = <&L7P>;
+ regulator-names = "cam_vio";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000>;
+ rgltr-max-voltage = <1800000>;
+ rgltr-load-current = <120000>;
+ gpio-no-mux = <0>;
+ gpio-custom1 = <0>;
+ gpio-req-tbl-num = <0>;
+ gpio-req-tbl-flags = <0>;
+ gpio-req-tbl-label = "CUSTOM_GPIO1";
+ status = "ok";
+ };
+
+ led_flash_rear_aux: qcom,camera-flash@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera-flash";
+ cci-master = <1>;
+ flash-type = <CAM_FLASH_TYPE_I2C>;
+ cam_vio-supply = <&L7P>;
+ regulator-names = "cam_vio";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000>;
+ rgltr-max-voltage = <1800000>;
+ rgltr-load-current = <120000>;
+ gpio-no-mux = <0>;
+ gpio-custom1 = <0>;
+ gpio-req-tbl-num = <0>;
+ gpio-req-tbl-flags = <0>;
+ gpio-req-tbl-label = "CUSTOM_GPIO1";
+ status = "ok";
+ };
+
+ led_flash_rear_aux2: qcom,camera-flash@2 {
+ cell-index = <2>;
+ compatible = "qcom,camera-flash";
+ cci-master = <1>;
+ flash-type = <CAM_FLASH_TYPE_I2C>;
+ cam_vio-supply = <&L7P>;
+ regulator-names = "cam_vio";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000>;
+ rgltr-max-voltage = <1800000>;
+ rgltr-load-current = <120000>;
+ gpio-no-mux = <0>;
+ gpio-custom1 = <0>;
+ gpio-req-tbl-num = <0>;
+ gpio-req-tbl-flags = <0>;
+ gpio-req-tbl-label = "CUSTOM_GPIO1";
+ status = "ok";
+ };
+
+ /* Rear*/
+ qcom,cam-sensor0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear>;
+ led-flash-src = <&led_flash_rear>;
+ eeprom-src = <&eeprom_rear>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear0_reset_suspend>;
+ gpios = <&tlmm 20 0>,
+ <&tlmm 18 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ /*Rear Aux*/
+ qcom,cam-sensor1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear_aux>;
+ led-flash-src = <&led_flash_rear_aux>;
+ eeprom-src = <&eeprom_rear_aux>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_rear1_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_rear1_reset_suspend>;
+ gpios = <&tlmm 21 0>,
+ <&tlmm 19 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ /*Front*/
+ qcom,cam-sensor2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_front0_reset_active
+ &cam_sensor_csi_mux_oe_active
+ &cam_sensor_csi_mux_sel_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_front0_reset_suspend
+ &cam_sensor_csi_mux_oe_suspend
+ &cam_sensor_csi_mux_sel_suspend>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 24 0>,
+ <&tlmm 66 0>,
+ <&tlmm 67 0>;
+ gpio-reset = <1>;
+ gpio-custom1 = <2>;
+ gpio-custom2 = <3>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_CSIMUX_OE0",
+ "CAM_CSIMUX_SEL0";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /*Rear Aux2*/
+ qcom,cam-sensor3 {
+ cell-index = <3>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_rear_aux2>;
+ eeprom-src = <&eeprom_rear_aux2>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_rear2_reset_active
+ &cam_sensor_csi_mux_oe_active
+ &cam_sensor_csi_mux_sel_active>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_rear2_reset_suspend
+ &cam_sensor_csi_mux_oe_suspend
+ &cam_sensor_csi_mux_sel_suspend>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 65 0>,
+ <&tlmm 66 0>,
+ <&tlmm 67 0>;
+ gpio-reset = <1>;
+ gpio-custom1 = <2>;
+ gpio-custom2 = <3>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3",
+ "CAM_CSIMUX_OE1",
+ "CAM_CSIMUX_SEL1";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/khaje-camera-sensor-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/khaje-camera-sensor-qrd.dtsi
new file mode 100755
index 0000000..fe31ddf
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/khaje-camera-sensor-qrd.dtsi
@@ -0,0 +1,433 @@
+#include <dt-bindings/clock/qcom,gcc-khaje.h>
+#include <dt-bindings/msm/msm-camera.h>
+
+&soc {
+ cam_res_mgr_label: qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator0 {
+ cell-index = <0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ actuator_rear_aux: qcom,actuator1 {
+ cell-index = <1>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ eeprom_rear: qcom,eeprom0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_vaf-supply = <&L5P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear0_reset_suspend>;
+ gpios = <&tlmm 20 0>,
+ <&tlmm 18 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom1 {
+ cell-index = <1>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_vaf-supply = <&L5P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_rear1_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_rear1_reset_suspend>;
+ gpios = <&tlmm 21 0>,
+ <&tlmm 19 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ eeprom_front: qcom,eeprom2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_front0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_front0_reset_suspend>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 24 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rear_aux2: qcom,eeprom3 {
+ cell-index = <3>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_rear2_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_rear2_reset_suspend>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 65 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ led_flash_rear: qcom,camera-flash@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ cci-master = <1>;
+ flash-type = <CAM_FLASH_TYPE_I2C>;
+ cam_vio-supply = <&L7P>;
+ regulator-names = "cam_vio";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000>;
+ rgltr-max-voltage = <1800000>;
+ rgltr-load-current = <120000>;
+ gpio-no-mux = <0>;
+ gpio-custom1 = <0>;
+ gpio-req-tbl-num = <0>;
+ gpio-req-tbl-flags = <0>;
+ gpio-req-tbl-label = "CUSTOM_GPIO1";
+ status = "ok";
+ };
+
+ led_flash_rear_aux: qcom,camera-flash@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera-flash";
+ cci-master = <1>;
+ flash-type = <CAM_FLASH_TYPE_I2C>;
+ cam_vio-supply = <&L7P>;
+ regulator-names = "cam_vio";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000>;
+ rgltr-max-voltage = <1800000>;
+ rgltr-load-current = <120000>;
+ gpio-no-mux = <0>;
+ gpio-custom1 = <0>;
+ gpio-req-tbl-num = <0>;
+ gpio-req-tbl-flags = <0>;
+ gpio-req-tbl-label = "CUSTOM_GPIO1";
+ status = "ok";
+ };
+
+ led_flash_rear_aux2: qcom,camera-flash@2 {
+ cell-index = <2>;
+ compatible = "qcom,camera-flash";
+ cci-master = <1>;
+ flash-type = <CAM_FLASH_TYPE_I2C>;
+ cam_vio-supply = <&L7P>;
+ regulator-names = "cam_vio";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000>;
+ rgltr-max-voltage = <1800000>;
+ rgltr-load-current = <120000>;
+ gpio-no-mux = <0>;
+ gpio-custom1 = <0>;
+ gpio-req-tbl-num = <0>;
+ gpio-req-tbl-flags = <0>;
+ gpio-req-tbl-label = "CUSTOM_GPIO1";
+ status = "ok";
+ };
+
+ /* Rear*/
+ qcom,cam-sensor0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear>;
+ led-flash-src = <&led_flash_rear>;
+ eeprom-src = <&eeprom_rear>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear0_reset_suspend>;
+ gpios = <&tlmm 20 0>,
+ <&tlmm 18 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ /*Rear Aux*/
+ qcom,cam-sensor1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear_aux>;
+ led-flash-src = <&led_flash_rear_aux>;
+ eeprom-src = <&eeprom_rear_aux>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_rear1_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_rear1_reset_suspend>;
+ gpios = <&tlmm 21 0>,
+ <&tlmm 19 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ /*Front*/
+ qcom,cam-sensor2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_front0_reset_active
+ &cam_sensor_csi_mux_oe_active
+ &cam_sensor_csi_mux_sel_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_front0_reset_suspend
+ &cam_sensor_csi_mux_oe_suspend
+ &cam_sensor_csi_mux_sel_suspend>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 24 0>,
+ <&tlmm 66 0>,
+ <&tlmm 67 0>;
+ gpio-reset = <1>;
+ gpio-custom1 = <2>;
+ gpio-custom2 = <3>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_CSIMUX_OE0",
+ "CAM_CSIMUX_SEL0";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /*Rear Aux2*/
+ qcom,cam-sensor3 {
+ cell-index = <3>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_rear_aux2>;
+ eeprom-src = <&eeprom_rear_aux2>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_rear2_reset_active
+ &cam_sensor_csi_mux_oe_active
+ &cam_sensor_csi_mux_sel_active>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_rear2_reset_suspend
+ &cam_sensor_csi_mux_oe_suspend
+ &cam_sensor_csi_mux_sel_suspend>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 65 0>,
+ <&tlmm 66 0>,
+ <&tlmm 67 0>;
+ gpio-reset = <1>;
+ gpio-custom1 = <2>;
+ gpio-custom2 = <3>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3",
+ "CAM_CSIMUX_OE1",
+ "CAM_CSIMUX_SEL1";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/khaje-camera.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/khaje-camera.dtsi
new file mode 100755
index 0000000..fa73692
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/khaje-camera.dtsi
@@ -0,0 +1,935 @@
+#include <dt-bindings/msm/msm-camera.h>
+
+&soc {
+ qcom,cam-req-mgr {
+ compatible = "qcom,cam-req-mgr";
+ status = "ok";
+ };
+
+ cam_csiphy0: qcom,csiphy0 {
+ cell-index = <0>;
+ compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
+ reg = <0x05C52000 0x2000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x52000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr", "mipi-csi-vdd1",
+ "mipi-csi-vdd2";
+ gdscr-supply = <&gcc_camss_top_gdsc>;
+ mipi-csi-vdd1-supply = <&L4A>;
+ mipi-csi-vdd2-supply = <&L18A>;
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <0 880000 1200000>;
+ rgltr-max-voltage = <0 1050000 1300000>;
+ rgltr-load-current = <0 0 15900 9000>;
+ clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_CPHY_0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy0_clk",
+ "csi0phytimer_clk_src",
+ "csi0phytimer_clk";
+ src-clock-name = "csi0phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ clock-rates =
+ <19200000 0 19200000 0>,
+ <256000000 0 300000000 0>,
+ <384000000 0 300000000 0>,
+ <384000000 0 30000000 0>;
+ qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
+ status = "ok";
+ };
+
+ cam_csiphy1: qcom,csiphy1 {
+ cell-index = <1>;
+ compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
+ reg = <0x05C54000 0x2000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x54000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr", "mipi-csi-vdd1",
+ "mipi-csi-vdd2";
+ gdscr-supply = <&gcc_camss_top_gdsc>;
+ mipi-csi-vdd1-supply = <&L4A>;
+ mipi-csi-vdd2-supply = <&L18A>;
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <0 880000 1200000>;
+ rgltr-max-voltage = <0 1050000 1300000>;
+ rgltr-load-current = <0 0 15900 9000>;
+ clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_CPHY_1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy1_clk",
+ "csi1phytimer_clk_src",
+ "csi1phytimer_clk";
+ src-clock-name = "csi1phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ clock-rates =
+ <19200000 0 19200000 0>,
+ <256000000 0 300000000 0>,
+ <384000000 0 300000000 0>,
+ <384000000 0 30000000 0>;
+ qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
+ status = "ok";
+ };
+
+ cam_csiphy2: qcom,csiphy2 {
+ cell-index = <2>;
+ compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
+ reg = <0x05C56000 0x2000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x56000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr", "mipi-csi-vdd1",
+ "mipi-csi-vdd2";
+ gdscr-supply = <&gcc_camss_top_gdsc>;
+ mipi-csi-vdd1-supply = <&L4A>;
+ mipi-csi-vdd2-supply = <&L18A>;
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <0 880000 1200000>;
+ rgltr-max-voltage = <0 1050000 1300000>;
+ rgltr-load-current = <0 0 15900 9000>;
+ clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_CPHY_2_CLK>,
+ <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI2PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy2_clk",
+ "csi2phytimer_clk_src",
+ "csi2phytimer_clk";
+ src-clock-name = "csi2phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ clock-rates =
+ <19200000 0 19200000 0>,
+ <256000000 0 300000000 0>,
+ <384000000 0 300000000 0>,
+ <384000000 0 30000000 0>;
+ qcom,cam-cx-ipeak = <&cx_ipeak_lm 8>;
+ status = "ok";
+ };
+
+ cam_cci0: qcom,cci0 {
+ cell-index = <0>;
+ compatible = "qcom,cci-v1.2", "qcom,cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x05C1B000 0x1000>;
+ reg-names = "cci";
+ reg-cam-base = <0x1B000>;
+ interrupt-names = "cci";
+ interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
+ status = "ok";
+ gdscr-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "gdscr";
+ clocks = <&gcc GCC_CAMSS_CCI_0_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK_SRC>;
+ clock-names = "cci_0_clk",
+ "cci_0_clk_src";
+ src-clock-name = "cci_0_clk_src";
+ clock-cntl-level = "svs";
+ clock-rates = <0 37500000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cci0_active &cci1_active>;
+ pinctrl-1 = <&cci0_suspend &cci1_suspend>;
+ gpios = <&tlmm 22 0>,
+ <&tlmm 23 0>,
+ <&tlmm 29 0>,
+ <&tlmm 30 0>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 1 1 1>;
+ gpio-req-tbl-label = "CCI_I2C_DATA0",
+ "CCI_I2C_CLK0",
+ "CCI_I2C_DATA1",
+ "CCI_I2C_CLK1";
+
+ i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
+ hw-thigh = <201>;
+ hw-tlow = <174>;
+ hw-tsu-sto = <204>;
+ hw-tsu-sta = <231>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <162>;
+ hw-tbuf = <227>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_custom_cci0: qcom,i2c_custom_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <1>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
+ hw-thigh = <16>;
+ hw-tlow = <22>;
+ hw-tsu-sto = <17>;
+ hw-tsu-sta = <18>;
+ hw-thd-dat = <16>;
+ hw-thd-sta = <15>;
+ hw-tbuf = <24>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <3>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+ };
+
+ qcom,cam_smmu {
+ compatible = "qcom,msm-cam-smmu";
+ status = "ok";
+
+ msm_cam_smmu_tfe {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x400 0x000>;
+ qcom,iommu-faults = "fatal";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ label = "tfe";
+ tfe_iova_mem_map: iova-mem-map {
+ /* IO region is approximately 3.4 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_ope {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x820 0x000>,
+ <&apps_smmu 0x840 0x000>;
+ qcom,iommu-faults = "fatal";
+ multiple-client-devices;
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ label = "ope", "ope-cdm0";
+ ope_iova_mem_map: iova-mem-map {
+ /* IO region is approximately 3.4 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_cpas_cdm {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x800 0x000>;
+ label = "cpas-cdm0";
+ qcom,iommu-faults = "fatal";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ cpas_cdm_iova_mem_map: iova-mem-map {
+ iova-mem-region-io {
+ /* IO region is approximately 3.4 GB */
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_secure {
+ compatible = "qcom,msm-cam-smmu-cb";
+ label = "cam-secure";
+ qcom,secure-cb;
+ };
+
+ };
+
+ qcom,cam-cpas@5c11000 {
+ cell-index = <0>;
+ compatible = "qcom,cam-cpas";
+ label = "cpas";
+ arch-compat = "cpas_top";
+ status = "ok";
+ reg-names = "cam_cpas_top", "cam_camnoc";
+ reg = <0x5c11000 0x1000>,
+ <0x5c13000 0x5800>;
+ reg-cam-base = <0x11000 0x13000>;
+ custom-id = <518>;
+ interrupt-names = "cpas_camnoc";
+ interrupts = <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>;
+ camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "gcc_camss_ahb_clk",
+ "gcc_camss_top_ahb_clk",
+ "gcc_camss_top_ahb_clk_src",
+ "gcc_camss_axi_clk",
+ "gcc_camss_axi_clk_src",
+ "gcc_camss_nrt_axi_clk",
+ "gcc_camss_rt_axi_clk";
+ clocks =
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>,
+ <&gcc GCC_CAMSS_AXI_CLK>,
+ <&gcc GCC_CAMSS_AXI_CLK_SRC>,
+ <&gcc GCC_CAMSS_NRT_AXI_CLK>,
+ <&gcc GCC_CAMSS_RT_AXI_CLK>;
+ src-clock-name = "gcc_camss_axi_clk_src";
+ clock-rates =
+ <0 0 0 0 0 0 0>,
+ <0 0 80000000 0 19200000 0 0>,
+ <0 0 80000000 0 150000000 0 0>,
+ <0 0 80000000 0 240000000 0 0>,
+ <0 0 80000000 0 300000000 0 0>,
+ <0 0 80000000 0 300000000 0 0>;
+ clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs",
+ "nominal", "turbo";
+ control-camnoc-axi-clk;
+ camnoc-bus-width = <32>;
+ camnoc-axi-clk-bw-margin-perc = <20>;
+ qcom,msm-bus,name = "cam_ahb";
+ qcom,msm-bus,num-cases = <7>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 133333>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 133333>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 300000>;
+ vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
+ RPMH_REGULATOR_LEVEL_MIN_SVS
+ RPMH_REGULATOR_LEVEL_LOW_SVS
+ RPMH_REGULATOR_LEVEL_SVS
+ RPMH_REGULATOR_LEVEL_SVS_L1
+ RPMH_REGULATOR_LEVEL_NOM
+ RPMH_REGULATOR_LEVEL_NOM_L1
+ RPMH_REGULATOR_LEVEL_NOM_L2
+ RPMH_REGULATOR_LEVEL_TURBO
+ RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ vdd-corner-ahb-mapping = "suspend", "minsvs",
+ "lowsvs", "svs", "svs_l1",
+ "nominal", "nominal", "nominal",
+ "turbo", "turbo";
+ client-id-based;
+ client-names =
+ "csiphy0", "csiphy1", "csiphy2", "cci0",
+ "cci1", "csid0", "csid1", "csid2", "tfe0",
+ "tfe1", "tfe2", "ope0", "cam-cdm-intf0",
+ "cpas-cdm0", "ope-cdm0", "tpg0", "tpg1";
+
+ camera-bus-nodes {
+ level2-nodes {
+ level-index = <2>;
+ level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum {
+ cell-index = <0>;
+ node-name = "level2-rt0-rd-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_hf_0";
+ ib-bw-voting-needed;
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_hf_0_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_HF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_HF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+ };
+
+ level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum {
+ cell-index = <1>;
+ node-name = "level2-nrt0-rd-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_sf_0";
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_sf_0_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_SF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_SF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+ };
+ };
+
+ level1-nodes {
+ level-index = <1>;
+ camnoc-max-needed;
+ level1_rt0_wr: level1-rt0-wr {
+ cell-index = <2>;
+ node-name = "level1-rt0-wr";
+ parent-node = <&level2_rt0_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
+ };
+
+ level1_nrt0_rd_wr: level1-nrt0-rd-wr {
+ cell-index = <3>;
+ node-name = "level1-nrt0-rd-wr";
+ parent-node = <&level2_nrt0_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
+ };
+ };
+
+ level0-nodes {
+ level-index = <0>;
+ ope0_all_wr: ope0-all-wr {
+ cell-index = <4>;
+ node-name = "ope0-all-wr";
+ client-name = "ope0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_OPE_WR_VID
+ CAM_CPAS_PATH_DATA_OPE_WR_DISP
+ CAM_CPAS_PATH_DATA_OPE_WR_REF>;
+ parent-node = <&level1_nrt0_rd_wr>;
+ };
+
+ ope0_all_rd: ope0-all-rd {
+ cell-index = <5>;
+ node-name = "ope0-all-rd";
+ client-name = "ope0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_OPE_RD_IN
+ CAM_CPAS_PATH_DATA_OPE_RD_REF>;
+ parent-node = <&level1_nrt0_rd_wr>;
+ };
+
+ tfe0_all_wr: tfe0-all-wr {
+ cell-index = <6>;
+ node-name = "tfe0-all-wr";
+ client-name = "tfe0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3
+ CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS>;
+ parent-node = <&level1_rt0_wr>;
+ };
+
+ tfe1_all_wr: tfe1-all-wr {
+ cell-index = <7>;
+ node-name = "tfe1-all-wr";
+ client-name = "tfe1";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3
+ CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS>;
+ parent-node = <&level1_rt0_wr>;
+ };
+
+ tfe2_all_wr: tfe2-all-wr {
+ cell-index = <8>;
+ node-name = "tfe2-all-wr";
+ client-name = "tfe2";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3
+ CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS>;
+ parent-node = <&level1_rt0_wr>;
+ };
+
+ cpas_cdm0_all_rd: cpas-cdm0-all-rd {
+ cell-index = <9>;
+ node-name = "cpas-cdm0-all-rd";
+ client-name = "cpas-cdm0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_rd_wr>;
+ };
+
+ ope_cdm0_all_rd: ope-cdm0-all-rd {
+ cell-index = <10>;
+ node-name = "ope-cdm0-all-rd";
+ client-name = "ope-cdm0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_rd_wr>;
+ };
+ };
+ };
+ };
+
+ qcom,cam-cdm-intf {
+ compatible = "qcom,cam-cdm-intf";
+ cell-index = <0>;
+ label = "cam-cdm-intf";
+ num-hw-cdm = <2>;
+ cdm-client-names = "vfe";
+ status = "ok";
+ };
+
+ cam_cpas_cdm: qcom,cpas-cdm0@5c23000 {
+ cell-index = <0>;
+ compatible = "qcom,cam-cpas-cdm2_1";
+ label = "cpas-cdm";
+ reg = <0x5c23000 0x400>;
+ reg-names = "cpas-cdm0";
+ reg-cam-base = <0x23000>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "cpas-cdm0";
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names = "cam_cc_cpas_top_ahb_clk";
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>;
+ clock-rates = <0>;
+ clock-cntl-level = "svs";
+ cdm-client-names = "tfe0", "tfe1", "tfe2";
+ config-fifo;
+ fifo-depths = <64 64 64 64>;
+ status = "ok";
+ };
+
+ cam_ope_cdm: qcom,ope-cdm0@5c42000 {
+ cell-index = <0>;
+ compatible = "qcom,cam-ope-cdm2_1";
+ label = "ope-cdm";
+ reg = <0x5c42000 0x400>;
+ reg-names = "ope-cdm0";
+ reg-cam-base = <0x42000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ope-cdm0";
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "ope_ahb_clk",
+ "ope_clk_src",
+ "ope_clk";
+ clocks =
+ <&gcc GCC_CAMSS_OPE_AHB_CLK>,
+ <&gcc GCC_CAMSS_OPE_CLK_SRC>,
+ <&gcc GCC_CAMSS_OPE_CLK>;
+ clock-rates = <0 0 0>,
+ <0 0 0>,
+ <0 0 0>,
+ <0 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ cdm-client-names = "ope";
+ config-fifo;
+ fifo-depths = <64 64 64 64>;
+ status = "ok";
+ };
+
+ qcom,cam-isp {
+ compatible = "qcom,cam-isp";
+ arch-compat = "tfe";
+ status = "ok";
+ };
+
+ cam_tfe_csid0: qcom,tfe_csid0@5c6e000 {
+ cell-index = <0>;
+ compatible = "qcom,csid530";
+ reg-names = "csid", "top", "camnoc";
+ reg = <0x5c6e000 0x5000>,
+ <0x5c11000 0x1000>,
+ <0x5c13000 0x4000>;
+ reg-cam-base = <0x6e000 0x11000 0x13000>;
+ interrupt-names = "csid0";
+ interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_csid_clk_src",
+ "tfe_csid_clk",
+ "cphy_rx_clk_src",
+ "tfe_cphy_rx_clk",
+ "tfe_clk_src",
+ "tfe_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
+ <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CLK>;
+ clock-rates =
+ <266571429 0 0 0 300000000 0>,
+ <426400000 0 0 0 460800000 0>,
+ <466500000 0 0 0 576000000 0>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_csid_clk_src";
+ clock-control-debugfs = "true";
+ ppi-enable;
+ status = "ok";
+ };
+
+ cam_tfe0: qcom,tfe0@5c6e000 {
+ cell-index = <0>;
+ compatible = "qcom,tfe530";
+ reg-names = "tfe0";
+ reg = <0x5c6e000 0x5000>;
+ reg-cam-base = <0x6e000>;
+ interrupt-names = "tfe0";
+ interrupts = <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_clk_src",
+ "tfe_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CLK>;
+ clock-rates =
+ <300000000 0>,
+ <460800000 0>,
+ <576000000 0>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_tfe_csid1: qcom,tfe_csid1@5c75000 {
+ cell-index = <1>;
+ compatible = "qcom,csid530";
+ reg-names = "csid", "top", "camnoc";
+ reg = <0x5c75000 0x5000>,
+ <0x5c11000 0x1000>,
+ <0x5c13000 0x4000>;
+ reg-cam-base = <0x75000 0x11000 0x13000>;
+ interrupt-names = "csid1";
+ interrupts = <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_csid_clk_src",
+ "tfe_csid_clk",
+ "cphy_rx_clk_src",
+ "tfe_cphy_rx_clk",
+ "tfe_clk_src",
+ "tfe_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
+ <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CLK>;
+ clock-rates =
+ <266571429 0 0 0 300000000 0>,
+ <426400000 0 0 0 460800000 0>,
+ <466500000 0 0 0 576000000 0>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_csid_clk_src";
+ clock-control-debugfs = "true";
+ ppi-enable;
+ status = "ok";
+ };
+
+ cam_tfe1: qcom,tfe1@5c75000 {
+ cell-index = <1>;
+ compatible = "qcom,tfe530";
+ reg-names = "tfe1";
+ reg = <0x5c75000 0x5000>;
+ reg-cam-base = <0x75000>;
+ interrupt-names = "tfe1";
+ interrupts = <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_clk_src",
+ "tfe_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CLK>;
+ clock-rates =
+ <300000000 0>,
+ <460800000 0>,
+ <576000000 0>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_tfe_csid2: qcom,tfe_csid2@5c7c000 {
+ cell-index = <2>;
+ compatible = "qcom,csid530";
+ reg-names = "csid", "top", "camnoc";
+ reg = <0x5c7c000 0x5000>,
+ <0x5c11000 0x1000>,
+ <0x5c13000 0x4000>;
+ reg-cam-base = <0x7c000 0x11000 0x13000>;
+ interrupt-names = "csid2";
+ interrupts = <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_csid_clk_src",
+ "tfe_csid_clk",
+ "cphy_rx_clk_src",
+ "tfe_cphy_rx_clk",
+ "tfe_clk_src",
+ "tfe_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_2_CSID_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_2_CSID_CLK>,
+ <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_2_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_TFE_2_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_2_CLK>;
+ clock-rates =
+ <266571429 0 0 0 300000000 0>,
+ <426400000 0 0 0 460800000 0>,
+ <466500000 0 0 0 576000000 0>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_csid_clk_src";
+ clock-control-debugfs = "true";
+ ppi-enable;
+ status = "ok";
+ };
+
+ cam_tfe2: qcom,tfe2@5c7c000 {
+ cell-index = <2>;
+ compatible = "qcom,tfe530";
+ reg-names = "tfe2";
+ reg = <0x5c7c000 0x5000>;
+ reg-cam-base = <0x7c000>;
+ interrupt-names = "tfe2";
+ interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_clk_src",
+ "tfe_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_2_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_2_CLK>;
+ clock-rates =
+ <300000000 0>,
+ <460800000 0>,
+ <576000000 0>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_ppi0: qcom,ppi0@5cb3000 {
+ cell-index = <0>;
+ compatible = "qcom,ppi100";
+ reg-names = "ppi0";
+ reg = <0x5cb3000 0x200>;
+ reg-cam-base = <0xb3000>;
+ interrupt-names = "ppi0";
+ interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&gcc GCC_CAMSS_CPHY_0_CLK>;
+ clock-names = "gcc_camss_cphy_0_clk";
+ clock-cntl-level = "svs";
+ clock-rates = <0>;
+ status = "ok";
+ };
+
+ cam_ppi1: qcom,ppi1@5cb3200 {
+ cell-index = <1>;
+ compatible = "qcom,ppi100";
+ reg-names = "ppi1";
+ reg = <0x5cb3200 0x200>;
+ reg-cam-base = <0xb3200>;
+ interrupt-names = "ppi1";
+ interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&gcc GCC_CAMSS_CPHY_1_CLK>;
+ clock-names = "gcc_camss_cphy_1_clk";
+ clock-cntl-level = "svs";
+ clock-rates = <0>;
+ status = "ok";
+ };
+
+ cam_ppi2: qcom,ppi2@5cb3400 {
+ cell-index = <2>;
+ compatible = "qcom,ppi100";
+ reg-names = "ppi2";
+ reg = <0x5cb3400 0x200>;
+ reg-cam-base = <0xb3400>;
+ interrupt-names = "ppi2";
+ interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&gcc GCC_CAMSS_CPHY_2_CLK>;
+ clock-names = "gcc_camss_cphy_2_clk";
+ clock-cntl-level = "svs";
+ clock-rates = <0>;
+ status = "ok";
+ };
+
+ cam_tfe_tpg0: qcom,tpg0@5c66000 {
+ cell-index = <0>;
+ compatible = "qcom,tpgv1";
+ reg-names = "tpg0", "top";
+ reg = <0x5c66000 0x400>,
+ <0x5c11000 0x1000>;
+ reg-cam-base = <0x66000 0x11000>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "cphy_rx_clk_src",
+ "tfe_0_cphy_rx_clk",
+ "gcc_camss_cphy_0_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_CPHY_0_CLK>;
+ clock-rates =
+ <256000000 0 0>,
+ <384000000 0 0>,
+ <384000000 0 0>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "cphy_rx_clk_src";
+ clock-control-debugfs = "false";
+ status = "ok";
+ };
+
+ cam_tfe_tpg1: qcom,tpg0@5c68000 {
+ cell-index = <1>;
+ compatible = "qcom,tpgv1";
+ reg-names = "tpg1", "top";
+ reg = <0x5c68000 0x400>,
+ <0x5c11000 0x1000>;
+ reg-cam-base = <0x68000 0x11000>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "cphy_rx_clk_src",
+ "tfe_1_cphy_rx_clk",
+ "gcc_camss_cphy_1_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_CPHY_1_CLK>;
+ clock-rates =
+ <256000000 0 0>,
+ <384000000 0 0>,
+ <384000000 0 0>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "cphy_rx_clk_src";
+ clock-control-debugfs = "false";
+ status = "ok";
+ };
+
+ qcom,cam-ope {
+ compatible = "qcom,cam-ope";
+ compat-hw-name = "qcom,ope";
+ num-ope = <1>;
+ status = "ok";
+ };
+
+ ope: qcom,ope@0x5c42000 {
+ cell-index = <0>;
+ compatible = "qcom,ope";
+ reg =
+ <0x5c42000 0x400>,
+ <0x5c42400 0x200>,
+ <0x5c42600 0x200>,
+ <0x5c42800 0x4400>,
+ <0x5c46c00 0x190>,
+ <0x5c46d90 0xA00>;
+ reg-names =
+ "ope_cdm",
+ "ope_top",
+ "ope_qos",
+ "ope_pp",
+ "ope_bus_rd",
+ "ope_bus_wr";
+ reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ope";
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "ope_ahb_clk",
+ "ope_clk_src",
+ "ope_clk";
+ clocks =
+ <&gcc GCC_CAMSS_OPE_AHB_CLK>,
+ <&gcc GCC_CAMSS_OPE_CLK_SRC>,
+ <&gcc GCC_CAMSS_OPE_CLK>;
+ clock-rates =
+ <171428571 200000000 0>,
+ <171428571 266600000 0>,
+ <240000000 480000000 0>,
+ <240000000 580000000 0>;
+ clock-cntl-level = "svs", "svs_l1", "nominal", "turbo";
+ src-clock-name = "ope_clk_src";
+ status = "ok";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-arglass.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-arglass.dtsi
new file mode 100755
index 0000000..9081ef0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-arglass.dtsi
@@ -0,0 +1,746 @@
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+
+&soc {
+ led_flash_rear: qcom,camera-flash@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ led_flash_rear_aux: qcom,camera-flash@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ led_flash_eye_track: qcom,camera-flash@2 {
+ cell-index = <2>;
+ compatible = "qcom,camera-flash";
+ gpios = <&tlmm 22 0>,
+ <&tlmm 23 0>,
+ <&tlmm 24 0>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <0 0 0>;
+ gpio-req-tbl-label = "TCKING_LED_1V2_EN",
+ "TCKING_LED_3V3_EN",
+ "TCKING_LED_EN";
+ gpio-req-tbl-delay = <20 20 20>;
+ status = "ok";
+ };
+
+ led_flash_hand_track: qcom,camera-flash@3 {
+ cell-index = <3>;
+ compatible = "qcom,camera-flash";
+ gpios = <&tlmm 118 0>;
+ gpio-req-tbl-num = <0>;
+ gpio-req-tbl-flags = <0>;
+ gpio-req-tbl-label = "HNDTCKING_LED_EN";
+ gpio-req-tbl-delay = <20>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear: qcom,camera-flash@4 {
+ cell-index = <4>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ led_flash_triple_rear_aux: qcom,camera-flash@5 {
+ cell-index = <5>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ led_flash_triple_rear_aux2: qcom,camera-flash@6 {
+ cell-index = <6>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ shared-gpios = <1141>;
+ pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend";
+ pinctrl-0 = <&cam_sensor_6dof_vio_active>;
+ pinctrl-1 = <&cam_sensor_6dof_vio_suspend>;
+ };
+
+ cam_csid_lite2: qcom,csid-lite2@acdd600 {
+ cell-index = <4>;
+ compatible = "qcom,csid-lite480";
+ reg-names = "csid-lite";
+ reg = <0xacdd600 0x1000>;
+ reg-cam-base = <0xdd600>;
+ interrupt-names = "csid-lite";
+ interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_lite_ahb",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <400000000 0 0 0 400000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_vfe_lite2: qcom,ife-lite2@acdd400 {
+ cell-index = <4>;
+ compatible = "qcom,vfe-lite480";
+ reg-names = "ife-lite";
+ reg = <0xacdd400 0x2200>;
+ reg-cam-base = <0xdd400>;
+ interrupt-names = "ife-lite";
+ interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_lite_ahb",
+ "ife_lite_axi",
+ "ife_clk_src",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <0 0 400000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_csid_lite3: qcom,csid-lite3@acdf800 {
+ cell-index = <5>;
+ compatible = "qcom,csid-lite480";
+ reg-names = "csid-lite";
+ reg = <0xacdf800 0x1000>;
+ reg-cam-base = <0xdf800>;
+ interrupt-names = "csid-lite";
+ interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_lite_ahb",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <400000000 0 0 0 400000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_vfe_lite3: qcom,ife-lite3@acdf600 {
+ cell-index = <5>;
+ compatible = "qcom,vfe-lite480";
+ reg-names = "ife-lite";
+ reg = <0xacdf600 0x2200>;
+ reg-cam-base = <0xdf600>;
+ interrupt-names = "ife-lite";
+ interrupts = <GIC_SPI 450 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_lite_ahb",
+ "ife_lite_axi",
+ "ife_clk_src",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <0 0 400000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_csid_lite4: qcom,csid-lite4@ace1a00 {
+ cell-index = <6>;
+ compatible = "qcom,csid-lite480";
+ reg-names = "csid-lite";
+ reg = <0xace1a00 0x1000>;
+ reg-cam-base = <0xe1a00>;
+ interrupt-names = "csid-lite";
+ interrupts = <GIC_SPI 453 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_lite_ahb",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <400000000 0 0 0 400000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_vfe_lite4: qcom,ife-lite4@ace1800 {
+ cell-index = <6>;
+ compatible = "qcom,vfe-lite480";
+ reg-names = "ife-lite";
+ reg = <0xace1800 0x2200>;
+ reg-cam-base = <0xe1800>;
+ interrupt-names = "ife-lite";
+ interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_lite_ahb",
+ "ife_lite_axi",
+ "ife_clk_src",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <0 0 400000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator0 {
+ cell-index = <0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_rear_aux: qcom,actuator1 {
+ cell-index = <1>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_wide: qcom,actuator4 {
+ cell-index = <4>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_tele: qcom,actuator5 {
+ cell-index = <5>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ eeprom_rear: qcom,eeprom0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom1 {
+ cell-index = <1>;
+ compatible = "qcom,eeprom";
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_wide: qcom,eeprom4 {
+ cell-index = <4>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_tele: qcom,eeprom5 {
+ cell-index = <5>;
+ compatible = "qcom,eeprom";
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* 6DOF Left */
+ qcom,cam-sensor0 {
+ cell-index = <3>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_hand_track>;
+ cam_vio-supply = <&pm8150a_l1>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8150a_l9>;
+ cam_vdig-supply = <&pm8150a_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <6000000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk5_active
+ &cam_sensor_active_6dofleft>;
+ pinctrl-1 = <&cam_sensor_mclk5_suspend
+ &cam_sensor_suspend_6dofleft>;
+ gpios = <&tlmm 99 0>,
+ <&tlmm 130 0>,
+ <&tlmm 41 0>;
+ gpio-reset = <1>;
+ gpio-vio = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK5",
+ "CAM_RESET5",
+ "CAM_VIO5";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK5_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* 6DOF Right */
+ qcom,cam-sensor1 {
+ cell-index = <4>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ cam_vio-supply = <&pm8150a_l1>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8150a_l9>;
+ cam_vdig-supply = <&pm8150a_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <6000000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk4_active
+ &cam_sensor_active_6dofright>;
+ pinctrl-1 = <&cam_sensor_mclk4_suspend
+ &cam_sensor_suspend_6dofright>;
+ gpios = <&tlmm 98 0>,
+ <&tlmm 131 0>,
+ <&tlmm 41 0>;
+ gpio-reset = <1>;
+ gpio-vio = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK4",
+ "CAM_RESET4",
+ "CAM_VIO4";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK4_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
+&cam_cci1 {
+ actuator_triple_uw: qcom,actuator6 {
+ cell-index = <6>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ eeprom_front: qcom,eeprom2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_uw: qcom,eeprom6 {
+ cell-index = <6>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_tof: qcom,eeprom3 {
+ cell-index = <3>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vdig-supply = <&vreg_tof>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <0 3600000 0>;
+ rgltr-max-voltage = <0 3600000 0>;
+ rgltr-load-current = <180000 120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_3>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_3>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 109 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* RGB */
+ qcom,cam-sensor2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&pm8150a_l5>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8150a_l4>;
+ cam_vdig-supply = <&pm8150a_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <600000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rgbleft>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rgbleft>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>,
+ <&tlmm 115 0>;
+ gpio-reset = <1>;
+ gpio-vio = <2>;
+ gpio-req-tbl-num = <0 1 2 >;
+ gpio-req-tbl-flags = <1 0 0 >;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_VIO2";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-cdp.dtsi
new file mode 100755
index 0000000..38cf6a0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-cdp.dtsi
@@ -0,0 +1,674 @@
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+
+&soc {
+ led_flash_rear: qcom,camera-flash0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_rear_aux: qcom,camera-flash1 {
+ cell-index = <1>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear: qcom,camera-flash@4 {
+ cell-index = <4>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear_aux: qcom,camera-flash@5 {
+ cell-index = <5>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear_aux2: qcom,camera-flash@6 {
+ cell-index = <6>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator0 {
+ cell-index = <0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_rear_aux: qcom,actuator1 {
+ cell-index = <1>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_wide: qcom,actuator4 {
+ cell-index = <4>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_tele: qcom,actuator5 {
+ cell-index = <5>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ eeprom_rear: qcom,eeprom0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom1 {
+ cell-index = <1>;
+ compatible = "qcom,eeprom";
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_wide: qcom,eeprom4 {
+ cell-index = <4>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_tele: qcom,eeprom5 {
+ cell-index = <5>;
+ compatible = "qcom,eeprom";
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear>;
+ led-flash-src = <&led_flash_rear>;
+ eeprom-src = <&eeprom_rear>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_rear_aux>;
+ led-flash-src = <&led_flash_rear_aux>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor4 {
+ cell-index = <4>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_triple_wide>;
+ led-flash-src = <&led_flash_triple_rear>;
+ eeprom-src = <&eeprom_triple_wide>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor5 {
+ cell-index = <5>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_triple_tele>;
+ actuator-src = <&actuator_triple_tele>;
+ led-flash-src = <&led_flash_triple_rear_aux>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
+&cam_cci1 {
+ actuator_triple_uw: qcom,actuator6 {
+ cell-index = <6>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ eeprom_front: qcom,eeprom2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <0 2800000 1056000 0 2856000>;
+ rgltr-max-voltage = <0 3000000 1056000 0 3104000>;
+ rgltr-load-current = <0 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_tof: qcom,eeprom3 {
+ cell-index = <3>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vdig-supply = <&vreg_tof>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <0 3600000 0>;
+ rgltr-max-voltage = <0 3600000 0>;
+ rgltr-load-current = <180000 120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_3>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_3>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 109 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_uw: qcom,eeprom6 {
+ cell-index = <6>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor3 {
+ cell-index = <3>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <3>;
+ eeprom-src = <&eeprom_tof>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vdig-supply = <&vreg_tof>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 3600000 0>;
+ rgltr-max-voltage = <1800000 3600000 0>;
+ rgltr-load-current = <180000 120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_3>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_3>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 109 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor6 {
+ cell-index = <6>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_triple_uw>;
+ actuator-src = <&actuator_triple_uw>;
+ led-flash-src = <&led_flash_triple_rear_aux2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-mtp.dtsi
new file mode 100755
index 0000000..a1dab47
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-mtp.dtsi
@@ -0,0 +1,676 @@
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+
+&soc {
+ led_flash_rear: qcom,camera-flash0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_rear_aux: qcom,camera-flash1 {
+ cell-index = <1>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear: qcom,camera-flash@4 {
+ cell-index = <4>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear_aux: qcom,camera-flash@5 {
+ cell-index = <5>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear_aux2: qcom,camera-flash@6 {
+ cell-index = <6>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator0 {
+ cell-index = <0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_rear_aux: qcom,actuator1 {
+ cell-index = <1>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_wide: qcom,actuator4 {
+ cell-index = <4>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_tele: qcom,actuator5 {
+ cell-index = <5>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ eeprom_rear: qcom,eeprom0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom1 {
+ cell-index = <1>;
+ compatible = "qcom,eeprom";
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_wide: qcom,eeprom4 {
+ cell-index = <4>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_tele: qcom,eeprom5 {
+ cell-index = <5>;
+ compatible = "qcom,eeprom";
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear>;
+ led-flash-src = <&led_flash_rear>;
+ eeprom-src = <&eeprom_rear>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_rear_aux>;
+ led-flash-src = <&led_flash_rear_aux>;
+ actuator-src = <&actuator_rear_aux>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor4 {
+ cell-index = <4>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_triple_wide>;
+ led-flash-src = <&led_flash_triple_rear>;
+ eeprom-src = <&eeprom_triple_wide>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor5 {
+ cell-index = <5>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_triple_tele>;
+ actuator-src = <&actuator_triple_tele>;
+ led-flash-src = <&led_flash_triple_rear_aux>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
+&cam_cci1 {
+ actuator_triple_uw: qcom,actuator6 {
+ cell-index = <6>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ eeprom_front: qcom,eeprom2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_uw: qcom,eeprom6 {
+ cell-index = <6>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_tof: qcom,eeprom3 {
+ cell-index = <3>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vdig-supply = <&vreg_tof>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <0 3600000 0>;
+ rgltr-max-voltage = <0 3600000 0>;
+ rgltr-load-current = <180000 120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_3>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_3>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 109 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor3 {
+ cell-index = <3>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <3>;
+ eeprom-src = <&eeprom_tof>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vdig-supply = <&vreg_tof>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 3600000 0>;
+ rgltr-max-voltage = <1800000 3600000 0>;
+ rgltr-load-current = <180000 120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_3>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_3>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 109 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor6 {
+ cell-index = <6>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_triple_uw>;
+ actuator-src = <&actuator_triple_uw>;
+ led-flash-src = <&led_flash_triple_rear_aux2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-qrd.dtsi
new file mode 100755
index 0000000..9e69a98
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-qrd.dtsi
@@ -0,0 +1,674 @@
+&soc {
+ led_flash_rear: qcom,camera-flash0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_rear_aux: qcom,camera-flash1 {
+ cell-index = <1>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear: qcom,camera-flash@4 {
+ cell-index = <4>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear_aux: qcom,camera-flash@5 {
+ cell-index = <5>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear_aux2: qcom,camera-flash@6 {
+ cell-index = <6>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator0 {
+ cell-index = <0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_rear_aux: qcom,actuator1 {
+ cell-index = <1>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_wide: qcom,actuator4 {
+ cell-index = <4>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_tele: qcom,actuator5 {
+ cell-index = <5>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_uw: qcom,actuator6 {
+ cell-index = <6>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ eeprom_rear: qcom,eeprom0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom1 {
+ cell-index = <1>;
+ compatible = "qcom,eeprom";
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_wide: qcom,eeprom4 {
+ cell-index = <4>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_tele: qcom,eeprom5 {
+ cell-index = <5>;
+ compatible = "qcom,eeprom";
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_uw: qcom,eeprom6 {
+ cell-index = <6>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear>;
+ led-flash-src = <&led_flash_rear>;
+ eeprom-src = <&eeprom_rear>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_rear_aux>;
+ led-flash-src = <&led_flash_rear_aux>;
+ actuator-src = <&actuator_rear_aux>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor4 {
+ cell-index = <4>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_triple_wide>;
+ led-flash-src = <&led_flash_triple_rear>;
+ eeprom-src = <&eeprom_triple_wide>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor5 {
+ cell-index = <5>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_triple_tele>;
+ actuator-src = <&actuator_triple_tele>;
+ led-flash-src = <&led_flash_triple_rear_aux>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor6 {
+ cell-index = <6>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_triple_uw>;
+ actuator-src = <&actuator_triple_uw>;
+ led-flash-src = <&led_flash_triple_rear_aux2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
+&cam_cci1 {
+ eeprom_front: qcom,eeprom2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_tof: qcom,eeprom3 {
+ cell-index = <3>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vdig-supply = <&vreg_tof>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <0 3600000 0>;
+ rgltr-max-voltage = <0 3600000 0>;
+ rgltr-load-current = <180000 120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_3>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_3>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 109 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor3 {
+ cell-index = <3>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <3>;
+ eeprom-src = <&eeprom_tof>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vdig-supply = <&vreg_tof>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 3600000 0>;
+ rgltr-max-voltage = <1800000 3600000 0>;
+ rgltr-load-current = <180000 120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_3>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_3>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 109 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-rb5.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-rb5.dtsi
new file mode 100755
index 0000000..2174021
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-rb5.dtsi
@@ -0,0 +1,356 @@
+&soc {
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&tlmm {
+ cam_sensor_active_gmsl: cam_sensor_active_gmsl {
+ /* RESET */
+ mux {
+ pins = "gpio99";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio99";
+ bias-pull-up;
+ drive-strength = <2>; /* 2 MA */
+ output-high;
+ };
+ };
+
+ cam_sensor_suspend_gmsl: cam_sensor_suspend_gmsl {
+ /* RESET */
+ mux {
+ pins = "gpio99";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio99";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+};
+
+&cam_cci0 {
+ qcom,cam-sensor0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 0>;
+ rgltr-max-voltage = <1800000 0>;
+ rgltr-load-current = <120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 0>;
+ rgltr-max-voltage = <1800000 0>;
+ rgltr-load-current = <120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor3 {
+ cell-index = <3>;
+ status = "disable";
+ };
+
+ qcom,cam-sensor4 {
+ cell-index = <4>;
+ status = "disable";
+ };
+
+ qcom,cam-sensor5 {
+ cell-index = <5>;
+ status = "disable";
+ };
+};
+
+&cam_cci1 {
+ eeprom_tof: qcom,eeprom3 {
+ cell-index = <3>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vdig-supply = <&pm8150_s4>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 1800000 0>;
+ rgltr-max-voltage = <1800000 1800000 0>;
+ rgltr-load-current = <120000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_3>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_3>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 144 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ qcom,cam-power-seq-type ="cam_reset","cam_vio","cam_clk","cam_reset";
+ qcom,cam-power-seq-val = "cam_reset","cam_vio"
+ ,"cam_mclk","cam_reset";
+ qcom,cam-power-seq-cfg-val = <0 1 24000000 1>;
+ qcom,cam-power-seq-delay = <1 0 1 18>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rb5_rear: qcom,eeprom0 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 0>;
+ rgltr-max-voltage = <1800000 0>;
+ rgltr-load-current = <120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_rb5_rear>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 0>;
+ rgltr-max-voltage = <1800000 0>;
+ rgltr-load-current = <120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor3 {
+ cell-index = <3>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <3>;
+ eeprom-src = <&eeprom_tof>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vdig-supply = <&pm8150_s4>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 1800000 0>;
+ rgltr-max-voltage = <1800000 1800000 0>;
+ rgltr-load-current = <120000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 144 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor4 {
+ cell-index = <4>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <4>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 0>;
+ rgltr-max-voltage = <1800000 0>;
+ rgltr-load-current = <120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_gmsl>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_gmsl>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 99 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET4";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor5 {
+ cell-index = <5>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <4>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 0>;
+ rgltr-max-voltage = <1800000 0>;
+ rgltr-load-current = <120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_gmsl>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_gmsl>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 99 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET4";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-vc.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-vc.dtsi
new file mode 100755
index 0000000..891567b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-vc.dtsi
@@ -0,0 +1,670 @@
+&soc {
+ led_flash_rear: qcom,camera-flash0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_rear_aux: qcom,camera-flash1 {
+ cell-index = <1>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear: qcom,camera-flash@4 {
+ cell-index = <4>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear_aux: qcom,camera-flash@5 {
+ cell-index = <5>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear_aux2: qcom,camera-flash@6 {
+ cell-index = <6>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "ok";
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator0 {
+ cell-index = <0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_rear_aux: qcom,actuator1 {
+ cell-index = <1>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_wide: qcom,actuator4 {
+ cell-index = <4>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_tele: qcom,actuator5 {
+ cell-index = <5>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_uw: qcom,actuator6 {
+ cell-index = <6>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ eeprom_rear: qcom,eeprom0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom1 {
+ cell-index = <1>;
+ compatible = "qcom,eeprom";
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_wide: qcom,eeprom4 {
+ cell-index = <4>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_tele: qcom,eeprom5 {
+ cell-index = <5>;
+ compatible = "qcom,eeprom";
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_uw: qcom,eeprom6 {
+ cell-index = <6>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <180>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <180>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_rear_aux>;
+ led-flash-src = <&led_flash_rear_aux>;
+ actuator-src = <&actuator_rear_aux>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor4 {
+ cell-index = <4>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_triple_wide>;
+ led-flash-src = <&led_flash_triple_rear>;
+ eeprom-src = <&eeprom_triple_wide>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor5 {
+ cell-index = <5>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_triple_tele>;
+ actuator-src = <&actuator_triple_tele>;
+ led-flash-src = <&led_flash_triple_rear_aux>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor6 {
+ cell-index = <6>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_triple_uw>;
+ actuator-src = <&actuator_triple_uw>;
+ led-flash-src = <&led_flash_triple_rear_aux2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
+&cam_cci1 {
+ eeprom_front: qcom,eeprom2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_tof: qcom,eeprom3 {
+ cell-index = <3>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vdig-supply = <&vreg_tof>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <0 3600000 0>;
+ rgltr-max-voltage = <0 3600000 0>;
+ rgltr-load-current = <180000 120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_3>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_3>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 109 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <180>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3960000>;
+ rgltr-load-current = <120000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor3 {
+ cell-index = <3>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <3>;
+ eeprom-src = <&eeprom_tof>;
+ sensor-position-roll = <0>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vdig-supply = <&vreg_tof>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 3600000 0>;
+ rgltr-max-voltage = <1800000 3600000 0>;
+ rgltr-load-current = <180000 120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_3>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_3>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 109 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xr.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xr.dtsi
new file mode 100755
index 0000000..8ca9dde
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xr.dtsi
@@ -0,0 +1,736 @@
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+
+&soc {
+ led_flash_rear: qcom,camera-flash@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ led_flash_rear_aux: qcom,camera-flash@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ led_flash_eye_track: qcom,camera-flash@2 {
+ cell-index = <2>;
+ compatible = "qcom,camera-flash";
+ gpios = <&tlmm 22 0>,
+ <&tlmm 23 0>,
+ <&tlmm 24 0>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <0 0 0>;
+ gpio-req-tbl-label = "TCKING_LED_1V2_EN",
+ "TCKING_LED_3V3_EN",
+ "TCKING_LED_EN";
+ gpio-req-tbl-delay = <20 20 20>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear: qcom,camera-flash@4 {
+ cell-index = <4>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ led_flash_triple_rear_aux: qcom,camera-flash@5 {
+ cell-index = <5>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ led_flash_triple_rear_aux2: qcom,camera-flash@6 {
+ cell-index = <6>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ shared-gpios = <1184 1183 1182 1214 1245 1217 1216 1215>;
+ pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend";
+ pinctrl-0 = <&cam_sensor_6dof_vana_active
+ &cam_sensor_6dof_vdig_active
+ &cam_sensor_6dof_vio_active
+ &cam_sensor_et_vana_active
+ &cam_sensor_et_vio_active
+ &cam_sensor_rgb_vana_active
+ &cam_sensor_rgb_vio_active
+ &cam_sensor_rgb_vdig_active>;
+ pinctrl-1 = <&cam_sensor_6dof_vana_suspend
+ &cam_sensor_6dof_vdig_suspend
+ &cam_sensor_6dof_vio_suspend
+ &cam_sensor_et_vana_suspend
+ &cam_sensor_et_vio_suspend
+ &cam_sensor_rgb_vana_suspend
+ &cam_sensor_rgb_vio_suspend
+ &cam_sensor_rgb_vdig_suspend>;
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator0 {
+ cell-index = <0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_rear_aux: qcom,actuator1 {
+ cell-index = <1>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_wide: qcom,actuator4 {
+ cell-index = <4>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_tele: qcom,actuator5 {
+ cell-index = <5>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ eeprom_rear: qcom,eeprom0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom1 {
+ cell-index = <1>;
+ compatible = "qcom,eeprom";
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_wide: qcom,eeprom4 {
+ cell-index = <4>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_tele: qcom,eeprom5 {
+ cell-index = <5>;
+ compatible = "qcom,eeprom";
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_front: qcom,eeprom2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_bob-supply = <&pm8150a_bob>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <600000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rgbleft>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rgbleft>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>,
+ <&tlmm 117 0>,
+ <&tlmm 116 0>,
+ <&tlmm 115 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-vdig = <4>;
+ gpio-req-tbl-num = <0 1 2 3 4>;
+ gpio-req-tbl-flags = <1 0 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_VANA2",
+ "CAM_VIO2",
+ "CAM_VDIG2";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* RGB Left (Master) */
+ qcom,cam-sensor2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <600000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rgbleft>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rgbleft>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>,
+ <&tlmm 117 0>,
+ <&tlmm 116 0>,
+ <&tlmm 115 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-vdig = <4>;
+ gpio-req-tbl-num = <0 1 2 3 4>;
+ gpio-req-tbl-flags = <1 0 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_VANA2",
+ "CAM_VIO2",
+ "CAM_VDIG2";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_tof: qcom,eeprom3 {
+ cell-index = <3>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_bob-supply = <&pm8150a_bob>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <600000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_rgbright>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_rgbright>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 109 0>,
+ <&tlmm 117 0>,
+ <&tlmm 116 0>,
+ <&tlmm 115 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-vdig = <4>;
+ gpio-req-tbl-num = <0 1 2 3 4>;
+ gpio-req-tbl-flags = <1 0 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3",
+ "CAM_VANA3",
+ "CAM_VIO3",
+ "CAM_VDIG3";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* RGB Right (Slave) */
+ qcom,cam-sensor3 {
+ cell-index = <3>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <3>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_tof>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <600000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_rgbright>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_rgbright>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 109 0>,
+ <&tlmm 117 0>,
+ <&tlmm 116 0>,
+ <&tlmm 115 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-vdig = <4>;
+ gpio-req-tbl-num = <0 1 2 3 4>;
+ gpio-req-tbl-flags = <1 0 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3",
+ "CAM_VANA3",
+ "CAM_VIO3",
+ "CAM_VDIG3";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* 6DOF Left (Slave) */
+ qcom,cam-sensor4 {
+ cell-index = <6>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <4>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <6000000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk4_active
+ &cam_sensor_active_6dofright>;
+ pinctrl-1 = <&cam_sensor_mclk4_suspend
+ &cam_sensor_suspend_6dofright>;
+ gpios = <&tlmm 98 0>,
+ <&tlmm 131 0>,
+ <&tlmm 84 0>,
+ <&tlmm 83 0>,
+ <&tlmm 82 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-vdig = <4>;
+ gpio-req-tbl-num = <0 1 2 3 4>;
+ gpio-req-tbl-flags = <1 0 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK4",
+ "CAM_RESET4",
+ "CAM_VANA4",
+ "CAM_VIO4",
+ "CAM_VDIG4";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK4_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* 6DOF Right (Master) */
+ qcom,cam-sensor5 {
+ cell-index = <5>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <5>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <6000000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk5_active
+ &cam_sensor_active_6dofleft>;
+ pinctrl-1 = <&cam_sensor_mclk5_suspend
+ &cam_sensor_suspend_6dofleft>;
+ gpios = <&tlmm 99 0>,
+ <&tlmm 130 0>,
+ <&tlmm 84 0>,
+ <&tlmm 83 0>,
+ <&tlmm 82 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-vdig = <4>;
+ gpio-req-tbl-num = <0 1 2 3 4>;
+ gpio-req-tbl-flags = <1 0 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK5",
+ "CAM_RESET5",
+ "CAM_VANA5",
+ "CAM_VIO5",
+ "CAM_VDIG5";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK5_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+
+};
+
+&cam_cci1 {
+ actuator_triple_uw: qcom,actuator6 {
+ cell-index = <6>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+
+ eeprom_triple_uw: qcom,eeprom6 {
+ cell-index = <6>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+
+ /* ET Left (Master) */
+ qcom,cam-sensor0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <600000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_etleft>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_etleft>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>,
+ <&tlmm 114 0>,
+ <&tlmm 145 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0",
+ "CAM_VANA0",
+ "CAM_VIO0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* ET Right (Slave) */
+ qcom,cam-sensor1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_eye_track>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <600000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_etright>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_etright>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>,
+ <&tlmm 114 0>,
+ <&tlmm 145 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1",
+ "CAM_VANA1",
+ "CAM_VIO1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xrfusion.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xrfusion.dtsi
new file mode 100755
index 0000000..2557ae7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera-sensor-xrfusion.dtsi
@@ -0,0 +1,999 @@
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+
+&soc {
+ led_flash_rear: qcom,camera-flash@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ led_flash_rear_aux: qcom,camera-flash@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ led_flash_eye_track: qcom,camera-flash@2 {
+ cell-index = <2>;
+ compatible = "qcom,camera-flash";
+ gpios = <&tlmm 22 0>,
+ <&tlmm 23 0>,
+ <&tlmm 24 0>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <0 0 0>;
+ gpio-req-tbl-label = "TCKING_LED_1V2_EN",
+ "TCKING_LED_3V3_EN",
+ "TCKING_LED_EN";
+ gpio-req-tbl-delay = <20 20 20>;
+ status = "ok";
+ };
+
+ led_flash_hand_track: qcom,camera-flash@3 {
+ cell-index = <3>;
+ compatible = "qcom,camera-flash";
+ gpios = <&tlmm 118 0>;
+ gpio-req-tbl-num = <0>;
+ gpio-req-tbl-flags = <0>;
+ gpio-req-tbl-label = "HNDTCKING_LED_EN";
+ gpio-req-tbl-delay = <20>;
+ status = "ok";
+ };
+
+ led_flash_triple_rear: qcom,camera-flash@4 {
+ cell-index = <4>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ led_flash_triple_rear_aux: qcom,camera-flash@5 {
+ cell-index = <5>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ led_flash_triple_rear_aux2: qcom,camera-flash@6 {
+ cell-index = <6>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ status = "disabled";
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ shared-gpios = <1143 1142 1141 1214 1245 1217 1216 1215>;
+ pinctrl-names = "cam_res_mgr_default", "cam_res_mgr_suspend";
+ pinctrl-0 = <&cam_sensor_6dof_vana_active
+ &cam_sensor_6dof_vdig_active
+ &cam_sensor_6dof_vio_active
+ &cam_sensor_et_vana_active
+ &cam_sensor_et_vio_active
+ &cam_sensor_rgb_vana_active
+ &cam_sensor_rgb_vio_active
+ &cam_sensor_rgb_vdig_active>;
+ pinctrl-1 = <&cam_sensor_6dof_vana_suspend
+ &cam_sensor_6dof_vdig_suspend
+ &cam_sensor_6dof_vio_suspend
+ &cam_sensor_et_vana_suspend
+ &cam_sensor_et_vio_suspend
+ &cam_sensor_rgb_vana_suspend
+ &cam_sensor_rgb_vio_suspend
+ &cam_sensor_rgb_vdig_suspend>;
+ };
+
+ cam_csid_lite2: qcom,csid-lite2@acdd600 {
+ cell-index = <4>;
+ compatible = "qcom,csid-lite480";
+ reg-names = "csid-lite";
+ reg = <0xacdd600 0x1000>;
+ reg-cam-base = <0xdd600>;
+ interrupt-names = "csid-lite";
+ interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_lite_ahb",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <400000000 0 0 0 400000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_vfe_lite2: qcom,ife-lite2@acdd400 {
+ cell-index = <4>;
+ compatible = "qcom,vfe-lite480";
+ reg-names = "ife-lite";
+ reg = <0xacdd400 0x2200>;
+ reg-cam-base = <0xdd400>;
+ interrupt-names = "ife-lite";
+ interrupts = <GIC_SPI 266 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_lite_ahb",
+ "ife_lite_axi",
+ "ife_clk_src",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <0 0 400000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_csid_lite3: qcom,csid-lite3@acdf800 {
+ cell-index = <5>;
+ compatible = "qcom,csid-lite480";
+ reg-names = "csid-lite";
+ reg = <0xacdf800 0x1000>;
+ reg-cam-base = <0xdf800>;
+ interrupt-names = "csid-lite";
+ interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_lite_ahb",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <400000000 0 0 0 400000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_vfe_lite3: qcom,ife-lite3@acdf600 {
+ cell-index = <5>;
+ compatible = "qcom,vfe-lite480";
+ reg-names = "ife-lite";
+ reg = <0xacdf600 0x2200>;
+ reg-cam-base = <0xdf600>;
+ interrupt-names = "ife-lite";
+ interrupts = <GIC_SPI 450 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_lite_ahb",
+ "ife_lite_axi",
+ "ife_clk_src",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <0 0 400000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_csid_lite4: qcom,csid-lite4@ace1a00 {
+ cell-index = <6>;
+ compatible = "qcom,csid-lite480";
+ reg-names = "csid-lite";
+ reg = <0xace1a00 0x1000>;
+ reg-cam-base = <0xe1a00>;
+ interrupt-names = "csid-lite";
+ interrupts = <GIC_SPI 453 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_lite_ahb",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <400000000 0 0 0 400000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_vfe_lite4: qcom,ife-lite4@ace1800 {
+ cell-index = <6>;
+ compatible = "qcom,vfe-lite480";
+ reg-names = "ife-lite";
+ reg = <0xace1800 0x2200>;
+ reg-cam-base = <0xe1800>;
+ interrupt-names = "ife-lite";
+ interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_lite_ahb",
+ "ife_lite_axi",
+ "ife_clk_src",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <0 0 400000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator0 {
+ cell-index = <0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_rear_aux: qcom,actuator1 {
+ cell-index = <1>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_wide: qcom,actuator4 {
+ cell-index = <4>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ actuator_triple_tele: qcom,actuator5 {
+ cell-index = <5>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+ eeprom_rear: qcom,eeprom0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom1 {
+ cell-index = <1>;
+ compatible = "qcom,eeprom";
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_wide: qcom,eeprom4 {
+ cell-index = <4>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l5>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_tele: qcom,eeprom5 {
+ cell-index = <5>;
+ compatible = "qcom,eeprom";
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_front: qcom,eeprom2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_bob-supply = <&pm8150a_bob>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <600000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rgbleft>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rgbleft>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>,
+ <&tlmm 117 0>,
+ <&tlmm 116 0>,
+ <&tlmm 115 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-vdig = <4>;
+ gpio-req-tbl-num = <0 1 2 3 4>;
+ gpio-req-tbl-flags = <1 0 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_VANA2",
+ "CAM_VIO2",
+ "CAM_VDIG2";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* RGB Left (Master) */
+ qcom,cam-sensor2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <600000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rgbleft>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rgbleft>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>,
+ <&tlmm 117 0>,
+ <&tlmm 116 0>,
+ <&tlmm 115 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-vdig = <4>;
+ gpio-req-tbl-num = <0 1 2 3 4>;
+ gpio-req-tbl-flags = <1 0 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_VANA2",
+ "CAM_VIO2",
+ "CAM_VDIG2";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_tof: qcom,eeprom3 {
+ cell-index = <3>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_bob-supply = <&pm8150a_bob>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <600000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_rgbright>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_rgbright>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 109 0>,
+ <&tlmm 117 0>,
+ <&tlmm 116 0>,
+ <&tlmm 115 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-vdig = <4>;
+ gpio-req-tbl-num = <0 1 2 3 4>;
+ gpio-req-tbl-flags = <1 0 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3",
+ "CAM_VANA3",
+ "CAM_VIO3",
+ "CAM_VDIG3";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* RGB Right(Slave) */
+ qcom,cam-sensor3 {
+ cell-index = <3>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <3>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ eeprom-src = <&eeprom_tof>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <600000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_rgbright>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_rgbright>;
+ gpios = <&tlmm 97 0>,
+ <&tlmm 109 0>,
+ <&tlmm 117 0>,
+ <&tlmm 116 0>,
+ <&tlmm 115 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-vdig = <4>;
+ gpio-req-tbl-num = <0 1 2 3 4>;
+ gpio-req-tbl-flags = <1 0 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3",
+ "CAM_VANA3",
+ "CAM_VIO3",
+ "CAM_VDIG3";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* 6DOF Left (Slave) */
+ qcom,cam-sensor4 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <4>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_hand_track>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <6000000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk4_active
+ &cam_sensor_active_6dofright>;
+ pinctrl-1 = <&cam_sensor_mclk4_suspend
+ &cam_sensor_suspend_6dofright>;
+ gpios = <&tlmm 98 0>,
+ <&tlmm 131 0>,
+ <&tlmm 43 0>,
+ <&tlmm 41 0>,
+ <&tlmm 42 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-vdig = <4>;
+ gpio-req-tbl-num = <0 1 2 3 4>;
+ gpio-req-tbl-flags = <1 0 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK4",
+ "CAM_RESET4",
+ "CAM_VANA4",
+ "CAM_VIO4",
+ "CAM_VDIG4";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK4_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* 6DOF Right (Master) */
+ qcom,cam-sensor5 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <5>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <6000000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk5_active
+ &cam_sensor_active_6dofleft>;
+ pinctrl-1 = <&cam_sensor_mclk5_suspend
+ &cam_sensor_suspend_6dofleft>;
+ gpios = <&tlmm 99 0>,
+ <&tlmm 130 0>,
+ <&tlmm 43 0>,
+ <&tlmm 41 0>,
+ <&tlmm 42 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-vdig = <4>;
+ gpio-req-tbl-num = <0 1 2 3 4>;
+ gpio-req-tbl-flags = <1 0 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK5",
+ "CAM_RESET5",
+ "CAM_VANA5",
+ "CAM_VIO5",
+ "CAM_VDIG5";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK5_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
+&cam_cci1 {
+ actuator_triple_uw: qcom,actuator6 {
+ cell-index = <6>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2856000>;
+ rgltr-max-voltage = <3104000>;
+ rgltr-load-current = <100000>;
+ };
+
+
+ eeprom_triple_uw: qcom,eeprom6 {
+ cell-index = <6>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l3>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&pm8150a_l7>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2856000>;
+ rgltr-max-voltage = <1800000 3000000 1056000 0 3104000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rst2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rst2>;
+ gpios = <&tlmm 96 0>,
+ <&tlmm 78 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "disabled";
+ clocks = <&clock_camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* ET Left (Master): Combo Mode */
+ qcom,cam-sensor0 {
+ cell-index = <4>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l1>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1104000 0 3960000>;
+ rgltr-load-current = <600000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_etleft>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_etleft>;
+ gpios = <&tlmm 94 0>,
+ <&tlmm 93 0>,
+ <&tlmm 114 0>,
+ <&tlmm 145 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0",
+ "CAM_VANA0",
+ "CAM_VIO0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* ET Right (Slave): Combo Mode */
+ qcom,cam-sensor1 {
+ cell-index = <5>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_eye_track>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <600000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_etright>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_etright>;
+ gpios = <&tlmm 95 0>,
+ <&tlmm 92 0>,
+ <&tlmm 114 0>,
+ <&tlmm 145 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1",
+ "CAM_VANA1",
+ "CAM_VIO1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* Face Tracking */
+ qcom,cam-sensor6 {
+ cell-index = <6>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ cam_bob-supply = <&pm8150a_bob>;
+ cam_vdig-supply = <&pm8009_l2>;
+ cam_vio-supply = <&pm8009_l7>;
+ cam_vana-supply = <&pm8009_l6>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_bob";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 3008000>;
+ rgltr-max-voltage = <1800000 3000000 1200000 0 3960000>;
+ rgltr-load-current = <6000000 80000 1200000 0 2000000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk6_active
+ &cam_sensor_active_etright>;
+ pinctrl-1 = <&cam_sensor_mclk6_suspend
+ &cam_sensor_active_etright>;
+ gpios = <&tlmm 100 0>,
+ <&tlmm 113 0>,
+ <&tlmm 51 0>,
+ <&tlmm 50 0>,
+ <&tlmm 49 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-vio = <3>;
+ gpio-vdig = <4>;
+ gpio-req-tbl-num = <0 1 2 3 4>;
+ gpio-req-tbl-flags = <1 0 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK6",
+ "CAM_RESET6",
+ "CAM_VANA6",
+ "CAM_VIO6",
+ "CAM_VDIG6";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_camcc CAM_CC_MCLK6_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera.dtsi
new file mode 100755
index 0000000..eb9b288
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/kona-camera.dtsi
@@ -0,0 +1,1754 @@
+#include <dt-bindings/msm/msm-camera.h>
+
+&soc {
+ qcom,cam-req-mgr {
+ compatible = "qcom,cam-req-mgr";
+ status = "ok";
+ };
+
+ cam_csiphy0: qcom,csiphy@ac6a000 {
+ cell-index = <0>;
+ compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
+ reg = <0x0ac6a000 0x2000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x6a000>;
+ interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ gdscr-supply = <&titan_top_gdsc>;
+ refgen-supply = <&refgen>;
+ regulator-names = "gdscr", "refgen";
+ csi-vdd-voltage = <1200000>;
+ mipi-csi-vdd-supply = <&pm8150_l9>;
+ clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSIPHY0_CLK>,
+ <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy0_clk",
+ "csi0phytimer_clk_src",
+ "csi0phytimer_clk";
+ src-clock-name = "csi0phytimer_clk_src";
+ clock-cntl-level = "turbo";
+ clock-rates =
+ <400000000 0 300000000 0>;
+ status = "ok";
+ };
+
+ cam_csiphy1: qcom,csiphy@ac6c000 {
+ cell-index = <1>;
+ compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
+ reg = <0xac6c000 0x2000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x6c000>;
+ interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ gdscr-supply = <&titan_top_gdsc>;
+ refgen-supply = <&refgen>;
+ regulator-names = "gdscr", "refgen";
+ csi-vdd-voltage = <1200000>;
+ mipi-csi-vdd-supply = <&pm8150_l9>;
+ clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSIPHY1_CLK>,
+ <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy1_clk",
+ "csi1phytimer_clk_src",
+ "csi1phytimer_clk";
+ src-clock-name = "csi1phytimer_clk_src";
+ clock-cntl-level = "turbo";
+ clock-rates =
+ <400000000 0 300000000 0>;
+
+ status = "ok";
+ };
+
+ cam_csiphy2: qcom,csiphy@ac6e000 {
+ cell-index = <2>;
+ compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
+ reg = <0xac6e000 0x2000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x6e000>;
+ interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ gdscr-supply = <&titan_top_gdsc>;
+ refgen-supply = <&refgen>;
+ regulator-names = "gdscr", "refgen";
+ csi-vdd-voltage = <1200000>;
+ mipi-csi-vdd-supply = <&pm8150_l9>;
+ clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSIPHY2_CLK>,
+ <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy2_clk",
+ "csi2phytimer_clk_src",
+ "csi2phytimer_clk";
+ src-clock-name = "csi2phytimer_clk_src";
+ clock-cntl-level = "turbo";
+ clock-rates =
+ <400000000 0 300000000 0>;
+ status = "ok";
+ };
+
+ cam_csiphy3: qcom,csiphy@ac70000 {
+ cell-index = <3>;
+ compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
+ reg = <0xac70000 0x2000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x70000>;
+ interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ gdscr-supply = <&titan_top_gdsc>;
+ refgen-supply = <&refgen>;
+ regulator-names = "gdscr", "refgen";
+ csi-vdd-voltage = <1200000>;
+ mipi-csi-vdd-supply = <&pm8150_l9>;
+ clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSIPHY3_CLK>,
+ <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy3_clk",
+ "csi3phytimer_clk_src",
+ "csi3phytimer_clk";
+ src-clock-name = "csi3phytimer_clk_src";
+ clock-cntl-level = "turbo";
+ clock-rates =
+ <400000000 0 300000000 0>;
+ status = "ok";
+ };
+
+ cam_csiphy4: qcom,csiphy@ac72000 {
+ cell-index = <4>;
+ compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
+ reg = <0xac72000 0x2000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x72000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ gdscr-supply = <&titan_top_gdsc>;
+ refgen-supply = <&refgen>;
+ regulator-names = "gdscr", "refgen";
+ csi-vdd-voltage = <1200000>;
+ mipi-csi-vdd-supply = <&pm8150_l9>;
+ clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSIPHY4_CLK>,
+ <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy4_clk",
+ "csi4phytimer_clk_src",
+ "csi4phytimer_clk";
+ src-clock-name = "csi4phytimer_clk_src";
+ clock-cntl-level = "turbo";
+ clock-rates =
+ <400000000 0 300000000 0>;
+ status = "ok";
+ };
+
+ cam_csiphy5: qcom,csiphy@ac74000 {
+ cell-index = <5>;
+ compatible = "qcom,csiphy-v1.2.1", "qcom,csiphy";
+ reg = <0xac74000 0x2000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x74000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ gdscr-supply = <&titan_top_gdsc>;
+ refgen-supply = <&refgen>;
+ regulator-names = "gdscr", "refgen";
+ csi-vdd-voltage = <1200000>;
+ mipi-csi-vdd-supply = <&pm8150_l9>;
+ clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSIPHY5_CLK>,
+ <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
+ <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy5_clk",
+ "csi5phytimer_clk_src",
+ "csi5phytimer_clk";
+ src-clock-name = "csi5phytimer_clk_src";
+ clock-cntl-level = "turbo";
+ clock-rates =
+ <400000000 0 300000000 0>;
+ status = "ok";
+ };
+
+ cam_cci0: qcom,cci@ac4f000 {
+ cell-index = <0>;
+ compatible = "qcom,cci";
+ reg = <0xac4f000 0x1000>;
+ reg-names = "cci";
+ reg-cam-base = <0x4f000>;
+ interrupt-names = "cci";
+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+ status = "ok";
+ gdscr-supply = <&titan_top_gdsc>;
+ regulator-names = "gdscr";
+ clocks = <&clock_camcc CAM_CC_CCI_0_CLK_SRC>,
+ <&clock_camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "cci_0_clk_src",
+ "cci_0_clk";
+ src-clock-name = "cci_0_clk_src";
+ clock-cntl-level = "lowsvs";
+ clock-rates = <37500000 0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cci0_active &cci1_active>;
+ pinctrl-1 = <&cci0_suspend &cci1_suspend>;
+ gpios = <&tlmm 101 0>,
+ <&tlmm 102 0>,
+ <&tlmm 103 0>,
+ <&tlmm 104 0>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 1 1 1>;
+ gpio-req-tbl-label = "CCI_I2C_DATA0",
+ "CCI_I2C_CLK0",
+ "CCI_I2C_DATA1",
+ "CCI_I2C_CLK1";
+
+ i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
+ hw-thigh = <201>;
+ hw-tlow = <174>;
+ hw-tsu-sto = <204>;
+ hw-tsu-sta = <231>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <162>;
+ hw-tbuf = <227>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_custom_cci0: qcom,i2c_custom_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <1>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
+ hw-thigh = <16>;
+ hw-tlow = <22>;
+ hw-tsu-sto = <17>;
+ hw-tsu-sta = <18>;
+ hw-thd-dat = <16>;
+ hw-thd-sta = <15>;
+ hw-tbuf = <24>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <3>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+ };
+
+ cam_cci1: qcom,cci@ac50000 {
+ cell-index = <1>;
+ compatible = "qcom,cci";
+ reg = <0xac50000 0x1000>;
+ reg-names = "cci";
+ reg-cam-base = <0x50000>;
+ interrupt-names = "cci";
+ interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
+ status = "ok";
+ gdscr-supply = <&titan_top_gdsc>;
+ regulator-names = "gdscr";
+ clocks = <&clock_camcc CAM_CC_CCI_1_CLK_SRC>,
+ <&clock_camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "cci_1_clk_src",
+ "cci_1_clk";
+ src-clock-name = "cci_1_clk_src";
+ clock-cntl-level = "lowsvs";
+ clock-rates = <37500000 0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cci2_active &cci3_active>;
+ pinctrl-1 = <&cci2_suspend &cci3_suspend>;
+ gpios = <&tlmm 105 0>,
+ <&tlmm 106 0>,
+ <&tlmm 107 0>,
+ <&tlmm 108 0>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 1 1 1>;
+ gpio-req-tbl-label = "CCI_I2C_DATA2",
+ "CCI_I2C_CLK2",
+ "CCI_I2C_DATA3",
+ "CCI_I2C_CLK3";
+
+ i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {
+ hw-thigh = <201>;
+ hw-tlow = <174>;
+ hw-tsu-sto = <204>;
+ hw-tsu-sta = <231>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <162>;
+ hw-tbuf = <227>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_custom_cci1: qcom,i2c_custom_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <1>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {
+ hw-thigh = <16>;
+ hw-tlow = <22>;
+ hw-tsu-sto = <17>;
+ hw-tsu-sta = <18>;
+ hw-thd-dat = <16>;
+ hw-thd-sta = <15>;
+ hw-tbuf = <24>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <3>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+ };
+
+ qcom,cam_smmu {
+ compatible = "qcom,msm-cam-smmu";
+ status = "ok";
+
+ msm_cam_smmu_ife {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x800 0x400>,
+ <&apps_smmu 0x801 0x400>,
+ <&apps_smmu 0x840 0x400>,
+ <&apps_smmu 0x841 0x400>,
+ <&apps_smmu 0xC00 0x400>,
+ <&apps_smmu 0xC01 0x400>,
+ <&apps_smmu 0xC40 0x400>,
+ <&apps_smmu 0xC41 0x400>;
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ label = "ife";
+ ife_iova_mem_map: iova-mem-map {
+ /* IO region is approximately 3.4 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_jpeg {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x2040 0x400>,
+ <&apps_smmu 0x2440 0x400>;
+ label = "jpeg";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ jpeg_iova_mem_map: iova-mem-map {
+ /* IO region is approximately 3.4 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_icp_fw {
+ compatible = "qcom,msm-cam-smmu-fw-dev";
+ label="icp";
+ memory-region = <&pil_camera_mem>;
+ };
+
+ msm_cam_smmu_icp {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x20E2 0x400>,
+ <&apps_smmu 0x24E2 0x400>,
+ <&apps_smmu 0x2000 0x400>,
+ <&apps_smmu 0x2001 0x400>,
+ <&apps_smmu 0x2400 0x400>,
+ <&apps_smmu 0x2401 0x400>,
+ <&apps_smmu 0x2060 0x400>,
+ <&apps_smmu 0x2061 0x400>,
+ <&apps_smmu 0x2460 0x400>,
+ <&apps_smmu 0x2461 0x400>,
+ <&apps_smmu 0x2020 0x400>,
+ <&apps_smmu 0x2021 0x400>,
+ <&apps_smmu 0x2420 0x400>,
+ <&apps_smmu 0x2421 0x400>;
+ label = "icp";
+ qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>;
+ iova-region-discard = <0xdff00000 0x300000>;
+ icp_iova_mem_map: iova-mem-map {
+ iova-mem-region-firmware {
+ /* Firmware region is 5MB */
+ iova-region-name = "firmware";
+ iova-region-start = <0x0>;
+ iova-region-len = <0x500000>;
+ iova-region-id = <0x0>;
+ status = "ok";
+ };
+
+ iova-mem-region-shared {
+ /* Shared region is 150MB long */
+ iova-region-name = "shared";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0x9600000>;
+ iova-region-id = <0x1>;
+ status = "ok";
+ };
+
+ iova-mem-region-secondary-heap {
+ /* Secondary heap region is 1MB long */
+ iova-region-name = "secheap";
+ iova-region-start = <0x10a00000>;
+ iova-region-len = <0x100000>;
+ iova-region-id = <0x4>;
+ status = "ok";
+ };
+
+ iova-mem-region-io {
+ /* IO region is approximately 3.7 GB */
+ iova-region-name = "io";
+ iova-region-start = <0x10c00000>;
+ iova-region-len = <0xee300000>;
+ iova-region-id = <0x3>;
+ iova-region-discard = <0xdff00000 0x300000>;
+ status = "ok";
+ };
+
+ iova-mem-qdss-region {
+ /* QDSS region is appropriate 1MB */
+ iova-region-name = "qdss";
+ iova-region-start = <0x10b00000>;
+ iova-region-len = <0x100000>;
+ iova-region-id = <0x5>;
+ qdss-phy-addr = <0x16790000>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_cpas_cdm {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x20C0 0x400>,
+ <&apps_smmu 0x24C0 0x400>;
+ label = "cpas-cdm0";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ cpas_cdm_iova_mem_map: iova-mem-map {
+ iova-mem-region-io {
+ /* IO region is approximately 3.4 GB */
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_secure {
+ compatible = "qcom,msm-cam-smmu-cb";
+ label = "cam-secure";
+ qcom,secure-cb;
+ };
+
+ msm_cam_smmu_fd {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x2080 0x400>,
+ <&apps_smmu 0x2480 0x400>;
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ label = "fd";
+ fd_iova_mem_map: iova-mem-map {
+ iova-mem-region-io {
+ /* IO region is approximately 3.4 GB */
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+ };
+
+ qcom,cam-cpas@ac40000 {
+ cell-index = <0>;
+ compatible = "qcom,cam-cpas";
+ label = "cpas";
+ arch-compat = "cpas_top";
+ status = "ok";
+ reg-names = "cam_cpas_top", "cam_camnoc";
+ reg = <0xac40000 0x1000>,
+ <0xac42000 0x8000>;
+ reg-cam-base = <0x40000 0x42000>;
+ interrupt-names = "cpas_camnoc";
+ interrupts = <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>;
+ camnoc-axi-min-ib-bw = <3000000000>;
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&titan_top_gdsc>;
+ clock-names =
+ "gcc_ahb_clk",
+ "gcc_axi_hf_clk",
+ "gcc_axi_sf_clk",
+ "slow_ahb_clk_src",
+ "cpas_ahb_clk",
+ "cpas_core_ahb_clk",
+ "camnoc_axi_clk_src",
+ "camnoc_axi_clk";
+ clocks =
+ <&clock_gcc GCC_CAMERA_AHB_CLK>,
+ <&clock_gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&clock_gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&clock_camcc CAM_CC_CPAS_AHB_CLK>,
+ <&clock_camcc CAM_CC_CORE_AHB_CLK>,
+ <&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
+ <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>;
+ src-clock-name = "camnoc_axi_clk_src";
+ clock-rates =
+ <0 0 0 0 0 0 0 0>,
+ <0 0 0 19200000 0 0 19200000 0>,
+ <0 0 0 80000000 0 0 300000000 0>,
+ <0 0 0 80000000 0 0 400000000 0>,
+ <0 0 0 80000000 0 0 400000000 0>,
+ <0 0 0 80000000 0 0 400000000 0>,
+ <0 0 0 80000000 0 0 400000000 0>,
+ <0 0 0 80000000 0 0 480000000 0>;
+ clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs",
+ "svs_l1", "nominal", "nominal_l1", "turbo";
+ control-camnoc-axi-clk;
+ camnoc-bus-width = <32>;
+ camnoc-axi-clk-bw-margin-perc = <20>;
+ qcom,msm-bus,name = "cam_ahb";
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 76800>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 76800>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 300000>;
+ vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
+ RPMH_REGULATOR_LEVEL_MIN_SVS
+ RPMH_REGULATOR_LEVEL_LOW_SVS
+ RPMH_REGULATOR_LEVEL_SVS
+ RPMH_REGULATOR_LEVEL_SVS_L1
+ RPMH_REGULATOR_LEVEL_NOM
+ RPMH_REGULATOR_LEVEL_NOM_L1
+ RPMH_REGULATOR_LEVEL_NOM_L2
+ RPMH_REGULATOR_LEVEL_TURBO
+ RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ vdd-corner-ahb-mapping = "suspend", "minsvs",
+ "lowsvs", "svs", "svs_l1",
+ "nominal", "nominal", "nominal",
+ "turbo", "turbo";
+ client-id-based;
+ client-names =
+ "csiphy0", "csiphy1", "csiphy2", "csiphy3",
+ "csiphy4", "csiphy5", "cci0", "cci1",
+ "csid0", "csid1", "csid2", "csid3",
+ "csid4", "csid5", "csid6", "ife0", "ife1",
+ "ife2", "ife3", "ife4", "ife5", "ife6",
+ "custom0", "ipe0", "cam-cdm-intf0", "cpas-cdm0",
+ "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", "fd0";
+
+ camera-bus-nodes {
+ level3-nodes {
+ level-index = <3>;
+ level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum {
+ cell-index = <0>;
+ node-name = "level3-rt0-rd-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_hf_0";
+ ib-bw-voting-needed;
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_hf_0_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_HF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_HF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+ };
+
+ level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum {
+ cell-index = <1>;
+ node-name = "level3-nrt0-rd-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_sf_0";
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_sf_0_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_SF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_SF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+ };
+
+ level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum {
+ cell-index = <2>;
+ node-name = "level3-nrt1-rd-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_sf_icp";
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_sf_icp_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_ICP
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_ICP
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+ };
+ };
+
+ level2-nodes {
+ level-index = <2>;
+ camnoc-max-needed;
+ level2_rt0_wr: level2-rt0-wr {
+ cell-index = <3>;
+ node-name = "level2-rt0-wr";
+ parent-node = <&level3_rt0_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
+ };
+
+ level2_rt0_rd: level2-rt0-rd {
+ cell-index = <4>;
+ node-name = "level2-rt0-rd";
+ parent-node = <&level3_rt0_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
+ };
+
+ level2_nrt0_wr: level2-nrt0-wr {
+ cell-index = <5>;
+ node-name = "level2-nrt0-wr";
+ parent-node = <&level3_nrt0_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
+ };
+
+ level2_nrt0_rd: level2-nrt0-rd {
+ cell-index = <6>;
+ node-name = "level2-nrt0-rd";
+ parent-node = <&level3_nrt0_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
+ };
+
+ level2_nrt1_rd: level2-nrt1-rd {
+ cell-index = <7>;
+ node-name = "level2-nrt1-rd";
+ parent-node = <&level3_nrt1_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ bus-width-factor = <4>;
+ };
+ };
+
+ level1-nodes {
+ level-index = <1>;
+ camnoc-max-needed;
+ level1_rt0_wr0: level1-rt0-wr0 {
+ cell-index = <8>;
+ node-name = "level1-rt0-wr0";
+ parent-node = <&level2_rt0_wr>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_rt0_wr1: level1-rt0-wr1 {
+ cell-index = <9>;
+ node-name = "level1-rt0-wr1";
+ parent-node = <&level2_rt0_wr>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_rt0_rd0: level1-rt0-rd0 {
+ cell-index = <10>;
+ node-name = "level1-rt0-rd0";
+ parent-node = <&level2_rt0_rd>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_rt0_wr2: level1-rt0-wr2 {
+ cell-index = <11>;
+ node-name = "level1-rt0-wr2";
+ parent-node = <&level2_rt0_wr>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_nrt0_wr0: level1-nrt0-wr0 {
+ cell-index = <12>;
+ node-name = "level1-nrt0-wr0";
+ parent-node = <&level2_nrt0_wr>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_nrt0_rd0: level1-nrt0-rd0 {
+ cell-index = <13>;
+ node-name = "level1-nrt0-rd0";
+ parent-node = <&level2_nrt0_rd>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_nrt0_wr1: level1-nrt0-wr1 {
+ cell-index = <14>;
+ node-name = "level1-nrt0-wr1";
+ parent-node = <&level2_nrt0_wr>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_nrt0_rd2: level1-nrt0-rd2 {
+ cell-index = <15>;
+ node-name = "level1-nrt0-rd2";
+ parent-node = <&level2_nrt0_rd>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+ };
+
+ level0-nodes {
+ level-index = <0>;
+ ife0_ubwc_stats_wr: ife0-ubwc-stats-wr {
+ cell-index = <16>;
+ node-name = "ife0-ubwc-stats-wr";
+ client-name = "ife0";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_UBWC_STATS>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS>;
+ parent-node = <&level1_rt0_wr0>;
+ };
+
+ ife1_ubwc_stats_wr: ife1-ubwc-stats-wr {
+ cell-index = <17>;
+ node-name = "ife1-ubwc-stats-wr";
+ client-name = "ife1";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_UBWC_STATS>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS>;
+ parent-node = <&level1_rt0_wr0>;
+ };
+
+ ife0_linear_pdaf_wr: ife0-linear-pdaf-wr {
+ cell-index = <18>;
+ node-name = "ife0-linear-pdaf-wr";
+ client-name = "ife0";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_LINEAR_PDAF>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_LINEAR
+ CAM_CPAS_PATH_DATA_IFE_PDAF>;
+ parent-node = <&level1_rt0_wr1>;
+ };
+
+ ife1_linear_pdaf_wr: ife1-linear-pdaf-wr {
+ cell-index = <19>;
+ node-name = "ife1-linear-pdaf-wr";
+ client-name = "ife1";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_LINEAR_PDAF>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_LINEAR
+ CAM_CPAS_PATH_DATA_IFE_PDAF>;
+ parent-node = <&level1_rt0_wr1>;
+ };
+
+ ife2_rdi_all_wr: ife2-rdi-all-wr {
+ cell-index = <20>;
+ node-name = "ife2-rdi-all-wr";
+ client-name = "ife2";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt0_wr1>;
+ };
+
+ ife3_rdi_all_wr: ife3-rdi-all-wr {
+ cell-index = <21>;
+ node-name = "ife3-rdi-all-wr";
+ client-name = "ife3";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt0_wr1>;
+ };
+
+ ife4_rdi_all_wr: ife4-rdi-all-wr {
+ cell-index = <22>;
+ node-name = "ife4-rdi-all-wr";
+ client-name = "ife4";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt0_wr1>;
+ };
+
+ ife5_rdi_all_wr: ife5-rdi-all-wr {
+ cell-index = <23>;
+ node-name = "ife5-rdi-all-wr";
+ client-name = "ife5";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt0_wr1>;
+ };
+
+ ife0_rdi_all_rd: ife0-rdi-all-rd {
+ cell-index = <24>;
+ node-name = "ife0-rdi-all-rd";
+ client-name = "ife0";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt0_rd0>;
+ };
+
+ ife1_rdi_all_rd: ife1-rdi-all-rd {
+ cell-index = <25>;
+ node-name = "ife1-rdi-all-rd";
+ client-name = "ife1";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt0_rd0>;
+ };
+
+ custom0_all_rd: custom0-all-rd {
+ cell-index = <26>;
+ node-name = "custom0-all-rd";
+ client-name = "custom0";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_rt0_rd0>;
+ };
+
+ ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr {
+ cell-index = <27>;
+ node-name = "ife0-rdi-pixel-raw-wr";
+ client-name = "ife0";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_PIXEL_RAW>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_PIXEL_RAW>;
+ parent-node = <&level1_rt0_wr2>;
+ };
+
+ ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr {
+ cell-index = <28>;
+ node-name = "ife1-rdi-pixel-raw-wr";
+ client-name = "ife1";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_PIXEL_RAW>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_PIXEL_RAW>;
+ parent-node = <&level1_rt0_wr2>;
+ };
+
+ ife6_rdi_all_wr: ife6-rdi-all-wr {
+ cell-index = <29>;
+ node-name = "ife6-rdi-all-wr";
+ client-name = "ife6";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt0_wr2>;
+ };
+
+ custom0_all_wr: custom0-all-wr {
+ cell-index = <30>;
+ node-name = "custom0-all-wr";
+ client-name = "custom0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level1_rt0_wr2>;
+ };
+
+ ipe0_all_wr: ipe0-all-wr {
+ cell-index = <31>;
+ node-name = "ipe0-all-wr";
+ client-name = "ipe0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IPE_WR_VID
+ CAM_CPAS_PATH_DATA_IPE_WR_DISP
+ CAM_CPAS_PATH_DATA_IPE_WR_REF>;
+ parent-node = <&level1_nrt0_wr0>;
+ };
+
+ bps0_all_wr: bps0-all-wr {
+ cell-index = <32>;
+ node-name = "bps0-all-wr";
+ client-name = "bps0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level1_nrt0_wr0>;
+ };
+
+ ipe0_ref_rd: ipe0-ref-rd {
+ cell-index = <33>;
+ node-name = "ipe0-ref-rd";
+ client-name = "ipe0";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IPE_RD_REF>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_rd0>;
+ };
+
+ bps0_all_rd: bps0-all-rd {
+ cell-index = <34>;
+ node-name = "bps0-all-rd";
+ client-name = "bps0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_rd0>;
+ };
+
+ ipe0_in_rd: ipe0-in-rd {
+ cell-index = <35>;
+ node-name = "ipe0-in-rd";
+ client-name = "ipe0";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IPE_RD_IN>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level2_nrt0_rd>;
+ };
+
+ jpeg_enc0_all_wr: jpeg-enc0-all-wr {
+ cell-index = <36>;
+ node-name = "jpeg-enc0-all-wr";
+ client-name = "jpeg-enc0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level1_nrt0_wr1>;
+ };
+
+ jpeg_dma0_all_wr: jpeg-dma0-all-wr {
+ cell-index = <37>;
+ node-name = "jpeg-dma0-all-wr";
+ client-name = "jpeg-dma0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level1_nrt0_wr1>;
+ };
+
+ jpeg_enc0_all_rd: jpeg-enc0-all-rd {
+ cell-index = <38>;
+ node-name = "jpeg-enc0-all-rd";
+ client-name = "jpeg-enc0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_rd2>;
+ };
+
+ jpeg_dma0_all_rd: jpeg-dma0-all-rd {
+ cell-index = <39>;
+ node-name = "jpeg-dma0-all-rd";
+ client-name = "jpeg-dma0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_rd2>;
+ };
+
+ fd0_all_wr: fd0-all-wr {
+ cell-index = <40>;
+ node-name = "fd0-all-wr";
+ client-name = "fd0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level2_nrt0_wr>;
+ };
+
+ fd0_all_rd: fd0-all-rd {
+ cell-index = <41>;
+ node-name = "fd0-all-rd";
+ client-name = "fd0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level2_nrt0_rd>;
+ };
+
+ cpas_cdm0_all_rd: cpas-cdm0-all-rd {
+ cell-index = <42>;
+ node-name = "cpas-cdm0-all-rd";
+ client-name = "cpas-cdm0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level2_nrt0_rd>;
+ };
+
+ icp0_all_rd: icp0-all-rd {
+ cell-index = <43>;
+ node-name = "icp0-all-rd";
+ client-name = "icp0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level2_nrt1_rd>;
+ };
+ };
+ };
+ };
+
+ qcom,cam-cdm-intf {
+ compatible = "qcom,cam-cdm-intf";
+ cell-index = <0>;
+ label = "cam-cdm-intf";
+ num-hw-cdm = <3>;
+ cdm-client-names = "vfe",
+ "jpegdma",
+ "jpegenc",
+ "fd";
+ status = "ok";
+ };
+
+ qcom,cpas-cdm0@ac4d000 {
+ cell-index = <0>;
+ compatible = "qcom,cam170-cpas-cdm0";
+ label = "cpas-cdm";
+ reg = <0xac4d000 0x1000>;
+ reg-names = "cpas-cdm";
+ reg-cam-base = <0x4d000>;
+ interrupts = <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "cpas-cdm";
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names = "cam_cc_cpas_slow_ahb_clk",
+ "cam_cc_cpas_ahb_clk";
+ clocks = <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&clock_camcc CAM_CC_CPAS_AHB_CLK>;
+ clock-rates = <0 0>;
+ clock-cntl-level = "svs";
+ cdm-client-names = "ife";
+ status = "ok";
+ };
+
+ qcom,cpas-cdm1@acb4200 {
+ cell-index = <1>;
+ compatible = "qcom,cam480-cpas-cdm1";
+ label = "cpas-cdm";
+ reg = <0xacb4200 0x1000>;
+ reg-names = "cpas-cdm";
+ reg-cam-base = <0xb4200>;
+ interrupts = <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "cpas-cdm";
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names = "cam_cc_cpas_slow_ahb_clk",
+ "cam_cc_cpas_ahb_clk";
+ clocks = <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&clock_camcc CAM_CC_CPAS_AHB_CLK>;
+ clock-rates = <0 0>;
+ clock-cntl-level = "svs";
+ cdm-client-names = "ife0";
+ status = "disabled";
+ };
+
+ qcom,cpas-cdm2@acc3200 {
+ cell-index = <2>;
+ compatible = "qcom,cam480-cpas-cdm2";
+ label = "cpas-cdm";
+ reg = <0xacc3200 0x1000>;
+ reg-names = "cpas-cdm";
+ reg-cam-base = <0xc3200>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "cpas-cdm";
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names = "cam_cc_cpas_slow_ahb_clk",
+ "cam_cc_cpas_ahb_clk";
+ clocks = <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&clock_camcc CAM_CC_CPAS_AHB_CLK>;
+ clock-rates = <0 0>;
+ clock-cntl-level = "svs";
+ cdm-client-names = "ife1";
+ status = "disabled";
+ };
+
+ qcom,cam-isp {
+ compatible = "qcom,cam-isp";
+ arch-compat = "ife";
+ status = "ok";
+ };
+
+ cam_csid0: qcom,csid0@acb5200 {
+ cell-index = <0>;
+ compatible = "qcom,csid480";
+ reg-names = "csid";
+ reg = <0xacb5200 0x1000>;
+ reg-cam-base = <0xb5200>;
+ interrupt-names = "csid";
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss", "ife0";
+ camss-supply = <&titan_top_gdsc>;
+ ife0-supply = <&ife_0_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_clk",
+ "ife_0_areg",
+ "ife_0_ahb",
+ "ife_axi_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_0_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_AREG_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_AXI_CLK>;
+ clock-rates =
+ <400000000 0 400000000 0 350000000 0 100000000 0 0>,
+ <400000000 0 400000000 0 475000000 0 200000000 0 0>,
+ <400000000 0 400000000 0 576000000 0 300000000 0 0>,
+ <400000000 0 400000000 0 720000000 0 400000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_vfe0: qcom,ife0@acb4000 {
+ cell-index = <0>;
+ compatible = "qcom,vfe480";
+ reg-names = "ife", "cam_camnoc";
+ reg = <0xacb4000 0xd000>,
+ <0xac42000 0x8000>;
+ reg-cam-base = <0xb4000 0x42000>;
+ interrupt-names = "ife";
+ interrupts = <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss", "ife0";
+ camss-supply = <&titan_top_gdsc>;
+ ife0-supply = <&ife_0_gdsc>;
+ clock-names =
+ "ife_0_ahb",
+ "ife_0_areg",
+ "ife_clk_src",
+ "ife_clk",
+ "ife_axi_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_0_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_AREG_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_0_CLK>,
+ <&clock_camcc CAM_CC_IFE_0_AXI_CLK>;
+ clock-rates =
+ <0 100000000 350000000 0 0>,
+ <0 200000000 475000000 0 0>,
+ <0 300000000 576000000 0 0>,
+ <0 400000000 720000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ scl-clk-names = "ife_0_areg";
+ clock-control-debugfs = "true";
+ clock-names-option = "ife_dsp_clk";
+ clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>;
+ clock-rates-option = <720000000>;
+ ubwc-static-cfg = <0x1026 0x1036>;
+ status = "ok";
+ };
+
+ cam_csid1: qcom,csid1@acc4200 {
+ cell-index = <1>;
+ compatible = "qcom,csid480";
+ reg-names = "csid";
+ reg = <0xacc4200 0x1000>;
+ reg-cam-base = <0xc4200>;
+ interrupt-names = "csid";
+ interrupts = <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss", "ife1";
+ camss-supply = <&titan_top_gdsc>;
+ ife1-supply = <&ife_1_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_clk",
+ "ife_1_areg",
+ "ife_1_ahb",
+ "ife_axi_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_1_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_AREG_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_AXI_CLK>;
+ clock-rates =
+ <400000000 0 400000000 0 350000000 0 100000000 0 0>,
+ <400000000 0 400000000 0 475000000 0 200000000 0 0>,
+ <400000000 0 400000000 0 576000000 0 300000000 0 0>,
+ <400000000 0 400000000 0 720000000 0 400000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_vfe1: qcom,ife1@acc3000 {
+ cell-index = <1>;
+ compatible = "qcom,vfe480";
+ reg-names = "ife", "cam_camnoc";
+ reg = <0xacc3000 0xd000>,
+ <0xac42000 0x8000>;
+ reg-cam-base = <0xc3000 0x42000>;
+ interrupt-names = "ife";
+ interrupts = <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss", "ife1";
+ camss-supply = <&titan_top_gdsc>;
+ ife1-supply = <&ife_1_gdsc>;
+ clock-names =
+ "ife_1_ahb",
+ "ife_1_areg",
+ "ife_clk_src",
+ "ife_clk",
+ "ife_axi_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_1_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_AREG_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_1_CLK>,
+ <&clock_camcc CAM_CC_IFE_1_AXI_CLK>;
+ clock-rates =
+ <0 100000000 350000000 0 0>,
+ <0 200000000 475000000 0 0>,
+ <0 300000000 576000000 0 0>,
+ <0 400000000 720000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ scl-clk-names = "ife_1_areg";
+ clock-control-debugfs = "true";
+ clock-names-option = "ife_dsp_clk";
+ clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>;
+ clock-rates-option = <720000000>;
+ ubwc-static-cfg = <0x1026 0x1036>;
+ status = "ok";
+ };
+
+ cam_csid_lite0: qcom,csid-lite0@acd9200 {
+ cell-index = <2>;
+ compatible = "qcom,csid-lite480";
+ reg-names = "csid-lite";
+ reg = <0xacd9200 0x1000>;
+ reg-cam-base = <0xd9200>;
+ interrupt-names = "csid-lite";
+ interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_lite_ahb",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <400000000 0 0 0 400000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_vfe_lite0: qcom,ife-lite0@acd9000 {
+ cell-index = <2>;
+ compatible = "qcom,vfe-lite480";
+ reg-names = "ife-lite";
+ reg = <0xacd9000 0x2200>;
+ reg-cam-base = <0xd9000>;
+ interrupt-names = "ife-lite";
+ interrupts = <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_lite_ahb",
+ "ife_lite_axi",
+ "ife_clk_src",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <0 0 400000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_csid_lite1: qcom,csid-lite1@acdb400 {
+ cell-index = <3>;
+ compatible = "qcom,csid-lite480";
+ reg-names = "csid-lite";
+ reg = <0xacdb400 0x1000>;
+ reg-cam-base = <0xdb400>;
+ interrupt-names = "csid-lite";
+ interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_lite_ahb",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <400000000 0 0 0 400000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_vfe_lite1: qcom,ife-lite1@acdb200 {
+ cell-index = <3>;
+ compatible = "qcom,vfe-lite480";
+ reg-names = "ife-lite";
+ reg = <0xacdb200 0x2200>;
+ reg-cam-base = <0xdb200>;
+ interrupt-names = "ife-lite";
+ interrupts = <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_lite_ahb",
+ "ife_lite_axi",
+ "ife_clk_src",
+ "ife_clk";
+ clocks =
+ <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_AXI_CLK>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&clock_camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <0 0 400000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>,
+ <0 0 480000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ qcom,cam-icp {
+ compatible = "qcom,cam-icp";
+ compat-hw-name = "qcom,a5",
+ "qcom,ipe0",
+ "qcom,bps";
+ num-a5 = <1>;
+ num-ipe = <1>;
+ num-bps = <1>;
+ status = "ok";
+ icp_pc_en;
+ ipe_bps_pc_en;
+ };
+
+ cam_a5: qcom,a5@ac00000 {
+ cell-index = <0>;
+ compatible = "qcom,cam-a5";
+ reg = <0xac00000 0x6000>,
+ <0xac10000 0x8000>,
+ <0xac18000 0x3000>;
+ reg-names = "a5_qgic", "a5_sierra", "a5_csr";
+ reg-cam-base = <0x00000 0x10000 0x18000>;
+ interrupts = <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a5";
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&titan_top_gdsc>;
+ clock-names =
+ "soc_fast_ahb",
+ "icp_ahb_clk",
+ "icp_clk_src",
+ "icp_clk";
+ src-clock-name = "icp_clk_src";
+ clocks =
+ <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>,
+ <&clock_camcc CAM_CC_ICP_AHB_CLK>,
+ <&clock_camcc CAM_CC_ICP_CLK_SRC>,
+ <&clock_camcc CAM_CC_ICP_CLK>;
+
+ clock-rates =
+ <100000000 0 400000000 0>,
+ <200000000 0 480000000 0>,
+ <300000000 0 600000000 0>,
+ <400000000 0 600000000 0>,
+ <400000000 0 600000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1",
+ "nominal", "turbo";
+ fw_name = "CAMERA_ICP.elf";
+ ubwc-ipe-fetch-cfg = <0x707b 0x7083>;
+ ubwc-ipe-write-cfg = <0x161ef 0x1620f>;
+ ubwc-bps-fetch-cfg = <0x707b 0x7083>;
+ ubwc-bps-write-cfg = <0x161ef 0x1620f>;
+ status = "ok";
+ };
+
+ cam_ipe0: qcom,ipe0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-ipe";
+ reg = <0xac9a000 0xc000>;
+ reg-names = "ipe0_top";
+ reg-cam-base = <0x9a000>;
+ regulator-names = "ipe0-vdd";
+ ipe0-vdd-supply = <&ipe_0_gdsc>;
+ clock-names =
+ "ipe_0_ahb_clk",
+ "ipe_0_areg_clk",
+ "ipe_0_axi_clk",
+ "ipe_0_clk_src",
+ "ipe_0_clk";
+ src-clock-name = "ipe_0_clk_src";
+ clock-control-debugfs = "true";
+ clocks =
+ <&clock_camcc CAM_CC_IPE_0_AHB_CLK>,
+ <&clock_camcc CAM_CC_IPE_0_AREG_CLK>,
+ <&clock_camcc CAM_CC_IPE_0_AXI_CLK>,
+ <&clock_camcc CAM_CC_IPE_0_CLK_SRC>,
+ <&clock_camcc CAM_CC_IPE_0_CLK>;
+
+ clock-rates =
+ <0 0 0 300000000 0>,
+ <0 0 0 475000000 0>,
+ <0 0 0 525000000 0>,
+ <0 0 0 700000000 0>,
+ <0 0 0 700000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1",
+ "nominal", "turbo";
+ status = "ok";
+ };
+
+ cam_bps: qcom,bps {
+ cell-index = <0>;
+ compatible = "qcom,cam-bps";
+ reg = <0xac7a000 0x8000>;
+ reg-names = "bps_top";
+ reg-cam-base = <0x7a000>;
+ regulator-names = "bps-vdd";
+ bps-vdd-supply = <&bps_gdsc>;
+ clock-names =
+ "bps_ahb_clk",
+ "bps_areg_clk",
+ "bps_axi_clk",
+ "bps_clk_src",
+ "bps_clk";
+ src-clock-name = "bps_clk_src";
+ clock-control-debugfs = "true";
+ clocks =
+ <&clock_camcc CAM_CC_BPS_AHB_CLK>,
+ <&clock_camcc CAM_CC_BPS_AREG_CLK>,
+ <&clock_camcc CAM_CC_BPS_AXI_CLK>,
+ <&clock_camcc CAM_CC_BPS_CLK_SRC>,
+ <&clock_camcc CAM_CC_BPS_CLK>;
+
+ clock-rates =
+ <0 0 0 200000000 0>,
+ <0 0 0 400000000 0>,
+ <0 0 0 480000000 0>,
+ <0 0 0 600000000 0>,
+ <0 0 0 600000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1",
+ "nominal", "turbo";
+ status = "ok";
+ };
+
+ qcom,cam-jpeg {
+ compatible = "qcom,cam-jpeg";
+ compat-hw-name = "qcom,jpegenc",
+ "qcom,jpegdma";
+ num-jpeg-enc = <1>;
+ num-jpeg-dma = <1>;
+ status = "ok";
+ };
+
+ cam_jpeg_enc: qcom,jpegenc@ac53000 {
+ cell-index = <0>;
+ compatible = "qcom,cam_jpeg_enc";
+ reg-names = "jpege_hw";
+ reg = <0xac53000 0x4000>;
+ reg-cam-base = <0x53000>;
+ interrupt-names = "jpeg";
+ interrupts = <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&titan_top_gdsc>;
+ clock-names =
+ "jpegenc_clk_src",
+ "jpegenc_clk";
+ clocks =
+ <&clock_camcc CAM_CC_JPEG_CLK_SRC>,
+ <&clock_camcc CAM_CC_JPEG_CLK>;
+
+ clock-rates = <600000000 0>;
+ src-clock-name = "jpegenc_clk_src";
+ clock-cntl-level = "nominal";
+ status = "ok";
+ };
+
+ cam_jpeg_dma: qcom,jpegdma@ac57000 {
+ cell-index = <0>;
+ compatible = "qcom,cam_jpeg_dma";
+ reg-names = "jpegdma_hw";
+ reg = <0xac57000 0x4000>;
+ reg-cam-base = <0x57000>;
+ interrupt-names = "jpegdma";
+ interrupts = <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&titan_top_gdsc>;
+ clock-names =
+ "jpegdma_clk_src",
+ "jpegdma_clk";
+ clocks =
+ <&clock_camcc CAM_CC_JPEG_CLK_SRC>,
+ <&clock_camcc CAM_CC_JPEG_CLK>;
+
+ clock-rates = <600000000 0>;
+ src-clock-name = "jpegdma_clk_src";
+ clock-cntl-level = "nominal";
+ status = "ok";
+ };
+
+ qcom,cam-fd {
+ compatible = "qcom,cam-fd";
+ compat-hw-name = "qcom,fd";
+ num-fd = <1>;
+ status = "ok";
+ };
+
+ cam_fd: qcom,fd@ac5f000 {
+ cell-index = <0>;
+ compatible = "qcom,fd600";
+ reg-names = "fd_core", "fd_wrapper";
+ reg = <0xac5f000 0x1000>,
+ <0xac60000 0x400>;
+ reg-cam-base = <0x5f000 0x60000>;
+ interrupt-names = "fd";
+ interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&titan_top_gdsc>;
+ clock-names =
+ "fd_core_clk_src",
+ "fd_core_clk",
+ "fd_core_uar_clk";
+ clocks =
+ <&clock_camcc CAM_CC_FD_CORE_CLK_SRC>,
+ <&clock_camcc CAM_CC_FD_CORE_CLK>,
+ <&clock_camcc CAM_CC_FD_CORE_UAR_CLK>;
+ src-clock-name = "fd_core_clk_src";
+ clock-control-debugfs = "true";
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ clock-rates =
+ <400000000 0 0>,
+ <480000000 0 0>,
+ <600000000 0 0>;
+ status = "ok";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera-sensor-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera-sensor-cdp.dtsi
new file mode 100755
index 0000000..5f98331
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera-sensor-cdp.dtsi
@@ -0,0 +1,421 @@
+#include <dt-bindings/clock/qcom,camcc-lagoon.h>
+
+&soc {
+ led_flash_triple_rear: qcom,camera-flash@4 {
+ cell-index = <4>;
+ reg = <0x04 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+ torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+ switch-source = <&pm6150l_switch2>;
+ };
+
+ led_flash_triple_rear_aux: qcom,camera-flash@5 {
+ cell-index = <5>;
+ reg = <0x05 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+ torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+ switch-source = <&pm6150l_switch2>;
+ };
+
+ led_flash_triple_rear_aux2: qcom,camera-flash@6 {
+ cell-index = <6>;
+ reg = <0x06 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+ torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+ switch-source = <&pm6150l_switch2>;
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_triple_rear: qcom,actuator@4 {
+ cell-index = <4>;
+ reg = <0x4>;
+ compatible = "qcom,actuator";
+ cci-device = <0>;
+ cci-master = <0>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ actuator_triple_rear_aux: qcom,actuator@5 {
+ cell-index = <5>;
+ reg = <0x5>;
+ compatible = "qcom,actuator";
+ cci-device = <0>;
+ cci-master = <1>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ eeprom_triple_rear: qcom,eeprom@4 {
+ cell-index = <4>;
+ reg = <4>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2904000 1104000 0 2800000>;
+ rgltr-max-voltage = <1800000 2904000 1104000 0 2800000>;
+ rgltr-load-current = <0 80000 105000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 29 0>,
+ <&tlmm 34 0>,
+ <&tlmm 50 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK4",
+ "CAM_RESET4",
+ "CAM_VANA4";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_rear_aux: qcom,eeprom@5 {
+ cell-index = <5>;
+ reg = <5>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>;
+ rgltr-load-current = <0 2000000 105000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 30 0>,
+ <&tlmm 35 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK5",
+ "CAM_RESET5";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@4 {
+ cell-index = <4>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x4>;
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_triple_rear>;
+ actuator-src = <&actuator_triple_rear>;
+ eeprom-src = <&eeprom_triple_rear>;
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ cam_v_custom1-supply = <&S2A>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_v_custom1";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2904000 1104000 0 1856000>;
+ rgltr-max-voltage = <1800000 2904000 1104000 0 2048000>;
+ rgltr-load-current = <0 80000 105000 0 80000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 29 0>,
+ <&tlmm 34 0>,
+ <&tlmm 50 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK4",
+ "CAM_RESET4",
+ "CAM_VANA4";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@5 {
+ cell-index = <5>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x5>;
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_triple_rear_aux>;
+ actuator-src = <&actuator_triple_rear_aux>;
+ eeprom-src = <&eeprom_triple_rear_aux>;
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 2000000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 30 0>,
+ <&tlmm 35 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK5",
+ "CAM_RESET5";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
+&cam_cci1 {
+ actuator_triple_rear_aux2: qcom,actuator@6 {
+ cell-index = <6>;
+ reg = <0x6>;
+ compatible = "qcom,actuator";
+ cci-device = <1>;
+ cci-master = <0>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ eeprom_front: qcom,eeprom@2 {
+ cell-index = <2>;
+ reg = <0x2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_front>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_front>;
+ gpios = <&tlmm 32 0>,
+ <&tlmm 37 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_rear_aux2: qcom,eeprom@6 {
+ cell-index = <6>;
+ reg = <6>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L7P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>;
+ rgltr-load-current = <0 80000 105000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rear_aux2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rear_aux2>;
+ gpios = <&tlmm 31 0>,
+ <&tlmm 36 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x02>;
+ csiphy-sd-index = <3>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_front>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_front>;
+ gpios = <&tlmm 32 0>,
+ <&tlmm 37 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@6 {
+ cell-index = <6>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x06>;
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_triple_rear_aux2>;
+ actuator-src = <&actuator_triple_rear_aux2>;
+ eeprom-src = <&eeprom_triple_rear_aux2>;
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L7P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rear_aux2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rear_aux2>;
+ gpios = <&tlmm 31 0>,
+ <&tlmm 36 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK6",
+ "CAM_RESET6";
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera-sensor-mtp.dtsi
new file mode 100755
index 0000000..8ac19c7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera-sensor-mtp.dtsi
@@ -0,0 +1,414 @@
+#include <dt-bindings/clock/qcom,camcc-lagoon.h>
+
+&soc {
+ led_flash_triple_rear: qcom,camera-flash@4 {
+ cell-index = <4>;
+ reg = <0x04 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+ torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+ switch-source = <&pm6150l_switch2>;
+ };
+
+ led_flash_triple_rear_aux: qcom,camera-flash@5 {
+ cell-index = <5>;
+ reg = <0x05 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+ torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+ switch-source = <&pm6150l_switch2>;
+ };
+
+ camera_vdig2_ldo: gpio-regulator1@0 {
+ compatible = "regulator-fixed";
+ reg = <0x00 0x00>;
+ regulator-name = "camera_vdig2_ldo";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <233>;
+ enable-active-high;
+ gpio = <&pm6150l_gpios 3 0>;
+ vin-supply = <&BOB>;
+ };
+
+ camera_vdig1_ldo: gpio-regulator1@1 {
+ compatible = "regulator-fixed";
+ reg = <0x01 0x01>;
+ regulator-name = "camera_vdig1_ldo";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-enable-ramp-delay = <233>;
+ enable-active-high;
+ gpio = <&pm6150l_gpios 2 0>;
+ //pinctrl-names = "default";
+ //pinctrl-0 = <&cam_sensor_0_vdig>;
+ vin-supply = <&S8E>;
+ };
+
+ camera_vdig0_ldo1: gpio-regulator1@2 {
+ compatible = "regulator-fixed";
+ reg = <0x02 0x02>;
+ regulator-name = "camera_vdig0_ldo1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-enable-ramp-delay = <233>;
+ enable-active-high;
+ gpio = <&pm6150l_gpios 4 0>;
+ vin-supply = <&BOB>;
+ };
+
+ camera_vaf_ldo: gpio-regulator-vaf@0 {
+ compatible = "regulator-fixed";
+ reg = <0x00 0x00>;
+ regulator-name = "camera_vaf_ldo";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-enable-ramp-delay = <233>;
+ enable-active-high;
+ gpio = <&tlmm 72 0>;
+ vin-supply = <&BOB>;
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&qupv3_se0_i2c {
+ status = "ok";
+ qcom,clk-freq-out = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ stmvl53l3@29 {
+ compatible = "st,stmvl53l1";
+ reg = <0x29>;
+ vdd-supply = <&L8A>;
+ xsdn-gpio = <&tlmm 102 0>;
+ intr-gpio = <&tlmm 3 0>;
+ boot-reg = <0x29>;
+ status = "ok";
+ pinctrl-names = "stmvl53l1_active","stmvl53l1_suspend",
+ "stmvl53l1_release";
+ pinctrl-0 = <&stmvl53l1_active>;
+ pinctrl-1 = <&stmvl53l1_int_suspend &stmvl53l1_reset_suspend>;
+ pinctrl-2 = <&stmvl53l1_release>;
+ };
+};
+
+
+&cam_cci0 {
+ ois0: qcom,ois@0 {
+ cell-index = <0>;
+ reg = <0x0>;
+ compatible = "qcom,ois";
+ interrupt-parent = <&tlmm>;
+ interrupts = <24 0x1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vsync_default>;
+ cci-device = <0>;
+ cci-master = <0>;
+ interrupt-gpios = <&tlmm 24 0x1>;
+ cam_vaf-supply = <&L7P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <3140000>;
+ rgltr-max-voltage = <3140000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ actuator_triple_rear: qcom,actuator@5 {
+ cell-index = <5>;
+ reg = <0x5>;
+ compatible = "qcom,actuator";
+ cci-device = <0>;
+ cci-master = <0>;
+ cam_vaf-supply = <&L7P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <3140000>;
+ rgltr-max-voltage = <3140000>;
+ rgltr-load-current = <277000>;
+ status = "ok";
+ };
+
+ actuator_triple_rear_aux: qcom,actuator@4 {
+ cell-index = <4>;
+ reg = <0x4>;
+ compatible = "qcom,actuator";
+ cci-device = <0>;
+ cci-master = <1>;
+ cam_vaf-supply = <&camera_vaf_ldo>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ eeprom_triple_rear: qcom,eeprom@4 {
+ cell-index = <4>;
+ reg = <4>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L5P>;
+ cam_vdig-supply = <&L2P>;
+ cam_vaf-supply = <&L7P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ cam_v_custom1-supply = <&camera_vdig0_ldo1>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig","cam_vaf",
+ "cam_clk","cam_v_custom1";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2900000 1100000 3140000 0 1800000>;
+ rgltr-max-voltage = <1800000 2900000 1100000 3140000 0 1800000>;
+ rgltr-load-current = <120000 80000 105000 105000 0 120000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear0_reset_suspend>;
+ gpios = <&tlmm 29 0>,
+ <&tlmm 34 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ eeprom_triple_rear_aux: qcom,eeprom@1 {
+ cell-index = <1>;
+ reg = <1>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L1P>;
+ cam_vaf-supply = <&camera_vaf_ldo>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ cam_v_custom1-supply = <&camera_vdig2_ldo>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig","cam_vaf",
+ "cam_clk","cam_v_custom1";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2900000 1200000 2800000 0 1800000>;
+ rgltr-max-voltage = <1800000 2900000 1200000 2800000 0 1800000>;
+ rgltr-load-current = <120000 80000 105000 105000 0 105000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_rear1_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_rear1_reset_suspend>;
+ gpios = <&tlmm 31 0>,
+ <&tlmm 36 0>,
+ <&tlmm 38 0>;
+ gpio-reset = <1>;
+ gpio-standby = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET1",
+ "CAM_PWDN1";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@0 { //48M imx582 ois
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x0>;
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_triple_rear>;
+ ois-src = <&ois0>;
+ eeprom-src = <&eeprom_triple_rear>;
+ led-flash-src = <&led_flash_triple_rear>;
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L5P>;
+ cam_vdig-supply = <&L2P>;
+ cam_vaf-supply = <&L7P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ cam_v_custom1-supply = <&camera_vdig0_ldo1>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig","cam_vaf",
+ "cam_clk","cam_v_custom1";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2900000 1100000 3140000 0 1800000>;
+ rgltr-max-voltage = <1800000 2900000 1100000 3140000 0 1800000>;
+ rgltr-load-current = <120000 80000 105000 105000 0 120000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear0_reset_suspend>;
+ gpios = <&tlmm 29 0>,
+ <&tlmm 34 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ qcom,cam-sensor@1 { //48M imx582 uw
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x1>;
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_triple_rear_aux>;
+ eeprom-src = <&eeprom_triple_rear_aux>;
+ led-flash-src = <&led_flash_triple_rear_aux>;
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L1P>;
+ cam_vaf-supply = <&camera_vaf_ldo>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ cam_v_custom1-supply = <&camera_vdig2_ldo>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig","cam_vaf",
+ "cam_clk","cam_v_custom1";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2900000 1200000 2800000 0 1800000>;
+ rgltr-max-voltage = <1800000 2900000 1200000 2800000 0 1800000>;
+ rgltr-load-current = <120000 80000 105000 105000 0 105000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_rear1_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_rear1_reset_suspend>;
+ gpios = <&tlmm 31 0>,
+ <&tlmm 36 0>,
+ <&tlmm 38 0>;
+ gpio-reset = <1>;
+ gpio-standby = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET1",
+ "CAM_PWDN1";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
+&cam_cci1 {
+ eeprom_front: qcom,eeprom@5 {
+ cell-index = <5>;
+ reg = <5>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&camera_vdig1_ldo>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1050000 0>;
+ rgltr-max-voltage = <1800000 2800000 1050000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_front>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_front>;
+ gpios = <&tlmm 30 0>,
+ <&tlmm 35 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@2 { //imx 576
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x02>;
+ csiphy-sd-index = <3>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&camera_vdig1_ldo>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1050000 0>;
+ rgltr-max-voltage = <1800000 2800000 1050000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_front>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_front>;
+ gpios = <&tlmm 30 0>,
+ <&tlmm 35 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera-sensor-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera-sensor-qrd.dtsi
new file mode 100755
index 0000000..1bb08da
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera-sensor-qrd.dtsi
@@ -0,0 +1,421 @@
+#include <dt-bindings/clock/qcom,camcc-lagoon.h>
+
+&soc {
+ led_flash_triple_rear: qcom,camera-flash@4 {
+ cell-index = <4>;
+ reg = <0x04 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+ torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+ switch-source = <&pm6150l_switch2>;
+ };
+
+ led_flash_triple_rear_aux: qcom,camera-flash@5 {
+ cell-index = <5>;
+ reg = <0x05 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+ torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+ switch-source = <&pm6150l_switch2>;
+ };
+
+ led_flash_triple_rear_aux2: qcom,camera-flash@6 {
+ cell-index = <6>;
+ reg = <0x06 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm6150l_flash0 &pm6150l_flash1>;
+ torch-source = <&pm6150l_torch0 &pm6150l_torch1>;
+ switch-source = <&pm6150l_switch2>;
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_triple_rear: qcom,actuator@4 {
+ cell-index = <4>;
+ reg = <0x4>;
+ compatible = "qcom,actuator";
+ cci-device = <0>;
+ cci-master = <0>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ actuator_triple_rear_aux: qcom,actuator@5 {
+ cell-index = <5>;
+ reg = <0x5>;
+ compatible = "qcom,actuator";
+ cci-device = <0>;
+ cci-master = <1>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ eeprom_triple_rear: qcom,eeprom@4 {
+ cell-index = <4>;
+ reg = <4>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2904000 1104000 0 2800000>;
+ rgltr-max-voltage = <1800000 2904000 1104000 0 2800000>;
+ rgltr-load-current = <0 80000 105000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 29 0>,
+ <&tlmm 34 0>,
+ <&tlmm 50 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK4",
+ "CAM_RESET4",
+ "CAM_VANA4";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_rear_aux: qcom,eeprom@5 {
+ cell-index = <5>;
+ reg = <5>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>;
+ rgltr-load-current = <0 2000000 105000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 30 0>,
+ <&tlmm 35 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK5",
+ "CAM_RESET5";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@4 {
+ cell-index = <4>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x4>;
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_triple_rear>;
+ actuator-src = <&actuator_triple_rear>;
+ eeprom-src = <&eeprom_triple_rear>;
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ cam_v_custom1-supply = <&S2A>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_v_custom1";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2904000 1104000 0 2096000>;
+ rgltr-max-voltage = <1800000 2904000 1104000 0 2096000>;
+ rgltr-load-current = <0 80000 105000 0 80000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 29 0>,
+ <&tlmm 34 0>,
+ <&tlmm 50 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK4",
+ "CAM_RESET4",
+ "CAM_VANA4";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@5 {
+ cell-index = <5>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x5>;
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_triple_rear_aux>;
+ actuator-src = <&actuator_triple_rear_aux>;
+ eeprom-src = <&eeprom_triple_rear_aux>;
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 2000000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 30 0>,
+ <&tlmm 35 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK5",
+ "CAM_RESET5";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
+&cam_cci1 {
+ actuator_triple_rear_aux2: qcom,actuator@6 {
+ cell-index = <6>;
+ reg = <0x6>;
+ compatible = "qcom,actuator";
+ cci-device = <1>;
+ cci-master = <0>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ eeprom_front: qcom,eeprom@2 {
+ cell-index = <2>;
+ reg = <0x2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_front>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_front>;
+ gpios = <&tlmm 32 0>,
+ <&tlmm 37 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_rear_aux2: qcom,eeprom@6 {
+ cell-index = <6>;
+ reg = <6>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L7P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>;
+ rgltr-load-current = <0 80000 105000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rear_aux2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rear_aux2>;
+ gpios = <&tlmm 31 0>,
+ <&tlmm 36 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x02>;
+ csiphy-sd-index = <3>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_front>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_front>;
+ gpios = <&tlmm 32 0>,
+ <&tlmm 37 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@6 {
+ cell-index = <6>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x06>;
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_triple_rear_aux2>;
+ actuator-src = <&actuator_triple_rear_aux2>;
+ eeprom-src = <&eeprom_triple_rear_aux2>;
+ cam_vio-supply = <&L6P>;
+ cam_vana-supply = <&L7P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_rear_aux2>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_rear_aux2>;
+ gpios = <&tlmm 31 0>,
+ <&tlmm 36 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK6",
+ "CAM_RESET6";
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera.dtsi
new file mode 100755
index 0000000..9850a58
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/lagoon-camera.dtsi
@@ -0,0 +1,1496 @@
+#include <dt-bindings/msm/msm-camera.h>
+
+&soc {
+ qcom,cam-req-mgr {
+ compatible = "qcom,cam-req-mgr";
+ status = "ok";
+ };
+
+ cam_csiphy0: qcom,csiphy0 {
+ cell-index = <0>;
+ compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
+ reg = <0x0ac65000 0x1000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x65000>;
+ interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr", "refgen", "mipi-csi-vdd1",
+ "mipi-csi-vdd2";
+ gdscr-supply = <&cam_cc_titan_top_gdsc>;
+ refgen-supply = <&refgen>;
+ mipi-csi-vdd1-supply = <&L18A>;
+ mipi-csi-vdd2-supply = <&L22A>;
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <0 0 880000 1200000>;
+ rgltr-max-voltage = <0 0 1049000 1305000>;
+ rgltr-load-current = <0 0 80000 80000>;
+ clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy0_clk",
+ "csi0phytimer_clk_src",
+ "csi0phytimer_clk";
+ src-clock-name = "csi0phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1";
+ clock-rates =
+ <300000000 0 300000000 0>,
+ <384000000 0 300000000 0>,
+ <400000000 0 300000000 0>;
+ status = "ok";
+ };
+
+ cam_csiphy1: qcom,csiphy1 {
+ cell-index = <1>;
+ compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
+ reg = <0xac66000 0x1000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x66000>;
+ interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr", "refgen", "mipi-csi-vdd1",
+ "mipi-csi-vdd2";
+ gdscr-supply = <&cam_cc_titan_top_gdsc>;
+ refgen-supply = <&refgen>;
+ mipi-csi-vdd1-supply = <&L18A>;
+ mipi-csi-vdd2-supply = <&L22A>;
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <0 0 880000 1200000>;
+ rgltr-max-voltage = <0 0 1049000 1305000>;
+ rgltr-load-current = <0 0 80000 80000>;
+ clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy1_clk",
+ "csi1phytimer_clk_src",
+ "csi1phytimer_clk";
+ src-clock-name = "csi1phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1";
+ clock-rates =
+ <300000000 0 300000000 0>,
+ <384000000 0 300000000 0>,
+ <400000000 0 300000000 0>;
+ status = "ok";
+ };
+
+ cam_csiphy2: qcom,csiphy2 {
+ cell-index = <2>;
+ compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
+ reg = <0xac67000 0x1000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x67000>;
+ interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr", "refgen", "mipi-csi-vdd1",
+ "mipi-csi-vdd2";
+ gdscr-supply = <&cam_cc_titan_top_gdsc>;
+ refgen-supply = <&refgen>;
+ mipi-csi-vdd1-supply = <&L18A>;
+ mipi-csi-vdd2-supply = <&L22A>;
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <0 0 880000 1200000>;
+ rgltr-max-voltage = <0 0 1049000 1305000>;
+ rgltr-load-current = <0 0 80000 80000>;
+ clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy2_clk",
+ "csi2phytimer_clk_src",
+ "csi2phytimer_clk";
+ src-clock-name = "csi2phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1";
+ clock-rates =
+ <300000000 0 300000000 0>,
+ <384000000 0 300000000 0>,
+ <400000000 0 300000000 0>;
+ status = "ok";
+ };
+
+ cam_csiphy3: qcom,csiphy3 {
+ cell-index = <3>;
+ compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy";
+ reg = <0xac68000 0x1000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x68000>;
+ interrupts = <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr", "refgen", "mipi-csi-vdd1",
+ "mipi-csi-vdd2";
+ gdscr-supply = <&cam_cc_titan_top_gdsc>;
+ refgen-supply = <&refgen>;
+ mipi-csi-vdd1-supply = <&L18A>;
+ mipi-csi-vdd2-supply = <&L22A>;
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <0 0 880000 1200000>;
+ rgltr-max-voltage = <0 0 1049000 1305000>;
+ rgltr-load-current = <0 0 80000 80000>;
+ clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy3_clk",
+ "csi3phytimer_clk_src",
+ "csi3phytimer_clk";
+ src-clock-name = "csi3phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1";
+ clock-rates =
+ <300000000 0 300000000 0>,
+ <384000000 0 300000000 0>,
+ <400000000 0 300000000 0>;
+ status = "ok";
+ };
+
+ cam_cci0: qcom,cci0 {
+ cell-index = <0>;
+ compatible = "qcom,cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xac4a000 0x1000>;
+ reg-names = "cci";
+ reg-cam-base = <0x4a000>;
+ interrupt-names = "cci";
+ interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>;
+ status = "ok";
+ gdscr-supply = <&cam_cc_titan_top_gdsc>;
+ regulator-names = "gdscr";
+ clocks = <&camcc CAM_CC_CCI_0_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK_SRC>;
+ clock-names = "cci_0_clk",
+ "cci_0_clk_src";
+ src-clock-name = "cci_0_clk_src";
+ clock-cntl-level = "lowsvs";
+ clock-rates = <0 37500000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cci0_active &cci1_active>;
+ pinctrl-1 = <&cci0_suspend &cci1_suspend>;
+ gpios = <&tlmm 39 0>,
+ <&tlmm 40 0>,
+ <&tlmm 41 0>,
+ <&tlmm 42 0>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 1 1 1>;
+ gpio-req-tbl-label = "CCI_I2C_DATA0",
+ "CCI_I2C_CLK0",
+ "CCI_I2C_DATA1",
+ "CCI_I2C_CLK1";
+
+ i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
+ hw-thigh = <201>;
+ hw-tlow = <174>;
+ hw-tsu-sto = <204>;
+ hw-tsu-sta = <231>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <162>;
+ hw-tbuf = <227>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_custom_cci0: qcom,i2c_custom_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <1>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
+ hw-thigh = <16>;
+ hw-tlow = <22>;
+ hw-tsu-sto = <17>;
+ hw-tsu-sta = <18>;
+ hw-thd-dat = <16>;
+ hw-thd-sta = <15>;
+ hw-tbuf = <24>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <3>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+ };
+
+ cam_cci1: qcom,cci1 {
+ cell-index = <1>;
+ compatible = "qcom,cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xac4b000 0x1000>;
+ reg-names = "cci";
+ reg-cam-base = <0x4b000>;
+ interrupt-names = "cci";
+ interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
+ status = "ok";
+ gdscr-supply = <&cam_cc_titan_top_gdsc>;
+ regulator-names = "gdscr";
+ clocks = <&camcc CAM_CC_CCI_1_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK_SRC>;
+ clock-names = "cci_clk",
+ "cci_1_clk_src";
+ src-clock-name = "cci_1_clk_src";
+ clock-cntl-level = "lowsvs";
+ clock-rates = <0 37500000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cci2_active>;
+ pinctrl-1 = <&cci2_suspend>;
+ gpios = <&tlmm 43 0>,
+ <&tlmm 44 0>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 1>;
+ gpio-req-tbl-label = "CCI_I2C_DATA2",
+ "CCI_I2C_CLK2";
+
+ i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {
+ hw-thigh = <201>;
+ hw-tlow = <174>;
+ hw-tsu-sto = <204>;
+ hw-tsu-sta = <231>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <162>;
+ hw-tbuf = <227>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_custom_cci1: qcom,i2c_custom_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <1>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {
+ hw-thigh = <16>;
+ hw-tlow = <22>;
+ hw-tsu-sto = <17>;
+ hw-tsu-sta = <18>;
+ hw-thd-dat = <16>;
+ hw-thd-sta = <15>;
+ hw-tbuf = <24>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <3>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+ };
+
+ qcom,cam_smmu {
+ compatible = "qcom,msm-cam-smmu";
+ status = "ok";
+ non-fatal-fault-disabled;
+
+ msm_cam_smmu_lrme {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0xD40 0x20>,
+ <&apps_smmu 0xD60 0x20>;
+ label = "lrme";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ lrme_iova_mem_map: iova-mem-map {
+ iova-mem-region-shared {
+ /* Shared region is 100MB long */
+ iova-region-name = "shared";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0x6400000>;
+ iova-region-id = <0x1>;
+ status = "ok";
+ };
+ /* IO region is approximately 3.3 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0xd800000>;
+ iova-region-len = <0xd2800000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_ife {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x820 0xc0>,
+ <&apps_smmu 0x840 0x0>,
+ <&apps_smmu 0x860 0xc0>,
+ <&apps_smmu 0x880 0x0>;
+ label = "ife";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ ife_iova_mem_map: iova-mem-map {
+ /* IO region is approximately 3.4 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_jpeg {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0xD00 0x20>,
+ <&apps_smmu 0xD20 0x20>;
+ label = "jpeg";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ jpeg_iova_mem_map: iova-mem-map {
+ /* IO region is approximately 3.4 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_icp_fw {
+ compatible = "qcom,msm-cam-smmu-fw-dev";
+ label="icp";
+ memory-region = <&pil_camera_mem>;
+ };
+
+ msm_cam_smmu_icp {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0xCA2 0x0>,
+ <&apps_smmu 0xC40 0x20>,
+ <&apps_smmu 0xC60 0x20>,
+ <&apps_smmu 0xCC0 0x20>,
+ <&apps_smmu 0xCE0 0x20>;
+ label = "icp";
+ qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>;
+ iova-region-discard = <0xdff00000 0x300000>;
+ icp_iova_mem_map: iova-mem-map {
+ iova-mem-region-firmware {
+ /* Firmware region is 5MB */
+ iova-region-name = "firmware";
+ iova-region-start = <0x0>;
+ iova-region-len = <0x500000>;
+ iova-region-id = <0x0>;
+ status = "ok";
+ };
+
+ iova-mem-region-shared {
+ /* Shared region is 150MB long */
+ iova-region-name = "shared";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0x9600000>;
+ iova-region-id = <0x1>;
+ iova-granularity = <0x15>;
+ status = "ok";
+ };
+
+ iova-mem-region-secondary-heap {
+ /* Secondary heap region is 1MB long */
+ iova-region-name = "secheap";
+ iova-region-start = <0x10A00000>;
+ iova-region-len = <0x100000>;
+ iova-region-id = <0x4>;
+ status = "ok";
+ };
+
+ iova-mem-region-io {
+ /* IO region is approximately 3.7 GB */
+ iova-region-name = "io";
+ iova-region-start = <0x10C00000>;
+ iova-region-len = <0xee300000>;
+ iova-region-id = <0x3>;
+ iova-region-discard = <0xdff00000 0x300000>;
+ status = "ok";
+ };
+
+ iova-mem-qdss-region {
+ /* qdss region is approximately 1MB */
+ iova-region-name = "qdss";
+ iova-region-start = <0x10B00000>;
+ iova-region-len = <0x100000>;
+ iova-region-id = <0x5>;
+ qdss-phy-addr = <0x16790000>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_cpas_cdm {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0xC80 0x0>;
+ label = "cpas-cdm0";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ cpas_cdm_iova_mem_map: iova-mem-map {
+ iova-mem-region-io {
+ /* IO region is approximately 3.4 GB */
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_secure {
+ compatible = "qcom,msm-cam-smmu-cb";
+ label = "cam-secure";
+ qcom,secure-cb;
+ };
+
+ };
+
+ qcom,cam-cdm-intf {
+ compatible = "qcom,cam-cdm-intf";
+ cell-index = <0>;
+ label = "cam-cdm-intf";
+ num-hw-cdm = <1>;
+ cdm-client-names = "vfe",
+ "jpegdma",
+ "jpegenc",
+ "lrmecdm";
+ status = "ok";
+ };
+
+ qcom,cpas-cdm0@ac48000 {
+ cell-index = <0>;
+ compatible = "qcom,cam170-cpas-cdm0";
+ label = "cpas-cdm";
+ reg = <0xac48000 0x1000>;
+ reg-names = "cpas-cdm";
+ reg-cam-base = <0x48000>;
+ interrupts = <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "cpas-cdm";
+ regulator-names = "camss";
+ camss-supply = <&cam_cc_titan_top_gdsc>;
+ clock-names =
+ "cam_cc_soc_ahb_clk",
+ "cam_cc_cpas_ahb_clk",
+ "cam_cc_camnoc_axi_clk";
+ clocks =
+ <&camcc CAM_CC_SOC_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_CLK>;
+ clock-rates = <0 0 0>;
+ clock-cntl-level = "svs";
+ cdm-client-names = "ife";
+ status = "ok";
+ };
+
+ qcom,cam-isp {
+ compatible = "qcom,cam-isp";
+ arch-compat = "ife";
+ status = "ok";
+ };
+
+ cam_csid0: qcom,csid0@acb3000 {
+ cell-index = <0>;
+ compatible = "qcom,csid170_200";
+ reg-names = "csid";
+ reg = <0xacb3000 0x1000>;
+ reg-cam-base = <0xb3000>;
+ interrupt-names = "csid0";
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss", "ife0";
+ camss-supply = <&cam_cc_titan_top_gdsc>;
+ ife0-supply = <&cam_cc_ife_0_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_clk",
+ "ife_axi_clk";
+ clocks =
+ <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK_SRC>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>;
+ clock-rates =
+ <300000000 0 0 0 320000000 0 0>,
+ <384000000 0 0 0 404000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 600000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ status = "ok";
+ };
+
+ cam_vfe0: qcom,vfe0@acaf000 {
+ cell-index = <0>;
+ compatible = "qcom,vfe170_150";
+ reg-names = "ife";
+ reg = <0xacaf000 0x4000>;
+ reg-cam-base = <0xaf000>;
+ interrupt-names = "ife0";
+ interrupts = <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss", "ife0";
+ camss-supply = <&cam_cc_titan_top_gdsc>;
+ ife0-supply = <&cam_cc_ife_0_gdsc>;
+ clock-names =
+ "ife_clk_src",
+ "ife_clk",
+ "ife_axi_clk";
+ clocks =
+ <&camcc CAM_CC_IFE_0_CLK_SRC>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>;
+ clock-rates =
+ <320000000 0 0>,
+ <404000000 0 0>,
+ <480000000 0 0>,
+ <600000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ clock-names-option = "ife_dsp_clk";
+ clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>;
+ clock-rates-option = <600000000>;
+ qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>;
+ status = "ok";
+ };
+
+ cam_csid1: qcom,csid1@acba000 {
+ cell-index = <1>;
+ compatible = "qcom,csid170_200";
+ reg-names = "csid";
+ reg = <0xacba000 0x1000>;
+ reg-cam-base = <0xba000>;
+ interrupt-names = "csid1";
+ interrupts = <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss", "ife1";
+ camss-supply = <&cam_cc_titan_top_gdsc>;
+ ife1-supply = <&cam_cc_ife_1_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_clk",
+ "ife_axi_clk";
+ clocks =
+ <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK_SRC>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>;
+ clock-rates =
+ <300000000 0 0 0 320000000 0 0>,
+ <384000000 0 0 0 404000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 600000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ status = "ok";
+ };
+
+ cam_vfe1: qcom,vfe1@acb6000 {
+ cell-index = <1>;
+ compatible = "qcom,vfe170_150";
+ reg-names = "ife";
+ reg = <0xacb6000 0x4000>;
+ reg-cam-base = <0xb6000>;
+ interrupt-names = "ife1";
+ interrupts = <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss", "ife1";
+ camss-supply = <&cam_cc_titan_top_gdsc>;
+ ife1-supply = <&cam_cc_ife_1_gdsc>;
+ clock-names =
+ "ife_clk_src",
+ "ife_clk",
+ "ife_axi_clk";
+ clocks =
+ <&camcc CAM_CC_IFE_1_CLK_SRC>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>;
+ clock-rates =
+ <320000000 0 0>,
+ <404000000 0 0>,
+ <480000000 0 0>,
+ <600000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ clock-names-option = "ife_dsp_clk";
+ clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>;
+ clock-rates-option = <600000000>;
+ qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>;
+ status = "ok";
+ };
+
+ cam_csid2: qcom,csid2@acc1000 {
+ cell-index = <2>;
+ compatible = "qcom,csid170_200";
+ reg-names = "csid2";
+ reg = <0xacc1000 0x1000>;
+ reg-cam-base = <0xc1000>;
+ interrupt-names = "csid";
+ interrupts = <GIC_SPI 717 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss", "ife2";
+ camss-supply = <&cam_cc_titan_top_gdsc>;
+ ife2-supply = <&cam_cc_ife_2_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_clk",
+ "ife_axi_clk";
+ clocks =
+ <&camcc CAM_CC_IFE_2_CSID_CLK_SRC>,
+ <&camcc CAM_CC_IFE_2_CSID_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_2_CLK_SRC>,
+ <&camcc CAM_CC_IFE_2_CLK>,
+ <&camcc CAM_CC_IFE_2_AXI_CLK>;
+ clock-rates =
+ <300000000 0 0 0 320000000 0 0>,
+ <384000000 0 0 0 404000000 0 0>,
+ <400000000 0 0 0 480000000 0 0>,
+ <400000000 0 0 0 600000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ status = "ok";
+ };
+
+ cam_vfe2: qcom,vfe2@acbd000 {
+ cell-index = <2>;
+ compatible = "qcom,vfe170_150";
+ reg-names = "ife2";
+ reg = <0xacbd000 0x4000>;
+ reg-cam-base = <0xbd000>;
+ interrupt-names = "ife";
+ interrupts = <GIC_SPI 718 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss", "ife2";
+ camss-supply = <&cam_cc_titan_top_gdsc>;
+ ife2-supply = <&cam_cc_ife_2_gdsc>;
+ clock-names =
+ "ife_clk_src",
+ "ife_clk",
+ "ife_axi_clk";
+ clocks =
+ <&camcc CAM_CC_IFE_2_CLK_SRC>,
+ <&camcc CAM_CC_IFE_2_CLK>,
+ <&camcc CAM_CC_IFE_2_AXI_CLK>;
+ clock-rates =
+ <320000000 0 0>,
+ <404000000 0 0>,
+ <480000000 0 0>,
+ <600000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ clock-names-option = "ife_dsp_clk";
+ clocks-option = <&camcc CAM_CC_IFE_2_DSP_CLK>;
+ clock-rates-option = <600000000>;
+ dsp-disabled;
+ qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>;
+ status = "ok";
+ };
+
+ cam_csid_lite: qcom,csid-lite@acc8000 {
+ cell-index = <3>;
+ compatible = "qcom,csid-lite170";
+ reg-names = "csid-lite";
+ reg = <0xacc8000 0x1000>;
+ reg-cam-base = <0xc8000>;
+ interrupt-names = "csid-lite";
+ interrupts = <GIC_SPI 473 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&cam_cc_titan_top_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_clk";
+ clocks =
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <300000000 0 0 0 320000000 0>,
+ <384000000 0 0 0 400000000 0>,
+ <400000000 0 0 0 480000000 0>,
+ <400000000 0 0 0 600000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ status = "ok";
+ };
+
+ cam_vfe_lite: qcom,vfe-lite@acc4000 {
+ cell-index = <3>;
+ compatible = "qcom,vfe-lite170";
+ reg-names = "ife-lite";
+ reg = <0xacc4000 0x4000>;
+ reg-cam-base = <0xc4000>;
+ interrupt-names = "ife-lite";
+ interrupts = <GIC_SPI 472 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&cam_cc_titan_top_gdsc>;
+ clock-names =
+ "ife_clk_src",
+ "ife_clk";
+ clocks =
+ <&camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <320000000 0>,
+ <400000000 0>,
+ <480000000 0>,
+ <600000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>;
+ status = "ok";
+ };
+
+ qcom,cam-icp {
+ compatible = "qcom,cam-icp";
+ compat-hw-name = "qcom,a5",
+ "qcom,ipe0",
+ "qcom,bps";
+ num-a5 = <1>;
+ num-ipe = <1>;
+ num-bps = <1>;
+ icp_pc_en;
+ status = "ok";
+ };
+
+ cam_a5: qcom,a5@ac00000 {
+ cell-index = <0>;
+ compatible = "qcom,cam-a5";
+ reg = <0xac00000 0x6000>,
+ <0xac10000 0x8000>,
+ <0xac18000 0x3000>;
+ reg-names = "a5_qgic", "a5_sierra", "a5_csr";
+ reg-cam-base = <0x00000 0x10000 0x18000>;
+ interrupts = <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a5";
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
+ clock-names =
+ "soc_fast_ahb",
+ "soc_ahb_clk",
+ "icp_clk",
+ "icp_clk_src";
+ src-clock-name = "icp_clk_src";
+ clocks =
+ <&camcc CAM_CC_FAST_AHB_CLK_SRC>,
+ <&camcc CAM_CC_SOC_AHB_CLK>,
+ <&camcc CAM_CC_ICP_CLK>,
+ <&camcc CAM_CC_ICP_CLK_SRC>;
+
+ clock-rates =
+ <100000000 0 0 384000000>,
+ <200000000 0 0 404000000>,
+ <300000000 0 0 600000000>,
+ <404000000 0 0 600000000>,
+ <404000000 0 0 600000000>;
+ clock-cntl-level = "lowsvs", "svs",
+ "svs_l1", "nominal", "turbo";
+ fw_name = "CAMERA_ICP.elf";
+ ubwc-cfg = <0x73 0x1CF>;
+ status = "ok";
+ };
+
+ cam_ipe0: qcom,ipe0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-ipe";
+ reg = <0xac87000 0xa000>;
+ reg-names = "ipe0_top";
+ reg-cam-base = <0x87000>;
+ regulator-names = "ipe0-vdd";
+ ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>;
+ clock-names =
+ "ipe_0_ahb_clk",
+ "ipe_0_areg_clk",
+ "ipe_0_axi_clk",
+ "ipe_0_clk",
+ "ipe_0_clk_src";
+ src-clock-name = "ipe_0_clk_src";
+ clocks = <&camcc CAM_CC_IPE_0_AHB_CLK>,
+ <&camcc CAM_CC_IPE_0_AREG_CLK>,
+ <&camcc CAM_CC_IPE_0_AXI_CLK>,
+ <&camcc CAM_CC_IPE_0_CLK>,
+ <&camcc CAM_CC_IPE_0_CLK_SRC>;
+
+ clock-rates =
+ <0 0 0 0 240000000>,
+ <0 0 0 0 320000000>,
+ <0 0 0 0 404000000>,
+ <0 0 0 0 538666666>,
+ <0 0 0 0 600000000>;
+ clock-cntl-level = "lowsvs", "svs",
+ "svs_l1", "nominal", "turbo";
+ qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>;
+ status = "ok";
+ };
+
+ cam_bps: qcom,bps {
+ cell-index = <0>;
+ compatible = "qcom,cam-bps";
+ reg = <0xac6f000 0x8000>;
+ reg-names = "bps_top";
+ reg-cam-base = <0x6f000>;
+ regulator-names = "bps-vdd";
+ bps-vdd-supply = <&cam_cc_bps_gdsc>;
+ clock-names = "bps_ahb_clk",
+ "bps_areg_clk",
+ "bps_axi_clk",
+ "bps_clk",
+ "bps_clk_src";
+ src-clock-name = "bps_clk_src";
+ clocks =
+ <&camcc CAM_CC_BPS_AHB_CLK>,
+ <&camcc CAM_CC_BPS_AREG_CLK>,
+ <&camcc CAM_CC_BPS_AXI_CLK>,
+ <&camcc CAM_CC_BPS_CLK>,
+ <&camcc CAM_CC_BPS_CLK_SRC>;
+
+ clock-rates =
+ <0 0 0 0 200000000>,
+ <0 0 0 0 404000000>,
+ <0 0 0 0 480000000>,
+ <0 0 0 0 600000000>,
+ <0 0 0 0 600000000>;
+ clock-cntl-level = "lowsvs", "svs",
+ "svs_l1", "nominal", "turbo";
+ qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>;
+ status = "ok";
+ };
+
+ qcom,cam-jpeg {
+ compatible = "qcom,cam-jpeg";
+ compat-hw-name = "qcom,jpegenc",
+ "qcom,jpegdma";
+ num-jpeg-enc = <1>;
+ num-jpeg-dma = <1>;
+ status = "ok";
+ };
+
+ cam_jpeg_enc: qcom,jpegenc@ac4e000 {
+ cell-index = <0>;
+ compatible = "qcom,cam_jpeg_enc";
+ reg-names = "jpege_hw";
+ reg = <0xac4e000 0x4000>;
+ reg-cam-base = <0x4e000>;
+ interrupt-names = "jpeg";
+ interrupts = <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
+ clock-names =
+ "jpegenc_clk_src",
+ "jpegenc_clk";
+ clocks =
+ <&camcc CAM_CC_JPEG_CLK_SRC>,
+ <&camcc CAM_CC_JPEG_CLK>;
+
+ clock-rates =
+ <600000000 0>;
+ src-clock-name = "jpegenc_clk_src";
+ clock-cntl-level = "nominal";
+ status = "ok";
+ };
+
+ cam_jpeg_dma: qcom,jpegdma@0xac52000 {
+ cell-index = <0>;
+ compatible = "qcom,cam_jpeg_dma";
+ reg-names = "jpegdma_hw";
+ reg = <0xac52000 0x4000>;
+ reg-cam-base = <0x52000>;
+ interrupt-names = "jpegdma";
+ interrupts = <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
+ clock-names =
+ "jpegdma_clk_src",
+ "jpegdma_clk";
+ clocks =
+ <&camcc CAM_CC_JPEG_CLK_SRC>,
+ <&camcc CAM_CC_JPEG_CLK>;
+
+ clock-rates =
+ <600000000 0>;
+ src-clock-name = "jpegdma_clk_src";
+ clock-cntl-level = "nominal";
+ status = "ok";
+ };
+
+ qcom,cam-lrme {
+ compatible = "qcom,cam-lrme";
+ arch-compat = "lrme";
+ status = "ok";
+ };
+
+ cam_lrme: qcom,lrme@ac6b000 {
+ cell-index = <0>;
+ compatible = "qcom,lrme";
+ reg-names = "lrme";
+ reg = <0xac6b000 0xa00>;
+ reg-cam-base = <0x6b000>;
+ interrupt-names = "lrme";
+ interrupts = <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&cam_cc_titan_top_gdsc>;
+ clock-names =
+ "lrme_clk_src",
+ "lrme_clk";
+ clocks =
+ <&camcc CAM_CC_LRME_CLK_SRC>,
+ <&camcc CAM_CC_LRME_CLK>;
+ clock-rates =
+ <200000000 0>,
+ <269333333 0>,
+ <323200000 0>,
+ <404000000 0>,
+ <404000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
+ "turbo";
+ src-clock-name = "lrme_clk_src";
+ status = "ok";
+ };
+
+ qcom,cam-cpas@ac40000 {
+ cell-index = <0>;
+ compatible = "qcom,cam-cpas";
+ label = "cpas";
+ arch-compat = "cpas_top";
+ status = "ok";
+ reg-names = "cam_cpas_top", "cam_camnoc", "core_top_csr_tcsr";
+ reg = <0xac40000 0x1000>,
+ <0xac42000 0x4600>,
+ <0x01fc0000 0x40000>;
+ reg-cam-base = <0x40000 0x42000 0x0>;
+ interrupt-names = "cpas_camnoc";
+ interrupts = <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>;
+ qcom,cpas-hw-ver = <0x170200>; /* Titan v170 v2.0.0 */
+ camnoc-axi-min-ib-bw = <3000000000>;
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
+ clock-names =
+ "gcc_ahb_clk",
+ "gcc_axi_clk",
+ "soc_ahb_clk",
+ "slow_ahb_clk_src",
+ "cpas_ahb_clk",
+ "camnoc_axi_clk";
+ clocks =
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_AXI_CLK>,
+ <&camcc CAM_CC_SOC_AHB_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_CLK>;
+ src-clock-name = "slow_ahb_clk_src";
+ clock-rates =
+ <0 0 0 0 0 0>,
+ <0 0 0 80000000 0 0>,
+ <0 0 0 80000000 0 0>,
+ <0 0 0 80000000 0 0>,
+ <0 0 0 80000000 0 0>,
+ <0 0 0 80000000 0 0>;
+ clock-cntl-level = "suspend", "lowsvs", "svs",
+ "svs_l1", "nominal", "turbo";
+ qcom,cam-cx-ipeak = <&cx_ipeak_lm 3>;
+ qcom,msm-bus,name = "cam_ahb";
+ qcom,msm-bus,num-cases = <7>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 120000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 300000>;
+ vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
+ RPMH_REGULATOR_LEVEL_MIN_SVS
+ RPMH_REGULATOR_LEVEL_LOW_SVS
+ RPMH_REGULATOR_LEVEL_SVS
+ RPMH_REGULATOR_LEVEL_SVS_L1
+ RPMH_REGULATOR_LEVEL_NOM
+ RPMH_REGULATOR_LEVEL_NOM_L1
+ RPMH_REGULATOR_LEVEL_NOM_L2
+ RPMH_REGULATOR_LEVEL_TURBO
+ RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ vdd-corner-ahb-mapping = "suspend",
+ "minsvs", "lowsvs", "svs", "svs_l1",
+ "nominal", "nominal", "nominal",
+ "turbo", "turbo";
+ client-id-based;
+ client-names =
+ "csiphy0", "csiphy1", "csiphy2", "csiphy3", "cci0",
+ "cci1", "csid0", "csid1", "csid2", "csid3",
+ "ife0", "ife1", "ife2", "ife3", "ipe0",
+ "cam-cdm-intf0", "cpas-cdm0", "bps0",
+ "icp0", "jpeg-dma0", "jpeg-enc0", "lrmecpas0";
+
+ camera-bus-nodes {
+ level3-nodes {
+ level-index = <3>;
+ level3_rt0_wr_sum: level3-rt0-wr-sum {
+ cell-index = <0>;
+ node-name = "level3-rt0-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_hf_0";
+ ib-bw-voting-needed;
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_hf_0_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_HF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_HF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+
+ qcom,axi-port-camnoc {
+ qcom,msm-bus,name =
+ "cam_hf_0_camnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_HF0_UNCOMP
+ MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_HF0_UNCOMP
+ MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>;
+ };
+ };
+
+ level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum {
+ cell-index = <1>;
+ node-name = "level3-nrt0-rd-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_sf_0";
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_sf_0_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_SF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_SF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+
+ qcom,axi-port-camnoc {
+ qcom,msm-bus,name =
+ "cam_sf_0_camnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_SF_UNCOMP
+ MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_SF_UNCOMP
+ MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>;
+ };
+ };
+
+ level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum {
+ cell-index = <2>;
+ node-name = "level3-nrt1-rd-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_sf_icp";
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_sf_icp_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_ICP
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_ICP
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+
+ qcom,axi-port-camnoc {
+ qcom,msm-bus,name =
+ "cam_sf_icp_camnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_ICP_UNCOMP
+ MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_ICP_UNCOMP
+ MSM_BUS_SLAVE_CAMNOC_UNCOMP 0 0>;
+ };
+ };
+ };
+
+ level2-nodes {
+ level-index = <2>;
+ level2_rt0_wr: level2-rt0-wr {
+ cell-index = <3>;
+ node-name = "level2-rt0-wr";
+ parent-node = <&level3_rt0_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
+ };
+
+ level2_nrt0_rd_wr: level2-nrt0-rd-wr {
+ cell-index = <4>;
+ node-name = "level2-nrt0-rd-wr";
+ parent-node = <&level3_nrt0_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level2_nrt1_rd: level2-nrt1-rd {
+ cell-index = <5>;
+ node-name = "level2-nrt1-rd";
+ parent-node = <&level3_nrt1_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ bus-width-factor = <4>;
+ };
+ };
+
+ level1-nodes {
+ level-index = <1>;
+ level1_rt0_wr: level1-rt0-wr {
+ cell-index = <6>;
+ node-name = "level1-rt0-wr";
+ parent-node = <&level2_rt0_wr>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_rt1_wr: level1-rt1-wr {
+ cell-index = <7>;
+ node-name = "level1-rt1-wr";
+ parent-node = <&level2_rt0_wr>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_nrt0_wr: level1-nrt0-wr {
+ cell-index = <8>;
+ node-name = "level1-nrt0-wr";
+ parent-node = <&level2_nrt0_rd_wr>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_nrt0_rd: level1-nrt0-rd {
+ cell-index = <9>;
+ node-name = "level1-nrt0-rd";
+ parent-node = <&level2_nrt0_rd_wr>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+ };
+
+ level0-nodes {
+ level-index = <0>;
+
+ ife0_rdi_all_wr: ife0-rdi-all-wr {
+ cell-index = <10>;
+ node-name = "ife0-rdi-all-wr";
+ client-name = "ife0";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt0_wr>;
+ };
+
+ ife1_rdi_all_wr: ife1-rdi-all-wr {
+ cell-index = <11>;
+ node-name = "ife1-rdi-all-wr";
+ client-name = "ife1";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt0_wr>;
+ };
+
+ ife2_rdi_all_wr: ife2-rdi-all-wr {
+ cell-index = <12>;
+ node-name = "ife2-rdi-all-wr";
+ client-name = "ife2";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt1_wr>;
+ };
+
+ ife3_rdi_all_wr: ife3-rdi-all-wr {
+ cell-index = <13>;
+ node-name = "ife3-rdi-all-wr";
+ client-name = "ife3";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt1_wr>;
+ };
+
+ ife0_pixelall_wr: ife0-pixelall-wr {
+ cell-index = <14>;
+ node-name = "ife0-pixelall-wr";
+ client-name = "ife0";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_PIXEL_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_LINEAR
+ CAM_CPAS_PATH_DATA_IFE_PDAF
+ CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS
+ CAM_CPAS_PATH_DATA_IFE_PIXEL_RAW>;
+ parent-node = <&level1_rt0_wr>;
+ };
+
+ ife1_pixelall_wr: ife1-pixelall-wr {
+ cell-index = <15>;
+ node-name = "ife1-pixelall-wr";
+ client-name = "ife1";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_PIXEL_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_LINEAR
+ CAM_CPAS_PATH_DATA_IFE_PDAF
+ CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS
+ CAM_CPAS_PATH_DATA_IFE_PIXEL_RAW>;
+ parent-node = <&level1_rt0_wr>;
+ };
+
+ ife2_pixelall_wr: ife2-pixelall-wr {
+ cell-index = <16>;
+ node-name = "ife2-pixelall-wr";
+ client-name = "ife2";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_PIXEL_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_LINEAR
+ CAM_CPAS_PATH_DATA_IFE_PDAF
+ CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS
+ CAM_CPAS_PATH_DATA_IFE_PIXEL_RAW>;
+ parent-node = <&level1_rt1_wr>;
+ };
+
+ bps0_all_wr: bps0-all-wr {
+ cell-index = <17>;
+ node-name = "bps0-all-wr";
+ client-name = "bps0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level1_nrt0_wr>;
+ };
+
+ bps0_all_rd: bps0-all-rd {
+ cell-index = <18>;
+ node-name = "bps0-all-rd";
+ client-name = "bps0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_rd>;
+ };
+
+ ipe0_all_rd: ipe0-all-rd {
+ cell-index = <19>;
+ node-name = "ipe0-all-rd";
+ client-name = "ipe0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IPE_RD_IN
+ CAM_CPAS_PATH_DATA_IPE_RD_REF>;
+ parent-node = <&level1_nrt0_rd>;
+ };
+
+ ipe0_all_wr: ipe0-all-wr {
+ cell-index = <20>;
+ node-name = "ipe0-all-wr";
+ client-name = "ipe0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IPE_WR_VID
+ CAM_CPAS_PATH_DATA_IPE_WR_DISP
+ CAM_CPAS_PATH_DATA_IPE_WR_REF>;
+ parent-node = <&level1_nrt0_wr>;
+ };
+
+ lrme0_all_rd: lrme0-all-rd {
+ cell-index = <21>;
+ node-name = "lrme0-all-rd";
+ client-name = "lrmecpas0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_rd>;
+ };
+
+ lrme0_all_wr: lrme0-all-wr {
+ cell-index = <22>;
+ node-name = "lrme0-all-wr";
+ client-name = "lrmecpas0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level1_nrt0_wr>;
+ };
+
+ cpas_cdm0_all_rd: cpas-cdm0-all-rd {
+ cell-index = <23>;
+ node-name = "cpas-cdm0-all-rd";
+ client-name = "cpas-cdm0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level2_nrt0_rd_wr>;
+ };
+
+ jpeg0_all_wr: jpeg0-all-wr {
+ cell-index = <24>;
+ node-name = "jpeg0-all-wr";
+ client-name = "jpeg-enc0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level2_nrt0_rd_wr>;
+ };
+
+ jpeg0_all_rd: jpeg0-all-rd {
+ cell-index = <25>;
+ node-name = "jpeg0-all-rd";
+ client-name = "jpeg-enc0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level2_nrt0_rd_wr>;
+ };
+
+ icp0_all_rd: icp0-all-rd {
+ cell-index = <26>;
+ node-name = "icp0-all-rd";
+ client-name = "icp0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level2_nrt1_rd>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/lito-camera-sensor-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/lito-camera-sensor-cdp.dtsi
new file mode 100755
index 0000000..c3467e2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/lito-camera-sensor-cdp.dtsi
@@ -0,0 +1,293 @@
+#include <dt-bindings/clock/qcom,camcc-lito.h>
+
+&soc {
+ led_flash_rear: qcom,camera-flash@0 {
+ cell-index = <0>;
+ reg = <0x00 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ };
+
+ led_flash_rear_aux: qcom,camera-flash@1 {
+ cell-index = <1>;
+ reg = <0x01 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator@0 {
+ cell-index = <0>;
+ reg = <0x0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ eeprom_rear: qcom,eeprom@0 {
+ cell-index = <0>;
+ reg = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1104000 0 2800000>;
+ rgltr-load-current = <0 80000 105000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 13 0>,
+ <&tlmm 30 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&S8C>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1350000 0>;
+ rgltr-max-voltage = <1800000 2800000 1350000 0>;
+ rgltr-load-current = <0 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 14 0>,
+ <&tlmm 29 0>,
+ <&tlmm 71 0>;
+ gpio-reset = <1>;
+ gpio-vdig = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1",
+ "CAM_VDIG1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ status="ok";
+ };
+
+ qcom,cam-sensor@0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x0>;
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear>;
+ led-flash-src = <&led_flash_rear>;
+ eeprom-src = <&eeprom_rear>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1104000 0>;
+ rgltr-max-voltage = <1800000 2800000 1104000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 13 0>,
+ <&tlmm 30 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x1>;
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_rear_aux>;
+ eeprom-src = <&eeprom_rear_aux>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&S8C>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1350000 0>;
+ rgltr-max-voltage = <1800000 2800000 1350000 0>;
+ rgltr-load-current = <0 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 14 0>,
+ <&tlmm 29 0>,
+ <&tlmm 71 0>;
+ gpio-reset = <1>;
+ gpio-vdig = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1",
+ "CAM_VDIG1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ status = "ok";
+ clock-rates = <24000000>;
+ };
+};
+
+&cam_cci1 {
+ eeprom_front: qcom,eeprom@2 {
+ cell-index = <2>;
+ reg = <0x2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_front>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_front>;
+ gpios = <&tlmm 15 0>,
+ <&tlmm 32 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x02>;
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_front>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_front>;
+ gpios = <&tlmm 15 0>,
+ <&tlmm 32 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/lito-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/lito-camera-sensor-mtp.dtsi
new file mode 100755
index 0000000..c3467e2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/lito-camera-sensor-mtp.dtsi
@@ -0,0 +1,293 @@
+#include <dt-bindings/clock/qcom,camcc-lito.h>
+
+&soc {
+ led_flash_rear: qcom,camera-flash@0 {
+ cell-index = <0>;
+ reg = <0x00 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ };
+
+ led_flash_rear_aux: qcom,camera-flash@1 {
+ cell-index = <1>;
+ reg = <0x01 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator@0 {
+ cell-index = <0>;
+ reg = <0x0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ eeprom_rear: qcom,eeprom@0 {
+ cell-index = <0>;
+ reg = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1104000 0 2800000>;
+ rgltr-load-current = <0 80000 105000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 13 0>,
+ <&tlmm 30 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&S8C>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1350000 0>;
+ rgltr-max-voltage = <1800000 2800000 1350000 0>;
+ rgltr-load-current = <0 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 14 0>,
+ <&tlmm 29 0>,
+ <&tlmm 71 0>;
+ gpio-reset = <1>;
+ gpio-vdig = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1",
+ "CAM_VDIG1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ status="ok";
+ };
+
+ qcom,cam-sensor@0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x0>;
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear>;
+ led-flash-src = <&led_flash_rear>;
+ eeprom-src = <&eeprom_rear>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1104000 0>;
+ rgltr-max-voltage = <1800000 2800000 1104000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 13 0>,
+ <&tlmm 30 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x1>;
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_rear_aux>;
+ eeprom-src = <&eeprom_rear_aux>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&S8C>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1350000 0>;
+ rgltr-max-voltage = <1800000 2800000 1350000 0>;
+ rgltr-load-current = <0 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 14 0>,
+ <&tlmm 29 0>,
+ <&tlmm 71 0>;
+ gpio-reset = <1>;
+ gpio-vdig = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1",
+ "CAM_VDIG1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ status = "ok";
+ clock-rates = <24000000>;
+ };
+};
+
+&cam_cci1 {
+ eeprom_front: qcom,eeprom@2 {
+ cell-index = <2>;
+ reg = <0x2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_front>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_front>;
+ gpios = <&tlmm 15 0>,
+ <&tlmm 32 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x02>;
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_front>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_front>;
+ gpios = <&tlmm 15 0>,
+ <&tlmm 32 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/lito-camera-sensor-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/lito-camera-sensor-qrd.dtsi
new file mode 100755
index 0000000..08cdafb
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/lito-camera-sensor-qrd.dtsi
@@ -0,0 +1,672 @@
+#include <dt-bindings/clock/qcom,camcc-lito.h>
+
+&soc {
+ led_flash_rear: qcom,camera-flash@0 {
+ cell-index = <0>;
+ reg = <0x00 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ };
+
+ led_flash_rear_aux: qcom,camera-flash@1 {
+ cell-index = <1>;
+ reg = <0x01 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ };
+
+ led_flash_triple_rear: qcom,camera-flash@4 {
+ cell-index = <4>;
+ reg = <0x04 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ };
+
+ led_flash_triple_rear_aux: qcom,camera-flash@5 {
+ cell-index = <5>;
+ reg = <0x05 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ };
+
+ led_flash_triple_rear_aux2: qcom,camera-flash@6 {
+ cell-index = <6>;
+ reg = <0x06 0x00>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm8150l_flash0 &pm8150l_flash1>;
+ torch-source = <&pm8150l_torch0 &pm8150l_torch1>;
+ switch-source = <&pm8150l_switch2>;
+ };
+
+ vreg_tof: regulator-dbb1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_tof";
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+ gpio = <&pm8150l_gpios 2 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <1000>;
+ enable-active-high;
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator@0 {
+ cell-index = <0>;
+ reg = <0x0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ actuator_triple_rear: qcom,actuator@4 {
+ cell-index = <4>;
+ reg = <0x4>;
+ compatible = "qcom,actuator";
+ cci-device = <0>;
+ cci-master = <0>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ actuator_triple_rear_aux2: qcom,actuator@6 {
+ cell-index = <6>;
+ reg = <0x6>;
+ compatible = "qcom,actuator";
+ cci-device = <0>;
+ cci-master = <1>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ eeprom_rear: qcom,eeprom@0 {
+ cell-index = <0>;
+ reg = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1104000 0 2800000>;
+ rgltr-load-current = <0 80000 105000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 13 0>,
+ <&tlmm 30 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&S8C>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1350000 0>;
+ rgltr-max-voltage = <1800000 2800000 1350000 0>;
+ rgltr-load-current = <0 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 14 0>,
+ <&tlmm 29 0>,
+ <&tlmm 71 0>;
+ gpio-reset = <1>;
+ gpio-vdig = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1",
+ "CAM_VDIG1";
+ sensor-position = <0>;
+ sensor-mode = <0>;
+ cci-master = <1>;
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ status="ok";
+ };
+
+ eeprom_triple_rear: qcom,eeprom@4 {
+ cell-index = <4>;
+ reg = <4>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1104000 0 2800000>;
+ rgltr-load-current = <0 80000 105000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 13 0>,
+ <&tlmm 30 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK4",
+ "CAM_RESET4";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_rear_aux2: qcom,eeprom@6 {
+ cell-index = <6>;
+ reg = <6>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0 2800000>;
+ rgltr-load-current = <0 80000 105000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk4_active
+ &cam_sensor_active_rear_aux2>;
+ pinctrl-1 = <&cam_sensor_mclk4_suspend
+ &cam_sensor_suspend_rear_aux2>;
+ gpios = <&tlmm 25 0>,
+ <&tlmm 21 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK6",
+ "CAM_RESET6";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK4_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x0>;
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear>;
+ led-flash-src = <&led_flash_rear>;
+ eeprom-src = <&eeprom_rear>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1104000 0>;
+ rgltr-max-voltage = <1800000 2800000 1104000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 13 0>,
+ <&tlmm 30 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x1>;
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_rear_aux>;
+ eeprom-src = <&eeprom_rear_aux>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&S8C>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1350000 0>;
+ rgltr-max-voltage = <1800000 2800000 1350000 0>;
+ rgltr-load-current = <0 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux>;
+ gpios = <&tlmm 14 0>,
+ <&tlmm 29 0>,
+ <&tlmm 71 0>;
+ gpio-reset = <1>;
+ gpio-vdig = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1",
+ "CAM_VDIG1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ status = "ok";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@4 {
+ cell-index = <4>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x4>;
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_triple_rear>;
+ actuator-src = <&actuator_triple_rear>;
+ eeprom-src = <&eeprom_triple_rear>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_v_custom1-supply = <&L6P>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_v_custom1";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1104000 0 1800000>;
+ rgltr-max-voltage = <1800000 2800000 1104000 0 1800000>;
+ rgltr-load-current = <0 80000 105000 0 80000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_active_rear>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_suspend_rear>;
+ gpios = <&tlmm 13 0>,
+ <&tlmm 30 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK4",
+ "CAM_RESET4";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@6 {
+ cell-index = <6>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x06>;
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_triple_rear_aux2>;
+ actuator-src = <&actuator_triple_rear_aux2>;
+ eeprom-src = <&eeprom_triple_rear_aux2>;
+ cam_vdig-supply = <&L1P>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk4_active
+ &cam_sensor_active_rear_aux2>;
+ pinctrl-1 = <&cam_sensor_mclk4_suspend
+ &cam_sensor_suspend_rear_aux2>;
+ gpios = <&tlmm 25 0>,
+ <&tlmm 21 0>,
+ <&tlmm 51 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK6",
+ "CAM_RESET6",
+ "CAM_VANA6";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK4_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
+&cam_cci1 {
+ actuator_triple_rear_aux: qcom,actuator@5 {
+ cell-index = <5>;
+ reg = <0x5>;
+ compatible = "qcom,actuator";
+ cci-device = <1>;
+ cci-master = <0>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ eeprom_front: qcom,eeprom@2 {
+ cell-index = <2>;
+ reg = <0x2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_front>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_front>;
+ gpios = <&tlmm 15 0>,
+ <&tlmm 32 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-position = <1>;
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ eeprom_triple_rear_aux: qcom,eeprom@5 {
+ cell-index = <5>;
+ reg = <5>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&BOB>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 3008000 1056000 0 2800000>;
+ rgltr-max-voltage = <1800000 4000000 1056000 0 2800000>;
+ rgltr-load-current = <0 2000000 105000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_triple_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_triple_rear_aux>;
+ gpios = <&tlmm 14 0>,
+ <&tlmm 29 0>,
+ <&tlmm 70 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK5",
+ "CAM_RESET5",
+ "CAM_VANA5";
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x02>;
+ csiphy-sd-index = <2>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_active_front>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_suspend_front>;
+ gpios = <&tlmm 15 0>,
+ <&tlmm 32 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@3 {
+ cell-index = <3>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <3>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ cam_vio-supply = <&L7P>;
+ cam_vdig-supply = <&vreg_tof>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <1800000 3600000 0>;
+ rgltr-max-voltage = <1800000 3600000 0>;
+ rgltr-load-current = <0 120000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_active_3>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_suspend_3>;
+ gpios = <&tlmm 16 0>,
+ <&tlmm 23 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK3_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ qcom,cam-sensor@5 {
+ cell-index = <5>;
+ compatible = "qcom,cam-sensor";
+ reg = <0x5>;
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ led-flash-src = <&led_flash_triple_rear_aux>;
+ actuator-src = <&actuator_triple_rear_aux>;
+ eeprom-src = <&eeprom_triple_rear_aux>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&BOB>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&titan_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 3008000 1056000 0>;
+ rgltr-max-voltage = <1800000 4000000 1056000 0>;
+ rgltr-load-current = <0 2000000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_triple_rear_aux>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_triple_rear_aux>;
+ gpios = <&tlmm 14 0>,
+ <&tlmm 29 0>,
+ <&tlmm 70 0>;
+ gpio-reset = <1>;
+ gpio-vana = <2>;
+ gpio-req-tbl-num = <0 1 2>;
+ gpio-req-tbl-flags = <1 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK5",
+ "CAM_RESET5",
+ "CAM_VANA5";
+ sensor-mode = <0>;
+ cci-device = <1>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/lito-camera.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/lito-camera.dtsi
new file mode 100755
index 0000000..c3c75bf
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/lito-camera.dtsi
@@ -0,0 +1,1617 @@
+#include <dt-bindings/msm/msm-camera.h>
+
+&soc {
+ qcom,cam-req-mgr {
+ compatible = "qcom,cam-req-mgr";
+ status = "ok";
+ };
+
+ cam_csiphy0: qcom,csiphy0 {
+ cell-index = <0>;
+ compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy";
+ reg = <0x0ace0000 0x2000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0xe0000>;
+ interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr", "refgen";
+ gdscr-supply = <&titan_top_gdsc>;
+ refgen-supply = <&refgen>;
+ csi-vdd-voltage = <880000>;
+ mipi-csi-vdd-supply = <&L5A>;
+ clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy0_clk",
+ "csi0phytimer_clk_src",
+ "csi0phytimer_clk";
+ src-clock-name = "csi0phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1";
+ clock-rates =
+ <300000000 0 300000000 0>,
+ <384000000 0 300000000 0>,
+ <400000000 0 300000000 0>;
+ status = "ok";
+ };
+
+ cam_csiphy1: qcom,csiphy1 {
+ cell-index = <1>;
+ compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy";
+ reg = <0xace2000 0x2000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0xe2000>;
+ interrupts = <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr", "refgen";
+ gdscr-supply = <&titan_top_gdsc>;
+ refgen-supply = <&refgen>;
+ csi-vdd-voltage = <880000>;
+ mipi-csi-vdd-supply = <&L5A>;
+ clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy1_clk",
+ "csi1phytimer_clk_src",
+ "csi1phytimer_clk";
+ src-clock-name = "csi1phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1";
+ clock-rates =
+ <300000000 0 300000000 0>,
+ <384000000 0 300000000 0>,
+ <400000000 0 300000000 0>;
+
+ status = "ok";
+ };
+
+ cam_csiphy2: qcom,csiphy2 {
+ cell-index = <2>;
+ compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy";
+ reg = <0xace4000 0x2000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0xe4000>;
+ interrupts = <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr", "refgen";
+ gdscr-supply = <&titan_top_gdsc>;
+ refgen-supply = <&refgen>;
+ csi-vdd-voltage = <880000>;
+ mipi-csi-vdd-supply = <&L5A>;
+ clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy2_clk",
+ "csi2phytimer_clk_src",
+ "csi2phytimer_clk";
+ src-clock-name = "csi2phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1";
+ clock-rates =
+ <300000000 0 300000000 0>,
+ <384000000 0 300000000 0>,
+ <400000000 0 300000000 0>;
+ status = "ok";
+ };
+
+ cam_csiphy3: qcom,csiphy3 {
+ cell-index = <3>;
+ compatible = "qcom,csiphy-v1.2.2", "qcom,csiphy";
+ reg = <0xace6000 0x2000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0xe6000>;
+ interrupts = <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr", "refgen";
+ gdscr-supply = <&titan_top_gdsc>;
+ refgen-supply = <&refgen>;
+ csi-vdd-voltage = <880000>;
+ mipi-csi-vdd-supply = <&L5A>;
+ clocks = <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSIPHY3_CLK>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
+ <&camcc CAM_CC_CSI3PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy3_clk",
+ "csi3phytimer_clk_src",
+ "csi3phytimer_clk";
+ src-clock-name = "csi3phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1";
+ clock-rates =
+ <300000000 0 300000000 0>,
+ <384000000 0 300000000 0>,
+ <400000000 0 300000000 0>;
+ status = "ok";
+ };
+
+ cam_cci0: qcom,cci0 {
+ cell-index = <0>;
+ compatible = "qcom,cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xac4a000 0x1000>;
+ reg-names = "cci";
+ reg-cam-base = <0x4a000>;
+ interrupt-names = "cci";
+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+ status = "ok";
+ gdscr-supply = <&titan_top_gdsc>;
+ regulator-names = "gdscr";
+ clocks = <&camcc CAM_CC_CCI_0_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK_SRC>;
+ clock-names = "cci_0_clk",
+ "cci_0_clk_src";
+ src-clock-name = "cci_0_clk_src";
+ clock-cntl-level = "lowsvs";
+ clock-rates = <0 37500000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cci0_active &cci1_active>;
+ pinctrl-1 = <&cci0_suspend &cci1_suspend>;
+ gpios = <&tlmm 17 0>,
+ <&tlmm 18 0>,
+ <&tlmm 19 0>,
+ <&tlmm 20 0>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 1 1 1>;
+ gpio-req-tbl-label = "CCI_I2C_DATA0",
+ "CCI_I2C_CLK0",
+ "CCI_I2C_DATA1",
+ "CCI_I2C_CLK1";
+
+ i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
+ hw-thigh = <201>;
+ hw-tlow = <174>;
+ hw-tsu-sto = <204>;
+ hw-tsu-sta = <231>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <162>;
+ hw-tbuf = <227>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_custom_cci0: qcom,i2c_custom_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <1>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
+ hw-thigh = <16>;
+ hw-tlow = <22>;
+ hw-tsu-sto = <17>;
+ hw-tsu-sta = <18>;
+ hw-thd-dat = <16>;
+ hw-thd-sta = <15>;
+ hw-tbuf = <24>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <3>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+ };
+
+ cam_cci1: qcom,cci1 {
+ cell-index = <1>;
+ compatible = "qcom,cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xac4b000 0x1000>;
+ reg-names = "cci";
+ reg-cam-base = <0x4b000>;
+ interrupt-names = "cci";
+ interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
+ status = "ok";
+ gdscr-supply = <&titan_top_gdsc>;
+ regulator-names = "gdscr";
+ clocks = <&camcc CAM_CC_CCI_1_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK_SRC>;
+ clock-names = "cci_clk",
+ "cci_1_clk_src";
+ src-clock-name = "cci_1_clk_src";
+ clock-cntl-level = "lowsvs";
+ clock-rates = <0 37500000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cci2_active>;
+ pinctrl-1 = <&cci2_suspend>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 28 0>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 1>;
+ gpio-req-tbl-label = "CCI_I2C_DATA2",
+ "CCI_I2C_CLK2";
+
+ i2c_freq_100Khz_cci1: qcom,i2c_standard_mode {
+ hw-thigh = <201>;
+ hw-tlow = <174>;
+ hw-tsu-sto = <204>;
+ hw-tsu-sta = <231>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <162>;
+ hw-tbuf = <227>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_400Khz_cci1: qcom,i2c_fast_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_custom_cci1: qcom,i2c_custom_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <1>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode {
+ hw-thigh = <16>;
+ hw-tlow = <22>;
+ hw-tsu-sto = <17>;
+ hw-tsu-sta = <18>;
+ hw-thd-dat = <16>;
+ hw-thd-sta = <15>;
+ hw-tbuf = <24>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <3>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+ };
+
+ qcom,cam_smmu {
+ compatible = "qcom,msm-cam-smmu";
+ status = "ok";
+
+ msm_cam_smmu_ife {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x900 0x5E0>,
+ <&apps_smmu 0x880 0x5E0>,
+ <&apps_smmu 0x820 0x5E0>,
+ <&apps_smmu 0x920 0x5E0>,
+ <&apps_smmu 0x8A0 0x5E0>,
+ <&apps_smmu 0x940 0x5E0>,
+ <&apps_smmu 0x8C0 0x5E0>,
+ <&apps_smmu 0xD00 0x5E0>,
+ <&apps_smmu 0xC80 0x5E0>,
+ <&apps_smmu 0xC20 0x5E0>,
+ <&apps_smmu 0xD20 0x5E0>,
+ <&apps_smmu 0xCA0 0x5E0>,
+ <&apps_smmu 0xD40 0x5E0>,
+ <&apps_smmu 0xCC0 0x5E0>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ label = "ife";
+ ife_iova_mem_map: iova-mem-map {
+ /* IO region is approximately 3.4 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_jpeg {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x1280 0x20>,
+ <&apps_smmu 0x12A0 0x20>;
+ label = "jpeg";
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ jpeg_iova_mem_map: iova-mem-map {
+ /* IO region is approximately 3.4 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_icp_fw {
+ compatible = "qcom,msm-cam-smmu-fw-dev";
+ label="icp";
+ memory-region = <&pil_camera_mem>;
+ };
+
+ msm_cam_smmu_icp {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x1042 0x0>,
+ <&apps_smmu 0x11A0 0x0>,
+ <&apps_smmu 0x1220 0x0>,
+ <&apps_smmu 0x1300 0x20>,
+ <&apps_smmu 0x1320 0x20>,
+ <&apps_smmu 0x1180 0x0>,
+ <&apps_smmu 0x1200 0x0>,
+ <&apps_smmu 0x11E0 0x0>,
+ <&apps_smmu 0x1260 0x0>;
+ label = "icp";
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>;
+ iova-region-discard = <0xdff00000 0x300000>;
+ icp_iova_mem_map: iova-mem-map {
+ iova-mem-region-firmware {
+ /* Firmware region is 5MB */
+ iova-region-name = "firmware";
+ iova-region-start = <0x0>;
+ iova-region-len = <0x500000>;
+ iova-region-id = <0x0>;
+ status = "ok";
+ };
+
+ iova-mem-region-shared {
+ /* Shared region is 150MB long */
+ iova-region-name = "shared";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0x9600000>;
+ iova-region-id = <0x1>;
+ status = "ok";
+ };
+
+ iova-mem-region-secondary-heap {
+ /* Secondary heap region is 1MB long */
+ iova-region-name = "secheap";
+ iova-region-start = <0x10a00000>;
+ iova-region-len = <0x100000>;
+ iova-region-id = <0x4>;
+ status = "ok";
+ };
+
+ iova-mem-region-io {
+ /* IO region is approximately 3.7 GB */
+ iova-region-name = "io";
+ iova-region-start = <0x10c00000>;
+ iova-region-len = <0xee300000>;
+ iova-region-id = <0x3>;
+ iova-region-discard = <0xdff00000 0x300000>;
+ status = "ok";
+ };
+
+ iova-mem-qdss-region {
+ /* QDSS region is appropriate 1MB */
+ iova-region-name = "qdss";
+ iova-region-start = <0x10b00000>;
+ iova-region-len = <0x100000>;
+ iova-region-id = <0x5>;
+ qdss-phy-addr = <0x16790000>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_cpas_cdm {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x1000 0x0>;
+ label = "cpas-cdm0";
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ cpas_cdm_iova_mem_map: iova-mem-map {
+ iova-mem-region-io {
+ /* IO region is approximately 3.4 GB */
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_secure {
+ compatible = "qcom,msm-cam-smmu-cb";
+ label = "cam-secure";
+ qcom,secure-cb;
+ };
+
+ msm_cam_smmu_fd {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x12C0 0x20>,
+ <&apps_smmu 0x12E0 0x20>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ label = "fd";
+ fd_iova_mem_map: iova-mem-map {
+ iova-mem-region-io {
+ /* IO region is approximately 3.4 GB */
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_lrme {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x11C0 0x0>,
+ <&apps_smmu 0x1240 0x0>;
+ label = "lrme";
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ lrme_iova_mem_map: iova-mem-map {
+ iova-mem-region-shared {
+ /* Shared region is 100MB long */
+ iova-region-name = "shared";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0x6400000>;
+ iova-region-id = <0x1>;
+ status = "ok";
+ };
+ /* IO region is approximately 3.3 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0xd800000>;
+ iova-region-len = <0xd2800000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+ };
+
+ qcom,cam-cdm-intf {
+ compatible = "qcom,cam-cdm-intf";
+ cell-index = <0>;
+ label = "cam-cdm-intf";
+ num-hw-cdm = <1>;
+ cdm-client-names = "vfe",
+ "jpegdma",
+ "jpegenc",
+ "fd",
+ "lrmecdm";
+ status = "ok";
+ };
+
+ qcom,cpas-cdm0 {
+ cell-index = <0>;
+ compatible = "qcom,cam170-cpas-cdm0";
+ label = "cpas-cdm";
+ reg = <0xac48000 0x1000>;
+ reg-names = "cpas-cdm";
+ reg-cam-base = <0x48000>;
+ interrupts = <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "cpas-cdm";
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names = "cam_cc_cpas_slow_ahb_clk",
+ "cam_cc_cpas_ahb_clk";
+ clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>;
+ clock-rates = <0 0>;
+ clock-cntl-level = "svs";
+ cdm-client-names = "ife";
+ status = "ok";
+ };
+
+ qcom,cam-isp {
+ compatible = "qcom,cam-isp";
+ arch-compat = "ife";
+ status = "ok";
+ };
+
+ cam_csid0: qcom,csid0 {
+ cell-index = <0>;
+ compatible = "qcom,csid175_200";
+ reg-names = "csid";
+ reg = <0xacb3000 0x1000>;
+ reg-cam-base = <0xb3000>;
+ interrupt-names = "csid";
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss", "ife0";
+ camss-supply = <&titan_top_gdsc>;
+ ife0-supply = <&ife_0_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_clk",
+ "ife_axi_clk";
+ clocks =
+ <&camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
+ <&camcc CAM_CC_IFE_0_CSID_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK_SRC>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>;
+ clock-rates =
+ <300000000 0 0 0 380000000 0 0>,
+ <384000000 0 0 0 510000000 0 0>,
+ <400000000 0 0 0 637000000 0 0>,
+ <400000000 0 0 0 760000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_vfe0: qcom,vfe0 {
+ cell-index = <0>;
+ compatible = "qcom,vfe175_130";
+ reg-names = "ife";
+ reg = <0xacaf000 0x5200>;
+ reg-cam-base = <0xaf000>;
+ interrupt-names = "ife";
+ interrupts = <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss", "ife0";
+ camss-supply = <&titan_top_gdsc>;
+ ife0-supply = <&ife_0_gdsc>;
+ clock-names =
+ "ife_clk_src",
+ "ife_clk",
+ "ife_axi_clk";
+ clocks =
+ <&camcc CAM_CC_IFE_0_CLK_SRC>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_AXI_CLK>;
+ clock-rates =
+ <380000000 0 0>,
+ <510000000 0 0>,
+ <637000000 0 0>,
+ <760000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ clock-control-debugfs = "true";
+ clock-names-option = "ife_dsp_clk";
+ clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>;
+ clock-rates-option = <760000000>;
+ status = "ok";
+ };
+
+ cam_csid1: qcom,csid1 {
+ cell-index = <1>;
+ compatible = "qcom,csid175_200";
+ reg-names = "csid";
+ reg = <0xacba000 0x1000>;
+ reg-cam-base = <0xba000>;
+ interrupt-names = "csid";
+ interrupts = <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss", "ife1";
+ camss-supply = <&titan_top_gdsc>;
+ ife1-supply = <&ife_1_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_clk",
+ "ife_axi_clk";
+ clocks =
+ <&camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
+ <&camcc CAM_CC_IFE_1_CSID_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK_SRC>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>;
+ clock-rates =
+ <300000000 0 0 0 380000000 0 0>,
+ <384000000 0 0 0 510000000 0 0>,
+ <400000000 0 0 0 637000000 0 0>,
+ <400000000 0 0 0 760000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_vfe1: qcom,vfe1 {
+ cell-index = <1>;
+ compatible = "qcom,vfe175_130";
+ reg-names = "ife";
+ reg = <0xacb6000 0x5200>;
+ reg-cam-base = <0xb6000>;
+ interrupt-names = "ife";
+ interrupts = <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss", "ife1";
+ camss-supply = <&titan_top_gdsc>;
+ ife1-supply = <&ife_1_gdsc>;
+ clock-names =
+ "ife_clk_src",
+ "ife_clk",
+ "ife_axi_clk";
+ clocks =
+ <&camcc CAM_CC_IFE_1_CLK_SRC>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_AXI_CLK>;
+ clock-rates =
+ <380000000 0 0>,
+ <510000000 0 0>,
+ <637000000 0 0>,
+ <760000000 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ clock-control-debugfs = "true";
+ clock-names-option = "ife_dsp_clk";
+ clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>;
+ clock-rates-option = <760000000>;
+ status = "ok";
+ };
+
+ cam_csid_lite0: qcom,csid-lite0 {
+ cell-index = <2>;
+ compatible = "qcom,csid-lite175";
+ reg-names = "csid-lite";
+ reg = <0xacc8000 0x1000>;
+ reg-cam-base = <0xc8000>;
+ interrupt-names = "csid-lite";
+ interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_csid_clk_src",
+ "ife_csid_clk",
+ "cphy_rx_clk_src",
+ "ife_cphy_rx_clk",
+ "ife_clk_src",
+ "ife_clk";
+ clocks =
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <300000000 0 0 0 320000000 0>,
+ <384000000 0 0 0 400000000 0>,
+ <400000000 0 0 0 480000000 0>,
+ <400000000 0 0 0 600000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_vfe_lite0: qcom,vfe-lite0 {
+ cell-index = <2>;
+ compatible = "qcom,vfe-lite175";
+ reg-names = "ife-lite";
+ reg = <0xacc4000 0x4000>;
+ reg-cam-base = <0xc4000>;
+ interrupt-names = "ife-lite";
+ interrupts = <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names =
+ "ife_clk_src",
+ "ife_clk";
+ clocks =
+ <&camcc CAM_CC_IFE_LITE_CLK_SRC>,
+ <&camcc CAM_CC_IFE_LITE_CLK>;
+ clock-rates =
+ <320000000 0>,
+ <400000000 0>,
+ <480000000 0>,
+ <600000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ src-clock-name = "ife_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ qcom,cam-icp {
+ compatible = "qcom,cam-icp";
+ compat-hw-name = "qcom,a5",
+ "qcom,ipe0",
+ "qcom,ipe1",
+ "qcom,bps";
+ num-a5 = <1>;
+ num-ipe = <2>;
+ num-bps = <1>;
+ icp_pc_en;
+ status = "ok";
+ };
+
+ cam_a5: qcom,a5 {
+ cell-index = <0>;
+ compatible = "qcom,cam-a5";
+ reg = <0xac00000 0x6000>,
+ <0xac10000 0x8000>,
+ <0xac18000 0x3000>;
+ reg-names = "a5_qgic", "a5_sierra", "a5_csr";
+ reg-cam-base = <0x00000 0x10000 0x18000>;
+ interrupts = <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "a5";
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&titan_top_gdsc>;
+ clock-names =
+ "soc_fast_ahb",
+ "icp_ahb_clk",
+ "icp_clk_src",
+ "icp_clk";
+ src-clock-name = "icp_clk_src";
+ clocks =
+ <&camcc CAM_CC_FAST_AHB_CLK_SRC>,
+ <&camcc CAM_CC_ICP_AHB_CLK>,
+ <&camcc CAM_CC_ICP_CLK_SRC>,
+ <&camcc CAM_CC_ICP_CLK>;
+
+ clock-rates =
+ <100000000 0 400000000 0>,
+ <200000000 0 480000000 0>,
+ <300000000 0 600000000 0>,
+ <400000000 0 600000000 0>,
+ <400000000 0 600000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1",
+ "nominal", "turbo";
+ fw_name = "CAMERA_ICP.elf";
+ ubwc-cfg = <0x1073 0x101CF>;
+ qos-val = <0x00000A0A>;
+ status = "ok";
+ };
+
+ cam_ipe0: qcom,ipe0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-ipe";
+ reg = <0xac87000 0x3000>;
+ reg-names = "ipe0_top";
+ reg-cam-base = <0x87000>;
+ regulator-names = "ipe0-vdd";
+ ipe0-vdd-supply = <&ipe_0_gdsc>;
+ clock-names =
+ "ipe_0_ahb_clk",
+ "ipe_0_areg_clk",
+ "ipe_0_axi_clk",
+ "ipe_0_clk_src",
+ "ipe_0_clk";
+ src-clock-name = "ipe_0_clk_src";
+ clock-control-debugfs = "true";
+ clocks =
+ <&camcc CAM_CC_IPE_0_AHB_CLK>,
+ <&camcc CAM_CC_IPE_0_AREG_CLK>,
+ <&camcc CAM_CC_IPE_0_AXI_CLK>,
+ <&camcc CAM_CC_IPE_0_CLK_SRC>,
+ <&camcc CAM_CC_IPE_0_CLK>;
+
+ clock-rates =
+ <0 0 0 300000000 0>,
+ <0 0 0 430000000 0>,
+ <0 0 0 520000000 0>,
+ <0 0 0 600000000 0>,
+ <0 0 0 600000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1",
+ "nominal", "turbo";
+ status = "ok";
+ };
+
+ cam_ipe1: qcom,ipe1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-ipe";
+ reg = <0xac91000 0x3000>;
+ reg-names = "ipe1_top";
+ reg-cam-base = <0x91000>;
+ regulator-names = "ipe1-vdd";
+ ipe1-vdd-supply = <&ipe_1_gdsc>;
+ clock-names =
+ "ipe_1_ahb_clk",
+ "ipe_1_areg_clk",
+ "ipe_1_axi_clk",
+ "ipe_1_clk_src",
+ "ipe_1_clk";
+ src-clock-name = "ipe_1_clk_src";
+ clock-control-debugfs = "true";
+ clocks =
+ <&camcc CAM_CC_IPE_1_AHB_CLK>,
+ <&camcc CAM_CC_IPE_1_AREG_CLK>,
+ <&camcc CAM_CC_IPE_1_AXI_CLK>,
+ <&camcc CAM_CC_IPE_0_CLK_SRC>,
+ <&camcc CAM_CC_IPE_1_CLK>;
+
+ clock-rates =
+ <0 0 0 300000000 0>,
+ <0 0 0 430000000 0>,
+ <0 0 0 520000000 0>,
+ <0 0 0 600000000 0>,
+ <0 0 0 600000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1",
+ "nominal", "turbo";
+ status = "ok";
+ };
+
+ cam_bps: qcom,bps {
+ cell-index = <0>;
+ compatible = "qcom,cam-bps";
+ reg = <0xac6f000 0x3000>;
+ reg-names = "bps_top";
+ reg-cam-base = <0x6f000>;
+ regulator-names = "bps-vdd";
+ bps-vdd-supply = <&bps_gdsc>;
+ clock-names =
+ "bps_ahb_clk",
+ "bps_areg_clk",
+ "bps_axi_clk",
+ "bps_clk_src",
+ "bps_clk";
+ src-clock-name = "bps_clk_src";
+ clock-control-debugfs = "true";
+ clocks =
+ <&camcc CAM_CC_BPS_AHB_CLK>,
+ <&camcc CAM_CC_BPS_AREG_CLK>,
+ <&camcc CAM_CC_BPS_AXI_CLK>,
+ <&camcc CAM_CC_BPS_CLK_SRC>,
+ <&camcc CAM_CC_BPS_CLK>;
+
+ clock-rates =
+ <0 0 0 200000000 0>,
+ <0 0 0 400000000 0>,
+ <0 0 0 480000000 0>,
+ <0 0 0 600000000 0>,
+ <0 0 0 600000000 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1",
+ "nominal", "turbo";
+ status = "ok";
+ };
+
+ qcom,cam-jpeg {
+ compatible = "qcom,cam-jpeg";
+ compat-hw-name = "qcom,jpegenc",
+ "qcom,jpegdma";
+ num-jpeg-enc = <1>;
+ num-jpeg-dma = <1>;
+ status = "ok";
+ };
+
+ cam_jpeg_enc: qcom,jpegenc {
+ cell-index = <0>;
+ compatible = "qcom,cam_jpeg_enc";
+ reg-names = "jpege_hw";
+ reg = <0xac4e000 0x4000>;
+ reg-cam-base = <0x4e000>;
+ interrupt-names = "jpeg";
+ interrupts = <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&titan_top_gdsc>;
+ clock-names =
+ "jpegenc_clk_src",
+ "jpegenc_clk";
+ clocks =
+ <&camcc CAM_CC_JPEG_CLK_SRC>,
+ <&camcc CAM_CC_JPEG_CLK>;
+
+ clock-rates = <600000000 0>;
+ src-clock-name = "jpegenc_clk_src";
+ clock-cntl-level = "nominal";
+ status = "ok";
+ };
+
+ cam_jpeg_dma: qcom,jpegdma {
+ cell-index = <0>;
+ compatible = "qcom,cam_jpeg_dma";
+ reg-names = "jpegdma_hw";
+ reg = <0xac52000 0x4000>;
+ reg-cam-base = <0x52000>;
+ interrupt-names = "jpegdma";
+ interrupts = <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&titan_top_gdsc>;
+ clock-names =
+ "jpegdma_clk_src",
+ "jpegdma_clk";
+ clocks =
+ <&camcc CAM_CC_JPEG_CLK_SRC>,
+ <&camcc CAM_CC_JPEG_CLK>;
+
+ clock-rates = <600000000 0>;
+ src-clock-name = "jpegdma_clk_src";
+ clock-cntl-level = "nominal";
+ status = "ok";
+ };
+
+ qcom,cam-fd {
+ compatible = "qcom,cam-fd";
+ compat-hw-name = "qcom,fd";
+ num-fd = <1>;
+ status = "ok";
+ };
+
+ cam_fd: qcom,fd {
+ cell-index = <0>;
+ compatible = "qcom,fd501";
+ reg-names = "fd_core", "fd_wrapper";
+ reg = <0xac5a000 0x1000>,
+ <0xac5b000 0x400>;
+ reg-cam-base = <0x5a000 0x5b000>;
+ interrupt-names = "fd";
+ interrupts = <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&titan_top_gdsc>;
+ clock-names =
+ "fd_core_clk_src",
+ "fd_core_clk",
+ "fd_core_uar_clk";
+ clocks =
+ <&camcc CAM_CC_FD_CORE_CLK_SRC>,
+ <&camcc CAM_CC_FD_CORE_CLK>,
+ <&camcc CAM_CC_FD_CORE_UAR_CLK>;
+ src-clock-name = "fd_core_clk_src";
+ clock-control-debugfs = "true";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal";
+ clock-rates =
+ <380000000 0 0>,
+ <384000000 0 0>,
+ <480000000 0 0>,
+ <600000000 0 0>;
+ status = "ok";
+ };
+
+ qcom,cam-lrme {
+ compatible = "qcom,cam-lrme";
+ arch-compat = "lrme";
+ status = "ok";
+ };
+
+ cam_lrme: qcom,lrme {
+ cell-index = <0>;
+ compatible = "qcom,lrme";
+ reg-names = "lrme";
+ reg = <0xac6b000 0xa00>;
+ reg-cam-base = <0x6b000>;
+ interrupt-names = "lrme";
+ interrupts = <GIC_SPI 476 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&titan_top_gdsc>;
+ clock-names = "lrme_clk_src",
+ "lrme_clk";
+ clocks = <&camcc CAM_CC_LRME_CLK_SRC>,
+ <&camcc CAM_CC_LRME_CLK>;
+ clock-rates = <240000000 240000000>,
+ <300000000 300000000>,
+ <320000000 320000000>,
+ <400000000 400000000>,
+ <400000000 400000000>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
+ "turbo";
+ src-clock-name = "lrme_clk_src";
+ status = "ok";
+ };
+
+ qcom,cam-cpas {
+ cell-index = <0>;
+ compatible = "qcom,cam-cpas";
+ label = "cpas";
+ arch-compat = "cpas_top";
+ status = "ok";
+ reg-names = "cam_cpas_top", "cam_camnoc";
+ reg = <0xac40000 0x1000>,
+ <0xac42000 0x6000>;
+ reg-cam-base = <0x40000 0x42000>;
+ cam_hw_fuse = <CAM_CPAS_QCFA_BINNING_ENABLE 0x00780210 29>,
+ <CAM_CPAS_SECURE_CAMERA_ENABLE 0x00780210 18>;
+ interrupt-names = "cpas_camnoc";
+ interrupts = <GIC_SPI 459 IRQ_TYPE_EDGE_RISING>;
+ camnoc-axi-min-ib-bw = <3000000000>;
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&titan_top_gdsc>;
+ clock-names =
+ "gcc_ahb_clk",
+ "gcc_axi_hf_clk",
+ "gcc_axi_sf_clk",
+ "slow_ahb_clk_src",
+ "cpas_ahb_clk",
+ "camnoc_axi_clk_src",
+ "camnoc_axi_clk";
+ clocks =
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
+ <&camcc CAM_CC_CAMNOC_AXI_CLK>;
+ src-clock-name = "camnoc_axi_clk_src";
+ clock-rates =
+ <0 0 0 0 0 0 0>,
+ <0 0 0 80000000 0 150000000 0>,
+ <0 0 0 80000000 0 240000000 0>,
+ <0 0 0 80000000 0 320000000 0>,
+ <0 0 0 80000000 0 400000000 0>,
+ <0 0 0 80000000 0 400000000 0>,
+ <0 0 0 80000000 0 480000000 0>;
+ clock-cntl-level = "suspend", "lowsvs", "svs",
+ "svs_l1", "nominal", "nominal_l1", "turbo";
+ control-camnoc-axi-clk;
+ camnoc-bus-width = <32>;
+ camnoc-axi-clk-bw-margin-perc = <20>;
+ qcom,msm-bus,name = "cam_ahb";
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 65000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 125000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 125000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 250000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 250000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 250000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 250000>;
+ vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
+ RPMH_REGULATOR_LEVEL_MIN_SVS
+ RPMH_REGULATOR_LEVEL_LOW_SVS
+ RPMH_REGULATOR_LEVEL_SVS
+ RPMH_REGULATOR_LEVEL_SVS_L1
+ RPMH_REGULATOR_LEVEL_NOM
+ RPMH_REGULATOR_LEVEL_NOM_L1
+ RPMH_REGULATOR_LEVEL_NOM_L2
+ RPMH_REGULATOR_LEVEL_TURBO
+ RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ vdd-corner-ahb-mapping = "suspend",
+ "minsvs", "lowsvs", "svs", "svs_l1",
+ "nominal", "nominal", "nominal",
+ "turbo", "turbo";
+ client-id-based;
+ client-names =
+ "csiphy0", "csiphy1", "csiphy2", "csiphy3",
+ "cci0", "cci1",
+ "csid0", "csid1", "csid2",
+ "ife0", "ife1", "ife2",
+ "ipe0", "ipe1", "cam-cdm-intf0", "cpas-cdm0",
+ "bps0", "icp0", "jpeg-dma0", "jpeg-enc0",
+ "fd0", "lrmecpas0";
+ camera-bus-nodes {
+ level3-nodes {
+ level-index = <3>;
+ level3_rt0_wr_sum: level3-rt0-wr-sum {
+ cell-index = <0>;
+ node-name = "level3-rt0-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_hf_3";
+ ib-bw-voting-needed;
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_hf_3_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_HF1
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_HF1
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+ };
+
+ level3_rt1_rd_wr_sum: level3-rt1-rd-wr-sum {
+ cell-index = <1>;
+ node-name = "level3-rt1-rd-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_hf_1";
+ ib-bw-voting-needed;
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_hf_1_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_HF0
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_HF0
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+ };
+
+ level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum {
+ cell-index = <2>;
+ node-name = "level3-nrt0-rd-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_sf_0";
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_sf_0_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_SF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_SF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+ };
+
+ level3_nrt1_rd_sum: level3-nrt1-rd-sum {
+ cell-index = <3>;
+ node-name = "level3-nrt1-rd-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_sf_icp";
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_hf_4_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_ICP
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_ICP
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+ };
+ };
+
+ level2-nodes {
+ level-index = <2>;
+ camnoc-max-needed;
+ level2_rt0_write0: level2-rt0-write0 {
+ cell-index = <4>;
+ node-name = "level2-rt0-write0";
+ parent-node = <&level3_rt0_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level2_rt1_read0: level2-rt1-read0 {
+ cell-index = <5>;
+ node-name = "level2-rt1-read0";
+ parent-node = <&level3_rt1_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
+ };
+
+ level2_rt1_write0: level2-rt1-write0 {
+ cell-index = <6>;
+ node-name = "level2-rt1-write0";
+ parent-node = <&level3_rt1_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
+ };
+
+ level2_nrt0_write0: level2-nrt0-write0 {
+ cell-index = <7>;
+ node-name = "level2-nrt0-write0";
+ parent-node = <&level3_nrt0_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level2_nrt0_read0: level2-nrt0-read0 {
+ cell-index = <8>;
+ node-name = "level2-nrt0-read0";
+ parent-node = <&level3_nrt0_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level2_nrt1_read0: level2-nrt1-read0 {
+ cell-index = <9>;
+ node-name = "level2-nrt1-read0";
+ parent-node = <&level3_nrt1_rd_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ bus-width-factor = <4>;
+ };
+ };
+
+ level1-nodes {
+ level-index = <1>;
+ camnoc-max-needed;
+ level1_rt0_write0: level1-rt0-write0 {
+ cell-index = <10>;
+ node-name = "level1-rt0-write0";
+ parent-node = <&level2_rt0_write0>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_rt1_write0: level1-rt1-write0 {
+ cell-index = <11>;
+ node-name = "level1-rt1-write0";
+ parent-node = <&level2_rt1_write0>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_rt1_read0: level1-rt1-read0 {
+ cell-index = <12>;
+ node-name = "level1-rt1-read0";
+ parent-node = <&level2_rt1_read0>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_rt1_write1: level1-rt1-write1 {
+ cell-index = <13>;
+ node-name = "level1-rt1-write1";
+ parent-node = <&level2_rt1_write0>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_nrt0_write0: level1-nrt0-write0 {
+ cell-index = <14>;
+ node-name = "level1-nrt0-write0";
+ parent-node = <&level2_nrt0_write0>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_nrt0_write1: level1-nrt0-write1 {
+ cell-index = <15>;
+ node-name = "level1-nrt0-write1";
+ parent-node = <&level2_nrt0_write0>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+
+ level1_nrt0_read0: level1-nrt0-read0 {
+ cell-index = <16>;
+ node-name = "level1-nrt0-read0";
+ parent-node = <&level2_nrt0_read0>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ };
+ };
+
+ level0-nodes {
+ level-index = <0>;
+ cpas_cdm0_all_rd: cpas-cdm0-all-rd {
+ cell-index = <17>;
+ node-name = "cpas-cdm0-all-rd";
+ client-name = "cpas-cdm0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level2_nrt0_read0>;
+ };
+
+ fd0_all_wr: fd0-all-wr {
+ cell-index = <18>;
+ node-name = "fd0-all-wr";
+ client-name = "fd0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level2_nrt0_write0>;
+ };
+
+ fd0_all_rd: fd0-all-rd {
+ cell-index = <19>;
+ node-name = "fd0-all-rd";
+ client-name = "fd0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level2_nrt0_read0>;
+ };
+
+ ife0_pixelall_wr: ife0-pixelall-wr {
+ cell-index = <20>;
+ node-name = "ife0-pixelall-wr";
+ client-name = "ife0";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_PIXEL_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_LINEAR
+ CAM_CPAS_PATH_DATA_IFE_PDAF
+ CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS
+ CAM_CPAS_PATH_DATA_IFE_PIXEL_RAW>;
+ parent-node = <&level1_rt1_write0>;
+ };
+
+ ife1_rdi_wr: ife1-rdi-wr {
+ cell-index = <21>;
+ node-name = "ife1-rdi-wr";
+ client-name = "ife1";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt0_write0>;
+ };
+
+ ife0_rdi_wr: ife0-rdi-wr {
+ cell-index = <22>;
+ node-name = "ife0-rdi-wr";
+ client-name = "ife0";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt0_write0>;
+ };
+
+ ife2_rdi_wr: ife2-rdi-wr {
+ cell-index = <23>;
+ node-name = "ife2-rdi-wr";
+ client-name = "ife2";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt0_write0>;
+ };
+
+ ife1_rdi_rd: ife1-rdi-rd {
+ cell-index = <24>;
+ node-name = "ife1-rdi-rd";
+ client-name = "ife1";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt1_read0>;
+ };
+
+ ife0_rdi_rd: ife0-rdi-rd {
+ cell-index = <25>;
+ node-name = "ife0-rdi-rd";
+ client-name = "ife0";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_RDI_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3>;
+ parent-node = <&level1_rt1_read0>;
+ };
+
+ ife1_pixelall_wr: ife1-pixelall-wr {
+ cell-index = <26>;
+ node-name = "ife1-pixelall-wr";
+ client-name = "ife1";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IFE_PIXEL_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_LINEAR
+ CAM_CPAS_PATH_DATA_IFE_PDAF
+ CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS
+ CAM_CPAS_PATH_DATA_IFE_PIXEL_RAW>;
+ parent-node = <&level1_rt1_write1>;
+ };
+
+ bps0_all_rd: bps0-all-rd {
+ cell-index = <27>;
+ node-name = "bps0-all-rd";
+ client-name = "bps0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_read0>;
+ };
+
+ ipe0_all_rd: ipe0-all-rd {
+ cell-index = <28>;
+ node-name = "ipe0-all-rd";
+ client-name = "ipe0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IPE_RD_IN
+ CAM_CPAS_PATH_DATA_IPE_RD_REF>;
+ parent-node = <&level1_nrt0_read0>;
+ };
+
+ ipe1_all_rd: ipe1-all-rd {
+ cell-index = <29>;
+ node-name = "ipe1-all-rd";
+ client-name = "ipe1";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IPE_RD_IN
+ CAM_CPAS_PATH_DATA_IPE_RD_REF>;
+ parent-node = <&level1_nrt0_read0>;
+ };
+
+ lrme0_all_rd: lrme0-all-rd {
+ cell-index = <30>;
+ node-name = "lrme0-all-rd";
+ client-name = "lrmecpas0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_read0>;
+ };
+
+ bps0_all_wr: bps0-all-wr {
+ cell-index = <31>;
+ node-name = "bps0-all-wr";
+ client-name = "bps0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level1_nrt0_write0>;
+ };
+
+ ipe0_ref_wr: ipe0-ref-wr {
+ cell-index = <32>;
+ node-name = "ipe0-ref-wr";
+ client-name = "ipe0";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IPE_WR_REF>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level1_nrt0_write0>;
+ };
+
+ ipe1_ref_wr: ipe1-ref-wr {
+ cell-index = <33>;
+ node-name = "ipe1-ref-wr";
+ client-name = "ipe1";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IPE_WR_REF>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level1_nrt0_write0>;
+ };
+
+ lrme0_all_wr: lrme0-all-wr {
+ cell-index = <34>;
+ node-name = "lrme0-all-wr";
+ client-name = "lrmecpas0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level1_nrt0_write0>;
+ };
+
+ ipe1_viddisp_wr: ipe1-viddisp-wr {
+ cell-index = <35>;
+ node-name = "ipe1-viddisp-wr";
+ client-name = "ipe1";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IPE_WR_VID_DISP>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IPE_WR_VID
+ CAM_CPAS_PATH_DATA_IPE_WR_DISP>;
+ parent-node = <&level1_nrt0_write1>;
+ };
+
+ ipe0_viddisp_wr: ipe0-viddisp-wr {
+ cell-index = <36>;
+ node-name = "ipe0-viddisp-wr";
+ client-name = "ipe0";
+ traffic-data =
+ <CAM_CPAS_PATH_DATA_IPE_WR_VID_DISP>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IPE_WR_VID
+ CAM_CPAS_PATH_DATA_IPE_WR_DISP>;
+ parent-node = <&level1_nrt0_write1>;
+ };
+
+ jpeg0_all_wr: jpeg0-all-wr {
+ cell-index = <37>;
+ node-name = "jpeg0-all-wr";
+ client-name = "jpeg-enc0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ parent-node = <&level2_nrt0_write0>;
+ };
+
+ jpeg0_all_rd: jpeg0-all-rd {
+ cell-index = <38>;
+ node-name = "jpeg0-all-rd";
+ client-name = "jpeg-enc0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level2_nrt0_read0>;
+ };
+
+ icp0_all_rd: icp0-all-rd {
+ cell-index = <39>;
+ node-name = "icp0-all-rd";
+ client-name = "icp0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level2_nrt1_read0>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/lito-v2-camera.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/lito-v2-camera.dtsi
new file mode 100755
index 0000000..9b292b1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/lito-v2-camera.dtsi
@@ -0,0 +1,16 @@
+/* Override CSIPHY version */
+&cam_csiphy0 {
+ compatible = "qcom,csiphy-v1.2.2.2", "qcom,csiphy";
+};
+
+&cam_csiphy1 {
+ compatible = "qcom,csiphy-v1.2.2.2", "qcom,csiphy";
+};
+
+&cam_csiphy2 {
+ compatible = "qcom,csiphy-v1.2.2.2", "qcom,csiphy";
+};
+
+&cam_csiphy3 {
+ compatible = "qcom,csiphy-v1.2.2.2", "qcom,csiphy";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/scuba-camera-sensor-idp.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/scuba-camera-sensor-idp.dtsi
new file mode 100755
index 0000000..6c7655b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/scuba-camera-sensor-idp.dtsi
@@ -0,0 +1,313 @@
+#include <dt-bindings/clock/qcom,gcc-scuba.h>
+&soc {
+ led_flash_rear: qcom,camera-flash@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm2250_flash0>;
+ torch-source = <&pm2250_torch0>;
+ switch-source = <&pm2250_switch0>;
+ status = "ok";
+ };
+
+ led_flash_rear_aux: qcom,camera-flash@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera-flash";
+ flash-source = <&pm2250_flash0>;
+ torch-source = <&pm2250_torch0>;
+ switch-source = <&pm2250_switch0>;
+ status = "ok";
+ };
+
+ qcom,cam-res-mgr {
+ compatible = "qcom,cam-res-mgr";
+ status = "ok";
+ };
+};
+
+&cam_cci0 {
+ actuator_rear: qcom,actuator0 {
+ cell-index = <0>;
+ compatible = "qcom,actuator";
+ cci-master = <0>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ actuator_rear_aux: qcom,actuator1 {
+ cell-index = <1>;
+ compatible = "qcom,actuator";
+ cci-master = <1>;
+ cam_vaf-supply = <&L5P>;
+ regulator-names = "cam_vaf";
+ rgltr-cntrl-support;
+ rgltr-min-voltage = <2800000>;
+ rgltr-max-voltage = <2800000>;
+ rgltr-load-current = <100000>;
+ status = "ok";
+ };
+
+ eeprom_rear: qcom,eeprom0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_vaf-supply = <&L5P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1050000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1050000 0 2800000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear0_reset_suspend>;
+ gpios = <&tlmm 20 0>,
+ <&tlmm 18 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ eeprom_rear_aux: qcom,eeprom1 {
+ cell-index = <1>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_vaf-supply = <&L5P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk", "cam_vaf";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>;
+ rgltr-load-current = <120000 80000 1200000 0 100000>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_rear1_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_rear1_reset_suspend>;
+ gpios = <&tlmm 21 0>,
+ <&tlmm 19 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ eeprom_front: qcom,eeprom2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_front0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_front0_reset_suspend>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 24 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+
+ /* Rear*/
+ qcom,cam-sensor0 {
+ cell-index = <0>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <0>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear>;
+ led-flash-src = <&led_flash_rear>;
+ eeprom-src = <&eeprom_rear>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L4P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1050000 0>;
+ rgltr-max-voltage = <1800000 2800000 1050000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear0_reset_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear0_reset_suspend>;
+ gpios = <&tlmm 20 0>,
+ <&tlmm 18 0>;
+ gpio-reset = <1>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ sensor-mode = <0>;
+ cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ /*Rear Aux*/
+ qcom,cam-sensor1 {
+ cell-index = <1>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ actuator-src = <&actuator_rear_aux>;
+ led-flash-src = <&led_flash_rear_aux>;
+ eeprom-src = <&eeprom_rear_aux>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L3P>;
+ cam_vdig-supply = <&L1P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1200000 0>;
+ rgltr-max-voltage = <1800000 2800000 1200000 0>;
+ rgltr-load-current = <120000 80000 1200000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_rear1_reset_active
+ &cam_sensor_csi_mux_oe_active
+ &cam_sensor_csi_mux_sel_active>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_rear1_reset_suspend
+ &cam_sensor_csi_mux_oe_suspend
+ &cam_sensor_csi_mux_sel_suspend>;
+ gpios = <&tlmm 21 0>,
+ <&tlmm 19 0>,
+ <&tlmm 113 0>,
+ <&tlmm 114 0>;
+ gpio-reset = <1>;
+ gpio-custom1 = <2>;
+ gpio-custom2 = <3>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1",
+ "CAM_CSIMUX_OE0",
+ "CAM_CSIMUX_SEL0";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <19200000>;
+ };
+
+ /*Front*/
+ qcom,cam-sensor2 {
+ cell-index = <2>;
+ compatible = "qcom,cam-sensor";
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <270>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <0>;
+ eeprom-src = <&eeprom_front>;
+ cam_vio-supply = <&L7P>;
+ cam_vana-supply = <&L6P>;
+ cam_vdig-supply = <&L2P>;
+ cam_clk-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "cam_vio", "cam_vana", "cam_vdig",
+ "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 2800000 1056000 0>;
+ rgltr-max-voltage = <1800000 2800000 1056000 0>;
+ rgltr-load-current = <0 80000 105000 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_front0_reset_active
+ &cam_sensor_csi_mux_oe_active
+ &cam_sensor_csi_mux_sel_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_front0_reset_suspend
+ &cam_sensor_csi_mux_oe_suspend
+ &cam_sensor_csi_mux_sel_suspend>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 24 0>,
+ <&tlmm 113 0>,
+ <&tlmm 114 0>;
+ gpio-reset = <1>;
+ gpio-custom1 = <2>;
+ gpio-custom2 = <3>;
+ gpio-req-tbl-num = <0 1>;
+ gpio-req-tbl-flags = <1 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_CSIMUX_OE0",
+ "CAM_CSIMUX_SEL0";
+ sensor-mode = <0>;
+ cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/scuba-camera.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/scuba-camera.dtsi
new file mode 100755
index 0000000..beff588
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/scuba-camera.dtsi
@@ -0,0 +1,762 @@
+#include <dt-bindings/msm/msm-camera.h>
+
+&soc {
+ qcom,cam-req-mgr {
+ compatible = "qcom,cam-req-mgr";
+ status = "ok";
+ };
+
+ cam_csiphy0: qcom,csiphy0 {
+ cell-index = <0>;
+ compatible = "qcom,csiphy-v2.0", "qcom,csiphy";
+ reg = <0x05C52000 0x1000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x52000>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr";
+ gdscr-supply = <&gcc_camss_top_gdsc>;
+ csi-vdd-voltage = <1200000>;
+ mipi-csi-vdd-supply = <&L5A>;
+ clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_CPHY_0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy0_clk",
+ "csi0phytimer_clk_src",
+ "csi0phytimer_clk";
+ src-clock-name = "csi0phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ clock-rates =
+ <19200000 0 19200000 0>,
+ <341330000 0 200000000 0>,
+ <341330000 0 200000000 0>,
+ <384000000 0 268800000 0>;
+ status = "ok";
+ };
+
+ cam_csiphy1: qcom,csiphy1 {
+ cell-index = <1>;
+ compatible = "qcom,csiphy-v2.0", "qcom,csiphy";
+ reg = <0x05C53000 0x1000>;
+ reg-names = "csiphy";
+ reg-cam-base = <0x53000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csiphy";
+ regulator-names = "gdscr";
+ gdscr-supply = <&gcc_camss_top_gdsc>;
+ csi-vdd-voltage = <1200000>;
+ mipi-csi-vdd-supply = <&L5A>;
+ clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_CPHY_1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>;
+ clock-names = "cphy_rx_clk_src",
+ "csiphy1_clk",
+ "csi1phytimer_clk_src",
+ "csi1phytimer_clk";
+ src-clock-name = "csi1phytimer_clk_src";
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ clock-rates =
+ <19200000 0 19200000 0>,
+ <341330000 0 200000000 0>,
+ <341330000 0 200000000 0>,
+ <384000000 0 268800000 0>;
+ status = "ok";
+ };
+
+ cam_cci0: qcom,cci0 {
+ cell-index = <0>;
+ compatible = "qcom,cci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x05C1B000 0x1000>;
+ reg-names = "cci";
+ reg-cam-base = <0x1B000>;
+ interrupt-names = "cci";
+ interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>;
+ status = "ok";
+ gdscr-supply = <&gcc_camss_top_gdsc>;
+ regulator-names = "gdscr";
+ clocks = <&gcc GCC_CAMSS_CCI_0_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK_SRC>;
+ clock-names = "cci_0_clk",
+ "cci_0_clk_src";
+ src-clock-name = "cci_0_clk_src";
+ clock-cntl-level = "svs";
+ clock-rates = <0 37500000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cci0_active &cci1_active>;
+ pinctrl-1 = <&cci0_suspend &cci1_suspend>;
+ gpios = <&tlmm 22 0>,
+ <&tlmm 23 0>,
+ <&tlmm 29 0>,
+ <&tlmm 30 0>;
+ gpio-req-tbl-num = <0 1 2 3>;
+ gpio-req-tbl-flags = <1 1 1 1>;
+ gpio-req-tbl-label = "CCI_I2C_DATA0",
+ "CCI_I2C_CLK0",
+ "CCI_I2C_DATA1",
+ "CCI_I2C_CLK1";
+
+ i2c_freq_100Khz_cci0: qcom,i2c_standard_mode {
+ hw-thigh = <201>;
+ hw-tlow = <174>;
+ hw-tsu-sto = <204>;
+ hw-tsu-sta = <231>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <162>;
+ hw-tbuf = <227>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_400Khz_cci0: qcom,i2c_fast_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_custom_cci0: qcom,i2c_custom_mode {
+ hw-thigh = <38>;
+ hw-tlow = <56>;
+ hw-tsu-sto = <40>;
+ hw-tsu-sta = <40>;
+ hw-thd-dat = <22>;
+ hw-thd-sta = <35>;
+ hw-tbuf = <62>;
+ hw-scl-stretch-en = <1>;
+ hw-trdhld = <6>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+
+ i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode {
+ hw-thigh = <16>;
+ hw-tlow = <22>;
+ hw-tsu-sto = <17>;
+ hw-tsu-sta = <18>;
+ hw-thd-dat = <16>;
+ hw-thd-sta = <15>;
+ hw-tbuf = <24>;
+ hw-scl-stretch-en = <0>;
+ hw-trdhld = <3>;
+ hw-tsp = <3>;
+ cci-clk-src = <37500000>;
+ status = "ok";
+ };
+ };
+
+ qcom,cam_smmu {
+ compatible = "qcom,msm-cam-smmu";
+ status = "ok";
+
+ msm_cam_smmu_tfe {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x400 0x000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ label = "tfe";
+ tfe_iova_mem_map: iova-mem-map {
+ /* IO region is approximately 3.4 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_ope {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x820 0x000>,
+ <&apps_smmu 0x840 0x000>;
+ qcom,iommu-faults = "non-fatal";
+ multiple-client-devices;
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ label = "ope", "ope-cdm0";
+ ope_iova_mem_map: iova-mem-map {
+ /* IO region is approximately 3.4 GB */
+ iova-mem-region-io {
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_cpas_cdm {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_smmu 0x800 0x000>;
+ label = "cpas-cdm0";
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
+ cpas_cdm_iova_mem_map: iova-mem-map {
+ iova-mem-region-io {
+ /* IO region is approximately 3.4 GB */
+ iova-region-name = "io";
+ iova-region-start = <0x7400000>;
+ iova-region-len = <0xd8c00000>;
+ iova-region-id = <0x3>;
+ status = "ok";
+ };
+ };
+ };
+
+ msm_cam_smmu_secure {
+ compatible = "qcom,msm-cam-smmu-cb";
+ label = "cam-secure";
+ qcom,secure-cb;
+ };
+
+ };
+
+ qcom,cam-cpas@5c11000 {
+ cell-index = <0>;
+ compatible = "qcom,cam-cpas";
+ label = "cpas";
+ arch-compat = "cpas_top";
+ status = "ok";
+ reg-names = "cam_cpas_top", "cam_camnoc";
+ reg = <0x5c11000 0x1000>,
+ <0x5c13000 0x4000>;
+ reg-cam-base = <0x11000 0x13000>;
+ cam_hw_fuse = <CAM_CPAS_SECURE_CAMERA_ENABLE 0x01B401E4 8>;
+ interrupt-names = "cpas_camnoc";
+ interrupts = <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>;
+ camnoc-axi-min-ib-bw = <3000000000>; /*Need to be verified*/
+ regulator-names = "camss-vdd";
+ camss-vdd-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "gcc_camss_ahb_clk",
+ "gcc_camss_top_ahb_clk",
+ "gcc_camss_top_ahb_clk_src",
+ "gcc_camss_axi_clk",
+ "gcc_camss_axi_clk_src",
+ "gcc_camss_nrt_axi_clk",
+ "gcc_camss_rt_axi_clk";
+ clocks =
+ <&gcc GCC_CAMERA_AHB_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>,
+ <&gcc GCC_CAMSS_AXI_CLK>,
+ <&gcc GCC_CAMSS_AXI_CLK_SRC>,
+ <&gcc GCC_CAMSS_NRT_AXI_CLK>,
+ <&gcc GCC_CAMSS_RT_AXI_CLK>;
+ src-clock-name = "gcc_camss_axi_clk_src";
+ clock-rates =
+ <0 0 0 0 0 0 0>,
+ <0 0 80000000 0 19200000 0 0>,
+ <0 0 80000000 0 150000000 0 0>,
+ <0 0 80000000 0 200000000 0 0>,
+ <0 0 80000000 0 300000000 0 0>,
+ <0 0 80000000 0 300000000 0 0>,
+ <0 0 80000000 0 300000000 0 0>;
+ clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs",
+ "svs_l1", "nominal", "turbo";
+ control-camnoc-axi-clk;
+ camnoc-bus-width = <32>;
+ camnoc-axi-clk-bw-margin-perc = <20>;
+ qcom,msm-bus,name = "cam_ahb";
+ qcom,msm-bus,num-cases = <7>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 133333>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 133333>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 150000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 300000>,
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_CAMERA_CFG 0 300000>;
+ vdd-corners = <RPMH_REGULATOR_LEVEL_RETENTION
+ RPMH_REGULATOR_LEVEL_MIN_SVS
+ RPMH_REGULATOR_LEVEL_LOW_SVS
+ RPMH_REGULATOR_LEVEL_SVS
+ RPMH_REGULATOR_LEVEL_SVS_L1
+ RPMH_REGULATOR_LEVEL_NOM
+ RPMH_REGULATOR_LEVEL_NOM_L1
+ RPMH_REGULATOR_LEVEL_NOM_L2
+ RPMH_REGULATOR_LEVEL_TURBO
+ RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ vdd-corner-ahb-mapping = "suspend", "minsvs",
+ "lowsvs", "svs", "svs_l1",
+ "nominal", "nominal", "nominal",
+ "turbo", "turbo";
+ client-id-based;
+ client-names =
+ "csiphy0", "csiphy1", "cci0",
+ "csid0", "csid1", "tfe0",
+ "tfe1", "ope0", "cam-cdm-intf0",
+ "cpas-cdm0", "ope-cdm0", "tpg0", "tpg1";
+
+ camera-bus-nodes {
+ level2-nodes {
+ level-index = <2>;
+ level2_rt0_rd_wr_sum: level2-rt0-rd-wr-sum {
+ cell-index = <0>;
+ node-name = "level2-rt0-rd-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_hf_0";
+ ib-bw-voting-needed;
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_hf_0_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_HF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_HF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+ };
+
+ level2_nrt0_rd_wr_sum: level2-nrt0-rd-wr-sum {
+ cell-index = <1>;
+ node-name = "level2-nrt0-rd-wr-sum";
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM>;
+ qcom,axi-port-name = "cam_sf_0";
+ qcom,axi-port-mnoc {
+ qcom,msm-bus,name =
+ "cam_sf_0_mnoc";
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_SF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_SF
+ MSM_BUS_SLAVE_EBI_CH0 0 0>;
+ };
+ };
+ };
+
+ level1-nodes {
+ level-index = <1>;
+ camnoc-max-needed;
+ level1_rt0_wr: level1-rt0-wr {
+ cell-index = <2>;
+ node-name = "level1-rt0-wr";
+ parent-node = <&level2_rt0_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
+ };
+
+ level1_nrt0_rd_wr: level1-nrt0-rd-wr {
+ cell-index = <3>;
+ node-name = "level1-nrt0-rd-wr";
+ parent-node = <&level2_nrt0_rd_wr_sum>;
+ traffic-merge-type =
+ <CAM_CPAS_TRAFFIC_MERGE_SUM_INTERLEAVE>;
+ };
+ };
+
+ level0-nodes {
+ level-index = <0>;
+ ope0_all_wr: ope0-all-wr {
+ cell-index = <4>;
+ node-name = "ope0-all-wr";
+ client-name = "ope0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_OPE_WR_VID
+ CAM_CPAS_PATH_DATA_OPE_WR_DISP
+ CAM_CPAS_PATH_DATA_OPE_WR_REF>;
+ parent-node = <&level1_nrt0_rd_wr>;
+ };
+
+ ope0_all_rd: ope0-all-rd {
+ cell-index = <5>;
+ node-name = "ope0-all-rd";
+ client-name = "ope0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_OPE_RD_IN
+ CAM_CPAS_PATH_DATA_OPE_RD_REF>;
+ parent-node = <&level1_nrt0_rd_wr>;
+ };
+
+ tfe0_all_wr: tfe0-all-wr {
+ cell-index = <6>;
+ node-name = "tfe0-all-wr";
+ client-name = "tfe0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3
+ CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS>;
+ parent-node = <&level1_rt0_wr>;
+ };
+
+ tfe1_all_wr: tfe1-all-wr {
+ cell-index = <7>;
+ node-name = "tfe1-all-wr";
+ client-name = "tfe1";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_WRITE>;
+ constituent-paths =
+ <CAM_CPAS_PATH_DATA_IFE_RDI0
+ CAM_CPAS_PATH_DATA_IFE_RDI1
+ CAM_CPAS_PATH_DATA_IFE_RDI2
+ CAM_CPAS_PATH_DATA_IFE_RDI3
+ CAM_CPAS_PATH_DATA_IFE_VID
+ CAM_CPAS_PATH_DATA_IFE_DISP
+ CAM_CPAS_PATH_DATA_IFE_STATS>;
+ parent-node = <&level1_rt0_wr>;
+ };
+
+ cpas_cdm0_all_rd: cpas-cdm0-all-rd {
+ cell-index = <9>;
+ node-name = "cpas-cdm0-all-rd";
+ client-name = "cpas-cdm0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_rd_wr>;
+ };
+
+ ope_cdm0_all_rd: ope-cdm0-all-rd {
+ cell-index = <10>;
+ node-name = "ope-cdm0-all-rd";
+ client-name = "ope-cdm0";
+ traffic-data = <CAM_CPAS_PATH_DATA_ALL>;
+ traffic-transaction-type =
+ <CAM_CPAS_TRANSACTION_READ>;
+ parent-node = <&level1_nrt0_rd_wr>;
+ };
+ };
+ };
+ };
+
+ qcom,cam-cdm-intf {
+ compatible = "qcom,cam-cdm-intf";
+ cell-index = <0>;
+ label = "cam-cdm-intf";
+ num-hw-cdm = <2>;
+ cdm-client-names = "vfe";
+ status = "ok";
+ };
+
+ cam_cpas_cdm: qcom,cpas-cdm0@5c23000 {
+ cell-index = <0>;
+ compatible = "qcom,cam-cpas-cdm2_0";
+ label = "cpas-cdm";
+ reg = <0x5c23000 0x400>;
+ reg-names = "cpas-cdm0";
+ reg-cam-base = <0x23000>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "cpas-cdm0";
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names = "cam_cc_cpas_top_ahb_clk";
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>;
+ clock-rates = <0>;
+ clock-cntl-level = "svs";
+ cdm-client-names = "tfe0", "tfe1";
+ config-fifo;
+ fifo-depths = <64 64 64 64>;
+ status = "ok";
+ };
+
+ cam_ope_cdm: qcom,ope-cdm0@5c42000 {
+ cell-index = <0>;
+ compatible = "qcom,cam-ope-cdm2_0";
+ label = "ope-cdm";
+ reg = <0x5c42000 0x400>;
+ reg-names = "ope-cdm0";
+ reg-cam-base = <0x42000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ope-cdm0";
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "ope_ahb_clk",
+ "ope_clk_src",
+ "ope_clk";
+ clocks =
+ <&gcc GCC_CAMSS_OPE_AHB_CLK>,
+ <&gcc GCC_CAMSS_OPE_CLK_SRC>,
+ <&gcc GCC_CAMSS_OPE_CLK>;
+ clock-rates = <0 0 0>,
+ <0 0 0>,
+ <0 0 0>,
+ <0 0 0>;
+ clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
+ cdm-client-names = "ope";
+ config-fifo;
+ fifo-depths = <64 64 64 64>;
+ status = "ok";
+ };
+
+ qcom,cam-isp {
+ compatible = "qcom,cam-isp";
+ arch-compat = "tfe";
+ status = "ok";
+ };
+
+ cam_tfe_csid0: qcom,tfe_csid0@5c6e000 {
+ cell-index = <0>;
+ compatible = "qcom,csid530";
+ reg-names = "csid", "top", "camnoc";
+ reg = <0x5c6e000 0x1000>,
+ <0x5c11000 0x1000>,
+ <0x5c13000 0x4000>;
+ reg-cam-base = <0x6e000 0x11000 0x13000>;
+ interrupt-names = "csid0";
+ interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_csid_clk_src",
+ "tfe_csid_clk",
+ "cphy_rx_clk_src",
+ "tfe_cphy_rx_clk",
+ "tfe_clk_src",
+ "tfe_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_0_CSID_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CSID_CLK>,
+ <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CLK>;
+ clock-rates =
+ <240000000 0 240000000 0 256000000 0>,
+ <384000000 0 341333333 0 460800000 0>,
+ <426400000 0 384000000 0 576000000 0>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_tfe0: qcom,tfe0@5c6e000 {
+ cell-index = <0>;
+ compatible = "qcom,tfe530";
+ reg-names = "tfe0";
+ reg = <0x5c6e000 0x5000>;
+ reg-cam-base = <0x6e000>;
+ interrupt-names = "tfe0";
+ interrupts = <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_clk_src",
+ "tfe_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CLK>;
+ clock-rates =
+ <256000000 0>,
+ <460800000 0>,
+ <576000000 0>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_tfe_csid1: qcom,tfe_csid1@5c75000 {
+ cell-index = <1>;
+ compatible = "qcom,csid530";
+ reg-names = "csid", "top", "camnoc";
+ reg = <0x5c75000 0x1000>,
+ <0x5c11000 0x1000>,
+ <0x5c13000 0x4000>;
+ reg-cam-base = <0x75000 0x11000 0x13000>;
+ interrupt-names = "csid1";
+ interrupts = <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_csid_clk_src",
+ "tfe_csid_clk",
+ "cphy_rx_clk_src",
+ "tfe_cphy_rx_clk",
+ "tfe_clk_src",
+ "tfe_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_1_CSID_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CSID_CLK>,
+ <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CLK>;
+ clock-rates =
+ <240000000 0 240000000 0 256000000 0>,
+ <384000000 0 341333333 0 460800000 0>,
+ <426400000 0 384000000 0 576000000 0>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_csid_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_tfe1: qcom,tfe1@5c75000 {
+ cell-index = <1>;
+ compatible = "qcom,tfe530";
+ reg-names = "tfe1";
+ reg = <0x5c75000 0x5000>;
+ reg-cam-base = <0x75000>;
+ interrupt-names = "tfe1";
+ interrupts = <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "tfe_clk_src",
+ "tfe_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CLK>;
+ clock-rates =
+ <256000000 0>,
+ <460800000 0>,
+ <576000000 0>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "tfe_clk_src";
+ clock-control-debugfs = "true";
+ status = "ok";
+ };
+
+ cam_tfe_tpg0: qcom,tpg0@5c66000 {
+ cell-index = <0>;
+ compatible = "qcom,tpgv1";
+ reg-names = "tpg0", "top";
+ reg = <0x5c66000 0x400>,
+ <0x5c11000 0x1000>;
+ reg-cam-base = <0x66000 0x11000>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "cphy_rx_clk_src",
+ "tfe_0_cphy_rx_clk",
+ "gcc_camss_cphy_0_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_CPHY_0_CLK>;
+ clock-rates =
+ <240000000 0 0>,
+ <341333333 0 0>,
+ <384000000 0 0>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "cphy_rx_clk_src";
+ clock-control-debugfs = "false";
+ status = "ok";
+ };
+
+ cam_tfe_tpg1: qcom,tpg0@5c68000 {
+ cell-index = <1>;
+ compatible = "qcom,tpgv1";
+ reg-names = "tpg0", "top";
+ reg = <0x5c68000 0x400>,
+ <0x5c11000 0x1000>;
+ reg-cam-base = <0x68000 0x11000>;
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "cphy_rx_clk_src",
+ "tfe_1_cphy_rx_clk",
+ "gcc_camss_cphy_1_clk";
+ clocks =
+ <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>,
+ <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>,
+ <&gcc GCC_CAMSS_CPHY_1_CLK>;
+ clock-rates =
+ <240000000 0 0>,
+ <341333333 0 0>,
+ <384000000 0 0>;
+ clock-cntl-level = "svs", "svs_l1", "turbo";
+ src-clock-name = "cphy_rx_clk_src";
+ clock-control-debugfs = "false";
+ status = "ok";
+ };
+
+ qcom,cam-ope {
+ compatible = "qcom,cam-ope";
+ compat-hw-name = "qcom,ope";
+ num-ope = <1>;
+ status = "ok";
+ };
+
+ ope: qcom,ope@0x5c42000 {
+ cell-index = <0>;
+ compatible = "qcom,ope";
+ reg =
+ <0x5c42000 0x400>,
+ <0x5c42400 0x200>,
+ <0x5c42600 0x200>,
+ <0x5c42800 0x4400>,
+ <0x5c46c00 0x190>,
+ <0x5c46d90 0xA00>;
+ reg-names =
+ "ope_cdm",
+ "ope_top",
+ "ope_qos",
+ "ope_pp",
+ "ope_bus_rd",
+ "ope_bus_wr";
+ reg-cam-base = <0x42000 0x42400 0x42600 0x42800 0x46c00 0x46d90>;
+ interrupts = <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ope";
+ regulator-names = "camss";
+ camss-supply = <&gcc_camss_top_gdsc>;
+ clock-names =
+ "ope_ahb_clk_src",
+ "ope_ahb_clk",
+ "ope_clk_src",
+ "ope_clk";
+ clocks =
+ <&gcc GCC_CAMSS_OPE_AHB_CLK_SRC>,
+ <&gcc GCC_CAMSS_OPE_AHB_CLK>,
+ <&gcc GCC_CAMSS_OPE_CLK_SRC>,
+ <&gcc GCC_CAMSS_OPE_CLK>;
+ clock-rates =
+ <171428571 0 200000000 0>,
+ <171428571 0 266600000 0>,
+ <240000000 0 465000000 0>,
+ <240000000 0 580000000 0>;
+ clock-cntl-level = "svs", "svs_l1", "nominal", "turbo";
+ src-clock-name = "ope_clk_src";
+ status = "ok";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/camera/zebra-scanner-sensor-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/camera/zebra-scanner-sensor-mtp.dtsi
new file mode 100644
index 0000000..906242f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/camera/zebra-scanner-sensor-mtp.dtsi
@@ -0,0 +1,58 @@
+/* Copyright (C) 2021 Tcl Corporation Limited */
+
+&qupv3_se7_i2c{
+ status = "ok";
+ qcom,clk-freq-out = <100000>;
+
+ zebra,scan-sensor@5c{
+ cell-index = <1>;
+ compatible = "zebra,se47xx";
+ reg = <0x5c>;
+ csiphy-sd-index = <1>;
+ sensor-position-roll = <90>;
+ sensor-position-pitch = <0>;
+ sensor-position-yaw = <180>;
+ cam_vana-supply = <&L11A>;
+ cam_clk-supply = <&cam_cc_titan_top_gdsc>;
+ regulator-names = "cam_vana", "cam_clk";
+ rgltr-cntrl-support;
+ pwm-switch;
+ rgltr-min-voltage = <1800000 0>;
+ rgltr-max-voltage = <1800000 0>;
+ rgltr-load-current = <0 0>;
+ gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_active_rear_aux2>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_suspend_rear_aux2>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 70 0>,
+ <&tlmm 18 0>,
+ <&tlmm 72 0>,
+ <&tlmm 73 0>,
+ <&tlmm 74 0>;
+ gpio-reset = <1>;
+ gpio-standby = <2>;
+ gpio-custom1 = <3>;
+ gpio-custom2 = <4>;
+ gpio-custom3 = <5>;
+ gpio-req-tbl-num = <0 1 2 3 4 5>;
+ gpio-req-tbl-flags = <1 0 0 0 0 0>;
+ gpio-req-tbl-label = "CAMIF_MCLK1",
+ "SCAN_SHIFT",
+ "BOOST_5V",
+ "SCAN_VCC_ILLUM",
+ "SCAN_VCC",
+ "SCAN_SHIFT_ENABLE";
+ sensor-mode = <0>;
+ cci-device = <0>;
+ cci-master = <1>;
+ status = "disabled";
+ clocks = <&camcc CAM_CC_MCLK1_CLK>;
+ clock-names = "cam_clk";
+ clock-cntl-level = "turbo";
+ clock-rates = <24000000>;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-ext-bridge-1080p.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-ext-bridge-1080p.dtsi
new file mode 100755
index 0000000..07d398e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-ext-bridge-1080p.dtsi
@@ -0,0 +1,46 @@
+&mdss_mdp {
+ dsi_ext_bridge_1080p: qcom,mdss_dsi_ext_bridge_1080p {
+ qcom,mdss-dsi-panel-name = "ext video mode dsi bridge";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-t-clk-post = <0x03>;
+ qcom,mdss-dsi-t-clk-pre = <0x24>;
+ qcom,mdss-dsi-force-clock-lane-hs;
+ qcom,mdss-dsi-ext-bridge-mode;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1920>;
+ qcom,mdss-dsi-panel-height = <1080>;
+ qcom,mdss-dsi-h-front-porch = <88>;
+ qcom,mdss-dsi-h-back-porch = <148>;
+ qcom,mdss-dsi-h-pulse-width = <44>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <36>;
+ qcom,mdss-dsi-v-front-porch = <4>;
+ qcom,mdss-dsi-v-pulse-width = <5>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi
new file mode 100755
index 0000000..9dc1a26
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi
@@ -0,0 +1,151 @@
+&mdss_mdp {
+ dsi_hx83112a_truly_video: qcom,mdss_dsi_hx83112a_truly_video {
+ qcom,mdss-dsi-panel-name =
+ "hx83112a video mode dsi truly panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <65>;
+ qcom,mdss-pan-physical-height-dimension = <129>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <42>;
+ qcom,mdss-dsi-h-back-porch = <42>;
+ qcom,mdss-dsi-h-pulse-width = <10>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <15>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <3>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 04 B9 83 11 2A
+ 39 01 00 00 00 00 09 B1 08 29 29 00 00 4F 54
+ 33
+ 39 01 00 00 00 00 11 B2 00 02 00 80 70 00 08
+ 26 FC 01 00 03 15 A3 87 09
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 03 D2 2C 2C
+ 39 01 00 00 00 00 1C B4 01 CE 01 CE 01 CE 0A
+ CE 0A CE 0A CE 00 FF 00 FF 00 00 22 23 00
+ 28 0A 13 14 00 8A
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 0A B4 00 92 12 22 88 12 12
+ 00 53
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 04 B6 82 82 E3
+ 39 01 00 00 00 00 02 CC 08
+ 39 01 00 00 00 00 2B D3 40 00 00 00 00 01 01
+ 0A 0A 07 07 00 08 09 09 09 09 32 10 09 00
+ 09 32 21 0A 00 0A 32 10 08 00 00 00 00 00
+ 00 00 00 00 0B 08 82
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 09 D3 00 00 19 00 00 0A 00
+ 81
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 31 D5 18 18 18 18 18 18 18
+ 18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0
+ 18 40 40 01 00 07 06 05 04 03 02 21 20 18
+ 18 19 19 18 18 03 03 18 18 18 18 18 18
+ 39 01 00 00 00 00 31 D6 18 18 18 18 18 18 18
+ 18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0
+ 18 40 40 02 03 04 05 06 07 00 01 20 21 18
+ 18 18 18 19 19 20 20 18 18 18 18 18 18
+ 39 01 00 00 00 00 19 D8 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA
+ AA AA AA AA AA AA AA AA AA AA AA AA AA AA
+ AA AA AA
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 0D D8 AF FF FA AA BA AA AA
+ FF FA AA BA AA
+ 39 01 00 00 00 00 02 BD 03
+ 39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA
+ AA AA AA AA AA AA AA AA AA AA AA AA AA AA
+ AA AA AA
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 18 E7 0E 0E 1E 6A 1D 6A 00
+ 32 02 02 00 00 02 02 02 05 14 14 32 B9 23
+ B9 08
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 0A E7 02 00 98 01 9A 0D A8
+ 0E 01
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 1E E7 00 00 08 00 01 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 04 00 00 00 00 02 00
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 02 C1 01
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
+ C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
+ 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
+ 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
+ C6 B8 9C 37 43 3D E5 00
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
+ C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
+ 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
+ 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
+ C6 B8 9C 37 43 3D E5 00
+ 39 01 00 00 00 00 02 BD 03
+ 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
+ C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
+ 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
+ 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
+ C6 B8 9C 37 43 3D E5 00
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 02 E9 C3
+ 39 01 00 00 00 00 03 CB 92 01
+ 39 01 00 00 00 00 02 E9 3F
+ 39 01 00 00 00 00 07 C7 70 00 04 E0 33 00
+ 39 01 00 00 00 00 03 51 0F FF
+ 39 01 00 00 00 00 02 53 24
+ 39 01 00 00 00 00 02 55 00
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 96 00 02 11 00
+ 05 01 00 00 32 00 02 29 00];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-hx8394d-720p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-hx8394d-720p-video.dtsi
new file mode 100755
index 0000000..6de6c6c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-hx8394d-720p-video.dtsi
@@ -0,0 +1,87 @@
+&mdss_mdp {
+ dsi_hx8394d_720_vid: qcom,mdss_dsi_hx8394d_720p_video {
+ qcom,mdss-dsi-panel-name = "hx8394d 720p video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <52>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <24>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <20>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 04 b9 ff 83 94
+ 39 01 00 00 00 00 03 ba 33 83
+ 39 01 00 00 00 00 10 b1 6c 12 12
+ 37 04 11 f1 80 ec 94 23 80 c0
+ d2 18
+ 39 01 00 00 00 00 0c b2 00 64 0e
+ 0d 32 23 08 08 1c 4d 00
+ 39 01 00 00 00 00 0d b4 00 ff 03
+ 50 03 50 03 50 01 6a 01 6a
+ 39 01 00 00 00 00 02 bc 07
+ 39 01 00 00 00 00 04 bf 41 0e 01
+ 39 01 00 00 00 00 1f d3 00 07 00
+ 00 00 10 00 32 10 05 00 00 32
+ 10 00 00 00 32 10 00 00 00 36
+ 03 09 09 37 00 00 37
+ 39 01 00 00 00 00 2d d5 02 03 00
+ 01 06 07 04 05 20 21 22 23 18
+ 18 18 18 18 18 18 18 18 18 18
+ 18 18 18 18 18 18 18 18 18 18
+ 18 18 18 18 18 24 25 18 18 19
+ 19
+ 39 01 00 00 00 00 2d d6 05 04 07
+ 06 01 00 03 02 23 22 21 20 18
+ 18 18 18 18 18 58 58 18 18 18
+ 18 18 18 18 18 18 18 18 18 18
+ 18 18 18 18 18 25 24 19 19 18
+ 18
+ 39 01 00 00 00 00 02 cc 09
+ 39 01 00 00 00 00 03 c0 30 14
+ 39 01 00 00 00 00 05 c7 00 c0 40 c0
+ 39 01 00 00 00 00 03 b6 43 43
+ 05 01 00 00 c8 00 02 11 00
+ 05 01 00 00 0a 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00
+ 05 01 00 00 00 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <1>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings = [
+ 79 1a 12 00 3e 42
+ 16 1e 15 03 04 00
+ ];
+ qcom,mdss-dsi-t-clk-post = <0x04>;
+ qcom,mdss-dsi-t-clk-pre = <0x1b>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
+ qcom,mdss-pan-physical-width-dimension = <59>;
+ qcom,mdss-pan-physical-height-dimension = <104>;
+
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi
new file mode 100755
index 0000000..8a05258
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi
@@ -0,0 +1,240 @@
+&mdss_mdp {
+ dsi_nt35597_truly_dsc_cmd: qcom,mdss_dsi_nt35597_dsc_cmd_truly {
+ qcom,mdss-dsi-panel-name =
+ "nt35597 cmd mode dsi truly panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <1>;
+ qcom,dsi-phy-num = <1>;
+ qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <131>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x1 0x1>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f ae
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6D
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c D8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 C0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x0(2 Port SDC)
+ * 0x01(1 PortA FBC)
+ * 0x02(MTK) 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+
+ qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi
new file mode 100755
index 0000000..2d888cb
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi
@@ -0,0 +1,226 @@
+&mdss_mdp {
+ dsi_nt35597_truly_dsc_video: qcom,mdss_dsi_nt35597_dsc_video_truly {
+ qcom,mdss-dsi-panel-name =
+ "nt35597 video mode dsi truly panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <1>;
+ qcom,dsi-phy-num = <1>;
+ qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <131>;
+ qcom,mdss-dsi-dma-schedule-line = <5>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f aE
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6d
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x00(2 Port SDC);
+ * 0x01(1 PortA FBC);
+ * 0x02(MTK); 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 39 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 03
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi
new file mode 100755
index 0000000..cddf916
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi
@@ -0,0 +1,219 @@
+&mdss_mdp {
+ dsi_dual_nt35597_truly_cmd: qcom,mdss_dsi_nt35597_truly_wqxga_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Dual nt35597 cmd mode dsi truly panel without DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <131>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x1 0x1>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1E
+ 15 01 00 00 00 00 02 0B 73
+ 15 01 00 00 00 00 02 0C 73
+ 15 01 00 00 00 00 02 0E B0
+ 15 01 00 00 00 00 02 0F AE
+ 15 01 00 00 00 00 02 11 B8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5A 00
+ 15 01 00 00 00 00 02 5B 01
+ 15 01 00 00 00 00 02 5C 80
+ 15 01 00 00 00 00 02 5D 81
+ 15 01 00 00 00 00 02 5E 00
+ 15 01 00 00 00 00 02 5F 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1C
+ 15 01 00 00 00 00 02 01 0B
+ 15 01 00 00 00 00 02 02 0C
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0F
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8A
+ 15 01 00 00 00 00 02 0A 13
+ 15 01 00 00 00 00 02 0B 13
+ 15 01 00 00 00 00 02 0C 15
+ 15 01 00 00 00 00 02 0D 15
+ 15 01 00 00 00 00 02 0E 17
+ 15 01 00 00 00 00 02 0F 17
+ 15 01 00 00 00 00 02 10 1C
+ 15 01 00 00 00 00 02 11 0B
+ 15 01 00 00 00 00 02 12 0C
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0F
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8A
+ 15 01 00 00 00 00 02 1A 13
+ 15 01 00 00 00 00 02 1B 13
+ 15 01 00 00 00 00 02 1C 15
+ 15 01 00 00 00 00 02 1D 15
+ 15 01 00 00 00 00 02 1E 17
+ 15 01 00 00 00 00 02 1F 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6D
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 E0 00
+ 15 01 00 00 00 00 02 DC 21
+ 15 01 00 00 00 00 02 DD 22
+ 15 01 00 00 00 00 02 DE 07
+ 15 01 00 00 00 00 02 DF 07
+ 15 01 00 00 00 00 02 E3 6D
+ 15 01 00 00 00 00 02 E1 07
+ 15 01 00 00 00 00 02 E2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 D8
+ 15 01 00 00 00 00 02 2A 2A
+ /* CLK */
+ 15 01 00 00 00 00 02 4B 03
+ 15 01 00 00 00 00 02 4C 11
+ 15 01 00 00 00 00 02 4D 10
+ 15 01 00 00 00 00 02 4E 01
+ 15 01 00 00 00 00 02 4F 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5B 43
+ 15 01 00 00 00 00 02 5C 00
+ 15 01 00 00 00 00 02 5F 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7A 80
+ 15 01 00 00 00 00 02 7B 91
+ 15 01 00 00 00 00 02 7C D8
+ 15 01 00 00 00 00 02 7D 60
+ 15 01 00 00 00 00 02 7F 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 B3 C0
+ 15 01 00 00 00 00 02 B4 00
+ 15 01 00 00 00 00 02 B5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0A
+ 15 01 00 00 00 00 02 94 0A
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8A 00
+ 15 01 00 00 00 00 02 9B FF
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9D B0
+ 15 01 00 00 00 00 02 9F 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 EC 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3B 03 0A 0A
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 E5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 BB 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 FB 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi
new file mode 100755
index 0000000..aff6950
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi
@@ -0,0 +1,206 @@
+&mdss_mdp {
+ dsi_dual_nt35597_truly_video: qcom,mdss_dsi_nt35597_wqxga_video_truly {
+ qcom,mdss-dsi-panel-name =
+ "Dual nt35597 video mode dsi truly panel without DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <131>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-underflow-color = <0x3ff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1E
+ 15 01 00 00 00 00 02 0B 73
+ 15 01 00 00 00 00 02 0C 73
+ 15 01 00 00 00 00 02 0E B0
+ 15 01 00 00 00 00 02 0F AE
+ 15 01 00 00 00 00 02 11 B8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5A 00
+ 15 01 00 00 00 00 02 5B 01
+ 15 01 00 00 00 00 02 5C 80
+ 15 01 00 00 00 00 02 5D 81
+ 15 01 00 00 00 00 02 5E 00
+ 15 01 00 00 00 00 02 5F 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 FF 24
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 00 1C
+ 15 01 00 00 00 00 02 01 0B
+ 15 01 00 00 00 00 02 02 0C
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0F
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8A
+ 15 01 00 00 00 00 02 0A 13
+ 15 01 00 00 00 00 02 0B 13
+ 15 01 00 00 00 00 02 0C 15
+ 15 01 00 00 00 00 02 0D 15
+ 15 01 00 00 00 00 02 0E 17
+ 15 01 00 00 00 00 02 0F 17
+ 15 01 00 00 00 00 02 10 1C
+ 15 01 00 00 00 00 02 11 0B
+ 15 01 00 00 00 00 02 12 0C
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0F
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8A
+ 15 01 00 00 00 00 02 1A 13
+ 15 01 00 00 00 00 02 1B 13
+ 15 01 00 00 00 00 02 1C 15
+ 15 01 00 00 00 00 02 1D 15
+ 15 01 00 00 00 00 02 1E 17
+ 15 01 00 00 00 00 02 1F 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6D
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 E0 00
+ 15 01 00 00 00 00 02 DC 21
+ 15 01 00 00 00 00 02 DD 22
+ 15 01 00 00 00 00 02 DE 07
+ 15 01 00 00 00 00 02 DF 07
+ 15 01 00 00 00 00 02 E3 6D
+ 15 01 00 00 00 00 02 E1 07
+ 15 01 00 00 00 00 02 E2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 D8
+ 15 01 00 00 00 00 02 2A 2A
+ /* CLK */
+ 15 01 00 00 00 00 02 4B 03
+ 15 01 00 00 00 00 02 4C 11
+ 15 01 00 00 00 00 02 4D 10
+ 15 01 00 00 00 00 02 4E 01
+ 15 01 00 00 00 00 02 4F 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5B 43
+ 15 01 00 00 00 00 02 5C 00
+ 15 01 00 00 00 00 02 5F 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7A 80
+ 15 01 00 00 00 00 02 7B 91
+ 15 01 00 00 00 00 02 7C D8
+ 15 01 00 00 00 00 02 7D 60
+ 15 01 00 00 00 00 02 7F 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 B3 C0
+ 15 01 00 00 00 00 02 B4 00
+ 15 01 00 00 00 00 02 B5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0A
+ 15 01 00 00 00 00 02 94 0A
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8A 00
+ 15 01 00 00 00 00 02 9B FF
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9D B0
+ 15 01 00 00 00 00 02 9F 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 EC 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 FF 10
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3B 03 0A 0A
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 E5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 BB 03
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 FB 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi
new file mode 100755
index 0000000..ffefa6a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35695b-truly-fhd-cmd.dtsi
@@ -0,0 +1,185 @@
+&mdss_mdp {
+ dsi_nt35695b_truly_fhd_cmd: qcom,mdss_dsi_nt35695b_truly_fhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "nt35695b truly fhd command mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,dsi-sec-ctrl-num = <1>;
+ qcom,dsi-sec-phy-num = <1>;
+ qcom,dsi-select-sec-clocks = "src_byte_clk1", "src_pixel_clk1";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-post-init-delay = <1>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <2>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command =
+ [15 01 00 00 10 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 03 55
+ 15 01 00 00 00 00 02 05 50
+ 15 01 00 00 00 00 02 06 a8
+ 15 01 00 00 00 00 02 07 ad
+ 15 01 00 00 00 00 02 08 0c
+ 15 01 00 00 00 00 02 0b aa
+ 15 01 00 00 00 00 02 0c aa
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f b3
+ 15 01 00 00 00 00 02 11 28
+ 15 01 00 00 00 00 02 12 10
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 4a
+ 15 01 00 00 00 00 02 15 12
+ 15 01 00 00 00 00 02 16 12
+ 15 01 00 00 00 00 02 30 01
+ 15 01 00 00 00 00 02 72 11
+ 15 01 00 00 00 00 02 58 82
+ 15 01 00 00 00 00 02 59 00
+ 15 01 00 00 00 00 02 5a 02
+ 15 01 00 00 00 00 02 5b 00
+ 15 01 00 00 00 00 02 5c 82
+ 15 01 00 00 00 00 02 5d 80
+ 15 01 00 00 00 00 02 5e 02
+ 15 01 00 00 00 00 02 5f 00
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 89
+ 15 01 00 00 00 00 02 04 8a
+ 15 01 00 00 00 00 02 05 0f
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 1c
+ 15 01 00 00 00 00 02 09 00
+ 15 01 00 00 00 00 02 0a 00
+ 15 01 00 00 00 00 02 0b 00
+ 15 01 00 00 00 00 02 0c 00
+ 15 01 00 00 00 00 02 0d 13
+ 15 01 00 00 00 00 02 0e 15
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 01
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 89
+ 15 01 00 00 00 00 02 14 8a
+ 15 01 00 00 00 00 02 15 0f
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 1c
+ 15 01 00 00 00 00 02 19 00
+ 15 01 00 00 00 00 02 1a 00
+ 15 01 00 00 00 00 02 1b 00
+ 15 01 00 00 00 00 02 1c 00
+ 15 01 00 00 00 00 02 1d 13
+ 15 01 00 00 00 00 02 1e 15
+ 15 01 00 00 00 00 02 1f 17
+ 15 01 00 00 00 00 02 20 00
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 55 25
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 93 06
+ 15 01 00 00 00 00 02 94 06
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b 0f
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ 15 01 00 00 00 00 02 b6 21
+ 15 01 00 00 00 00 02 b7 22
+ 15 01 00 00 00 00 02 b8 07
+ 15 01 00 00 00 00 02 b9 07
+ 15 01 00 00 00 00 02 ba 22
+ 15 01 00 00 00 00 02 bd 20
+ 15 01 00 00 00 00 02 be 07
+ 15 01 00 00 00 00 02 bf 07
+ 15 01 00 00 00 00 02 c1 6d
+ 15 01 00 00 00 00 02 c4 24
+ 15 01 00 00 00 00 02 e3 00
+ 15 01 00 00 00 00 02 ec 00
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 14
+ 00 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35695b-truly-fhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35695b-truly-fhd-video.dtsi
new file mode 100755
index 0000000..fe84525
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt35695b-truly-fhd-video.dtsi
@@ -0,0 +1,177 @@
+&mdss_mdp {
+ dsi_nt35695b_truly_fhd_video: qcom,mdss_dsi_nt35695b_truly_fhd_video {
+ qcom,mdss-dsi-panel-name =
+ "nt35695b truly fhd video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-post-init-delay = <1>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-v-back-porch = <2>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command =
+ [15 01 00 00 10 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 03 55
+ 15 01 00 00 00 00 02 05 50
+ 15 01 00 00 00 00 02 06 a8
+ 15 01 00 00 00 00 02 07 ad
+ 15 01 00 00 00 00 02 08 0c
+ 15 01 00 00 00 00 02 0b aa
+ 15 01 00 00 00 00 02 0c aa
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f b3
+ 15 01 00 00 00 00 02 11 28
+ 15 01 00 00 00 00 02 12 10
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 4a
+ 15 01 00 00 00 00 02 15 12
+ 15 01 00 00 00 00 02 16 12
+ 15 01 00 00 00 00 02 30 01
+ 15 01 00 00 00 00 02 72 11
+ 15 01 00 00 00 00 02 58 82
+ 15 01 00 00 00 00 02 59 00
+ 15 01 00 00 00 00 02 5a 02
+ 15 01 00 00 00 00 02 5b 00
+ 15 01 00 00 00 00 02 5c 82
+ 15 01 00 00 00 00 02 5d 80
+ 15 01 00 00 00 00 02 5e 02
+ 15 01 00 00 00 00 02 5f 00
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 89
+ 15 01 00 00 00 00 02 04 8a
+ 15 01 00 00 00 00 02 05 0f
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 1c
+ 15 01 00 00 00 00 02 09 00
+ 15 01 00 00 00 00 02 0a 00
+ 15 01 00 00 00 00 02 0b 00
+ 15 01 00 00 00 00 02 0c 00
+ 15 01 00 00 00 00 02 0d 13
+ 15 01 00 00 00 00 02 0e 15
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 01
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 89
+ 15 01 00 00 00 00 02 14 8a
+ 15 01 00 00 00 00 02 15 0f
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 1c
+ 15 01 00 00 00 00 02 19 00
+ 15 01 00 00 00 00 02 1a 00
+ 15 01 00 00 00 00 02 1b 00
+ 15 01 00 00 00 00 02 1c 00
+ 15 01 00 00 00 00 02 1d 13
+ 15 01 00 00 00 00 02 1e 15
+ 15 01 00 00 00 00 02 1f 17
+ 15 01 00 00 00 00 02 20 00
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 55 25
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 93 06
+ 15 01 00 00 00 00 02 94 06
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b 0f
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ 15 01 00 00 00 00 02 b6 21
+ 15 01 00 00 00 00 02 b7 22
+ 15 01 00 00 00 00 02 b8 07
+ 15 01 00 00 00 00 02 b9 07
+ 15 01 00 00 00 00 02 ba 22
+ 15 01 00 00 00 00 02 bd 20
+ 15 01 00 00 00 00 02 be 07
+ 15 01 00 00 00 00 02 bf 07
+ 15 01 00 00 00 00 02 c1 6d
+ 15 01 00 00 00 00 02 c4 24
+ 15 01 00 00 00 00 02 e3 00
+ 15 01 00 00 00 00 02 ec 00
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bb 03
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00
+ 14 00 02 28 00 05 01 00 00 78 00
+ 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi
new file mode 100755
index 0000000..d066925
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi
@@ -0,0 +1,80 @@
+&mdss_mdp {
+ dsi_dual_nt36850_truly_cmd: qcom,mdss_dsi_nt36850_truly_wqhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Dual nt36850 cmd mode dsi truly panel without DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 50>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <140>;
+ qcom,mdss-dsi-h-pulse-width = <20>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <20>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 36 00
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 03 44 03 e8
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 2c
+ 15 01 00 00 00 00 02 55 01
+ 05 01 00 00 0a 00 02 20 00
+ 15 01 00 00 00 00 02 bb 10
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi
new file mode 100755
index 0000000..11eb3a3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi
@@ -0,0 +1,129 @@
+&mdss_mdp {
+ dsi_dual_s6e3ha3_amoled_cmd: qcom,mdss_dsi_s6e3ha3_amoled_wqhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Dual s6e3ha3 amoled cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <31>;
+ qcom,mdss-dsi-v-front-porch = <30>;
+ qcom,mdss-dsi-v-pulse-width = <8>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-on-command = [05 01 00 00 05 00 02 11 00
+ 39 01 00 00 00 00 05 2a 00 00 05 9f
+ 39 01 00 00 00 00 05 2b 00 00 09 ff
+ 39 01 00 00 00 00 03 f0 5a 5a
+ 39 01 00 00 00 00 02 b0 10
+ 39 01 00 00 00 00 02 b5 a0
+ 39 01 00 00 00 00 02 c4 03
+ 39 01 00 00 00 00 0a
+ f6 42 57 37 00 aa cc d0 00 00
+ 39 01 00 00 00 00 02 f9 03
+ 39 01 00 00 00 00 14
+ c2 00 00 d8 d8 00 80 2b 05 08
+ 0e 07 0b 05 0d 0a 15 13 20 1e
+ 39 01 00 00 78 00 03 f0 a5 a5
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 53 20
+ 39 01 00 00 00 00 02 51 60
+ 05 01 00 00 05 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 3c 00 02 28 00
+ 05 01 00 00 b4 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-lp-mode-on = [39 00 00 00 05 00 03 f0 5a 5a
+ 39 00 00 00 05 00 03 f1 5a 5a
+ 39 00 00 00 05 00 03 fc 5a 5a
+ 39 00 00 00 05 00 02 b0 17
+ 39 00 00 00 05 00 02 cb 10
+ 39 00 00 00 05 00 02 b0 2d
+ 39 00 00 00 05 00 02 cb cd
+ 39 00 00 00 05 00 02 b0 0e
+ 39 00 00 00 05 00 02 cb 02
+ 39 00 00 00 05 00 02 b0 0f
+ 39 00 00 00 05 00 02 cb 09
+ 39 00 00 00 05 00 02 b0 02
+ 39 00 00 00 05 00 02 f2 c9
+ 39 00 00 00 05 00 02 b0 03
+ 39 00 00 00 05 00 02 f2 c0
+ 39 00 00 00 05 00 02 b0 03
+ 39 00 00 00 05 00 02 f4 aa
+ 39 00 00 00 05 00 02 b0 08
+ 39 00 00 00 05 00 02 b1 30
+ 39 00 00 00 05 00 02 b0 09
+ 39 00 00 00 05 00 02 b1 0a
+ 39 00 00 00 05 00 02 b0 0d
+ 39 00 00 00 05 00 02 b1 10
+ 39 00 00 00 05 00 02 b0 00
+ 39 00 00 00 05 00 02 f7 03
+ 39 00 00 00 05 00 02 fe 30
+ 39 01 00 00 05 00 02 fe b0];
+ qcom,mdss-dsi-lp-mode-off = [39 00 00 00 05 00 03 f0 5a 5a
+ 39 00 00 00 05 00 03 f1 5a 5a
+ 39 00 00 00 05 00 03 fc 5a 5a
+ 39 00 00 00 05 00 02 b0 2d
+ 39 00 00 00 05 00 02 cb 4d
+ 39 00 00 00 05 00 02 b0 17
+ 39 00 00 00 05 00 02 cb 04
+ 39 00 00 00 05 00 02 b0 0e
+ 39 00 00 00 05 00 02 cb 06
+ 39 00 00 00 05 00 02 b0 0f
+ 39 00 00 00 05 00 02 cb 05
+ 39 00 00 00 05 00 02 b0 02
+ 39 00 00 00 05 00 02 f2 b8
+ 39 00 00 00 05 00 02 b0 03
+ 39 00 00 00 05 00 02 f2 80
+ 39 00 00 00 05 00 02 b0 03
+ 39 00 00 00 05 00 02 f4 8a
+ 39 00 00 00 05 00 02 b0 08
+ 39 00 00 00 05 00 02 b1 10
+ 39 00 00 00 05 00 02 b0 09
+ 39 00 00 00 05 00 02 b1 0a
+ 39 00 00 00 05 00 02 b0 0d
+ 39 00 00 00 05 00 02 b1 80
+ 39 00 00 00 05 00 02 b0 00
+ 39 00 00 00 05 00 02 f7 03
+ 39 00 00 00 05 00 02 fe 30
+ 39 01 00 00 05 00 02 fe b0];
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,dcs-cmd-by-left;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,mdss-pan-physical-width-dimension = <68>;
+ qcom,mdss-pan-physical-height-dimension = <122>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-1080p-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-1080p-cmd.dtsi
new file mode 100755
index 0000000..8ffa0eb
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-1080p-cmd.dtsi
@@ -0,0 +1,79 @@
+&mdss_mdp {
+ dsi_sharp_1080_cmd: qcom,mdss_dsi_sharp_1080p_cmd {
+ qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel";
+ qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-panel-destination = "display_1";
+ qcom,mdss-dsi-panel-clockrate = <850000000>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <64>;
+ qcom,mdss-pan-physical-height-dimension = <117>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <0>;
+ qcom,mdss-dsi-h-back-porch = <0>;
+ qcom,mdss-dsi-h-pulse-width = <0>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <0>;
+ qcom,mdss-dsi-v-front-porch = <0>;
+ qcom,mdss-dsi-v-pulse-width = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 b0 03
+ 05 01 00 00 78 00 01 11
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 24
+ 15 01 00 00 00 00 02 ff 23
+ 15 01 00 00 00 00 02 08 05
+ 15 01 00 00 00 00 02 46 90
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 ff f0
+ 15 01 00 00 00 00 02 92 01
+ 15 01 00 00 00 00 02 ff 10
+ /* enable TE generation */
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 28 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 40 00 01 10];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dsc-4k-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dsc-4k-cmd.dtsi
new file mode 100755
index 0000000..89df5ff
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dsc-4k-cmd.dtsi
@@ -0,0 +1,96 @@
+&mdss_mdp {
+ dsi_sharp_4k_dsc_cmd: qcom,mdss_dsi_sharp_4k_dsc_cmd {
+ qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>;
+ qcom,mdss-pan-physical-width-dimension = <71>;
+ qcom,mdss-pan-physical-height-dimension = <129>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,dcs-cmd-by-left;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-jitter = <0x8 0xa>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <1080>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dsc-4k-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dsc-4k-video.dtsi
new file mode 100755
index 0000000..feb5540
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dsc-4k-video.dtsi
@@ -0,0 +1,89 @@
+&mdss_mdp {
+ dsi_sharp_4k_dsc_video: qcom,mdss_dsi_sharp_4k_dsc_video {
+ qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>;
+ qcom,mdss-pan-physical-width-dimension = <71>;
+ qcom,mdss-pan-physical-height-dimension = <129>;
+ qcom,mdss-dsi-tx-eot-append;
+
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 10
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <1080>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi
new file mode 100755
index 0000000..c909864d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi
@@ -0,0 +1,86 @@
+&mdss_mdp {
+ dsi_dual_sharp_wqhd_cmd: qcom,mdss_dsi_sharp_wqhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Dual Sharp WQHD cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,dcs-cmd-by-left;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-pan-physical-width-dimension = <68>;
+ qcom,mdss-pan-physical-height-dimension = <121>;
+
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09
+ 20 00 20 02 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ 15 01 00 00 00 00 02 90 01
+ 15 01 00 00 00 00 02 03 00
+ 15 01 00 00 00 00 02 58 01
+ 15 01 00 00 00 00 02 c9 00
+ 15 01 00 00 00 00 02 c0 15
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualdsi-wqhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualdsi-wqhd-video.dtsi
new file mode 100755
index 0000000..3733007
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualdsi-wqhd-video.dtsi
@@ -0,0 +1,82 @@
+&mdss_mdp {
+ dsi_dual_sharp_wqhd_video: qcom,mdss_dsi_sharp_wqhd_video {
+ qcom,mdss-dsi-panel-name =
+ "Dual Sharp wqhd video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-pan-physical-width-dimension = <68>;
+ qcom,mdss-pan-physical-height-dimension = <121>;
+
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09
+ 20 00 20 02 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 10
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ 15 01 00 00 00 00 02 90 01
+ 15 01 00 00 00 00 02 03 00
+ 15 01 00 00 00 00 02 58 01
+ 15 01 00 00 00 00 02 c9 00
+ 15 01 00 00 00 00 02 c0 15
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ };
+ };
+ };
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi
new file mode 100755
index 0000000..06a95ca
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi
@@ -0,0 +1,626 @@
+&mdss_mdp {
+ dsi_dual_sharp_1080_120hz_cmd: qcom,mdss_dual_sharp_1080p_120hz_cmd {
+ qcom,mdss-dsi-panel-name =
+ "sharp 1080p 120hz dual dsi cmd mode panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 10>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,cmd-sync-wait-broadcast;
+ qcom,cmd-sync-wait-trigger;
+ qcom,mdss-tear-check-frame-rate = <12000>;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <28>;
+ qcom,mdss-dsi-h-back-porch = <4>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <12>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+ qcom,mdss-dsi-on-command =
+ [15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 ba 07
+ 15 01 00 00 00 00 02 c0 00
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 d9 00
+ 15 01 00 00 00 00 02 ef 70
+ 15 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 06 3b 03 0e 0c 08 1c
+ 15 01 00 00 00 00 02 e9 0e
+ 15 01 00 00 00 00 02 ea 0c
+ 15 01 00 00 00 00 02 35 00
+ 15 01 00 00 00 00 02 c0 00
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 59 6a
+ 15 01 00 00 00 00 02 0b 1b
+ 15 01 00 00 00 00 02 61 f7
+ 15 01 00 00 00 00 02 62 6c
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 04 c8
+ 15 01 00 00 00 00 02 05 1a
+ 15 01 00 00 00 00 02 0d 93
+ 15 01 00 00 00 00 02 0e 93
+ 15 01 00 00 00 00 02 0f 7e
+ 15 01 00 00 00 00 02 06 69
+ 15 01 00 00 00 00 02 07 bc
+ 15 01 00 00 00 00 02 10 03
+ 15 01 00 00 00 00 02 11 64
+ 15 01 00 00 00 00 02 12 5a
+ 15 01 00 00 00 00 02 13 40
+ 15 01 00 00 00 00 02 14 40
+ 15 01 00 00 00 00 02 15 00
+ 15 01 00 00 00 00 02 33 13
+ 15 01 00 00 00 00 02 5a 40
+ 15 01 00 00 00 00 02 5b 40
+ 15 01 00 00 00 00 02 5e 80
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 80
+ 15 01 00 00 00 00 02 14 80
+ 15 01 00 00 00 00 02 01 80
+ 15 01 00 00 00 00 02 15 80
+ 15 01 00 00 00 00 02 02 80
+ 15 01 00 00 00 00 02 16 80
+ 15 01 00 00 00 00 02 03 0a
+ 15 01 00 00 00 00 02 17 0c
+ 15 01 00 00 00 00 02 04 06
+ 15 01 00 00 00 00 02 18 08
+ 15 01 00 00 00 00 02 05 80
+ 15 01 00 00 00 00 02 19 80
+ 15 01 00 00 00 00 02 06 80
+ 15 01 00 00 00 00 02 1a 80
+ 15 01 00 00 00 00 02 07 80
+ 15 01 00 00 00 00 02 1b 80
+ 15 01 00 00 00 00 02 08 80
+ 15 01 00 00 00 00 02 1c 80
+ 15 01 00 00 00 00 02 09 80
+ 15 01 00 00 00 00 02 1d 80
+ 15 01 00 00 00 00 02 0a 80
+ 15 01 00 00 00 00 02 1e 80
+ 15 01 00 00 00 00 02 0b 1a
+ 15 01 00 00 00 00 02 1f 1b
+ 15 01 00 00 00 00 02 0c 16
+ 15 01 00 00 00 00 02 20 17
+ 15 01 00 00 00 00 02 0d 1c
+ 15 01 00 00 00 00 02 21 1d
+ 15 01 00 00 00 00 02 0e 18
+ 15 01 00 00 00 00 02 22 19
+ 15 01 00 00 00 00 02 0f 0e
+ 15 01 00 00 00 00 02 23 10
+ 15 01 00 00 00 00 02 10 80
+ 15 01 00 00 00 00 02 24 80
+ 15 01 00 00 00 00 02 11 80
+ 15 01 00 00 00 00 02 25 80
+ 15 01 00 00 00 00 02 12 80
+ 15 01 00 00 00 00 02 26 80
+ 15 01 00 00 00 00 02 13 80
+ 15 01 00 00 00 00 02 27 80
+ 15 01 00 00 00 00 02 74 ff
+ 15 01 00 00 00 00 02 75 ff
+ 15 01 00 00 00 00 02 8d 00
+ 15 01 00 00 00 00 02 8e 00
+ 15 01 00 00 00 00 02 8f 9c
+ 15 01 00 00 00 00 02 90 0c
+ 15 01 00 00 00 00 02 91 0e
+ 15 01 00 00 00 00 02 d6 00
+ 15 01 00 00 00 00 02 d7 20
+ 15 01 00 00 00 00 02 d8 00
+ 15 01 00 00 00 00 02 d9 88
+ 15 01 00 00 00 00 02 e5 05
+ 15 01 00 00 00 00 02 e6 10
+ 15 01 00 00 00 00 02 54 06
+ 15 01 00 00 00 00 02 55 05
+ 15 01 00 00 00 00 02 56 04
+ 15 01 00 00 00 00 02 58 03
+ 15 01 00 00 00 00 02 59 33
+ 15 01 00 00 00 00 02 5a 33
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5d 01
+ 15 01 00 00 00 00 02 5e 0a
+ 15 01 00 00 00 00 02 5f 0a
+ 15 01 00 00 00 00 02 60 0a
+ 15 01 00 00 00 00 02 61 0a
+ 15 01 00 00 00 00 02 62 10
+ 15 01 00 00 00 00 02 63 01
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 65 00
+ 15 01 00 00 00 00 02 ef 00
+ 15 01 00 00 00 00 02 f0 00
+ 15 01 00 00 00 00 02 6d 20
+ 15 01 00 00 00 00 02 66 44
+ 15 01 00 00 00 00 02 68 01
+ 15 01 00 00 00 00 02 69 00
+ 15 01 00 00 00 00 02 67 11
+ 15 01 00 00 00 00 02 6a 06
+ 15 01 00 00 00 00 02 6b 31
+ 15 01 00 00 00 00 02 6c 90
+ 15 01 00 00 00 00 02 ab c3
+ 15 01 00 00 00 00 02 b1 49
+ 15 01 00 00 00 00 02 aa 80
+ 15 01 00 00 00 00 02 b0 90
+ 15 01 00 00 00 00 02 b2 a4
+ 15 01 00 00 00 00 02 b3 00
+ 15 01 00 00 00 00 02 b4 23
+ 15 01 00 00 00 00 02 b5 00
+ 15 01 00 00 00 00 02 b6 00
+ 15 01 00 00 00 00 02 b7 00
+ 15 01 00 00 00 00 02 b8 00
+ 15 01 00 00 00 00 02 b9 00
+ 15 01 00 00 00 00 02 ba 00
+ 15 01 00 00 00 00 02 bb 00
+ 15 01 00 00 00 00 02 bc 00
+ 15 01 00 00 00 00 02 bd 00
+ 15 01 00 00 00 00 02 be 00
+ 15 01 00 00 00 00 02 bf 00
+ 15 01 00 00 00 00 02 c0 00
+ 15 01 00 00 00 00 02 c7 40
+ 15 01 00 00 00 00 02 c9 00
+ 15 01 00 00 00 00 02 c1 2a
+ 15 01 00 00 00 00 02 c2 2a
+ 15 01 00 00 00 00 02 c3 00
+ 15 01 00 00 00 00 02 c4 00
+ 15 01 00 00 00 00 02 c5 00
+ 15 01 00 00 00 00 02 c6 00
+ 15 01 00 00 00 00 02 c8 ab
+ 15 01 00 00 00 00 02 ca 00
+ 15 01 00 00 00 00 02 cb 00
+ 15 01 00 00 00 00 02 cc 20
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+ 15 01 00 00 00 00 02 b3 00
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+ 15 01 00 00 00 00 02 b5 00
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+ 15 01 00 00 00 00 02 cb 02
+ 15 01 00 00 00 00 02 cc 4a
+ 15 01 00 00 00 00 02 cd 02
+ 15 01 00 00 00 00 02 ce 4c
+ 15 01 00 00 00 00 02 cf 02
+ 15 01 00 00 00 00 02 d0 85
+ 15 01 00 00 00 00 02 d1 02
+ 15 01 00 00 00 00 02 d2 c3
+ 15 01 00 00 00 00 02 d3 02
+ 15 01 00 00 00 00 02 d4 e9
+ 15 01 00 00 00 00 02 d5 03
+ 15 01 00 00 00 00 02 d6 16
+ 15 01 00 00 00 00 02 d7 03
+ 15 01 00 00 00 00 02 d8 34
+ 15 01 00 00 00 00 02 d9 03
+ 15 01 00 00 00 00 02 da 56
+ 15 01 00 00 00 00 02 db 03
+ 15 01 00 00 00 00 02 dc 62
+ 15 01 00 00 00 00 02 dd 03
+ 15 01 00 00 00 00 02 de 6c
+ 15 01 00 00 00 00 02 df 03
+ 15 01 00 00 00 00 02 e0 74
+ 15 01 00 00 00 00 02 e1 03
+ 15 01 00 00 00 00 02 e2 80
+ 15 01 00 00 00 00 02 e3 03
+ 15 01 00 00 00 00 02 e4 89
+ 15 01 00 00 00 00 02 e5 03
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+ 15 01 00 00 00 00 02 e7 03
+ 15 01 00 00 00 00 02 e8 8d
+ 15 01 00 00 00 00 02 e9 03
+ 15 01 00 00 00 00 02 ea 8e
+ 15 01 00 00 00 00 02 FF 10
+ 05 01 00 00 00 00 01 29];
+ qcom,mdss-dsi-off-command =
+ [15 01 00 00 00 00 02 ff 10
+ 05 01 00 00 10 00 01 28
+ 15 01 00 00 00 00 02 b0 00
+ 05 01 00 00 40 00 01 10
+ 15 01 00 00 00 00 02 4f 01];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-cmd.dtsi
new file mode 100755
index 0000000..f62ce3b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-cmd.dtsi
@@ -0,0 +1,347 @@
+&mdss_mdp {
+ dsi_sim_cmd: qcom,mdss_dsi_sim_cmd {
+ qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-panel-mode-switch;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-t-clk-post = <0x03>;
+ qcom,mdss-dsi-t-clk-pre = <0x27>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <100>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-cmd-mode;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,cmd-to-video-mode-switch-commands = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 07 01 00 00 00 00 02 01 00
+ 39 01 00 00 00 00 06 b2 00 5d 04 80 49
+ 15 01 00 00 00 00 02 3d 10
+ 15 01 00 00 00 00 02 36 00
+ 15 01 00 00 00 00 02 55 0c
+ ];
+ qcom,cmd-to-video-mode-switch-commands-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <100>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-video-mode;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,video-to-cmd-mode-switch-commands = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 07 01 00 00 00 00 02 01 00
+ 39 01 00 00 00 00 06 b2 00 5d 04 80 49
+ 15 01 00 00 00 00 02 3d 11
+ 15 01 00 00 00 00 02 36 00
+ 15 01 00 00 00 00 02 55 0b
+ ];
+ qcom,video-to-cmd-mode-switch-commands-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <100>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@3 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <460>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <740>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@4 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <840>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <1380>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <360>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dsc-10bit-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dsc-10bit-cmd.dtsi
new file mode 100755
index 0000000..310ce40
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dsc-10bit-cmd.dtsi
@@ -0,0 +1,474 @@
+&mdss_mdp {
+ dsi_sim_dsc_10b_cmd: qcom,mdss_dsi_sim_dsc_10b_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Simulator cmd mode DSC3:1 10bit dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <30>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f aE
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6d
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x0(2 Port SDC)
+ * 0x01(1 PortA FBC)
+ * 0x02(MTK) 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+
+ qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <10>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <0>;
+ qcom,mdss-dsi-h-back-porch = <0>;
+ qcom,mdss-dsi-h-pulse-width = <0>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <0>;
+ qcom,mdss-dsi-v-front-porch = <0>;
+ qcom,mdss-dsi-v-pulse-width = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 b0 03
+ 05 01 00 00 78 00 01 11
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 24
+ 15 01 00 00 00 00 02 ff 23
+ 15 01 00 00 00 00 02 08 05
+ 15 01 00 00 00 00 02 46 90
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 ff f0
+ 15 01 00 00 00 00 02 92 01
+ 15 01 00 00 00 00 02 ff 10
+ /* enable TE generation */
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 28 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 40 00 01 10];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <10>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f aE
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6d
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x0(2 Port SDC)
+ * 0x01(1 PortA FBC)
+ * 0x02(MTK) 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+
+ qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <10>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dsc375-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dsc375-cmd.dtsi
new file mode 100755
index 0000000..ef40a2e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dsc375-cmd.dtsi
@@ -0,0 +1,280 @@
+&mdss_mdp {
+ dsi_sim_dsc_375_cmd: qcom,mdss_dsi_sim_dsc_375_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Simulator cmd mode DSC 3.75:1 dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f aE
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6d
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x0(2 Port SDC)
+ * 0x01(1 PortA FBC)
+ * 0x02(MTK) 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+
+ qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <0>;
+ qcom,mdss-dsi-h-back-porch = <0>;
+ qcom,mdss-dsi-h-pulse-width = <0>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <0>;
+ qcom,mdss-dsi-v-front-porch = <0>;
+ qcom,mdss-dsi-v-pulse-width = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 b0 03
+ 05 01 00 00 78 00 01 11
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 24
+ 15 01 00 00 00 00 02 ff 23
+ 15 01 00 00 00 00 02 08 05
+ 15 01 00 00 00 00 02 46 90
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 ff f0
+ 15 01 00 00 00 00 02 92 01
+ 15 01 00 00 00 00 02 ff 10
+ /* enable TE generation */
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 28 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 40 00 01 10];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-cmd.dtsi
new file mode 100755
index 0000000..5f4be88f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-cmd.dtsi
@@ -0,0 +1,141 @@
+&mdss_mdp {
+ dsi_dual_sim_cmd: qcom,mdss_dsi_dual_sim_cmd {
+ qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,cmd-sync-wait-broadcast;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-hor-line-idle = <0 40 256>,
+ <40 120 128>,
+ <120 240 64>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,panel-ack-disabled;
+ qcom,mdss-dsi-qsync-min-refresh-rate = <45>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <28>;
+ qcom,mdss-dsi-h-back-porch = <4>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <12>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+ qcom,mdss-dsi-on-command =
+ [/* exit sleep mode, wait 0ms */
+ 05 01 00 00 00 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 00 00 02 28 00
+ 05 01 00 00 00 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_hs_mode";
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <1280>;
+ qcom,mdss-dsi-panel-height = <1440>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <44>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command =
+ [/* exit sleep mode, wait 0ms */
+ 05 01 00 00 00 00 01 29];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 00 00 02 28 00
+ 05 01 00 00 00 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_hs_mode";
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <40>;
+ qcom,mdss-dsi-on-command =
+ [/* exit sleep mode, wait 0ms */
+ 05 01 00 00 00 00 01 29];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 00 00 02 28 00
+ 05 01 00 00 00 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi
new file mode 100755
index 0000000..87b4a76
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi
@@ -0,0 +1,327 @@
+&mdss_mdp {
+ dsi_dual_sim_dsc_375_cmd: qcom,mdss_dsi_dual_sim_dsc_375_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Sim dual cmd mode DSC 3.75:1 dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,cmd-sync-wait-broadcast;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-hor-line-idle = <0 40 256>,
+ <40 120 128>,
+ <120 240 64>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <1080>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1E
+ 15 01 00 00 00 00 02 0B 73
+ 15 01 00 00 00 00 02 0C 73
+ 15 01 00 00 00 00 02 0E B0
+ 15 01 00 00 00 00 02 0F AE
+ 15 01 00 00 00 00 02 11 B8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5A 00
+ 15 01 00 00 00 00 02 5B 01
+ 15 01 00 00 00 00 02 5C 80
+ 15 01 00 00 00 00 02 5D 81
+ 15 01 00 00 00 00 02 5E 00
+ 15 01 00 00 00 00 02 5F 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1C
+ 15 01 00 00 00 00 02 01 0B
+ 15 01 00 00 00 00 02 02 0C
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0F
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8A
+ 15 01 00 00 00 00 02 0A 13
+ 15 01 00 00 00 00 02 0B 13
+ 15 01 00 00 00 00 02 0C 15
+ 15 01 00 00 00 00 02 0D 15
+ 15 01 00 00 00 00 02 0E 17
+ 15 01 00 00 00 00 02 0F 17
+ 15 01 00 00 00 00 02 10 1C
+ 15 01 00 00 00 00 02 11 0B
+ 15 01 00 00 00 00 02 12 0C
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0F
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8A
+ 15 01 00 00 00 00 02 1A 13
+ 15 01 00 00 00 00 02 1B 13
+ 15 01 00 00 00 00 02 1C 15
+ 15 01 00 00 00 00 02 1D 15
+ 15 01 00 00 00 00 02 1E 17
+ 15 01 00 00 00 00 02 1F 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6D
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 E0 00
+ 15 01 00 00 00 00 02 DC 21
+ 15 01 00 00 00 00 02 DD 22
+ 15 01 00 00 00 00 02 DE 07
+ 15 01 00 00 00 00 02 DF 07
+ 15 01 00 00 00 00 02 E3 6D
+ 15 01 00 00 00 00 02 E1 07
+ 15 01 00 00 00 00 02 E2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 D8
+ 15 01 00 00 00 00 02 2A 2A
+ /* CLK */
+ 15 01 00 00 00 00 02 4B 03
+ 15 01 00 00 00 00 02 4C 11
+ 15 01 00 00 00 00 02 4D 10
+ 15 01 00 00 00 00 02 4E 01
+ 15 01 00 00 00 00 02 4F 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5B 43
+ 15 01 00 00 00 00 02 5C 00
+ 15 01 00 00 00 00 02 5F 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7A 80
+ 15 01 00 00 00 00 02 7B 91
+ 15 01 00 00 00 00 02 7C D8
+ 15 01 00 00 00 00 02 7D 60
+ 15 01 00 00 00 00 02 7F 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 B3 C0
+ 15 01 00 00 00 00 02 B4 00
+ 15 01 00 00 00 00 02 B5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0A
+ 15 01 00 00 00 00 02 94 0A
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8A 00
+ 15 01 00 00 00 00 02 9B FF
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9D B0
+ 15 01 00 00 00 00 02 9F 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 EC 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3B 03 0A 0A
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 E5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 BB 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 FB 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-width = <2520>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <1080>;
+ qcom,mdss-dsc-slice-width = <1260>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-video.dtsi
new file mode 100755
index 0000000..3bee9f6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-dualmipi-video.dtsi
@@ -0,0 +1,63 @@
+&mdss_mdp {
+ dsi_dual_sim_vid: qcom,mdss_dsi_dual_sim_video {
+ qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-panel-broadcast-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
+ qcom,panel-ack-disabled;
+ qcom,mdss-dsi-qsync-min-refresh-rate = <45>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1280>;
+ qcom,mdss-dsi-panel-height = <1440>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <44>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-sec-hd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-sec-hd-cmd.dtsi
new file mode 100755
index 0000000..e9d3135
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-sec-hd-cmd.dtsi
@@ -0,0 +1,68 @@
+&mdss_mdp {
+ dsi_sim_sec_hd_cmd: qcom,mdss_dsi_sim_sec_hd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "sim hd command mode secondary dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-sec-ctrl-num = <1>;
+ qcom,dsi-sec-phy-num = <1>;
+ qcom,dsi-select-sec-clocks = "src_byte_clk1", "src_pixel_clk1";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,panel-ack-disabled;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-post-init-delay = <1>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <2>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+
+ qcom,mdss-dsi-on-command = [
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-video.dtsi
new file mode 100755
index 0000000..5a2ac01
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sim-video.dtsi
@@ -0,0 +1,62 @@
+&mdss_mdp {
+ dsi_sim_vid: qcom,mdss_dsi_sim_video {
+ qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-t-clk-post = <0x04>;
+ qcom,mdss-dsi-t-clk-pre = <0x1b>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 0>, <0 0>, <1 0>;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <640>;
+ qcom,mdss-dsi-panel-height = <480>;
+ qcom,mdss-dsi-h-front-porch = <8>;
+ qcom,mdss-dsi-h-back-porch = <8>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <6>;
+ qcom,mdss-dsi-v-front-porch = <6>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 00 00 00 00 00 00 00 00 00 00 00];
+ qcom,mdss-dsi-on-command =
+ [32 01 00 00 00 00 02 00 00];
+ qcom,mdss-dsi-off-command =
+ [22 01 00 00 00 00 02 00 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi
new file mode 100755
index 0000000..6195f8c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi
@@ -0,0 +1,103 @@
+&mdss_mdp {
+ dsi_sw43404_amoled_fhd_plus_cmd: qcom,mdss_dsi_sw43404_fhd_plus_cmd {
+ qcom,mdss-dsi-panel-name =
+ "sw43404 amoled boe fhd+ panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-pan-physical-width-dimension = <68>;
+ qcom,mdss-pan-physical-height-dimension = <138>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <160>;
+ qcom,mdss-dsi-h-back-porch = <72>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x3 0x1>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 07 01 00 00 00 00 02 01 00
+ 0a 01 00 00 00 00 80 11 00 00 89 30 80
+ 08 70 04 38 02 1c 02 1c 02 1c 02 00
+ 02 0e 00 20 34 29 00 07 00 0C 00 2e
+ 00 31 18 00 10 F0 03 0C 20 00 06 0B
+ 0B 33 0E 1C 2A 38 46 54 62 69 70 77
+ 79 7B 7D 7E 01 02 01 00 09 40 09 BE
+ 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6
+ 2A F6 2B 34 2B 74 3B 74 6B F4 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 15 01 00 00 00 00 02 5e 10
+ 39 01 00 00 00 00 06 b9 bf 11 40 00 30
+ 39 01 00 00 00 00 09 F8 00 08 10 08 2D
+ 00 00 2D
+ 15 01 00 00 00 00 02 55 08
+ 05 01 00 00 1e 00 02 11 00
+ 15 01 00 00 78 00 02 3d 01
+ 39 01 00 00 00 00 03 b0 a5 00
+ 05 01 00 00 78 00 02 35 00
+ 05 01 00 00 3c 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <270>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi
new file mode 100755
index 0000000..032fc39
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi
@@ -0,0 +1,121 @@
+&mdss_mdp {
+ dsi_sw43404_amoled_cmd: qcom,mdss_dsi_sw43404_amoled_wqhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "sw43404 amoled cmd mode dsi boe panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-qsync-min-refresh-rate = <55>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2880>;
+ qcom,mdss-dsi-h-front-porch = <60>;
+ qcom,mdss-dsi-h-back-porch = <30>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 03 5c 42 00
+ 07 01 00 00 00 00 02 01 00
+ 0a 01 00 00 00 00 80 11 00 00 89 30 80
+ 0B 40 05 A0 05 A0 02 D0 02 D0 02 00
+ 02 68 00 20 9A DB 00 0A 00 0C 00 12
+ 00 0E 18 00 10 F0 03 0C 20 00 06 0B
+ 0B 33 0E 1C 2A 38 46 54 62 69 70 77
+ 79 7B 7D 7E 01 02 01 00 09 40 09 BE
+ 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6
+ 2A F6 2B 34 2B 74 3B 74 6B F4 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 09 F8 00 08 10 08 2D
+ 00 00 2D
+ 15 01 00 00 00 00 02 55 08
+ 05 01 00 00 1e 00 02 11 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 15 01 00 00 00 00 02 e0 18
+ 39 01 00 00 00 00 0c c0 00 53 6f 51 50
+ 51 34 4f 5a 33 19
+ 05 01 00 00 78 00 02 35 00
+ 05 01 00 00 3c 00 02 29 00
+ ];
+
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 5a 01];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 5a 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-lp1-command = [
+ 05 01 00 00 00 00 02 39 00
+ ];
+ qcom,mdss-dsi-lp1-command-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-nolp-command = [
+ 05 01 00 00 00 00 02 38 00
+ ];
+ qcom,mdss-dsi-nolp-command-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <180>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi
new file mode 100755
index 0000000..37c0dfcd
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi
@@ -0,0 +1,101 @@
+&mdss_mdp {
+ dsi_sw43404_amoled_video: qcom,mdss_dsi_sw43404_amoled_wqhd_video {
+ qcom,mdss-dsi-panel-name =
+ "sw43404 amoled video mode dsi boe panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2880>;
+ qcom,mdss-dsi-h-front-porch = <10>;
+ qcom,mdss-dsi-h-back-porch = <10>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <10>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 07 01 00 00 00 00 02 01 00
+ 39 01 00 00 00 00 06 b2 00 5d 04 80 49
+ 15 01 00 00 00 00 02 3d 10
+ 15 01 00 00 00 00 02 36 00
+ 15 01 00 00 00 00 02 55 08
+ 39 01 00 00 00 00 09 f8 00 08 10 08 2d
+ 00 00 2d
+ 39 01 00 00 3c 00 03 51 00 00
+ 05 01 00 00 50 00 02 11 00
+ 39 01 00 00 00 00 03 b0 34 04
+ 39 01 00 00 00 00 05 c1 00 00 00 46
+ 39 01 00 00 00 00 03 b0 a5 00
+ 0a 01 00 00 00 00 80 11 00 00 89 30 80
+ 0B 40 05 A0 02 d0 02 D0 02 D0 02 00
+ 02 68 00 20 4e a8 00 0A 00 0C 00 23
+ 00 1c 18 00 10 F0 03 0C 20 00 06 0B
+ 0B 33 0E 1C 2A 38 46 54 62 69 70 77
+ 79 7B 7D 7E 01 02 01 00 09 40 09 BE
+ 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6
+ 2A F6 2B 34 2B 74 3B 74 6B F4 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 15 01 00 00 00 00 02 e0 18
+ 39 01 00 00 00 00 0c c0 00 53 6f 51 50
+ 51 34 4f 5a 33 19
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-lp1-command = [
+ 05 01 00 00 00 00 02 39 00
+ ];
+ qcom,mdss-dsi-lp1-command-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-nolp-command = [
+ 05 01 00 00 00 00 02 38 00
+ ];
+ qcom,mdss-dsi-nolp-command-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <180>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-td4328-1080p-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-td4328-1080p-cmd.dtsi
new file mode 100755
index 0000000..476c34c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-td4328-1080p-cmd.dtsi
@@ -0,0 +1,169 @@
+&mdss_mdp {
+ dsi_td4328_truly_cmd: qcom,mdss_dsi_td4328_truly_cmd {
+ qcom,mdss-dsi-panel-name =
+ "td4328 cmd mode dsi truly panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <70>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <10>;
+ qcom,mdss-dsi-v-front-porch = <5>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+ qcom,mdss-dsi-on-command = [
+ 29 01 00 00 00 00 02 B0 00
+ 29 01 00 00 00 00 04 B3 00 00 06
+ 29 01 00 00 00 00 02 B4 00
+ 29 01 00 00 00 00 06 B6 33 DB 80 12 00
+ 29 01 00 00 00 00 08 B8 57 3D 19 1E 0A
+ 50 50
+ 29 01 00 00 00 00 08 B9 6F 3D 28 3C 14
+ C8 C8
+ 29 01 00 00 00 00 08 BA B5 33 41 64 23
+ A0 A0
+ 29 01 00 00 00 00 03 BB 14 14
+ 29 01 00 00 00 00 03 BC 37 32
+ 29 01 00 00 00 00 03 BD 64 32
+ 29 01 00 00 00 00 02 BE 04
+ 29 01 00 00 00 00 02 C0 00
+ 29 01 00 00 00 00 2E C1 04 48 00 00 26
+ 15 19 0B 63 D2 D9 9A 73 EF BD E7 5C
+ 6B 93 4D 22 18 8B 2A 41 00 00 00 00
+ 00 00 00 00 00 40 02 22 1B 06 03 00
+ 07 FF 00 01
+ 29 01 00 00 00 00 18 C2 01 F8 70 08 68
+ 08 0C 10 00 08 30 00 00 00 00 00 00
+ 20 02 43 00 00 00
+ 29 01 00 00 00 00 3F C3 87 D8 7D 87 D0
+ 00 00 00 00 00 00 04 3A 00 00 00 04
+ 44 00 00 01 01 03 28 00 01 00 01 00
+ 00 19 00 0C 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 32 00 19 00 5A
+ 02 32 00 19 00 5A 02 40 00
+ 29 01 00 00 00 00 15 C4 70 00 00 00 11
+ 11 00 00 00 02 02 31 01 00 00 00 02
+ 01 01 01
+ 29 01 00 00 00 00 08 C5 08 00 00 00 00
+ 70 00
+ 29 01 00 00 00 00 40 C6 5B 2D 2D 07 54
+ 07 54 01 02 01 02 07 07 00 00 07 07
+ 0F 11 07 5B 00 5B 5B C2 C2 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 27 C7 01 1D 2E 41 4F
+ 5A 71 80 8B 95 45 4F 5C 71 7B 88 98
+ A6 BE 01 1D 2E 41 4F 5A 71 80 8B 95
+ 45 4F 5C 71 7B 88 98 A6 BE
+ 29 01 00 00 00 00 38 C8 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00
+ 29 01 00 00 00 00 14 C9 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00
+ 29 01 00 00 00 00 2C CA 1C FC FC FC 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 1C CB FF FF FF FF 0F
+ 00 08 00 01 00 31 F0 40 08 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 02 CC 02
+ 29 01 00 00 00 00 27 CD 10 80 37 C0 1A
+ 00 5C 02 19 90 11 88 D8 6C D8 6C 01
+ 00 00 00 32 00 32 00 5D 02 32 32 01
+ 33 00 33 00 5E 02 32 32 AF
+ 29 01 00 00 00 00 1A CE 5D 40 49 53 59
+ 5E 63 68 6E 74 7E 8A 98 A8 BB D0 FF
+ 04 00 04 04 42 00 69 5A
+ 29 01 00 00 00 00 03 CF 4A 1D
+ 29 01 00 00 00 00 12 D0 33 57 D4 31 01
+ 10 10 10 19 19 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 02 D1 00
+ 29 01 00 00 00 00 20 D2 10 00 00 10 75
+ 0F 03 25 20 00 00 00 00 00 00 00 00
+ 04 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 17 D3 1B 3B BB 77 77
+ 77 BB B3 33 00 00 6D 6E C7 C7 33 BB
+ F2 FD C6 0B 07
+ 29 01 00 00 00 00 08 D4 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 08 D5 03 00 00 02 2B
+ 02 2B
+ 29 01 00 00 00 00 02 D6 01
+ 29 01 00 00 00 00 22 D7 F6 FF 03 05 41
+ 24 80 1F C7 1F 1B 00 0C 07 20 00 00
+ 00 00 00 0C 00 1F 00 FC 00 00 AA 67
+ 7E 5D 06 00
+ 29 01 00 00 00 00 03 D9 20 14
+ 29 01 00 00 00 00 05 DD 30 06 23 65
+ 29 01 00 00 00 00 05 DE 00 3F FF 50
+ 29 01 00 00 00 00 06 E7 00 00 00 46 61
+ 29 01 00 00 00 00 02 EA 1F
+ 29 01 00 00 00 00 04 EE 41 51 00
+ 29 01 00 00 00 00 03 F1 00 00
+ 39 01 00 00 00 00 05 2A 00 00 04 37
+ 39 01 00 00 00 00 05 2B 00 00 08 6F
+ 39 01 00 00 00 00 01 2C
+ 29 01 00 00 00 00 02 B0 00
+ 39 01 00 00 00 00 02 51 FF
+ 39 01 00 00 00 00 02 53 0C
+ 39 01 00 00 00 00 02 55 00
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 96 00 01 11
+ 05 01 00 00 32 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-td4328-1080p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-td4328-1080p-video.dtsi
new file mode 100755
index 0000000..e9b7bac
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/dsi-panel-td4328-1080p-video.dtsi
@@ -0,0 +1,164 @@
+&mdss_mdp {
+ dsi_td4328_truly_video: qcom,mdss_dsi_td4328_truly_video {
+ qcom,mdss-dsi-panel-name =
+ "td4328 video mode dsi truly panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <70>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <10>;
+ qcom,mdss-dsi-v-front-porch = <5>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 29 01 00 00 00 00 02 B0 00
+ 29 01 00 00 00 00 04 B3 31 00 06
+ 29 01 00 00 00 00 02 B4 00
+ 29 01 00 00 00 00 06 B6 33 DB 80 12 00
+ 29 01 00 00 00 00 08 B8 57 3D 19 1E 0A
+ 50 50
+ 29 01 00 00 00 00 08 B9 6F 3D 28 3C 14
+ C8 C8
+ 29 01 00 00 00 00 08 BA B5 33 41 64 23
+ A0 A0
+ 29 01 00 00 00 00 03 BB 14 14
+ 29 01 00 00 00 00 03 BC 37 32
+ 29 01 00 00 00 00 03 BD 64 32
+ 29 01 00 00 00 00 02 BE 04
+ 29 01 00 00 00 00 02 C0 00
+ 29 01 00 00 00 00 2E C1 04 48 00 00 26
+ 15 19 0B 63 D2 D9 9A 73 EF BD E7 5C
+ 6B 93 4D 22 18 8B 2A 41 00 00 00 00
+ 00 00 00 00 00 40 02 22 1B 06 03 00
+ 07 FF 00 01
+ 29 01 00 00 00 00 18 C2 01 F8 70 08 68
+ 08 0C 10 00 08 30 00 00 00 00 00 00
+ 20 02 43 00 00 00
+ 29 01 00 00 00 00 3F C3 87 D8 7D 87 D0
+ 00 00 00 00 00 00 04 3A 00 00 00 04
+ 44 00 00 01 01 03 28 00 01 00 01 00
+ 00 19 00 0C 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 32 00 19 00 5A
+ 02 32 00 19 00 5A 02 40 00
+ 29 01 00 00 00 00 15 C4 70 00 00 00 11
+ 11 00 00 00 02 02 31 01 00 00 00 02
+ 01 01 01
+ 29 01 00 00 00 00 08 C5 08 00 00 00 00
+ 70 00
+ 29 01 00 00 00 00 40 C6 5B 2D 2D 07 54
+ 07 54 01 02 01 02 07 07 00 00 07 07
+ 0F 11 07 5B 00 5B 5B C2 C2 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 27 C7 01 1D 2E 41 4F
+ 5A 71 80 8B 95 45 4F 5C 71 7B 88 98
+ A6 BE 01 1D 2E 41 4F 5A 71 80 8B 95
+ 45 4F 5C 71 7B 88 98 A6 BE
+ 29 01 00 00 00 00 38 C8 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00
+ 29 01 00 00 00 00 14 C9 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00
+ 29 01 00 00 00 00 2C CA 1C FC FC FC 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 1C CB FF FF FF FF 0F
+ 00 08 00 01 00 31 F0 40 08 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 02 CC 02
+ 29 01 00 00 00 00 27 CD 10 80 37 C0 1A
+ 00 5C 02 19 90 11 88 D8 6C D8 6C 01
+ 00 00 00 32 00 32 00 5D 02 32 32 01
+ 33 00 33 00 5E 02 32 32 AF
+ 29 01 00 00 00 00 1A CE 5D 40 49 53 59
+ 5E 63 68 6E 74 7E 8A 98 A8 BB D0 FF
+ 04 00 04 04 42 00 69 5A
+ 29 01 00 00 00 00 03 CF 4A 1D
+ 29 01 00 00 00 00 12 D0 33 57 D4 31 01
+ 10 10 10 19 19 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 02 D1 00
+ 29 01 00 00 00 00 20 D2 10 00 00 10 75
+ 0F 03 25 20 00 00 00 00 00 00 00 00
+ 04 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 17 D3 1B 3B BB 77 77
+ 77 BB B3 33 00 00 6D 6E DB DB 33 BB
+ F2 FD C6 0B 07
+ 29 01 00 00 00 00 08 D4 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 08 D5 03 00 00 02 40
+ 02 40
+ 29 01 00 00 00 00 02 D6 01
+ 29 01 00 00 00 00 22 D7 F6 FF 03 05 41
+ 24 80 1F C7 1F 1B 00 0C 07 20 00 00
+ 00 00 00 0C 00 1F 00 FC 00 00 AA 67
+ 7E 5D 06 00
+ 29 01 00 00 00 00 03 D9 20 14
+ 29 01 00 00 00 00 05 DD 30 06 23 65
+ 29 01 00 00 00 00 05 DE 00 3F FF 90
+ 29 01 00 00 00 00 06 E7 00 00 00 46 61
+ 29 01 00 00 00 00 02 EA 1F
+ 29 01 00 00 00 00 04 EE 41 51 00
+ 29 01 00 00 00 00 03 F1 00 00
+ 39 01 00 00 00 00 05 2A 00 00 04 37
+ 39 01 00 00 00 00 05 2B 00 00 08 6F
+ 39 01 00 00 00 00 01 2C
+ 39 01 00 00 00 00 02 51 FF
+ 39 01 00 00 00 00 02 53 0C
+ 39 01 00 00 00 00 02 55 00
+ 05 01 00 00 96 00 01 11
+ 05 01 00 00 32 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-cdp-lcd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-cdp-lcd.dtsi
new file mode 100755
index 0000000..a7d85df
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-cdp-lcd.dtsi
@@ -0,0 +1,36 @@
+&dsi_sharp_4k_dsc_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ /delete-property/ qcom,platform-en-gpio;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ /delete-property/ qcom,platform-en-gpio;
+};
+
+&dsi_sharp_1080_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&dsi_dual_nt35597_truly_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&dsi_dual_nt35597_truly_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&sde_dsi {
+ /delete-property/ avdd-supply;
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+ qcom,dsi-default-panel = <&dsi_sharp_4k_dsc_cmd>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-cdp.dtsi
new file mode 100755
index 0000000..fadbce6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-cdp.dtsi
@@ -0,0 +1,152 @@
+#include "kona-sde-display.dtsi"
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-en-gpio = <&tlmm 60 0>;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-en-gpio = <&tlmm 60 0>;
+};
+
+&dsi_sharp_1080_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_nt35597_truly_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_nt35597_truly_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-sec-reset-gpio = <&tlmm 128 0>;
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_sec_hd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-sec-reset-gpio = <&tlmm 128 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-mtp.dtsi
new file mode 100755
index 0000000..b81aad8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-mtp.dtsi
@@ -0,0 +1,87 @@
+#include "kona-sde-display.dtsi"
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_sec_hd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-sec-reset-gpio = <&tlmm 128 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-qrd.dtsi
new file mode 100755
index 0000000..1f6e32a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-qrd.dtsi
@@ -0,0 +1,76 @@
+#include "kona-sde-display.dtsi"
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-rumi.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-rumi.dtsi
new file mode 100755
index 0000000..3eb83e4
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display-rumi.dtsi
@@ -0,0 +1 @@
+#include "kona-sde-display.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display.dtsi
new file mode 100755
index 0000000..6257b55
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-display.dtsi
@@ -0,0 +1,528 @@
+#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi"
+#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi"
+#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi"
+#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
+#include "dsi-panel-sharp-dsc-4k-video.dtsi"
+#include "dsi-panel-sharp-1080p-cmd.dtsi"
+#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
+#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
+#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
+#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
+#include "dsi-panel-sim-cmd.dtsi"
+#include "dsi-panel-sim-video.dtsi"
+#include "dsi-panel-sim-dsc375-cmd.dtsi"
+#include "dsi-panel-sim-dsc-10bit-cmd.dtsi"
+#include "dsi-panel-sim-dualmipi-cmd.dtsi"
+#include "dsi-panel-sim-dualmipi-video.dtsi"
+#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
+#include "dsi-panel-sim-sec-hd-cmd.dtsi"
+#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
+
+&tlmm {
+ display_panel_avdd_default: display_panel_avdd_default {
+ mux {
+ pins = "gpio61";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio61";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ output-high;
+ };
+ };
+};
+
+&soc {
+ ext_disp: qcom,msm-ext-disp {
+ compatible = "qcom,msm-ext-disp";
+
+ ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
+ compatible = "qcom,msm-ext-disp-audio-codec-rx";
+ };
+ };
+
+ dsi_panel_pwr_supply: dsi_panel_pwr_supply {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "vdd";
+ qcom,supply-min-voltage = <3300000>;
+ qcom,supply-max-voltage = <3300000>;
+ qcom,supply-enable-load = <857000>;
+ qcom,supply-disable-load = <0>;
+ qcom,supply-post-on-sleep = <0>;
+ };
+ };
+
+ dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "avdd";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+ };
+
+ display_panel_avdd: display_gpio_regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "display_panel_avdd";
+ regulator-min-microvolt = <5500000>;
+ regulator-max-microvolt = <5500000>;
+ regulator-enable-ramp-delay = <233>;
+ gpio = <&tlmm 61 0>;
+ enable-active-high;
+ regulator-boot-on;
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_panel_avdd_default>;
+ };
+
+ sde_dsi: qcom,dsi-display-primary {
+ compatible = "qcom,dsi-display";
+ label = "primary";
+
+ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+ qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+
+ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll PCLK_MUX_0_CLK>,
+ <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
+ <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
+ clock-names = "src_byte_clk0", "src_pixel_clk0",
+ "src_byte_clk1", "src_pixel_clk1";
+
+ pinctrl-names = "panel_active", "panel_suspend";
+ pinctrl-0 = <&sde_dsi_active &sde_te_active>;
+ pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
+
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,panel-te-source = <0>;
+
+ vddio-supply = <&pm8150_l14>;
+ vdd-supply = <&pm8150a_l11>;
+ avdd-supply = <&display_panel_avdd>;
+
+ qcom,mdp = <&mdss_mdp>;
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
+ };
+
+ sde_dsi1: qcom,dsi-display-secondary {
+ compatible = "qcom,dsi-display";
+ label = "secondary";
+
+ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+ qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+
+ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll PCLK_MUX_0_CLK>,
+ <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
+ <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
+ clock-names = "src_byte_clk0", "src_pixel_clk0",
+ "src_byte_clk1", "src_pixel_clk1";
+
+ pinctrl-names = "panel_active", "panel_suspend";
+ pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
+ pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
+
+ qcom,platform-te-gpio = <&tlmm 67 0>;
+ qcom,panel-te-source = <1>;
+
+ vddio-supply = <&pm8150_l14>;
+ vdd-supply = <&pm8150a_l11>;
+ avdd-supply = <&display_panel_avdd>;
+
+ qcom,mdp = <&mdss_mdp>;
+ };
+
+ sde_wb: qcom,wb-display@0 {
+ compatible = "qcom,wb-display";
+ cell-index = <0>;
+ label = "wb_display";
+ };
+};
+
+&sde_dp {
+ qcom,dp-usbpd-detection = <&pm8150b_pdphy>;
+ qcom,ext-disp = <&ext_disp>;
+ qcom,dp-aux-switch = <&fsa4480>;
+
+ qcom,usbplug-cc-gpio = <&tlmm 65 0>;
+
+ pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
+ pinctrl-0 = <&sde_dp_usbplug_cc_active>;
+ pinctrl-1 = <&sde_dp_usbplug_cc_suspend>;
+};
+
+&mdss_mdp {
+ connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>;
+};
+
+/* PHY TIMINGS REVISION W */
+&dsi_sw43404_amoled_cmd {
+ qcom,ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
+ 05 03 02 04 00 12 15];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
+ };
+ };
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-supported-dfps-list = <60 57 55>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp";
+ qcom,mdss-dsi-min-refresh-rate = <55>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
+ 05 03 02 04 00 12 15];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04
+ 05 02 03 04 00 11 14];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 270 270 270 1080 270>;
+ };
+ };
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sharp_1080_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ qcom,mdss-dsi-panel-clockrate = <900000000>;
+ };
+ };
+};
+
+&dsi_dual_nt35597_truly_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_nt35597_truly_video {
+ qcom,mdss-dsi-min-refresh-rate = <53>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
+ 08 08 05 02 04 00 19 17];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
+ 08 08 05 02 04 00 19 17];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ qcom,panel-roi-alignment = <720 40 720 40 720 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+
+ timing@3 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ qcom,panel-roi-alignment = <540 40 540 40 540 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+
+ timing@4 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ qcom,panel-roi-alignment = <360 40 360 40 360 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+ };
+};
+
+&dsi_sim_vid {
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 0 1>,
+ <2 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 { /* 1080p */
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 { /* qhd */
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>, /* dsc merge */
+ <2 1 1>; /* 3d mux */
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 { /* QHD 60fps */
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 { /* 1080 60fps */
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>, /* dsc merge */
+ <2 1 1>; /* 3d mux */
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 { /* QHD 90fps */
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_sim_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
+ 09 06 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_sim_vid {
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 { /* qhd */
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 { /* 4k */
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 { /* 5k */
+ qcom,mdss-dsi-panel-phy-timings = [00 46 13 14 33 30 12
+ 14 0e 02 04 00 37 22];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_sec_hd_cmd {
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
+ 08 08 05 02 04 00 19 17];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ qcom,panel-roi-alignment = <720 40 720 40 720 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-pll.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-pll.dtsi
new file mode 100755
index 0000000..e6bda66
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde-pll.dtsi
@@ -0,0 +1,82 @@
+&soc {
+ mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94900 {
+ compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
+ label = "MDSS DSI 0 PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+ reg = <0xae94900 0x260>,
+ <0xae94400 0x800>,
+ <0xaf03000 0x8>;
+ reg-names = "pll_base", "phy_base", "gdsc_base";
+ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ gdsc-supply = <&mdss_core_gdsc>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi1_pll: qcom,mdss_dsi_pll@ae96900 {
+ compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
+ label = "MDSS DSI 1 PLL";
+ cell-index = <1>;
+ #clock-cells = <1>;
+ reg = <0xae96900 0x260>,
+ <0xae96400 0x800>,
+ <0xaf03000 0x8>;
+ reg-names = "pll_base", "phy_base", "gdsc_base";
+ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ gdsc-supply = <&mdss_core_gdsc>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dp_pll: qcom,mdss_dp_pll@c011000 {
+ compatible = "qcom,mdss_dp_pll_7nm";
+ label = "MDSS DP PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+
+ reg = <0x088ea000 0x200>,
+ <0x088eaa00 0x200>,
+ <0x088ea200 0x200>,
+ <0x088ea600 0x200>,
+ <0xaf03000 0x8>;
+ reg-names = "pll_base", "phy_base", "ln_tx0_base",
+ "ln_tx1_base", "gdsc_base";
+
+ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_DISP_AHB_CLK>,
+ <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "iface_clk", "ref_clk_src",
+ "gcc_iface", "pipe_clk";
+ clock-rate = <0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/display/kona-sde.dtsi b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde.dtsi
new file mode 100755
index 0000000..d6a849e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/display/kona-sde.dtsi
@@ -0,0 +1,688 @@
+#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
+
+&soc {
+ mdss_mdp: qcom,mdss_mdp@ae00000 {
+ compatible = "qcom,sde-kms";
+ reg = <0x0ae00000 0x84208>,
+ <0x0aeb0000 0x2008>,
+ <0x0aeac000 0x214>,
+ <0x0ae8f000 0x02c>,
+ <0x0af50000 0x038>;
+ reg-names = "mdp_phys",
+ "vbif_phys",
+ "regdma_phys",
+ "sid_phys",
+ "swfuse_phys";
+
+ clocks =
+ <&clock_gcc GCC_DISP_AHB_CLK>,
+ <&clock_gcc GCC_DISP_HF_AXI_CLK>,
+ <&clock_gcc GCC_DISP_SF_AXI_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
+ clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
+ "iface_clk", "core_clk", "vsync_clk",
+ "lut_clk", "rot_clk";
+ clock-rate = <0 0 0 0 300000000 19200000 300000000 19200000>;
+ clock-max-rate = <0 0 0 0 460000000 19200000 460000000
+ 460000000>;
+
+ mmcx-supply = <&VDD_MMCX_LEVEL>;
+
+ /* interrupt config */
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #power-domain-cells = <0>;
+
+ /* hw blocks */
+ qcom,sde-off = <0x1000>;
+ qcom,sde-len = <0x494>;
+
+ qcom,sde-ctl-off = <0x2000 0x2200 0x2400
+ 0x2600 0x2800 0x2a00>;
+ qcom,sde-ctl-size = <0x1dc>;
+ qcom,sde-ctl-display-pref = "primary", "none", "none",
+ "none", "none";
+
+ qcom,sde-mixer-off = <0x45000 0x46000 0x47000
+ 0x48000 0x49000 0x4a000>;
+ qcom,sde-mixer-size = <0x320>;
+ qcom,sde-mixer-display-pref = "primary", "primary", "none",
+ "none", "none", "none";
+
+ qcom,sde-mixer-cwb-pref = "none", "none", "cwb",
+ "cwb", "cwb", "cwb";
+
+ qcom,sde-dspp-top-off = <0x1300>;
+ qcom,sde-dspp-top-size = <0x80>;
+ qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
+ qcom,sde-dspp-size = <0x1800>;
+
+ qcom,sde-dest-scaler-top-off = <0x00061000>;
+ qcom,sde-dest-scaler-top-size = <0x1c>;
+ qcom,sde-dest-scaler-off = <0x800 0x1000>;
+ qcom,sde-dest-scaler-size = <0x800>;
+
+ qcom,sde-wb-off = <0x66000>;
+ qcom,sde-wb-size = <0x2c8>;
+ qcom,sde-wb-xin-id = <6>;
+ qcom,sde-wb-id = <2>;
+ qcom,sde-wb-clk-ctrl = <0x2bc 16>;
+
+ qcom,sde-intf-off = <0x6b000 0x6b800
+ 0x6c000 0x6c800>;
+ qcom,sde-intf-size = <0x2b8>;
+ qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
+
+ qcom,sde-pp-off = <0x71000 0x71800
+ 0x72000 0x72800 0x73000 0x73800>;
+ qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>;
+ qcom,sde-pp-size = <0xd4>;
+ qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>;
+
+ qcom,sde-merge-3d-off = <0x84000 0x84100 0x84200>;
+ qcom,sde-merge-3d-size = <0x100>;
+
+ qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0 0x0>;
+
+ qcom,sde-cdm-off = <0x7a200>;
+ qcom,sde-cdm-size = <0x224>;
+
+ qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>;
+ qcom,sde-dsc-size = <0x140>;
+
+ qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0
+ 0x30e0 0x30e0 0x30e0>;
+ qcom,sde-dither-version = <0x00010000>;
+ qcom,sde-dither-size = <0x20>;
+
+ qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
+ "dma", "dma", "dma", "dma";
+
+ qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
+ 0x25000 0x27000 0x29000 0x2b000>;
+ qcom,sde-sspp-src-size = <0x1f8>;
+
+ qcom,sde-sspp-xin-id = <0 4 8 12
+ 1 5 9 13>;
+ qcom,sde-sspp-excl-rect = <1 1 1 1
+ 1 1 1 1>;
+ qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;
+ qcom,sde-smart-dma-rev = "smart_dma_v2p5";
+
+ qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>;
+
+ qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
+ 0xb0 0xc8 0xe0 0xf8 0x110>;
+
+ qcom,sde-max-per-pipe-bw-kbps = <4400000 4400000
+ 4400000 4400000
+ 4400000 4400000
+ 4400000 4400000>;
+
+ qcom,sde-max-per-pipe-bw-high-kbps = <5300000 5300000
+ 5300000 5300000
+ 5300000 5300000
+ 5300000 5300000>;
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+ qcom,sde-sspp-clk-ctrl =
+ <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
+ <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
+ qcom,sde-sspp-csc-off = <0x1a00>;
+ qcom,sde-csc-type = "csc-10bit";
+ qcom,sde-qseed-type = "qseedv3lite";
+ qcom,sde-sspp-qseed-off = <0xa00>;
+ qcom,sde-mixer-linewidth = <2560>;
+ qcom,sde-sspp-linewidth = <4096>;
+ qcom,sde-wb-linewidth = <4096>;
+ qcom,sde-mixer-blendstages = <0xb>;
+ qcom,sde-highest-bank-bit = <0x3>;
+ qcom,sde-ubwc-version = <0x400>;
+ qcom,sde-ubwc-swizzle = <0x6>;
+ qcom,sde-ubwc-bw-calc-version = <0x1>;
+ qcom,sde-ubwc-static = <0x1>;
+ qcom,sde-macrotile-mode = <0x1>;
+ qcom,sde-smart-panel-align-mode = <0xc>;
+ qcom,sde-panic-per-pipe;
+ qcom,sde-has-cdp;
+ qcom,sde-has-src-split;
+ qcom,sde-pipe-order-version = <0x1>;
+ qcom,sde-has-dim-layer;
+ qcom,sde-has-dest-scaler;
+ qcom,sde-has-idle-pc;
+ qcom,sde-max-dest-scaler-input-linewidth = <2048>;
+ qcom,sde-max-dest-scaler-output-linewidth = <2560>;
+ qcom,sde-max-bw-low-kbps = <13700000>;
+ qcom,sde-max-bw-high-kbps = <16600000>;
+ qcom,sde-min-core-ib-kbps = <2400000>;
+ qcom,sde-min-llcc-ib-kbps = <800000>;
+ qcom,sde-min-dram-ib-kbps = <800000>;
+ qcom,sde-dram-channels = <2>;
+ qcom,sde-num-nrt-paths = <0>;
+ qcom,sde-dspp-ltm-version = <0x00010000>;
+ /* offsets are based off dspp 0 and dspp 1 */
+ qcom,sde-dspp-ltm-off = <0x2a000 0x28100>;
+
+ qcom,sde-uidle-off = <0x80000>;
+ qcom,sde-uidle-size = <0x70>;
+
+ qcom,sde-vbif-off = <0>;
+ qcom,sde-vbif-size = <0x1040>;
+ qcom,sde-vbif-id = <0>;
+ qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
+
+ qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
+ qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;
+ qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>;
+
+ /* macrotile & macrotile-qseed has the same configs */
+ qcom,sde-danger-lut = <0x000000ff 0x0000ffff
+ 0x00000000 0x00000000 0x0000ffff>;
+
+ qcom,sde-safe-lut-linear = <0 0xfff0>;
+ qcom,sde-safe-lut-macrotile = <0 0xff00>;
+ /* same as safe-lut-macrotile */
+ qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>;
+ qcom,sde-safe-lut-nrt = <0 0xffff>;
+ qcom,sde-safe-lut-cwb = <0 0x3ff>;
+
+ qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;
+ qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;
+ qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;
+ qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;
+ qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>;
+
+ qcom,sde-cdp-setting = <1 1>, <1 0>;
+
+ qcom,sde-qos-cpu-mask = <0x3>;
+ qcom,sde-qos-cpu-dma-latency = <300>;
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+
+ qcom,sde-reg-dma-off = <0>;
+ qcom,sde-reg-dma-version = <0x00010002>;
+ qcom,sde-reg-dma-trigger-off = <0x119c>;
+ qcom,sde-reg-dma-xin-id = <7>;
+ qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
+
+ qcom,sde-secure-sid-mask = <0x4000821>;
+
+ qcom,sde-sspp-vig-blocks {
+ qcom,sde-vig-csc-off = <0x1a00>;
+ qcom,sde-vig-qseed-off = <0xa00>;
+ qcom,sde-vig-qseed-size = <0xa0>;
+ qcom,sde-vig-gamut = <0x1d00 0x00060000>;
+ qcom,sde-vig-igc = <0x1d00 0x00060000>;
+ qcom,sde-vig-inverse-pma;
+ };
+
+ qcom,sde-sspp-dma-blocks {
+ dgm@0 {
+ qcom,sde-dma-igc = <0x400 0x00050000>;
+ qcom,sde-dma-gc = <0x600 0x00050000>;
+ qcom,sde-dma-inverse-pma;
+ qcom,sde-dma-csc-off = <0x200>;
+ };
+
+ dgm@1 {
+ qcom,sde-dma-igc = <0x1400 0x00050000>;
+ qcom,sde-dma-gc = <0x600 0x00050000>;
+ qcom,sde-dma-inverse-pma;
+ qcom,sde-dma-csc-off = <0x1200>;
+ };
+ };
+
+ qcom,sde-dspp-blocks {
+ qcom,sde-dspp-igc = <0x0 0x00030001>;
+ qcom,sde-dspp-hsic = <0x800 0x00010007>;
+ qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+ qcom,sde-dspp-hist = <0x800 0x00010007>;
+ qcom,sde-dspp-sixzone= <0x900 0x00010007>;
+ qcom,sde-dspp-vlut = <0xa00 0x00010008>;
+ qcom,sde-dspp-gamut = <0x1000 0x00040001>;
+ qcom,sde-dspp-pcc = <0x1700 0x00040000>;
+ qcom,sde-dspp-gc = <0x17c0 0x00010008>;
+ qcom,sde-dspp-dither = <0x82c 0x00010007>;
+ };
+
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "mmcx";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
+ compatible = "qcom,smmu_sde_unsec";
+ iommus = <&apps_smmu 0x820 0x402>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-earlymap; /* for cont-splash */
+ };
+
+ smmu_sde_sec: qcom,smmu_sde_sec_cb {
+ compatible = "qcom,smmu_sde_sec";
+ iommus = <&apps_smmu 0x821 0x400>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xa>;
+ };
+
+ /* data and reg bus scale settings */
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "mdss_sde";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>, <23 512 0 0>,
+ <22 512 0 6400000>, <23 512 0 6400000>,
+ <22 512 0 6400000>, <23 512 0 6400000>;
+ };
+
+ qcom,sde-reg-bus {
+ qcom,msm-bus,name = "mdss_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 150000>,
+ <1 590 0 300000>;
+ };
+ };
+
+ sde_dp: qcom,dp_display@ae90000 {
+ cell-index = <0>;
+ compatible = "qcom,dp-display";
+
+ vdda-1p2-supply = <&pm8150_l9>;
+ vdda-0p9-supply = <&pm8150_l18>;
+
+ reg = <0xae90000 0x0dc>,
+ <0xae90200 0x0c0>,
+ <0xae90400 0x508>,
+ <0xae91000 0x094>,
+ <0x88eaa00 0x200>,
+ <0x88ea200 0x200>,
+ <0x88ea600 0x200>,
+ <0xaf02000 0x1a0>,
+ <0x780000 0x621c>,
+ <0x88ea040 0x10>,
+ <0x88e8000 0x20>,
+ <0x0aee1000 0x034>,
+ <0xae91400 0x094>;
+ /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */
+ reg-names = "dp_ahb", "dp_aux", "dp_link",
+ "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
+ "dp_mmss_cc", "qfprom_physical", "dp_pll",
+ "usb3_dp_com", "hdcp_physical", "dp_p1";
+
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <12 0>;
+
+ clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
+ <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
+ <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
+ <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
+ clock-names = "core_aux_clk", "core_usb_ref_clk_src",
+ "core_usb_pipe_clk", "link_clk", "link_iface_clk",
+ "pixel_clk_rcg", "pixel_parent",
+ "pixel1_clk_rcg", "pixel1_parent",
+ "strm0_pixel_clk", "strm1_pixel_clk";
+
+ qcom,phy-version = <0x420>;
+ qcom,aux-cfg0-settings = [20 00];
+ qcom,aux-cfg1-settings = [24 13];
+ qcom,aux-cfg2-settings = [28 A4];
+ qcom,aux-cfg3-settings = [2c 00];
+ qcom,aux-cfg4-settings = [30 0a];
+ qcom,aux-cfg5-settings = [34 26];
+ qcom,aux-cfg6-settings = [38 0a];
+ qcom,aux-cfg7-settings = [3c 03];
+ qcom,aux-cfg8-settings = [40 b7];
+ qcom,aux-cfg9-settings = [44 03];
+
+ qcom,max-pclk-frequency-khz = <675000>;
+
+ qcom,mst-enable;
+ qcom,widebus-enable;
+ qcom,dsc-feature-enable;
+ qcom,fec-feature-enable;
+ qcom,max-dp-dsc-blks = <2>;
+ qcom,max-dp-dsc-input-width-pixs = <2048>;
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1200000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <33000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <912000>;
+ qcom,supply-max-voltage = <912000>;
+ qcom,supply-enable-load = <126000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ sde_rscc: qcom,sde_rscc@af20000 {
+ cell-index = <0>;
+ compatible = "qcom,sde-rsc";
+ reg = <0xaf20000 0x3c50>,
+ <0xaf30000 0x3fd4>;
+ reg-names = "drv", "wrapper";
+ qcom,sde-rsc-version = <3>;
+
+ qcom,sde-dram-channels = <2>;
+
+ vdd-supply = <&mdss_core_gdsc>;
+ clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
+ clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
+
+ /* data and reg bus scale settings */
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "disp_rsc_mnoc_llcc";
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <20003 20513 0 0>, <20004 20513 0 0>,
+ <20003 20513 0 6400000>, <20004 20513 0 6400000>,
+ <20003 20513 0 6400000>, <20004 20513 0 6400000>;
+ };
+
+ qcom,sde-ebi-bus {
+ qcom,msm-bus,name = "disp_rsc_ebi";
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <20000 20512 0 0>,
+ <20000 20512 0 6400000>,
+ <20000 20512 0 6400000>;
+ };
+ };
+
+ mdss_rotator: qcom,mdss_rotator@aea8800 {
+ compatible = "qcom,sde_rotator";
+ reg = <0x0ae00000 0xac000>,
+ <0x0aeb8000 0x3000>;
+ reg-names = "mdp_phys",
+ "rot_vbif_phys";
+ status = "disabled";
+
+ #list-cells = <1>;
+
+ qcom,mdss-rot-mode = <1>;
+ qcom,mdss-highest-bank-bit = <0x3>;
+
+ /* Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_rotator";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <25 512 0 0>,
+ <25 512 0 6400000>,
+ <25 512 0 6400000>;
+
+ rot-vdd-supply = <&mdss_core_gdsc>;
+ qcom,supply-names = "rot-vdd";
+
+ clocks =
+ <&clock_gcc GCC_DISP_AHB_CLK>,
+ <&clock_gcc GCC_DISP_SF_AXI_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
+ clock-names = "gcc_iface", "gcc_bus",
+ "iface_clk", "rot_clk";
+
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <2 0>;
+
+ power-domains = <&mdss_mdp>;
+
+ /* Offline rotator QoS setting */
+ qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
+ qcom,mdss-rot-vbif-memtype = <3 3>;
+ qcom,mdss-rot-cdp-setting = <1 1>;
+ qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
+ qcom,mdss-rot-danger-lut = <0x0 0x0>;
+ qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
+
+ qcom,mdss-default-ot-rd-limit = <32>;
+ qcom,mdss-default-ot-wr-limit = <32>;
+
+ qcom,mdss-sbuf-headroom = <20>;
+
+ /* reg bus scale settings */
+ rot_reg: qcom,rot-reg-bus {
+ qcom,msm-bus,name = "mdss_rot_reg";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>;
+ };
+
+ smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
+ compatible = "qcom,smmu_sde_rot_unsec";
+ iommus = <&apps_smmu 0x215C 0x0400>;
+ qcom,iommu-dma = "disabled";
+ };
+ };
+
+ mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
+ compatible = "qcom,dsi-ctrl-hw-v2.4";
+ label = "dsi-ctrl-0";
+ cell-index = <0>;
+ reg = <0xae94000 0x400>,
+ <0xaf08000 0x4>;
+ reg-names = "dsi_ctrl", "disp_cc_base";
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <4 0>;
+ vdda-1p2-supply = <&pm8150_l9>;
+ refgen-supply = <&refgen>;
+ clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+ <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>;
+ clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+ "pixel_clk", "pixel_clk_rcg", "esc_clk";
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1200000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <26700>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
+ compatible = "qcom,dsi-ctrl-hw-v2.4";
+ label = "dsi-ctrl-1";
+ cell-index = <1>;
+ reg = <0xae96000 0x400>,
+ <0xaf08000 0x4>;
+ reg-names = "dsi_ctrl", "disp_cc_base";
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <5 0>;
+ vdda-1p2-supply = <&pm8150_l9>;
+ refgen-supply = <&refgen>;
+ clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
+ <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>;
+ clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+ "pixel_clk", "pixel_clk_rcg", "esc_clk";
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1200000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <26700>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 {
+ compatible = "qcom,dsi-phy-v4.1";
+ label = "dsi-phy-0";
+ cell-index = <0>;
+ reg = <0xae94400 0x760>;
+ reg-names = "dsi_phy";
+ vdda-0p9-supply = <&pm8150_l5>;
+ qcom,platform-strength-ctrl = [55 03
+ 55 03
+ 55 03
+ 55 03
+ 55 00];
+ qcom,platform-lane-config = [00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 8a 8a];
+ qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <880000>;
+ qcom,supply-max-voltage = <880000>;
+ qcom,supply-enable-load = <46000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96400 {
+ compatible = "qcom,dsi-phy-v4.1";
+ label = "dsi-phy-1";
+ cell-index = <1>;
+ reg = <0xae96400 0x760>;
+ reg-names = "dsi_phy";
+ vdda-0p9-supply = <&pm8150_l5>;
+ qcom,platform-strength-ctrl = [55 03
+ 55 03
+ 55 03
+ 55 03
+ 55 00];
+ qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+ qcom,platform-lane-config = [00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 8a 8a];
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <880000>;
+ qcom,supply-max-voltage = <880000>;
+ qcom,supply-enable-load = <46000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-adv7533-1080p.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-adv7533-1080p.dtsi
new file mode 100755
index 0000000..0a4f9e6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-adv7533-1080p.dtsi
@@ -0,0 +1,63 @@
+&mdss_mdp {
+ dsi_adv7533_1080p: qcom,mdss_dsi_adv7533_1080p {
+ label = "adv7533 1080p video mode dsi panel";
+ qcom,mdss-dsi-panel-name = "dsi_adv7533_1080p";
+ qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-destination = "display_1";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <1920>;
+ qcom,mdss-dsi-panel-height = <1080>;
+ qcom,mdss-dsi-h-front-porch = <88>;
+ qcom,mdss-dsi-h-back-porch = <148>;
+ qcom,mdss-dsi-h-pulse-width = <44>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <36>;
+ qcom,mdss-dsi-v-front-porch = <4>;
+ qcom,mdss-dsi-v-pulse-width = <5>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-on-command = [
+ 05 01 00 00 c8 00 02 11 00
+ 05 01 00 00 0a 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00
+ 05 01 00 00 00 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <1>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings = [
+ E6 38 26 00 68 6C 2A 3A 2C 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x02>;
+ qcom,mdss-dsi-t-clk-pre = <0x2B>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
+ qcom,mdss-pan-physical-width-dimension = <160>;
+ qcom,mdss-pan-physical-height-dimension = <90>;
+ qcom,mdss-dsi-force-clock-lane-hs;
+ qcom,mdss-dsi-always-on;
+ qcom,mdss-dsi-panel-timings-phy-v2 = [1d 1a 03 05 01 03 04 a0
+ 1d 1a 03 05 01 03 04 a0
+ 1d 1a 03 05 01 03 04 a0
+ 1d 1a 03 05 01 03 04 a0
+ 1d 1a 03 05 01 03 04 a0];
+ qcom,dba-panel;
+ qcom,bridge-name = "adv7533";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-adv7533-720p.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-adv7533-720p.dtsi
new file mode 100755
index 0000000..82f6b92
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-adv7533-720p.dtsi
@@ -0,0 +1,62 @@
+&mdss_mdp {
+dsi_adv7533_720p: qcom,mdss_dsi_adv7533_720p {
+ label = "adv7533 720p video mode dsi panel";
+ qcom,mdss-dsi-panel-name = "dsi_adv7533_720p";
+ qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-destination = "display_1";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <1280>;
+ qcom,mdss-dsi-panel-height = <720>;
+ qcom,mdss-dsi-h-front-porch = <110>;
+ qcom,mdss-dsi-h-back-porch = <220>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <20>;
+ qcom,mdss-dsi-v-front-porch = <5>;
+ qcom,mdss-dsi-v-pulse-width = <5>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-on-command = [
+ 05 01 00 00 c8 00 02 11 00
+ 05 01 00 00 0a 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00
+ 05 01 00 00 00 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <1>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-panel-timings = [
+ A4 24 18 00 4E 52 1C 28 1C 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x03>;
+ qcom,mdss-dsi-t-clk-pre = <0x20>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
+ qcom,mdss-pan-physical-width-dimension = <160>;
+ qcom,mdss-pan-physical-height-dimension = <90>;
+ qcom,mdss-dsi-force-clock-lane-hs;
+ qcom,mdss-dsi-always-on;
+ qcom,mdss-dsi-panel-timings-phy-v2 = [1c 19 02 03 01 03 04 a0
+ 1c 19 02 03 01 03 04 a0
+ 1c 19 02 03 01 03 04 a0
+ 1c 19 02 03 01 03 04 a0
+ 1c 08 02 03 01 03 04 a0];
+ qcom,dba-panel;
+ qcom,bridge-name = "adv7533";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi
new file mode 100755
index 0000000..68de1d6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-arglass-seeya-dual-1080p-video.dtsi
@@ -0,0 +1,116 @@
+&mdss_mdp {
+ dsi_dual_arglass_seeya_video: qcom,mdss_dsi_arglass_seeya_video {
+ qcom,mdss-dsi-panel-name =
+ "sy049wdm02 uoled video mode dsi seeya panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-count = <2>;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1920>;
+ qcom,mdss-dsi-panel-height = <1080>;
+ qcom,mdss-dsi-h-front-porch = <32>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <16>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-on-command = [
+ //cmd1
+ 39 01 00 00 00 00 02 53 29
+ 39 01 00 00 00 00 03 51 FF 01
+ 39 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 07 80 01 E0 E0 0E 00 31
+ 39 01 00 00 00 00 08 81 03 04 00 10 00 10 00
+ 39 01 00 00 00 00 08 82 03 04 00 10 00 10 01
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 26 20
+ //pps
+ 39 01 00 00 00 00 11 70 00 00 00 89 20 80 04 38
+ 07 80 00 1e 03 C0 03 C0
+ 39 01 00 00 00 00 02 65 10
+ 39 01 00 00 00 00 11 70 02 00 00 00 00 20 03 B4
+ 00 0D 00 0C 03 50 01 E9
+ 39 01 00 00 00 00 02 65 20
+ 39 01 00 00 00 00 0D 70 18 00 10 F0 03 0C 20 00
+ 06 0B 0B 33
+ // cmd2 p1
+ 39 01 00 00 00 00 03 F0 AA 11
+ 39 01 00 00 00 00 02 C0 00
+ 39 01 00 00 00 00 09 C2 03 FF 03 FF 03 FF 03 FF
+ // cmd2 p2
+ 39 01 00 00 00 00 03 F0 AA 12
+ 39 01 00 00 00 00 03 BF 37 A9
+ /* H mirror dsi1 */
+ 39 01 00 00 00 00 03 FF 5A 80
+ 39 01 00 00 00 00 02 65 2F
+ 39 01 00 00 00 00 02 F2 01
+ 39 01 00 00 00 00 02 36 02
+ /* v mirror dsi0 */
+ 39 01 00 04 00 00 03 FF 5A 80
+ 39 01 00 04 00 00 02 65 2F
+ 39 01 00 04 00 00 02 F2 01
+ 39 01 00 04 00 00 02 36 01
+ 39 01 00 04 00 00 03 F0 AA 13
+ 39 01 00 04 00 00 02 65 01
+ 39 01 00 04 00 00 02 C1 A2
+ 39 01 00 04 00 00 07 C4 12 53 64 31 42 56
+ 39 01 00 04 00 00 03 F0 AA 16
+ 39 01 00 04 00 00 07 B6 12 53 64 31 42 56
+ 39 01 00 04 00 00 03 B0 00 55
+ /* CMDs PP0 */
+ 39 01 00 00 00 00 03 FF 5A 80
+ 39 01 00 00 00 00 02 65 2F
+ 39 01 00 00 00 00 02 F2 01
+ //cmd3 p1
+ 39 01 00 00 00 00 03 FF 5A 81
+ 39 01 00 00 00 00 02 65 05
+ 39 01 00 00 00 00 02 F2 22
+ 39 01 00 00 00 00 02 65 0A
+ 39 01 00 00 00 00 02 F2 00
+ 39 01 00 00 00 00 02 65 16
+ 39 01 00 00 00 00 0F F9 01 5F 61 64 67 6A 6D 6F
+ 75 7B 80 86 8B 91
+ 05 01 00 00 14 00 01 11
+ 05 01 00 00 64 00 01 29
+ 39 01 00 00 00 00 03 F0 AA 11
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 0a 00
+ 02 28 00 05 01 00 00 3c 00 02 10 00];
+
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <30>;
+ qcom,mdss-dsc-slice-width = <960>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-edo-rm67162-qvga-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-edo-rm67162-qvga-cmd.dtsi
new file mode 100755
index 0000000..ce5ac64
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-edo-rm67162-qvga-cmd.dtsi
@@ -0,0 +1,76 @@
+&mdss_mdp {
+ dsi_edo_rm67162_qvga_cmd: qcom,mdss_dsi_edo_rm67162_qvga_cmd {
+ qcom,mdss-dsi-panel-name = "rm67162 qvga cmd mode dsi panel";
+ qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-destination = "display_1";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <320>;
+ qcom,mdss-dsi-panel-height = <360>;
+ qcom,mdss-dsi-h-front-porch = <140>;
+ qcom,mdss-dsi-h-back-porch = <164>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <1>;
+ qcom,mdss-dsi-v-front-porch = <6>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-pixel-packing = "tight";
+ qcom,mdss-dsi-pixel-alignment = <0>;
+ qcom,mdss-dsi-on-command = [29 01 00 00 00 00 02 FE 0A
+ 29 01 00 00 00 00 02 29 90
+ 29 01 00 00 00 00 02 FE 05
+ 29 01 00 00 00 00 02 05 00
+ 29 01 00 00 00 00 02 FE 00
+ 29 01 00 00 00 00 02 35 00
+ 29 01 00 00 00 00 02 51 80
+ 29 01 00 00 00 00 02 53 20
+ 29 01 00 00 78 00 02 11 00
+ 29 01 00 00 05 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 05 00 02 51 00
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00
+ 05 01 00 00 14 00 02 4F 01];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-idle-on-command = [
+ 15 01 00 00 00 00 02 FE 00
+ 05 01 00 00 00 00 01 39 /* Idle-Mode On */
+ ];
+ qcom,mdss-dsi-idle-off-command = [
+ 05 01 00 00 00 00 01 38 /* Idle-Mode Off */
+ ];
+ qcom,mdss-dsi-idle-on-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-idle-off-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-h-sync-pulse = <1>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-v-sync-rd-ptr-irq-line = <0x2c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33 22 27
+ 1e 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x09>;
+ qcom,mdss-dsi-t-clk-pre = <0x2c>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 1>, <0 12>, <1 12>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-ext-bridge-1080p.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-ext-bridge-1080p.dtsi
new file mode 100755
index 0000000..07d398e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-ext-bridge-1080p.dtsi
@@ -0,0 +1,46 @@
+&mdss_mdp {
+ dsi_ext_bridge_1080p: qcom,mdss_dsi_ext_bridge_1080p {
+ qcom,mdss-dsi-panel-name = "ext video mode dsi bridge";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-t-clk-post = <0x03>;
+ qcom,mdss-dsi-t-clk-pre = <0x24>;
+ qcom,mdss-dsi-force-clock-lane-hs;
+ qcom,mdss-dsi-ext-bridge-mode;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1920>;
+ qcom,mdss-dsi-panel-height = <1080>;
+ qcom,mdss-dsi-h-front-porch = <88>;
+ qcom,mdss-dsi-h-back-porch = <148>;
+ qcom,mdss-dsi-h-pulse-width = <44>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <36>;
+ qcom,mdss-dsi-v-front-porch = <4>;
+ qcom,mdss-dsi-v-pulse-width = <5>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-ext-bridge-4k-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-ext-bridge-4k-video.dtsi
new file mode 100755
index 0000000..8e9a04a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-ext-bridge-4k-video.dtsi
@@ -0,0 +1,45 @@
+&mdss_mdp {
+ dsi_ext_bridge_4k_vid: qcom,mdss_dsi_ext_bridge_4k_video {
+ qcom,mdss-dsi-panel-name = "ext 4k video mode dsi bridge";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-t-clk-post = <0x1e>;
+ qcom,mdss-dsi-t-clk-pre = <0x2e>;
+ qcom,mdss-dsi-force-clock-lane-hs;
+ qcom,mdss-dsi-ext-bridge-mode;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1920>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <88>;
+ qcom,mdss-dsi-h-back-porch = <200>;
+ qcom,mdss-dsi-h-pulse-width = <44>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <72>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <10>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,display-topology = <2 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-ft8716u-1080p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-ft8716u-1080p-video.dtsi
new file mode 100644
index 0000000..7d85622
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-ft8716u-1080p-video.dtsi
@@ -0,0 +1,285 @@
+/* Copyright (C) 2017 Tcl Corporation Limited */
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+&mdss_mdp {
+ dsi_ft8716u_1080_video: qcom,mdss_dsi_ft8716u_1080p_video {
+ qcom,mdss-dsi-panel-name = "ft8716u 1080p video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <1>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 02 0A 08];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-check-mode = "i2c_reg_read";
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-panel-status-value = <0x9C>;
+ //qcom,mdss-dsi-panel-status-value = <0x1C>;
+ qcom,mdss-dsi-panel-status-command_for_one = [14 01 00 01 05 00 01 EB];
+ qcom,mdss-dsi-panel-status-read-length_for_one = <1>;
+ qcom,mdss-dsi-panel-status-value_for_one = <0x01>;
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-init-delay-us = <50000>;
+ qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 23 21 07 07 05 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x0d>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 6>, <1 150>;
+ qcom,mdss-pan-physical-width-dimension = <65>;
+ qcom,mdss-pan-physical-height-dimension = <115>;
+ qcom,mdss-dsi-dma-schedule-line = <10>;
+ qcom,mdss-dsi-panel-hdr-enabled; //for test
+ qcom,mdss-dsi-panel-hdr-color-primaries = <15400 16350 33300 16650
+ 11250 35850 6950 2750>; //for test
+ qcom,mdss-dsi-panel-peak-brightness = <3500000>; //for test
+ qcom,mdss-dsi-panel-blackness-level = <350>; //for test
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <8>;
+ qcom,mdss-dsi-h-back-porch = <16>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <12>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-panel-framerate = <62>;
+ qcom,mdss-dsi-on-command = [
+ 05 01 00 00 78 00 02 00 00
+
+ 29 01 00 00 01 00 04 FF 87 16 01
+ 29 01 00 00 01 00 02 00 80
+ 29 01 00 00 01 00 03 FF 87 16
+ 29 01 00 00 01 00 02 00 80
+ 29 01 00 00 01 00 10 C0 00 77 00 10 10 00 77 10
+ 10 00 72 00 10 10 00
+ 29 01 00 00 01 00 02 00 80
+ 29 01 00 00 01 00 02 F3 70
+ 29 01 00 00 01 00 02 00 A0
+ 29 01 00 00 01 00 08 C0 05 01 01 09 01 16 08
+ 29 01 00 00 01 00 02 00 D0
+ 29 01 00 00 01 00 08 C0 05 01 01 09 01 16 08
+ 29 01 00 00 01 00 02 00 82
+ 29 01 00 00 01 00 04 A5 20 01 0C
+ 29 01 00 00 01 00 02 00 87
+ 29 01 00 00 01 00 05 A5 00 00 00 77
+ 29 01 00 00 01 00 02 00 A0
+ 29 01 00 00 01 00 02 B3 32
+ 29 01 00 00 01 00 02 00 A6
+ 29 01 00 00 01 00 02 B3 48
+ 29 01 00 00 01 00 02 00 80
+ 29 01 00 00 01 00 0D C2 82 00 00 00 81 00 00 00
+ 84 00 32 8A
+ 29 01 00 00 01 00 02 00 B0
+ 29 01 00 00 01 00 10 C2 80 04 00 07 86 01 05 00
+ 07 86 82 02 00 07 86
+ 29 01 00 00 01 00 02 00 C0
+ 29 01 00 00 01 00 0B C2 81 03 00 07 86 81 03 00
+ 7A 00
+ 29 01 00 00 01 00 02 00 DA
+ 29 01 00 00 01 00 03 C2 33 33
+ 29 01 00 00 01 00 02 00 AA
+
+ 29 01 00 00 01 00 03 C3 9C 99
+ 29 01 00 00 01 00 02 00 AC
+ 29 01 00 00 01 00 02 C3 99
+ 29 01 00 00 01 00 02 00 D3
+ 29 01 00 00 01 00 02 C3 10
+ 29 01 00 00 01 00 02 00 E3
+ 29 01 00 00 01 00 02 C3 10
+ 29 01 00 00 01 00 02 00 80
+ 29 01 00 00 01 00 0D CC 02 03 06 07
+ 08 09 0A 18 22
+ 22 22 22
+ 29 01 00 00 01 00 02 00 90
+ 29 01 00 00 01 00 0D CC 03 02 09 08
+ 07 06 19 0A 22
+ 22 22 22
+ 29 01 00 00 01 00 02 00 A0
+ 29 01 00 00 01 00 10 CC 1A 1B 1C 1D
+ 1E 1F 18 19 20
+ 21 04 14 15 0A
+ 22
+ 29 01 00 00 01 00 02 00 B0
+ 29 01 00 00 01 00 06 CC 22 22 22 22 22
+ 29 01 00 00 01 00 02 00 80
+ 29 01 00 00 01 00 09 CB 00 00 00 00 00
+ 00 00 00
+ 29 01 00 00 01 00 02 00 90
+ 29 01 00 00 01 00 10 CB 00 00 00 00 00
+ 00 00 00 00 00 00
+ 00 00 00 00
+ 29 01 00 00 01 00 02 00 A0
+ 29 01 00 00 01 00 10 CB 00 00 00 00 00
+ 00 00 00 00 00 00
+ 00 00 00 00
+ 29 01 00 00 01 00 02 00 B0
+ 29 01 00 00 01 00 03 CB 00 00
+ 29 01 00 00 01 00 02 00 C0
+ 29 01 00 00 01 00 10 CB 05 05 05 05 05
+ 05 05 05 00 00 00
+ 00 05 05 05
+ 29 01 00 00 01 00 02 00 D0
+ 29 01 00 00 01 00 10 CB 00 00 00 05 05
+ 05 05 05 00 00 05
+ 00 00 00 00
+ 29 01 00 00 01 00 02 00 E0
+ 29 01 00 00 01 00 03 CB 00 00
+ 29 01 00 00 01 00 02 00 F0
+ 29 01 00 00 01 00 09 CB 0F 00 00 3F 00
+ C0 00 00
+ 29 01 00 00 01 00 02 00 80
+ 29 01 00 00 01 00 10 CD 22 22 22 22 01
+ 06 04 08 07 18 17
+ 05 03 1A 22
+ 29 01 00 00 01 00 02 00 90
+ 29 01 00 00 01 00 04 CD 0F 0E 0D
+ 29 01 00 00 01 00 02 00 A0
+ 29 01 00 00 01 00 10 CD 22 02 03 05 07
+ 08 18 17 04 06 1A
+ 22 22 22 22
+ 29 01 00 00 01 00 02 00 B0
+ 29 01 00 00 01 00 04 CD 0F 0E 0D
+ 29 01 00 00 01 00 02 00 81
+ 29 01 00 00 01 00 0D F3 10 82 C0 42 80
+ C0 10 82 C0 42 80
+ C0
+ 29 01 00 00 01 00 02 00 90
+ 29 01 00 00 01 00 05 CF FF 00 FE 00
+ 29 01 00 00 01 00 02 00 94
+ 29 01 00 00 01 00 05 CF 00 00 10 20
+ 29 01 00 00 01 00 02 00 A4
+ 29 01 00 00 01 00 05 CF 00 07 01 80
+ 29 01 00 00 01 00 02 00 D0
+ 29 01 00 00 01 00 02 CF 08
+ 29 01 00 00 01 00 02 00 80
+ 29 01 00 00 01 00 0A CE 25 00 78 00 78
+ FF 00 20 05
+ 29 01 00 00 01 00 02 00 90
+ 29 01 00 00 01 00 09 CE 00 5C 0E 00 00
+ 5C 00 75
+ 29 01 00 00 01 00 02 00 B0
+ 29 01 00 00 01 00 07 CE 00 00 60 60 00
+ 60
+ 29 01 00 00 01 00 02 00 C0
+ 29 01 00 00 01 00 03 F4 93 36
+ 29 01 00 00 01 00 02 00 00
+ 29 01 00 00 01 00 19 E1 00 07 18 2B 37
+ 42 55 64 6B 73 7D
+ 87 70 67 64 5D 4F
+ 44 35 2C 25 18 09
+ 07
+ 29 01 00 00 01 00 02 00 00
+ 29 01 00 00 01 00 19 E2 00 07 18 2B 37
+ 42 55 64 6B 73 7D
+ 87 70 67 64 5D 4F
+ 44 35 2C 25 18 09
+ 07
+ 29 01 00 00 01 00 02 00 80
+ 29 01 00 00 01 00 0B C5 00 C1 DD C4 14
+ 1E 00 55 50 00
+ 29 01 00 00 01 00 02 00 90
+ 29 01 00 00 01 00 0B C5 55 1E 14 00 88
+ 10 4B 3C 55 50
+ 29 01 00 00 01 00 02 00 00
+ 29 01 00 00 01 00 03 D8 31 31
+ 29 01 00 00 01 00 02 00 88
+ 29 01 00 00 01 00 03 C3 33 33
+ 29 01 00 00 01 00 02 00 98
+ 29 01 00 00 01 00 03 C3 33 33
+ 29 01 00 00 01 00 02 00 80
+ 29 01 00 00 01 00 02 C4 41
+ 29 01 00 00 01 00 02 00 94
+ 29 01 00 00 01 00 02 C5 48
+ 29 01 00 00 01 00 02 00 C3
+ 29 01 00 00 01 00 02 F5 26
+ 29 01 00 00 01 00 02 00 C7
+ 29 01 00 00 01 00 02 F5 26
+ 29 01 00 00 01 00 02 00 D3
+ 29 01 00 00 01 00 02 F5 26
+ 29 01 00 00 01 00 02 00 D7
+ 29 01 00 00 01 00 02 F5 26
+ 29 01 00 00 01 00 02 00 95
+ 29 01 00 00 01 00 02 F5 26
+ 29 01 00 00 01 00 02 00 98
+ 29 01 00 00 01 00 02 F5 26
+ 29 01 00 00 01 00 02 00 B1
+ 29 01 00 00 01 00 02 F5 21
+ 29 01 00 00 01 00 02 00 87
+ 29 01 00 00 01 00 03 C3 33 33
+ 29 01 00 00 01 00 02 00 97
+ 29 01 00 00 01 00 03 C3 33 33
+ 29 01 00 00 01 00 02 00 83
+ 29 01 00 00 01 00 02 C3 44
+ 29 01 00 00 01 00 02 00 93
+ 29 01 00 00 01 00 02 C3 44
+ 29 01 00 00 01 00 02 00 81
+ 29 01 00 00 01 00 02 C3 33
+ 29 01 00 00 01 00 02 00 91
+ 29 01 00 00 01 00 02 C3 33
+ 29 01 00 00 01 00 02 00 81
+ 29 01 00 00 01 00 02 CF 04
+ 29 01 00 00 01 00 02 00 84
+ 29 01 00 00 01 00 02 CF 04
+ 29 01 00 00 01 00 02 00 81
+ 29 01 00 00 01 00 02 C4 C0
+ 29 01 00 00 01 00 02 00 8D
+ 29 01 00 00 01 00 02 F5 21
+ 29 01 00 00 01 00 02 00 8C
+ 29 01 00 00 01 00 02 F5 15
+
+
+ 29 01 00 00 01 00 02 00 DA
+ 29 01 00 00 01 00 02 CF 16
+ 29 01 00 00 01 00 02 00 80
+ 29 01 00 00 01 00 02 CE 05
+ 29 01 00 00 01 00 02 00 C1
+ 29 01 00 00 01 00 02 C0 11
+ 05 01 00 00 96 00 02 11 00
+ 05 01 00 00 23 00 02 29 00];
+
+ qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx83112a-auo-1080p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx83112a-auo-1080p-video.dtsi
new file mode 100644
index 0000000..64e1b52
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx83112a-auo-1080p-video.dtsi
@@ -0,0 +1,165 @@
+/* Copyright (C) 2017 Tcl Corporation Limited */
+/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+&mdss_mdp {
+ dsi_hx83112a_auo_1080_video: qcom,mdss_dsi_hx83112a_auo_1080p_video {
+ qcom,mdss-dsi-panel-name = "hx83112a auo 1080p video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <1>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-init-delay-us = <50000>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>;
+ qcom,mdss-pan-physical-width-dimension = <65>;
+ qcom,mdss-pan-physical-height-dimension = <115>;
+ qcom,mdss-dsi-dma-schedule-line = <10>;
+ qcom,mdss-dsi-panel-hdr-enabled; //for test
+ qcom,mdss-dsi-panel-hdr-color-primaries = <15400 16350 33300 16650
+ 11250 35850 6950 2750>; //for test
+ qcom,mdss-dsi-panel-peak-brightness = <3500000>; //for test
+ qcom,mdss-dsi-panel-blackness-level = <350>; //for test
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2340>;
+ qcom,mdss-dsi-h-front-porch = <28>;
+ qcom,mdss-dsi-h-back-porch = <8>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <5>;
+ qcom,mdss-dsi-v-front-porch = <27>;
+ qcom,mdss-dsi-v-pulse-width = <5>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 04 B9 83 11 2A
+ 39 01 00 00 00 00 09 B1 08 28 28 83 83 4C 4F
+ 33
+ 39 01 00 00 00 00 0F B2 00 02 00 90 24 00 08
+ 19 EA 11 11 00 11 A3
+ 39 01 00 00 00 00 1C B4 58 68 58 68 0F EF 0B
+ C0 0B C0 0B C0 00 FF 00 FF 00 00 14 15 00
+ 29 11 07 12 00 29
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 0A B4 00 12 12 11 88 12 12
+ 00 53
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 02 BD 03
+ 39 01 00 00 00 00 3A C1 FF FE FB F8 F4 F1 ED
+ E6 E2 DE DB D6 D3 CF CA C6 C2 BE B9 B0 A7
+ 9E 96 8D 84 7C 74 6B 62 5A 51 49 41 39 31
+ 29 21 19 12 0A 06 05 02 01 00 00 C9 B3 08
+ 0E F2 E1 59 F4 22 AD 40
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 3A C1 FF FE FB F8 F4 F1 ED
+ E6 E2 DE DB D6 D3 CF CA C6 C2 BE B9 B0 A7
+ 9E 96 8D 84 7C 74 6B 62 5A 51 49 41 39 31
+ 29 21 19 12 0A 06 05 02 01 00 00 C9 B3 08
+ 0E F2 E1 59 F4 22 AD 40
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 3A C1 FF FE FB F8 F4 F1 ED
+ E6 E2 DE DB D6 D3 CF CA C6 C2 BE B9 B0 A7
+ 9E 96 8D 84 7C 74 6B 62 5A 51 49 41 39 31
+ 29 21 19 12 0A 06 05 02 01 00 00 C9 B3 08
+ 0E F2 E1 59 F4 22 AD 40
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 02 C1 01
+ 39 01 00 00 00 00 07 C7 70 00 04 E0 33 00
+ 39 01 00 00 00 00 02 CC 08
+ 39 01 00 00 00 00 03 D2 2B 2B
+ 39 01 00 00 00 00 32 D3 80 00 00 00 00 01 00
+ 08 08 03 03 22 18 07 07 07 07 32 10 06 00
+ 06 32 10 07 00 07 32 19 31 09 31 00 00 05
+ 00 00 00 00 08 09 30 00 00 00 06 0D 00 0F
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 09 D3 00 00 19 10 00 0A 00
+ 81
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 31 D5 18 18 18 18 18 18 18
+ 18 C0 C0 18 18 19 19 18 18 40 40 18 18 18
+ 18 3F 3F 28 28 24 24 02 03 02 03 00 01 00
+ 01 31 31 31 31 30 30 30 30 2F 2F 2F 2F
+ 39 01 00 00 00 00 31 D6 18 18 18 18 18 18 18
+ 18 40 40 18 18 18 18 19 19 40 40 18 18 18
+ 18 3F 3F 24 24 28 28 01 00 01 00 03 02 03
+ 02 31 31 31 31 30 30 30 30 2F 2F 2F 2F
+ 39 01 00 00 00 00 19 D8 AA EA AA AA AA AA AA
+ EA AA AA AA AA AA EA AB AA AA AA AA EA AB
+ AA AA AA
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 19 D8 AA 2E 28 00 00 00 AA
+ 2E 28 00 00 00 AA EE AA AA AA AA AA EE AA
+ AA AA AA
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 0D D8 AA FF FF FF FF FF AA
+ FF FF FF FF FF
+ 39 01 00 00 00 00 02 BD 03
+ 39 01 00 00 00 00 19 D8 AA AA EA AA AA AA AA
+ AA EA AA AA AA AA FF FF FF FF FF AA FF FF
+ FF FF FF
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 18 E7 0E 0E 1E 65 1C 65 00
+ 50 20 20 00 00 02 02 02 05 14 14 32 B9 23
+ B9 08
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 09 E7 02 00 A8 01 A8 0D A4
+ 0E
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 1E E7 00 00 08 00 01 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 04 00 00 00 00 02 00
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 02 E9 C3
+ 39 01 00 00 00 00 03 CB D1 D6
+ 39 01 00 00 00 00 02 E9 3F
+ 39 01 00 00 00 00 02 E9 C6
+ 39 01 00 00 00 00 02 BF 37
+ 39 01 00 00 00 00 02 E9 3F
+ 05 01 00 00 96 00 02 11 00
+ 05 01 00 00 32 00 02 29 00];
+
+ qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi
new file mode 100755
index 0000000..9dc1a26
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx83112a-truly-singlemipi-fhd-video.dtsi
@@ -0,0 +1,151 @@
+&mdss_mdp {
+ dsi_hx83112a_truly_video: qcom,mdss_dsi_hx83112a_truly_video {
+ qcom,mdss-dsi-panel-name =
+ "hx83112a video mode dsi truly panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <65>;
+ qcom,mdss-pan-physical-height-dimension = <129>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <42>;
+ qcom,mdss-dsi-h-back-porch = <42>;
+ qcom,mdss-dsi-h-pulse-width = <10>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <15>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <3>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 04 B9 83 11 2A
+ 39 01 00 00 00 00 09 B1 08 29 29 00 00 4F 54
+ 33
+ 39 01 00 00 00 00 11 B2 00 02 00 80 70 00 08
+ 26 FC 01 00 03 15 A3 87 09
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 03 D2 2C 2C
+ 39 01 00 00 00 00 1C B4 01 CE 01 CE 01 CE 0A
+ CE 0A CE 0A CE 00 FF 00 FF 00 00 22 23 00
+ 28 0A 13 14 00 8A
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 0A B4 00 92 12 22 88 12 12
+ 00 53
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 04 B6 82 82 E3
+ 39 01 00 00 00 00 02 CC 08
+ 39 01 00 00 00 00 2B D3 40 00 00 00 00 01 01
+ 0A 0A 07 07 00 08 09 09 09 09 32 10 09 00
+ 09 32 21 0A 00 0A 32 10 08 00 00 00 00 00
+ 00 00 00 00 0B 08 82
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 09 D3 00 00 19 00 00 0A 00
+ 81
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 31 D5 18 18 18 18 18 18 18
+ 18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0
+ 18 40 40 01 00 07 06 05 04 03 02 21 20 18
+ 18 19 19 18 18 03 03 18 18 18 18 18 18
+ 39 01 00 00 00 00 31 D6 18 18 18 18 18 18 18
+ 18 31 31 30 30 2F 2F 31 31 30 30 2F 2F C0
+ 18 40 40 02 03 04 05 06 07 00 01 20 21 18
+ 18 18 18 19 19 20 20 18 18 18 18 18 18
+ 39 01 00 00 00 00 19 D8 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA
+ AA AA AA AA AA AA AA AA AA AA AA AA AA AA
+ AA AA AA
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 0D D8 AF FF FA AA BA AA AA
+ FF FA AA BA AA
+ 39 01 00 00 00 00 02 BD 03
+ 39 01 00 00 00 00 19 D8 AA AA AA AA AA AA AA
+ AA AA AA AA AA AA AA AA AA AA AA AA AA AA
+ AA AA AA
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 18 E7 0E 0E 1E 6A 1D 6A 00
+ 32 02 02 00 00 02 02 02 05 14 14 32 B9 23
+ B9 08
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 0A E7 02 00 98 01 9A 0D A8
+ 0E 01
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 1E E7 00 00 08 00 01 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 04 00 00 00 00 02 00
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 02 C1 01
+ 39 01 00 00 00 00 02 BD 01
+ 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
+ C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
+ 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
+ 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
+ C6 B8 9C 37 43 3D E5 00
+ 39 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
+ C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
+ 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
+ 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
+ C6 B8 9C 37 43 3D E5 00
+ 39 01 00 00 00 00 02 BD 03
+ 39 01 00 00 00 00 3A C1 FF F7 F0 E9 E2 DB D4
+ C6 BF B8 B1 AB A5 9F 99 94 8E 8A 85 7C 74
+ 6C 65 5F 58 52 4B 47 42 3C 37 31 2C 27 22
+ 1C 18 12 0D 08 05 04 02 01 00 27 B9 BE 54
+ C6 B8 9C 37 43 3D E5 00
+ 39 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 02 E9 C3
+ 39 01 00 00 00 00 03 CB 92 01
+ 39 01 00 00 00 00 02 E9 3F
+ 39 01 00 00 00 00 07 C7 70 00 04 E0 33 00
+ 39 01 00 00 00 00 03 51 0F FF
+ 39 01 00 00 00 00 02 53 24
+ 39 01 00 00 00 00 02 55 00
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 96 00 02 11 00
+ 05 01 00 00 32 00 02 29 00];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx8394d-720p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx8394d-720p-video.dtsi
new file mode 100755
index 0000000..6de6c6c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx8394d-720p-video.dtsi
@@ -0,0 +1,87 @@
+&mdss_mdp {
+ dsi_hx8394d_720_vid: qcom,mdss_dsi_hx8394d_720p_video {
+ qcom,mdss-dsi-panel-name = "hx8394d 720p video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <52>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <24>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <20>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 04 b9 ff 83 94
+ 39 01 00 00 00 00 03 ba 33 83
+ 39 01 00 00 00 00 10 b1 6c 12 12
+ 37 04 11 f1 80 ec 94 23 80 c0
+ d2 18
+ 39 01 00 00 00 00 0c b2 00 64 0e
+ 0d 32 23 08 08 1c 4d 00
+ 39 01 00 00 00 00 0d b4 00 ff 03
+ 50 03 50 03 50 01 6a 01 6a
+ 39 01 00 00 00 00 02 bc 07
+ 39 01 00 00 00 00 04 bf 41 0e 01
+ 39 01 00 00 00 00 1f d3 00 07 00
+ 00 00 10 00 32 10 05 00 00 32
+ 10 00 00 00 32 10 00 00 00 36
+ 03 09 09 37 00 00 37
+ 39 01 00 00 00 00 2d d5 02 03 00
+ 01 06 07 04 05 20 21 22 23 18
+ 18 18 18 18 18 18 18 18 18 18
+ 18 18 18 18 18 18 18 18 18 18
+ 18 18 18 18 18 24 25 18 18 19
+ 19
+ 39 01 00 00 00 00 2d d6 05 04 07
+ 06 01 00 03 02 23 22 21 20 18
+ 18 18 18 18 18 58 58 18 18 18
+ 18 18 18 18 18 18 18 18 18 18
+ 18 18 18 18 18 25 24 19 19 18
+ 18
+ 39 01 00 00 00 00 02 cc 09
+ 39 01 00 00 00 00 03 c0 30 14
+ 39 01 00 00 00 00 05 c7 00 c0 40 c0
+ 39 01 00 00 00 00 03 b6 43 43
+ 05 01 00 00 c8 00 02 11 00
+ 05 01 00 00 0a 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00
+ 05 01 00 00 00 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <1>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings = [
+ 79 1a 12 00 3e 42
+ 16 1e 15 03 04 00
+ ];
+ qcom,mdss-dsi-t-clk-post = <0x04>;
+ qcom,mdss-dsi-t-clk-pre = <0x1b>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>;
+ qcom,mdss-pan-physical-width-dimension = <59>;
+ qcom,mdss-pan-physical-height-dimension = <104>;
+
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx8394f-720p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx8394f-720p-video.dtsi
new file mode 100755
index 0000000..9a10e0c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx8394f-720p-video.dtsi
@@ -0,0 +1,121 @@
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------
+ */
+&mdss_mdp {
+ dsi_hx8394f_720p_video: qcom,mdss_dsi_hx8394f_720p_video {
+ qcom,mdss-dsi-panel-name = "hx8394f 720p video mode dsi panel";
+ qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-destination = "display_1";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <16>;
+ qcom,mdss-dsi-h-back-porch = <16>;
+ qcom,mdss-dsi-h-pulse-width = <10>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <12>;
+ qcom,mdss-dsi-v-front-porch = <15>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-on-command = [39 01 00 00 00 00 04 B9 FF 83 94
+ 39 01 00 00 00 00 07
+ BA 63 03 68 6B B2 C0
+ 39 01 00 00 00 00 0B
+ B1 50 12 72 09 33 54 B1 31 6B 2F
+ 39 01 00 00 00 00 07
+ B2 00 80 64 0E 0D 2F
+ 39 01 00 00 00 00 16
+ B4 73 74 73 74 73 74 01 0C 86 75
+ 00 3F 73 74 73 74 73 74 01 0C 86
+ 39 01 00 00 00 00 22
+ D3 00 00 07 07 40 07 10 00 08 10
+ 08 00 08 54 15 0E 05 0E 02 15 06
+ 05 06 47 44 0A 0A 4B 10 07 07 0E
+ 40
+ 39 01 00 00 00 00 2D
+ D5 1A 1A 1B 1B 00 01 02 03 04 05
+ 06 07 08 09 0A 0B 24 25 18 18 26
+ 27 18 18 18 18 18 18 18 18 18 18
+ 18 18 18 18 18 18 20 21 18 18 18
+ 18
+ 39 01 00 00 00 00 2D
+ D6 1A 1A 1B 1B 0B 0A 09 08 07 06
+ 05 04 03 02 01 00 21 20 18 18 27
+ 26 18 18 18 18 18 18 18 18 18 18
+ 18 18 18 18 18 18 25 24 18 18 18
+ 18
+ 39 01 00 00 00 00 3B
+ E0 00 0C 19 20 23 26 29 28 51 61
+ 70 6F 76 86 89 8D 99 9A 95 A1 B0
+ 57 55 58 5C 5e 64 6B 7F 00 0C 19
+ 20 23 26 29 28 51 61 70 6F 76 86
+ 89 8D 99 9A 95 A1 B0 57 55 58 5C
+ 5E 64 6B 7F
+ 39 01 00 00 00 00 03 C0 1F 31
+ 15 01 00 00 00 00 02 CC 0B
+ 15 01 00 00 00 00 02 D4 02
+ 15 01 00 00 00 00 02 BD 02
+ 39 01 00 00 00 00 0D
+ D8 FF FF FF FF FF FF FF FF FF FF
+ FF FF
+ 15 01 00 00 00 00 02 BD 00
+ 15 01 00 00 00 00 02 BD 01
+ 15 01 00 00 00 00 02 B1 00
+ 15 01 00 00 00 00 02 BD 00
+ 39 01 00 00 00 00 08
+ BF 40 81 50 00 1A FC 01
+ 39 01 00 00 00 00 03 B6 7D 7D
+ 05 01 00 00 78 00 02 11 00
+ 39 01 00 00 00 00 0D
+ B2 00 80 64 0E 0D 2F 00 00 00 00
+ C0 18
+ 05 01 00 00 14 00 02 29 00];
+
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <1>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings
+ = [72 16 0e 00 38 3c 12 1a 10 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x04>;
+ qcom,mdss-dsi-t-clk-pre = <0x18>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 01 D9
+ 06 01 00 01 05 00 01 09
+ 06 01 00 01 05 00 01 45];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-read-length = <4 4 3>;
+ qcom,mdss-dsi-panel-status-valid-params = <1 3 2>;
+ qcom,mdss-dsi-panel-status-value =
+ <0x80 0x80 0x73 0x04 0x05 0x0f>,
+ <0x80 0x80 0x73 0x04 0x05 0x1e>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx8399c-fhd-plus-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx8399c-fhd-plus-video.dtsi
new file mode 100755
index 0000000..1a3f598
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx8399c-fhd-plus-video.dtsi
@@ -0,0 +1,120 @@
+&mdss_mdp {
+ dsi_hx8399c_truly_vid: qcom,mdss_dsi_hx8399_truly_fhd_video {
+ qcom,mdss-dsi-panel-name =
+ "hx8399c video mode dsi truly panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <42>;
+ qcom,mdss-dsi-h-back-porch = <42>;
+ qcom,mdss-dsi-h-pulse-width = <10>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <15>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <3>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-pan-physical-width-dimension = <65>;
+ qcom,mdss-pan-physical-height-dimension = <129>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 04
+ b9 ff 83 99
+ 39 01 00 00 00 00 02
+ d2 88
+ 39 01 00 00 00 00 0c
+ b1 02 04 72 92 01
+ 32 aa 11 11 52 57
+ 39 01 00 00 00 00 10
+ b2 00 80 80 cc 05 07 5a
+ 11 10 10 00 1e 70 03 d4
+ 39 01 00 00 00 00 2d
+ b4 00 ff 59 59 01 ab 00
+ 00 09 00 03 05 00 28 03
+ 0b 0d 21 03 02 00 0c a3
+ 80 59 59 02 ab 00 00 09
+ 00 03 05 00 28 03 0b 0d
+ 02 00 0c a3 01
+ 39 01 00 00 05 00 22
+ d3 00 0c 03 03 00 00 10
+ 10 00 00 03 00 03 00 08
+ 78 08 78 00 00 00 00 00
+ 24 02 05 05 03 00 00 00
+ 05 40
+ 39 01 00 00 05 00 21
+ d5 20 20 19 19 18 18 02
+ 03 00 01 24 24 18 18 18
+ 18 24 24 00 00 00 00 00
+ 00 00 00 2f 2f 30 30 31
+ 31
+ 39 01 00 00 05 00 21
+ d6 24 24 18 18 19 19 01
+ 00 03 02 24 24 18 18 18
+ 18 20 20 40 40 40 40 40
+ 40 40 40 2f 2f 30 30 31
+ 31
+ 39 01 00 00 00 00 02
+ bd 00
+ 39 01 00 00 00 00 11
+ d8 aa aa aa aa aa aa aa
+ aa aa ba aa aa aa ba aa
+ aa
+ 39 01 00 00 00 00 02
+ bd 01
+ 39 01 00 00 00 00 11
+ d8 00 00 00 00 00 00 00
+ 00 82 ea aa aa 82 ea aa
+ aa
+ 39 01 00 00 00 00 02
+ bd 02
+ 39 01 00 00 00 00 09
+ d8 ff ff c0 3f ff ff c0
+ 3f
+ 39 01 00 00 00 00 02
+ bd 00
+ 39 01 00 00 05 00 37
+ e0 01 21 31 2d 66 6f 7b
+ 75 7a 81 86 89 8c 90 95
+ 97 9a a1 a2 aa 9e ad b0
+ 5b 57 63 7a 01 21 31 2d
+ 66 6f 7b 75 7a 81 86 89
+ 8c 90 95 97 9a a1 a2 aa
+ 9e ad b0 5b 57 63 7a
+ 39 01 00 00 00 00 03
+ b6 7e 7e
+ 39 01 00 00 00 00 02
+ cc 08
+ 05 01 00 00 96 00 02 11 00
+ 05 01 00 00 32 00 02 29 00];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-t-clk-post = <0x0e>;
+ qcom,mdss-dsi-t-clk-pre = <0x31>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx8399c-hd-plus-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx8399c-hd-plus-video.dtsi
new file mode 100755
index 0000000..00766ed
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-hx8399c-hd-plus-video.dtsi
@@ -0,0 +1,123 @@
+&mdss_mdp {
+ dsi_hx8399c_hd_vid: qcom,mdss_dsi_hx8399c_hd_video {
+ qcom,mdss-dsi-panel-name =
+ "hx8399c video mode dsi hd panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1440>;
+ qcom,mdss-dsi-h-front-porch = <48>;
+ qcom,mdss-dsi-h-back-porch = <48>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <40>;
+ qcom,mdss-dsi-v-front-porch = <36>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 04
+ b9 ff 83 99
+ 39 01 00 00 00 00 02
+ d2 88
+ 39 01 00 00 00 00 0c
+ b1 02 04 72 92 01
+ 32 aa 11 11 52 57
+ 39 01 00 00 00 00 10
+ b2 00 80 80 cc 05 07 5a
+ 11 10 10 00 1e 70 03 d4
+ 39 01 00 00 00 00 2d
+ b4 00 ff 59 59 01 ab 00
+ 00 09 00 03 05 00 28 03
+ 0b 0d 21 03 02 00 0c a3
+ 80 59 59 02 ab 00 00 09
+ 00 03 05 00 28 03 0b 0d
+ 02 00 0c a3 01
+ 39 01 00 00 05 00 22
+ d3 00 0c 03 03 00 00 10
+ 10 00 00 03 00 03 00 08
+ 78 08 78 00 00 00 00 00
+ 24 02 05 05 03 00 00 00
+ 05 40
+ 39 01 00 00 05 00 21
+ d5 20 20 19 19 18 18 02
+ 03 00 01 24 24 18 18 18
+ 18 24 24 00 00 00 00 00
+ 00 00 00 2f 2f 30 30 31
+ 31
+ 39 01 00 00 05 00 21
+ d6 24 24 18 18 19 19 01
+ 00 03 02 24 24 18 18 18
+ 18 20 20 40 40 40 40 40
+ 40 40 40 2f 2f 30 30 31
+ 31
+ 39 01 00 00 00 00 02
+ bd 00
+ 39 01 00 00 00 00 11
+ d8 aa aa aa aa aa aa aa
+ aa aa ba aa aa aa ba aa
+ aa
+ 39 01 00 00 00 00 02
+ bd 01
+ 39 01 00 00 00 00 11
+ d8 00 00 00 00 00 00 00
+ 00 82 ea aa aa 82 ea aa
+ aa
+ 39 01 00 00 00 00 02
+ bd 02
+ 39 01 00 00 00 00 09
+ d8 ff ff c0 3f ff ff c0
+ 3f
+ 39 01 00 00 00 00 02
+ bd 00
+ 39 01 00 00 05 00 37
+ e0 01 21 31 2d 66 6f 7b
+ 75 7a 81 86 89 8c 90 95
+ 97 9a a1 a2 aa 9e ad b0
+ 5b 57 63 7a 01 21 31 2d
+ 66 6f 7b 75 7a 81 86 89
+ 8c 90 95 97 9a a1 a2 aa
+ 9e ad b0 5b 57 63 7a
+ 39 01 00 00 00 00 03
+ b6 7e 7e
+ 39 01 00 00 00 00 02
+ cc 08
+ 39 01 00 00 00 00 02
+ 35 00
+ 39 01 00 00 00 00 02
+ dd 03
+ 05 01 00 00 96 00 02 11 00
+ 05 01 00 00 14 00 02 29 00];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings =
+ [7a 1a 12 00 3e 42 16 1e 14 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x0a>;
+ qcom,mdss-dsi-t-clk-pre = <0x1d>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-icn9706-720-1440p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-icn9706-720-1440p-video.dtsi
new file mode 100755
index 0000000..482e6a7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-icn9706-720-1440p-video.dtsi
@@ -0,0 +1,86 @@
+&mdss_mdp {
+ dsi_icn9706_720_1440_vid: qcom,mdss_dsi_icn9706_720_1440p_video {
+ qcom,mdss-dsi-panel-name =
+ "icn9706 720 1440p video mode dsi panel";
+ qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
+ qcom,mdss-dsi-panel-destination = "display_1";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1440>;
+ qcom,mdss-dsi-h-front-porch = <84>;
+ qcom,mdss-dsi-h-back-porch = <84>;
+ qcom,mdss-dsi-h-pulse-width = <24>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <20>;
+ qcom,mdss-dsi-v-front-porch = <24>;
+ qcom,mdss-dsi-v-pulse-width = <8>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <1>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings = [8b 1e 14 00 44 48 18 22 19
+ 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x04>;
+ qcom,mdss-dsi-t-clk-pre = <0x1c>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-on-command = [39 01 00 00 64 00 02 01 00
+ 39 01 00 00 00 00 03 f0 5a 5a
+ 39 01 00 00 00 00 03 f1 5a 5a
+ 39 01 00 00 00 00 03 f0 b4 4b
+ 39 01 00 00 00 00 03 b6 10 10
+ 39 01 00 00 00 00 15 b4 0a 08 12 10 0e 0c 00 00
+ 00 03 00 03 03 03 03 03 03 03 04 06
+ 39 01 00 00 00 00 15 b3 0b 09 13 11 0f 0d 00 00
+ 00 03 00 03 03 03 03 03 03 03 05 07
+ 39 01 00 00 00 00 0d b0 54 32 23 45 44 44 44 44
+ 60 01 60 01
+ 39 01 00 00 00 00 09 b1 32 84 02 83 15 01 57 01
+ 39 01 00 00 00 00 02 b2 33
+ 39 01 00 00 00 00 07 bd 54 14 6a 6a 20 19
+ 39 01 00 00 00 00 12 b7 01 01 09 11 0d 15 19 0d
+ 21 1d 00 00 20 00 02 ff 3c
+ 39 01 00 00 00 00 06 b8 23 01 30 34 53
+ 39 01 00 00 00 00 05 b9 a1 2c ff c4
+ 39 01 00 00 00 00 03 ba 88 23
+ 39 01 00 00 00 00 07 c1 16 16 04 0c 10 04
+ 39 01 00 00 00 00 03 c2 12 68
+ 39 01 00 00 00 00 04 c3 22 31 04
+ 39 01 00 00 00 00 06 c7 05 23 6b 41 00
+ 39 01 00 00 00 00 27 c8 7c 54 3d 2d 26 16 1b 08
+ 25 28 2d 4f 3e 48 3d 3d 35 25 06 7c 54 3d 2d
+ 26 16 1b 08 25 28 2d 4f 3e 48 3d 3d 35 25 06
+ 39 01 00 00 00 00 09 c6 00 00 68 00 00 60 36 00
+ 05 01 00 00 64 00 02 11 00
+ 05 01 00 00 32 00 02 29 00];
+
+ qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 32 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "bta_check";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 2>, <0 20>, <1 50>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-pan-physical-width-dimension = <63>;
+ qcom,mdss-pan-physical-height-dimension = <112>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-lgd-incell-sw49106-fhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-lgd-incell-sw49106-fhd-video.dtsi
new file mode 100755
index 0000000..1184a2e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-lgd-incell-sw49106-fhd-video.dtsi
@@ -0,0 +1,103 @@
+&mdss_mdp {
+ dsi_lgd_incell_sw49106_fhd_video:
+ qcom,mdss_dsi_lgd_incell_sw49106_fhd_video {
+ qcom,mdss-dsi-panel-name =
+ "lgd incell sw49106 fhd video";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <8>;
+ qcom,mdss-dsi-h-back-porch = <8>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <92>;
+ qcom,mdss-dsi-v-front-porch = <170>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings = [F8 3C 28 00 6E 72 2E
+ 40 30 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x02>;
+ qcom,mdss-dsi-t-clk-pre = <0x2D>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-on-command = [05 01 00 00 0B 00 02 35 00
+ 15 01 00 00 00 00 02 36 00
+ 15 01 00 00 00 00 02 51 FF
+ 15 01 00 00 00 00 02 53 24
+ 15 01 00 00 00 00 02 55 80
+ 39 01 00 00 00 00 02 B0 AC
+ 39 01 00 00 00 00 06 B1 46 00 80 14 85
+ 39 01 00 00 00 00 08 B3 05 08 14 00 1C 00 02
+ 39 01 00 00 00 00 10 B4 83 08 00 04 04 04 04 00
+ 00 00 00 00 00 00 00
+ 39 01 00 00 00 00 13 B5 03 1E 0B 02 29 00 00 00
+ 00 04 00 24 00 10 10 10 10 00
+ 39 01 00 00 00 00 0A B6 00 72 39 13 08 67 00 60 46
+ 39 01 00 00 00 00 05 B7 00 50 37 04
+ 39 01 00 00 00 00 0C B8 70 38 14 ED 08 04 00 01
+ 0A A0 00
+ 39 01 00 00 00 00 06 C0 8A 8F 18 C1 12
+ 39 01 00 00 00 00 07 C1 01 00 30 C2 C7 0F
+ 39 01 00 00 00 00 03 C2 2A 00
+ 39 01 00 00 00 00 07 C3 05 0E 0E 50 88 09
+ 39 01 00 00 00 00 04 C4 A2 E8 F4
+ 39 01 00 00 00 00 05 C5 C2 2A 4E 08
+ 39 01 00 00 00 00 03 C6 15 01
+ 39 01 00 00 00 00 07 CA 00 00 03 84 55 F5
+ 39 01 00 00 00 00 03 CB 3F A0
+ 39 01 00 00 00 00 09 CC F0 03 10 55 11 FC 34 34
+ 39 01 00 00 00 00 07 CD 11 50 50 90 00 F3
+ 39 01 00 00 00 00 07 CE A0 28 28 34 00 AB
+ 39 01 00 00 00 00 10 D0 10 1B 22 2A 35 42 4A 53 4D
+ 44 34 23 10 03 81
+ 39 01 00 00 00 00 10 D1 09 15 1C 25 31 3F 47 52 4F
+ 45 34 22 0E 01 83
+ 39 01 00 00 00 00 10 D2 10 1B 22 29 34 41 49 52 4E
+ 44 34 23 10 03 81
+ 39 01 00 00 00 00 10 D3 09 15 1C 24 30 3E 46 51 50
+ 45 34 22 0E 01 83
+ 39 01 00 00 00 00 10 D4 10 1B 22 2A 35 42 4A 53 4D
+ 44 34 23 10 03 81
+ 39 01 00 00 00 00 10 D5 09 15 1C 25 31 3F 47 52 4F
+ 45 34 22 0E 01 83
+ 39 01 00 00 00 00 0D E5 24 23 11 10 00 0A 08 06 04
+ 11 0E 23
+ 39 01 00 00 00 00 0D E6 24 23 11 10 01 0B 09 07 05
+ 11 0E 23
+ 39 01 00 00 00 00 07 E7 15 16 17 18 19 1A
+ 39 01 00 00 00 00 07 E8 1B 1C 1D 1E 1F 20
+ 39 01 00 00 00 00 05 ED 00 01 53 0C
+ 39 01 00 00 00 00 03 F0 B2 00
+ 39 01 00 00 00 00 05 F2 01 00 17 00
+ 39 01 00 00 64 00 07 F3 00 50 90 C9 00 01
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 05 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 64 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 400>, <0 400>, <1 400>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-post-init-delay = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi
new file mode 100755
index 0000000..f05fc5f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi
@@ -0,0 +1,93 @@
+&mdss_mdp {
+ dsi_dual_nt35597_cmd: qcom,mdss_dsi_nt35597_wqxga_cmd{
+ qcom,mdss-dsi-panel-name =
+ "Dual nt35597 cmd mode dsi panel without DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings = [cd 32 22 00 60 64 26 34 29 03
+ 04 00];
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <131>;
+ qcom,mdss-dsi-t-clk-post = <0x0d>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,ulps-enabled;
+ qcom,mdss-dsi-on-command = [15 01 00 00 10 00 02 ff 10
+ 15 01 00 00 10 00 02 fb 01
+ 15 01 00 00 10 00 02 ba 03
+ 15 01 00 00 10 00 02 e5 01
+ 15 01 00 00 10 00 02 35 00
+ 15 01 00 00 10 00 02 bb 10
+ 15 01 00 00 10 00 02 b0 03
+ 15 01 00 00 10 00 02 ff e0
+ 15 01 00 00 10 00 02 fb 01
+ 15 01 00 00 10 00 02 6b 3d
+ 15 01 00 00 10 00 02 6c 3d
+ 15 01 00 00 10 00 02 6d 3d
+ 15 01 00 00 10 00 02 6e 3d
+ 15 01 00 00 10 00 02 6f 3d
+ 15 01 00 00 10 00 02 35 02
+ 15 01 00 00 10 00 02 36 72
+ 15 01 00 00 10 00 02 37 10
+ 15 01 00 00 10 00 02 08 c0
+ 15 01 00 00 10 00 02 ff 24
+ 15 01 00 00 10 00 02 fb 01
+ 15 01 00 00 10 00 02 c6 06
+ 15 01 00 00 10 00 02 ff 10
+ 05 01 00 00 a0 00 02 11 00
+ 05 01 00 00 a0 00 02 29 00];
+
+ qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00
+ 05 01 00 00 3c 00 02 10 00];
+
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,config-select = <&dsi_dual_nt35597_cmd_config0>;
+
+ dsi_dual_nt35597_cmd_config0: config0 {
+ qcom,split-mode = "dualctl-split";
+ };
+
+ dsi_dual_nt35597_cmd_config1: config1 {
+ qcom,split-mode = "pingpong-split";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-dualmipi-wqxga-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-dualmipi-wqxga-video.dtsi
new file mode 100755
index 0000000..4059d72
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-dualmipi-wqxga-video.dtsi
@@ -0,0 +1,84 @@
+&mdss_mdp {
+ dsi_dual_nt35597_video: qcom,mdss_dsi_nt35597_wqxga_video {
+ qcom,mdss-dsi-panel-name = "Dual nt35597 video mode dsi
+ panel without DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0x3ff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 ba 03
+ 15 01 00 00 00 00 02 e5 01
+ 15 01 00 00 00 00 02 35 00
+ 15 01 00 00 00 00 02 bb 03
+ 15 01 00 00 00 00 02 b0 03
+ 39 01 00 00 00 00 06 3b 03 08 08 64 9a
+ 15 01 00 00 00 00 02 ff e0
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 6b 3d
+ 15 01 00 00 00 00 02 6c 3d
+ 15 01 00 00 00 00 02 6d 3d
+ 15 01 00 00 00 00 02 6e 3d
+ 15 01 00 00 00 00 02 6f 3d
+ 15 01 00 00 00 00 02 35 02
+ 15 01 00 00 00 00 02 36 72
+ 15 01 00 00 00 00 02 37 10
+ 15 01 00 00 00 00 02 08 c0
+ 15 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 32 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 0a 00 02 28 00
+ 05 01 00 00 3c 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings = [e2 36 24 00 66 6a 28 38 2a
+ 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x0d>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <131>;
+ qcom,mdss-dsi-min-refresh-rate = <55>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+
+ qcom,config-select = <&dsi_dual_nt35597_video_config0>;
+
+ dsi_dual_nt35597_video_config0: config0 {
+ qcom,split-mode = "dualctl-split";
+ };
+
+ dsi_dual_nt35597_video_config1: config1 {
+ qcom,split-mode = "pingpong-split";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi
new file mode 100755
index 0000000..8a05258
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi
@@ -0,0 +1,240 @@
+&mdss_mdp {
+ dsi_nt35597_truly_dsc_cmd: qcom,mdss_dsi_nt35597_dsc_cmd_truly {
+ qcom,mdss-dsi-panel-name =
+ "nt35597 cmd mode dsi truly panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <1>;
+ qcom,dsi-phy-num = <1>;
+ qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <131>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x1 0x1>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f ae
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6D
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c D8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 C0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x0(2 Port SDC)
+ * 0x01(1 PortA FBC)
+ * 0x02(MTK) 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+
+ qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi
new file mode 100755
index 0000000..2d888cb
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi
@@ -0,0 +1,226 @@
+&mdss_mdp {
+ dsi_nt35597_truly_dsc_video: qcom,mdss_dsi_nt35597_dsc_video_truly {
+ qcom,mdss-dsi-panel-name =
+ "nt35597 video mode dsi truly panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <1>;
+ qcom,dsi-phy-num = <1>;
+ qcom,dsi-select-clocks = "src_byte_clk1", "src_pixel_clk1";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <131>;
+ qcom,mdss-dsi-dma-schedule-line = <5>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f aE
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6d
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x00(2 Port SDC);
+ * 0x01(1 PortA FBC);
+ * 0x02(MTK); 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 39 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 03
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi
new file mode 100755
index 0000000..6c24158
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi
@@ -0,0 +1,230 @@
+&mdss_mdp {
+ dsi_dual_nt35597_truly_cmd: qcom,mdss_dsi_nt35597_truly_wqxga_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Dual nt35597 cmd mode dsi truly panel without DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <131>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,config-select = <&dsi_dual_nt35597_truly_cmd_config0>;
+ dsi_dual_nt35597_truly_cmd_config0: config0 {
+ qcom,split-mode = "dualctl-split";
+ };
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x1 0x1>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1E
+ 15 01 00 00 00 00 02 0B 73
+ 15 01 00 00 00 00 02 0C 73
+ 15 01 00 00 00 00 02 0E B0
+ 15 01 00 00 00 00 02 0F AE
+ 15 01 00 00 00 00 02 11 B8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5A 00
+ 15 01 00 00 00 00 02 5B 01
+ 15 01 00 00 00 00 02 5C 80
+ 15 01 00 00 00 00 02 5D 81
+ 15 01 00 00 00 00 02 5E 00
+ 15 01 00 00 00 00 02 5F 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1C
+ 15 01 00 00 00 00 02 01 0B
+ 15 01 00 00 00 00 02 02 0C
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0F
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8A
+ 15 01 00 00 00 00 02 0A 13
+ 15 01 00 00 00 00 02 0B 13
+ 15 01 00 00 00 00 02 0C 15
+ 15 01 00 00 00 00 02 0D 15
+ 15 01 00 00 00 00 02 0E 17
+ 15 01 00 00 00 00 02 0F 17
+ 15 01 00 00 00 00 02 10 1C
+ 15 01 00 00 00 00 02 11 0B
+ 15 01 00 00 00 00 02 12 0C
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0F
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8A
+ 15 01 00 00 00 00 02 1A 13
+ 15 01 00 00 00 00 02 1B 13
+ 15 01 00 00 00 00 02 1C 15
+ 15 01 00 00 00 00 02 1D 15
+ 15 01 00 00 00 00 02 1E 17
+ 15 01 00 00 00 00 02 1F 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6D
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 E0 00
+ 15 01 00 00 00 00 02 DC 21
+ 15 01 00 00 00 00 02 DD 22
+ 15 01 00 00 00 00 02 DE 07
+ 15 01 00 00 00 00 02 DF 07
+ 15 01 00 00 00 00 02 E3 6D
+ 15 01 00 00 00 00 02 E1 07
+ 15 01 00 00 00 00 02 E2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 D8
+ 15 01 00 00 00 00 02 2A 2A
+ /* CLK */
+ 15 01 00 00 00 00 02 4B 03
+ 15 01 00 00 00 00 02 4C 11
+ 15 01 00 00 00 00 02 4D 10
+ 15 01 00 00 00 00 02 4E 01
+ 15 01 00 00 00 00 02 4F 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5B 43
+ 15 01 00 00 00 00 02 5C 00
+ 15 01 00 00 00 00 02 5F 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7A 80
+ 15 01 00 00 00 00 02 7B 91
+ 15 01 00 00 00 00 02 7C D8
+ 15 01 00 00 00 00 02 7D 60
+ 15 01 00 00 00 00 02 7F 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 B3 C0
+ 15 01 00 00 00 00 02 B4 00
+ 15 01 00 00 00 00 02 B5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0A
+ 15 01 00 00 00 00 02 94 0A
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8A 00
+ 15 01 00 00 00 00 02 9B FF
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9D B0
+ 15 01 00 00 00 00 02 9F 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 EC 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3B 03 0A 0A
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 E5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 BB 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 FB 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-panel-timings = [cd 32 22 00 60
+ 64 26 34 29 03 04 00];
+ qcom,mdss-dsi-panel-timings-phy-v2 =
+ [23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 18 07 08 04 03 04 a0];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi
new file mode 100755
index 0000000..e0602a1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi
@@ -0,0 +1,217 @@
+&mdss_mdp {
+ dsi_dual_nt35597_truly_video: qcom,mdss_dsi_nt35597_wqxga_video_truly {
+ qcom,mdss-dsi-panel-name =
+ "Dual nt35597 video mode dsi truly panel without DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <131>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-underflow-color = <0x3ff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,config-select = <&dsi_dual_nt35597_truly_video_config0>;
+ dsi_dual_nt35597_truly_video_config0: config0 {
+ qcom,split-mode = "dualctl-split";
+ };
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1E
+ 15 01 00 00 00 00 02 0B 73
+ 15 01 00 00 00 00 02 0C 73
+ 15 01 00 00 00 00 02 0E B0
+ 15 01 00 00 00 00 02 0F AE
+ 15 01 00 00 00 00 02 11 B8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5A 00
+ 15 01 00 00 00 00 02 5B 01
+ 15 01 00 00 00 00 02 5C 80
+ 15 01 00 00 00 00 02 5D 81
+ 15 01 00 00 00 00 02 5E 00
+ 15 01 00 00 00 00 02 5F 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 FF 24
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 00 1C
+ 15 01 00 00 00 00 02 01 0B
+ 15 01 00 00 00 00 02 02 0C
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0F
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8A
+ 15 01 00 00 00 00 02 0A 13
+ 15 01 00 00 00 00 02 0B 13
+ 15 01 00 00 00 00 02 0C 15
+ 15 01 00 00 00 00 02 0D 15
+ 15 01 00 00 00 00 02 0E 17
+ 15 01 00 00 00 00 02 0F 17
+ 15 01 00 00 00 00 02 10 1C
+ 15 01 00 00 00 00 02 11 0B
+ 15 01 00 00 00 00 02 12 0C
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0F
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8A
+ 15 01 00 00 00 00 02 1A 13
+ 15 01 00 00 00 00 02 1B 13
+ 15 01 00 00 00 00 02 1C 15
+ 15 01 00 00 00 00 02 1D 15
+ 15 01 00 00 00 00 02 1E 17
+ 15 01 00 00 00 00 02 1F 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6D
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 E0 00
+ 15 01 00 00 00 00 02 DC 21
+ 15 01 00 00 00 00 02 DD 22
+ 15 01 00 00 00 00 02 DE 07
+ 15 01 00 00 00 00 02 DF 07
+ 15 01 00 00 00 00 02 E3 6D
+ 15 01 00 00 00 00 02 E1 07
+ 15 01 00 00 00 00 02 E2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 D8
+ 15 01 00 00 00 00 02 2A 2A
+ /* CLK */
+ 15 01 00 00 00 00 02 4B 03
+ 15 01 00 00 00 00 02 4C 11
+ 15 01 00 00 00 00 02 4D 10
+ 15 01 00 00 00 00 02 4E 01
+ 15 01 00 00 00 00 02 4F 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5B 43
+ 15 01 00 00 00 00 02 5C 00
+ 15 01 00 00 00 00 02 5F 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7A 80
+ 15 01 00 00 00 00 02 7B 91
+ 15 01 00 00 00 00 02 7C D8
+ 15 01 00 00 00 00 02 7D 60
+ 15 01 00 00 00 00 02 7F 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 B3 C0
+ 15 01 00 00 00 00 02 B4 00
+ 15 01 00 00 00 00 02 B5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0A
+ 15 01 00 00 00 00 02 94 0A
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8A 00
+ 15 01 00 00 00 00 02 9B FF
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9D B0
+ 15 01 00 00 00 00 02 9F 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 EC 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 FF 10
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3B 03 0A 0A
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 E5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 BB 03
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 FB 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-panel-timings = [e2 36 24 00 66
+ 6a 28 38 2a 03 04 00];
+ qcom,mdss-dsi-panel-timings-phy-v2 =
+ [23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 18 07 08 04 03 04 a0];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35695b-truly-fhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35695b-truly-fhd-cmd.dtsi
new file mode 100755
index 0000000..698c466
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35695b-truly-fhd-cmd.dtsi
@@ -0,0 +1,183 @@
+&mdss_mdp {
+ dsi_nt35695b_truly_fhd_cmd: qcom,mdss_dsi_nt35695b_truly_fhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "nt35695b truly fhd command mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,dsi-sec-ctrl-num = <1>;
+ qcom,dsi-sec-phy-num = <1>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-post-init-delay = <1>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <2>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command =
+ [15 01 00 00 10 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 03 55
+ 15 01 00 00 00 00 02 05 50
+ 15 01 00 00 00 00 02 06 a8
+ 15 01 00 00 00 00 02 07 ad
+ 15 01 00 00 00 00 02 08 0c
+ 15 01 00 00 00 00 02 0b aa
+ 15 01 00 00 00 00 02 0c aa
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f b3
+ 15 01 00 00 00 00 02 11 28
+ 15 01 00 00 00 00 02 12 10
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 4a
+ 15 01 00 00 00 00 02 15 12
+ 15 01 00 00 00 00 02 16 12
+ 15 01 00 00 00 00 02 30 01
+ 15 01 00 00 00 00 02 72 11
+ 15 01 00 00 00 00 02 58 82
+ 15 01 00 00 00 00 02 59 00
+ 15 01 00 00 00 00 02 5a 02
+ 15 01 00 00 00 00 02 5b 00
+ 15 01 00 00 00 00 02 5c 82
+ 15 01 00 00 00 00 02 5d 80
+ 15 01 00 00 00 00 02 5e 02
+ 15 01 00 00 00 00 02 5f 00
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 89
+ 15 01 00 00 00 00 02 04 8a
+ 15 01 00 00 00 00 02 05 0f
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 1c
+ 15 01 00 00 00 00 02 09 00
+ 15 01 00 00 00 00 02 0a 00
+ 15 01 00 00 00 00 02 0b 00
+ 15 01 00 00 00 00 02 0c 00
+ 15 01 00 00 00 00 02 0d 13
+ 15 01 00 00 00 00 02 0e 15
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 01
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 89
+ 15 01 00 00 00 00 02 14 8a
+ 15 01 00 00 00 00 02 15 0f
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 1c
+ 15 01 00 00 00 00 02 19 00
+ 15 01 00 00 00 00 02 1a 00
+ 15 01 00 00 00 00 02 1b 00
+ 15 01 00 00 00 00 02 1c 00
+ 15 01 00 00 00 00 02 1d 13
+ 15 01 00 00 00 00 02 1e 15
+ 15 01 00 00 00 00 02 1f 17
+ 15 01 00 00 00 00 02 20 00
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 55 25
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 93 06
+ 15 01 00 00 00 00 02 94 06
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b 0f
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ 15 01 00 00 00 00 02 b6 21
+ 15 01 00 00 00 00 02 b7 22
+ 15 01 00 00 00 00 02 b8 07
+ 15 01 00 00 00 00 02 b9 07
+ 15 01 00 00 00 00 02 ba 22
+ 15 01 00 00 00 00 02 bd 20
+ 15 01 00 00 00 00 02 be 07
+ 15 01 00 00 00 00 02 bf 07
+ 15 01 00 00 00 00 02 c1 6d
+ 15 01 00 00 00 00 02 c4 24
+ 15 01 00 00 00 00 02 e3 00
+ 15 01 00 00 00 00 02 ec 00
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 14
+ 00 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35695b-truly-fhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35695b-truly-fhd-video.dtsi
new file mode 100755
index 0000000..78ae48b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt35695b-truly-fhd-video.dtsi
@@ -0,0 +1,179 @@
+&mdss_mdp {
+ dsi_nt35695b_truly_fhd_video: qcom,mdss_dsi_nt35695b_truly_fhd_video {
+ qcom,mdss-dsi-panel-name =
+ "nt35695b truly fhd video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,dsi-sec-ctrl-num = <1>;
+ qcom,dsi-sec-phy-num = <1>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-post-init-delay = <1>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-v-back-porch = <2>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command =
+ [15 01 00 00 10 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 03 55
+ 15 01 00 00 00 00 02 05 50
+ 15 01 00 00 00 00 02 06 a8
+ 15 01 00 00 00 00 02 07 ad
+ 15 01 00 00 00 00 02 08 0c
+ 15 01 00 00 00 00 02 0b aa
+ 15 01 00 00 00 00 02 0c aa
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f b3
+ 15 01 00 00 00 00 02 11 28
+ 15 01 00 00 00 00 02 12 10
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 4a
+ 15 01 00 00 00 00 02 15 12
+ 15 01 00 00 00 00 02 16 12
+ 15 01 00 00 00 00 02 30 01
+ 15 01 00 00 00 00 02 72 11
+ 15 01 00 00 00 00 02 58 82
+ 15 01 00 00 00 00 02 59 00
+ 15 01 00 00 00 00 02 5a 02
+ 15 01 00 00 00 00 02 5b 00
+ 15 01 00 00 00 00 02 5c 82
+ 15 01 00 00 00 00 02 5d 80
+ 15 01 00 00 00 00 02 5e 02
+ 15 01 00 00 00 00 02 5f 00
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 89
+ 15 01 00 00 00 00 02 04 8a
+ 15 01 00 00 00 00 02 05 0f
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 1c
+ 15 01 00 00 00 00 02 09 00
+ 15 01 00 00 00 00 02 0a 00
+ 15 01 00 00 00 00 02 0b 00
+ 15 01 00 00 00 00 02 0c 00
+ 15 01 00 00 00 00 02 0d 13
+ 15 01 00 00 00 00 02 0e 15
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 01
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 89
+ 15 01 00 00 00 00 02 14 8a
+ 15 01 00 00 00 00 02 15 0f
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 1c
+ 15 01 00 00 00 00 02 19 00
+ 15 01 00 00 00 00 02 1a 00
+ 15 01 00 00 00 00 02 1b 00
+ 15 01 00 00 00 00 02 1c 00
+ 15 01 00 00 00 00 02 1d 13
+ 15 01 00 00 00 00 02 1e 15
+ 15 01 00 00 00 00 02 1f 17
+ 15 01 00 00 00 00 02 20 00
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 55 25
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 93 06
+ 15 01 00 00 00 00 02 94 06
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b 0f
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ 15 01 00 00 00 00 02 b6 21
+ 15 01 00 00 00 00 02 b7 22
+ 15 01 00 00 00 00 02 b8 07
+ 15 01 00 00 00 00 02 b9 07
+ 15 01 00 00 00 00 02 ba 22
+ 15 01 00 00 00 00 02 bd 20
+ 15 01 00 00 00 00 02 be 07
+ 15 01 00 00 00 00 02 bf 07
+ 15 01 00 00 00 00 02 c1 6d
+ 15 01 00 00 00 00 02 c4 24
+ 15 01 00 00 00 00 02 e3 00
+ 15 01 00 00 00 00 02 ec 00
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bb 03
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00
+ 14 00 02 28 00 05 01 00 00 78 00
+ 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36525-truly-hd-plus-vid.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36525-truly-hd-plus-vid.dtsi
new file mode 100755
index 0000000..366a916
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36525-truly-hd-plus-vid.dtsi
@@ -0,0 +1,304 @@
+&mdss_mdp {
+ dsi_nt36525_truly_video: qcom,mdss_dsi_nt36525_truly_video {
+ qcom,mdss-dsi-panel-name =
+ "nt36525 video mode dsi truly panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <65>;
+ qcom,mdss-pan-physical-height-dimension = <129>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1520>;
+ qcom,mdss-dsi-h-front-porch = <80>;
+ qcom,mdss-dsi-h-back-porch = <88>;
+ qcom,mdss-dsi-h-pulse-width = <20>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 05 A9
+ 15 01 00 00 00 00 02 07 73
+ 15 01 00 00 00 00 02 08 C1
+ 15 01 00 00 00 00 02 0E 87
+ 15 01 00 00 00 00 02 0F 55
+ 15 01 00 00 00 00 02 1F 00
+ 15 01 00 00 00 00 02 69 A9
+ 15 01 00 00 00 00 02 6D 33
+ 15 01 00 00 00 00 02 89 64
+ 15 01 00 00 00 00 02 8A 64
+ 15 01 00 00 00 00 02 8B 64
+ 15 01 00 00 00 00 02 8C 64
+ 15 01 00 00 00 00 02 95 EB
+ 15 01 00 00 00 00 02 96 EB
+ 15 01 00 00 00 00 02 FF 23
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 12 AB
+ 15 01 00 00 00 00 02 15 F5
+ 15 01 00 00 00 00 02 16 0B
+ 15 01 00 00 00 00 02 FF 24
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 02 05
+ 15 01 00 00 00 00 02 03 05
+ 15 01 00 00 00 00 02 04 9F
+ 15 01 00 00 00 00 02 05 9F
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+ 15 01 00 00 00 00 02 92 05
+ 15 01 00 00 00 00 02 93 F0
+ 15 01 00 00 00 00 02 99 0D
+ 15 01 00 00 00 00 02 9A 36
+ 15 01 00 00 00 00 02 9B 0C
+ 15 01 00 00 00 00 02 9C 9E
+ 15 01 00 00 00 00 02 FF 27
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 14 55
+ 15 01 00 00 00 00 02 FF 27
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 9E 00
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 FB 01
+ 29 01 00 00 00 00 11 B0 00 00 00 2E 00 65 00 8C 00 AA 00 C4 00 DA 00 ED
+ 29 01 00 00 00 00 11 B1 00 FE 01 36 01 5C 01 99 01 C3 02 03 02 33 02 34
+ 29 01 00 00 00 00 11 B2 02 64 02 98 02 C0 02 F1 03 10 03 47 03 53 03 64
+ 29 01 00 00 00 00 0D B3 03 76 03 8C 03 A6 03 C3 03 D9 03 FF
+ 29 01 00 00 00 00 11 B4 00 00 00 2E 00 65 00 8C 00 AA 00 C4 00 DA 00 ED
+ 29 01 00 00 00 00 11 B5 00 FE 01 36 01 5C 01 99 01 C3 02 03 02 33 02 34
+ 29 01 00 00 00 00 11 B6 02 64 02 98 02 C0 02 F1 03 10 03 47 03 53 03 64
+ 29 01 00 00 00 00 0D B7 03 76 03 8C 03 A6 03 C3 03 D9 03 FF
+ 29 01 00 00 00 00 11 B8 00 00 00 2E 00 65 00 8C 00 AA 00 C4 00 DA 00 ED
+ 29 01 00 00 00 00 11 B9 00 FE 01 36 01 5C 01 99 01 C3 02 03 02 33 02 34
+ 29 01 00 00 00 00 11 BA 02 64 02 98 02 C0 02 F1 03 10 03 47 03 53 03 64
+ 29 01 00 00 00 00 0D BB 03 76 03 8C 03 A6 03 C3 03 D9 03 FF
+ 15 01 00 00 00 00 02 FF 21
+ 15 01 00 00 00 00 02 FB 01
+ 29 01 00 00 00 00 11 B0 00 00 00 2E 00 65 00 8C 00 AA 00 C4 00 DA 00 ED
+ 29 01 00 00 00 00 11 B1 00 FE 01 36 01 5C 01 99 01 C3 02 03 02 33 02 34
+ 29 01 00 00 00 00 11 B2 02 64 02 98 02 C0 02 F1 03 10 03 47 03 53 03 64
+ 29 01 00 00 00 00 0D B3 03 76 03 8C 03 A6 03 C3 03 D9 03 FF
+ 29 01 00 00 00 00 11 B4 00 00 00 2E 00 65 00 8C 00 AA 00 C4 00 DA 00 ED
+ 29 01 00 00 00 00 11 B5 00 FE 01 36 01 5C 01 99 01 C3 02 03 02 33 02 34
+ 29 01 00 00 00 00 11 B6 02 64 02 98 02 C0 02 F1 03 10 03 47 03 53 03 64
+ 29 01 00 00 00 00 0D B7 03 76 03 8C 03 A6 03 C3 03 D9 03 FF
+ 29 01 00 00 00 00 11 B8 00 00 00 2E 00 65 00 8C 00 AA 00 C4 00 DA 00 ED
+ 29 01 00 00 00 00 11 B9 00 FE 01 36 01 5C 01 99 01 C3 02 03 02 33 02 34
+ 29 01 00 00 00 00 11 BA 02 64 02 98 02 C0 02 F1 03 10 03 47 03 53 03 64
+ 29 01 00 00 00 00 0D BB 03 76 03 8C 03 A6 03 C3 03 D9 03 FF
+ 15 01 00 00 00 00 02 FF 10
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 BA 03
+ 05 01 00 00 96 00 02 11 00
+ 05 01 00 00 00 00 02 29 00];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36672e-fhd-plus-120hz-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36672e-fhd-plus-120hz-video.dtsi
new file mode 100755
index 0000000..2662407
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36672e-fhd-plus-120hz-video.dtsi
@@ -0,0 +1,334 @@
+&mdss_mdp {
+ dsi_nt36672e_fhd_plus_120hz_video: qcom,mdss_dsi_nt36672e_fhd_plus_120hz_video {
+ qcom,mdss-dsi-panel-name =
+ "nt36672e fhd plus 120Hz Video panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750
+ 15800 13250 34450 7500 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <6450000>;
+ qcom,mdss-dsi-panel-blackness-level = <4961>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2408>;
+ qcom,mdss-dsi-h-front-porch = <76>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <10>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <10>;
+ qcom,mdss-dsi-v-front-porch = <46>;
+ qcom,mdss-dsi-v-pulse-width = <10>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 B0 00
+ 15 01 00 00 00 00 02 C0 03
+ 39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07
+ 0D B7 0C B7
+ 39 01 00 00 00 00 03 C2 1B A0
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 01 66
+ 15 01 00 00 00 00 02 06 40
+ 15 01 00 00 00 00 02 07 38
+ 15 01 00 00 00 00 02 2F 83
+ 15 01 00 00 00 00 02 69 91
+ 15 01 00 00 00 00 02 95 D1
+ 15 01 00 00 00 00 02 96 D1
+ 15 01 00 00 00 00 02 F2 64
+ 15 01 00 00 00 00 02 F4 64
+ 15 01 00 00 00 00 02 F6 64
+ 15 01 00 00 00 00 02 F8 64
+
+ 15 01 00 00 00 00 02 89 1C
+ 15 01 00 00 00 00 02 8A 1C
+ 15 01 00 00 00 00 02 8B 1C
+ 15 01 00 00 00 00 02 8C 1C
+
+ 15 01 00 00 00 00 02 FF 24
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 01 0F
+ 15 01 00 00 00 00 02 03 0C
+ 15 01 00 00 00 00 02 05 1D
+
+ 15 01 00 00 00 00 02 08 2F
+ 15 01 00 00 00 00 02 09 2E
+ 15 01 00 00 00 00 02 0A 2D
+ 15 01 00 00 00 00 02 0B 2C
+
+ 15 01 00 00 00 00 02 11 17
+ 15 01 00 00 00 00 02 12 13
+ 15 01 00 00 00 00 02 13 15
+ 15 01 00 00 00 00 02 15 14
+ 15 01 00 00 00 00 02 16 16
+ 15 01 00 00 00 00 02 17 18
+ 15 01 00 00 00 00 02 1B 01
+ 15 01 00 00 00 00 02 1D 1D
+
+ 15 01 00 00 00 00 02 20 2F
+ 15 01 00 00 00 00 02 21 2E
+ 15 01 00 00 00 00 02 22 2D
+ 15 01 00 00 00 00 02 23 2C
+
+ 15 01 00 00 00 00 02 29 17
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+ 15 01 00 00 00 00 02 2F 14
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+
+ 15 01 00 00 00 00 02 90 13
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+ 15 01 00 00 00 00 02 C6 C0
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+ 15 01 00 00 00 00 02 E9 02
+
+ 15 01 00 00 00 00 02 FF 25
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+
+ 15 01 00 00 00 00 02 72 41
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+
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+
+ 15 01 00 00 00 00 02 FF 27
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+ 15 01 00 00 00 00 02 20 81
+ 15 01 00 00 00 00 02 21 6A
+ 15 01 00 00 00 00 02 25 81
+ 15 01 00 00 00 00 02 26 94
+ 15 01 00 00 00 00 02 6E 00
+ 15 01 00 00 00 00 02 6F 00
+ 15 01 00 00 00 00 02 70 00
+ 15 01 00 00 00 00 02 71 00
+ 15 01 00 00 00 00 02 72 00
+ 15 01 00 00 00 00 02 75 00
+ 15 01 00 00 00 00 02 76 00
+ 15 01 00 00 00 00 02 77 00
+ 15 01 00 00 00 00 02 7D 09
+ 15 01 00 00 00 00 02 7E 67
+ 15 01 00 00 00 00 02 80 23
+ 15 01 00 00 00 00 02 82 09
+ 15 01 00 00 00 00 02 83 67
+ 15 01 00 00 00 00 02 88 01
+ 15 01 00 00 00 00 02 89 10
+ 15 01 00 00 00 00 02 A5 10
+ 15 01 00 00 00 00 02 A6 23
+ 15 01 00 00 00 00 02 A7 01
+ 15 01 00 00 00 00 02 B6 40
+
+ 15 01 00 00 00 00 02 FF 2A
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 00 91
+ 15 01 00 00 00 00 02 03 20
+ 15 01 00 00 00 00 02 07 50
+ 15 01 00 00 00 00 02 0A 70
+ 15 01 00 00 00 00 02 0C 04
+ 15 01 00 00 00 00 02 0D 40
+ 15 01 00 00 00 00 02 0F 01
+ 15 01 00 00 00 00 02 11 E0
+ 15 01 00 00 00 00 02 15 0F
+ 15 01 00 00 00 00 02 16 A4
+ 15 01 00 00 00 00 02 19 0F
+ 15 01 00 00 00 00 02 1A 78
+ 15 01 00 00 00 00 02 1B 23
+ 15 01 00 00 00 00 02 1D 36
+ 15 01 00 00 00 00 02 1E 3E
+ 15 01 00 00 00 00 02 1F 3E
+ 15 01 00 00 00 00 02 20 3E
+ 15 01 00 00 00 00 02 28 FD
+ 15 01 00 00 00 00 02 29 12
+ 15 01 00 00 00 00 02 2A E1
+ 15 01 00 00 00 00 02 2D 0A
+ 15 01 00 00 00 00 02 30 49
+ 15 01 00 00 00 00 02 33 96
+ 15 01 00 00 00 00 02 34 FF
+ 15 01 00 00 00 00 02 35 40
+ 15 01 00 00 00 00 02 36 DE
+ 15 01 00 00 00 00 02 37 F9
+ 15 01 00 00 00 00 02 38 45
+ 15 01 00 00 00 00 02 39 D9
+ 15 01 00 00 00 00 02 3A 49
+ 15 01 00 00 00 00 02 4A F0
+
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 11 B0 00 00 00 17 00 46 00 63 00 81 00 96
+ 00 AB 00 BD
+ 39 01 00 00 00 00 11 B1 00 CF 01 03 01 2F 01 6E 01 9D 01 E7
+ 02 22 02 24
+ 39 01 00 00 00 00 11 B2 02 5D 02 9B 02 C4 02 F9 03 1B 03 48
+ 03 56 03 65
+ 39 01 00 00 00 00 0F B3 03 75 03 87 03 9B 03 B1 03 CA 03 D7
+ 00 00
+ 39 01 00 00 00 00 11 B4 00 00 00 19 00 4B 00 69 00 87 00 9C
+ 00 B2 00 C3
+ 39 01 00 00 00 00 11 B5 00 D5 01 0B 01 35 01 73 01 A3 01 EC
+ 02 27 02 29
+ 39 01 00 00 00 00 11 B6 02 60 02 9F 02 C7 02 FB 03 1D 03 4C
+ 03 5A 03 69
+ 39 01 00 00 00 00 0F B7 03 7A 03 8C 03 A0 03 B5 03 CB 03 D7
+ 00 00
+ 39 01 00 00 00 00 11 B8 00 00 00 19 00 4D 00 6A 00 87 00 9C
+ 00 B1 00 C2
+ 39 01 00 00 00 00 11 B9 00 D3 01 08 01 32 01 70 01 9F 01 E8
+ 02 23 02 25
+ 39 01 00 00 00 00 11 BA 02 5C 02 9B 02 C3 02 F8 03 1A 03 4C
+ 03 5B 03 6B
+ 39 01 00 00 00 00 0F BB 03 7D 03 92 03 A7 03 BB 03 CE 03 D7
+ 00 00
+
+ 15 01 00 00 00 00 02 FF 21
+ 15 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 11 B0 00 00 00 17 00 46 00 63 00 81 00 96
+ 00 AB 00 BD
+ 39 01 00 00 00 00 11 B1 00 CF 01 03 01 2F 01 6E 01 9D 01 E7
+ 02 22 02 24
+ 39 01 00 00 00 00 11 B2 02 5D 02 9B 02 C4 02 F9 03 1B 03 48
+ 03 56 03 65
+ 39 01 00 00 00 00 0F B3 03 75 03 87 03 9B 03 B1 03 CA 03 D7
+ 00 00
+ 39 01 00 00 00 00 11 B4 00 00 00 19 00 4B 00 69 00 87 00 9C
+ 00 B2 00 C3
+ 39 01 00 00 00 00 11 B5 00 D5 01 0B 01 35 01 73 01 A3 01 EC
+ 02 27 02 29
+ 39 01 00 00 00 00 11 B6 02 60 02 9F 02 C7 02 FB 03 1D 03 4C
+ 03 5A 03 69
+ 39 01 00 00 00 00 0F B7 03 7A 03 8C 03 A0 03 B5 03 CB 03 D7
+ 00 00
+ 39 01 00 00 00 00 11 B8 00 00 00 19 00 4D 00 6A 00 87 00 9C
+ 00 B1 00 C2
+ 39 01 00 00 00 00 11 B9 00 D3 01 08 01 32 01 70 01 9F 01 E8
+ 02 23 02 25
+ 39 01 00 00 00 00 11 BA 02 5C 02 9B 02 C3 02 F8 03 1A 03 4C
+ 03 5B 03 6B
+ 39 01 00 00 00 00 0F BB 03 7D 03 92 03 A7 03 BB 03 CE 03 D7
+ 00 00
+
+ 15 01 00 00 00 00 02 FF 10
+ 15 01 00 00 00 00 02 FF F0
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 5A 00
+ 15 01 00 00 00 00 02 FF 10
+
+ 15 01 00 00 00 00 02 FF 10
+ 15 01 00 00 00 00 02 FB 01
+
+ 15 01 00 00 00 00 02 51 FF //CABC
+ 15 01 00 00 00 00 02 53 2C
+ 15 01 00 00 00 00 02 55 01
+
+ 05 01 00 00 C8 00 01 11
+ 05 01 00 00 96 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi
new file mode 100755
index 0000000..92f70b5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi
@@ -0,0 +1,312 @@
+&mdss_mdp {
+ dsi_nt36672e_fhd_plus_60_video: qcom,mdss_dsi_nt36672e_fhd_plus_60_video {
+ qcom,mdss-dsi-panel-name =
+ "nt36672e 60 Hz fhd plus video mode panel without DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <39000 16000 33750
+ 39800 13250 34450 7500 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <6450000>;
+ qcom,mdss-dsi-panel-blackness-level = <4961>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2408>;
+ qcom,mdss-dsi-h-front-porch = <76>;
+ qcom,mdss-dsi-h-back-porch = <56>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <10>;
+ qcom,mdss-dsi-v-front-porch = <46>;
+ qcom,mdss-dsi-v-pulse-width = <10>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 FF 10
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 B0 00
+ 39 01 00 00 00 00 02 C0 00
+ 39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7
+ 39 01 00 00 00 00 03 C2 1B A0
+ 39 01 00 00 00 00 02 FF 20
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 01 66
+ 39 01 00 00 00 00 02 06 40
+ 39 01 00 00 00 00 02 07 38
+ 39 01 00 00 00 00 02 2F 83
+ 39 01 00 00 00 00 02 69 91
+ 39 01 00 00 00 00 02 95 D1
+ 39 01 00 00 00 00 02 96 D1
+ 39 01 00 00 00 00 02 F2 64
+ 39 01 00 00 00 00 02 F3 54
+ 39 01 00 00 00 00 02 F4 64
+ 39 01 00 00 00 00 02 F5 54
+ 39 01 00 00 00 00 02 F6 64
+ 39 01 00 00 00 00 02 F7 54
+ 39 01 00 00 00 00 02 F8 64
+ 39 01 00 00 00 00 02 F9 54
+ 39 01 00 00 00 00 02 FF 24
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 01 0F
+ 39 01 00 00 00 00 02 03 0C
+ 39 01 00 00 00 00 02 05 1D
+ 39 01 00 00 00 00 02 08 2F
+ 39 01 00 00 00 00 02 09 2E
+ 39 01 00 00 00 00 02 0A 2D
+ 39 01 00 00 00 00 02 0B 2C
+ 39 01 00 00 00 00 02 11 17
+ 39 01 00 00 00 00 02 12 13
+ 39 01 00 00 00 00 02 13 15
+ 39 01 00 00 00 00 02 15 14
+ 39 01 00 00 00 00 02 16 16
+ 39 01 00 00 00 00 02 17 18
+ 39 01 00 00 00 00 02 1B 01
+ 39 01 00 00 00 00 02 1D 1D
+ 39 01 00 00 00 00 02 20 2F
+ 39 01 00 00 00 00 02 21 2E
+ 39 01 00 00 00 00 02 22 2D
+ 39 01 00 00 00 00 02 23 2C
+ 39 01 00 00 00 00 02 29 17
+ 39 01 00 00 00 00 02 2A 13
+ 39 01 00 00 00 00 02 2B 15
+ 39 01 00 00 00 00 02 2F 14
+ 39 01 00 00 00 00 02 30 16
+ 39 01 00 00 00 00 02 31 18
+ 39 01 00 00 00 00 02 32 04
+ 39 01 00 00 00 00 02 34 10
+ 39 01 00 00 00 00 02 35 1F
+ 39 01 00 00 00 00 02 36 1F
+ 39 01 00 00 00 00 02 4D 14
+ 39 01 00 00 00 00 02 4E 36
+ 39 01 00 00 00 00 02 4F 36
+ 39 01 00 00 00 00 02 53 36
+ 39 01 00 00 00 00 02 71 30
+ 39 01 00 00 00 00 02 79 11
+ 39 01 00 00 00 00 02 7A 82
+ 39 01 00 00 00 00 02 7B 8F
+ 39 01 00 00 00 00 02 7D 04
+ 39 01 00 00 00 00 02 80 04
+ 39 01 00 00 00 00 02 81 04
+ 39 01 00 00 00 00 02 82 13
+ 39 01 00 00 00 00 02 84 31
+ 39 01 00 00 00 00 02 85 00
+ 39 01 00 00 00 00 02 86 00
+ 39 01 00 00 00 00 02 87 00
+ 39 01 00 00 00 00 02 90 13
+ 39 01 00 00 00 00 02 92 31
+ 39 01 00 00 00 00 02 93 00
+ 39 01 00 00 00 00 02 94 00
+ 39 01 00 00 00 00 02 95 00
+ 39 01 00 00 00 00 02 9C F4
+ 39 01 00 00 00 00 02 9D 01
+ 39 01 00 00 00 00 02 A0 0F
+ 39 01 00 00 00 00 02 A2 0F
+ 39 01 00 00 00 00 02 A3 02
+ 39 01 00 00 00 00 02 A4 04
+ 39 01 00 00 00 00 02 A5 04
+ 39 01 00 00 00 00 02 C6 C0
+ 39 01 00 00 00 00 02 C9 00
+ 39 01 00 00 00 00 02 D9 80
+ 39 01 00 00 00 00 02 E9 02
+ 39 01 00 00 00 00 02 FF 25
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 18 22
+ 39 01 00 00 00 00 02 19 E4
+ 39 01 00 00 00 00 02 21 40
+ 39 01 00 00 00 00 02 66 D8
+ 39 01 00 00 00 00 02 68 50
+ 39 01 00 00 00 00 02 69 10
+ 39 01 00 00 00 00 02 6B 00
+ 39 01 00 00 00 00 02 6D 0D
+ 39 01 00 00 00 00 02 6E 48
+ 39 01 00 00 00 00 02 72 41
+ 39 01 00 00 00 00 02 73 4A
+ 39 01 00 00 00 00 02 74 D0
+ 39 01 00 00 00 00 02 77 62
+ 39 01 00 00 00 00 02 79 7E
+ 39 01 00 00 00 00 02 7D 03
+ 39 01 00 00 00 00 02 7E 15
+ 39 01 00 00 00 00 02 7F 00
+ 39 01 00 00 00 00 02 84 4D
+ 39 01 00 00 00 00 02 CF 80
+ 39 01 00 00 00 00 02 D6 80
+ 39 01 00 00 00 00 02 D7 80
+ 39 01 00 00 00 00 02 EF 20
+ 39 01 00 00 00 00 02 F0 84
+ 39 01 00 00 00 00 02 FF 26
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 81 0F
+ 39 01 00 00 00 00 02 83 01
+ 39 01 00 00 00 00 02 84 03
+ 39 01 00 00 00 00 02 85 01
+ 39 01 00 00 00 00 02 86 03
+ 39 01 00 00 00 00 02 87 01
+ 39 01 00 00 00 00 02 88 05
+ 39 01 00 00 00 00 02 8A 1A
+ 39 01 00 00 00 00 02 8B 11
+ 39 01 00 00 00 00 02 8C 24
+ 39 01 00 00 00 00 02 8E 42
+ 39 01 00 00 00 00 02 8F 11
+ 39 01 00 00 00 00 02 90 11
+ 39 01 00 00 00 00 02 91 11
+ 39 01 00 00 00 00 02 9A 80
+ 39 01 00 00 00 00 02 9B 04
+ 39 01 00 00 00 00 02 9C 00
+ 39 01 00 00 00 00 02 9D 00
+ 39 01 00 00 00 00 02 9E 00
+ 39 01 00 00 00 00 02 FF 27
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 01 68
+ 39 01 00 00 00 00 02 20 81
+ 39 01 00 00 00 00 02 21 6A
+ 39 01 00 00 00 00 02 25 81
+ 39 01 00 00 00 00 02 26 94
+ 39 01 00 00 00 00 02 6E 00
+ 39 01 00 00 00 00 02 6F 00
+ 39 01 00 00 00 00 02 70 00
+ 39 01 00 00 00 00 02 71 00
+ 39 01 00 00 00 00 02 72 00
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 00 00 02 76 00
+ 39 01 00 00 00 00 02 77 00
+ 39 01 00 00 00 00 02 7D 09
+ 39 01 00 00 00 00 02 7E 67
+ 39 01 00 00 00 00 02 80 23
+ 39 01 00 00 00 00 02 82 09
+ 39 01 00 00 00 00 02 83 67
+ 39 01 00 00 00 00 02 88 01
+ 39 01 00 00 00 00 02 89 10
+ 39 01 00 00 00 00 02 A5 10
+ 39 01 00 00 00 00 02 A6 23
+ 39 01 00 00 00 00 02 A7 01
+ 39 01 00 00 00 00 02 B6 40
+ 39 01 00 00 00 00 02 E5 02
+ 39 01 00 00 00 00 02 E6 D3
+ 39 01 00 00 00 00 02 EB 03
+ 39 01 00 00 00 00 02 EC 28
+ 39 01 00 00 00 00 02 FF 2A
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 00 91
+ 39 01 00 00 00 00 02 03 20
+ 39 01 00 00 00 00 02 07 50
+ 39 01 00 00 00 00 02 0A 70
+ 39 01 00 00 00 00 02 0C 04
+ 39 01 00 00 00 00 02 0D 40
+ 39 01 00 00 00 00 02 0F 01
+ 39 01 00 00 00 00 02 11 E0
+ 39 01 00 00 00 00 02 15 0F
+ 39 01 00 00 00 00 02 16 A4
+ 39 01 00 00 00 00 02 19 0F
+ 39 01 00 00 00 00 02 1A 78
+ 39 01 00 00 00 00 02 1B 23
+ 39 01 00 00 00 00 02 1D 36
+ 39 01 00 00 00 00 02 1E 3E
+ 39 01 00 00 00 00 02 1F 3E
+ 39 01 00 00 00 00 02 20 3E
+ 39 01 00 00 00 00 02 28 FD
+ 39 01 00 00 00 00 02 29 12
+ 39 01 00 00 00 00 02 2A E1
+ 39 01 00 00 00 00 02 2D 0A
+ 39 01 00 00 00 00 02 30 49
+ 39 01 00 00 00 00 02 33 96
+ 39 01 00 00 00 00 02 34 FF
+ 39 01 00 00 00 00 02 35 40
+ 39 01 00 00 00 00 02 36 DE
+ 39 01 00 00 00 00 02 37 F9
+ 39 01 00 00 00 00 02 38 45
+ 39 01 00 00 00 00 02 39 D9
+ 39 01 00 00 00 00 02 3A 49
+ 39 01 00 00 00 00 02 4A F0
+ 39 01 00 00 00 00 02 7A 09
+ 39 01 00 00 00 00 02 7B 40
+ 39 01 00 00 00 00 02 7F F0
+ 39 01 00 00 00 00 02 83 0F
+ 39 01 00 00 00 00 02 84 A4
+ 39 01 00 00 00 00 02 87 0F
+ 39 01 00 00 00 00 02 88 78
+ 39 01 00 00 00 00 02 89 23
+ 39 01 00 00 00 00 02 8B 36
+ 39 01 00 00 00 00 02 8C 7D
+ 39 01 00 00 00 00 02 8D 7D
+ 39 01 00 00 00 00 02 8E 7D
+ 39 01 00 00 00 00 02 FF 20
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 11 B0 00 00 00 17 00 49 00 6A 00 89 00 9F 00 B6 00 C8
+ 39 01 00 00 00 00 11 B1 00 D9 01 10 01 3A 01 7A 01 A9 01 F2 02 2D 02 2E
+ 39 01 00 00 00 00 11 B2 02 64 02 A3 02 CA 03 00 03 1E 03 4A 03 59 03 6A
+ 39 01 00 00 00 00 0F B3 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00
+ 39 01 00 00 00 00 11 B4 00 00 00 1B 00 51 00 71 00 90 00 A7 00 BF 00 D1
+ 39 01 00 00 00 00 11 B5 00 E2 01 1A 01 43 01 83 01 B2 01 FA 02 34 02 36
+ 39 01 00 00 00 00 11 B6 02 6B 02 A8 02 D0 03 03 03 21 03 4D 03 5B 03 6B
+ 39 01 00 00 00 00 0F B7 03 7E 03 94 03 AC 03 C8 03 EC 03 FE 00 00
+ 39 01 00 00 00 00 11 B8 00 00 00 1B 00 51 00 72 00 92 00 A8 00 BF 00 D1
+ 39 01 00 00 00 00 11 B9 00 E2 01 18 01 42 01 81 01 AF 01 F5 02 2F 02 31
+ 39 01 00 00 00 00 11 BA 02 68 02 A6 02 CD 03 01 03 1F 03 4A 03 59 03 6A
+ 39 01 00 00 00 00 0F BB 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00
+ 39 01 00 00 00 00 02 FF 21
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 11 B0 00 00 00 17 00 49 00 6A 00 89 00 9F 00 B6 00 C8
+ 39 01 00 00 00 00 11 B1 00 D9 01 10 01 3A 01 7A 01 A9 01 F2 02 2D 02 2E
+ 39 01 00 00 00 00 11 B2 02 64 02 A3 02 CA 03 00 03 1E 03 4A 03 59 03 6A
+ 39 01 00 00 00 00 0F B3 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00
+ 39 01 00 00 00 00 11 B4 00 00 00 1B 00 51 00 71 00 90 00 A7 00 BF 00 D1
+ 39 01 00 00 00 00 11 B5 00 E2 01 1A 01 43 01 83 01 B2 01 FA 02 34 02 36
+ 39 01 00 00 00 00 11 B6 02 6B 02 A8 02 D0 03 03 03 21 03 4D 03 5B 03 6B
+ 39 01 00 00 00 00 0F B7 03 7E 03 94 03 AC 03 C8 03 EC 03 FE 00 00
+ 39 01 00 00 00 00 11 B8 00 00 00 1B 00 51 00 72 00 92 00 A8 00 BF 00 D1
+ 39 01 00 00 00 00 11 B9 00 E2 01 18 01 42 01 81 01 AF 01 F5 02 2F 02 31
+ 39 01 00 00 00 00 11 BA 02 68 02 A6 02 CD 03 01 03 1F 03 4A 03 59 03 6A
+ 39 01 00 00 00 00 0F BB 03 7D 03 93 03 AB 03 C8 03 EC 03 FE 00 00
+ 39 01 00 00 00 00 02 FF 2C
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 61 1F
+ 39 01 00 00 00 00 02 62 1F
+ 39 01 00 00 00 00 02 7E 03
+ 39 01 00 00 00 00 02 6A 14
+ 39 01 00 00 00 00 02 6B 36
+ 39 01 00 00 00 00 02 6C 36
+ 39 01 00 00 00 00 02 6D 36
+ 39 01 00 00 00 00 02 53 04
+ 39 01 00 00 00 00 02 54 04
+ 39 01 00 00 00 00 02 55 04
+ 39 01 00 00 00 00 02 56 0F
+ 39 01 00 00 00 00 02 58 0F
+ 39 01 00 00 00 00 02 59 0F
+ 39 01 00 00 00 00 02 FF F0
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 5A 00
+ 15 01 00 00 00 00 02 FF 10
+ 15 01 00 00 00 00 02 FB 01
+ 15 01 00 00 00 00 02 51 FF
+ 15 01 00 00 00 00 02 53 24
+ 15 01 00 00 00 00 02 55 01
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 64 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi
new file mode 100755
index 0000000..02f1cee
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi
@@ -0,0 +1,480 @@
+&mdss_mdp {
+ dsi_nt36672e_fhd_plus_90hz_video: qcom,mdss_dsi_nt36672e_fhd_plus_90hz_video {
+ qcom,mdss-dsi-panel-name =
+ "nt36672e 90Hz fhd plus video mode panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <39000 16000 33750
+ 39800 13250 34450 7500 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <6450000>;
+ qcom,mdss-dsi-panel-blackness-level = <4961>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2408>;
+ qcom,mdss-dsi-h-front-porch = <76>;
+ qcom,mdss-dsi-h-back-porch = <68>;
+ qcom,mdss-dsi-h-pulse-width = <10>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <10>;
+ qcom,mdss-dsi-v-front-porch = <46>;
+ qcom,mdss-dsi-v-pulse-width = <10>;
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 FF 10
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 B0 00
+ 39 01 00 00 00 00 02 C0 03
+ 39 01 00 00 00 00 11 C1 89 28 00 08 00 AA 02 0E 00 2B 00 07 0D B7 0C B7
+ 39 01 00 00 00 00 03 C2 1B A0
+
+ 39 01 00 00 00 00 02 FF 20
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 01 66
+ 39 01 00 00 00 00 02 06 40
+ 39 01 00 00 00 00 02 07 38
+ 39 01 00 00 00 00 02 18 66
+ 39 01 00 00 00 00 02 1B 01
+ 39 01 00 00 00 00 02 5C 90
+ 39 01 00 00 00 00 02 5E AA
+ 39 01 00 00 00 00 02 69 91
+
+ 39 01 00 00 00 00 02 89 0D
+ 39 01 00 00 00 00 02 8A 0D
+ 39 01 00 00 00 00 02 8D 0D
+ 39 01 00 00 00 00 02 8E 0D
+ 39 01 00 00 00 00 02 8F 0D
+ 39 01 00 00 00 00 02 91 0D
+
+ 39 01 00 00 00 00 02 95 D1
+ 39 01 00 00 00 00 02 96 D1
+ 39 01 00 00 00 00 02 F2 65
+ 39 01 00 00 00 00 02 F3 64
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+ 39 01 00 00 00 00 02 E9 00
+
+
+ 39 01 00 00 00 00 02 FF 21
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 11 B0 00 00 00 15 00 3F 00 5F 00 7E 00 97 00 AF 00 C3
+ 39 01 00 00 00 00 11 B1 00 D7 01 0A 01 32 01 6F 01 9E 01 E5 02 1D 02 1E
+ 39 01 00 00 00 00 11 B2 02 56 02 94 02 BC 02 F1 03 13 03 41 03 4F 03 5F
+ 39 01 00 00 00 00 0F B3 03 71 03 84 03 99 03 B0 03 CA 03 D7 00 00
+ 39 01 00 00 00 00 11 B4 00 00 00 17 00 46 00 69 00 8C 00 A5 00 BE 00 D1
+ 39 01 00 00 00 00 11 B5 00 E4 01 18 01 40 01 7C 01 AA 01 F0 02 27 02 28
+ 39 01 00 00 00 00 11 B6 02 5E 02 9B 02 C3 02 F6 03 18 03 45 03 54 03 63
+ 39 01 00 00 00 00 0F B7 03 75 03 87 03 9C 03 B2 03 CA 03 D7 00 00
+ 39 01 00 00 00 00 11 B8 00 00 00 18 00 49 00 6B 00 8E 00 A8 00 C1 00 D3
+ 39 01 00 00 00 00 11 B9 00 E5 01 18 01 3F 01 7B 01 A8 01 EC 02 24 02 26
+ 39 01 00 00 00 00 11 BA 02 5A 02 97 02 C0 02 F4 03 15 03 43 03 51 03 61
+ 39 01 00 00 00 00 0F BB 03 72 03 85 03 9A 03 B1 03 CA 03 D7 00 00
+
+ 39 01 00 00 00 00 02 FF E0
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 35 82
+ 39 01 00 00 00 00 02 85 32
+
+ 39 01 00 00 00 00 02 FF F0
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 1C 01
+ 39 01 00 00 00 00 02 33 01
+ 39 01 00 00 00 00 02 5A 00
+
+ 39 01 00 00 00 00 02 FF D0
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 53 22
+ 39 01 00 00 00 00 02 54 02
+
+ 39 01 00 00 00 00 02 FF C0
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 9C 11
+ 39 01 00 00 00 00 02 9D 11
+
+ 39 01 00 00 00 00 02 FF 2B
+ 39 01 00 00 00 00 02 FB 01
+ 39 01 00 00 00 00 02 B7 0A
+ 39 01 00 00 00 00 02 B8 1C
+ 39 01 00 00 00 00 02 C0 01
+
+ 39 01 00 00 00 00 02 FF 10
+ 39 01 00 00 00 00 02 35 01
+ 39 01 00 00 00 00 02 51 FF
+ 39 01 00 00 00 00 02 53 0C
+ 39 01 00 00 00 00 02 55 00
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 28 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi
new file mode 100755
index 0000000..f1f5e54
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi
@@ -0,0 +1,404 @@
+&mdss_mdp {
+ dsi_dual_nt36850_truly_cmd: qcom,mdss_dsi_nt36850_truly_wqhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Dual nt36850 cmd mode dsi truly panel without DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <140>;
+ qcom,mdss-dsi-h-pulse-width = <20>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <20>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 19
+ 15 01 00 00 00 00 02 01 03
+ 15 01 00 00 00 00 02 02 04
+ 15 01 00 00 00 00 02 03 1b
+ 15 01 00 00 00 00 02 04 1d
+ 15 01 00 00 00 00 02 05 01
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+ 15 01 00 00 00 00 02 07 0f
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+ 15 01 00 00 00 00 02 09 00
+ 15 01 00 00 00 00 02 0a 00
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+ 15 01 00 00 00 00 02 0c 16
+ 15 01 00 00 00 00 02 0d 14
+ 15 01 00 00 00 00 02 0e 15
+ 15 01 00 00 00 00 02 0f 00
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+ 15 01 00 00 00 00 02 12 04
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+ 15 01 00 00 00 00 02 13 20
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+ 15 01 00 00 00 00 02 19 43
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+ 15 01 00 00 00 00 02 1b 25
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+ 15 01 00 00 00 00 02 24 00
+ 15 01 00 00 00 00 02 25 a7
+ 15 01 00 00 00 00 02 26 80
+ 15 01 00 00 00 00 02 27 a5
+ 15 01 00 00 00 00 02 28 06
+ 15 01 00 00 00 00 02 29 85
+ 15 01 00 00 00 00 02 2a 30
+ 15 01 00 00 00 00 02 2b 97
+ 15 01 00 00 00 00 02 2f 25
+ 15 01 00 00 00 00 02 30 26
+ 15 01 00 00 00 00 02 31 41
+ 15 01 00 00 00 00 02 32 04
+ 15 01 00 00 00 00 02 33 04
+ 15 01 00 00 00 00 02 34 2b
+ 15 01 00 00 00 00 02 35 00
+ 15 01 00 00 00 00 02 36 00
+ 15 01 00 00 00 00 02 37 c8
+ 15 01 00 00 00 00 02 38 26
+ 15 01 00 00 00 00 02 39 25
+ 15 01 00 00 00 00 02 3a 26
+ 15 01 00 00 00 00 02 3f eb
+ 15 01 00 00 00 00 02 41 21
+ 15 01 00 00 00 00 02 42 03
+ 15 01 00 00 00 00 02 43 00
+ 15 01 00 00 00 00 02 44 11
+ 15 01 00 00 00 00 02 45 00
+ 15 01 00 00 00 00 02 46 00
+ 15 01 00 00 00 00 02 47 00
+ 15 01 00 00 00 00 02 48 03
+ 15 01 00 00 00 00 02 49 03
+ 15 01 00 00 00 00 02 4a 00
+ 15 01 00 00 00 00 02 4b 00
+ 15 01 00 00 00 00 02 4c 01
+ 15 01 00 00 00 00 02 4d 4e
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 4c
+ 15 01 00 00 00 00 02 50 0d
+ 15 01 00 00 00 00 02 51 0e
+ 15 01 00 00 00 00 02 52 20
+ 15 01 00 00 00 00 02 53 97
+ 15 01 00 00 00 00 02 54 4b
+ 15 01 00 00 00 00 02 55 4c
+ 15 01 00 00 00 00 02 56 20
+ 15 01 00 00 00 00 02 58 04
+ 15 01 00 00 00 00 02 59 04
+ 15 01 00 00 00 00 02 5a 09
+ 15 01 00 00 00 00 02 5b 00
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5d c8
+ 15 01 00 00 00 00 02 5e 4c
+ 15 01 00 00 00 00 02 5f 4b
+ 15 01 00 00 00 00 02 60 00
+ 15 01 00 00 00 00 02 80 2b
+ 15 01 00 00 00 00 02 81 43
+ 15 01 00 00 00 00 02 82 03
+ 15 01 00 00 00 00 02 83 25
+ 15 01 00 00 00 00 02 84 11
+ 15 01 00 00 00 00 02 85 00
+ 15 01 00 00 00 00 02 86 80
+ 15 01 00 00 00 00 02 87 00
+ 15 01 00 00 00 00 02 88 00
+ 15 01 00 00 00 00 02 89 03
+ 15 01 00 00 00 00 02 8a 22
+ 15 01 00 00 00 00 02 8b 25
+ 15 01 00 00 00 00 02 8c 00
+ 15 01 00 00 00 00 02 8d a4
+ 15 01 00 00 00 00 02 8e 00
+ 15 01 00 00 00 00 02 8f a2
+ 15 01 00 00 00 00 02 90 06
+ 15 01 00 00 00 00 02 91 63
+ 15 01 00 00 00 00 02 92 30
+ 15 01 00 00 00 00 02 93 97
+ 15 01 00 00 00 00 02 94 25
+ 15 01 00 00 00 00 02 95 26
+ 15 01 00 00 00 00 02 96 41
+ 15 01 00 00 00 00 02 97 04
+ 15 01 00 00 00 00 02 98 04
+ 15 01 00 00 00 00 02 99 f0
+ 15 01 00 00 00 00 02 9a 00
+ 15 01 00 00 00 00 02 9b 00
+ 15 01 00 00 00 00 02 9c c8
+ 15 01 00 00 00 00 02 9d 50
+ 15 01 00 00 00 00 02 9e 26
+ 15 01 00 00 00 00 02 9f 25
+ 15 01 00 00 00 00 02 a0 26
+ 15 01 00 00 00 00 02 a2 00
+ 15 01 00 00 00 00 02 a3 33
+ 15 01 00 00 00 00 02 a5 40
+ 15 01 00 00 00 00 02 a6 40
+ 15 01 00 00 00 00 02 ac 91
+ 15 01 00 00 00 00 02 ad 66
+ 15 01 00 00 00 00 02 ae 66
+ 15 01 00 00 00 00 02 b1 40
+ 15 01 00 00 00 00 02 b2 40
+ 15 01 00 00 00 00 02 b4 40
+ 15 01 00 00 00 00 02 b5 40
+ 15 01 00 00 00 00 02 b7 40
+ 15 01 00 00 00 00 02 b8 40
+ 15 01 00 00 00 00 02 ba 22
+ 15 01 00 00 00 00 02 bb 00
+ 15 01 00 00 00 00 02 c2 01
+ 15 01 00 00 00 00 02 c3 01
+ 15 01 00 00 00 00 02 c4 01
+ 15 01 00 00 00 00 02 c5 01
+ 15 01 00 00 00 00 02 c6 01
+ 15 01 00 00 00 00 02 c8 00
+ 15 01 00 00 00 00 02 c9 00
+ 15 01 00 00 00 00 02 ca 00
+ 15 01 00 00 00 00 02 cd 00
+ 15 01 00 00 00 00 02 ce 00
+ 15 01 00 00 00 00 02 d6 04
+ 15 01 00 00 00 00 02 d7 00
+ 15 01 00 00 00 00 02 d8 0d
+ 15 01 00 00 00 00 02 d9 00
+ 15 01 00 00 00 00 02 da 00
+ 15 01 00 00 00 00 02 db 00
+ 15 01 00 00 00 00 02 dc 00
+ 15 01 00 00 00 00 02 dd 00
+ 15 01 00 00 00 00 02 de 00
+ 15 01 00 00 00 00 02 df 01
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 e1 00
+ 15 01 00 00 00 00 02 e2 19
+ 15 01 00 00 00 00 02 e3 04
+ 15 01 00 00 00 00 02 e4 00
+ 15 01 00 00 00 00 02 e5 04
+ 15 01 00 00 00 00 02 e6 00
+ 15 01 00 00 00 00 02 e7 12
+ 15 01 00 00 00 00 02 e8 00
+ 15 01 00 00 00 00 02 e9 50
+ 15 01 00 00 00 00 02 ea 10
+ 15 01 00 00 00 00 02 eb 02
+ 15 01 00 00 00 00 02 ff 27
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 ff 28
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 60 0a
+ 15 01 00 00 00 00 02 63 32
+ 15 01 00 00 00 00 02 64 01
+ 15 01 00 00 00 00 02 68 da
+ 15 01 00 00 00 00 02 69 00
+ 15 01 00 00 00 00 02 ff 29
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 60 0a
+ 15 01 00 00 00 00 02 63 32
+ 15 01 00 00 00 00 02 64 01
+ 15 01 00 00 00 00 02 68 da
+ 15 01 00 00 00 00 02 69 00
+ 15 01 00 00 00 00 02 ff e0
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 35 40
+ 15 01 00 00 00 00 02 36 40
+ 15 01 00 00 00 00 02 37 00
+ 15 01 00 00 00 00 02 89 c6
+ 15 01 00 00 00 00 02 ff f0
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 ea 40
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 36 00
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 03 44 03 e8
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 2c
+ 15 01 00 00 00 00 02 55 01
+ 05 01 00 00 0a 00 02 20 00
+ 15 01 00 00 00 00 02 bb 10
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 14 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,cmd-sync-wait-broadcast;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-panel-timings =
+ [da 34 24 00 64 68 28 38 2a 03 04 00];
+ qcom,mdss-dsi-t-clk-pre = <0x29>;
+ qcom,mdss-dsi-t-clk-post = <0x03>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd.dtsi
new file mode 100755
index 0000000..f28d7f6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-120hz-cmd.dtsi
@@ -0,0 +1,334 @@
+&mdss_mdp {
+ dsi_r66451_amoled_120hz_cmd: qcom,mdss_dsi_r66451_fhd_plus_120hz_cmd {
+ qcom,mdss-dsi-panel-name =
+ "r66451 amoled cmd mode dsi visionox 120HZ panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-physical-type = "oled";
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 10>, <1 20>;
+
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-pan-physical-width-dimension = <72>;
+ qcom,mdss-pan-physical-height-dimension = <157>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <120>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2340>;
+ qcom,mdss-dsi-h-front-porch = <95>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <25>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 1a c2 09 24 0c 00 00
+ 0c 00 00 00 09 3c 00 00 00 00 00 00
+ 00 00 00 00 00 30 00 6c
+ ];
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 0c c2 09 24 0c 00 00
+ 0c 00 00 00 09 3c
+ 39 01 00 00 00 00 1a d7 00 b9 3c 00 40
+ 04 00 a0 0a 00 40 00 00 00 00 00 00
+ 19 3c 00 40 04 00 a0 0a
+ 39 01 00 00 00 00 02 b0 80
+ 39 01 00 00 00 00 14 de 40 00 18 00 18
+ 00 18 00 18 10 00 18 00 18 00 18 02
+ 00 00
+ 39 01 00 00 00 00 02 b0 04
+ 39 01 00 00 00 00 03 e8 00 02
+ 39 01 00 00 00 00 03 e4 00 08
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 11 c4 00 00 00 00
+ 00 00 00 00 00 00 00 02 00 00 00 32
+ 39 01 00 00 00 00 19 cf 64 0b 00 00 00
+ 00 00 00 08 00 0b 77 01 01 01 01 01
+ 01 02 02 02 02 02 03
+ 39 01 00 00 00 00 15 d3 45 00 00 01 13
+ 15 00 15 07 0f 77 77 77 37 b2 11 00
+ a0 3c 9c
+ 39 01 00 00 00 00 1a d7 00 b9 34 00 40
+ 04 00 a0 0a 00 40 00 00 00 00 00 00
+ 19 34 00 40 04 00 a0 0a
+ 39 01 00 00 00 00 34 d8 00 00 00 00 00
+ 00 00 00 00 3a 00 3a 00 3a 00 3a 00
+ 3a 05 00 00 00 00 00 00 00 00 00 0a
+ 00 0a 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 0a 00 32 00 0a 00 22
+ 39 01 00 00 00 00 2b df 50 42 58 81 2d
+ 00 00 00 00 00 00 6b 00 00 00 00 00
+ 00 00 00 01 0f ff d4 0e 00 00 00 00
+ 00 00 0f 53 f1 00 00 00 00 00 00 00
+ 00
+ 39 01 00 00 00 00 02 f7 01
+ 39 01 00 00 00 00 02 b0 80
+ 39 01 00 00 00 00 0a e4 34 b4 00 00 00
+ 39 04 09 34
+ 39 01 00 00 00 00 02 e6 00
+ 39 01 00 00 00 00 02 b0 04
+ 39 01 00 00 00 00 03 df 50 40
+ 39 01 00 00 00 00 06 f3 50 00 00 00 00
+ 39 01 00 00 00 00 02 f2 11
+ 39 01 00 00 00 00 06 f3 01 00 00 00 01
+ 39 01 00 00 00 00 03 f4 00 02
+ 39 01 00 00 00 00 02 f2 19
+ 39 01 00 00 00 00 03 df 50 42
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 05 2a 00 00 04 37
+ 39 01 00 00 00 00 05 2b 00 00 09 23
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 14 00 01 29
+ ];
+
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-timing-switch-command-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <20>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2340>;
+ qcom,mdss-dsi-h-front-porch = <95>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <25>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 1a c2 09 24 0c 00 00
+ 0c 03 14 00 09 3c 00 00 00 00 00 00
+ 00 00 00 00 00 30 00 6c
+ ];
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 0c c2 09 24 0c 00 00
+ 0c 00 00 00 09 3c
+ 39 01 00 00 00 00 1a d7 00 b9 3c 00 40
+ 04 00 a0 0a 00 40 00 00 00 00 00 00
+ 19 3c 00 40 04 00 a0 0a
+ 39 01 00 00 00 00 02 b0 80
+ 39 01 00 00 00 00 14 de 40 00 18 00 18
+ 00 18 00 18 10 00 18 00 18 00 18 02
+ 00 00
+ 39 01 00 00 00 00 02 b0 04
+ 39 01 00 00 00 00 03 e8 00 02
+ 39 01 00 00 00 00 03 e4 00 08
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 11 c4 00 00 00 00
+ 00 00 00 00 00 00 00 02 00 00 00 32
+ 39 01 00 00 00 00 19 cf 64 0b 00 00 00
+ 00 00 00 08 00 0b 77 01 01 01 01 01
+ 01 02 02 02 02 02 03
+ 39 01 00 00 00 00 15 d3 45 00 00 01 13
+ 15 00 15 07 0f 77 77 77 37 b2 11 00
+ a0 3c 9c
+ 39 01 00 00 00 00 1a d7 00 b9 34 00 40
+ 04 00 a0 0a 00 40 00 00 00 00 00 00
+ 19 34 00 40 04 00 a0 0a
+ 39 01 00 00 00 00 34 d8 00 00 00 00 00
+ 00 00 00 00 3a 00 3a 00 3a 00 3a 00
+ 3a 05 00 00 00 00 00 00 00 00 00 0a
+ 00 0a 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 0a 00 32 00 0a 00 22
+ 39 01 00 00 00 00 2b df 50 42 58 81 2d
+ 00 00 00 00 00 00 6b 00 00 00 00 00
+ 00 00 00 01 0f ff d4 0e 00 00 00 00
+ 00 00 0f 53 f1 00 00 00 00 00 00 00
+ 00
+ 39 01 00 00 00 00 02 f7 01
+ 39 01 00 00 00 00 02 b0 80
+ 39 01 00 00 00 00 0a e4 34 b4 00 00 00
+ 39 04 09 34
+ 39 01 00 00 00 00 02 e6 00
+ 39 01 00 00 00 00 02 b0 04
+ 39 01 00 00 00 00 03 df 50 40
+ 39 01 00 00 00 00 06 f3 50 00 00 00 00
+ 39 01 00 00 00 00 02 f2 11
+ 39 01 00 00 00 00 06 f3 01 00 00 00 01
+ 39 01 00 00 00 00 03 f4 00 02
+ 39 01 00 00 00 00 02 f2 19
+ 39 01 00 00 00 00 03 df 50 42
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 05 2a 00 00 04 37
+ 39 01 00 00 00 00 05 2b 00 00 09 23
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 14 00 01 29
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 1a c2 09 24 0c 00 00
+ 0c 03 14 00 09 3c 00 00 00 00 00 00
+ 00 00 00 00 00 30 00 6c
+ ];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-timing-switch-command-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <20>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2340>;
+ qcom,mdss-dsi-h-front-porch = <95>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <25>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 1a c2 09 24 0c 00 00
+ 0c 09 3c 00 09 3c 00 00 00 00 00 00
+ 00 00 00 00 00 30 00 6c
+ ];
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 0c c2 09 24 0c 00 00
+ 0c 00 00 00 09 3c
+ 39 01 00 00 00 00 1a d7 00 b9 3c 00 40
+ 04 00 a0 0a 00 40 00 00 00 00 00 00
+ 19 3c 00 40 04 00 a0 0a
+ 39 01 00 00 00 00 02 b0 80
+ 39 01 00 00 00 00 14 de 40 00 18 00 18
+ 00 18 00 18 10 00 18 00 18 00 18 02
+ 00 00
+ 39 01 00 00 00 00 02 b0 04
+ 39 01 00 00 00 00 03 e8 00 02
+ 39 01 00 00 00 00 03 e4 00 08
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 11 c4 00 00 00 00
+ 00 00 00 00 00 00 00 02 00 00 00 32
+ 39 01 00 00 00 00 19 cf 64 0b 00 00 00
+ 00 00 00 08 00 0b 77 01 01 01 01 01
+ 01 02 02 02 02 02 03
+ 39 01 00 00 00 00 15 d3 45 00 00 01 13
+ 15 00 15 07 0f 77 77 77 37 b2 11 00
+ a0 3c 9c
+ 39 01 00 00 00 00 1a d7 00 b9 34 00 40
+ 04 00 a0 0a 00 40 00 00 00 00 00 00
+ 19 34 00 40 04 00 a0 0a
+ 39 01 00 00 00 00 34 d8 00 00 00 00 00
+ 00 00 00 00 3a 00 3a 00 3a 00 3a 00
+ 3a 05 00 00 00 00 00 00 00 00 00 0a
+ 00 0a 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 0a 00 32 00 0a 00 22
+ 39 01 00 00 00 00 2b df 50 42 58 81 2d
+ 00 00 00 00 00 00 6b 00 00 00 00 00
+ 00 00 00 01 0f ff d4 0e 00 00 00 00
+ 00 00 0f 53 f1 00 00 00 00 00 00 00
+ 00
+ 39 01 00 00 00 00 02 f7 01
+ 39 01 00 00 00 00 02 b0 80
+ 39 01 00 00 00 00 0a e4 34 b4 00 00 00
+ 39 04 09 34
+ 39 01 00 00 00 00 02 e6 00
+ 39 01 00 00 00 00 02 b0 04
+ 39 01 00 00 00 00 03 df 50 40
+ 39 01 00 00 00 00 06 f3 50 00 00 00 00
+ 39 01 00 00 00 00 02 f2 11
+ 39 01 00 00 00 00 06 f3 01 00 00 00 01
+ 39 01 00 00 00 00 03 f4 00 02
+ 39 01 00 00 00 00 02 f2 19
+ 39 01 00 00 00 00 03 df 50 42
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 05 2a 00 00 04 37
+ 39 01 00 00 00 00 05 2b 00 00 09 23
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 14 00 01 29
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 1a c2 09 24 0c 00 00
+ 0c 09 3c 00 09 3c 00 00 00 00 00 00
+ 00 00 00 00 00 30 00 6c
+ ];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-timing-switch-command-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <20>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-120hz-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-120hz-video.dtsi
new file mode 100755
index 0000000..b312662
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-120hz-video.dtsi
@@ -0,0 +1,107 @@
+&mdss_mdp {
+ dsi_r66451_amoled_120hz_video: qcom,mdss_dsi_r66451_fhd_plus_120hz_video {
+ qcom,mdss-dsi-panel-name =
+ "r66451 amoled video mode dsi visionox 120HZ panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-physical-type = "oled";
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 10>, <1 20>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-pan-physical-width-dimension = <72>;
+ qcom,mdss-pan-physical-height-dimension = <157>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <120>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2340>;
+ qcom,mdss-dsi-h-front-porch = <96>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <32>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <25>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 02 b3 01
+ 39 01 00 00 00 00 02 b0 04
+ 39 01 00 00 00 00 03 e8 00 02
+ 39 01 00 00 00 00 03 e4 00 08
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 11 c4 00 00 00 00
+ 00 00 00 00 00 00 00 02 00 00 00 32
+ 39 01 00 00 00 00 19 cf 64 0b 00 00 00
+ 00 00 00 08 00 0b 77 01 01 01 01 01
+ 01 02 02 02 02 02 03
+ 39 01 00 00 00 00 15 d3 45 00 00 01 13
+ 15 00 15 07 0f 77 77 77 37 b2 11 00
+ a0 3c 9c
+ 39 01 00 00 00 00 1a d7 00 b9 34 00 40
+ 04 00 a0 0a 00 40 00 00 00 00 00 00
+ 19 34 00 40 04 00 a0 0a
+ 39 01 00 00 00 00 34 d8 00 00 00 00 00
+ 00 00 00 00 3a 00 3a 00 3a 00 3a 00
+ 3a 05 00 00 00 00 00 00 00 00 00 0a
+ 00 0a 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 0a 00 32 00 0a 00 22
+ 39 01 00 00 00 00 2b df 50 42 58 81 2d
+ 00 00 00 00 00 00 6b 00 00 00 00 00
+ 00 00 00 01 0f ff d4 0e 00 00 00 00
+ 00 00 0f 53 f1 00 00 00 00 00 00 00
+ 00
+ 39 01 00 00 00 00 02 f7 01
+ 39 01 00 00 00 00 02 b0 80
+ 39 01 00 00 00 00 0a e4 34 b4 00 00 00
+ 39 04 09 34
+ 39 01 00 00 00 00 02 e6 00
+ 39 01 00 00 00 00 02 b0 04
+ 39 01 00 00 00 00 03 df 50 40
+ 39 01 00 00 00 00 06 f3 50 00 00 00 00
+ 39 01 00 00 00 00 02 f2 11
+ 39 01 00 00 00 00 06 f3 01 00 00 00 01
+ 39 01 00 00 00 00 03 f4 00 02
+ 39 01 00 00 00 00 02 f2 19
+ 39 01 00 00 00 00 03 df 50 42
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 05 2a 00 00 04 37
+ 39 01 00 00 00 00 05 2b 00 00 09 23
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 00 00 01 29
+ ];
+
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <20>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi
new file mode 100755
index 0000000..a959920
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi
@@ -0,0 +1,134 @@
+&mdss_mdp {
+ dsi_r66451_amoled_144hz_cmd: qcom,mdss_dsi_r66451_fhd_plus_144hz_cmd {
+ qcom,mdss-dsi-panel-name =
+ "r66451 amoled cmd mode dsi visionox panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-physical-type = "oled";
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,dsi-sec-ctrl-num = <1>;
+ qcom,dsi-sec-phy-num = <1>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <144>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2340>;
+ qcom,mdss-dsi-h-front-porch = <95>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <25>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 B0 04
+ 39 01 00 00 00 00 03 E8 00 02
+ 39 01 00 00 00 00 03 E4 00 08
+ 39 01 00 00 00 00 02 B0 00
+ 39 01 00 00 00 00 32 C4 00 00 00 00 00
+ 00 00 00 10 00 00 02 00 00 00 29 00
+ 01 00 00 00 00 00 00 00 00 00 00 00
+ 22 00 00 00 00 11 00 00 0C 00 00 00
+ 00 30 00 00 00 00 00 00
+ 39 01 00 00 00 00 86 CF 64 0B 00 00 00
+ 00 00 00 08 00 0B 77 01 01 01 01 01
+ 01 02 02 02 02 02 03 00 00 00 00 00
+ 00 00 00 00 00 00 00 02 C9 02 C9 02
+ C9 03 FF 03 FF 03 FF 00 00 00 00 00
+ 00 00 00 00 00 00 00 02 C9 02 C9 02
+ C9 03 FF 03 FF 03 FF 01 62 01 62 01
+ 62 01 62 01 62 01 62 01 62 01 62 01
+ 62 01 62 01 62 01 62 19 19 19 19 19
+ 19 19 19 19 19 19 19 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 0F F6 0F
+ F6 0F F6 0F F6 0F F6 19
+ 39 01 00 00 00 00 0D D0 44 44 B2 28 00
+ 28 5A 00 5A 0D 17 01
+ 39 01 00 00 00 00 15 D3 49 00 00 01 1A
+ 15 00 15 07 0F 77 77 77 37 B2 11 00
+ A0 3C 9A
+ 39 01 00 00 00 00 1A D7 00 B9 40 00 40
+ 04 00 F0 0F 00 40 00 00 00 00 00 00
+ 19 40 00 40 04 00 F0 0F
+ 39 01 00 00 00 00 34 D8 00 00 00 00 00
+ 00 00 00 00 30 00 30 00 30 00 30 00
+ 30 05 00 00 00 00 00 00 00 00 00 0F
+ 00 0F 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 0F 00 2F 00 0F 00 20
+ 39 01 00 00 00 00 2B DF 50 42 58 81 2D
+ 00 00 00 00 00 00 6B 00 00 00 00 00
+ 00 00 00 01 0F FF D4 0E 00 00 00 00
+ 00 00 0F 53 18 00 0F 00 00 00 00 00
+ 00
+ 39 01 00 00 00 00 02 F7 01
+ 39 01 00 00 00 00 02 B0 80
+ 39 01 00 00 00 00 0a E4 34 B4 00 00 00
+ 30 04 0C E2
+ 39 01 00 00 00 00 02 E6 00
+ 39 01 00 00 00 00 02 B0 04
+ 39 01 00 00 00 00 03 DF 50 40
+ 39 01 00 00 00 00 06 F3 50 00 00 00 00
+ 39 01 00 00 00 00 02 F2 11
+ 39 01 00 00 00 00 06 F3 01 00 00 00 01
+ 39 01 00 00 00 00 03 F4 00 02
+ 39 01 00 00 00 00 02 F2 19
+ 39 01 00 00 00 00 03 DF 50 42
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 05 2A 00 00 04 37
+ 39 01 00 00 00 00 05 2B 00 00 09 23
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 00 00 01 29
+ ];
+
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-timing-switch-command-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <20>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi
new file mode 100755
index 0000000..1303acb
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi
@@ -0,0 +1,95 @@
+&mdss_mdp {
+ dsi_r66451_amoled_60hz_cmd: qcom,mdss_dsi_r66451_fhd_plus_60hz_cmd {
+ qcom,mdss-dsi-panel-name =
+ "r66451 amoled cmd mode dsi visionox 60HZ panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-physical-type = "oled";
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 10>, <1 20>;
+
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2340>;
+ qcom,mdss-dsi-h-front-porch = <95>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <25>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 13 d8 00 00 00 00 00
+ 00 00 00 00 5b 00 5b 00 5b 00 5b 00
+ 5b
+ 39 01 00 00 00 00 02 b0 80
+ 39 01 00 00 00 00 02 e6 00
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 19 cf 64 0b 00 00 00
+ 00 00 00 08 00 0b 77 01 01 01 01 01
+ 01 04 04 04 04 04 05
+ 39 01 00 00 00 00 02 b0 04
+ 39 01 00 00 00 00 02 f7 01
+ 39 01 00 00 00 00 03 df 50 40
+ 39 01 00 00 00 00 06 f3 50 00 00 00 00
+ 39 01 00 00 00 00 02 f2 11
+ 39 01 00 00 00 00 06 f3 01 00 00 00 01
+ 39 01 00 00 00 00 03 f4 00 02
+ 39 01 00 00 00 00 02 f2 19
+ 39 01 00 00 00 00 03 df 50 42
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 05 2a 00 00 04 37
+ 39 01 00 00 00 00 05 2b 00 00 09 23
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 00 00 01 29
+ ];
+
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <20>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi
new file mode 100755
index 0000000..cfda350
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi
@@ -0,0 +1,86 @@
+&mdss_mdp {
+ dsi_r66451_amoled_60hz_video: qcom,mdss_dsi_r66451_fhd_plus_60hz_video {
+ qcom,mdss-dsi-panel-name =
+ "r66451 amoled video mode dsi visionox 60HZ panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-physical-type = "oled";
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 10>, <1 20>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2340>;
+ qcom,mdss-dsi-h-front-porch = <95>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <25>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 02 b3 01
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 13 d8 00 00 00 00 00
+ 00 00 00 00 5b 00 5b 00 5b 00 5b 00
+ 5b
+ 39 01 00 00 00 00 02 b0 80
+ 39 01 00 00 00 00 02 e6 00
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 19 cf 64 0b 00 00 00
+ 00 00 00 08 00 0b 77 01 01 01 01 01
+ 01 04 04 04 04 04 05
+ 39 01 00 00 00 00 02 b0 04
+ 39 01 00 00 00 00 02 f7 01
+ 39 01 00 00 00 00 03 df 50 40
+ 39 01 00 00 00 00 06 f3 50 00 00 00 00
+ 39 01 00 00 00 00 02 f2 11
+ 39 01 00 00 00 00 06 f3 01 00 00 00 01
+ 39 01 00 00 00 00 03 f4 00 02
+ 39 01 00 00 00 00 02 f2 19
+ 39 01 00 00 00 00 03 df 50 42
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 05 2a 00 00 04 37
+ 39 01 00 00 00 00 05 2b 00 00 09 23
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 00 00 01 29
+ ];
+
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <20>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi
new file mode 100755
index 0000000..3b1a851
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi
@@ -0,0 +1,91 @@
+&mdss_mdp {
+ dsi_r66451_amoled_90hz_cmd: qcom,mdss_dsi_r66451_fhd_plus_90hz_cmd {
+ qcom,mdss-dsi-panel-name =
+ "r66451 amoled cmd mode dsi visionox 90HZ panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-physical-type = "oled";
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 10>, <1 20>;
+
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2340>;
+ qcom,mdss-dsi-h-front-porch = <95>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <25>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 b0 80
+ 39 01 00 00 00 00 02 e6 00
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 19 cf 64 0b 00 00 00
+ 00 00 00 08 00 0b 77 01 01 01 01 01
+ 01 04 04 04 04 04 05
+ 39 01 00 00 00 00 02 b0 04
+ 39 01 00 00 00 00 02 f7 01
+ 39 01 00 00 00 00 03 df 50 40
+ 39 01 00 00 00 00 06 f3 50 00 00 00 00
+ 39 01 00 00 00 00 02 f2 11
+ 39 01 00 00 00 00 06 f3 01 00 00 00 01
+ 39 01 00 00 00 00 03 f4 00 02
+ 39 01 00 00 00 00 02 f2 19
+ 39 01 00 00 00 00 03 df 50 42
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 05 2a 00 00 04 37
+ 39 01 00 00 00 00 05 2b 00 00 09 23
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 00 00 01 29
+ ];
+
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <20>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi
new file mode 100755
index 0000000..dd76a02
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi
@@ -0,0 +1,82 @@
+&mdss_mdp {
+ dsi_r66451_amoled_90hz_video: qcom,mdss_dsi_r66451_fhd_plus_90hz_video {
+ qcom,mdss-dsi-panel-name =
+ "r66451 amoled video mode dsi visionox 90HZ panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-physical-type = "oled";
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 10>, <1 20>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2340>;
+ qcom,mdss-dsi-h-front-porch = <95>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <25>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 02 b3 01
+ 39 01 00 00 00 00 02 b0 80
+ 39 01 00 00 00 00 02 e6 00
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 19 cf 64 0b 00 00 00
+ 00 00 00 08 00 0b 77 01 01 01 01 01
+ 01 04 04 04 04 04 05
+ 39 01 00 00 00 00 02 b0 04
+ 39 01 00 00 00 00 02 f7 01
+ 39 01 00 00 00 00 03 df 50 40
+ 39 01 00 00 00 00 06 f3 50 00 00 00 00
+ 39 01 00 00 00 00 02 f2 11
+ 39 01 00 00 00 00 06 f3 01 00 00 00 01
+ 39 01 00 00 00 00 03 f4 00 02
+ 39 01 00 00 00 00 02 f2 19
+ 39 01 00 00 00 00 03 df 50 42
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 05 2a 00 00 04 37
+ 39 01 00 00 00 00 05 2b 00 00 09 23
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 00 00 01 29
+ ];
+
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <20>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-hd-plus-90hz-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-hd-plus-90hz-cmd.dtsi
new file mode 100755
index 0000000..c5b9f65
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-hd-plus-90hz-cmd.dtsi
@@ -0,0 +1,86 @@
+&mdss_mdp {
+ dsi_r66451_amoled_hd_90hz_cmd: qcom,mdss_dsi_r66451_hd_plus_90hz_cmd {
+ qcom,mdss-dsi-panel-name =
+ "r66451 amoled cmd mode dsi visionox 90HZ panel without DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-physical-type = "oled";
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 10>, <1 20>;
+
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1560>;
+ qcom,mdss-dsi-h-front-porch = <95>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <25>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 b0 80
+ 39 01 00 00 00 00 02 e6 00
+ 39 01 00 00 00 00 02 d9 09
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 19 cf 64 0b 00 00 00
+ 00 00 00 08 00 0b 77 01 01 01 01 01
+ 01 04 04 04 04 04 05
+ 39 01 00 00 00 00 02 b0 04
+ 39 01 00 00 00 00 03 eb 00 00
+ 39 01 00 00 00 00 02 f7 00
+ 39 01 00 00 00 00 03 df 50 40
+ 39 01 00 00 00 00 06 f3 50 00 00 00 00
+ 39 01 00 00 00 00 02 f2 11
+ 39 01 00 00 00 00 06 f3 01 00 00 00 01
+ 39 01 00 00 00 00 03 f4 00 02
+ 39 01 00 00 00 00 02 f2 19
+ 39 01 00 00 00 00 03 df 50 42
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 05 2a 00 00 02 cf
+ 39 01 00 00 00 00 05 2b 00 00 06 17
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 00 00 01 29
+ ];
+
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-hd-plus-90hz-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-hd-plus-90hz-video.dtsi
new file mode 100755
index 0000000..abb12bd
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r66451-hd-plus-90hz-video.dtsi
@@ -0,0 +1,76 @@
+&mdss_mdp {
+ dsi_r66451_amoled_hd_90hz_video: qcom,mdss_dsi_r66451_hd_plus_90hz_video {
+ qcom,mdss-dsi-panel-name =
+ "r66451 amoled video mode dsi visionox 90HZ panel without DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-physical-type = "oled";
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 10>, <1 20>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1560>;
+ qcom,mdss-dsi-h-front-porch = <95>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <25>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 02 b3 01
+ 39 01 00 00 00 00 02 b0 80
+ 39 01 00 00 00 00 02 e6 00
+ 39 01 00 00 00 00 02 d9 09
+ 39 01 00 00 00 00 02 b0 00
+ 39 01 00 00 00 00 19 cf 64 0b 00 00 00
+ 00 00 00 08 00 0b 77 01 01 01 01 01
+ 01 04 04 04 04 04 05
+ 39 01 00 00 00 00 02 b0 04
+ 39 01 00 00 00 00 03 eb 00 00
+ 39 01 00 00 00 00 02 f7 00
+ 39 01 00 00 00 00 03 df 50 40
+ 39 01 00 00 00 00 06 f3 50 00 00 00 00
+ 39 01 00 00 00 00 02 f2 11
+ 39 01 00 00 00 00 06 f3 01 00 00 00 01
+ 39 01 00 00 00 00 03 f4 00 02
+ 39 01 00 00 00 00 02 f2 19
+ 39 01 00 00 00 00 03 df 50 42
+ 39 01 00 00 00 00 05 2a 00 00 02 cf
+ 39 01 00 00 00 00 05 2b 00 00 06 17
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 00 00 01 29
+ ];
+
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r69006-1080p-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r69006-1080p-cmd.dtsi
new file mode 100755
index 0000000..d51176e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r69006-1080p-cmd.dtsi
@@ -0,0 +1,145 @@
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------
+ */
+
+&mdss_mdp {
+ dsi_r69006_1080p_cmd: qcom,mdss_dsi_r69006_1080p_cmd {
+ qcom,mdss-dsi-panel-name = "r69006 1080p cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <82>;
+ qcom,mdss-dsi-h-pulse-width = <20>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <9>;
+ qcom,mdss-dsi-v-front-porch = <3>;
+ qcom,mdss-dsi-v-pulse-width = <15>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-on-command = [23 01 00 00 00 00 02 B0 00
+ 29 01 00 00 00 00 06
+ B3 04 10 00 00 00
+ 29 01 00 00 00 00 03
+ B4 0C 00
+ 29 01 00 00 00 00 04
+ B6 3B D3 00
+ 23 01 00 00 00 00
+ 02 C0 00
+ 15 01 00 00 00 00
+ 02 36 98
+ 23 01 00 00 00 00
+ 02 CC 04
+ 29 01 00 00 00 00 20
+ C1 84 00 10 EF 8B F1 FF
+ FF DF 9C C5 9A 73 8D AD
+ 63 FE FF FF CB F8 01 00
+ AA 40 02 C2 01 08 00 01
+ 29 01 00 00 00 00 0A
+ CB 0D FE 1F 2C 00 00 00
+ 00 00
+ 29 01 00 00 00 00 0B
+ C2 01 F7 80 04 63 00 60
+ 00 01 30
+ 29 01 00 00 00 00 07
+ C3 55 01 00 01 00 00
+ 29 01 00 00 00 00 12
+ C4 70 00 00 00 00 00 00
+ 00 00 02 01 00 05 01 00
+ 00 00
+ 29 01 00 00 00 00 0F
+ C6 57 07 4A 07 4A 01 0E
+ 01 02 01 02 09 15 07
+ 29 01 00 00 00 00 1F
+ C7 00 06 0C 16 27 35 3F
+ 4D 33 3C 49 5B 64 66 67
+ 00 06 0C 16 27 35 3F 4D
+ 33 3C 49 5B 64 66 67
+ 29 01 00 00 00 00 14
+ C8 00 00 FE 01 08 E7 00
+ 00 FD 02 03 A8 00 00 FC
+ E7 E9 C9 00
+ 29 01 00 00 00 00 09
+ C9 1F 68 1F 68 4C 4C C4
+ 11
+ 29 01 00 00 00 00 11
+ D0 11 01 91 0B D9 19 19
+ 00 00 00 19 99 00 00 00
+ 00
+ 29 01 00 00 00 00 1D
+ D3 1B 3B BB AD A5 33 33
+ 33 00 80 AD A8 37 33 33
+ 33 33 F7 F2 1F 7D 7C FF
+ 0F 99 00 FF FF
+ 29 01 00 00 00 00 04
+ D4 57 33 03
+ 29 01 00 00 00 00 0C
+ D5 66 00 00 01 32 01 32
+ 00 0b 00 0b
+ 29 01 00 00 00 00 02 BE 04
+ 29 01 00 00 00 00 11
+ CF 40 10 00 00 00 00 32
+ 00 00 00 00 00 00 00 00
+ 00
+ 29 01 00 00 00 00 06
+ DE 00 00 3F FF 10
+ 29 01 00 00 00 00 02 E9 00
+ 29 01 00 00 00 00 02 F2 00
+ 23 01 00 00 00 00 02 D6 01
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 51 FF
+ 39 01 00 00 00 00 02 53 2C
+ 39 01 00 00 00 00 02 55 00
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 14 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 0A 00 02 28 00
+ 29 01 00 00 00 00 1d D3 13 3B BB A5 A5 33 33 33
+ 00 80 A4 A8 37 33 33 33 33 F7 F2 1F 7D
+ 7C FF 0F 99 00 FF FF
+ 05 01 00 00 5A 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-panel-timings = [6E 3F 36 00 5A 4F 38 41 54
+ 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x1e>;
+ qcom,mdss-dsi-t-clk-pre = <0x30>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 01 0A];
+ qcom,mdss-dsi-panel-status-command-mode = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-panel-status-value = <0x1C>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ qcom,mdss-dsi-rx-eot-ignore;
+ qcom,mdss-dsi-tx-eot-append;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r69006-1080p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r69006-1080p-video.dtsi
new file mode 100755
index 0000000..e3e84797
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-r69006-1080p-video.dtsi
@@ -0,0 +1,125 @@
+/*---------------------------------------------------------------------------
+ * This file is autogenerated file using gcdb parser. Please do not edit it.
+ * Update input XML file to add a new entry or update variable in this file
+ * VERSION = "1.0"
+ *---------------------------------------------------------------------------
+ */
+
+&mdss_mdp {
+ dsi_r69006_1080p_video: qcom,mdss_dsi_r69006_1080p_video {
+ qcom,mdss-dsi-panel-name = "r69006 1080p video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <82>;
+ qcom,mdss-dsi-h-pulse-width = <20>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <9>;
+ qcom,mdss-dsi-v-front-porch = <3>;
+ qcom,mdss-dsi-v-pulse-width = <15>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-on-command = [23 01 00 00 00 00 02 B0 00
+ 29 01 00 00 00 00 06
+ B3 05 10 00 00 00
+ 29 01 00 00 00 00 03 B4 0c 00
+ 29 01 00 00 00 00 04 B6 3b c3 00
+ 23 01 00 00 00 00 02 C0 00
+ 15 01 00 00 00 00 02 36 98
+ 23 01 00 00 00 00 02 CC 04
+ 29 01 00 00 00 00 20
+ C1 84 00 10 EF 8B
+ F1 FF FF DF 9C C5
+ 9A 73 8D AD 63 FE
+ FF FF CB F8 01 00
+ AA 40 00 C2 01 08
+ 00 01
+ 29 01 00 00 00 00 0A
+ CB 0D FE 1F 2C 00
+ 00 00 00 00
+ 29 01 00 00 00 00 0B
+ C2 01 F7 80 04 63
+ 00 60 00 01 30
+ 29 01 00 00 00 00 07
+ C3 55 01 00 01 00
+ 00
+ 29 01 00 00 00 00 12
+ C4 70 00 00 00 00
+ 00 00 00 00 02 01
+ 00 05 01 00 00 00
+ 29 01 00 00 00 00 0F
+ C6 59 07 4a 07 4a
+ 01 0E 01 02 01 02
+ 09 15 07
+ 29 01 00 00 00 00 1F
+ C7 00 30 32 34 42
+ 4E 56 62 44 4A 54
+ 62 6B 73 7F 08 30
+ 32 34 42 4E 56 62
+ 44 4A 54 62 6B 73
+ 7F
+ 29 01 00 00 00 00 14
+ C8 00 00 00 00 00
+ FC 00 00 00 00 00
+ FC 00 00 00 00 00
+ FC 00
+ 29 01 00 00 00 00 09
+ C9 1F 68 1F 68 4C
+ 4C C4 11
+ 29 01 00 00 00 00 11
+ D0 33 01 91 0B D9
+ 19 19 00 00 00 19
+ 99 00 00 00 00
+ 29 01 00 00 00 00 1D
+ D3 1B 3B BB AD A5
+ 33 33 33 00 80 AD
+ A8 6f 6f 33 33 33
+ F7 F2 1F 7D 7C FF
+ 0F 99 00 FF FF
+ 29 01 00 00 00 00 04
+ D4 57 33 03
+ 29 01 00 00 00 00 0C
+ D5 66 00 00 01 27
+ 01 27 00 6D 00 6D
+ 23 01 00 00 00 00 02 D6 81
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <1>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings = [7d 25 1d 00 37 33
+ 22 27 1e 03 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x20>;
+ qcom,mdss-dsi-t-clk-pre = <0x2c>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 2>, <1 20>;
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 05 00 01 0A];
+ qcom,mdss-dsi-panel-status-command-mode = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-panel-status-value = <0x1C>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-rm67195-amoled-fhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-rm67195-amoled-fhd-cmd.dtsi
new file mode 100755
index 0000000..9cdfd59
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-rm67195-amoled-fhd-cmd.dtsi
@@ -0,0 +1,119 @@
+&mdss_mdp {
+ dsi_rm67195_amoled_fhd_cmd: qcom,mdss_dsi_rm67195_amoled_fhd_cmd{
+ qcom,mdss-dsi-panel-name =
+ "rm67195 amoled fhd cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <12>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 fe 0d
+ 15 01 00 00 00 00 02 0b c0
+ 15 01 00 00 00 00 02 42 00
+ 15 01 00 00 00 00 02 18 08
+ 15 01 00 00 00 00 02 08 41
+ 15 01 00 00 00 00 02 46 02
+ 15 01 00 00 00 00 02 1e 04
+ 15 01 00 00 02 00 02 1e 00
+ 15 01 00 00 00 00 02 fe 0a
+ 15 01 00 00 00 00 02 24 17
+ 15 01 00 00 00 00 02 04 07
+ 15 01 00 00 00 00 02 1a 0c
+ 15 01 00 00 02 00 02 0f 44
+ 15 01 00 00 00 00 02 fe 0b
+ 15 01 00 00 00 00 02 28 40
+ 15 01 00 00 02 00 02 29 4f
+ 15 01 00 00 00 00 02 fe 04
+ 15 01 00 00 00 00 02 0a d8
+ 15 01 00 00 00 00 02 0c e6
+ 15 01 00 00 00 00 02 4e 20
+ 15 01 00 00 00 00 02 4f 1b
+ 15 01 00 00 00 00 02 50 2f
+ 15 01 00 00 02 00 02 51 08
+ 15 01 00 00 00 00 02 fe 09
+ 15 01 00 00 00 00 02 00 08
+ 15 01 00 00 00 00 02 01 08
+ 15 01 00 00 00 00 02 02 00
+ 15 01 00 00 00 00 02 03 00
+ 15 01 00 00 00 00 02 04 10
+ 15 01 00 00 00 00 02 05 00
+ 15 01 00 00 00 00 02 06 08
+ 15 01 00 00 00 00 02 07 08
+ 15 01 00 00 00 00 02 08 00
+ 15 01 00 00 00 00 02 12 24
+ 15 01 00 00 00 00 02 13 49
+ 15 01 00 00 00 00 02 14 92
+ 15 01 00 00 00 00 02 15 49
+ 15 01 00 00 00 00 02 16 92
+ 15 01 00 00 00 00 02 17 24
+ 15 01 00 00 00 00 02 18 24
+ 15 01 00 00 00 00 02 19 49
+ 15 01 00 00 00 00 02 1a 92
+ 15 01 00 00 00 00 02 1b 49
+ 15 01 00 00 00 00 02 1c 92
+ 15 01 00 00 00 00 02 1d 24
+ 15 01 00 00 00 00 02 1e 24
+ 15 01 00 00 00 00 02 1f 49
+ 15 01 00 00 00 00 02 20 92
+ 15 01 00 00 00 00 02 21 49
+ 15 01 00 00 00 00 02 22 92
+ 15 01 00 00 00 00 02 23 24
+ 15 01 00 00 00 00 02 9b 07
+ 15 01 00 00 02 00 02 9c a5
+ 15 01 00 00 00 00 02 fe 00
+ 15 01 00 00 00 00 02 c2 08
+ 15 01 00 00 02 00 02 35 00
+ 39 01 00 00 00 00 03 44 03 e8
+ 05 01 00 00 82 00 02 11 00
+ 05 01 00 00 14 00 02 29 00];
+
+ qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00
+ 05 01 00 00 82 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_pulse";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-t-clk-post = <0x0d>;
+ qcom,mdss-dsi-t-clk-pre = <0x2f>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,mdss-pan-physical-width-dimension = <70>;
+ qcom,mdss-pan-physical-height-dimension = <125>;
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>;
+ qcom,mdss-dsi-panel-orientation = "180";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi
new file mode 100755
index 0000000..3137cb6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi
@@ -0,0 +1,72 @@
+&mdss_mdp {
+ dsi_rm69299_visionox_amoled_cmd:
+ qcom,mdss_dsi_rm69299_visionox_amoled_cmd {
+ qcom,mdss-dsi-panel-name =
+ "rm69299 amoled fhd+ cmd mode dsi visionox panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-physical-type = "oled";
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2248>;
+ qcom,mdss-dsi-h-front-porch = <26>;
+ qcom,mdss-dsi-h-back-porch = <36>;
+ qcom,mdss-dsi-h-pulse-width = <2>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <56>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 FE 00
+ 39 01 00 00 00 00 02 C2 08
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 51 FF
+ 05 01 00 00 96 00 02 11 00
+ 05 01 00 00 32 00 02 29 00];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-lp1-command =
+ [05 01 00 00 00 00 02 39 00];
+ qcom,mdss-dsi-lp1-command-state ="dsi_lp_mode";
+ qcom,mdss-dsi-nolp-command =
+ [05 01 00 00 00 00 02 38 00];
+ qcom,mdss-dsi-nolp-command-state =
+ "dsi_lp_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-rm69299-visionox-fhd-plus-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-rm69299-visionox-fhd-plus-video.dtsi
new file mode 100755
index 0000000..5cd896f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-rm69299-visionox-fhd-plus-video.dtsi
@@ -0,0 +1,72 @@
+&mdss_mdp {
+ dsi_rm69299_visionox_amoled_video:
+ qcom,mdss_dsi_rm69299_visionox_amoled_video {
+ qcom,mdss-dsi-panel-name =
+ "rm69299 amoled fhd+ video mode dsi visionox panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-physical-type = "oled";
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2248>;
+ qcom,mdss-dsi-h-front-porch = <26>;
+ qcom,mdss-dsi-h-back-porch = <36>;
+ qcom,mdss-dsi-h-pulse-width = <2>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <56>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 FE 00
+ 39 01 00 00 00 00 02 C2 08
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 51 FF
+ 05 01 00 00 96 00 02 11 00
+ 05 01 00 00 32 00 02 29 00];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-lp1-command =
+ [05 01 00 00 00 00 02 39 00];
+ qcom,mdss-dsi-lp1-command-state ="dsi_lp_mode";
+ qcom,mdss-dsi-nolp-command =
+ [05 01 00 00 00 00 02 38 00];
+ qcom,mdss-dsi-nolp-command-state =
+ "dsi_lp_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi
new file mode 100755
index 0000000..11eb3a3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-s6e3ha3-amoled-dualmipi-wqhd-cmd.dtsi
@@ -0,0 +1,129 @@
+&mdss_mdp {
+ dsi_dual_s6e3ha3_amoled_cmd: qcom,mdss_dsi_s6e3ha3_amoled_wqhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Dual s6e3ha3 amoled cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <31>;
+ qcom,mdss-dsi-v-front-porch = <30>;
+ qcom,mdss-dsi-v-pulse-width = <8>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-on-command = [05 01 00 00 05 00 02 11 00
+ 39 01 00 00 00 00 05 2a 00 00 05 9f
+ 39 01 00 00 00 00 05 2b 00 00 09 ff
+ 39 01 00 00 00 00 03 f0 5a 5a
+ 39 01 00 00 00 00 02 b0 10
+ 39 01 00 00 00 00 02 b5 a0
+ 39 01 00 00 00 00 02 c4 03
+ 39 01 00 00 00 00 0a
+ f6 42 57 37 00 aa cc d0 00 00
+ 39 01 00 00 00 00 02 f9 03
+ 39 01 00 00 00 00 14
+ c2 00 00 d8 d8 00 80 2b 05 08
+ 0e 07 0b 05 0d 0a 15 13 20 1e
+ 39 01 00 00 78 00 03 f0 a5 a5
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 53 20
+ 39 01 00 00 00 00 02 51 60
+ 05 01 00 00 05 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 3c 00 02 28 00
+ 05 01 00 00 b4 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-lp-mode-on = [39 00 00 00 05 00 03 f0 5a 5a
+ 39 00 00 00 05 00 03 f1 5a 5a
+ 39 00 00 00 05 00 03 fc 5a 5a
+ 39 00 00 00 05 00 02 b0 17
+ 39 00 00 00 05 00 02 cb 10
+ 39 00 00 00 05 00 02 b0 2d
+ 39 00 00 00 05 00 02 cb cd
+ 39 00 00 00 05 00 02 b0 0e
+ 39 00 00 00 05 00 02 cb 02
+ 39 00 00 00 05 00 02 b0 0f
+ 39 00 00 00 05 00 02 cb 09
+ 39 00 00 00 05 00 02 b0 02
+ 39 00 00 00 05 00 02 f2 c9
+ 39 00 00 00 05 00 02 b0 03
+ 39 00 00 00 05 00 02 f2 c0
+ 39 00 00 00 05 00 02 b0 03
+ 39 00 00 00 05 00 02 f4 aa
+ 39 00 00 00 05 00 02 b0 08
+ 39 00 00 00 05 00 02 b1 30
+ 39 00 00 00 05 00 02 b0 09
+ 39 00 00 00 05 00 02 b1 0a
+ 39 00 00 00 05 00 02 b0 0d
+ 39 00 00 00 05 00 02 b1 10
+ 39 00 00 00 05 00 02 b0 00
+ 39 00 00 00 05 00 02 f7 03
+ 39 00 00 00 05 00 02 fe 30
+ 39 01 00 00 05 00 02 fe b0];
+ qcom,mdss-dsi-lp-mode-off = [39 00 00 00 05 00 03 f0 5a 5a
+ 39 00 00 00 05 00 03 f1 5a 5a
+ 39 00 00 00 05 00 03 fc 5a 5a
+ 39 00 00 00 05 00 02 b0 2d
+ 39 00 00 00 05 00 02 cb 4d
+ 39 00 00 00 05 00 02 b0 17
+ 39 00 00 00 05 00 02 cb 04
+ 39 00 00 00 05 00 02 b0 0e
+ 39 00 00 00 05 00 02 cb 06
+ 39 00 00 00 05 00 02 b0 0f
+ 39 00 00 00 05 00 02 cb 05
+ 39 00 00 00 05 00 02 b0 02
+ 39 00 00 00 05 00 02 f2 b8
+ 39 00 00 00 05 00 02 b0 03
+ 39 00 00 00 05 00 02 f2 80
+ 39 00 00 00 05 00 02 b0 03
+ 39 00 00 00 05 00 02 f4 8a
+ 39 00 00 00 05 00 02 b0 08
+ 39 00 00 00 05 00 02 b1 10
+ 39 00 00 00 05 00 02 b0 09
+ 39 00 00 00 05 00 02 b1 0a
+ 39 00 00 00 05 00 02 b0 0d
+ 39 00 00 00 05 00 02 b1 80
+ 39 00 00 00 05 00 02 b0 00
+ 39 00 00 00 05 00 02 f7 03
+ 39 00 00 00 05 00 02 fe 30
+ 39 01 00 00 05 00 02 fe b0];
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,dcs-cmd-by-left;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,mdss-pan-physical-width-dimension = <68>;
+ qcom,mdss-pan-physical-height-dimension = <122>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-1080p-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-1080p-cmd.dtsi
new file mode 100755
index 0000000..c78aa1c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-1080p-cmd.dtsi
@@ -0,0 +1,78 @@
+&mdss_mdp {
+ dsi_sharp_1080_cmd: qcom,mdss_dsi_sharp_1080p_cmd {
+ qcom,mdss-dsi-panel-name = "sharp 1080p cmd mode dsi panel";
+ qcom,mdss-dsi-panel-controller = <&mdss_dsi0>;
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-panel-destination = "display_1";
+ qcom,mdss-dsi-panel-clockrate = <850000000>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <64>;
+ qcom,mdss-pan-physical-height-dimension = <117>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <0>;
+ qcom,mdss-dsi-h-back-porch = <0>;
+ qcom,mdss-dsi-h-pulse-width = <0>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <0>;
+ qcom,mdss-dsi-v-front-porch = <0>;
+ qcom,mdss-dsi-v-pulse-width = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 b0 03
+ 05 01 00 00 78 00 01 11
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 24
+ 15 01 00 00 00 00 02 ff 23
+ 15 01 00 00 00 00 02 08 05
+ 15 01 00 00 00 00 02 46 90
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 ff f0
+ 15 01 00 00 00 00 02 92 01
+ 15 01 00 00 00 00 02 ff 10
+ /* enable TE generation */
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 28 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 40 00 01 10];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dsc-4k-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dsc-4k-cmd.dtsi
new file mode 100755
index 0000000..08c6a92
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dsc-4k-cmd.dtsi
@@ -0,0 +1,95 @@
+&mdss_mdp {
+ dsi_sharp_4k_dsc_cmd: qcom,mdss_dsi_sharp_4k_dsc_cmd {
+ qcom,mdss-dsi-panel-name = "Sharp 4k cmd mode dsc dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>;
+ qcom,mdss-pan-physical-width-dimension = <71>;
+ qcom,mdss-pan-physical-height-dimension = <129>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,dcs-cmd-by-left;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-jitter = <0x8 0xa>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <1080>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dsc-4k-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dsc-4k-video.dtsi
new file mode 100755
index 0000000..54894686
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dsc-4k-video.dtsi
@@ -0,0 +1,88 @@
+&mdss_mdp {
+ dsi_sharp_4k_dsc_video: qcom,mdss_dsi_sharp_4k_dsc_video {
+ qcom,mdss-dsi-panel-name = "Sharp 4k video mode dsc dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 100>, <0 100>, <1 100>;
+ qcom,mdss-pan-physical-width-dimension = <71>;
+ qcom,mdss-pan-physical-height-dimension = <129>;
+ qcom,mdss-dsi-tx-eot-append;
+
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 10
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <1080>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi
new file mode 100755
index 0000000..c909864d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi
@@ -0,0 +1,86 @@
+&mdss_mdp {
+ dsi_dual_sharp_wqhd_cmd: qcom,mdss_dsi_sharp_wqhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Dual Sharp WQHD cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,dcs-cmd-by-left;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-pan-physical-width-dimension = <68>;
+ qcom,mdss-pan-physical-height-dimension = <121>;
+
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09
+ 20 00 20 02 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ 15 01 00 00 00 00 02 90 01
+ 15 01 00 00 00 00 02 03 00
+ 15 01 00 00 00 00 02 58 01
+ 15 01 00 00 00 00 02 c9 00
+ 15 01 00 00 00 00 02 c0 15
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dualdsi-wqhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dualdsi-wqhd-video.dtsi
new file mode 100755
index 0000000..3733007
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dualdsi-wqhd-video.dtsi
@@ -0,0 +1,82 @@
+&mdss_mdp {
+ dsi_dual_sharp_wqhd_video: qcom,mdss_dsi_sharp_wqhd_video {
+ qcom,mdss-dsi-panel-name =
+ "Dual Sharp wqhd video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 20>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-pan-physical-width-dimension = <68>;
+ qcom,mdss-pan-physical-height-dimension = <121>;
+
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09
+ 20 00 20 02 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 10
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ 15 01 00 00 00 00 02 90 01
+ 15 01 00 00 00 00 02 03 00
+ 15 01 00 00 00 00 02 58 01
+ 15 01 00 00 00 00 02 c9 00
+ 15 01 00 00 00 00 02 c0 15
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ };
+ };
+ };
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi
new file mode 100755
index 0000000..06a95ca
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dualmipi-1080p-120hz.dtsi
@@ -0,0 +1,626 @@
+&mdss_mdp {
+ dsi_dual_sharp_1080_120hz_cmd: qcom,mdss_dual_sharp_1080p_120hz_cmd {
+ qcom,mdss-dsi-panel-name =
+ "sharp 1080p 120hz dual dsi cmd mode panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 10>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,cmd-sync-wait-broadcast;
+ qcom,cmd-sync-wait-trigger;
+ qcom,mdss-tear-check-frame-rate = <12000>;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <28>;
+ qcom,mdss-dsi-h-back-porch = <4>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <12>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+ qcom,mdss-dsi-on-command =
+ [15 01 00 00 00 00 02 ff 10
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+ 15 01 00 00 00 00 02 64 6c
+ 15 01 00 00 00 00 02 65 03
+ 15 01 00 00 00 00 02 66 74
+ 15 01 00 00 00 00 02 67 03
+ 15 01 00 00 00 00 02 68 80
+ 15 01 00 00 00 00 02 69 03
+ 15 01 00 00 00 00 02 6a 89
+ 15 01 00 00 00 00 02 6b 03
+ 15 01 00 00 00 00 02 6c 8b
+ 15 01 00 00 00 00 02 6d 03
+ 15 01 00 00 00 00 02 6e 8d
+ 15 01 00 00 00 00 02 6f 03
+ 15 01 00 00 00 00 02 70 8e
+ 15 01 00 00 00 00 02 71 00
+ 15 01 00 00 00 00 02 72 71
+ 15 01 00 00 00 00 02 73 00
+ 15 01 00 00 00 00 02 74 84
+ 15 01 00 00 00 00 02 75 00
+ 15 01 00 00 00 00 02 76 a5
+ 15 01 00 00 00 00 02 77 00
+ 15 01 00 00 00 00 02 78 bb
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 7a ce
+ 15 01 00 00 00 00 02 7b 00
+ 15 01 00 00 00 00 02 7c e0
+ 15 01 00 00 00 00 02 7d 00
+ 15 01 00 00 00 00 02 7e ef
+ 15 01 00 00 00 00 02 7f 00
+ 15 01 00 00 00 00 02 80 ff
+ 15 01 00 00 00 00 02 81 01
+ 15 01 00 00 00 00 02 82 0b
+ 15 01 00 00 00 00 02 83 01
+ 15 01 00 00 00 00 02 84 38
+ 15 01 00 00 00 00 02 85 01
+ 15 01 00 00 00 00 02 86 5b
+ 15 01 00 00 00 00 02 87 01
+ 15 01 00 00 00 00 02 88 95
+ 15 01 00 00 00 00 02 89 01
+ 15 01 00 00 00 00 02 8a c4
+ 15 01 00 00 00 00 02 8b 02
+ 15 01 00 00 00 00 02 8c 0d
+ 15 01 00 00 00 00 02 8d 02
+ 15 01 00 00 00 00 02 8e 4a
+ 15 01 00 00 00 00 02 8f 02
+ 15 01 00 00 00 00 02 90 4c
+ 15 01 00 00 00 00 02 91 02
+ 15 01 00 00 00 00 02 92 85
+ 15 01 00 00 00 00 02 93 02
+ 15 01 00 00 00 00 02 94 c3
+ 15 01 00 00 00 00 02 95 02
+ 15 01 00 00 00 00 02 96 e9
+ 15 01 00 00 00 00 02 97 03
+ 15 01 00 00 00 00 02 98 16
+ 15 01 00 00 00 00 02 99 03
+ 15 01 00 00 00 00 02 9a 34
+ 15 01 00 00 00 00 02 9b 03
+ 15 01 00 00 00 00 02 9c 56
+ 15 01 00 00 00 00 02 9d 03
+ 15 01 00 00 00 00 02 9e 62
+ 15 01 00 00 00 00 02 9f 03
+ 15 01 00 00 00 00 02 a0 6c
+ 15 01 00 00 00 00 02 a2 03
+ 15 01 00 00 00 00 02 a3 74
+ 15 01 00 00 00 00 02 a4 03
+ 15 01 00 00 00 00 02 a5 80
+ 15 01 00 00 00 00 02 a6 03
+ 15 01 00 00 00 00 02 a7 89
+ 15 01 00 00 00 00 02 a9 03
+ 15 01 00 00 00 00 02 aa 8b
+ 15 01 00 00 00 00 02 ab 03
+ 15 01 00 00 00 00 02 ac 8d
+ 15 01 00 00 00 00 02 ad 03
+ 15 01 00 00 00 00 02 ae 8e
+ 15 01 00 00 00 00 02 af 00
+ 15 01 00 00 00 00 02 b0 71
+ 15 01 00 00 00 00 02 b1 00
+ 15 01 00 00 00 00 02 b2 84
+ 15 01 00 00 00 00 02 b3 00
+ 15 01 00 00 00 00 02 b4 a5
+ 15 01 00 00 00 00 02 b5 00
+ 15 01 00 00 00 00 02 b6 bb
+ 15 01 00 00 00 00 02 b7 00
+ 15 01 00 00 00 00 02 b8 ce
+ 15 01 00 00 00 00 02 b9 00
+ 15 01 00 00 00 00 02 ba e0
+ 15 01 00 00 00 00 02 bb 00
+ 15 01 00 00 00 00 02 bc ef
+ 15 01 00 00 00 00 02 bd 00
+ 15 01 00 00 00 00 02 be ff
+ 15 01 00 00 00 00 02 bf 01
+ 15 01 00 00 00 00 02 c0 0b
+ 15 01 00 00 00 00 02 c1 01
+ 15 01 00 00 00 00 02 c2 38
+ 15 01 00 00 00 00 02 c3 01
+ 15 01 00 00 00 00 02 c4 5b
+ 15 01 00 00 00 00 02 c5 01
+ 15 01 00 00 00 00 02 c6 95
+ 15 01 00 00 00 00 02 c7 01
+ 15 01 00 00 00 00 02 c8 c4
+ 15 01 00 00 00 00 02 c9 02
+ 15 01 00 00 00 00 02 ca 0d
+ 15 01 00 00 00 00 02 cb 02
+ 15 01 00 00 00 00 02 cc 4a
+ 15 01 00 00 00 00 02 cd 02
+ 15 01 00 00 00 00 02 ce 4c
+ 15 01 00 00 00 00 02 cf 02
+ 15 01 00 00 00 00 02 d0 85
+ 15 01 00 00 00 00 02 d1 02
+ 15 01 00 00 00 00 02 d2 c3
+ 15 01 00 00 00 00 02 d3 02
+ 15 01 00 00 00 00 02 d4 e9
+ 15 01 00 00 00 00 02 d5 03
+ 15 01 00 00 00 00 02 d6 16
+ 15 01 00 00 00 00 02 d7 03
+ 15 01 00 00 00 00 02 d8 34
+ 15 01 00 00 00 00 02 d9 03
+ 15 01 00 00 00 00 02 da 56
+ 15 01 00 00 00 00 02 db 03
+ 15 01 00 00 00 00 02 dc 62
+ 15 01 00 00 00 00 02 dd 03
+ 15 01 00 00 00 00 02 de 6c
+ 15 01 00 00 00 00 02 df 03
+ 15 01 00 00 00 00 02 e0 74
+ 15 01 00 00 00 00 02 e1 03
+ 15 01 00 00 00 00 02 e2 80
+ 15 01 00 00 00 00 02 e3 03
+ 15 01 00 00 00 00 02 e4 89
+ 15 01 00 00 00 00 02 e5 03
+ 15 01 00 00 00 00 02 e6 8b
+ 15 01 00 00 00 00 02 e7 03
+ 15 01 00 00 00 00 02 e8 8d
+ 15 01 00 00 00 00 02 e9 03
+ 15 01 00 00 00 00 02 ea 8e
+ 15 01 00 00 00 00 02 FF 10
+ 05 01 00 00 00 00 01 29];
+ qcom,mdss-dsi-off-command =
+ [15 01 00 00 00 00 02 ff 10
+ 05 01 00 00 10 00 01 28
+ 15 01 00 00 00 00 02 b0 00
+ 05 01 00 00 40 00 01 10
+ 15 01 00 00 00 00 02 4f 01];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dualmipi-wqxga-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dualmipi-wqxga-video.dtsi
new file mode 100755
index 0000000..d0fafd5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-dualmipi-wqxga-video.dtsi
@@ -0,0 +1,71 @@
+&mdss_mdp {
+ dsi_dual_sharp_video: qcom,mdss_dsi_sharp_wqxga_video {
+ qcom,mdss-dsi-panel-name = "Dual SHARP video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <800>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <76>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <11>;
+ qcom,mdss-dsi-v-front-porch = <2>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-on-command = [05 01 00 00 a0 00 02 11 00
+ 05 01 00 00 02 00 02 29 00];
+ qcom,mdss-dsi-pre-off-command = [05 01 00 00 02 00 02 28 00
+ 05 01 00 00 a0 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,cmd-sync-wait-broadcast;
+ qcom,mdss-dsi-panel-timings = [e2 36 24 00 66 6a 28 38 2a 03
+ 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x02>;
+ qcom,mdss-dsi-t-clk-pre = <0x2a>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <50>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <2>;
+ qcom,mdss-dsi-reset-sequence = <1 2>, <0 5>, <1 120>;
+ qcom,mdss-pan-physical-width-dimension = <83>;
+ qcom,mdss-pan-physical-height-dimension = <133>;
+ qcom,mdss-dsi-min-refresh-rate = <53>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+ qcom,mdss-dsi-panel-status-check-mode = "bta_check";
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14880 15935 32435
+ 16555 14945 30910 7790 3415>;
+ qcom,mdss-dsi-panel-peak-brightness = <5643000>;
+ qcom,mdss-dsi-panel-blackness-level = <6134>;
+ qcom,config-select = <&dsi_dual_sharp_video_config0>;
+
+ dsi_dual_sharp_video_config0: config0 {
+ qcom,split-mode = "dualctl-split";
+ };
+
+ dsi_dual_sharp_video_config1: config1 {
+ qcom,split-mode = "pingpong-split";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-qsync-fhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-qsync-fhd-cmd.dtsi
new file mode 100755
index 0000000..fae031c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-qsync-fhd-cmd.dtsi
@@ -0,0 +1,361 @@
+&mdss_mdp {
+ dsi_sharp_qsync_fhd_cmd: qcom,mdss_dsi_sharp_qsync_fhd_cmd {
+ qcom,mdss-dsi-panel-name = "Sharp fhd cmd mode qsync dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+
+ qcom,mdss-dsi-panel-mode-switch;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <134>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-dma-schedule-line = <5>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750
+ 15800 13250 34450 7500 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <6450000>;
+ qcom,mdss-dsi-panel-blackness-level = <4961>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <20>;
+ qcom,mdss-dsi-h-back-porch = <12>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <16>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-jitter = <0x3 0x1>;
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 16 0a
+ 39 01 00 00 00 00 02 17 30
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ ];
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 03
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 10
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 14 00
+ 39 01 00 00 00 00 02 15 10
+ 39 01 00 00 00 00 02 16 0a
+ 39 01 00 00 00 00 02 17 30
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bc 00
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <20>;
+ qcom,mdss-dsi-h-back-porch = <12>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <16>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+ qcom,mdss-dsi-panel-jitter = <0x3 0x1>;
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 16 00
+ 39 01 00 00 00 00 02 17 10
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 00
+ ];
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 03
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 10
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 14 00
+ 39 01 00 00 00 00 02 15 10
+ 39 01 00 00 00 00 02 16 00
+ 39 01 00 00 00 00 02 17 10
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 00
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bc 00
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <20>;
+ qcom,mdss-dsi-h-back-porch = <12>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <16>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-panel-jitter = <0x3 0x1>;
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 16 03
+ 39 01 00 00 00 00 02 17 70
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 02
+ ];
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 03
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 10
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 14 00
+ 39 01 00 00 00 00 02 15 10
+ 39 01 00 00 00 00 02 16 03
+ 39 01 00 00 00 00 02 17 70
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bc 00
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-qsync-fhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-qsync-fhd-video.dtsi
new file mode 100755
index 0000000..185f326
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-qsync-fhd-video.dtsi
@@ -0,0 +1,119 @@
+&mdss_mdp {
+ dsi_sharp_qsync_fhd_video: qcom,mdss_dsi_sharp_qsync_fhd_video {
+ qcom,mdss-dsi-panel-name =
+ "Sharp fhd video mode qsync dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <134>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750
+ 15800 13250 34450 7500 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <6450000>;
+ qcom,mdss-dsi-panel-blackness-level = <4961>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <124>;
+ qcom,mdss-dsi-h-back-porch = <20>;
+ qcom,mdss-dsi-h-pulse-width = <20>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <1968>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 03
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 03
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 05 be 00 10 00 10
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bc 00
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-qsync-wqhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-qsync-wqhd-cmd.dtsi
new file mode 100755
index 0000000..215b3ab
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-qsync-wqhd-cmd.dtsi
@@ -0,0 +1,921 @@
+&mdss_mdp {
+ dsi_sharp_qsync_wqhd_cmd: qcom,mdss_dsi_sharp_qsync_wqhd_cmd {
+ qcom,mdss-dsi-panel-name = "Sharp 2k cmd mode qsync dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+
+ qcom,mdss-dsi-panel-mode-switch;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <134>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-dma-schedule-line = <5>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750
+ 15800 13250 34450 7500 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <6450000>;
+ qcom,mdss-dsi-panel-blackness-level = <4961>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-cmd-mode;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <20>;
+ qcom,mdss-dsi-h-back-porch = <12>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <16>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-jitter = <0x3 0x1>;
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 c0 83
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 68 00 d5 00 0a 0d b7 09 89
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 16 0a
+ 39 01 00 00 00 00 02 17 30
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 15 01 00 00 00 00 02 ff 10
+ 05 01 00 00 00 00 01 28
+ 05 01 00 00 00 00 01 29
+ ];
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 03
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 83
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 68 00 d5 00 0a 0d b7 09 89
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 10
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 14 00
+ 39 01 00 00 00 00 02 15 10
+ 39 01 00 00 00 00 02 16 0a
+ 39 01 00 00 00 00 02 17 30
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bc 00
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,cmd-to-video-mode-post-switch-commands = [
+ 39 00 00 00 00 00 02 ff 10
+ 39 00 00 00 00 00 02 fb 01
+ 39 00 00 00 00 00 02 bb 13
+ 39 00 00 00 00 00 02 ff 26
+ 39 00 00 00 00 00 02 fb 01
+ 39 00 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 06
+ ];
+ qcom,video-to-cmd-mode-post-switch-commands-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-video-mode;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <80>;
+ qcom,mdss-dsi-h-back-porch = <12>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <2608>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 03
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 83
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 68 00 d5 00 0a 0d b7 09 89
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 03
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 05 be 00 10 00 10
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bc 00
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,video-to-cmd-mode-switch-commands = [
+ 39 00 00 00 00 00 02 ff 10
+ 39 00 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 bb 10
+ ];
+ qcom,video-to-cmd-mode-post-switch-commands = [
+ 39 00 00 00 00 00 02 ff 10
+ 39 00 00 00 00 00 02 fb 01
+ 39 00 00 00 00 00 02 bb 10
+ 39 00 00 00 00 00 02 ff 26
+ 39 00 00 00 00 00 02 fb 01
+ 39 00 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 00
+ ];
+ qcom,video-to-cmd-mode-switch-commands-state =
+ "dsi_lp_mode";
+ qcom,video-to-cmd-mode-post-switch-commands-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <20>;
+ qcom,mdss-dsi-h-back-porch = <12>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <16>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-jitter = <0x3 0x1>;
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 16 0a
+ 39 01 00 00 00 00 02 17 30
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 15 01 00 00 00 00 02 ff 10
+ 05 01 00 00 00 00 01 28
+ 05 01 00 00 00 00 01 29
+ ];
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 03
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 10
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 14 00
+ 39 01 00 00 00 00 02 15 10
+ 39 01 00 00 00 00 02 16 0a
+ 39 01 00 00 00 00 02 17 30
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bc 00
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@3 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <20>;
+ qcom,mdss-dsi-h-back-porch = <12>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <16>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-panel-jitter = <0x3 0x1>;
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 c0 83
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 68 00 d5 00 0a 0d b7 09 89
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 16 03
+ 39 01 00 00 00 00 02 17 70
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 02
+ 15 01 00 00 00 00 02 ff 10
+ 05 01 00 00 00 00 01 28
+ 05 01 00 00 00 00 01 29
+ ];
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 03
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 83
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 68 00 d5 00 0a 0d b7 09 89
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 10
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 14 00
+ 39 01 00 00 00 00 02 15 10
+ 39 01 00 00 00 00 02 16 03
+ 39 01 00 00 00 00 02 17 70
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bc 00
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@4 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <20>;
+ qcom,mdss-dsi-h-back-porch = <12>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <16>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+ qcom,mdss-dsi-panel-jitter = <0x3 0x1>;
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 c0 83
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 68 00 d5 00 0a 0d b7 09 89
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 16 00
+ 39 01 00 00 00 00 02 17 10
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 03
+ 15 01 00 00 00 00 02 ff 10
+ 05 01 00 00 00 00 01 28
+ 05 01 00 00 00 00 01 29
+ ];
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 03
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 83
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 68 00 d5 00 0a 0d b7 09 89
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 10
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 14 00
+ 39 01 00 00 00 00 02 15 10
+ 39 01 00 00 00 00 02 16 00
+ 39 01 00 00 00 00 02 17 10
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,cmd-to-video-mode-post-switch-commands = [
+ 39 00 00 00 00 00 02 ff 10
+ 39 00 00 00 00 00 02 fb 01
+ 39 00 00 00 00 00 02 bb 13
+ 39 00 00 00 00 00 02 ff 26
+ 39 00 00 00 00 00 02 fb 01
+ 39 00 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 06
+ ];
+ qcom,video-to-cmd-mode-post-switch-commands-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bc 00
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@5 {
+ qcom,mdss-dsi-video-mode;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <20>;
+ qcom,mdss-dsi-h-back-porch = <12>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <16>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 03
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 83
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 68 00 d5 00 0a 0d b7 09 89
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 03
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 05 be 00 10 00 10
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bc 00
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,video-to-cmd-mode-switch-commands = [
+ 39 00 00 00 00 00 02 ff 10
+ 39 00 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 bb 10
+ ];
+ qcom,video-to-cmd-mode-post-switch-commands = [
+ 39 00 00 00 00 00 02 ff 10
+ 39 00 00 00 00 00 02 fb 01
+ 39 00 00 00 00 00 02 bb 10
+ 39 00 00 00 00 00 02 ff 26
+ 39 00 00 00 00 00 02 fb 01
+ 39 00 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 00
+ ];
+ qcom,video-to-cmd-mode-switch-commands-state =
+ "dsi_lp_mode";
+ qcom,video-to-cmd-mode-post-switch-commands-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@6 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <20>;
+ qcom,mdss-dsi-h-back-porch = <12>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <16>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+ qcom,mdss-dsi-panel-jitter = <0x3 0x1>;
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 16 00
+ 39 01 00 00 00 00 02 17 10
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 00
+ 15 01 00 00 00 00 02 ff 10
+ 05 01 00 00 00 00 01 28
+ 05 01 00 00 00 00 01 29
+ ];
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 03
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 10
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 14 00
+ 39 01 00 00 00 00 02 15 10
+ 39 01 00 00 00 00 02 16 00
+ 39 01 00 00 00 00 02 17 10
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 00
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bc 00
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@7 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <80>;
+ qcom,mdss-dsi-h-back-porch = <12>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <16>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-panel-jitter = <0x3 0x1>;
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 16 03
+ 39 01 00 00 00 00 02 17 70
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 02
+ 15 01 00 00 00 00 02 ff 10
+ 05 01 00 00 00 00 01 28
+ 05 01 00 00 00 00 01 29
+ ];
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 03
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 10
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 14 00
+ 39 01 00 00 00 00 02 15 10
+ 39 01 00 00 00 00 02 16 03
+ 39 01 00 00 00 00 02 17 70
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bc 00
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-qsync-wqhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-qsync-wqhd-video.dtsi
new file mode 100755
index 0000000..0268ded
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sharp-qsync-wqhd-video.dtsi
@@ -0,0 +1,120 @@
+&mdss_mdp {
+ dsi_sharp_qsync_wqhd_video: qcom,mdss_dsi_sharp_qsync_wqhd_video {
+ qcom,mdss-dsi-panel-name =
+ "Sharp 2k video mode qsync dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <74>;
+ qcom,mdss-pan-physical-height-dimension = <134>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <15000 16000 33750
+ 15800 13250 34450 7500 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <6450000>;
+ qcom,mdss-dsi-panel-blackness-level = <4961>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <80>;
+ qcom,mdss-dsi-h-back-porch = <12>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <2608>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 03
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 83
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 68 00 d5 00 0a 0d b7 09 89
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 03
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 05 be 00 10 00 10
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bc 00
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-cmd.dtsi
new file mode 100755
index 0000000..b0748f8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-cmd.dtsi
@@ -0,0 +1,346 @@
+&mdss_mdp {
+ dsi_sim_cmd: qcom,mdss_dsi_sim_cmd {
+ qcom,mdss-dsi-panel-name = "Simulator cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-panel-mode-switch;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-t-clk-post = <0x03>;
+ qcom,mdss-dsi-t-clk-pre = <0x27>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <100>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-cmd-mode;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,cmd-to-video-mode-switch-commands = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 07 01 00 00 00 00 02 01 00
+ 39 01 00 00 00 00 06 b2 00 5d 04 80 49
+ 15 01 00 00 00 00 02 3d 10
+ 15 01 00 00 00 00 02 36 00
+ 15 01 00 00 00 00 02 55 0c
+ ];
+ qcom,cmd-to-video-mode-switch-commands-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <100>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-video-mode;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,video-to-cmd-mode-switch-commands = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 07 01 00 00 00 00 02 01 00
+ 39 01 00 00 00 00 06 b2 00 5d 04 80 49
+ 15 01 00 00 00 00 02 3d 11
+ 15 01 00 00 00 00 02 36 00
+ 15 01 00 00 00 00 02 55 0b
+ ];
+ qcom,video-to-cmd-mode-switch-commands-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <100>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@3 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <460>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <740>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@4 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <840>;
+ qcom,mdss-dsi-h-pulse-width = <40>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <100>;
+ qcom,mdss-dsi-v-front-porch = <1380>;
+ qcom,mdss-dsi-v-pulse-width = <40>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 21 09 09 24 23 08 08 08 03 04 00];
+ qcom,mdss-dsi-on-command =
+ [29 01 00 00 00 00 02 b0 03
+ 05 01 00 00 0a 00 01 00
+ /* Soft reset, wait 10ms */
+ 15 01 00 00 0a 00 02 3a 77
+ /* Set Pixel format (24 bpp) */
+ 39 01 00 00 0a 00 05 2a 00 00 04 ff
+ /* Set Column address */
+ 39 01 00 00 0a 00 05 2b 00 00 05 9f
+ /* Set page address */
+ 15 01 00 00 0a 00 02 35 00
+ /* Set tear on */
+ 39 01 00 00 0a 00 03 44 00 00
+ /* Set tear scan line */
+ 15 01 00 00 0a 00 02 51 ff
+ /* write display brightness */
+ 15 01 00 00 0a 00 02 53 24
+ /* write control brightness */
+ 15 01 00 00 0a 00 02 55 00
+ /* CABC brightness */
+ 05 01 00 00 78 00 01 11
+ /* exit sleep mode, wait 120ms */
+ 05 01 00 00 10 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <40>;
+ qcom,mdss-dsc-slice-width = <360>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dsc-10bit-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dsc-10bit-cmd.dtsi
new file mode 100755
index 0000000..edb09ed
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dsc-10bit-cmd.dtsi
@@ -0,0 +1,473 @@
+&mdss_mdp {
+ dsi_sim_dsc_10b_cmd: qcom,mdss_dsi_sim_dsc_10b_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Simulator cmd mode DSC3:1 10bit dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <30>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f aE
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6d
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x0(2 Port SDC)
+ * 0x01(1 PortA FBC)
+ * 0x02(MTK) 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+
+ qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <10>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <0>;
+ qcom,mdss-dsi-h-back-porch = <0>;
+ qcom,mdss-dsi-h-pulse-width = <0>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <0>;
+ qcom,mdss-dsi-v-front-porch = <0>;
+ qcom,mdss-dsi-v-pulse-width = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 b0 03
+ 05 01 00 00 78 00 01 11
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 24
+ 15 01 00 00 00 00 02 ff 23
+ 15 01 00 00 00 00 02 08 05
+ 15 01 00 00 00 00 02 46 90
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 ff f0
+ 15 01 00 00 00 00 02 92 01
+ 15 01 00 00 00 00 02 ff 10
+ /* enable TE generation */
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 28 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 40 00 01 10];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <10>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f aE
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6d
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x0(2 Port SDC)
+ * 0x01(1 PortA FBC)
+ * 0x02(MTK) 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+
+ qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <10>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dsc375-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dsc375-cmd.dtsi
new file mode 100755
index 0000000..ce0faca
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dsc375-cmd.dtsi
@@ -0,0 +1,325 @@
+&mdss_mdp {
+ dsi_sim_dsc_375_cmd: qcom,mdss_dsi_sim_dsc_375_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Simulator cmd mode DSC 3.75:1 dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1e
+ 15 01 00 00 00 00 02 0b 73
+ 15 01 00 00 00 00 02 0c 73
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f aE
+ 15 01 00 00 00 00 02 11 b8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5a 00
+ 15 01 00 00 00 00 02 5b 01
+ 15 01 00 00 00 00 02 5c 80
+ 15 01 00 00 00 00 02 5d 81
+ 15 01 00 00 00 00 02 5e 00
+ 15 01 00 00 00 00 02 5f 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1c
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0f
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8a
+ 15 01 00 00 00 00 02 0a 13
+ 15 01 00 00 00 00 02 0b 13
+ 15 01 00 00 00 00 02 0c 15
+ 15 01 00 00 00 00 02 0d 15
+ 15 01 00 00 00 00 02 0e 17
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 1c
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0f
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8a
+ 15 01 00 00 00 00 02 1a 13
+ 15 01 00 00 00 00 02 1b 13
+ 15 01 00 00 00 00 02 1c 15
+ 15 01 00 00 00 00 02 1d 15
+ 15 01 00 00 00 00 02 1e 17
+ 15 01 00 00 00 00 02 1f 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 e0 00
+ 15 01 00 00 00 00 02 dc 21
+ 15 01 00 00 00 00 02 dd 22
+ 15 01 00 00 00 00 02 de 07
+ 15 01 00 00 00 00 02 df 07
+ 15 01 00 00 00 00 02 e3 6d
+ 15 01 00 00 00 00 02 e1 07
+ 15 01 00 00 00 00 02 e2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ /* CLK */
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 7f 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0a
+ 15 01 00 00 00 00 02 94 0a
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b ff
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9d b0
+ 15 01 00 00 00 00 02 9f 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 ec 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VESA DSC PPS settings
+ * (1440x2560 slide 16H)
+ */
+ 39 01 00 00 00 00 11 c1 09
+ 20 00 10 02 00 02 68 01 bb
+ 00 0a 06 67 04 c5
+
+ 39 01 00 00 00 00 03 c2 10 f0
+ /* C0h = 0x0(2 Port SDC)
+ * 0x01(1 PortA FBC)
+ * 0x02(MTK) 0x03(1 PortA VESA)
+ */
+ 15 01 00 00 00 00 02 c0 03
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3b 03 0a 0a
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 e5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 bb 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 fb 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+
+ qcom,mdss-dsi-on-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <0>;
+ qcom,mdss-dsi-h-back-porch = <0>;
+ qcom,mdss-dsi-h-pulse-width = <0>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <0>;
+ qcom,mdss-dsi-v-front-porch = <0>;
+ qcom,mdss-dsi-v-pulse-width = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 b0 03
+ 05 01 00 00 78 00 01 11
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 24
+ 15 01 00 00 00 00 02 ff 23
+ 15 01 00 00 00 00 02 08 05
+ 15 01 00 00 00 00 02 46 90
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 ff f0
+ 15 01 00 00 00 00 02 92 01
+ 15 01 00 00 00 00 02 ff 10
+ /* enable TE generation */
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 28 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 40 00 01 10];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <144>;
+ qcom,mdss-dsi-on-command = [
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 b0 03
+ 05 01 00 00 78 00 01 11
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 24
+ 15 01 00 00 00 00 02 ff 23
+ 15 01 00 00 00 00 02 08 05
+ 15 01 00 00 00 00 02 46 90
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 ff f0
+ 15 01 00 00 00 00 02 92 01
+ 15 01 00 00 00 00 02 ff 10
+ /* enable TE generation */
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 28 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 40 00 01 10];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dualmipi-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dualmipi-cmd.dtsi
new file mode 100755
index 0000000..6407ef2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dualmipi-cmd.dtsi
@@ -0,0 +1,140 @@
+&mdss_mdp {
+ dsi_dual_sim_cmd: qcom,mdss_dsi_dual_sim_cmd {
+ qcom,mdss-dsi-panel-name = "Sim dual cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,cmd-sync-wait-broadcast;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-hor-line-idle = <0 40 256>,
+ <40 120 128>,
+ <120 240 64>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,panel-ack-disabled;
+ qcom,mdss-dsi-qsync-min-refresh-rate = <45>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <28>;
+ qcom,mdss-dsi-h-back-porch = <4>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <12>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+ qcom,mdss-dsi-on-command =
+ [/* exit sleep mode, wait 0ms */
+ 05 01 00 00 00 00 01 29];
+ /* Set display on, wait 16ms */
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 00 00 02 28 00
+ 05 01 00 00 00 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_hs_mode";
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <1280>;
+ qcom,mdss-dsi-panel-height = <1440>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <44>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command =
+ [/* exit sleep mode, wait 0ms */
+ 05 01 00 00 00 00 01 29];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 00 00 02 28 00
+ 05 01 00 00 00 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_hs_mode";
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <40>;
+ qcom,mdss-dsi-on-command =
+ [/* exit sleep mode, wait 0ms */
+ 05 01 00 00 00 00 01 29];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 00 00 02 28 00
+ 05 01 00 00 00 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi
new file mode 100755
index 0000000..ef10fbd
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dualmipi-dsc375-cmd.dtsi
@@ -0,0 +1,1490 @@
+&mdss_mdp {
+ dsi_dual_sim_dsc_375_cmd: qcom,mdss_dsi_dual_sim_dsc_375_cmd {
+ qcom,mdss-dsi-panel-name =
+ "Sim dual cmd mode DSC 3.75:1 dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,cmd-sync-wait-broadcast;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-hor-line-idle = <0 40 256>,
+ <40 120 128>,
+ <120 240 64>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <30>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <1080>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <1080>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <90>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <1080>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@3 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <3840>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <1080>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@4 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <30>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@5 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@6 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <90>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@7 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@8 {
+ qcom,mdss-dsi-panel-framerate = <30>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1E
+ 15 01 00 00 00 00 02 0B 73
+ 15 01 00 00 00 00 02 0C 73
+ 15 01 00 00 00 00 02 0E B0
+ 15 01 00 00 00 00 02 0F AE
+ 15 01 00 00 00 00 02 11 B8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5A 00
+ 15 01 00 00 00 00 02 5B 01
+ 15 01 00 00 00 00 02 5C 80
+ 15 01 00 00 00 00 02 5D 81
+ 15 01 00 00 00 00 02 5E 00
+ 15 01 00 00 00 00 02 5F 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1C
+ 15 01 00 00 00 00 02 01 0B
+ 15 01 00 00 00 00 02 02 0C
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0F
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8A
+ 15 01 00 00 00 00 02 0A 13
+ 15 01 00 00 00 00 02 0B 13
+ 15 01 00 00 00 00 02 0C 15
+ 15 01 00 00 00 00 02 0D 15
+ 15 01 00 00 00 00 02 0E 17
+ 15 01 00 00 00 00 02 0F 17
+ 15 01 00 00 00 00 02 10 1C
+ 15 01 00 00 00 00 02 11 0B
+ 15 01 00 00 00 00 02 12 0C
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0F
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8A
+ 15 01 00 00 00 00 02 1A 13
+ 15 01 00 00 00 00 02 1B 13
+ 15 01 00 00 00 00 02 1C 15
+ 15 01 00 00 00 00 02 1D 15
+ 15 01 00 00 00 00 02 1E 17
+ 15 01 00 00 00 00 02 1F 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6D
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 E0 00
+ 15 01 00 00 00 00 02 DC 21
+ 15 01 00 00 00 00 02 DD 22
+ 15 01 00 00 00 00 02 DE 07
+ 15 01 00 00 00 00 02 DF 07
+ 15 01 00 00 00 00 02 E3 6D
+ 15 01 00 00 00 00 02 E1 07
+ 15 01 00 00 00 00 02 E2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 D8
+ 15 01 00 00 00 00 02 2A 2A
+ /* CLK */
+ 15 01 00 00 00 00 02 4B 03
+ 15 01 00 00 00 00 02 4C 11
+ 15 01 00 00 00 00 02 4D 10
+ 15 01 00 00 00 00 02 4E 01
+ 15 01 00 00 00 00 02 4F 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5B 43
+ 15 01 00 00 00 00 02 5C 00
+ 15 01 00 00 00 00 02 5F 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7A 80
+ 15 01 00 00 00 00 02 7B 91
+ 15 01 00 00 00 00 02 7C D8
+ 15 01 00 00 00 00 02 7D 60
+ 15 01 00 00 00 00 02 7F 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 B3 C0
+ 15 01 00 00 00 00 02 B4 00
+ 15 01 00 00 00 00 02 B5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0A
+ 15 01 00 00 00 00 02 94 0A
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8A 00
+ 15 01 00 00 00 00 02 9B FF
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9D B0
+ 15 01 00 00 00 00 02 9F 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 EC 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3B 03 0A 0A
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 E5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 BB 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 FB 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@9 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1E
+ 15 01 00 00 00 00 02 0B 73
+ 15 01 00 00 00 00 02 0C 73
+ 15 01 00 00 00 00 02 0E B0
+ 15 01 00 00 00 00 02 0F AE
+ 15 01 00 00 00 00 02 11 B8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5A 00
+ 15 01 00 00 00 00 02 5B 01
+ 15 01 00 00 00 00 02 5C 80
+ 15 01 00 00 00 00 02 5D 81
+ 15 01 00 00 00 00 02 5E 00
+ 15 01 00 00 00 00 02 5F 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1C
+ 15 01 00 00 00 00 02 01 0B
+ 15 01 00 00 00 00 02 02 0C
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0F
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8A
+ 15 01 00 00 00 00 02 0A 13
+ 15 01 00 00 00 00 02 0B 13
+ 15 01 00 00 00 00 02 0C 15
+ 15 01 00 00 00 00 02 0D 15
+ 15 01 00 00 00 00 02 0E 17
+ 15 01 00 00 00 00 02 0F 17
+ 15 01 00 00 00 00 02 10 1C
+ 15 01 00 00 00 00 02 11 0B
+ 15 01 00 00 00 00 02 12 0C
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0F
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8A
+ 15 01 00 00 00 00 02 1A 13
+ 15 01 00 00 00 00 02 1B 13
+ 15 01 00 00 00 00 02 1C 15
+ 15 01 00 00 00 00 02 1D 15
+ 15 01 00 00 00 00 02 1E 17
+ 15 01 00 00 00 00 02 1F 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6D
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 E0 00
+ 15 01 00 00 00 00 02 DC 21
+ 15 01 00 00 00 00 02 DD 22
+ 15 01 00 00 00 00 02 DE 07
+ 15 01 00 00 00 00 02 DF 07
+ 15 01 00 00 00 00 02 E3 6D
+ 15 01 00 00 00 00 02 E1 07
+ 15 01 00 00 00 00 02 E2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 D8
+ 15 01 00 00 00 00 02 2A 2A
+ /* CLK */
+ 15 01 00 00 00 00 02 4B 03
+ 15 01 00 00 00 00 02 4C 11
+ 15 01 00 00 00 00 02 4D 10
+ 15 01 00 00 00 00 02 4E 01
+ 15 01 00 00 00 00 02 4F 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5B 43
+ 15 01 00 00 00 00 02 5C 00
+ 15 01 00 00 00 00 02 5F 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7A 80
+ 15 01 00 00 00 00 02 7B 91
+ 15 01 00 00 00 00 02 7C D8
+ 15 01 00 00 00 00 02 7D 60
+ 15 01 00 00 00 00 02 7F 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 B3 C0
+ 15 01 00 00 00 00 02 B4 00
+ 15 01 00 00 00 00 02 B5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0A
+ 15 01 00 00 00 00 02 94 0A
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8A 00
+ 15 01 00 00 00 00 02 9B FF
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9D B0
+ 15 01 00 00 00 00 02 9F 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 EC 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3B 03 0A 0A
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 E5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 BB 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 FB 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@10 {
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1E
+ 15 01 00 00 00 00 02 0B 73
+ 15 01 00 00 00 00 02 0C 73
+ 15 01 00 00 00 00 02 0E B0
+ 15 01 00 00 00 00 02 0F AE
+ 15 01 00 00 00 00 02 11 B8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5A 00
+ 15 01 00 00 00 00 02 5B 01
+ 15 01 00 00 00 00 02 5C 80
+ 15 01 00 00 00 00 02 5D 81
+ 15 01 00 00 00 00 02 5E 00
+ 15 01 00 00 00 00 02 5F 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1C
+ 15 01 00 00 00 00 02 01 0B
+ 15 01 00 00 00 00 02 02 0C
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0F
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8A
+ 15 01 00 00 00 00 02 0A 13
+ 15 01 00 00 00 00 02 0B 13
+ 15 01 00 00 00 00 02 0C 15
+ 15 01 00 00 00 00 02 0D 15
+ 15 01 00 00 00 00 02 0E 17
+ 15 01 00 00 00 00 02 0F 17
+ 15 01 00 00 00 00 02 10 1C
+ 15 01 00 00 00 00 02 11 0B
+ 15 01 00 00 00 00 02 12 0C
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0F
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8A
+ 15 01 00 00 00 00 02 1A 13
+ 15 01 00 00 00 00 02 1B 13
+ 15 01 00 00 00 00 02 1C 15
+ 15 01 00 00 00 00 02 1D 15
+ 15 01 00 00 00 00 02 1E 17
+ 15 01 00 00 00 00 02 1F 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6D
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 E0 00
+ 15 01 00 00 00 00 02 DC 21
+ 15 01 00 00 00 00 02 DD 22
+ 15 01 00 00 00 00 02 DE 07
+ 15 01 00 00 00 00 02 DF 07
+ 15 01 00 00 00 00 02 E3 6D
+ 15 01 00 00 00 00 02 E1 07
+ 15 01 00 00 00 00 02 E2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 D8
+ 15 01 00 00 00 00 02 2A 2A
+ /* CLK */
+ 15 01 00 00 00 00 02 4B 03
+ 15 01 00 00 00 00 02 4C 11
+ 15 01 00 00 00 00 02 4D 10
+ 15 01 00 00 00 00 02 4E 01
+ 15 01 00 00 00 00 02 4F 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5B 43
+ 15 01 00 00 00 00 02 5C 00
+ 15 01 00 00 00 00 02 5F 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7A 80
+ 15 01 00 00 00 00 02 7B 91
+ 15 01 00 00 00 00 02 7C D8
+ 15 01 00 00 00 00 02 7D 60
+ 15 01 00 00 00 00 02 7F 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 B3 C0
+ 15 01 00 00 00 00 02 B4 00
+ 15 01 00 00 00 00 02 B5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0A
+ 15 01 00 00 00 00 02 94 0A
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8A 00
+ 15 01 00 00 00 00 02 9B FF
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9D B0
+ 15 01 00 00 00 00 02 9F 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 EC 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3B 03 0A 0A
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 E5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 BB 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 FB 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@11 {
+ qcom,mdss-dsi-panel-framerate = <120>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <2560>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <32>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-on-command = [
+ /* CMD2_P0 */
+ 15 01 00 00 00 00 02 FF 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 05 40
+ 15 01 00 00 00 00 02 06 19
+ 15 01 00 00 00 00 02 07 1E
+ 15 01 00 00 00 00 02 0B 73
+ 15 01 00 00 00 00 02 0C 73
+ 15 01 00 00 00 00 02 0E B0
+ 15 01 00 00 00 00 02 0F AE
+ 15 01 00 00 00 00 02 11 B8
+ 15 01 00 00 00 00 02 13 00
+ 15 01 00 00 00 00 02 58 80
+ 15 01 00 00 00 00 02 59 01
+ 15 01 00 00 00 00 02 5A 00
+ 15 01 00 00 00 00 02 5B 01
+ 15 01 00 00 00 00 02 5C 80
+ 15 01 00 00 00 00 02 5D 81
+ 15 01 00 00 00 00 02 5E 00
+ 15 01 00 00 00 00 02 5F 01
+ 15 01 00 00 00 00 02 72 31
+ 15 01 00 00 00 00 02 68 03
+ /* CMD2_P4 */
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 1C
+ 15 01 00 00 00 00 02 01 0B
+ 15 01 00 00 00 00 02 02 0C
+ 15 01 00 00 00 00 02 03 01
+ 15 01 00 00 00 00 02 04 0F
+ 15 01 00 00 00 00 02 05 10
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 89
+ 15 01 00 00 00 00 02 09 8A
+ 15 01 00 00 00 00 02 0A 13
+ 15 01 00 00 00 00 02 0B 13
+ 15 01 00 00 00 00 02 0C 15
+ 15 01 00 00 00 00 02 0D 15
+ 15 01 00 00 00 00 02 0E 17
+ 15 01 00 00 00 00 02 0F 17
+ 15 01 00 00 00 00 02 10 1C
+ 15 01 00 00 00 00 02 11 0B
+ 15 01 00 00 00 00 02 12 0C
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 0F
+ 15 01 00 00 00 00 02 15 10
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 89
+ 15 01 00 00 00 00 02 19 8A
+ 15 01 00 00 00 00 02 1A 13
+ 15 01 00 00 00 00 02 1B 13
+ 15 01 00 00 00 00 02 1C 15
+ 15 01 00 00 00 00 02 1D 15
+ 15 01 00 00 00 00 02 1E 17
+ 15 01 00 00 00 00 02 1F 17
+ /* STV */
+ 15 01 00 00 00 00 02 20 40
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6D
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ /* Vend */
+ 15 01 00 00 00 00 02 E0 00
+ 15 01 00 00 00 00 02 DC 21
+ 15 01 00 00 00 00 02 DD 22
+ 15 01 00 00 00 00 02 DE 07
+ 15 01 00 00 00 00 02 DF 07
+ 15 01 00 00 00 00 02 E3 6D
+ 15 01 00 00 00 00 02 E1 07
+ 15 01 00 00 00 00 02 E2 07
+ /* UD */
+ 15 01 00 00 00 00 02 29 D8
+ 15 01 00 00 00 00 02 2A 2A
+ /* CLK */
+ 15 01 00 00 00 00 02 4B 03
+ 15 01 00 00 00 00 02 4C 11
+ 15 01 00 00 00 00 02 4D 10
+ 15 01 00 00 00 00 02 4E 01
+ 15 01 00 00 00 00 02 4F 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 55 25
+ /* Reset XDONB */
+ 15 01 00 00 00 00 02 5B 43
+ 15 01 00 00 00 00 02 5C 00
+ 15 01 00 00 00 00 02 5F 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ /* Resolution:1440x2560*/
+ 15 01 00 00 00 00 02 72 02
+ /* mux */
+ 15 01 00 00 00 00 02 7A 80
+ 15 01 00 00 00 00 02 7B 91
+ 15 01 00 00 00 00 02 7C D8
+ 15 01 00 00 00 00 02 7D 60
+ 15 01 00 00 00 00 02 7F 15
+ 15 01 00 00 00 00 02 75 15
+ /* ABOFF */
+ 15 01 00 00 00 00 02 B3 C0
+ 15 01 00 00 00 00 02 B4 00
+ 15 01 00 00 00 00 02 B5 00
+ /* Source EQ */
+ 15 01 00 00 00 00 02 78 00
+ 15 01 00 00 00 00 02 79 00
+ 15 01 00 00 00 00 02 80 00
+ 15 01 00 00 00 00 02 83 00
+ /* FP BP */
+ 15 01 00 00 00 00 02 93 0A
+ 15 01 00 00 00 00 02 94 0A
+ /* Inversion Type */
+ 15 01 00 00 00 00 02 8A 00
+ 15 01 00 00 00 00 02 9B FF
+ /* IMGSWAP =1 @PortSwap=1 */
+ 15 01 00 00 00 00 02 9D B0
+ 15 01 00 00 00 00 02 9F 63
+ 15 01 00 00 00 00 02 98 10
+ /* FRM */
+ 15 01 00 00 00 00 02 EC 00
+ /* CMD1 */
+ 15 01 00 00 00 00 02 ff 10
+ /* VBP+VSA=,VFP = 10H */
+ 15 01 00 00 00 00 04 3B 03 0A 0A
+ /* FTE on */
+ 15 01 00 00 00 00 02 35 00
+ /* EN_BK =1(auto black) */
+ 15 01 00 00 00 00 02 E5 01
+ /* CMD mode(10) VDO mode(03) */
+ 15 01 00 00 00 00 02 BB 10
+ /* Non Reload MTP */
+ 15 01 00 00 00 00 02 FB 01
+ /* SlpOut + DispOn */
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <16>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@12 {
+ qcom,mdss-dsi-panel-width = <2520>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <1080>;
+ qcom,mdss-dsc-slice-width = <1260>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@13 {
+ qcom,mdss-dsi-panel-width = <360>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <30>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <360>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@14 {
+ qcom,mdss-dsi-panel-width = <360>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <360>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@15 {
+ qcom,mdss-dsi-panel-width = <360>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <90>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <360>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@16 {
+ qcom,mdss-dsi-panel-width = <360>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <120>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <360>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <10>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@17 {
+ qcom,mdss-dsi-panel-width = <540>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <30>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <4>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <7>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <144>;
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 11 91 09 20 00 20 02
+ 00 03 1c 04 21 00
+ 0f 03 19 01 97
+ 39 01 00 00 00 00 03 92 10 f0
+ 15 01 00 00 00 00 02 90 03
+ 15 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 04
+ 15 01 00 00 00 00 02 c0 03
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 07
+ 15 01 00 00 00 00 02 ef 01
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 00
+ 15 01 00 00 00 00 02 b4 01
+ 15 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 39 01 00 00 00 00 05 ff aa 55 a5 80
+ 15 01 00 00 00 00 02 6f 01
+ 15 01 00 00 00 00 02 f3 10
+ 39 01 00 00 00 00 05 ff aa 55 a5 00
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <32>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dualmipi-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dualmipi-video.dtsi
new file mode 100755
index 0000000..9121f2c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-dualmipi-video.dtsi
@@ -0,0 +1,62 @@
+&mdss_mdp {
+ dsi_dual_sim_vid: qcom,mdss_dsi_dual_sim_video {
+ qcom,mdss-dsi-panel-name = "Sim dual video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-panel-broadcast-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 200>, <1 20>;
+ qcom,panel-ack-disabled;
+ qcom,mdss-dsi-qsync-min-refresh-rate = <45>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1280>;
+ qcom,mdss-dsi-panel-height = <1440>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <44>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <4>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command =
+ [05 01 00 00 32 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_hs_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 51 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-sec-hd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-sec-hd-cmd.dtsi
new file mode 100755
index 0000000..973dc51
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-sec-hd-cmd.dtsi
@@ -0,0 +1,67 @@
+&mdss_mdp {
+ dsi_sim_sec_hd_cmd: qcom,mdss_dsi_sim_sec_hd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "sim hd command mode secondary dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-sec-ctrl-num = <1>;
+ qcom,dsi-sec-phy-num = <1>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,panel-ack-disabled;
+ qcom,mdss-dsi-te-using-wd;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-post-init-delay = <1>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <2>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+
+ qcom,mdss-dsi-on-command = [
+ /* sleep out + delay 120ms */
+ 05 01 00 00 78 00 01 11
+ /* display on + delay 120ms */
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 78 00 02 28 00
+ 05 01 00 00 78 00 02 10 00
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-video.dtsi
new file mode 100755
index 0000000..f5a522b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sim-video.dtsi
@@ -0,0 +1,61 @@
+&mdss_mdp {
+ dsi_sim_vid: qcom,mdss_dsi_sim_video {
+ qcom,mdss-dsi-panel-name = "Simulator video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-t-clk-post = <0x04>;
+ qcom,mdss-dsi-t-clk-pre = <0x1b>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 0>, <0 0>, <1 0>;
+ qcom,panel-ack-disabled;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <640>;
+ qcom,mdss-dsi-panel-height = <480>;
+ qcom,mdss-dsi-h-front-porch = <8>;
+ qcom,mdss-dsi-h-back-porch = <8>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <6>;
+ qcom,mdss-dsi-v-front-porch = <6>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-timings =
+ [00 00 00 00 00 00 00 00 00 00 00 00];
+ qcom,mdss-dsi-on-command =
+ [32 01 00 00 00 00 02 00 00];
+ qcom,mdss-dsi-off-command =
+ [22 01 00 00 00 00 02 00 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi
new file mode 100755
index 0000000..4d77525
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi
@@ -0,0 +1,102 @@
+&mdss_mdp {
+ dsi_sw43404_amoled_fhd_plus_cmd: qcom,mdss_dsi_sw43404_fhd_plus_cmd {
+ qcom,mdss-dsi-panel-name =
+ "sw43404 amoled boe fhd+ panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-physical-type = "oled";
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-pan-physical-width-dimension = <68>;
+ qcom,mdss-pan-physical-height-dimension = <138>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <160>;
+ qcom,mdss-dsi-h-back-porch = <72>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x3 0x1>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 07 01 00 00 00 00 02 01 00
+ 0a 01 00 00 00 00 80 11 00 00 89 30 80
+ 08 70 04 38 02 1c 02 1c 02 1c 02 00
+ 02 0e 00 20 34 29 00 07 00 0C 00 2e
+ 00 31 18 00 10 F0 03 0C 20 00 06 0B
+ 0B 33 0E 1C 2A 38 46 54 62 69 70 77
+ 79 7B 7D 7E 01 02 01 00 09 40 09 BE
+ 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6
+ 2A F6 2B 34 2B 74 3B 74 6B F4 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 15 01 00 00 00 00 02 5e 10
+ 39 01 00 00 00 00 06 b9 bf 11 40 00 30
+ 39 01 00 00 00 00 09 F8 00 08 10 08 2D
+ 00 00 2D
+ 15 01 00 00 00 00 02 55 08
+ 05 01 00 00 1e 00 02 11 00
+ 15 01 00 00 78 00 02 3d 01
+ 39 01 00 00 00 00 03 b0 a5 00
+ 05 01 00 00 78 00 02 35 00
+ 05 01 00 00 3c 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <270>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi
new file mode 100755
index 0000000..1c08e19
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi
@@ -0,0 +1,311 @@
+&mdss_mdp {
+ dsi_sw43404_amoled_cmd: qcom,mdss_dsi_sw43404_amoled_wqhd_cmd {
+ qcom,mdss-dsi-panel-name =
+ "sw43404 amoled cmd mode dsi boe panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-physical-type = "oled";
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+ qcom,mdss-dsi-qsync-min-refresh-rate = <55>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2880>;
+ qcom,mdss-dsi-h-front-porch = <60>;
+ qcom,mdss-dsi-h-back-porch = <30>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <8>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x6 0x1>;
+ qcom,mdss-mdp-transfer-time-us = <15300>;
+
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 0c b1 a0 9f 42 4f 63 0e 0a 10 0e 0a 10
+ 39 01 00 00 00 00 07 e4 30 06 00 40 34 03
+ ];
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 03 5c 42 00
+ 07 01 00 00 00 00 02 01 00
+ 0a 01 00 00 00 00 80 11 00 00 89 30 80
+ 0B 40 05 A0 05 A0 02 D0 02 D0 02 00
+ 02 68 00 20 9A DB 00 0A 00 0C 00 12
+ 00 0E 18 00 10 F0 03 0C 20 00 06 0B
+ 0B 33 0E 1C 2A 38 46 54 62 69 70 77
+ 79 7B 7D 7E 01 02 01 00 09 40 09 BE
+ 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6
+ 2A F6 2B 34 2B 74 3B 74 6B F4 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 09 F8 00 08 10 08 2D
+ 00 00 2D
+ 15 01 00 00 00 00 02 55 08
+ 05 01 00 00 1e 00 02 11 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 15 01 00 00 00 00 02 e0 18
+ 39 01 00 00 00 00 0c c0 00 53 6f 51 50
+ 51 34 4f 5a 33 19
+ 05 01 00 00 78 00 02 35 00
+ 05 01 00 00 3c 00 02 29 00
+ ];
+
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 5a 01];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 5a 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-lp1-command = [
+ 05 01 00 00 00 00 02 39 00
+ ];
+ qcom,mdss-dsi-lp1-command-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-nolp-command = [
+ 05 01 00 00 00 00 02 38 00
+ ];
+ qcom,mdss-dsi-nolp-command-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <180>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-framerate = <50>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2880>;
+ qcom,mdss-dsi-h-front-porch = <60>;
+ qcom,mdss-dsi-h-back-porch = <30>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <10>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10
+ 39 01 00 00 00 00 07 e4 30 06 00 40 34 03
+ ];
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 03 5c 42 00
+ 07 01 00 00 00 00 02 01 00
+ 0a 01 00 00 00 00 80 11 00 00 89 30 80
+ 0B 40 05 A0 05 A0 02 D0 02 D0 02 00
+ 02 68 00 20 9A DB 00 0A 00 0C 00 12
+ 00 0E 18 00 10 F0 03 0C 20 00 06 0B
+ 0B 33 0E 1C 2A 38 46 54 62 69 70 77
+ 79 7B 7D 7E 01 02 01 00 09 40 09 BE
+ 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6
+ 2A F6 2B 34 2B 74 3B 74 6B F4 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 09 F8 00 08 10 08 2D
+ 00 00 2D
+ 15 01 00 00 00 00 02 55 00
+ 05 01 00 00 1e 00 02 11 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 15 01 00 00 00 00 02 e0 18
+ 39 01 00 00 00 00 0c c0 00 53 6f 51 50
+ 51 34 4f 5a 33 19
+ 05 01 00 00 78 00 02 35 00
+ 05 01 00 00 3c 00 02 29 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10
+ 39 01 00 00 00 00 07 e4 30 06 00 40 34 03
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10
+ 39 01 00 00 00 00 07 e4 30 06 00 40 34 03
+ ];
+
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 5a 01];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 5a 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-lp1-command = [
+ 05 01 00 00 00 00 02 39 00
+ ];
+ qcom,mdss-dsi-lp1-command-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-nolp-command = [
+ 05 01 00 00 00 00 02 38 00
+ ];
+ qcom,mdss-dsi-nolp-command-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <180>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-framerate = <40>;
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2880>;
+ qcom,mdss-dsi-h-front-porch = <60>;
+ qcom,mdss-dsi-h-back-porch = <30>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <12>;
+ qcom,mdss-dsi-v-front-porch = <8>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+
+ qcom,mdss-dsi-timing-switch-command = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 0c b1 a0 9f 63 4f 63 0e 0a 10 0e 0a 10
+ 39 01 00 00 00 00 07 e4 30 06 00 40 34 03
+ ];
+
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 03 5c 42 00
+ 07 01 00 00 00 00 02 01 00
+ 0a 01 00 00 00 00 80 11 00 00 89 30 80
+ 0B 40 05 A0 05 A0 02 D0 02 D0 02 00
+ 02 68 00 20 9A DB 00 0A 00 0C 00 12
+ 00 0E 18 00 10 F0 03 0C 20 00 06 0B
+ 0B 33 0E 1C 2A 38 46 54 62 69 70 77
+ 79 7B 7D 7E 01 02 01 00 09 40 09 BE
+ 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6
+ 2A F6 2B 34 2B 74 3B 74 6B F4 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 09 F8 00 08 10 08 2D
+ 00 00 2D
+ 15 01 00 00 00 00 02 55 00
+ 05 01 00 00 1e 00 02 11 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 15 01 00 00 00 00 02 e0 18
+ 39 01 00 00 00 00 0c c0 00 53 6f 51 50
+ 51 34 4f 5a 33 19
+ 05 01 00 00 78 00 02 35 00
+ 05 01 00 00 3c 00 02 29 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 0c b1 a0 9f 4f 4f 63 0e 0a 10 0e 0a 10
+ 39 01 00 00 00 00 07 e4 30 06 00 40 34 03
+ 39 01 00 00 00 00 03 b0 a5 00
+ 39 01 00 00 00 00 0c b1 a0 9f 63 4f 63 0e 0a 10 0e 0a 10
+ 39 01 00 00 00 00 07 e4 30 06 00 40 34 03
+ ];
+
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-qsync-on-commands =
+ [15 01 00 00 00 00 02 5a 01];
+ qcom,mdss-dsi-qsync-on-commands-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-qsync-off-commands =
+ [15 01 00 00 00 00 02 5a 00];
+ qcom,mdss-dsi-qsync-off-commands-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-lp1-command = [
+ 05 01 00 00 00 00 02 39 00
+ ];
+ qcom,mdss-dsi-lp1-command-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-nolp-command = [
+ 05 01 00 00 00 00 02 38 00
+ ];
+ qcom,mdss-dsi-nolp-command-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <180>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi
new file mode 100755
index 0000000..ecac0d4
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi
@@ -0,0 +1,100 @@
+&mdss_mdp {
+ dsi_sw43404_amoled_video: qcom,mdss_dsi_sw43404_amoled_wqhd_video {
+ qcom,mdss-dsi-panel-name =
+ "sw43404 amoled video mode dsi boe panel with DSC";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-physical-type = "oled";
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,adjust-timer-wakeup-ms = <1>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <2880>;
+ qcom,mdss-dsi-h-front-porch = <10>;
+ qcom,mdss-dsi-h-back-porch = <10>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <10>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 03 b0 a5 00
+ 07 01 00 00 00 00 02 01 00
+ 39 01 00 00 00 00 06 b2 00 5d 04 80 49
+ 15 01 00 00 00 00 02 3d 10
+ 15 01 00 00 00 00 02 36 00
+ 15 01 00 00 00 00 02 55 08
+ 39 01 00 00 00 00 09 f8 00 08 10 08 2d
+ 00 00 2d
+ 39 01 00 00 3c 00 03 51 00 00
+ 05 01 00 00 50 00 02 11 00
+ 39 01 00 00 00 00 03 b0 34 04
+ 39 01 00 00 00 00 05 c1 00 00 00 46
+ 39 01 00 00 00 00 03 b0 a5 00
+ 0a 01 00 00 00 00 80 11 00 00 89 30 80
+ 0B 40 05 A0 02 d0 02 D0 02 D0 02 00
+ 02 68 00 20 4e a8 00 0A 00 0C 00 23
+ 00 1c 18 00 10 F0 03 0C 20 00 06 0B
+ 0B 33 0E 1C 2A 38 46 54 62 69 70 77
+ 79 7B 7D 7E 01 02 01 00 09 40 09 BE
+ 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6
+ 2A F6 2B 34 2B 74 3B 74 6B F4 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 39 01 00 00 00 00 03 b0 a5 00
+ 15 01 00 00 00 00 02 e0 18
+ 39 01 00 00 00 00 0c c0 00 53 6f 51 50
+ 51 34 4f 5a 33 19
+ 05 01 00 00 78 00 02 29 00
+ ];
+ qcom,mdss-dsi-off-command = [05 01 00 00 78 00
+ 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-lp1-command = [
+ 05 01 00 00 00 00 02 39 00
+ ];
+ qcom,mdss-dsi-lp1-command-state =
+ "dsi_lp_mode";
+ qcom,mdss-dsi-nolp-command = [
+ 05 01 00 00 00 00 02 38 00
+ ];
+ qcom,mdss-dsi-nolp-command-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <180>;
+ qcom,mdss-dsc-slice-width = <720>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-td4328-1080p-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-td4328-1080p-cmd.dtsi
new file mode 100755
index 0000000..476c34c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-td4328-1080p-cmd.dtsi
@@ -0,0 +1,169 @@
+&mdss_mdp {
+ dsi_td4328_truly_cmd: qcom,mdss_dsi_td4328_truly_cmd {
+ qcom,mdss-dsi-panel-name =
+ "td4328 cmd mode dsi truly panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <70>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <10>;
+ qcom,mdss-dsi-v-front-porch = <5>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+ qcom,mdss-dsi-on-command = [
+ 29 01 00 00 00 00 02 B0 00
+ 29 01 00 00 00 00 04 B3 00 00 06
+ 29 01 00 00 00 00 02 B4 00
+ 29 01 00 00 00 00 06 B6 33 DB 80 12 00
+ 29 01 00 00 00 00 08 B8 57 3D 19 1E 0A
+ 50 50
+ 29 01 00 00 00 00 08 B9 6F 3D 28 3C 14
+ C8 C8
+ 29 01 00 00 00 00 08 BA B5 33 41 64 23
+ A0 A0
+ 29 01 00 00 00 00 03 BB 14 14
+ 29 01 00 00 00 00 03 BC 37 32
+ 29 01 00 00 00 00 03 BD 64 32
+ 29 01 00 00 00 00 02 BE 04
+ 29 01 00 00 00 00 02 C0 00
+ 29 01 00 00 00 00 2E C1 04 48 00 00 26
+ 15 19 0B 63 D2 D9 9A 73 EF BD E7 5C
+ 6B 93 4D 22 18 8B 2A 41 00 00 00 00
+ 00 00 00 00 00 40 02 22 1B 06 03 00
+ 07 FF 00 01
+ 29 01 00 00 00 00 18 C2 01 F8 70 08 68
+ 08 0C 10 00 08 30 00 00 00 00 00 00
+ 20 02 43 00 00 00
+ 29 01 00 00 00 00 3F C3 87 D8 7D 87 D0
+ 00 00 00 00 00 00 04 3A 00 00 00 04
+ 44 00 00 01 01 03 28 00 01 00 01 00
+ 00 19 00 0C 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 32 00 19 00 5A
+ 02 32 00 19 00 5A 02 40 00
+ 29 01 00 00 00 00 15 C4 70 00 00 00 11
+ 11 00 00 00 02 02 31 01 00 00 00 02
+ 01 01 01
+ 29 01 00 00 00 00 08 C5 08 00 00 00 00
+ 70 00
+ 29 01 00 00 00 00 40 C6 5B 2D 2D 07 54
+ 07 54 01 02 01 02 07 07 00 00 07 07
+ 0F 11 07 5B 00 5B 5B C2 C2 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 27 C7 01 1D 2E 41 4F
+ 5A 71 80 8B 95 45 4F 5C 71 7B 88 98
+ A6 BE 01 1D 2E 41 4F 5A 71 80 8B 95
+ 45 4F 5C 71 7B 88 98 A6 BE
+ 29 01 00 00 00 00 38 C8 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00
+ 29 01 00 00 00 00 14 C9 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00
+ 29 01 00 00 00 00 2C CA 1C FC FC FC 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 1C CB FF FF FF FF 0F
+ 00 08 00 01 00 31 F0 40 08 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 02 CC 02
+ 29 01 00 00 00 00 27 CD 10 80 37 C0 1A
+ 00 5C 02 19 90 11 88 D8 6C D8 6C 01
+ 00 00 00 32 00 32 00 5D 02 32 32 01
+ 33 00 33 00 5E 02 32 32 AF
+ 29 01 00 00 00 00 1A CE 5D 40 49 53 59
+ 5E 63 68 6E 74 7E 8A 98 A8 BB D0 FF
+ 04 00 04 04 42 00 69 5A
+ 29 01 00 00 00 00 03 CF 4A 1D
+ 29 01 00 00 00 00 12 D0 33 57 D4 31 01
+ 10 10 10 19 19 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 02 D1 00
+ 29 01 00 00 00 00 20 D2 10 00 00 10 75
+ 0F 03 25 20 00 00 00 00 00 00 00 00
+ 04 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 17 D3 1B 3B BB 77 77
+ 77 BB B3 33 00 00 6D 6E C7 C7 33 BB
+ F2 FD C6 0B 07
+ 29 01 00 00 00 00 08 D4 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 08 D5 03 00 00 02 2B
+ 02 2B
+ 29 01 00 00 00 00 02 D6 01
+ 29 01 00 00 00 00 22 D7 F6 FF 03 05 41
+ 24 80 1F C7 1F 1B 00 0C 07 20 00 00
+ 00 00 00 0C 00 1F 00 FC 00 00 AA 67
+ 7E 5D 06 00
+ 29 01 00 00 00 00 03 D9 20 14
+ 29 01 00 00 00 00 05 DD 30 06 23 65
+ 29 01 00 00 00 00 05 DE 00 3F FF 50
+ 29 01 00 00 00 00 06 E7 00 00 00 46 61
+ 29 01 00 00 00 00 02 EA 1F
+ 29 01 00 00 00 00 04 EE 41 51 00
+ 29 01 00 00 00 00 03 F1 00 00
+ 39 01 00 00 00 00 05 2A 00 00 04 37
+ 39 01 00 00 00 00 05 2B 00 00 08 6F
+ 39 01 00 00 00 00 01 2C
+ 29 01 00 00 00 00 02 B0 00
+ 39 01 00 00 00 00 02 51 FF
+ 39 01 00 00 00 00 02 53 0C
+ 39 01 00 00 00 00 02 55 00
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 96 00 01 11
+ 05 01 00 00 32 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-td4328-1080p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-td4328-1080p-video.dtsi
new file mode 100755
index 0000000..e9b7bac
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-td4328-1080p-video.dtsi
@@ -0,0 +1,164 @@
+&mdss_mdp {
+ dsi_td4328_truly_video: qcom,mdss_dsi_td4328_truly_video {
+ qcom,mdss-dsi-panel-name =
+ "td4328 video mode dsi truly panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,dsi-select-clocks = "src_byte_clk0", "src_pixel_clk0";
+
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <70>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <10>;
+ qcom,mdss-dsi-v-front-porch = <5>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 29 01 00 00 00 00 02 B0 00
+ 29 01 00 00 00 00 04 B3 31 00 06
+ 29 01 00 00 00 00 02 B4 00
+ 29 01 00 00 00 00 06 B6 33 DB 80 12 00
+ 29 01 00 00 00 00 08 B8 57 3D 19 1E 0A
+ 50 50
+ 29 01 00 00 00 00 08 B9 6F 3D 28 3C 14
+ C8 C8
+ 29 01 00 00 00 00 08 BA B5 33 41 64 23
+ A0 A0
+ 29 01 00 00 00 00 03 BB 14 14
+ 29 01 00 00 00 00 03 BC 37 32
+ 29 01 00 00 00 00 03 BD 64 32
+ 29 01 00 00 00 00 02 BE 04
+ 29 01 00 00 00 00 02 C0 00
+ 29 01 00 00 00 00 2E C1 04 48 00 00 26
+ 15 19 0B 63 D2 D9 9A 73 EF BD E7 5C
+ 6B 93 4D 22 18 8B 2A 41 00 00 00 00
+ 00 00 00 00 00 40 02 22 1B 06 03 00
+ 07 FF 00 01
+ 29 01 00 00 00 00 18 C2 01 F8 70 08 68
+ 08 0C 10 00 08 30 00 00 00 00 00 00
+ 20 02 43 00 00 00
+ 29 01 00 00 00 00 3F C3 87 D8 7D 87 D0
+ 00 00 00 00 00 00 04 3A 00 00 00 04
+ 44 00 00 01 01 03 28 00 01 00 01 00
+ 00 19 00 0C 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 32 00 19 00 5A
+ 02 32 00 19 00 5A 02 40 00
+ 29 01 00 00 00 00 15 C4 70 00 00 00 11
+ 11 00 00 00 02 02 31 01 00 00 00 02
+ 01 01 01
+ 29 01 00 00 00 00 08 C5 08 00 00 00 00
+ 70 00
+ 29 01 00 00 00 00 40 C6 5B 2D 2D 07 54
+ 07 54 01 02 01 02 07 07 00 00 07 07
+ 0F 11 07 5B 00 5B 5B C2 C2 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 27 C7 01 1D 2E 41 4F
+ 5A 71 80 8B 95 45 4F 5C 71 7B 88 98
+ A6 BE 01 1D 2E 41 4F 5A 71 80 8B 95
+ 45 4F 5C 71 7B 88 98 A6 BE
+ 29 01 00 00 00 00 38 C8 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00
+ 29 01 00 00 00 00 14 C9 00 00 00 00 00
+ FC 00 00 00 00 00 FC 00 00 00 00 00
+ FC 00
+ 29 01 00 00 00 00 2C CA 1C FC FC FC 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 1C CB FF FF FF FF 0F
+ 00 08 00 01 00 31 F0 40 08 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 02 CC 02
+ 29 01 00 00 00 00 27 CD 10 80 37 C0 1A
+ 00 5C 02 19 90 11 88 D8 6C D8 6C 01
+ 00 00 00 32 00 32 00 5D 02 32 32 01
+ 33 00 33 00 5E 02 32 32 AF
+ 29 01 00 00 00 00 1A CE 5D 40 49 53 59
+ 5E 63 68 6E 74 7E 8A 98 A8 BB D0 FF
+ 04 00 04 04 42 00 69 5A
+ 29 01 00 00 00 00 03 CF 4A 1D
+ 29 01 00 00 00 00 12 D0 33 57 D4 31 01
+ 10 10 10 19 19 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 02 D1 00
+ 29 01 00 00 00 00 20 D2 10 00 00 10 75
+ 0F 03 25 20 00 00 00 00 00 00 00 00
+ 04 00 00 00 00 00 00 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 17 D3 1B 3B BB 77 77
+ 77 BB B3 33 00 00 6D 6E DB DB 33 BB
+ F2 FD C6 0B 07
+ 29 01 00 00 00 00 08 D4 00 00 00 00 00
+ 00 00
+ 29 01 00 00 00 00 08 D5 03 00 00 02 40
+ 02 40
+ 29 01 00 00 00 00 02 D6 01
+ 29 01 00 00 00 00 22 D7 F6 FF 03 05 41
+ 24 80 1F C7 1F 1B 00 0C 07 20 00 00
+ 00 00 00 0C 00 1F 00 FC 00 00 AA 67
+ 7E 5D 06 00
+ 29 01 00 00 00 00 03 D9 20 14
+ 29 01 00 00 00 00 05 DD 30 06 23 65
+ 29 01 00 00 00 00 05 DE 00 3F FF 90
+ 29 01 00 00 00 00 06 E7 00 00 00 46 61
+ 29 01 00 00 00 00 02 EA 1F
+ 29 01 00 00 00 00 04 EE 41 51 00
+ 29 01 00 00 00 00 03 F1 00 00
+ 39 01 00 00 00 00 05 2A 00 00 04 37
+ 39 01 00 00 00 00 05 2B 00 00 08 6F
+ 39 01 00 00 00 00 01 2C
+ 39 01 00 00 00 00 02 51 FF
+ 39 01 00 00 00 00 02 53 0C
+ 39 01 00 00 00 00 02 55 00
+ 05 01 00 00 96 00 01 11
+ 05 01 00 00 32 00 01 29];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-td4330-truly-v2-singlemipi-fhd-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-td4330-truly-v2-singlemipi-fhd-cmd.dtsi
new file mode 100755
index 0000000..49fdd74
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-td4330-truly-v2-singlemipi-fhd-cmd.dtsi
@@ -0,0 +1,562 @@
+&mdss_mdp {
+ dsi_td4330_truly_v2_cmd: qcom,mdss_dsi_td4330_truly_v2_cmd {
+ qcom,mdss-dsi-panel-name =
+ "td4330 v2 cmd mode dsi truly panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-panel-mode-switch;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-cmd-mode;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2280>;
+ qcom,mdss-dsi-h-front-porch = <80>;
+ qcom,mdss-dsi-h-back-porch = <80>;
+ qcom,mdss-dsi-h-pulse-width = <20>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <13>;
+ qcom,mdss-dsi-v-front-porch = <16>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+ qcom,mdss-dsi-on-command = [
+ 29 01 00 00 00 00 02
+ B0 00
+ 29 01 00 00 00 00 0D
+ B6 30 6B 00 06 03 0A 13 1A 6C
+ 18 19 02
+ 29 01 00 00 00 00 05
+ B7 40 00 00 00
+ 29 01 00 00 00 00 08
+ B8 57 3D 19 BE 1E 0A 0A
+ 29 01 00 00 00 00 08
+ B9 6F 3D 28 BE 3C 14 0A
+ 29 01 00 00 00 00 08
+ BA B5 33 41 BE 64 23 0A
+ 29 01 00 00 00 00 0C
+ BB 44 26 C3 1F 19 06 03 C0 00
+ 00 10
+ 29 01 00 00 00 00 0C
+ BC 32 4C C3 52 32 1F 03 F2 00
+ 00 13
+ 29 01 00 00 00 00 0C
+ BD 24 68 C3 AA 3F 32 03 FF 00
+ 00 25
+ 29 01 00 00 00 00 0D
+ BE 00 00 00 00 00 00 00 00 00
+ 00 00 00
+ 29 01 00 00 00 00 0D
+ C0 00 DC 00 DC 04 08 E8 00 04
+ 00 03 78
+ 29 01 00 00 00 00 24
+ C1 30 00 00 11 11 00 00 00 22
+ 00 05 20 FA 00 08 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00
+ 29 01 00 00 00 00 79
+ C2 06 E0 6E 01 03 00 02 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 11 00 00 00 00 04 A0 C9
+ 00 00 00 00 00 00 48 EB 00 00
+ 01 00 00 00 11 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 11 00 00 00 00
+ 00 00 DC 00 00 00 00 04 00 08
+ EF 00 00 00 00 00 11 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00
+ 29 01 00 00 00 00 6D
+ C3 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 AA AA AA 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 62
+ C4 00 4C 00 3F 00 83 00 00 87
+ 86 85 84 00 00 00 00 00 61 5D
+ 5F 00 5E 60 62 00 00 00 02 00
+ 83 00 00 87 86 85 84 00 00 00
+ 00 00 61 5D 5F 00 5E 60 62 FF
+ FF FF FF FF FF 00 0F 0E 00 0F
+ 0E 00 00 00 00 00 00 00 0F EE
+ 00 0F EE 00 00 E0 00 00 E0 0E
+ 00 00 00 0E 00 00 00 00 00 FF
+ 57 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 06
+ C5 08 00 00 00 00
+ 29 01 00 00 00 00 3A
+ C6 02 0A 08 FC FF FF FF 00 00
+ 13 01 F0 0C 06 01 43 43 43 00
+ 00 00 01 77 09 28 28 06 01 43
+ 43 43 00 00 00 01 61 00 00 00
+ 1C 01 00 00 00 00 00 00 00 00
+ 00 00 00 00 20 20 00 00
+ 29 01 00 00 00 00 4D
+ C7 00 00 00 E0 01 E9 02 7E 02
+ 05 02 90 02 F6 02 40 02 5C 02
+ 77 02 C8 02 1B 02 5B 02 BD 02
+ 27 02 C3 03 54 03 D8 03 FF 00
+ 00 00 E0 01 E9 02 7E 02 05 02
+ 90 02 F6 02 40 02 5C 02 77 02
+ C8 02 1B 02 5B 02 BD 02 27 02
+ C3 03 54 03 D8 03 FF
+ 29 01 00 00 00 00 42
+ C8 41 00 FF FA 00 FF 00 00 FE
+ F6 FE E9 00 00 FF F7 FB E1 00
+ 00 00 00 00 FF 00 00 FF FA 00
+ FF 00 FE F6 FE E9 00 FF F7 FB
+ E1 00 00 00 00 FF 00 FF FA 00
+ FF 00 FE F6 FE E9 00 FF F7 FB
+ E1 00 00 00 00 FF
+ 29 01 00 00 00 00 19
+ C9 00 FF FA 00 FF 00 00 FE F6
+ FE E9 00 00 FF F7 FB E1 00 00
+ 00 00 00 FF 00
+ 29 01 00 00 00 00 42
+ CA 1C FC FC FC 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00
+ 29 01 00 00 00 00 0B
+ CC 00 00 4D 8B 55 4D 8B AA 4D
+ 8B
+ 29 01 00 00 00 00 02
+ CD 00
+ 29 01 00 00 00 00 24
+ CE 5D 40 49 53 59 5E 63 68 6E
+ 74 7E 8A 98 A8 BB D0 E7 FF 04
+ 00 04 04 42 04 69 5A 40 11 F4
+ 00 00 84 FA 00 00
+ 29 01 00 00 00 00 07
+ CF 00 00 80 46 61 00
+ 29 01 00 00 00 00 12
+ D0 F6 95 11 B1 55 CF 00 F6 D3
+ 11 F0 01 12 CF 02 20 11
+ 29 01 00 00 00 00 23
+ D1 D3 D3 33 33 07 03 3B 33 77
+ 37 77 37 35 77 07 77 F7 33 73
+ 07 33 33 03 33 1B 03 32 3D 0A
+ 30 13 13 20 00
+ 29 01 00 00 00 00 05
+ D2 00 00 07 00
+ 29 01 00 00 00 00 9A
+ D3 03 00 00 00 00 00 00 0F 00
+ 57 00 00 32 00 00 1A 70 01 19
+ 80 01 01 F0 02 00 E0 06 FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF
+ 29 01 00 00 00 00 05
+ E5 03 00 00 00
+ 29 01 00 00 00 00 09
+ D5 02 42 02 42 02 DC 02 DC
+ 29 01 00 00 00 00 02
+ D6 C0
+ 29 01 00 00 00 00 32
+ D7 21 10 52 52 00 B6 04 FD 00
+ B6 04 FD 00 82 80 83 84 85 83
+ 80 84 45 85 85 85 87 04 06 02
+ 04 04 07 10 0C 0B 0A 0A 07 06
+ 00 08 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 05
+ DD 30 06 23 65
+ 29 01 00 00 00 00 0D
+ DE 00 00 00 0F FF 00 00 00 00
+ 00 00 10
+ 29 01 00 00 00 00 02
+ E3 FF
+ 29 01 00 00 00 00 07
+ E6 00 00 00 00 00 00
+ 29 01 00 00 00 00 0B
+ E7 50 04 00 00 00 00 00 00 00
+ 00
+ 29 01 00 00 00 00 05
+ E8 00 01 23 00
+ 29 01 00 00 00 00 1E
+ EA 01 02 47 80 47 00 00 00 05
+ 00 13 60 02 47 80 47 00 00 00
+ 00 13 60 00 11 00 30 10 21 02
+ 29 01 00 00 00 00 08
+ EB 00 00 00 00 01 00 11
+ 29 01 00 00 00 00 04
+ EC 00 00 00
+ 29 01 00 00 00 00 21
+ ED 01 01 02 02 02 02 00 00 00
+ 00 00 00 0A 00 00 00 00 10 00
+ 18 00 18 00 B0 00 00 00 00 00
+ DA 10 00
+ 29 01 00 00 00 00 61
+ EE 03 0F 00 00 00 00 40 1F 00
+ 00 0F F2 3F 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 10
+ 01 00 09 01 8C D8 EF 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 50 1F 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 8C
+ EF 00 70 4A 08 D0 00 00 00 00
+ 3C 3C 3C 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 70
+ 4A 08 D0 00 00 00 00 3C 3C 3C
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 03 08 EC 50 10 00 10
+ 00 0A 0A 00 00 00 00 10 0F 00
+ 03 51 00 50 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 03 08 EC
+ 29 01 00 00 00 00 02
+ B0 03
+ 29 01 00 00 00 00 02
+ B0 04
+ 29 01 00 00 00 00 02
+ D6 00
+ 39 01 00 00 00 00 03
+ 51 FF F0
+ 39 01 00 00 00 00 02
+ 53 0C
+ 39 01 00 00 00 00 02
+ 55 00
+ 39 01 00 00 00 00 02
+ 35 00
+ 39 01 00 00 00 00 05
+ 2A 00 00 04 37
+ 39 01 00 00 00 00 05
+ 2B 00 00 08 E7
+ 05 01 00 00 FF 00 02
+ 29 00
+ 05 01 00 00 FF 00 02
+ 11 00];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,video-to-cmd-mode-post-switch-commands = [
+ 15 01 00 00 00 00 02 B0 00
+ 29 01 00 00 00 00 05 B7 40 00 00 00];
+ qcom,video-to-cmd-mode-post-switch-commands-state =
+ "dsi_lp_mode";
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-video-mode;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2280>;
+ qcom,mdss-dsi-h-front-porch = <40>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <20>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <6>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 29 01 00 00 00 00 02
+ B0 00
+ 29 01 00 00 00 00 0D
+ B6 30 6B 00 06 03 0A 13 1A 6C
+ 18 19 02
+ 29 01 00 00 00 00 05
+ B7 51 00 00 00
+ 29 01 00 00 00 00 08
+ B8 57 3D 19 BE 1E 0A 0A
+ 29 01 00 00 00 00 08
+ B9 6F 3D 28 BE 3C 14 0A
+ 29 01 00 00 00 00 08
+ BA B5 33 41 BE 64 23 0A
+ 29 01 00 00 00 00 0C
+ BB 44 26 C3 1F 19 06 03 C0 00
+ 00 10
+ 29 01 00 00 00 00 0C
+ BC 32 4C C3 52 32 1F 03 F2 00
+ 00 13
+ 29 01 00 00 00 00 0C
+ BD 24 68 C3 AA 3F 32 03 FF 00
+ 00 25
+ 29 01 00 00 00 00 0D
+ BE 00 00 00 00 00 00 00 00 00
+ 00 00 00
+ 29 01 00 00 00 00 0D
+ C0 00 DC 00 DC 04 08 E8 00 04
+ 00 03 78
+ 29 01 00 00 00 00 24
+ C1 30 00 00 11 11 00 00 00 22
+ 00 05 20 FA 00 08 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00
+ 29 01 00 00 00 00 79
+ C2 06 E0 6E 01 03 00 02 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 11 00 00 00 00 04 A0 C9
+ 00 00 00 00 00 00 48 EB 00 00
+ 01 00 00 00 11 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 11 00 00 00 00
+ 00 00 DC 00 00 00 00 04 00 08
+ EF 00 00 00 00 00 11 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00
+ 29 01 00 00 00 00 6D
+ C3 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 AA AA AA 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 62
+ C4 00 4C 00 3F 00 83 00 00 87
+ 86 85 84 00 00 00 00 00 61 5D
+ 5F 00 5E 60 62 00 00 00 02 00
+ 83 00 00 87 86 85 84 00 00 00
+ 00 00 61 5D 5F 00 5E 60 62 FF
+ FF FF FF FF FF 00 0F 0E 00 0F
+ 0E 00 00 00 00 00 00 00 0F EE
+ 00 0F EE 00 00 E0 00 00 E0 0E
+ 00 00 00 0E 00 00 00 00 00 FF
+ 57 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 06
+ C5 08 00 00 00 00
+ 29 01 00 00 00 00 3A
+ C6 02 0A 08 FC FF FF FF 00 00
+ 13 01 F0 0C 06 01 43 43 43 00
+ 00 00 01 77 09 28 28 06 01 43
+ 43 43 00 00 00 01 61 00 00 00
+ 1C 01 00 00 00 00 00 00 00 00
+ 00 00 00 00 20 20 00 00
+ 29 01 00 00 00 00 4D
+ C7 00 00 00 E0 01 E9 02 7E 02
+ 05 02 90 02 F6 02 40 02 5C 02
+ 77 02 C8 02 1B 02 5B 02 BD 02
+ 27 02 C3 03 54 03 D8 03 FF 00
+ 00 00 E0 01 E9 02 7E 02 05 02
+ 90 02 F6 02 40 02 5C 02 77 02
+ C8 02 1B 02 5B 02 BD 02 27 02
+ C3 03 54 03 D8 03 FF
+ 29 01 00 00 00 00 42
+ C8 41 00 FF FA 00 FF 00 00 FE
+ F6 FE E9 00 00 FF F7 FB E1 00
+ 00 00 00 00 FF 00 00 FF FA 00
+ FF 00 FE F6 FE E9 00 FF F7 FB
+ E1 00 00 00 00 FF 00 FF FA 00
+ FF 00 FE F6 FE E9 00 FF F7 FB
+ E1 00 00 00 00 FF
+ 29 01 00 00 00 00 19
+ C9 00 FF FA 00 FF 00 00 FE F6
+ FE E9 00 00 FF F7 FB E1 00 00
+ 00 00 00 FF 00
+ 29 01 00 00 00 00 42
+ CA 1C FC FC FC 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00
+ 29 01 00 00 00 00 0B
+ CC 00 00 4D 8B 55 4D 8B AA 4D
+ 8B
+ 29 01 00 00 00 00 02
+ CD 00
+ 29 01 00 00 00 00 24
+ CE 5D 40 49 53 59 5E 63 68 6E
+ 74 7E 8A 98 A8 BB D0 E7 FF 04
+ 00 04 04 42 04 69 5A 40 11 F4
+ 00 00 84 FA 00 00
+ 29 01 00 00 00 00 07
+ CF 00 00 80 46 61 00
+ 29 01 00 00 00 00 12
+ D0 F6 95 11 B1 55 CF 00 F6 D3
+ 11 F0 01 12 CF 02 20 11
+ 29 01 00 00 00 00 23
+ D1 D3 D3 33 33 07 03 3B 33 77
+ 37 77 37 35 77 07 77 F7 33 73
+ 07 33 33 03 33 1B 03 32 3D 0A
+ 30 13 13 20 00
+ 29 01 00 00 00 00 05
+ D2 00 00 07 00
+ 29 01 00 00 00 00 9A
+ D3 03 00 00 00 00 00 00 0F 00
+ 57 00 00 32 00 00 1A 70 01 19
+ 80 01 01 F0 02 00 E0 06 FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF
+ 29 01 00 00 00 00 05
+ E5 03 00 00 00
+ 29 01 00 00 00 00 09
+ D5 02 42 02 42 02 DC 02 DC
+ 29 01 00 00 00 00 02
+ D6 C0
+ 29 01 00 00 00 00 32
+ D7 21 10 52 52 00 B6 04 FD 00
+ B6 04 FD 00 82 80 83 84 85 83
+ 80 84 45 85 85 85 87 04 06 02
+ 04 04 07 10 0C 0B 0A 0A 07 06
+ 00 08 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 05
+ DD 30 06 23 65
+ 29 01 00 00 00 00 0D
+ DE 00 00 00 0F FF 00 00 00 00
+ 00 00 10
+ 29 01 00 00 00 00 02
+ E3 FF
+ 29 01 00 00 00 00 07
+ E6 00 00 00 00 00 00
+ 29 01 00 00 00 00 0B
+ E7 50 04 00 00 00 00 00 00 00
+ 00
+ 29 01 00 00 00 00 05
+ E8 00 01 23 00
+ 29 01 00 00 00 00 1E
+ EA 01 02 47 80 47 00 00 00 05
+ 00 12 60 02 47 80 47 00 00 00
+ 00 13 60 00 11 00 30 10 21 02
+ 29 01 00 00 00 00 08
+ EB 00 00 00 00 01 00 11
+ 29 01 00 00 00 00 04
+ EC 00 00 00
+ 29 01 00 00 00 00 21
+ ED 01 01 02 02 02 02 00 00 00
+ 00 00 00 0A 00 00 00 00 10 00
+ 18 00 18 00 B0 00 00 00 00 00
+ DA 10 00
+ 29 01 00 00 00 00 61
+ EE 03 0F 00 00 00 00 40 1F 00
+ 00 0F F2 3F 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 10
+ 01 00 09 01 8C D8 EF 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 50 1F 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 8C
+ EF 00 70 4A 08 D0 00 00 00 00
+ 3C 3C 3C 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 70
+ 4A 08 D0 00 00 00 00 3C 3C 3C
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 03 08 EC 50 10 00 10
+ 00 0A 0A 00 00 00 00 10 0F 00
+ 03 51 00 50 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 03 08 EC
+ 29 01 00 00 00 00 02
+ B0 03
+ 29 01 00 00 00 00 02
+ B0 04
+ 29 01 00 00 00 00 02
+ D6 00
+ 39 01 00 00 00 00 03
+ 51 FF F0
+ 39 01 00 00 00 00 02
+ 53 0C
+ 39 01 00 00 00 00 02
+ 55 00
+ 39 01 00 00 00 00 02
+ 35 00
+ 39 01 00 00 00 00 05
+ 2A 00 00 04 37
+ 39 01 00 00 00 00 05
+ 2B 00 00 08 E7
+ 05 01 00 00 FF 00 02
+ 29 00
+ 05 01 00 00 FF 00 02
+ 11 00];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,cmd-to-video-mode-post-switch-commands = [
+ 15 01 00 00 00 00 02 B0 00
+ 29 01 00 00 00 00 05 B7 51 00 00 00];
+ qcom,cmd-to-video-mode-post-switch-commands-state =
+ "dsi_lp_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-td4330-truly-v2-singlemipi-fhd-vid.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-td4330-truly-v2-singlemipi-fhd-vid.dtsi
new file mode 100755
index 0000000..b3500c42
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-td4330-truly-v2-singlemipi-fhd-vid.dtsi
@@ -0,0 +1,567 @@
+&mdss_mdp {
+ dsi_td4330_truly_v2_video: qcom,mdss_dsi_td4330_truly_v2_video {
+ qcom,mdss-dsi-panel-name =
+ "td4330 v2 video mode dsi truly panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+
+ qcom,mdss-dsi-panel-mode-switch;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-lane-map = "lane_map_0123";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-pan-physical-width-dimension = <65>;
+ qcom,mdss-pan-physical-height-dimension = <129>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-video-mode;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2280>;
+ qcom,mdss-dsi-h-front-porch = <40>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <20>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <6>;
+ qcom,mdss-dsi-v-front-porch = <10>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command = [
+ 29 01 00 00 00 00 02
+ B0 00
+ 29 01 00 00 00 00 0D
+ B6 30 6B 00 06 03 0A 13 1A 6C
+ 18 19 02
+ 29 01 00 00 00 00 05
+ B7 51 00 00 00
+ 29 01 00 00 00 00 08
+ B8 57 3D 19 BE 1E 0A 0A
+ 29 01 00 00 00 00 08
+ B9 6F 3D 28 BE 3C 14 0A
+ 29 01 00 00 00 00 08
+ BA B5 33 41 BE 64 23 0A
+ 29 01 00 00 00 00 0C
+ BB 44 26 C3 1F 19 06 03 C0 00
+ 00 10
+ 29 01 00 00 00 00 0C
+ BC 32 4C C3 52 32 1F 03 F2 00
+ 00 13
+ 29 01 00 00 00 00 0C
+ BD 24 68 C3 AA 3F 32 03 FF 00
+ 00 25
+ 29 01 00 00 00 00 0D
+ BE 00 00 00 00 00 00 00 00 00
+ 00 00 00
+ 29 01 00 00 00 00 0D
+ C0 00 DC 00 DC 04 08 E8 00 04
+ 00 03 78
+ 29 01 00 00 00 00 24
+ C1 30 00 00 11 11 00 00 00 22
+ 00 05 20 FA 00 08 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00
+ 29 01 00 00 00 00 79
+ C2 06 E0 6E 01 03 00 02 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 11 00 00 00 00 04 A0 C9
+ 00 00 00 00 00 00 48 EB 00 00
+ 01 00 00 00 11 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 11 00 00 00 00
+ 00 00 DC 00 00 00 00 04 00 08
+ EF 00 00 00 00 00 11 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00
+ 29 01 00 00 00 00 6D
+ C3 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 AA AA AA 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 62
+ C4 00 4C 00 3F 00 83 00 00 87
+ 86 85 84 00 00 00 00 00 61 5D
+ 5F 00 5E 60 62 00 00 00 02 00
+ 83 00 00 87 86 85 84 00 00 00
+ 00 00 61 5D 5F 00 5E 60 62 FF
+ FF FF FF FF FF 00 0F 0E 00 0F
+ 0E 00 00 00 00 00 00 00 0F EE
+ 00 0F EE 00 00 E0 00 00 E0 0E
+ 00 00 00 0E 00 00 00 00 00 FF
+ 57 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 06
+ C5 08 00 00 00 00
+ 29 01 00 00 00 00 3A
+ C6 02 0A 08 FC FF FF FF 00 00
+ 13 01 F0 0C 06 01 43 43 43 00
+ 00 00 01 77 09 28 28 06 01 43
+ 43 43 00 00 00 01 61 00 00 00
+ 1C 01 00 00 00 00 00 00 00 00
+ 00 00 00 00 20 20 00 00
+ 29 01 00 00 00 00 4D
+ C7 00 00 00 E0 01 E9 02 7E 02
+ 05 02 90 02 F6 02 40 02 5C 02
+ 77 02 C8 02 1B 02 5B 02 BD 02
+ 27 02 C3 03 54 03 D8 03 FF 00
+ 00 00 E0 01 E9 02 7E 02 05 02
+ 90 02 F6 02 40 02 5C 02 77 02
+ C8 02 1B 02 5B 02 BD 02 27 02
+ C3 03 54 03 D8 03 FF
+ 29 01 00 00 00 00 42
+ C8 41 00 FF FA 00 FF 00 00 FE
+ F6 FE E9 00 00 FF F7 FB E1 00
+ 00 00 00 00 FF 00 00 FF FA 00
+ FF 00 FE F6 FE E9 00 FF F7 FB
+ E1 00 00 00 00 FF 00 FF FA 00
+ FF 00 FE F6 FE E9 00 FF F7 FB
+ E1 00 00 00 00 FF
+ 29 01 00 00 00 00 19
+ C9 00 FF FA 00 FF 00 00 FE F6
+ FE E9 00 00 FF F7 FB E1 00 00
+ 00 00 00 FF 00
+ 29 01 00 00 00 00 42
+ CA 1C FC FC FC 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00
+ 29 01 00 00 00 00 0B
+ CC 00 00 4D 8B 55 4D 8B AA 4D
+ 8B
+ 29 01 00 00 00 00 02
+ CD 00
+ 29 01 00 00 00 00 24
+ CE 5D 40 49 53 59 5E 63 68 6E
+ 74 7E 8A 98 A8 BB D0 E7 FF 04
+ 00 04 04 42 04 69 5A 40 11 F4
+ 00 00 84 FA 00 00
+ 29 01 00 00 00 00 07
+ CF 00 00 80 46 61 00
+ 29 01 00 00 00 00 12
+ D0 F6 95 11 B1 55 CF 00 F6 D3
+ 11 F0 01 12 CF 02 20 11
+ 29 01 00 00 00 00 23
+ D1 D3 D3 33 33 07 03 3B 33 77
+ 37 77 37 35 77 07 77 F7 33 73
+ 07 33 33 03 33 1B 03 32 3D 0A
+ 30 13 13 20 00
+ 29 01 00 00 00 00 05
+ D2 00 00 07 00
+ 29 01 00 00 00 00 9A
+ D3 03 00 00 00 00 00 00 0F 00
+ 57 00 00 32 00 00 1A 70 01 19
+ 80 01 01 F0 02 00 E0 06 FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF
+ 29 01 00 00 00 00 05
+ E5 03 00 00 00
+ 29 01 00 00 00 00 09
+ D5 02 42 02 42 02 DC 02 DC
+ 29 01 00 00 00 00 02
+ D6 C0
+ 29 01 00 00 00 00 32
+ D7 21 10 52 52 00 B6 04 FD 00
+ B6 04 FD 00 82 80 83 84 85 83
+ 80 84 45 85 85 85 87 04 06 02
+ 04 04 07 10 0C 0B 0A 0A 07 06
+ 00 08 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 05
+ DD 30 06 23 65
+ 29 01 00 00 00 00 0D
+ DE 00 00 00 0F FF 00 00 00 00
+ 00 00 10
+ 29 01 00 00 00 00 02
+ E3 FF
+ 29 01 00 00 00 00 07
+ E6 00 00 00 00 00 00
+ 29 01 00 00 00 00 0B
+ E7 50 04 00 00 00 00 00 00 00
+ 00
+ 29 01 00 00 00 00 05
+ E8 00 01 23 00
+ 29 01 00 00 00 00 1E
+ EA 01 02 47 80 47 00 00 00 05
+ 00 12 60 02 47 80 47 00 00 00
+ 00 13 60 00 11 00 30 10 21 02
+ 29 01 00 00 00 00 08
+ EB 00 00 00 00 01 00 11
+ 29 01 00 00 00 00 04
+ EC 00 00 00
+ 29 01 00 00 00 00 21
+ ED 01 01 02 02 02 02 00 00 00
+ 00 00 00 0A 00 00 00 00 10 00
+ 18 00 18 00 B0 00 00 00 00 00
+ DA 10 00
+ 29 01 00 00 00 00 61
+ EE 03 0F 00 00 00 00 40 1F 00
+ 00 0F F2 3F 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 10
+ 01 00 09 01 8C D8 EF 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 50 1F 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 8C
+ EF 00 70 4A 08 D0 00 00 00 00
+ 3C 3C 3C 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 70
+ 4A 08 D0 00 00 00 00 3C 3C 3C
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 03 08 EC 50 10 00 10
+ 00 0A 0A 00 00 00 00 10 0F 00
+ 03 51 00 50 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 03 08 EC
+ 29 01 00 00 00 00 02
+ B0 03
+ 29 01 00 00 00 00 02
+ B0 04
+ 29 01 00 00 00 00 02
+ D6 00
+ 39 01 00 00 00 00 03
+ 51 FF F0
+ 39 01 00 00 00 00 02
+ 53 0C
+ 39 01 00 00 00 00 02
+ 55 00
+ 39 01 00 00 00 00 02
+ 35 00
+ 39 01 00 00 00 00 05
+ 2A 00 00 04 37
+ 39 01 00 00 00 00 05
+ 2B 00 00 08 E7
+ 05 01 00 00 FF 00 02
+ 29 00
+ 05 01 00 00 FF 00 02
+ 11 00];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,cmd-to-video-mode-post-switch-commands = [
+ 15 01 00 00 00 00 02 B0 00
+ 29 01 00 00 00 00 05 B7 51 00 00 00];
+ qcom,cmd-to-video-mode-post-switch-commands-state =
+ "dsi_lp_mode";
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-cmd-mode;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <2280>;
+ qcom,mdss-dsi-h-front-porch = <80>;
+ qcom,mdss-dsi-h-back-porch = <80>;
+ qcom,mdss-dsi-h-pulse-width = <20>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <13>;
+ qcom,mdss-dsi-v-front-porch = <16>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-jitter = <0x4 0x1>;
+ qcom,mdss-dsi-on-command = [
+ 29 01 00 00 00 00 02
+ B0 00
+ 29 01 00 00 00 00 0D
+ B6 30 6B 00 06 03 0A 13 1A 6C
+ 18 19 02
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+ B7 40 00 00 00
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+ B8 57 3D 19 BE 1E 0A 0A
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+ B9 6F 3D 28 BE 3C 14 0A
+ 29 01 00 00 00 00 08
+ BA B5 33 41 BE 64 23 0A
+ 29 01 00 00 00 00 0C
+ BB 44 26 C3 1F 19 06 03 C0 00
+ 00 10
+ 29 01 00 00 00 00 0C
+ BC 32 4C C3 52 32 1F 03 F2 00
+ 00 13
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+ BD 24 68 C3 AA 3F 32 03 FF 00
+ 00 25
+ 29 01 00 00 00 00 0D
+ BE 00 00 00 00 00 00 00 00 00
+ 00 00 00
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+ C0 00 DC 00 DC 04 08 E8 00 04
+ 00 03 78
+ 29 01 00 00 00 00 24
+ C1 30 00 00 11 11 00 00 00 22
+ 00 05 20 FA 00 08 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00
+ 29 01 00 00 00 00 79
+ C2 06 E0 6E 01 03 00 02 00 00
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+ EF 00 00 00 00 00 11 00 00 00
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+ 00
+ 29 01 00 00 00 00 6D
+ C3 00 00 00 00 00 00 00 00 00
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+ C4 00 4C 00 3F 00 83 00 00 87
+ 86 85 84 00 00 00 00 00 61 5D
+ 5F 00 5E 60 62 00 00 00 02 00
+ 83 00 00 87 86 85 84 00 00 00
+ 00 00 61 5D 5F 00 5E 60 62 FF
+ FF FF FF FF FF 00 0F 0E 00 0F
+ 0E 00 00 00 00 00 00 00 0F EE
+ 00 0F EE 00 00 E0 00 00 E0 0E
+ 00 00 00 0E 00 00 00 00 00 FF
+ 57 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 06
+ C5 08 00 00 00 00
+ 29 01 00 00 00 00 3A
+ C6 02 0A 08 FC FF FF FF 00 00
+ 13 01 F0 0C 06 01 43 43 43 00
+ 00 00 01 77 09 28 28 06 01 43
+ 43 43 00 00 00 01 61 00 00 00
+ 1C 01 00 00 00 00 00 00 00 00
+ 00 00 00 00 20 20 00 00
+ 29 01 00 00 00 00 4D
+ C7 00 00 00 E0 01 E9 02 7E 02
+ 05 02 90 02 F6 02 40 02 5C 02
+ 77 02 C8 02 1B 02 5B 02 BD 02
+ 27 02 C3 03 54 03 D8 03 FF 00
+ 00 00 E0 01 E9 02 7E 02 05 02
+ 90 02 F6 02 40 02 5C 02 77 02
+ C8 02 1B 02 5B 02 BD 02 27 02
+ C3 03 54 03 D8 03 FF
+ 29 01 00 00 00 00 42
+ C8 41 00 FF FA 00 FF 00 00 FE
+ F6 FE E9 00 00 FF F7 FB E1 00
+ 00 00 00 00 FF 00 00 FF FA 00
+ FF 00 FE F6 FE E9 00 FF F7 FB
+ E1 00 00 00 00 FF 00 FF FA 00
+ FF 00 FE F6 FE E9 00 FF F7 FB
+ E1 00 00 00 00 FF
+ 29 01 00 00 00 00 19
+ C9 00 FF FA 00 FF 00 00 FE F6
+ FE E9 00 00 FF F7 FB E1 00 00
+ 00 00 00 FF 00
+ 29 01 00 00 00 00 42
+ CA 1C FC FC FC 00 00 00 00 00
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+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00
+ 29 01 00 00 00 00 0B
+ CC 00 00 4D 8B 55 4D 8B AA 4D
+ 8B
+ 29 01 00 00 00 00 02
+ CD 00
+ 29 01 00 00 00 00 24
+ CE 5D 40 49 53 59 5E 63 68 6E
+ 74 7E 8A 98 A8 BB D0 E7 FF 04
+ 00 04 04 42 04 69 5A 40 11 F4
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+ D0 F6 95 11 B1 55 CF 00 F6 D3
+ 11 F0 01 12 CF 02 20 11
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+ D1 D3 D3 33 33 07 03 3B 33 77
+ 37 77 37 35 77 07 77 F7 33 73
+ 07 33 33 03 33 1B 03 32 3D 0A
+ 30 13 13 20 00
+ 29 01 00 00 00 00 05
+ D2 00 00 07 00
+ 29 01 00 00 00 00 9A
+ D3 03 00 00 00 00 00 00 0F 00
+ 57 00 00 32 00 00 1A 70 01 19
+ 80 01 01 F0 02 00 E0 06 FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF FF F7 FF FF F7 FF
+ FF F7 FF FF F7 FF FF F7 FF FF
+ F7 FF FF F7 FF FF F7 FF FF F7
+ FF FF F7 FF
+ 29 01 00 00 00 00 05
+ E5 03 00 00 00
+ 29 01 00 00 00 00 09
+ D5 02 42 02 42 02 DC 02 DC
+ 29 01 00 00 00 00 02
+ D6 C0
+ 29 01 00 00 00 00 32
+ D7 21 10 52 52 00 B6 04 FD 00
+ B6 04 FD 00 82 80 83 84 85 83
+ 80 84 45 85 85 85 87 04 06 02
+ 04 04 07 10 0C 0B 0A 0A 07 06
+ 00 08 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 05
+ DD 30 06 23 65
+ 29 01 00 00 00 00 0D
+ DE 00 00 00 0F FF 00 00 00 00
+ 00 00 10
+ 29 01 00 00 00 00 02
+ E3 FF
+ 29 01 00 00 00 00 07
+ E6 00 00 00 00 00 00
+ 29 01 00 00 00 00 0B
+ E7 50 04 00 00 00 00 00 00 00
+ 00
+ 29 01 00 00 00 00 05
+ E8 00 01 23 00
+ 29 01 00 00 00 00 1E
+ EA 01 02 47 80 47 00 00 00 05
+ 00 13 60 02 47 80 47 00 00 00
+ 00 13 60 00 11 00 30 10 21 02
+ 29 01 00 00 00 00 08
+ EB 00 00 00 00 01 00 11
+ 29 01 00 00 00 00 04
+ EC 00 00 00
+ 29 01 00 00 00 00 21
+ ED 01 01 02 02 02 02 00 00 00
+ 00 00 00 0A 00 00 00 00 10 00
+ 18 00 18 00 B0 00 00 00 00 00
+ DA 10 00
+ 29 01 00 00 00 00 61
+ EE 03 0F 00 00 00 00 40 1F 00
+ 00 0F F2 3F 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 10
+ 01 00 09 01 8C D8 EF 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 50 1F 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 8C
+ EF 00 70 4A 08 D0 00 00 00 00
+ 3C 3C 3C 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 70
+ 4A 08 D0 00 00 00 00 3C 3C 3C
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 03 08 EC 50 10 00 10
+ 00 0A 0A 00 00 00 00 10 0F 00
+ 03 51 00 50 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 03 08 EC
+ 29 01 00 00 00 00 02
+ B0 03
+ 29 01 00 00 00 00 02
+ B0 04
+ 29 01 00 00 00 00 02
+ D6 00
+ 39 01 00 00 00 00 03
+ 51 FF F0
+ 39 01 00 00 00 00 02
+ 53 0C
+ 39 01 00 00 00 00 02
+ 55 00
+ 39 01 00 00 00 00 02
+ 35 00
+ 39 01 00 00 00 00 05
+ 2A 00 00 04 37
+ 39 01 00 00 00 00 05
+ 2B 00 00 08 E7
+ 05 01 00 00 FF 00 02
+ 29 00
+ 05 01 00 00 FF 00 02
+ 11 00];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 96 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,video-to-cmd-mode-post-switch-commands = [
+ 15 01 00 00 00 00 02 B0 00
+ 29 01 00 00 00 00 05 B7 40 00 00 00];
+ qcom,video-to-cmd-mode-post-switch-commands-state =
+ "dsi_lp_mode";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-truly-1080p-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-truly-1080p-cmd.dtsi
new file mode 100755
index 0000000..af3576a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-truly-1080p-cmd.dtsi
@@ -0,0 +1,84 @@
+&mdss_mdp {
+ dsi_truly_1080_cmd: qcom,mdss_dsi_truly_1080p_cmd {
+ qcom,mdss-dsi-panel-name = "truly 1080p cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <96>;
+ qcom,mdss-dsi-h-back-porch = <64>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <16>;
+ qcom,mdss-dsi-v-front-porch = <4>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings = [e6 38 26 00 68 6e 2a 3c 44 03
+ 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x02>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-on-command = [23 01 00 00 00 00 02 d6 01
+ 15 01 00 00 00 00 02 35 00
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 2c
+ 15 01 00 00 00 00 02 55 00
+ 05 01 00 00 78 00 02 11 00
+ 23 01 00 00 00 00 02 b0 04
+ 29 01 00 00 00 00 07 b3 04 00 00 00 00 00
+ 29 01 00 00 00 00 03 b6 3a d3
+ 29 01 00 00 00 00 03 c0 00 00
+ 29 01 00 00 00 00 23 c1 84 60 10 eb ff 6f ce ff ff 17 02
+ 58 73 ae b1 20 c6 ff ff 1f f3 ff 5f 10 10 10 10 00 02 01
+ 22 22 00 01
+ 29 01 00 00 00 00 08 c2 31 f7 80 06 08 00 00
+ 29 01 00 00 00 00 17 c4 70 00 00 00 00 04 00 00 00 0c 06
+ 00 00 00 00 00 04 00 00 00 0c 06
+ 29 01 00 00 00 00 29 c6 78 69 00 69 00 69 00 00 00 00 00
+ 69 00 69 00 69 10 19 07 00 78 00 69 00 69 00 69 00 00 00
+ 00 00 69 00 69 00 69 10 19 07
+ 29 01 00 00 00 00 0a cb 31 fc 3f 8c 00 00 00 00 c0
+ 23 01 00 00 00 00 02 cc 0b
+ 29 01 00 00 00 00 0b d0 11 81 bb 1e 1e 4c 19 19 0c 00
+ 29 01 00 00 00 00 1a d3 1b 33 bb bb b3 33 33 33 00 01 00
+ a0 d8 a0 0d 4e 4e 33 3b 22 72 07 3d bf 33
+ 29 01 00 00 00 00 08 d5 06 00 00 01 51 01 32
+ 29 01 00 00 00 00 1f c7 01 0a 11 18 26 33 3e 50 38 42 52
+ 60 67 6e 77 01 0a 11 18 26 33 3e 50 38 42 52 60 67 6e 77
+ 29 01 00 00 14 00 14 c8 01 00 00 00 00 fc 00 00 00 00
+ 00 fc 00 00 00 00 00 fc 00
+ 05 01 00 00 14 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-post-init-delay = <1>;
+ qcom,ulps-enabled;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-truly-1080p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-truly-1080p-video.dtsi
new file mode 100755
index 0000000..f081ef9
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-truly-1080p-video.dtsi
@@ -0,0 +1,78 @@
+&mdss_mdp {
+ dsi_truly_1080_vid: qcom,mdss_dsi_truly_1080p_video {
+ qcom,mdss-dsi-panel-name = "truly 1080p video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <96>;
+ qcom,mdss-dsi-h-back-porch = <64>;
+ qcom,mdss-dsi-h-pulse-width = <16>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <16>;
+ qcom,mdss-dsi-v-front-porch = <4>;
+ qcom,mdss-dsi-v-pulse-width = <1>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings = [e6 38 26 00 68 6e 2a 3c 44 03
+ 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x02>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-on-command = [15 01 00 00 00 00 02 35 00
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 2c
+ 15 01 00 00 00 00 02 55 00
+ 05 01 00 00 78 00 02 11 00
+ 23 01 00 00 00 00 02 b0 00
+ 29 01 00 00 00 00 07 b3 14 00 00 00 00 00
+ 29 01 00 00 00 00 03 b6 3a d3
+ 29 01 00 00 00 00 03 c0 00 00
+ 29 01 00 00 00 00 23 c1 84 60 10 eb ff 6f ce ff ff 17 02
+ 58 73 ae b1 20 c6 ff ff 1f f3 ff 5f 10 10 10 10 00 02 01
+ 22 22 00 01
+ 29 01 00 00 00 00 08 c2 31 f7 80 06 08 00 00
+ 29 01 00 00 00 00 17 c4 70 00 00 00 00 04 00 00 00 0c 06
+ 00 00 00 00 00 04 00 00 00 0c 06
+ 29 01 00 00 00 00 29 c6 00 69 00 69 00 69 00 00 00 00 00
+ 69 00 69 00 69 10 19 07 00 01 00 69 00 69 00 69 00 00 00
+ 00 00 69 00 69 00 69 10 19 07
+ 29 01 00 00 00 00 0a cb 31 fc 3f 8c 00 00 00 00 c0
+ 23 01 00 00 00 00 02 cc 0b
+ 29 01 00 00 00 00 0b d0 11 81 bb 1e 1e 4c 19 19 0c 00
+ 29 01 00 00 00 00 1a d3 1b 33 bb bb b3 33 33 33 00 01 00
+ a0 d8 a0 0d 4e 4e 33 3b 22 72 07 3d bf 33
+ 29 01 00 00 00 00 08 d5 06 00 00 01 51 01 32
+ 29 01 00 00 00 00 1f c7 01 0a 11 18 26 33 3e 50 38 42 52
+ 60 67 6e 77 01 0a 11 18 26 33 3e 50 38 42 52 60 67 6e 77
+ 29 01 00 00 14 00 14 c8 01 00 00 00 00 fc 00 00 00 00
+ 00 fc 00 00 00 00 00 fc 00
+ 05 01 00 00 14 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-post-init-delay = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-truly-720p-cmd.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-truly-720p-cmd.dtsi
new file mode 100755
index 0000000..e9227d9
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-truly-720p-cmd.dtsi
@@ -0,0 +1,243 @@
+&mdss_mdp {
+ dsi_truly_720_cmd: qcom,mdss_dsi_truly_720p_cmd {
+ qcom,mdss-dsi-panel-name = "truly 720p cmd mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_cmd_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <6>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <32>;
+ qcom,mdss-dsi-v-front-porch = <32>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings = [87 2c 12 00 40 44 16 1e 17 03
+ 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x04>;
+ qcom,mdss-dsi-t-clk-pre = <0x1b>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-on-command = [29 01 00 00 00 00 06 f0 55 aa 52
+ 08 00
+ 29 01 00 00 00 00 03 b1 78 21
+ 23 01 00 00 00 00 02 b6 0f
+ 29 01 00 00 00 00 03 bc 00 00
+ 29 01 00 00 00 00 06 bd 02 67 20 20 00
+ 29 01 00 00 00 00 0b e7 f2 e6 d8 cc bf b2 a5 99 99 95
+ 29 01 00 00 00 00 0b e8 f2 e6 d8 cc bf b2 a5 99 99 95
+ 29 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 29 01 00 00 00 00 03 bc a0 00
+ 29 01 00 00 00 00 03 bd a0 00
+ 23 01 00 00 00 00 02 ca 01
+ 23 01 00 00 00 00 02 c0 0c
+ 23 01 00 00 00 00 02 be 4e
+ 29 01 00 00 00 00 03 b3 38 38
+ 29 01 00 00 00 00 03 b4 11 11
+ 29 01 00 00 00 00 03 b6 05 05
+ 29 01 00 00 00 00 03 b9 45 45
+ 29 01 00 00 00 00 03 ba 25 25
+ 29 01 00 00 00 00 03 c4 11 11
+ 23 01 00 00 00 00 02 c6 66
+ 29 01 00 00 00 00 06 f0 55 aa 52 08 02
+ 23 01 00 00 00 00 02 ee 00
+ 29 01 00 00 00 00 11 b0 00 37 00 48 00 69 00 8a 00 ab 00
+ cb 00 eb 01 1c
+ 29 01 00 00 00 00 11 b1 01 41 01 7c 01 aa 01 f3 02 2d 02
+ 2e 02 63 02 9d
+ 29 01 00 00 00 00 11 b2 02 c3 02 f6 03 19 03 54 03 85 03
+ b2 03 c1 03 d1
+ 29 01 00 00 00 00 05 b3 03 e0 03 e8
+ 29 01 00 00 00 00 11 bc 00 37 00 48 00 69 00 8a 00 ab 00
+ cb 00 eb 01 1c
+ 29 01 00 00 00 00 11 bd 01 41 01 7c 01 aa 01 f3 02 2d 02
+ 2e 02 63 02 9d
+ 29 01 00 00 00 00 11 be 02 c3 02 f6 03 19 03 54 03 85 03
+ b2 03 c1 03 d1
+ 29 01 00 00 00 00 05 bf 03 e0 03 e8
+ 29 01 00 00 00 00 11 b4 00 d1 00 d7 00 e4 00 f1 00 fe 01
+ 12 01 26 01 48
+ 29 01 00 00 00 00 11 b5 01 64 01 95 01 bd 02 01 02 36 02
+ 38 02 6c 02 a7
+ 29 01 00 00 00 00 11 b6 02 ce 03 04 03 2b 03 5b 03 89 03
+ b2 03 c1 03 d1
+ 29 01 00 00 00 00 05 b7 03 e0 03 e8
+ 29 01 00 00 00 00 11 c0 00 d1 00 d7 00 e4 00 f1 00 fe 01
+ 12 01 26 01 48
+ 29 01 00 00 00 00 11 c1 01 64 01 95 01 bd 02 01 02 36 02
+ 38 02 6c 02 a7
+ 29 01 00 00 00 00 11 c2 02 ce 03 04 03 2b 03 5b 03 89 03
+ b2 03 c1 03 d1
+ 29 01 00 00 00 00 05 c3 03 e0 03 e8
+ 29 01 00 00 00 00 11 b8 00 37 00 45 00 61 00 7d 00 9a 00
+ bb 00 dc 01 0b
+ 29 01 00 00 00 00 11 b9 01 31 01 6e 01 9e 01 ea 02 24 02
+ 25 02 58 02 90
+ 29 01 00 00 00 00 11 ba 02 b4 02 e4 03 04 03 44 03 7f 03
+ b2 03 c1 03 d1
+ 29 01 00 00 00 00 05 bb 03 e0 03 e8
+ 29 01 00 00 00 00 11 c4 00 37 00 45 00 61 00 7d 00 9a 00
+ bb 00 dc 01 0b
+ 29 01 00 00 00 00 11 c5 01 31 01 6e 01 9e 01 ea 02 24 02
+ 25 02 58 02 90
+ 29 01 00 00 00 00 11 c6 02 b4 02 e4 03 04 03 44 03 7f 03
+ b2 03 c1 03 d1
+ 29 01 00 00 00 00 05 c7 03 e0 03 e8
+ 29 01 00 00 00 00 06 f0 55 aa 52 08 06
+ 29 01 00 00 00 00 03 b0 29 2a
+ 29 01 00 00 00 00 03 b1 10 12
+ 29 01 00 00 00 00 03 b2 14 16
+ 29 01 00 00 00 00 03 b3 18 1a
+ 29 01 00 00 00 00 03 b4 02 04
+ 29 01 00 00 00 00 03 b5 34 34
+ 29 01 00 00 00 00 03 b6 34 2e
+ 29 01 00 00 00 00 03 b7 2e 2e
+ 29 01 00 00 00 00 03 b8 34 00
+ 29 01 00 00 00 00 03 b9 34 34
+ 29 01 00 00 00 00 03 ba 34 34
+ 29 01 00 00 00 00 03 bb 01 34
+ 29 01 00 00 00 00 03 bc 2e 2e
+ 29 01 00 00 00 00 03 bd 2e 34
+ 29 01 00 00 00 00 03 be 34 34
+ 29 01 00 00 00 00 03 bf 05 03
+ 29 01 00 00 00 00 03 c0 1b 19
+ 29 01 00 00 00 00 03 c1 17 15
+ 29 01 00 00 00 00 03 c2 13 11
+ 29 01 00 00 00 00 03 c3 2a 29
+ 29 01 00 00 00 00 03 e5 2e 2e
+ 29 01 00 00 00 00 03 c4 29 2a
+ 29 01 00 00 00 00 03 c5 1b 19
+ 29 01 00 00 00 00 03 c6 17 15
+ 29 01 00 00 00 00 03 c7 13 11
+ 29 01 00 00 00 00 03 c8 01 05
+ 29 01 00 00 00 00 03 c9 34 34
+ 29 01 00 00 00 00 03 ca 34 2e
+ 29 01 00 00 00 00 03 cb 2e 2e
+ 29 01 00 00 00 00 03 cc 34 03
+ 29 01 00 00 00 00 03 cd 34 34
+ 29 01 00 00 00 00 03 ce 34 34
+ 29 01 00 00 00 00 03 cf 02 34
+ 29 01 00 00 00 00 03 d0 2e 2e
+ 29 01 00 00 00 00 03 d1 2e 34
+ 29 01 00 00 00 00 03 d2 34 34
+ 29 01 00 00 00 00 03 d3 04 00
+ 29 01 00 00 00 00 03 d4 10 12
+ 29 01 00 00 00 00 03 d5 14 16
+ 29 01 00 00 00 00 03 d6 18 1a
+ 29 01 00 00 00 00 03 d7 2a 29
+ 29 01 00 00 00 00 03 e6 2e 2e
+ 29 01 00 00 00 00 06 d8 00 00 00 54 00
+ 29 01 00 00 00 00 06 d9 00 15 00 00 00
+ 23 01 00 00 00 00 02 e7 00
+ 29 01 00 00 00 00 06 f0 55 aa 52 08 03
+ 29 01 00 00 00 00 03 b1 00 00
+ 29 01 00 00 00 00 03 b0 00 00
+ 29 01 00 00 00 00 06 b2 05 00 00 00 00
+ 29 01 00 00 00 00 06 b3 05 00 00 00 00
+ 29 01 00 00 00 00 06 b4 05 00 00 00 00
+ 29 01 00 00 00 00 06 b5 05 00 17 00 00
+ 29 01 00 00 00 00 06 b6 12 00 19 00 00
+ 29 01 00 00 00 00 06 b7 12 00 19 00 00
+ 29 01 00 00 00 00 06 b8 12 00 19 00 00
+ 29 01 00 00 00 00 06 b9 12 00 19 00 00
+ 29 01 00 00 00 00 06 ba 57 00 00 00 00
+ 29 01 00 00 00 00 06 bb 57 00 00 00 00
+ 29 01 00 00 00 00 06 bc 75 00 1a 00 00
+ 29 01 00 00 00 00 06 bd 53 00 1a 00 00
+ 29 01 00 00 00 00 05 c0 00 34 00 00
+ 29 01 00 00 00 00 05 c1 00 34 00 00
+ 29 01 00 00 00 00 05 c2 00 34 00 00
+ 29 01 00 00 00 00 05 c3 00 34 00 00
+ 23 01 00 00 00 00 02 c4 20
+ 23 01 00 00 00 00 02 c5 00
+ 23 01 00 00 00 00 02 c6 00
+ 23 01 00 00 00 00 02 c7 00
+ 29 01 00 00 00 00 06 f0 55 aa 52 08 05
+ 23 01 00 00 00 00 02 ed 30
+ 29 01 00 00 00 00 03 b0 17 06
+ 23 01 00 00 00 00 02 b8 08
+ 29 01 00 00 00 00 06 bd 03 07 00 03 00
+ 29 01 00 00 00 00 03 b1 17 06
+ 23 01 00 00 00 00 02 b9 00
+ 29 01 00 00 00 00 03 b2 00 00
+ 23 01 00 00 00 00 02 ba 00
+ 29 01 00 00 00 00 03 b3 17 06
+ 23 01 00 00 00 00 02 bb 0a
+ 29 01 00 00 00 00 03 b4 17 06
+ 29 01 00 00 00 00 03 b5 17 06
+ 29 01 00 00 00 00 03 b6 14 03
+ 29 01 00 00 00 00 03 b7 00 00
+ 23 01 00 00 00 00 02 bc 02
+ 23 01 00 00 00 00 02 e5 06
+ 23 01 00 00 00 00 02 e6 06
+ 23 01 00 00 00 00 02 e7 00
+ 23 01 00 00 00 00 02 e8 06
+ 23 01 00 00 00 00 02 e9 06
+ 23 01 00 00 00 00 02 ea 06
+ 23 01 00 00 00 00 02 eb 00
+ 23 01 00 00 00 00 02 ec 00
+ 23 01 00 00 00 00 02 c0 07
+ 23 01 00 00 00 00 02 c1 80
+ 23 01 00 00 00 00 02 c2 a4
+ 23 01 00 00 00 00 02 c3 05
+ 23 01 00 00 00 00 02 c4 00
+ 23 01 00 00 00 00 02 c5 02
+ 23 01 00 00 00 00 02 c6 22
+ 23 01 00 00 00 00 02 c7 03
+ 29 01 00 00 00 00 03 c8 05 30
+ 29 01 00 00 00 00 03 c9 01 31
+ 29 01 00 00 00 00 03 ca 03 21
+ 29 01 00 00 00 00 03 cb 01 20
+ 29 01 00 00 00 00 06 d1 00 05 09 07 10
+ 29 01 00 00 00 00 06 d2 10 05 0e 03 10
+ 29 01 00 00 00 00 06 d3 20 00 48 07 10
+ 29 01 00 00 00 00 06 d4 30 00 43 07 10
+ 23 01 00 00 00 00 02 d0 00
+ 29 01 00 00 00 00 04 cc 00 00 3e
+ 29 01 00 00 00 00 04 cd 00 00 3e
+ 29 01 00 00 00 00 04 ce 00 00 02
+ 29 01 00 00 00 00 04 cf 00 00 02
+ 23 01 00 00 00 00 02 6f 11
+ 23 01 00 00 00 00 02 f3 01
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 2c
+ 15 01 00 00 00 00 02 55 03
+ 15 01 00 00 c8 00 02 35 00
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 0a 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-post-init-delay = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-truly-720p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-truly-720p-video.dtsi
new file mode 100755
index 0000000..715b49b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-truly-720p-video.dtsi
@@ -0,0 +1,237 @@
+&mdss_mdp {
+ dsi_truly_720_vid: qcom,mdss_dsi_truly_720p_video {
+ qcom,mdss-dsi-panel-name = "truly 720p video mode dsi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-width = <720>;
+ qcom,mdss-dsi-panel-height = <1280>;
+ qcom,mdss-dsi-h-front-porch = <100>;
+ qcom,mdss-dsi-h-back-porch = <100>;
+ qcom,mdss-dsi-h-pulse-width = <6>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <32>;
+ qcom,mdss-dsi-v-front-porch = <32>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-traffic-mode = "burst_mode";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-panel-timings = [87 2c 12 00 40 44 16 1e 17 03
+ 04 00];
+ qcom,mdss-dsi-t-clk-post = <0x04>;
+ qcom,mdss-dsi-t-clk-pre = <0x1b>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-on-command = [29 01 00 00 00 00 06 f0 55 aa 52
+ 08 00
+ 29 01 00 00 00 00 03 b1 78 21
+ 23 01 00 00 00 00 02 b6 0f
+ 29 01 00 00 00 00 03 bc 00 00
+ 29 01 00 00 00 00 06 bd 02 b0 1e 1e 00
+ 29 01 00 00 00 00 0b e7 f2 e6 d8 cc bf b2 a5 99 99 95
+ 29 01 00 00 00 00 0b e8 f2 e6 d8 cc bf b2 a5 99 99 95
+ 29 01 00 00 00 00 06 f0 55 aa 52 08 01
+ 29 01 00 00 00 00 03 bc a0 00
+ 29 01 00 00 00 00 03 bd a0 00
+ 23 01 00 00 00 00 02 ca 01
+ 23 01 00 00 00 00 02 c0 0c
+ 23 01 00 00 00 00 02 be 4e
+ 29 01 00 00 00 00 03 b3 38 38
+ 29 01 00 00 00 00 03 b4 11 11
+ 29 01 00 00 00 00 03 b6 05 05
+ 29 01 00 00 00 00 03 b9 45 45
+ 29 01 00 00 00 00 03 ba 25 25
+ 29 01 00 00 00 00 03 c4 11 11
+ 23 01 00 00 00 00 02 c6 66
+ 29 01 00 00 00 00 06 f0 55 aa 52 08 02
+ 23 01 00 00 00 00 02 ee 00
+ 29 01 00 00 00 00 11 b0 00 37 00 48 00 69 00 8a 00 ab 00
+ cb 00 eb 01 1c
+ 29 01 00 00 00 00 11 b1 01 41 01 7c 01 aa 01 f3 02 2d 02
+ 2e 02 63 02 9d
+ 29 01 00 00 00 00 11 b2 02 c3 02 f6 03 19 03 54 03 85 03
+ b2 03 c1 03 d1
+ 29 01 00 00 00 00 05 b3 03 e0 03 e8
+ 29 01 00 00 00 00 11 bc 00 37 00 48 00 69 00 8a 00 ab 00
+ cb 00 eb 01 1c
+ 29 01 00 00 00 00 11 bd 01 41 01 7c 01 aa 01 f3 02 2d 02
+ 2e 02 63 02 9d
+ 29 01 00 00 00 00 11 be 02 c3 02 f6 03 19 03 54 03 85 03
+ b2 03 c1 03 d1
+ 29 01 00 00 00 00 05 bf 03 e0 03 e8
+ 29 01 00 00 00 00 11 b4 00 d1 00 d7 00 e4 00 f1 00 fe 01
+ 12 01 26 01 48
+ 29 01 00 00 00 00 11 b5 01 64 01 95 01 bd 02 01 02 36 02
+ 38 02 6c 02 a7
+ 29 01 00 00 00 00 11 b6 02 ce 03 04 03 2b 03 5b 03 89 03
+ b2 03 c1 03 d1
+ 29 01 00 00 00 00 05 b7 03 e0 03 e8
+ 29 01 00 00 00 00 11 c0 00 d1 00 d7 00 e4 00 f1 00 fe 01
+ 12 01 26 01 48
+ 29 01 00 00 00 00 11 c1 01 64 01 95 01 bd 02 01 02 36 02
+ 38 02 6c 02 a7
+ 29 01 00 00 00 00 11 c2 02 ce 03 04 03 2b 03 5b 03 89 03
+ b2 03 c1 03 d1
+ 29 01 00 00 00 00 05 c3 03 e0 03 e8
+ 29 01 00 00 00 00 11 b8 00 37 00 45 00 61 00 7d 00 9a 00
+ bb 00 dc 01 0b
+ 29 01 00 00 00 00 11 b9 01 31 01 6e 01 9e 01 ea 02 24 02
+ 25 02 58 02 90
+ 29 01 00 00 00 00 11 ba 02 b4 02 e4 03 04 03 44 03 7f 03
+ b2 03 c1 03 d1
+ 29 01 00 00 00 00 05 bb 03 e0 03 e8
+ 29 01 00 00 00 00 11 c4 00 37 00 45 00 61 00 7d 00 9a 00
+ bb 00 dc 01 0b
+ 29 01 00 00 00 00 11 c5 01 31 01 6e 01 9e 01 ea 02 24 02
+ 25 02 58 02 90
+ 29 01 00 00 00 00 11 c6 02 b4 02 e4 03 04 03 44 03 7f 03
+ b2 03 c1 03 d1
+ 29 01 00 00 00 00 05 c7 03 e0 03 e8
+ 29 01 00 00 00 00 06 f0 55 aa 52 08 06
+ 29 01 00 00 00 00 03 b0 29 2a
+ 29 01 00 00 00 00 03 b1 10 12
+ 29 01 00 00 00 00 03 b2 14 16
+ 29 01 00 00 00 00 03 b3 18 1a
+ 29 01 00 00 00 00 03 b4 02 04
+ 29 01 00 00 00 00 03 b5 34 34
+ 29 01 00 00 00 00 03 b6 34 2e
+ 29 01 00 00 00 00 03 b7 2e 2e
+ 29 01 00 00 00 00 03 b8 34 00
+ 29 01 00 00 00 00 03 b9 34 34
+ 29 01 00 00 00 00 03 ba 34 34
+ 29 01 00 00 00 00 03 bb 01 34
+ 29 01 00 00 00 00 03 bc 2e 2e
+ 29 01 00 00 00 00 03 bd 2e 34
+ 29 01 00 00 00 00 03 be 34 34
+ 29 01 00 00 00 00 03 bf 05 03
+ 29 01 00 00 00 00 03 c0 1b 19
+ 29 01 00 00 00 00 03 c1 17 15
+ 29 01 00 00 00 00 03 c2 13 11
+ 29 01 00 00 00 00 03 c3 2a 29
+ 29 01 00 00 00 00 03 e5 2e 2e
+ 29 01 00 00 00 00 03 c4 29 2a
+ 29 01 00 00 00 00 03 c5 1b 19
+ 29 01 00 00 00 00 03 c6 17 15
+ 29 01 00 00 00 00 03 c7 13 11
+ 29 01 00 00 00 00 03 c8 01 05
+ 29 01 00 00 00 00 03 c9 34 34
+ 29 01 00 00 00 00 03 ca 34 2e
+ 29 01 00 00 00 00 03 cb 2e 2e
+ 29 01 00 00 00 00 03 cc 34 03
+ 29 01 00 00 00 00 03 cd 34 34
+ 29 01 00 00 00 00 03 ce 34 34
+ 29 01 00 00 00 00 03 cf 02 34
+ 29 01 00 00 00 00 03 d0 2e 2e
+ 29 01 00 00 00 00 03 d1 2e 34
+ 29 01 00 00 00 00 03 d2 34 34
+ 29 01 00 00 00 00 03 d3 04 00
+ 29 01 00 00 00 00 03 d4 10 12
+ 29 01 00 00 00 00 03 d5 14 16
+ 29 01 00 00 00 00 03 d6 18 1a
+ 29 01 00 00 00 00 03 d7 2a 29
+ 29 01 00 00 00 00 03 e6 2e 2e
+ 29 01 00 00 00 00 06 d8 00 00 00 54 00
+ 29 01 00 00 00 00 06 d9 00 15 00 00 00
+ 23 01 00 00 00 00 02 e7 00
+ 29 01 00 00 00 00 06 f0 55 aa 52 08 03
+ 29 01 00 00 00 00 03 b1 00 00
+ 29 01 00 00 00 00 03 b0 00 00
+ 29 01 00 00 00 00 06 b2 05 00 00 00 00
+ 29 01 00 00 00 00 06 b3 05 00 00 00 00
+ 29 01 00 00 00 00 06 b4 05 00 00 00 00
+ 29 01 00 00 00 00 06 b5 05 00 17 00 00
+ 29 01 00 00 00 00 06 b6 12 00 19 00 00
+ 29 01 00 00 00 00 06 b7 12 00 19 00 00
+ 29 01 00 00 00 00 06 b8 12 00 19 00 00
+ 29 01 00 00 00 00 06 b9 12 00 19 00 00
+ 29 01 00 00 00 00 06 ba 57 00 00 00 00
+ 29 01 00 00 00 00 06 bb 57 00 00 00 00
+ 29 01 00 00 00 00 06 bc 75 00 1a 00 00
+ 29 01 00 00 00 00 06 bd 53 00 1a 00 00
+ 29 01 00 00 00 00 05 c0 00 34 00 00
+ 29 01 00 00 00 00 05 c1 00 34 00 00
+ 29 01 00 00 00 00 05 c2 00 34 00 00
+ 29 01 00 00 00 00 05 c3 00 34 00 00
+ 23 01 00 00 00 00 02 c4 20
+ 23 01 00 00 00 00 02 c5 00
+ 23 01 00 00 00 00 02 c6 00
+ 23 01 00 00 00 00 02 c7 00
+ 29 01 00 00 00 00 06 f0 55 aa 52 08 05
+ 23 01 00 00 00 00 02 ed 30
+ 29 01 00 00 00 00 03 b0 17 06
+ 23 01 00 00 00 00 02 b8 08
+ 29 01 00 00 00 00 06 bd 03 07 00 03 00
+ 29 01 00 00 00 00 03 b1 17 06
+ 23 01 00 00 00 00 02 b9 00
+ 29 01 00 00 00 00 03 b2 00 00
+ 23 01 00 00 00 00 02 ba 00
+ 29 01 00 00 00 00 03 b3 17 06
+ 23 01 00 00 00 00 02 bb 0a
+ 29 01 00 00 00 00 03 b4 17 06
+ 29 01 00 00 00 00 03 b5 17 06
+ 29 01 00 00 00 00 03 b6 14 03
+ 29 01 00 00 00 00 03 b7 00 00
+ 23 01 00 00 00 00 02 bc 02
+ 23 01 00 00 00 00 02 e5 06
+ 23 01 00 00 00 00 02 e6 06
+ 23 01 00 00 00 00 02 e7 00
+ 23 01 00 00 00 00 02 e8 06
+ 23 01 00 00 00 00 02 e9 06
+ 23 01 00 00 00 00 02 ea 06
+ 23 01 00 00 00 00 02 eb 00
+ 23 01 00 00 00 00 02 ec 00
+ 23 01 00 00 00 00 02 c0 07
+ 23 01 00 00 00 00 02 c1 80
+ 23 01 00 00 00 00 02 c2 a4
+ 23 01 00 00 00 00 02 c3 05
+ 23 01 00 00 00 00 02 c4 00
+ 23 01 00 00 00 00 02 c5 02
+ 23 01 00 00 00 00 02 c6 22
+ 23 01 00 00 00 00 02 c7 03
+ 29 01 00 00 00 00 03 c8 05 30
+ 29 01 00 00 00 00 03 c9 01 31
+ 29 01 00 00 00 00 03 ca 03 21
+ 29 01 00 00 00 00 03 cb 01 20
+ 29 01 00 00 00 00 06 d1 00 05 09 07 10
+ 29 01 00 00 00 00 06 d2 10 05 0e 03 10
+ 29 01 00 00 00 00 06 d3 20 00 48 07 10
+ 29 01 00 00 00 00 06 d4 30 00 43 07 10
+ 23 01 00 00 00 00 02 d0 00
+ 29 01 00 00 00 00 04 cc 00 00 3e
+ 29 01 00 00 00 00 04 cd 00 00 3e
+ 29 01 00 00 00 00 04 ce 00 00 02
+ 29 01 00 00 00 00 04 cf 00 00 02
+ 23 01 00 00 00 00 02 6f 11
+ 23 01 00 00 00 00 02 f3 01
+ 15 01 00 00 00 00 02 51 ff
+ 15 01 00 00 00 00 02 53 2c
+ 15 01 00 00 00 00 02 55 03
+ 15 01 00 00 c8 00 02 35 00
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 0a 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 14 00 02 28 00
+ 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-reset-sequence = <1 10>, <0 10>, <1 10>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-lp11-init;
+ qcom,mdss-dsi-post-init-delay = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/dsi-panel-xrsmrtvwr-jdi-dual-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-xrsmrtvwr-jdi-dual-video.dtsi
new file mode 100755
index 0000000..e6ce614
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/dsi-panel-xrsmrtvwr-jdi-dual-video.dtsi
@@ -0,0 +1,87 @@
+&mdss_mdp {
+ dsi_dual_xrsmrtvwr_jdi_video: qcom,mdss_dsi_xrsmrtvwr_video_jdi {
+ qcom,mdss-dsi-panel-name =
+ "Dual Smart XR Viewer LPM029M483A R63455 jdi panel";
+ qcom,mdss-dsi-panel-type = "dsi_video_mode";
+ qcom,mdss-dsi-virtual-channel-id = <0>;
+ qcom,mdss-dsi-stream = <0>;
+ qcom,mdss-dsi-panel-hdr-enabled;
+ qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000
+ 17000 15500 30000 8000 3000>;
+ qcom,mdss-dsi-panel-peak-brightness = <4200000>;
+ qcom,mdss-dsi-panel-blackness-level = <3230>;
+
+ qcom,dsi-ctrl-num = <0 1>;
+ qcom,dsi-phy-num = <0 1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+
+ qcom,mdss-dsi-traffic-mode = "non_burst_sync_event";
+ qcom,mdss-dsi-bllp-eof-power-mode;
+ qcom,mdss-dsi-bllp-power-mode;
+ qcom,mdss-dsi-lane-0-state;
+ qcom,mdss-dsi-lane-1-state;
+ qcom,mdss-dsi-lane-2-state;
+ qcom,mdss-dsi-lane-3-state;
+ qcom,mdss-dsi-dma-trigger = "trigger_sw";
+ qcom,mdss-dsi-mdp-trigger = "none";
+ qcom,mdss-dsi-reset-sequence = <1 20>, <0 20>, <1 50>;
+ qcom,mdss-pan-physical-width-dimension = <52>;
+ qcom,mdss-pan-physical-height-dimension = <52>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-color-order = "rgb_swap_rgb";
+ qcom,mdss-dsi-underflow-color = <0xff>;
+ qcom,mdss-dsi-border-color = <0>;
+ qcom,mdss-dsi-bpp = <24>;
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1440>;
+ qcom,mdss-dsi-panel-height = <1440>;
+ qcom,mdss-dsi-h-front-porch = <40>;
+ qcom,mdss-dsi-h-back-porch = <40>;
+ qcom,mdss-dsi-h-pulse-width = <20>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <16>;
+ qcom,mdss-dsi-v-front-porch = <322>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-panel-framerate = <75>;
+ qcom,mdss-dsi-on-command = [
+ 29 01 00 00 00 00 02 B0 04
+ 29 01 00 00 00 00 02 D6 00
+ 29 01 00 00 00 00 0A B6 30 6B 80 06 33
+ 8A 00 1A 7A
+ 29 01 00 00 00 00 05 B7 54 00 00 00
+ 29 01 00 00 00 00 0D B9 00 85 01 BF 00
+ 00 00 00 00 85 01 BF
+ 29 01 00 00 00 00 09 C0 61 86 58 02 08
+ 70 04 EC
+ 29 01 00 00 00 00 02 F1 1E
+ 29 01 00 00 00 00 09 C6 A0 05 A0 05 43
+ 9F 05 43
+ 29 01 00 00 00 00 02 CD 11
+ 29 01 00 00 00 00 08 CF 00 00 80 46 61
+ 00 00
+ 29 01 00 00 00 00 07 EC 01 8E 00 00 00
+ 00
+ 39 01 00 00 00 00 02 03 00
+ 39 01 00 00 00 00 03 44 00 00
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 36 00
+ 39 01 00 00 00 00 02 3A 77
+ 05 01 00 00 02 00 02 29 00
+ 05 01 00 00 80 00 02 11 00
+ 29 01 00 00 00 00 02 D6 80
+ 29 01 00 00 00 00 02 B0 03
+ ];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 32 00 02 34 00
+ 05 01 00 00 78 00 02 10 00
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/fg-gen3-batterydata-I13Z5P-680mAh.dtsi b/arch/arm64/boot/dts/vendor/qcom/fg-gen3-batterydata-I13Z5P-680mAh.dtsi
new file mode 100755
index 0000000..570198a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/fg-gen3-batterydata-I13Z5P-680mAh.dtsi
@@ -0,0 +1,71 @@
+qcom,3388014_i13z5p_680mah_averaged_masterslave_mar26th2018 {
+ qcom,fastchg-current-ma = <480>;
+ /* #3388014_I13Z5P_680mAh_averaged_MasterSlave_Mar26th2018*/
+ qcom,max-voltage-uv = <4400000>;
+ qcom,fg-cc-cv-threshold-mv = <4390>;
+ qcom,nom-batt-capacity-mah = <680>;
+ qcom,batt-id-kohm = <200>;
+ qcom,battery-beta = <3435>;
+ qcom,battery-type =
+ "3388014_i13z5p_680mah_averaged_masterslave_mar26th2018";
+ qcom,checksum = <0x8C0B>;
+ qcom,gui-version = "PM660GUI - 0.0.0.45";
+ qcom,fg-profile-data = [
+ 5E 24 56 0C
+ E9 12 B0 0D
+ 05 1D 59 01
+ F8 05 8C 02
+ 24 1B CF 13
+ D6 35 86 3B
+ A2 00 00 00
+ 1A 00 00 00
+ 00 00 1F CD
+ 57 AD 6C CA
+ 47 00 08 00
+ FD DA E6 ED
+ 09 EC 03 E2
+ 58 07 89 01
+ 21 14 BA 5A
+ 0A 06 09 20
+ 27 00 14 00
+ 55 20 C3 04
+ 3A 0B 7C 05
+ 01 1D 39 02
+ 41 0D 1A 0B
+ 89 18 A6 2B
+ 2E 54 B7 72
+ 75 00 00 00
+ 07 00 00 00
+ 00 00 9C CC
+ DE C3 51 A4
+ 48 00 00 00
+ 77 EB E6 ED
+ 6F EC D3 D2
+ FF 07 DF F3
+ 91 E3 56 1A
+ 99 33 CC FF
+ 07 10 00 00
+ BB 02 66 46
+ 48 00 40 00
+ D8 02 0A FA
+ FF 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ ];
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/fg-gen3-batterydata-ascent-3450mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/fg-gen3-batterydata-ascent-3450mah.dtsi
new file mode 100755
index 0000000..c8aab94
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/fg-gen3-batterydata-ascent-3450mah.dtsi
@@ -0,0 +1,78 @@
+qcom,ascent_3450mah {
+ /* Ascent_wConn_Aging_3450mAh_averaged_MasterSlave_Jul11th2017 */
+ qcom,max-voltage-uv = <4350000>;
+ qcom,fg-cc-cv-threshold-mv = <4340>;
+ qcom,fastchg-current-ma = <3450>;
+ qcom,batt-id-kohm = <60>;
+ qcom,jeita-fcc-ranges = <0 100 1725000
+ 101 400 3450000
+ 401 450 2760000>;
+ qcom,jeita-fv-ranges = <0 100 4250000
+ 101 400 4350000
+ 401 450 4250000>;
+ qcom,step-chg-ranges = <3600000 4200000 3450000
+ 4201000 4300000 2760000
+ 4301000 4350000 2070000>;
+ qcom,battery-beta = <3435>;
+ qcom,battery-type = "ascent_3450mah_averaged_masterslave_oct30th2017";
+ qcom,checksum = <0xAAE2>;
+ qcom,gui-version = "PMI8998GUI - 2.0.0.58";
+ qcom,fg-profile-data = [
+ 8F 1F 94 05
+ 73 0A 4A 06
+ 27 1D 21 EA
+ 16 0A 3A 0C
+ 07 18 97 22
+ A5 3C EC 4A
+ 5C 00 00 00
+ 10 00 00 00
+ 00 00 43 C5
+ 92 BC 89 BB
+ 11 00 08 00
+ 69 DA AD 07
+ 4B FD 19 FA
+ 7E 01 49 13
+ EB F3 78 3B
+ 24 06 09 20
+ 27 00 14 00
+ 7E 1F F2 05
+ 19 0A AB 06
+ 6C 1D B9 07
+ 1A 12 FF 1D
+ 6F 18 EB 22
+ B9 45 6F 52
+ 55 00 00 00
+ 0E 00 00 00
+ 00 00 33 CC
+ 72 CA B3 C4
+ 0F 00 00 00
+ 93 00 AD 07
+ 8D FD F6 00
+ 6F E3 44 0B
+ AB FC F9 1B
+ C3 33 CC FF
+ 07 10 00 00
+ A4 0D 99 45
+ 0F 00 40 00
+ A4 01 0A FA
+ FF 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ ];
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/fg-gen3-batterydata-itech-3000mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/fg-gen3-batterydata-itech-3000mah.dtsi
new file mode 100755
index 0000000..5a3d5ac
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/fg-gen3-batterydata-itech-3000mah.dtsi
@@ -0,0 +1,69 @@
+qcom,itech_3000mah {
+ /* #Itech_B00826LF_3000mAh_ver1660_averaged_MasterSlave_Jan10th2017*/
+ qcom,max-voltage-uv = <4350000>;
+ qcom,fg-cc-cv-threshold-mv = <4340>;
+ qcom,fastchg-current-ma = <2000>;
+ qcom,batt-id-kohm = <100>;
+ qcom,battery-beta = <3435>;
+ qcom,battery-type = "itech_b00826lf_3000mah_ver1660_jan10th2017";
+ qcom,checksum = <0xFB8F>;
+ qcom,gui-version = "PMI8998GUI - 2.0.0.54";
+ qcom,fg-profile-data = [
+ A4 1F 6E 05
+ 9C 0A 2B FC
+ 32 1D 23 E5
+ 60 0B 1B 15
+ AD 17 8C 22
+ EA 3C 89 4A
+ 5B 00 00 00
+ 12 00 00 00
+ 00 00 62 C2
+ 0C CD D8 C2
+ 19 00 08 00
+ 85 EA C7 EC
+ E2 05 2F 01
+ 9B F5 12 12
+ 5E 05 88 3B
+ 22 06 09 20
+ 27 00 14 00
+ 7D 1F DD 05
+ 3F 0A E5 FC
+ 72 1D E3 F5
+ 6F 12 C0 1D
+ 88 18 FB 22
+ 8D 45 C6 52
+ 54 00 00 00
+ 0F 00 00 00
+ 00 00 BD CD
+ 55 C2 5D C5
+ 14 00 00 00
+ 7E 00 C7 EC
+ 60 06 BB 00
+ 59 06 61 03
+ D9 FC 75 1B
+ B3 33 CC FF
+ 07 10 00 00
+ 3E 0B 99 45
+ 14 00 40 00
+ AE 01 0A FA
+ FF 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ ];
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/fg-gen3-batterydata-qrd-skuk-4v4-3000mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/fg-gen3-batterydata-qrd-skuk-4v4-3000mah.dtsi
new file mode 100755
index 0000000..8c157e4
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/fg-gen3-batterydata-qrd-skuk-4v4-3000mah.dtsi
@@ -0,0 +1,69 @@
+qcom,qrd_msm8998_skuk_3000mah {
+ /* QRD8997_ST1031GA_3000mAh_averaged_MasterSlave_Jan10th2017 */
+ qcom,max-voltage-uv = <4400000>;
+ qcom,fg-cc-cv-threshold-mv = <4390>;
+ qcom,fastchg-current-ma = <3000>;
+ qcom,batt-id-kohm = <68>;
+ qcom,battery-beta = <3380>;
+ qcom,battery-type = "qrd8997_st1031ga_3000mah";
+ qcom,checksum = <0xD299>;
+ qcom,gui-version = "PMI8998GUI - 2.0.0.54";
+ qcom,fg-profile-data = [
+ 70 1F B1 05
+ 6F 0A A1 FC
+ 8C 1D D7 FD
+ C4 12 AC 1D
+ 7E 18 01 23
+ 8C 45 B6 52
+ 55 00 00 00
+ 0F 00 00 00
+ 00 00 92 C5
+ 95 CD A0 CA
+ 1F 00 08 00
+ 9F E3 C3 EC
+ F7 FC 25 F3
+ 02 01 FF 12
+ 29 DC 1D 3A
+ 1C 06 09 20
+ 27 00 14 00
+ AC 1F B4 05
+ 57 0A EF FC
+ 6A 1D E9 E2
+ 11 0B BB 14
+ 40 19 DC 22
+ 79 45 03 53
+ 53 00 00 00
+ 0E 00 00 00
+ 00 00 05 CC
+ 3A BB 24 CA
+ 1C 00 00 00
+ 56 F2 C3 EC
+ A6 06 A2 F2
+ 9A 06 CC 01
+ 8C EA CF 1A
+ BA 33 CC FF
+ 07 10 00 00
+ 3A 0C 66 46
+ 1C 00 40 00
+ 98 01 0A FA
+ FF 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ ];
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-alium-3600mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-alium-3600mah.dtsi
new file mode 100755
index 0000000..0be77e5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-alium-3600mah.dtsi
@@ -0,0 +1,141 @@
+qcom,alium_860_89032_0000_3600mah_averaged_masterslave_sep24th2018 {
+ /* #Alium_860_89032_0000_3600mAh_averaged_MasterSlave_Sept24th2018*/
+ qcom,max-voltage-uv = <4350000>;
+ qcom,fastchg-current-ma = <5400>;
+ qcom,jeita-fcc-ranges = <0 100 2500000
+ 101 400 3600000
+ 401 450 2500000>;
+ qcom,jeita-fv-ranges = <0 100 4250000
+ 101 400 4350000
+ 401 450 4250000>;
+ qcom,step-chg-ranges = <3600000 3800000 5400000
+ 3800001 4300000 3600000
+ 4300001 4350000 2500000>;
+ /* COLD = 0 DegC, HOT = 45 DegC */
+ qcom,jeita-hard-thresholds = <0x58cd 0x20b8>;
+ /* COOL = 10 DegC, WARM = 40 DegC */
+ qcom,jeita-soft-thresholds = <0x4ccc 0x25e3>;
+ /* COLD hys = 13 DegC, WARM hys = 37 DegC */
+ qcom,jeita-soft-hys-thresholds = <0x48d4 0x2943>;
+ qcom,jeita-soft-fcc-ua = <2500000 2500000>;
+ qcom,jeita-soft-fv-uv = <4250000 4250000>;
+ qcom,ocv-based-step-chg;
+ qcom,batt-id-kohm = <107>;
+ qcom,battery-beta = <4250>;
+ qcom,therm-room-temp = <100000>;
+ qcom,fg-cc-cv-threshold-mv = <4340>;
+ qcom,battery-type = "alium_860_89032_0000_3600mah_sept24th2018";
+ qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>;
+ qcom,therm-center-offset = <0x70>;
+ qcom,therm-pull-up = <100>;
+ qcom,rslow-normal-coeffs = <0xdf 0x02 0x77 0x1a>;
+ qcom,rslow-low-coeffs = <0x51 0x04 0xd0 0x13>;
+ qcom,checksum = <0x1538>;
+ qcom,gui-version = "PM855GUI - 1.0.0.10";
+ qcom,fg-profile-data = [
+ 09 00 C7 EA
+ C4 DC 8E E2
+ 3A DD 00 00
+ 15 BC A5 8A
+ 02 80 D1 92
+ AB 9D 47 80
+ 10 00 DF 02
+ 77 1A 85 EC
+ E1 FD CE 07
+ 32 00 75 EB
+ AA ED F3 CD
+ 0C 0A 7A E4
+ ED C5 40 1B
+ D0 02 1F CA
+ FF 00 52 00
+ 4D 00 4A 00
+ 3C 00 35 00
+ 38 00 39 00
+ 48 00 43 00
+ 3F 00 FF 00
+ 38 00 40 00
+ 46 00 50 00
+ 45 00 5C 00
+ 7E 64 60 00
+ 50 08 50 10
+ FF 00 6A 00
+ 5F 00 63 00
+ 6E 00 60 00
+ 7D 20 96 40
+ 75 50 6B 13
+ 63 00 D8 00
+ 14 22 7E 0D
+ 21 02 AA 04
+ ED 1C D4 09
+ 64 0C D3 23
+ A4 18 D3 42
+ B5 55 91 02
+ 90 12 2A 1F
+ 02 06 1F 0A
+ A3 06 AE 1C
+ 8D 02 96 04
+ D2 03 D1 17
+ 51 23 3F 45
+ 28 53 69 14
+ 93 20 8E EC
+ 18 CB C8 C5
+ DB 1C 7B C9
+ 7C 05 E6 C2
+ B9 17 2C 93
+ 87 85 A2 92
+ 91 A8 09 80
+ 92 F2 1A 0D
+ F4 FC 5E EB
+ 00 F8 FB ED
+ 15 E2 F6 0F
+ 75 02 72 05
+ 49 01 10 00
+ FA E5 E2 03
+ 8D 05 85 02
+ CE 07 32 00
+ 23 03 46 02
+ 9C 04 03 02
+ 48 07 0A 00
+ BA 03 97 02
+ 65 05 50 00
+ 3A 00 41 00
+ 43 64 45 00
+ 45 10 45 18
+ 46 08 44 00
+ 47 00 3A 08
+ 4B 08 37 00
+ 47 20 4E 40
+ 54 58 60 10
+ 57 00 5F 00
+ 57 08 55 00
+ 4B 00 50 00
+ 3E 08 52 08
+ 52 00 5C 20
+ 6F 40 7D 58
+ 67 10 63 00
+ 69 08 4F 10
+ D8 00 8C 2A
+ DB 04 28 02
+ AD 04 0B 1D
+ 50 22 A7 45
+ 0D 52 A2 18
+ 74 03 AD 04
+ 35 02 AE 13
+ 3F 0A 5A 20
+ DD 04 F1 02
+ D8 05 C7 1C
+ DD 02 3D 04
+ EB 03 97 18
+ 52 03 D5 04
+ 19 02 72 00
+ 14 22 7E 05
+ 21 02 AA 04
+ ED 1C D4 01
+ 64 04 D3 03
+ A4 18 D3 02
+ B5 05 91 02
+ 90 00 7C 01
+ C0 00 FA 00
+ 04 0E 00 00
+ ];
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-ascent-3450mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-ascent-3450mah.dtsi
new file mode 100755
index 0000000..5c8618c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-ascent-3450mah.dtsi
@@ -0,0 +1,139 @@
+qcom,ascent_wconn_3450mah_fresh_averaged_masterslave_feb28th2019 {
+ qcom,profile-revision = <24>;
+ /* #Ascent_wConn_3450mAh_Fresh_averaged_MasterSlave_Feb28th2019*/
+ qcom,max-voltage-uv = <4350000>;
+ qcom,fastchg-current-ma = <3450>;
+ qcom,jeita-fcc-ranges = <0 100 1725000
+ 101 400 3450000
+ 401 450 2760000>;
+ qcom,jeita-fv-ranges = <0 100 4250000
+ 101 400 4350000
+ 401 450 4250000>;
+ /* COLD = 0 DegC, HOT = 45 DegC */
+ qcom,jeita-hard-thresholds = <0x58cd 0x20b8>;
+ /* COOL = 10 DegC, WARM = 40 DegC */
+ qcom,jeita-soft-thresholds = <0x4ccc 0x25e3>;
+ /* COLD hys = 13 DegC, WARM hys = 37 DegC */
+ qcom,jeita-soft-hys-thresholds = <0x48d4 0x2943>;
+ qcom,jeita-soft-fcc-ua = <1725000 2760000>;
+ qcom,jeita-soft-fv-uv = <4250000 4250000>;
+ qcom,fg-cc-cv-threshold-mv = <4340>;
+ qcom,nom-batt-capacity-mah = <3450>;
+ qcom,batt-id-kohm = <60>;
+ qcom,battery-beta = <3435>;
+ qcom,therm-room-temp = <68000>;
+ qcom,battery-type = "ascent_3450mah_averaged_masterslave_feb28th2019";
+ qcom,therm-coefficients = <0x2313 0xc42 0xea62 0xcc3d 0x8313>;
+ qcom,therm-center-offset = <0x5b>;
+ qcom,therm-pull-up = <100>;
+ qcom,rslow-normal-coeffs = <0x43 0x0a 0x7b 0x1a>;
+ qcom,rslow-low-coeffs = <0xd0 0x13 0x18 0x22>;
+ qcom,checksum = <0xC0ED>;
+ qcom,gui-version = "PM855GUI - 1.0.0.13";
+ qcom,fg-profile-data = [
+ 09 00 63 EA
+ 65 DD F5 DB
+ 02 D4 00 00
+ A5 BD 62 8A
+ FA 87 3A A4
+ 16 9A D5 80
+ 0E 00 43 0A
+ 7B 1A 3B F4
+ 4D F2 CE 07
+ 32 00 1F F3
+ 18 D4 81 DA
+ D4 02 0B E4
+ F3 C4 F6 1B
+ AB F3 AF C4
+ 60 00 4A 00
+ 42 00 43 00
+ 42 00 3A 00
+ 3C 00 49 00
+ 3D 00 39 00
+ 3A 00 60 00
+ 26 00 24 00
+ 33 00 3D 00
+ 36 00 94 00
+ 58 64 41 00
+ 3A 00 35 08
+ 60 F8 18 00
+ 25 00 3B 08
+ 3C 08 3D 00
+ 83 20 4E 40
+ 44 50 42 12
+ 3E 00 D8 00
+ 6D 20 B5 0C
+ E5 FA 2B 04
+ 7C 1C F0 0A
+ 55 0C A7 23
+ 95 17 74 43
+ 11 55 74 03
+ 79 14 A1 1F
+ 9B 05 5A 02
+ EF F4 AE 1C
+ 34 02 90 05
+ 8E 0A 1D 17
+ 66 23 70 45
+ A8 52 7B 14
+ DE 1E 75 EE
+ 7D D3 02 C4
+ AA 1C F8 C1
+ 06 04 25 BA
+ 33 18 BD 8A
+ F2 85 21 A2
+ 78 98 09 80
+ 3D FA AD 0D
+ 2F 02 61 03
+ 00 F8 DF D5
+ 6D EA F9 0F
+ E8 F5 6A D5
+ 0F 11 0C 18
+ 03 F5 6A 03
+ B0 05 D8 01
+ CE 07 32 00
+ 9F 03 19 04
+ 0B 05 5D 02
+ 79 03 E4 05
+ 4A 03 FB 05
+ AB 02 55 00
+ 3F 00 41 00
+ 40 64 40 00
+ 44 F8 37 00
+ 3B F0 41 00
+ 43 00 36 10
+ 60 10 3E 00
+ 4A 20 4E 40
+ 52 58 5D 0F
+ 45 00 46 00
+ 4B 08 5E F8
+ 43 00 5E 00
+ 42 08 52 10
+ 50 00 65 20
+ 78 40 59 50
+ 65 12 66 00
+ 5E 00 47 08
+ D8 00 A8 1F
+ 53 04 7D 0B
+ 52 0C A9 1C
+ 7D 23 B8 45
+ 44 52 5E 18
+ A8 03 4D 04
+ 9D 02 6C 13
+ 3F 0A 85 1F
+ F5 05 11 02
+ 6D 05 A7 1C
+ 0E 03 06 04
+ 11 02 47 18
+ 1C 03 61 05
+ 15 03 6C 00
+ 6C 20 DD 04
+ E4 02 EF 05
+ C4 1C 1F 02
+ D9 05 31 02
+ 7B 18 C5 02
+ D2 05 60 02
+ 85 00 A4 01
+ C0 00 FA 00
+ A4 0D 00 00
+ ];
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-atl466274-3650mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-atl466274-3650mah.dtsi
new file mode 100755
index 0000000..f5e78e3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-atl466274-3650mah.dtsi
@@ -0,0 +1,138 @@
+
+qcom,atl466274_3650mah_averaged_masterslave_may14th2019 {
+ /* #ATL466274_3650mAh_averaged_MasterSlave_May14th2019*/
+ qcom,max-voltage-uv = <4400000>;
+ qcom,fg-cc-cv-threshold-mv = <4390>;
+ qcom,fastchg-current-ma = <5325>;
+ qcom,batt-id-kohm = <31>;
+ /* COLD = 0 DegC, HOT = 55 DegC */
+ qcom,jeita-hard-thresholds = <0x58cd 0x181d>;
+ /* COOL = 10 DegC, WARM = 45 DegC */
+ qcom,jeita-soft-thresholds = <0x4ccc 0x20b8>;
+ /* COOL hys = 13 DegC, WARM hys = 42 DegC */
+ qcom,jeita-soft-hys-thresholds = <0x48d4 0x23c0>;
+ qcom,jeita-fcc-ranges = <0 100 1065000
+ 101 200 1775000
+ 201 450 5325000
+ 451 550 1775000>;
+ qcom,jeita-fv-ranges = <0 100 4400000
+ 101 200 4400000
+ 201 450 4400000
+ 451 550 4050000>;
+ qcom,jeita-soft-fcc-ua = <1065000 1775000>;
+ qcom,jeita-soft-fv-uv = <4400000 4050000>;
+ qcom,battery-beta = <4250>;
+ qcom,battery-type = "ATL466274_3650mah_masterslave_may14th2019";
+ qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>;
+ qcom,therm-center-offset = <0x70>;
+ qcom,rslow-normal-coeffs = <0xb1 0xfa 0x99 0x13>;
+ qcom,rslow-low-coeffs = <0x79 0x15 0x21 0xfa>;
+ qcom,checksum = <0xCC95>;
+ qcom,gui-version = "PM855GUI - 1.0.0.13";
+ qcom,fg-profile-data = [
+ 09 00 CB E3
+ B1 DD D0 DB
+ 31 D4 00 00
+ 9F BD BE 83
+ FE 87 38 9C
+ 6C 87 9B 80
+ 1A 00 B1 FA
+ 99 13 B9 06
+ 13 FA CE 07
+ 32 00 3D EB
+ F9 ED BF D5
+ 38 0A 45 DB
+ BD 9C 6F 12
+ 8B E3 55 C4
+ 60 00 4A 00
+ 47 00 43 00
+ 34 00 31 00
+ 34 00 43 00
+ 40 00 42 00
+ 44 00 60 00
+ 33 00 3D 00
+ 47 00 3F 00
+ 37 00 75 00
+ 5D 64 49 00
+ 40 00 40 08
+ 60 00 50 00
+ 4C 00 58 08
+ 4C 10 45 00
+ 84 28 5D 48
+ 4F 58 48 0E
+ 45 00 D8 08
+ 6F 20 6F 14
+ 61 03 7F FD
+ A0 1C E7 02
+ 0D 04 24 22
+ 9B 17 2C 42
+ B2 55 61 03
+ 71 13 44 22
+ 57 05 4B 0A
+ 5F 04 06 1D
+ D3 02 A2 05
+ F5 02 30 18
+ 25 23 6C 45
+ E4 52 95 12
+ D5 1F 3F E5
+ D9 CA DF BD
+ E0 1C 8B C9
+ 5B 05 43 BB
+ 55 17 B2 8B
+ E2 84 97 93
+ 84 98 09 80
+ A3 03 CD 05
+ 66 05 3D F2
+ 00 F8 58 D5
+ E3 E2 F7 07
+ D5 EB 0A C5
+ 37 18 17 00
+ 33 E7 CB 02
+ 36 07 5E 03
+ CE 07 32 00
+ 2B 03 07 04
+ 3D 05 D6 02
+ EB 05 73 03
+ 9F 03 33 03
+ 02 05 4C 00
+ 3D 00 42 00
+ 42 64 46 00
+ 4A 00 3E 08
+ 44 F8 46 00
+ 46 00 3B 10
+ 3E 10 3B 00
+ 49 28 4A 48
+ 52 60 64 0D
+ 40 00 48 00
+ 50 08 4C 00
+ 39 00 3E 00
+ 3D 10 48 10
+ 42 00 51 20
+ 65 40 43 58
+ 4D 0E 48 00
+ 38 00 20 08
+ D8 00 2D 20
+ 39 05 B1 0A
+ 33 0C BD 1C
+ 71 23 97 45
+ 8D 52 5C 18
+ 22 02 7F 05
+ 0C 02 6A 11
+ 3F 0A 36 20
+ E5 04 25 03
+ 8D 05 C5 1C
+ FD 02 FA 05
+ 37 02 88 18
+ B2 03 1A 04
+ DA 02 6C 00
+ 78 20 8C 04
+ 75 03 37 05
+ D7 1C 3B 02
+ 84 05 BF 02
+ 93 18 11 03
+ 4E 05 45 03
+ 7A 00 1D 01
+ C0 00 FA 00
+ 47 0E 00 00
+ ];
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-goertek-6100mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-goertek-6100mah.dtsi
new file mode 100755
index 0000000..42b6763
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-goertek-6100mah.dtsi
@@ -0,0 +1,123 @@
+qcom,4295629_goertek_vdl_6100mah_pm8150b_sep18th2020 {
+ /* 4295629_Goertek_MorpheusVDL_6100mAh_avged_MasterSlave_Sept18th2020 */
+ qcom,max-voltage-uv = <4350000>;
+ qcom,fg-cc-cv-threshold-mv = <4340>;
+ qcom,nom-batt-capacity-mah = <6100>;
+ qcom,batt-id-kohm = <35>;
+ qcom,battery-beta = <4250>;
+ qcom,therm-room-temp = <100000>;
+ qcom,battery-type = "4295629_goertek_vdl_6100mah_pm8150b_sep18th2020";
+ qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>;
+ qcom,therm-center-offset = <0x70>;
+ qcom,therm-pull-up = <100>;
+ qcom,rslow-normal-coeffs = <0x4d 0xf4 0xd1 0x12>;
+ qcom,rslow-low-coeffs = <0x5e 0x15 0x67 0x07>;
+ qcom,checksum = <0xF24D>;
+ qcom,gui-version = "PM855GUI - 1.0.0.14";
+ qcom,fg-profile-data = [
+ 09 00 8B E2
+ ED DD A2 DB
+ 26 D4 00 00
+ 39 B5 DC 83
+ F7 87 C8 82
+ DF 8D 03 80
+ 23 00 4D F4
+ D1 12 76 04
+ FC 02 CE 07
+ 32 00 FD EA
+ E4 ED F5 CB
+ 20 03 47 DA
+ 69 B2 EF 1A
+ 85 01 DA BB
+ 60 00 46 00
+ 46 00 44 00
+ 38 00 30 00
+ 34 00 3B 00
+ 49 00 48 00
+ 4B 00 60 00
+ 3E 00 3C 00
+ 3C 00 39 00
+ 33 00 59 00
+ 4B 64 4A 00
+ 44 00 47 08
+ 60 F0 51 00
+ 4D 00 54 10
+ 4D 10 47 00
+ 74 20 5D 40
+ 51 50 4C 11
+ 4B 00 D8 00
+ DB 1F 97 05
+ 05 EA 53 04
+ 44 1C CD 0B
+ 6E 0D 86 22
+ 0A 18 23 43
+ 50 5D 3E 03
+ 6F 11 84 1E
+ FD FE 89 02
+ 19 04 D3 1C
+ 23 FA 5B 05
+ 00 03 DF 17
+ A2 23 B1 44
+ 12 52 67 14
+ 85 1E EB E5
+ A6 CA 6B CF
+ DD 1C FD A2
+ 7A 05 EF B2
+ E6 17 01 83
+ B9 85 5E A2
+ 7D A0 09 80
+ 5B FA 8F FC
+ EA 02 D0 03
+ 00 00 BC DD
+ 86 EA FC 07
+ 19 F2 EC D5
+ FB 1F 17 00
+ A9 EC 27 02
+ 05 06 B1 01
+ CE 07 32 00
+ 84 01 37 02
+ C9 05 EE 02
+ DF 05 44 03
+ 58 02 50 03
+ 9E 05 4D 00
+ 3F 00 41 00
+ 42 64 47 00
+ 4A 00 42 08
+ 49 00 45 00
+ 47 00 3E 10
+ 4B 10 3F 00
+ 47 28 47 48
+ 4F 60 57 0C
+ 41 00 55 F8
+ 52 08 50 00
+ 39 00 48 00
+ 3B 08 47 10
+ 49 00 5B 20
+ 68 40 4A 58
+ 55 0F 4E 00
+ 45 00 2A 00
+ D8 F8 05 20
+ A7 05 32 0A
+ 96 0E CE 1C
+ 71 23 9E 45
+ 70 52 7E 18
+ 44 02 1B 05
+ 90 02 6A 11
+ 3F 0A 85 1F
+ 07 04 06 02
+ BB 06 CE 1C
+ EE 02 17 04
+ 13 02 9F 18
+ 88 03 67 04
+ 8C 02 6A 00
+ 08 1F 7E 06
+ 70 03 FD 05
+ D0 1C 6B 02
+ 17 05 24 03
+ AC 18 14 03
+ 3A 05 76 03
+ 6C 00 DF 00
+ C0 00 FA 00
+ 59 19 00 00
+ ];
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-goertek-650mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-goertek-650mah.dtsi
new file mode 100755
index 0000000..f85b7aa
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-goertek-650mah.dtsi
@@ -0,0 +1,123 @@
+qcom,5376013_goertek_oracle_650mah_pm8150b_sept23rd2021 {
+ /* #5376013_Goertek_Oracle_650mAH_averaged_MasterSlave_Sept23rd2021*/
+ qcom,max-voltage-uv = <4480000>;
+ qcom,fg-cc-cv-threshold-mv = <4470>;
+ qcom,nom-batt-capacity-mah = <650>;
+ qcom,batt-id-kohm = <100>;
+ qcom,battery-beta = <4250>;
+ qcom,therm-room-temp = <100000>;
+ qcom,battery-type = "goertek_oracle_650mah_pm8150b_sept23rd2021";
+ qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>;
+ qcom,therm-center-offset = <0x70>;
+ qcom,therm-pull-up = <100>;
+ qcom,rslow-normal-coeffs = <0x3b 0xf2 0x34 0x0b>;
+ qcom,rslow-low-coeffs = <0x3f 0x0d 0x0c 0xea>;
+ qcom,checksum = <0x4B53>;
+ qcom,gui-version = "PM855GUI - 1.0.0.14";
+ qcom,fg-profile-data = [
+ 09 00 2F 01
+ F8 05 9C 03
+ 0F FC 00 00
+ 3D CC 0D A2
+ CC 87 E0 C2
+ F1 C5 80 87
+ 52 00 3B F2
+ 34 0B FE D5
+ 9A E2 CE 07
+ 32 00 6E F2
+ 15 E2 4A E2
+ 62 13 97 F2
+ FA C5 F1 1A
+ 15 07 DE CD
+ 60 00 42 00
+ 40 00 3E 00
+ 39 00 3D 00
+ 3C 00 41 00
+ 51 00 54 00
+ 4C 00 60 00
+ 34 00 3F 00
+ 40 00 38 00
+ 44 00 36 00
+ 61 64 4A 00
+ 3B E8 3E 00
+ 60 F0 21 00
+ 28 08 23 18
+ 30 18 3D 00
+ 2A 18 53 40
+ 30 58 2A 07
+ 33 00 D8 00
+ 6F 1C 14 0B
+ 1C 02 59 0D
+ 6E 19 D9 13
+ 4E 0D 1E 1B
+ B6 18 43 33
+ 78 3D 80 03
+ 4F 1B 3C 1F
+ 2A 05 63 0B
+ 30 05 C3 19
+ 85 0A EC 0D
+ 6B 0B C4 17
+ 68 1A C5 2D
+ 60 3B 85 20
+ ED 1E 75 F5
+ 3E F3 40 F5
+ FE 19 3D EA
+ 97 04 D5 CA
+ E3 17 1E A2
+ BA 84 0E CA
+ 87 C0 09 80
+ B6 03 29 FD
+ B7 03 1C 05
+ 00 F8 87 E4
+ 04 D2 CB DF
+ 50 E2 8D CC
+ E4 25 30 00
+ E8 E6 85 02
+ EF 06 7E 00
+ CE 07 32 00
+ 15 03 56 02
+ C3 05 C9 05
+ 62 04 42 02
+ C4 02 49 01
+ EB 05 60 00
+ 39 00 46 00
+ 47 64 4B 00
+ 52 08 53 10
+ 52 08 51 00
+ 50 00 3F 08
+ 60 08 54 00
+ 5B 20 5B 38
+ 58 48 6B 15
+ 74 00 5E 08
+ 6B 10 60 00
+ 6C 00 60 00
+ 77 08 69 08
+ 70 00 5F 20
+ 73 38 7E 48
+ 60 18 6F 00
+ 72 08 8B 10
+ D8 08 7F 23
+ 9F 04 F1 02
+ 83 05 E1 1C
+ 27 22 DF 3D
+ 4E 4A C7 18
+ 7B 02 65 04
+ A4 03 8E 17
+ 3F 0A 8C 21
+ 99 05 4E 02
+ 25 04 9A 1C
+ 3B 02 F0 05
+ 4A 02 C4 18
+ 0F 02 69 05
+ 49 02 87 00
+ 38 22 36 05
+ 9E 02 C3 05
+ 65 1C 21 02
+ D7 04 89 03
+ B0 18 07 02
+ 67 05 59 02
+ 91 00 10 03
+ C0 00 FA 00
+ 93 02 00 00
+ ];
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-mlp466274-3650mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-mlp466274-3650mah.dtsi
new file mode 100755
index 0000000..5c82394
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/fg-gen4-batterydata-mlp466274-3650mah.dtsi
@@ -0,0 +1,135 @@
+qcom,mlp466274_3650mah_averaged_masterslave_jan21st2019 {
+ /* #mlp466274_3650mAh_averaged_MasterSlave_Jan21st2019*/
+ qcom,max-voltage-uv = <4400000>;
+ qcom,fg-cc-cv-threshold-mv = <4390>;
+ qcom,fastchg-current-ma = <5325>;
+ qcom,batt-id-kohm = <44>;
+ /* COLD = 0 DegC, HOT = 55 DegC */
+ qcom,jeita-hard-thresholds = <0x58cd 0x181d>;
+ /* COOL = 15 DegC, WARM = 45 DegC */
+ qcom,jeita-soft-thresholds = <0x4621 0x20b8>;
+ /* COOL hys = 18 DegC, WARM hys = 42 DegC */
+ qcom,jeita-soft-hys-thresholds = <0x4206 0x23c0>;
+ qcom,jeita-fcc-ranges = <0 150 710000
+ 151 450 5325000
+ 451 550 1775000>;
+ qcom,jeita-fv-ranges = <0 150 4150000
+ 151 450 4400000
+ 451 550 4150000>;
+ qcom,jeita-soft-fcc-ua = <710000 1775000>;
+ qcom,jeita-soft-fv-uv = <4150000 4150000>;
+ qcom,battery-beta = <4250>;
+ qcom,battery-type = "mlp466274_3650mah_masterslave_jan21st2019";
+ qcom,therm-coefficients = <0x2318 0xd0c 0xdaf7 0xc556 0x848d>;
+ qcom,therm-center-offset = <0x70>;
+ qcom,rslow-normal-coeffs = <0xa9 0x15 0x87 0x0d>;
+ qcom,rslow-low-coeffs = <0xae 0x0c 0x65 0xfc>;
+ qcom,checksum = <0x393C>;
+ qcom,gui-version = "PM855GUI - 1.0.0.13";
+ qcom,fg-profile-data = [
+ 09 00 15 EA
+ CA DC 05 E3
+ 99 DC 00 00
+ A6 BD 4F 8A
+ F9 87 88 9D
+ 79 9A E7 87
+ 48 00 A9 15
+ 87 0D 7C 04
+ 30 02 CE 07
+ 32 00 BF EB
+ 95 ED 67 D5
+ 16 0A 1A EB
+ 5C B2 FE 0D
+ A9 06 23 BB
+ 60 00 3E 00
+ 3D 00 3E 00
+ 38 00 32 00
+ 33 00 38 00
+ 40 00 4A 00
+ 5A 00 60 00
+ 51 00 41 00
+ 36 00 31 00
+ 2E 00 3C 00
+ 45 64 43 00
+ 47 00 40 00
+ 60 00 54 00
+ 45 00 50 08
+ 53 08 3F 00
+ 66 28 61 48
+ 51 58 4A 0E
+ 47 00 D8 00
+ F6 1F 7F 0D
+ FA 03 53 07
+ 73 1C DE 0A
+ 82 0C 64 23
+ 1A 17 4E 42
+ 8C 55 99 03
+ 7D 13 79 1F
+ 98 05 91 0A
+ 2B 06 BE 1C
+ 32 02 67 05
+ F4 02 F9 17
+ 27 23 72 45
+ DB 52 72 13
+ FE 1F 14 ED
+ F1 CA CA 85
+ D3 1C 8C C1
+ 78 05 11 BB
+ 4C 17 80 8B
+ 33 85 0F 9B
+ 88 80 09 80
+ 01 F2 F2 05
+ FE 03 AC FB
+ 00 F8 51 DD
+ 44 EB F4 07
+ 89 F5 8C CA
+ 33 18 2A 00
+ 11 DD AB 01
+ 86 05 2F 03
+ CE 07 32 00
+ 3D 03 D9 03
+ 45 05 01 07
+ 23 02 17 05
+ C8 03 9F 07
+ 33 03 50 00
+ 3F 00 3F 00
+ 41 64 43 00
+ 42 F8 3F 00
+ 45 00 44 00
+ 42 00 3B 10
+ 45 10 3D 00
+ 44 20 43 40
+ 45 58 4B 0F
+ 39 00 3A 00
+ 44 08 56 00
+ 4B 00 3E 00
+ 3A 10 48 10
+ 45 00 4D 20
+ 5F 40 40 58
+ 42 10 4E 00
+ 4B 08 2C 10
+ D8 08 B3 1F
+ 41 FC B9 03
+ EF 06 C5 1C
+ 57 23 D8 45
+ 2D 52 7D 18
+ 86 03 8C 04
+ 5C 02 6C 12
+ 3F 0A 68 20
+ D1 04 1D 03
+ A0 05 B9 1C
+ 1B 03 FB 05
+ 1F 02 94 18
+ 4E 03 DD 04
+ 14 02 70 00
+ 9D 23 A2 04
+ D6 02 A4 05
+ E6 1C D7 03
+ 78 04 CB 03
+ 84 18 F7 02
+ 88 05 D7 02
+ 95 00 58 01
+ C0 00 FA 00
+ 29 0E 00 00
+ ];
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/ipcc-test-lagoon.dtsi b/arch/arm64/boot/dts/vendor/qcom/ipcc-test-lagoon.dtsi
new file mode 100755
index 0000000..b4bfb42
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/ipcc-test-lagoon.dtsi
@@ -0,0 +1,9 @@
+#include "ipcc-test.dtsi"
+
+&soc {
+ /delete-node/ ipcc-self-ping-slpi;
+};
+
+&ipcc_self_ping_npu {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/ipcc-test-lito.dtsi b/arch/arm64/boot/dts/vendor/qcom/ipcc-test-lito.dtsi
new file mode 100755
index 0000000..b4bfb42
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/ipcc-test-lito.dtsi
@@ -0,0 +1,9 @@
+#include "ipcc-test.dtsi"
+
+&soc {
+ /delete-node/ ipcc-self-ping-slpi;
+};
+
+&ipcc_self_ping_npu {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/ipcc-test.dtsi b/arch/arm64/boot/dts/vendor/qcom/ipcc-test.dtsi
new file mode 100755
index 0000000..e442628
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/ipcc-test.dtsi
@@ -0,0 +1,38 @@
+#include <dt-bindings/soc/qcom,ipcc.h>
+
+&soc {
+ ipcc_self_ping_apss: ipcc-self-ping-apss {
+ compatible = "qcom,ipcc-self-ping";
+ interrupts-extended = <&ipcc_mproc IPCC_CLIENT_APSS
+ IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_LEVEL_HIGH>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_APSS IPCC_MPROC_SIGNAL_SMP2P>;
+ };
+
+ ipcc_self_ping_cdsp: ipcc-self-ping-cdsp {
+ compatible = "qcom,ipcc-self-ping";
+ interrupts-extended = <&ipcc_mproc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_PING>;
+ };
+
+ ipcc_self_ping_adsp: ipcc-self-ping-adsp {
+ compatible = "qcom,ipcc-self-ping";
+ interrupts-extended = <&ipcc_mproc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_PING>;
+ };
+
+ ipcc_self_ping_slpi: ipcc-self-ping-slpi {
+ compatible = "qcom,ipcc-self-ping";
+ interrupts-extended = <&ipcc_mproc IPCC_CLIENT_SLPI
+ IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_PING>;
+ };
+
+ ipcc_self_ping_npu: ipcc-self-ping-npu {
+ compatible = "qcom,ipcc-self-ping";
+ interrupts-extended = <&ipcc_mproc IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_PING IRQ_TYPE_LEVEL_HIGH>;
+ mboxes = <&msm_npu IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_PING>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-atp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-atp-overlay.dts
new file mode 100755
index 0000000..bc5789f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-atp-overlay.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-atp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Khaje ATP";
+ compatible = "qcom,khaje-atp", "qcom,khaje", "qcom,atp";
+ qcom,msm-id = <518 0x10000>;
+ qcom,board-id = <33 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-atp.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-atp.dts
new file mode 100755
index 0000000..fc94ce2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-atp.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-atp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Khaje ATP";
+ compatible = "qcom,khaje-atp", "qcom,khaje", "qcom,atp";
+ qcom,board-id = <33 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-atp.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-atp.dtsi
new file mode 100755
index 0000000..50b6b9a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-atp.dtsi
@@ -0,0 +1,309 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/input.h>
+#include "bengal-audio-overlay.dtsi"
+#include "khaje-sde-display.dtsi"
+#include "khaje-pm7250b.dtsi"
+
+&pm6125_gpios {
+ eldo9_pin {
+ usb_eldo9:gpio@c000 {
+ pins = "gpio1";
+ function = "normal";
+ qcom,drive-strength = <2>;
+ power-source = <0>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&soc {
+ vdda_usb_ss_dp_core: vdda_usb_ss_dp_core {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_supply";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ enable-active-high;
+ gpio = <&pm6125_gpios 1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_eldo9>;
+ };
+};
+
+&sdhc_1 {
+ vdd-supply = <&L24A>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L11A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&L22A>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L5A>;
+ qcom,vdd-io-voltage-level = <1800000 2960000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ vdd-io-bias-supply = <&L7A>;
+ qcom,vdd-io-bias-voltage-level = <1256000 1256000>;
+ qcom,vdd-io-bias-current-level = <0 6000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v4";
+
+ vdda-phy-supply = <&L4A>; /* 0.9v */
+ vdda-pll-supply = <&L18A>; /* 1.8v */
+ vdda-phy-max-microamp = <85700>;
+ vdda-pll-max-microamp = <18300>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&L24A>;
+ vcc-voltage-level = <2950000 2960000>;
+ vccq2-supply = <&L11A>;
+ vccq2-voltage-level = <1800000 1800000>;
+ vcc-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+ vccq2-pwr-collapse-sup;
+
+ qcom,vddp-ref-clk-supply = <&L18A>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vddp-ref-clk-min-uV = <1232000>;
+ qcom,vddp-ref-clk-max-uV = <1232000>;
+
+ status = "ok";
+};
+
+&usb_qmp_dp_phy {
+ vdd-supply = <&vdda_usb_ss_dp_core>;
+};
+
+&pm6125_vadc {
+ pinctrl-0 = <&camera_therm_default &emmc_therm_default &rf_pa1_therm_default>;
+
+ rf_pa1_therm {
+ reg = <ADC_GPIO4_PU2>;
+ label = "rf_pa1_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm6125_adc_tm {
+ io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>,
+ <&pm6125_vadc ADC_AMUX_THM2_PU2>,
+ <&pm6125_vadc ADC_XO_THERM_PU2>,
+ <&pm6125_vadc ADC_GPIO4_PU2>;
+
+ rf_pa1_therm {
+ reg = <ADC_GPIO4_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&thermal_zones {
+ rf-pa1-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm6125_adc_tm ADC_GPIO4_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&pm6125_gpios {
+
+ rf_pa1_therm {
+ rf_pa1_therm_default: rf_pa1_therm_default {
+ pins = "gpio7";
+ bias-high-impedance;
+ };
+ };
+
+ key_vol_up {
+ key_vol_up_default: key_vol_up_default {
+ pins = "gpio5";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+ };
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ linux,can-disable;
+ debounce-interval = <15>;
+ gpio-key,wakeup;
+ };
+ };
+};
+
+&pm7250b_charger {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+ <&pm7250b_vadc ADC_USB_IN_I>,
+ <&pm7250b_vadc ADC_CHG_TEMP>,
+ <&pm7250b_vadc ADC_DIE_TEMP>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+ <&pm7250b_vadc ADC_SBUx>,
+ <&pm7250b_vadc ADC_VPH_PWR>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp",
+ "die_temp",
+ "conn_temp",
+ "sbux_res",
+ "vph_voltage";
+ qcom,batteryless-platform;
+ qcom,sec-charger-config = <0>;
+ qcom,auto-recharge-soc = <98>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,charger-temp-max = <800>;
+ qcom,suspend-input-on-debug-batt;
+};
+
+&pm7250b_qg {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU2>,
+ <&pm7250b_vadc ADC_BAT_ID_PU2>;
+ io-channel-names = "batt-therm",
+ "batt-id";
+ qcom,qg-iterm-ma = <150>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+};
+
+&pm8008_8 {
+ status = "disabled";
+};
+
+&pm8008_9 {
+ status = "disabled";
+};
+
+&pm6125_pwm {
+ status = "okay";
+};
+
+&dsi_nt36672e_fhd_plus_90hz_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm6125_pwm 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+ qcom,platform-en-gpio = <&pm7250b_gpios 5 0>;
+ qcom,platform-bklight-en-gpio = <&pm7250b_gpios 1 0>;
+ /delete-property/ qcom,esd-check-enabled;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_90hz_video>;
+ pinctrl-0 = <&sde_dsi_active &sde_te_active &disp_lcd_bias_en_default>;
+};
+
+&qupv3_se2_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="novatek,NVT-ts";
+
+ novatek@62 {
+ compatible = "novatek,NVT-ts";
+ reg = <0x62>;
+ status = "ok";
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+
+ novatek,reset-gpio = <&tlmm 86 0x00>;
+ novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+ panel = <&dsi_nt36672e_fhd_plus_90hz_video>;
+ };
+};
+
+&pm7250b_charger {
+ dpdm-supply = <&usb2_phy0>;
+
+ smb5_vbus: qcom,smb5-vbus {
+ regulator-name = "smb5-vbus";
+ };
+
+ smb5_vconn: qcom,smb5-vconn {
+ regulator-name = "smb5-vconn";
+ };
+};
+
+&pm7250b_pdphy {
+ vdd-pdphy-supply = <&L15A>;
+ vbus-supply = <&smb5_vbus>;
+ vconn-supply = <&smb5_vconn>;
+};
+
+&usb0 {
+ extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi-overlay.dts
new file mode 100755
index 0000000..566b24f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-idp-nopmi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. KHAJE IDP nopmi";
+ compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+ qcom,msm-id = <518 0x10000>;
+ qcom,board-id = <0x10022 0>;
+ qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi.dts
new file mode 100755
index 0000000..31d8418
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-idp-nopmi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. KHAJE IDP nopmi";
+ compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+ qcom,board-id = <0x10022 0>;
+ qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi.dtsi
new file mode 100755
index 0000000..ec89efa
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-nopmi.dtsi
@@ -0,0 +1,30 @@
+#include "khaje-idp.dtsi"
+
+&dsi_td4330_truly_v2_video {
+ /delete-property/ qcom,esd-check-enabled;
+};
+
+&dsi_td4330_truly_v2_cmd {
+ /delete-property/ qcom,esd-check-enabled;
+};
+
+&dsi_nt36672e_fhd_plus_90hz_video {
+ /delete-property/ qcom,esd-check-enabled;
+};
+
+&qupv3_se2_i2c {
+ synaptics_tcm@20 {
+ status = "disabled";
+ };
+
+ novatek@62 {
+ status = "disabled";
+ };
+};
+
+&usb0 {
+ /delete-property/ extcon;
+ dwc3@4e00000 {
+ dr_mode = "peripheral";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-overlay.dts
new file mode 100755
index 0000000..dea903c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-overlay.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm7250b.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Khaje IDP";
+ compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+ qcom,msm-id = <518 0x10000>;
+ qcom,board-id = <0x10022 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm7250b.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm7250b.dtsi
new file mode 100755
index 0000000..7008c7e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm7250b.dtsi
@@ -0,0 +1,156 @@
+#include "khaje-pm7250b.dtsi"
+#include "khaje-thermal-pm7250b-overlay.dtsi"
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+&soc {
+ mtp_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "qg-batterydata-alium-3600mah.dtsi"
+ };
+};
+
+&pm7250b_gpios {
+ pm7250b_smb_int_default: pm7250b_smb_int_default {
+ pins = "gpio6";
+ function = "gpio";
+ input-enable;
+ bias-pull-up;
+ qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+ power-source = <0>;
+ };
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #include "smb1355.dtsi"
+};
+
+&smb1355 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm7250b_smb_int_default>;
+ status = "ok";
+};
+
+&smb1355_charger {
+ qcom,parallel-mode = <1>;
+ qcom,hw-die-temp-mitigation;
+ status = "ok";
+};
+
+&pm7250b_charger {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+ <&pm7250b_vadc ADC_USB_IN_I>,
+ <&pm7250b_vadc ADC_CHG_TEMP>,
+ <&pm7250b_vadc ADC_DIE_TEMP>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+ <&pm7250b_vadc ADC_SBUx>,
+ <&pm7250b_vadc ADC_VPH_PWR>,
+ <&pm7250b_vadc ADC_AMUX_THM1_PU2>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp",
+ "die_temp",
+ "conn_temp",
+ "sbux_res",
+ "vph_voltage",
+ "skin_temp";
+ qcom,battery-data = <&mtp_batterydata>;
+ qcom,sec-charger-config = <2>;
+ qcom,auto-recharge-soc = <98>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,fcc-stepping-enable;
+ qcom,fcc-step-delay-ms = <100>;
+ qcom,fcc-step-size-ua = <100000>;
+ qcom,smb-internal-pull-kohm = <0>;
+ qcom,en-skin-therm-mitigation;
+ qcom,hvdcp3-standalone-config;
+};
+
+&pm7250b_qg {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU2>,
+ <&pm7250b_vadc ADC_BAT_ID_PU2>;
+ io-channel-names = "batt-therm",
+ "batt-id";
+ qcom,battery-data = <&mtp_batterydata>;
+ qcom,qg-iterm-ma = <100>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+ qcom,tcss-enable;
+ qcom,fvss-enable;
+ qcom,fvss-vbatt-mv = <3500>;
+ qcom,bass-enable;
+ qcom,vbatt-cutoff-mv = <3400>;
+ qcom,vbatt-low-mv = <3500>;
+ qcom,vbatt-low-cold-mv = <3800>;
+ qcom,vbatt-empty-mv = <3200>;
+ qcom,vbatt-empty-cold-mv = <3100>;
+};
+
+&sde_dsi {
+ pinctrl-0 = <&sde_dsi_active &sde_te_active &disp_lcd_bias_en_default>;
+};
+
+&dsi_td4330_truly_v2_video {
+ qcom,platform-en-gpio = <&pm7250b_gpios 5 0>;
+ qcom,platform-bklight-en-gpio = <&pm7250b_gpios 1 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+ qcom,platform-en-gpio = <&pm7250b_gpios 5 0>;
+ qcom,platform-bklight-en-gpio = <&pm7250b_gpios 1 0>;
+};
+
+&dsi_nt36672e_fhd_plus_90hz_video {
+ qcom,platform-en-gpio = <&pm7250b_gpios 5 0>;
+ qcom,platform-bklight-en-gpio = <&pm7250b_gpios 1 0>;
+};
+
+&dsi_nt36672e_fhd_plus_120hz_video {
+ qcom,platform-en-gpio = <&pm7250b_gpios 5 0>;
+ qcom,platform-bklight-en-gpio = <&pm7250b_gpios 1 0>;
+};
+
+&cam_res_mgr_label {
+ gpios = <&pm7250b_gpios 4 0>;
+};
+
+&led_flash_rear {
+ gpios = <&pm7250b_gpios 4 0>;
+};
+
+&led_flash_rear_aux {
+ gpios = <&pm7250b_gpios 4 0>;
+};
+
+&led_flash_rear_aux2 {
+ gpios = <&pm7250b_gpios 4 0>;
+};
+
+&pm7250b_charger {
+ dpdm-supply = <&usb2_phy0>;
+
+ smb5_vbus: qcom,smb5-vbus {
+ regulator-name = "smb5-vbus";
+ };
+
+ smb5_vconn: qcom,smb5-vconn {
+ regulator-name = "smb5-vconn";
+ };
+};
+
+&pm7250b_pdphy {
+ vdd-pdphy-supply = <&L15A>;
+ vbus-supply = <&smb5_vbus>;
+ vconn-supply = <&smb5_vconn>;
+};
+
+&usb0 {
+ extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm8010-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm8010-overlay.dts
new file mode 100755
index 0000000..6031d88
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm8010-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm8010.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Khaje IDP with PM8010";
+ compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+ qcom,msm-id = <518 0x10000>;
+ qcom,board-id = <0x10222 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm8010.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm8010.dts
new file mode 100755
index 0000000..85b55f0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm8010.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm8010.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. KHAJE IDP with PM8010";
+ compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+ qcom,board-id = <0x10222 0>;
+ qcom,pmic-id = <0x02D 0x2E 0x0 0x0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm8010.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm8010.dtsi
new file mode 100755
index 0000000..5979c7c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-pm8010.dtsi
@@ -0,0 +1,34 @@
+&soc {
+};
+
+&pm8008_regulators {
+ compatible = "qcom,pm8010-regulator";
+};
+
+&L1P {
+ qcom,min-dropout-voltage = <40000>;
+};
+
+&L2P {
+ qcom,min-dropout-voltage = <64000>;
+};
+
+&L3P {
+ qcom,min-dropout-voltage = <96000>;
+};
+
+&L4P {
+ qcom,min-dropout-voltage = <136000>;
+};
+
+&L5P {
+ qcom,min-dropout-voltage = <176000>;
+};
+
+&L6P {
+ qcom,min-dropout-voltage = <168000>;
+};
+
+&L7P {
+ qcom,min-dropout-voltage = <80000>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-usbc-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-usbc-overlay.dts
new file mode 100755
index 0000000..4993cda
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-usbc-overlay.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm7250b.dtsi"
+#include "khaje-idp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. KHAJE IDP USBC Audio";
+ compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+ qcom,msm-id = <518 0x10000>;
+ qcom,board-id = <0x1010022 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-usbc.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-usbc.dts
new file mode 100755
index 0000000..7a62a6d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-usbc.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm7250b.dtsi"
+#include "khaje-idp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. KHAJE IDP USBC Audio";
+ compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+ qcom,msm-id = <518 0x10000>;
+ qcom,board-id = <0x1010022 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp-usbc.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-usbc.dtsi
new file mode 100755
index 0000000..2a627c5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp-usbc.dtsi
@@ -0,0 +1,6 @@
+&bengal_snd {
+ qcom,msm-mbhc-usbc-audio-supported = <1>;
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-idp.dts
new file mode 100755
index 0000000..3787ab3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm7250b.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. KHAJE IDP";
+ compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+ qcom,board-id = <0x10022 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idp.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-idp.dtsi
new file mode 100755
index 0000000..e9b0f26
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idp.dtsi
@@ -0,0 +1,362 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/input.h>
+#include "bengal-audio-overlay.dtsi"
+#include "camera/khaje-camera-sensor-idp.dtsi"
+#include "bengal-thermal-overlay.dtsi"
+#include "khaje-sde-display.dtsi"
+
+&qupv3_se4_2uart {
+ status = "ok";
+};
+
+&pm6125_vadc {
+ pinctrl-0 = <&camera_therm_default &emmc_therm_default &rf_pa1_therm_default>;
+
+ rf_pa1_therm {
+ reg = <ADC_GPIO4_PU2>;
+ label = "rf_pa1_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm6125_adc_tm {
+ io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>,
+ <&pm6125_vadc ADC_AMUX_THM2_PU2>,
+ <&pm6125_vadc ADC_XO_THERM_PU2>,
+ <&pm6125_vadc ADC_GPIO4_PU2>;
+
+ rf_pa1_therm {
+ reg = <ADC_GPIO4_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&thermal_zones {
+ rf-pa1-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm6125_adc_tm ADC_GPIO4_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&pm6125_gpios {
+
+ rf_pa1_therm {
+ rf_pa1_therm_default: rf_pa1_therm_default {
+ pins = "gpio7";
+ bias-high-impedance;
+ };
+ };
+
+ key_vol_up {
+ key_vol_up_default: key_vol_up_default {
+ pins = "gpio5";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+ };
+
+ eldo9_pin {
+ usb_eldo9:gpio@c000 {
+ pins = "gpio1";
+ function = "normal";
+ qcom,drive-strength = <2>;
+ power-source = <0>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ linux,can-disable;
+ debounce-interval = <15>;
+ gpio-key,wakeup;
+ };
+ };
+
+ vdda_usb_ss_dp_core: vdda_usb_ss_dp_core {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_supply";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ enable-active-high;
+ gpio = <&pm6125_gpios 1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_eldo9>;
+ };
+};
+
+&usb_qmp_dp_phy {
+ vdd-supply = <&vdda_usb_ss_dp_core>;
+};
+
+&qupv3_se1_i2c {
+ awinic@64 {
+ compatible = "awinic,aw2016_led";
+ reg = <0x64>;
+
+ awinic,red {
+ awinic,name = "red";
+ awinic,id = <0>;
+ awinic,imax = <2>;
+ awinic,led-current = <3>;
+ awinic,max-brightness = <255>;
+ awinic,rise-time-ms = <6>;
+ awinic,hold-time-ms = <0>;
+ awinic,fall-time-ms = <6>;
+ awinic,off-time-ms = <4>;
+ };
+
+ awinic,green {
+ awinic,name = "green";
+ awinic,id = <1>;
+ awinic,imax = <2>;
+ awinic,led-current = <3>;
+ awinic,max-brightness = <255>;
+ awinic,rise-time-ms = <6>;
+ awinic,hold-time-ms = <0>;
+ awinic,fall-time-ms = <6>;
+ awinic,off-time-ms = <4>;
+ };
+
+ awinic,blue {
+ awinic,name = "blue";
+ awinic,id = <2>;
+ awinic,imax = <2>;
+ awinic,led-current = <3>;
+ awinic,max-brightness = <255>;
+ awinic,rise-time-ms = <6>;
+ awinic,hold-time-ms = <0>;
+ awinic,fall-time-ms = <6>;
+ awinic,off-time-ms = <4>;
+ };
+
+ };
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 70 0x00>;
+ qcom,nq-ven = <&tlmm 69 0x00>;
+ qcom,nq-firm = <&tlmm 31 0x00>;
+ qcom,nq-clkreq = <&tlmm 71 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <70 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&sdhc_1 {
+ vdd-supply = <&L24A>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L11A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&L22A>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L5A>;
+ qcom,vdd-io-voltage-level = <1800000 2960000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ vdd-io-bias-supply = <&L7A>;
+ qcom,vdd-io-bias-voltage-level = <1256000 1256000>;
+ qcom,vdd-io-bias-current-level = <0 6000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v4";
+
+ vdda-phy-supply = <&L4A>; /* 0.9v */
+ vdda-pll-supply = <&L18A>; /* 1.8v */
+ vdda-phy-max-microamp = <85700>;
+ vdda-pll-max-microamp = <18300>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&L24A>;
+ vcc-voltage-level = <2950000 2960000>;
+ vccq2-supply = <&L11A>;
+ vccq2-voltage-level = <1800000 1800000>;
+ vcc-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+ vccq2-pwr-collapse-sup;
+
+ qcom,vddp-ref-clk-supply = <&L18A>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vddp-ref-clk-min-uV = <1232000>;
+ qcom,vddp-ref-clk-max-uV = <1232000>;
+
+ status = "ok";
+};
+
+&pm6125_pwm {
+ status = "ok";
+};
+
+&dsi_td4330_truly_v2_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm6125_pwm 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm6125_pwm 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 81 0>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_nt36672e_fhd_plus_90hz_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm6125_pwm 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_nt36672e_fhd_plus_120hz_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm6125_pwm 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_td4330_truly_v2_video>;
+};
+
+&qupv3_se2_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="synaptics,tcm-i2c";
+
+ synaptics_tcm@20 {
+ compatible = "synaptics,tcm-i2c";
+ reg = <0x20>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+ synaptics,irq-gpio = <&tlmm 80 0x2008>;
+ synaptics,irq-on-state = <0>;
+ synaptics,reset-gpio = <&tlmm 86 0x00>;
+ synaptics,reset-on-state = <0>;
+ synaptics,reset-active-ms = <20>;
+ synaptics,reset-delay-ms = <200>;
+ synaptics,power-delay-ms = <200>;
+ synaptics,ubl-i2c-addr = <0x20>;
+ synaptics,extend_report;
+ synaptics,firmware-name = "synaptics_firmware_k.img";
+
+ panel = <&dsi_td4330_truly_v2_video &dsi_td4330_truly_v2_cmd>;
+ };
+
+ novatek@62 {
+ compatible = "novatek,NVT-ts";
+ reg = <0x62>;
+ status = "ok";
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+
+ novatek,reset-gpio = <&tlmm 86 0x00>;
+ novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+ panel = <&dsi_nt36672e_fhd_plus_90hz_video
+ &dsi_nt36672e_fhd_plus_120hz_video>;
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idps-display-90hz-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-idps-display-90hz-overlay.dts
new file mode 100755
index 0000000..02711ed
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idps-display-90hz-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm7250b.dtsi"
+#include "khaje-idps-display-90hz.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. KHAJE IDPS + 90Hz";
+ compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+ qcom,msm-id = <518 0x10000>;
+ qcom,board-id = <0x10122 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idps-display-90hz.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-idps-display-90hz.dts
new file mode 100755
index 0000000..a9fc4d4
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idps-display-90hz.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-idp.dtsi"
+#include "khaje-idp-pm7250b.dtsi"
+#include "khaje-idps-display-90hz.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. KHAJE IDPS + 90Hz";
+ compatible = "qcom,khaje-idp", "qcom,khaje", "qcom,idp";
+ qcom,board-id = <0x10122 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-idps-display-90hz.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-idps-display-90hz.dtsi
new file mode 100755
index 0000000..f42bc20
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-idps-display-90hz.dtsi
@@ -0,0 +1,6 @@
+&soc {
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_nt36672e_fhd_plus_90hz_video>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-pinctrl.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-pinctrl.dtsi
new file mode 100755
index 0000000..5c85f5f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-pinctrl.dtsi
@@ -0,0 +1,140 @@
+#include "bengal-pinctrl.dtsi"
+
+&tlmm {
+ compatible = "qcom,khaje-pinctrl";
+
+ cam_flash_torch_active: cam_flash_torch_active {
+ /* TORCH */
+ mux {
+ pins = "gpio85";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio85";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_flash_torch_suspend: cam_flash_torch_suspend {
+ /* TORCH */
+ mux {
+ pins = "gpio85";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio85";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_flash_tx_active: cam_flash_tx_active {
+ /* TX */
+ mux {
+ pins = "gpio93";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio93";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_flash_tx_suspend: cam_flash_tx_suspend {
+ /* TX */
+ mux {
+ pins = "gpio93";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio93";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ nfc {
+ nfc_clk_req_active {
+ /* active state */
+ mux {
+ /* GPIO 71: NFC CLOCK REQUEST */
+ pins = "gpio71";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio71";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_clk_req_suspend {
+ /* sleep state */
+ mux {
+ /* GPIO 71: NFC CLOCK REQUEST */
+ pins = "gpio71";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio71";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable;
+ };
+ };
+ };
+
+ pmx_ts_reset_active {
+ ts_reset_active: ts_reset_active {
+ mux {
+ pins = "gpio86";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio86";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_reset_suspend {
+ ts_reset_suspend: ts_reset_suspend {
+ mux {
+ pins = "gpio86";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio86";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_release {
+ ts_release: ts_release {
+ mux {
+ pins = "gpio80", "gpio86";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio80", "gpio86";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-pm7250b.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-pm7250b.dtsi
new file mode 100755
index 0000000..f5761bb
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-pm7250b.dtsi
@@ -0,0 +1,93 @@
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include "pm7250b.dtsi"
+
+&pm7250b_clkdiv {
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+};
+
+&pm7250b_vadc {
+ charger_skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "charger_skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "conn_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm7250b_adc_tm {
+ io-channels = <&pm7250b_vadc ADC_AMUX_THM1_PU2>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>;
+
+ /* Channel nodes */
+ charger_skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&thermal_zones {
+ charger-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm7250b_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ conn-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm7250b_adc_tm ADC_AMUX_THM3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&pm7250b_gpios {
+ disp_lcd_bias_en {
+ disp_lcd_bias_en_default: disp_lcd_bias_en_default {
+ pins = "gpio5";
+ function = "func1";
+ input-disable;
+ output-enable;
+ bias-disable;
+ power-source = <0>;
+ qcom,drive-strength = <2>;
+ };
+ };
+};
+
+&pm7250b_pon {
+ qcom,log-kpd-event;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-hvdcp3p5-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-hvdcp3p5-overlay.dts
new file mode 100755
index 0000000..a5fb87e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-hvdcp3p5-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-qrd.dtsi"
+#include "khaje-qrd-pm7250b.dtsi"
+#include "khaje-qrd-hvdcp3p5.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Khaje QRD HVDCP3P5";
+ compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+ qcom,msm-id = <518 0x10000>;
+ qcom,board-id = <0x1010B 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-hvdcp3p5.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-hvdcp3p5.dts
new file mode 100755
index 0000000..7b4d493
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-hvdcp3p5.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-qrd.dtsi"
+#include "khaje-qrd-pm7250b.dtsi"
+#include "khaje-qrd-hvdcp3p5.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. KHAJE QRD HVDCP3P5";
+ compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+ qcom,board-id = <0x1010B 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-hvdcp3p5.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-hvdcp3p5.dtsi
new file mode 100755
index 0000000..f87a199
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-hvdcp3p5.dtsi
@@ -0,0 +1,20 @@
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+&pm7250b_gpios {
+ pm7250b_smb_int_default: pm7250b_smb_int_default {
+ pins = "gpio6";
+ function = "gpio";
+ input-enable;
+ bias-pull-up;
+ qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+ power-source = <0>;
+ };
+};
+
+&smb1394 {
+ qcom,enable-toggle-stat;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm7250b_smb_int_default>;
+ interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&spmi_bus>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nopmi-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nopmi-overlay.dts
new file mode 100755
index 0000000..eab9366
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nopmi-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-qrd-nopmi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. KHAJE QRD nopmi overlay";
+ compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+ qcom,msm-id = <518 0x10000>;
+ qcom,board-id = <0x1000B 0>;
+ qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nopmi.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nopmi.dts
new file mode 100755
index 0000000..f36f81e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nopmi.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-qrd-nopmi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. KHAJE QRD nopmi";
+ compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+ qcom,board-id = <0x1000B 0>;
+ qcom,pmic-id = <0x2D 0x0 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nopmi.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nopmi.dtsi
new file mode 100755
index 0000000..0aff33e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nopmi.dtsi
@@ -0,0 +1,35 @@
+#include "khaje-qrd.dtsi"
+
+&sde_dsi {
+ /delete-property/ lab-supply;
+ /delete-property/ ibb-supply;
+};
+
+&dsi_td4330_truly_v2_video {
+ /delete-property/ qcom,esd-check-enabled;
+};
+
+&dsi_td4330_truly_v2_cmd {
+ /delete-property/ qcom,esd-check-enabled;
+};
+
+&qupv3_se2_i2c {
+ synaptics_tcm@20 {
+ status = "disabled";
+ };
+
+ novatek@62 {
+ status = "disabled";
+ };
+
+ focaltech@38 {
+ status = "disabled";
+ };
+};
+
+&usb0 {
+ /delete-property/ extcon;
+ dwc3@4e00000 {
+ dr_mode = "peripheral";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nowcd9375-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nowcd9375-overlay.dts
new file mode 100755
index 0000000..17dcc66
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nowcd9375-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-qrd.dtsi"
+#include "khaje-qrd-pm7250b.dtsi"
+#include "khaje-qrd-nowcd9375.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Khaje QRD NOWCD9375";
+ compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+ qcom,msm-id = <518 0x10000>;
+ qcom,board-id = <0x2010B 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nowcd9375.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nowcd9375.dts
new file mode 100755
index 0000000..891a070
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nowcd9375.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-qrd.dtsi"
+#include "khaje-qrd-pm7250b.dtsi"
+#include "khaje-qrd-nowcd9375.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. KHAJE QRD NOWCD9375";
+ compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+ qcom,board-id = <0x2010B 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nowcd9375.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nowcd9375.dtsi
new file mode 100755
index 0000000..05fd549
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-nowcd9375.dtsi
@@ -0,0 +1,17 @@
+#include "khaje-qrd-hvdcp3p5.dtsi"
+
+&wcd937x_codec {
+ status = "disabled";
+};
+
+&wcd937x_rx_slave {
+ status = "disabled";
+};
+
+&wcd937x_tx_slave {
+ status = "disabled";
+};
+
+&bengal_snd {
+ qcom,codec-max-aux-devs = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-overlay.dts
new file mode 100755
index 0000000..7c8960f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-overlay.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "khaje-qrd.dtsi"
+#include "khaje-qrd-pm7250b.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Khaje QRD";
+ compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+ qcom,msm-id = <518 0x10000>;
+ qcom,board-id = <0x1000B 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
+
+&bengal_snd {
+ qcom,wcd-datalane-mismatch = <1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-pm7250b.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-pm7250b.dtsi
new file mode 100755
index 0000000..db33ce0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd-pm7250b.dtsi
@@ -0,0 +1,192 @@
+#include "khaje-pm7250b.dtsi"
+#include "khaje-thermal-pm7250b-overlay.dtsi"
+
+&sde_dsi {
+ pinctrl-0 = <&sde_dsi_active &sde_te_active &disp_lcd_bias_en_default>;
+};
+
+&dsi_td4330_truly_v2_video {
+ qcom,platform-en-gpio = <&pm7250b_gpios 5 0>;
+ qcom,platform-bklight-en-gpio = <&pm7250b_gpios 1 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+ qcom,platform-en-gpio = <&pm7250b_gpios 5 0>;
+ qcom,platform-bklight-en-gpio = <&pm7250b_gpios 1 0>;
+};
+
+&soc {
+ qrd_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "qg-batterydata-atl466271_3300mAh.dtsi"
+ };
+};
+
+&tlmm {
+ smb_int_default: smb_int_default {
+ mux {
+ pins = "gpio105";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio105";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #include "smb1394.dtsi"
+};
+
+&smb1394 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_int_default>;
+ interrupt-parent = <&tlmm>;
+ interrupt-names = "smb1394";
+ interrupts = <105 IRQ_TYPE_LEVEL_LOW>;
+ status = "ok";
+};
+
+&smb1394_div2_cp_primary {
+ io-channels = <&pm7250b_vadc ADC_AMUX_THM2>;
+ io-channel-names = "die_temp";
+ qcom,parallel-input-mode = <1>;
+ qcom,parallel-output-mode = <2>;
+ status = "ok";
+};
+
+&pm7250b_vadc {
+ smb1390_therm@e {
+ qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_SMB1398_TEMP>;
+ };
+};
+
+&pm7250b_charger {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+ <&pm7250b_vadc ADC_USB_IN_I>,
+ <&pm7250b_vadc ADC_CHG_TEMP>,
+ <&pm7250b_vadc ADC_DIE_TEMP>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+ <&pm7250b_vadc ADC_SBUx>,
+ <&pm7250b_vadc ADC_VPH_PWR>,
+ <&pm7250b_vadc ADC_AMUX_THM1_PU2>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp",
+ "die_temp",
+ "conn_temp",
+ "sbux_res",
+ "vph_voltage",
+ "skin_temp";
+ qcom,battery-data = <&qrd_batterydata>;
+ qcom,sec-charger-config = <1>;
+ qcom,auto-recharge-soc = <98>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,fcc-stepping-enable;
+ qcom,fcc-step-delay-ms = <100>;
+ qcom,fcc-step-size-ua = <100000>;
+ qcom,smb-internal-pull-kohm = <0>;
+ qcom,thermal-mitigation = <8000000 7500000 7000000 6500000 6000000 5500000
+ 5000000 4500000 4000000 3500000 3000000 2500000 2000000 1500000
+ 1000000 500000>;
+};
+
+&pm7250b_qg {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU2>,
+ <&pm7250b_vadc ADC_BAT_ID_PU2>;
+ io-channel-names = "batt-therm",
+ "batt-id";
+ qcom,qg-iterm-ma = <150>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+ qcom,tcss-enable;
+ qcom,fvss-enable;
+ qcom,fvss-vbatt-mv = <3500>;
+ qcom,bass-enable;
+ qcom,vbatt-cutoff-mv = <3400>;
+ qcom,vbatt-low-mv = <3500>;
+ qcom,vbatt-low-cold-mv = <3800>;
+ qcom,vbatt-empty-mv = <3200>;
+ qcom,vbatt-empty-cold-mv = <3100>;
+ qcom,use-cp-iin-sns;
+};
+
+&cam_res_mgr_label {
+ gpios = <&pm7250b_gpios 4 0>;
+};
+
+&led_flash_rear {
+ gpios = <&pm7250b_gpios 4 0>;
+};
+
+&led_flash_rear_aux {
+ gpios = <&pm7250b_gpios 4 0>;
+};
+
+&led_flash_rear_aux2 {
+ gpios = <&pm7250b_gpios 4 0>;
+};
+
+&pm7250b_charger {
+ dpdm-supply = <&usb2_phy0>;
+
+ smb5_vbus: qcom,smb5-vbus {
+ regulator-name = "smb5-vbus";
+ };
+
+ smb5_vconn: qcom,smb5-vconn {
+ regulator-name = "smb5-vconn";
+ };
+};
+
+&pm7250b_pdphy {
+ vdd-pdphy-supply = <&L15A>;
+ vbus-supply = <&smb5_vbus>;
+ vconn-supply = <&smb5_vconn>;
+};
+
+&usb0 {
+ extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>;
+};
+
+&thermal_zones {
+ quiet-thermal-step {
+ cooling-maps {
+ quiet_batt_cdev1 {
+ trip = <&quiet_batt_trip0>;
+ cooling-device = <&pm7250b_charger 8 8>;
+ };
+
+ quiet_batt_cdev2 {
+ trip = <&quiet_batt_trip1>;
+ cooling-device = <&pm7250b_charger 12 12>;
+ };
+
+ quiet_batt_cdev3 {
+ trip = <&quiet_batt_trip2>;
+ cooling-device = <&pm7250b_charger 14 14>;
+ };
+
+ quiet_batt_cdev4 {
+ trip = <&quiet_batt_trip3>;
+ cooling-device = <&pm7250b_charger 16 16>;
+ };
+
+ quiet_batt_cdev5 {
+ trip = <&quiet_batt_trip4>;
+ cooling-device = <&pm7250b_charger 18 18>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd.dts
new file mode 100755
index 0000000..df4c7c1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+#include "khaje-qrd.dtsi"
+#include "khaje-qrd-pm7250b.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. KHAJE QRD";
+ compatible = "qcom,khaje-qrd", "qcom,khaje", "qcom,qrd";
+ qcom,board-id = <0x1000B 0>;
+ qcom,pmic-id = <0x2D 0x2E 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd.dtsi
new file mode 100755
index 0000000..8ac9939
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-qrd.dtsi
@@ -0,0 +1,547 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/input/input.h>
+#include "bengal-thermal-overlay.dtsi"
+#include "camera/khaje-camera-sensor-qrd.dtsi"
+#include "bengal-audio-overlay.dtsi"
+#include "khaje-sde-display.dtsi"
+
+&pm6125_gpios {
+ key_vol_up {
+ key_vol_up_default: key_vol_up_default {
+ pins = "gpio5";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+ };
+
+ eldo9_pin {
+ usb_eldo9:gpio@c000 {
+ pins = "gpio1";
+ function = "normal";
+ qcom,drive-strength = <2>;
+ power-source = <0>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm6125_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ linux,can-disable;
+ debounce-interval = <15>;
+ gpio-key,wakeup;
+ };
+ };
+
+ vdda_usb_ss_dp_core: vdda_usb_ss_dp_core {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_supply";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ enable-active-high;
+ gpio = <&pm6125_gpios 1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_eldo9>;
+ };
+};
+
+&usb_qmp_dp_phy {
+ vdd-supply = <&vdda_usb_ss_dp_core>;
+};
+
+&qupv3_se1_i2c {
+ awinic@64 {
+ compatible = "awinic,aw2016_led";
+ reg = <0x64>;
+
+ awinic,red {
+ awinic,name = "red";
+ awinic,id = <0>;
+ awinic,imax = <2>;
+ awinic,led-current = <3>;
+ awinic,max-brightness = <255>;
+ awinic,rise-time-ms = <6>;
+ awinic,hold-time-ms = <0>;
+ awinic,fall-time-ms = <6>;
+ awinic,off-time-ms = <4>;
+ };
+
+ awinic,green {
+ awinic,name = "green";
+ awinic,id = <1>;
+ awinic,imax = <2>;
+ awinic,led-current = <3>;
+ awinic,max-brightness = <255>;
+ awinic,rise-time-ms = <6>;
+ awinic,hold-time-ms = <0>;
+ awinic,fall-time-ms = <6>;
+ awinic,off-time-ms = <4>;
+ };
+
+ awinic,blue {
+ awinic,name = "blue";
+ awinic,id = <2>;
+ awinic,imax = <2>;
+ awinic,led-current = <3>;
+ awinic,max-brightness = <255>;
+ awinic,rise-time-ms = <6>;
+ awinic,hold-time-ms = <0>;
+ awinic,fall-time-ms = <6>;
+ awinic,off-time-ms = <4>;
+ };
+
+ };
+};
+
+&bengal_snd {
+ qcom,model = "bengal-qrd-snd-card";
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
+ qcom,wcn-btfm = <1>;
+ qcom,ext-disp-audio-rx = <0>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic4",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "SpkrMono WSA_IN", "AUX",
+ "TX SWR_MIC0", "ADC1_OUTPUT",
+ "TX SWR_MIC4", "ADC2_OUTPUT",
+ "TX SWR_MIC5", "ADC3_OUTPUT",
+ "TX SWR_MIC0", "VA_TX_SWR_CLK",
+ "TX SWR_MIC1", "VA_TX_SWR_CLK",
+ "TX SWR_MIC2", "VA_TX_SWR_CLK",
+ "TX SWR_MIC3", "VA_TX_SWR_CLK",
+ "TX SWR_MIC4", "VA_TX_SWR_CLK",
+ "TX SWR_MIC5", "VA_TX_SWR_CLK",
+ "TX SWR_MIC6", "VA_TX_SWR_CLK",
+ "TX SWR_MIC7", "VA_TX_SWR_CLK",
+ "TX SWR_MIC8", "VA_TX_SWR_CLK",
+ "TX SWR_MIC9", "VA_TX_SWR_CLK",
+ "TX SWR_MIC10", "VA_TX_SWR_CLK",
+ "TX SWR_MIC11", "VA_TX_SWR_CLK",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "TX_AIF1 CAP", "VA_TX_SWR_CLK",
+ "TX_AIF2 CAP", "VA_TX_SWR_CLK",
+ "TX_AIF3 CAP", "VA_TX_SWR_CLK",
+ "VA SWR_MIC0", "ADC1_OUTPUT",
+ "VA SWR_MIC4", "ADC2_OUTPUT",
+ "VA SWR_MIC5", "ADC3_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ asoc-codec = <&stub_codec>, <&bolero>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec";
+ qcom,wsa-max-devs = <1>;
+ qcom,wsa-devs = <&wsa881x_i2c_e>;
+ qcom,wsa-aux-dev-prefix = "SpkrMono";
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&wcd937x_codec>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&bolero>,
+ <&lpi_tlmm>;
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 70 0x00>;
+ qcom,nq-ven = <&tlmm 69 0x00>;
+ qcom,nq-firm = <&tlmm 31 0x00>;
+ qcom,nq-clkreq = <&tlmm 71 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <70 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&sdhc_1 {
+ vdd-supply = <&L24A>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L11A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&L22A>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L5A>;
+ qcom,vdd-io-voltage-level = <1800000 2960000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ vdd-io-bias-supply = <&L7A>;
+ qcom,vdd-io-bias-voltage-level = <1256000 1256000>;
+ qcom,vdd-io-bias-current-level = <0 6000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v4";
+
+ vdda-phy-supply = <&L4A>; /* 0.9v */
+ vdda-pll-supply = <&L18A>; /* 1.8v */
+ vdda-phy-max-microamp = <85700>;
+ vdda-pll-max-microamp = <18300>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&L24A>;
+ vcc-voltage-level = <2950000 2960000>;
+ vccq2-supply = <&L11A>;
+ vccq2-voltage-level = <1800000 1800000>;
+ vcc-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+ vccq2-pwr-collapse-sup;
+
+ qcom,vddp-ref-clk-supply = <&L18A>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vddp-ref-clk-min-uV = <1232000>;
+ qcom,vddp-ref-clk-max-uV = <1232000>;
+
+ status = "ok";
+};
+
+&pm6125_pwm {
+ status = "ok";
+};
+
+&dsi_td4330_truly_v2_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm6125_pwm 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm6125_pwm 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 81 0>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_td4330_truly_v2_video>;
+};
+
+&qupv3_se2_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="synaptics,tcm-i2c";
+
+ synaptics_tcm@20 {
+ compatible = "synaptics,tcm-i2c";
+ reg = <0x20>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+ synaptics,irq-gpio = <&tlmm 80 0x2008>;
+ synaptics,irq-on-state = <0>;
+ synaptics,reset-gpio = <&tlmm 86 0x00>;
+ synaptics,reset-on-state = <0>;
+ synaptics,reset-active-ms = <20>;
+ synaptics,reset-delay-ms = <200>;
+ synaptics,power-delay-ms = <200>;
+ synaptics,ubl-i2c-addr = <0x20>;
+ synaptics,extend_report;
+ synaptics,firmware-name = "synaptics_firmware_k.img";
+
+ panel = <&dsi_td4330_truly_v2_video &dsi_td4330_truly_v2_cmd>;
+ };
+};
+
+&thermal_zones {
+ quiet-thermal-step {
+ polling-delay-passive = <2000>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm6125_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+
+ trips {
+ quiet_batt_trip0: batt-trip0 {
+ temperature = <41000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ quiet_modem_trip0: modem-trip0 {
+ temperature = <42000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ quiet_batt_trip1: batt-trip1 {
+ temperature = <43000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ quiet_batt_trip2: batt-trip2 {
+ temperature = <45000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ quiet_gold_trip: gold-trip {
+ temperature = <47000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ quiet_batt_trip3: batt-trip3 {
+ temperature = <47000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ quiet_batt_trip4: batt-trip4 {
+ temperature = <48000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ quiet_gpu_trip: gpu-trip {
+ temperature = <48000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ quiet_silver_trip: silver-trip {
+ temperature = <50000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ quiet_hvx_trip: hvx-trip {
+ temperature = <52000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ quiet_modem_trip1: modem-trip1 {
+ temperature = <60000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ gold_cdev {
+ trip = <&quiet_gold_trip>;
+ /* limit to 1766400khz */
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-4)>;
+ };
+
+ silver_cdev {
+ trip = <&quiet_silver_trip>;
+ /* limit to 1516800khz */
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-4)>;
+ };
+
+ gpu_cdev {
+ trip = <&quiet_gpu_trip>;
+ /* limit 785000000hz */
+ cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+
+ hvx_cdev {
+ trip = <&quiet_hvx_trip>;
+ cooling-device = <&cdsp_sw 4 4>;
+ };
+
+ mdm_cdev0 {
+ trip = <&quiet_modem_trip0>;
+ cooling-device = <&modem_proc 1 1>;
+ };
+
+ mdm_cdev1 {
+ trip = <&quiet_modem_trip1>;
+ cooling-device = <&modem_proc 3 3>;
+ };
+ };
+ };
+
+ pa-therm0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm6125_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+
+ trips {
+ pa_therm0_trip0: pa-therm0-trip0 {
+ temperature = <52000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ pa_therm0_trip1: pa-therm0-trip1 {
+ temperature = <54000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ pa_therm0_trip2: pa-therm0-trip2 {
+ temperature = <60000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ modem_cdev0 {
+ trip = <&pa_therm0_trip0>;
+ cooling-device = <&modem_pa 1 1>;
+ };
+
+ modem_cdev1 {
+ trip = <&pa_therm0_trip1>;
+ cooling-device = <&modem_pa 2 2>;
+ };
+
+ modem_cdev2 {
+ trip = <&pa_therm0_trip2>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+ };
+ };
+};
+
+&tlmm {
+ fpc_reset_int: fpc_reset_int {
+ fpc_reset_low: reset_low {
+ mux {
+ pins = "gpio104";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio104";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ fpc_reset_high: reset_high {
+ mux {
+ pins = "gpio104";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio104";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ fpc_int_low: int_low {
+ mux {
+ pins = "gpio97";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio97";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+ };
+ };
+};
+
+&soc {
+ fingerprint: fpc1020 {
+ compatible = "fpc,fpc1020";
+ interrupt-parent = <&tlmm>;
+ interrupts = <97 0>;
+ fpc,gpio_rst = <&tlmm 104 0>;
+ fpc,gpio_irq = <&tlmm 97 0>;
+ fpc,enable-on-boot;
+ pinctrl-names = "fpc1020_reset_reset",
+ "fpc1020_reset_active",
+ "fpc1020_irq_active";
+ pinctrl-0 = <&fpc_reset_low>;
+ pinctrl-1 = <&fpc_reset_high>;
+ pinctrl-2 = <&fpc_int_low>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-regulator.dtsi
new file mode 100755
index 0000000..51508ac
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-regulator.dtsi
@@ -0,0 +1,152 @@
+#include "bengal-regulator.dtsi"
+
+&S6A {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1419000>;
+ qcom,init-voltage = <1352000>;
+};
+
+&S7A {
+ regulator-min-microvolt = <1569000>;
+ regulator-max-microvolt = <2040000>;
+ qcom,init-voltage = <2040000>;
+};
+
+&S8A {
+ regulator-min-microvolt = <1060000>;
+ regulator-max-microvolt = <1170000>;
+ qcom,init-voltage = <1128000>;
+};
+
+&L1A {
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1150000>;
+ qcom,init-voltage = <1000000>;
+};
+
+&L4A {
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1050000>;
+ qcom,init-voltage = <880000>;
+};
+
+&L5A {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3050000>;
+ qcom,init-voltage = <2960000>;
+};
+
+&L6A {
+ regulator-min-microvolt = <570000>;
+ regulator-max-microvolt = <650000>;
+ qcom,init-voltage = <624000>;
+};
+
+&L7A {
+ regulator-max-microvolt = <1300000>;
+ qcom,init-voltage = <1256000>;
+};
+
+&L8A {
+ qcom,init-voltage = <704000>;
+};
+
+&L9A {
+ regulator-min-microvolt = <1504000>;
+ qcom,init-voltage = <1800000>;
+};
+
+&L10A {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ qcom,init-voltage = <1800000>;
+};
+
+&L11A {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1950000>;
+ qcom,init-voltage = <1800000>;
+};
+
+&L12A {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ qcom,init-voltage = <1800000>;
+};
+
+&L13A {
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ qcom,init-voltage = <1800000>;
+};
+
+&L14A {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ qcom,init-voltage = <1700000>;
+};
+
+&L15A {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ qcom,init-voltage = <3080000>;
+};
+
+&L16A {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ qcom,init-voltage = <1700000>;
+};
+
+&L17A {
+ regulator-min-microvolt = <1220000>;
+ regulator-max-microvolt = <1304000>;
+ qcom,init-voltage = <1220000>;
+};
+
+&L18A {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,init-voltage = <1232000>;
+};
+
+&L19A {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <1620000>;
+};
+
+&L20A {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <1620000>;
+};
+
+&L21A {
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3544000>;
+ qcom,init-voltage = <1600000>;
+};
+
+&L22A {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <2960000>;
+};
+
+&L24A {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ qcom,init-voltage = <2960000>;
+};
+
+&soc {
+ refgen: refgen-regulator@1600000 {
+ compatible = "qcom,refgen-kona-regulator";
+ reg = <0x1600000 0x84>;
+ regulator-name = "refgen";
+ regulator-enable-ramp-delay = <5>;
+ proxy-supply = <&refgen>;
+ qcom,proxy-consumer-enable;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-sde-display.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-sde-display.dtsi
new file mode 100755
index 0000000..e3c3b4b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-sde-display.dtsi
@@ -0,0 +1,185 @@
+#include "dsi-panel-td4330-truly-v2-singlemipi-fhd-cmd.dtsi"
+#include "dsi-panel-td4330-truly-v2-singlemipi-fhd-vid.dtsi"
+#include "dsi-panel-nt36672e-fhd-plus-90hz-video.dtsi"
+#include "dsi-panel-nt36672e-fhd-plus-120hz-video.dtsi"
+#include "dsi-panel-sim-video.dtsi"
+#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
+
+&soc {
+ dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+ };
+
+ sde_dsi: qcom,dsi-display-primary {
+ compatible = "qcom,dsi-display";
+ label = "primary";
+ qcom,dsi-ctrl = <&mdss_dsi0>;
+ qcom,dsi-phy = <&mdss_dsi_phy0>;
+
+ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll PCLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll PCLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>;
+ clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+ pinctrl-names = "panel_active", "panel_suspend";
+ pinctrl-0 = <&sde_dsi_active &sde_te_active>;
+ pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
+
+ qcom,platform-te-gpio = <&tlmm 81 0>;
+ qcom,panel-te-source = <0>;
+
+ vddio-supply = <&L9A>;
+ qcom,mdp = <&mdss_mdp>;
+
+ qcom,dsi-default-panel =
+ <&dsi_td4330_truly_v2_video>;
+ };
+
+ sde_wb: qcom,wb-display@0 {
+ status = "disabled";
+ compatible = "qcom,wb-display";
+ cell-index = <0>;
+ label = "wb_display";
+ };
+
+ msm_notifier: qcom,msm_notifier@0 {
+ compatible = "qcom,msm-notifier";
+ panel = <&dsi_nt36672e_fhd_plus_90hz_video
+ &dsi_nt36672e_fhd_plus_120hz_video>;
+ };
+};
+
+&mdss_mdp {
+ connectors = <&sde_dsi>;
+};
+
+&dsi_td4330_truly_v2_video {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x1c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x1c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-supported-dfps-list = <60 55 48>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update =
+ "dfps_immediate_porch_mode_vfp";
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+ qcom,dsi-dyn-clk-enable;
+ qcom,dsi-dyn-clk-list =
+ <976190400 988392784 984325320 980257864>;
+ qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 21 08 08 25 22 09
+ 08 09 02 04 00 1D 18];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 23 09 09 26 24 09
+ 09 09 02 04 00 1E 19];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_td4330_truly_v2_cmd {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x1c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x1c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,ulps-enabled;
+ qcom,dsi-dyn-clk-enable;
+ qcom,dsi-dyn-clk-list =
+ <944315056 928576464 932511112 936445760 940380400>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 23 09 09 26 24 09
+ 09 09 02 04 00 1E 19];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <40 40 40 40 40 40>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 21 08 08 25 22 09
+ 08 09 02 04 00 1D 18];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_nt36672e_fhd_plus_90hz_video {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
+ 06 07 02 04 00 16 16];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_nt36672e_fhd_plus_120hz_video {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 08 24 22 08
+ 08 08 02 04 00 1b 18];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_vid {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1B 1B 01
+ 01 02 02 04 00 0A 11];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-sde-pll.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-sde-pll.dtsi
new file mode 100755
index 0000000..5ea9587
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-sde-pll.dtsi
@@ -0,0 +1,20 @@
+&soc {
+ mdss_dsi0_pll: qcom,mdss_dsi0_pll {
+ compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
+ label = "MDSS DSI 0 PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+ reg = <0x5e94900 0x264>,
+ <0x5e94400 0x800>,
+ <0x5f01004 0x8>,
+ <0x5e94200 0x100>;
+ reg-names = "pll_base", "phy_base",
+ "gdsc_base", "dynamic_pll_base";
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ memory-region = <&dfps_data_memory>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-sde.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-sde.dtsi
new file mode 100755
index 0000000..a50c98d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-sde.dtsi
@@ -0,0 +1,418 @@
+#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
+
+&soc {
+ mdss_mdp: qcom,mdss_mdp {
+ compatible = "qcom,sde-kms";
+ reg = <0x5e00000 0x8f030>,
+ <0x5eb0000 0x2008>,
+ <0x5e8f000 0x030>;
+
+ reg-names = "mdp_phys",
+ "vbif_phys",
+ "sid_phys";
+
+ clocks =
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_THROTTLE_CORE_CLK>,
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>;
+ clock-names = "gcc_iface", "gcc_bus", "throttle_clk",
+ "div_clk",
+ "iface_clk", "core_clk", "vsync_clk",
+ "lut_clk", "rot_clk";
+ clock-rate = <0 0 0 0 0 383000000 19200000 383000000 200000000>;
+ clock-max-rate = <0 0 0 0 0 560000000 19200000 560000000
+ 560000000>;
+
+ sde-vdd-supply = <&mdss_core_gdsc>;
+
+ /* interrupt config */
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #power-domain-cells = <0>;
+ #list-cells = <1>;
+
+ /* hw blocks */
+ qcom,sde-off = <0x1000>;
+ qcom,sde-len = <0x494>;
+
+ qcom,sde-ctl-off = <0x2000>;
+ qcom,sde-ctl-size = <0x1dc>;
+ qcom,sde-ctl-display-pref = "primary";
+
+ qcom,sde-mixer-off = <0x45000>;
+ qcom,sde-mixer-size = <0x320>;
+ qcom,sde-mixer-display-pref = "primary";
+
+ qcom,sde-dspp-top-off = <0x1300>;
+ qcom,sde-dspp-top-size = <0x80>;
+ qcom,sde-dspp-off = <0x55000>;
+ qcom,sde-dspp-size = <0x1800>;
+
+ qcom,sde-dspp-rc-version = <0x00010000>;
+ qcom,sde-dspp-rc-off = <0x15800>;
+ qcom,sde-dspp-rc-size = <0x100>;
+ qcom,sde-dspp-rc-mem-size = <2720>;
+
+ qcom,sde-intf-off = <0x0 0x6b800>;
+ qcom,sde-intf-size = <0x2c0>;
+ qcom,sde-intf-type = "none", "dsi";
+
+ qcom,sde-pp-off = <0x71000>;
+ qcom,sde-pp-size = <0xd4>;
+
+ qcom,sde-dsc-off = <0x81000>;
+ qcom,sde-dsc-size = <0x140>;
+
+ qcom,sde-dither-off = <0x30e0>;
+ qcom,sde-dither-version = <0x00010000>;
+ qcom,sde-dither-size = <0x20>;
+
+ qcom,sde-sspp-type = "vig", "dma";
+
+ qcom,sde-sspp-off = <0x5000 0x25000>;
+ qcom,sde-sspp-src-size = <0x1f8>;
+
+ qcom,sde-sspp-xin-id = <0 1>;
+ qcom,sde-sspp-excl-rect = <1 1>;
+ qcom,sde-sspp-smart-dma-priority = <2 1>;
+ qcom,sde-smart-dma-rev = "smart_dma_v2p5";
+
+ qcom,sde-mixer-pair-mask = <0>;
+
+ qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
+ 0xb0 0xc8 0xe0 0xf8 0x110>;
+
+ qcom,sde-mixer-stage-base-layer;
+
+ qcom,sde-max-per-pipe-bw-kbps = <3200000 3200000>;
+
+ qcom,sde-max-per-pipe-bw-high-kbps = <3200000 3200000>;
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+ qcom,sde-sspp-clk-ctrl =
+ <0x2ac 0>, <0x2ac 8>;
+ qcom,sde-sspp-csc-off = <0x1a00>;
+ qcom,sde-csc-type = "csc-10bit";
+ qcom,sde-qseed-type = "qseedv3lite";
+ qcom,sde-sspp-qseed-off = <0xa00>;
+ qcom,sde-mixer-linewidth = <2048>;
+ qcom,sde-sspp-linewidth = <2160>;
+ qcom,sde-mixer-blendstages = <0x4>;
+ qcom,sde-highest-bank-bit = <0x1>;
+ qcom,sde-ubwc-version = <0x100>;
+ qcom,sde-ubwc-swizzle = <0x7>;
+ qcom,sde-ubwc-static = <0x11F>;
+ qcom,sde-panic-per-pipe;
+ qcom,sde-has-cdp;
+
+ qcom,sde-has-dim-layer;
+ qcom,sde-has-idle-pc;
+
+ qcom,sde-max-bw-low-kbps = <3200000>;
+ qcom,sde-max-bw-high-kbps = <4300000>;
+ qcom,sde-min-core-ib-kbps = <2400000>;
+ qcom,sde-min-llcc-ib-kbps = <0>;
+ qcom,sde-min-dram-ib-kbps = <1600000>;
+ qcom,sde-dram-channels = <1>;
+ qcom,sde-num-nrt-paths = <0>;
+
+ qcom,sde-vbif-off = <0>;
+ qcom,sde-vbif-size = <0x2008>;
+ qcom,sde-vbif-id = <0>;
+ qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
+
+ qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
+ qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
+
+ /*Pending macrotile & macrotile-qseed has the same configs */
+
+ qcom,sde-danger-lut = <0x000000ff 0x0000ffff
+ 0x00000000 0x00000000 0x0000ffff>;
+
+ qcom,sde-safe-lut-linear = <0 0xfff0>;
+ qcom,sde-safe-lut-macrotile = <0 0xff00>;
+ /* same as safe-lut-macrotile */
+ qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>;
+ qcom,sde-safe-lut-nrt = <0 0xffff>;
+
+ qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;
+ qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;
+ qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;
+ qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;
+
+ qcom,sde-cdp-setting = <1 1>, <1 0>;
+
+ qcom,sde-qos-cpu-mask = <0x3>;
+ qcom,sde-qos-cpu-dma-latency = <300>;
+
+ qcom,sde-secure-sid-mask = <0x0000421>;
+ qcom,sde-num-mnoc-ports = <1>;
+ qcom,sde-axi-bus-width = <16>;
+
+ qcom,sde-sspp-vig-blocks {
+ qcom,sde-vig-csc-off = <0x1a00>;
+ qcom,sde-vig-qseed-off = <0xa00>;
+ qcom,sde-vig-qseed-size = <0xa0>;
+ qcom,sde-vig-inverse-pma;
+ };
+
+ qcom,sde-dspp-blocks {
+ qcom,sde-dspp-igc = <0x0 0x00030001>;
+ qcom,sde-dspp-hsic = <0x800 0x00010007>;
+ qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+ qcom,sde-dspp-hist = <0x800 0x00010007>;
+ qcom,sde-dspp-sixzone= <0x900 0x00010007>;
+ qcom,sde-dspp-vlut = <0xa00 0x00010008>;
+ qcom,sde-dspp-pcc = <0x1700 0x00040000>;
+ qcom,sde-dspp-gc = <0x17c0 0x00010008>;
+ qcom,sde-dspp-dither = <0x82c 0x00010007>;
+ };
+
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "sde-vdd";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
+ compatible = "qcom,smmu_sde_unsec";
+ iommus = <&apps_smmu 0x420 0x2>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-earlymap; /* for cont-splash */
+ };
+
+ smmu_sde_sec: qcom,smmu_sde_sec_cb {
+ compatible = "qcom,smmu_sde_sec";
+ iommus = <&apps_smmu 0x421 0x0>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xa>;
+ };
+
+ /* data and reg bus scale settings */
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "mdss_sde";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>,
+ <22 512 0 4800000>,
+ <22 512 0 4800000>;
+ };
+
+ qcom,sde-reg-bus {
+ qcom,msm-bus,name = "mdss_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 150000>,
+ <1 590 0 300000>;
+ };
+
+ qcom,sde-limits {
+ qcom,sde-linewidth-limits {
+ qcom,sde-limit-name = "sspp_linewidth_usecases";
+ qcom,sde-limit-cases = "vig", "dma", "scale";
+ qcom,sde-limit-ids= <0x1 0x2 0x4>;
+ qcom,sde-limit-values = <0x1 4096>,
+ <0x5 2560>,
+ <0x2 2160>;
+ };
+
+ qcom,sde-bw-limits {
+ qcom,sde-limit-name = "sde_bwlimit_usecases";
+ qcom,sde-limit-cases = "per_vig_pipe",
+ "per_dma_pipe",
+ "total_max_bw",
+ "camera_concurrency";
+ qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>;
+ qcom,sde-limit-values = <0x1 3200000>,
+ <0x9 3200000>,
+ <0x2 3200000>,
+ <0xa 3200000>,
+ <0x4 4300000>,
+ <0xc 3200000>;
+ };
+ };
+ };
+
+ mdss_rotator: qcom,mdss_rotator {
+ compatible = "qcom,sde_rotator";
+ reg = <0x5e00000 0xac000>,
+ <0x5eb0000 0x2008>;
+ reg-names = "mdp_phys",
+ "rot_vbif_phys";
+
+ #list-cells = <1>;
+
+ qcom,mdss-rot-mode = <1>;
+
+ /* Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_rotator";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>,
+ <22 512 0 6400000>,
+ <22 512 0 6400000>;
+
+ rot-vdd-supply = <&mdss_core_gdsc>;
+ qcom,supply-names = "rot-vdd";
+
+ clocks =
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>;
+ clock-names = "gcc_iface",
+ "iface_clk", "rot_clk";
+
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <2 0>;
+
+ power-domains = <&mdss_mdp>;
+ /*Offline rotator RT setting */
+ qcom,mdss-rot-parent = <&mdss_mdp 0>;
+ qcom,mdss-rot-xin-id = <10 11>;
+
+ /* Offline rotator QoS setting */
+ qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
+ qcom,mdss-rot-cdp-setting = <1 1>;
+ qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
+ qcom,mdss-rot-danger-lut = <0x0 0x0>;
+ qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
+
+ qcom,mdss-default-ot-rd-limit = <32>;
+ qcom,mdss-default-ot-wr-limit = <32>;
+
+ qcom,mdss-sbuf-headroom = <20>;
+
+ /* reg bus scale settings */
+ rot_reg: qcom,rot-reg-bus {
+ qcom,msm-bus,name = "mdss_rot_reg";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>;
+ };
+
+ smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
+ compatible = "qcom,smmu_sde_rot_unsec";
+ iommus = <&apps_smmu 0x43C 0x0>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ };
+
+ smmu_rot_sec: qcom,smmu_rot_sec_cb {
+ compatible = "qcom,smmu_sde_rot_sec";
+ iommus = <&apps_smmu 0x43D 0x0>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xa>;
+ };
+ };
+
+ mdss_dsi0: qcom,mdss_dsi0_ctrl {
+ compatible = "qcom,dsi-ctrl-hw-v2.4";
+ label = "dsi-ctrl-0";
+ cell-index = <0>;
+ frame-threshold-time-us = <1000>;
+ reg = <0x5e94000 0x400>,
+ <0x5f08000 0x4>;
+ reg-names = "dsi_ctrl", "disp_cc_base";
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <4 0>;
+ vdda-1p2-supply = <&L18A>;
+ refgen-supply = <&refgen>;
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>;
+ clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+ "pixel_clk", "pixel_clk_rcg",
+ "esc_clk";
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1232000>;
+ qcom,supply-max-voltage = <1232000>;
+ qcom,supply-enable-load = <21800>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi_phy0: qcom,mdss_dsi_phy0 {
+ compatible = "qcom,dsi-phy-v4.1";
+ label = "dsi-phy-0";
+ cell-index = <0>;
+ reg = <0x5e94400 0x800>,
+ <0x5e94200 0x100>;
+ reg-names = "dsi_phy", "dyn_refresh_base";
+ vdda-0p9-supply = <&L4A>;
+ qcom,platform-strength-ctrl = [55 03
+ 55 03
+ 55 03
+ 55 03
+ 55 00];
+ qcom,platform-lane-config = [00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 8a 8a];
+ qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <880000>;
+ qcom,supply-max-voltage = <880000>;
+ qcom,supply-enable-load = <36000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-thermal-pm7250b-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-thermal-pm7250b-overlay.dtsi
new file mode 100755
index 0000000..da51394
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-thermal-pm7250b-overlay.dtsi
@@ -0,0 +1,116 @@
+#include <dt-bindings/thermal/thermal.h>
+
+&thermal_zones {
+ pm7250b-tz {
+ cooling-maps {
+ trip0_bat {
+ trip = <&pm7250b_trip0>;
+ cooling-device =
+ <&pm7250b_charger (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ trip1_bat {
+ trip = <&pm7250b_trip1>;
+ cooling-device =
+ <&pm7250b_charger THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+
+ soc {
+ cooling-maps {
+ soc_cpu4 {
+ trip = <&soc_trip>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+
+ soc_cpu5 {
+ trip = <&soc_trip>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+
+ soc_cpu6 {
+ trip = <&soc_trip>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ soc_cpu7 {
+ trip = <&soc_trip>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pm7250b-bcl-lvl0 {
+ cooling-maps {
+ lbat0_cpufreq4 {
+ trip = <&b_bcl_lvl0>;
+ cooling-device =
+ <&CPU4 (THERMAL_MAX_LIMIT-4)
+ (THERMAL_MAX_LIMIT-4)>;
+ };
+
+ lbat0_cpu6 {
+ trip = <&b_bcl_lvl0>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ lbat0_cpu7 {
+ trip = <&b_bcl_lvl0>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+
+ lbat0_gpu {
+ trip = <&b_bcl_lvl0>;
+ cooling-device = <&msm_gpu 2 2>;
+ };
+
+ lbat0_cdsp {
+ trip = <&b_bcl_lvl0>;
+ cooling-device = <&cdsp_sw 2 2>;
+ };
+ };
+ };
+
+ pm7250b-bcl-lvl1 {
+ cooling-maps {
+ lbat1_cpu4 {
+ trip = <&b_bcl_lvl1>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+
+ lbat1_cpu5 {
+ trip = <&b_bcl_lvl1>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+
+ lbat1_gpu {
+ trip = <&b_bcl_lvl1>;
+ cooling-device = <&msm_gpu 4 4>;
+ };
+
+ lbat1_cdsp {
+ trip = <&b_bcl_lvl1>;
+ cooling-device = <&cdsp_sw 4 4>;
+ };
+ };
+ };
+
+ pm7250b-bcl-lvl2 {
+ cooling-maps {
+ lbat2_gpu {
+ trip = <&b_bcl_lvl2>;
+ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ lbat2_cdsp {
+ trip = <&b_bcl_lvl2>;
+ cooling-device = <&cdsp_sw THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje-usb.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje-usb.dtsi
new file mode 100755
index 0000000..849cdf3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje-usb.dtsi
@@ -0,0 +1,355 @@
+#include <dt-bindings/clock/qcom,gcc-khaje.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/phy/qcom,khaje-qmp-usb3.h>
+&soc {
+ /* Primary USB port related controller */
+ usb0: ssusb@4e00000 {
+ compatible = "qcom,dwc-usb3-msm";
+ reg = <0x4e00000 0x100000>;
+ reg-names = "core_base";
+
+ iommus = <&apps_smmu 0x120 0x0>;
+ qcom,iommu-dma = "atomic";
+ qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "pwr_event_irq", "ss_phy_irq",
+ "dp_hs_phy_irq", "dm_hs_phy_irq";
+
+ clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+ clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+ "xo", "sleep_clk", "utmi_clk";
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+ reset-names = "core_reset";
+
+ USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
+ dpdm-supply = <&usb2_phy0>;
+
+ qcom,core-clk-rate = <133333333>;
+ qcom,core-clk-rate-hs = <66666667>;
+ qcom,num-gsi-evt-buffs = <0x3>;
+ qcom,gsi-reg-offset =
+ <0x0fc /* GSI_GENERAL_CFG */
+ 0x110 /* GSI_DBL_ADDR_L */
+ 0x120 /* GSI_DBL_ADDR_H */
+ 0x130 /* GSI_RING_BASE_ADDR_L */
+ 0x144 /* GSI_RING_BASE_ADDR_H */
+ 0x1a4>; /* GSI_IF_STS */
+ qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
+ qcom,gsi-disable-io-coherency;
+
+ qcom,msm-bus,name = "usb0";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ /* suspend vote */
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>,
+
+ /* nominal vote */
+ <MSM_BUS_MASTER_USB3
+ MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+ /* svs vote */
+ <MSM_BUS_MASTER_USB3
+ MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+ /* min vote */
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 1 1>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 1 1>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 1 1>;
+
+ dwc3@4e00000 {
+ compatible = "snps,dwc3";
+ reg = <0x4e00000 0xe000>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;
+ tx-fifo-resize;
+ linux,sysdev_is_parent;
+ snps,disable-clk-gating;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3-u1u2-disable;
+ snps,usb3_lpm_capable;
+ usb-core-id = <0>;
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+
+ qcom,usbbam@0x04f04000 {
+ compatible = "qcom,usb-bam-msm";
+ reg = <0x04f04000 0x17000>;
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+
+ qcom,usb-bam-fifo-baseaddr = <0xc121000>;
+ qcom,usb-bam-num-pipes = <4>;
+ qcom,disable-clk-gating;
+ qcom,usb-bam-override-threshold = <0x4001>;
+ qcom,usb-bam-max-mbps-highspeed = <400>;
+ qcom,usb-bam-max-mbps-superspeed = <3600>;
+ qcom,reset-bam-on-connect;
+
+ qcom,pipe0 {
+ label = "ssusb-qdss-in-0";
+ qcom,usb-bam-mem-type = <2>;
+ qcom,dir = <1>;
+ qcom,pipe-num = <0>;
+ qcom,peer-bam = <0>;
+ qcom,peer-bam-physical-address = <0x08064000>;
+ qcom,src-bam-pipe-index = <0>;
+ qcom,dst-bam-pipe-index = <0>;
+ qcom,data-fifo-offset = <0x0>;
+ qcom,data-fifo-size = <0x1800>;
+ qcom,descriptor-fifo-offset = <0x1800>;
+ qcom,descriptor-fifo-size = <0x800>;
+ };
+ };
+ };
+
+ /* Primary USB port related High Speed PHY */
+ usb2_phy0: hsphy@1613000 {
+ compatible = "qcom,usb-hsphy-snps-femto";
+ reg = <0x1613000 0x110>,
+ <0x1612000 0x4>;
+ reg-names = "hsusb_phy_base",
+ "eud_enable_reg";
+
+ vdd-supply = <&L4A>;
+ vdda18-supply = <&L12A>;
+ vdda33-supply = <&L15A>;
+ qcom,vdd-voltage-level = <0 880000 880000>;
+
+ clocks = <&rpmcc CXO_SMD_OTG_CLK>,
+ <&gcc GCC_AHB2PHY_USB_CLK>;
+ clock-names = "ref_clk_src", "cfg_ahb_clk";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ reset-names = "phy_reset";
+ qcom,param-override-seq =
+ <0xa6 0x6c>, /* override_x0 */
+ <0x85 0x70>, /* override_x1 */
+ <0x16 0x74>; /* override_x2 */
+ };
+
+ /* Primary USB port related QMP USB PHY */
+ usb_qmp_dp_phy: ssphy@1615000 {
+ compatible = "qcom,usb-ssphy-qmp-dp-combo";
+ reg = <0x01615000 0x3000>;
+ reg-names = "qmp_phy_base";
+
+ core-supply = <&L18A>;
+ qcom,vdd-voltage-level = <0 880000 880000>;
+ qcom,core-voltage-level = <0 1232000 1260000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
+ <&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
+ <&rpmcc CXO_SMD_OTG_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_AHB2PHY_USB_CLK>;
+
+ clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+ "pipe_clk_ext_src", "ref_clk_src",
+ "com_aux_clk","cfg_ahb_clk";
+
+ resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>;
+ reset-names = "global_phy_reset", "phy_reset";
+
+ qcom,qmp-phy-reg-offset =
+ <USB3_DP_PCS_PCS_STATUS1
+ USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
+ USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+ USB3_DP_PCS_POWER_DOWN_CONTROL
+ USB3_DP_PCS_SW_RESET
+ USB3_DP_PCS_START_CONTROL
+ 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
+ 0x2a18 /* USB3_DP_DP_PHY_PD_CTL */
+ USB3_DP_COM_POWER_DOWN_CTRL
+ USB3_DP_COM_SW_RESET
+ USB3_DP_COM_RESET_OVRD_CTRL
+ USB3_DP_COM_PHY_MODE_CTRL
+ USB3_DP_COM_TYPEC_CTRL
+ USB3_DP_COM_SWI_CTRL
+ USB3_DP_PCS_CLAMP_ENABLE>;
+
+ qcom,qmp-phy-init-seq =
+ /* <reg_offset, value, delay> */
+ <USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
+ USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
+ USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
+ USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
+ USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
+ USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
+ USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
+ USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
+ USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0
+ USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
+ USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0
+ USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
+ USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
+ USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
+ USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
+ USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
+ USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
+ USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
+ USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
+ USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
+ USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
+ USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
+ USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
+ USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0
+ USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
+ USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
+ USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
+ USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0
+ USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
+ USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x60 0
+ USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x60 0
+ USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x11 0
+ USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x02 0
+ USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5 0
+ USB3_DP_QSERDES_TXA_LANE_MODE_2 0x00 0
+ USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
+ USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x40 0
+ USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09 0
+ USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0
+ USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
+ USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
+ USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
+ USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
+ USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
+ USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0
+ USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
+ USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0
+ USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0
+ USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
+ USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0C 0
+ USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
+ USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
+ USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
+ USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
+ USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
+ USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
+ USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
+ USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xFF 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7F 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7F 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x97 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x7B 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB4 0
+ USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
+ USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
+ USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
+ USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
+ USB3_DP_QSERDES_RXA_GM_CAL 0x1F 0
+ USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
+ USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x60 0
+ USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x60 0
+ USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x11 0
+ USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x02 0
+ USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5 0
+ USB3_DP_QSERDES_TXB_LANE_MODE_2 0x00 0
+ USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
+ USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x54 0
+ USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09 0
+ USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0
+ USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
+ USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
+ USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
+ USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
+ USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
+ USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0
+ USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
+ USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0
+ USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0
+ USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
+ USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0C 0
+ USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
+ USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
+ USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
+ USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
+ USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
+ USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
+ USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
+ USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xA6 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x7B 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB4 0
+ USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
+ USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
+ USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
+ USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
+ USB3_DP_QSERDES_RXB_GM_CAL 0x1F 0
+ USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
+ USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
+ USB3_DP_PCS_RX_SIGDET_LVL 0xA9 0
+ USB3_DP_PCS_CDR_RESET_TIME 0x0A 0
+ USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
+ USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
+ USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
+ USB3_DP_PCS_EQ_CONFIG1 0x4B 0
+ USB3_DP_PCS_EQ_CONFIG5 0x10 0
+ USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
+ USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
+ 0xffffffff 0xffffffff 0x00>;
+ };
+
+ usb_nop_phy: usb_nop_phy {
+ compatible = "usb-nop-xceiv";
+ };
+
+ usb_audio_qmi_dev {
+ compatible = "qcom,usb-audio-qmi-dev";
+ iommus = <&apps_smmu 0x1cf 0x0>;
+ qcom,iommu-dma = "disabled";
+ qcom,usb-audio-stream-id = <0xf>;
+ qcom,usb-audio-intr-num = <2>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje.dts b/arch/arm64/boot/dts/vendor/qcom/khaje.dts
new file mode 100755
index 0000000..b522b78
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "khaje.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Khaje SoC";
+ compatible = "qcom,khaje";
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/khaje.dtsi b/arch/arm64/boot/dts/vendor/qcom/khaje.dtsi
new file mode 100755
index 0000000..0d5c32b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/khaje.dtsi
@@ -0,0 +1,4407 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,dispcc-khaje.h>
+#include <dt-bindings/clock/qcom,gcc-khaje.h>
+#include <dt-bindings/clock/qcom,gpucc-khaje.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/soc/qcom,dcc_v2.h>
+
+#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
+#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
+
+#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
+ opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
+ opp-supported-hw = <ddrtype>;}
+
+#define DDR_TYPE_LPDDR3 5
+#define DDR_TYPE_LPDDR4X 7
+
+/ {
+ model = "Qualcomm Technologies, Inc. Khaje SoC";
+ compatible = "qcom,khaje";
+ qcom,msm-id = <518 0x10000>;
+ interrupt-parent = <&wakegic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+ mem-offline {
+ compatible = "qcom,mem-offline";
+ offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
+ <0x1 0xc0000000 0x0 0x80000000>,
+ <0x2 0xc0000000 0x1 0x40000000>;
+ granule = <512>;
+ };
+
+ aliases {
+ sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
+ sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
+ swr0 = &swr0;
+ swr1 = &swr1;
+ ufshc1 = &ufshc_mem; /* Embedded UFS slot */
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ #cooling-cells = <2>;
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ };
+
+ L1_I_0: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_0: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x1>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+ L1_I_1: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_1: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x2>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+ L1_I_2: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_2: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x3>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+ L1_I_3: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_3: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ next-level-cache = <&L2_1>;
+ qcom,freq-domain = <&cpufreq_hw 1 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+ #cooling-cells = <2>;
+ L2_1: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ };
+
+ L1_I_100: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_100: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x101>;
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ qcom,freq-domain = <&cpufreq_hw 1 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+
+ L1_I_101: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_101: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x102>;
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ qcom,freq-domain = <&cpufreq_hw 1 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+
+ L1_I_102: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_102: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x103>;
+ capacity-dmips-mhz = <1638>;
+ dynamic-power-coefficient = <282>;
+ enable-method = "psci";
+ next-level-cache = <&L2_1>;
+ qcom,freq-domain = <&cpufreq_hw 1 7>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+
+ L1_I_103: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_103: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ firmware: firmware {
+ android {
+ compatible = "android,firmware";
+ vbmeta {
+ compatible="android,vbmeta";
+ parts = "vbmeta,boot,system,vendor,dtbo,recovery";
+ };
+
+ fstab {
+ compatible = "android,fstab";
+ vendor {
+ compatible = "android,vendor";
+ dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,discard";
+ fsmgr_flags = "wait,slotselect,avb";
+ status = "ok";
+ };
+ };
+ };
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: hyp_region@45700000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45700000 0x0 0x600000>;
+ };
+
+ xbl_aop_mem: xbl_aop_region@45e00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45e00000 0x0 0x140000>;
+ };
+
+ sec_apps_mem: sec_apps_region@45fff000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45fff000 0x0 0x1000>;
+ };
+
+ smem_mem: smem_region@46000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x46000000 0x0 0x200000>;
+ };
+
+ removed_mem: removed_region@60000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x60000000 0x0 0x3900000>;
+ };
+
+ pil_modem_mem: modem_region@4ab00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x4ab00000 0x0 0x6900000>;
+ };
+
+ pil_video_mem: pil_video_region@51400000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51400000 0x0 0x500000>;
+ };
+
+ wlan_msa_mem: wlan_msa_region@51900000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51900000 0x0 0x100000>;
+ };
+
+ pil_cdsp_mem: cdsp_regions@51a00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51a00000 0x0 0x1e00000>;
+ };
+
+ pil_adsp_mem: pil_adsp_region@53800000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x53800000 0x0 0x1e00000>;
+ };
+
+ pil_ipa_fw_mem: ipa_fw_region@55600000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x55600000 0x0 0x10000>;
+ };
+
+ pil_ipa_gsi_mem: ipa_gsi_region@55610000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x55610000 0x0 0x5000>;
+ };
+
+ pil_gpu_mem: gpu_region@55615000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x55615000 0x0 0x2000>;
+ };
+
+ user_contig_mem: user_contig_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ qseecom_mem: qseecom_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1400000>;
+ };
+
+ qseecom_ta_mem: qseecom_ta_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ cdsp_sec_mem: cdsp_sec_regions@46200000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x46200000 0x0 0x1e00000>;
+ };
+
+ secure_display_memory: secure_display_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x00000000 0 0xffffffff>;
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x5c00000>;
+ };
+
+ cont_splash_memory: cont_splash_region@5c000000 {
+ reg = <0x0 0x5c000000 0x0 0x00f00000>;
+ label = "cont_splash_region";
+ };
+
+ disp_rdump_memory: disp_rdump_region@5c000000 {
+ reg = <0x0 0x5c000000 0x0 0x00f00000>;
+ label = "disp_rdump_region";
+ };
+
+ dfps_data_memory: dfps_data_region@5cf00000 {
+ reg = <0x0 0x5cf00000 0x0 0x0100000>;
+ label = "dfps_data_region";
+ };
+
+ adsp_mem: adsp_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x00000000 0 0xffffffff>;
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x800000>;
+ };
+
+ dump_mem: mem_dump_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ size = <0 0x800000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+
+ chosen {
+ bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
+ };
+
+ soc: soc { };
+};
+
+#include "bengal-coresight.dtsi"
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ intc: interrupt-controller@f200000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ reg = <0xf200000 0x10000>, /* GICD */
+ <0xf300000 0x100000>; /* GICR * 8 */
+ interrupts = <1 9 4>;
+ };
+
+ jtag_mm0: jtagmm@9040000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9040000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU0>;
+ };
+
+ jtag_mm1: jtagmm@9140000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9140000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU1>;
+ };
+
+ jtag_mm2: jtagmm@9240000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9240000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU2>;
+ };
+
+ jtag_mm3: jtagmm@9340000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9340000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU3>;
+ };
+
+ jtag_mm4: jtagmm@9440000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9440000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU4>;
+ };
+
+ jtag_mm5: jtagmm@9540000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9540000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU5>;
+ };
+
+ jtag_mm6: jtagmm@9640000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9640000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU6>;
+ };
+
+ jtag_mm7: jtagmm@9740000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9740000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU7>;
+ };
+
+ qcom,memshare {
+ compatible = "qcom,memshare";
+
+ qcom,client_1 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x0>;
+ qcom,client-id = <0>;
+ qcom,allocate-boot-time;
+ label = "modem";
+ };
+
+ qcom,client_2 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x0>;
+ qcom,client-id = <2>;
+ label = "modem";
+ };
+
+ mem_client_3_size: qcom,client_3 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x500000>;
+ qcom,client-id = <1>;
+ qcom,allocate-on-request;
+ label = "modem";
+ };
+ };
+
+ slim_aud: slim@a5c0000 {
+ cell-index = <1>;
+ compatible = "qcom,slim-ngd";
+ reg = <0xa5c0000 0x2c000>,
+ <0xa584000 0x20000>, <0xa66e000 0x2000>;
+ reg-names = "slimbus_physical",
+ "slimbus_bam_physical", "slimbus_lpass_mem";
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "slimbus_irq", "slimbus_bam_irq";
+ qcom,apps-ch-pipes = <0x0>;
+ qcom,ea-pc = <0x3b0>;
+ status = "ok";
+
+ /* Slimbus Slave DT for WCN3990 */
+ btfmslim_codec: wcn3990 {
+ compatible = "qcom,btfmslim_slave";
+ elemental-addr = [00 01 20 02 17 02];
+ qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
+ qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
+ };
+ };
+
+ wakegic: wake-gic {
+ compatible = "qcom,mpm-gic-khaje", "qcom,mpm-gic";
+ interrupts-extended = <&wakegic GIC_SPI 197
+ IRQ_TYPE_EDGE_RISING>;
+ reg = <0x45f01b8 0x1000>,
+ <0xf011008 0x4>; /* MSM_APCS_GCC_BASE 4K */
+ reg-names = "vmpm", "ipc";
+ qcom,num-mpm-irqs = <96>;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <3>;
+ };
+
+ wakegpio: wake-gpio {
+ compatible = "qcom,mpm-gpio";
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <2>;
+ };
+
+ bluetooth: bt_wcn3990 {
+ compatible = "qca,wcn3990";
+ qca,bt-sw-ctrl-gpio = <&tlmm 87 0>; /* SW_CTRL */
+ qca,bt-vdd-io-supply = <&L9A>; /* IO */
+ qca,bt-vdd-core-supply = <&L17A>; /* RFA */
+ qca,bt-vdd-pa-supply = <&L23A>; /* CH0 */
+ qca,bt-vdd-xtal-supply = <&L16A>; /* XO */
+
+ qca,bt-vdd-io-voltage-level = <1700000 1900000>;
+ qca,bt-vdd-core-voltage-level = <1304000 1304000>;
+ qca,bt-vdd-pa-voltage-level = <3000000 3312000>;
+ qca,bt-vdd-xtal-voltage-level = <1700000 1900000>;
+
+ qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 1 0xf08>,
+ <1 2 0xf08>,
+ <1 3 0xf08>,
+ <1 0 0xf08>;
+ clock-frequency = <19200000>;
+ };
+
+ dcc: dcc_v2@1be2000 {
+ compatible = "qcom,dcc-v2";
+ reg = <0x1be2000 0x1000>,
+ <0x1bee000 0x2000>;
+ reg-names = "dcc-base", "dcc-ram-base";
+ dcc-ram-offset = <0x2000>;
+
+ link_list1 {
+ qcom,curr-link-list = <3>;
+ qcom,data-sink = "sram";
+ qcom,link-list = <DCC_READ 0x0F1880B4 1 0>,
+ <DCC_READ 0x0F1980B4 1 0>,
+ <DCC_READ 0x0F1A80B4 1 0>,
+ <DCC_READ 0x0F1B80B4 1 0>,
+ <DCC_READ 0x0F0880B4 1 0>,
+ <DCC_READ 0x0F0980B4 1 0>,
+ <DCC_READ 0x0F0A80B4 1 0>,
+ <DCC_READ 0x0F0B80B4 1 0>,
+ <DCC_READ 0x0F1D1228 1 0>,
+ <DCC_READ 0x0F1880B0 1 0>,
+ <DCC_READ 0x0F1980B0 1 0>,
+ <DCC_READ 0x0F1A80B0 1 0>,
+ <DCC_READ 0x0F1B80B0 1 0>,
+ <DCC_READ 0x0F0880B0 1 0>,
+ <DCC_READ 0x0F0980B0 1 0>,
+ <DCC_READ 0x0F0A80B0 1 0>,
+ <DCC_READ 0x0F0B80B0 1 0>,
+ <DCC_READ 0x0F1880B8 1 0>,
+ <DCC_READ 0x0F1980B8 1 0>,
+ <DCC_READ 0x0F1A80B8 1 0>,
+ <DCC_READ 0x0F1B80B8 1 0>,
+ <DCC_READ 0x0F0880B8 1 0>,
+ <DCC_READ 0x0F0980B8 1 0>,
+ <DCC_READ 0x0F0A80B8 1 0>,
+ <DCC_READ 0x0F0B80B8 1 0>,
+ <DCC_READ 0x0F1D160C 1 0>,
+ <DCC_READ 0x0F1D120C 1 0>,
+ <DCC_READ 0x0F1D1434 1 0>,
+ <DCC_READ 0x0F1D141C 5 0>,
+ <DCC_READ 0x0F1D1448 1 0>,
+ <DCC_READ 0x0F1D144C 1 0>,
+ <DCC_READ 0xA754520 1 0>,
+ <DCC_READ 0xA751020 1 0>,
+ <DCC_READ 0xA751024 1 0>,
+ <DCC_READ 0xA751030 1 0>,
+ <DCC_READ 0xA751200 1 0>,
+ <DCC_READ 0xA751214 1 0>,
+ <DCC_READ 0xA751228 1 0>,
+ <DCC_READ 0xA75123C 1 0>,
+ <DCC_READ 0xA751250 1 0>,
+ <DCC_READ 0xA751204 1 0>,
+ <DCC_READ 0xA751218 1 0>,
+ <DCC_READ 0xA75122C 1 0>,
+ <DCC_READ 0xA751240 1 0>,
+ <DCC_READ 0xA751254 1 0>,
+ <DCC_READ 0xA751208 1 0>,
+ <DCC_READ 0xA75121C 1 0>,
+ <DCC_READ 0xA751230 1 0>,
+ <DCC_READ 0xA751244 1 0>,
+ <DCC_READ 0xA751258 1 0>,
+ <DCC_READ 0xA754510 1 0>,
+ <DCC_READ 0xA754514 1 0>,
+ <DCC_READ 0xA750010 1 0>,
+ <DCC_READ 0xA750014 1 0>,
+ <DCC_READ 0xA750900 1 0>,
+ <DCC_READ 0xA750904 1 0>,
+ <DCC_READ 0x0A402028 1 0>,
+ <DCC_READ 0x0A900010 1 0>,
+ <DCC_READ 0x0A900014 1 0>,
+ <DCC_READ 0x0A900018 1 0>,
+ <DCC_READ 0x0A900030 1 0>,
+ <DCC_READ 0x0A900038 1 0>,
+ <DCC_READ 0x0A900040 1 0>,
+ <DCC_READ 0x0A900048 1 0>,
+ <DCC_READ 0x0A9000D0 1 0>,
+ <DCC_READ 0x0A900210 1 0>,
+ <DCC_READ 0x0A900230 1 0>,
+ <DCC_READ 0x0A900250 1 0>,
+ <DCC_READ 0x0A900270 1 0>,
+ <DCC_READ 0x0A900290 1 0>,
+ <DCC_READ 0x0A9002B0 1 0>,
+ <DCC_READ 0x0A900208 1 0>,
+ <DCC_READ 0x0A900228 1 0>,
+ <DCC_READ 0x0A900248 1 0>,
+ <DCC_READ 0x0A900268 1 0>,
+ <DCC_READ 0x0A900288 1 0>,
+ <DCC_READ 0x0A9002A8 1 0>,
+ <DCC_READ 0x0A90020C 1 0>,
+ <DCC_READ 0x0A90022C 1 0>,
+ <DCC_READ 0x0A90024C 1 0>,
+ <DCC_READ 0x0A90026C 1 0>,
+ <DCC_READ 0x0A90028C 1 0>,
+ <DCC_READ 0x0A9002AC 1 0>,
+ <DCC_READ 0x0A900404 1 0>,
+ <DCC_READ 0x0A900408 1 0>,
+ <DCC_READ 0x0A900400 1 0>,
+ <DCC_READ 0x0A900D04 1 0>,
+ <DCC_READ 0x0A4B0010 1 0>,
+ <DCC_READ 0x0A4B0014 1 0>,
+ <DCC_READ 0x0A4B0018 1 0>,
+ <DCC_READ 0x0A4B0210 1 0>,
+ <DCC_READ 0x0A4B0230 1 0>,
+ <DCC_READ 0x0A4B0250 1 0>,
+ <DCC_READ 0x0A4B0270 1 0>,
+ <DCC_READ 0x0A4B0290 1 0>,
+ <DCC_READ 0x0A4B02B0 1 0>,
+ <DCC_READ 0x0A4B0208 1 0>,
+ <DCC_READ 0x0A4B0228 1 0>,
+ <DCC_READ 0x0A4B0248 1 0>,
+ <DCC_READ 0x0A4B0268 1 0>,
+ <DCC_READ 0x0A4B0288 1 0>,
+ <DCC_READ 0x0A4B02A8 1 0>,
+ <DCC_READ 0x0A4B020C 1 0>,
+ <DCC_READ 0x0A4B022C 1 0>,
+ <DCC_READ 0x0A4B024C 1 0>,
+ <DCC_READ 0x0A4B026C 1 0>,
+ <DCC_READ 0x0A4B028C 1 0>,
+ <DCC_READ 0x0A4B02AC 1 0>,
+ <DCC_READ 0x0A4B0400 1 0>,
+ <DCC_READ 0x0A4B0404 1 0>,
+ <DCC_READ 0x0A4B0408 1 0>,
+ <DCC_READ 0x4488100 1 0>,
+ <DCC_READ 0x4488400 2 0>,
+ <DCC_READ 0x4488410 1 0>,
+ <DCC_READ 0x4488420 2 0>,
+ <DCC_READ 0x4488430 2 0>,
+ <DCC_READ 0x448c100 1 0>,
+ <DCC_READ 0x448c400 2 0>,
+ <DCC_READ 0x448c410 1 0>,
+ <DCC_READ 0x448c420 2 0>,
+ <DCC_READ 0x448c430 2 0>,
+ <DCC_READ 0x4490100 1 0>,
+ <DCC_READ 0x4490400 2 0>,
+ <DCC_READ 0x4490410 1 0>,
+ <DCC_READ 0x4490420 2 0>,
+ <DCC_READ 0x4490430 2 0>,
+ <DCC_READ 0x4494100 1 0>,
+ <DCC_READ 0x4494400 2 0>,
+ <DCC_READ 0x4494410 1 0>,
+ <DCC_READ 0x4494420 2 0>,
+ <DCC_READ 0x4494430 2 0>,
+ <DCC_READ 0x449810c 1 0>,
+ <DCC_READ 0x4498400 2 0>,
+ <DCC_READ 0x4498410 1 0>,
+ <DCC_READ 0x4498420 2 0>,
+ <DCC_READ 0x4498430 2 0>,
+ <DCC_READ 0x44a0100 1 0>,
+ <DCC_READ 0x44a0400 2 0>,
+ <DCC_READ 0x44a0410 1 0>,
+ <DCC_READ 0x44a0420 2 0>,
+ <DCC_READ 0x44a0430 2 0>,
+ <DCC_READ 0x44b0560 1 0>,
+ <DCC_READ 0x44b05a0 1 0>,
+ <DCC_READ 0x44b1800 1 0>,
+ <DCC_READ 0x44b408c 1 0>,
+ <DCC_READ 0x44b409c 1 0>,
+ <DCC_READ 0x44b0520 1 0>,
+ <DCC_READ 0x44b5070 2 0>,
+ <DCC_READ 0x44bc220 1 0>,
+ <DCC_READ 0x44bc400 7 0>,
+ <DCC_READ 0x44bc420 9 0>,
+ <DCC_READ 0x44bd800 1 0>,
+ <DCC_READ 0x44c5800 1 0>,
+ <DCC_READ 0x4480040 2 0>,
+ <DCC_READ 0x4480810 2 0>,
+ <DCC_READ 0x44b0a40 1 0>,
+ <DCC_READ 0x4506044 1 0>,
+ <DCC_READ 0x45061dc 1 0>,
+ <DCC_READ 0x45061ec 1 0>,
+ <DCC_READ 0x4506028 2 0>,
+ <DCC_READ 0x4506094 1 0>,
+ <DCC_READ 0x4506608 1 0>,
+ <DCC_READ 0x447d02c 4 0>,
+ <DCC_READ 0x447d040 1 0>,
+ <DCC_READ 0x450002c 2 0>,
+ <DCC_READ 0x4500094 1 0>,
+ <DCC_READ 0x450009c 1 0>,
+ <DCC_READ 0x45000c4 2 0>,
+ <DCC_READ 0x45003dc 1 0>,
+ <DCC_READ 0x45005d8 1 0>,
+ <DCC_READ 0x450102c 2 0>,
+ <DCC_READ 0x4501094 1 0>,
+ <DCC_READ 0x450109c 1 0>,
+ <DCC_READ 0x45010c4 2 0>,
+ <DCC_READ 0x45013dc 1 0>,
+ <DCC_READ 0x45015d8 1 0>,
+ <DCC_READ 0x450202c 2 0>,
+ <DCC_READ 0x4502094 1 0>,
+ <DCC_READ 0x450209c 1 0>,
+ <DCC_READ 0x45020c4 2 0>,
+ <DCC_READ 0x45023dc 1 0>,
+ <DCC_READ 0x45025d8 1 0>,
+ <DCC_READ 0x450302c 2 0>,
+ <DCC_READ 0x4503094 1 0>,
+ <DCC_READ 0x450309c 1 0>,
+ <DCC_READ 0x45030c4 2 0>,
+ <DCC_READ 0x45033dc 1 0>,
+ <DCC_READ 0x45035d8 1 0>,
+ <DCC_READ 0x450402c 2 0>,
+ <DCC_READ 0x4504094 1 0>,
+ <DCC_READ 0x450409c 1 0>,
+ <DCC_READ 0x45040c8 2 0>,
+ <DCC_READ 0x45043dc 1 0>,
+ <DCC_READ 0x45045d8 1 0>,
+ <DCC_READ 0x450502c 2 0>,
+ <DCC_READ 0x4505094 1 0>,
+ <DCC_READ 0x450509c 1 0>,
+ <DCC_READ 0x45050c4 2 0>,
+ <DCC_READ 0x45053dc 1 0>,
+ <DCC_READ 0x45055d8 1 0>,
+ <DCC_READ 0x141102C 1 0>,
+ <DCC_READ 0x1436004 1 0>,
+ <DCC_READ 0x1471154 1 0>,
+ <DCC_READ 0x141050C 1 0>,
+ <DCC_READ 0x143600C 1 0>,
+ <DCC_READ 0x1436018 1 0>,
+ <DCC_READ 0x147C000 1 0>,
+ <DCC_READ 0x147D000 1 0>,
+ <DCC_READ 0x1436048 1 0>,
+ <DCC_READ 0x1436040 1 0>,
+ <DCC_READ 0x5991004 1 0>,
+ <DCC_READ 0x599100c 1 0>,
+ <DCC_READ 0x5991010 1 0>,
+ <DCC_READ 0x5991014 1 0>,
+ <DCC_READ 0x5991054 1 0>,
+ <DCC_READ 0x5991060 1 0>,
+ <DCC_READ 0x599106c 1 0>,
+ <DCC_READ 0x5991070 1 0>,
+ <DCC_READ 0x5991074 1 0>,
+ <DCC_READ 0x5991078 1 0>,
+ <DCC_READ 0x599107c 1 0>,
+ <DCC_READ 0x599108c 1 0>,
+ <DCC_READ 0x5991098 1 0>,
+ <DCC_READ 0x599109c 1 0>,
+ <DCC_READ 0x5991540 1 0>,
+ <DCC_READ 0x5995000 1 0>,
+ <DCC_READ 0x5995004 1 0>,
+ <DCC_READ 0x599101C 1 0>,
+ <DCC_READ 0x5991020 1 0>,
+ <DCC_READ 0x5990000 1 0>,
+ <DCC_READ 0x5990100 1 0>,
+ <DCC_READ 0x5991508 1 0>,
+ <DCC_READ 0x59910A4 1 0>,
+ <DCC_READ 0x5991578 1 0>,
+ <DCC_READ 0x5990010 1 0>,
+ <DCC_READ 0x5990110 1 0>,
+ <DCC_READ 0xf189000 1 0>,
+ <DCC_READ 0xf18900c 1 0>,
+ <DCC_READ 0xf189c0c 1 0>,
+ <DCC_READ 0xf189c10 1 0>,
+ <DCC_READ 0xf189c20 1 0>,
+ <DCC_READ 0xf199000 1 0>,
+ <DCC_READ 0xf19900c 1 0>,
+ <DCC_READ 0xf199c0c 1 0>,
+ <DCC_READ 0xf199c10 1 0>,
+ <DCC_READ 0xf199c20 1 0>,
+ <DCC_READ 0xf1a9000 1 0>,
+ <DCC_READ 0xf1a900c 1 0>,
+ <DCC_READ 0xf1a9c0c 1 0>,
+ <DCC_READ 0xf1a9c10 1 0>,
+ <DCC_READ 0xf1a9c20 1 0>,
+ <DCC_READ 0xf1b9000 1 0>,
+ <DCC_READ 0xf1b900c 1 0>,
+ <DCC_READ 0xf1b9c0c 1 0>,
+ <DCC_READ 0xf1b9c10 1 0>,
+ <DCC_READ 0xf1b9c18 1 0>,
+ <DCC_READ 0xf089000 1 0>,
+ <DCC_READ 0xf08900c 1 0>,
+ <DCC_READ 0xf089c0c 1 0>,
+ <DCC_READ 0xf089c10 1 0>,
+ <DCC_READ 0xf089c20 1 0>,
+ <DCC_READ 0xf099000 1 0>,
+ <DCC_READ 0xf09900c 1 0>,
+ <DCC_READ 0xf099c0c 1 0>,
+ <DCC_READ 0xf099c10 1 0>,
+ <DCC_READ 0xf099c20 1 0>,
+ <DCC_READ 0xf0a9000 1 0>,
+ <DCC_READ 0xf0a900c 1 0>,
+ <DCC_READ 0xf0a9c0c 1 0>,
+ <DCC_READ 0xf0a9c10 1 0>,
+ <DCC_READ 0xf0a9c20 1 0>,
+ <DCC_READ 0xf0b9000 1 0>,
+ <DCC_READ 0xf0b900c 1 0>,
+ <DCC_READ 0xf0b9c0c 1 0>,
+ <DCC_READ 0xf0b9c10 1 0>,
+ <DCC_READ 0xf0b9c20 1 0>,
+ <DCC_READ 0xf112000 1 0>,
+ <DCC_READ 0xf11200c 1 0>,
+ <DCC_READ 0xf112c0c 1 0>,
+ <DCC_READ 0xf112c10 1 0>,
+ <DCC_READ 0xf112c20 1 0>,
+ <DCC_READ 0xf012000 1 0>,
+ <DCC_READ 0xf01200c 1 0>,
+ <DCC_READ 0xf012c0c 1 0>,
+ <DCC_READ 0xf012c10 1 0>,
+ <DCC_READ 0xf012c20 1 0>,
+ <DCC_READ 0xf1d2000 1 0>,
+ <DCC_READ 0xf1d200c 1 0>,
+ <DCC_READ 0xf1d2c0c 1 0>,
+ <DCC_READ 0xf1d2c10 1 0>,
+ <DCC_READ 0xf1d2c20 1 0>,
+ <DCC_READ 0xf011014 1 0>,
+ <DCC_READ 0xf011018 1 0>,
+ <DCC_READ 0xf011218 1 0>,
+ <DCC_READ 0xf011234 1 0>,
+ <DCC_READ 0xf011220 1 0>,
+ <DCC_READ 0xf011264 1 0>,
+ <DCC_READ 0xf011290 1 0>,
+ <DCC_READ 0xf111014 1 0>,
+ <DCC_READ 0xf111018 1 0>,
+ <DCC_READ 0xf111218 1 0>,
+ <DCC_READ 0xf111234 1 0>,
+ <DCC_READ 0xf111264 1 0>,
+ <DCC_READ 0xf111290 1 0>,
+ <DCC_READ 0x0F521700 1 0>,
+ <DCC_READ 0x0F523700 1 0>,
+ <DCC_READ 0x0F112C18 1 0>,
+ <DCC_READ 0x0F012C18 1 0>,
+ <DCC_READ 0x0F513A84 1 0>,
+ <DCC_READ 0x0F513A88 1 0>,
+ <DCC_READ 0x01B60110 1 0>,
+ <DCC_READ 0x1900010 1 0>,
+ <DCC_READ 0x1900020 1 0>,
+ <DCC_READ 0x1900024 1 0>,
+ <DCC_READ 0x1900028 1 0>,
+ <DCC_READ 0x190002C 1 0>,
+ <DCC_READ 0x1900030 1 0>,
+ <DCC_READ 0x1900034 1 0>,
+ <DCC_READ 0x1900038 1 0>,
+ <DCC_READ 0x190003C 1 0>,
+ <DCC_READ 0x1900300 1 0>,
+ <DCC_READ 0x1900304 1 0>,
+ <DCC_READ 0x1900308 1 0>,
+ <DCC_READ 0x190030C 1 0>,
+ <DCC_READ 0x1900310 1 0>,
+ <DCC_READ 0x1900314 1 0>,
+ <DCC_READ 0x1900900 1 0>,
+ <DCC_READ 0x1900904 1 0>,
+ <DCC_READ 0x1900B00 1 0>,
+ <DCC_READ 0x1900D00 1 0>,
+ <DCC_READ 0x1909100 1 0>,
+ <DCC_READ 0x1909104 1 0>,
+ <DCC_READ 0x1480140 1 0>,
+ <DCC_READ 0x1481140 1 0>,
+ <DCC_READ 0x1415008 1 0>,
+ <DCC_READ 0x1416008 1 0>,
+ <DCC_READ 0x44B0120 1 0>,
+ <DCC_READ 0x44B0124 1 0>,
+ <DCC_READ 0x44B0128 1 0>,
+ <DCC_READ 0x44B012C 1 0>,
+ <DCC_READ 0x44B0130 1 0>,
+ <DCC_READ 0x44B0100 1 0>,
+ <DCC_READ 0x44B0020 1 0>,
+ <DCC_READ 0x44C4000 1 0>,
+ <DCC_READ 0x44C4020 1 0>,
+ <DCC_READ 0x44C4030 1 0>,
+ <DCC_READ 0x44C4100 1 0>,
+ <DCC_READ 0x44C410C 1 0>,
+ <DCC_READ 0x44C4400 1 0>,
+ <DCC_READ 0x44C4410 1 0>,
+ <DCC_READ 0x44C4420 1 0>,
+ <DCC_READ 0x1900240 1 0>,
+ <DCC_READ 0x1900244 1 0>,
+ <DCC_READ 0x1900248 1 0>,
+ <DCC_READ 0x190024C 1 0>,
+ <DCC_READ 0x1900250 1 0>,
+ <DCC_READ 0x1900258 1 0>,
+ <DCC_READ 0x1411004 1 0>,
+ <DCC_READ 0x1411028 1 0>,
+ <DCC_READ 0x1458004 1 0>,
+ <DCC_READ 0x1880108 1 0>,
+ <DCC_READ 0x1880110 1 0>,
+ <DCC_READ 0x1880120 1 0>,
+ <DCC_READ 0x1880124 1 0>,
+ <DCC_READ 0x1880128 1 0>,
+ <DCC_READ 0x188012C 1 0>,
+ <DCC_READ 0x1880130 1 0>,
+ <DCC_READ 0x1880134 1 0>,
+ <DCC_READ 0x1880138 1 0>,
+ <DCC_READ 0x188013C 1 0>,
+ <DCC_READ 0x1880300 1 0>,
+ <DCC_READ 0x1880304 1 0>,
+ <DCC_READ 0x1880308 1 0>,
+ <DCC_READ 0x188030C 1 0>,
+ <DCC_READ 0x1880310 1 0>,
+ <DCC_READ 0x1880314 1 0>,
+ <DCC_READ 0x1880318 1 0>,
+ <DCC_READ 0x188031C 1 0>,
+ <DCC_READ 0x1880700 1 0>,
+ <DCC_READ 0x1880704 1 0>,
+ <DCC_READ 0x1880708 1 0>,
+ <DCC_READ 0x188070C 1 0>,
+ <DCC_READ 0x1880710 1 0>,
+ <DCC_READ 0x1880714 1 0>,
+ <DCC_READ 0x1880718 1 0>,
+ <DCC_READ 0x188071C 1 0>,
+ <DCC_READ 0x1881100 1 0>,
+ <DCC_READ 0x1880240 1 0>,
+ <DCC_READ 0x1880248 1 0>,
+ <DCC_READ 0xF017000 1 0>,
+ <DCC_READ 0xF01700C 1 0>,
+ <DCC_READ 0xF017010 1 0>,
+ <DCC_READ 0xF017014 1 0>,
+ <DCC_READ 0xF017018 1 0>,
+ <DCC_READ 0xF017020 1 0>,
+ <DCC_READ 0x1414008 1 0>,
+ <DCC_READ 0x1414004 1 0>,
+ <DCC_READ 0x5991554 1 0>,
+ <DCC_READ 0x5991544 1 0>,
+ <DCC_READ 0x599155C 1 0>,
+ <DCC_READ 0x440B00C 1 0>,
+ <DCC_READ 0x440B014 1 0>,
+ <DCC_READ 0x0F522C14 1 0>,
+ <DCC_READ 0x0F522C1C 1 0>,
+ <DCC_READ 0x0F522C10 1 0>,
+ <DCC_READ 0x0F524C10 1 0>,
+ <DCC_READ 0x0F524C14 1 0>,
+ <DCC_READ 0x0F524C18 1 0>,
+ <DCC_READ 0x0F524C1C 1 0>,
+ <DCC_READ 0x0F521920 1 0>,
+ <DCC_READ 0x0F52102C 1 0>,
+ <DCC_READ 0x0F521044 1 0>,
+ <DCC_READ 0x0F521710 1 0>,
+ <DCC_READ 0x0F52176C 1 0>,
+ <DCC_READ 0x0F523920 1 0>,
+ <DCC_READ 0x0F52302C 1 0>,
+ <DCC_READ 0x0F523044 1 0>,
+ <DCC_READ 0x0F523710 1 0>,
+ <DCC_READ 0x0F52376C 1 0>,
+ <DCC_READ 0x0F116000 1 0>,
+ <DCC_READ 0x0F116004 1 0>,
+ <DCC_READ 0x0F11602C 1 0>,
+ <DCC_READ 0x0F016000 1 0>,
+ <DCC_READ 0x0F016004 1 0>,
+ <DCC_READ 0x0F01602C 1 0>,
+ <DCC_READ 0x0F111250 1 0>,
+ <DCC_READ 0x0F111254 1 0>,
+ <DCC_READ 0x0F111258 1 0>,
+ <DCC_READ 0x0F11125C 1 0>,
+ <DCC_READ 0x0F111260 1 0>,
+ <DCC_READ 0x0F188078 1 0>,
+ <DCC_READ 0x0F188084 1 0>,
+ <DCC_READ 0x0F198078 1 0>,
+ <DCC_READ 0x0F198084 1 0>,
+ <DCC_READ 0x0F1A8078 1 0>,
+ <DCC_READ 0x0F1A8084 1 0>,
+ <DCC_READ 0x0F1B8078 1 0>,
+ <DCC_READ 0x0F1B8084 1 0>,
+ <DCC_READ 0x0F521818 1 0>,
+ <DCC_READ 0x0F52181C 1 0>,
+ <DCC_READ 0x0F521828 1 0>,
+ <DCC_READ 0x0F523818 1 0>,
+ <DCC_READ 0x0F52381C 1 0>,
+ <DCC_READ 0x0F523828 1 0>,
+ <DCC_READ 0x0F522C18 1 0>,
+ <DCC_READ 0x0F111310 1 0>,
+ <DCC_READ 0x0F111314 1 0>,
+ <DCC_READ 0x0F111318 1 0>,
+ <DCC_READ 0x0F01125C 1 0>,
+ <DCC_READ 0x0F011258 1 0>,
+ <DCC_READ 0x0F011310 1 0>,
+ <DCC_READ 0x0F011314 1 0>,
+ <DCC_READ 0x0F011318 1 0>,
+ <DCC_WRITE 0x9870010 0x14000 0>,
+ <DCC_READ 0xF011600 1 0>,
+ <DCC_READ 0xF011608 1 0>,
+ <DCC_READ 0xF01160C 1 0>,
+ <DCC_READ 0xF011610 1 0>,
+ <DCC_READ 0xF011614 1 0>,
+ <DCC_READ 0xF011618 1 0>,
+ <DCC_READ 0xF01161C 1 0>,
+ <DCC_READ 0xF011620 1 0>,
+ <DCC_READ 0xF011624 1 0>,
+ <DCC_READ 0xF011628 1 0>,
+ <DCC_READ 0xF01162C 1 0>,
+ <DCC_READ 0xF011630 1 0>,
+ <DCC_READ 0xF011634 1 0>,
+ <DCC_READ 0xF011638 1 0>,
+ <DCC_READ 0xF01163C 1 0>,
+ <DCC_READ 0xF011640 1 0>,
+ <DCC_READ 0xF011644 1 0>,
+ <DCC_READ 0xF011648 1 0>,
+ <DCC_READ 0xF01164C 1 0>,
+ <DCC_READ 0xF011650 1 0>,
+ <DCC_READ 0xF011654 1 0>,
+ <DCC_READ 0xF011658 1 0>,
+ <DCC_READ 0xF01165C 1 0>,
+ <DCC_READ 0xF011664 1 0>,
+ <DCC_READ 0xF111600 1 0>,
+ <DCC_READ 0xF111608 1 0>,
+ <DCC_READ 0xF11160C 1 0>,
+ <DCC_READ 0xF111610 1 0>,
+ <DCC_READ 0xF111614 1 0>,
+ <DCC_READ 0xF111618 1 0>,
+ <DCC_READ 0xF11161C 1 0>,
+ <DCC_READ 0xF111620 1 0>,
+ <DCC_READ 0xF111624 1 0>,
+ <DCC_READ 0xF111628 1 0>,
+ <DCC_READ 0xF11162C 1 0>,
+ <DCC_READ 0xF111630 1 0>,
+ <DCC_READ 0xF111634 1 0>,
+ <DCC_READ 0xF111638 1 0>,
+ <DCC_READ 0xF11163C 1 0>,
+ <DCC_READ 0xF111640 1 0>,
+ <DCC_READ 0xF111644 1 0>,
+ <DCC_READ 0xF111648 1 0>,
+ <DCC_READ 0xF111650 1 0>,
+ <DCC_READ 0xF111654 1 0>,
+ <DCC_READ 0xF111658 1 0>,
+ <DCC_READ 0xF11165C 1 0>,
+ <DCC_READ 0xF111664 1 0>,
+ <DCC_READ 0xF011400 1 0>,
+ <DCC_READ 0xF111400 1 0>,
+ <DCC_WRITE 0x9870010 0x0 0>,
+ <DCC_READ 0x06130010 1 0>,
+ <DCC_READ 0x06130014 1 0>,
+ <DCC_READ 0x06130018 1 0>,
+ <DCC_READ 0x06130210 1 0>,
+ <DCC_READ 0x06130230 1 0>,
+ <DCC_READ 0x06130250 1 0>,
+ <DCC_READ 0x06130270 1 0>,
+ <DCC_READ 0x06130290 1 0>,
+ <DCC_READ 0x061302B0 1 0>,
+ <DCC_READ 0x06130208 1 0>,
+ <DCC_READ 0x06130228 1 0>,
+ <DCC_READ 0x06130248 1 0>,
+ <DCC_READ 0x06130268 1 0>,
+ <DCC_READ 0x06130288 1 0>,
+ <DCC_READ 0x061302A8 1 0>,
+ <DCC_READ 0x0613020C 1 0>,
+ <DCC_READ 0x0613022C 1 0>,
+ <DCC_READ 0x0613024C 1 0>,
+ <DCC_READ 0x0613026C 1 0>,
+ <DCC_READ 0x0613028C 1 0>,
+ <DCC_READ 0x061302AC 1 0>,
+ <DCC_READ 0x06130400 1 0>,
+ <DCC_READ 0x06130404 1 0>,
+ <DCC_READ 0x06130408 1 0>,
+ <DCC_READ 0x6082028 1 0>,
+ <DCC_READ 0x0143300C 1 0>,
+ <DCC_READ 0x0B3B0010 1 0>,
+ <DCC_READ 0x0B3B0014 1 0>,
+ <DCC_READ 0x0B3B0018 1 0>,
+ <DCC_READ 0x0B3B0210 1 0>,
+ <DCC_READ 0x0B3B0230 1 0>,
+ <DCC_READ 0x0B3B0250 1 0>,
+ <DCC_READ 0x0B3B0270 1 0>,
+ <DCC_READ 0x0B3B0290 1 0>,
+ <DCC_READ 0x0B3B02B0 1 0>,
+ <DCC_READ 0x0B3B0208 1 0>,
+ <DCC_READ 0x0B3B0228 1 0>,
+ <DCC_READ 0x0B3B0248 1 0>,
+ <DCC_READ 0x0B3B0268 1 0>,
+ <DCC_READ 0x0B3B0288 1 0>,
+ <DCC_READ 0x0B3B02A8 1 0>,
+ <DCC_READ 0x0B3B020C 1 0>,
+ <DCC_READ 0x0B3B022C 1 0>,
+ <DCC_READ 0x0B3B024C 1 0>,
+ <DCC_READ 0x0B3B026C 1 0>,
+ <DCC_READ 0x0B3B028C 1 0>,
+ <DCC_READ 0x0B3B02AC 1 0>,
+ <DCC_READ 0x0B3B0400 1 0>,
+ <DCC_READ 0x0B3B0404 1 0>,
+ <DCC_READ 0x0B3B0408 1 0>,
+ <DCC_READ 0x0B302028 1 0>,
+ <DCC_READ 0x0B300044 1 0>,
+ <DCC_READ 0x0B300304 1 0>,
+ <DCC_READ 0x5C6F000 1 0>,
+ <DCC_READ 0x5C42000 1 0>,
+ <DCC_READ 0x5C42400 1 0>,
+ <DCC_READ 0x5C23000 1 0>;
+ };
+
+ link_list2 {
+ qcom,curr-link-list = <2>;
+ qcom,data-sink = "sram";
+ qcom,link-list = <DCC_READ 0x01480140 1 0>,
+ <DCC_READ 0x01481140 1 0>,
+ <DCC_READ 0x0148014C 1 0>,
+ <DCC_READ 0x0148114C 1 0>,
+ <DCC_READ 0x01477008 1 0>,
+ <DCC_READ 0x01439000 1 0>,
+ <DCC_READ 0x01415010 1 0>,
+ <DCC_READ 0x01416010 1 0>,
+ <DCC_READ 0x0142A00C 1 0>,
+ <DCC_READ 0x1400000 1 0>,
+ <DCC_READ 0x1400004 1 0>,
+ <DCC_READ 0x1400008 1 0>,
+ <DCC_READ 0x140000C 1 0>,
+ <DCC_READ 0x1400010 1 0>,
+ <DCC_READ 0x1400014 1 0>,
+ <DCC_READ 0x1400018 1 0>,
+ <DCC_READ 0x140001C 1 0>,
+ <DCC_READ 0x1400020 1 0>,
+ <DCC_READ 0x1400024 1 0>,
+ <DCC_READ 0x1401000 1 0>,
+ <DCC_READ 0x1401004 1 0>,
+ <DCC_READ 0x1401008 1 0>,
+ <DCC_READ 0x140100C 1 0>,
+ <DCC_READ 0x1401010 1 0>,
+ <DCC_READ 0x1401014 1 0>,
+ <DCC_READ 0x1401018 1 0>,
+ <DCC_READ 0x140101C 1 0>,
+ <DCC_READ 0x1401020 1 0>,
+ <DCC_READ 0x1401024 1 0>,
+ <DCC_READ 0x1402000 1 0>,
+ <DCC_READ 0x1402004 1 0>,
+ <DCC_READ 0x1402008 1 0>,
+ <DCC_READ 0x140200C 1 0>,
+ <DCC_READ 0x1402010 1 0>,
+ <DCC_READ 0x1402014 1 0>,
+ <DCC_READ 0x1402018 1 0>,
+ <DCC_READ 0x140201C 1 0>,
+ <DCC_READ 0x1402020 1 0>,
+ <DCC_READ 0x1402024 1 0>,
+ <DCC_READ 0x1403000 1 0>,
+ <DCC_READ 0x1403004 1 0>,
+ <DCC_READ 0x1403008 1 0>,
+ <DCC_READ 0x140300C 1 0>,
+ <DCC_READ 0x1403010 1 0>,
+ <DCC_READ 0x1403014 1 0>,
+ <DCC_READ 0x1403018 1 0>,
+ <DCC_READ 0x140301C 1 0>,
+ <DCC_READ 0x1403020 1 0>,
+ <DCC_READ 0x1403024 1 0>,
+ <DCC_READ 0x1404000 1 0>,
+ <DCC_READ 0x1404004 1 0>,
+ <DCC_READ 0x1404008 1 0>,
+ <DCC_READ 0x140400C 1 0>,
+ <DCC_READ 0x1404010 1 0>,
+ <DCC_READ 0x1404014 1 0>,
+ <DCC_READ 0x1404018 1 0>,
+ <DCC_READ 0x140401C 1 0>,
+ <DCC_READ 0x1404020 1 0>,
+ <DCC_READ 0x1404024 1 0>,
+ <DCC_READ 0x1405000 1 0>,
+ <DCC_READ 0x1405004 1 0>,
+ <DCC_READ 0x1405008 1 0>,
+ <DCC_READ 0x140500C 1 0>,
+ <DCC_READ 0x1405010 1 0>,
+ <DCC_READ 0x1405014 1 0>,
+ <DCC_READ 0x1405018 1 0>,
+ <DCC_READ 0x140501C 1 0>,
+ <DCC_READ 0x1405020 1 0>,
+ <DCC_READ 0x1405024 1 0>,
+ <DCC_READ 0x1406000 1 0>,
+ <DCC_READ 0x1406004 1 0>,
+ <DCC_READ 0x1406008 1 0>,
+ <DCC_READ 0x140600C 1 0>,
+ <DCC_READ 0x1406010 1 0>,
+ <DCC_READ 0x1406014 1 0>,
+ <DCC_READ 0x1406018 1 0>,
+ <DCC_READ 0x140601C 1 0>,
+ <DCC_READ 0x1406020 1 0>,
+ <DCC_READ 0x1406024 1 0>,
+ <DCC_READ 0x1407000 1 0>,
+ <DCC_READ 0x1407004 1 0>,
+ <DCC_READ 0x1407008 1 0>,
+ <DCC_READ 0x140700C 1 0>,
+ <DCC_READ 0x1407010 1 0>,
+ <DCC_READ 0x1407014 1 0>,
+ <DCC_READ 0x1407018 1 0>,
+ <DCC_READ 0x140701C 1 0>,
+ <DCC_READ 0x1407020 1 0>,
+ <DCC_READ 0x1407024 1 0>,
+ <DCC_READ 0x1407028 1 0>,
+ <DCC_READ 0x140702C 1 0>,
+ <DCC_READ 0x1407030 1 0>,
+ <DCC_READ 0x1407034 1 0>,
+ <DCC_READ 0x1408000 1 0>,
+ <DCC_READ 0x1408004 1 0>,
+ <DCC_READ 0x1408008 1 0>,
+ <DCC_READ 0x140800C 1 0>,
+ <DCC_READ 0x1408010 1 0>,
+ <DCC_READ 0x1408014 1 0>,
+ <DCC_READ 0x1408018 1 0>,
+ <DCC_READ 0x140801C 1 0>,
+ <DCC_READ 0x1408020 1 0>,
+ <DCC_READ 0x1408024 1 0>,
+ <DCC_READ 0x1409000 1 0>,
+ <DCC_READ 0x1409004 1 0>,
+ <DCC_READ 0x1409008 1 0>,
+ <DCC_READ 0x140900C 1 0>,
+ <DCC_READ 0x1409010 1 0>,
+ <DCC_READ 0x1409014 1 0>,
+ <DCC_READ 0x1409018 1 0>,
+ <DCC_READ 0x140901C 1 0>,
+ <DCC_READ 0x1409020 1 0>,
+ <DCC_READ 0x1409024 1 0>,
+ <DCC_READ 0x141001C 1 0>,
+ <DCC_READ 0x14103EC 1 0>,
+ <DCC_READ 0x1414024 1 0>,
+ <DCC_READ 0x1415004 1 0>,
+ <DCC_READ 0x1415008 1 0>,
+ <DCC_READ 0x141500C 1 0>,
+ <DCC_READ 0x1415034 1 0>,
+ <DCC_READ 0x1416004 1 0>,
+ <DCC_READ 0x1416008 1 0>,
+ <DCC_READ 0x141600C 1 0>,
+ <DCC_READ 0x1416038 1 0>,
+ <DCC_READ 0x141703C 1 0>,
+ <DCC_READ 0x1417040 1 0>,
+ <DCC_READ 0x141A004 1 0>,
+ <DCC_READ 0x141A008 1 0>,
+ <DCC_READ 0x141A00C 1 0>,
+ <DCC_READ 0x141A01C 1 0>,
+ <DCC_READ 0x141A020 1 0>,
+ <DCC_READ 0x141A034 1 0>,
+ <DCC_READ 0x141A038 1 0>,
+ <DCC_READ 0x141A060 1 0>,
+ <DCC_READ 0x141A064 1 0>,
+ <DCC_READ 0x141E00C 1 0>,
+ <DCC_READ 0x141E010 1 0>,
+ <DCC_READ 0x141F02C 1 0>,
+ <DCC_READ 0x141F148 1 0>,
+ <DCC_READ 0x141F14C 1 0>,
+ <DCC_READ 0x141F15C 1 0>,
+ <DCC_READ 0x141F278 1 0>,
+ <DCC_READ 0x141F27C 1 0>,
+ <DCC_READ 0x141F28C 1 0>,
+ <DCC_READ 0x141F3A8 1 0>,
+ <DCC_READ 0x141F3AC 1 0>,
+ <DCC_READ 0x141F3BC 1 0>,
+ <DCC_READ 0x141F4D8 1 0>,
+ <DCC_READ 0x141F4DC 1 0>,
+ <DCC_READ 0x141F4EC 1 0>,
+ <DCC_READ 0x141F608 1 0>,
+ <DCC_READ 0x141F60C 1 0>,
+ <DCC_READ 0x141F61C 1 0>,
+ <DCC_READ 0x141F738 1 0>,
+ <DCC_READ 0x141F73C 1 0>,
+ <DCC_READ 0x141F74C 1 0>,
+ <DCC_READ 0x1420010 1 0>,
+ <DCC_READ 0x1420014 1 0>,
+ <DCC_READ 0x1426018 1 0>,
+ <DCC_READ 0x142601C 1 0>,
+ <DCC_READ 0x1426030 1 0>,
+ <DCC_READ 0x1426034 1 0>,
+ <DCC_READ 0x1427024 1 0>,
+ <DCC_READ 0x1428014 1 0>,
+ <DCC_READ 0x1428018 1 0>,
+ <DCC_READ 0x142802C 1 0>,
+ <DCC_READ 0x1428030 1 0>,
+ <DCC_READ 0x1429004 1 0>,
+ <DCC_READ 0x1429008 1 0>,
+ <DCC_READ 0x142900C 1 0>,
+ <DCC_READ 0x1429040 1 0>,
+ <DCC_READ 0x1429044 1 0>,
+ <DCC_READ 0x142A000 1 0>,
+ <DCC_READ 0x142A004 1 0>,
+ <DCC_READ 0x142A008 1 0>,
+ <DCC_READ 0x142A154 1 0>,
+ <DCC_READ 0x142A158 1 0>,
+ <DCC_READ 0x142B13C 1 0>,
+ <DCC_READ 0x142B140 1 0>,
+ <DCC_READ 0x142B158 1 0>,
+ <DCC_READ 0x142B15C 1 0>,
+ <DCC_READ 0x142E00C 1 0>,
+ <DCC_READ 0x142E010 1 0>,
+ <DCC_READ 0x142F00C 1 0>,
+ <DCC_READ 0x142F010 1 0>,
+ <DCC_READ 0x1432004 1 0>,
+ <DCC_READ 0x1432008 1 0>,
+ <DCC_READ 0x143200C 1 0>,
+ <DCC_READ 0x1432034 1 0>,
+ <DCC_READ 0x1432080 1 0>,
+ <DCC_READ 0x1438010 1 0>,
+ <DCC_READ 0x1438014 1 0>,
+ <DCC_READ 0x1438028 1 0>,
+ <DCC_READ 0x143802C 1 0>,
+ <DCC_READ 0x143B000 1 0>,
+ <DCC_READ 0x143B004 1 0>,
+ <DCC_READ 0x143B008 1 0>,
+ <DCC_READ 0x143B00C 1 0>,
+ <DCC_READ 0x143B010 1 0>,
+ <DCC_READ 0x143B014 1 0>,
+ <DCC_READ 0x143B018 1 0>,
+ <DCC_READ 0x143B01C 1 0>,
+ <DCC_READ 0x143B020 1 0>,
+ <DCC_READ 0x143B024 1 0>,
+ <DCC_READ 0x143D01C 1 0>,
+ <DCC_READ 0x143D020 1 0>,
+ <DCC_READ 0x143E000 1 0>,
+ <DCC_READ 0x143E004 1 0>,
+ <DCC_READ 0x143E008 1 0>,
+ <DCC_READ 0x143E00C 1 0>,
+ <DCC_READ 0x143E010 1 0>,
+ <DCC_READ 0x143E014 1 0>,
+ <DCC_READ 0x143E018 1 0>,
+ <DCC_READ 0x143E01C 1 0>,
+ <DCC_READ 0x143E020 1 0>,
+ <DCC_READ 0x143E024 1 0>,
+ <DCC_READ 0x143E060 1 0>,
+ <DCC_READ 0x143F000 1 0>,
+ <DCC_READ 0x143F004 1 0>,
+ <DCC_READ 0x143F008 1 0>,
+ <DCC_READ 0x143F00C 1 0>,
+ <DCC_READ 0x143F010 1 0>,
+ <DCC_READ 0x143F014 1 0>,
+ <DCC_READ 0x143F018 1 0>,
+ <DCC_READ 0x143F01C 1 0>,
+ <DCC_READ 0x143F020 1 0>,
+ <DCC_READ 0x143F024 1 0>,
+ <DCC_READ 0x1442018 1 0>,
+ <DCC_READ 0x144201C 1 0>,
+ <DCC_READ 0x1442030 1 0>,
+ <DCC_READ 0x1442034 1 0>,
+ <DCC_READ 0x1445004 1 0>,
+ <DCC_READ 0x1445008 1 0>,
+ <DCC_READ 0x144500C 1 0>,
+ <DCC_READ 0x1445020 1 0>,
+ <DCC_READ 0x1445024 1 0>,
+ <DCC_READ 0x1445048 1 0>,
+ <DCC_READ 0x144504C 1 0>,
+ <DCC_READ 0x1445060 1 0>,
+ <DCC_READ 0x1445064 1 0>,
+ <DCC_READ 0x144507C 1 0>,
+ <DCC_READ 0x1445080 1 0>,
+ <DCC_READ 0x1446004 1 0>,
+ <DCC_READ 0x1446008 1 0>,
+ <DCC_READ 0x1446024 1 0>,
+ <DCC_READ 0x1446150 1 0>,
+ <DCC_READ 0x1448024 1 0>,
+ <DCC_READ 0x144D004 1 0>,
+ <DCC_READ 0x144D008 1 0>,
+ <DCC_READ 0x144E004 1 0>,
+ <DCC_READ 0x144E008 1 0>,
+ <DCC_READ 0x144F004 1 0>,
+ <DCC_READ 0x144F008 1 0>,
+ <DCC_READ 0x1451000 1 0>,
+ <DCC_READ 0x1451004 1 0>,
+ <DCC_READ 0x145101C 1 0>,
+ <DCC_READ 0x1451020 1 0>,
+ <DCC_READ 0x1451038 1 0>,
+ <DCC_READ 0x145103C 1 0>,
+ <DCC_READ 0x1451054 1 0>,
+ <DCC_READ 0x1451058 1 0>,
+ <DCC_READ 0x1452004 1 0>,
+ <DCC_READ 0x1452008 1 0>,
+ <DCC_READ 0x1452028 1 0>,
+ <DCC_READ 0x145202C 1 0>,
+ <DCC_READ 0x1454004 1 0>,
+ <DCC_READ 0x1455000 1 0>,
+ <DCC_READ 0x1455004 1 0>,
+ <DCC_READ 0x1457000 1 0>,
+ <DCC_READ 0x1457004 1 0>,
+ <DCC_READ 0x1457008 1 0>,
+ <DCC_READ 0x145700C 1 0>,
+ <DCC_READ 0x1457010 1 0>,
+ <DCC_READ 0x145A000 1 0>,
+ <DCC_READ 0x145A004 1 0>,
+ <DCC_READ 0x145A008 1 0>,
+ <DCC_READ 0x145A00C 1 0>,
+ <DCC_READ 0x145A010 1 0>,
+ <DCC_READ 0x145B000 1 0>,
+ <DCC_READ 0x145B004 1 0>,
+ <DCC_READ 0x145B00C 1 0>,
+ <DCC_READ 0x1463020 1 0>,
+ <DCC_READ 0x1469000 1 0>,
+ <DCC_READ 0x1469004 1 0>,
+ <DCC_READ 0x1469008 1 0>,
+ <DCC_READ 0x146900C 1 0>,
+ <DCC_READ 0x1469010 1 0>,
+ <DCC_READ 0x146B000 1 0>,
+ <DCC_READ 0x146B004 1 0>,
+ <DCC_READ 0x146B008 1 0>,
+ <DCC_READ 0x146B00C 1 0>,
+ <DCC_READ 0x146B010 1 0>,
+ <DCC_READ 0x146B014 1 0>,
+ <DCC_READ 0x146B018 1 0>,
+ <DCC_READ 0x146B01C 1 0>,
+ <DCC_READ 0x146B020 1 0>,
+ <DCC_READ 0x146C000 1 0>,
+ <DCC_READ 0x146C004 1 0>,
+ <DCC_READ 0x146C00C 1 0>,
+ <DCC_READ 0x1475000 1 0>,
+ <DCC_READ 0x1475004 1 0>,
+ <DCC_READ 0x147500C 1 0>,
+ <DCC_READ 0x1477000 1 0>,
+ <DCC_READ 0x1477004 1 0>,
+ <DCC_READ 0x147700C 1 0>,
+ <DCC_READ 0x1478030 1 0>,
+ <DCC_READ 0x1479000 1 0>,
+ <DCC_READ 0x1479004 1 0>,
+ <DCC_READ 0x147900C 1 0>,
+ <DCC_READ 0x147A000 1 0>,
+ <DCC_READ 0x147A004 1 0>,
+ <DCC_READ 0x147A00C 1 0>,
+ <DCC_READ 0x1480018 1 0>,
+ <DCC_READ 0x1480144 1 0>,
+ <DCC_READ 0x1481144 1 0>,
+ <DCC_READ 0x148B004 1 0>,
+ <DCC_READ 0x1490004 1 0>,
+ <DCC_READ 0x1490008 1 0>,
+ <DCC_READ 0x1490024 1 0>,
+ <DCC_READ 0x1490028 1 0>,
+ <DCC_READ 0x149002C 1 0>,
+ <DCC_READ 0x1490034 1 0>,
+ <DCC_READ 0x1495000 1 0>,
+ <DCC_READ 0x1495004 1 0>,
+ <DCC_READ 0x149500C 1 0>,
+ <DCC_READ 0x14B5000 1 0>,
+ <DCC_READ 0x14C4000 1 0>,
+ <DCC_READ 0x14C5000 1 0>,
+ <DCC_READ 0x14C6000 1 0>,
+ <DCC_READ 0x14C7000 1 0>,
+ <DCC_READ 0x440C000 1 0>,
+ <DCC_READ 0x440C004 1 0>,
+ <DCC_READ 0x440C008 1 0>,
+ <DCC_READ 0x440C040 1 0>,
+ <DCC_READ 0x440C044 1 0>,
+ <DCC_READ 0x440C048 1 0>,
+ <DCC_READ 0x440C04C 1 0>,
+ <DCC_READ 0x440C050 1 0>,
+ <DCC_READ 0x440C054 1 0>,
+ <DCC_READ 0x440C058 1 0>,
+ <DCC_READ 0x440C05C 1 0>,
+ <DCC_READ 0x440C060 1 0>,
+ <DCC_READ 0x440C068 1 0>,
+ <DCC_READ 0x440C06C 1 0>,
+ <DCC_READ 0x440E050 1 0>,
+ <DCC_READ 0x440E054 1 0>,
+ <DCC_READ 0x440E0A0 1 0>,
+ <DCC_READ 0x440E0A4 1 0>,
+ <DCC_READ 0x440F010 1 0>;
+ };
+ };
+
+ timer@f120000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xf120000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@f121000 {
+ frame-number = <0>;
+ interrupts = <0 8 0x4>,
+ <0 7 0x4>;
+ reg = <0xf121000 0x1000>,
+ <0xf122000 0x1000>;
+ };
+
+ frame@f123000 {
+ frame-number = <1>;
+ interrupts = <0 9 0x4>;
+ reg = <0xf123000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f124000 {
+ frame-number = <2>;
+ interrupts = <0 10 0x4>;
+ reg = <0xf124000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f125000 {
+ frame-number = <3>;
+ interrupts = <0 11 0x4>;
+ reg = <0xf125000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f126000 {
+ frame-number = <4>;
+ interrupts = <0 12 0x4>;
+ reg = <0xf126000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f127000 {
+ frame-number = <5>;
+ interrupts = <0 13 0x4>;
+ reg = <0xf127000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f128000 {
+ frame-number = <6>;
+ interrupts = <0 14 0x4>;
+ reg = <0xf128000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ arm64_cpu_erp {
+ compatible = "arm,arm64-cpu-erp";
+ interrupt-names = "pri-dbe-irq",
+ "sec-dbe-irq",
+ "pri-ext-irq",
+ "sec-ext-irq";
+ interrupts = <0 43 4>,
+ <0 44 4>,
+ <0 41 4>,
+ <0 42 4>;
+ poll-delay-ms = <5000>;
+ };
+
+ l2cache_pmu {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "qcom,l2cache-pmu";
+ ranges;
+
+ cluster0@f111000 {
+ cluster-id = <0>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf111000 0x1000>;
+ };
+
+ cluster1@f011000 {
+ cluster-id = <1>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xf011000 0x1000>;
+ };
+ };
+
+ qcom,msm-imem@c125000 {
+ compatible = "qcom,msm-imem";
+ reg = <0xc125000 0x1000>;
+ ranges = <0x0 0xc125000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mem_dump_table@10 {
+ compatible = "qcom,msm-imem-mem_dump_table";
+ reg = <0x10 0x8>;
+ };
+
+ restart_reason@65c {
+ compatible = "qcom,msm-imem-restart_reason";
+ reg = <0x65c 0x4>;
+ };
+
+ dload_type@1c {
+ compatible = "qcom,msm-imem-dload-type";
+ reg = <0x1c 0x4>;
+ };
+
+ boot_stats@6b0 {
+ compatible = "qcom,msm-imem-boot_stats";
+ reg = <0x6b0 0x20>;
+ };
+
+ kaslr_offset@6d0 {
+ compatible = "qcom,msm-imem-kaslr_offset";
+ reg = <0x6d0 0xc>;
+ };
+
+ pil@94c {
+ compatible = "qcom,msm-imem-pil";
+ reg = <0x94c 0xc8>;
+ };
+
+ diag_dload@c8 {
+ compatible = "qcom,msm-imem-diag-dload";
+ reg = <0xc8 0xc8>;
+ };
+ };
+
+ restart@440b000 {
+ compatible = "qcom,pshold";
+ reg = <0x440b000 0x4>,
+ <0x03d3000 0x4>;
+ reg-names = "pshold-base", "tcsr-boot-misc-detect";
+ };
+
+ qcom_seecom: qseecom@61800000 {
+ compatible = "qcom,qseecom";
+ reg = <0x61800000 0x2100000>;
+ reg-names = "secapp-region";
+ memory-region = <&qseecom_mem>;
+ qcom,hlos-num-ce-hw-instances = <1>;
+ qcom,hlos-ce-hw-instance = <0>;
+ qcom,qsee-ce-hw-instance = <0>;
+ qcom,disk-encrypt-pipe-pair = <2>;
+ qcom,support-fde;
+ qcom,fde-key-size;
+ qcom,appsbl-qseecom-support;
+ qcom,commonlib64-loaded-by-uefi;
+ qcom,msm-bus,name = "qseecom-noc";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 0 0>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 200000 400000>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 300000 800000>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 400000 1000000>;
+ clock-names =
+ "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks =
+ <&rpmcc QSEECOM_CE1_CLK>,
+ <&rpmcc QSEECOM_CE1_CLK>,
+ <&rpmcc QSEECOM_CE1_CLK>,
+ <&rpmcc QSEECOM_CE1_CLK>;
+ qcom,ce-opp-freq = <192000000>;
+ qcom,qsee-reentrancy-support = <2>;
+ };
+
+ qcom_smcinvoke: smcinvoke@61800000 {
+ compatible = "qcom,smcinvoke";
+ reg = <0x61800000 0x2100000>;
+ reg-names = "secapp-region";
+ };
+
+ qcom_rng: qrng@1b53000 {
+ compatible = "qcom,msm-rng";
+ reg = <0x1b53000 0x1000>;
+ qcom,msm-rng-iface-clk;
+ qcom,no-qrng-config;
+ qcom,msm-bus,name = "msm-rng-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_PRNG 0 0>, /* No vote */
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_PRNG 0 300000>; /* 75 MHz */
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "iface_clk";
+ };
+
+ qcom_tzlog: tz-log@c125720 {
+ compatible = "qcom,tz-log";
+ reg = <0xc125720 0x3000>;
+ qcom,hyplog-enabled;
+ hyplog-address-offset = <0x410>;
+ hyplog-size-offset = <0x414>;
+ };
+
+ qcom_cedev: qcedev@1b20000 {
+ compatible = "qcom,qcedev";
+ reg = <0x1b20000 0x20000>,
+ <0x1b04000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <3>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,ce-hw-shared;
+ qcom,bam-ee = <0>;
+ qcom,msm-bus,name = "qcedev-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 0 0>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 393600 393600>;
+ clock-names =
+ "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks =
+ <&rpmcc QCEDEV_CE1_CLK>,
+ <&rpmcc QCEDEV_CE1_CLK>,
+ <&rpmcc QCEDEV_CE1_CLK>,
+ <&rpmcc QCEDEV_CE1_CLK>;
+ qcom,ce-opp-freq = <192000000>;
+ qcom,smmu-s1-enable;
+ iommus = <&apps_smmu 0x0086 0x0011>,
+ <&apps_smmu 0x0096 0x0011>;
+ qcom,iommu-dma = "atomic";
+
+ qcom_cedev_ns_cb {
+ compatible = "qcom,qcedev,context-bank";
+ label = "ns_context";
+ iommus = <&apps_smmu 0x92 0>,
+ <&apps_smmu 0x98 0x1>,
+ <&apps_smmu 0x9F 0>;
+ qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>;
+ };
+
+ qcom_cedev_s_cb {
+ compatible = "qcom,qcedev,context-bank";
+ label = "secure_context";
+ iommus = <&apps_smmu 0x93 0>,
+ <&apps_smmu 0x9C 0x1>,
+ <&apps_smmu 0x9E 0>;
+ qcom,iommu-dma-addr-pool = <0x70000000 0X10000000>;
+ qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
+ qcom,secure-context-bank;
+ };
+ };
+
+ qcom_crypto: qcrypto@1b20000 {
+ compatible = "qcom,qcrypto";
+ reg = <0x1b20000 0x20000>,
+ <0x1b04000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <2>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,bam-ee = <0>;
+ qcom,ce-hw-shared;
+ qcom,clk-mgmt-sus-res;
+ qcom,msm-bus,name = "qcrypto-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST
+ 0 0>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST
+ 393600 393600>;
+ clock-names =
+ "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks =
+ <&rpmcc QCRYPTO_CE1_CLK>,
+ <&rpmcc QCRYPTO_CE1_CLK>,
+ <&rpmcc QCRYPTO_CE1_CLK>,
+ <&rpmcc QCRYPTO_CE1_CLK>;
+ qcom,use-sw-aes-cbc-ecb-ctr-algo;
+ qcom,use-sw-aes-xts-algo;
+ qcom,use-sw-aes-ccm-algo;
+ qcom,use-sw-ahash-algo;
+ qcom,use-sw-aead-algo;
+ qcom,use-sw-hmac-algo;
+ qcom,smmu-s1-enable;
+ iommus = <&apps_smmu 0x0084 0x0011>,
+ <&apps_smmu 0x0094 0x0011>;
+ qcom,iommu-dma = "atomic";
+ };
+
+ qcom,mpm2-sleep-counter@4403000 {
+ compatible = "qcom,mpm2-sleep-counter";
+ reg = <0x4403000 0x1000>;
+ clock-frequency = <32768>;
+ };
+
+ qcom,msm-rtb {
+ compatible = "qcom,msm-rtb";
+ qcom,rtb-size = <0x100000>;
+ };
+
+ cpu_pmu: cpu-pmu {
+ compatible = "arm,armv8-pmuv3";
+ qcom,irq-is-percpu;
+ interrupts = <1 6 4>;
+ };
+
+ eud: qcom,msm-eud@1610000 {
+ compatible = "qcom,msm-eud";
+ interrupt-names = "eud_irq";
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x1610000 0x2000>,
+ <0x1612000 0x1000>,
+ <0x3E5018 0x4>;
+ reg-names = "eud_base", "eud_mode_mgr2",
+ "eud_tcsr_check_reg";
+ qcom,secure-eud-en;
+ qcom,eud-tcsr-check-enable;
+ qcom,eud-clock-vote-req;
+ clocks = <&gcc GCC_AHB2PHY_USB_CLK>;
+ clock-names = "eud_ahb2phy_clk";
+ status = "ok";
+ };
+
+ qcom,msm-gladiator-v2@f100000 {
+ compatible = "qcom,msm-gladiator-v2";
+ reg = <0xf100000 0xdc00>;
+ reg-names = "gladiator_base";
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "atb_clk";
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ };
+
+ wdog: qcom,wdt@f017000 {
+ compatible = "qcom,msm-watchdog";
+ reg = <0xf017000 0x1000>;
+ reg-names = "wdt-base";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bark-time = <11000>;
+ qcom,pet-time = <9360>;
+ qcom,ipi-ping;
+ qcom,wakeup-enable;
+ };
+
+ rpm_bus: qcom,rpm-smd {
+ compatible = "qcom,rpm-smd";
+ rpm-channel-name = "rpm_requests";
+ interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+ rpm-channel-type = <15>; /* SMD_APPS_RPM */
+ };
+
+ qcom,chd_silver {
+ compatible = "qcom,core-hang-detect";
+ label = "silver";
+ qcom,threshold-arr = <0x0f1880b0 0x0f1980b0
+ 0x0f1a80b0 0x0f1b80b0>;
+ qcom,config-arr = <0x0f1880b8 0x0f1980b8
+ 0x0f1a80b8 0x0f1b80b8>;
+ };
+
+ qcom,chd_gold {
+ compatible = "qcom,core-hang-detect";
+ label = "gold";
+ qcom,threshold-arr = <0x0f0880b0 0x0f0980b0
+ 0x0f0a80b0 0x0f0b80b0>;
+ qcom,config-arr = <0x0f0880b8 0x0f0980b8
+ 0x0f0a80b8 0x0f0b80b8>;
+ };
+
+ qcom,ghd {
+ compatible = "qcom,gladiator-hang-detect";
+ qcom,threshold-arr = <0x0f1d141c 0x0f1d1420
+ 0x0f1d1424 0x0f1d1428
+ 0x0f1d142c 0x0f1d1430>;
+ qcom,config-reg = <0x0f1d1434>;
+ };
+
+ qcom,lpass@ab00000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0xab00000 0x00100>;
+
+ vdd_lpi_cx-supply = <&L3A_LEVEL>;
+ qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx";
+ qcom,vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ vdd_lpi_mx-supply = <&L2A_LEVEL>;
+ qcom,vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+
+ clocks = <&rpmcc CXO_SMD_PIL_LPASS_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+ qcom,mas-crypto = <&mas_crypto_c0>;
+
+ qcom,pas-id = <1>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <423>;
+ qcom,minidump-id = <5>;
+ qcom,sysmon-id = <1>;
+ qcom,ssctl-instance-id = <0x14>;
+ qcom,firmware-name = "adsp";
+ memory-region = <&pil_adsp_mem>;
+ qcom,complete-ramdump;
+ qcom,minidump-as-elf32;
+
+ /* Inputs from lpass */
+ interrupts-extended = <&intc 0 282 1>,
+ <&adsp_smp2p_in 0 0>,
+ <&adsp_smp2p_in 2 0>,
+ <&adsp_smp2p_in 1 0>,
+ <&adsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack";
+
+ /* Outputs to lpass */
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+ };
+
+ qcom,turing@b300000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0xb300000 0x100000>;
+
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,proxy-reg-names = "vdd_cx";
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+
+ clocks = <&rpmcc CXO_SMD_PIL_CDSP_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+ qcom,mas-crypto = <&mas_crypto_c0>;
+
+ qcom,pas-id = <18>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <601>;
+ qcom,minidump-id = <7>;
+ qcom,sysmon-id = <7>;
+ qcom,ssctl-instance-id = <0x17>;
+ qcom,firmware-name = "cdsp";
+ memory-region = <&pil_cdsp_mem>;
+ qcom,complete-ramdump;
+ qcom,minidump-as-elf32;
+
+ /* Inputs from turing */
+ interrupts-extended = <&intc 0 265 1>,
+ <&cdsp_smp2p_in 0 0>,
+ <&cdsp_smp2p_in 2 0>,
+ <&cdsp_smp2p_in 1 0>,
+ <&cdsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack";
+
+ /* Outputs to turing */
+ qcom,smem-states = <&cdsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+ };
+
+ mem_dump {
+ compatible = "qcom,mem-dump";
+ memory-region = <&dump_mem>;
+
+ c0_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x0>;
+ };
+
+ c1_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x1>;
+ };
+
+ c2_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x2>;
+ };
+
+ c3_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x3>;
+ };
+
+ c100_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x4>;
+ };
+
+ c101_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x5>;
+ };
+
+ c102_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x6>;
+ };
+
+ c103_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x7>;
+ };
+
+ c_scandump {
+ qcom,dump-size = <0x40000>;
+ qcom,dump-id = <0xeb>;
+ };
+
+ l1_icache0 {
+ qcom,dump-size = <0x8900>;
+ qcom,dump-id = <0x60>;
+ };
+
+ l1_icache1 {
+ qcom,dump-size = <0x8900>;
+ qcom,dump-id = <0x61>;
+ };
+
+ l1_icache2 {
+ qcom,dump-size = <0x8900>;
+ qcom,dump-id = <0x62>;
+ };
+
+ l1_icache3 {
+ qcom,dump-size = <0x8900>;
+ qcom,dump-id = <0x63>;
+ };
+
+ l1_icache100 {
+ qcom,dump-size = <0x11100>;
+ qcom,dump-id = <0x64>;
+ };
+
+ l1_icache101 {
+ qcom,dump-size = <0x11100>;
+ qcom,dump-id = <0x65>;
+ };
+
+ l1_icache102 {
+ qcom,dump-size = <0x11100>;
+ qcom,dump-id = <0x66>;
+ };
+
+ l1_icache103 {
+ qcom,dump-size = <0x11100>;
+ qcom,dump-id = <0x67>;
+ };
+
+ l1_dcache0 {
+ qcom,dump-size = <0x9100>;
+ qcom,dump-id = <0x80>;
+ };
+
+ l1_dcache1 {
+ qcom,dump-size = <0x9100>;
+ qcom,dump-id = <0x81>;
+ };
+
+ l1_dcache2 {
+ qcom,dump-size = <0x9100>;
+ qcom,dump-id = <0x82>;
+ };
+
+ l1_dcache3 {
+ qcom,dump-size = <0x9100>;
+ qcom,dump-id = <0x83>;
+ };
+
+ l1_dcache100 {
+ qcom,dump-size = <0x12100>;
+ qcom,dump-id = <0x84>;
+ };
+
+ l1_dcache101 {
+ qcom,dump-size = <0x12100>;
+ qcom,dump-id = <0x85>;
+ };
+
+ l1_dcache102 {
+ qcom,dump-size = <0x12100>;
+ qcom,dump-id = <0x86>;
+ };
+
+ l1_dcache103 {
+ qcom,dump-size = <0x12100>;
+ qcom,dump-id = <0x87>;
+ };
+
+ l2_tlb0 {
+ qcom,dump-size = <0x2100>;
+ qcom,dump-id = <0x120>;
+ };
+
+ l2_tlb1 {
+ qcom,dump-size = <0x2100>;
+ qcom,dump-id = <0x121>;
+ };
+
+ l2_tlb2 {
+ qcom,dump-size = <0x2100>;
+ qcom,dump-id = <0x122>;
+ };
+
+ l2_tlb3 {
+ qcom,dump-size = <0x2100>;
+ qcom,dump-id = <0x123>;
+ };
+
+ l2_tlb100 {
+ qcom,dump-size = <0x4900>;
+ qcom,dump-id = <0x124>;
+ };
+
+ l2_tlb101 {
+ qcom,dump-size = <0x4900>;
+ qcom,dump-id = <0x125>;
+ };
+
+ l2_tlb102 {
+ qcom,dump-size = <0x4900>;
+ qcom,dump-id = <0x126>;
+ };
+
+ l2_tlb103 {
+ qcom,dump-size = <0x4900>;
+ qcom,dump-id = <0x127>;
+ };
+
+ rpm_sw {
+ qcom,dump-size = <0x28000>;
+ qcom,dump-id = <0xea>;
+ };
+
+ pmic {
+ qcom,dump-size = <0x40000>;
+ qcom,dump-id = <0xe4>;
+ };
+
+ fcm {
+ qcom,dump-size = <0x8400>;
+ qcom,dump-id = <0xee>;
+ };
+
+ tmc_etf {
+ qcom,dump-size = <0x8000>;
+ qcom,dump-id = <0xf0>;
+ };
+
+ etr_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x100>;
+ };
+
+ etf_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x101>;
+ };
+
+ misc_data {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xe8>;
+ };
+ };
+
+ sdhc_1: sdhci@4744000 {
+ compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe";
+ reg = <0x4744000 0x1000>, <0x4745000 0x1000>,
+ <0x4748000 0x8000>;
+ reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";
+
+ interrupts-extended = <&intc GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 19 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "hc_irq", "pwr_irq", "tb_trig_irq";
+
+ qcom,bus-width = <8>;
+ qcom,large-address-bus;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
+ 192000000 384000000>;
+ qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+
+ qcom,devfreq,freq-table = <50000000 200000000>;
+
+ qcom,scaling-lower-bus-speed-mode = "DDR52";
+
+ qcom,msm-bus,name = "sdhc1";
+ qcom,msm-bus,num-cases = <9>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <78 512 0 0>, <1 606 0 0>,
+ /* 400 KB/s*/
+ <78 512 1046 1600>,
+ <1 606 1600 1600>,
+ /* 20 MB/s */
+ <78 512 20480 80000>,
+ <1 606 80000 80000>,
+ /* 25 MB/s */
+ <78 512 25600 250000>,
+ <1 606 50000 133320>,
+ /* 50 MB/s */
+ <78 512 51200 250000>,
+ <1 606 65000 133320>,
+ /* 100 MB/s */
+ <78 512 102400 250000>,
+ <1 606 65000 133320>,
+ /* 200 MB/s */
+ <78 512 204800 800000>,
+ <1 606 200000 300000>,
+ /* 400 MB/s */
+ <78 512 204800 800000>,
+ <1 606 200000 300000>,
+ /* Max. bandwidth */
+ <78 512 1338562 4096000>,
+ <1 606 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100750000 200000000 400000000 4294967295>;
+
+ /* PM QoS */
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <26 26>;
+ qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
+ qcom,pm-qos-cmdq-latency-us = <26 26>, <26 26>;
+ qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>;
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface_clk", "core_clk", "ice_core_clk";
+
+ qcom,ice-clk-rates = <300000000 100000000>;
+
+ /* Add support for gcc hw reset */
+ resets = <&gcc GCC_SDCC1_BCR>;
+ reset-names = "core_reset";
+
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2C010800 0x80040868>;
+ qcom,nonremovable;
+ status = "disabled";
+ };
+
+ sdhc_2: sdhci@4784000 {
+ compatible = "qcom,sdhci-msm-v5";
+ reg = <0x4784000 0x1000>;
+ reg-names = "hc_mem";
+
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <4>;
+ qcom,large-address-bus;
+
+ qcom,clk-rates = <400000 20000000 25000000
+ 50000000 100000000 202000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
+ "SDR104";
+
+ qcom,devfreq,freq-table = <50000000 202000000>;
+
+ qcom,msm-bus,name = "sdhc2";
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <81 512 0 0>, <1 608 0 0>,
+ /* 400 KB/s*/
+ <81 512 1046 3200>,
+ <1 608 1600 1600>,
+ /* 20 MB/s */
+ <81 512 52286 250000>,
+ <1 608 80000 133320>,
+ /* 25 MB/s */
+ <81 512 65360 250000>,
+ <1 608 100000 133320>,
+ /* 50 MB/s */
+ <81 512 130718 250000>,
+ <1 608 133320 133320>,
+ /* 100 MB/s */
+ <81 512 261438 250000>,
+ <1 608 150000 133320>,
+ /* 200 MB/s */
+ <81 512 261438 800000>,
+ <1 608 300000 300000>,
+ /* Max. bandwidth */
+ <81 512 1338562 4096000>,
+ <1 608 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100750000 200000000 4294967295>;
+
+ /* PM QoS */
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <26 26>;
+ qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
+ qcom,pm-qos-legacy-latency-us = <26 26>, <26 26>;
+
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>;
+ clock-names = "iface_clk", "core_clk";
+
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>;
+ qcom,vbias-skip-wa;
+
+ status = "disabled";
+ };
+
+ ufsphy_mem: ufsphy_mem@4807000 {
+ reg = <0x4807000 0xe00>; /* PHY regs */
+ reg-names = "phy_mem";
+ #phy-cells = <0>;
+
+ lanes-per-direction = <2>;
+
+ clock-names = "ref_clk_src",
+ "ref_clk",
+ "ref_aux_clk";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_UFS_CLKREF_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+ status = "disabled";
+ };
+
+ ufshc_mem: ufshc@4804000 {
+ compatible = "qcom,ufshc";
+ reg = <0x4804000 0x3000>, <0x4810000 0x8000>;
+ reg-names = "ufs_mem", "ufs_ice";
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufsphy_mem>;
+ phy-names = "ufsphy";
+
+ lanes-per-direction = <2>;
+ dev-ref-clk-freq = <0>; /* 19.2 MHz */
+ spm-level = <5>;
+
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "core_clk_ice",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ clocks =
+ <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ freq-table-hz =
+ <50000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <37500000 150000000>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ qcom,msm-bus,name = "ufshc_mem";
+ qcom,msm-bus,num-cases = <22>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /*
+ * During HS G3 UFS runs at nominal voltage corner, vote
+ * higher bandwidth to push other buses in the data path
+ * to run at nominal to achieve max throughput.
+ * 4GBps pushes BIMC to run at nominal.
+ * 200MBps pushes CNOC to run at nominal.
+ * Vote for half of this bandwidth for HS G3 1-lane.
+ * For max bandwidth, vote high enough to push the buses
+ * to run in turbo voltage corner.
+ */
+ <123 512 0 0>, <1 757 0 0>, /* No vote */
+ <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */
+ <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */
+ <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */
+ <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */
+ <123 512 1844 0>, <1 757 1000 0>, /* PWM G1 L2 */
+ <123 512 3688 0>, <1 757 1000 0>, /* PWM G2 L2 */
+ <123 512 7376 0>, <1 757 1000 0>, /* PWM G3 L2 */
+ <123 512 14752 0>, <1 757 1000 0>, /* PWM G4 L2 */
+ <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */
+ <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */
+ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */
+ <123 512 255591 0>, <1 757 1000 0>, /* HS G1 RA L2 */
+ <123 512 511181 0>, <1 757 1000 0>, /* HS G2 RA L2 */
+ <123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */
+ <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */
+ <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */
+ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */
+ <123 512 298189 0>, <1 757 1000 0>, /* HS G1 RB L2 */
+ <123 512 596378 0>, <1 757 1000 0>, /* HS G2 RB L2 */
+ /* As UFS working in HS G3 RB L2 mode, aggregated
+ * bandwidth (AB) should take care of providing
+ * optimum throughput requested. However, as tested,
+ * in order to scale up CNOC clock, instantaneous
+ * bindwidth (IB) needs to be given a proper value too.
+ */
+ <123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */
+ <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
+
+ qcom,bus-vector-names = "MIN",
+ "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
+ "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
+ "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
+ "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",
+ "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
+ "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",
+ "MAX";
+
+ /* PM QoS */
+ qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
+ qcom,pm-qos-cpu-group-latency-us = <26 26>;
+ qcom,pm-qos-default-cpu = <0>;
+
+ pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
+ pinctrl-0 = <&ufs_dev_reset_assert>;
+ pinctrl-1 = <&ufs_dev_reset_deassert>;
+
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "core_reset";
+ non-removable;
+
+ status = "disabled";
+ };
+
+ thermal_zones: thermal-zones {};
+
+ tsens0:tsens@c222000 {
+ compatible = "qcom,tsens24xx";
+ reg = <0x04410000 0x8>,
+ <0x04411000 0x1ff>;
+ reg-names = "tsens_srot_physical",
+ "tsens_tm_physical";
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tsens-upper-lower", "tsens-critical";
+ tsens-reinit-wa;
+ #thermal-sensor-cells = <1>;
+ };
+
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ clock-output-names = "xo_board";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ clock-output-names = "sleep_clk";
+ #clock-cells = <0>;
+ };
+
+ usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <1000>;
+ clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
+ #clock-cells = <0>;
+ };
+ };
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-bengal";
+ #clock-cells = <1>;
+ };
+
+ qcom,rmtfs_sharedmem@0 {
+ compatible = "qcom,sharedmem-uio";
+ reg = <0x0 0x200000>;
+ reg-names = "rmtfs";
+ qcom,client-id = <0x00000001>;
+ qcom,guard-memory;
+ qcom,vm-nav-path;
+ };
+
+ gcc: clock-controller@1400000 {
+ compatible = "qcom,khaje-gcc", "syscon";
+ reg = <0x1400000 0x1f0000>;
+ reg-names = "cc_base";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ dispcc: clock-controller@5f00000 {
+ compatible = "qcom,khaje-dispcc", "syscon";
+ reg = <0x05f00000 0x20000>;
+ reg-names = "cc_base";
+ clock-names = "cfg_ahb_clk";
+ clocks = <&gcc GCC_DISP_AHB_CLK>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gpucc: clock-controller@5990000 {
+ compatible = "qcom,khaje-gpucc", "syscon";
+ reg = <0x5990000 0x9000>;
+ reg-names = "cc_base";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mccc_debug: syscon@447d200 {
+ compatible = "syscon";
+ reg = <0x447d200 0x100>;
+ };
+
+ cpucc_debug: syscon@f11101c {
+ compatible = "syscon";
+ reg = <0xf11101c 0x4>;
+ };
+
+ debugcc: clock-controller@0 {
+ compatible = "qcom,khaje-debugcc";
+ qcom,gcc = <&gcc>;
+ qcom,dispcc = <&dispcc>;
+ qcom,gpucc = <&gpucc>;
+ qcom,mccc = <&mccc_debug>;
+ qcom,cpucc = <&cpucc_debug>;
+ clock-names = "xo_clk_src";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ #clock-cells = <1>;
+ };
+
+ cpufreq_hw: qcom,cpufreq-hw {
+ compatible = "qcom,cpufreq-hw";
+ reg = <0xf521000 0x1000>, <0xf523000 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+ qcom,no-accumulative-counter;
+ qcom,max-lut-entries = <12>;
+ #freq-domain-cells = <2>;
+ };
+
+ qcom,cpufreq-hw-debug@0f521000 {
+ compatible = "qcom,cpufreq-hw-debug";
+ reg = <0x0f521000 0x800>;
+ reg-names = "domain-top";
+ qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;
+ };
+
+ tcsr_mutex_block: syscon@00340000 {
+ compatible = "syscon";
+ reg = <0x340000 0x20000>;
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_block 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ smem: qcom,smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ rpm_msg_ram: memory@045f0000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x45f0000 0x7000>;
+ };
+
+ apcs_glb: mailbox@0f111000 {
+ compatible = "qcom,bengal-apcs-hmss-global";
+ reg = <0xF111000 0x1000>;
+
+ #mbox-cells = <1>;
+ };
+
+ qcom,msm-cdsp-loader {
+ compatible = "qcom,cdsp-loader";
+ qcom,proc-img-to-load = "cdsp";
+ };
+
+ qcom,msm-adsprpc-mem {
+ compatible = "qcom,msm-adsprpc-mem-region";
+ memory-region = <&adsp_mem>;
+ restrict-access;
+ };
+
+ qcom,msm_fastrpc {
+ compatible = "qcom,msm-fastrpc-compute";
+ qcom,rpc-latency-us = <611>;
+ qcom,adsp-remoteheap-vmid = <22 37>;
+ qcom,fastrpc-adsp-audio-pdr;
+ qcom,fastrpc-adsp-sensors-pdr;
+
+ qcom,msm_fastrpc_compute_cb1 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x0C01 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb2 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x0C02 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb3 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x0C03 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb4 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x0C04 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb5 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x0C05 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb6 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x0C06 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb9 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ qcom,secure-context-bank;
+ iommus = <&apps_smmu 0x0C09 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb10 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C3 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb11 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C4 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb12 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C5 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb13 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C6 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb14 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C7 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ };
+
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ qcom,rpm_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_adsp>,
+ <&glink_cdsp>;
+ };
+
+ };
+
+ qcom,glink {
+ compatible = "qcom,glink";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ glink_modem: modem {
+ qcom,remote-pid = <1>;
+ transport = "smem";
+ mboxes = <&apcs_glb 12>;
+ mbox-names = "mpss_smem";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
+
+ label = "modem";
+ qcom,glink-label = "mpss";
+
+ qcom,modem_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,low-latency;
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,modem_ds {
+ qcom,glink-channels = "DS";
+ qcom,intents = <0x4000 2>;
+ };
+
+ qcom,modem_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_adsp>,
+ <&glink_cdsp>;
+ };
+ };
+
+ glink_adsp: adsp {
+ qcom,remote-pid = <2>;
+ transport = "smem";
+ mboxes = <&apcs_glb 8>;
+ mbox-names = "adsp_smem";
+ interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
+
+ label = "adsp";
+ qcom,glink-label = "lpass";
+
+ qcom,adsp_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,low-latency;
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,apr_tal_rpmsg {
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,intents = <0x200 20>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,adsp_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_cdsp>;
+ };
+ };
+
+ glink_cdsp: cdsp {
+ qcom,remote-pid = <5>;
+ transport = "smem";
+ mboxes = <&apcs_glb 28>;
+ mbox-names = "cdsp_smem";
+ interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>;
+
+ label = "cdsp";
+ qcom,glink-label = "cdsp";
+
+ qcom,cdsp_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,msm_cdsprm_rpmsg {
+ compatible = "qcom,msm-cdsprm-rpmsg";
+ qcom,glink-channels = "cdsprmglink-apps-dsp";
+ qcom,intents = <0x20 12>;
+
+ msm_cdsp_rm: qcom,msm_cdsp_rm {
+ compatible = "qcom,msm-cdsp-rm";
+ qcom,qos-latency-us = <100>;
+ qcom,qos-maxhold-ms = <20>;
+ };
+ };
+
+ qcom,cdsp_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_adsp>;
+ };
+ };
+ };
+
+ qcom,glinkpkt {
+ compatible = "qcom,glinkpkt";
+
+ qcom,glinkpkt-at-mdm0 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DS";
+ qcom,glinkpkt-dev-name = "at_mdm0";
+ };
+
+ qcom,glinkpkt-apr-apps2 {
+ qcom,glinkpkt-edge = "adsp";
+ qcom,glinkpkt-ch-name = "apr_apps2";
+ qcom,glinkpkt-dev-name = "apr_apps2";
+ };
+
+ qcom,glinkpkt-data40-cntl {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA40_CNTL";
+ qcom,glinkpkt-dev-name = "smdcntl8";
+ };
+
+ qcom,glinkpkt-data1 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA1";
+ qcom,glinkpkt-dev-name = "smd7";
+ };
+
+ qcom,glinkpkt-data4 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA4";
+ qcom,glinkpkt-dev-name = "smd8";
+ };
+
+ qcom,glinkpkt-data11 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA11";
+ qcom,glinkpkt-dev-name = "smd11";
+ };
+ };
+
+ qcom,smp2p_sleepstate {
+ compatible = "qcom,smp2p-sleepstate";
+ qcom,smem-states = <&sleepstate_smp2p_out 0>;
+ interrupt-parent = <&sleepstate_smp2p_in>;
+ interrupts = <0 0>;
+ interrupt-names = "smp2p-sleepstate-in";
+ };
+
+ qcom,smp2p-modem {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 14>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ /* ipa - inbound entry from mss */
+ smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
+ qcom,entry-name = "wlan";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ };
+
+ qcom,smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 10>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
+ qcom,entry-name = "rdbg";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
+ qcom,entry-name = "rdbg";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sleepstate_smp2p_out: sleepstate-out {
+ qcom,entry-name = "sleepstate";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ sleepstate_smp2p_in: qcom,sleepstate-in {
+ qcom,entry-name = "sleepstate_see";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 30>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
+ qcom,entry-name = "rdbg";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
+ qcom,entry-name = "rdbg";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,sps {
+ compatible = "qcom,msm-sps-4k";
+ qcom,pipe-attr-ee;
+ };
+
+ qfprom: qfprom@1b40000 {
+ compatible = "qcom,qfprom";
+ reg = <0x1b40000 0x7000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ read-only;
+ ranges;
+
+ stm_debug_fuse: stm@20f0 {
+ reg = <0x20f0 0x4>;
+ };
+
+ feat_conf5: feat_conf5@6018 {
+ reg = <0x6018 0x4>;
+ };
+
+ feat_conf10: feat_conf10@602c {
+ reg = <0x602c 0x4>;
+ };
+
+ adsp_variant: adsp_variant@6011 {
+ reg = <0x6011 0x1>;
+ bits = <3 1>;
+ };
+
+ gpu_speed_bin: gpu_speed_bin@6006 {
+ reg = <0x6006 0x2>;
+ bits = <5 8>;
+ };
+
+ gpu_gaming_bin: gpu_gaming_bin@602d {
+ reg = <0x602d 0x1>;
+ bits = <5 1>;
+ };
+
+ feat_conf11: feat_conf11@6030 {
+ reg = <0x6030 0x1>;
+ bits = <0 8>;
+ };
+ };
+
+ spmi_bus: qcom,spmi@1c40000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x1c40000 0x1100>,
+ <0x1e00000 0x2000000>,
+ <0x3e00000 0x100000>,
+ <0x3f00000 0xa0000>,
+ <0x1c0a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
+ icnss: qcom,icnss@C800000 {
+ compatible = "qcom,icnss";
+ reg = <0xC800000 0x800000>,
+ <0xb0000000 0x10000>;
+ reg-names = "membase", "smmu_iova_ipa";
+ iommus = <&apps_smmu 0x1A0 0x1>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
+ <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
+ <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
+ <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH /* CE10 */ >,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH /* CE11 */ >;
+ qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
+ qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
+ qcom,iommu-dma = "fastmap";
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ qcom,iommu-geometry = <0xa0000000 0x10010000>;
+ vdd-cx-mx-supply = <&L8A>;
+ vdd-1.8-xo-supply = <&L16A>;
+ vdd-1.3-rfa-supply = <&L17A>;
+ vdd-3.3-ch0-supply = <&L23A>;
+ qcom,vdd-cx-mx-config = <640000 640000>;
+ qcom,vdd-3.3-ch0-config = <3000000 3312000>;
+ qcom,smp2p_map_wlan_1_in {
+ interrupts-extended = <&smp2p_wlan_1_in 0 0>,
+ <&smp2p_wlan_1_in 1 0>;
+ interrupt-names = "qcom,smp2p-force-fatal-error",
+ "qcom,smp2p-early-crash-ind";
+ };
+ };
+
+ qcom,venus@5ab0000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x5ab0000 0x20000>;
+
+ vdd-supply = <&gcc_venus_gdsc>;
+ qcom,proxy-reg-names = "vdd";
+
+ clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>,
+ <&gcc GCC_VENUS_CTL_AXI_CLK>,
+ <&gcc GCC_VIDEO_AHB_CLK>,
+ <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>;
+ clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk";
+ qcom,proxy-clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk";
+ qcom,mas-crypto = <&mas_crypto_c0>;
+
+ qcom,core-freq = <240000000>;
+ qcom,ahb-freq = <240000000>;
+
+ qcom,pas-id = <9>;
+ qcom,msm-bus,name = "pil-venus";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <63 512 0 0>,
+ <63 512 0 304000>;
+ qcom,proxy-timeout-ms = <100>;
+ qcom,firmware-name = "venus";
+ memory-region = <&pil_video_mem>;
+ };
+
+ cx_ipeak_lm: cx_ipeak@3ed000 {
+ compatible = "qcom,cx-ipeak-v2";
+ reg = <0x3ed000 0xe008>;
+ };
+
+ pil_modem: qcom,mss@6080000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x6080000 0x100>;
+
+ clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+ qcom,mas-crypto = <&mas_crypto_c0>;
+
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+ qcom,proxy-reg-names = "vdd_cx";
+
+ qcom,firmware-name = "modem";
+ memory-region = <&pil_modem_mem>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,sysmon-id = <0>;
+ qcom,ssctl-instance-id = <0x12>;
+ qcom,pas-id = <4>;
+ qcom,smem-id = <421>;
+ qcom,minidump-id = <3>;
+ qcom,aux-minidump-ids = <4>;
+ qcom,complete-ramdump;
+ qcom,sequential-fw-load;
+
+ qcom,msm-bus,name = "pil-modem";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0 0 8171520>;
+
+ /* Inputs from mss */
+ interrupts-extended = <&intc 0 307 1>,
+ <&modem_smp2p_in 0 0>,
+ <&modem_smp2p_in 2 0>,
+ <&modem_smp2p_in 1 0>,
+ <&modem_smp2p_in 3 0>,
+ <&modem_smp2p_in 7 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack",
+ "qcom,shutdown-ack";
+
+ /* Outputs to mss */
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+ };
+
+ ddr_bw_opp_table: ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY_DDR( 200, 8, 0x80); /* 1525 MB/s */
+ BW_OPP_ENTRY_DDR( 547, 8, 0x80); /* 4173 MB/s */
+ BW_OPP_ENTRY_DDR( 768, 8, 0x80); /* 5859 MB/s */
+ BW_OPP_ENTRY_DDR(1017, 8, 0x80); /* 7759 MB/s */
+ BW_OPP_ENTRY_DDR(1555, 8, 0x80); /*11863 MB/s */
+ BW_OPP_ENTRY_DDR(1804, 8, 0x80); /*13763 MB/s */
+ BW_OPP_ENTRY_DDR(2092, 8, 0x80); /*15960 MB/s */
+ };
+
+ suspendable_ddr4_bw_opp_table: suspendable-ddr4-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY_DDR( 0, 8, 0x80); /* 0 MB/s */
+ BW_OPP_ENTRY_DDR( 200, 8, 0x80); /* 1525 MB/s */
+ BW_OPP_ENTRY_DDR( 547, 8, 0x80); /* 4173 MB/s */
+ BW_OPP_ENTRY_DDR( 768, 8, 0x80); /* 5859 MB/s */
+ BW_OPP_ENTRY_DDR(1017, 8, 0x80); /* 7759 MB/s */
+ BW_OPP_ENTRY_DDR(1555, 8, 0x80); /*11863 MB/s */
+ BW_OPP_ENTRY_DDR(1804, 8, 0x80); /*13763 MB/s */
+ BW_OPP_ENTRY_DDR(2092, 8, 0x80); /*15960 MB/s */
+ };
+
+ cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@01b8e200 {
+ compatible = "qcom,bimc-bwmon4";
+ reg = <0x01b8e300 0x100>, <0x01b8e200 0x100>;
+ reg-names = "base", "global_base";
+ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&cpu_cpu_ddr_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,target-dev = <&cpu0_cpu_ddr_lat>;
+ qcom,cachemiss-ev = <0x17>;
+ qcom,stall-cycle-ev = <0xE7>;
+ qcom,core-dev-table =
+ < 1190400 MHZ_TO_MBPS( 547, 8) >,
+ < 1516800 MHZ_TO_MBPS( 768, 8) >,
+ < 1804800 MHZ_TO_MBPS(1017, 8) >;
+ };
+
+ cpu0_computemon: qcom,cpu0-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 1190400 MHZ_TO_MBPS( 547, 8) >,
+ < 1516800 MHZ_TO_MBPS( 768, 8) >,
+ < 1804800 MHZ_TO_MBPS(1017, 8) >;
+ };
+ };
+
+ cpu4_cpu_ddr_lat: qcom,cpu4-cpu-ddr-lat {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+
+ cpu4_cpu_ddr_latmon: qcom,cpu4-cpu-ddr-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+ qcom,target-dev = <&cpu4_cpu_ddr_lat>;
+ qcom,cachemiss-ev = <0x17>;
+ qcom,stall-cycle-ev = <0x24>;
+ qcom,core-dev-table =
+ < 1056000 MHZ_TO_MBPS( 547, 8) >,
+ < 1344000 MHZ_TO_MBPS(1017, 8) >,
+ < 1766400 MHZ_TO_MBPS(1555, 8) >,
+ < 2208000 MHZ_TO_MBPS(1804, 8) >,
+ < 2803200 MHZ_TO_MBPS(2092, 8) >;
+ };
+
+ cpu4_computemon: qcom,cpu4-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+ qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 1056000 MHZ_TO_MBPS( 547, 8) >,
+ < 1344000 MHZ_TO_MBPS( 768, 8) >,
+ < 1766400 MHZ_TO_MBPS(1017, 8) >,
+ < 2208000 MHZ_TO_MBPS(1804, 8) >,
+ < 2803200 MHZ_TO_MBPS(2092, 8) >;
+ };
+ };
+
+ qcom,msm_gsi {
+ compatible = "qcom,msm_gsi";
+ };
+
+ qcom,rmnet-ipa {
+ compatible = "qcom,rmnet-ipa3";
+ qcom,rmnet-ipa-ssr;
+ qcom,ipa-platform-type-msm;
+ qcom,ipa-advertise-sg-support;
+ qcom,ipa-napi-enable;
+ };
+
+ ipa_hw: qcom,ipa@0x5800000 {
+ compatible = "qcom,ipa";
+ reg = <0x5800000 0x34000>,
+ <0x5804000 0x28000>;
+ reg-names = "ipa-base", "gsi-base";
+ interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ipa-irq", "gsi-irq";
+ qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */
+ qcom,ipa-hw-mode = <0>;
+ qcom,platform-type = <1>; /* MSM platform */
+ qcom,ee = <0>;
+ qcom,use-ipa-tethering-bridge;
+ qcom,modem-cfg-emb-pipe-flt;
+ qcom,ipa-wdi2;
+ qcom,ipa-wdi2_over_gsi;
+ qcom,ipa-endp-delay-wa;
+ qcom,ipa-fltrt-not-hashable;
+ qcom,use-64-bit-dma-mask;
+ qcom,arm-smmu;
+ qcom,smmu-fast-map;
+ qcom,use-ipa-pm;
+ qcom,skip-ieob-mask-wa;
+ clocks = <&rpmcc RPM_SMD_IPA_CLK>;
+ clock-names = "core_clk";
+ qcom,msm-bus,name = "ipa";
+ qcom,msm-bus,num-cases = <5>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+ /* SVS2 */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 465000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 68570>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 30>,
+ /* SVS */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 2000000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 267461>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 109890>,
+ /* NOMINAL */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 4000000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 712961>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 491520>,
+ /* TURBO */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 5598900>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 1436481>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 491520>;
+ qcom,bus-vector-names =
+ "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
+ qcom,throughput-threshold = <310 600 1000>;
+ qcom,scaling-exceptions = <>;
+
+ /* smp2p information */
+ qcom,smp2p_map_ipa_1_out {
+ compatible = "qcom,smp2p-map-ipa-1-out";
+ qcom,smem-states = <&smp2p_ipa_1_out 0>;
+ qcom,smem-state-names = "ipa-smp2p-out";
+ };
+
+ qcom,smp2p_map_ipa_1_in {
+ compatible = "qcom,smp2p-map-ipa-1-in";
+ interrupts-extended = <&smp2p_ipa_1_in 0 0>;
+ interrupt-names = "ipa-smp2p-in";
+ };
+ };
+
+ ipa_smmu_ap: ipa_smmu_ap {
+ compatible = "qcom,ipa-smmu-ap-cb";
+ iommus = <&apps_smmu 0x0140 0x0>;
+ qcom,iommu-dma-addr-pool = <0x10000000 0x30000000>;
+ /* modem tables in IMEM */
+ qcom,iommu-dma = "fastmap";
+ qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>;
+ qcom,iommu-geometry = <0 0xB0000000>;
+ };
+
+ ipa_smmu_wlan: ipa_smmu_wlan {
+ compatible = "qcom,ipa-smmu-wlan-cb";
+ iommus = <&apps_smmu 0x0141 0x0>;
+ /* ipa-uc ram */
+ qcom,iommu-dma = "atomic";
+ };
+
+ ipa_smmu_uc: ipa_smmu_uc {
+ compatible = "qcom,ipa-smmu-uc-cb";
+ iommus = <&apps_smmu 0x0142 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40400000 0x1fc00000>;
+ };
+
+ qcom,ipa_fws {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <0xf>;
+ qcom,firmware-name = "ipa_fws";
+ qcom,pil-force-shutdown;
+ memory-region = <&pil_ipa_fw_mem>;
+ };
+
+ qcom,demux {
+ compatible = "qcom,demux";
+ };
+
+tpdm_turing_llm: tpdm@8861000 {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-tpdm-turing_llm";
+ qcom,dummy-source;
+
+ port {
+ tpdm_turing_llm_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_tpdm_turing_llm>;
+ };
+ };
+ };
+
+ /delete-node/ tpdm@8a58000;
+ tpdm_west: tpdm@8a58000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8a58000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-west";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_west_out_tpda11: endpoint {
+ remote-endpoint =
+ <&tpda11_in_tpdm_west>;
+ };
+ };
+ };
+
+ tpdm_spdm: tpdm@800f000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x0800f000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-spdm";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_spdm_out_tpda13: endpoint {
+ remote-endpoint =
+ <&tpda13_in_tpdm_spdm>;
+ };
+ };
+ };
+
+ /delete-node/ funnel@8861000;
+ funnel_turing: funnel@8863000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x8863000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-turing";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_turing_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_funnel_turing>;
+ source = <&turing_etm0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_turing_out_tpda5: endpoint {
+ remote-endpoint =
+ <&tpda5_in_funnel_turing>;
+ };
+ };
+
+ port@2 {
+ reg = <0>;
+ funnel_turing_in_tpdm_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_turing_out_funnel_turing>;
+ };
+ };
+
+ port@3 {
+ reg = <1>;
+ funnel_turing_in_tpdm_turing_llm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_turing_llm_out_funnel_turing>;
+ };
+ };
+
+ port@4 {
+ reg = <2>;
+ funnel_turing_in_turing_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&turing_etm0_out_funnel_turing>;
+ };
+ };
+ };
+ };
+
+ /delete-node/ tpda@8004000;
+ tpda: tpda@8004000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x8004000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda";
+
+ qcom,tpda-atid = <65>;
+ qcom,dsb-elem-size = <0 32>,
+ <1 32>,
+ <5 32>,
+ <11 32>,
+ <12 32>,
+ <15 32>;
+ qcom,cmb-elem-size = <7 32>,
+ <8 32>,
+ <10 32>,
+ <15 64>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_tpda>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda0_in_tpdm_dl_ct: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dl_ct_out_tpda0>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ tpda1_in_funnel_gpu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_gpu_out_tpda1>;
+ };
+ };
+
+ port@3 {
+ reg = <5>;
+ tpda5_in_funnel_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_turing_out_tpda5>;
+ };
+ };
+
+ port@4 {
+ reg = <7>;
+ tpda7_in_tpdm_vsense: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_vsense_out_tpda7>;
+ };
+ };
+
+ port@5 {
+ reg = <8>;
+ tpda8_in_tpdm_dcc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dcc_out_tpda8>;
+ };
+ };
+
+ port@6 {
+ reg = <10>;
+ tpda10_in_tpdm_prng: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_prng_out_tpda10>;
+ };
+ };
+
+ port@7 {
+ reg = <11>;
+ tpda11_in_tpdm_west: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_west_out_tpda11>;
+ };
+ };
+
+ port@8 {
+ reg = <12>;
+ tpda12_in_tpdm_qm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_qm_out_tpda12>;
+ };
+ };
+
+ port@9 {
+ reg = <13>;
+ tpda13_in_tpdm_spdm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_spdm_out_tpda13>;
+ };
+ };
+
+ port@10 {
+ reg = <15>;
+ tpda15_in_tpdm_pimem: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_pimem_out_tpda15>;
+ };
+ };
+
+ };
+ };
+
+ /delete-node/ cti@8867000;
+ cti_turing_q6: cti@8862000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8862000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-turing-q6";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+};
+
+#include "bengal-gdsc.dtsi"
+#include "khaje-usb.dtsi"
+#include "bengal-ion.dtsi"
+#include "bengal-bus.dtsi"
+#include "bengal-vidc.dtsi"
+#include "pm6125.dtsi"
+
+&gcc_camss_top_gdsc {
+ status = "ok";
+};
+
+&gcc_ufs_phy_gdsc {
+ status = "ok";
+};
+
+&gcc_usb30_prim_gdsc {
+ status = "ok";
+};
+
+&gcc_vcodec0_gdsc {
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&gcc_venus_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_turing_mmu_tbu1_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_turing_mmu_tbu0_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {
+ status = "ok";
+};
+
+&mdss_core_gdsc {
+ reg = <0x5f01004 0x4>;
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&gpu_cx_gdsc {
+ parent-supply = <&VDD_CX_LEVEL>;
+ status = "ok";
+};
+
+&gpu_gx_gdsc {
+ parent-supply = <&VDD_CX_LEVEL>;
+ status = "ok";
+};
+
+#include "msm-arm-smmu-bengal.dtsi"
+#include "pm6125-rpm-regulator.dtsi"
+#include "khaje-regulator.dtsi"
+#include "bengal-pm.dtsi"
+#include "khaje-pinctrl.dtsi"
+#include "bengal-qupv3.dtsi"
+#include "bengal-gpu.dtsi"
+#include "bengal-audio.dtsi"
+#include "khaje-sde-pll.dtsi"
+#include "khaje-sde.dtsi"
+
+&soc {
+ /delete-node/ gpu_bw_tbl;
+ /delete-node/ gpubw;
+ /delete-node/ gpu_opp_table;
+
+ gpu_bw_tbl: gpu-bw-tbl {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 0, 8); /* 0 MB/s */
+ BW_OPP_ENTRY( 200, 8); /* 1525 MB/s */
+ BW_OPP_ENTRY( 547, 8); /* 4173 MB/s */
+ BW_OPP_ENTRY( 768, 8); /* 5859 MB/s */
+ BW_OPP_ENTRY(1017, 8); /* 7759 MB/s */
+ BW_OPP_ENTRY(1555, 8); /*11863 MB/s */
+ BW_OPP_ENTRY(1804, 8); /*13763 MB/s */
+ BW_OPP_ENTRY(2092, 8); /*15960 MB/s */
+ };
+
+ gpubw: qcom,gpubw {
+ compatible = "qcom,devbw";
+ governor = "bw_vbif";
+ qcom,src-dst-ports = <26 512>;
+ operating-points-v2 = <&gpu_bw_tbl>;
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-1114800000 {
+ opp-hz = /bits/ 64 <1114800000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+
+ opp-1025000000 {
+ opp-hz = /bits/ 64 <1025000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ opp-785000000 {
+ opp-hz = /bits/ 64 <785000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-465000000 {
+ opp-hz = /bits/ 64 <465000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-320000000 {
+ opp-hz = /bits/ 64 <320000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+};
+
+&msm_gpu {
+ qcom,chipid = <0x06010001>;
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,vectors-KBps =
+ <26 512 0 0>,
+ <26 512 0 1600000>, /* 1 bus=200 (LOW SVS) */
+ <26 512 0 4376000>, /* 2 bus=547 (LOW SVS) */
+ <26 512 0 6144000>, /* 3 bus=768 (SVS) */
+ <26 512 0 8136000>, /* 4 bus=1017 (SVS_L1) */
+ <26 512 0 12440000>, /* 5 bus=1555 (NOM) */
+ <26 512 0 14432000>, /* 6 bus=1804 (TURBO) */
+ <26 512 0 16736000>; /* 7 bus=2092 (TURBO_L1) */
+
+ /delete-node/ qcom,gpu-pwrlevel-bins;
+ /*
+ * Speed-bin zero is default speed bin.
+ * For rest of the speed bins, speed-bin value
+ * is calculated as FMAX/4.8 MHz round up to zero
+ * decimal places plus two margin to account for
+ * clock jitters.
+ */
+ qcom,gpu-pwrlevel-bins {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "qcom,gpu-pwrlevel-bins";
+
+ qcom,gpu-pwrlevels-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <0>;
+
+ qcom,initial-pwrlevel = <6>;
+ qcom,ca-target-pwrlevel = <5>;
+
+ /* TURBO_L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <1260000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <7>;
+ };
+
+ /* TURBO_L1 */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <1114800000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <7>;
+ };
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <1025000000>;
+ qcom,bus-freq = <6>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <785000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <5>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <600000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <2>;
+ qcom,bus-max = <4>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <320000000>;
+ qcom,bus-freq = <2>;
+ qcom,bus-min = <1>;
+ qcom,bus-max = <2>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <235>;
+
+ qcom,initial-pwrlevel = <5>;
+ qcom,ca-target-pwrlevel = <4>;
+
+ /* TURBO_L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <1114800000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <7>;
+ };
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <1025000000>;
+ qcom,bus-freq = <6>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <785000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <5>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <600000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <2>;
+ qcom,bus-max = <4>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <320000000>;
+ qcom,bus-freq = <2>;
+ qcom,bus-min = <1>;
+ qcom,bus-max = <2>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <216>;
+
+ qcom,initial-pwrlevel = <4>;
+ qcom,ca-target-pwrlevel = <3>;
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <1025000000>;
+ qcom,bus-freq = <6>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <785000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <5>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <600000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <2>;
+ qcom,bus-max = <4>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <320000000>;
+ qcom,bus-freq = <2>;
+ qcom,bus-min = <1>;
+ qcom,bus-max = <2>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+ };
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #include "pm8008.dtsi"
+};
+
+&pm8008_regulators {
+ /delete-property/ qcom,enable-ocp-broadcast;
+};
+
+&pm8008_8 {
+ /* PM8008 IRQ STAT */
+ interrupt-parent = <&tlmm>;
+ interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm8008_active &pm8008_interrupt>;
+};
+
+&pm8008_regulators {
+ vdd_l1_l2-supply = <&S6A>;
+ vdd_l7-supply = <&S7A>;
+};
+
+&L1P {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,min-dropout-voltage = <56000>;
+};
+
+&L2P {
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1150000>;
+ qcom,min-dropout-voltage = <88000>;
+};
+
+&L3P {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ qcom,min-dropout-voltage = <96000>;
+};
+
+&L4P {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ qcom,min-dropout-voltage = <136000>;
+};
+
+&L5P {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ qcom,min-dropout-voltage = <240000>;
+};
+
+&L6P {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+ qcom,min-dropout-voltage = <168000>;
+};
+
+&L7P {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,min-dropout-voltage = <112000>;
+};
+
+&qupv3_se4_2uart {
+ status = "ok";
+};
+
+&qupv3_se3_4uart {
+ status = "ok";
+};
+
+&pm6125_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&camera_therm_default &emmc_therm_default>;
+
+ pa_therm0 {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "pa_therm0";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ quiet_therm {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "quiet_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ camera_flash_therm {
+ reg = <ADC_GPIO1_PU2>;
+ label = "camera_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ emmc_ufs_therm {
+ reg = <ADC_GPIO2_PU2>;
+ label = "emmc_ufs_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm6125_gpios {
+ camera_therm {
+ camera_therm_default: camera_therm_default {
+ pins = "gpio3";
+ bias-high-impedance;
+ };
+ };
+
+ emmc_therm {
+ emmc_therm_default: emmc_therm_default {
+ pins = "gpio4";
+ bias-high-impedance;
+ };
+ };
+
+};
+
+&spmi_bus {
+ qcom,pm6125@0 {
+ pm6125_adc_tm_iio: adc_tm@3400 {
+ compatible = "qcom,adc-tm5-iio";
+ reg = <0x3400 0x100>;
+ #thermal-sensor-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ io-channels = <&pm6125_vadc ADC_GPIO1_PU2>,
+ <&pm6125_vadc ADC_GPIO2_PU2>;
+
+ camera_flash_therm {
+ reg = <ADC_GPIO1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ emmc_ufs_therm {
+ reg = <ADC_GPIO2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+ };
+ };
+};
+
+&pm6125_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ io-channels = <&pm6125_vadc ADC_AMUX_THM1_PU2>,
+ <&pm6125_vadc ADC_AMUX_THM2_PU2>,
+ <&pm6125_vadc ADC_XO_THERM_PU2>;
+
+ /* Channel nodes */
+ pa_therm0 {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ quiet_therm {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ xo_therm {
+ reg = <ADC_XO_THERM_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&msm_vidc {
+ qcom,cx-ipeak-data = <&cx_ipeak_lm 6>;
+ qcom,clock-freq-threshold = <300000000>;
+};
+
+#include "bengal-thermal.dtsi"
+#include "camera/khaje-camera.dtsi"
+#include "msm-rdbg.dtsi"
+
+&cxip_cdev {
+ status = "disabled";
+};
+
+&rpm_bus {
+ rpm_smd_cdev: rpm-smd-cdev {
+ compatible = "qcom,rpm-smd-cooling-device";
+ #cooling-cells = <2>;
+ };
+};
+
+&thermal_zones {
+ mapss-lowc {
+ cooling-maps {
+ rpm_smd_vdd_cdev {
+ trip = <&mapss_cap_trip>;
+ cooling-device = <&rpm_smd_cdev 2 2>;
+ };
+ };
+ };
+
+ camera-lowc {
+ cooling-maps {
+ rpm_smd_vdd_cdev {
+ trip = <&camera_cap_trip>;
+ cooling-device = <&rpm_smd_cdev 2 2>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-arglass-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/kona-arglass-overlay.dts
new file mode 100755
index 0000000..71a4251
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-arglass-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-kona.h>
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "kona-arglass.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona AR Glass";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x1040008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-arglass.dts b/arch/arm64/boot/dts/vendor/qcom/kona-arglass.dts
new file mode 100755
index 0000000..417f4c9
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-arglass.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona.dtsi"
+#include "kona-arglass.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona AR Glass";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x1040008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-arglass.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-arglass.dtsi
new file mode 100755
index 0000000..f892b1e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-arglass.dtsi
@@ -0,0 +1,1067 @@
+#include <dt-bindings/gpio/gpio.h>
+#include "kona-pmic-overlay.dtsi"
+#include "kona-sde-display.dtsi"
+#include "kona-audio-overlay.dtsi"
+#include "kona-audio-overlay-ar.dtsi"
+#include "kona-thermal-overlay.dtsi"
+#include "kona-xr-pinctrl-overlay.dtsi"
+#include "camera/kona-camera-sensor-arglass.dtsi"
+
+&tlmm {
+ mag_rst_gpio_default: mag_rst_gpio_default {
+ mux {
+ pins = "gpio125";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio125";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ output-high;
+ };
+ };
+
+ mag_rst_gpio_sleep: mag_rst_gpio_sleep {
+ mux {
+ pins = "gpio125";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio125";
+ drive-strength = <8>;
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_1_sd_n {
+ spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+ mux {
+ pins = "gpio127";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio127";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_1_sd_n_active: spkr_1_sd_n_active {
+ mux {
+ pins = "gpio127";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio127";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ spkr_2_sd_n {
+ spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
+ mux {
+ pins = "gpio129";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio129";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_2_sd_n_active: spkr_2_sd_n_active {
+ mux {
+ pins = "gpio129";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio129";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ cam_sensor_6dof_vio_active: cam_sensor_6dof_vio_active {
+ /* VIO LDO */
+ mux {
+ pins = "gpio41";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio41";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vio_suspend: cam_sensor_6dof_vio_suspend {
+ /* VIO LDO */
+ mux {
+ pins = "gpio41";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio41";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+};
+
+&vendor {
+ kona_arglass_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "fg-gen4-batterydata-goertek-650mah.dtsi"
+ };
+};
+
+&qupv3_se12_2uart {
+ status = "okay";
+};
+
+&pm8150a_amoled {
+ status = "disabled";
+};
+
+&qupv3_se6_4uart {
+ status = "ok";
+};
+
+&dai_mi2s2 {
+ status = "disabled";
+ qcom,msm-mi2s-tx-lines = <1>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
+ &tert_mi2s_sd0_active>;
+ pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
+ &tert_mi2s_sd0_sleep>;
+};
+
+&pm8150_l10 {
+ regulator-max-microvolt = <3304000>;
+ qcom,init-voltage = <3304000>;
+};
+
+&qupv3_se1_i2c {
+ status = "disabled";
+ qcom,clk-freq-out = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ xrfancontroller: xrfancontroller@50 {
+ compatible = "maxim,xrfancontroller";
+ reg = <0x50>;
+ /* Manetometer gpio */
+ mag_rst_gpio = <&tlmm 125 0>;
+ enable-active-high;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mag_rst_gpio_default>;
+ pinctrl-1 = <&mag_rst_gpio_sleep>;
+ qcom,fan-pwr-en = <&tlmm 38 0x00>;
+ qcom,fan-pwr-bp = <&tlmm 39 0x00>;
+ };
+};
+
+&qupv3_se13_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v4";
+
+ vdda-phy-supply = <&pm8150_l5>;
+ vdda-phy-always-on;
+ vdda-pll-supply = <&pm8150_l9>;
+ vdda-phy-max-microamp = <89900>;
+ vdda-pll-max-microamp = <18800>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm8150_l17>;
+ vcc-voltage-level = <2504000 2950000>;
+ vcc-low-voltage-sup;
+ vccq-supply = <&pm8150_l6>;
+ vccq2-supply = <&pm8150_s4>;
+ vcc-max-microamp = <800000>;
+ vccq-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+
+ qcom,vddp-ref-clk-supply = <&pm8150_l6>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vccq-parent-supply = <&pm8150a_s8>;
+ qcom,vccq-parent-max-microamp = <210000>;
+
+ status = "ok";
+};
+
+&soc {
+ qcom,qbt_handler {
+ status = "disabled";
+ };
+
+ qcom,xr-stdalonevwr-misc {
+ compatible = "qcom,xr-stdalonevwr-misc";
+ /* IMU CLK Enable PM8150 GPIO 3 & MAG_RST_GPIO */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&imu_clkin_default &mag_rst_gpio_default>;
+ pinctrl-1 = <&imu_clkin_sleep &mag_rst_gpio_sleep>;
+ };
+};
+
+&vreg_hap_boost {
+ status = "ok";
+};
+
+&pm8150b_haptics {
+ qcom,vmax-mv = <1697>;
+ qcom,play-rate-us = <5882>;
+ vdd-supply = <&vreg_hap_boost>;
+
+ wf_0 {
+ /* CLICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_1 {
+ /* DOUBLE CLICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_2 {
+ /* TICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_3 {
+ /* THUD */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_4 {
+ /* POP */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_5 {
+ /* HEAVY CLICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+};
+
+&pm8150b_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "conn_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ chg_sbux@99 {
+ reg = <ADC_SBUx>;
+ label = "chg_sbux";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ mid_chg_div6@1e {
+ reg = <ADC_MID_CHG_DIV6>;
+ label = "chg_mid";
+ qcom,pre-scaling = <1 6>;
+ };
+
+ usb_in_i_uv@7 {
+ reg = <ADC_USB_IN_I>;
+ label = "usb_in_i_uv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ usb_in_v_div_16@8 {
+ reg = <ADC_USB_IN_V_16>;
+ label = "usb_in_v_div_16";
+ qcom,pre-scaling = <1 16>;
+ };
+};
+
+&qupv3_se15_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ redriver: redriver@1c {
+ compatible = "onnn,redriver";
+ reg = <0x1c>;
+ extcon = <&pm8150b_pdphy>, <&pm8150b_pdphy>;
+ eq = /bits/ 8 <
+ /* Parameters for USB */
+ 0x4 0x4 0x4 0x4
+ /* Parameters for DP */
+ 0x6 0x4 0x4 0x6>;
+ flat-gain = /bits/ 8 <
+ /* Parameters for USB */
+ 0x3 0x1 0x1 0x3
+ /* Parameters for DP */
+ 0x2 0x1 0x1 0x2>;
+ output-comp = /bits/ 8 <
+ /* Parameters for USB */
+ 0x3 0x3 0x3 0x3
+ /* Parameters for DP */
+ 0x3 0x3 0x3 0x3>;
+ loss-match = /bits/ 8 <
+ /* Parameters for USB */
+ 0x1 0x3 0x3 0x1
+ /* Parameters for DP */
+ 0x3 0x3 0x3 0x3>;
+ };
+
+ #include "smb1390.dtsi"
+};
+
+&smb1390 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_stat_default>;
+ status = "ok";
+};
+
+&smb1390_charger {
+ io-channels = <&pm8150b_vadc ADC_AMUX_THM2>;
+ io-channel-names = "cp_die_temp";
+ qcom,parallel-output-mode = <2>;
+ status = "ok";
+};
+
+&smb1390_slave {
+ status = "ok";
+};
+
+&smb1390_slave_charger {
+ status = "ok";
+};
+
+&pm8150b_charger {
+ status = "ok";
+ qcom,sec-charger-config = <1>;
+ qcom,auto-recharge-soc = <98>;
+ io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>,
+ <&pm8150b_vadc ADC_USB_IN_I>,
+ <&pm8150b_vadc ADC_SBUx>,
+ <&pm8150b_vadc ADC_VPH_PWR>,
+ <&pm8150b_vadc ADC_CHG_TEMP>;
+ io-channel-names = "mid_voltage",
+ "usb_in_current",
+ "sbux_res",
+ "vph_voltage",
+ "chg_temp";
+ qcom,battery-data = <&kona_arglass_batterydata>;
+ qcom,sw-jeita-enable;
+ qcom,wd-bark-time-secs = <16>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,hvdcp-disable;
+ qcom,thermal-mitigation = <5325000 4500000 4000000 3500000 3000000
+ 2500000 2000000 1500000 1000000 500000>;
+};
+
+&pm8150b_fg {
+ status = "ok";
+ qcom,battery-data = <&kona_arglass_batterydata>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,five-pin-battery;
+ qcom,cl-wt-enable;
+ qcom,soc-scale-mode-en;
+ qcom,fg-force-load-profile;
+ /* ESR fast calibration */
+ qcom,fg-esr-timer-chg-fast = <0 7>;
+ qcom,fg-esr-timer-dischg-fast = <0 7>;
+ qcom,fg-esr-timer-chg-slow = <0 96>;
+ qcom,fg-esr-timer-dischg-slow = <0 96>;
+ qcom,fg-esr-cal-soc-thresh = <26 230>;
+ qcom,fg-esr-cal-temp-thresh = <10 40>;
+};
+
+&pm8150_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vcoin@85 {
+ reg = <ADC_VCOIN>;
+ label = "vcoin";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ xo_therm@4c {
+ reg = <ADC_XO_THERM_PU2>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "pa_therm1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150l_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ camera_flash_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "camera_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_msm_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "skin_msm_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm2@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "pa_therm2";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150b_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ io-channels = <&pm8150b_vadc ADC_AMUX_THM3_PU2>;
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ io-channels = <&pm8150_vadc ADC_XO_THERM_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM1_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM2_PU2>;
+
+ xo_therm@4c {
+ reg = <ADC_XO_THERM_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150l_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera_flash_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ skin_msm_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm2@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&spmi_debug_bus {
+ status = "ok";
+};
+
+&sde_dsi {
+ /delete-property/ avdd-supply;
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+ qcom,dsi-default-panel = <&dsi_dual_arglass_seeya_video>;
+};
+
+&display_panel_avdd {
+ status = "disabled";
+};
+
+&pm8150l_lcdb {
+ status = "ok";
+};
+
+&pm8150l_wled {
+ status = "ok";
+};
+
+&dsi_dual_arglass_seeya_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-ctrl-dcs-subtype = <0xc2>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <1023>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-bklight-en-gpio = <&tlmm 46 0>;
+ qcom,5v-boost-gpio = <&tlmm 61 0>;
+ /delete-property/ qcom,platform-en-gpio;
+};
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&thermal_zones {
+ conn-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM3_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-msm-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&sdhc_2 {
+ vdd-supply = <&pm8150a_l9>;
+ qcom,vdd-voltage-level = <2950000 2960000>;
+ qcom,vdd-current-level = <200 800000>;
+
+ vdd-io-supply = <&pm8150a_l6>;
+ qcom,vdd-io-voltage-level = <1808000 2960000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>;
+
+ cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; /* Morpheus has to be HIGH */
+
+ status = "disabled";
+};
+
+&vendor {
+ bluetooth: bt_qca6390 {
+ compatible = "qca,qca6390";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en_sleep>;
+ qca,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */
+ qca,bt-sw-ctrl-gpio = <&tlmm 124 0>; /* SW_CTRL */
+ qca,bt-vdd-aon-supply = <&pm8150_s6>;
+ qca,bt-vdd-dig-supply = <&pm8150_s6>;
+ qca,bt-vdd-rfa1-supply = <&pm8150_s5>;
+ qca,bt-vdd-rfa2-supply = <&pm8150a_s8>;
+ qca,bt-vdd-asd-supply = <&pm8150_l16>;
+
+ qca,bt-vdd-aon-voltage-level = <950000 950000>;
+ qca,bt-vdd-dig-voltage-level = <950000 952000>;
+ qca,bt-vdd-rfa1-voltage-level = <1900000 1900000>;
+ qca,bt-vdd-rfa2-voltage-level = <1350000 1350000>;
+ qca,bt-vdd-asd-voltage-level = <3024000 3304000>;
+
+ qca,bt-vdd-asd-current-level = <10000>;
+ };
+};
+
+&usb0 {
+ dwc3@a600000 {
+ maximum-speed = "super-speed-plus";
+ };
+};
+
+&usb1 {
+ qcom,default-mode-none;
+};
+
+&wil6210 {
+ status = "disabled";
+};
+
+&usb2_phy0 {
+ qcom,param-override-seq =
+ <0xc7 0x6c
+ 0x0f 0x70
+ 0x03 0x74>;
+};
+
+&mdss_mdp {
+ qcom,sde-mixer-display-pref = "primary", "primary", "primary",
+ "primary", "none", "none";
+};
+
+&kona_snd {
+ qcom,model = "kona-arglass-snd-card";
+ qcom,mi2s-audio-intf = <0>;
+ qcom,audio-routing =
+ "TX DMIC0", "Digital Mic0",
+ "TX DMIC1", "Digital Mic1",
+ "TX DMIC2", "Digital Mic2",
+ "TX DMIC3", "Digital Mic3",
+ "TX DMIC4", "Digital Mic4",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA DMIC0", "Digital Mic0",
+ "VA DMIC1", "Digital Mic1",
+ "VA DMIC2", "Digital Mic2",
+ "VA DMIC3", "Digital Mic3",
+ "VA DMIC4", "Digital Mic4",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+ qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
+ qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
+ qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
+ asoc-codec = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
+ "msm-ext-disp-audio-codec-rx";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>,
+ <&wsa881x_0213>, <&wsa881x_0214>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+ "SpkrLeft", "SpkrRight";
+ qcom,codec-max-aux-devs = <0>;
+ /delete-property/ qcom,codec-aux-devs;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
+ <&bolero>;
+};
+
+&wcd938x_tx_slave {
+ status = "disabled";
+};
+
+&wcd938x_rx_slave {
+ status = "disabled";
+};
+
+&wcd938x_codec {
+ status = "disabled";
+};
+
+&kona_snd_ar {
+ qcom,model = "kona-arglass-snd-card";
+ qcom,mi2s-audio-intf = <0>;
+ qcom,audio-routing =
+ "TX DMIC0", "Digital Mic0",
+ "TX DMIC1", "Digital Mic1",
+ "TX DMIC2", "Digital Mic2",
+ "TX DMIC3", "Digital Mic3",
+ "TX DMIC4", "Digital Mic4",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA DMIC0", "Digital Mic0",
+ "VA DMIC1", "Digital Mic1",
+ "VA DMIC2", "Digital Mic2",
+ "VA DMIC3", "Digital Mic3",
+ "VA DMIC4", "Digital Mic4",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+ qcom,codec-max-aux-devs = <0>;
+ /delete-property/ qcom,codec-aux-devs;
+};
+
+&wcd938x_tx_slave_ar {
+ status = "disabled";
+};
+
+&wcd938x_rx_slave_ar {
+ status = "disabled";
+};
+
+&wcd938x_codec_ar {
+ status = "disabled";
+};
+
+&pm8150a_l4 {
+ qcom,init-voltage = <2800000>;
+};
+
+&pm8150a_l3 {
+ qcom,init-voltage = <1200000>;
+};
+
+&pm8150a_l9 {
+ qcom,init-voltage = <2800000>;
+};
+
+&sde_dp {
+ status="disabled";
+};
+
+&mdss_mdp {
+ connectors = <&sde_wb &sde_dsi &sde_dsi1 &sde_rscc>;
+};
+
+&wlan {
+ vdd-wlan-dig-supply = <&pm8150_s6>;
+ qcom,vdd-wlan-dig-config = <950000 950000 0 0 1>;
+ qcom,cmd_db_name = "smpa6";
+};
+
+&flash_led {
+ qcom,hw-strobe-option = <0>;
+ qcom,strobe-sel = <1>;
+ qcom,ramp-up-step = <200>;
+ qcom,ramp-down-step = <200>;
+ status = "okay";
+};
+
+&pm8150l_flash0 {
+ qcom,strobe-sel = <1>;
+ status = "okay";
+};
+
+&pm8150l_flash1 {
+ qcom,strobe-sel = <1>;
+ status = "okay";
+};
+
+&pm8150l_flash2 {
+ qcom,strobe-sel = <1>;
+ status = "okay";
+};
+
+&pm8150l_torch0 {
+ qcom,strobe-sel = <1>;
+ status = "okay";
+};
+
+&pm8150l_torch1 {
+ qcom,strobe-sel = <1>;
+ status = "okay";
+};
+
+&pm8150l_torch2 {
+ qcom,strobe-sel = <1>;
+ status = "okay";
+};
+
+&pm8150b_pdphy {
+ /* Restricting only to 5V@3A */
+ qcom,default-sink-caps = <5000 3000>; /* 5V @ 3A */
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-audio-ar.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-audio-ar.dtsi
new file mode 100755
index 0000000..edefccc
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-audio-ar.dtsi
@@ -0,0 +1,109 @@
+#include <dt-bindings/sound/qcom,gpr.h>
+
+&glink_adsp {
+ audio_gpr: qcom,gpr {
+ compatible = "qcom,gpr";
+ qcom,glink-channels = "adsp_apps";
+ qcom,intents = <0x200 20>;
+ reg = <GPR_DOMAIN_ADSP>;
+ spf_core {
+ compatible = "qcom,spf_core";
+ reg = <GPR_SVC_ADSP_CORE>;
+ };
+
+ audio-pkt {
+ compatible = "qcom,audio-pkt";
+ qcom,audiopkt-ch-name = "apr_audio_svc";
+ reg = <GPR_SVC_MAX>;
+ };
+
+ audio_prm: q6prm {
+ compatible = "qcom,audio_prm";
+ reg = <GPR_SVC_ASM>;
+ };
+
+ voice-mhi {
+ compatible = "qcom,voice_mhi_gpr";
+ reg = <GPR_SVC_VPM>;
+ };
+ };
+};
+
+&soc {
+ spf_core_platform: spf_core_platform {
+ compatible = "qcom,spf-core-platform";
+ };
+
+ audio_pkt_core_platform: qcom,audio-pkt-core-platform {
+ compatible = "qcom,audio-pkt-core-platform";
+ };
+};
+
+&spf_core_platform {
+ msm_audio_ion_ar: qcom,msm-audio-ion-ar {
+ compatible = "qcom,msm-audio-ion";
+ qcom,smmu-version = <2>;
+ qcom,smmu-enabled;
+ iommus = <&apps_smmu 0x1801 0x0>;
+ qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>;
+ qcom,smmu-sid-mask = /bits/ 64 <0xf>;
+ };
+
+ lpass_core_hw_vote_ar: vote_lpass_core_hw_ar {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_CORE_HW_VOTE>;
+ #clock-cells = <1>;
+ };
+
+ lpass_audio_hw_vote_ar: vote_lpass_audio_hw_ar {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_AUDIO_HW_VOTE>;
+ #clock-cells = <1>;
+ };
+
+ bolero_ar: bolero-cdc-ar {
+ compatible = "qcom,bolero-codec";
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote_ar 0>,
+ <&lpass_audio_hw_vote_ar 0>;
+ bolero-clk-rsc-mngr-ar {
+ compatible = "qcom,bolero-clk-rsc-mngr";
+ };
+
+ tx_macro_ar: tx-macro-ar@3220000 {
+ swr_ar2: tx_swr_master_ar {
+ };
+ };
+
+ rx_macro_ar: rx-macro-ar@3200000 {
+ swr_ar1: rx_swr_master_ar {
+ };
+ };
+
+ wsa_macro_ar: wsa-macro-ar@3240000 {
+ swr_ar0: wsa_swr_master_ar {
+ };
+ };
+ };
+
+ voice_mhi_audio_ar: qcom,voice-mhi-audio-ar {
+ compatible = "qcom,voice-mhi-audio";
+ memory-region = <&mailbox_mem>;
+ voice_mhi_voting;
+ };
+
+ kona_snd_ar: sound_ar {
+ compatible = "qcom,kona-asoc-snd";
+ qcom,mi2s-audio-intf = <1>;
+ qcom,auxpcm-audio-intf = <1>;
+ qcom,tdm-audio-intf = <1>;
+ qcom,wcn-bt = <0>;
+ qcom,ext-disp-audio-rx = <0>;
+ qcom,afe-rxtx-lb = <0>;
+
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote_ar 0>;
+ fsa4480-i2c-handle = <&fsa4480>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-audio-overlay-ar.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-audio-overlay-ar.dtsi
new file mode 100755
index 0000000..8cc61d5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-audio-overlay-ar.dtsi
@@ -0,0 +1,382 @@
+#include "kona-lpi-ar.dtsi"
+#include "kona-va-bolero-ar.dtsi"
+
+&bolero_ar {
+ qcom,num-macros = <4>;
+ bolero-clk-rsc-mngr-ar {
+ compatible = "qcom,bolero-clk-rsc-mngr";
+ qcom,fs-gen-sequence = <0x3000 0x1>,
+ <0x3004 0x1>, <0x3080 0x2>;
+ qcom,rx_mclk_mode_muxsel = <0x033240D8>;
+ qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
+ qcom,va_mclk_mode_muxsel = <0x033A0000>;
+ clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
+ "wsa_core_clk", "wsa_npl_clk", "va_core_clk", "va_npl_clk";
+ clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
+ <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
+ <&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
+ <&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
+ };
+
+ tx_macro_ar: tx-macro-ar@3220000 {
+ compatible = "qcom,tx-macro";
+ reg = <0x3220000 0x0>;
+ clock-names = "tx_core_clk", "tx_npl_clk";
+ clocks = <&clock_audio_tx_1 0>,
+ <&clock_audio_tx_2 0>;
+ qcom,tx-swr-gpios = <&tx_swr_gpios_ar>;
+ qcom,tx-dmic-sample-rate = <2400000>;
+ swr_ar2: tx_swr_master_ar {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote_ar 0>,
+ <&lpass_audio_hw_vote_ar 0>;
+ qcom,swr-master-version = <0x01050001>;
+ qcom,swr_master_id = <3>;
+ qcom,mipi-sdw-block-packing-mode = <1>;
+ swrm-io-base = <0x3230000 0x0>;
+ interrupts-extended =
+ <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq", "swr_wake_irq";
+ qcom,swr-wakeup-required = <1>;
+ qcom,swr-num-ports = <5>;
+ qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,
+ <2 ADC1 0x1>, <2 ADC2 0x2>,
+ <3 ADC3 0x1>, <3 ADC4 0x2>,
+ <4 DMIC0 0x1>, <4 DMIC1 0x2>,
+ <4 DMIC2 0x4>, <4 DMIC3 0x8>,
+ <5 DMIC4 0x1>, <5 DMIC5 0x2>,
+ <5 DMIC6 0x4>, <5 DMIC7 0x8>;
+ qcom,swr-num-dev = <1>;
+ qcom,swr-clock-stop-mode0 = <1>;
+ qcom,swr-mstr-irq-wakeup-capable = <1>;
+ wcd938x_tx_slave_ar: wcd938x-tx-slave_ar {
+ compatible = "qcom,wcd938x-slave";
+ reg = <0x0D 0x01170223>;
+ };
+ };
+ };
+
+ rx_macro_ar: rx-macro-ar@3200000 {
+ compatible = "qcom,rx-macro";
+ reg = <0x3200000 0x0>;
+ clock-names = "rx_core_clk", "rx_npl_clk";
+ clocks = <&clock_audio_rx_1 0>,
+ <&clock_audio_rx_2 0>;
+ qcom,rx-swr-gpios = <&rx_swr_gpios_ar>;
+ qcom,rx_mclk_mode_muxsel = <0x033240D8>;
+ qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ swr_ar1: rx_swr_master_ar {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote_ar 0>,
+ <&lpass_audio_hw_vote_ar 0>;
+ qcom,swr-master-version = <0x01050001>;
+ qcom,swr_master_id = <2>;
+ qcom,mipi-sdw-block-packing-mode = <1>;
+ swrm-io-base = <0x3210000 0x0>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq";
+ qcom,swr-num-ports = <5>;
+ qcom,disable-div2-clk-switch = <1>;
+ qcom,swr-port-mapping = <1 HPH_L 0x1>,
+ <1 HPH_R 0x2>, <2 CLSH 0x1>,
+ <3 COMP_L 0x1>, <3 COMP_R 0x2>,
+ <4 LO 0x1>, <5 DSD_L 0x1>,
+ <5 DSD_R 0x2>;
+ qcom,swr-num-dev = <1>;
+ qcom,swr-clock-stop-mode0 = <1>;
+ wcd938x_rx_slave_ar: wcd938x-rx-slave-ar {
+ compatible = "qcom,wcd938x-slave";
+ reg = <0x0D 0x01170224>;
+ };
+ };
+ };
+
+ wsa_macro_ar: wsa-macro-ar@3240000 {
+ compatible = "qcom,wsa-macro";
+ reg = <0x3240000 0x0>;
+ clock-names = "wsa_core_clk", "wsa_npl_clk";
+ clocks = <&clock_audio_wsa_1 0>,
+ <&clock_audio_wsa_2 0>;
+ qcom,wsa-swr-gpios = <&wsa_swr_gpios_ar>;
+ qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ swr_ar0: wsa_swr_master_ar {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote_ar 0>,
+ <&lpass_audio_hw_vote_ar 0>;
+ qcom,swr-master-version = <0x01050001>;
+ qcom,swr_master_id = <1>;
+ qcom,mipi-sdw-block-packing-mode = <0>;
+ swrm-io-base = <0x3250000 0x0>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq";
+ qcom,swr-num-ports = <8>;
+ qcom,swr-port-mapping = <1 SPKR_L 0x1>,
+ <2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
+ <4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
+ <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
+ <8 SPKR_R_VI 0x3>;
+ qcom,swr-num-dev = <2>;
+ wsa881x_0211_ar: wsa881x_ar@20170211 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x20170211>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+ qcom,bolero-handle = <&bolero_ar>;
+ };
+
+ wsa881x_0212_ar: wsa881x_ar@20170212 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x20170212>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero_ar>;
+ };
+
+ wsa881x_0213_ar: wsa881x_ar@21170213 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x21170213>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+ qcom,bolero-handle = <&bolero_ar>;
+ };
+
+ wsa881x_0214_ar: wsa881x_ar@21170214 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x21170214>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero_ar>;
+ };
+ };
+
+ };
+
+ wcd938x_codec_ar: wcd938x-codec-ar {
+ compatible = "qcom,wcd938x-codec";
+ qcom,split-codec = <1>;
+ qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
+ <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
+ <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
+ <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
+ <4 DSD_R 0x2 0 DSD_R>;
+ qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
+ <0 ADC2 0x2 0 ADC2>, <1 ADC3 0x1 0 ADC3>,
+ <1 ADC4 0x2 0 ADC4>, <2 DMIC0 0x1 0 DMIC0>,
+ <2 DMIC1 0x2 0 DMIC1>, <2 MBHC 0x4 0 DMIC2>,
+ <2 DMIC2 0x4 0 DMIC2>, <2 DMIC3 0x8 0 DMIC3>,
+ <3 DMIC4 0x1 0 DMIC4>, <3 DMIC5 0x2 0 DMIC5>,
+ <3 DMIC6 0x4 0 DMIC6>, <3 DMIC7 0x8 0 DMIC7>;
+
+ qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
+ qcom,rx-slave = <&wcd938x_rx_slave_ar>;
+ qcom,tx-slave = <&wcd938x_tx_slave_ar>;
+
+ cdc-vdd-rxtx-supply = <&S4A>;
+ qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-rxtx-current = <30000>;
+
+ cdc-vddio-supply = <&S4A>;
+ qcom,cdc-vddio-voltage = <1800000 1800000>;
+ qcom,cdc-vddio-current = <30000>;
+
+ cdc-vdd-buck-supply = <&S4A>;
+ qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-buck-current = <650000>;
+
+ cdc-vdd-mic-bias-supply = <&BOB>;
+ qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
+ qcom,cdc-vdd-mic-bias-current = <30000>;
+
+ qcom,cdc-micbias1-mv = <1800>;
+ qcom,cdc-micbias2-mv = <1800>;
+ qcom,cdc-micbias3-mv = <1800>;
+ qcom,cdc-micbias4-mv = <1800>;
+
+ qcom,cdc-static-supplies = "cdc-vdd-rxtx",
+ "cdc-vddio",
+ "cdc-vdd-buck",
+ "cdc-vdd-mic-bias";
+ };
+
+};
+
+&kona_snd_ar {
+ qcom,model = "kona-mtp-snd-card";
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
+ qcom,mi2s-tdm-is-hw-vote-needed = <1>, <0>, <1>, <0>, <0>, <0>;
+ qcom,wcn-bt = <0>;
+ qcom,ext-disp-audio-rx = <1>;
+ qcom,tdm-max-slots = <8>;
+ qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
+ qcom,mi2s-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic4",
+ "AMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Analog Mic5",
+ "TX DMIC0", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic0",
+ "TX DMIC1", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic1",
+ "TX DMIC2", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "TX DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "TX DMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "TX DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic4",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA DMIC4", "VA MIC BIAS4",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC0", "VA_SWR_CLK",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_ADC2", "VA_SWR_CLK",
+ "VA SWR_ADC3", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_ADC0", "ADC1_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT",
+ "VA SWR_ADC2", "ADC3_OUTPUT",
+ "VA SWR_ADC3", "ADC4_OUTPUT",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios_ar>;
+ qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios_ar>;
+ qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios_ar>;
+ asoc-codec = <&stub_codec>, <&bolero_ar>, <&ext_disp_audio_codec>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
+ "msm-ext-disp-audio-codec-rx";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa881x_0211_ar>, <&wsa881x_0212_ar>,
+ <&wsa881x_0213_ar>, <&wsa881x_0214_ar>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+ "SpkrLeft", "SpkrRight";
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&wcd938x_codec_ar>;
+ qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm_ar>,
+ <&bolero_ar>;
+};
+
+&spf_core_platform {
+ cdc_dmic01_gpios_ar: cdc_dmic01_pinctrl_ar {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic01_clk_active_ar &cdc_dmic01_data_active_ar>;
+ pinctrl-1 = <&cdc_dmic01_clk_sleep_ar &cdc_dmic01_data_sleep_ar>;
+ qcom,lpi-gpios;
+ };
+
+ cdc_dmic23_gpios_ar: cdc_dmic23_pinctrl_ar {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic23_clk_active_ar &cdc_dmic23_data_active_ar>;
+ pinctrl-1 = <&cdc_dmic23_clk_sleep_ar &cdc_dmic23_data_sleep_ar>;
+ qcom,lpi-gpios;
+ };
+
+ cdc_dmic45_gpios_ar: cdc_dmic45_pinctrl_ar {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic45_clk_active_ar &cdc_dmic45_data_active_ar>;
+ pinctrl-1 = <&cdc_dmic45_clk_sleep_ar &cdc_dmic45_data_sleep_ar>;
+ qcom,lpi-gpios;
+ qcom,tlmm-gpio = <158>;
+ };
+
+ wsa_swr_gpios_ar: wsa_swr_clk_data_pinctrl_ar {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wsa_swr_clk_active_ar &wsa_swr_data_active_ar>;
+ pinctrl-1 = <&wsa_swr_clk_sleep_ar &wsa_swr_data_sleep_ar>;
+ qcom,lpi-gpios;
+ };
+
+ rx_swr_gpios_ar: rx_swr_clk_data_pinctrl_ar {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&rx_swr_clk_active_ar &rx_swr_data_active_ar
+ &rx_swr_data1_active_ar>;
+ pinctrl-1 = <&rx_swr_clk_sleep_ar &rx_swr_data_sleep_ar
+ &rx_swr_data1_sleep_ar>;
+ qcom,lpi-gpios;
+ };
+
+ tx_swr_gpios_ar: tx_swr_clk_data_pinctrl_ar {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&tx_swr_clk_active_ar &tx_swr_data1_active_ar
+ &tx_swr_data2_active_ar>;
+ pinctrl-1 = <&tx_swr_clk_sleep_ar &tx_swr_data1_sleep_ar
+ &tx_swr_data2_sleep_ar>;
+ qcom,lpi-gpios;
+ qcom,tlmm-gpio = <147>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-audio-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-audio-overlay.dtsi
new file mode 100755
index 0000000..7899483
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-audio-overlay.dtsi
@@ -0,0 +1,469 @@
+#include <dt-bindings/clock/qcom,audio-ext-clk.h>
+#include <dt-bindings/sound/qcom,bolero-clk-rsc.h>
+#include <dt-bindings/sound/audio-codec-port-types.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "kona-lpi.dtsi"
+#include "kona-va-bolero.dtsi"
+
+&bolero {
+ qcom,num-macros = <4>;
+ bolero-clk-rsc-mngr {
+ compatible = "qcom,bolero-clk-rsc-mngr";
+ qcom,fs-gen-sequence = <0x3000 0x1>,
+ <0x3004 0x1>, <0x3080 0x2>;
+ qcom,rx_mclk_mode_muxsel = <0x033240D8>;
+ qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
+ qcom,va_mclk_mode_muxsel = <0x033A0000>;
+ clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
+ "wsa_core_clk", "wsa_npl_clk", "va_core_clk", "va_npl_clk";
+ clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
+ <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
+ <&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
+ <&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
+ };
+
+ tx_macro: tx-macro@3220000 {
+ compatible = "qcom,tx-macro";
+ reg = <0x3220000 0x0>;
+ clock-names = "tx_core_clk", "tx_npl_clk";
+ clocks = <&clock_audio_tx_1 0>,
+ <&clock_audio_tx_2 0>;
+ qcom,tx-swr-gpios = <&tx_swr_gpios>;
+ qcom,tx-dmic-sample-rate = <2400000>;
+ swr2: tx_swr_master {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ qcom,swr-master-version = <0x01050001>;
+ qcom,swr_master_id = <3>;
+ qcom,mipi-sdw-block-packing-mode = <1>;
+ swrm-io-base = <0x3230000 0x0>;
+ interrupts-extended =
+ <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq", "swr_wake_irq";
+ qcom,swr-wakeup-required = <1>;
+ qcom,swr-num-ports = <5>;
+ qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,
+ <2 ADC1 0x1>, <2 ADC2 0x2>,
+ <3 ADC3 0x1>, <3 ADC4 0x2>,
+ <4 DMIC0 0x1>, <4 DMIC1 0x2>,
+ <4 DMIC2 0x4>, <4 DMIC3 0x8>,
+ <5 DMIC4 0x1>, <5 DMIC5 0x2>,
+ <5 DMIC6 0x4>, <5 DMIC7 0x8>;
+ qcom,swr-num-dev = <1>;
+ qcom,swr-clock-stop-mode0 = <1>;
+ qcom,swr-mstr-irq-wakeup-capable = <1>;
+ wcd938x_tx_slave: wcd938x-tx-slave {
+ compatible = "qcom,wcd938x-slave";
+ reg = <0x0D 0x01170223>;
+ };
+ };
+ };
+
+ rx_macro: rx-macro@3200000 {
+ compatible = "qcom,rx-macro";
+ reg = <0x3200000 0x0>;
+ clock-names = "rx_core_clk", "rx_npl_clk";
+ clocks = <&clock_audio_rx_1 0>,
+ <&clock_audio_rx_2 0>;
+ qcom,rx-swr-gpios = <&rx_swr_gpios>;
+ qcom,rx_mclk_mode_muxsel = <0x033240D8>;
+ qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ swr1: rx_swr_master {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ qcom,swr-master-version = <0x01050001>;
+ qcom,swr_master_id = <2>;
+ qcom,mipi-sdw-block-packing-mode = <1>;
+ swrm-io-base = <0x3210000 0x0>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq";
+ qcom,swr-num-ports = <5>;
+ qcom,disable-div2-clk-switch = <1>;
+ qcom,swr-port-mapping = <1 HPH_L 0x1>,
+ <1 HPH_R 0x2>, <2 CLSH 0x1>,
+ <3 COMP_L 0x1>, <3 COMP_R 0x2>,
+ <4 LO 0x1>, <5 DSD_L 0x1>,
+ <5 DSD_R 0x2>;
+ qcom,swr-num-dev = <1>;
+ qcom,swr-clock-stop-mode0 = <1>;
+ wcd938x_rx_slave: wcd938x-rx-slave {
+ compatible = "qcom,wcd938x-slave";
+ reg = <0x0D 0x01170224>;
+ };
+ };
+ };
+
+ wsa_macro: wsa-macro@3240000 {
+ compatible = "qcom,wsa-macro";
+ reg = <0x3240000 0x0>;
+ clock-names = "wsa_core_clk", "wsa_npl_clk";
+ clocks = <&clock_audio_wsa_1 0>,
+ <&clock_audio_wsa_2 0>;
+ qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
+ qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ swr0: wsa_swr_master {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ qcom,swr-master-version = <0x01050001>;
+ qcom,swr_master_id = <1>;
+ qcom,mipi-sdw-block-packing-mode = <0>;
+ swrm-io-base = <0x3250000 0x0>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq";
+ qcom,swr-num-ports = <8>;
+ qcom,swr-port-mapping = <1 SPKR_L 0x1>,
+ <2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
+ <4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
+ <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
+ <8 SPKR_R_VI 0x3>;
+ qcom,swr-num-dev = <2>;
+ wsa881x_0211: wsa881x@20170211 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x20170211>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+ qcom,bolero-handle = <&bolero>;
+ };
+
+ wsa881x_0212: wsa881x@20170212 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x20170212>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero>;
+ };
+
+ wsa881x_0213: wsa881x@21170213 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x21170213>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+ qcom,bolero-handle = <&bolero>;
+ };
+
+ wsa881x_0214: wsa881x@21170214 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x21170214>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero>;
+ };
+ };
+
+ };
+
+ wcd938x_codec: wcd938x-codec {
+ compatible = "qcom,wcd938x-codec";
+ qcom,split-codec = <1>;
+ qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
+ <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
+ <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
+ <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
+ <4 DSD_R 0x2 0 DSD_R>;
+ qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
+ <0 ADC2 0x2 0 ADC2>, <1 ADC3 0x1 0 ADC3>,
+ <1 ADC4 0x2 0 ADC4>, <2 DMIC0 0x1 0 DMIC0>,
+ <2 DMIC1 0x2 0 DMIC1>, <2 MBHC 0x4 0 DMIC2>,
+ <2 DMIC2 0x4 0 DMIC2>, <2 DMIC3 0x8 0 DMIC3>,
+ <3 DMIC4 0x1 0 DMIC4>, <3 DMIC5 0x2 0 DMIC5>,
+ <3 DMIC6 0x4 0 DMIC6>, <3 DMIC7 0x8 0 DMIC7>;
+
+ qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
+ qcom,rx-slave = <&wcd938x_rx_slave>;
+ qcom,tx-slave = <&wcd938x_tx_slave>;
+
+ cdc-vdd-rxtx-supply = <&S4A>;
+ qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-rxtx-current = <30000>;
+
+ cdc-vddio-supply = <&S4A>;
+ qcom,cdc-vddio-voltage = <1800000 1800000>;
+ qcom,cdc-vddio-current = <30000>;
+
+ cdc-vdd-buck-supply = <&S4A>;
+ qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-buck-current = <650000>;
+
+ cdc-vdd-mic-bias-supply = <&BOB>;
+ qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
+ qcom,cdc-vdd-mic-bias-current = <30000>;
+
+ qcom,cdc-micbias1-mv = <1800>;
+ qcom,cdc-micbias2-mv = <1800>;
+ qcom,cdc-micbias3-mv = <1800>;
+ qcom,cdc-micbias4-mv = <1800>;
+
+ qcom,cdc-static-supplies = "cdc-vdd-rxtx",
+ "cdc-vddio",
+ "cdc-vdd-buck",
+ "cdc-vdd-mic-bias";
+ };
+
+};
+
+&kona_snd {
+ qcom,model = "kona-mtp-snd-card";
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
+ qcom,wcn-bt = <1>;
+ qcom,ext-disp-audio-rx = <1>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic4",
+ "AMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Analog Mic5",
+ "TX DMIC0", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic0",
+ "TX DMIC1", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic1",
+ "TX DMIC2", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "TX DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "TX DMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "TX DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic4",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA DMIC4", "VA MIC BIAS4",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC0", "VA_SWR_CLK",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_ADC2", "VA_SWR_CLK",
+ "VA SWR_ADC3", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_ADC0", "ADC1_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT",
+ "VA SWR_ADC2", "ADC3_OUTPUT",
+ "VA SWR_ADC3", "ADC4_OUTPUT",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
+ qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
+ qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
+ asoc-codec = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
+ "msm-ext-disp-audio-codec-rx";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>,
+ <&wsa881x_0213>, <&wsa881x_0214>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+ "SpkrLeft", "SpkrRight";
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&wcd938x_codec>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
+ <&bolero>;
+};
+
+&q6core {
+ cdc_dmic01_gpios: cdc_dmic01_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
+ pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ cdc_dmic23_gpios: cdc_dmic23_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
+ pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ cdc_dmic45_gpios: cdc_dmic45_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
+ pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
+ qcom,lpi-gpios;
+ qcom,tlmm-gpio = <158>;
+ };
+
+ wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
+ pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ rx_swr_gpios: rx_swr_clk_data_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
+ &rx_swr_data1_active>;
+ pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
+ &rx_swr_data1_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ tx_swr_gpios: tx_swr_clk_data_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active
+ &tx_swr_data2_active>;
+ pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep
+ &tx_swr_data2_sleep>;
+ qcom,lpi-gpios;
+ qcom,tlmm-gpio = <147>;
+ };
+};
+
+&soc {
+ wsa_spkr_en1: wsa_spkr_en1_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ pinctrl-1 = <&spkr_1_sd_n_sleep>;
+ };
+
+ wsa_spkr_en2: wsa_spkr_en2_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&spkr_2_sd_n_active>;
+ pinctrl-1 = <&spkr_2_sd_n_sleep>;
+ };
+
+ wcd938x_rst_gpio: msm_cdc_pinctrl@32 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wcd938x_reset_active>;
+ pinctrl-1 = <&wcd938x_reset_sleep>;
+ };
+
+ clock_audio_wsa_1: wsa_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x309>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_wsa_2: wsa_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_3>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30A>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_rx_1: rx_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
+ qcom,codec-lpass-ext-clk-freq = <22579200>;
+ qcom,codec-lpass-clk-id = <0x30E>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_rx_2: rx_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>;
+ qcom,codec-lpass-ext-clk-freq = <22579200>;
+ qcom,codec-lpass-clk-id = <0x30F>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_tx_1: tx_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30C>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_tx_2: tx_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30D>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_va_1: va_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30B>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_va_2: va_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_8>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x310>;
+ #clock-cells = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-audio.dtsi
new file mode 100755
index 0000000..ae746f1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-audio.dtsi
@@ -0,0 +1,181 @@
+#include <dt-bindings/clock/qcom,audio-ext-clk.h>
+#include "msm-audio-lpass.dtsi"
+
+&msm_audio_ion {
+ iommus = <&apps_smmu 0x1801 0x0>;
+ qcom,smmu-sid-mask = /bits/ 64 <0xf>;
+};
+
+&soc {
+ qcom,avtimer@39f0000 {
+ compatible = "qcom,avtimer";
+ reg = <0x039f000c 0x4>,
+ <0x039f0010 0x4>;
+ reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
+ qcom,clk-div = <192>;
+ qcom,clk-mult = <10>;
+ };
+};
+
+&audio_apr {
+ q6core: qcom,q6core-audio {
+ compatible = "qcom,q6core-audio";
+
+ lpass_core_hw_vote: vote_lpass_core_hw {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_CORE_HW_VOTE>;
+ #clock-cells = <1>;
+ };
+
+ lpass_audio_hw_vote: vote_lpass_audio_hw {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_AUDIO_HW_VOTE>;
+ #clock-cells = <1>;
+ };
+
+ bolero: bolero-cdc {
+ compatible = "qcom,bolero-codec";
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ bolero-clk-rsc-mngr {
+ compatible = "qcom,bolero-clk-rsc-mngr";
+ };
+
+ tx_macro: tx-macro@3220000 {
+ swr2: tx_swr_master {
+ };
+ };
+
+ rx_macro: rx-macro@3200000 {
+ swr1: rx_swr_master {
+ };
+ };
+
+ wsa_macro: wsa-macro@3240000 {
+ swr0: wsa_swr_master {
+ };
+ };
+ };
+ };
+
+ voice_mhi_audio: qcom,voice-mhi-audio {
+ compatible = "qcom,voice-mhi-audio";
+ memory-region = <&mailbox_mem>;
+ voice_mhi_voting;
+ };
+};
+
+&q6core {
+ kona_snd: sound {
+ compatible = "qcom,kona-asoc-snd";
+ qcom,mi2s-audio-intf = <1>;
+ qcom,auxpcm-audio-intf = <1>;
+ qcom,tdm-audio-intf = <1>;
+ qcom,wcn-bt = <0>;
+ qcom,ext-disp-audio-rx = <0>;
+ qcom,afe-rxtx-lb = <0>;
+
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+
+ asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
+ <&loopback>, <&compress>, <&hostless>,
+ <&afe>, <&lsm>, <&routing>, <&compr>,
+ <&pcm_noirq>;
+ asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
+ "msm-pcm-dsp.2", "msm-voip-dsp",
+ "msm-pcm-voice", "msm-pcm-loopback",
+ "msm-compress-dsp", "msm-pcm-hostless",
+ "msm-pcm-afe", "msm-lsm-client",
+ "msm-pcm-routing", "msm-compr-dsp",
+ "msm-pcm-dsp-noirq";
+ asoc-cpu = <&dai_dp>, <&dai_dp1>,
+ <&dai_mi2s0>, <&dai_mi2s1>,
+ <&dai_mi2s2>, <&dai_mi2s3>,
+ <&dai_mi2s4>, <&dai_mi2s5>, <&dai_pri_auxpcm>,
+ <&dai_sec_auxpcm>, <&dai_tert_auxpcm>,
+ <&dai_quat_auxpcm>, <&dai_quin_auxpcm>,
+ <&dai_sen_auxpcm>,
+ <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>,
+ <&afe_proxy_tx>, <&incall_record_rx>,
+ <&incall_record_tx>, <&incall_music_rx>,
+ <&incall_music_2_rx>,
+ <&proxy_rx>, <&proxy_tx>,
+ <&usb_audio_rx>, <&usb_audio_tx>,
+ <&sb_7_rx>, <&sb_7_tx>,
+ <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>,
+ <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>,
+ <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>,
+ <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>,
+ <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>,
+ <&dai_sen_tdm_rx_0>, <&dai_sen_tdm_tx_0>,
+ <&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>,
+ <&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>,
+ <&wsa_cdc_dma_2_tx>,
+ <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>,
+ <&va_cdc_dma_2_tx>,
+ <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>,
+ <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>,
+ <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>,
+ <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>,
+ <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>,
+ <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>,
+ <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>,
+ <&afe_loopback_tx>;
+ asoc-cpu-names = "msm-dai-q6-dp.0", "msm-dai-q6-dp.1",
+ "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",
+ "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",
+ "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5",
+ "msm-dai-q6-auxpcm.1",
+ "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3",
+ "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5",
+ "msm-dai-q6-auxpcm.6", "msm-dai-q6-dev.224",
+ "msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
+ "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
+ "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
+ "msm-dai-q6-dev.32770",
+ "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195",
+ "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673",
+ "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399",
+ "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865",
+ "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881",
+ "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897",
+ "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913",
+ "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929",
+ "msm-dai-q6-tdm.36944", "msm-dai-q6-tdm.36945",
+ "msm-dai-cdc-dma-dev.45056",
+ "msm-dai-cdc-dma-dev.45057",
+ "msm-dai-cdc-dma-dev.45058",
+ "msm-dai-cdc-dma-dev.45059",
+ "msm-dai-cdc-dma-dev.45061",
+ "msm-dai-cdc-dma-dev.45089",
+ "msm-dai-cdc-dma-dev.45091",
+ "msm-dai-cdc-dma-dev.45093",
+ "msm-dai-cdc-dma-dev.45104",
+ "msm-dai-cdc-dma-dev.45105",
+ "msm-dai-cdc-dma-dev.45106",
+ "msm-dai-cdc-dma-dev.45107",
+ "msm-dai-cdc-dma-dev.45108",
+ "msm-dai-cdc-dma-dev.45109",
+ "msm-dai-cdc-dma-dev.45110",
+ "msm-dai-cdc-dma-dev.45111",
+ "msm-dai-cdc-dma-dev.45112",
+ "msm-dai-cdc-dma-dev.45113",
+ "msm-dai-cdc-dma-dev.45114",
+ "msm-dai-cdc-dma-dev.45115",
+ "msm-dai-cdc-dma-dev.45116",
+ "msm-dai-cdc-dma-dev.45118",
+ "msm-dai-q6-dev.24577";
+ fsa4480-i2c-handle = <&fsa4480>;
+ };
+};
+
+&qupv3_se15_i2c {
+ status = "ok";
+ fsa4480: fsa4480@43 {
+ compatible = "qcom,fsa4480-i2c";
+ reg = <0x43>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-bus.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-bus.dtsi
new file mode 100755
index 0000000..a730648
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-bus.dtsi
@@ -0,0 +1,2250 @@
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ ad_hoc_bus: ad-hoc-bus {
+ compatible = "qcom,msm-bus-device";
+ reg = <0x016E0000 0x1f180>,
+ <0x1700000 0x3d180>,
+ <0x1500000 0x28000>,
+ <0x90C0000 0x4200>,
+ <0x9100000 0xae200>,
+ <0x9100000 0xae200>,
+ <0x1740000 0x1f080>,
+ <0x1620000 0x1c200>,
+ <0x1620000 0x40000>,
+ <0x1700000 0x3d180>,
+ <0x9990000 0x1600>;
+
+ reg-names = "aggre1_noc-base", "aggre2_noc-base",
+ "config_noc-base", "dc_noc-base",
+ "mc_virt-base", "gem_noc-base",
+ "mmss_noc-base", "system_noc-base",
+ "ipa_virt-base", "compute_noc-base", "npu_noc-base";
+
+ /*RSCs*/
+ rsc_apps: rsc-apps {
+ cell-id = <MSM_BUS_RSC_APPS>;
+ label = "apps_rsc";
+ qcom,rsc-dev;
+ qcom,req_state = <2>;
+ };
+
+ rsc_disp: rsc-disp {
+ cell-id = <MSM_BUS_RSC_DISP>;
+ label = "disp_rsc";
+ qcom,rsc-dev;
+ qcom,req_state = <2>;
+ };
+
+ /*BCMs*/
+ bcm_acv: bcm-acv {
+ cell-id = <MSM_BUS_BCM_ACV>;
+ label = "ACV";
+ qcom,bcm-name = "ACV";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_alc: bcm-alc {
+ cell-id = <MSM_BUS_BCM_ALC>;
+ label = "ALC";
+ qcom,bcm-name = "ALC";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mc0: bcm-mc0 {
+ cell-id = <MSM_BUS_BCM_MC0>;
+ label = "MC0";
+ qcom,bcm-name = "MC0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh0: bcm-sh0 {
+ cell-id = <MSM_BUS_BCM_SH0>;
+ label = "SH0";
+ qcom,bcm-name = "SH0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm0: bcm-mm0 {
+ cell-id = <MSM_BUS_BCM_MM0>;
+ label = "MM0";
+ qcom,bcm-name = "MM0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_ce0: bcm-ce0 {
+ cell-id = <MSM_BUS_BCM_CE0>;
+ label = "CE0";
+ qcom,bcm-name = "CE0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_ip0: bcm-ip0 {
+ cell-id = <MSM_BUS_BCM_IP0>;
+ label = "IP0";
+ qcom,bcm-name = "IP0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm1: bcm-mm1 {
+ cell-id = <MSM_BUS_BCM_MM1>;
+ label = "MM1";
+ qcom,bcm-name = "MM1";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh2: bcm-sh2 {
+ cell-id = <MSM_BUS_BCM_SH2>;
+ label = "SH2";
+ qcom,bcm-name = "SH2";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm2: bcm-mm2 {
+ cell-id = <MSM_BUS_BCM_MM2>;
+ label = "MM2";
+ qcom,bcm-name = "MM2";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_qup0: bcm-qup0 {
+ cell-id = <MSM_BUS_BCM_QUP0>;
+ label = "QUP0";
+ qcom,bcm-name = "QUP0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh3: bcm-sh3 {
+ cell-id = <MSM_BUS_BCM_SH3>;
+ label = "SH3";
+ qcom,bcm-name = "SH3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm3: bcm-mm3 {
+ cell-id = <MSM_BUS_BCM_MM3>;
+ label = "MM3";
+ qcom,bcm-name = "MM3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh4: bcm-sh4 {
+ cell-id = <MSM_BUS_BCM_SH4>;
+ label = "SH4";
+ qcom,bcm-name = "SH4";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn0: bcm-sn0 {
+ cell-id = <MSM_BUS_BCM_SN0>;
+ label = "SN0";
+ qcom,bcm-name = "SN0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_co0: bcm-co0 {
+ cell-id = <MSM_BUS_BCM_CO0>;
+ label = "CO0";
+ qcom,bcm-name = "CO0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_cn0: bcm-cn0 {
+ cell-id = <MSM_BUS_BCM_CN0>;
+ label = "CN0";
+ qcom,bcm-name = "CN0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn1: bcm-sn1 {
+ cell-id = <MSM_BUS_BCM_SN1>;
+ label = "SN1";
+ qcom,bcm-name = "SN1";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn2: bcm-sn2 {
+ cell-id = <MSM_BUS_BCM_SN2>;
+ label = "SN2";
+ qcom,bcm-name = "SN2";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_co2: bcm-co2 {
+ cell-id = <MSM_BUS_BCM_CO2>;
+ label = "CO2";
+ qcom,bcm-name = "CO2";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn3: bcm-sn3 {
+ cell-id = <MSM_BUS_BCM_SN3>;
+ label = "SN3";
+ qcom,bcm-name = "SN3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn4: bcm-sn4 {
+ cell-id = <MSM_BUS_BCM_SN4>;
+ label = "SN4";
+ qcom,bcm-name = "SN4";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn5: bcm-sn5 {
+ cell-id = <MSM_BUS_BCM_SN5>;
+ label = "SN5";
+ qcom,bcm-name = "SN5";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn6: bcm-sn6 {
+ cell-id = <MSM_BUS_BCM_SN6>;
+ label = "SN6";
+ qcom,bcm-name = "SN6";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn7: bcm-sn7 {
+ cell-id = <MSM_BUS_BCM_SN7>;
+ label = "SN7";
+ qcom,bcm-name = "SN7";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn8: bcm-sn8 {
+ cell-id = <MSM_BUS_BCM_SN8>;
+ label = "SN8";
+ qcom,bcm-name = "SN8";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn9: bcm-sn9 {
+ cell-id = <MSM_BUS_BCM_SN9>;
+ label = "SN9";
+ qcom,bcm-name = "SN9";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn11: bcm-sn11 {
+ cell-id = <MSM_BUS_BCM_SN11>;
+ label = "SN11";
+ qcom,bcm-name = "SN11";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn12: bcm-sn12 {
+ cell-id = <MSM_BUS_BCM_SN12>;
+ label = "SN12";
+ qcom,bcm-name = "SN12";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_acv_display: bcm-acv_display {
+ cell-id = <MSM_BUS_BCM_ACV_DISPLAY>;
+ label = "ACV_DISPLAY";
+ qcom,bcm-name = "ACV";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_alc_display: bcm-alc_display {
+ cell-id = <MSM_BUS_BCM_ALC_DISPLAY>;
+ label = "ALC_DISPLAY";
+ qcom,bcm-name = "ALC";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mc0_display: bcm-mc0_display {
+ cell-id = <MSM_BUS_BCM_MC0_DISPLAY>;
+ label = "MC0_DISPLAY";
+ qcom,bcm-name = "MC0";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh0_display: bcm-sh0_display {
+ cell-id = <MSM_BUS_BCM_SH0_DISPLAY>;
+ label = "SH0_DISPLAY";
+ qcom,bcm-name = "SH0";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm0_display: bcm-mm0_display {
+ cell-id = <MSM_BUS_BCM_MM0_DISPLAY>;
+ label = "MM0_DISPLAY";
+ qcom,bcm-name = "MM0";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm1_display: bcm-mm1_display {
+ cell-id = <MSM_BUS_BCM_MM1_DISPLAY>;
+ label = "MM1_DISPLAY";
+ qcom,bcm-name = "MM1";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm2_display: bcm-mm2_display {
+ cell-id = <MSM_BUS_BCM_MM2_DISPLAY>;
+ label = "MM2_DISPLAY";
+ qcom,bcm-name = "MM2";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+
+ /*Buses*/
+ fab_aggre1_noc: fab-aggre1_noc {
+ cell-id = <MSM_BUS_FAB_A1_NOC>;
+ label = "fab-aggre1_noc";
+ qcom,fab-dev;
+ qcom,base-name = "aggre1_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <8192>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_aggre2_noc: fab-aggre2_noc {
+ cell-id = <MSM_BUS_FAB_A2_NOC>;
+ label = "fab-aggre2_noc";
+ qcom,fab-dev;
+ qcom,base-name = "aggre2_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <12288>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_compute_noc: fab-compute_noc {
+ cell-id = <MSM_BUS_FAB_COMP_NOC>;
+ label = "fab-compute_noc";
+ qcom,fab-dev;
+ qcom,base-name = "compute_noc-base";
+ qcom,qos-off = <2048>;
+ qcom,base-offset = <208896>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_config_noc: fab-config_noc {
+ cell-id = <MSM_BUS_FAB_CONFIG_NOC>;
+ label = "fab-config_noc";
+ qcom,fab-dev;
+ qcom,base-name = "config_noc-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <24576>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_dc_noc: fab-dc_noc {
+ cell-id = <MSM_BUS_FAB_DC_NOC>;
+ label = "fab-dc_noc";
+ qcom,fab-dev;
+ qcom,base-name = "dc_noc-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_gem_noc: fab-gem_noc {
+ cell-id = <MSM_BUS_FAB_GEM_NOC>;
+ label = "fab-gem_noc";
+ qcom,fab-dev;
+ qcom,base-name = "gem_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <135168>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_ipa_virt: fab-ipa_virt {
+ cell-id = <MSM_BUS_FAB_IPA_VIRT>;
+ label = "fab-ipa_virt";
+ qcom,fab-dev;
+ qcom,base-name = "ipa_virt-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ clocks = <>;
+ };
+
+ fab_mc_virt: fab-mc_virt {
+ cell-id = <MSM_BUS_FAB_MC_VIRT>;
+ label = "fab-mc_virt";
+ qcom,fab-dev;
+ qcom,base-name = "mc_virt-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ clocks = <>;
+ };
+
+ fab_mmss_noc: fab-mmss_noc {
+ cell-id = <MSM_BUS_FAB_MMSS_NOC>;
+ label = "fab-mmss_noc";
+ qcom,fab-dev;
+ qcom,base-name = "mmss_noc-base";
+ qcom,qos-off = <2048>;
+ qcom,base-offset = <40960>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_npu_noc: fab-npu_noc {
+ cell-id = <MSM_BUS_FAB_NPU_NOC>;
+ label = "fab-npu_noc";
+ qcom,fab-dev;
+ qcom,base-name = "npu_noc-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_system_noc: fab-system_noc {
+ cell-id = <MSM_BUS_FAB_SYS_NOC>;
+ label = "fab-system_noc";
+ qcom,fab-dev;
+ qcom,base-name = "system_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <73728>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_gem_noc_display: fab-gem_noc_display {
+ cell-id = <MSM_BUS_FAB_GEM_NOC_DISPLAY>;
+ label = "fab-gem_noc_display";
+ qcom,fab-dev;
+ qcom,base-name = "gem_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <135168>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_mc_virt_display: fab-mc_virt_display {
+ cell-id = <MSM_BUS_FAB_MC_VIRT_DISPLAY>;
+ label = "fab-mc_virt_display";
+ qcom,fab-dev;
+ qcom,base-name = "mc_virt-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ clocks = <>;
+ };
+
+ fab_mmss_noc_display: fab-mmss_noc_display {
+ cell-id = <MSM_BUS_FAB_MMSS_NOC_DISPLAY>;
+ label = "fab-mmss_noc_display";
+ qcom,fab-dev;
+ qcom,base-name = "mmss_noc-base";
+ qcom,qos-off = <2048>;
+ qcom,base-offset = <40960>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+
+ /*Masters*/
+
+ mas_qhm_a1noc_cfg: mas-qhm-a1noc-cfg {
+ cell-id = <MSM_BUS_MASTER_A1NOC_CFG>;
+ label = "mas-qhm-a1noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_aggre1_noc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ };
+
+ mas_qhm_qspi: mas-qhm-qspi {
+ cell-id = <MSM_BUS_MASTER_QSPI_0>;
+ label = "mas-qhm-qspi";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <7>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_qhm_qup1: mas-qhm-qup1 {
+ cell-id = <MSM_BUS_MASTER_QUP_1>;
+ label = "mas-qhm-qup1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <5>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,bcms = <&bcm_qup0>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_qhm_qup2: mas-qhm-qup2 {
+ cell-id = <MSM_BUS_MASTER_QUP_2>;
+ label = "mas-qhm-qup2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <6>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,bcms = <&bcm_qup0>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_qhm_tsif: mas-qhm-tsif {
+ cell-id = <MSM_BUS_MASTER_TSIF>;
+ label = "mas-qhm-tsif";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <8>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_pcie3_modem: mas-xm-pcie3-modem {
+ cell-id = <MSM_BUS_MASTER_PCIE_2>;
+ label = "mas-xm-pcie3-modem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <4>;
+ qcom,connections = <&slv_qns_pcie_modem_mem_noc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_sdc4: mas-xm-sdc4 {
+ cell-id = <MSM_BUS_MASTER_SDCC_4>;
+ label = "mas-xm-sdc4";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <2>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_ufs_mem: mas-xm-ufs-mem {
+ cell-id = <MSM_BUS_MASTER_UFS_MEM>;
+ label = "mas-xm-ufs-mem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <3>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,node-qos-clks {
+ clocks =
+ <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
+ clock-names =
+ "clk-aggre-ufs-phy-axi-no-rate";
+ };
+ };
+
+ mas_xm_usb3_0: mas-xm-usb3-0 {
+ cell-id = <MSM_BUS_MASTER_USB3>;
+ label = "mas-xm-usb3-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <0>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,node-qos-clks {
+ clocks =
+ <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+ clock-names =
+ "clk-usb3-prim-axi-no-rate";
+ };
+ };
+
+ mas_xm_usb3_1: mas-xm-usb3-1 {
+ cell-id = <MSM_BUS_MASTER_USB3_1>;
+ label = "mas-xm-usb3-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <1>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,node-qos-clks {
+ clocks =
+ <&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
+ clock-names =
+ "clk-usb3-sec-axi-no-rate";
+ };
+ };
+
+ mas_qhm_a2noc_cfg: mas-qhm-a2noc-cfg {
+ cell-id = <MSM_BUS_MASTER_A2NOC_CFG>;
+ label = "mas-qhm-a2noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_aggre2_noc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ };
+
+ mas_qhm_qdss_bam: mas-qhm-qdss-bam {
+ cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
+ label = "mas-qhm-qdss-bam";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <11>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_qhm_qup0: mas-qhm-qup0 {
+ cell-id = <MSM_BUS_MASTER_QUP_0>;
+ label = "mas-qhm-qup0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <12>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,bcms = <&bcm_qup0>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_qnm_cnoc: mas-qnm-cnoc {
+ cell-id = <MSM_BUS_MASTER_CNOC_A2NOC>;
+ label = "mas-qnm-cnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <0>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,forwarding;
+ };
+
+ mas_qxm_crypto: mas-qxm-crypto {
+ cell-id = <MSM_BUS_MASTER_CRYPTO_CORE_0>;
+ label = "mas-qxm-crypto";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <1>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,bcms = <&bcm_ce0>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,forwarding;
+ };
+
+ mas_qxm_ipa: mas-qxm-ipa {
+ cell-id = <MSM_BUS_MASTER_IPA>;
+ label = "mas-qxm-ipa";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <2>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,forwarding;
+ qcom,defer-init-qos;
+ qcom,node-qos-bcms = <7035 0 1>;
+ };
+
+ mas_xm_pcie3_0: mas-xm-pcie3-0 {
+ cell-id = <MSM_BUS_MASTER_PCIE>;
+ label = "mas-xm-pcie3-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <8>;
+ qcom,connections = <&slv_qns_pcie_mem_noc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_pcie3_1: mas-xm-pcie3-1 {
+ cell-id = <MSM_BUS_MASTER_PCIE_1>;
+ label = "mas-xm-pcie3-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <9>;
+ qcom,connections = <&slv_qns_pcie_mem_noc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_qdss_etr: mas-xm-qdss-etr {
+ cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
+ label = "mas-xm-qdss-etr";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <7>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_sdc2: mas-xm-sdc2 {
+ cell-id = <MSM_BUS_MASTER_SDCC_2>;
+ label = "mas-xm-sdc2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <3>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_ufs_card: mas-xm-ufs-card {
+ cell-id = <MSM_BUS_MASTER_UFS_CARD>;
+ label = "mas-xm-ufs-card";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <4>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,blacklist = <&slv_qns_cnoc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_qnm_npu: mas-qnm-npu {
+ cell-id = <MSM_BUS_MASTER_NPU>;
+ label = "mas-qnm-npu";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <6 7>;
+ qcom,connections = <&slv_qns_cdsp_mem_noc>;
+ qcom,bus-dev = <&fab_compute_noc>;
+ qcom,bcms = <&bcm_co2>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_qnm_snoc: mas-qnm-snoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_MAS>;
+ label = "mas-qnm-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_compute_dsp
+ &slv_qhs_camera_cfg &slv_qhs_tlmm1
+ &slv_qhs_tlmm0 &slv_qhs_sdc4
+ &slv_qhs_tlmm2 &slv_qhs_sdc2
+ &slv_qhs_mnoc_cfg &slv_qhs_ufs_mem_cfg
+ &slv_qhs_snoc_cfg &slv_qhs_pdm
+ &slv_qhs_cx_rdpm &slv_qhs_pcie1_cfg
+ &slv_qhs_a2_noc_cfg &slv_qhs_qdss_cfg
+ &slv_qhs_display_cfg &slv_qhs_pcie_modem_cfg
+ &slv_qhs_tcsr &slv_qhs_dcc_cfg
+ &slv_qhs_ddrss_cfg &slv_qhs_ipc_router
+ &slv_qhs_pcie0_cfg &slv_qhs_cpr_mmcx
+ &slv_qhs_npu_cfg &slv_qhs_ahb2phy0
+ &slv_qhs_ahb2phy1 &slv_qhs_gpuss_cfg
+ &slv_qhs_venus_cfg &slv_qhs_tsif
+ &slv_qhs_ipa &slv_qhs_imem_cfg
+ &slv_qhs_usb3_0 &slv_srvc_cnoc
+ &slv_qhs_ufs_card_cfg &slv_qhs_usb3_1
+ &slv_qhs_lpass_cfg &slv_qhs_cpr_cx
+ &slv_qhs_a1_noc_cfg &slv_qhs_aoss
+ &slv_qhs_prng &slv_qhs_vsense_ctrl_cfg
+ &slv_qhs_qspi &slv_qhs_crypto0_cfg
+ &slv_qhs_pimem_cfg &slv_qhs_cpr_mx
+ &slv_qhs_qup0 &slv_qhs_qup1
+ &slv_qhs_qup2 &slv_qhs_clk_ctl>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ mas_xm_qdss_dap: mas-xm-qdss-dap {
+ cell-id = <MSM_BUS_MASTER_QDSS_DAP>;
+ label = "mas-xm-qdss-dap";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_compute_dsp
+ &slv_qhs_camera_cfg &slv_qhs_tlmm1
+ &slv_qhs_tlmm0 &slv_qhs_sdc4
+ &slv_qhs_tlmm2 &slv_qhs_sdc2
+ &slv_qhs_mnoc_cfg &slv_qhs_ufs_mem_cfg
+ &slv_qhs_snoc_cfg &slv_qhs_pdm
+ &slv_qhs_cx_rdpm &slv_qhs_pcie1_cfg
+ &slv_qhs_a2_noc_cfg &slv_qhs_qdss_cfg
+ &slv_qhs_display_cfg &slv_qhs_pcie_modem_cfg
+ &slv_qhs_tcsr &slv_qhs_dcc_cfg
+ &slv_qhs_ddrss_cfg &slv_qhs_ipc_router
+ &slv_qns_cnoc_a2noc &slv_qhs_pcie0_cfg
+ &slv_qhs_cpr_mmcx &slv_qhs_npu_cfg
+ &slv_qhs_ahb2phy0 &slv_qhs_ahb2phy1
+ &slv_qhs_gpuss_cfg &slv_qhs_venus_cfg
+ &slv_qhs_tsif &slv_qhs_ipa
+ &slv_qhs_imem_cfg &slv_qhs_usb3_0
+ &slv_srvc_cnoc &slv_qhs_ufs_card_cfg
+ &slv_qhs_usb3_1 &slv_qhs_lpass_cfg
+ &slv_qhs_cpr_cx &slv_qhs_a1_noc_cfg
+ &slv_qhs_aoss &slv_qhs_prng
+ &slv_qhs_vsense_ctrl_cfg &slv_qhs_qspi
+ &slv_qhs_crypto0_cfg &slv_qhs_pimem_cfg
+ &slv_qhs_cpr_mx &slv_qhs_qup0
+ &slv_qhs_qup1 &slv_qhs_qup2
+ &slv_qhs_clk_ctl>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ qcom,blacklist = <&slv_qns_gem_noc_snoc>;
+ };
+
+ mas_qhm_cnoc_dc_noc: mas-qhm-cnoc-dc-noc {
+ cell-id = <MSM_BUS_MASTER_CNOC_DC_NOC>;
+ label = "mas-qhm-cnoc-dc-noc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_memnoc &slv_qhs_llcc>;
+ qcom,bus-dev = <&fab_dc_noc>;
+ };
+
+ mas_alm_gpu_tcu: mas-alm-gpu-tcu {
+ cell-id = <MSM_BUS_MASTER_GPU_TCU>;
+ label = "mas-alm-gpu-tcu";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <127>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,bcms = <&bcm_sh2>;
+ qcom,ap-owned;
+ qcom,prio = <1>;
+ };
+
+ mas_alm_sys_tcu: mas-alm-sys-tcu {
+ cell-id = <MSM_BUS_MASTER_SYS_TCU>;
+ label = "mas-alm-sys-tcu";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <128>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,bcms = <&bcm_sh2>;
+ qcom,ap-owned;
+ qcom,prio = <6>;
+ };
+
+ mas_chm_apps: mas-chm-apps {
+ cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
+ label = "mas-chm-apps";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc &slv_qns_sys_pcie>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,bcms = <&bcm_sh4>;
+ };
+
+ mas_qhm_gemnoc_cfg: mas-qhm-gemnoc-cfg {
+ cell-id = <MSM_BUS_MASTER_GEM_NOC_CFG>;
+ label = "mas-qhm-gemnoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_odd_gemnoc
+ &slv_srvc_even_gemnoc &slv_srvc_sys_gemnoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ };
+
+ mas_qnm_cmpnoc: mas-qnm-cmpnoc {
+ cell-id = <MSM_BUS_MASTER_COMPUTE_NOC>;
+ label = "mas-qnm-cmpnoc";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <0 64>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,bcms = <&bcm_sh3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_qnm_gpu: mas-qnm-gpu {
+ cell-id = <MSM_BUS_MASTER_GRAPHICS_3D>;
+ label = "mas-qnm-gpu";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <1 65>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_qnm_mnoc_hf: mas-qnm-mnoc-hf {
+ cell-id = <MSM_BUS_MASTER_MNOC_HF_MEM_NOC>;
+ label = "mas-qnm-mnoc-hf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <2 66>;
+ qcom,connections = <&slv_qns_llcc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qnm_mnoc_sf: mas-qnm-mnoc-sf {
+ cell-id = <MSM_BUS_MASTER_MNOC_SF_MEM_NOC>;
+ label = "mas-qnm-mnoc-sf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <3 67>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qnm_pcie: mas-qnm-pcie {
+ cell-id = <MSM_BUS_MASTER_ANOC_PCIE_GEM_NOC>;
+ label = "mas-qnm-pcie";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <129>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_qnm_snoc_gc: mas-qnm-snoc-gc {
+ cell-id = <MSM_BUS_MASTER_SNOC_GC_MEM_NOC>;
+ label = "mas-qnm-snoc-gc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <130>;
+ qcom,connections = <&slv_qns_llcc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_qnm_snoc_sf: mas-qnm-snoc-sf {
+ cell-id = <MSM_BUS_MASTER_SNOC_SF_MEM_NOC>;
+ label = "mas-qnm-snoc-sf";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <131>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc &slv_qns_sys_pcie>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_ipa_core_master: mas-ipa-core-master {
+ cell-id = <MSM_BUS_MASTER_IPA_CORE>;
+ label = "mas-ipa-core-master";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_ipa_core_slave>;
+ qcom,bus-dev = <&fab_ipa_virt>;
+ };
+
+ mas_llcc_mc: mas-llcc-mc {
+ cell-id = <MSM_BUS_MASTER_LLCC>;
+ label = "mas-llcc-mc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <4>;
+ qcom,connections = <&slv_ebi>;
+ qcom,bus-dev = <&fab_mc_virt>;
+ };
+
+ mas_qhm_mnoc_cfg: mas-qhm-mnoc-cfg {
+ cell-id = <MSM_BUS_MASTER_CNOC_MNOC_CFG>;
+ label = "mas-qhm-mnoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_mnoc>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ };
+
+ mas_qnm_camnoc_hf: mas-qnm-camnoc-hf {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_HF>;
+ label = "mas-qnm-camnoc-hf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <4 5>;
+ qcom,connections = <&slv_qns_mem_noc_hf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm1>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qnm_camnoc_icp: mas-qnm-camnoc-icp {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_ICP>;
+ label = "mas-qnm-camnoc-icp";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <2>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <5>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qnm_camnoc_sf: mas-qnm-camnoc-sf {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_SF>;
+ label = "mas-qnm-camnoc-sf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <0 1>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qnm_video0: mas-qnm-video0 {
+ cell-id = <MSM_BUS_MASTER_VIDEO_P0>;
+ label = "mas-qnm-video0";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <12>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qnm_video1: mas-qnm-video1 {
+ cell-id = <MSM_BUS_MASTER_VIDEO_P1>;
+ label = "mas-qnm-video1";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <13>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qnm_video_cvp: mas-qnm-video-cvp {
+ cell-id = <MSM_BUS_MASTER_VIDEO_PROC>;
+ label = "mas-qnm-video-cvp";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <14>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qxm_mdp0: mas-qxm-mdp0 {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT0>;
+ label = "mas-qxm-mdp0";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <6>;
+ qcom,connections = <&slv_qns_mem_noc_hf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm1>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qxm_mdp1: mas-qxm-mdp1 {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT1>;
+ label = "mas-qxm-mdp1";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <8>;
+ qcom,connections = <&slv_qns_mem_noc_hf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm1>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qxm_rot: mas-qxm-rot {
+ cell-id = <MSM_BUS_MASTER_ROTATOR>;
+ label = "mas-qxm-rot";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <10>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_amm_npu_sys: mas-amm-npu-sys {
+ cell-id = <MSM_BUS_MASTER_NPU_SYS>;
+ label = "mas-amm-npu-sys";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <4>;
+ qcom,connections = <&slv_qns_npu_sys>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ mas_amm_npu_sys_cdp_w: mas-amm-npu-sys-cdp-w {
+ cell-id = <MSM_BUS_MASTER_NPU_CDP>;
+ label = "mas-amm-npu-sys-cdp-w";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <2>;
+ qcom,connections = <&slv_qns_npu_sys>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ mas_qhm_cfg: mas-qhm-cfg {
+ cell-id = <MSM_BUS_MASTER_NPU_NOC_CFG>;
+ label = "mas-qhm-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_noc
+ &slv_qhs_isense &slv_qhs_llm
+ &slv_qhs_dma_bwmon &slv_qhs_cp
+ &slv_qhs_tcm &slv_qhs_cal_dp0
+ &slv_qhs_cal_dp1 &slv_qhs_dpm>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ mas_qhm_snoc_cfg: mas-qhm-snoc-cfg {
+ cell-id = <MSM_BUS_MASTER_SNOC_CFG>;
+ label = "mas-qhm-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_snoc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ mas_qnm_aggre1_noc: mas-qnm-aggre1-noc {
+ cell-id = <MSM_BUS_A1NOC_SNOC_MAS>;
+ label = "mas-qnm-aggre1-noc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_gemnoc_sf>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn7>;
+ };
+
+ mas_qnm_aggre2_noc: mas-qnm-aggre2-noc {
+ cell-id = <MSM_BUS_A2NOC_SNOC_MAS>;
+ label = "mas-qnm-aggre2-noc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_gemnoc_sf>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn8>;
+ };
+
+ mas_qnm_gemnoc: mas-qnm-gemnoc {
+ cell-id = <MSM_BUS_MASTER_GEM_NOC_SNOC>;
+ label = "mas-qnm-gemnoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qxs_pimem
+ &slv_qxs_imem &slv_qhs_apss
+ &slv_qns_cnoc &slv_xs_sys_tcu_cfg
+ &slv_xs_qdss_stm>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn11>;
+ };
+
+ mas_qnm_gemnoc_pcie: mas-qnm-gemnoc-pcie {
+ cell-id = <MSM_BUS_MASTER_GEM_NOC_PCIE_SNOC>;
+ label = "mas-qnm-gemnoc-pcie";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_xs_pcie_modem
+ &slv_xs_pcie_0 &slv_xs_pcie_1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn9>;
+ };
+
+ mas_qxm_pimem: mas-qxm-pimem {
+ cell-id = <MSM_BUS_MASTER_PIMEM>;
+ label = "mas-qxm-pimem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <0>;
+ qcom,connections = <&slv_qns_gemnoc_gc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,forwarding;
+ };
+
+ mas_xm_gic: mas-xm-gic {
+ cell-id = <MSM_BUS_MASTER_GIC>;
+ label = "mas-xm-gic";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <1>;
+ qcom,connections = <&slv_qns_gemnoc_gc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,forwarding;
+ };
+
+ mas_alc: mas-alc {
+ cell-id = <MSM_BUS_MASTER_ALC>;
+ label = "mas-alc";
+ qcom,buswidth = <1>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mc_virt>;
+ qcom,bcms = <&bcm_alc>;
+ };
+
+ mas_qnm_mnoc_hf_display: mas-qnm-mnoc-hf_display {
+ cell-id = <MSM_BUS_MASTER_MNOC_HF_MEM_NOC_DISPLAY>;
+ label = "mas-qnm-mnoc-hf_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <2 66>;
+ qcom,connections = <&slv_qns_llcc_display>;
+ qcom,bus-dev = <&fab_gem_noc_display>;
+ };
+
+ mas_qnm_mnoc_sf_display: mas-qnm-mnoc-sf_display {
+ cell-id = <MSM_BUS_MASTER_MNOC_SF_MEM_NOC_DISPLAY>;
+ label = "mas-qnm-mnoc-sf_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <3 67>;
+ qcom,connections = <&slv_qns_llcc_display>;
+ qcom,bus-dev = <&fab_gem_noc_display>;
+ };
+
+ mas_llcc_mc_display: mas-llcc-mc_display {
+ cell-id = <MSM_BUS_MASTER_LLCC_DISPLAY>;
+ label = "mas-llcc-mc_display";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <4>;
+ qcom,connections = <&slv_ebi_display>;
+ qcom,bus-dev = <&fab_mc_virt_display>;
+ };
+
+ mas_qxm_mdp0_display: mas-qxm-mdp0_display {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT0_DISPLAY>;
+ label = "mas-qxm-mdp0_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <6>;
+ qcom,connections = <&slv_qns_mem_noc_hf_display>;
+ qcom,bus-dev = <&fab_mmss_noc_display>;
+ qcom,bcms = <&bcm_mm1_display>;
+ };
+
+ mas_qxm_mdp1_display: mas-qxm-mdp1_display {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT1_DISPLAY>;
+ label = "mas-qxm-mdp1_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <8>;
+ qcom,connections = <&slv_qns_mem_noc_hf_display>;
+ qcom,bus-dev = <&fab_mmss_noc_display>;
+ qcom,bcms = <&bcm_mm1_display>;
+ };
+
+ mas_qxm_rot_display: mas-qxm-rot_display {
+ cell-id = <MSM_BUS_MASTER_ROTATOR_DISPLAY>;
+ label = "mas-qxm-rot_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <10>;
+ qcom,connections = <&slv_qns_mem_noc_sf_display>;
+ qcom,bus-dev = <&fab_mmss_noc_display>;
+ };
+
+ /*Internal nodes*/
+
+ /*Slaves*/
+
+ slv_qns_a1noc_snoc:slv-qns-a1noc-snoc {
+ cell-id = <MSM_BUS_A1NOC_SNOC_SLV>;
+ label = "slv-qns-a1noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,connections = <&mas_qnm_aggre1_noc>;
+ };
+
+ slv_qns_pcie_modem_mem_noc:slv-qns-pcie-modem-mem-noc {
+ cell-id = <MSM_BUS_SLAVE_ANOC_PCIE_GEM_NOC_1>;
+ label = "slv-qns-pcie-modem-mem-noc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,connections = <&mas_qnm_pcie>;
+ qcom,bcms = <&bcm_sn12>;
+ };
+
+ slv_srvc_aggre1_noc:slv-srvc-aggre1-noc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_A1NOC>;
+ label = "slv-srvc-aggre1-noc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ };
+
+ slv_qns_a2noc_snoc:slv-qns-a2noc-snoc {
+ cell-id = <MSM_BUS_A2NOC_SNOC_SLV>;
+ label = "slv-qns-a2noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,connections = <&mas_qnm_aggre2_noc>;
+ };
+
+ slv_qns_pcie_mem_noc:slv-qns-pcie-mem-noc {
+ cell-id = <MSM_BUS_SLAVE_ANOC_PCIE_GEM_NOC>;
+ label = "slv-qns-pcie-mem-noc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,connections = <&mas_qnm_pcie>;
+ qcom,bcms = <&bcm_sn12>;
+ };
+
+ slv_srvc_aggre2_noc:slv-srvc-aggre2-noc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_A2NOC>;
+ label = "slv-srvc-aggre2-noc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ };
+
+ slv_qns_cdsp_mem_noc:slv-qns-cdsp-mem-noc {
+ cell-id = <MSM_BUS_SLAVE_CDSP_MEM_NOC>;
+ label = "slv-qns-cdsp-mem-noc";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_compute_noc>;
+ qcom,connections = <&mas_qnm_cmpnoc>;
+ qcom,bcms = <&bcm_co0>;
+ };
+
+ slv_qhs_a1_noc_cfg:slv-qhs-a1-noc-cfg {
+ cell-id = <MSM_BUS_SLAVE_A1NOC_CFG>;
+ label = "slv-qhs-a1-noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_a1noc_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_a2_noc_cfg:slv-qhs-a2-noc-cfg {
+ cell-id = <MSM_BUS_SLAVE_A2NOC_CFG>;
+ label = "slv-qhs-a2-noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_a2noc_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ahb2phy0:slv-qhs-ahb2phy0 {
+ cell-id = <MSM_BUS_SLAVE_AHB2PHY_SOUTH>;
+ label = "slv-qhs-ahb2phy0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ahb2phy1:slv-qhs-ahb2phy1 {
+ cell-id = <MSM_BUS_SLAVE_AHB2PHY_NORTH>;
+ label = "slv-qhs-ahb2phy1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_aoss:slv-qhs-aoss {
+ cell-id = <MSM_BUS_SLAVE_AOSS>;
+ label = "slv-qhs-aoss";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_camera_cfg:slv-qhs-camera-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_CFG>;
+ label = "slv-qhs-camera-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ qcom,disable-ports = <0 1 2>;
+ mmcx-supply = <&VDD_MMCX_LEVEL>;
+ node-reg-names = "mmcx";
+ };
+
+ slv_qhs_clk_ctl:slv-qhs-clk-ctl {
+ cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
+ label = "slv-qhs-clk-ctl";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_compute_dsp:slv-qhs-compute-dsp {
+ cell-id = <MSM_BUS_SLAVE_CDSP_CFG>;
+ label = "slv-qhs-compute-dsp";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_cpr_cx:slv-qhs-cpr-cx {
+ cell-id = <MSM_BUS_SLAVE_RBCPR_CX_CFG>;
+ label = "slv-qhs-cpr-cx";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_cpr_mmcx:slv-qhs-cpr-mmcx {
+ cell-id = <MSM_BUS_SLAVE_RBCPR_MMCX_CFG>;
+ label = "slv-qhs-cpr-mmcx";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_cpr_mx:slv-qhs-cpr-mx {
+ cell-id = <MSM_BUS_SLAVE_RBCPR_MX_CFG>;
+ label = "slv-qhs-cpr-mx";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_crypto0_cfg:slv-qhs-crypto0-cfg {
+ cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>;
+ label = "slv-qhs-crypto0-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_cx_rdpm:slv-qhs-cx-rdpm {
+ cell-id = <MSM_BUS_SLAVE_CX_RDPM>;
+ label = "slv-qhs-cx-rdpm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_dcc_cfg:slv-qhs-dcc-cfg {
+ cell-id = <MSM_BUS_SLAVE_DCC_CFG>;
+ label = "slv-qhs-dcc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ddrss_cfg:slv-qhs-ddrss-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_DDRSS>;
+ label = "slv-qhs-ddrss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_cnoc_dc_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_display_cfg:slv-qhs-display-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_CFG>;
+ label = "slv-qhs-display-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ qcom,disable-ports = <3 4>;
+ mmcx-supply = <&VDD_MMCX_LEVEL>;
+ node-reg-names = "mmcx";
+ };
+
+ slv_qhs_gpuss_cfg:slv-qhs-gpuss-cfg {
+ cell-id = <MSM_BUS_SLAVE_GRAPHICS_3D_CFG>;
+ label = "slv-qhs-gpuss-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_imem_cfg:slv-qhs-imem-cfg {
+ cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
+ label = "slv-qhs-imem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ipa:slv-qhs-ipa {
+ cell-id = <MSM_BUS_SLAVE_IPA_CFG>;
+ label = "slv-qhs-ipa";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ipc_router:slv-qhs-ipc-router {
+ cell-id = <MSM_BUS_SLAVE_IPC_ROUTER_CFG>;
+ label = "slv-qhs-ipc-router";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_lpass_cfg:slv-qhs-lpass-cfg {
+ cell-id = <MSM_BUS_SLAVE_LPASS>;
+ label = "slv-qhs-lpass-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_mnoc_cfg:slv-qhs-mnoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_MNOC_CFG>;
+ label = "slv-qhs-mnoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_mnoc_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_npu_cfg:slv-qhs-npu-cfg {
+ cell-id = <MSM_BUS_SLAVE_NPU_CFG>;
+ label = "slv-qhs-npu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_pcie0_cfg:slv-qhs-pcie0-cfg {
+ cell-id = <MSM_BUS_SLAVE_PCIE_0_CFG>;
+ label = "slv-qhs-pcie0-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_pcie1_cfg:slv-qhs-pcie1-cfg {
+ cell-id = <MSM_BUS_SLAVE_PCIE_1_CFG>;
+ label = "slv-qhs-pcie1-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_pcie_modem_cfg:slv-qhs-pcie-modem-cfg {
+ cell-id = <MSM_BUS_SLAVE_PCIE_2_CFG>;
+ label = "slv-qhs-pcie-modem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_pdm:slv-qhs-pdm {
+ cell-id = <MSM_BUS_SLAVE_PDM>;
+ label = "slv-qhs-pdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_pimem_cfg:slv-qhs-pimem-cfg {
+ cell-id = <MSM_BUS_SLAVE_PIMEM_CFG>;
+ label = "slv-qhs-pimem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_prng:slv-qhs-prng {
+ cell-id = <MSM_BUS_SLAVE_PRNG>;
+ label = "slv-qhs-prng";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_qdss_cfg:slv-qhs-qdss-cfg {
+ cell-id = <MSM_BUS_SLAVE_QDSS_CFG>;
+ label = "slv-qhs-qdss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_qspi:slv-qhs-qspi {
+ cell-id = <MSM_BUS_SLAVE_QSPI_0>;
+ label = "slv-qhs-qspi";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_qup0:slv-qhs-qup0 {
+ cell-id = <MSM_BUS_SLAVE_QUP_0>;
+ label = "slv-qhs-qup0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_qup1:slv-qhs-qup1 {
+ cell-id = <MSM_BUS_SLAVE_QUP_1>;
+ label = "slv-qhs-qup1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_qup2:slv-qhs-qup2 {
+ cell-id = <MSM_BUS_SLAVE_QUP_2>;
+ label = "slv-qhs-qup2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_sdc2:slv-qhs-sdc2 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_2>;
+ label = "slv-qhs-sdc2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_sdc4:slv-qhs-sdc4 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_4>;
+ label = "slv-qhs-sdc4";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_snoc_cfg:slv-qhs-snoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
+ label = "slv-qhs-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_snoc_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_tcsr:slv-qhs-tcsr {
+ cell-id = <MSM_BUS_SLAVE_TCSR>;
+ label = "slv-qhs-tcsr";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_tlmm0:slv-qhs-tlmm0 {
+ cell-id = <MSM_BUS_SLAVE_TLMM_NORTH>;
+ label = "slv-qhs-tlmm0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_tlmm1:slv-qhs-tlmm1 {
+ cell-id = <MSM_BUS_SLAVE_TLMM_SOUTH>;
+ label = "slv-qhs-tlmm1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_tlmm2:slv-qhs-tlmm2 {
+ cell-id = <MSM_BUS_SLAVE_TLMM_WEST>;
+ label = "slv-qhs-tlmm2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_tsif:slv-qhs-tsif {
+ cell-id = <MSM_BUS_SLAVE_TSIF>;
+ label = "slv-qhs-tsif";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ufs_card_cfg:slv-qhs-ufs-card-cfg {
+ cell-id = <MSM_BUS_SLAVE_UFS_CARD_CFG>;
+ label = "slv-qhs-ufs-card-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ufs_mem_cfg:slv-qhs-ufs-mem-cfg {
+ cell-id = <MSM_BUS_SLAVE_UFS_MEM_CFG>;
+ label = "slv-qhs-ufs-mem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_usb3_0:slv-qhs-usb3-0 {
+ cell-id = <MSM_BUS_SLAVE_USB3>;
+ label = "slv-qhs-usb3-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_usb3_1:slv-qhs-usb3-1 {
+ cell-id = <MSM_BUS_SLAVE_USB3_1>;
+ label = "slv-qhs-usb3-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_venus_cfg:slv-qhs-venus-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_CFG>;
+ label = "slv-qhs-venus-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ qcom,disable-ports = <5 6 7>;
+ mmcx-supply = <&VDD_MMCX_LEVEL>;
+ node-reg-names = "mmcx";
+ };
+
+ slv_qhs_vsense_ctrl_cfg:slv-qhs-vsense-ctrl-cfg {
+ cell-id = <MSM_BUS_SLAVE_VSENSE_CTRL_CFG>;
+ label = "slv-qhs-vsense-ctrl-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qns_cnoc_a2noc:slv-qns-cnoc-a2noc {
+ cell-id = <MSM_BUS_SLAVE_CNOC_A2NOC>;
+ label = "slv-qns-cnoc-a2noc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qnm_cnoc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_srvc_cnoc:slv-srvc-cnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_CNOC>;
+ label = "slv-srvc-cnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_llcc:slv-qhs-llcc {
+ cell-id = <MSM_BUS_SLAVE_LLCC_CFG>;
+ label = "slv-qhs-llcc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_dc_noc>;
+ };
+
+ slv_qhs_memnoc:slv-qhs-memnoc {
+ cell-id = <MSM_BUS_SLAVE_GEM_NOC_CFG>;
+ label = "slv-qhs-memnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_dc_noc>;
+ qcom,connections = <&mas_qhm_gemnoc_cfg>;
+ };
+
+ slv_qns_gem_noc_snoc:slv-qns-gem-noc-snoc {
+ cell-id = <MSM_BUS_SLAVE_GEM_NOC_SNOC>;
+ label = "slv-qns-gem-noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,connections = <&mas_qnm_gemnoc>;
+ };
+
+ slv_qns_llcc:slv-qns-llcc {
+ cell-id = <MSM_BUS_SLAVE_LLCC>;
+ label = "slv-qns-llcc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <4>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,connections = <&mas_llcc_mc>;
+ qcom,bcms = <&bcm_sh0>;
+ };
+
+ slv_qns_sys_pcie:slv-qns-sys-pcie {
+ cell-id = <MSM_BUS_SLAVE_MEM_NOC_PCIE_SNOC>;
+ label = "slv-qns-sys-pcie";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,connections = <&mas_qnm_gemnoc_pcie>;
+ };
+
+ slv_srvc_even_gemnoc:slv-srvc-even-gemnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_GEM_NOC_1>;
+ label = "slv-srvc-even-gemnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ };
+
+ slv_srvc_odd_gemnoc:slv-srvc-odd-gemnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_GEM_NOC_2>;
+ label = "slv-srvc-odd-gemnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ };
+
+ slv_srvc_sys_gemnoc:slv-srvc-sys-gemnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_GEM_NOC>;
+ label = "slv-srvc-sys-gemnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ };
+
+ slv_ipa_core_slave:slv-ipa-core-slave {
+ cell-id = <MSM_BUS_SLAVE_IPA_CORE>;
+ label = "slv-ipa-core-slave";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_ipa_virt>;
+ qcom,bcms = <&bcm_ip0>;
+ };
+
+ slv_ebi:slv-ebi {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ label = "slv-ebi";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <4>;
+ qcom,bus-dev = <&fab_mc_virt>;
+ qcom,bcms = <&bcm_mc0>, <&bcm_acv>;
+ };
+
+ slv_qns_mem_noc_hf:slv-qns-mem-noc-hf {
+ cell-id = <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>;
+ label = "slv-qns-mem-noc-hf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,connections = <&mas_qnm_mnoc_hf>;
+ qcom,bcms = <&bcm_mm0>;
+ };
+
+ slv_qns_mem_noc_sf:slv-qns-mem-noc-sf {
+ cell-id = <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>;
+ label = "slv-qns-mem-noc-sf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,connections = <&mas_qnm_mnoc_sf>;
+ qcom,bcms = <&bcm_mm2>;
+ };
+
+ slv_srvc_mnoc:slv-srvc-mnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_MNOC>;
+ label = "slv-srvc-mnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ };
+
+ slv_qhs_cal_dp0:slv-qhs-cal-dp0 {
+ cell-id = <MSM_BUS_SLAVE_NPU_CAL_DP0>;
+ label = "slv-qhs-cal-dp0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_cal_dp1:slv-qhs-cal-dp1 {
+ cell-id = <MSM_BUS_SLAVE_NPU_CAL_DP1>;
+ label = "slv-qhs-cal-dp1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_cp:slv-qhs-cp {
+ cell-id = <MSM_BUS_SLAVE_NPU_CP>;
+ label = "slv-qhs-cp";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_dma_bwmon:slv-qhs-dma-bwmon {
+ cell-id = <MSM_BUS_SLAVE_NPU_INT_DMA_BWMON_CFG>;
+ label = "slv-qhs-dma-bwmon";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_dpm:slv-qhs-dpm {
+ cell-id = <MSM_BUS_SLAVE_NPU_DPM>;
+ label = "slv-qhs-dpm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_isense:slv-qhs-isense {
+ cell-id = <MSM_BUS_SLAVE_ISENSE_CFG>;
+ label = "slv-qhs-isense";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_llm:slv-qhs-llm {
+ cell-id = <MSM_BUS_SLAVE_NPU_LLM_CFG>;
+ label = "slv-qhs-llm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_tcm:slv-qhs-tcm {
+ cell-id = <MSM_BUS_SLAVE_NPU_TCM>;
+ label = "slv-qhs-tcm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qns_npu_sys:slv-qns-npu-sys {
+ cell-id = <MSM_BUS_SLAVE_NPU_COMPUTE_NOC>;
+ label = "slv-qns-npu-sys";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_srvc_noc:slv-srvc-noc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_NPU_NOC>;
+ label = "slv-srvc-noc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_apss:slv-qhs-apss {
+ cell-id = <MSM_BUS_SLAVE_APPSS>;
+ label = "slv-qhs-apss";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ slv_qns_cnoc:slv-qns-cnoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_SLV>;
+ label = "slv-qns-cnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_snoc>;
+ };
+
+ slv_qns_gemnoc_gc:slv-qns-gemnoc-gc {
+ cell-id = <MSM_BUS_SLAVE_SNOC_GEM_NOC_GC>;
+ label = "slv-qns-gemnoc-gc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_snoc_gc>;
+ qcom,bcms = <&bcm_sn2>;
+ };
+
+ slv_qns_gemnoc_sf:slv-qns-gemnoc-sf {
+ cell-id = <MSM_BUS_SLAVE_SNOC_GEM_NOC_SF>;
+ label = "slv-qns-gemnoc-sf";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_snoc_sf>;
+ qcom,bcms = <&bcm_sn0>;
+ };
+
+ slv_qxs_imem:slv-qxs-imem {
+ cell-id = <MSM_BUS_SLAVE_OCIMEM>;
+ label = "slv-qxs-imem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn1>;
+ };
+
+ slv_qxs_pimem:slv-qxs-pimem {
+ cell-id = <MSM_BUS_SLAVE_PIMEM>;
+ label = "slv-qxs-pimem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn3>;
+ };
+
+ slv_srvc_snoc:slv-srvc-snoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_SNOC>;
+ label = "slv-srvc-snoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ slv_xs_pcie_0:slv-xs-pcie-0 {
+ cell-id = <MSM_BUS_SLAVE_PCIE_0>;
+ label = "slv-xs-pcie-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn6>;
+ };
+
+ slv_xs_pcie_1:slv-xs-pcie-1 {
+ cell-id = <MSM_BUS_SLAVE_PCIE_1>;
+ label = "slv-xs-pcie-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn6>;
+ };
+
+ slv_xs_pcie_modem:slv-xs-pcie-modem {
+ cell-id = <MSM_BUS_SLAVE_PCIE_2>;
+ label = "slv-xs-pcie-modem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn5>;
+ };
+
+ slv_xs_qdss_stm:slv-xs-qdss-stm {
+ cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
+ label = "slv-xs-qdss-stm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn4>;
+ };
+
+ slv_xs_sys_tcu_cfg:slv-xs-sys-tcu-cfg {
+ cell-id = <MSM_BUS_SLAVE_TCU>;
+ label = "slv-xs-sys-tcu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ slv_qns_llcc_display:slv-qns-llcc_display {
+ cell-id = <MSM_BUS_SLAVE_LLCC_DISPLAY>;
+ label = "slv-qns-llcc_display";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <4>;
+ qcom,bus-dev = <&fab_gem_noc_display>;
+ qcom,connections = <&mas_llcc_mc_display>;
+ qcom,bcms = <&bcm_sh0_display>;
+ };
+
+ slv_ebi_display:slv-ebi_display {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0_DISPLAY>;
+ label = "slv-ebi_display";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <4>;
+ qcom,bus-dev = <&fab_mc_virt_display>;
+ qcom,bcms = <&bcm_mc0_display>, <&bcm_acv_display>;
+ };
+
+ slv_qns_mem_noc_hf_display:slv-qns-mem-noc-hf_display {
+ cell-id = <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC_DISPLAY>;
+ label = "slv-qns-mem-noc-hf_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_mmss_noc_display>;
+ qcom,connections = <&mas_qnm_mnoc_hf_display>;
+ qcom,bcms = <&bcm_mm0_display>;
+ };
+
+ slv_qns_mem_noc_sf_display:slv-qns-mem-noc-sf_display {
+ cell-id = <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC_DISPLAY>;
+ label = "slv-qns-mem-noc-sf_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_mmss_noc_display>;
+ qcom,connections = <&mas_qnm_mnoc_sf_display>;
+ qcom,bcms = <&bcm_mm2_display>;
+ };
+ };
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd-overlay.dts
new file mode 100755
index 0000000..5e4e20c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd-overlay.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "kona-cdp-lcd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona CDP (LCD)";
+ compatible = "qcom,kona-cdp", "qcom,kona", "qcom,cdp";
+ qcom,board-id = <0x10101 0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd-tron-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd-tron-overlay.dts
new file mode 100755
index 0000000..efee808
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd-tron-overlay.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include "kona-cdp-lcd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona CDP (LCD) tron";
+ compatible = "qcom,kona-cdp", "qcom,kona", "qcom,cdp";
+ qcom,board-id = <0x01020001 0>;
+};
+
+&mdm0 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd-tron.dts b/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd-tron.dts
new file mode 100755
index 0000000..b367423
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd-tron.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+#include "kona.dtsi"
+#include "kona-cdp-lcd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona CDP (LCD) tron";
+ compatible = "qcom,kona-cdp", "qcom,kona", "qcom,cdp";
+ qcom,board-id = <0x01020001 0>;
+};
+
+&mdm0 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd.dts b/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd.dts
new file mode 100755
index 0000000..d1e2288d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona.dtsi"
+#include "kona-cdp-lcd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona CDP (LCD)";
+ compatible = "qcom,kona-cdp", "qcom,kona", "qcom,cdp";
+ qcom,board-id = <0x10101 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd.dtsi
new file mode 100755
index 0000000..c5013f2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-cdp-lcd.dtsi
@@ -0,0 +1,183 @@
+#include "kona-cdp.dtsi"
+
+&pm8150a_amoled {
+ status = "disabled";
+};
+
+&pm8150l_lcdb {
+ status = "ok";
+};
+
+&pm8150l_wled {
+ qcom,string-cfg = <7>;
+ status = "ok";
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x77>;
+ qcom,mdss-dsi-panel-on-check-value = <0x77>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ /delete-property/ qcom,platform-en-gpio;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0c];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x77>;
+ qcom,mdss-dsi-panel-on-check-value = <0x77>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-qsync-min-refresh-rate = <55>;
+ /delete-property/ qcom,platform-en-gpio;
+};
+
+&dsi_nt36672e_fhd_plus_60_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ /delete-property/ qcom,platform-en-gpio;
+};
+
+&dsi_sharp_qsync_wqhd_cmd {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ /delete-property/ qcom,platform-en-gpio;
+};
+
+&dsi_sharp_qsync_wqhd_video {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ /delete-property/ qcom,platform-en-gpio;
+};
+
+&dsi_sharp_1080_cmd {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&dsi_dual_nt35597_truly_cmd {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&dsi_dual_nt35597_truly_video {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+};
+
+&dsi_dual_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+};
+
+&dsi_sim_sec_hd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+ qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+};
+
+&sde_dsi {
+ /delete-property/ avdd-supply;
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+ qcom,dsi-default-panel = <&dsi_sharp_4k_dsc_cmd>;
+};
+
+&sde_dsi1 {
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-cdp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/kona-cdp-overlay.dts
new file mode 100755
index 0000000..ad04489
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-cdp-overlay.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-kona.h>
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "kona-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona CDP";
+ compatible = "qcom,kona-cdp", "qcom,kona", "qcom,cdp";
+ qcom,board-id = <0x10001 0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/kona-cdp.dts
new file mode 100755
index 0000000..d593aec
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-cdp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona.dtsi"
+#include "kona-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona CDP";
+ compatible = "qcom,kona-cdp", "qcom,kona", "qcom,cdp";
+ qcom,board-id = <0x10001 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-cdp.dtsi
new file mode 100755
index 0000000..cb06ea8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-cdp.dtsi
@@ -0,0 +1,893 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "kona-pmic-overlay.dtsi"
+#include "kona-sde-display.dtsi"
+#include "camera/kona-camera-sensor-cdp.dtsi"
+#include "kona-audio-overlay.dtsi"
+#include "kona-thermal-overlay.dtsi"
+
+&qupv3_se12_2uart {
+ status = "ok";
+};
+
+&pm8150a_amoled {
+ status = "ok";
+};
+
+&qupv3_se6_4uart {
+ status = "ok";
+};
+
+&dai_mi2s2 {
+ qcom,msm-mi2s-tx-lines = <1>;
+};
+
+&q6core {
+ cdc_tert_mi2s_gpios: msm_cdc_pinctrl_tert {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
+ &tert_mi2s_sd0_active>;
+ pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
+ &tert_mi2s_sd0_sleep>;
+ };
+};
+
+&kona_snd {
+ qcom,tert-mi2s-gpios = <&cdc_tert_mi2s_gpios>;
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ qcom,clk-freq-out = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 111 0x00>;
+ qcom,nq-ven = <&tlmm 6 0x00>;
+ qcom,nq-firm = <&tlmm 110 0x00>;
+ qcom,nq-clkreq = <&tlmm 7 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <111 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v4";
+
+ vdda-phy-supply = <&pm8150_l5>;
+ vdda-phy-always-on;
+ vdda-pll-supply = <&pm8150_l9>;
+ vdda-phy-max-microamp = <89900>;
+ vdda-pll-max-microamp = <18800>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm8150_l17>;
+ vcc-voltage-level = <2504000 2950000>;
+ vcc-low-voltage-sup;
+ vccq-supply = <&pm8150_l6>;
+ vccq2-supply = <&pm8150_s4>;
+ vccq-max-microamp = <800000>;
+ vcc-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+
+ qcom,vddp-ref-clk-supply = <&pm8150_l6>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vccq-parent-supply = <&pm8150a_s8>;
+ qcom,vccq-parent-max-microamp = <210000>;
+
+ status = "ok";
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_home_default
+ &key_vol_up_default>;
+
+ home {
+ label = "home";
+ gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_HOME>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+
+ qcom,qbt_handler {
+ compatible = "qcom,qbt-handler";
+ qcom,ipc-gpio = <&tlmm 23 0>;
+ qcom,finger-detect-gpio = <&pm8150_gpios 1 0>;
+ status = "disabled";
+ };
+};
+
+&qupv3_se13_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "ok";
+ qcom,i2c-touch-active = "st,fts";
+
+ st_fts@49 {
+ compatible = "st,fts";
+ reg = <0x49>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <39 0x2008>;
+ vdd-supply = <&pm8150a_l1>;
+ avdd-supply = <&pm8150_l13>;
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ st,irq-gpio = <&tlmm 39 0x2008>;
+ st,reset-gpio = <&tlmm 38 0x00>;
+ st,regulator_dvdd = "vdd";
+ st,regulator_avdd = "avdd";
+ panel = <&dsi_sw43404_amoled_cmd &dsi_sw43404_amoled_video
+ &dsi_sw43404_amoled_fhd_plus_cmd>;
+ };
+
+ synaptics_dsx@22 {
+ compatible = "synaptics,dsx-i2c";
+ reg = <0x22>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <39 0x2008>;
+ vdd-supply = <&pm8150a_l1>;
+ avdd-supply = <&pm8150_l13>;
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&pmx_ts_release>;
+ synaptics,pwr-reg-name = "avdd";
+ synaptics,bus-reg-name = "vdd";
+ synaptics,ub-i2c-addr = <0x22>;
+ synaptics,max-y-for-2d = <1859>;
+ synaptics,irq-gpio = <&tlmm 39 0x2008>;
+ synaptics,reset-gpio = <&tlmm 38 0x0>;
+ synaptics,irq-on-state = <0>;
+ synaptics,power-delay-ms = <200>;
+ synaptics,reset-delay-ms = <200>;
+ synaptics,reset-on-state = <0>;
+ synaptics,reset-active-ms = <20>;
+
+ panel = <&dsi_sharp_qsync_wqhd_cmd &dsi_sharp_qsync_wqhd_video>;
+ };
+
+ focaltech@38 {
+ compatible = "focaltech,fts_ts";
+ reg = <0x38>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <39 0x2008>;
+ focaltech,reset-gpio = <&tlmm 38 0x00>;
+ focaltech,irq-gpio = <&tlmm 39 0x2008>;
+ focaltech,max-touch-number = <5>;
+ focaltech,display-coords = <0 0 1080 2340>;
+
+ vdd-supply = <&pm8150_l13>;
+
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&pmx_ts_release>;
+
+ panel = <&dsi_r66451_amoled_144hz_cmd>;
+ };
+
+ novatek@62 {
+ compatible = "novatek,NVT-ts";
+ reg = <0x62>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <39 0x2008>;
+
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&pmx_ts_release>;
+
+ novatek,reset-gpio = <&tlmm 38 0x00>;
+ novatek,irq-gpio = <&tlmm 39 0x2008>;
+
+ panel = <&dsi_nt36672e_fhd_plus_60_video>;
+
+ };
+};
+
+&vendor {
+ bluetooth: bt_qca6390 {
+ compatible = "qca,qca6390";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en_sleep>;
+ qca,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */
+ qca,bt-sw-ctrl-gpio = <&tlmm 124 0>; /* SW_CTRL */
+ qca,bt-vdd-aon-supply = <&pm8150_s6>;
+ qca,bt-vdd-dig-supply = <&pm8009_s2>;
+ qca,bt-vdd-rfa1-supply = <&pm8150_s5>;
+ qca,bt-vdd-rfa2-supply = <&pm8150a_s8>;
+ qca,bt-vdd-asd-supply = <&pm8150_l16>;
+
+ qca,bt-vdd-aon-voltage-level = <950000 950000>;
+ qca,bt-vdd-dig-voltage-level = <950000 952000>;
+ qca,bt-vdd-rfa1-voltage-level = <1900000 1900000>;
+ qca,bt-vdd-rfa2-voltage-level = <1350000 1350000>;
+ qca,bt-vdd-asd-voltage-level = <3024000 3304000>;
+
+ qca,bt-vdd-asd-current-level = <10000>;
+ };
+
+ extcon_usb1: extcon_usb1 {
+ compatible = "linux,extcon-usb-gpio";
+ vbus-gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>;
+ id-gpio = <&tlmm 91 GPIO_ACTIVE_HIGH>;
+ vbus-out-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_vbus_det_default
+ &usb2_id_det_default
+ &usb2_vbus_boost_default>;
+ };
+};
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-en-gpio = <&tlmm 60 0>;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-en-gpio = <&tlmm 60 0>;
+};
+
+&dsi_sharp_qsync_wqhd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-en-gpio = <&tlmm 60 0>;
+};
+
+&dsi_sharp_qsync_wqhd_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-en-gpio = <&tlmm 60 0>;
+};
+
+&dsi_nt36672e_fhd_plus_60_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-en-gpio = <&tlmm 60 0>;
+};
+
+&dsi_sharp_1080_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_nt35597_truly_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_nt35597_truly_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-sec-reset-gpio = <&tlmm 128 0>;
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_avdd>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_sec_hd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-sec-reset-gpio = <&tlmm 128 0>;
+};
+
+&dsi_r66451_amoled_144hz_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,mdss-dsi-bl-inverted-dbv;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
+};
+
+&pm8150b_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "conn_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ chg_sbux@99 {
+ reg = <ADC_SBUx>;
+ label = "chg_sbux";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ mid_chg_div6@1e {
+ reg = <ADC_MID_CHG_DIV6>;
+ label = "chg_mid";
+ qcom,pre-scaling = <1 6>;
+ };
+
+ usb_in_i_uv@7 {
+ reg = <ADC_USB_IN_I>;
+ label = "usb_in_i_uv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ usb_in_v_div_16@8 {
+ reg = <ADC_USB_IN_V_16>;
+ label = "usb_in_v_div_16";
+ qcom,pre-scaling = <1 16>;
+ };
+};
+
+&pm8150b_charger {
+ status = "ok";
+ qcom,batteryless-platform;
+ io-channels = <&pm8150b_vadc ADC_USB_IN_V_16>,
+ <&pm8150b_vadc ADC_USB_IN_I>,
+ <&pm8150b_vadc ADC_CHG_TEMP>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp";
+};
+
+&pm8150b_fg {
+ status = "ok";
+};
+
+&pm8150_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vcoin@85 {
+ reg = <ADC_VCOIN>;
+ label = "vcoin";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ xo_therm@4c {
+ reg = <ADC_XO_THERM_PU2>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "pa_therm1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150l_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ camera_flash_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "camera_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_msm_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "skin_msm_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm2@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "pa_therm2";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150b_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ io-channels = <&pm8150b_vadc ADC_AMUX_THM3_PU2>;
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ io-channels = <&pm8150_vadc ADC_XO_THERM_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM1_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM2_PU2>;
+
+ xo_therm@4c {
+ reg = <ADC_XO_THERM_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150l_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera_flash_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ skin_msm_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm2@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&spmi_debug_bus {
+ status = "ok";
+};
+
+&kona_snd {
+ qcom,model = "kona-cdp-snd-card";
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic4",
+ "AMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Analog Mic5",
+ "TX DMIC0", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic0",
+ "TX DMIC1", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic1",
+ "TX DMIC2", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "TX DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "TX DMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "TX DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "DMIC1", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic0",
+ "DMIC2", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic1",
+ "DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "DMIC4", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "DMIC6", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "DMIC7", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic6",
+ "DMIC8", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic7",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic4",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA DMIC4", "VA MIC BIAS4",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC0", "VA_SWR_CLK",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_ADC2", "VA_SWR_CLK",
+ "VA SWR_ADC3", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_ADC0", "ADC1_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT",
+ "VA SWR_ADC2", "ADC3_OUTPUT",
+ "VA SWR_ADC3", "ADC4_OUTPUT",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT";
+};
+
+&thermal_zones {
+ conn-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-msm-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&sdhc_2 {
+ vdd-supply = <&pm8150a_l9>;
+ qcom,vdd-voltage-level = <2950000 2960000>;
+ qcom,vdd-current-level = <200 800000>;
+
+ vdd-io-supply = <&pm8150a_l6>;
+ qcom,vdd-io-voltage-level = <1808000 2960000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>;
+
+ cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&usb1 {
+ extcon = <&extcon_usb1>;
+};
+
+&wil6210 {
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-coresight.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-coresight.dtsi
new file mode 100755
index 0000000..b5c7e56
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-coresight.dtsi
@@ -0,0 +1,3520 @@
+&soc {
+ replicator_qdss: replicator@6046000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+
+ reg = <0x6046000 0x1000>;
+ reg-names = "replicator-base";
+
+ coresight-name = "coresight-replicator-qdss";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ replicator0_out_tmc_etr: endpoint {
+ remote-endpoint=
+ <&tmc_etr_in_replicator0>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ replicator_cx_in_swao_out: endpoint {
+ slave-mode;
+ remote-endpoint=
+ <&replicator_swao_out_cx_in>;
+ };
+ };
+ };
+ };
+
+ replicator_swao: replicator@6b06000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+
+ reg = <0x6b06000 0x1000>;
+ reg-names = "replicator-base";
+
+ coresight-name = "coresight-replicator-swao";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Always have EUD before funnel leading to ETR. If both
+ * sink are active we need to give preference to EUD
+ * over ETR
+ */
+ port@0 {
+ reg = <1>;
+ replicator_swao_out_eud: endpoint {
+ remote-endpoint =
+ <&eud_in_replicator_swao>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ replicator_swao_out_cx_in: endpoint {
+ remote-endpoint =
+ <&replicator_cx_in_swao_out>;
+ };
+ };
+
+ port@2 {
+ reg = <0>;
+ replicator_swao_in_tmc_etf_swao: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tmc_etf_swao_out_replicator_swao>;
+ };
+ };
+ };
+ };
+
+ dummy_eud: dummy_sink {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-eud";
+
+ qcom,dummy-sink;
+ port {
+ eud_in_replicator_swao: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&replicator_swao_out_eud>;
+ };
+ };
+ };
+
+ tmc_etf_swao: tmc@6b05000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+
+ reg = <0x6b05000 0x1000>;
+ reg-names = "tmc-base";
+
+ coresight-name = "coresight-tmc-etf";
+ coresight-ctis = <&cti0_swao &cti3_swao>;
+ coresight-csr = <&swao_csr>;
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tmc_etf_swao_out_replicator_swao: endpoint {
+ remote-endpoint=
+ <&replicator_swao_in_tmc_etf_swao>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tmc_etf_swao_in_funnel_swao: endpoint {
+ slave-mode;
+ remote-endpoint=
+ <&funnel_swao_out_tmc_etf_swao>;
+ };
+ };
+ };
+ };
+
+ funnel_swao: funnel@6b04000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6b04000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-swao";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_swao_out_tmc_etf_swao: endpoint {
+ remote-endpoint =
+ <&tmc_etf_swao_in_funnel_swao>;
+ };
+ };
+
+ port@1 {
+ reg = <3>;
+ funnel_swao_in_ssc_etm0: endpoint {
+ slave-mode;
+ remote-endpoint=
+ <&ssc_etm0_out_funnel_swao>;
+ };
+ };
+
+ port@2 {
+ reg = <5>;
+ funnel_swao_in_audio_etm0: endpoint {
+ slave-mode;
+ remote-endpoint=
+ <&audio_etm0_out_funnel_swao>;
+ };
+ };
+
+ port@3 {
+ reg = <6>;
+ funnel_swao_in_tpda_swao: endpoint {
+ slave-mode;
+ remote-endpoint=
+ <&tpda_swao_out_funnel_swao>;
+ };
+ };
+
+ port@4 {
+ reg = <7>;
+ funnel_swao_in_funnel_merg: endpoint {
+ slave-mode;
+ remote-endpoint=
+ <&funnel_merg_out_funnel_swao>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ funnel_swao_in_lpass_lpi: endpoint {
+ slave-mode;
+ remote-endpoint=
+ <&lpass_lpi_out_funnel_swao>;
+ };
+ };
+ };
+ };
+
+ tpda_swao: tpda@6b08000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x6b08000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-swao";
+
+ qcom,tpda-atid = <71>;
+ qcom,dsb-elem-size = <1 32>;
+ qcom,cmb-elem-size = <0 64>;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_swao_out_funnel_swao: endpoint {
+ remote-endpoint =
+ <&funnel_swao_in_tpda_swao>;
+ };
+
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_swao_in_tpdm_swao0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_swao0_out_tpda_swao>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ tpda_swao_in_tpdm_swao1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_swao1_out_tpda_swao>;
+ };
+ };
+ };
+ };
+
+ tpdm_swao0: tpdm@6b09000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+
+ reg = <0x6b09000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-swao-0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_swao0_out_tpda_swao: endpoint {
+ remote-endpoint = <&tpda_swao_in_tpdm_swao0>;
+ };
+ };
+ };
+
+ tpdm_swao1: tpdm@6b0a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6b0a000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name="coresight-tpdm-swao-1";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_swao1_out_tpda_swao: endpoint {
+ remote-endpoint = <&tpda_swao_in_tpdm_swao1>;
+ };
+ };
+ };
+
+ tmc_etr: tmc@6048000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+
+ reg = <0x6048000 0x1000>,
+ <0x6064000 0x15000>;
+ reg-names = "tmc-base", "bam-base";
+
+ iommus = <&apps_smmu 0x0480 0>,
+ <&apps_smmu 0x0520 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ arm,buffer-size = <0x400000>;
+ arm,scatter-gather;
+
+ coresight-name = "coresight-tmc-etr";
+ coresight-ctis = <&cti0 &cti3_swao>;
+ coresight-csr = <&csr>;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "byte-cntr-irq";
+
+ port {
+ tmc_etr_in_replicator0: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator0_out_tmc_etr>;
+ };
+ };
+ };
+
+ funnel_merg: funnel@6045000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6045000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-merg";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_merg_out_funnel_swao: endpoint {
+ remote-endpoint =
+ <&funnel_swao_in_funnel_merg>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_merg_in_funnel_in0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_in0_out_funnel_merg>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_merg_in_funnel_in1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_in1_out_funnel_merg>;
+ };
+ };
+ };
+ };
+
+ stm: stm@6002000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb962>;
+
+ reg = <0x6002000 0x1000>,
+ <0x16280000 0x180000>,
+ <0x7820f0 0x4>;
+ reg-names = "stm-base", "stm-stimulus-base", "stm-debug-status";
+
+ coresight-name = "coresight-stm";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ stm_out_funnel_in0: endpoint {
+ remote-endpoint = <&funnel_in0_in_stm>;
+ };
+ };
+ };
+
+ csr: csr@6001000 {
+ compatible = "qcom,coresight-csr";
+ reg = <0x6001000 0x1000>;
+ reg-names = "csr-base";
+
+ coresight-name = "coresight-csr";
+ qcom,usb-bam-support;
+ qcom,hwctrl-set-support;
+ qcom,set-byte-cntr-support;
+
+ qcom,blk-size = <1>;
+ };
+
+ swao_csr: csr@6b0c000 {
+ compatible = "qcom,coresight-csr";
+ reg = <0x6b0c000 0x1000>;
+ reg-names = "csr-base";
+
+ coresight-name = "coresight-swao-csr";
+ qcom,timestamp-support;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,blk-size = <1>;
+ };
+
+ funnel_in0: funnel@6041000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6041000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-in0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_in0_out_funnel_merg: endpoint {
+ remote-endpoint =
+ <&funnel_merg_in_funnel_in0>;
+ };
+ };
+
+ port@1 {
+ reg = <6>;
+ funnel_in0_in_funnel_qatb: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_qatb_out_funnel_in0>;
+ };
+ };
+
+ port@2 {
+ reg = <7>;
+ funnel_in0_in_stm: endpoint {
+ slave-mode;
+ remote-endpoint = <&stm_out_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel_in1: funnel@6042000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6042000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-in1";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_in1_out_funnel_merg: endpoint {
+ remote-endpoint =
+ <&funnel_merg_in_funnel_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_in1_in_funnel_dl_north: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_north_out_funnel_in1>;
+ };
+ };
+
+ port@2 {
+ reg = <4>;
+ funnel_in1_in_funnel_apss_merg: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_apss_merg_out_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ funnel_gpu: funnel@6902000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6902000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-gpu";
+
+ clocks = <&clock_aop QDSS_CLK>,
+ <&clock_gpucc GPU_CC_CXO_CLK>,
+ <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&clock_gpucc GPU_CC_CX_GMU_CLK>,
+ <&clock_gpucc GPU_CC_AHB_CLK>,
+ <&clock_cpucc L3_GPU_VOTE_CLK>;
+
+ clock-names = "apb_pclk",
+ "rbbmtimer_clk",
+ "mem_clk",
+ "mem_iface_clk",
+ "gmu_clk",
+ "gpu_cc_ahb",
+ "l3_vote";
+
+ qcom,proxy-clks = "rbbmtimer_clk",
+ "mem_clk",
+ "mem_iface_clk",
+ "gmu_clk",
+ "gpu_cc_ahb",
+ "l3_vote";
+
+ vddcx-supply = <&gpu_cx_gdsc>;
+ vdd-supply = <&gpu_gx_gdsc>;
+ regulator-names = "vddcx", "vdd";
+ qcom,proxy-regs = "vddcx", "vdd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_gpu_out_tpda: endpoint {
+ remote-endpoint =
+ <&tpda_in_funnel_gpu>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_gpu_in_tpdm_gpu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_gpu_out_funnel_gpu>;
+ };
+ };
+ };
+ };
+
+ tpdm_gpu: tpdm@6900000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6900000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-gpu";
+
+ clocks = <&clock_aop QDSS_CLK>,
+ <&clock_gpucc GPU_CC_CXO_CLK>,
+ <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&clock_gpucc GPU_CC_CX_GMU_CLK>,
+ <&clock_gpucc GPU_CC_AHB_CLK>,
+ <&clock_cpucc L3_GPU_VOTE_CLK>;
+ clock-names = "apb_pclk",
+ "rbbmtimer_clk",
+ "mem_clk",
+ "mem_iface_clk",
+ "gmu_clk",
+ "gpu_cc_ahb",
+ "l3_vote";
+
+ qcom,proxy-clks = "rbbmtimer_clk",
+ "mem_clk",
+ "mem_iface_clk",
+ "gmu_clk",
+ "gpu_cc_ahb",
+ "l3_vote";
+
+ vddcx-supply = <&gpu_cx_gdsc>;
+ vdd-supply = <&gpu_gx_gdsc>;
+ regulator-names = "vddcx", "vdd";
+ qcom,proxy-regs = "vddcx", "vdd";
+
+ port {
+ tpdm_gpu_out_funnel_gpu: endpoint {
+ remote-endpoint = <&funnel_gpu_in_tpdm_gpu>;
+ };
+ };
+ };
+
+ tpda: tpda@6004000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x6004000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda";
+
+ qcom,tpda-atid = <65>;
+ qcom,bc-elem-size = <16 32>,
+ <24 32>,
+ <25 32>;
+ qcom,tc-elem-size = <16 32>,
+ <25 32>;
+ qcom,dsb-elem-size = <1 32>,
+ <6 32>,
+ <7 32>,
+ <10 32>,
+ <11 32>,
+ <12 32>,
+ <13 32>,
+ <14 32>,
+ <16 32>,
+ <19 32>,
+ <24 32>,
+ <25 32>;
+ qcom,cmb-elem-size = <7 64>,
+ <13 32>,
+ <15 32>,
+ <16 32>,
+ <17 32>,
+ <18 64>,
+ <20 64>,
+ <21 64>,
+ <22 32>,
+ <23 32>,
+ <25 64>;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_tpda>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ tpda_in_funnel_gpu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_gpu_out_tpda>;
+ };
+ };
+
+ port@2 {
+ reg = <6>;
+ tpda_6_in_tpdm_venus: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_venus_out_tpda6>;
+ };
+ };
+
+ port@3 {
+ reg = <7>;
+ tpda_7_in_tpdm_mdss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_mdss_out_tpda7>;
+ };
+ };
+
+ port@4 {
+ reg = <9>;
+ tpda_9_in_tpdm_mm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_mm_out_tpda9>;
+ };
+ };
+
+ port@5 {
+ reg = <10>;
+ tpda_10_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_tpda_10>;
+ };
+ };
+
+ port@6 {
+ reg = <11>;
+ tpda_11_in_tpdm_ddr_ch02: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_ddr_ch02_out_tpda11>;
+ };
+ };
+
+ port@7 {
+ reg = <12>;
+ tpda_12_in_tpdm_ddr_ch13: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_ddr_ch13_out_tpda12>;
+ };
+ };
+
+ port@8 {
+ reg = <13>;
+ tpda_13_in_tpdm_ddr: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_ddr_out_tpda13>;
+ };
+ };
+
+ port@9 {
+ reg = <14>;
+ tpda_14_in_tpdm_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_turing_out_tpda14>;
+ };
+ };
+
+ port@10 {
+ reg = <15>;
+ tpda_15_in_tpdm_llm_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_llm_turing_out_tpda15>;
+ };
+ };
+
+ port@11 {
+ reg = <16>;
+ tpda_16_in_tpdm_npu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_npu_out_tpda16>;
+ };
+ };
+
+ port@12 {
+ reg = <17>;
+ tpda_17_in_tpdm_npu_llm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_npu_llm_out_tpda17>;
+ };
+ };
+
+ port@13 {
+ reg = <18>;
+ tpda_18_in_tpdm_npu_dpm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_npu_dpm_out_tpda18>;
+ };
+ };
+
+ port@14 {
+ reg = <19>;
+ tpda_19_in_tpdm_dlct: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dlct_out_tpda19>;
+ };
+ };
+
+ port@15 {
+ reg = <20>;
+ tpda_20_in_tpdm_ipcc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_ipcc_out_tpda20>;
+ };
+ };
+
+ port@16 {
+ reg = <21>;
+ tpda_in_tpdm_vsense: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_vsense_out_tpda>;
+ };
+ };
+
+ port@17 {
+ reg = <22>;
+ tpda_in_tpdm_dcc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dcc_out_tpda>;
+ };
+ };
+
+ port@18 {
+ reg = <23>;
+ tpda_in_tpdm_prng: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_prng_out_tpda>;
+ };
+ };
+
+ port@19 {
+ reg = <24>;
+ tpda_in_tpdm_qm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_qm_out_tpda>;
+ };
+ };
+
+ port@20 {
+ reg = <25>;
+ tpda_in_tpdm_pimem: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_pimem_out_tpda>;
+ };
+ };
+ };
+ };
+
+ tpdm_dcc: tpdm@6870000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6870000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dcc";
+
+ qcom,hw-enable-check;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_dcc_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_dcc>;
+ };
+ };
+ };
+
+ tpdm_vsense: tpdm@6840000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6840000 0x1000>;
+ reg-names = "tpdm-base";
+
+ status = "disabled";
+ coresight-name = "coresight-tpdm-vsense";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_vsense_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_vsense>;
+ };
+ };
+ };
+
+ tpdm_prng: tpdm@684c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x684c000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-prng";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_prng_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_prng>;
+ };
+ };
+ };
+
+ tpdm_pimem: tpdm@6850000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6850000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-pimem";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_pimem_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_pimem>;
+ };
+ };
+ };
+
+ funnel_lpass: funnel@6846000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6846000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-lpass";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_lpass_out_funnel_dl_center: endpoint {
+ remote-endpoint =
+ <&funnel_dl_center_in_funnel_lpass>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_lpass_in_tpdm_lpass: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_lpass_out_funnel_lpass>;
+ };
+ };
+ };
+ };
+
+ tpdm_lpass: tpdm@6844000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6844000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-lpass";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_lpass_out_funnel_lpass: endpoint {
+ remote-endpoint = <&funnel_lpass_in_tpdm_lpass>;
+ };
+ };
+ };
+
+ tpdm_dl_north: tpdm@6ac0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6ac0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dl-north";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_dl_north_out_tpda_dl_north: endpoint {
+ remote-endpoint =
+ <&tpda_dl_north_in_tpdm_dl_north>;
+ };
+ };
+ };
+
+ tpdm_lpass_lpi: tpdm@6b26000 {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-tpdm-lpass-lpi";
+ qcom,dummy-source;
+
+ port {
+ lpass_lpi_out_funnel_swao: endpoint {
+ remote-endpoint =
+ <&funnel_swao_in_lpass_lpi>;
+ };
+ };
+ };
+
+ tpda_dl_north: tpda@6ac1000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x06ac1000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-dl-north";
+ qcom,tpda-atid = <97>;
+
+ qcom,dsb-elem-size = <0 32>;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_dl_north_out_funnel_dl_north: endpoint {
+ remote-endpoint =
+ <&funnel_dl_north_in_tpda_dl_north>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_dl_north_in_tpdm_dl_north: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dl_north_out_tpda_dl_north>;
+ };
+ };
+ };
+ };
+
+ funnel_dl_south: funnel@69c2000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x69c2000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-dl-south";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_south_out_funnel_dl_compute: endpoint {
+ remote-endpoint =
+ <&funnel_dl_compute_in_funnel_dl_south>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_dl_south_in_tpda_dl_south: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_dl_south_out_funnel_dl_south>;
+ };
+ };
+ };
+ };
+
+ tpda_dl_south: tpda@69c1000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x69c1000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-dl-south";
+
+ qcom,tpda-atid = <75>;
+ qcom,dsb-elem-size = <0 64>;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_dl_south_out_funnel_dl_south: endpoint {
+ remote-endpoint =
+ <&funnel_dl_south_in_tpda_dl_south>;
+ };
+
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_dl_south_in_tpdm_dl_south: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dl_south_out_tpda_dl_south>;
+ };
+ };
+ };
+ };
+
+ tpdm_dl_south: tpdm@69c0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x69c0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dl-south";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_dl_south_out_tpda_dl_south: endpoint {
+ remote-endpoint =
+ <&tpda_dl_south_in_tpdm_dl_south>;
+ };
+ };
+ };
+
+ funnel_dl_north: funnel@6ac2000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6ac2000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-dl-north";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_dl_north_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_funnel_dl_north>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_dl_north_in_tpda_dl_north: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_dl_north_out_funnel_dl_north>;
+ };
+ };
+ };
+ };
+
+ funnel_dl_compute: funnel@6c39000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6c39000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-dl-compute";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_compute_out_funnel_dl_center: endpoint {
+ remote-endpoint =
+ <&funnel_dl_center_in_funnel_compute>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_compute_in_funnel_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_turing_out_funnel_dl_compute>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_compute_in_funnel_npu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_npu_out_funnel_dl_compute>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_dl_compute_in_funnel_dl_south: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_south_out_funnel_dl_compute>;
+ };
+ };
+ };
+ };
+
+ tpdm_npu: tpdm@6c47000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c47000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-npu";
+
+ clocks = <&clock_aop QDSS_CLK>,
+ <&clock_gcc GCC_NPU_AXI_CLK>,
+ <&clock_gcc GCC_NPU_CFG_AHB_CLK>,
+ <&clock_npucc NPU_CC_XO_CLK>,
+ <&clock_npucc NPU_CC_CORE_CLK>,
+ <&clock_npucc NPU_CC_CORE_CLK_SRC>,
+ <&clock_npucc NPU_CC_ATB_CLK>;
+
+ clock-names = "apb_pclk",
+ "gcc_npu_axi_clk",
+ "gcc_npu_cfg_ahb_clk",
+ "npu_cc_xo_clk",
+ "npu_core_clk",
+ "npu_core_clk_src",
+ "npu_cc_atb_clk";
+
+ qcom,proxy-clks = "gcc_npu_axi_clk",
+ "gcc_npu_cfg_ahb_clk",
+ "npu_cc_xo_clk",
+ "npu_core_clk",
+ "npu_core_clk_src",
+ "npu_cc_atb_clk";
+
+ vdd-supply = <&npu_core_gdsc>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,proxy-regs ="vdd", "vdd_cx";
+
+ port {
+ tpdm_npu_out_funnel_npu: endpoint {
+ remote-endpoint = <&funnel_npu_in_tpdm_npu>;
+ };
+ };
+ };
+
+ tpdm_npu_llm: tpdm@6c40000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c40000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-npu-llm";
+ clocks = <&clock_aop QDSS_CLK>,
+ <&clock_gcc GCC_NPU_AXI_CLK>,
+ <&clock_gcc GCC_NPU_CFG_AHB_CLK>,
+ <&clock_npucc NPU_CC_XO_CLK>,
+ <&clock_npucc NPU_CC_CORE_CLK>,
+ <&clock_npucc NPU_CC_CORE_CLK_SRC>,
+ <&clock_npucc NPU_CC_ATB_CLK>,
+ <&clock_npucc NPU_CC_LLM_CLK>,
+ <&clock_npucc NPU_CC_LLM_XO_CLK>,
+ <&clock_npucc NPU_CC_LLM_TEMP_CLK>,
+ <&clock_npucc NPU_CC_LLM_CURR_CLK>,
+ <&clock_npucc NPU_CC_DL_LLM_CLK>;
+
+ clock-names = "apb_pclk",
+ "gcc_npu_axi_clk",
+ "gcc_npu_cfg_ahb_clk",
+ "npu_cc_xo_clk",
+ "npu_core_clk",
+ "npu_core_clk_src",
+ "npu_cc_atb_clk",
+ "npu_cc_llm_clk",
+ "npu_cc_llm_xo_clk",
+ "npu_cc_llm_temp_clk",
+ "npu_cc_llm_curr_clk",
+ "npu_cc_dl_llm_clk";
+
+ qcom,proxy-clks = "gcc_npu_axi_clk",
+ "gcc_npu_cfg_ahb_clk",
+ "npu_cc_xo_clk",
+ "npu_core_clk",
+ "npu_core_clk_src",
+ "npu_cc_atb_clk",
+ "npu_cc_llm_clk",
+ "npu_cc_llm_xo_clk",
+ "npu_cc_llm_temp_clk",
+ "npu_cc_llm_curr_clk",
+ "npu_cc_dl_llm_clk";
+
+ vdd-supply = <&npu_core_gdsc>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,proxy-regs ="vdd", "vdd_cx";
+
+ port {
+ tpdm_npu_llm_out_funnel_npu: endpoint {
+ remote-endpoint = <&funnel_npu_in_tpdm_npu_llm>;
+ };
+ };
+ };
+
+ tpdm_npu_dpm: tpdm@6c41000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c41000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-npu-dpm";
+
+ clocks = <&clock_aop QDSS_CLK>,
+ <&clock_gcc GCC_NPU_AXI_CLK>,
+ <&clock_gcc GCC_NPU_CFG_AHB_CLK>,
+ <&clock_npucc NPU_CC_XO_CLK>,
+ <&clock_npucc NPU_CC_CORE_CLK>,
+ <&clock_npucc NPU_CC_CORE_CLK_SRC>,
+ <&clock_npucc NPU_CC_ATB_CLK>,
+ <&clock_npucc NPU_CC_DPM_CLK>,
+ <&clock_npucc NPU_CC_DPM_XO_CLK>,
+ <&clock_npucc NPU_CC_DL_DPM_CLK>;
+
+ clock-names = "apb_pclk",
+ "gcc_npu_axi_clk",
+ "gcc_npu_cfg_ahb_clk",
+ "npu_cc_xo_clk",
+ "npu_core_clk",
+ "npu_core_clk_src",
+ "npu_cc_atb_clk",
+ "npu_cc_dpm_clk",
+ "npu_cc_dpm_xo_clk",
+ "npu_cc_dl_dpm_clk";
+
+ qcom,proxy-clks = "gcc_npu_axi_clk",
+ "gcc_npu_cfg_ahb_clk",
+ "npu_cc_xo_clk",
+ "npu_core_clk",
+ "npu_core_clk_src",
+ "npu_cc_atb_clk",
+ "npu_cc_dpm_clk",
+ "npu_cc_dpm_xo_clk",
+ "npu_cc_dl_dpm_clk";
+
+ vdd-supply = <&npu_core_gdsc>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,proxy-regs ="vdd", "vdd_cx";
+
+ port {
+ tpdm_npu_dpm_out_funnel_npu: endpoint {
+ remote-endpoint = <&funnel_npu_in_tpdm_npu_dpm>;
+ };
+ };
+ };
+
+ funnel_dl_center: funnel@6c2d000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6c2d000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-dl-center";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpdm_venus_out_tpda6: endpoint {
+ remote-endpoint =
+ <&tpda_6_in_tpdm_venus>;
+ source = <&tpdm_venus>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ tpdm_mdss_out_tpda7: endpoint {
+ remote-endpoint =
+ <&tpda_7_in_tpdm_mdss>;
+ source = <&tpdm_mdss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ tpdm_mm_out_tpda9: endpoint {
+ remote-endpoint =
+ <&tpda_9_in_tpdm_mm>;
+ source = <&tpdm_mm>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_dl_center_out_tpda_10: endpoint {
+ remote-endpoint =
+ <&tpda_10_in_funnel_dl_center>;
+ source = <&tpdm_lpass>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ tpdm_ddr_ch02_out_tpda11: endpoint {
+ remote-endpoint =
+ <&tpda_11_in_tpdm_ddr_ch02>;
+ source = <&tpdm_ddr_ch02>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ tpdm_ddr_ch13_out_tpda12: endpoint {
+ remote-endpoint =
+ <&tpda_12_in_tpdm_ddr_ch13>;
+ source = <&tpdm_ddr_ch13>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ tpdm_ddr_out_tpda13: endpoint {
+ remote-endpoint =
+ <&tpda_13_in_tpdm_ddr>;
+ source = <&tpdm_ddr>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ tpdm_turing_out_tpda14: endpoint {
+ remote-endpoint =
+ <&tpda_14_in_tpdm_turing>;
+ source = <&tpdm_turing>;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+ tpdm_llm_turing_out_tpda15: endpoint {
+ remote-endpoint =
+ <&tpda_15_in_tpdm_llm_turing>;
+ source = <&tpdm_llm_turing>;
+ };
+ };
+
+ port@9 {
+ reg = <9>;
+ tpdm_npu_out_tpda16: endpoint {
+ remote-endpoint =
+ <&tpda_16_in_tpdm_npu>;
+ source = <&tpdm_npu>;
+ };
+ };
+
+ port@10 {
+ reg = <10>;
+ tpdm_npu_llm_out_tpda17: endpoint {
+ remote-endpoint =
+ <&tpda_17_in_tpdm_npu_llm>;
+ source = <&tpdm_npu_llm>;
+ };
+ };
+
+ port@11 {
+ reg = <11>;
+ tpdm_npu_dpm_out_tpda18: endpoint {
+ remote-endpoint =
+ <&tpda_18_in_tpdm_npu_dpm>;
+ source = <&tpdm_npu_dpm>;
+ };
+ };
+
+ port@12 {
+ reg = <12>;
+ tpdm_dlct_out_tpda19: endpoint {
+ remote-endpoint =
+ <&tpda_19_in_tpdm_dlct>;
+ source = <&tpdm_dlct>;
+ };
+ };
+
+ port@13 {
+ reg = <13>;
+ tpdm_ipcc_out_tpda20: endpoint {
+ remote-endpoint =
+ <&tpda_20_in_tpdm_ipcc>;
+ source = <&tpdm_ipcc>;
+ };
+ };
+
+ port@14 {
+ reg = <14>;
+ funnel_dl_center_out_qatb3: endpoint {
+ remote-endpoint =
+ <&qatb3_in_funnel_dl_center>;
+ };
+ };
+
+ port@15 {
+ reg = <2>;
+ funnel_dl_center_in_funnel_dl_mm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_mm_out_funnel_dl_center>;
+ };
+ };
+
+ port@16 {
+ reg = <3>;
+ funnel_dl_center_in_funnel_lpass: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_lpass_out_funnel_dl_center>;
+ };
+ };
+
+ port@17 {
+ reg = <4>;
+ funnel_dl_center_in_funnel_ddr_0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_ddr_0_out_funnel_dl_center>;
+ };
+ };
+
+ port@18 {
+ reg = <5>;
+ funnel_dl_center_in_funnel_compute: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_compute_out_funnel_dl_center>;
+ };
+ };
+
+ port@19 {
+ reg = <6>;
+ funnel_center_in_tpdm_dlct: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dlct_out_funnel_center>;
+ };
+ };
+
+ port@20 {
+ reg = <7>;
+ funnel_center_in_tpdm_ipcc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_ipcc_out_funnel_center>;
+ };
+ };
+ };
+ };
+
+ tpdm_dlct: tpdm@6c28000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c28000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dlct";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_dlct_out_funnel_center: endpoint {
+ remote-endpoint = <&funnel_center_in_tpdm_dlct>;
+ };
+ };
+ };
+
+ tpdm_ipcc: tpdm@6c29000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c29000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-ipcc";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_ipcc_out_funnel_center: endpoint {
+ remote-endpoint = <&funnel_center_in_tpdm_ipcc>;
+ };
+ };
+ };
+
+ tpdm_qm: tpdm@69d0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x69d0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-qm";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_qm_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_qm>;
+ };
+ };
+ };
+
+ tpda_apss: tpda@7863000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x7863000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-apss";
+
+ qcom,tpda-atid = <66>;
+ qcom,dsb-elem-size = <3 32>;
+ qcom,cmb-elem-size = <0 32>,
+ <1 32>,
+ <2 64>;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_apss_out_funnel_apss_merg: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merg_in_tpda_apss>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_apss_in_tpdm_llm_silver: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_llm_silver_out_tpda_apss>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ tpda_apss_in_tpdm_llm_gold: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_llm_gold_out_tpda_apss>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ tpda_apss_in_tpdm_actpm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_actpm_out_tpda_apss>;
+ };
+ };
+
+ port@4 {
+ reg = <3>;
+ tpda_apss_in_tpdm_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_apss_out_tpda_apss>;
+ };
+ };
+ };
+ };
+
+ tpdm_llm_silver: tpdm@78a0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x78a0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-llm-silver";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_llm_silver_out_tpda_apss: endpoint {
+ remote-endpoint =
+ <&tpda_apss_in_tpdm_llm_silver>;
+ };
+ };
+ };
+
+ tpdm_llm_gold: tpdm@78b0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x78b0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-llm-gold";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_llm_gold_out_tpda_apss: endpoint {
+ remote-endpoint =
+ <&tpda_apss_in_tpdm_llm_gold>;
+ };
+ };
+ };
+
+ tpdm_actpm: tpdm@7860000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x7860000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-actpm";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_actpm_out_tpda_apss: endpoint {
+ remote-endpoint =
+ <&tpda_apss_in_tpdm_actpm>;
+ };
+ };
+ };
+
+ tpdm_apss: tpdm@7861000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x7861000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-apss";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_apss_out_tpda_apss: endpoint {
+ remote-endpoint =
+ <&tpda_apss_in_tpdm_apss>;
+ };
+ };
+ };
+
+ funnel_dl_mm: funnel@6c0b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6c0b000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-dl-mm";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_dl_mm_out_funnel_dl_center: endpoint {
+ remote-endpoint =
+ <&funnel_dl_center_in_funnel_dl_mm>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_dl_mm_in_funnel_venus: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_venus_out_funnel_dl_mm>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_dl_mm_in_tpdm_mdss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_mdss_out_funnel_dl_mm>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_dl_mm_in_tpdm_mm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_mm_out_funnel_dl_mm>;
+ };
+ };
+ };
+ };
+
+ funnel_venus: funnel@6832000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6832000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-venus";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_venus_out_funnel_dl_mm: endpoint {
+ remote-endpoint =
+ <&funnel_dl_mm_in_funnel_venus>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_venus_in_tpdm_venus: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_venus_out_funnel_venus>;
+ };
+ };
+
+ };
+ };
+
+ tpdm_venus: tpdm@6830000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6830000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-venus";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_venus_out_funnel_venus: endpoint {
+ remote-endpoint =
+ <&funnel_venus_in_tpdm_venus>;
+ };
+ };
+ };
+
+ tpdm_mdss: tpdm@6c60000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c60000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-mdss";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_mdss_out_funnel_dl_mm: endpoint {
+ remote-endpoint =
+ <&funnel_dl_mm_in_tpdm_mdss>;
+ };
+ };
+ };
+
+ tpdm_mm: tpdm@6c08000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c08000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-mm";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_mm_out_funnel_dl_mm: endpoint {
+ remote-endpoint =
+ <&funnel_dl_mm_in_tpdm_mm>;
+ };
+ };
+ };
+
+ funnel_npu: funnel@6c44000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6c44000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-npu";
+
+ clocks = <&clock_aop QDSS_CLK>,
+ <&clock_gcc GCC_NPU_AXI_CLK>,
+ <&clock_gcc GCC_NPU_CFG_AHB_CLK>,
+ <&clock_npucc NPU_CC_XO_CLK>,
+ <&clock_npucc NPU_CC_CORE_CLK>,
+ <&clock_npucc NPU_CC_CORE_CLK_SRC>,
+ <&clock_npucc NPU_CC_ATB_CLK>;
+
+ clock-names = "apb_pclk",
+ "gcc_npu_axi_clk",
+ "gcc_npu_cfg_ahb_clk",
+ "npu_cc_xo_clk",
+ "npu_core_clk",
+ "npu_core_clk_src",
+ "npu_cc_atb_clk";
+
+ qcom,proxy-clks = "gcc_npu_axi_clk",
+ "gcc_npu_cfg_ahb_clk",
+ "npu_cc_xo_clk",
+ "npu_core_clk",
+ "npu_core_clk_src",
+ "npu_cc_atb_clk";
+
+ vdd-supply = <&npu_core_gdsc>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ regulator-names = "vdd", "vdd_cx";
+ qcom,proxy-regs ="vdd", "vdd_cx";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_npu_out_funnel_dl_compute: endpoint {
+ remote-endpoint =
+ <&funnel_compute_in_funnel_npu>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_npu_in_tpdm_npu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_npu_out_funnel_npu>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_npu_in_tpdm_npu_llm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_npu_llm_out_funnel_npu>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ funnel_npu_in_tpdm_npu_dpm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_npu_dpm_out_funnel_npu>;
+ };
+ };
+
+ port@4 {
+ reg = <3>;
+ funnel_npu_in_npu_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&npu_etm0_out_funnel_npu>;
+ };
+ };
+ };
+ };
+
+ funnel_turing: funnel@6983000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6983000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-turing";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_turing_out_funnel_dl_compute: endpoint {
+ remote-endpoint =
+ <&funnel_compute_in_funnel_turing>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_turing_in_tpdm_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_turing_out_funnel_turing>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_turing_in_tpdm_llm_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_llm_turing_out_funnel_turing>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ funnel_turing_in_turing_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&turing_etm0_out_funnel_turing>;
+ };
+ };
+ };
+ };
+
+ tpdm_turing: tpdm@6980000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6980000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-turing";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_turing_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_tpdm_turing>;
+ };
+ };
+ };
+
+ tpdm_llm_turing: tpdm@69810000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6981000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-turing-llm";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ status = "disabled";
+
+ port {
+ tpdm_llm_turing_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_tpdm_llm_turing>;
+ };
+ };
+ };
+
+ funnel_ddr_0: funnel@6e04000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6e04000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-ddr-0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_ddr_0_out_funnel_dl_center: endpoint {
+ remote-endpoint =
+ <&funnel_dl_center_in_funnel_ddr_0>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_ddr_0_in_funnel_ddr_ch02: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_ddr_ch02_out_funnel_ddr_0>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_ddr_0_in_funnel_ddr_ch13: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_ddr_ch13_out_funnel_ddr_0>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ funnel_ddr_0_in_tpdm_ddr: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_ddr_out_funnel_ddr_0>;
+ };
+ };
+ };
+ };
+
+ funnel_ddr_ch02: funnel@6e12000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6e12000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-ddr-ch02";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_ddr_ch02_out_funnel_ddr_0: endpoint {
+ remote-endpoint =
+ <&funnel_ddr_0_in_funnel_ddr_ch02>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_ddr_ch02_in_tpdm_ddr_ch02: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_ddr_ch02_out_funnel_ddr_ch02>;
+ };
+ };
+ };
+ };
+
+ funnel_ddr_ch13: funnel@6e22000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6e22000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-ddr-ch13";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_ddr_ch13_out_funnel_ddr_0: endpoint {
+ remote-endpoint =
+ <&funnel_ddr_0_in_funnel_ddr_ch13>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_ddr_ch13_in_tpdm_ddr_ch13: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_ddr_ch13_out_funnel_ddr_ch13>;
+ };
+ };
+ };
+ };
+
+ tpdm_ddr_ch02: tpdm@6e10000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x06e10000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-ddr-ch02";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_ddr_ch02_out_funnel_ddr_ch02: endpoint {
+ remote-endpoint =
+ <&funnel_ddr_ch02_in_tpdm_ddr_ch02>;
+ };
+ };
+ };
+
+ tpdm_ddr_ch13: tpdm@6e20000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x06e20000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-ddr-ch13";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_ddr_ch13_out_funnel_ddr_ch13: endpoint {
+ remote-endpoint =
+ <&funnel_ddr_ch13_in_tpdm_ddr_ch13>;
+ };
+ };
+ };
+
+ tpdm_ddr: tpdm@6e00000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x06e00000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-ddr";
+
+ status = "disabled";
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_ddr_out_funnel_ddr_0: endpoint {
+ remote-endpoint = <&funnel_ddr_0_in_tpdm_ddr>;
+ };
+ };
+ };
+
+ funnel_qatb: funnel@6005000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6005000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-qatb";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_qatb_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_funnel_qatb>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_qatb_in_tpda: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_out_funnel_qatb>;
+ };
+ };
+
+ port@2 {
+ reg = <3>;
+ qatb3_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_qatb3>;
+ };
+ };
+ };
+ };
+
+ cti0_apss: cti@78e0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x78e0000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss_cti0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1_apss: cti@78f0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x78f0000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss_cti1";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2_apss: cti@7900000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7900000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss_cti2";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0_ddr0: cti@6e01000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6e01000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_0_cti_0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1_ddr0: cti@6e02000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6e02000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_0_cti_1";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2_ddr0: cti@6e03000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6e03000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_0_cti_2";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0_ddr1: cti@6e0c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6e0c000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_1_cti_0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1_ddr1: cti@6e0d000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6e0d000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_1_cti_1";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2_ddr1: cti@6e0e000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6e0e000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_1_cti_2";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_ddr_ch02: cti@6e11000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6e11000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_ch02_dl_cti_0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_ddr_ch13: cti@6e21000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6e21000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_ch13_dl_cti_0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0_dlmm: cti@6c09000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c09000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlmm_cti0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1_dlmm: cti@6c0a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c0a000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlmm_cti1";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0_dlct: cti@6c2a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c2a000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct_cti0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1_dlct: cti@6c2b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c2b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct_cti1";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2_dlct: cti@6c2c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c2c000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct_cti2";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0: cti@6010000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6010000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti1: cti@6011000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6011000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti1";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti2: cti@6012000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6012000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti2";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,cti-gpio-trigout = <4>;
+ pinctrl-names = "cti-trigout-pctrl";
+ pinctrl-0 = <&trigout_a>;
+ };
+
+ cti3: cti@6013000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6013000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti3";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti4: cti@6014000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6014000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti4";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti5: cti@6015000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6015000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti5";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti6: cti@6016000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6016000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti6";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti7: cti@6017000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6017000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti7";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti8: cti@6018000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6018000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti8";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti9: cti@6019000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6019000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti9";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti10: cti@601a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601a000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti10";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti11: cti@601b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti11";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti12: cti@601c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601c000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti12";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti13: cti@601d000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601d000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti13";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti14: cti@601e000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601e000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti14";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti15: cti@601f000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601f000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti15";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti_cpu0: cti@7020000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7020000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu0";
+ cpu = <&CPU0>;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti_cpu1: cti@7120000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7120000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu1";
+ cpu = <&CPU1>;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu2: cti@7220000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7220000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu2";
+ cpu = <&CPU2>;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu3: cti@7320000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7320000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu3";
+ cpu = <&CPU3>;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu4: cti@7420000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7420000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu4";
+ cpu = <&CPU4>;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu5: cti@7520000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7520000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu5";
+ cpu = <&CPU5>;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu6: cti@7620000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7620000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu6";
+ cpu = <&CPU6>;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu7: cti@7720000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7720000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu7";
+ cpu = <&CPU7>;
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_gpu_m3: cti@6962000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6962000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-gpu_cortex_m3";
+ status = "disabled";
+ clocks = <&clock_aop QDSS_CLK>,
+ <&clock_gpucc GPU_CC_CXO_CLK>,
+ <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&clock_gpucc GPU_CC_CX_GMU_CLK>,
+ <&clock_gpucc GPU_CC_AHB_CLK>,
+ <&clock_cpucc L3_GPU_VOTE_CLK>;
+
+ clock-names = "apb_pclk",
+ "rbbmtimer_clk",
+ "mem_clk",
+ "mem_iface_clk",
+ "gmu_clk",
+ "gpu_cc_ahb",
+ "l3_vote";
+
+ qcom,proxy-clks = "rbbmtimer_clk",
+ "mem_clk",
+ "mem_iface_clk",
+ "gmu_clk",
+ "gpu_cc_ahb",
+ "l3_vote";
+
+ vddcx-supply = <&gpu_cx_gdsc>;
+ vdd-supply = <&gpu_gx_gdsc>;
+ regulator-names = "vddcx", "vdd";
+ qcom,proxy-regs = "vddcx", "vdd";
+ };
+
+ cti_gpu_isdb: cti@6961000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6961000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-gpu_isdb_cti";
+ status = "disabled";
+ clocks = <&clock_aop QDSS_CLK>,
+ <&clock_gpucc GPU_CC_CXO_CLK>,
+ <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&clock_gpucc GPU_CC_CX_GMU_CLK>,
+ <&clock_gpucc GPU_CC_AHB_CLK>,
+ <&clock_cpucc L3_GPU_VOTE_CLK>;
+
+ clock-names = "apb_pclk",
+ "rbbmtimer_clk",
+ "mem_clk",
+ "mem_iface_clk",
+ "gmu_clk",
+ "gpu_cc_ahb",
+ "l3_vote";
+
+ qcom,proxy-clks = "rbbmtimer_clk",
+ "mem_clk",
+ "mem_iface_clk",
+ "gmu_clk",
+ "gpu_cc_ahb",
+ "l3_vote";
+
+ vddcx-supply = <&gpu_cx_gdsc>;
+ vdd-supply = <&gpu_gx_gdsc>;
+ regulator-names = "vddcx", "vdd";
+ qcom,proxy-regs = "vddcx", "vdd";
+ };
+
+ cti_iris: cti@6831000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6831000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-iris_dl_cti";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_lpass: cti@6845000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6845000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-lpass_dl_cti";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_lpass_lpi: cti@6b21000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b21000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-lpass_lpi_cti";
+ status = "disabled";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_lpass_q6: cti@6b2b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b2b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-lpass_q6_cti";
+ status = "disabled";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_mdss: cti@6c61000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c61000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-mdss_dl_cti";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_npu_dl0: cti@6c42000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c42000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-npu_dl_cti_0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_npu_dl1: cti@6c43000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c43000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-npu_dl_cti_1";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_npu: cti@6c4b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c4b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-npu_q6_cti";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_titan: cti@6c13000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c13000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-sierra_a6_cti";
+ status = "disabled";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_sdc: cti@6b40000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b40000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ssc_cortex_m3";
+ status = "disabled";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_ssc0: cti@6b4b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b4b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ssc_cti0_q6";
+ status = "disabled";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_ssc1: cti@6b41000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b41000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ssc_cti1";
+ status = "disabled";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_ssc4: cti@6b4e000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b4e000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ssc_cti_noc";
+ status = "disabled";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0_swao:cti@6b00000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b00000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-swao_cti0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1_swao:cti@6b01000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b01000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-swao_cti1";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2_swao:cti@6b02000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b02000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-swao_cti2";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti3_swao:cti@6b03000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b03000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-swao_cti3";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_turing:cti@6982000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6982000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-turing_dl_cti";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_turing_q6:cti@698b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x698b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-turing_q6_cti";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_compute:cti@6c38000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c38000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-compute_dl_cti";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ ipcb_tgu: tgu@6b0b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb999>;
+ reg = <0x06b0b000 0x1000>;
+ reg-names = "tgu-base";
+ tgu-steps = <3>;
+ tgu-conditions = <4>;
+ tgu-regs = <4>;
+ tgu-timer-counters = <8>;
+
+ coresight-name = "coresight-tgu-ipcb";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ etm_turing: turing_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-turing-etm0";
+ qcom,inst-id = <13>;
+
+ port {
+ turing_etm0_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_turing_etm0>;
+ };
+ };
+ };
+
+ audio_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-audio-etm0";
+ qcom,inst-id = <5>;
+
+ port {
+ audio_etm0_out_funnel_swao: endpoint {
+ remote-endpoint =
+ <&funnel_swao_in_audio_etm0>;
+ };
+ };
+ };
+
+ ssc_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-ssc-etm0";
+ qcom,inst-id = <8>;
+
+ port {
+ ssc_etm0_out_funnel_swao: endpoint {
+ remote-endpoint =
+ <&funnel_swao_in_ssc_etm0>;
+ };
+ };
+ };
+
+ npu_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-npu-etm0";
+ qcom,inst-id = <14>;
+
+ port {
+ npu_etm0_out_funnel_npu: endpoint {
+ remote-endpoint =
+ <&funnel_npu_in_npu_etm0>;
+ };
+ };
+ };
+
+ funnel_apss_merg: funnel@7810000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x7810000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-apss-merg";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_apss_merg_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_funnel_apss_merg>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_apss_merg_in_funnel_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_apss_out_funnel_apss_merg>;
+ };
+ };
+
+ port@2 {
+ reg = <3>;
+ funnel_apss_merg_in_tpda_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_apss_out_funnel_apss_merg>;
+ };
+ };
+
+ };
+ };
+
+ etm0: etm@7040000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7040000 0x1000>;
+ cpu = <&CPU0>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm0";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm0_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm0>;
+ };
+ };
+ };
+
+ etm1: etm@7140000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7140000 0x1000>;
+ cpu = <&CPU1>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm1";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm1_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm1>;
+ };
+ };
+ };
+
+ etm2: etm@7240000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7240000 0x1000>;
+ cpu = <&CPU2>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm2";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm2_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm2>;
+ };
+ };
+ };
+
+ etm3: etm@7340000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7340000 0x1000>;
+ cpu = <&CPU3>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm3";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm3_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm3>;
+ };
+ };
+ };
+
+ etm4: etm@7440000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7440000 0x1000>;
+ cpu = <&CPU4>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm4";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm4_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm4>;
+ };
+ };
+ };
+
+ etm5: etm@7540000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7540000 0x1000>;
+ cpu = <&CPU5>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm5";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm5_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm5>;
+ };
+ };
+ };
+
+ etm6: etm@7640000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7640000 0x1000>;
+ cpu = <&CPU6>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm6";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm6_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm6>;
+ };
+ };
+ };
+
+ etm7: etm@7740000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7740000 0x1000>;
+ cpu = <&CPU7>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm7";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm7_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm7>;
+ };
+ };
+ };
+
+ funnel_apss: funnel@7800000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x7800000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-apss";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_apss_out_funnel_apss_merg: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merg_in_funnel_apss>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_apss_in_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm0_out_funnel_apss>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_apss_in_etm1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm1_out_funnel_apss>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ funnel_apss_in_etm2: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm2_out_funnel_apss>;
+ };
+ };
+
+ port@4 {
+ reg = <3>;
+ funnel_apss_in_etm3: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm3_out_funnel_apss>;
+ };
+ };
+
+ port@5 {
+ reg = <4>;
+ funnel_apss_in_etm4: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm4_out_funnel_apss>;
+ };
+ };
+
+ port@6 {
+ reg = <5>;
+ funnel_apss_in_etm5: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm5_out_funnel_apss>;
+ };
+ };
+
+ port@7 {
+ reg = <6>;
+ funnel_apss_in_etm6: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm6_out_funnel_apss>;
+ };
+ };
+
+ port@8 {
+ reg = <7>;
+ funnel_apss_in_etm7: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm7_out_funnel_apss>;
+ };
+ };
+ };
+ };
+
+ hwevent {
+ compatible = "qcom,coresight-hwevent";
+
+ coresight-name = "coresight-hwevent";
+ coresight-csr = <&csr>;
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-cvp.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-cvp.dtsi
new file mode 100755
index 0000000..460cd4a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-cvp.dtsi
@@ -0,0 +1,93 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/clock/qcom,videocc-kona.h>
+
+&soc {
+ msm_cvp: qcom,cvp@ab00000 {
+ compatible = "qcom,msm-cvp", "qcom,kona-cvp";
+ status = "ok";
+ reg = <0xab00000 0x100000>;
+ interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+
+ /* LLCC Cache */
+ cache-slice-names = "cvp";
+
+ /* Supply */
+ cvp-supply = <&mvs1c_gdsc>;
+ cvp-core-supply = <&mvs1_gdsc>;
+
+ /* Clocks */
+ clock-names = "gcc_video_axi1", "cvp_clk", "core_clk";
+ clocks = <&clock_gcc GCC_VIDEO_AXI1_CLK>,
+ <&clock_videocc VIDEO_CC_MVS1C_CLK>,
+ <&clock_videocc VIDEO_CC_MVS1_CLK>;
+ qcom,proxy-clock-names = "gcc_video_axi1",
+ "cvp_clk", "core_clk";
+
+ /* V2 clock frequency plan */
+ qcom,clock-configs = <0x0 0x1 0x1>;
+ qcom,allowed-clock-rates = <280000000 366000000 444000000>;
+
+ resets = <&clock_gcc GCC_VIDEO_AXI1_CLK_ARES>,
+ <&clock_videocc VIDEO_CC_MVS1C_CLK_ARES>;
+ reset-names = "cvp_axi_reset", "cvp_core_reset";
+
+ qcom,reg-presets = <0xB0088 0x0>;
+
+ /* Buses */
+ cvp_cnoc {
+ compatible = "qcom,msm-cvp,bus";
+ label = "cvp-cnoc";
+ qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
+ qcom,bus-governor = "performance";
+ qcom,bus-range-kbps = <1000 1000>;
+ };
+
+ cvp_bus_ddr {
+ compatible = "qcom,msm-cvp,bus";
+ label = "cvp-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_PROC>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,bus-governor = "performance";
+ qcom,bus-range-kbps = <1000 6533000>;
+ };
+
+ /* MMUs */
+ cvp_non_secure_cb {
+ compatible = "qcom,msm-cvp,context-bank";
+ label = "cvp_hlos";
+ iommus =
+ <&apps_smmu 0x2120 0x400>;
+ buffer-types = <0xfff>;
+ qcom,iommu-dma-addr-pool = <0x4b000000 0x90000000>;
+ };
+
+
+ cvp_secure_nonpixel_cb {
+ compatible = "qcom,msm-cvp,context-bank";
+ label = "cvp_sec_nonpixel";
+ iommus =
+ <&apps_smmu 0x2124 0x400>;
+ buffer-types = <0x741>;
+ qcom,iommu-dma-addr-pool = <0x01000000 0x25800000>;
+ qcom,iommu-vmid = <0xB>;
+ };
+
+ cvp_secure_pixel_cb {
+ compatible = "qcom,msm-cvp,context-bank";
+ label = "cvp_sec_pixel";
+ iommus =
+ <&apps_smmu 0x2123 0x400>;
+ buffer-types = <0x106>;
+ qcom,iommu-dma-addr-pool = <0x26800000 0x24800000>;
+ qcom,iommu-vmid = <0xA>;
+ };
+
+ /* Memory Heaps */
+ qcom,msm-cvp,mem_cdsp {
+ compatible = "qcom,msm-cvp,mem-cdsp";
+ memory-region = <&cdsp_mem>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-gpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-gpu.dtsi
new file mode 100755
index 0000000..9160458
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-gpu.dtsi
@@ -0,0 +1,350 @@
+
+#define MHZ_TO_KBPS(mhz, w) ((mhz * 1000000 * w) / (1024))
+
+&soc {
+ pil_gpu: qcom,kgsl-hyp {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <13>;
+ qcom,firmware-name = "a650_zap";
+ };
+
+ msm_bus: qcom,kgsl-busmon {
+ label = "kgsl-busmon";
+ compatible = "qcom,kgsl-busmon";
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
+ gpubw: qcom,gpubw {
+ compatible = "qcom,devbw-ddr";
+ governor = "bw_vbif";
+ qcom,src-dst-ports = <26 512>;
+ operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-381000000 {
+ opp-hz = /bits/ 64 <381000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-290000000 {
+ opp-hz = /bits/ 64 <290000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+
+ msm_gpu: qcom,kgsl-3d0@3d00000 {
+ label = "kgsl-3d0";
+ compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
+ status = "ok";
+ reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
+ <0x3de0000 0x10000>, <0x3d8b000 0x2000>,
+ <0x06900000 0x80000>;
+ reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
+ "isense_cntl", "qdss_gfx";
+ interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+ qcom,id = <0>;
+
+ qcom,chipid = <0x06050000>;
+
+ qcom,initial-pwrlevel = <2>;
+
+ qcom,idle-timeout = <80>; /* msecs */
+
+ qcom,no-nap;
+
+ qcom,highest-bank-bit = <16>;
+
+ qcom,min-access-length = <32>;
+
+ qcom,ubwc-mode = <4>;
+
+ qcom,snapshot-size = <0x200000>; /* bytes */
+
+ qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
+
+ #cooling-cells = <2>;
+ qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";
+
+ qcom,pm-qos-active-latency = <44>;
+
+ clocks = <&clock_gpucc GPU_CC_CXO_CLK>,
+ <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&clock_gpucc GPU_CC_CX_GMU_CLK>,
+ <&clock_gpucc GPU_CC_AHB_CLK>,
+ <&clock_cpucc L3_GPU_VOTE_CLK>;
+
+ clock-names = "rbbmtimer_clk", "mem_clk",
+ "mem_iface_clk", "gmu_clk",
+ "gpu_cc_ahb", "l3_vote";
+
+ qcom,isense-clk-on-level = <1>;
+
+ /* Bus Scale Settings */
+ qcom,gpubw-dev = <&gpubw>;
+ qcom,bus-control;
+
+ /* GDSC regulator names */
+ regulator-names = "vddcx", "vdd";
+ /* GDSC oxili regulators */
+ vddcx-supply = <&gpu_cx_gdsc>;
+ vdd-supply = <&gpu_gx_gdsc>;
+
+ /* GPU OPP data */
+ operating-points-v2 = <&gpu_opp_table>;
+
+ nvmem-cells = <&gpu_lm_efuse>, <&gpu_speed_bin>;
+ nvmem-cell-names = "isense_slope", "speed_bin";
+
+ qcom,bus-accesses-ddr7 = <970>;
+ qcom,bus-accesses-ddr8 = <1162>;
+
+ /* bus table */
+ qcom,gpu-bus-table-0 {
+ compatible = "qcom,gpu-bus-table",
+ "qcom,gpu-bus-table-ddr7";
+ qcom,msm-bus,name = "grp3d";
+ qcom,msm-bus,num-cases = <12>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <26 512 0 MHZ_TO_KBPS(0, 4)>, /* index=0 */
+ <26 512 0 MHZ_TO_KBPS(200, 4)>, /* index=1 */
+ <26 512 0 MHZ_TO_KBPS(300, 4)>, /* index=2 */
+ <26 512 0 MHZ_TO_KBPS(451, 4)>, /* index=3 */
+ <26 512 0 MHZ_TO_KBPS(547, 4)>, /* index=4 */
+ <26 512 0 MHZ_TO_KBPS(681, 4)>, /* index=5 */
+ <26 512 0 MHZ_TO_KBPS(768, 4)>, /* index=6 */
+ <26 512 0 MHZ_TO_KBPS(1017, 4)>, /* index=7 */
+ <26 512 0 MHZ_TO_KBPS(1353, 4)>, /* index=8 */
+ <26 512 0 MHZ_TO_KBPS(1555, 4)>, /* index=9 */
+ <26 512 0 MHZ_TO_KBPS(1804, 4)>, /* index=10 */
+ <26 512 0 MHZ_TO_KBPS(2092, 4)>; /* index=11 */
+ };
+
+ qcom,gpu-bus-table-1 {
+ compatible = "qcom,gpu-bus-table",
+ "qcom,gpu-bus-table-ddr8";
+ qcom,msm-bus,name = "grp3d";
+ qcom,msm-bus,num-cases = <12>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <26 512 0 MHZ_TO_KBPS(0, 4)>, /* index=0 */
+ <26 512 0 MHZ_TO_KBPS(200, 4)>, /* index=1 */
+ <26 512 0 MHZ_TO_KBPS(300, 4)>, /* index=2 */
+ <26 512 0 MHZ_TO_KBPS(451, 4)>, /* index=3 */
+ <26 512 0 MHZ_TO_KBPS(547, 4)>, /* index=4 */
+ <26 512 0 MHZ_TO_KBPS(681, 4)>, /* index=5 */
+ <26 512 0 MHZ_TO_KBPS(768, 4)>, /* index=6 */
+ <26 512 0 MHZ_TO_KBPS(1017, 4)>, /* index=7 */
+ <26 512 0 MHZ_TO_KBPS(1555, 4)>, /* index=8 */
+ <26 512 0 MHZ_TO_KBPS(1804, 4)>, /* index=9 */
+ <26 512 0 MHZ_TO_KBPS(2092, 4)>, /* index=10 */
+ <26 512 0 MHZ_TO_KBPS(2736, 4)>; /* index=11 */
+ };
+
+ qcom,l3-pwrlevels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "qcom,l3-pwrlevels";
+
+ qcom,l3-pwrlevel@0 {
+ reg = <0>;
+ qcom,l3-freq = <0>;
+ };
+
+ qcom,l3-pwrlevel@1 {
+ reg = <1>;
+ qcom,l3-freq = <864000000>;
+ };
+
+ qcom,l3-pwrlevel@2 {
+ reg = <2>;
+ qcom,l3-freq = <1344000000>;
+ };
+ };
+
+ /* GPU Mempools */
+ qcom,gpu-mempools {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,gpu-mempools";
+
+ /* 4K Page Pool configuration */
+ qcom,gpu-mempool@0 {
+ reg = <0>;
+ qcom,mempool-page-size = <4096>;
+ qcom,mempool-reserved = <2048>;
+ qcom,mempool-allocate;
+ };
+ /* 8K Page Pool configuration */
+ qcom,gpu-mempool@1 {
+ reg = <1>;
+ qcom,mempool-page-size = <8192>;
+ qcom,mempool-reserved = <1024>;
+ qcom,mempool-allocate;
+ };
+ /* 64K Page Pool configuration */
+ qcom,gpu-mempool@2 {
+ reg = <2>;
+ qcom,mempool-page-size = <65536>;
+ qcom,mempool-reserved = <256>;
+ };
+ /* 1M Page Pool configuration */
+ qcom,gpu-mempool@3 {
+ reg = <3>;
+ qcom,mempool-page-size = <1048576>;
+ qcom,mempool-reserved = <32>;
+ };
+ };
+
+ /* Power levels */
+ qcom,gpu-pwrlevels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "qcom,gpu-pwrlevels";
+
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <480000000>;
+ qcom,bus-freq-ddr7 = <11>;
+ qcom,bus-min-ddr7 = <11>;
+ qcom,bus-max-ddr7 = <11>;
+
+ qcom,bus-freq-ddr8 = <11>;
+ qcom,bus-min-ddr8 = <11>;
+ qcom,bus-max-ddr8 = <11>;
+ };
+
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <381000000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <7>;
+ qcom,bus-max-ddr7 = <11>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <7>;
+ qcom,bus-max-ddr8 = <11>;
+ };
+
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <290000000>;
+ qcom,bus-freq-ddr7 = <2>;
+ qcom,bus-min-ddr7 = <1>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <2>;
+ qcom,bus-min-ddr8 = <1>;
+ qcom,bus-max-ddr8 = <8>;
+ };
+
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+ };
+
+ kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
+ compatible = "qcom,kgsl-smmu-v2";
+
+ reg = <0x03da0000 0x10000>;
+ /* CB5(ATOS) & CB5/6/7 are protected by HYP */
+ qcom,protect = <0xa0000 0xc000>;
+
+ clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&clock_gpucc GPU_CC_AHB_CLK>;
+ clock-names = "gcc_gpu_memnoc_gfx",
+ "gcc_gpu_snoc_dvm_gfx",
+ "gpu_cc_ahb";
+
+ qcom,secure_align_mask = <0xfff>;
+ qcom,retention;
+ qcom,hyp_secure_alloc;
+
+ gfx3d_user: gfx3d_user {
+ compatible = "qcom,smmu-kgsl-cb";
+ label = "gfx3d_user";
+ iommus = <&kgsl_smmu 0x0 0x401>;
+ qcom,iommu-dma = "disabled";
+ qcom,gpu-offset = <0xa8000>;
+ };
+
+ gfx3d_secure: gfx3d_secure {
+ compatible = "qcom,smmu-kgsl-cb";
+ label = "gfx3d_secure";
+ iommus = <&kgsl_smmu 0x2 0x400>;
+ qcom,iommu-dma = "disabled";
+ };
+ };
+
+ gmu: qcom,gmu@3d6a000 {
+ label = "kgsl-gmu";
+ compatible = "qcom,gpu-gmu";
+
+ reg = <0x3d6a000 0x30000>,
+ <0xb290000 0x10000>,
+ <0xb490000 0x10000>;
+ reg-names = "kgsl_gmu_reg",
+ "kgsl_gmu_pdc_cfg",
+ "kgsl_gmu_pdc_seq";
+
+ interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
+ <0 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";
+
+ qcom,msm-bus,name = "cnoc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <26 10036 0 0>, /* CNOC off */
+ <26 10036 0 100>; /* CNOC on */
+
+ regulator-names = "vddcx", "vdd";
+ vddcx-supply = <&gpu_cx_gdsc>;
+ vdd-supply = <&gpu_gx_gdsc>;
+
+ clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,
+ <&clock_gpucc GPU_CC_CXO_CLK>,
+ <&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&clock_gpucc GPU_CC_AHB_CLK>,
+ <&clock_aop QDSS_CLK>;
+
+ clock-names = "gmu_clk", "cxo_clk", "axi_clk",
+ "memnoc_clk", "gpu_cc_ahb",
+ "apb_pclk";
+
+ /* AOP mailbox for sending ACD enable and disable messages */
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "aop";
+
+ gmu_user: gmu_user {
+ compatible = "qcom,smmu-gmu-user-cb";
+ iommus = <&kgsl_smmu 0x4 0x400>;
+ qcom,iommu-dma = "disabled";
+ };
+
+ gmu_kernel: gmu_kernel {
+ compatible = "qcom,smmu-gmu-kernel-cb";
+ iommus = <&kgsl_smmu 0x5 0x400>;
+ qcom,iommu-dma = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-hdk-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/kona-hdk-overlay.dts
new file mode 100755
index 0000000..4368a5f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-hdk-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-kona.h>
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "kona-hdk.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona HDK";
+ compatible = "qcom,kona-hdk", "qcom,kona", "qcom,hdk";
+ qcom,board-id = <0x01001F 0x01>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-hdk.dts b/arch/arm64/boot/dts/vendor/qcom/kona-hdk.dts
new file mode 100755
index 0000000..0c62e71
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-hdk.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.dtsi"
+#include "kona-hdk.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona HDK";
+ compatible = "qcom,kona-hdk", "qcom,kona", "qcom,hdk";
+ qcom,board-id = <0x01001F 0x01>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-hdk.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-hdk.dtsi
new file mode 100755
index 0000000..bc96ee8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-hdk.dtsi
@@ -0,0 +1,135 @@
+#include "kona-qrd.dtsi"
+
+&qupv3_se13_i2c {
+ status = "ok";
+ qcom,i2c-touch-active = "";
+
+ st_fts@49 {
+ st,x-flip;
+ st,y-flip;
+ };
+};
+
+&kona_snd {
+ qcom,msm-mbhc-usbc-audio-supported = <0>;
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+};
+
+&redriver {
+ status = "disabled";
+};
+
+&usb1 {
+ qcom,ignore-wakeup-src-in-hostmode;
+
+ dwc3@a800000 {
+ dr_mode = "host";
+ };
+};
+
+&usb2_phy0 {
+ qcom,param-override-seq =
+ <0xc7 0x6c
+ 0x03 0x70
+ 0x03 0x74>;
+};
+
+&mdm0 {
+ status = "disabled";
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ qcom,clk-freq-out = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ lt9611: lt,lt9611@2b {
+ compatible = "lt,lt9611uxc";
+ reg = <0x2b>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <1 0>;
+ interrupt-names = "lt_irq";
+ lt,irq-gpio = <&tlmm 1 0x0>;
+ lt,reset-gpio = <&tlmm 2 0x0>;
+ instance_id = <0>;
+ lt,non-pluggable;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <<9611_pins>;
+
+ lt,preferred-mode = "1920x1080";
+
+ lt,customize-modes {
+ lt,customize-mode-id@0 {
+ lt,mode-h-active = <1920>;
+ lt,mode-h-front-porch = <88>;
+ lt,mode-h-pulse-width = <44>;
+ lt,mode-h-back-porch = <148>;
+ lt,mode-h-active-high;
+ lt,mode-v-active = <1080>;
+ lt,mode-v-front-porch = <4>;
+ lt,mode-v-pulse-width = <5>;
+ lt,mode-v-back-porch = <36>;
+ lt,mode-v-active-high;
+ lt,mode-refresh-rate = <60>;
+ lt,mode-clock-in-khz = <148500>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lt9611_in: endpoint {
+ remote-endpoint = <&ext_dsi_out>;
+ };
+ };
+
+ };
+ };
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_ext_bridge_1080p>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ ext_dsi_out: endpoint {
+ remote-endpoint = <<9611_in>;
+ };
+ };
+ };
+};
+
+&pcie2 {
+ qcom,boot-option = <0x0>;
+};
+
+&mhi_0 {
+ reg = <0x100 0x0 0x0 0x0 0x0>;
+};
+
+&pcie2_rp {
+ #address-cells = <5>;
+ #size-cells = <0>;
+
+ nvme: nvme {
+ reg = <0 0 0 0 0>;
+ qcom,iommu-group = <&nvme_pci_iommu_group>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nvme_pci_iommu_group: nvme_pci_iommu_group {
+ qcom,iommu-dma-addr-pool = <0x20000000 0x40000000>;
+ qcom,iommu-dma = "fastmap";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-ion.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-ion.dtsi
new file mode 100755
index 0000000..610d9f3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-ion.dtsi
@@ -0,0 +1,62 @@
+&soc {
+ qcom,ion {
+ compatible = "qcom,msm-ion";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ system_heap: qcom,ion-heap@25 {
+ reg = <25>;
+ qcom,ion-heap-type = "SYSTEM";
+ };
+
+ adsp_heap: qcom,ion-heap@22 {
+ reg = <22>;
+ memory-region = <&sdsp_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ system_secure_heap: qcom,ion-heap@9 {
+ reg = <9>;
+ qcom,ion-heap-type = "SYSTEM_SECURE";
+ };
+
+ qcom,ion-heap@26 { /* USER CONTIG HEAP */
+ reg = <26>;
+ memory-region = <&user_contig_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@27 { /* QSEECOM HEAP */
+ reg = <27>;
+ memory-region = <&qseecom_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@19 { /* QSEECOM TA HEAP */
+ reg = <19>;
+ memory-region = <&qseecom_ta_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@13 { /* SPSS HEAP */
+ reg = <13>;
+ memory-region = <&sp_mem>;
+ qcom,ion-heap-type = "HYP_CMA";
+ };
+
+ qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */
+ reg = <10>;
+ memory-region = <&secure_display_memory>;
+ qcom,ion-heap-type = "HYP_CMA";
+ };
+
+ qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */
+ reg = <14>;
+ qcom,ion-heap-type = "SECURE_CARVEOUT";
+ cdsp {
+ memory-region = <&cdsp_secure_heap>;
+ token = <0x20000000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-iot-rb5-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-iot-rb5-audio.dtsi
new file mode 100755
index 0000000..7d658cf
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-iot-rb5-audio.dtsi
@@ -0,0 +1,300 @@
+
+&spkr_2_sd_n_sleep {
+ mux {
+ pins = "gpio130";
+ };
+
+ config {
+ pins = "gpio130";
+ };
+};
+
+&spkr_2_sd_n_active {
+ mux {
+ pins = "gpio130";
+ };
+
+ config {
+ pins = "gpio130";
+ };
+};
+
+
+&bolero {
+ qcom,num-macros = <4>;
+ bolero-clk-rsc-mngr {
+ compatible = "qcom,bolero-clk-rsc-mngr";
+ qcom,fs-gen-sequence = <0x3000 0x1>,
+ <0x3004 0x1>, <0x3080 0x2>;
+ qcom,rx_mclk_mode_muxsel = <0x033240D8>;
+ qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
+ qcom,va_mclk_mode_muxsel = <0x033A0000>;
+ clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
+ "wsa_core_clk", "wsa_npl_clk", "va_core_clk", "va_npl_clk";
+ clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
+ <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
+ <&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
+ <&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
+ };
+
+ tx_macro: tx-macro@3220000 {
+ compatible = "qcom,tx-macro";
+ reg = <0x3220000 0x0>;
+ clock-names = "tx_core_clk", "tx_npl_clk";
+ clocks = <&clock_audio_tx_1 0>,
+ <&clock_audio_tx_2 0>;
+ qcom,tx-swr-gpios = <&tx_swr_gpios>;
+ qcom,tx-dmic-sample-rate = <2400000>;
+ swr2: tx_swr_master {
+ status = "disabled";
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ qcom,swr_master_id = <3>;
+ qcom,mipi-sdw-block-packing-mode = <1>;
+ swrm-io-base = <0x3230000 0x0>;
+ interrupts-extended =
+ <&intc GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq", "swr_wake_irq";
+ qcom,swr-wakeup-required = <1>;
+ qcom,swr-num-ports = <5>;
+ qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,
+ <2 ADC1 0x1>, <2 ADC2 0x2>,
+ <3 ADC3 0x1>, <3 ADC4 0x2>,
+ <4 DMIC0 0x1>, <4 DMIC1 0x2>,
+ <4 DMIC2 0x4>, <4 DMIC3 0x8>,
+ <5 DMIC4 0x1>, <5 DMIC5 0x2>,
+ <5 DMIC6 0x4>, <5 DMIC7 0x8>;
+ qcom,swr-num-dev = <1>;
+ qcom,swr-clock-stop-mode0 = <1>;
+ qcom,swr-mstr-irq-wakeup-capable = <1>;
+ wcd938x_tx_slave: wcd938x-tx-slave {
+ compatible = "qcom,wcd938x-slave";
+ reg = <0x0D 0x01170223>;
+ };
+ };
+ };
+
+ rx_macro: rx-macro@3200000 {
+ compatible = "qcom,rx-macro";
+ reg = <0x3200000 0x0>;
+ clock-names = "rx_core_clk", "rx_npl_clk";
+ clocks = <&clock_audio_rx_1 0>,
+ <&clock_audio_rx_2 0>;
+ qcom,rx-swr-gpios = <&rx_swr_gpios>;
+ qcom,rx_mclk_mode_muxsel = <0x033240D8>;
+ qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ swr1: rx_swr_master {
+ status = "disabled";
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ qcom,swr_master_id = <2>;
+ qcom,mipi-sdw-block-packing-mode = <1>;
+ swrm-io-base = <0x3210000 0x0>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq";
+ qcom,swr-num-ports = <5>;
+ qcom,swr-port-mapping = <1 HPH_L 0x1>,
+ <1 HPH_R 0x2>, <2 CLSH 0x1>,
+ <3 COMP_L 0x1>, <3 COMP_R 0x2>,
+ <4 LO 0x1>, <5 DSD_L 0x1>,
+ <5 DSD_R 0x2>;
+ qcom,swr-num-dev = <1>;
+ qcom,swr-clock-stop-mode0 = <1>;
+ wcd938x_rx_slave: wcd938x-rx-slave {
+ compatible = "qcom,wcd938x-slave";
+ reg = <0x0D 0x01170224>;
+ };
+ };
+ };
+
+ wsa_macro: wsa-macro@3240000 {
+ compatible = "qcom,wsa-macro";
+ reg = <0x3240000 0x0>;
+ clock-names = "wsa_core_clk", "wsa_npl_clk";
+ clocks = <&clock_audio_wsa_1 0>,
+ <&clock_audio_wsa_2 0>;
+ qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
+ qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ swr0: wsa_swr_master {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ qcom,swr_master_id = <1>;
+ qcom,mipi-sdw-block-packing-mode = <0>;
+ swrm-io-base = <0x3250000 0x0>;
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq";
+ qcom,swr-num-ports = <8>;
+ qcom,swr-port-mapping = <1 SPKR_L 0x1>,
+ <2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
+ <4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
+ <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
+ <8 SPKR_R_VI 0x3>;
+ qcom,swr-num-dev = <2>;
+ wsa881x_0211: wsa881x@20170211 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x20170211>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero>;
+ };
+
+ wsa881x_0212: wsa881x@20170212 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x20170212>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero>;
+ };
+
+ wsa881x_0213: wsa881x@21170213 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x21170213>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero>;
+ };
+
+ wsa881x_0214: wsa881x@21170214 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x21170214>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero>;
+ };
+ };
+
+ };
+
+ wcd938x_codec: wcd938x-codec {
+ status = "disabled";
+ compatible = "qcom,wcd938x-codec";
+ qcom,split-codec = <1>;
+ qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
+ <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
+ <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
+ <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
+ <4 DSD_R 0x2 0 DSD_R>;
+ qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
+ <0 ADC2 0x2 0 ADC2>, <1 ADC3 0x1 0 ADC3>,
+ <1 ADC4 0x2 0 ADC4>, <2 DMIC0 0x1 0 DMIC0>,
+ <2 DMIC1 0x2 0 DMIC1>, <2 MBHC 0x4 0 DMIC2>,
+ <2 DMIC2 0x4 0 DMIC2>, <2 DMIC3 0x8 0 DMIC3>,
+ <3 DMIC4 0x1 0 DMIC4>, <3 DMIC5 0x2 0 DMIC5>,
+ <3 DMIC6 0x4 0 DMIC6>, <3 DMIC7 0x8 0 DMIC7>;
+
+ qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
+ qcom,rx-slave = <&wcd938x_rx_slave>;
+ qcom,tx-slave = <&wcd938x_tx_slave>;
+
+ cdc-vdd-rxtx-supply = <&S4A>;
+ qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-rxtx-current = <30000>;
+
+ cdc-vddio-supply = <&S4A>;
+ qcom,cdc-vddio-voltage = <1800000 1800000>;
+ qcom,cdc-vddio-current = <30000>;
+
+ cdc-vdd-buck-supply = <&S4A>;
+ qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-buck-current = <650000>;
+
+ cdc-vdd-mic-bias-supply = <&BOB>;
+ qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
+ qcom,cdc-vdd-mic-bias-current = <30000>;
+
+ qcom,cdc-micbias1-mv = <1800>;
+ qcom,cdc-micbias2-mv = <1800>;
+ qcom,cdc-micbias3-mv = <1800>;
+ qcom,cdc-micbias4-mv = <1800>;
+
+ qcom,cdc-static-supplies = "cdc-vdd-rxtx",
+ "cdc-vddio",
+ "cdc-vdd-buck",
+ "cdc-vdd-mic-bias";
+ };
+
+};
+
+&kona_snd {
+ qcom,model = "kona-iot-snd-card";
+ qcom,audio-routing =
+ "TX DMIC0", "Digital Mic0",
+ "TX DMIC1", "Digital Mic1",
+ "TX DMIC2", "Digital Mic2",
+ "TX DMIC3", "Digital Mic3",
+ "TX DMIC4", "Digital Mic4",
+ "TX DMIC5", "Digital Mic5",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA DMIC0", "Digital Mic0",
+ "VA DMIC1", "Digital Mic1",
+ "VA DMIC2", "Digital Mic2",
+ "VA DMIC3", "Digital Mic3",
+ "VA DMIC4", "Digital Mic4",
+ "VA DMIC5", "Digital Mic5",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT";
+ qcom,msm-mbhc-usbc-audio-supported = <1>;
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>,
+ <&wsa881x_0213>, <&wsa881x_0214>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+ "SpkrLeft", "SpkrRight";
+ qcom,codec-max-aux-devs = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-lpi-ar.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-lpi-ar.dtsi
new file mode 100755
index 0000000..adb00ed
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-lpi-ar.dtsi
@@ -0,0 +1,1679 @@
+&spf_core_platform {
+ lpi_tlmm_ar: lpi_pinctrl_ar {
+ compatible = "qcom,lpi-pinctrl";
+ reg = <0x33c0000 0x0>;
+ qcom,slew-reg = <0x355a000 0x0>;
+ qcom,num-gpios = <14>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
+ <0x00002000>, <0x00003000>,
+ <0x00004000>, <0x00005000>,
+ <0x00006000>, <0x00007000>,
+ <0x00008000>, <0x00009000>,
+ <0x0000A000>, <0x0000B000>,
+ <0x0000C000>, <0x0000D000>;
+ qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>,
+ <0x00000004>, <0x00000008>,
+ <0x0000000A>, <0x0000000C>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000010>, <0x00000012>,
+ <0x00000000>, <0x00000000>;
+
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote_ar 0>,
+ <&lpass_audio_hw_vote_ar 0>;
+
+ quat_mi2s_sck_ar {
+ quat_mi2s_sck_sleep_ar: quat_mi2s_sck_sleep_ar {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sck_active_ar: quat_mi2s_sck_active_ar {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_ws_ar {
+ quat_mi2s_ws_sleep_ar: quat_mi2s_ws_sleep_ar {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_ws_active_ar: quat_mi2s_ws_active_ar {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd0_ar {
+ quat_mi2s_sd0_sleep_ar: quat_mi2s_sd0_sleep_ar {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd0_active_ar: quat_mi2s_sd0_active_ar {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd1_ar {
+ quat_mi2s_sd1_sleep_ar: quat_mi2s_sd1_sleep_ar {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd1_active_ar: quat_mi2s_sd1_active_ar {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd2_ar {
+ quat_mi2s_sd2_sleep_ar: quat_mi2s_sd2_sleep_ar {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd2_active_ar: quat_mi2s_sd2_active_ar {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd3_ar {
+ quat_mi2s_sd3_sleep_ar: quat_mi2s_sd3_sleep_ar {
+ mux {
+ pins = "gpio5";
+ function = "func4";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd3_active_ar: quat_mi2s_sd3_active_ar {
+ mux {
+ pins = "gpio5";
+ function = "func4";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sck_ar {
+ lpi_i2s1_sck_sleep_ar: lpi_i2s1_sck_sleep_ar {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sck_active_ar: lpi_i2s1_sck_active_ar {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_ws_ar {
+ lpi_i2s1_ws_sleep_ar: lpi_i2s1_ws_sleep_ar {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_ws_active_ar: lpi_i2s1_ws_active_ar {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sd0_ar {
+ lpi_i2s1_sd0_sleep_ar: lpi_i2s1_sd0_sleep_ar {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sd0_active_ar: lpi_i2s1_sd0_active_ar {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sd1_ar {
+ lpi_i2s1_sd1_sleep_ar: lpi_i2s1_sd1_sleep_ar {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sd1_active_ar: lpi_i2s1_sd1_active_ar {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sck_ar {
+ lpi_i2s2_sck_sleep_ar: lpi_i2s2_sck_sleep_ar {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sck_active_ar: lpi_i2s2_sck_active_ar {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_ws_ar {
+ lpi_i2s2_ws_sleep_ar: lpi_i2s2_ws_sleep_ar {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_ws_active_ar: lpi_i2s2_ws_active_ar {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sd0_ar {
+ lpi_i2s2_sd0_sleep_ar: lpi_i2s2_sd0_sleep_ar {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sd0_active_ar: lpi_i2s2_sd0_active_ar {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sd1_ar {
+ lpi_i2s2_sd1_sleep_ar: lpi_i2s2_sd1_sleep_ar {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sd1_active_ar: lpi_i2s2_sd1_active_ar {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sck_ar {
+ quat_tdm_sck_sleep_ar: quat_tdm_sck_sleep_ar {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sck_active_ar: quat_tdm_sck_active_ar {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_ws_ar {
+ quat_tdm_ws_sleep_ar: quat_tdm_ws_sleep_ar {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_ws_active_ar: quat_tdm_ws_active_ar {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd0_ar {
+ quat_tdm_sd0_sleep_ar: quat_tdm_sd0_sleep_ar {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd0_active_ar: quat_tdm_sd0_active_ar {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd1_ar {
+ quat_tdm_sd1_sleep_ar: quat_tdm_sd1_sleep_ar {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd1_active_ar: quat_tdm_sd1_active_ar {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd2_ar {
+ quat_tdm_sd2_sleep_ar: quat_tdm_sd2_sleep_ar {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd2_active_ar: quat_tdm_sd2_active_ar {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd3_ar {
+ quat_tdm_sd3_sleep_ar: quat_tdm_sd3_sleep_ar {
+ mux {
+ pins = "gpio5";
+ function = "func4";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd3_active_ar: quat_tdm_sd3_active_ar {
+ mux {
+ pins = "gpio5";
+ function = "func4";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sck_ar {
+ lpi_tdm1_sck_sleep_ar: lpi_tdm1_sck_sleep_ar {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sck_active_ar: lpi_tdm1_sck_active_ar {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_ws_ar {
+ lpi_tdm1_ws_sleep_ar: lpi_tdm1_ws_sleep_ar {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_ws_active_ar: lpi_tdm1_ws_active_ar {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sd0_ar {
+ lpi_tdm1_sd0_sleep_ar: lpi_tdm1_sd0_sleep_ar {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sd0_active_ar: lpi_tdm1_sd0_active_ar {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sd1_ar {
+ lpi_tdm1_sd1_sleep_ar: lpi_tdm1_sd1_sleep_ar {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sd1_active_ar: lpi_tdm1_sd1_active_ar {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sck_ar {
+ lpi_tdm2_sck_sleep_ar: lpi_tdm2_sck_sleep_ar {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sck_active_ar: lpi_tdm2_sck_active_ar {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_ws_ar {
+ lpi_tdm2_ws_sleep_ar: lpi_tdm2_ws_sleep_ar {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_ws_active_ar: lpi_tdm2_ws_active_ar {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sd0_ar {
+ lpi_tdm2_sd0_sleep_ar: lpi_tdm2_sd0_sleep_ar {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sd0_active_ar: lpi_tdm2_sd0_active_ar {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sd1_ar {
+ lpi_tdm2_sd1_sleep_ar: lpi_tdm2_sd1_sleep_ar {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sd1_active_ar: lpi_tdm2_sd1_active_ar {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sck_ar {
+ quat_aux_sck_sleep_ar: quat_aux_sck_sleep_ar {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sck_active_ar: quat_aux_sck_active_ar {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_ws_ar {
+ quat_aux_ws_sleep_ar: quat_aux_ws_sleep_ar {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_ws_active_ar: quat_aux_ws_active_ar {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd0_ar {
+ quat_aux_sd0_sleep_ar: quat_aux_sd0_sleep_ar {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd0_active_ar: quat_aux_sd0_active_ar {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd1_ar {
+ quat_aux_sd1_sleep_ar: quat_aux_sd1_sleep_ar {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd1_active_ar: quat_aux_sd1_active_ar {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd2_ar {
+ quat_aux_sd2_sleep_ar: quat_aux_sd2_sleep_ar {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd2_active_ar: quat_aux_sd2_active_ar {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd3_ar {
+ quat_aux_sd3_sleep_ar: quat_aux_sd3_sleep_ar {
+ mux {
+ pins = "gpio5";
+ function = "func4";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd3_active_ar: quat_aux_sd3_active_ar {
+ mux {
+ pins = "gpio5";
+ function = "func4";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sck_ar {
+ lpi_aux1_sck_sleep_ar: lpi_aux1_sck_sleep_ar {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sck_active_ar: lpi_aux1_sck_active_ar {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_ws_ar {
+ lpi_aux1_ws_sleep_ar: lpi_aux1_ws_sleep_ar {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_ws_active_ar: lpi_aux1_ws_active_ar {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sd0_ar {
+ lpi_aux1_sd0_sleep_ar: lpi_aux1_sd0_sleep_ar {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sd0_active_ar: lpi_aux1_sd0_active_ar {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sd1_ar {
+ lpi_aux1_sd1_sleep_ar: lpi_aux1_sd1_sleep_ar {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sd1_active_ar: lpi_aux1_sd1_active_ar {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sck_ar {
+ lpi_aux2_sck_sleep_ar: lpi_aux2_sck_sleep_ar {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sck_active_ar: lpi_aux2_sck_active_ar {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_ws_ar {
+ lpi_aux2_ws_sleep_ar: lpi_aux2_ws_sleep_ar {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_ws_active_ar: lpi_aux2_ws_active_ar {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sd0_ar {
+ lpi_aux2_sd0_sleep_ar: lpi_aux2_sd0_sleep_ar {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sd0_active_ar: lpi_aux2_sd0_active_ar {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sd1_ar {
+ lpi_aux2_sd1_sleep_ar: lpi_aux2_sd1_sleep_ar {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sd1_active_ar: lpi_aux2_sd1_active_ar {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ wsa_swr_clk_pin_ar {
+ wsa_swr_clk_sleep_ar: wsa_swr_clk_sleep_ar {
+ mux {
+ pins = "gpio10";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ wsa_swr_clk_active_ar: wsa_swr_clk_active_ar {
+ mux {
+ pins = "gpio10";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+ };
+ };
+
+ wsa_swr_data_pin_ar {
+ wsa_swr_data_sleep_ar: wsa_swr_data_sleep_ar {
+ mux {
+ pins = "gpio11";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ wsa_swr_data_active_ar: wsa_swr_data_active_ar {
+ mux {
+ pins = "gpio11";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+ };
+
+ tx_swr_clk_sleep_ar: tx_swr_clk_sleep_ar {
+ mux {
+ pins = "gpio0";
+ function = "func1";
+ input-enable;
+ bias-pull-down;
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>;
+ };
+ };
+
+ tx_swr_clk_active_ar: tx_swr_clk_active_ar {
+ mux {
+ pins = "gpio0";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+ };
+
+ tx_swr_data1_sleep_ar: tx_swr_data1_sleep_ar {
+ mux {
+ pins = "gpio1";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>;
+ input-enable;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_data1_active_ar: tx_swr_data1_active_ar {
+ mux {
+ pins = "gpio1";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_data2_sleep_ar: tx_swr_data2_sleep_ar {
+ mux {
+ pins = "gpio2";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ tx_swr_data2_active_ar: tx_swr_data2_active_ar {
+ mux {
+ pins = "gpio2";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_clk_sleep_ar: rx_swr_clk_sleep_ar {
+ mux {
+ pins = "gpio3";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_clk_active_ar: rx_swr_clk_active_ar {
+ mux {
+ pins = "gpio3";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+ };
+
+ rx_swr_data_sleep_ar: rx_swr_data_sleep_ar {
+ mux {
+ pins = "gpio4";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_data_active_ar: rx_swr_data_active_ar {
+ mux {
+ pins = "gpio4";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_data1_sleep_ar: rx_swr_data1_sleep_ar {
+ mux {
+ pins = "gpio5";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_data1_active_ar: rx_swr_data1_active_ar {
+ mux {
+ pins = "gpio5";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ cdc_dmic01_clk_active_ar: dmic01_clk_active_ar {
+ mux {
+ pins = "gpio6";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic01_clk_sleep_ar: dmic01_clk_sleep_ar {
+ mux {
+ pins = "gpio6";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic01_data_active_ar: dmic01_data_active_ar {
+ mux {
+ pins = "gpio7";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic01_data_sleep_ar: dmic01_data_sleep_ar {
+ mux {
+ pins = "gpio7";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ cdc_dmic23_clk_active_ar: dmic23_clk_active_ar {
+ mux {
+ pins = "gpio8";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic23_clk_sleep_ar: dmic23_clk_sleep_ar {
+ mux {
+ pins = "gpio8";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic23_data_active_ar: dmic23_data_active_ar {
+ mux {
+ pins = "gpio9";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic23_data_sleep_ar: dmic23_data_sleep_ar {
+ mux {
+ pins = "gpio9";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ cdc_dmic45_clk_active_ar: dmic45_clk_active_ar {
+ mux {
+ pins = "gpio12";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic45_clk_sleep_ar: dmic45_clk_sleep_ar {
+ mux {
+ pins = "gpio12";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic45_data_active_ar: dmic45_data_active_ar {
+ mux {
+ pins = "gpio13";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic45_data_sleep_ar: dmic45_data_sleep_ar {
+ mux {
+ pins = "gpio13";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-lpi.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-lpi.dtsi
new file mode 100755
index 0000000..66c579d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-lpi.dtsi
@@ -0,0 +1,1679 @@
+&q6core {
+ lpi_tlmm: lpi_pinctrl@33c0000 {
+ compatible = "qcom,lpi-pinctrl";
+ reg = <0x33c0000 0x0>;
+ qcom,slew-reg = <0x355a000 0x0>;
+ qcom,num-gpios = <14>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
+ <0x00002000>, <0x00003000>,
+ <0x00004000>, <0x00005000>,
+ <0x00006000>, <0x00007000>,
+ <0x00008000>, <0x00009000>,
+ <0x0000A000>, <0x0000B000>,
+ <0x0000C000>, <0x0000D000>;
+ qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>,
+ <0x00000004>, <0x00000008>,
+ <0x0000000A>, <0x0000000C>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000010>, <0x00000012>,
+ <0x00000000>, <0x00000000>;
+
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+
+ quat_mi2s_sck {
+ quat_mi2s_sck_sleep: quat_mi2s_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sck_active: quat_mi2s_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_ws {
+ quat_mi2s_ws_sleep: quat_mi2s_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_ws_active: quat_mi2s_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd0 {
+ quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd0_active: quat_mi2s_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd1 {
+ quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd1_active: quat_mi2s_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd2 {
+ quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd2_active: quat_mi2s_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd3 {
+ quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func4";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd3_active: quat_mi2s_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func4";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sck {
+ lpi_i2s1_sck_sleep: lpi_i2s1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sck_active: lpi_i2s1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_ws {
+ lpi_i2s1_ws_sleep: lpi_i2s1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_ws_active: lpi_i2s1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sd0 {
+ lpi_i2s1_sd0_sleep: lpi_i2s1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sd0_active: lpi_i2s1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sd1 {
+ lpi_i2s1_sd1_sleep: lpi_i2s1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sd1_active: lpi_i2s1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sck {
+ lpi_i2s2_sck_sleep: lpi_i2s2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sck_active: lpi_i2s2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_ws {
+ lpi_i2s2_ws_sleep: lpi_i2s2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_ws_active: lpi_i2s2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sd0 {
+ lpi_i2s2_sd0_sleep: lpi_i2s2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sd0_active: lpi_i2s2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sd1 {
+ lpi_i2s2_sd1_sleep: lpi_i2s2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sd1_active: lpi_i2s2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sck {
+ quat_tdm_sck_sleep: quat_tdm_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sck_active: quat_tdm_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_ws {
+ quat_tdm_ws_sleep: quat_tdm_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_ws_active: quat_tdm_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd0 {
+ quat_tdm_sd0_sleep: quat_tdm_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd0_active: quat_tdm_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd1 {
+ quat_tdm_sd1_sleep: quat_tdm_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd1_active: quat_tdm_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd2 {
+ quat_tdm_sd2_sleep: quat_tdm_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd2_active: quat_tdm_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd3 {
+ quat_tdm_sd3_sleep: quat_tdm_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func4";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd3_active: quat_tdm_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func4";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sck {
+ lpi_tdm1_sck_sleep: lpi_tdm1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sck_active: lpi_tdm1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_ws {
+ lpi_tdm1_ws_sleep: lpi_tdm1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_ws_active: lpi_tdm1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sd0 {
+ lpi_tdm1_sd0_sleep: lpi_tdm1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sd0_active: lpi_tdm1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sd1 {
+ lpi_tdm1_sd1_sleep: lpi_tdm1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sd1_active: lpi_tdm1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sck {
+ lpi_tdm2_sck_sleep: lpi_tdm2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sck_active: lpi_tdm2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_ws {
+ lpi_tdm2_ws_sleep: lpi_tdm2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_ws_active: lpi_tdm2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sd0 {
+ lpi_tdm2_sd0_sleep: lpi_tdm2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sd0_active: lpi_tdm2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sd1 {
+ lpi_tdm2_sd1_sleep: lpi_tdm2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sd1_active: lpi_tdm2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sck {
+ quat_aux_sck_sleep: quat_aux_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sck_active: quat_aux_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_ws {
+ quat_aux_ws_sleep: quat_aux_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_ws_active: quat_aux_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd0 {
+ quat_aux_sd0_sleep: quat_aux_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd0_active: quat_aux_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd1 {
+ quat_aux_sd1_sleep: quat_aux_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd1_active: quat_aux_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd2 {
+ quat_aux_sd2_sleep: quat_aux_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd2_active: quat_aux_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd3 {
+ quat_aux_sd3_sleep: quat_aux_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func4";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd3_active: quat_aux_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func4";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sck {
+ lpi_aux1_sck_sleep: lpi_aux1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sck_active: lpi_aux1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_ws {
+ lpi_aux1_ws_sleep: lpi_aux1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_ws_active: lpi_aux1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sd0 {
+ lpi_aux1_sd0_sleep: lpi_aux1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sd0_active: lpi_aux1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sd1 {
+ lpi_aux1_sd1_sleep: lpi_aux1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sd1_active: lpi_aux1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sck {
+ lpi_aux2_sck_sleep: lpi_aux2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sck_active: lpi_aux2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_ws {
+ lpi_aux2_ws_sleep: lpi_aux2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_ws_active: lpi_aux2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sd0 {
+ lpi_aux2_sd0_sleep: lpi_aux2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sd0_active: lpi_aux2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sd1 {
+ lpi_aux2_sd1_sleep: lpi_aux2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sd1_active: lpi_aux2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ wsa_swr_clk_pin {
+ wsa_swr_clk_sleep: wsa_swr_clk_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ wsa_swr_clk_active: wsa_swr_clk_active {
+ mux {
+ pins = "gpio10";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+ };
+ };
+
+ wsa_swr_data_pin {
+ wsa_swr_data_sleep: wsa_swr_data_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ wsa_swr_data_active: wsa_swr_data_active {
+ mux {
+ pins = "gpio11";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+ };
+
+ tx_swr_clk_sleep: tx_swr_clk_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func1";
+ input-enable;
+ bias-pull-down;
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>;
+ };
+ };
+
+ tx_swr_clk_active: tx_swr_clk_active {
+ mux {
+ pins = "gpio0";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+ };
+
+ tx_swr_data1_sleep: tx_swr_data1_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>;
+ input-enable;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_data1_active: tx_swr_data1_active {
+ mux {
+ pins = "gpio1";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_data2_sleep: tx_swr_data2_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ tx_swr_data2_active: tx_swr_data2_active {
+ mux {
+ pins = "gpio2";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_clk_sleep: rx_swr_clk_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_clk_active: rx_swr_clk_active {
+ mux {
+ pins = "gpio3";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+ };
+
+ rx_swr_data_sleep: rx_swr_data_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_data_active: rx_swr_data_active {
+ mux {
+ pins = "gpio4";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_data1_sleep: rx_swr_data1_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_data1_active: rx_swr_data1_active {
+ mux {
+ pins = "gpio5";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ cdc_dmic01_clk_active: dmic01_clk_active {
+ mux {
+ pins = "gpio6";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic01_clk_sleep: dmic01_clk_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic01_data_active: dmic01_data_active {
+ mux {
+ pins = "gpio7";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic01_data_sleep: dmic01_data_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ cdc_dmic23_clk_active: dmic23_clk_active {
+ mux {
+ pins = "gpio8";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic23_clk_sleep: dmic23_clk_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic23_data_active: dmic23_data_active {
+ mux {
+ pins = "gpio9";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic23_data_sleep: dmic23_data_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ cdc_dmic45_clk_active: dmic45_clk_active {
+ mux {
+ pins = "gpio12";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic45_clk_sleep: dmic45_clk_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic45_data_active: dmic45_data_active {
+ mux {
+ pins = "gpio13";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic45_data_sleep: dmic45_data_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-mhi.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-mhi.dtsi
new file mode 100755
index 0000000..31fb61c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-mhi.dtsi
@@ -0,0 +1,774 @@
+&pcie2_rp {
+ #address-cells = <5>;
+ #size-cells = <0>;
+
+ mhi_0: qcom,mhi@0 {
+ reg = <0 0 0 0 0 >;
+
+ /* controller specific configuration */
+ qcom,iommu-group = <&mhi_0_iommu_group>;
+
+ /* controller ddr frequency scaling configuration */
+ qcom,msm-bus,name = "mhi0";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_PCIE_2 MSM_BUS_SLAVE_EBI_CH0
+ 0 0>,
+ <MSM_BUS_MASTER_PCIE_2 MSM_BUS_SLAVE_EBI_CH0
+ 0 0>,
+ <MSM_BUS_MASTER_PCIE_2 MSM_BUS_SLAVE_EBI_CH0
+ 500000 0>, /* 4 Gbps */
+ <MSM_BUS_MASTER_PCIE_2 MSM_BUS_SLAVE_EBI_CH0
+ 1000000 0>; /* 8 Gbps */
+
+ esoc-names = "mdm";
+ esoc-0 = <&mdm0>;
+
+ /* mhi bus specific settings */
+ mhi,max-channels = <111>;
+ mhi,timeout = <2000>;
+ mhi,buffer-len = <0x8000>;
+ mhi,sfr-support;
+ mhi,name = "esoc0";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mhi_0_iommu_group: mhi_0_iommu_group {
+ qcom,iommu-dma-addr-pool = <0x20000000 0x1fffffff>;
+ qcom,iommu-dma = "fastmap";
+ qcom,iommu-pagetable = "coherent";
+ };
+
+ mhi_channels: mhi_channels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mhi_chan@0 {
+ reg = <0>;
+ label = "LOOPBACK";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <2>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@1 {
+ reg = <1>;
+ label = "LOOPBACK";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <2>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@2 {
+ reg = <2>;
+ label = "SAHARA";
+ mhi,num-elements = <128>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x2>;
+ };
+
+ mhi_chan@3 {
+ reg = <3>;
+ label = "SAHARA";
+ mhi,num-elements = <128>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x2>;
+ };
+
+ mhi_chan@4 {
+ reg = <4>;
+ label = "DIAG";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@5 {
+ reg = <5>;
+ label = "DIAG";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <3>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@8 {
+ reg = <8>;
+ label = "QDSS";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@9 {
+ reg = <9>;
+ label = "QDSS";
+ mhi,num-elements = <128>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@10 {
+ reg = <10>;
+ label = "EFS";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@11 {
+ reg = <11>;
+ label = "EFS";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ mhi,wake-capable;
+ };
+
+ mhi_chan@14 {
+ reg = <14>;
+ label = "QMI0";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@15 {
+ reg = <15>;
+ label = "QMI0";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <2>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@16 {
+ reg = <16>;
+ label = "QMI1";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <3>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@17 {
+ reg = <17>;
+ label = "QMI1";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <3>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@18 {
+ reg = <18>;
+ label = "IP_CTRL";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@19 {
+ reg = <19>;
+ label = "IP_CTRL";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ mhi,auto-queue;
+ };
+
+ mhi_chan@20 {
+ reg = <20>;
+ label = "IPCR";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <2>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <1>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ mhi,auto-start;
+ };
+
+ mhi_chan@21 {
+ reg = <21>;
+ label = "IPCR";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <2>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ mhi,auto-queue;
+ mhi,auto-start;
+ };
+
+ mhi_chan@22 {
+ reg = <22>;
+ label = "TF";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <2>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@23 {
+ reg = <23>;
+ label = "TF";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <2>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@25 {
+ reg = <25>;
+ label = "BL";
+ mhi,num-elements = <32>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x2>;
+ mhi,auto-queue;
+ mhi,auto-start;
+ };
+
+ mhi_chan@26 {
+ reg = <26>;
+ label = "DCI";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <3>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@27 {
+ reg = <27>;
+ label = "DCI";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <3>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@32 {
+ reg = <32>;
+ label = "DUN";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <3>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@33 {
+ reg = <33>;
+ label = "DUN";
+ mhi,num-elements = <64>;
+ mhi,event-ring = <3>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@50 {
+ reg = <50>;
+ label = "ADSP_0";
+ mhi,event-ring = <4>;
+ mhi,chan-dir = <0>;
+ mhi,data-type = <3>;
+ mhi,ee = <0x4>;
+ mhi,offload-chan;
+ };
+
+ mhi_chan@51 {
+ reg = <51>;
+ label = "ADSP_1";
+ mhi,event-ring = <4>;
+ mhi,chan-dir = <0>;
+ mhi,data-type = <3>;
+ mhi,ee = <0x4>;
+ mhi,offload-chan;
+ };
+
+ mhi_chan@52 {
+ reg = <52>;
+ label = "SLPI_0";
+ mhi,event-ring = <5>;
+ mhi,chan-dir = <0>;
+ mhi,data-type = <3>;
+ mhi,ee = <0x4>;
+ mhi,offload-chan;
+ };
+
+ mhi_chan@53 {
+ reg = <53>;
+ label = "SLPI_1";
+ mhi,event-ring = <5>;
+ mhi,chan-dir = <0>;
+ mhi,data-type = <3>;
+ mhi,ee = <0x4>;
+ mhi,offload-chan;
+ };
+
+ mhi_chan@70 {
+ reg = <70>;
+ label = "ADSP_2";
+ mhi,event-ring = <4>;
+ mhi,chan-dir = <0>;
+ mhi,data-type = <3>;
+ mhi,ee = <0x4>;
+ mhi,offload-chan;
+ };
+
+ mhi_chan@71 {
+ reg = <71>;
+ label = "ADSP_3";
+ mhi,event-ring = <4>;
+ mhi,chan-dir = <0>;
+ mhi,data-type = <3>;
+ mhi,ee = <0x4>;
+ mhi,offload-chan;
+ };
+
+ mhi_chan@72 {
+ reg = <72>;
+ label = "SLPI_2";
+ mhi,event-ring = <5>;
+ mhi,chan-dir = <0>;
+ mhi,data-type = <3>;
+ mhi,ee = <0x4>;
+ mhi,offload-chan;
+ };
+
+ mhi_chan@73 {
+ reg = <73>;
+ label = "SLPI_3";
+ mhi,event-ring = <5>;
+ mhi,chan-dir = <0>;
+ mhi,data-type = <3>;
+ mhi,ee = <0x4>;
+ mhi,offload-chan;
+ };
+
+ mhi_chan@80 {
+ reg = <80>;
+ label = "AUDIO_VOICE_0";
+ mhi,event-ring = <0>;
+ mhi,chan-dir = <0>;
+ mhi,ee = <0x4>;
+ mhi,data-type = <3>;
+ mhi,offload-chan;
+ status = "ok";
+ };
+
+ mhi_chan@100 {
+ reg = <100>;
+ label = "IP_HW0";
+ mhi,num-elements = <512>;
+ mhi,event-ring = <7>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <1>;
+ mhi,doorbell-mode = <3>;
+ mhi,ee = <0x4>;
+ mhi,db-mode-switch;
+ };
+
+ mhi_chan@101 {
+ reg = <101>;
+ label = "IP_HW0";
+ mhi,num-elements = <512>;
+ mhi,event-ring = <8>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <4>;
+ mhi,doorbell-mode = <3>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@102 {
+ reg = <102>;
+ label = "IP_HW_ADPL";
+ mhi,event-ring = <9>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <3>;
+ mhi,ee = <0x4>;
+ mhi,offload-chan;
+ mhi,lpm-notify;
+ };
+
+ mhi_chan@103 {
+ reg = <103>;
+ label = "IP_HW_QDSS";
+ mhi,num-elements = <128>;
+ mhi,event-ring = <10>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@104 {
+ reg = <104>;
+ label = "IP_HW0_RSC";
+ mhi,num-elements = <512>;
+ mhi,local-elements = <3078>;
+ mhi,event-ring = <8>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <5>;
+ mhi,doorbell-mode = <3>;
+ mhi,ee = <0x4>;
+ mhi,chan-type = <3>;
+ };
+
+ mhi_chan@105 {
+ reg = <105>;
+ label = "IP_HW_MHIP_0";
+ mhi,event-ring = <11>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <3>;
+ mhi,ee = <0x4>;
+ mhi,offload-chan;
+ };
+
+ mhi_chan@106 {
+ reg = <106>;
+ label = "IP_HW_MHIP_0";
+ mhi,event-ring = <12>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <3>;
+ mhi,ee = <0x4>;
+ mhi,offload-chan;
+ mhi,lpm-notify;
+ };
+
+ mhi_chan@107 {
+ reg = <107>;
+ label = "IP_HW_MHIP_1";
+ mhi,event-ring = <13>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <3>;
+ mhi,ee = <0x4>;
+ mhi,offload-chan;
+ };
+
+ mhi_chan@108 {
+ reg = <108>;
+ label = "IP_HW_MHIP_1";
+ mhi,event-ring = <14>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <3>;
+ mhi,ee = <0x4>;
+ mhi,offload-chan;
+ mhi,lpm-notify;
+ };
+
+ mhi_chan@109 {
+ reg = <109>;
+ label = "RMNET_CTL";
+ mhi,num-elements = <128>;
+ mhi,event-ring = <15>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <1>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+
+ mhi_chan@110 {
+ reg = <110>;
+ label = "RMNET_CTL";
+ mhi,num-elements = <128>;
+ mhi,event-ring = <16>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x4>;
+ };
+ };
+
+ mhi_events: mhi_events {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mhi_event@0 {
+ reg = <0>;
+ mhi,num-elements = <32>;
+ mhi,intmod = <0>;
+ mhi,msi = <1>;
+ mhi,priority = <0>;
+ mhi,brstmode = <2>;
+ mhi,data-type = <1>;
+ };
+
+ mhi_event@1 {
+ mhi,num-elements = <256>;
+ mhi,intmod = <0>;
+ mhi,msi = <2>;
+ mhi,priority = <1>;
+ mhi,brstmode = <2>;
+ };
+
+ mhi_event@2 {
+ mhi,num-elements = <256>;
+ mhi,intmod = <0>;
+ mhi,msi = <3>;
+ mhi,priority = <1>;
+ mhi,brstmode = <2>;
+ };
+
+ mhi_event@3 {
+ mhi,num-elements = <256>;
+ mhi,intmod = <0>;
+ mhi,msi = <4>;
+ mhi,priority = <1>;
+ mhi,brstmode = <2>;
+ };
+
+ mhi_event@4 {
+ mhi,num-elements = <512>;
+ mhi,intmod = <5>;
+ mhi,msi = <0>;
+ mhi,priority = <1>;
+ mhi,brstmode = <3>;
+ mhi,client-manage;
+ mhi,offload;
+ };
+
+ mhi_event@5 {
+ mhi,num-elements = <512>;
+ mhi,intmod = <5>;
+ mhi,msi = <0>;
+ mhi,priority = <1>;
+ mhi,brstmode = <3>;
+ mhi,client-manage;
+ mhi,offload;
+ };
+
+ mhi_event@6 {
+ mhi,num-elements = <64>;
+ mhi,intmod = <0>;
+ mhi,msi = <0>;
+ mhi,priority = <2>;
+ mhi,brstmode = <2>;
+ mhi,data-type = <3>;
+ };
+
+ mhi_event@7 {
+ mhi,num-elements = <1024>;
+ mhi,intmod = <5>;
+ mhi,msi = <5>;
+ mhi,chan = <100>;
+ mhi,priority = <1>;
+ mhi,brstmode = <3>;
+ mhi,hw-ev;
+ };
+
+ mhi_event@8 {
+ mhi,num-elements = <2048>;
+ mhi,intmod = <5>;
+ mhi,msi = <6>;
+ mhi,chan = <101>;
+ mhi,priority = <1>;
+ mhi,brstmode = <3>;
+ mhi,hw-ev;
+ mhi,client-manage;
+ mhi,force-uncached;
+ };
+
+ mhi_event@9 {
+ mhi,num-elements = <0>;
+ mhi,intmod = <0>;
+ mhi,msi = <0>;
+ mhi,chan = <102>;
+ mhi,priority = <1>;
+ mhi,brstmode = <3>;
+ mhi,hw-ev;
+ mhi,client-manage;
+ mhi,offload;
+ };
+
+ mhi_event@10 {
+ mhi,num-elements = <1024>;
+ mhi,intmod = <5>;
+ mhi,msi = <7>;
+ mhi,chan = <103>;
+ mhi,priority = <1>;
+ mhi,brstmode = <2>;
+ mhi,hw-ev;
+ };
+
+ mhi_event@11 {
+ mhi,num-elements = <0>;
+ mhi,intmod = <0>;
+ mhi,msi = <0>;
+ mhi,chan = <105>;
+ mhi,priority = <1>;
+ mhi,brstmode = <3>;
+ mhi,hw-ev;
+ mhi,client-manage;
+ mhi,offload;
+ };
+
+ mhi_event@12 {
+ mhi,num-elements = <0>;
+ mhi,intmod = <0>;
+ mhi,msi = <0>;
+ mhi,chan = <106>;
+ mhi,priority = <1>;
+ mhi,brstmode = <3>;
+ mhi,hw-ev;
+ mhi,client-manage;
+ mhi,offload;
+ };
+
+ mhi_event@13 {
+ mhi,num-elements = <0>;
+ mhi,intmod = <0>;
+ mhi,msi = <0>;
+ mhi,chan = <107>;
+ mhi,priority = <1>;
+ mhi,brstmode = <3>;
+ mhi,hw-ev;
+ mhi,client-manage;
+ mhi,offload;
+ };
+
+ mhi_event@14 {
+ mhi,num-elements = <0>;
+ mhi,intmod = <0>;
+ mhi,msi = <0>;
+ mhi,chan = <108>;
+ mhi,priority = <1>;
+ mhi,brstmode = <3>;
+ mhi,hw-ev;
+ mhi,client-manage;
+ mhi,offload;
+ };
+
+ mhi_event@15 {
+ mhi,num-elements = <1024>;
+ mhi,intmod = <1>;
+ mhi,msi = <8>;
+ mhi,chan = <109>;
+ mhi,priority = <0>;
+ mhi,brstmode = <2>;
+ mhi,hw-ev;
+ };
+
+ mhi_event@16 {
+ mhi,num-elements = <1024>;
+ mhi,intmod = <0>;
+ mhi,msi = <9>;
+ mhi,chan = <110>;
+ mhi,priority = <0>;
+ mhi,brstmode = <2>;
+ mhi,hw-ev;
+ };
+ };
+
+ mhi_devices: mhi_devices {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mhi_netdev_0: mhi_rmnet@0 {
+ reg = <0x0>;
+ mhi,chan = "IP_HW0";
+ mhi,interface-name = "rmnet_mhi";
+ mhi,mru = <0x8000>;
+ mhi,chain-skb;
+ mhi,rsc-child = <&mhi_netdev_0_rsc>;
+ };
+
+ mhi_netdev_0_rsc: mhi_rmnet@1 {
+ reg = <0x1>;
+ mhi,chan = "IP_HW0_RSC";
+ mhi,mru = <0x8000>;
+ mhi,rsc-parent = <&mhi_netdev_0>;
+ };
+
+ mhi_qdss_dev_0 {
+ mhi,chan = "QDSS";
+ mhi,default-channel;
+ };
+
+ mhi_qdss_dev_1 {
+ mhi,chan = "IP_HW_QDSS";
+ };
+
+ mhi_qrtr {
+ mhi,chan = "IPCR";
+ qcom,net-id = <3>;
+ mhi,early-notify;
+ };
+
+ mhi_subsys_adsp_0: mhi_dev@2 {
+ reg = <0x2>;
+ mhi,chan = "ADSP_0";
+ mhi,max-devices = <4>;
+ mhi,early-notify;
+ };
+
+ mhi_subsys_slpi_0: mhi_dev@3 {
+ reg = <0x3>;
+ mhi,chan = "SLPI_0";
+ mhi,max-devices = <4>;
+ mhi,early-notify;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-mtp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/kona-mtp-overlay.dts
new file mode 100755
index 0000000..1928b89
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-mtp-overlay.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-kona.h>
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "kona-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona MTP";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x10008 0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-mtp-sa.dts b/arch/arm64/boot/dts/vendor/qcom/kona-mtp-sa.dts
new file mode 100755
index 0000000..8eb1117
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-mtp-sa.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+#include "kona.dtsi"
+#include "kona-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona standalone MTP";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x02010008 0>;
+};
+
+&mdm0 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-mtp-ws-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/kona-mtp-ws-overlay.dts
new file mode 100755
index 0000000..778ed9b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-mtp-ws-overlay.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "kona-mtp-ws.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona MTP (WS)";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x03010008 0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-mtp-ws.dts b/arch/arm64/boot/dts/vendor/qcom/kona-mtp-ws.dts
new file mode 100755
index 0000000..bffdb81
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-mtp-ws.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona.dtsi"
+#include "kona-mtp-ws.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona MTP (WS)";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x03010008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-mtp-ws.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-mtp-ws.dtsi
new file mode 100755
index 0000000..362c9fd
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-mtp-ws.dtsi
@@ -0,0 +1,28 @@
+#include "kona-mtp.dtsi"
+
+&wlan {
+ vdd-wlan-dig-supply = <&pm8150_s6>;
+ qcom,vdd-wlan-dig-config = <950000 950000 0 0 1>;
+ qcom,cmd_db_name = "smpa6";
+};
+
+&bluetooth {
+ compatible = "qca,qca6390";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en_sleep>;
+ qca,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */
+ qca,bt-sw-ctrl-gpio = <&tlmm 124 0>; /* SW_CTRL */
+ qca,bt-vdd-aon-supply = <&pm8150_s6>;
+ qca,bt-vdd-dig-supply = <&pm8150_s6>;
+ qca,bt-vdd-rfa1-supply = <&pm8150_s5>;
+ qca,bt-vdd-rfa2-supply = <&pm8150a_s8>;
+ qca,bt-vdd-asd-supply = <&pm8150_l16>;
+
+ qca,bt-vdd-aon-voltage-level = <950000 950000>;
+ qca,bt-vdd-dig-voltage-level = <950000 950000>;
+ qca,bt-vdd-rfa1-voltage-level = <1900000 1900000>;
+ qca,bt-vdd-rfa2-voltage-level = <1350000 1350000>;
+ qca,bt-vdd-asd-voltage-level = <3024000 3304000>;
+
+ qca,bt-vdd-asd-current-level = <10000>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/kona-mtp.dts
new file mode 100755
index 0000000..2b12870
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-mtp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona.dtsi"
+#include "kona-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona MTP";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x10008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-mtp.dtsi
new file mode 100755
index 0000000..476ccf0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-mtp.dtsi
@@ -0,0 +1,654 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#include "kona-pmic-overlay.dtsi"
+#include "kona-sde-display.dtsi"
+#include "camera/kona-camera-sensor-mtp.dtsi"
+#include "kona-audio-overlay.dtsi"
+#include "kona-audio-overlay-ar.dtsi"
+#include "kona-thermal-overlay.dtsi"
+
+&qupv3_se12_2uart {
+ status = "ok";
+};
+
+&pm8150a_amoled {
+ status = "ok";
+};
+
+&qupv3_se6_4uart {
+ status = "ok";
+};
+
+&dai_mi2s2 {
+ qcom,msm-mi2s-tx-lines = <1>;
+};
+
+&q6core {
+ cdc_tert_mi2s_gpios: msm_cdc_pinctrl_tert {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
+ &tert_mi2s_sd0_active>;
+ pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
+ &tert_mi2s_sd0_sleep>;
+ };
+};
+
+&kona_snd {
+ qcom,tert-mi2s-gpios = <&cdc_tert_mi2s_gpios>;
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ qcom,clk-freq-out = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 111 0x00>;
+ qcom,nq-ven = <&tlmm 6 0x00>;
+ qcom,nq-firm = <&tlmm 110 0x00>;
+ qcom,nq-clkreq = <&tlmm 7 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <111 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v4";
+
+ vdda-phy-supply = <&pm8150_l5>;
+ vdda-phy-always-on;
+ vdda-pll-supply = <&pm8150_l9>;
+ vdda-phy-max-microamp = <89900>;
+ vdda-pll-max-microamp = <18800>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm8150_l17>;
+ vcc-voltage-level = <2504000 2950000>;
+ vcc-low-voltage-sup;
+ vccq-supply = <&pm8150_l6>;
+ vccq2-supply = <&pm8150_s4>;
+ vcc-max-microamp = <800000>;
+ vccq-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+
+ qcom,vddp-ref-clk-supply = <&pm8150_l6>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vccq-parent-supply = <&pm8150a_s8>;
+ qcom,vccq-parent-max-microamp = <210000>;
+
+ status = "ok";
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+
+ qcom,qbt_handler {
+ compatible = "qcom,qbt-handler";
+ qcom,ipc-gpio = <&tlmm 23 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_home_default>;
+ qcom,finger-detect-gpio = <&pm8150_gpios 1 0>;
+ };
+};
+
+&qupv3_se13_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "ok";
+ qcom,i2c-touch-active = "st,fts";
+
+ st_fts@49 {
+ compatible = "st,fts";
+ reg = <0x49>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <39 0x2008>;
+ vdd-supply = <&pm8150a_l1>;
+ avdd-supply = <&pm8150_l13>;
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ st,irq-gpio = <&tlmm 39 0x2008>;
+ st,reset-gpio = <&tlmm 38 0x00>;
+ st,regulator_dvdd = "vdd";
+ st,regulator_avdd = "avdd";
+ st,x-flip = <1>;
+ st,y-flip = <1>;
+ panel = <&dsi_sw43404_amoled_cmd &dsi_sw43404_amoled_video
+ &dsi_sw43404_amoled_fhd_plus_cmd>;
+ };
+};
+
+&vendor {
+ bluetooth: bt_qca6390 {
+ compatible = "qca,qca6390";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en_sleep>;
+ qca,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */
+ qca,wl-reset-gpio = <&tlmm 20 0>; /* WL_EN */
+ qca,bt-sw-ctrl-gpio = <&tlmm 124 0>; /* SW_CTRL */
+ qca,bt-vdd-aon-supply = <&pm8150_s6>;
+ qca,bt-vdd-dig-supply = <&pm8009_s2>;
+ qca,bt-vdd-rfa1-supply = <&pm8150_s5>;
+ qca,bt-vdd-rfa2-supply = <&pm8150a_s8>;
+ qca,bt-vdd-asd-supply = <&pm8150_l16>;
+
+ qca,bt-vdd-aon-voltage-level = <950000 950000>;
+ qca,bt-vdd-dig-voltage-level = <950000 952000>;
+ qca,bt-vdd-rfa1-voltage-level = <1900000 1900000>;
+ qca,bt-vdd-rfa2-voltage-level = <1350000 1350000>;
+ qca,bt-vdd-asd-voltage-level = <3024000 3304000>;
+
+ qca,bt-vdd-asd-current-level = <10000>;
+ };
+
+ kona_mtp_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "fg-gen4-batterydata-alium-3600mah.dtsi"
+ #include "fg-gen4-batterydata-ascent-3450mah.dtsi"
+ };
+
+ extcon_usb1: extcon_usb1 {
+ compatible = "linux,extcon-usb-gpio";
+ vbus-gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>;
+ id-gpio = <&tlmm 91 GPIO_ACTIVE_HIGH>;
+ vbus-out-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_vbus_det_default
+ &usb2_id_det_default
+ &usb2_vbus_boost_default>;
+ };
+};
+
+&vreg_hap_boost {
+ status = "ok";
+};
+
+&pm8150b_haptics {
+ vdd-supply = <&vreg_hap_boost>;
+};
+
+&pm8150b_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "conn_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ chg_sbux@99 {
+ reg = <ADC_SBUx>;
+ label = "chg_sbux";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ mid_chg_div6@1e {
+ reg = <ADC_MID_CHG_DIV6>;
+ label = "chg_mid";
+ qcom,pre-scaling = <1 6>;
+ };
+
+ usb_in_i_uv@7 {
+ reg = <ADC_USB_IN_I>;
+ label = "usb_in_i_uv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ usb_in_v_div_16@8 {
+ reg = <ADC_USB_IN_V_16>;
+ label = "usb_in_v_div_16";
+ qcom,pre-scaling = <1 16>;
+ };
+};
+
+&pm8150b_charger {
+ status = "ok";
+ qcom,sec-charger-config = <1>;
+ qcom,auto-recharge-soc = <98>;
+ io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>,
+ <&pm8150b_vadc ADC_USB_IN_I>,
+ <&pm8150b_vadc ADC_SBUx>,
+ <&pm8150b_vadc ADC_VPH_PWR>,
+ <&pm8150b_vadc ADC_CHG_TEMP>;
+ io-channel-names = "mid_voltage",
+ "usb_in_current",
+ "sbux_res",
+ "vph_voltage",
+ "chg_temp";
+ qcom,battery-data = <&kona_mtp_batterydata>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,wd-bark-time-secs = <16>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,fcc-stepping-enable;
+ qcom,smb-internal-pull-kohm = <0>;
+};
+
+&pm8150b_fg {
+ status = "ok";
+ qcom,battery-data = <&kona_mtp_batterydata>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,five-pin-battery;
+ qcom,cl-wt-enable;
+ qcom,soc-scale-mode-en;
+ qcom,force-calib-level = <130>;
+ /* ESR fast calibration */
+ qcom,fg-esr-timer-chg-fast = <0 7>;
+ qcom,fg-esr-timer-dischg-fast = <0 7>;
+ qcom,fg-esr-timer-chg-slow = <0 96>;
+ qcom,fg-esr-timer-dischg-slow = <0 96>;
+ qcom,fg-esr-cal-soc-thresh = <26 230>;
+ qcom,fg-esr-cal-temp-thresh = <10 40>;
+};
+
+&qupv3_se15_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+#include "smb1390.dtsi"
+
+ halo,hl6111r@25 {
+ compatible = "halo,hl6111r";
+ reg = <0x25>;
+ status = "ok";
+ };
+};
+
+&smb1390 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_stat_default>;
+ status = "ok";
+};
+
+&smb1390_charger {
+ io-channels = <&pm8150b_vadc ADC_AMUX_THM2>;
+ io-channel-names = "cp_die_temp";
+ qcom,parallel-output-mode = <2>;
+ qcom,min-ilim-ua = <750000>;
+ status = "ok";
+};
+
+&smb1390_slave {
+ status = "ok";
+};
+
+&smb1390_slave_charger {
+ status = "ok";
+};
+
+&pm8150_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vcoin@85 {
+ reg = <ADC_VCOIN>;
+ label = "vcoin";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "pa_therm1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150l_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ camera_flash_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "camera_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_msm_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "skin_msm_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm2@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "pa_therm2";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150b_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ io-channels = <&pm8150b_vadc ADC_AMUX_THM3_PU2>;
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ io-channels = <&pm8150_vadc ADC_AMUX_THM1_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM2_PU2>;
+
+ skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150l_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera_flash_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ skin_msm_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm2@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&spmi_debug_bus {
+ status = "ok";
+};
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_sec_hd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-sec-reset-gpio = <&tlmm 128 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
+};
+
+&thermal_zones {
+ conn-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-msm-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&sdhc_2 {
+ vdd-supply = <&pm8150a_l9>;
+ qcom,vdd-voltage-level = <2950000 2960000>;
+ qcom,vdd-current-level = <200 800000>;
+
+ vdd-io-supply = <&pm8150a_l6>;
+ qcom,vdd-io-voltage-level = <1808000 2960000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>;
+
+ cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&usb1 {
+ extcon = <&extcon_usb1>;
+};
+
+&wil6210 {
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-npu.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-npu.dtsi
new file mode 100755
index 0000000..17d6e02
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-npu.dtsi
@@ -0,0 +1,272 @@
+&soc {
+ msm_npu: qcom,msm_npu@9800000 {
+ compatible = "qcom,msm-npu";
+ status = "ok";
+ reg = <0x9900000 0x20000>,
+ <0x99F0000 0x10000>,
+ <0x9980000 0x10000>,
+ <0x17c00000 0x10000>,
+ <0x01F40000 0x40000>;
+ reg-names = "tcm", "core", "cc", "apss_shared", "tcsr";
+ interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq",
+ "general_irq";
+ iommus = <&apps_smmu 0x1081 0x400>, <&apps_smmu 0x1082 0x400>,
+ <&apps_smmu 0x10A1 0x400>, <&apps_smmu 0x10A2 0x400>,
+ <&apps_smmu 0x10C1 0x400>, <&apps_smmu 0x10C2 0x400>;
+ qcom,npu-dsp-sid-mapped;
+
+ clocks = <&clock_npucc NPU_CC_XO_CLK>,
+ <&clock_npucc NPU_CC_CORE_CLK>,
+ <&clock_npucc NPU_CC_CAL_HM0_CLK>,
+ <&clock_npucc NPU_CC_CAL_HM1_CLK>,
+ <&clock_npucc NPU_CC_CAL_HM0_CDC_CLK>,
+ <&clock_npucc NPU_CC_CAL_HM1_CDC_CLK>,
+ <&clock_npucc NPU_CC_NOC_AXI_CLK>,
+ <&clock_npucc NPU_CC_NOC_AHB_CLK>,
+ <&clock_npucc NPU_CC_NOC_DMA_CLK>,
+ <&clock_npucc NPU_CC_LLM_CLK>,
+ <&clock_npucc NPU_CC_LLM_XO_CLK>,
+ <&clock_npucc NPU_CC_LLM_TEMP_CLK>,
+ <&clock_npucc NPU_CC_LLM_CURR_CLK>,
+ <&clock_npucc NPU_CC_DL_LLM_CLK>,
+ <&clock_npucc NPU_CC_ISENSE_CLK>,
+ <&clock_npucc NPU_CC_DPM_CLK>,
+ <&clock_npucc NPU_CC_DPM_XO_CLK>,
+ <&clock_npucc NPU_CC_DL_DPM_CLK>,
+ <&clock_npucc NPU_CC_RSC_XO_CLK>,
+ <&clock_npucc NPU_CC_DPM_TEMP_CLK>,
+ <&clock_npucc NPU_CC_CAL_HM0_DPM_IP_CLK>,
+ <&clock_npucc NPU_CC_CAL_HM1_DPM_IP_CLK>,
+ <&clock_npucc NPU_CC_S2P_CLK>,
+ <&clock_npucc NPU_CC_BWMON_CLK>,
+ <&clock_npucc NPU_CC_CAL_HM0_PERF_CNT_CLK>,
+ <&clock_npucc NPU_CC_CAL_HM1_PERF_CNT_CLK>,
+ <&clock_npucc NPU_CC_BTO_CORE_CLK>,
+ <&clock_npucc NPU_DSP_CORE_CLK_SRC>;
+ clock-names = "xo_clk",
+ "npu_core_clk",
+ "cal_hm0_clk",
+ "cal_hm1_clk",
+ "cal_hm0_cdc_clk",
+ "cal_hm1_cdc_clk",
+ "axi_clk",
+ "ahb_clk",
+ "dma_clk",
+ "llm_clk",
+ "llm_xo_clk",
+ "llm_temp_clk",
+ "llm_curr_clk",
+ "dl_llm_clk",
+ "isense_clk",
+ "dpm_clk",
+ "dpm_xo_clk",
+ "dl_dpm_clk",
+ "rsc_xo_clk",
+ "dpm_temp_clk",
+ "cal_hm0_dpm_ip_clk",
+ "cal_hm1_dpm_ip_clk",
+ "s2p_clk",
+ "bwmon_clk",
+ "cal_hm0_perf_cnt_clk",
+ "cal_hm1_perf_cnt_clk",
+ "bto_core_clk",
+ "dsp_core_clk_src";
+
+ vdd-supply = <&npu_core_gdsc>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,proxy-reg-names ="vdd", "vdd_cx";
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+ resets = <&clock_npucc NPU_CC_DPM_TEMP_CLK_ARES>,
+ <&clock_npucc NPU_CC_LLM_CURR_CLK_ARES>,
+ <&clock_npucc NPU_CC_LLM_TEMP_CLK_ARES>;
+ reset-names = "dpm_temp_clk", "llm_curr_clk", "llm_temp_clk";
+ #cooling-cells = <2>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_GLINK_QMP>,
+ <&ipcc_mproc IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_SMP2P>,
+ <&ipcc_mproc IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_PING>;
+ mbox-names = "ipcc-glink", "ipcc-smp2p", "ipcc-ping";
+ #mbox-cells = <2>;
+ qcom,npubw-devs = <&npu_npu_llcc_bw>, <&npu_llcc_ddr_bw>,
+ <&npudsp_npu_ddr_bw>;
+ qcom,npubw-dev-names = "llcc_bw", "llcc_ddr_bw", "dsp_ddr_bw";
+ qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>,
+ <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_CLK_CTL>;
+ qcom,npu-pwrlevels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,npu-pwrlevels";
+ initial-pwrlevel = <4>;
+ qcom,npu-pwrlevel@0 {
+ reg = <0>;
+ vreg = <1>;
+ clk-freq = <19200000
+ 100000000
+ 300000000
+ 300000000
+ 300000000
+ 300000000
+ 200000000
+ 40000000
+ 300000000
+ 100000000
+ 19200000
+ 50000000
+ 50000000
+ 100000000
+ 100000000
+ 100000000
+ 19200000
+ 100000000
+ 19200000
+ 50000000
+ 200000000
+ 200000000
+ 50000000
+ 19200000
+ 300000000
+ 300000000
+ 19200000
+ 300000000>;
+ };
+
+ qcom,npu-pwrlevel@1 {
+ reg = <1>;
+ vreg = <2>;
+ clk-freq = <19200000
+ 200000000
+ 466000000
+ 466000000
+ 466000000
+ 466000000
+ 267000000
+ 40000000
+ 403000000
+ 200000000
+ 19200000
+ 50000000
+ 50000000
+ 200000000
+ 200000000
+ 200000000
+ 19200000
+ 200000000
+ 19200000
+ 50000000
+ 466000000
+ 466000000
+ 50000000
+ 19200000
+ 466000000
+ 466000000
+ 19200000
+ 400000000>;
+ };
+
+ qcom,npu-pwrlevel@2 {
+ reg = <2>;
+ vreg = <3>;
+ clk-freq = <19200000
+ 333000000
+ 533000000
+ 533000000
+ 533000000
+ 533000000
+ 403000000
+ 75000000
+ 533000000
+ 214000000
+ 19200000
+ 50000000
+ 100000000
+ 214000000
+ 214000000
+ 214000000
+ 19200000
+ 214000000
+ 19200000
+ 50000000
+ 533000000
+ 533000000
+ 50000000
+ 19200000
+ 533000000
+ 533000000
+ 19200000
+ 500000000>;
+ };
+
+ qcom,npu-pwrlevel@3 {
+ reg = <3>;
+ vreg = <4>;
+ clk-freq = <19200000
+ 428000000
+ 850000000
+ 850000000
+ 850000000
+ 850000000
+ 533000000
+ 75000000
+ 700000000
+ 300000000
+ 19200000
+ 100000000
+ 200000000
+ 300000000
+ 300000000
+ 300000000
+ 19200000
+ 300000000
+ 19200000
+ 100000000
+ 850000000
+ 850000000
+ 100000000
+ 19200000
+ 850000000
+ 850000000
+ 19200000
+ 660000000>;
+ };
+
+ qcom,npu-pwrlevel@4 {
+ reg = <4>;
+ vreg = <6>;
+ clk-freq = <19200000
+ 500000000
+ 1000000000
+ 1000000000
+ 1000000000
+ 1000000000
+ 700000000
+ 75000000
+ 806000000
+ 300000000
+ 19200000
+ 100000000
+ 200000000
+ 300000000
+ 300000000
+ 300000000
+ 19200000
+ 300000000
+ 19200000
+ 100000000
+ 1000000000
+ 1000000000
+ 100000000
+ 19200000
+ 1000000000
+ 1000000000
+ 19200000
+ 800000000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-pcie.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-pcie.dtsi
new file mode 100755
index 0000000..230f2b5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-pcie.dtsi
@@ -0,0 +1,814 @@
+#include <dt-bindings/clock/qcom,gcc-kona.h>
+
+&soc {
+ pcie0: qcom,pcie@1c00000 {
+ compatible = "qcom,pci-msm";
+
+ reg = <0x01c00000 0x3000>,
+ <0x01c06000 0x1000>,
+ <0x60000000 0xf1d>,
+ <0x60000f20 0xa8>,
+ <0x60001000 0x1000>,
+ <0x60100000 0x100000>;
+ reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
+
+ cell-index = <0>;
+ linux,pci-domain = <0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
+ <0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;
+
+ interrupt-parent = <&pcie0>;
+ interrupts = <0 1 2 3 4>;
+ interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+ "int_d";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0xffffffff>;
+ interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ msi-parent = <&pcie0_msi>;
+
+ perst-gpio = <&tlmm 79 0>;
+ wake-gpio = <&tlmm 81 0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pcie0_clkreq_default
+ &pcie0_perst_default
+ &pcie0_wake_default>;
+ pinctrl-1 = <&pcie0_clkreq_sleep
+ &pcie0_perst_default
+ &pcie0_wake_default>;
+
+ gdsc-vdd-supply = <&pcie_0_gdsc>;
+ vreg-1p8-supply = <&pm8150_l9>;
+ vreg-0p9-supply = <&pm8150_l5>;
+ vreg-cx-supply = <&VDD_CX_LEVEL>;
+ qcom,vreg-1p8-voltage-level = <1200000 1200000 16000>;
+ qcom,vreg-0p9-voltage-level = <880000 880000 73500>;
+ qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+ RPMH_REGULATOR_LEVEL_NOM 0>;
+ qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
+ RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
+ RPMH_REGULATOR_LEVEL_NOM 100000000>;
+
+ qcom,msm-bus,name = "pcie0";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <45 512 0 0>,
+ <45 512 500 800>;
+
+ clocks = <&clock_gcc GCC_PCIE_0_PIPE_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_PCIE_0_AUX_CLK>,
+ <&clock_gcc GCC_PCIE_0_CFG_AHB_CLK>,
+ <&clock_gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+ <&clock_gcc GCC_PCIE_0_SLV_AXI_CLK>,
+ <&clock_gcc GCC_PCIE_WIFI_CLKREF_EN>,
+ <&clock_gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+ <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&clock_gcc GCC_PCIE0_PHY_REFGEN_CLK>,
+ <&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
+ clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
+ "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
+ "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
+ "pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
+ "pcie_tbu_clk", "pcie_phy_refgen_clk",
+ "pcie_ddrss_sf_tbu_clk";
+ max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
+ <0>, <0>, <0>, <0>, <100000000>, <0>;
+
+ resets = <&clock_gcc GCC_PCIE_0_BCR>,
+ <&clock_gcc GCC_PCIE_0_PHY_BCR>;
+ reset-names = "pcie_0_core_reset",
+ "pcie_0_phy_reset";
+
+ dma-coherent;
+ qcom,smmu-sid-base = <0x1c00>;
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>;
+
+ qcom,boot-option = <0x1>;
+ qcom,drv-supported;
+ qcom,drv-l1ss-timeout-us = <10000>; /* 10ms */
+ qcom,use-19p2mhz-aux-clk;
+ qcom,no-l0s-supported;
+ qcom,l1-2-th-scale = <2>; /* 1us */
+ qcom,l1-2-th-value = <70>;
+ qcom,slv-addr-space-size = <0x4000000>;
+ qcom,ep-latency = <10>;
+
+ qcom,config-recovery;
+
+ qcom,pcie-phy-ver = <1102>;
+ qcom,phy-status-offset = <0x814>;
+ qcom,phy-status-bit = <6>;
+ qcom,phy-power-down-offset = <0x840>;
+ qcom,phy-sequence = <0x0840 0x03 0x0
+ 0x0094 0x08 0x0
+ 0x0154 0x34 0x0
+ 0x016c 0x08 0x0
+ 0x0058 0x0f 0x0
+ 0x00a4 0x42 0x0
+ 0x0110 0x24 0x0
+ 0x011c 0x03 0x0
+ 0x0118 0xb4 0x0
+ 0x010c 0x02 0x0
+ 0x01bc 0x11 0x0
+ 0x00bc 0x82 0x0
+ 0x00d4 0x03 0x0
+ 0x00d0 0x55 0x0
+ 0x00cc 0x55 0x0
+ 0x00b0 0x1a 0x0
+ 0x00ac 0x0a 0x0
+ 0x00c4 0x68 0x0
+ 0x00e0 0x02 0x0
+ 0x00dc 0xaa 0x0
+ 0x00d8 0xab 0x0
+ 0x00b8 0x34 0x0
+ 0x00b4 0x14 0x0
+ 0x0158 0x01 0x0
+ 0x0074 0x06 0x0
+ 0x007c 0x16 0x0
+ 0x0084 0x36 0x0
+ 0x0078 0x06 0x0
+ 0x0080 0x16 0x0
+ 0x0088 0x36 0x0
+ 0x01b0 0x1e 0x0
+ 0x01ac 0xca 0x0
+ 0x01b8 0x18 0x0
+ 0x01b4 0xa2 0x0
+ 0x0050 0x07 0x0
+ 0x0010 0x01 0x0
+ 0x001c 0x31 0x0
+ 0x0020 0x01 0x0
+ 0x0024 0xde 0x0
+ 0x0028 0x07 0x0
+ 0x0030 0x4c 0x0
+ 0x0034 0x06 0x0
+ 0x029c 0x12 0x0
+ 0x0284 0x35 0x0
+ 0x023c 0x11 0x0
+ 0x051c 0x03 0x0
+ 0x0518 0x1c 0x0
+ 0x0524 0x1e 0x0
+ 0x04e8 0x00 0x0
+ 0x04ec 0x0e 0x0
+ 0x04f0 0x4a 0x0
+ 0x04f4 0x0f 0x0
+ 0x05b4 0x04 0x0
+ 0x0434 0x7f 0x0
+ 0x0444 0x70 0x0
+ 0x0510 0x17 0x0
+ 0x04d4 0x04 0x0
+ 0x04d8 0x07 0x0
+ 0x0598 0xd4 0x0
+ 0x059c 0x54 0x0
+ 0x05a0 0xdb 0x0
+ 0x05a4 0x3b 0x0
+ 0x05a8 0x31 0x0
+ 0x0584 0x24 0x0
+ 0x0588 0xe4 0x0
+ 0x058c 0xec 0x0
+ 0x0590 0x3b 0x0
+ 0x0594 0x36 0x0
+ 0x0570 0x3f 0x0
+ 0x0574 0x3f 0x0
+ 0x0578 0xff 0x0
+ 0x057c 0x7f 0x0
+ 0x0580 0x14 0x0
+ 0x04fc 0x00 0x0
+ 0x04f8 0xc0 0x0
+ 0x0460 0x30 0x0
+ 0x0464 0x00 0x0
+ 0x05bc 0x0c 0x0
+ 0x04dc 0x1b 0x0
+ 0x0408 0x0c 0x0
+ 0x0414 0x03 0x0
+ 0x05b8 0x30 0x0
+ 0x09a4 0x01 0x0
+ 0x0c90 0x00 0x0
+ 0x0c40 0x01 0x0
+ 0x0c48 0x01 0x0
+ 0x0c50 0x00 0x0
+ 0x0cb4 0x33 0x0
+ 0x0cbc 0x00 0x0
+ 0x0ce0 0x58 0x0
+ 0x0ca4 0x0f 0x0
+ 0x0048 0x90 0x0
+ 0x0c1c 0xc1 0x0
+ 0x0988 0x77 0x0
+ 0x0998 0x0b 0x0
+ 0x08dc 0x0d 0x0
+ 0x09ec 0x12 0x0
+ 0x0800 0x00 0x0
+ 0x0844 0x03 0x0>;
+
+ pcie0_rp: pcie0_rp {
+ reg = <0 0 0 0 0>;
+ };
+ };
+
+ pcie0_msi: qcom,pcie0_msi@17a10040 {
+ compatible = "qcom,pci-msi";
+ msi-controller;
+ reg = <0x17a10040 0x0>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pcie1: qcom,pcie@1c08000 {
+ compatible = "qcom,pci-msm";
+
+ reg = <0x01c08000 0x3000>,
+ <0x01c0e000 0x2000>,
+ <0x40000000 0xf1d>,
+ <0x40000f20 0xa8>,
+ <0x40001000 0x1000>,
+ <0x40100000 0x100000>;
+ reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
+
+ cell-index = <1>;
+ linux,pci-domain = <1>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x40200000 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x40300000 0x0 0x1fd00000>;
+
+ interrupt-parent = <&pcie1>;
+ interrupts = <0 1 2 3 4>;
+ interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+ "int_d";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0xffffffff>;
+ interrupt-map = <0 0 0 0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
+ msi-parent = <&pcie1_msi>;
+
+ perst-gpio = <&tlmm 82 0>;
+ wake-gpio = <&tlmm 84 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_clkreq_default
+ &pcie1_perst_default
+ &pcie1_wake_default>;
+
+ gdsc-vdd-supply = <&pcie_1_gdsc>;
+ vreg-1p8-supply = <&pm8150_l9>;
+ vreg-0p9-supply = <&pm8150_l5>;
+ vreg-cx-supply = <&VDD_CX_LEVEL>;
+ qcom,vreg-1p8-voltage-level = <1200000 1200000 25000>;
+ qcom,vreg-0p9-voltage-level = <880000 880000 98800>;
+ qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+ RPMH_REGULATOR_LEVEL_NOM 0>;
+ qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
+ RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
+ RPMH_REGULATOR_LEVEL_NOM 100000000>;
+
+ qcom,msm-bus,name = "pcie1";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <100 512 0 0>,
+ <100 512 500 800>;
+
+ clocks = <&clock_gcc GCC_PCIE_1_PIPE_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_PCIE_1_AUX_CLK>,
+ <&clock_gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ <&clock_gcc GCC_PCIE_1_MSTR_AXI_CLK>,
+ <&clock_gcc GCC_PCIE_1_SLV_AXI_CLK>,
+ <&clock_gcc GCC_PCIE_WIGIG_CLKREF_EN>,
+ <&clock_gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
+ <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&clock_gcc GCC_PCIE1_PHY_REFGEN_CLK>,
+ <&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
+ clock-names = "pcie_1_pipe_clk", "pcie_1_ref_clk_src",
+ "pcie_1_aux_clk", "pcie_1_cfg_ahb_clk",
+ "pcie_1_mstr_axi_clk", "pcie_1_slv_axi_clk",
+ "pcie_1_ldo", "pcie_1_slv_q2a_axi_clk",
+ "pcie_tbu_clk", "pcie_phy_refgen_clk",
+ "pcie_ddrss_sf_tbu_clk";
+ max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
+ <0>, <0>, <0>, <0>, <100000000>, <0>;
+
+ resets = <&clock_gcc GCC_PCIE_1_BCR>,
+ <&clock_gcc GCC_PCIE_1_PHY_BCR>;
+ reset-names = "pcie_1_core_reset",
+ "pcie_1_phy_reset";
+
+ dma-coherent;
+ qcom,smmu-sid-base = <0x1c80>;
+ iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
+ <0x100 &apps_smmu 0x1c81 0x1>;
+
+ qcom,boot-option = <0x1>;
+ qcom,drv-supported;
+ qcom,use-19p2mhz-aux-clk;
+ qcom,no-l0s-supported;
+ qcom,slv-addr-space-size = <0x20000000>;
+ qcom,ep-latency = <10>;
+
+ qcom,pcie-phy-ver = <1102>;
+ qcom,phy-status-offset = <0xa14>;
+ qcom,phy-status-bit = <6>;
+ qcom,phy-power-down-offset = <0xa40>;
+ qcom,phy-sequence = <0x0a40 0x03 0x0
+ 0x0010 0x01 0x0
+ 0x001c 0x31 0x0
+ 0x0020 0x01 0x0
+ 0x0024 0xde 0x0
+ 0x0028 0x07 0x0
+ 0x0030 0x4c 0x0
+ 0x0034 0x06 0x0
+ 0x0048 0x90 0x0
+ 0x0058 0x0f 0x0
+ 0x0074 0x06 0x0
+ 0x0078 0x06 0x0
+ 0x007c 0x16 0x0
+ 0x0080 0x16 0x0
+ 0x0084 0x36 0x0
+ 0x0088 0x36 0x0
+ 0x0094 0x08 0x0
+ 0x00a4 0x42 0x0
+ 0x00ac 0x0a 0x0
+ 0x00b0 0x1a 0x0
+ 0x00b4 0x14 0x0
+ 0x00b8 0x34 0x0
+ 0x00bc 0x82 0x0
+ 0x00c4 0x68 0x0
+ 0x00cc 0x55 0x0
+ 0x00d0 0x55 0x0
+ 0x00d4 0x03 0x0
+ 0x00d8 0xab 0x0
+ 0x00dc 0xaa 0x0
+ 0x00e0 0x02 0x0
+ 0x010c 0x02 0x0
+ 0x0110 0x24 0x0
+ 0x0118 0xb4 0x0
+ 0x011c 0x03 0x0
+ 0x0154 0x34 0x0
+ 0x0158 0x01 0x0
+ 0x016c 0x08 0x0
+ 0x01ac 0xca 0x0
+ 0x01b0 0x1e 0x0
+ 0x01b4 0xa2 0x0
+ 0x01b8 0x18 0x0
+ 0x01bc 0x11 0x0
+ 0x023c 0x11 0x0
+ 0x0284 0x75 0x0
+ 0x029c 0x12 0x0
+ 0x0304 0x02 0x0
+ 0x0408 0x0c 0x0
+ 0x0414 0x03 0x0
+ 0x0434 0x7f 0x0
+ 0x0444 0x70 0x0
+ 0x0460 0x30 0x0
+ 0x04d4 0x04 0x0
+ 0x04d8 0x07 0x0
+ 0x04dc 0x1b 0x0
+ 0x04e8 0x04 0x0
+ 0x04ec 0x0e 0x0
+ 0x04f0 0x4a 0x0
+ 0x04f4 0x0f 0x0
+ 0x04f8 0xc0 0x0
+ 0x04fc 0x00 0x0
+ 0x0510 0x17 0x0
+ 0x0518 0x1c 0x0
+ 0x051c 0x03 0x0
+ 0x0524 0x1e 0x0
+ 0x0570 0xbf 0x0
+ 0x0574 0x3f 0x0
+ 0x0578 0xff 0x0
+ 0x057c 0x7f 0x0
+ 0x0580 0x15 0x0
+ 0x0584 0x24 0x0
+ 0x0588 0xe4 0x0
+ 0x058c 0xec 0x0
+ 0x0590 0x3b 0x0
+ 0x0594 0x36 0x0
+ 0x0598 0xd4 0x0
+ 0x059c 0x54 0x0
+ 0x05a0 0xdb 0x0
+ 0x05a4 0x3b 0x0
+ 0x05a8 0x31 0x0
+ 0x05bc 0x0c 0x0
+ 0x05b8 0x38 0x0
+ 0x063c 0x11 0x0
+ 0x0684 0x75 0x0
+ 0x069c 0x12 0x0
+ 0x0704 0x20 0x0
+ 0x0808 0x0c 0x0
+ 0x0814 0x03 0x0
+ 0x0834 0x7f 0x0
+ 0x0844 0x70 0x0
+ 0x0860 0x30 0x0
+ 0x08d4 0x04 0x0
+ 0x08d8 0x07 0x0
+ 0x08dc 0x1b 0x0
+ 0x08e8 0x04 0x0
+ 0x08ec 0x0e 0x0
+ 0x08f0 0x4a 0x0
+ 0x08f4 0x0f 0x0
+ 0x08f8 0xc0 0x0
+ 0x08fc 0x00 0x0
+ 0x0910 0x17 0x0
+ 0x0918 0x1c 0x0
+ 0x091c 0x03 0x0
+ 0x0924 0x1e 0x0
+ 0x0970 0xbf 0x0
+ 0x0974 0x3f 0x0
+ 0x0978 0xff 0x0
+ 0x097c 0x7f 0x0
+ 0x0980 0x15 0x0
+ 0x0984 0x24 0x0
+ 0x0988 0xe4 0x0
+ 0x098c 0xec 0x0
+ 0x0990 0x3b 0x0
+ 0x0994 0x36 0x0
+ 0x0998 0xd4 0x0
+ 0x099c 0x54 0x0
+ 0x09a0 0xdb 0x0
+ 0x09a4 0x3b 0x0
+ 0x09a8 0x31 0x0
+ 0x09bc 0x0c 0x0
+ 0x09b8 0x38 0x0
+ 0x0adc 0x05 0x0
+ 0x0b88 0x77 0x0
+ 0x0b98 0x0b 0x0
+ 0x0ba4 0x01 0x0
+ 0x0be0 0x0f 0x0
+ 0x0e0c 0x0d 0x0
+ 0x0e14 0x07 0x0
+ 0x0e1c 0xc1 0x0
+ 0x0e40 0x01 0x0
+ 0x0e48 0x01 0x0
+ 0x0e90 0x00 0x0
+ 0x0eb4 0x33 0x0
+ 0x0ebc 0x00 0x0
+ 0x0ee0 0x58 0x0
+ 0x0a00 0x00 0x0
+ 0x0a44 0x03 0x0>;
+
+ pcie1_rp: pcie1_rp {
+ reg = <0 0 0 0 0>;
+ };
+ };
+
+ pcie1_msi: qcom,pcie1_msi@17a10040 {
+ compatible = "qcom,pci-msi";
+ msi-controller;
+ reg = <0x17a10040 0x0>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 800 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 801 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 802 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 803 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 804 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 805 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 806 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 807 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 808 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 809 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 810 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 811 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 812 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 813 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 814 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 815 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 816 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 817 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 818 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 819 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 820 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 821 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 822 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 823 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 824 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 825 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 826 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 827 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 828 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 829 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 830 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 831 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pcie2: qcom,pcie@1c10000 {
+ compatible = "qcom,pci-msm";
+
+ reg = <0x01c10000 0x3000>,
+ <0x01c16000 0x2000>,
+ <0x64000000 0xf1d>,
+ <0x64000f20 0xa8>,
+ <0x64001000 0x1000>,
+ <0x64100000 0x100000>;
+ reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";
+
+ cell-index = <2>;
+ linux,pci-domain = <2>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x64200000 0x64200000 0x0 0x100000>,
+ <0x02000000 0x0 0x64300000 0x64300000 0x0 0x3d00000>;
+
+ interrupt-parent = <&pcie2>;
+ interrupts = <0 1 2 3 4>;
+ interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
+ "int_d";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0xffffffff>;
+ interrupt-map = <0 0 0 0 &intc GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 1 &intc GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 2 &intc GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 3 &intc GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
+ 0 0 0 4 &intc GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
+ msi-parent = <&pcie2_msi>;
+
+ perst-gpio = <&tlmm 85 0>;
+ wake-gpio = <&tlmm 87 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_clkreq_default
+ &pcie2_perst_default
+ &pcie2_wake_default>;
+
+ gdsc-vdd-supply = <&pcie_2_gdsc>;
+ vreg-1p8-supply = <&pm8150_l9>;
+ vreg-0p9-supply = <&pm8150_l5>;
+ vreg-cx-supply = <&VDD_CX_LEVEL>;
+ qcom,vreg-1p8-voltage-level = <1200000 1200000 25500>;
+ qcom,vreg-0p9-voltage-level = <880000 880000 98800>;
+ qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
+ RPMH_REGULATOR_LEVEL_NOM 0>;
+ qcom,bw-scale = <RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
+ RPMH_REGULATOR_LEVEL_LOW_SVS 19200000
+ RPMH_REGULATOR_LEVEL_NOM 100000000>;
+
+ qcom,msm-bus,name = "pcie2";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <108 512 0 0>,
+ <108 512 500 800>;
+
+ clocks = <&clock_gcc GCC_PCIE_2_PIPE_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_PCIE_2_AUX_CLK>,
+ <&clock_gcc GCC_PCIE_2_CFG_AHB_CLK>,
+ <&clock_gcc GCC_PCIE_2_MSTR_AXI_CLK>,
+ <&clock_gcc GCC_PCIE_2_SLV_AXI_CLK>,
+ <&clock_gcc GCC_PCIE_MDM_CLKREF_EN>,
+ <&clock_gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>,
+ <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
+ <&clock_gcc GCC_PCIE2_PHY_REFGEN_CLK>,
+ <&clock_gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
+ clock-names = "pcie_2_pipe_clk", "pcie_2_ref_clk_src",
+ "pcie_2_aux_clk", "pcie_2_cfg_ahb_clk",
+ "pcie_2_mstr_axi_clk", "pcie_2_slv_axi_clk",
+ "pcie_2_ldo", "pcie_2_slv_q2a_axi_clk",
+ "pcie_tbu_clk", "pcie_phy_refgen_clk",
+ "pcie_ddrss_sf_tbu_clk";
+ max-clock-frequency-hz = <0>, <0>, <19200000>, <0>, <0>, <0>,
+ <0>, <0>, <0>, <0>, <100000000>, <0>;
+
+ resets = <&clock_gcc GCC_PCIE_2_BCR>,
+ <&clock_gcc GCC_PCIE_2_PHY_BCR>;
+ reset-names = "pcie_2_core_reset",
+ "pcie_2_phy_reset";
+
+ dma-coherent;
+ qcom,smmu-sid-base = <0x1d00>;
+ iommu-map = <0x0 &apps_smmu 0x1d00 0x1>,
+ <0x100 &apps_smmu 0x1d01 0x1>;
+
+ qcom,boot-option = <0x1>;
+ qcom,drv-supported;
+ qcom,use-19p2mhz-aux-clk;
+ qcom,no-l0s-supported;
+ qcom,slv-addr-space-size = <0x4000000>;
+ qcom,ep-latency = <10>;
+
+ qcom,pcie-phy-ver = <1102>;
+ qcom,phy-status-offset = <0xa14>;
+ qcom,phy-status-bit = <6>;
+ qcom,phy-power-down-offset = <0xa40>;
+ qcom,phy-sequence = <0x0a40 0x03 0x0
+ 0x0010 0x01 0x0
+ 0x001c 0x31 0x0
+ 0x0020 0x01 0x0
+ 0x0024 0xde 0x0
+ 0x0028 0x07 0x0
+ 0x0030 0x4c 0x0
+ 0x0034 0x06 0x0
+ 0x0048 0x90 0x0
+ 0x0058 0x0f 0x0
+ 0x0074 0x06 0x0
+ 0x0078 0x06 0x0
+ 0x007c 0x16 0x0
+ 0x0080 0x16 0x0
+ 0x0084 0x36 0x0
+ 0x0088 0x36 0x0
+ 0x0094 0x08 0x0
+ 0x00a4 0x42 0x0
+ 0x00ac 0x0a 0x0
+ 0x00b0 0x1a 0x0
+ 0x00b4 0x14 0x0
+ 0x00b8 0x34 0x0
+ 0x00bc 0x82 0x0
+ 0x00c4 0x68 0x0
+ 0x00cc 0x55 0x0
+ 0x00d0 0x55 0x0
+ 0x00d4 0x03 0x0
+ 0x00d8 0xab 0x0
+ 0x00dc 0xaa 0x0
+ 0x00e0 0x02 0x0
+ 0x010c 0x02 0x0
+ 0x0110 0x24 0x0
+ 0x0118 0xb4 0x0
+ 0x011c 0x03 0x0
+ 0x0154 0x34 0x0
+ 0x0158 0x01 0x0
+ 0x016c 0x08 0x0
+ 0x01ac 0xca 0x0
+ 0x01b0 0x1e 0x0
+ 0x01b4 0xa2 0x0
+ 0x01b8 0x18 0x0
+ 0x01bc 0x11 0x0
+ 0x023c 0x11 0x0
+ 0x0284 0x75 0x0
+ 0x029c 0x12 0x0
+ 0x0304 0x02 0x0
+ 0x0408 0x0c 0x0
+ 0x0414 0x03 0x0
+ 0x0434 0x7f 0x0
+ 0x0444 0x70 0x0
+ 0x0460 0x30 0x0
+ 0x04d4 0x04 0x0
+ 0x04d8 0x07 0x0
+ 0x04dc 0x1b 0x0
+ 0x04e8 0x04 0x0
+ 0x04ec 0x0e 0x0
+ 0x04f0 0x4a 0x0
+ 0x04f4 0x0f 0x0
+ 0x04f8 0xc0 0x0
+ 0x04fc 0x00 0x0
+ 0x0510 0x17 0x0
+ 0x0518 0x1c 0x0
+ 0x051c 0x03 0x0
+ 0x0524 0x1e 0x0
+ 0x0570 0xbf 0x0
+ 0x0574 0x3f 0x0
+ 0x0578 0xff 0x0
+ 0x057c 0x7f 0x0
+ 0x0580 0x15 0x0
+ 0x0584 0x24 0x0
+ 0x0588 0xe4 0x0
+ 0x058c 0xec 0x0
+ 0x0590 0x3b 0x0
+ 0x0594 0x36 0x0
+ 0x0598 0xd4 0x0
+ 0x059c 0x54 0x0
+ 0x05a0 0xdb 0x0
+ 0x05a4 0x3b 0x0
+ 0x05a8 0x31 0x0
+ 0x05bc 0x0c 0x0
+ 0x05b8 0x38 0x0
+ 0x063c 0x11 0x0
+ 0x0684 0x75 0x0
+ 0x069c 0x12 0x0
+ 0x0704 0x20 0x0
+ 0x0808 0x0c 0x0
+ 0x0814 0x03 0x0
+ 0x0834 0x7f 0x0
+ 0x0844 0x70 0x0
+ 0x0860 0x30 0x0
+ 0x08d4 0x04 0x0
+ 0x08d8 0x07 0x0
+ 0x08dc 0x1b 0x0
+ 0x08e8 0x04 0x0
+ 0x08ec 0x0e 0x0
+ 0x08f0 0x4a 0x0
+ 0x08f4 0x0f 0x0
+ 0x08f8 0xc0 0x0
+ 0x08fc 0x00 0x0
+ 0x0910 0x17 0x0
+ 0x0918 0x1c 0x0
+ 0x091c 0x03 0x0
+ 0x0924 0x1e 0x0
+ 0x0970 0xbf 0x0
+ 0x0974 0x3f 0x0
+ 0x0978 0xff 0x0
+ 0x097c 0x7f 0x0
+ 0x0980 0x15 0x0
+ 0x0984 0x24 0x0
+ 0x0988 0xe4 0x0
+ 0x098c 0xec 0x0
+ 0x0990 0x3b 0x0
+ 0x0994 0x36 0x0
+ 0x0998 0xd4 0x0
+ 0x099c 0x54 0x0
+ 0x09a0 0xdb 0x0
+ 0x09a4 0x3b 0x0
+ 0x09a8 0x31 0x0
+ 0x09bc 0x0c 0x0
+ 0x09b8 0x38 0x0
+ 0x0adc 0x05 0x0
+ 0x0b88 0x77 0x0
+ 0x0b98 0x0b 0x0
+ 0x0ba4 0x01 0x0
+ 0x0be0 0x0f 0x0
+ 0x0e0c 0x0d 0x0
+ 0x0e14 0x07 0x0
+ 0x0e1c 0xc1 0x0
+ 0x0e40 0x01 0x0
+ 0x0e48 0x01 0x0
+ 0x0e90 0x00 0x0
+ 0x0eb4 0x33 0x0
+ 0x0ebc 0x00 0x0
+ 0x0ee0 0x58 0x0
+ 0x0a00 0x00 0x0
+ 0x0a44 0x03 0x0>;
+
+ pcie2_rp: pcie2_rp {
+ reg = <0 0 0 0 0>;
+ };
+ };
+
+ pcie2_msi: qcom,pcie2_msi@17a10040 {
+ compatible = "qcom,pci-msi";
+ msi-controller;
+ reg = <0x17a10040 0x0>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 832 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 833 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 834 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 835 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 836 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 837 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 838 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 839 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 840 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 841 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 842 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 843 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 844 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 845 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 846 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 847 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 848 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 849 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 850 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 851 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 852 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 853 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 854 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 855 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 856 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 857 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 858 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 859 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 860 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 862 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 863 IRQ_TYPE_EDGE_RISING>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-pinctrl.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-pinctrl.dtsi
new file mode 100755
index 0000000..51c240c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-pinctrl.dtsi
@@ -0,0 +1,4808 @@
+&soc {
+ tlmm: pinctrl@f000000 {
+ compatible = "qcom,kona-pinctrl";
+ reg = <0x0F000000 0x1000000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ wakeup-parent = <&pdc>;
+ irqdomain-map = <0 0 &pdc 79 0>,
+ <1 0 &pdc 84 0>,
+ <2 0 &pdc 80 0>,
+ <3 0 &pdc 82 0>,
+ <4 0 &pdc 107 0>,
+ <7 0 &pdc 43 0>,
+ <11 0 &pdc 42 0>,
+ <14 0 &pdc 44 0>,
+ <15 0 &pdc 52 0>,
+ <19 0 &pdc 67 0>,
+ <23 0 &pdc 68 0>,
+ <24 0 &pdc 105 0>,
+ <27 0 &pdc 92 0>,
+ <28 0 &pdc 106 0>,
+ <31 0 &pdc 69 0>,
+ <35 0 &pdc 70 0>,
+ <39 0 &pdc 73 0>,
+ <40 0 &pdc 108 0>,
+ <43 0 &pdc 71 0>,
+ <45 0 &pdc 72 0>,
+ <47 0 &pdc 83 0>,
+ <51 0 &pdc 74 0>,
+ <55 0 &pdc 77 0>,
+ <59 0 &pdc 78 0>,
+ <63 0 &pdc 75 0>,
+ <64 0 &pdc 81 0>,
+ <65 0 &pdc 87 0>,
+ <66 0 &pdc 88 0>,
+ <67 0 &pdc 89 0>,
+ <68 0 &pdc 54 0>,
+ <70 0 &pdc 85 0>,
+ <77 0 &pdc 46 0>,
+ <80 0 &pdc 90 0>,
+ <81 0 &pdc 91 0>,
+ <83 0 &pdc 97 0>,
+ <84 0 &pdc 98 0>,
+ <86 0 &pdc 99 0>,
+ <88 0 &pdc 101 0>,
+ <89 0 &pdc 102 0>,
+ <92 0 &pdc 103 0>,
+ <93 0 &pdc 104 0>,
+ <100 0 &pdc 53 0>,
+ <103 0 &pdc 47 0>,
+ <104 0 &pdc 48 0>,
+ <108 0 &pdc 49 0>,
+ <109 0 &pdc 94 0>,
+ <110 0 &pdc 95 0>,
+ <111 0 &pdc 96 0>,
+ <112 0 &pdc 55 0>,
+ <113 0 &pdc 56 0>,
+ <118 0 &pdc 50 0>,
+ <121 0 &pdc 51 0>,
+ <122 0 &pdc 57 0>,
+ <123 0 &pdc 58 0>,
+ <124 0 &pdc 45 0>,
+ <126 0 &pdc 59 0>,
+ <128 0 &pdc 76 0>,
+ <129 0 &pdc 86 0>,
+ <132 0 &pdc 93 0>,
+ <133 0 &pdc 65 0>,
+ <134 0 &pdc 66 0>,
+ <136 0 &pdc 62 0>,
+ <137 0 &pdc 63 0>,
+ <138 0 &pdc 64 0>,
+ <142 0 &pdc 60 0>,
+ <143 0 &pdc 61 0>,
+ <147 0 &pdc 109 0>, /* bi_mx_lpass_1_aoss_mx */
+ <150 0 &pdc 110 0>,
+ <157 0 &pdc 111 0>,
+ <158 0 &pdc 112 0>,
+ <160 0 &pdc 113 0>,
+ <162 0 &pdc 114 0>,
+ <164 0 &pdc 115 0>,
+ <166 0 &pdc 116 0>,
+ <167 0 &pdc 117 0>,
+ <175 0 &pdc 118 0>,
+ <177 0 &pdc 119 0>,
+ <179 0 &pdc 120 0>;
+ irqdomain-map-mask = <0xff 0>;
+ irqdomain-map-pass-thru = <0 0xff>;
+
+ trigout_a: trigout_a {
+ mux {
+ pins = "gpio2";
+ function = "qdss_cti";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se2_2uart_pins: qupv3_se2_2uart_pins {
+ qupv3_se2_2uart_active: qupv3_se2_2uart_active {
+ mux {
+ pins = "gpio117", "gpio118";
+ function = "qup2";
+ };
+
+ config {
+ pins = "gpio117", "gpio118";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se2_2uart_sleep: qupv3_se2_2uart_sleep {
+ mux {
+ pins = "gpio117", "gpio118";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio117", "gpio118";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ qupv3_se6_4uart_pins: qupv3_se6_4uart_pins {
+ qupv3_se6_default_cts:
+ qupv3_se6_default_cts {
+ mux {
+ pins = "gpio16";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se6_default_rtsrx:
+ qupv3_se6_default_rtsrx {
+ mux {
+ pins = "gpio17", "gpio19";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio17", "gpio19";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ qupv3_se6_default_tx:
+ qupv3_se6_default_tx {
+ mux {
+ pins = "gpio18";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio18";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se6_ctsrx: qupv3_se6_ctsrx {
+ mux {
+ pins = "gpio16", "gpio19";
+ function = "qup6";
+ };
+
+ config {
+ pins = "gpio16", "gpio19";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se6_rts: qupv3_se6_rts {
+ mux {
+ pins = "gpio17";
+ function = "qup6";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ qupv3_se6_tx: qupv3_se6_tx {
+ mux {
+ pins = "gpio18";
+ function = "qup6";
+ };
+
+ config {
+ pins = "gpio18";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ qupv3_se13_4uart_pins: qupv3_se13_4uart_pins {
+ qupv3_se13_default_cts:
+ qupv3_se13_default_cts {
+ mux {
+ pins = "gpio36";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio36";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se13_default_rtsrx:
+ qupv3_se13_default_rtsrx {
+ mux {
+ pins = "gpio37", "gpio39";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio37", "gpio39";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ qupv3_se13_default_tx:
+ qupv3_se13_default_tx {
+ mux {
+ pins = "gpio38";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio38";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se13_ctsrx: qupv3_se13_ctsrx {
+ mux {
+ pins = "gpio36", "gpio39";
+ function = "qup13";
+ };
+
+ config {
+ pins = "gpio36", "gpio39";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se13_rts: qupv3_se13_rts {
+ mux {
+ pins = "gpio37";
+ function = "qup13";
+ };
+
+ config {
+ pins = "gpio37";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ qupv3_se13_tx: qupv3_se13_tx {
+ mux {
+ pins = "gpio38";
+ function = "qup13";
+ };
+
+ config {
+ pins = "gpio38";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ qupv3_se12_2uart_pins: qupv3_se12_2uart_pins {
+ qupv3_se12_2uart_active: qupv3_se12_2uart_active {
+ mux {
+ pins = "gpio34", "gpio35";
+ function = "qup12";
+ };
+
+ config {
+ pins = "gpio34", "gpio35";
+ drive-strength = <2>;
+ };
+ };
+
+ qupv3_se12_2uart_sleep: qupv3_se12_2uart_sleep {
+ mux {
+ pins = "gpio34", "gpio35";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ config {
+ pins = "gpio34", "gpio35";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+
+ qupv3_se17_4uart_pins: qupv3_se17_4uart_pins {
+ qupv3_se17_ctsrx: qupv3_se17_ctsrx {
+ mux {
+ pins = "gpio52", "gpio55";
+ function = "qup17";
+ };
+
+ config {
+ pins = "gpio52", "gpio55";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+
+ qupv3_se17_rts: qupv3_se17_rts {
+ mux {
+ pins = "gpio53";
+ function = "qup17";
+ };
+
+ config {
+ pins = "gpio53";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ qupv3_se17_tx: qupv3_se17_tx {
+ mux {
+ pins = "gpio54";
+ function = "qup17";
+ };
+
+ config {
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ qupv3_se18_2uart_pins: qupv3_se18_2uart_pins {
+ qupv3_se18_rx: qupv3_se18_rx {
+ mux {
+ pins = "gpio59";
+ function = "qup18";
+ };
+
+ config {
+ pins = "gpio59";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+
+ qupv3_se18_tx: qupv3_se18_tx {
+ mux {
+ pins = "gpio58";
+ function = "qup18";
+ };
+
+ config {
+ pins = "gpio58";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_active {
+ ts_active: ts_active {
+ mux {
+ pins = "gpio38", "gpio39";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio38", "gpio39";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_int_suspend {
+ ts_int_suspend: ts_int_suspend {
+ mux {
+ pins = "gpio39";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio39";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_reset_suspend {
+ ts_reset_suspend: ts_reset_suspend {
+ mux {
+ pins = "gpio38";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio38";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_release {
+ pmx_ts_release: pmx_ts_release {
+ mux {
+ pins = "gpio38", "gpio39";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio38", "gpio39";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ ufs_dev_reset_assert: ufs_dev_reset_assert {
+ config {
+ pins = "ufs_reset";
+ bias-pull-down; /* default: pull down */
+ /*
+ * UFS_RESET driver strengths are having
+ * different values/steps compared to typical
+ * GPIO drive strengths.
+ *
+ * Following table clarifies:
+ *
+ * HDRV value | UFS_RESET | Typical GPIO
+ * (dec) | (mA) | (mA)
+ * 0 | 0.8 | 2
+ * 1 | 1.55 | 4
+ * 2 | 2.35 | 6
+ * 3 | 3.1 | 8
+ * 4 | 3.9 | 10
+ * 5 | 4.65 | 12
+ * 6 | 5.4 | 14
+ * 7 | 6.15 | 16
+ *
+ * POR value for UFS_RESET HDRV is 3 which means
+ * 3.1mA and we want to use that. Hence just
+ * specify 8mA to "drive-strength" binding and
+ * that should result into writing 3 to HDRV
+ * field.
+ */
+ drive-strength = <8>; /* default: 3.1 mA */
+ output-low; /* active low reset */
+ };
+ };
+
+ ufs_dev_reset_deassert: ufs_dev_reset_deassert {
+ config {
+ pins = "ufs_reset";
+ bias-pull-down; /* default: pull down */
+ /*
+ * default: 3.1 mA
+ * check comments under ufs_dev_reset_assert
+ */
+ drive-strength = <8>;
+ output-high; /* active low reset */
+ };
+ };
+
+ storage_cd: storage_cd {
+ mux {
+ pins = "gpio77";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio77";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_clk_on: sdc2_clk_on {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_clk_off: sdc2_clk_off {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_clk_ds_400KHz: sdc2_clk_ds_400KHz {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_clk_ds_50MHz: sdc2_clk_ds_50MHz {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_clk_ds_100MHz: sdc2_clk_ds_100MHz {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_clk_ds_200MHz: sdc2_clk_ds_200MHz {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_cmd_on: sdc2_cmd_on {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_cmd_off: sdc2_cmd_off {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_cmd_ds_400KHz: sdc2_cmd_ds_400KHz {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_cmd_ds_50MHz: sdc2_cmd_ds_50MHz {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_cmd_ds_100MHz: sdc2_cmd_ds_100MHz {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_cmd_ds_200MHz: sdc2_cmd_ds_200MHz {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_data_on: sdc2_data_on {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_data_off: sdc2_data_off {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_data_ds_400KHz: sdc2_data_ds_400KHz {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_data_ds_50MHz: sdc2_data_ds_50MHz {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_data_ds_100MHz: sdc2_data_ds_100MHz {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_data_ds_200MHz: sdc2_data_ds_200MHz {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ /* add pins for DisplayPort */
+ sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active {
+ mux {
+ pins = "gpio65";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio65";
+ bias-disable;
+ drive-strength = <16>;
+ };
+ };
+
+ sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_suspend {
+ mux {
+ pins = "gpio65";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio65";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+ };
+
+ ap2mdm {
+ ap2mdm_active: ap2mdm_active {
+ mux {
+ /* ap2mdm-status
+ * ap2mdm-errfatal
+ * ap2mdm-vddmin
+ */
+ pins = "gpio56", "gpio57";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio56", "gpio57";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ ap2mdm_sleep: ap2mdm_sleep {
+ mux {
+ /* ap2mdm-status
+ * ap2mdm-errfatal
+ * ap2mdm-vddmin
+ */
+ pins = "gpio56", "gpio57";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio56", "gpio57";
+ drive-strength = <8>;
+ bias-disable;
+ };
+
+ };
+ };
+
+ mdm2ap {
+ mdm2ap_active: mdm2ap_active {
+ mux {
+ /* mdm2ap-status
+ * mdm2ap-errfatal
+ * mdm2ap-vddmin
+ */
+ pins = "gpio1", "gpio3";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio1", "gpio3";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ mdm2ap_sleep: mdm2ap_sleep {
+ mux {
+ /* mdm2ap-status
+ * mdm2ap-errfatal
+ * mdm2ap-vddmin
+ */
+ pins = "gpio1", "gpio3";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio1", "gpio3";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+ };
+
+ pcie0 {
+ pcie0_perst_default: pcie0_perst_default {
+ mux {
+ pins = "gpio79";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio79";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie0_clkreq_default: pcie0_clkreq_default {
+ mux {
+ pins = "gpio80";
+ function = "pci_e0";
+ };
+
+ config {
+ pins = "gpio80";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie0_wake_default: pcie0_wake_default {
+ mux {
+ pins = "gpio81";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio81";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie0_clkreq_sleep: pcie0_clkreq_sleep {
+ mux {
+ pins = "gpio80";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio80";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pcie1 {
+ pcie1_perst_default: pcie1_perst_default {
+ mux {
+ pins = "gpio82";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio82";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie1_clkreq_default: pcie1_clkreq_default {
+ mux {
+ pins = "gpio83";
+ function = "pci_e1";
+ };
+
+ config {
+ pins = "gpio83";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie1_wake_default: pcie1_wake_default {
+ mux {
+ pins = "gpio84";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio84";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pcie2 {
+ pcie2_perst_default: pcie2_perst_default {
+ mux {
+ pins = "gpio85";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio85";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ pcie2_clkreq_default: pcie2_clkreq_default {
+ mux {
+ pins = "gpio86";
+ function = "pci_e2";
+ };
+
+ config {
+ pins = "gpio86";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pcie2_wake_default: pcie2_wake_default {
+ mux {
+ pins = "gpio87";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio87";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ cnss_pins {
+ cnss_wlan_en_active: cnss_wlan_en_active {
+ mux {
+ pins = "gpio20";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio20";
+ drive-strength = <16>;
+ output-high;
+ bias-pull-up;
+ };
+ };
+
+ cnss_wlan_en_sleep: cnss_wlan_en_sleep {
+ mux {
+ pins = "gpio20";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio20";
+ drive-strength = <2>;
+ output-low;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_sde: pmx_sde {
+ sde_dsi_active: sde_dsi_active {
+ mux {
+ pins = "gpio75", "gpio60";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio75", "gpio60";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable = <0>; /* no pull */
+ };
+ };
+
+ sde_dsi_suspend: sde_dsi_suspend {
+ mux {
+ pins = "gpio75", "gpio60";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio75", "gpio60";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+
+ sde_dsi1_active: sde_dsi1_active {
+ mux {
+ pins = "gpio128";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio128";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable = <0>; /* no pull */
+ };
+ };
+
+ sde_dsi1_suspend: sde_dsi1_suspend {
+ mux {
+ pins = "gpio128";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio128";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+ };
+
+ pmx_sde_te {
+ sde_te_active: sde_te_active {
+ mux {
+ pins = "gpio66";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio66";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+
+ sde_te_suspend: sde_te_suspend {
+ mux {
+ pins = "gpio66";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio66";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+
+ sde_te1_active: sde_te1_active {
+ mux {
+ pins = "gpio67";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio67";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+
+ sde_te1_suspend: sde_te1_suspend {
+ mux {
+ pins = "gpio67";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio67";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+ };
+
+ pri_aux_pcm_clk {
+ pri_aux_pcm_clk_sleep: pri_aux_pcm_clk_sleep {
+ mux {
+ pins = "gpio138";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio138";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_aux_pcm_clk_active: pri_aux_pcm_clk_active {
+ mux {
+ pins = "gpio138";
+ function = "mi2s0_sck";
+ };
+
+ config {
+ pins = "gpio138";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ pri_aux_pcm_sync {
+ pri_aux_pcm_sync_sleep: pri_aux_pcm_sync_sleep {
+ mux {
+ pins = "gpio141";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio141";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_aux_pcm_sync_active: pri_aux_pcm_sync_active {
+ mux {
+ pins = "gpio141";
+ function = "mi2s0_ws";
+ };
+
+ config {
+ pins = "gpio141";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ pri_aux_pcm_din {
+ pri_aux_pcm_din_sleep: pri_aux_pcm_din_sleep {
+ mux {
+ pins = "gpio139";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio139";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_aux_pcm_din_active: pri_aux_pcm_din_active {
+ mux {
+ pins = "gpio139";
+ function = "mi2s0_data0";
+ };
+
+ config {
+ pins = "gpio139";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ pri_aux_pcm_dout {
+ pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep {
+ mux {
+ pins = "gpio140";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio140";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_aux_pcm_dout_active: pri_aux_pcm_dout_active {
+ mux {
+ pins = "gpio140";
+ function = "mi2s0_data1";
+ };
+
+ config {
+ pins = "gpio140";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ sec_aux_pcm {
+ sec_aux_pcm_clk_sleep: sec_aux_pcm_clk_sleep {
+ mux {
+ pins = "gpio142";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio142";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_aux_pcm_clk_active: sec_aux_pcm_clk_active {
+ mux {
+ pins = "gpio142";
+ function = "mi2s1_sck";
+ };
+
+ config {
+ pins = "gpio142";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+
+ sec_aux_pcm_ws_sleep: sec_aux_pcm_ws_sleep {
+ mux {
+ pins = "gpio145";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio145";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_aux_pcm_ws_active: sec_aux_pcm_ws_active {
+ mux {
+ pins = "gpio145";
+ function = "mi2s1_ws";
+ };
+
+ config {
+ pins = "gpio145";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ sec_aux_pcm_din {
+ sec_aux_pcm_din_sleep: sec_aux_pcm_din_sleep {
+ mux {
+ pins = "gpio143";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio143";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_aux_pcm_din_active: sec_aux_pcm_din_active {
+ mux {
+ pins = "gpio143";
+ function = "mi2s1_data0";
+ };
+
+ config {
+ pins = "gpio143";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ sec_aux_pcm_dout {
+ sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep {
+ mux {
+ pins = "gpio144";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio144";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_aux_pcm_dout_active: sec_aux_pcm_dout_active {
+ mux {
+ pins = "gpio144";
+ function = "mi2s1_data1";
+ };
+
+ config {
+ pins = "gpio144";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ tert_aux_pcm {
+ tert_aux_pcm_clk_sleep: tert_aux_pcm_clk_sleep {
+ mux {
+ pins = "gpio133";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio133";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_aux_pcm_clk_active: tert_aux_pcm_clk_active {
+ mux {
+ pins = "gpio133";
+ function = "mi2s2_sck";
+ };
+
+ config {
+ pins = "gpio133";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+
+ tert_aux_pcm_ws_sleep: tert_aux_pcm_ws_sleep {
+ mux {
+ pins = "gpio135";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio135";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_aux_pcm_ws_active: tert_aux_pcm_ws_active {
+ mux {
+ pins = "gpio135";
+ function = "mi2s2_ws";
+ };
+
+ config {
+ pins = "gpio135";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ tert_aux_pcm_din {
+ tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep {
+ mux {
+ pins = "gpio134";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio134";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_aux_pcm_din_active: tert_aux_pcm_din_active {
+ mux {
+ pins = "gpio134";
+ function = "mi2s2_data0";
+ };
+
+ config {
+ pins = "gpio134";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ tert_aux_pcm_dout {
+ tert_aux_pcm_dout_sleep: tert_aux_pcm_dout_sleep {
+ mux {
+ pins = "gpio137";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio137";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_aux_pcm_dout_active: tert_aux_pcm_dout_active {
+ mux {
+ pins = "gpio137";
+ function = "mi2s2_data1";
+ };
+
+ config {
+ pins = "gpio137";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ pri_tdm_clk {
+ pri_tdm_clk_sleep: pri_tdm_clk_sleep {
+ mux {
+ pins = "gpio138";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio138";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_tdm_clk_active: pri_tdm_clk_active {
+ mux {
+ pins = "gpio138";
+ function = "mi2s0_sck";
+ };
+
+ config {
+ pins = "gpio138";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ pri_tdm_sync {
+ pri_tdm_sync_sleep: pri_tdm_sync_sleep {
+ mux {
+ pins = "gpio141";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio141";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_tdm_sync_active: pri_tdm_sync_active {
+ mux {
+ pins = "gpio141";
+ function = "mi2s0_ws";
+ };
+
+ config {
+ pins = "gpio141";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ pri_tdm_din {
+ pri_tdm_din_sleep: pri_tdm_din_sleep {
+ mux {
+ pins = "gpio139";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio139";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_tdm_din_active: pri_tdm_din_active {
+ mux {
+ pins = "gpio139";
+ function = "mi2s0_data0";
+ };
+
+ config {
+ pins = "gpio139";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ pri_tdm_dout {
+ pri_tdm_dout_sleep: pri_tdm_dout_sleep {
+ mux {
+ pins = "gpio140";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio140";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_tdm_dout_active: pri_tdm_dout_active {
+ mux {
+ pins = "gpio140";
+ function = "mi2s0_data1";
+ };
+
+ config {
+ pins = "gpio140";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ sec_tdm {
+ sec_tdm_sck_sleep: sec_tdm_sck_sleep {
+ mux {
+ pins = "gpio142";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio142";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_tdm_sck_active: sec_tdm_sck_active {
+ mux {
+ pins = "gpio142";
+ function = "mi2s1_sck";
+ };
+
+ config {
+ pins = "gpio142";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+
+ sec_tdm_ws_sleep: sec_tdm_ws_sleep {
+ mux {
+ pins = "gpio145";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio145";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_tdm_ws_active: sec_tdm_ws_active {
+ mux {
+ pins = "gpio145";
+ function = "mi2s1_ws";
+ };
+
+ config {
+ pins = "gpio145";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ sec_tdm_din {
+ sec_tdm_din_sleep: sec_tdm_din_sleep {
+ mux {
+ pins = "gpio143";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio143";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_tdm_din_active: sec_tdm_din_active {
+ mux {
+ pins = "gpio143";
+ function = "mi2s1_data0";
+ };
+
+ config {
+ pins = "gpio143";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ sec_tdm_dout {
+ sec_tdm_dout_sleep: sec_tdm_dout_sleep {
+ mux {
+ pins = "gpio144";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio144";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_tdm_dout_active: sec_tdm_dout_active {
+ mux {
+ pins = "gpio144";
+ function = "mi2s1_data1";
+ };
+
+ config {
+ pins = "gpio144";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ tert_tdm {
+ tert_tdm_clk_sleep: tert_tdm_clk_sleep {
+ mux {
+ pins = "gpio133";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio133";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_tdm_clk_active: tert_tdm_clk_active {
+ mux {
+ pins = "gpio133";
+ function = "mi2s2_sck";
+ };
+
+ config {
+ pins = "gpio133";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+
+ tert_tdm_ws_sleep: tert_tdm_ws_sleep {
+ mux {
+ pins = "gpio135";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio135";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_tdm_ws_active: tert_tdm_ws_active {
+ mux {
+ pins = "gpio135";
+ function = "mi2s2_ws";
+ };
+
+ config {
+ pins = "gpio135";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ tert_tdm_din {
+ tert_tdm_din_sleep: tert_tdm_din_sleep {
+ mux {
+ pins = "gpio134";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio134";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_tdm_din_active: tert_tdm_din_active {
+ mux {
+ pins = "gpio134";
+ function = "mi2s2_data0";
+ };
+
+ config {
+ pins = "gpio134";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ tert_tdm_dout {
+ tert_tdm_dout_sleep: tert_tdm_dout_sleep {
+ mux {
+ pins = "gpio137";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio137";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_tdm_dout_active: tert_tdm_dout_active {
+ mux {
+ pins = "gpio137";
+ function = "mi2s2_data1";
+ };
+
+ config {
+ pins = "gpio137";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ pri_mi2s_mclk {
+ pri_mi2s_mclk_sleep: pri_mi2s_mclk_sleep {
+ mux {
+ pins = "gpio136";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio136";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_mi2s_mclk_active: pri_mi2s_mclk_active {
+ mux {
+ pins = "gpio136";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio136";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ pri_mi2s_sck {
+ pri_mi2s_sck_sleep: pri_mi2s_sck_sleep {
+ mux {
+ pins = "gpio138";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio138";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_mi2s_sck_active: pri_mi2s_sck_active {
+ mux {
+ pins = "gpio138";
+ function = "mi2s0_sck";
+ };
+
+ config {
+ pins = "gpio138";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ pri_mi2s_ws {
+ pri_mi2s_ws_sleep: pri_mi2s_ws_sleep {
+ mux {
+ pins = "gpio141";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio141";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_mi2s_ws_active: pri_mi2s_ws_active {
+ mux {
+ pins = "gpio141";
+ function = "mi2s0_ws";
+ };
+
+ config {
+ pins = "gpio141";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ pri_mi2s_sd0 {
+ pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep {
+ mux {
+ pins = "gpio139";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio139";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_mi2s_sd0_active: pri_mi2s_sd0_active {
+ mux {
+ pins = "gpio139";
+ function = "mi2s0_data0";
+ };
+
+ config {
+ pins = "gpio139";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ pri_mi2s_sd1 {
+ pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep {
+ mux {
+ pins = "gpio140";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio140";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_mi2s_sd1_active: pri_mi2s_sd1_active {
+ mux {
+ pins = "gpio140";
+ function = "mi2s0_data1";
+ };
+
+ config {
+ pins = "gpio140";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ sec_mi2s_mclk {
+ sec_mi2s_mclk_sleep: sec_mi2s_mclk_sleep {
+ mux {
+ pins = "gpio137";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio137";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_mi2s_mclk_active: sec_mi2s_mclk_active {
+ mux {
+ pins = "gpio137";
+ function = "sec_mi2s";
+ };
+
+ config {
+ pins = "gpio137";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ sec_mi2s_sck {
+ sec_mi2s_sck_sleep: sec_mi2s_sck_sleep {
+ mux {
+ pins = "gpio142";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio142";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_mi2s_sck_active: sec_mi2s_sck_active {
+ mux {
+ pins = "gpio142";
+ function = "mi2s1_sck";
+ };
+
+ config {
+ pins = "gpio142";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ sec_mi2s_ws {
+ sec_mi2s_ws_sleep: sec_mi2s_ws_sleep {
+ mux {
+ pins = "gpio145";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio145";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_mi2s_ws_active: sec_mi2s_ws_active {
+ mux {
+ pins = "gpio145";
+ function = "mi2s1_ws";
+ };
+
+ config {
+ pins = "gpio145";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ sec_mi2s_sd0 {
+ sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep {
+ mux {
+ pins = "gpio143";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio143";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_mi2s_sd0_active: sec_mi2s_sd0_active {
+ mux {
+ pins = "gpio143";
+ function = "mi2s1_data0";
+ };
+
+ config {
+ pins = "gpio143";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ sec_mi2s_sd1 {
+ sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep {
+ mux {
+ pins = "gpio144";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio144";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_mi2s_sd1_active: sec_mi2s_sd1_active {
+ mux {
+ pins = "gpio144";
+ function = "mi2s1_data1";
+ };
+
+ config {
+ pins = "gpio144";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ tert_mi2s_sck {
+ tert_mi2s_sck_sleep: tert_mi2s_sck_sleep {
+ mux {
+ pins = "gpio133";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio133";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_mi2s_sck_active: tert_mi2s_sck_active {
+ mux {
+ pins = "gpio133";
+ function = "mi2s2_sck";
+ };
+
+ config {
+ pins = "gpio133";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ tert_mi2s_ws {
+ tert_mi2s_ws_sleep: tert_mi2s_ws_sleep {
+ mux {
+ pins = "gpio135";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio135";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_mi2s_ws_active: tert_mi2s_ws_active {
+ mux {
+ pins = "gpio135";
+ function = "mi2s2_ws";
+ };
+
+ config {
+ pins = "gpio135";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ tert_mi2s_sd0 {
+ tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep {
+ mux {
+ pins = "gpio134";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio134";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_mi2s_sd0_active: tert_mi2s_sd0_active {
+ mux {
+ pins = "gpio134";
+ function = "mi2s2_data0";
+ };
+
+ config {
+ pins = "gpio134";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ tert_mi2s_sd1 {
+ tert_mi2s_sd1_sleep: tert_mi2s_sd1_sleep {
+ mux {
+ pins = "gpio137";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio137";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_mi2s_sd1_active: tert_mi2s_sd1_active {
+ mux {
+ pins = "gpio137";
+ function = "mi2s2_data1";
+ };
+
+ config {
+ pins = "gpio137";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ /* WSA speaker reset pins */
+ spkr_1_sd_n {
+ spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+ mux {
+ pins = "gpio26";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio26";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_1_sd_n_active: spkr_1_sd_n_active {
+ mux {
+ pins = "gpio26";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio26";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ spkr_2_sd_n {
+ spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
+ mux {
+ pins = "gpio127";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio127";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_2_sd_n_active: spkr_2_sd_n_active {
+ mux {
+ pins = "gpio127";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio127";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ wcd938x_reset_active: wcd938x_reset_active {
+ mux {
+ pins = "gpio32";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio32";
+ drive-strength = <16>;
+ output-high;
+ };
+ };
+
+ wcd938x_reset_sleep: wcd938x_reset_sleep {
+ mux {
+ pins = "gpio32";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio32";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cam_sensor_mclk0_active: cam_sensor_mclk0_active {
+ /* MCLK0 */
+ mux {
+ pins = "gpio94";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio94";
+ bias-disable; /* No PULL */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
+ /* MCLK0 */
+ mux {
+ pins = "gpio94";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio94";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ cam_sensor_mclk1_active: cam_sensor_mclk1_active {
+ /* MCLK1 */
+ mux {
+ pins = "gpio95";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio95";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
+ /* MCLK1 */
+ mux {
+ pins = "gpio95";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio95";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk2_active: cam_sensor_mclk2_active {
+ /* MCLK2 */
+ mux {
+ pins = "gpio96";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio96";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
+ /* MCLK2 */
+ mux {
+ pins = "gpio96";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio96";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk3_active: cam_sensor_mclk3_active {
+ /* MCLK3 */
+ mux {
+ pins = "gpio97";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio97";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend {
+ /* MCLK3 */
+ mux {
+ pins = "gpio97";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio97";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk4_active: cam_sensor_mclk4_active {
+ /* MCLK4 */
+ mux {
+ pins = "gpio98";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio98";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend {
+ /* MCLK4 */
+ mux {
+ pins = "gpio98";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio98";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk5_active: cam_sensor_mclk5_active {
+ /* MCLK5 */
+ mux {
+ pins = "gpio99";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio99";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk5_suspend: cam_sensor_mclk5_suspend {
+ /* MCLK5 */
+ mux {
+ pins = "gpio99";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio99";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk6_active: cam_sensor_mclk6_active {
+ /* MCLK6 */
+ mux {
+ pins = "gpio100";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio100";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk6_suspend: cam_sensor_mclk6_suspend {
+ /* MCLK6 */
+ mux {
+ pins = "gpio100";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio100";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_active_rear: cam_sensor_active_rear {
+ /* RESET REAR */
+ mux {
+ pins = "gpio93";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio93";
+ bias-disable; /* No PULL */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ cam_sensor_suspend_rear: cam_sensor_suspend_rear {
+ /* RESET REAR */
+ mux {
+ pins = "gpio93";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio93";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <8>; /* 8 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_rear_aux: cam_sensor_active_rear_aux {
+ /* RESET REARAUX */
+ mux {
+ pins = "gpio92";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio92";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_rear_aux: cam_sensor_suspend_rear_aux {
+ /* RESET REARAUX */
+ mux {
+ pins = "gpio92";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio92";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_rst2: cam_sensor_active_rst2 {
+ /* RESET 2 */
+ mux {
+ pins = "gpio78";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio78";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 {
+ /* RESET 2 */
+ mux {
+ pins = "gpio78";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio78";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_rst3: cam_sensor_active_rst3 {
+ /* RESET 2 */
+ mux {
+ pins = "gpio144";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio144";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 {
+ /* RESET 2 */
+ mux {
+ pins = "gpio144";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio144";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_rst4: cam_sensor_active_rst4 {
+ /* RESET 2 */
+ mux {
+ pins = "gpio25";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio25";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_rst4: cam_sensor_suspend_rst4 {
+ /* RESET 2 */
+ mux {
+ pins = "gpio25";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio25";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_3: cam_sensor_active_3 {
+ /* RESET 3 */
+ mux {
+ pins = "gpio109";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio109";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_3: cam_sensor_suspend_3 {
+ /* RESET 3 */
+ mux {
+ pins = "gpio109";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio109";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_4: cam_sensor_active_4 {
+ /* RESET 4 */
+ mux {
+ pins = "gpio130";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio130";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_4: cam_sensor_suspend_4 {
+ /* RESET 4 */
+ mux {
+ pins = "gpio130";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio130";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_5: cam_sensor_active_5 {
+ /* RESET 5 */
+ mux {
+ pins = "gpio131";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio131";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_5: cam_sensor_suspend_5 {
+ /* RESET 5 */
+ mux {
+ pins = "gpio131";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio131";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_6: cam_sensor_active_6 {
+ /* RESET 6 */
+ mux {
+ pins = "gpio114";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio114";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_6: cam_sensor_suspend_6 {
+ /* RESET 6 */
+ mux {
+ pins = "gpio114";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio114";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cci0_active: cci0_active {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio101","gpio102"; // Only 2
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio101","gpio102";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci0_suspend: cci0_suspend {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio101","gpio102";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio101","gpio102";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci1_active: cci1_active {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio103","gpio104";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio103","gpio104";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci1_suspend: cci1_suspend {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio103","gpio104";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio103","gpio104";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci2_active: cci2_active {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio105","gpio106";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio105","gpio106";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci2_suspend: cci2_suspend {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio105","gpio106";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio105","gpio106";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci3_active: cci3_active {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio107","gpio108";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio107","gpio108";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci3_suspend: cci3_suspend {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio107","gpio108";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio107","gpio108";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ tsif0_signals_active: tsif0_signals_active {
+ tsif1_clk {
+ pins = "gpio69"; /* TSIF0 CLK */
+ function = "tsif0_clk";
+ };
+
+ tsif1_en {
+ pins = "gpio70"; /* TSIF0 Enable */
+ function = "tsif0_en";
+ };
+
+ tsif1_data {
+ pins = "gpio71"; /* TSIF0 DATA */
+ function = "tsif0_data";
+ };
+
+ signals_cfg {
+ pins = "gpio69", "gpio70", "gpio71";
+ drive_strength = <2>; /* 2 mA */
+ bias-pull-down; /* pull down */
+ };
+ };
+
+ /* sync signal is only used if configured to mode-2 */
+ tsif0_sync_active: tsif0_sync_active {
+ tsif1_sync {
+ pins = "gpio72"; /* TSIF0 SYNC */
+ function = "tsif0_sync";
+ drive_strength = <2>; /* 2 mA */
+ bias-pull-down; /* pull down */
+ };
+ };
+
+ tsif1_signals_active: tsif1_signals_active {
+ tsif2_clk {
+ pins = "gpio73"; /* TSIF1 CLK */
+ function = "tsif1_clk";
+ };
+
+ tsif2_en {
+ pins = "gpio74"; /* TSIF1 Enable */
+ function = "tsif1_en";
+ };
+
+ tsif2_data {
+ pins = "gpio75"; /* TSIF1 DATA */
+ function = "tsif1_data";
+ };
+
+ signals_cfg {
+ pins = "gpio73", "gpio74", "gpio75";
+ drive_strength = <2>; /* 2 mA */
+ bias-pull-down; /* pull down */
+ };
+ };
+
+ /* sync signal is only used if configured to mode-2 */
+ tsif1_sync_active: tsif1_sync_active {
+ tsif2_sync {
+ pins = "gpio76"; /* TSIF1 SYNC */
+ function = "tsif1_sync";
+ drive_strength = <2>; /* 2 mA */
+ bias-pull-down; /* pull down */
+ };
+ };
+
+ sde_led_driver_en1_gpio: sde_led_driver_en1_gpio {
+ mux {
+ pins = "gpio144";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio144";
+ bias-pull-down;
+ drive-strength = <16>;
+ };
+ };
+
+ sde_led_driver_en2_gpio: sde_led_driver_en2_gpio {
+ mux {
+ pins = "gpio140";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio140";
+ bias-pull-down;
+ drive-strength = <16>;
+ };
+ };
+
+ sde_led_5v_en_gpio: sde_led_5v_en_gpio {
+ mux {
+ pins = "gpio134";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio134";
+ bias-pull-down;
+ drive-strength = <16>;
+ };
+ };
+
+ sde_display_1p8_en_gpio: sde_display_1p8_en_gpio {
+ mux {
+ pins = "gpio133";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio133";
+ bias-pull-down;
+ drive-strength = <16>;
+ };
+ };
+
+ cam_sensor_6dof_vana_active: cam_sensor_6dof_vana_active {
+ /* AVDD LDO */
+ mux {
+ pins = "gpio84";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio84";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vana_suspend: cam_sensor_6dof_vana_suspend {
+ /* AVDD LDO */
+ mux {
+ pins = "gpio84";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio84";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vdig_active: cam_sensor_6dof_vdig_active {
+ /* VDIG LDO */
+ mux {
+ pins = "gpio82";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio82";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vdig_suspend: cam_sensor_6dof_vdig_suspend {
+ /* VDIG LDO */
+ mux {
+ pins = "gpio82";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio82";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vio_active: cam_sensor_6dof_vio_active {
+ /* VIO LDO */
+ mux {
+ pins = "gpio83";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio83";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vio_suspend: cam_sensor_6dof_vio_suspend {
+ /* VIO LDO */
+ mux {
+ pins = "gpio83";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio83";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_et_vana_active: cam_sensor_et_vana_active {
+ /* AVDD LDO */
+ mux {
+ pins = "gpio114";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio114";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_et_vana_suspend: cam_sensor_et_vana_suspend {
+ /* AVDD LDO */
+ mux {
+ pins = "gpio114";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio114";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_et_vio_active: cam_sensor_et_vio_active {
+ /* VIO LDO */
+ mux {
+ pins = "gpio145";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio145";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_et_vio_suspend: cam_sensor_et_vio_suspend {
+ /* VIO LDO */
+ mux {
+ pins = "gpio145";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio145";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rgb_vana_active: cam_sensor_rgb_vana_active {
+ mux {
+ pins = "gpio117";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio117";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rgb_vana_suspend: cam_sensor_rgb_vana_suspend {
+ mux {
+ pins = "gpio117";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio117";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rgb_vio_active: cam_sensor_rgb_vio_active {
+ mux {
+ pins = "gpio116";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio116";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rgb_vio_suspend: cam_sensor_rgb_vio_suspend {
+ mux {
+ pins = "gpio116";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio116";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rgb_vdig_active: cam_sensor_rgb_vdig_active {
+ mux {
+ pins = "gpio115";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio115";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rgb_vdig_suspend: cam_sensor_rgb_vdig_suspend {
+ mux {
+ pins = "gpio115";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio115";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_active_etleft: cam_sensor_active_etleft {
+ /* RESET REAR */
+ mux {
+ pins = "gpio93";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio93";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_etleft: cam_sensor_suspend_etleft {
+ /* RESET REAR */
+ mux {
+ pins = "gpio93";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio93";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_etright: cam_sensor_active_etright {
+ /* RESET REAR */
+ mux {
+ pins = "gpio92";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio92";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_etright: cam_sensor_suspend_etright {
+ /* RESET REAR */
+ mux {
+ pins = "gpio92";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio92";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_6dofleft: cam_sensor_active_6dofleft {
+ /* RESET REAR */
+ mux {
+ pins = "gpio130";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio130";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_6dofleft: cam_sensor_suspend_6dofleft {
+ /* RESET REAR */
+ mux {
+ pins = "gpio130";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio130";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_6dofright: cam_sensor_active_6dofright {
+ /* RESET REAR */
+ mux {
+ pins = "gpio131";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio131";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_6dofright: cam_sensor_suspend_6dofright {
+ /* RESET REAR */
+ mux {
+ pins = "gpio131";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio131";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_rgbright: cam_sensor_active_rgbright {
+ /* RESET REAR */
+ mux {
+ pins = "gpio109";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio109";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_rgbright: cam_sensor_suspend_rgbright {
+ /* RESET REAR */
+ mux {
+ pins = "gpio109";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio109";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_rgbleft: cam_sensor_active_rgbleft {
+ /* RESET REAR */
+ mux {
+ pins = "gpio78";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio78";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_rgbleft: cam_sensor_suspend_rgbleft {
+ /* RESET REAR */
+ mux {
+ pins = "gpio78";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio78";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ bt_en_sleep: bt_en_sleep {
+ mux {
+ pins = "gpio21";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio21";
+ drive-strength = <2>;
+ output-low;
+ bias-pull-down;
+ };
+ };
+
+ ch101_rst: ch101_rst {
+ mux {
+ pins = "gpio140";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio140";
+ output-high;
+ drive-strength = <2>;
+ };
+ };
+
+ ch101_tmr_rst: ch101_tmr_rst {
+ mux {
+ pins = "gpio0";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio0";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+ };
+
+ ch101_0_irq: ch101_0_irq {
+ mux {
+ pins = "gpio129", "gpio141", "gpio113";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio129", "gpio141", "gpio113";
+ bias-no-pull;
+ drive-strength = <2>;
+ };
+ };
+
+ ch101_1_irq: ch101_1_irq {
+ mux {
+ pins = "gpio122", "gpio123", "gpio66";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio122", "gpio123", "gpio66";
+ bias-no-pull;
+ drive-strength = <2>;
+ };
+ };
+
+ /* QUPv3_0 North SE0 mappings */
+ qupv3_se0_i3c_pins: qupv3_se0_i3c_pins {
+ qupv3_se0_i3c_active: qupv3_se0_i3c_active {
+ mux {
+ pins = "gpio28", "gpio29";
+ function = "ibi_i3c";
+ };
+
+ config {
+ pins = "gpio28", "gpio29";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se0_i3c_sleep: qupv3_se0_i3c_sleep {
+ mux {
+ pins = "gpio28", "gpio29";
+ function = "ibi_i3c";
+ };
+
+ config {
+ pins = "gpio28", "gpio29";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se0_i3c_disable: qupv3_se0_i3c_disable {
+ mux {
+ pins = "gpio28", "gpio29";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio28", "gpio29";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ /* QUPv3_0 North SE1 mappings */
+ qupv3_se1_i3c_pins: qupv3_se1_i3c_pins {
+ qupv3_se1_i3c_active: qupv3_se1_i3c_active {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "ibi_i3c";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se1_i3c_sleep: qupv3_se1_i3c_sleep {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "ibi_i3c";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se1_i3c_disable: qupv3_se1_i3c_disable {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ /* SE 0 pin mappings */
+ qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
+ qupv3_se0_i2c_active: qupv3_se0_i2c_active {
+ mux {
+ pins = "gpio28", "gpio29";
+ function = "qup0";
+ };
+
+ config {
+ pins = "gpio28", "gpio29";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
+ mux {
+ pins = "gpio28", "gpio29";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio28", "gpio29";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 1 pin mappings */
+ qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
+ qupv3_se1_i2c_active: qupv3_se1_i2c_active {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "qup1";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ lt9611_pins: lt9611_pins {
+ mux {
+ pins = "gpio2", "gpio1";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio2", "gpio1";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ };
+ };
+
+ nfc {
+ nfc_int_active: nfc_int_active {
+ /* active state */
+ mux {
+ /* GPIO 111 NFC Read Interrupt */
+ pins = "gpio111";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio111";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_int_suspend: nfc_int_suspend {
+ /* sleep state */
+ mux {
+ /* GPIO 111 NFC Read Interrupt */
+ pins = "gpio111";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio111";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_enable_active: nfc_enable_active {
+ /* active state */
+ mux {
+ /* 6: Enable 110: Firmware */
+ pins = "gpio6", "gpio110";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6", "gpio110";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_enable_suspend: nfc_enable_suspend {
+ /* sleep state */
+ mux {
+ /* 6: Enable 110: Firmware */
+ pins = "gpio6", "gpio110";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6", "gpio110";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable;
+ };
+ };
+
+ nfc_clk_req_active: nfc_clk_req_active {
+ /* active state */
+ mux {
+ /* GPIO 7: NFC CLOCK REQUEST */
+ pins = "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_clk_req_suspend: nfc_clk_req_suspend {
+ /* sleep state */
+ mux {
+ /* GPIO 7: NFC CLOCK REQUEST */
+ pins = "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable;
+ };
+ };
+ };
+
+ /* SE 2 pin mappings */
+ qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
+ qupv3_se2_i2c_active: qupv3_se2_i2c_active {
+ mux {
+ pins = "gpio115", "gpio116";
+ function = "qup2";
+ };
+
+ config {
+ pins = "gpio115", "gpio116";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
+ mux {
+ pins = "gpio115", "gpio116";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio115", "gpio116";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 3 pin mappings */
+ qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
+ qupv3_se3_i2c_active: qupv3_se3_i2c_active {
+ mux {
+ pins = "gpio119", "gpio120";
+ function = "qup3";
+ };
+
+ config {
+ pins = "gpio119", "gpio120";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
+ mux {
+ pins = "gpio119", "gpio120";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio119", "gpio120";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 4 pin mappings */
+ qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
+ qupv3_se4_i2c_active: qupv3_se4_i2c_active {
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "qup4";
+ };
+
+ config {
+ pins = "gpio8", "gpio9";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8", "gpio9";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 5 pin mappings */
+ qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
+ qupv3_se5_i2c_active: qupv3_se5_i2c_active {
+ mux {
+ pins = "gpio12", "gpio13";
+ function = "qup5";
+ };
+
+ config {
+ pins = "gpio12", "gpio13";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
+ mux {
+ pins = "gpio12", "gpio13";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio12", "gpio13";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 6 pin mappings */
+ qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
+ qupv3_se6_i2c_active: qupv3_se6_i2c_active {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "qup6";
+ };
+
+ config {
+ pins = "gpio16", "gpio17";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
+ mux {
+ pins = "gpio16", "gpio17";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio16", "gpio17";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 7 pin mappings */
+ qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
+ qupv3_se7_i2c_active: qupv3_se7_i2c_active {
+ mux {
+ pins = "gpio20", "gpio21";
+ function = "qup7";
+ };
+
+ config {
+ pins = "gpio20", "gpio21";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
+ mux {
+ pins = "gpio20", "gpio21";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio20", "gpio21";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ qupv3_se0_spi_pins: qupv3_se0_spi_pins {
+ qupv3_se0_spi_active: qupv3_se0_spi_active {
+ mux {
+ pins = "gpio28", "gpio29", "gpio30",
+ "gpio31";
+ function = "qup0";
+ };
+
+ config {
+ pins = "gpio28", "gpio29", "gpio30",
+ "gpio31";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
+ mux {
+ pins = "gpio28", "gpio29", "gpio30",
+ "gpio31";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio28", "gpio29", "gpio30",
+ "gpio31";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se1_spi_pins: qupv3_se1_spi_pins {
+ qupv3_se1_spi_active: qupv3_se1_spi_active {
+ mux {
+ pins = "gpio4", "gpio5", "gpio6",
+ "gpio7";
+ function = "qup1";
+ };
+
+ config {
+ pins = "gpio4", "gpio5", "gpio6",
+ "gpio7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
+ mux {
+ pins = "gpio4", "gpio5", "gpio6",
+ "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio4", "gpio5", "gpio6",
+ "gpio7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se2_spi_pins: qupv3_se2_spi_pins {
+ qupv3_se2_spi_active: qupv3_se2_spi_active {
+ mux {
+ pins = "gpio115", "gpio116", "gpio117",
+ "gpio118";
+ function = "qup2";
+ };
+
+ config {
+ pins = "gpio115", "gpio116", "gpio117",
+ "gpio118";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
+ mux {
+ pins = "gpio115", "gpio116", "gpio117",
+ "gpio118";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio115", "gpio116", "gpio117",
+ "gpio118";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se3_spi_pins: qupv3_se3_spi_pins {
+ qupv3_se3_spi_active: qupv3_se3_spi_active {
+ mux {
+ pins = "gpio119", "gpio120", "gpio121",
+ "gpio122";
+ function = "qup3";
+ };
+
+ config {
+ pins = "gpio119", "gpio120", "gpio121",
+ "gpio122";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
+ mux {
+ pins = "gpio119", "gpio120", "gpio121",
+ "gpio122";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio119", "gpio120", "gpio121",
+ "gpio122";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se4_spi_pins: qupv3_se4_spi_pins {
+ qupv3_se4_spi_active: qupv3_se4_spi_active {
+ mux {
+ pins = "gpio8", "gpio9", "gpio10",
+ "gpio11";
+ function = "qup4";
+ };
+
+ config {
+ pins = "gpio8", "gpio9", "gpio10",
+ "gpio11";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
+ mux {
+ pins = "gpio8", "gpio9", "gpio10",
+ "gpio11";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8", "gpio9", "gpio10",
+ "gpio11";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se5_spi_pins: qupv3_se5_spi_pins {
+ qupv3_se5_spi_active: qupv3_se5_spi_active {
+ mux {
+ pins = "gpio12", "gpio13", "gpio14",
+ "gpio15";
+ function = "qup5";
+ };
+
+ config {
+ pins = "gpio12", "gpio13", "gpio14",
+ "gpio15";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
+ mux {
+ pins = "gpio12", "gpio13", "gpio14",
+ "gpio15";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio12", "13", "gpio14",
+ "gpio15";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se6_spi_pins: qupv3_se6_spi_pins {
+ qupv3_se6_spi_active: qupv3_se6_spi_active {
+ mux {
+ pins = "gpio16", "gpio17", "gpio18",
+ "gpio19";
+ function = "qup6";
+ };
+
+ config {
+ pins = "gpio16", "gpio17", "gpio18",
+ "gpio19";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
+ mux {
+ pins = "gpio16", "gpio17", "gpio18",
+ "gpio19";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio16", "gpio17", "gpio18",
+ "gpio19";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se7_spi_pins: qupv3_se7_spi_pins {
+ qupv3_se7_spi_active: qupv3_se7_spi_active {
+ mux {
+ pins = "gpio20", "gpio21", "gpio22",
+ "gpio23";
+ function = "qup7";
+ };
+
+ config {
+ pins = "gpio20", "gpio21", "gpio22",
+ "gpio23";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
+ mux {
+ pins = "gpio20", "gpio21", "gpio22",
+ "gpio23";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio20", "gpio21", "gpio22",
+ "gpio23";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ /* QUPv3_1 South_1 SE mappings */
+ /* SE 8 pin mappings */
+ qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
+ qupv3_se8_i2c_active: qupv3_se8_i2c_active {
+ mux {
+ pins = "gpio24", "gpio25";
+ function = "qup8";
+ };
+
+ config {
+ pins = "gpio24", "gpio25";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
+ mux {
+ pins = "gpio24", "gpio25";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio24", "gpio25";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 9 pin mappings */
+ qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
+ qupv3_se9_i2c_active: qupv3_se9_i2c_active {
+ mux {
+ pins = "gpio125", "gpio126";
+ function = "qup9";
+ };
+
+ config {
+ pins = "gpio125", "gpio126";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
+ mux {
+ pins = "gpio125", "gpio126";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio125", "gpio126";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 10 pin mappings */
+ qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
+ qupv3_se10_i2c_active: qupv3_se10_i2c_active {
+ mux {
+ pins = "gpio129", "gpio130";
+ function = "qup10";
+ };
+
+ config {
+ pins = "gpio129", "gpio130";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
+ mux {
+ pins = "gpio129", "gpio130";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio129", "gpio130";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 11 pin mappings */
+ qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
+ qupv3_se11_i2c_active: qupv3_se11_i2c_active {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "qup11";
+ };
+
+ config {
+ pins = "gpio60", "gpio61";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
+ mux {
+ pins = "gpio60", "gpio61";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio60", "gpio61";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 12 pin mappings */
+ qupv3_se12_i2c_pins: qupv3_se12_i2c_pins {
+ qupv3_se12_i2c_active: qupv3_se12_i2c_active {
+ mux {
+ pins = "gpio32", "gpio33";
+ function = "qup12";
+ };
+
+ config {
+ pins = "gpio32", "gpio33";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se12_i2c_sleep: qupv3_se12_i2c_sleep {
+ mux {
+ pins = "gpio32", "gpio33";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio32", "gpio33";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 13 pin mappings */
+ qupv3_se13_i2c_pins: qupv3_se13_i2c_pins {
+ qupv3_se13_i2c_active: qupv3_se13_i2c_active {
+ mux {
+ pins = "gpio36", "gpio37";
+ function = "qup13";
+ };
+
+ config {
+ pins = "gpio36", "gpio37";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se13_i2c_sleep: qupv3_se13_i2c_sleep {
+ mux {
+ pins = "gpio36", "gpio37";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio36", "gpio37";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ qupv3_se8_spi_pins: qupv3_se8_spi_pins {
+ qupv3_se8_spi_active: qupv3_se8_spi_active {
+ mux {
+ pins = "gpio24", "gpio25", "gpio26",
+ "gpio27";
+ function = "qup8";
+ };
+
+ config {
+ pins = "gpio24", "gpio25", "gpio26",
+ "gpio27";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
+ mux {
+ pins = "gpio24", "gpio25", "gpio26",
+ "gpio27";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio24", "gpio25", "gpio26",
+ "gpio27";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se9_spi_pins: qupv3_se9_spi_pins {
+ qupv3_se9_spi_active: qupv3_se9_spi_active {
+ mux {
+ pins = "gpio125", "gpio126", "gpio127",
+ "gpio128";
+ function = "qup9";
+ };
+
+ config {
+ pins = "gpio125", "gpio126", "gpio127",
+ "gpio128";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
+ mux {
+ pins = "gpio125", "gpio126", "gpio127",
+ "gpio128";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio125", "gpio126", "gpio127",
+ "gpio128";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se10_spi_pins: qupv3_se10_spi_pins {
+ qupv3_se10_spi_active: qupv3_se10_spi_active {
+ mux {
+ pins = "gpio129", "gpio130", "gpio131",
+ "gpio132";
+ function = "qup10";
+ };
+
+ config {
+ pins = "gpio129", "gpio130", "gpio131",
+ "gpio132";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
+ mux {
+ pins = "gpio129", "gpio130", "gpio131",
+ "gpio132";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio129", "gpio130", "gpio131",
+ "gpio132";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se11_spi_pins: qupv3_se11_spi_pins {
+ qupv3_se11_spi_active: qupv3_se11_spi_active {
+ mux {
+ pins = "gpio60", "gpio61", "gpio62",
+ "gpio63";
+ function = "qup11";
+ };
+
+ config {
+ pins = "gpio60", "gpio61", "gpio62",
+ "gpio63";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
+ mux {
+ pins = "gpio60", "gpio61", "gpio62",
+ "gpio63";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio60", "gpio61", "gpio62",
+ "gpio63";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se12_spi_pins: qupv3_se12_spi_pins {
+ qupv3_se12_spi_active: qupv3_se12_spi_active {
+ mux {
+ pins = "gpio32", "gpio33", "gpio34",
+ "gpio35";
+ function = "qup12";
+ };
+
+ config {
+ pins = "gpio32", "gpio33", "gpio34",
+ "gpio35";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se12_spi_sleep: qupv3_se12_spi_sleep {
+ mux {
+ pins = "gpio32", "gpio33", "gpio34",
+ "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio32", "gpio33", "gpio34",
+ "gpio35";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se13_spi_pins: qupv3_se13_spi_pins {
+ qupv3_se13_spi_active: qupv3_se13_spi_active {
+ mux {
+ pins = "gpio36", "gpio37", "gpio38",
+ "gpio39";
+ function = "qup13";
+ };
+
+ config {
+ pins = "gpio36", "gpio37", "gpio38",
+ "gpio39";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se13_spi_sleep: qupv3_se13_spi_sleep {
+ mux {
+ pins = "gpio36", "gpio37", "gpio38",
+ "gpio39";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio36", "gpio37", "gpio38",
+ "gpio39";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ /* QUPv3_2 South_2 SE mappings */
+ /* SE 14 pin mappings */
+ qupv3_se14_i2c_pins: qupv3_se14_i2c_pins {
+ qupv3_se14_i2c_active: qupv3_se14_i2c_active {
+ mux {
+ pins = "gpio40", "gpio41";
+ function = "qup14";
+ };
+
+ config {
+ pins = "gpio40", "gpio41";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se14_i2c_sleep: qupv3_se14_i2c_sleep {
+ mux {
+ pins = "gpio40", "gpio41";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio40", "gpio41";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 15 pin mappings */
+ qupv3_se15_i2c_pins: qupv3_se15_i2c_pins {
+ qupv3_se15_i2c_active: qupv3_se15_i2c_active {
+ mux {
+ pins = "gpio44", "gpio45";
+ function = "qup15";
+ };
+
+ config {
+ pins = "gpio44", "gpio45";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se15_i2c_sleep: qupv3_se15_i2c_sleep {
+ mux {
+ pins = "gpio44", "gpio45";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio44", "gpio45";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 16 pin mappings */
+ qupv3_se16_i2c_pins: qupv3_se16_i2c_pins {
+ qupv3_se16_i2c_active: qupv3_se16_i2c_active {
+ mux {
+ pins = "gpio48", "gpio49";
+ function = "qup16";
+ };
+
+ config {
+ pins = "gpio48", "gpio49";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se16_i2c_sleep: qupv3_se16_i2c_sleep {
+ mux {
+ pins = "gpio48", "gpio49";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio48", "gpio49";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 17 pin mappings */
+ qupv3_se17_i2c_pins: qupv3_se17_i2c_pins {
+ qupv3_se17_i2c_active: qupv3_se17_i2c_active {
+ mux {
+ pins = "gpio52", "gpio53";
+ function = "qup17";
+ };
+
+ config {
+ pins = "gpio52", "gpio53";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se17_i2c_sleep: qupv3_se17_i2c_sleep {
+ mux {
+ pins = "gpio52", "gpio53";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio52", "gpio53";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 18 pin mappings */
+ qupv3_se18_i2c_pins: qupv3_se18_i2c_pins {
+ qupv3_se18_i2c_active: qupv3_se18_i2c_active {
+ mux {
+ pins = "gpio56", "gpio57";
+ function = "qup18";
+ };
+
+ config {
+ pins = "gpio56", "gpio57";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se18_i2c_sleep: qupv3_se18_i2c_sleep {
+ mux {
+ pins = "gpio56", "gpio57";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio56", "gpio57";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 19 pin mappings */
+ qupv3_se19_i2c_pins: qupv3_se19_i2c_pins {
+ qupv3_se19_i2c_active: qupv3_se19_i2c_active {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "qup19";
+ };
+
+ config {
+ pins = "gpio0", "gpio1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se19_i2c_sleep: qupv3_se19_i2c_sleep {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio0", "gpio1";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ qupv3_se14_spi_pins: qupv3_se14_spi_pins {
+ qupv3_se14_spi_active: qupv3_se14_spi_active {
+ mux {
+ pins = "gpio40", "gpio41", "gpio42",
+ "gpio43";
+ function = "qup14";
+ };
+
+ config {
+ pins = "gpio40", "gpio41", "gpio42",
+ "gpio43";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se14_spi_sleep: qupv3_se14_spi_sleep {
+ mux {
+ pins = "gpio40", "gpio41", "gpio42",
+ "gpio43";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio40", "gpio41", "gpio42",
+ "gpio43";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se15_spi_pins: qupv3_se15_spi_pins {
+ qupv3_se15_spi_active: qupv3_se15_spi_active {
+ mux {
+ pins = "gpio44", "gpio45", "gpio46",
+ "gpio47";
+ function = "qup15";
+ };
+
+ config {
+ pins = "gpio44", "gpio45", "gpio46",
+ "gpio47";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se15_spi_sleep: qupv3_se15_spi_sleep {
+ mux {
+ pins = "gpio44", "gpio45", "gpio46",
+ "gpio47";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio44", "gpio45", "gpio46",
+ "gpio47";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se16_spi_pins: qupv3_se16_spi_pins {
+ qupv3_se16_spi_active: qupv3_se16_spi_active {
+ mux {
+ pins = "gpio48", "gpio49", "gpio50",
+ "gpio51";
+ function = "qup16";
+ };
+
+ config {
+ pins = "gpio48", "gpio49", "gpio50",
+ "gpio51";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se16_spi_sleep: qupv3_se16_spi_sleep {
+ mux {
+ pins = "gpio48", "gpio49", "gpio50",
+ "gpio51";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio48", "gpio49", "gpio50",
+ "gpio51";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se17_spi_pins: qupv3_se17_spi_pins {
+ qupv3_se17_spi_active: qupv3_se17_spi_active {
+ mux {
+ pins = "gpio52", "gpio53", "gpio54",
+ "gpio55";
+ function = "qup17";
+ };
+
+ config {
+ pins = "gpio52", "gpio53", "gpio54",
+ "gpio55";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se17_spi_sleep: qupv3_se17_spi_sleep {
+ mux {
+ pins = "gpio52", "gpio53", "gpio54",
+ "gpio55";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio52", "gpio53", "gpio54",
+ "gpio55";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se18_spi_pins: qupv3_se18_spi_pins {
+ qupv3_se18_spi_active: qupv3_se18_spi_active {
+ mux {
+ pins = "gpio56", "gpio57", "gpio58",
+ "gpio59";
+ function = "qup18";
+ };
+
+ config {
+ pins = "gpio56", "gpio57", "gpio58",
+ "gpio59";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se18_spi_sleep: qupv3_se18_spi_sleep {
+ mux {
+ pins = "gpio56", "gpio57", "gpio58",
+ "gpio59";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio56", "gpio57", "gpio58",
+ "gpio59";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se19_spi_pins: qupv3_se19_spi_pins {
+ qupv3_se19_spi_active: qupv3_se19_spi_active {
+ mux {
+ pins = "gpio0", "gpio1", "gpio2",
+ "gpio3";
+ function = "qup19";
+ };
+
+ config {
+ pins = "gpio0", "gpio1", "gpio2",
+ "gpio3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se19_spi_sleep: qupv3_se19_spi_sleep {
+ mux {
+ pins = "gpio0", "gpio1", "gpio2",
+ "gpio3";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio0", "gpio1", "gpio2",
+ "gpio3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ usb2_id_det_default: usb2_id_det_default {
+ config {
+ pins = "gpio91";
+ function = "gpio";
+ input-enable;
+ bias-pull-up;
+ };
+ };
+
+ wil6210_refclk_en_pin: wil6210_refclk_en_pin {
+ mux {
+ pins = "gpio14";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio14";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-pm.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-pm.dtsi
new file mode 100755
index 0000000..a5eba34
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-pm.dtsi
@@ -0,0 +1,118 @@
+&soc {
+ qcom,lpm-levels {
+ compatible = "qcom,lpm-levels";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,pm-cluster@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "L3";
+ qcom,clstr-tmr-add = <1000>;
+ qcom,psci-mode-shift = <4>;
+ qcom,psci-mode-mask = <0xfff>;
+
+ qcom,pm-cluster-level@0 { /* D1 */
+ reg = <0>;
+ label = "l3-wfi";
+ qcom,psci-mode = <0x1>;
+ qcom,entry-latency-us = <48>;
+ qcom,exit-latency-us = <51>;
+ qcom,min-residency-us = <99>;
+ };
+
+ qcom,pm-cluster-level@1 { /* LLCC off, AOSS sleep */
+ reg = <1>;
+ label = "llcc-off";
+ qcom,psci-mode = <0xC24>;
+ qcom,entry-latency-us = <3263>;
+ qcom,exit-latency-us = <6562>;
+ qcom,min-residency-us = <9987>;
+ qcom,min-child-idx = <1>;
+ qcom,is-reset;
+ qcom,notify-rpm;
+ };
+
+ qcom,pm-cpu@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+ qcom,ref-stddev = <500>;
+ qcom,tmr-add = <1000>;
+ qcom,ref-premature-cnt = <1>;
+ qcom,disable-ipi-prediction;
+ qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ qcom,pm-cpu-level@0 { /* C1 */
+ reg = <0>;
+ label = "wfi";
+ qcom,psci-cpu-mode = <0x1>;
+ qcom,entry-latency-us = <57>;
+ qcom,exit-latency-us = <43>;
+ qcom,min-residency-us = <100>;
+ };
+
+ qcom,pm-cpu-level@1 { /* C4 */
+ reg = <1>;
+ label = "rail-pc";
+ qcom,psci-cpu-mode = <0x4>;
+ qcom,entry-latency-us = <360>;
+ qcom,exit-latency-us = <531>;
+ qcom,min-residency-us = <3934>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+ };
+
+ qcom,pm-cpu@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+ qcom,disable-ipi-prediction;
+ qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>;
+
+ qcom,pm-cpu-level@2 { /* C1 */
+ reg = <2>;
+ label = "wfi";
+ qcom,psci-cpu-mode = <0x1>;
+ qcom,entry-latency-us = <57>;
+ qcom,exit-latency-us = <43>;
+ qcom,min-residency-us = <83>;
+ };
+
+ qcom,pm-cpu-level@3 { /* C4 */
+ reg = <3>;
+ label = "rail-pc";
+ qcom,psci-cpu-mode = <0x4>;
+ qcom,entry-latency-us = <702>;
+ qcom,exit-latency-us = <1061>;
+ qcom,min-residency-us = <4488>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+ };
+ };
+ };
+
+ qcom,rpm-stats@c3f0004 {
+ compatible = "qcom,rpm-stats";
+ reg = <0xc300000 0x1000>, <0xc3f0004 0x4>;
+ reg-names = "phys_addr_base", "offset_addr";
+ qcom,num-records = <3>;
+ };
+
+ qcom,ddr-stats@c3f0000 {
+ compatible = "qcom,ddr-stats";
+ reg = <0xc300000 0x1000>, <0xc3f001c 0x4>;
+ reg-names = "phys_addr_base", "offset_addr";
+ };
+
+ qcom,rpmh-master-stats@b221200 {
+ compatible = "qcom,rpmh-master-stats-v1";
+ reg = <0xb221200 0x60>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-pmic-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-pmic-overlay.dtsi
new file mode 100755
index 0000000..37658de
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-pmic-overlay.dtsi
@@ -0,0 +1,217 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+#include "pm8150.dtsi"
+#include "pm8150b.dtsi"
+#include "pm8150l.dtsi"
+#include "pm8009.dtsi"
+
+&spmi_bus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ qcom,pmxprairie@8 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x8 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ qcom,modem-reset;
+ };
+ };
+
+ qcom,pmxprairie@9 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x9 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+};
+
+&pm8150_gpios {
+ key_home {
+ key_home_default: key_home_default {
+ pins = "gpio1";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+ };
+
+ imu_clkin {
+ imu_clkin_default: imu_clkin_default {
+ pins = "gpio3";
+ function = "func1";
+ output-low;
+ power-source = <0>;
+ bias-disable;
+ qcom,dtest-buffer = <1>;
+ qcom,drive-strength = <1>;
+ };
+
+ imu_clkin_sleep: imu_clkin_sleep {
+ pins = "gpio3";
+ function = "func1";
+ input-enable;
+ bias-pull-down;
+ power-source = <0>;
+ qcom,dtest-buffer = <1>;
+ qcom,drive-strength = <1>;
+ };
+ };
+
+ key_vol_up {
+ key_vol_up_default: key_vol_up_default {
+ pins = "gpio6";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <1>;
+ };
+ };
+
+ key_confirm {
+ key_confirm_default: key_confirm_default {
+ pins = "gpio7";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+ };
+
+ usb2_vbus_boost {
+ usb2_vbus_boost_default: usb2_vbus_boost_default {
+ pins = "gpio9";
+ function = "normal";
+ output-low;
+ power-source = <1>; /* 1.8V input supply */
+ };
+ };
+
+ usb2_vbus_det {
+ usb2_vbus_det_default: usb2_vbus_det_default {
+ pins = "gpio10";
+ function = "normal";
+ input-enable;
+ bias-pull-down;
+ power-source = <1>; /* 1.8V input supply */
+ };
+ };
+};
+
+&pm8150b_gpios {
+ qnovo_fet_ctrl {
+ qnovo_fet_ctrl_state1: qnovo_fet_ctrl_state1 {
+ pins = "gpio8";
+ function = "normal";
+ input-enable;
+ output-disable;
+ bias-disable;
+ power-source = <0>;
+ };
+
+ qnovo_fet_ctrl_state2: qnovo_fet_ctrl_state2 {
+ pins = "gpio8";
+ function = "normal";
+ input-enable;
+ output-disable;
+ bias-pull-down;
+ power-source = <0>;
+ };
+ };
+
+ smb_stat {
+ smb_stat_default: smb_stat_default {
+ pins = "gpio6";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+ power-source = <0>;
+ };
+ };
+};
+
+&pm8150b_qnovo {
+ pinctrl-names = "q_state1", "q_state2";
+ pinctrl-0 = <&qnovo_fet_ctrl_state1>;
+ pinctrl-1 = <&qnovo_fet_ctrl_state2>;
+};
+
+&pm8150b_fg {
+ nvmem-names = "fg_sdam";
+ nvmem = <&pm8150_sdam_2>;
+};
+
+&pm8150b_charger {
+ dpdm-supply = <&usb2_phy0>;
+ smb5_vconn: qcom,smb5-vconn {
+ regulator-name = "smb5-vconn";
+ };
+
+ smb5_vbus: qcom,smb5-vbus {
+ regulator-name = "smb5-vbus";
+ };
+};
+
+&pm8150b_pdphy {
+ vdd-pdphy-supply = <&pm8150_l2>;
+ vbus-supply = <&smb5_vbus>;
+ vconn-supply = <&smb5_vconn>;
+};
+
+&pm8150b_gpios {
+ haptics_boost {
+ haptics_boost_default: haptics_boost_default {
+ pins = "gpio5";
+ function = "normal";
+ output-enable;
+ input-disable;
+ bias-disable;
+ qcom,drive-strength = <3>; /* high */
+ power-source = <1>; /* 1.8 V */
+ };
+ };
+};
+
+&soc {
+ vreg_tof: regulator-dbb1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_tof";
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+ gpio = <&pm8009_gpios 1 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <1000>;
+ enable-active-high;
+ };
+
+ vreg_hap_boost: regulator-haptics-boost {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_hap_boost";
+ gpio = <&pm8150b_gpios 5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&haptics_boost_default>;
+ startup-delay-us = <1000>;
+ enable-active-high;
+ status = "disabled";
+ };
+};
+
+&usb0 {
+ extcon = <&pm8150b_pdphy>, <&eud>;
+};
+
+&usb_qmp_dp_phy {
+ extcon = <&pm8150b_pdphy>;
+};
+
+&sde_dp {
+ extcon = <&pm8150b_pdphy>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-qrd-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/kona-qrd-overlay.dts
new file mode 100755
index 0000000..68b9dca
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-qrd-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-kona.h>
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "kona-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona QRD";
+ compatible = "qcom,kona-qrd", "qcom,kona", "qcom,qrd";
+ qcom,board-id = <11 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/kona-qrd.dts
new file mode 100755
index 0000000..cc9a4a6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-qrd.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona.dtsi"
+#include "kona-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona QRD";
+ compatible = "qcom,kona-qrd", "qcom,kona", "qcom,qrd";
+ qcom,board-id = <11 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-qrd.dtsi
new file mode 100755
index 0000000..b6c38d6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-qrd.dtsi
@@ -0,0 +1,1016 @@
+#include <dt-bindings/gpio/gpio.h>
+#include "kona-pmic-overlay.dtsi"
+#include "kona-sde-display.dtsi"
+#include "camera/kona-camera-sensor-qrd.dtsi"
+#include "kona-audio-overlay.dtsi"
+#include "kona-thermal-overlay.dtsi"
+
+&vendor {
+ kona_qrd_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "fg-gen4-batterydata-mlp466274-3650mah.dtsi"
+ #include "fg-gen4-batterydata-atl466274-3650mah.dtsi"
+ };
+};
+
+&qupv3_se12_2uart {
+ status = "okay";
+};
+
+&pm8150a_amoled {
+ status = "ok";
+};
+
+&qupv3_se6_4uart {
+ status = "ok";
+};
+
+&dai_mi2s2 {
+ qcom,msm-mi2s-tx-lines = <1>;
+};
+
+&q6core {
+ cdc_tert_mi2s_gpios: msm_cdc_pinctrl_tert {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
+ &tert_mi2s_sd0_active>;
+ pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
+ &tert_mi2s_sd0_sleep>;
+ };
+};
+
+&kona_snd {
+ qcom,model = "kona-qrd-snd-card";
+ qcom,audio-routing =
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "TX DMIC0", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic0",
+ "TX DMIC1", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic1",
+ "TX DMIC2", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "TX DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "TX DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT";
+ qcom,wsa-max-devs = <1>;
+ qcom,wsa-devs = <&wsa881x_0212>, <&wsa881x_0214>;
+ qcom,wsa-aux-dev-prefix = "SpkrRight", "SpkrRight";
+
+ qcom,msm-mbhc-usbc-audio-supported = <1>;
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+
+ qcom,tert-mi2s-gpios = <&cdc_tert_mi2s_gpios>;
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ qcom,clk-freq-out = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 111 0x00>;
+ qcom,nq-ven = <&tlmm 6 0x00>;
+ qcom,nq-firm = <&tlmm 110 0x00>;
+ qcom,nq-clkreq = <&tlmm 7 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <111 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&qupv3_se13_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "ok";
+ qcom,i2c-touch-active = "st,fts";
+
+ st_fts@49 {
+ compatible = "st,fts";
+ reg = <0x49>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <39 0x2008>;
+ vdd-supply = <&pm8150a_l1>;
+ avdd-supply = <&pm8150_l13>;
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ st,irq-gpio = <&tlmm 39 0x2008>;
+ st,reset-gpio = <&tlmm 38 0x00>;
+ st,regulator_dvdd = "vdd";
+ st,regulator_avdd = "avdd";
+ panel = <&dsi_sw43404_amoled_cmd &dsi_sw43404_amoled_video
+ &dsi_sw43404_amoled_fhd_plus_cmd>;
+ };
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v4";
+
+ vdda-phy-supply = <&pm8150_l5>;
+ vdda-phy-always-on;
+ vdda-pll-supply = <&pm8150_l9>;
+ vdda-phy-max-microamp = <89900>;
+ vdda-pll-max-microamp = <18800>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm8150_l17>;
+ vcc-voltage-level = <2504000 2950000>;
+ vcc-low-voltage-sup;
+ vccq-supply = <&pm8150_l6>;
+ vccq2-supply = <&pm8150_s4>;
+ vcc-max-microamp = <800000>;
+ vccq-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+
+ qcom,vddp-ref-clk-supply = <&pm8150_l6>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vccq-parent-supply = <&pm8150a_s8>;
+ qcom,vccq-parent-max-microamp = <210000>;
+
+ status = "ok";
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+
+ qcom,qbt_handler {
+ compatible = "qcom,qbt-handler";
+ qcom,ipc-gpio = <&tlmm 23 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_home_default>;
+ qcom,finger-detect-gpio = <&pm8150_gpios 1 0>;
+ };
+};
+
+&vreg_hap_boost {
+ status = "ok";
+};
+
+&pm8150b_haptics {
+ qcom,vmax-mv = <1697>;
+ qcom,play-rate-us = <5882>;
+ vdd-supply = <&vreg_hap_boost>;
+
+ wf_0 {
+ /* CLICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_1 {
+ /* DOUBLE CLICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_2 {
+ /* TICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_3 {
+ /* THUD */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_4 {
+ /* POP */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_5 {
+ /* HEAVY CLICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+};
+
+&pm8150b_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "conn_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ chg_sbux@99 {
+ reg = <ADC_SBUx>;
+ label = "chg_sbux";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ mid_chg_div6@1e {
+ reg = <ADC_MID_CHG_DIV6>;
+ label = "chg_mid";
+ qcom,pre-scaling = <1 6>;
+ };
+
+ usb_in_i_uv@7 {
+ reg = <ADC_USB_IN_I>;
+ label = "usb_in_i_uv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ usb_in_v_div_16@8 {
+ reg = <ADC_USB_IN_V_16>;
+ label = "usb_in_v_div_16";
+ qcom,pre-scaling = <1 16>;
+ };
+};
+
+&qupv3_se15_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "ok";
+ redriver: redriver@1c {
+ compatible = "onnn,redriver";
+ reg = <0x1c>;
+ extcon = <&pm8150b_pdphy>, <&pm8150b_pdphy>;
+ eq = /bits/ 8 <
+ /* Parameters for USB */
+ 0x4 0x4 0x4 0x4
+ /* Parameters for DP */
+ 0x6 0x4 0x4 0x6>;
+ flat-gain = /bits/ 8 <
+ /* Parameters for USB */
+ 0x3 0x1 0x1 0x3
+ /* Parameters for DP */
+ 0x2 0x1 0x1 0x2>;
+ output-comp = /bits/ 8 <
+ /* Parameters for USB */
+ 0x3 0x3 0x3 0x3
+ /* Parameters for DP */
+ 0x3 0x3 0x3 0x3>;
+ loss-match = /bits/ 8 <
+ /* Parameters for USB */
+ 0x1 0x3 0x3 0x1
+ /* Parameters for DP */
+ 0x3 0x3 0x3 0x3>;
+ };
+
+
+ #include "smb1390.dtsi"
+};
+
+&smb1390 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_stat_default>;
+ status = "ok";
+};
+
+&smb1390_charger {
+ io-channels = <&pm8150b_vadc ADC_AMUX_THM2>;
+ io-channel-names = "cp_die_temp";
+ qcom,parallel-output-mode = <2>;
+ qcom,min-ilim-ua = <750000>;
+ qcom,parallel-input-mode = <1>;
+ status = "ok";
+};
+
+&smb1390_slave {
+ status = "ok";
+};
+
+&smb1390_slave_charger {
+ status = "ok";
+};
+
+&pm8150b_charger {
+ status = "ok";
+ qcom,sec-charger-config = <1>;
+ qcom,auto-recharge-soc = <98>;
+ io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>,
+ <&pm8150b_vadc ADC_USB_IN_I>,
+ <&pm8150b_vadc ADC_SBUx>,
+ <&pm8150b_vadc ADC_VPH_PWR>,
+ <&pm8150b_vadc ADC_CHG_TEMP>;
+ io-channel-names = "mid_voltage",
+ "usb_in_current",
+ "sbux_res",
+ "vph_voltage",
+ "chg_temp";
+ qcom,battery-data = <&kona_qrd_batterydata>;
+ qcom,sw-jeita-enable;
+ qcom,wd-bark-time-secs = <16>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,fcc-stepping-enable;
+ qcom,smb-internal-pull-kohm = <0>;
+ qcom,thermal-mitigation = <5325000 4500000 4000000 3500000 3000000
+ 2500000 2000000 1500000 1000000 500000>;
+};
+
+&pm8150b_fg {
+ status = "ok";
+ qcom,battery-data = <&kona_qrd_batterydata>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,five-pin-battery;
+ qcom,cl-wt-enable;
+ qcom,soc-scale-mode-en;
+ /* ESR fast calibration */
+ qcom,fg-esr-timer-chg-fast = <0 7>;
+ qcom,fg-esr-timer-dischg-fast = <0 7>;
+ qcom,fg-esr-timer-chg-slow = <0 96>;
+ qcom,fg-esr-timer-dischg-slow = <0 96>;
+ qcom,fg-esr-cal-soc-thresh = <26 230>;
+ qcom,fg-esr-cal-temp-thresh = <10 40>;
+};
+
+&pm8150_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vcoin@85 {
+ reg = <ADC_VCOIN>;
+ label = "vcoin";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ xo_therm@4c {
+ reg = <ADC_XO_THERM_PU2>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "pa_therm1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150l_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ camera_flash_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "camera_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_msm_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "skin_msm_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm2@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "pa_therm2";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150b_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ io-channels = <&pm8150b_vadc ADC_AMUX_THM3_PU2>;
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ io-channels = <&pm8150_vadc ADC_XO_THERM_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM1_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM2_PU2>;
+
+ xo_therm@4c {
+ reg = <ADC_XO_THERM_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150l_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera_flash_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ skin_msm_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm2@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&spmi_debug_bus {
+ status = "ok";
+};
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
+};
+
+&thermal_zones {
+ conn-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-msm-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ active-config1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpu-skin-avg-step {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-governor = "step_wise";
+ trips {
+ virt_trip: virt-trip {
+ temperature = <64600>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ gpu_cdev {
+ trip = <&virt_trip>;
+ cooling-device = <&msm_gpu 0 1>;
+ };
+ };
+ };
+
+ skin-msm-therm-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ skin_trip: skin-config0 {
+ temperature = <46000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ lcd_cdev {
+ trip = <&skin_trip>;
+ cooling-device = <&mdss_mdp 153 153>;
+ };
+ };
+ };
+
+ xo-therm-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>;
+
+ trips {
+ xo_lvl0: active-config0 {
+ temperature = <42000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ xo_lvl1: active-config1 {
+ temperature = <46000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ xo_lvl2: active-config2 {
+ temperature = <56000>;
+ hysteresis = <6000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ xo_skin_lvl0 {
+ trip = <&xo_lvl0>;
+ cooling-device = <&modem_mmw_skin2 1 1>;
+ };
+
+ xo_skin_lvl1 {
+ trip = <&xo_lvl1>;
+ cooling-device = <&modem_mmw_skin2 2 2>;
+ };
+
+ xo_skin_lvl2 {
+ trip = <&xo_lvl2>;
+ cooling-device = <&modem_mmw_skin2 3 3>;
+ };
+ };
+ };
+
+ mmw-pa1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>;
+
+ trips {
+ pa1_lvl0: active-config0 {
+ temperature = <44000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ pa1_lvl1: active-config1 {
+ temperature = <48000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ pa1_lvl2: active-config2 {
+ temperature = <56000>;
+ hysteresis = <6000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ pa1_skin_lvl0 {
+ trip = <&pa1_lvl0>;
+ cooling-device = <&modem_mmw_skin0 1 1>;
+ };
+
+ pa1_skin_lvl1 {
+ trip = <&pa1_lvl1>;
+ cooling-device = <&modem_mmw_skin0 2 2>;
+ };
+
+ pa1_skin_lvl2 {
+ trip = <&pa1_lvl2>;
+ cooling-device = <&modem_mmw_skin0 3 3>;
+ };
+ };
+ };
+
+ mmw-pa2-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>;
+
+ trips {
+ pa2_lvl0: active-config0 {
+ temperature = <42000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ pa2_lvl1: active-config1 {
+ temperature = <46000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ pa2_lvl2: active-config2 {
+ temperature = <56000>;
+ hysteresis = <6000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ pa2_skin_lvl0 {
+ trip = <&pa2_lvl0>;
+ cooling-device = <&modem_mmw_skin1 1 1>;
+ };
+
+ pa2_skin_lvl1 {
+ trip = <&pa2_lvl1>;
+ cooling-device = <&modem_mmw_skin1 2 2>;
+ };
+
+ pa2_skin_lvl2 {
+ trip = <&pa2_lvl2>;
+ cooling-device = <&modem_mmw_skin1 3 3>;
+ };
+ };
+ };
+
+ skin-therm-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ disable-thermal-zone;
+
+ trips {
+ skin_therm0: active-config0 {
+ temperature = <62000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ skin_therm1: active-config1 {
+ temperature = <65000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ skin_therm2: active-config2 {
+ temperature = <72000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ skin_lvl0 {
+ trip = <&skin_therm0>;
+ cooling-device = <&modem_skin 1 1>;
+ };
+
+ skin_lvl1 {
+ trip = <&skin_therm1>;
+ cooling-device = <&modem_skin 2 2>;
+ };
+
+ skin_lvl2 {
+ trip = <&skin_therm2>;
+ cooling-device = <&modem_skin 3 3>;
+ };
+ };
+
+ };
+};
+
+&sdhc_2 {
+ vdd-supply = <&pm8150a_l9>;
+ qcom,vdd-voltage-level = <2950000 2960000>;
+ qcom,vdd-current-level = <200 800000>;
+
+ vdd-io-supply = <&pm8150a_l6>;
+ qcom,vdd-io-voltage-level = <1808000 2960000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>;
+
+ cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&vendor {
+ bluetooth: bt_qca6390 {
+ compatible = "qca,qca6390";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en_sleep>;
+ qca,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */
+ qca,bt-sw-ctrl-gpio = <&tlmm 124 0>; /* SW_CTRL */
+ qca,bt-vdd-aon-supply = <&pm8150_s6>;
+ qca,bt-vdd-dig-supply = <&pm8009_s2>;
+ qca,bt-vdd-rfa1-supply = <&pm8150_s5>;
+ qca,bt-vdd-rfa2-supply = <&pm8150a_s8>;
+ qca,bt-vdd-asd-supply = <&pm8150_l16>;
+
+ qca,bt-vdd-aon-voltage-level = <950000 950000>;
+ qca,bt-vdd-dig-voltage-level = <950000 952000>;
+ qca,bt-vdd-rfa1-voltage-level = <1900000 1900000>;
+ qca,bt-vdd-rfa2-voltage-level = <1350000 1350000>;
+ qca,bt-vdd-asd-voltage-level = <3024000 3304000>;
+
+ qca,bt-vdd-asd-current-level = <10000>;
+ };
+};
+
+&usb0 {
+ dwc3@a600000 {
+ maximum-speed = "super-speed-plus";
+ };
+};
+
+&usb1 {
+ qcom,default-mode-none;
+};
+
+&wil6210 {
+ status = "ok";
+};
+
+&usb2_phy0 {
+ qcom,param-override-seq =
+ <0xc7 0x6c
+ 0x0f 0x70
+ 0x03 0x74>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-qupv3.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-qupv3.dtsi
new file mode 100755
index 0000000..2b30fff
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-qupv3.dtsi
@@ -0,0 +1,1073 @@
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ /* QUPv3_0 wrapper instance : North QUP*/
+ qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
+ compatible = "qcom,qupv3-geni-se";
+ reg = <0x9c0000 0x2000>;
+ qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_0>;
+ qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ iommus = <&apps_smmu 0x5a3 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+ qcom,iommu-dma = "fastmap";
+ };
+
+ /* QUPV3_0_SE0 */
+ i3c0: i3c-master@980000 {
+ compatible = "qcom,geni-i3c";
+ reg = <0x980000 0x4000>,
+ <0x0EC30000 0x10000>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep", "disable";
+ pinctrl-0 = <&qupv3_se0_i3c_active>;
+ pinctrl-1 = <&qupv3_se0_i3c_sleep>;
+ pinctrl-2 = <&qupv3_se0_i3c_disable>;
+ interrupts-extended = <&intc GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 31 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <3>;
+ #size-cells = <0>;
+ qcom,wrapper-core = <&qupv3_0>;
+ qcom,ibi-ctrl-id = <0>;
+ status = "disabled";
+ };
+
+ /* QUPV3_0_SE1 */
+ i3c1: i3c-master@984000 {
+ compatible = "qcom,geni-i3c";
+ reg = <0x984000 0x4000>,
+ <0xEC40000 0x10000>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep", "disable";
+ pinctrl-0 = <&qupv3_se1_i3c_active>;
+ pinctrl-1 = <&qupv3_se1_i3c_sleep>;
+ pinctrl-2 = <&qupv3_se1_i3c_disable>;
+ interrupts-extended = <&intc GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 33 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 32 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <3>;
+ #size-cells = <0>;
+ qcom,wrapper-core = <&qupv3_0>;
+ qcom,ibi-ctrl-id = <1>;
+ status = "disabled";
+ };
+
+ /* Debug UART Instance for RUMI platform */
+ qupv3_se2_2uart: qcom,qup_uart@988000 {
+ compatible = "qcom,msm-geni-console";
+ reg = <0x988000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se2_2uart_active>;
+ pinctrl-1 = <&qupv3_se2_2uart_sleep>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,wrapper-core = <&qupv3_0>;
+ qcom,change-sampling-rate;
+ status = "disabled";
+ };
+
+ /*
+ * HS UART instances. HS UART usecases can be supported on these
+ * instances only.
+ */
+ qupv3_se6_4uart: qcom,qup_uart@998000 {
+ compatible = "qcom,msm-geni-serial-hs";
+ reg = <0x998000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "active", "sleep";
+ pinctrl-0 = <&qupv3_se6_default_cts>,
+ <&qupv3_se6_default_rtsrx>, <&qupv3_se6_default_tx>;
+ pinctrl-1 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
+ <&qupv3_se6_tx>;
+ pinctrl-2 = <&qupv3_se6_ctsrx>, <&qupv3_se6_rts>,
+ <&qupv3_se6_tx>;
+ interrupts-extended = <&intc GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 19 0>;
+ status = "disabled";
+ qcom,wakeup-byte = <0xFD>;
+ qcom,wrapper-core = <&qupv3_0>;
+ };
+
+ /* I2C */
+ qupv3_se0_i2c: i2c@980000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x980000 0x4000>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 0 3 64 0>,
+ <&gpi_dma0 1 0 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se0_i2c_active>;
+ pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se1_i2c: i2c@984000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x984000 0x4000>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 1 3 64 0>,
+ <&gpi_dma0 1 1 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se1_i2c_active>;
+ pinctrl-1 = <&qupv3_se1_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se2_i2c: i2c@988000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x988000 0x4000>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 2 3 64 0>,
+ <&gpi_dma0 1 2 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se2_i2c_active>;
+ pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se3_i2c: i2c@98c000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x98c000 0x4000>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 3 3 64 0>,
+ <&gpi_dma0 1 3 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se3_i2c_active>;
+ pinctrl-1 = <&qupv3_se3_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se4_i2c: i2c@990000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x990000 0x4000>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 4 3 64 0>,
+ <&gpi_dma0 1 4 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se4_i2c_active>;
+ pinctrl-1 = <&qupv3_se4_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se5_i2c: i2c@994000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x994000 0x4000>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 5 3 64 0>,
+ <&gpi_dma0 1 5 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se5_i2c_active>;
+ pinctrl-1 = <&qupv3_se5_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se6_i2c: i2c@998000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x998000 0x4000>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 6 3 64 0>,
+ <&gpi_dma0 1 6 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se6_i2c_active>;
+ pinctrl-1 = <&qupv3_se6_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se7_i2c: i2c@99c000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x99c000 0x4000>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 7 3 64 0>,
+ <&gpi_dma0 1 7 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se7_i2c_active>;
+ pinctrl-1 = <&qupv3_se7_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ /* SPI */
+ qupv3_se0_spi: spi@980000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x980000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se0_spi_active>;
+ pinctrl-1 = <&qupv3_se0_spi_sleep>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 0 1 64 0>,
+ <&gpi_dma0 1 0 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se1_spi: spi@984000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x984000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se1_spi_active>;
+ pinctrl-1 = <&qupv3_se1_spi_sleep>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 1 1 64 0>,
+ <&gpi_dma0 1 1 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se2_spi: spi@988000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x988000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se2_spi_active>;
+ pinctrl-1 = <&qupv3_se2_spi_sleep>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 2 1 64 0>,
+ <&gpi_dma0 1 2 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se3_spi: spi@98c000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x98c000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se3_spi_active>;
+ pinctrl-1 = <&qupv3_se3_spi_sleep>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 3 1 64 0>,
+ <&gpi_dma0 1 3 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se4_spi: spi@990000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x990000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se4_spi_active>;
+ pinctrl-1 = <&qupv3_se4_spi_sleep>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 4 1 64 0>,
+ <&gpi_dma0 1 4 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se5_spi: spi@994000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x994000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se5_spi_active>;
+ pinctrl-1 = <&qupv3_se5_spi_sleep>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 5 1 64 0>,
+ <&gpi_dma0 1 5 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se6_spi: spi@998000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x998000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se6_spi_active>;
+ pinctrl-1 = <&qupv3_se6_spi_sleep>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 6 1 64 0>,
+ <&gpi_dma0 1 6 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se7_spi: spi@99c000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x99c000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se7_spi_active>;
+ pinctrl-1 = <&qupv3_se7_spi_sleep>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 7 1 64 0>,
+ <&gpi_dma0 1 7 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ /* QUPv3 South_1 & South_2 Instances
+ * South_1 0 : SE 8
+ * South_1 1 : SE 9
+ * South_1 2 : SE 10
+ * South_1 3 : SE 11
+ * South_1 4 : SE 12
+ * South_1 5 : SE 13
+ * South_2 0 : SE 14
+ * South_2 1 : SE 15
+ * South_2 2 : SE 16
+ * South_2 3 : SE 17
+ * South_2 4 : SE 18
+ * South_2 5 : SE 19
+ */
+
+ /* QUPv3_1 wrapper instance : South_1 QUP */
+ qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
+ compatible = "qcom,qupv3-geni-se";
+ reg = <0xac0000 0x2000>;
+ qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_1>;
+ qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ iommus = <&apps_smmu 0x43 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+ qcom,iommu-dma = "fastmap";
+ };
+
+ /* Debug UART Instance for CDP/MTP platform */
+ qupv3_se12_2uart: qcom,qup_uart@a90000 {
+ compatible = "qcom,msm-geni-console";
+ reg = <0xa90000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se12_2uart_active>;
+ pinctrl-1 = <&qupv3_se12_2uart_sleep>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,wrapper-core = <&qupv3_1>;
+ qcom,change-sampling-rate;
+ status = "disabled";
+ };
+ qupv3_se13_4uart: qcom,qup_uart@a94000 {
+ compatible = "qcom,msm-geni-serial-hs";
+ reg = <0xa94000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "active", "sleep";
+ pinctrl-0 = <&qupv3_se13_default_cts>,
+ <&qupv3_se13_default_rtsrx>, <&qupv3_se13_default_tx>;
+ pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,
+ <&qupv3_se13_tx>;
+ pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,
+ <&qupv3_se13_tx>;
+ interrupts-extended = <&intc GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 39 0>;
+ status = "disabled";
+ qcom,wakeup-byte = <0xFD>;
+ qcom,wrapper-core = <&qupv3_1>;
+ };
+
+ /* I2C */
+ qupv3_se8_i2c: i2c@a80000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0xa80000 0x4000>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 0 3 64 0>,
+ <&gpi_dma1 1 0 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se8_i2c_active>;
+ pinctrl-1 = <&qupv3_se8_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ qupv3_se9_i2c: i2c@a84000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0xa84000 0x4000>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 1 3 64 0>,
+ <&gpi_dma1 1 1 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se9_i2c_active>;
+ pinctrl-1 = <&qupv3_se9_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ qupv3_se10_i2c: i2c@a88000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0xa88000 0x4000>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 2 3 64 0>,
+ <&gpi_dma1 1 2 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se10_i2c_active>;
+ pinctrl-1 = <&qupv3_se10_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ qupv3_se11_i2c: i2c@a8c000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0xa8c000 0x4000>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 3 3 64 0>,
+ <&gpi_dma1 1 3 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se11_i2c_active>;
+ pinctrl-1 = <&qupv3_se11_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ qupv3_se12_i2c: i2c@a90000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0xa90000 0x4000>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 4 3 64 0>,
+ <&gpi_dma1 1 4 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se12_i2c_active>;
+ pinctrl-1 = <&qupv3_se12_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ qupv3_se13_i2c: i2c@a94000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0xa94000 0x4000>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 5 3 64 0>,
+ <&gpi_dma1 1 5 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se13_i2c_active>;
+ pinctrl-1 = <&qupv3_se13_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ /* SPI */
+ qupv3_se8_spi: spi@a80000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xa80000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se8_spi_active>;
+ pinctrl-1 = <&qupv3_se8_spi_active>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
+ dmas = <&gpi_dma1 0 0 1 64 0>,
+ <&gpi_dma1 1 0 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se9_spi: spi@a84000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xa84000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se9_spi_active>;
+ pinctrl-1 = <&qupv3_se9_spi_sleep>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
+ dmas = <&gpi_dma1 0 1 1 64 0>,
+ <&gpi_dma1 1 1 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se10_spi: spi@a88000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xa88000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se10_spi_active>;
+ pinctrl-1 = <&qupv3_se10_spi_sleep>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
+ dmas = <&gpi_dma1 0 2 1 64 0>,
+ <&gpi_dma1 1 2 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se11_spi: spi@a8c000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xa8c000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se11_spi_active>;
+ pinctrl-1 = <&qupv3_se11_spi_sleep>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
+ dmas = <&gpi_dma1 0 3 1 64 0>,
+ <&gpi_dma1 1 3 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se12_spi: spi@a90000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xa90000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se12_spi_active>;
+ pinctrl-1 = <&qupv3_se12_spi_sleep>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
+ dmas = <&gpi_dma1 0 4 1 64 0>,
+ <&gpi_dma1 1 4 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se13_spi: spi@a94000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xa94000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se13_spi_active>;
+ pinctrl-1 = <&qupv3_se13_spi_sleep>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
+ dmas = <&gpi_dma1 0 5 1 64 0>,
+ <&gpi_dma1 1 5 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ /* QUPv3_2 wrapper instance : South_2 QUP */
+ qupv3_2: qcom,qupv3_2_geni_se@8c0000 {
+ compatible = "qcom,qupv3-geni-se";
+ reg = <0x8c0000 0x2000>;
+ qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_2>;
+ qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ iommus = <&apps_smmu 0x63 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+ qcom,iommu-dma = "fastmap";
+ };
+
+ /*
+ * HS UART : Modem/Audio backup
+ */
+ qupv3_se17_4uart: qcom,qup_uart@88c000 {
+ compatible = "qcom,msm-geni-serial-hs";
+ reg = <0x88c000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
+ <&qupv3_se17_tx>;
+ pinctrl-1 = <&qupv3_se17_ctsrx>, <&qupv3_se17_rts>,
+ <&qupv3_se17_tx>;
+ interrupts-extended = <&intc GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 55 0>;
+ status = "disabled";
+ qcom,wakeup-byte = <0xFD>;
+ qcom,wrapper-core = <&qupv3_2>;
+ };
+
+ /*
+ * HS UART : 2-wire Modem
+ */
+ qupv3_se18_2uart: qcom,qup_uart@890000 {
+ compatible = "qcom,msm-geni-serial-hs";
+ reg = <0x890000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se18_rx>, <&qupv3_se18_tx>;
+ pinctrl-1 = <&qupv3_se18_rx>, <&qupv3_se18_tx>;
+ interrupts-extended = <&intc GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 59 0>;
+ status = "disabled";
+ qcom,wakeup-byte = <0xFD>;
+ qcom,wrapper-core = <&qupv3_2>;
+ };
+
+ /* I2C */
+ qupv3_se14_i2c: i2c@880000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x880000 0x4000>;
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ dmas = <&gpi_dma2 0 0 3 64 0>,
+ <&gpi_dma2 1 0 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se14_i2c_active>;
+ pinctrl-1 = <&qupv3_se14_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_2>;
+ status = "disabled";
+ };
+
+ qupv3_se15_i2c: i2c@884000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x884000 0x4000>;
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S1_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ dmas = <&gpi_dma2 0 1 3 64 0>,
+ <&gpi_dma2 1 1 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se15_i2c_active>;
+ pinctrl-1 = <&qupv3_se15_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_2>;
+ status = "ok";
+ };
+
+ qupv3_se16_i2c: i2c@888000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x888000 0x4000>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S2_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ dmas = <&gpi_dma2 0 2 3 64 0>,
+ <&gpi_dma2 1 2 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se16_i2c_active>;
+ pinctrl-1 = <&qupv3_se16_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_2>;
+ status = "disabled";
+ };
+
+ qupv3_se17_i2c: i2c@88c000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x88c000 0x4000>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ dmas = <&gpi_dma2 0 3 3 64 0>,
+ <&gpi_dma2 1 3 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se17_i2c_active>;
+ pinctrl-1 = <&qupv3_se17_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_2>;
+ status = "disabled";
+ };
+
+ qupv3_se18_i2c: i2c@890000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x890000 0x4000>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ dmas = <&gpi_dma2 0 4 3 64 0>,
+ <&gpi_dma2 1 4 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se18_i2c_active>;
+ pinctrl-1 = <&qupv3_se18_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_2>;
+ status = "disabled";
+ };
+
+ qupv3_se19_i2c: i2c@894000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x894000 0x4000>;
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ dmas = <&gpi_dma2 0 5 3 64 0>,
+ <&gpi_dma2 1 5 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se19_i2c_active>;
+ pinctrl-1 = <&qupv3_se19_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_2>;
+ status = "disabled";
+ };
+
+ /* SPI */
+ qupv3_se14_spi: spi@880000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x880000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S0_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se14_spi_active>;
+ pinctrl-1 = <&qupv3_se14_spi_sleep>;
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_2>;
+ dmas = <&gpi_dma2 0 0 1 64 0>,
+ <&gpi_dma2 1 0 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se15_spi: spi@884000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x884000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S1_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se15_spi_active>;
+ pinctrl-1 = <&qupv3_se15_spi_sleep>;
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_2>;
+ dmas = <&gpi_dma2 0 1 1 64 0>,
+ <&gpi_dma2 1 1 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se16_spi: spi@888000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x888000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S2_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se16_spi_active>;
+ pinctrl-1 = <&qupv3_se16_spi_sleep>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_2>;
+ dmas = <&gpi_dma2 0 2 1 64 0>,
+ <&gpi_dma2 1 2 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se17_spi: spi@88c000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x88c000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se17_spi_active>;
+ pinctrl-1 = <&qupv3_se17_spi_sleep>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_2>;
+ dmas = <&gpi_dma2 0 3 1 64 0>,
+ <&gpi_dma2 1 3 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se18_spi: spi@890000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x890000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S4_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se18_spi_active>;
+ pinctrl-1 = <&qupv3_se18_spi_sleep>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_2>;
+ dmas = <&gpi_dma2 0 4 1 64 0>,
+ <&gpi_dma2 1 4 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se19_spi: spi@894000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x894000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&clock_gcc GCC_QUPV3_WRAP2_S5_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
+ <&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se19_spi_active>;
+ pinctrl-1 = <&qupv3_se19_spi_sleep>;
+ interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_2>;
+ dmas = <&gpi_dma2 0 5 1 64 0>,
+ <&gpi_dma2 1 5 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-regulators.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-regulators.dtsi
new file mode 100755
index 0000000..528403c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-regulators.dtsi
@@ -0,0 +1,936 @@
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+
+/* RPMh regulators */
+&apps_rsc {
+ /* PM8150A S3 = VDD_MX supply */
+ rpmh-regulator-mxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "mx.lvl";
+ pm8150a_s3_mmcx_sup_level-parent-supply =
+ <&VDD_CX_MMCX_SUPPLY_LEVEL>;
+
+ VDD_MX_LEVEL: S3C_LEVEL:
+ pm8150a_s3_level: regulator-pm8150a-s3-level {
+ regulator-name = "pm8150a_s3_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ VDD_MX_LEVEL_AO: S3C_LEVEL_AO:
+ pm8150a_s3_level_ao: regulator-pm8150a-s3-level-ao {
+ regulator-name = "pm8150a_s3_level_ao";
+ qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ VDD_MX_MMCX_SUPPLY_LEVEL: regulator-pm8150a-s3-mmcx-sup-level {
+ regulator-name = "pm8150a_s3_mmcx_sup_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ /* PM8150 S3 + S2 + S1 = VDD_CX supply */
+ rpmh-regulator-cxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "cx.lvl";
+ pm8150_s3_level-parent-supply = <&VDD_MX_LEVEL>;
+ pm8150_s3_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>;
+ proxy-supply = <&VDD_CX_MMCX_SUPPLY_LEVEL>;
+
+ VDD_CX_LEVEL: S3A_LEVEL:
+ pm8150_s3_level: regulator-pm8150-s3-level {
+ regulator-name = "pm8150_s3_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ qcom,min-dropout-voltage-level = <(-1)>;
+ };
+
+ VDD_CX_LEVEL_AO: S3A_LEVEL_AO:
+ pm8150_s3_level_ao: regulator-pm8150-s3-level-ao {
+ regulator-name = "pm8150_s3_level_ao";
+ qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ qcom,min-dropout-voltage-level = <(-1)>;
+ };
+
+ VDD_CX_MMCX_SUPPLY_LEVEL: regulator-pm8150-s3-mmcx-sup-level {
+ regulator-name = "pm8150_s3_mmcx_sup_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level =
+ <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ qcom,proxy-consumer-enable;
+ qcom,proxy-consumer-voltage
+ = <RPMH_REGULATOR_LEVEL_TURBO
+ RPMH_REGULATOR_LEVEL_MAX>;
+ };
+ };
+
+ rpmh-regulator-smpa4 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpa4";
+ S4A: pm8150_s4: regulator-pm8150-s4 {
+ regulator-name = "pm8150_s4";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1920000>;
+ qcom,init-voltage = <1800000>;
+ };
+ };
+
+ rpmh-regulator-smpa5 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpa5";
+ S5A: pm8150_s5: regulator-pm8150-s5 {
+ regulator-name = "pm8150_s5";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1824000>;
+ regulator-max-microvolt = <2040000>;
+ qcom,init-voltage = <1824000>;
+ };
+ };
+
+ rpmh-regulator-smpa6 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpa6";
+ S6A: pm8150_s6: regulator-pm8150-s6 {
+ regulator-name = "pm8150_s6";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1128000>;
+ qcom,init-voltage = <600000>;
+ };
+ };
+
+ rpmh-regulator-ldoa2 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa2";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L2A: pm8150_l2: regulator-pm8150-l2 {
+ regulator-name = "pm8150_l2";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <3072000>;
+ regulator-max-microvolt = <3072000>;
+ qcom,init-voltage = <3072000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa3 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa3";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 30000>;
+ L3A: pm8150_l3: regulator-pm8150-l3 {
+ regulator-name = "pm8150_l3";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <928000>;
+ regulator-max-microvolt = <932000>;
+ qcom,init-voltage = <928000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ /* PM8150 L4 = VDD_SSC_MX supply */
+ rpmh-regulator-lmxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "lmx.lvl";
+ L4A_LEVEL: pm8150_l4_level: regulator-pm8150-l4-level {
+ regulator-name = "pm8150_l4_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ rpmh-regulator-ldoa5 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa5";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 30000>;
+ proxy-supply = <&pm8150_l5>;
+ L5A: pm8150_l5: regulator-pm8150-l5 {
+ regulator-name = "pm8150_l5";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ qcom,init-voltage = <880000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+ qcom,proxy-consumer-enable;
+ qcom,proxy-consumer-current = <100000>;
+ };
+
+ L5A_AO: pm8150_l5_ao: regulator-pm8150-l5-ao {
+ regulator-name = "pm8150_l5_ao";
+ qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ qcom,init-voltage = <880000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ regulator-pm8150-l5-so {
+ regulator-name = "pm8150_l5_so";
+ qcom,set = <RPMH_REGULATOR_SET_SLEEP>;
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ qcom,init-voltage = <880000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ qcom,init-enable = <0>;
+ };
+ };
+
+ rpmh-regulator-ldoa6 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa6";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 30000>;
+ L6A: pm8150_l6: regulator-pm8150-l6 {
+ regulator-name = "pm8150_l6";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ qcom,init-voltage = <1200000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa7 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa7";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L7A: pm8150_l7: regulator-pm8150-l7 {
+ regulator-name = "pm8150_l7";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1704000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa9 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa9";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 30000>;
+ proxy-supply = <&pm8150_l9>;
+ L9A: pm8150_l9: regulator-pm8150-l9 {
+ regulator-name = "pm8150_l9";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ qcom,init-voltage = <1200000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_HPM>;
+ qcom,proxy-consumer-enable;
+ qcom,proxy-consumer-current = <100000>;
+ };
+ };
+
+ rpmh-regulator-ldoa10 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa10";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L10A: pm8150_l10: regulator-pm8150-l10 {
+ regulator-name = "pm8150_l10";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ qcom,init-voltage = <1800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ /* PM8150 L11 = VDD_SSC_CX supply */
+ rpmh-regulator-lcxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "lcx.lvl";
+ L11A_LEVEL: pm8150_l11_level: regulator-pm8150-l11-level {
+ regulator-name = "pm8150_l11_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt
+ = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ rpmh-regulator-ldoa12 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa12";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L12A: pm8150_l12: regulator-pm8150-l12 {
+ regulator-name = "pm8150_l12";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ L12A_AO: pm8150_l12_ao: regulator-pm8150-l12-ao {
+ regulator-name = "pm8150_l12_ao";
+ qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ regulator-pm8150-l12-so {
+ regulator-name = "pm8150_l12_so";
+ qcom,set = <RPMH_REGULATOR_SET_SLEEP>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ qcom,init-enable = <0>;
+ };
+ };
+
+ rpmh-regulator-ldoa13 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa13";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L13A: pm8150_l13: regulator-pm8150-l13 {
+ regulator-name = "pm8150_l13";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3008000>;
+ qcom,init-voltage = <3008000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa14 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa14";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ proxy-supply = <&pm8150_l14>;
+ L14A: pm8150_l14: regulator-pm8150-l14 {
+ regulator-name = "pm8150_l14";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ qcom,proxy-consumer-enable;
+ qcom,proxy-consumer-current = <62000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1880000>;
+ qcom,init-voltage = <1800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa15 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa15";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L15A: pm8150_l15: regulator-pm8150-l15 {
+ regulator-name = "pm8150_l15";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa16 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa16";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L16A: pm8150_l16: regulator-pm8150-l16 {
+ regulator-name = "pm8150_l16";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <3024000>;
+ regulator-max-microvolt = <3304000>;
+ qcom,init-voltage = <3024000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa17 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa17";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L17A: pm8150_l17: regulator-pm8150-l17 {
+ regulator-name = "pm8150_l17";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <2496000>;
+ regulator-max-microvolt = <3008000>;
+ qcom,init-voltage = <2496000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa18 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa18";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 30000>;
+ L18A: pm8150_l18: regulator-pm8150-l18 {
+ regulator-name = "pm8150_l18";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <920000>;
+ qcom,init-voltage = <800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ /* PM8150A S1 + S2 = VDD_GFX supply */
+ rpmh-regulator-gfxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "gfx.lvl";
+ VDD_GFX_LEVEL: S1C_LEVEL:
+ pm8150a_s1_level: regulator-pm8150a-s1-level {
+ regulator-name = "pm8150a_s1_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt
+ = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ /* PM8150A S4 + S5 = VDD_MMCX supply */
+ rpmh-regulator-mmcxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "mmcx.lvl";
+ pm8150a_s4_level-parent-supply = <&VDD_MX_MMCX_SUPPLY_LEVEL>;
+ pm8150a_s4_level_ao-parent-supply = <&VDD_MX_LEVEL_AO>;
+ proxy-supply = <&VDD_MMCX_LEVEL>;
+
+ VDD_MMCX_LEVEL: S4C_LEVEL:
+ pm8150a_s4_level: regulator-pm8150a-s4-level {
+ regulator-name = "pm8150a_s4_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt
+ = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ regulator-max-microvolt
+ = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ qcom,min-dropout-voltage-level = <(-1)>;
+ qcom,proxy-consumer-enable;
+ qcom,proxy-consumer-voltage
+ = <RPMH_REGULATOR_LEVEL_TURBO
+ RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ VDD_MMCX_LEVEL_AO: S4C_LEVEL_AO:
+ pm8150a_s4_level_ao: regulator-pm8150a-s4-level-ao {
+ regulator-name = "pm8150a_s4_level_ao";
+ qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+ regulator-min-microvolt
+ = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ regulator-max-microvolt
+ = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ qcom,min-dropout-voltage-level = <(-1)>;
+ };
+
+ regulator-pm8150a-s4-level-so {
+ regulator-name = "pm8150a_s4_level_so";
+ qcom,set = <RPMH_REGULATOR_SET_SLEEP>;
+ regulator-min-microvolt
+ = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ regulator-max-microvolt
+ = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+
+ /* PM8150A S6 = VDD_EBI supply */
+ rpmh-regulator-ebilvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "ebi.lvl";
+ S6C_LEVEL: pm8150a_s6_level: regulator-pm8150a-s6-level {
+ regulator-name = "pm8150a_s6_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt
+ = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ rpmh-regulator-smpc7 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpc7";
+ S7C: pm8150a_s7: regulator-pm8150a-s7 {
+ regulator-name = "pm8150a_s7";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <348000>;
+ regulator-max-microvolt = <1000000>;
+ qcom,init-voltage = <348000>;
+ };
+ };
+
+ rpmh-regulator-smpc8 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpc8";
+ qcom,regulator-type = "pmic5-hfsmps";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_RET
+ RPMH_REGULATOR_MODE_AUTO>;
+ qcom,mode-threshold-currents = <0 200000>;
+ S8C: pm8150a_s8: regulator-pm8150a-s8 {
+ regulator-name = "pm8150a_s8";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1400000>;
+ qcom,init-voltage = <1200000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_RET>;
+ };
+ };
+
+ rpmh-regulator-ldoc1 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc1";
+ qcom,regulator-type = "pmic5-ldo";
+ L1C: pm8150a_l1: regulator-pm8150a-l1 {
+ regulator-name = "pm8150a_l1";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ };
+ };
+
+ rpmh-regulator-ldoc2 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc2";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 30000>;
+ L2C: pm8150a_l2: regulator-pm8150a-l2 {
+ regulator-name = "pm8150a_l2";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1304000>;
+ qcom,init-voltage = <1200000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc3 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc3";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 30000>;
+ L3C: pm8150a_l3: regulator-pm8150a-l3 {
+ regulator-name = "pm8150a_l3";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1200000>;
+ qcom,init-voltage = <800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc4 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc4";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L4C: pm8150a_l4: regulator-pm8150a-l4 {
+ regulator-name = "pm8150a_l4";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ qcom,init-voltage = <1800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc5 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc5";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L5C: pm8150a_l5: regulator-pm8150a-l5 {
+ regulator-name = "pm8150a_l5";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2800000>;
+ qcom,init-voltage = <1800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc6 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc6";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L6C: pm8150a_l6: regulator-pm8150a-l6 {
+ regulator-name = "pm8150a_l6";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ qcom,init-voltage = <1800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc7 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc7";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L7C: pm8150a_l7: regulator-pm8150a-l7 {
+ regulator-name = "pm8150a_l7";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <2856000>;
+ regulator-max-microvolt = <3104000>;
+ qcom,init-voltage = <2856000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc8 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc8";
+ qcom,regulator-type = "pmic5-ldo";
+ L8C: pm8150a_l8: regulator-pm8150a-l8 {
+ regulator-name = "pm8150a_l8";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ };
+ };
+
+ rpmh-regulator-ldoc9 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc9";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L9C: pm8150a_l9: regulator-pm8150a-l9 {
+ regulator-name = "pm8150a_l9";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <2960000>;
+ qcom,init-voltage = <2704000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc10 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc10";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L10C: pm8150a_l10: regulator-pm8150a-l10 {
+ regulator-name = "pm8150a_l10";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ qcom,init-voltage = <3000000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc11 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc11";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ proxy-supply = <&pm8150a_l11>;
+ L11C: pm8150a_l11: regulator-pm8150a-l11 {
+ regulator-name = "pm8150a_l11";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ qcom,proxy-consumer-enable;
+ qcom,proxy-consumer-current = <857000>;
+ regulator-min-microvolt = <3104000>;
+ regulator-max-microvolt = <3304000>;
+ qcom,init-voltage = <3104000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-bobc1 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "bobc1";
+ qcom,regulator-type = "pmic5-bob";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_PASS
+ RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1000000 2000000>;
+ qcom,send-defaults;
+
+ BOB: pm8150a_bob: regulator-pm8150a-bob {
+ regulator-name = "pm8150a_bob";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ qcom,init-voltage = <3312000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_PASS>;
+ };
+
+ BOB_AO: pm8150a_bob_ao: regulator-pm8150a-bob-ao {
+ regulator-name = "pm8150a_bob_ao";
+ qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ qcom,init-voltage = <3008000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+
+ rpmh-regulator-smpf1 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpf1";
+ S1F: pm8009_s1: regulator-pm8009-s1 {
+ regulator-name = "pm8009_s1";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ qcom,init-voltage = <1200000>;
+ };
+ };
+
+ rpmh-regulator-smpf2 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpf2";
+ S2F: pm8009_s2: regulator-pm8009-s2 {
+ regulator-name = "pm8009_s2";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <512000>;
+ regulator-max-microvolt = <1100000>;
+ qcom,init-voltage = <512000>;
+ };
+ };
+
+ rpmh-regulator-ldof1 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldof1";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 30000>;
+ L1F: pm8009_l1: regulator-pm8009-l1 {
+ regulator-name = "pm8009_l1";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1104000>;
+ regulator-max-microvolt = <1104000>;
+ qcom,init-voltage = <1104000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldof2 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldof2";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 30000>;
+ L2F: pm8009_l2: regulator-pm8009-l2 {
+ regulator-name = "pm8009_l2";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ qcom,init-voltage = <1200000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldof3 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldof3";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 30000>;
+ L3F: pm8009_l3: regulator-pm8009-l3 {
+ regulator-name = "pm8009_l3";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1056000>;
+ regulator-max-microvolt = <1056000>;
+ qcom,init-voltage = <1056000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldof5 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldof5";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L5F: pm8009_l5: regulator-pm8009-l5 {
+ regulator-name = "pm8009_l5";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ qcom,init-voltage = <2800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldof6 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldof6";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L6F: pm8009_l6: regulator-pm8009-l6 {
+ regulator-name = "pm8009_l6";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ qcom,init-voltage = <2800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldof7 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldof7";
+ qcom,regulator-type = "pmic5-ldo";
+ L7F: pm8009_l7: regulator-pm8009-l7 {
+ regulator-name = "pm8009_l7";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ };
+ };
+};
+
+&soc {
+ refgen: refgen-regulator@88e7000 {
+ compatible = "qcom,refgen-kona-regulator";
+ reg = <0x88e7000 0x84>;
+ regulator-name = "refgen";
+ regulator-enable-ramp-delay = <5>;
+ proxy-supply = <&refgen>;
+ qcom,proxy-consumer-enable;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-rumi-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/kona-rumi-overlay.dts
new file mode 100755
index 0000000..1c11804
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-rumi-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-kona.h>
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "kona-rumi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona RUMI";
+ compatible = "qcom,kona-rumi", "qcom,kona", "qcom,rumi";
+ qcom,board-id = <0x1000F 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-rumi.dts b/arch/arm64/boot/dts/vendor/qcom/kona-rumi.dts
new file mode 100755
index 0000000..8eb9874
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-rumi.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/memreserve/ 0x90000000 0x00000100;
+
+#include "kona.dtsi"
+#include "kona-rumi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona RUMI";
+ compatible = "qcom,kona-rumi", "qcom,kona", "qcom,rumi";
+ qcom,board-id = <0x1000F 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-rumi.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-rumi.dtsi
new file mode 100755
index 0000000..87b0300
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-rumi.dtsi
@@ -0,0 +1,155 @@
+#include <dt-bindings/gpio/gpio.h>
+#include "kona-pmic-overlay.dtsi"
+#include "kona-sde-display.dtsi"
+#include "msm-audio-lpass.dtsi"
+
+&arch_timer {
+ clock-frequency = <500000>;
+};
+
+&memtimer {
+ clock-frequency = <500000>;
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qrbtc-sdm845";
+
+ vdda-phy-supply = <&pm8150_l5>;
+ vdda-pll-supply = <&pm8150_l9>;
+ vdda-phy-max-microamp = <89900>;
+ vdda-pll-max-microamp = <18300>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ limit-tx-hs-gear = <1>;
+ limit-rx-hs-gear = <1>;
+
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm8150_l17>;
+ vccq2-supply = <&pm8150_s4>;
+ vcc-max-microamp = <750000>;
+ vccq2-max-microamp = <750000>;
+
+ qcom,vddp-ref-clk-supply = <&pm8150_l6>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+
+ qcom,disable-lpm;
+ rpm-level = <0>;
+ spm-level = <0>;
+ status = "ok";
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pcie2: qcom,pcie@1c10000 {
+ reg = <0x01c10000 0x4000>,
+ <0x01c16000 0x2000>,
+ <0x64000000 0xf1d>,
+ <0x64000f20 0xa8>,
+ <0x64001000 0x1000>,
+ <0x64100000 0x100000>,
+ <0x64200000 0x100000>,
+ <0x64300000 0x4000000>,
+ <0x01c15000 0x1000>;
+ reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf",
+ "io", "bars", "rumi";
+
+ qcom,target-link-speed = <0x1>;
+ qcom,link-check-max-count = <200>; /* 1 sec */
+ qcom,no-l1-supported;
+ qcom,no-l1ss-supported;
+ qcom,no-aux-clk-sync;
+ };
+
+ usb_emu_phy: usb_emu_phy@a720000 {
+ compatible = "qcom,usb-emu-phy";
+ reg = <0x0a720000 0x9500>,
+ <0x0a6f8800 0x100>;
+ reg-names = "base", "qscratch_base";
+
+ qcom,emu-init-seq = <0xffff 0x4
+ 0xfff0 0x4
+ 0x100000 0x20
+ 0x0 0x20
+ 0x101f0 0x20
+ 0x100000 0x3c
+ 0x0 0x3c
+ 0x10060 0x3c
+ 0x0 0x4>;
+ };
+};
+
+&usb0 {
+ /delete-property/ extcon;
+ dwc3@a600000 {
+ usb-phy = <&usb_emu_phy>, <&usb_nop_phy>;
+ maximum-speed = "high-speed";
+ };
+};
+
+&qupv3_se12_2uart {
+ status = "disabled";
+};
+
+/* RUMI UART console */
+&qupv3_se2_2uart {
+ status = "ok";
+};
+
+&audio_apr {
+ sound-stub {
+ compatible = "qcom,kona-asoc-snd-stub";
+ qcom,model = "kona-stub-snd-card";
+
+ qcom,audio-routing =
+ "AIF4 VI", "MCLK";
+
+ asoc-platform = <&pcm0>, <&routing>;
+ asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-routing";
+ asoc-cpu = <&dai_pri_auxpcm>;
+ asoc-cpu-names = "msm-dai-q6-auxpcm.1";
+ asoc-codec = <&stub_codec>;
+ asoc-codec-names = "msm-stub-codec.1";
+ };
+};
+
+&ipa_hw {
+ qcom,ipa-hw-mode = <1>; /* IPA hw type = Virtual */
+};
+
+&mhi_0 {
+ mhi,timeout = <10000>;
+
+ mhi_channels {
+ mhi_chan@25 {
+ status = "disabled";
+ };
+ };
+};
+
+&sdhc_2 {
+ vdd-supply = <&pm8150a_l9>;
+ qcom,vdd-voltage-level = <2950000 2960000>;
+ qcom,vdd-current-level = <200 800000>;
+
+ vdd-io-supply = <&pm8150a_l6>;
+ qcom,vdd-io-voltage-level = <1808000 2960000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>;
+
+ cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+
+ status = "disabled";
+};
+
+&wdog {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-sa-mtp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/kona-sa-mtp-overlay.dts
new file mode 100755
index 0000000..8ef8c78
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-sa-mtp-overlay.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-kona.h>
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "kona-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona standalone MTP";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x02010008 0>;
+};
+
+&mdm0 {
+ status = "disabled";
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-sde-display.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-sde-display.dtsi
new file mode 100755
index 0000000..71ad423
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-sde-display.dtsi
@@ -0,0 +1,977 @@
+#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi"
+#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi"
+#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi"
+#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
+#include "dsi-panel-sharp-dsc-4k-video.dtsi"
+#include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi"
+#include "dsi-panel-sharp-qsync-wqhd-video.dtsi"
+#include "dsi-panel-sharp-1080p-cmd.dtsi"
+#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
+#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
+#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
+#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
+#include "dsi-panel-ext-bridge-1080p.dtsi"
+#include "dsi-panel-ext-bridge-4k-video.dtsi"
+#include "dsi-panel-sim-cmd.dtsi"
+#include "dsi-panel-sim-video.dtsi"
+#include "dsi-panel-sim-dsc375-cmd.dtsi"
+#include "dsi-panel-sim-dsc-10bit-cmd.dtsi"
+#include "dsi-panel-sim-dualmipi-cmd.dtsi"
+#include "dsi-panel-sim-dualmipi-video.dtsi"
+#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
+#include "dsi-panel-sim-sec-hd-cmd.dtsi"
+#include "dsi-panel-xrsmrtvwr-jdi-dual-video.dtsi"
+#include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi"
+#include "dsi-panel-arglass-seeya-dual-1080p-video.dtsi"
+#include "dsi-panel-nt36672e-fhd-plus-60hz-video.dtsi"
+#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
+
+&tlmm {
+ display_panel_avdd_default: display_panel_avdd_default {
+ mux {
+ pins = "gpio61";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio61";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ output-high;
+ };
+ };
+};
+
+&soc {
+ ext_disp: qcom,msm-ext-disp {
+ compatible = "qcom,msm-ext-disp";
+
+ ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
+ compatible = "qcom,msm-ext-disp-audio-codec-rx";
+ };
+ };
+
+ dsi_panel_pwr_supply: dsi_panel_pwr_supply {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "vdd";
+ qcom,supply-min-voltage = <3300000>;
+ qcom,supply-max-voltage = <3300000>;
+ qcom,supply-enable-load = <857000>;
+ qcom,supply-disable-load = <0>;
+ qcom,supply-post-on-sleep = <0>;
+ };
+
+ qcom,panel-supply-entry@2 {
+ reg = <2>;
+ qcom,supply-name = "lab";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@3 {
+ reg = <3>;
+ qcom,supply-name = "ibb";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+ };
+
+ dsi_panel_pwr_supply_lab_ibb: dsi_panel_pwr_supply_lab_ibb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "lab";
+ qcom,supply-min-voltage = <5600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@2 {
+ reg = <2>;
+ qcom,supply-name = "ibb";
+ qcom,supply-min-voltage = <5600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+ };
+
+ dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "avdd";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+ };
+
+ display_panel_avdd: display_gpio_regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "display_panel_avdd";
+ regulator-min-microvolt = <5500000>;
+ regulator-max-microvolt = <5500000>;
+ regulator-enable-ramp-delay = <233>;
+ gpio = <&tlmm 61 0>;
+ enable-active-high;
+ regulator-boot-on;
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_panel_avdd_default>;
+ };
+
+ sde_dsi: qcom,dsi-display-primary {
+ compatible = "qcom,dsi-display";
+ label = "primary";
+
+ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+ qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+
+ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll PCLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll PCLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll CPHY_BYTECLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll CPHY_PCLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll SHADOW_CPHY_BYTECLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll SHADOW_CPHY_PCLK_SRC_0_CLK>,
+ <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
+ <&mdss_dsi1_pll PCLK_MUX_1_CLK>,
+ <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>,
+ <&mdss_dsi1_pll PCLK_SRC_1_CLK>,
+ <&mdss_dsi1_pll CPHY_BYTECLK_SRC_1_CLK>,
+ <&mdss_dsi1_pll CPHY_PCLK_SRC_1_CLK>,
+ <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>,
+ <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>,
+ <&mdss_dsi1_pll SHADOW_CPHY_BYTECLK_SRC_1_CLK>,
+ <&mdss_dsi1_pll SHADOW_CPHY_PCLK_SRC_1_CLK>;
+
+ clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "cphy_byte_clk0", "cphy_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0",
+ "shadow_cphybyte_clk0", "shadow_cphypixel_clk0",
+ "mux_byte_clk1", "mux_pixel_clk1",
+ "src_byte_clk1", "src_pixel_clk1",
+ "cphy_byte_clk1", "cphy_pixel_clk1",
+ "shadow_byte_clk1", "shadow_pixel_clk1",
+ "shadow_cphybyte_clk1", "shadow_cphypixel_clk1";
+
+ pinctrl-names = "panel_active", "panel_suspend";
+ pinctrl-0 = <&sde_dsi_active &sde_te_active>;
+ pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
+
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,panel-te-source = <0>;
+
+ vddio-supply = <&pm8150_l14>;
+ vdd-supply = <&pm8150a_l11>;
+ avdd-supply = <&display_panel_avdd>;
+ lab-supply = <&ab_vreg>;
+ ibb-supply = <&ibb_vreg>;
+
+ qcom,mdp = <&mdss_mdp>;
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_cmd>;
+ };
+
+ sde_dsi1: qcom,dsi-display-secondary {
+ compatible = "qcom,dsi-display";
+ label = "secondary";
+
+ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+ qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+
+ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll PCLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll CPHY_BYTECLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll CPHY_PCLK_SRC_0_CLK>,
+ <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
+ <&mdss_dsi1_pll PCLK_MUX_1_CLK>,
+ <&mdss_dsi1_pll CPHY_BYTECLK_SRC_1_CLK>,
+ <&mdss_dsi1_pll CPHY_PCLK_SRC_1_CLK>;
+ clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+ "cphy_byte_clk0", "cphy_pixel_clk0",
+ "mux_byte_clk1", "mux_pixel_clk1",
+ "cphy_byte_clk1", "cphy_pixel_clk1";
+
+ pinctrl-names = "panel_active", "panel_suspend";
+ pinctrl-0 = <&sde_dsi1_active &sde_te1_active>;
+ pinctrl-1 = <&sde_dsi1_suspend &sde_te1_suspend>;
+
+ qcom,platform-te-gpio = <&tlmm 67 0>;
+ qcom,panel-te-source = <1>;
+
+ vddio-supply = <&pm8150_l14>;
+ vdd-supply = <&pm8150a_l11>;
+ avdd-supply = <&display_panel_avdd>;
+
+ qcom,mdp = <&mdss_mdp>;
+ };
+
+ sde_wb: qcom,wb-display@0 {
+ compatible = "qcom,wb-display";
+ cell-index = <0>;
+ label = "wb_display";
+ };
+
+ msm_notifier: qcom,msm_notifier@0 {
+ compatible = "qcom,msm-notifier";
+ panel = <&dsi_sw43404_amoled_cmd &dsi_sharp_qsync_wqhd_cmd
+ &dsi_dual_sim_dsc_375_cmd>;
+ };
+};
+
+&sde_dp {
+ qcom,dp-usbpd-detection = <&pm8150b_pdphy>;
+ qcom,ext-disp = <&ext_disp>;
+ qcom,dp-aux-switch = <&fsa4480>;
+
+ qcom,usbplug-cc-gpio = <&tlmm 65 0>;
+
+ pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
+ pinctrl-0 = <&sde_dp_usbplug_cc_active>;
+ pinctrl-1 = <&sde_dp_usbplug_cc_suspend>;
+};
+
+&mdss_mdp {
+ connectors = <&sde_dp &sde_wb &sde_dsi &sde_dsi1 &sde_rscc>;
+};
+
+/* PHY TIMINGS REVISION W */
+&dsi_ext_bridge_1080p {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 17];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_ext_bridge_4k_vid {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 3a 0f 0f 2e 2b 0f
+ 10 0b 02 04 00 2e 1e];
+ qcom,display-topology = <2 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_arglass_seeya_video {
+ qcom,mdss-dsi-min-refresh-rate = <60>;
+ qcom,mdss-dsi-max-refresh-rate = <90>;
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 12 1E
+ 04 04 04 03 02 04 0F 09];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_xrsmrtvwr_jdi_video {
+ qcom,mdss-dsi-min-refresh-rate = <53>;
+ qcom,mdss-dsi-max-refresh-rate = <80>;
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 17 05 05 20 1F
+ 06 06 03 02 04 00 13 15];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sw43404_amoled_cmd {
+ qcom,ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+
+ qcom,dsi-dyn-clk-enable;
+ qcom,dsi-dyn-clk-list = <552424501 549895420 547366339>;
+
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
+ 05 03 02 04 00 12 15];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 1f 1e 05
+ 05 03 02 04 00 12 14];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-phy-timings = [00 11 03 04 1e 1e 04
+ 04 02 02 04 00 10 14];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
+ };
+ };
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-supported-dfps-list = <60 57 55>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp";
+ qcom,mdss-dsi-min-refresh-rate = <55>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+
+ qcom,dsi-dyn-clk-enable;
+ qcom,dsi-dyn-clk-list =
+ <534712320 532484352 530256384>;
+
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
+ 05 03 02 04 00 12 15];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04
+ 05 02 03 04 00 11 14];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 270 270 270 1080 270>;
+ qcom,mdss-dsi-panel-clockrate = <400000000>;
+ };
+ };
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sharp_qsync_wqhd_cmd {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 { /* WQHD 60FPS CMD */
+ qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 1d 1c 03
+ 03 01 02 04 00 0c 12];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
+ };
+
+ timing@1 { /* WQHD 60FPS VID */
+ qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06
+ 06 03 02 04 00 13 15];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 { /* FHD 60FPS CMD */
+ qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 1b 1c 02
+ 02 00 02 04 00 0a 12];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
+ };
+
+ timing@3 { /* WQHD 90FPS CMD */
+ qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 1e 1e 04
+ 04 02 02 04 00 0f 13];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
+ };
+
+ timing@4 { /* WQHD 120FPS CMD */
+ qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1f 1e 05
+ 05 03 02 04 00 12 14];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
+ };
+
+ timing@5 { /* WQHD 120FPS VID */
+ qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06
+ 06 03 02 04 00 13 15];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@6 { /* FHD 120FPS CMD */
+ qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04
+ 04 02 02 04 00 0e 13];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
+ };
+
+ timing@7 { /* FHD 90FPS CMD */
+ qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03
+ 02 01 02 04 00 0c 12];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
+ };
+ };
+};
+
+&dsi_sharp_qsync_wqhd_video {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06
+ 06 03 02 04 00 13 15];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_nt36672e_fhd_plus_60_video {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1f 1e 05
+ 05 03 02 04 00 12 14];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sharp_1080_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ qcom,mdss-dsi-panel-clockrate = <900000000>;
+ };
+ };
+};
+
+&dsi_dual_nt35597_truly_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_nt35597_truly_video {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-min-refresh-rate = <53>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
+ 08 08 05 02 04 00 19 17];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
+ 08 08 05 02 04 00 19 17];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ qcom,panel-roi-alignment = <720 40 720 40 720 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ qcom,panel-roi-alignment = <720 40 720 40 720 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ qcom,panel-roi-alignment = <720 40 720 40 720 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+
+ timing@3 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ qcom,panel-roi-alignment = <540 40 540 40 540 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+
+ timing@4 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ qcom,panel-roi-alignment = <360 40 360 40 360 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+ };
+};
+
+&dsi_sim_vid {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 0 1>,
+ <2 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 { /* 1080p */
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 { /* qhd */
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>, /* dsc merge */
+ <2 1 1>; /* 3d mux */
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
+ 06 04 02 04 00 16 16];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 { /* QHD 60fps */
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 { /* 1080 60fps */
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>, /* dsc merge */
+ <2 1 1>; /* 3d mux */
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 { /* QHD 90fps */
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_sim_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
+ 09 06 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_sim_vid {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 { /* 4k 30 FPS*/
+ qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04
+ 04 02 02 04 00 0e 13];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 { /* 4k 60 FPS*/
+ qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
+ 06 04 02 04 00 15 16];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 { /* 4k 90 FPS*/
+ qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 25 23 09
+ 09 06 02 04 00 1c 19];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@3 { /* 4k 120 FPS*/
+ qcom,mdss-dsi-panel-phy-timings = [00 2c 0c 0c 29 27 0c
+ 0c 08 02 04 00 24 1b];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@4 { /* 1080 30 FPS*/
+ qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01
+ 01 01 02 04 00 0a 11];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@5 { /* 1080 60 FPS*/
+ qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03
+ 02 01 02 04 00 0c 12];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@6 { /* 1080 90 FPS*/
+ qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04
+ 03 02 02 04 00 0e 13];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@7 { /* 1080 120 FPS*/
+ qcom,mdss-dsi-panel-phy-timings = [00 11 04 04 1e 1e 04
+ 04 02 02 04 00 10 14];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@8 { /* qhd 30 FPS*/
+ qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02
+ 02 01 02 04 00 0b 12];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@9 { /* qhd 60 FPS*/
+ qcom,mdss-dsi-panel-phy-timings = [00 0f 03 03 1e 1d 04
+ 04 02 02 04 00 0f 13];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@10 { /* qhd 90 FPS*/
+ qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1f 05
+ 05 03 02 04 00 12 15];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@11 { /* qhd 120 FPS*/
+ qcom,mdss-dsi-panel-phy-timings = [00 19 06 06 21 20 07
+ 06 04 02 04 00 15 16];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@12 { /* 5k */
+ qcom,mdss-dsi-panel-phy-timings = [00 1a 07 06 22 21 07
+ 07 04 02 04 00 16 16];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@13 { /* 720p 30 FPS */
+ qcom,mdss-dsi-panel-phy-timings = [03 07 00 01 1a 1a 01
+ 01 00 02 04 00 08 11];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@14 { /* 720p 60 FPS */
+ qcom,mdss-dsi-panel-phy-timings = [01 09 01 01 1b 1b 01
+ 01 01 02 04 00 0a 11];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@15 { /* 720p 90 FPS */
+ qcom,mdss-dsi-panel-phy-timings = [00 0a 02 02 1c 1c 02
+ 02 01 02 04 00 0b 12];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@16 { /* 720 120 FPS */
+ qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03
+ 03 01 02 04 00 0c 12];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@17 { /* 1080 144 FPS */
+ qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1f 1e 05
+ 05 03 02 04 00 12 14];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_sec_hd_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
+ 08 08 05 02 04 00 19 17];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ qcom,panel-roi-alignment = <720 40 720 40 720 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+ };
+};
+
+&dsi_r66451_amoled_144hz_cmd {
+ qcom,ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x1c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 17 09
+ 09 09 02 04 00 1d 0e];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-sde-pll.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-sde-pll.dtsi
new file mode 100755
index 0000000..0484c59
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-sde-pll.dtsi
@@ -0,0 +1,67 @@
+&soc {
+ mdss_dsi0_pll: qcom,mdss_dsi_pll@ae94900 {
+ compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
+ label = "MDSS DSI 0 PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+ reg = <0xae94900 0x260>,
+ <0xae94400 0x800>,
+ <0xaf03000 0x8>,
+ <0xae94200 0x100>;
+ reg-names = "pll_base", "phy_base", "gdsc_base",
+ "dynamic_pll_base";
+ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ memory-region = <&dfps_data_memory>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ };
+
+ mdss_dsi1_pll: qcom,mdss_dsi_pll@ae96900 {
+ compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
+ label = "MDSS DSI 1 PLL";
+ cell-index = <1>;
+ #clock-cells = <1>;
+ reg = <0xae96900 0x260>,
+ <0xae96400 0x800>,
+ <0xaf03000 0x8>,
+ <0xae96200 0x100>;
+ reg-names = "pll_base", "phy_base", "gdsc_base",
+ "dynamic_pll_base";
+ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ };
+
+ mdss_dp_pll: qcom,mdss_dp_pll@c011000 {
+ compatible = "qcom,mdss_dp_pll_7nm";
+ label = "MDSS DP PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+
+ reg = <0x088ea000 0x200>,
+ <0x088eaa00 0x200>,
+ <0x088ea200 0x200>,
+ <0x088ea2b8 0x8>,
+ <0x088ea2e8 0x4>,
+ <0x088ea600 0x200>,
+ <0x088ea6b8 0x8>,
+ <0x088ea6e8 0x4>,
+ <0xaf03000 0x8>;
+ reg-names = "pll_base", "phy_base",
+ "ln_tx0_base", "ln_tx0_tran_base", "ln_tx0_vmode_base",
+ "ln_tx1_base", "ln_tx1_tran_base", "ln_tx1_vmode_base",
+ "gdsc_base";
+
+ clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_DISP_AHB_CLK>,
+ <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "iface_clk", "ref_clk_src",
+ "gcc_iface", "pipe_clk";
+ clock-rate = <0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-sde.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-sde.dtsi
new file mode 100755
index 0000000..7f87604
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-sde.dtsi
@@ -0,0 +1,737 @@
+#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
+
+&soc {
+ mdss_mdp: qcom,mdss_mdp@ae00000 {
+ compatible = "qcom,sde-kms";
+ reg = <0x0ae00000 0x84208>,
+ <0x0aeb0000 0x2008>,
+ <0x0aeac000 0x214>,
+ <0x0ae8f000 0x02c>,
+ <0x0af50000 0x038>;
+ reg-names = "mdp_phys",
+ "vbif_phys",
+ "regdma_phys",
+ "sid_phys",
+ "swfuse_phys";
+
+ clocks =
+ <&clock_gcc GCC_DISP_AHB_CLK>,
+ <&clock_gcc GCC_DISP_HF_AXI_CLK>,
+ <&clock_gcc GCC_DISP_SF_AXI_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
+ clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
+ "iface_clk", "core_clk", "vsync_clk",
+ "lut_clk", "rot_clk";
+ clock-rate = <0 0 0 0 300000000 19200000 300000000 19200000>;
+ clock-max-rate = <0 0 0 0 460000000 19200000 460000000
+ 460000000>;
+
+ mmcx-supply = <&VDD_MMCX_LEVEL>;
+
+ /* interrupt config */
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #power-domain-cells = <0>;
+
+ /* hw blocks */
+ qcom,sde-off = <0x1000>;
+ qcom,sde-len = <0x494>;
+
+ qcom,sde-ctl-off = <0x2000 0x2200 0x2400
+ 0x2600 0x2800 0x2a00>;
+ qcom,sde-ctl-size = <0x1dc>;
+ qcom,sde-ctl-display-pref = "primary", "none", "none",
+ "none", "none";
+
+ qcom,sde-mixer-off = <0x45000 0x46000 0x47000
+ 0x48000 0x49000 0x4a000>;
+ qcom,sde-mixer-size = <0x320>;
+ qcom,sde-mixer-display-pref = "primary", "primary", "none",
+ "none", "none", "none";
+
+ qcom,sde-mixer-cwb-pref = "none", "none", "cwb",
+ "cwb", "cwb", "cwb";
+
+ qcom,sde-dspp-top-off = <0x1300>;
+ qcom,sde-dspp-top-size = <0x80>;
+ qcom,sde-dspp-off = <0x55000 0x57000 0x59000 0x5b000>;
+ qcom,sde-dspp-size = <0x1800>;
+
+ qcom,sde-dest-scaler-top-off = <0x00061000>;
+ qcom,sde-dest-scaler-top-size = <0x1c>;
+ qcom,sde-dest-scaler-off = <0x800 0x1000>;
+ qcom,sde-dest-scaler-size = <0x800>;
+
+ qcom,sde-wb-off = <0x66000>;
+ qcom,sde-wb-size = <0x2c8>;
+ qcom,sde-wb-xin-id = <6>;
+ qcom,sde-wb-id = <2>;
+ qcom,sde-wb-clk-ctrl = <0x2bc 16>;
+
+ qcom,sde-intf-off = <0x6b000 0x6b800
+ 0x6c000 0x6c800>;
+ qcom,sde-intf-size = <0x2b8>;
+ qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
+
+ qcom,sde-pp-off = <0x71000 0x71800
+ 0x72000 0x72800 0x73000 0x73800>;
+ qcom,sde-pp-slave = <0x0 0x0 0x0 0x0 0x0 0x0>;
+ qcom,sde-pp-size = <0xd4>;
+ qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1 0x2 0x2>;
+
+ qcom,sde-merge-3d-off = <0x84000 0x84100 0x84200>;
+ qcom,sde-merge-3d-size = <0x100>;
+
+ qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0 0x0 0x0>;
+
+ qcom,sde-cdm-off = <0x7a200>;
+ qcom,sde-cdm-size = <0x224>;
+
+ qcom,sde-dsc-off = <0x81000 0x81400 0x81800 0x81c00>;
+ qcom,sde-dsc-size = <0x140>;
+ qcom,sde-dsc-pair-mask = <2 1 4 3>;
+ qcom,sde-dsc-linewidth = <2048>;
+
+ qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0
+ 0x30e0 0x30e0 0x30e0>;
+ qcom,sde-dither-version = <0x00010000>;
+ qcom,sde-dither-size = <0x20>;
+
+ qcom,sde-sspp-type = "vig", "vig", "vig", "vig",
+ "dma", "dma", "dma", "dma";
+
+ qcom,sde-sspp-off = <0x5000 0x7000 0x9000 0xb000
+ 0x25000 0x27000 0x29000 0x2b000>;
+ qcom,sde-sspp-src-size = <0x1f8>;
+
+ qcom,sde-sspp-xin-id = <0 4 8 12
+ 1 5 9 13>;
+ qcom,sde-sspp-excl-rect = <1 1 1 1
+ 1 1 1 1>;
+ qcom,sde-sspp-smart-dma-priority = <5 6 7 8 1 2 3 4>;
+ qcom,sde-smart-dma-rev = "smart_dma_v2p5";
+
+ qcom,sde-mixer-pair-mask = <2 1 4 3 6 5>;
+
+ qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
+ 0xb0 0xc8 0xe0 0xf8 0x110>;
+
+ qcom,sde-max-per-pipe-bw-kbps = <4400000 4400000
+ 4400000 4400000
+ 4400000 4400000
+ 4400000 4400000>;
+
+ qcom,sde-max-per-pipe-bw-high-kbps = <5300000 5300000
+ 5300000 5300000
+ 5300000 5300000
+ 5300000 5300000>;
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+ qcom,sde-sspp-clk-ctrl =
+ <0x2ac 0>, <0x2b4 0>, <0x2bc 0>, <0x2c4 0>,
+ <0x2ac 8>, <0x2b4 8>, <0x2bc 8>, <0x2c4 8>;
+ qcom,sde-sspp-csc-off = <0x1a00>;
+ qcom,sde-csc-type = "csc-10bit";
+ qcom,sde-qseed-type = "qseedv3lite";
+ qcom,sde-sspp-qseed-off = <0xa00>;
+ qcom,sde-mixer-linewidth = <2560>;
+ qcom,sde-sspp-linewidth = <4096>;
+ qcom,sde-wb-linewidth = <4096>;
+ qcom,sde-mixer-blendstages = <0xb>;
+ qcom,sde-highest-bank-bit = <0x3>;
+ qcom,sde-ubwc-version = <0x400>;
+ qcom,sde-ubwc-swizzle = <0x6>;
+ qcom,sde-ubwc-bw-calc-version = <0x1>;
+ qcom,sde-ubwc-static = <0x1>;
+ qcom,sde-macrotile-mode = <0x1>;
+ qcom,sde-smart-panel-align-mode = <0xc>;
+ qcom,sde-panic-per-pipe;
+ qcom,sde-has-cdp;
+ qcom,sde-has-src-split;
+ qcom,sde-pipe-order-version = <0x1>;
+ qcom,sde-has-dim-layer;
+ qcom,sde-has-dest-scaler;
+ qcom,sde-has-idle-pc;
+ qcom,sde-max-dest-scaler-input-linewidth = <2048>;
+ qcom,sde-max-dest-scaler-output-linewidth = <2560>;
+ qcom,sde-max-bw-low-kbps = <13700000>;
+ qcom,sde-max-bw-high-kbps = <16600000>;
+ qcom,sde-min-core-ib-kbps = <4800000>;
+ qcom,sde-min-llcc-ib-kbps = <0>;
+ qcom,sde-min-dram-ib-kbps = <800000>;
+ qcom,sde-dram-channels = <2>;
+ qcom,sde-num-nrt-paths = <0>;
+ qcom,sde-dspp-ltm-version = <0x00010000>;
+ /* offsets are based off dspp 0 and dspp 1 */
+ qcom,sde-dspp-ltm-off = <0x2a000 0x28100>;
+
+ qcom,sde-uidle-off = <0x80000>;
+ qcom,sde-uidle-size = <0x70>;
+
+ qcom,sde-vbif-off = <0>;
+ qcom,sde-vbif-size = <0x1040>;
+ qcom,sde-vbif-id = <0>;
+ qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
+
+ qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
+ qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;
+ qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>;
+
+ /* macrotile & macrotile-qseed has the same configs */
+ qcom,sde-danger-lut = <0x000000ff 0x0000ffff
+ 0x00000000 0x00000000 0x0000ffff>;
+
+ qcom,sde-safe-lut-linear = <0 0xfff0>;
+ qcom,sde-safe-lut-macrotile = <0 0xff00>;
+ /* same as safe-lut-macrotile */
+ qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>;
+ qcom,sde-safe-lut-nrt = <0 0xffff>;
+ qcom,sde-safe-lut-cwb = <0 0x3ff>;
+
+ qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;
+ qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;
+ qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;
+ qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;
+ qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>;
+
+ qcom,sde-cdp-setting = <1 1>, <1 0>;
+
+ qcom,sde-qos-cpu-mask = <0x3>;
+ qcom,sde-qos-cpu-dma-latency = <300>;
+ qcom,sde-qos-cpu-irq-latency = <300>;
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+
+ qcom,sde-reg-dma-off = <0>;
+ qcom,sde-reg-dma-version = <0x00010002>;
+ qcom,sde-reg-dma-trigger-off = <0x119c>;
+ qcom,sde-reg-dma-xin-id = <7>;
+ qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
+
+ qcom,sde-secure-sid-mask = <0x4000821>;
+
+ qcom,sde-sspp-vig-blocks {
+ qcom,sde-vig-csc-off = <0x1a00>;
+ qcom,sde-vig-qseed-off = <0xa00>;
+ qcom,sde-vig-qseed-size = <0xa0>;
+ qcom,sde-vig-gamut = <0x1d00 0x00060000>;
+ qcom,sde-vig-igc = <0x1d00 0x00060000>;
+ qcom,sde-vig-inverse-pma;
+ };
+
+ qcom,sde-sspp-dma-blocks {
+ dgm@0 {
+ qcom,sde-dma-igc = <0x400 0x00050000>;
+ qcom,sde-dma-gc = <0x600 0x00050000>;
+ qcom,sde-dma-inverse-pma;
+ qcom,sde-dma-csc-off = <0x200>;
+ };
+
+ dgm@1 {
+ qcom,sde-dma-igc = <0x1400 0x00050000>;
+ qcom,sde-dma-gc = <0x600 0x00050000>;
+ qcom,sde-dma-inverse-pma;
+ qcom,sde-dma-csc-off = <0x1200>;
+ };
+ };
+
+ qcom,sde-dspp-blocks {
+ qcom,sde-dspp-igc = <0x0 0x00030001>;
+ qcom,sde-dspp-hsic = <0x800 0x00010007>;
+ qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+ qcom,sde-dspp-hist = <0x800 0x00010007>;
+ qcom,sde-dspp-sixzone= <0x900 0x00010007>;
+ qcom,sde-dspp-vlut = <0xa00 0x00010008>;
+ qcom,sde-dspp-gamut = <0x1000 0x00040002>;
+ qcom,sde-dspp-pcc = <0x1700 0x00040000>;
+ qcom,sde-dspp-gc = <0x17c0 0x00010008>;
+ qcom,sde-dspp-dither = <0x82c 0x00010007>;
+ };
+
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "mmcx";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
+ compatible = "qcom,smmu_sde_unsec";
+ iommus = <&apps_smmu 0x820 0x402>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-earlymap; /* for cont-splash */
+ };
+
+ smmu_sde_sec: qcom,smmu_sde_sec_cb {
+ compatible = "qcom,smmu_sde_sec";
+ iommus = <&apps_smmu 0x821 0x400>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xa>;
+ };
+
+ /* data and reg bus scale settings */
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "mdss_sde";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>, <23 512 0 0>,
+ <22 512 0 6400000>, <23 512 0 6400000>,
+ <22 512 0 6400000>, <23 512 0 6400000>;
+ };
+
+ qcom,sde-reg-bus {
+ qcom,msm-bus,name = "mdss_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 150000>,
+ <1 590 0 300000>;
+ };
+ qcom,sde-limits {
+ qcom,sde-linewidth-limits {
+ qcom,sde-limit-name = "sspp_linewidth_usecases";
+ qcom,sde-limit-cases = "vig", "dma", "scale", "inline_rot";
+ qcom,sde-limit-ids= <0x1 0x2 0x4 0x8>;
+ qcom,sde-limit-values = <0x1 4096>,
+ <0x5 2560>,
+ <0x2 4096>,
+ <0x9 1088>;
+ };
+
+ qcom,sde-bw-limits {
+ qcom,sde-limit-name = "sde_bwlimit_usecases";
+ qcom,sde-limit-cases = "per_vig_pipe",
+ "per_dma_pipe",
+ "total_max_bw",
+ "camera_concurrency",
+ "cwb_concurrency";
+ qcom,sde-limit-ids = <0x1 0x2 0x4 0x8 0x10>;
+ qcom,sde-limit-values = <0x1 5300000>,
+ <0x11 5300000>,
+ <0x9 4400000>,
+ <0x19 4400000>,
+ <0x2 5300000>,
+ <0x12 5300000>,
+ <0xa 4400000>,
+ <0x1a 4400000>,
+ <0x4 16600000>,
+ <0x14 16600000>,
+ <0xc 13700000>,
+ <0x1c 13700000>;
+ };
+ };
+ };
+
+ sde_dp: qcom,dp_display@ae90000 {
+ cell-index = <0>;
+ compatible = "qcom,dp-display";
+
+ vdda-1p2-supply = <&pm8150_l9>;
+ vdda-0p9-supply = <&pm8150_l18>;
+
+ reg = <0xae90000 0x0dc>,
+ <0xae90200 0x0c0>,
+ <0xae90400 0x508>,
+ <0xae91000 0x094>,
+ <0x88eaa00 0x200>,
+ <0x88ea200 0x200>,
+ <0x88ea600 0x200>,
+ <0xaf02000 0x1a0>,
+ <0x88ea040 0x10>,
+ <0x88e8000 0x20>,
+ <0x0aee1000 0x034>,
+ <0xae91400 0x094>;
+ /* dp_ctrl: dp_ahb, dp_aux, dp_link, dp_p0 */
+ reg-names = "dp_ahb", "dp_aux", "dp_link",
+ "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
+ "dp_mmss_cc", "dp_pll",
+ "usb3_dp_com", "hdcp_physical", "dp_p1";
+
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <12 0>;
+
+ clocks = <&clock_dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
+ <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
+ <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
+ <&clock_dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
+ clock-names = "core_aux_clk", "core_usb_ref_clk_src",
+ "core_usb_pipe_clk", "link_clk", "link_iface_clk",
+ "pixel_clk_rcg", "pixel_parent",
+ "pixel1_clk_rcg", "pixel1_parent",
+ "strm0_pixel_clk", "strm1_pixel_clk";
+
+ qcom,phy-version = <0x420>;
+ qcom,aux-cfg0-settings = [20 00];
+ qcom,aux-cfg1-settings = [24 13];
+ qcom,aux-cfg2-settings = [28 A4];
+ qcom,aux-cfg3-settings = [2c 00];
+ qcom,aux-cfg4-settings = [30 0a];
+ qcom,aux-cfg5-settings = [34 26];
+ qcom,aux-cfg6-settings = [38 0a];
+ qcom,aux-cfg7-settings = [3c 03];
+ qcom,aux-cfg8-settings = [40 b7];
+ qcom,aux-cfg9-settings = [44 03];
+
+ qcom,max-pclk-frequency-khz = <675000>;
+
+ qcom,mst-enable;
+ qcom,widebus-enable;
+ qcom,dsc-feature-enable;
+ qcom,fec-feature-enable;
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1200000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <33000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <912000>;
+ qcom,supply-max-voltage = <912000>;
+ qcom,supply-enable-load = <126000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ sde_rscc: qcom,sde_rscc@af20000 {
+ cell-index = <0>;
+ compatible = "qcom,sde-rsc";
+ reg = <0xaf20000 0x3c50>,
+ <0xaf30000 0x3fd4>;
+ reg-names = "drv", "wrapper";
+ qcom,sde-rsc-version = <3>;
+
+ qcom,sde-dram-channels = <2>;
+
+ vdd-supply = <&mdss_core_gdsc>;
+ clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
+ clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
+
+ /* data and reg bus scale settings */
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "disp_rsc_mnoc_llcc";
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <20003 20513 0 0>, <20004 20513 0 0>,
+ <20003 20513 0 6400000>, <20004 20513 0 6400000>,
+ <20003 20513 0 6400000>, <20004 20513 0 6400000>;
+ };
+
+ qcom,sde-ebi-bus {
+ qcom,msm-bus,name = "disp_rsc_ebi";
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <20000 20512 0 0>,
+ <20000 20512 0 6400000>,
+ <20000 20512 0 6400000>;
+ };
+
+ qcom,sde-reg-bus {
+ qcom,msm-bus,name = "disp_rsc_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 150000>,
+ <1 590 0 300000>;
+ };
+ };
+
+ mdss_rotator: qcom,mdss_rotator@aea8800 {
+ compatible = "qcom,sde_rotator";
+ reg = <0x0ae00000 0xac000>,
+ <0x0aeb8000 0x3000>;
+ reg-names = "mdp_phys",
+ "rot_vbif_phys";
+ status = "disabled";
+
+ #list-cells = <1>;
+
+ qcom,mdss-rot-mode = <1>;
+ qcom,mdss-highest-bank-bit = <0x3>;
+
+ /* Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_rotator";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <25 512 0 0>,
+ <25 512 0 6400000>,
+ <25 512 0 6400000>;
+
+ rot-vdd-supply = <&mdss_core_gdsc>;
+ qcom,supply-names = "rot-vdd";
+
+ clocks =
+ <&clock_gcc GCC_DISP_AHB_CLK>,
+ <&clock_gcc GCC_DISP_SF_AXI_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_ROT_CLK>;
+ clock-names = "gcc_iface", "gcc_bus",
+ "iface_clk", "rot_clk";
+
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <2 0>;
+
+ power-domains = <&mdss_mdp>;
+
+ /* Offline rotator QoS setting */
+ qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
+ qcom,mdss-rot-vbif-memtype = <3 3>;
+ qcom,mdss-rot-cdp-setting = <1 1>;
+ qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
+ qcom,mdss-rot-danger-lut = <0x0 0x0>;
+ qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
+
+ qcom,mdss-default-ot-rd-limit = <32>;
+ qcom,mdss-default-ot-wr-limit = <32>;
+
+ qcom,mdss-sbuf-headroom = <20>;
+
+ /* reg bus scale settings */
+ rot_reg: qcom,rot-reg-bus {
+ qcom,msm-bus,name = "mdss_rot_reg";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>;
+ };
+
+ smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
+ compatible = "qcom,smmu_sde_rot_unsec";
+ iommus = <&apps_smmu 0x215C 0x0400>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ };
+ };
+
+ mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
+ compatible = "qcom,dsi-ctrl-hw-v2.4";
+ label = "dsi-ctrl-0";
+ cell-index = <0>;
+ frame-threshold-time-us = <800>;
+ reg = <0xae94000 0x400>,
+ <0xaf08000 0x4>;
+ reg-names = "dsi_ctrl", "disp_cc_base";
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <4 0>;
+ vdda-1p2-supply = <&pm8150_l9>;
+ refgen-supply = <&refgen>;
+ clocks = <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&clock_dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+ <&clock_dispcc DISP_CC_MDSS_ESC0_CLK>;
+ clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+ "pixel_clk", "pixel_clk_rcg", "esc_clk";
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1200000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <26700>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi1: qcom,mdss_dsi_ctrl1@ae96000 {
+ compatible = "qcom,dsi-ctrl-hw-v2.4";
+ label = "dsi-ctrl-1";
+ cell-index = <1>;
+ frame-threshold-time-us = <800>;
+ reg = <0xae96000 0x400>,
+ <0xaf08000 0x4>;
+ reg-names = "dsi_ctrl", "disp_cc_base";
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <5 0>;
+ vdda-1p2-supply = <&pm8150_l9>;
+ refgen-supply = <&refgen>;
+ clocks = <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&clock_dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK>,
+ <&clock_dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
+ <&clock_dispcc DISP_CC_MDSS_ESC1_CLK>;
+ clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+ "pixel_clk", "pixel_clk_rcg", "esc_clk";
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1200000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <26700>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94400 {
+ compatible = "qcom,dsi-phy-v4.1";
+ label = "dsi-phy-0";
+ cell-index = <0>;
+ reg = <0xae94400 0x7c0>,
+ <0xae94200 0x100>;
+ reg-names = "dsi_phy", "dyn_refresh_base";
+ vdda-0p9-supply = <&pm8150_l5>;
+ qcom,platform-strength-ctrl = [55 03
+ 55 03
+ 55 03
+ 55 03
+ 55 00];
+ qcom,platform-lane-config = [00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 8a 8a];
+ qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <880000>;
+ qcom,supply-max-voltage = <880000>;
+ qcom,supply-enable-load = <46000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi_phy1: qcom,mdss_dsi_phy1@ae96400 {
+ compatible = "qcom,dsi-phy-v4.1";
+ label = "dsi-phy-1";
+ cell-index = <1>;
+ reg = <0xae96400 0x7c0>,
+ <0xae96200 0x100>;
+ reg-names = "dsi_phy", "dyn_refresh_base";
+ vdda-0p9-supply = <&pm8150_l5>;
+ qcom,platform-strength-ctrl = [55 03
+ 55 03
+ 55 03
+ 55 03
+ 55 00];
+ qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+ qcom,platform-lane-config = [00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 8a 8a];
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <880000>;
+ qcom,supply-max-voltage = <880000>;
+ qcom,supply-enable-load = <46000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-smp2p.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-smp2p.dtsi
new file mode 100755
index 0000000..11b8f95
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-smp2p.dtsi
@@ -0,0 +1,133 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
+
+&soc {
+
+ qcom,smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
+ qcom,entry-name = "rdbg";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
+ qcom,entry-name = "rdbg";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p-dsps {
+ compatible = "qcom,smp2p";
+ qcom,smem = <481>, <430>;
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <3>;
+
+ dsps_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ dsps_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sleepstate_smp2p_out: sleepstate-out {
+ qcom,entry-name = "sleepstate";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ sleepstate_smp2p_in: qcom,sleepstate-in {
+ qcom,entry-name = "sleepstate_see";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_qvrexternal5_out: qcom,smp2p-qvrexternal5-out {
+ qcom,entry-name = "qvrexternal";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
+ qcom,entry-name = "rdbg";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
+ qcom,entry-name = "rdbg";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p-npu {
+ compatible = "qcom,smp2p";
+ qcom,smem = <617>, <616>;
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&msm_npu IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <10>;
+
+ npu_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ npu_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-thermal-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-thermal-overlay.dtsi
new file mode 100755
index 0000000..4d8cb9a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-thermal-overlay.dtsi
@@ -0,0 +1,130 @@
+#include <dt-bindings/thermal/thermal.h>
+
+&mdss_mdp {
+ #cooling-cells = <2>;
+};
+
+&thermal_zones {
+ soc {
+ cooling-maps {
+ soc_cpu4 {
+ trip = <&soc_trip>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+
+ soc_cpu5 {
+ trip = <&soc_trip>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+
+ soc_cpu6 {
+ trip = <&soc_trip>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ soc_cpu7 {
+ trip = <&soc_trip>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pm8150b-bcl-lvl0 {
+ cooling-maps {
+ vbat_cpu4 {
+ trip = <&b_bcl_lvl0>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+
+ vbat_cpu5 {
+ trip = <&b_bcl_lvl0>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+
+ vbat_gpu0 {
+ trip = <&b_bcl_lvl0>;
+ cooling-device = <&msm_gpu 2 2>;
+ };
+ };
+ };
+
+ pm8150b-bcl-lvl1 {
+ cooling-maps {
+ vbat_cpu6 {
+ trip = <&b_bcl_lvl1>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ vbat_cpu7 {
+ trip = <&b_bcl_lvl1>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+
+ vbat_gpu1 {
+ trip = <&b_bcl_lvl1>;
+ cooling-device = <&msm_gpu 4 4>;
+ };
+ };
+ };
+
+ pm8150b-bcl-lvl2 {
+ cooling-maps {
+ vbat_gpu2 {
+ trip = <&b_bcl_lvl2>;
+ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+
+ pm8150l-bcl-lvl0 {
+ disable-thermal-zone;
+ cooling-maps {
+ vph_cpu4 {
+ trip = <&l_bcl_lvl0>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+
+ vph_cpu5 {
+ trip = <&l_bcl_lvl0>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+
+ vph_gpu0 {
+ trip = <&l_bcl_lvl0>;
+ cooling-device = <&msm_gpu 2 2>;
+ };
+ };
+ };
+
+ pm8150l-bcl-lvl1 {
+ disable-thermal-zone;
+ cooling-maps {
+ vph_cpu6 {
+ trip = <&l_bcl_lvl1>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ vph_cpu7 {
+ trip = <&l_bcl_lvl1>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+
+ vph_gpu1 {
+ trip = <&l_bcl_lvl1>;
+ cooling-device = <&msm_gpu 4 4>;
+ };
+ };
+ };
+
+ pm8150l-bcl-lvl2 {
+ disable-thermal-zone;
+ cooling-maps {
+ vph_gpu2 {
+ trip = <&l_bcl_lvl2>;
+ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-thermal.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-thermal.dtsi
new file mode 100755
index 0000000..318d2a3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-thermal.dtsi
@@ -0,0 +1,1674 @@
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/thermal/qmi_thermal.h>
+
+&cpufreq_hw {
+ qcom,cpu-isolation {
+ compatible = "qcom,cpu-isolate";
+ cpu0_isolate: cpu0-isolate {
+ qcom,cpu = <&CPU0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1_isolate: cpu1-isolate {
+ qcom,cpu = <&CPU1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2_isolate: cpu2-isolate {
+ qcom,cpu = <&CPU2>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3_isolate: cpu3-isolate {
+ qcom,cpu = <&CPU3>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4_isolate: cpu4-isolate {
+ qcom,cpu = <&CPU4>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5_isolate: cpu5-isolate {
+ qcom,cpu = <&CPU5>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6_isolate: cpu6-isolate {
+ qcom,cpu = <&CPU6>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7_isolate: cpu7-isolate {
+ qcom,cpu = <&CPU7>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ qcom,limits-dcvs {
+ compatible = "qcom,msm-hw-limits";
+ isens_vref_0p8-supply = <&pm8150_l5_ao>;
+ isens-vref-0p8-settings = <880000 880000 20000>;
+ isens_vref_1p8-supply = <&pm8150_l12_ao>;
+ isens-vref-1p8-settings = <1800000 1800000 20000>;
+ };
+};
+
+&soc {
+ qmi-tmd-devices {
+ compatible = "qcom,qmi-cooling-devices";
+
+ modem {
+ qcom,instance-id = <QMI_MODEM_NR_INST_ID>;
+
+ modem_pa: modem_pa {
+ qcom,qmi-dev-name = "pa";
+ #cooling-cells = <2>;
+ };
+
+ modem_pa_fr1: modem_pa_fr1 {
+ qcom,qmi-dev-name = "pa_fr1";
+ #cooling-cells = <2>;
+ };
+
+ modem_tj: modem_tj {
+ qcom,qmi-dev-name = "modem";
+ #cooling-cells = <2>;
+ };
+
+ modem_current: modem_current {
+ qcom,qmi-dev-name = "modem_current";
+ #cooling-cells = <2>;
+ };
+
+ modem_skin: modem_skin {
+ qcom,qmi-dev-name = "modem_skin";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw_skin0: modem_mmw_skin0 {
+ qcom,qmi-dev-name = "mmw_skin0";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw_skin1: modem_mmw_skin1 {
+ qcom,qmi-dev-name = "mmw_skin1";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw_skin2: modem_mmw_skin2 {
+ qcom,qmi-dev-name = "mmw_skin2";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw_skin3: modem_mmw_skin3 {
+ qcom,qmi-dev-name = "mmw_skin3";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw0: modem_mmw0 {
+ qcom,qmi-dev-name = "mmw0";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw1: modem_mmw1 {
+ qcom,qmi-dev-name = "mmw1";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw2: modem_mmw2 {
+ qcom,qmi-dev-name = "mmw2";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw3: modem_mmw3 {
+ qcom,qmi-dev-name = "mmw3";
+ #cooling-cells = <2>;
+ };
+
+ modem_bcl: modem_bcl {
+ qcom,qmi-dev-name = "vbatt_low";
+ #cooling-cells = <2>;
+ };
+
+ modem_charge_state: modem_charge_state {
+ qcom,qmi-dev-name = "charge_state";
+ #cooling-cells = <2>;
+ };
+ };
+ };
+
+ qmi_sensor: qmi-ts-sensors {
+ compatible = "qcom,qmi-sensors";
+ #thermal-sensor-cells = <1>;
+
+ modem {
+ qcom,instance-id = <QMI_MODEM_NR_INST_ID>;
+ qcom,qmi-sensor-names = "pa",
+ "pa_1",
+ "qfe_wtr0",
+ "modem_tsens",
+ "qfe_mmw0",
+ "qfe_mmw1",
+ "qfe_mmw2",
+ "qfe_mmw3",
+ "xo_therm",
+ "qfe_mmw_streamer0",
+ "qfe_mmw0_mod",
+ "qfe_mmw1_mod",
+ "qfe_mmw2_mod",
+ "qfe_mmw3_mod",
+ "qfe_ret_pa0",
+ "qfe_wtr_pa0",
+ "qfe_wtr_pa1",
+ "qfe_wtr_pa2",
+ "qfe_wtr_pa3",
+ "sys_therm1",
+ "sys_therm2",
+ "modem_tsens1";
+ };
+ };
+
+ lmh_isense_cdsp {
+ compatible = "qcom,msm-limits-cdsp";
+ };
+};
+
+&thermal_zones {
+ aoss0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 0>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 1>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 3>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 4>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 5>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 6>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 7>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 8>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 9>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 10>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-4-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 11>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-5-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 12>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-6-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 13>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-7-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 14>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 15>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ aoss-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 0>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cwlan-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 1>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ video-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 2>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ ddr-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 3>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ q6-hvx-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 4>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 5>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cmpss-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 6>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ npu-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 7>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens1 8>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ active-config1 {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-max-step {
+ polling-delay-passive = <10>;
+ polling-delay = <100>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ gpu_trip0: gpu-trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ gpu_cdev {
+ trip = <&gpu_trip0>;
+ cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ apc-0-max-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ silver-trip {
+ temperature = <120000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+
+ apc-1-max-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ gold-trip {
+ temperature = <120000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+
+ pop-mem-step {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 3>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ pop_trip: pop-trip {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ pop_cdev4 {
+ trip = <&pop_trip>;
+ cooling-device =
+ <&CPU4 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+
+ pop_cdev7 {
+ trip = <&pop_trip>;
+ cooling-device =
+ <&CPU7 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu-0-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 1>;
+ wake-capable-sensor;
+ trips {
+ cpu00_config: cpu00-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu00_cdev {
+ trip = <&cpu00_config>;
+ cooling-device = <&cpu0_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 2>;
+ wake-capable-sensor;
+ trips {
+ cpu01_config: cpu01-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu01_cdev {
+ trip = <&cpu01_config>;
+ cooling-device = <&cpu1_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-2-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 3>;
+ wake-capable-sensor;
+ trips {
+ cpu02_config: cpu02-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu02_cdev {
+ trip = <&cpu02_config>;
+ cooling-device = <&cpu2_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-3-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 4>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu03_config: cpu03-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu03_cdev {
+ trip = <&cpu03_config>;
+ cooling-device = <&cpu3_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 7>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpufreq_10_config: cpufreq-10-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu10_config: cpu10-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_10_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu10_cdev {
+ trip = <&cpu10_config>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 8>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpufreq_11_config: cpufreq-11-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu11_config: cpu11-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_11_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu11_cdev {
+ trip = <&cpu11_config>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-2-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 9>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpufreq_12_config: cpufreq-12-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu12_config: cpu12-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_12_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu12_cdev {
+ trip = <&cpu12_config>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-3-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 10>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpufreq_13_config: cpufreq-13-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu13_config: cpu13-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_13_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu13_cdev {
+ trip = <&cpu13_config>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-4-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 11>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpufreq_14_config: cpufreq-14-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu14_config: cpu14-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_14_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu14_cdev {
+ trip = <&cpu14_config>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-5-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 12>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpufreq_15_config: cpufreq-15-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu15_config: cpu15-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_15_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu15_cdev {
+ trip = <&cpu15_config>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-6-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 13>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpufreq_16_config: cpufreq-16-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu16_config: cpu16-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_16_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu16_cdev {
+ trip = <&cpu16_config>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-7-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 14>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpufreq_17_config: cpufreq-17-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu17_config: cpu17-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_17_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu17_cdev {
+ trip = <&cpu17_config>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ cwlan-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 1>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cwlan_trip0: cwlan-trip0 {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev {
+ trip = <&cwlan_trip0>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&cwlan_trip0>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&cwlan_trip0>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&cwlan_trip0>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&cwlan_trip0>;
+ cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+ };
+ };
+
+ video-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 2>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ video_trip0: video-trip0 {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev {
+ trip = <&video_trip0>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&video_trip0>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&video_trip0>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&video_trip0>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&video_trip0>;
+ cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+ };
+ };
+
+ ddr-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 3>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ ddr_trip0: ddr-trip0 {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev {
+ trip = <&ddr_trip0>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&ddr_trip0>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&ddr_trip0>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&ddr_trip0>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&ddr_trip0>;
+ cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+ };
+ };
+
+ q6-hvx-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 4>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ q6_hvx_trip0: q6-hvx-trip0 {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev {
+ trip = <&q6_hvx_trip0>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&q6_hvx_trip0>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&q6_hvx_trip0>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&q6_hvx_trip0>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&q6_hvx_trip0>;
+ cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+ };
+ };
+
+ camera-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 5>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ camera_trip0: camera-trip0 {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev {
+ trip = <&camera_trip0>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&camera_trip0>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&camera_trip0>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&camera_trip0>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&camera_trip0>;
+ cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+ };
+ };
+
+ cmpss-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 6>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cmpss_trip0: cmpss-trip0 {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev {
+ trip = <&cmpss_trip0>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&cmpss_trip0>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&cmpss_trip0>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&cmpss_trip0>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&cmpss_trip0>;
+ cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+ };
+ };
+
+ npu-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 7>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ npu_trip0: npu-trip0 {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev {
+ trip = <&npu_trip0>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&npu_trip0>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&npu_trip0>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&npu_trip0>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&npu_trip0>;
+ cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+ };
+ };
+
+ modem-lte-sub6-pa1 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_PA)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-lte-sub6-pa2 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_PA_1)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_0)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_1)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_2)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_3)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-skin-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_XO_THERM)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-wifi-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_SYS_THERM_1)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-ambient-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_SYS_THERM_2)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_MODEM_TSENS)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_MODEM_TSENS_1)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-streamer-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_STREAMER_0)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw0-mod-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_0_MOD)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw1-mod-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_1_MOD)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw2-mod-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_2_MOD)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw3-mod-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_NR_INST_ID+QMI_QFE_MMW_3_MOD)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-usb.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-usb.dtsi
new file mode 100755
index 0000000..f03520c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-usb.dtsi
@@ -0,0 +1,595 @@
+#include <dt-bindings/clock/qcom,gcc-kona.h>
+#include <dt-bindings/phy/qcom,kona-qmp-usb3.h>
+
+&soc {
+ /* Primary USB port related controller */
+ usb0: ssusb@a600000 {
+ compatible = "qcom,dwc-usb3-msm";
+ reg = <0x0a600000 0x100000>;
+ reg-names = "core_base";
+
+ iommus = <&apps_smmu 0x0 0x0>;
+ qcom,iommu-dma = "atomic";
+ qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
+ <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 15 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+ "ss_phy_irq", "dm_hs_phy_irq";
+ qcom,use-pdc-interrupts;
+
+ USB3_GDSC-supply = <&usb30_prim_gdsc>;
+ dpdm-supply = <&usb2_phy0>;
+ clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ /*
+ * GCC_USB3_SEC_CLKREF_EN provides ref_clk for both
+ * USB instances.
+ */
+ <&clock_gcc GCC_USB3_SEC_CLKREF_EN>;
+ clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+ "utmi_clk", "sleep_clk", "xo";
+
+ resets = <&clock_gcc GCC_USB30_PRIM_BCR>;
+ reset-names = "core_reset";
+
+ qcom,core-clk-rate = <200000000>;
+ qcom,core-clk-rate-hs = <66666667>;
+ qcom,num-gsi-evt-buffs = <0x3>;
+ qcom,gsi-reg-offset =
+ <0x0fc /* GSI_GENERAL_CFG */
+ 0x110 /* GSI_DBL_ADDR_L */
+ 0x120 /* GSI_DBL_ADDR_H */
+ 0x130 /* GSI_RING_BASE_ADDR_L */
+ 0x144 /* GSI_RING_BASE_ADDR_H */
+ 0x1a4>; /* GSI_IF_STS */
+ qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
+
+ qcom,msm-bus,name = "usb0";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ /* suspend vote */
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>,
+
+ /* nominal vote */
+ <MSM_BUS_MASTER_USB3
+ MSM_BUS_SLAVE_EBI_CH0 1000000 2500000>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+ /* svs vote */
+ <MSM_BUS_MASTER_USB3
+ MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+ /* min vote */
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 1 1>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 1 1>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 1 1>;
+
+ dwc3@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0a600000 0xd93c>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;
+ linux,sysdev_is_parent;
+ snps,disable-clk-gating;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3-u1u2-disable;
+ usb-core-id = <0>;
+ tx-fifo-resize;
+ maximum-speed = "super-speed-plus";
+ dr_mode = "drd";
+ };
+
+ qcom,usbbam@a704000 {
+ compatible = "qcom,usb-bam-msm";
+ reg = <0xa704000 0x17000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+
+ qcom,usb-bam-fifo-baseaddr = <0x146bb000>;
+ qcom,usb-bam-num-pipes = <4>;
+ qcom,disable-clk-gating;
+ qcom,usb-bam-override-threshold = <0x4001>;
+ qcom,usb-bam-max-mbps-highspeed = <400>;
+ qcom,usb-bam-max-mbps-superspeed = <3600>;
+ qcom,reset-bam-on-connect;
+
+ qcom,pipe0 {
+ label = "ssusb-qdss-in-0";
+ qcom,usb-bam-mem-type = <2>;
+ qcom,dir = <1>;
+ qcom,pipe-num = <0>;
+ qcom,peer-bam = <0>;
+ qcom,peer-bam-physical-address = <0x6064000>;
+ qcom,src-bam-pipe-index = <0>;
+ qcom,dst-bam-pipe-index = <0>;
+ qcom,data-fifo-offset = <0x0>;
+ qcom,data-fifo-size = <0x1800>;
+ qcom,descriptor-fifo-offset = <0x1800>;
+ qcom,descriptor-fifo-size = <0x800>;
+ };
+ };
+ };
+
+ /* Primary USB port related High Speed PHY */
+ usb2_phy0: hsphy@88e3000 {
+ compatible = "qcom,usb-hsphy-snps-femto";
+ reg = <0x88e3000 0x110>,
+ <0x088e2000 0x4>;
+ reg-names = "hsusb_phy_base",
+ "eud_enable_reg";
+
+ vdd-supply = <&pm8150_l5>;
+ vdda18-supply = <&pm8150_l12>;
+ vdda33-supply = <&pm8150_l2>;
+ qcom,vdd-voltage-level = <0 880000 880000>;
+
+ clocks = <&clock_rpmh RPMH_CXO_CLK>;
+ clock-names = "ref_clk_src";
+
+ resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;
+ reset-names = "phy_reset";
+ qcom,param-override-seq = <0x43 0x70>;
+ };
+
+ /* Primary USB port related QMP USB DP Combo PHY */
+ usb_qmp_dp_phy: ssphy@88e8000 {
+ compatible = "qcom,usb-ssphy-qmp-dp-combo";
+ reg = <0x88e8000 0x3000>;
+ reg-names = "qmp_phy_base";
+
+ vdd-supply = <&pm8150_l18>;
+ qcom,vdd-voltage-level = <0 912000 912000>;
+ qcom,vdd-max-load-uA = <47000>;
+ core-supply = <&pm8150_l9>;
+ qcom,vbus-valid-override;
+ qcom,qmp-phy-init-seq =
+ /* <reg_offset, value, delay> */
+ <USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
+ USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
+ USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
+ USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
+ USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
+ USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
+ USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
+ USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
+ USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0
+ USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
+ USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0
+ USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
+ USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
+ USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
+ USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
+ USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
+ USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
+ USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
+ USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
+ USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
+ USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
+ USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
+ USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
+ USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0
+ USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
+ USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
+ USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
+ USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0
+ USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
+ USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x60 0
+ USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x60 0
+ USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x11 0
+ USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x02 0
+ USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5 0
+ USB3_DP_QSERDES_TXA_LANE_MODE_2 0x00 0
+ USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
+ USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x40 0
+ USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09 0
+ USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0
+ USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
+ USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
+ USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
+ USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
+ USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
+ USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0
+ USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
+ USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0
+ USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0
+ USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
+ USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0C 0
+ USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
+ USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
+ USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
+ USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
+ USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
+ USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
+ USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
+ USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xFF 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7F 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7F 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x97 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x7B 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB4 0
+ USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
+ USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
+ USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
+ USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
+ USB3_DP_QSERDES_RXA_GM_CAL 0x1F 0
+ USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
+ USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x60 0
+ USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x60 0
+ USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x11 0
+ USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x02 0
+ USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5 0
+ USB3_DP_QSERDES_TXB_LANE_MODE_2 0x00 0
+ USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
+ USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x54 0
+ USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09 0
+ USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0
+ USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
+ USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
+ USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
+ USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
+ USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
+ USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0
+ USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
+ USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0
+ USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0
+ USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
+ USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0C 0
+ USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
+ USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
+ USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
+ USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
+ USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
+ USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
+ USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
+ USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xA6 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x7B 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB4 0
+ USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
+ USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
+ USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
+ USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
+ USB3_DP_QSERDES_RXB_GM_CAL 0x1F 0
+ USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
+ USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
+ USB3_DP_PCS_RX_SIGDET_LVL 0xA9 0
+ USB3_DP_PCS_CDR_RESET_TIME 0x0A 0
+ USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
+ USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
+ USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
+ USB3_DP_PCS_EQ_CONFIG1 0x4B 0
+ USB3_DP_PCS_EQ_CONFIG5 0x10 0
+ USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
+ USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
+ 0xffffffff 0xffffffff 0x00>;
+
+ qcom,qmp-phy-reg-offset =
+ <USB3_DP_PCS_PCS_STATUS1
+ USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
+ USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+ USB3_DP_PCS_POWER_DOWN_CONTROL
+ USB3_DP_PCS_SW_RESET
+ USB3_DP_PCS_START_CONTROL
+ 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
+ 0x2a18 /* USB3_DP_DP_PHY_PD_CTL */
+ USB3_DP_COM_POWER_DOWN_CTRL
+ USB3_DP_COM_SW_RESET
+ USB3_DP_COM_RESET_OVRD_CTRL
+ USB3_DP_COM_PHY_MODE_CTRL
+ USB3_DP_COM_TYPEC_CTRL
+ USB3_DP_COM_SWI_CTRL
+ USB3_DP_PCS_CLAMP_ENABLE>;
+
+ clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
+ <&clock_gcc USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+ "pipe_clk_ext_src", "ref_clk_src",
+ "com_aux_clk";
+
+ resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+ <&clock_gcc GCC_USB3_PHY_PRIM_BCR>;
+ reset-names = "global_phy_reset", "phy_reset";
+ };
+
+ usb_audio_qmi_dev {
+ compatible = "qcom,usb-audio-qmi-dev";
+ iommus = <&apps_smmu 0x180f 0x0>;
+ qcom,iommu-dma = "disabled";
+ qcom,usb-audio-stream-id = <0xf>;
+ qcom,usb-audio-intr-num = <2>;
+ };
+
+ usb_nop_phy: usb_nop_phy {
+ compatible = "usb-nop-xceiv";
+ };
+
+ /* Secondary USB port related controller */
+ usb1: ssusb@a800000 {
+ compatible = "qcom,dwc-usb3-msm";
+ reg = <0xa800000 0x100000>;
+ reg-names = "core_base";
+
+ iommus = <&apps_smmu 0x20 0x0>;
+ qcom,iommu-dma = "atomic";
+ qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
+ <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 13 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+ "ss_phy_irq", "dm_hs_phy_irq";
+ qcom,use-pdc-interrupts;
+
+ USB3_GDSC-supply = <&usb30_sec_gdsc>;
+ clocks = <&clock_gcc GCC_USB30_SEC_MASTER_CLK>,
+ <&clock_gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+ <&clock_gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+ <&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+ <&clock_gcc GCC_USB30_SEC_SLEEP_CLK>,
+ <&clock_gcc GCC_USB3_SEC_CLKREF_EN>;
+
+ clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+ "utmi_clk", "sleep_clk", "xo";
+
+ resets = <&clock_gcc GCC_USB30_SEC_BCR>;
+ reset-names = "core_reset";
+
+ qcom,core-clk-rate = <200000000>;
+ qcom,core-clk-rate-hs = <66666667>;
+ qcom,num-gsi-evt-buffs = <0x3>;
+ qcom,gsi-reg-offset =
+ <0x0fc /* GSI_GENERAL_CFG */
+ 0x110 /* GSI_DBL_ADDR_L */
+ 0x120 /* GSI_DBL_ADDR_H */
+ 0x130 /* GSI_RING_BASE_ADDR_L */
+ 0x144 /* GSI_RING_BASE_ADDR_H */
+ 0x1a4>; /* GSI_IF_STS */
+ qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
+ qcom,charging-disabled;
+
+ qcom,msm-bus,name = "usb1";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ /* suspend vote */
+ <MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3_1 0 0>,
+
+ /* nominal vote */
+ <MSM_BUS_MASTER_USB3_1
+ MSM_BUS_SLAVE_EBI_CH0 1000000 2500000>,
+ <MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3_1 0 40000>,
+
+ /* svs vote */
+ <MSM_BUS_MASTER_USB3_1
+ MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
+ <MSM_BUS_MASTER_USB3_1 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3_1 0 40000>;
+
+ dwc3@a800000 {
+ compatible = "snps,dwc3";
+ reg = <0xa800000 0xd93c>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ usb-phy = <&usb2_phy1>, <&usb_qmp_phy>;
+ linux,sysdev_is_parent;
+ snps,disable-clk-gating;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3_lpm_capable;
+ usb-core-id = <1>;
+ tx-fifo-resize;
+ maximum-speed = "super-speed";
+ dr_mode = "drd";
+ };
+ };
+
+ /* Primary USB port related High Speed PHY */
+ usb2_phy1: hsphy@88e4000 {
+ compatible = "qcom,usb-hsphy-snps-femto";
+ reg = <0x88e4000 0x110>;
+ reg-names = "hsusb_phy_base";
+
+ vdd-supply = <&pm8150_l5>;
+ vdda18-supply = <&pm8150_l12>;
+ vdda33-supply = <&pm8150_l2>;
+ qcom,vdd-voltage-level = <0 880000 880000>;
+
+ clocks = <&clock_rpmh RPMH_CXO_CLK>;
+ clock-names = "ref_clk_src";
+
+ resets = <&clock_gcc GCC_QUSB2PHY_SEC_BCR>;
+ reset-names = "phy_reset";
+ qcom,param-override-seq = <0x43 0x70>;
+ };
+
+ /* Secondary USB port related QMP PHY */
+ usb_qmp_phy: ssphy@88eb000 {
+ compatible = "qcom,usb-ssphy-qmp-v2";
+ reg = <0x88eb000 0x1000>,
+ <0x088eb88c 0x4>;
+ reg-names = "qmp_phy_base",
+ "pcs_clamp_enable_reg";
+
+ vdd-supply = <&pm8150_l18>;
+ qcom,vdd-voltage-level = <0 912000 912000>;
+ qcom,vdd-max-load-uA = <47000>;
+ core-supply = <&pm8150_l9>;
+ qcom,vbus-valid-override;
+ qcom,qmp-phy-init-seq =
+ /* <reg_offset, value, delay> */
+ <USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a 0
+ USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
+ USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01 0
+ USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82 0
+ USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0
+ USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0
+ USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
+ USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca 0
+ USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e 0
+ USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06 0
+ USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
+ USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
+ USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
+ USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
+ USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
+ USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04 0
+ USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0
+ USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
+ USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
+ USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
+ USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82 0
+ USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab 0
+ USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea 0
+ USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
+ USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
+ USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
+ USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06 0
+ USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
+ USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
+ USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca 0
+ USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e 0
+ USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20 0
+ USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01 0
+ USB3_UNI_QSERDES_COM_SSC_PER1 0x31 0
+ USB3_UNI_QSERDES_COM_SSC_PER2 0x01 0
+ USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde 0
+ USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
+ USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde 0
+ USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
+ USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02 0
+ USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xb8 0
+ USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xff 0
+ USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xbf 0
+ USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7f 0
+ USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0x7f 0
+ USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb4 0
+ USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7b 0
+ USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c 0
+ USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc 0
+ USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc 0
+ USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0
+ USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04 0
+ USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0
+ USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05 0
+ USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05 0
+ USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f 0
+ USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff 0
+ USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f 0
+ USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f 0
+ USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0
+ USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0
+ USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0c 0
+ USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
+ USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a 0
+ USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a 0
+ USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04 0
+ USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
+ USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
+ USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04 0
+ USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e 0
+ USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00 0
+ USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0 0
+ USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38 0
+ USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06 0
+ USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c 0
+ USB3_UNI_QSERDES_RX_GM_CAL 0x1f 0
+ USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12 0
+ USB3_UNI_QSERDES_TX_LANE_MODE_1 0xd5 0
+ USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82 0
+ USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40 0
+ USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x11 0
+ USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x02 0
+ USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0 0
+ USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0
+ USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20 0
+ USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13 0
+ USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0
+ USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
+ USB3_UNI_PCS_RX_SIGDET_LVL 0xa9 0
+ USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c 0
+ USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
+ USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8 0
+ USB3_UNI_PCS_CDR_RESET_TIME 0x0a 0
+ USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88 0
+ USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13 0
+ USB3_UNI_PCS_EQ_CONFIG1 0x4b 0
+ USB3_UNI_PCS_EQ_CONFIG5 0x10 0
+ USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21 0
+ 0xffffffff 0xffffffff 0x00>;
+
+ qcom,qmp-phy-reg-offset =
+ <USB3_UNI_PCS_PCS_STATUS1
+ USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
+ USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+ USB3_UNI_PCS_POWER_DOWN_CONTROL
+ USB3_UNI_PCS_SW_RESET
+ USB3_UNI_PCS_START_CONTROL>;
+
+ clocks = <&clock_gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+ <&clock_gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
+ <&clock_gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>,
+ <&clock_gcc USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_USB3_SEC_CLKREF_EN>,
+ <&clock_gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
+ clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
+ "pipe_clk_ext_src", "ref_clk_src",
+ "ref_clk", "com_aux_clk";
+
+ resets = <&clock_gcc GCC_USB3_PHY_SEC_BCR>,
+ <&clock_gcc GCC_USB3PHY_PHY_SEC_BCR>;
+ reset-names = "phy_reset", "phy_phy_reset";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2-arglass.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2-arglass.dts
new file mode 100755
index 0000000..8d4b0f0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2-arglass.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.dtsi"
+#include "kona-arglass.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona AR Glass";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x1040008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2-cdp.dts
new file mode 100755
index 0000000..06e939b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2-cdp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.dtsi"
+#include "kona-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona CDP";
+ compatible = "qcom,kona-cdp", "qcom,kona", "qcom,cdp";
+ qcom,board-id = <0x10001 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2-gpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-v2-gpu.dtsi
new file mode 100755
index 0000000..d9deb32
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2-gpu.dtsi
@@ -0,0 +1,590 @@
+&soc {
+ msm_bus: qcom,kgsl-busmon {
+ label = "kgsl-busmon";
+ compatible = "qcom,kgsl-busmon";
+ operating-points-v2 = <&gpu_opp_table_v2>;
+ };
+
+ gpu_opp_table_v2: gpu-opp-table_v2 {
+ compatible = "operating-points-v2";
+
+ opp-670000000 {
+ opp-hz = /bits/ 64 <670000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-587000000 {
+ opp-hz = /bits/ 64 <587000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-525000000 {
+ opp-hz = /bits/ 64 <525000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ };
+
+ opp-490000000 {
+ opp-hz = /bits/ 64 <490000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-441600000 {
+ opp-hz = /bits/ 64 <441600000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-305000000 {
+ opp-hz = /bits/ 64 <305000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+};
+
+&msm_gpu {
+ qcom,chipid = <0x06050001>;
+
+ /* GPU OPP data */
+ operating-points-v2 = <&gpu_opp_table_v2>;
+
+ /delete-property/qcom,initial-pwrlevel;
+ /delete-node/qcom,gpu-pwrlevels;
+
+ /* Power levels bins */
+ qcom,gpu-pwrlevel-bins {
+ compatible="qcom,gpu-pwrlevel-bins";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,gpu-pwrlevels-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,speed-bin = <0>;
+ qcom,initial-pwrlevel = <5>;
+ qcom,throttle-pwrlevel = <0>;
+
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <587000000>;
+ qcom,bus-freq-ddr7 = <11>;
+ qcom,bus-min-ddr7 = <11>;
+ qcom,bus-max-ddr7 = <11>;
+
+ qcom,bus-freq-ddr8 = <11>;
+ qcom,bus-min-ddr8 = <11>;
+ qcom,bus-max-ddr8 = <11>;
+
+ qcom,acd-level = <0x802b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <525000000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <9>;
+ qcom,bus-max-ddr7 = <11>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <8>;
+ qcom,bus-max-ddr8 = <11>;
+
+ qcom,acd-level = <0x802b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <490000000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <7>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <441600000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <7>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq-ddr7 = <7>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <6>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <305000000>;
+ qcom,bus-freq-ddr7 = <3>;
+ qcom,bus-min-ddr7 = <2>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <3>;
+ qcom,bus-min-ddr8 = <2>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,speed-bin = <1>;
+ qcom,initial-pwrlevel = <6>;
+ qcom,throttle-pwrlevel = <1>;
+
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <670000000>;
+ qcom,bus-freq-ddr7 = <11>;
+ qcom,bus-min-ddr7 = <11>;
+ qcom,bus-max-ddr7 = <11>;
+
+ qcom,bus-freq-ddr8 = <11>;
+ qcom,bus-min-ddr8 = <11>;
+ qcom,bus-max-ddr8 = <11>;
+
+ qcom,acd-level = <0x802b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <587000000>;
+ qcom,bus-freq-ddr7 = <11>;
+ qcom,bus-min-ddr7 = <11>;
+ qcom,bus-max-ddr7 = <11>;
+
+ qcom,bus-freq-ddr8 = <11>;
+ qcom,bus-min-ddr8 = <11>;
+ qcom,bus-max-ddr8 = <11>;
+
+ qcom,acd-level = <0x802b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <525000000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <9>;
+ qcom,bus-max-ddr7 = <11>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <8>;
+ qcom,bus-max-ddr8 = <11>;
+
+ qcom,acd-level = <0x802b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <490000000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <7>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <441600000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <7>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq-ddr7 = <7>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <6>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <305000000>;
+ qcom,bus-freq-ddr7 = <3>;
+ qcom,bus-min-ddr7 = <2>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <3>;
+ qcom,bus-min-ddr8 = <2>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,speed-bin = <3>;
+ qcom,initial-pwrlevel = <4>;
+
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <525000000>;
+ qcom,bus-freq-ddr7 = <11>;
+ qcom,bus-min-ddr7 = <10>;
+ qcom,bus-max-ddr7 = <11>;
+
+ qcom,bus-freq-ddr8 = <11>;
+ qcom,bus-min-ddr8 = <10>;
+ qcom,bus-max-ddr8 = <11>;
+
+ qcom,acd-level = <0x802b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <490000000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <7>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <441600000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <7>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq-ddr7 = <7>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <6>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <305000000>;
+ qcom,bus-freq-ddr7 = <3>;
+ qcom,bus-min-ddr7 = <2>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <3>;
+ qcom,bus-min-ddr8 = <2>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,speed-bin = <2>;
+ qcom,initial-pwrlevel = <6>;
+ qcom,throttle-pwrlevel = <1>;
+
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <670000000>;
+ qcom,bus-freq-ddr7 = <11>;
+ qcom,bus-min-ddr7 = <11>;
+ qcom,bus-max-ddr7 = <11>;
+
+ qcom,bus-freq-ddr8 = <11>;
+ qcom,bus-min-ddr8 = <11>;
+ qcom,bus-max-ddr8 = <11>;
+
+ qcom,acd-level = <0x802b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <587000000>;
+ qcom,bus-freq-ddr7 = <11>;
+ qcom,bus-min-ddr7 = <11>;
+ qcom,bus-max-ddr7 = <11>;
+
+ qcom,bus-freq-ddr8 = <11>;
+ qcom,bus-min-ddr8 = <11>;
+ qcom,bus-max-ddr8 = <11>;
+
+ qcom,acd-level = <0x802b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <525000000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <9>;
+ qcom,bus-max-ddr7 = <11>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <8>;
+ qcom,bus-max-ddr8 = <11>;
+
+ qcom,acd-level = <0x802b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <490000000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <7>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <441600000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <7>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq-ddr7 = <7>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <6>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <305000000>;
+ qcom,bus-freq-ddr7 = <3>;
+ qcom,bus-min-ddr7 = <2>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <3>;
+ qcom,bus-min-ddr8 = <2>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,speed-bin = <4>;
+ qcom,initial-pwrlevel = <6>;
+ qcom,throttle-pwrlevel = <1>;
+
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <670000000>;
+ qcom,bus-freq-ddr7 = <11>;
+ qcom,bus-min-ddr7 = <11>;
+ qcom,bus-max-ddr7 = <11>;
+
+ qcom,bus-freq-ddr8 = <11>;
+ qcom,bus-min-ddr8 = <11>;
+ qcom,bus-max-ddr8 = <11>;
+
+ qcom,acd-level = <0x802b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <587000000>;
+ qcom,bus-freq-ddr7 = <11>;
+ qcom,bus-min-ddr7 = <11>;
+ qcom,bus-max-ddr7 = <11>;
+
+ qcom,bus-freq-ddr8 = <11>;
+ qcom,bus-min-ddr8 = <11>;
+ qcom,bus-max-ddr8 = <11>;
+
+ qcom,acd-level = <0x802b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <525000000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <9>;
+ qcom,bus-max-ddr7 = <11>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <8>;
+ qcom,bus-max-ddr8 = <11>;
+
+ qcom,acd-level = <0x802b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <490000000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <7>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <441600000>;
+ qcom,bus-freq-ddr7 = <9>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <7>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq-ddr7 = <7>;
+ qcom,bus-min-ddr7 = <6>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <8>;
+ qcom,bus-min-ddr8 = <6>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <305000000>;
+ qcom,bus-freq-ddr7 = <3>;
+ qcom,bus-min-ddr7 = <2>;
+ qcom,bus-max-ddr7 = <9>;
+
+ qcom,bus-freq-ddr8 = <3>;
+ qcom,bus-min-ddr8 = <2>;
+ qcom,bus-max-ddr8 = <9>;
+
+ qcom,acd-level = <0xa02b5ffd>;
+ };
+
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2-mtp-sa.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2-mtp-sa.dts
new file mode 100755
index 0000000..413f5b0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2-mtp-sa.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+#include "kona-v2.dtsi"
+#include "kona-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona standalone MTP";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x02010008 0>;
+};
+
+&mdm0 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2-mtp-ws.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2-mtp-ws.dts
new file mode 100755
index 0000000..dd76c77
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2-mtp-ws.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.dtsi"
+#include "kona-mtp-ws.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona V2 MTP (WS)";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x03010008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2-mtp.dts
new file mode 100755
index 0000000..792a32b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2-mtp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.dtsi"
+#include "kona-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona MTP";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x10008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2-qrd.dts
new file mode 100755
index 0000000..6581125
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2-qrd.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.dtsi"
+#include "kona-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona QRD";
+ compatible = "qcom,kona-qrd", "qcom,kona", "qcom,qrd";
+ qcom,board-id = <11 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2-rumi.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2-rumi.dts
new file mode 100755
index 0000000..77006e3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2-rumi.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.dtsi"
+#include "kona-rumi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona RUMI";
+ compatible = "qcom,kona-rumi", "qcom,kona", "qcom,rumi";
+ qcom,board-id = <15 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2-xrfusion-ult.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2-xrfusion-ult.dts
new file mode 100755
index 0000000..63b13ab
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2-xrfusion-ult.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.dtsi"
+#include "kona-xrfusion-ult.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona XR 5G UltraSound";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x1030008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2-xrfusion.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2-xrfusion.dts
new file mode 100755
index 0000000..7a0a7ab
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2-xrfusion.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.dtsi"
+#include "kona-xrfusion.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona XR 5G Fusion";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x1020008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-arglass.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-arglass.dts
new file mode 100755
index 0000000..3ae4924
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-arglass.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.1.dtsi"
+#include "kona-arglass.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v2.1 AR Glass";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x1040008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-cdp.dts
new file mode 100755
index 0000000..94599ad
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-cdp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.1.dtsi"
+#include "kona-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v2.1 CDP";
+ compatible = "qcom,kona-cdp", "qcom,kona", "qcom,cdp";
+ qcom,board-id = <0x10001 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-gpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-gpu.dtsi
new file mode 100755
index 0000000..bc52046
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-gpu.dtsi
@@ -0,0 +1,3 @@
+&msm_gpu {
+ qcom,chipid = <0x06050002>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-hdk.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-hdk.dts
new file mode 100755
index 0000000..965f4023
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-hdk.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.1.dtsi"
+#include "kona-hdk.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v2.1 HDK";
+ compatible = "qcom,kona-hdk", "qcom,kona", "qcom,hdk";
+ qcom,board-id = <0x01001F 0x01>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-iot-rb5.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-iot-rb5.dts
new file mode 100755
index 0000000..0e44528
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-iot-rb5.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.1.dtsi"
+#include "kona-v2.1-iot-rb5.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v2.1 IOT RB5";
+ compatible = "qcom,kona-iot", "qcom,kona", "qcom,iot";
+ qcom,board-id = <11 3>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-iot-rb5.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-iot-rb5.dtsi
new file mode 100755
index 0000000..4b2aa98
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-iot-rb5.dtsi
@@ -0,0 +1,427 @@
+#include "kona-qrd.dtsi"
+#include "kona-iot-rb5-audio.dtsi"
+#include "camera/kona-camera-sensor-rb5.dtsi"
+
+&qupv3_se12_2uart {
+ status = "okay";
+};
+
+&qupv3_se1_i2c {
+ status = "okay";
+};
+
+&qupv3_se6_4uart {
+ status = "ok";
+};
+
+&qupv3_se13_4uart {
+ status = "ok";
+ qrc:qrc@100 {
+ compatible = "qcom,qrc-uart";
+ status = "ok";
+ qcom,qrc-reset-gpio = <&tlmm 114 0>;
+ qcom,qrc-boot-gpio = <&tlmm 109 0>;
+ };
+};
+
+&pm8150l_gpios {
+ lt9611_rst_pin_out {
+ lt9611_rst_pin_out_default: lt9611_rst_pin_out_default {
+ pins = "gpio5";
+ function = "normal";
+ output-enable;
+ input-disable;
+ bias-pull-down;
+ power-source = <0>;
+ };
+ };
+
+ rb5_fan_controller_pin_init: rb5_fan_controller_pin_init {
+ pins = "gpio10";
+ function = "normal";
+ output-enable;
+ input-disable;
+ bias-pull-down;
+ power-source = <0>;
+ };
+};
+
+&mdss_mdp {
+ connectors = <&sde_dp &sde_dsi &sde_dsi1 &sde_rscc>;
+};
+
+&mdss_dsi0_pll {
+ /delete-property/ qcom,dsi-pll-ssc-en;
+};
+
+&mdss_dsi1_pll {
+ /delete-property/ qcom,dsi-pll-ssc-en;
+};
+
+<9611_pins {
+ mux {
+ pins = "gpio63";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio63";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ };
+};
+
+&qupv3_se5_i2c {
+ status = "ok";
+ lt9611: lt,lt9611@2b {
+ compatible = "lt,lt9611uxc";
+ reg = <0x2b>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <63 0>;
+ interrupt-names = "lt_irq";
+ lt,irq-gpio = <&tlmm 63 0x0>;
+ lt,reset-gpio = <&pm8150l_gpios 5 0x0>;
+ instance_id = <0>;
+ lt,non-pluggable;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <<9611_pins <9611_rst_pin_out_default>;
+
+ lt,preferred-mode = "1920x1080";
+
+ totalVoltage-supply = <&pm8150a_l11>;
+ lt,supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lt,supply-entry@0 {
+ reg = <0>;
+ lt,supply-name = "totalVoltage";
+ lt,supply-min-voltage = <3300000>;
+ lt,supply-max-voltage = <3300000>;
+ lt,supply-enable-load = <200000>;
+ lt,supply-post-on-sleep = <50>;
+ };
+ };
+
+ lt,customize-modes {
+ lt,customize-mode-id@0 {
+ lt,mode-h-active = <1920>;
+ lt,mode-h-front-porch = <88>;
+ lt,mode-h-pulse-width = <44>;
+ lt,mode-h-back-porch = <148>;
+ lt,mode-h-active-high;
+ lt,mode-v-active = <1080>;
+ lt,mode-v-front-porch = <4>;
+ lt,mode-v-pulse-width = <5>;
+ lt,mode-v-back-porch = <36>;
+ lt,mode-v-active-high;
+ lt,mode-refresh-rate = <60>;
+ lt,mode-clock-in-khz = <148500>;
+ };
+
+ lt,customize-mode-id@1 {
+ lt,mode-h-active = <3840>;
+ lt,mode-h-front-porch = <176>;
+ lt,mode-h-pulse-width = <88>;
+ lt,mode-h-back-porch = <400>;
+ lt,mode-h-active-high;
+ lt,mode-v-active = <2160>;
+ lt,mode-v-front-porch = <8>;
+ lt,mode-v-pulse-width = <10>;
+ lt,mode-v-back-porch = <72>;
+ lt,mode-v-active-high;
+ lt,mode-refresh-rate = <60>;
+ lt,mode-clock-in-khz = <608040>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ lt9611_in_0: endpoint {
+ remote-endpoint = <&ext_dsi_0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ lt9611_in_1: endpoint {
+ remote-endpoint = <&ext_dsi_1_out>;
+ };
+ };
+
+ };
+ };
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_ext_bridge_1080p>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ ext_dsi_0_out: endpoint {
+ remote-endpoint = <<9611_in_0>;
+ };
+ };
+ };
+};
+
+&sde_dsi1 {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ ext_dsi_1_out: endpoint {
+ remote-endpoint = <<9611_in_1>;
+ };
+ };
+ };
+};
+
+&usb1 {
+ /delete-property/ qcom,default-mode-none;
+ dwc3@a800000 {
+ dr_mode = "host";
+ };
+};
+
+&soc {
+ msm_vidc: qcom,vidc@aa00000 {
+ compatible = "qcom,msm-vidc", "qcom,qcs8250-vidc";
+ };
+
+ clk40M: can_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <40000000>;
+ };
+
+ rb5_fan_controller {
+ compatible = "qcom,rb5_fan_controller";
+ qcom,pwr-enable-gpio = <&pm8150l_gpios 10 0x0>;
+ pinctrl-name = "default";
+ pinctrl-0 = <&rb5_fan_controller_pin_init>;
+ status = "ok";
+ };
+
+ rb5_gpios_enable {
+ compatible = "qcom,rb5_gpios_enable";
+ qcom,enable-gpio = <&tlmm 60 0x0>;
+ status = "ok";
+ };
+};
+
+&usb0 {
+ qcom,charging-disabled;
+};
+
+&usb2_phy0 {
+ qcom,param-override-seq = <0x43 0x70>;
+};
+
+&pm8150b_charger {
+ qcom,batteryless-platform;
+ qcom,lpd-disable;
+};
+
+&qupv3_se0_spi {
+ status = "okay";
+ can@0 {
+ compatible = "microchip,mcp2517fd";
+ reg = <0>;
+ clocks = <&clk40M>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <15 0>;
+ interrupt-names = "can_irq";
+ spi-max-frequency = <10000000>;
+ gpio-controller;
+ status = "okay";
+ };
+};
+
+&pcie1 {
+ status = "okay";
+ qcom,boot-option = <0x0>;
+};
+
+&pcie2 {
+ status = "okay";
+ qcom,boot-option = <0x0>;
+};
+
+&thermal_zones {
+ /delete-node/ modem-lte-sub6-pa1;
+ /delete-node/ modem-lte-sub6-pa2;
+ /delete-node/ modem-mmw0-usr;
+ /delete-node/ modem-mmw1-usr;
+ /delete-node/ modem-mmw2-usr;
+ /delete-node/ modem-mmw3-usr;
+ /delete-node/ modem-skin-usr;
+ /delete-node/ modem-wifi-usr;
+ /delete-node/ modem-ambient-usr;
+ /delete-node/ modem-0-usr;
+ /delete-node/ modem-1-usr;
+ /delete-node/ modem-streamer-usr;
+ /delete-node/ modem-mmw0-mod-usr;
+ /delete-node/ modem-mmw1-mod-usr;
+ /delete-node/ modem-mmw2-mod-usr;
+ /delete-node/ modem-mmw3-mod-usr;
+
+ /delete-node/ skin-therm-usr;
+ /delete-node/ skin-therm-step;
+ /delete-node/ camera-therm-usr;
+
+ /delete-node/ mmw-pa1-usr;
+ /delete-node/ mmw-pa1-step;
+ /delete-node/ mmw-pa2-usr;
+ /delete-node/ mmw-pa2-step;
+ /delete-node/ xo-therm-step;
+ /delete-node/ xo-therm-usr;
+ /delete-node/ skin-msm-therm-step;
+
+ pm8250-wifi-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <52000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150l-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8250-xo-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ };
+ };
+
+ pm8150l-skin-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ skin_trip: skin-config0 {
+ temperature = <50000>;
+ hysteresis = <48000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ lcd_cdev {
+ trip = <&skin_trip>;
+ cooling-device = <&mdss_mdp 153 153>;
+ };
+ };
+ };
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ qcom,clk-freq-out = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* TDK Chirp IO Expander */
+ ch_io_expander@22 {
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "semtech,sx1508q";
+ reg = <0x22>;
+ gpio-controller;
+ };
+};
+
+&qupv3_se15_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "ok";
+ qcom,clk-freq-out = <400000>;
+
+ /* TDK Chirp 3, 4, and 5 are connected to QUP15 */
+ ch101_1: ch101_1@45 {
+ compatible = "invensense,ch101";
+ reg = <0x45>;
+ rst-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>;
+ rtc_rst-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ prg-gpios = <3 4 5>;
+ int-gpios = <&tlmm 122 GPIO_ACTIVE_HIGH>,
+ <&tlmm 123 GPIO_ACTIVE_HIGH>,
+ <&tlmm 66 GPIO_ACTIVE_HIGH>;
+ };
+
+ #include "smb1390.dtsi"
+};
+
+&qupv3_se4_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "ok";
+ qcom,clk-freq-out = <400000>;
+
+ /* TDK Chirp 0, 1, and 2 are connected to QUP4 */
+ ch101_0: ch101_0@45 {
+ compatible = "invensense,ch101";
+ reg = <0x45>;
+ rst-gpios = <&tlmm 140 GPIO_ACTIVE_HIGH>;
+ rtc_rst-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>;
+ prg-gpios = <0 1 2>;
+ int-gpios = <&tlmm 129 GPIO_ACTIVE_HIGH>,
+ <&tlmm 141 GPIO_ACTIVE_HIGH>,
+ <&tlmm 113 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&qupv3_se17_spi {
+ status = "okay";
+ temp_sensor@0 {
+ compatible = "tdktherm";
+ reg = <0>; // Chip select ID
+ spi-max-frequency = <10000000>; // Can support up to 24 MHz
+ spi-cpol;
+ spi-cpha;
+ status = "okay";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-mtp-sa.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-mtp-sa.dts
new file mode 100755
index 0000000..daaf65a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-mtp-sa.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+#include "kona-v2.1.dtsi"
+#include "kona-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v2.1 standalone MTP";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x02010008 0>;
+};
+
+&mdm0 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-mtp-ws.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-mtp-ws.dts
new file mode 100755
index 0000000..5619b98
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-mtp-ws.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.1.dtsi"
+#include "kona-mtp-ws.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v2.1 MTP (WS)";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x03010008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-mtp.dts
new file mode 100755
index 0000000..ec73498
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-mtp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.1.dtsi"
+#include "kona-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v2.1 MTP";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x10008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-qrd.dts
new file mode 100755
index 0000000..29824a8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-qrd.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.1.dtsi"
+#include "kona-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v2.1 QRD";
+ compatible = "qcom,kona-qrd", "qcom,kona", "qcom,qrd";
+ qcom,board-id = <11 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-xrfusion-ult.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-xrfusion-ult.dts
new file mode 100755
index 0000000..5b09a68
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-xrfusion-ult.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.1.dtsi"
+#include "kona-xrfusion-ult.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v2.1 XR 5G UltraSound";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x1030008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-xrfusion.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-xrfusion.dts
new file mode 100755
index 0000000..268462c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1-xrfusion.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona-v2.1.dtsi"
+#include "kona-xrfusion.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v2.1 XR 5G Fusion";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x1020008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1.dts
new file mode 100755
index 0000000..e2b673c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "kona-v2.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v2.1 SoC";
+ compatible = "qcom,kona";
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.1.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1.dtsi
new file mode 100755
index 0000000..76658bf
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.1.dtsi
@@ -0,0 +1,10 @@
+
+#include "kona-v2.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v2.1";
+ compatible = "qcom,kona";
+ qcom,msm-id = <356 0x20001>;
+};
+
+#include "kona-v2.1-gpu.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.dts b/arch/arm64/boot/dts/vendor/qcom/kona-v2.dts
new file mode 100755
index 0000000..65a8d498
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "kona-v2.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v2 SoC";
+ compatible = "qcom,kona";
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-v2.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-v2.dtsi
new file mode 100755
index 0000000..8ca5010
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-v2.dtsi
@@ -0,0 +1,393 @@
+#include "kona.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v2";
+ compatible = "qcom,kona";
+ qcom,msm-id = <356 0x20000>;
+};
+
+&CPU4 {
+ dynamic-power-coefficient = <533>;
+};
+
+&CPU5 {
+ dynamic-power-coefficient = <533>;
+};
+
+&CPU6 {
+ dynamic-power-coefficient = <533>;
+};
+
+&CPU7 {
+ dynamic-power-coefficient = <642>;
+};
+
+&clock_camcc {
+ compatible = "qcom,camcc-kona-v2", "syscon";
+};
+
+&clock_videocc {
+ compatible = "qcom,videocc-kona-v2", "syscon";
+};
+
+&clock_npucc {
+ compatible = "qcom,npucc-kona-v2", "syscon";
+};
+
+&spss_utils {
+ qcom,spss-dev-firmware-name = "spss2d"; /* 8 chars max */
+ qcom,spss-test-firmware-name = "spss2t"; /* 8 chars max */
+ qcom,spss-prod-firmware-name = "spss2p"; /* 8 chars max */
+};
+
+#include "kona-v2-gpu.dtsi"
+
+&cpu0_cpu_l3_latmon {
+ qcom,core-dev-table =
+ < 300000 300000000 >,
+ < 403200 403200000 >,
+ < 518400 518400000 >,
+ < 691200 614400000 >,
+ < 883200 825600000 >,
+ < 1075200 921600000 >,
+ < 1171200 1017600000 >,
+ < 1344000 1132800000 >,
+ < 1420800 1228800000 >,
+ < 1516800 1324800000 >,
+ < 1612800 1516800000 >,
+ < 1804800 1612800000 >;
+};
+
+&cpu4_cpu_l3_latmon {
+ qcom,core-dev-table =
+ < 300000 300000000 >,
+ < 825600 614400000 >,
+ < 1171200 825600000 >,
+ < 1478400 1017600000 >,
+ < 1670400 1228800000 >,
+ < 2054400 1324800000 >,
+ < 2419200 1516800000 >,
+ < 2841600 1612800000 >;
+};
+
+&cpu7_cpu_l3_latmon {
+ qcom,core-dev-table =
+ < 300000 300000000 >,
+ < 825600 614400000 >,
+ < 1171200 825600000 >,
+ < 1478400 1017600000 >,
+ < 1670400 1228800000 >,
+ < 2054400 1324800000 >,
+ < 2419200 1516800000 >,
+ < 2841600 1612800000 >;
+};
+
+&cpu0_cpu_llcc_latmon {
+ qcom,core-dev-table =
+ < 300000 MHZ_TO_MBPS( 150, 16) >,
+ < 787200 MHZ_TO_MBPS( 300, 16) >,
+ < 1516800 MHZ_TO_MBPS( 466, 16) >,
+ < 1804800 MHZ_TO_MBPS( 600, 16) >;
+};
+
+&cpu4_cpu_llcc_latmon {
+ qcom,core-dev-table =
+ < 300000 MHZ_TO_MBPS( 150, 16) >,
+ < 710400 MHZ_TO_MBPS( 300, 16) >,
+ < 1056000 MHZ_TO_MBPS( 466, 16) >,
+ < 1286400 MHZ_TO_MBPS( 600, 16) >,
+ < 1862400 MHZ_TO_MBPS( 806, 16) >,
+ < 2419200 MHZ_TO_MBPS( 933, 16) >,
+ < 2841600 MHZ_TO_MBPS( 1000, 16) >;
+};
+
+&cpu0_llcc_ddr_latmon {
+ qcom,cachemiss-ev = <0x1000>;
+ ddr4-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
+ qcom,core-dev-table =
+ < 300000 MHZ_TO_MBPS( 200, 4) >,
+ < 787200 MHZ_TO_MBPS( 451, 4) >,
+ < 1171200 MHZ_TO_MBPS( 547, 4) >,
+ < 1516800 MHZ_TO_MBPS( 768, 4) >,
+ < 1804800 MHZ_TO_MBPS( 1017, 4) >;
+ };
+
+ ddr5-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR5>;
+ qcom,core-dev-table =
+ < 300000 MHZ_TO_MBPS( 200, 4) >,
+ < 787200 MHZ_TO_MBPS( 451, 4) >,
+ < 1171200 MHZ_TO_MBPS( 547, 4) >,
+ < 1516800 MHZ_TO_MBPS( 768, 4) >,
+ < 1804800 MHZ_TO_MBPS( 1017, 4) >;
+ };
+};
+
+&cpu4_llcc_ddr_latmon {
+ qcom,cachemiss-ev = <0x1000>;
+ ddr4-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
+ qcom,core-dev-table =
+ < 300000 MHZ_TO_MBPS( 200, 4) >,
+ < 710400 MHZ_TO_MBPS( 451, 4) >,
+ < 825600 MHZ_TO_MBPS( 547, 4) >,
+ < 1056000 MHZ_TO_MBPS( 768, 4) >,
+ < 1286400 MHZ_TO_MBPS(1017, 4) >,
+ < 1574400 MHZ_TO_MBPS(1353, 4) >,
+ < 1862400 MHZ_TO_MBPS(1555, 4) >,
+ < 2419200 MHZ_TO_MBPS(1804, 4) >,
+ < 2745600 MHZ_TO_MBPS(2092, 4) >,
+ < 2841600 MHZ_TO_MBPS(2736, 4) >;
+ };
+
+ ddr5-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR5>;
+ qcom,core-dev-table =
+ < 300000 MHZ_TO_MBPS( 200, 4) >,
+ < 710400 MHZ_TO_MBPS( 451, 4) >,
+ < 825600 MHZ_TO_MBPS( 547, 4) >,
+ < 1056000 MHZ_TO_MBPS( 768, 4) >,
+ < 1286400 MHZ_TO_MBPS(1017, 4) >,
+ < 1862400 MHZ_TO_MBPS(1555, 4) >,
+ < 2419200 MHZ_TO_MBPS(1804, 4) >,
+ < 2745600 MHZ_TO_MBPS(2092, 4) >,
+ < 2841600 MHZ_TO_MBPS(2736, 4) >;
+ };
+};
+
+&cpu4_computemon {
+ ddr4-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
+ qcom,core-dev-table =
+ < 1862400 MHZ_TO_MBPS( 200, 4) >,
+ < 2745600 MHZ_TO_MBPS(1017, 4) >,
+ < 2841600 MHZ_TO_MBPS(2092, 4) >;
+ };
+
+ ddr5-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR5>;
+ qcom,core-dev-table =
+ < 1862400 MHZ_TO_MBPS( 200, 4) >,
+ < 2745600 MHZ_TO_MBPS(1017, 4) >,
+ < 2841600 MHZ_TO_MBPS(2736, 4) >;
+ };
+};
+
+&cpu4_qoslatmon {
+ qcom,cachemiss-ev = <0x1000>;
+};
+
+/* NPU overrides */
+&msm_npu {
+ qcom,npu-pwrlevels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,npu-pwrlevels";
+ initial-pwrlevel = <5>;
+ qcom,npu-pwrlevel@0 {
+ reg = <0>;
+ vreg = <1>;
+ clk-freq = <19200000
+ 100000000
+ 300000000
+ 300000000
+ 300000000
+ 300000000
+ 200000000
+ 40000000
+ 300000000
+ 100000000
+ 19200000
+ 50000000
+ 50000000
+ 100000000
+ 100000000
+ 100000000
+ 19200000
+ 100000000
+ 19200000
+ 50000000
+ 200000000
+ 200000000
+ 50000000
+ 19200000
+ 300000000
+ 300000000
+ 19200000
+ 300000000>;
+ };
+
+ qcom,npu-pwrlevel@1 {
+ reg = <1>;
+ vreg = <2>;
+ clk-freq = <19200000
+ 200000000
+ 406000000
+ 406000000
+ 406000000
+ 406000000
+ 267000000
+ 40000000
+ 403000000
+ 200000000
+ 19200000
+ 50000000
+ 50000000
+ 200000000
+ 200000000
+ 200000000
+ 19200000
+ 200000000
+ 19200000
+ 50000000
+ 406000000
+ 406000000
+ 50000000
+ 19200000
+ 406000000
+ 406000000
+ 19200000
+ 400000000>;
+ };
+
+ qcom,npu-pwrlevel@2 {
+ reg = <2>;
+ vreg = <3>;
+ clk-freq = <19200000
+ 333000000
+ 533000000
+ 533000000
+ 533000000
+ 533000000
+ 403000000
+ 75000000
+ 533000000
+ 214000000
+ 19200000
+ 50000000
+ 100000000
+ 214000000
+ 214000000
+ 214000000
+ 19200000
+ 214000000
+ 19200000
+ 50000000
+ 533000000
+ 533000000
+ 50000000
+ 19200000
+ 533000000
+ 533000000
+ 19200000
+ 500000000>;
+ };
+
+ qcom,npu-pwrlevel@3 {
+ reg = <3>;
+ vreg = <4>;
+ clk-freq = <19200000
+ 428000000
+ 730000000
+ 730000000
+ 730000000
+ 730000000
+ 533000000
+ 75000000
+ 700000000
+ 300000000
+ 19200000
+ 100000000
+ 200000000
+ 300000000
+ 300000000
+ 300000000
+ 19200000
+ 300000000
+ 19200000
+ 100000000
+ 730000000
+ 730000000
+ 100000000
+ 19200000
+ 730000000
+ 730000000
+ 19200000
+ 660000000>;
+ };
+
+ qcom,npu-pwrlevel@4 {
+ reg = <4>;
+ vreg = <6>;
+ clk-freq = <19200000
+ 500000000
+ 920000000
+ 920000000
+ 920000000
+ 920000000
+ 700000000
+ 75000000
+ 806000000
+ 300000000
+ 19200000
+ 100000000
+ 200000000
+ 300000000
+ 300000000
+ 300000000
+ 19200000
+ 300000000
+ 19200000
+ 100000000
+ 920000000
+ 920000000
+ 100000000
+ 19200000
+ 920000000
+ 920000000
+ 19200000
+ 800000000>;
+ };
+
+ qcom,npu-pwrlevel@5 {
+ reg = <5>;
+ vreg = <7>;
+ clk-freq = <19200000
+ 500000000
+ 1000000000
+ 1000000000
+ 1000000000
+ 1000000000
+ 700000000
+ 75000000
+ 806000000
+ 300000000
+ 19200000
+ 100000000
+ 200000000
+ 300000000
+ 300000000
+ 300000000
+ 19200000
+ 300000000
+ 19200000
+ 100000000
+ 1000000000
+ 1000000000
+ 100000000
+ 19200000
+ 1000000000
+ 1000000000
+ 19200000
+ 800000000>;
+ };
+ };
+};
+
+&cpufreq_hw {
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-va-bolero-ar.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-va-bolero-ar.dtsi
new file mode 100755
index 0000000..b462231
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-va-bolero-ar.dtsi
@@ -0,0 +1,15 @@
+&bolero_ar {
+ va_macro_ar: va-macro-ar@3370000 {
+ compatible = "qcom,va-macro";
+ reg = <0x3370000 0x0>;
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote_ar 0>;
+ va-vdd-micb-supply = <&S4A>;
+ qcom,va-vdd-micb-voltage = <1800000 1800000>;
+ qcom,va-vdd-micb-current = <11200>;
+ qcom,va-dmic-sample-rate = <600000>;
+ qcom,va-clk-mux-select = <1>;
+ qcom,va-island-mode-muxsel = <0x033A0000>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-va-bolero.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-va-bolero.dtsi
new file mode 100755
index 0000000..fc56b31
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-va-bolero.dtsi
@@ -0,0 +1,19 @@
+&bolero {
+ va_macro: va-macro@3370000 {
+ compatible = "qcom,va-macro";
+ reg = <0x3370000 0x0>;
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+ va-vdd-micb-supply = <&S4A>;
+ qcom,va-vdd-micb-voltage = <1800000 1800000>;
+ qcom,va-vdd-micb-current = <11200>;
+ qcom,va-dmic-sample-rate = <600000>;
+ qcom,va-clk-mux-select = <1>;
+ qcom,va-island-mode-muxsel = <0x033A0000>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ };
+};
+
+&va_cdc_dma_0_tx {
+ qcom,msm-dai-is-island-supported = <1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-vidc.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-vidc.dtsi
new file mode 100755
index 0000000..a0b09ca
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-vidc.dtsi
@@ -0,0 +1,121 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/clock/qcom,videocc-kona.h>
+
+&soc {
+ msm_vidc: qcom,vidc@aa00000 {
+ compatible = "qcom,msm-vidc", "qcom,kona-vidc";
+ status = "ok";
+ sku-index = <0>;
+ reg = <0x0aa00000 0x00100000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ /* IOMMU Config */
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* LLCC Cache */
+ cache-slice-names = "vidsc0";
+
+ /* Supply */
+ iris-ctl-supply = <&mvs0c_gdsc>;
+ vcodec-supply = <&mvs0_gdsc>;
+
+ /* Clocks */
+ clock-names = "gcc_video_axi0",
+ "core_clk", "vcodec_clk";
+ clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,
+ <&clock_videocc VIDEO_CC_MVS0C_CLK>,
+ <&clock_videocc VIDEO_CC_MVS0_CLK>;
+ qcom,proxy-clock-names = "gcc_video_axi0",
+ "core_clk", "vcodec_clk";
+ /* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/
+ qcom,clock-configs = <0x0 0x1 0x1>;
+ qcom,allowed-clock-rates = <239999999 338000000
+ 366000000 444000000>;
+ resets = <&clock_gcc GCC_VIDEO_AXI0_CLK_ARES>,
+ <&clock_videocc VIDEO_CC_MVS0C_CLK_ARES>;
+ reset-names = "video_axi_reset", "video_core_reset";
+
+ qcom,reg-presets = <0xB0088 0x0>;
+
+ /* Buses */
+ bus_cnoc {
+ compatible = "qcom,msm-vidc,bus";
+ label = "cnoc";
+ qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <762 762>;
+ };
+
+ venus_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_LLCC>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "venus-ddr";
+ qcom,bus-range-kbps = <762 15000000>;
+ };
+
+ venus_bus_llcc {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-llcc";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_LLCC>;
+ qcom,mode = "venuc-llcc";
+ qcom,bus-range-kbps = <2288 15000000>;
+ };
+
+ /* MMUs */
+ non_secure_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_ns";
+ iommus = <&apps_smmu 0x2100 0x0400>;
+ qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-pagetable = "LLC";
+ buffer-types = <0xfff>;
+ virtual-addr-pool = <0x25800000 0xba800000>;
+ };
+
+ secure_non_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_non_pixel";
+ iommus = <&apps_smmu 0x2104 0x0400>;
+ qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-pagetable = "LLC";
+ qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
+ buffer-types = <0x480>;
+ virtual-addr-pool = <0x01000000 0x24800000>;
+ qcom,secure-context-bank;
+ };
+
+ secure_bitstream_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_bitstream";
+ iommus = <&apps_smmu 0x2101 0x0404>;
+ qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-pagetable = "LLC";
+ qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
+ buffer-types = <0x241>;
+ virtual-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,secure-context-bank;
+ };
+
+ secure_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_pixel";
+ iommus = <&apps_smmu 0x2103 0x0400>;
+ qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-pagetable = "LLC";
+ qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
+ buffer-types = <0x106>;
+ virtual-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,secure-context-bank;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-xr-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/kona-xr-overlay.dts
new file mode 100755
index 0000000..76f19e6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-xr-overlay.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-kona.h>
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "kona-xr.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. XR kona Standalone";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x1010008 0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-xr-pinctrl-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-xr-pinctrl-overlay.dtsi
new file mode 100755
index 0000000..bc6d7f0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-xr-pinctrl-overlay.dtsi
@@ -0,0 +1,195 @@
+&cam_sensor_mclk0_active {
+ /* MCLK0 */
+ mux {
+ pins = "gpio94";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio94";
+ bias-disable; /* No PULL */
+ drive-strength = <16>; /* 2 MA */
+ };
+};
+
+&cam_sensor_mclk0_suspend {
+ /* MCLK0 */
+ mux {
+ pins = "gpio94";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio94";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <16>; /* 2 MA */
+ };
+};
+
+&cam_sensor_mclk1_active {
+ /* MCLK1 */
+ mux {
+ pins = "gpio95";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio95";
+ bias-disable; /* No PULL */
+ drive-strength = <16>; /* 2 MA */
+ };
+};
+
+&cam_sensor_mclk1_suspend {
+ /* MCLK1 */
+ mux {
+ pins = "gpio95";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio95";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <16>; /* 2 MA */
+ };
+};
+
+&cam_sensor_mclk2_active {
+ /* MCLK2 */
+ mux {
+ pins = "gpio96";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio96";
+ bias-disable; /* No PULL */
+ drive-strength = <16>; /* 2 MA */
+ };
+};
+
+&cam_sensor_mclk2_suspend {
+ /* MCLK2 */
+ mux {
+ pins = "gpio96";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio96";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <16>; /* 2 MA */
+ };
+};
+
+&cam_sensor_mclk3_active {
+ /* MCLK3 */
+ mux {
+ pins = "gpio97";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio97";
+ bias-disable; /* No PULL */
+ drive-strength = <16>; /* 2 MA */
+ };
+};
+
+&cam_sensor_mclk3_suspend {
+ /* MCLK3 */
+ mux {
+ pins = "gpio97";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio97";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <16>; /* 2 MA */
+ };
+};
+
+&cam_sensor_mclk4_active {
+ /* MCLK4 */
+ mux {
+ pins = "gpio98";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio98";
+ bias-disable; /* No PULL */
+ drive-strength = <16>; /* 2 MA */
+ };
+};
+
+&cam_sensor_mclk4_suspend {
+ /* MCLK4 */
+ mux {
+ pins = "gpio98";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio98";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <16>; /* 2 MA */
+ };
+};
+
+&cam_sensor_mclk5_active {
+ /* MCLK5 */
+ mux {
+ pins = "gpio99";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio99";
+ bias-disable; /* No PULL */
+ drive-strength = <16>; /* 2 MA */
+ };
+};
+
+&cam_sensor_mclk5_suspend {
+ /* MCLK5 */
+ mux {
+ pins = "gpio99";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio99";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <16>; /* 2 MA */
+ };
+};
+
+&cam_sensor_mclk6_active {
+ /* MCLK6 */
+ mux {
+ pins = "gpio100";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio100";
+ bias-disable; /* No PULL */
+ drive-strength = <16>; /* 2 MA */
+ };
+};
+
+&cam_sensor_mclk6_suspend {
+ /* MCLK6 */
+ mux {
+ pins = "gpio100";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio100";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <16>; /* 2 MA */
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-xr.dts b/arch/arm64/boot/dts/vendor/qcom/kona-xr.dts
new file mode 100755
index 0000000..eba0487
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-xr.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona.dtsi"
+#include "kona-xr.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona XR Standalone";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x10108 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-xr.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-xr.dtsi
new file mode 100755
index 0000000..00b68e1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-xr.dtsi
@@ -0,0 +1,1220 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+
+#include "kona-pmic-overlay.dtsi"
+#include "kona-sde-display.dtsi"
+#include "kona-audio-overlay.dtsi"
+#include "kona-thermal-overlay.dtsi"
+#include "kona-xr-pinctrl-overlay.dtsi"
+#include "camera/kona-camera-sensor-xr.dtsi"
+
+&tlmm {
+ spkr_1_sd_n {
+ spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+ mux {
+ pins = "gpio127";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio127";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_1_sd_n_active: spkr_1_sd_n_active {
+ mux {
+ pins = "gpio127";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio127";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ spkr_2_sd_n {
+ spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
+ mux {
+ pins = "gpio129";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio129";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_2_sd_n_active: spkr_2_sd_n_active {
+ mux {
+ pins = "gpio129";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio129";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ pri_aux_pcm_dout {
+ pri_aux_pcm_dout_sleep: pri_aux_pcm_dout_sleep {
+ mux {
+ pins = "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_aux_pcm_dout_active: pri_aux_pcm_dout_active {
+ mux {
+ pins = "gpio7";
+ function = "mi2s0_data1";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ sec_aux_pcm_dout {
+ sec_aux_pcm_dout_sleep: sec_aux_pcm_dout_sleep {
+ mux {
+ pins = "gpio6";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_aux_pcm_dout_active: sec_aux_pcm_dout_active {
+ mux {
+ pins = "gpio6";
+ function = "mi2s0_data1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ tert_aux_pcm {
+ tert_aux_pcm_clk_sleep: tert_aux_pcm_clk_sleep {
+ mux {
+ pins = "gpio9";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_aux_pcm_clk_active: tert_aux_pcm_clk_active {
+ mux {
+ pins = "gpio9";
+ function = "mi2s2_sck";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ tert_aux_pcm_din {
+ tert_aux_pcm_din_sleep: tert_aux_pcm_din_sleep {
+ mux {
+ pins = "gpio8";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_aux_pcm_din_active: tert_aux_pcm_din_active {
+ mux {
+ pins = "gpio8";
+ function = "mi2s2_data0";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ pri_tdm_dout {
+ pri_tdm_dout_sleep: pri_tdm_dout_sleep {
+ mux {
+ pins = "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_tdm_dout_active: pri_tdm_dout_active {
+ mux {
+ pins = "gpio7";
+ function = "mi2s0_data1";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ sec_tdm_dout {
+ sec_tdm_dout_sleep: sec_tdm_dout_sleep {
+ mux {
+ pins = "gpio6";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_tdm_dout_active: sec_tdm_dout_active {
+ mux {
+ pins = "gpio6";
+ function = "mi2s1_data1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ tert_tdm {
+ tert_tdm_clk_sleep: tert_tdm_clk_sleep {
+ mux {
+ pins = "gpio9";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_tdm_clk_active: tert_tdm_clk_active {
+ mux {
+ pins = "gpio9";
+ function = "mi2s2_sck";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ tert_tdm_din {
+ tert_tdm_din_sleep: tert_tdm_din_sleep {
+ mux {
+ pins = "gpio8";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_tdm_din_active: tert_tdm_din_active {
+ mux {
+ pins = "gpio8";
+ function = "mi2s2_data0";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ pri_mi2s_sd1 {
+ pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep {
+ mux {
+ pins = "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_mi2s_sd1_active: pri_mi2s_sd1_active {
+ mux {
+ pins = "gpio7";
+ function = "mi2s2_data0";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ sec_mi2s_sd1 {
+ sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep {
+ mux {
+ pins = "gpio6";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_mi2s_sd1_active: sec_mi2s_sd1_active {
+ mux {
+ pins = "gpio6";
+ function = "mi2s1_data1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ tert_mi2s_sck {
+ tert_mi2s_sck_sleep: tert_mi2s_sck_sleep {
+ mux {
+ pins = "gpio9";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_mi2s_sck_active: tert_mi2s_sck_active {
+ mux {
+ pins = "gpio9";
+ function = "mi2s2_sck";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ tert_mi2s_sd0 {
+ tert_mi2s_sd0_sleep: tert_mi2s_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ tert_mi2s_sd0_active: tert_mi2s_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "mi2s2_data0";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ display_panel_led1_default: display_panel_led1_default {
+ mux {
+ pins = "gpio144";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio144";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ output-high;
+ };
+ };
+
+ display_panel_led2_default: display_panel_led2_default {
+ mux {
+ pins = "gpio140";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio140";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ output-high;
+ };
+ };
+
+};
+
+&qupv3_se12_2uart {
+ status = "ok";
+};
+
+&qupv3_se6_4uart {
+ status = "ok";
+};
+
+&dai_mi2s2 {
+ status = "ok";
+ qcom,msm-mi2s-tx-lines = <1>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
+ &tert_mi2s_sd0_active>;
+ pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
+ &tert_mi2s_sd0_sleep>;
+};
+
+&kona_snd {
+ qcom,model = "kona-xr-standalone-snd-card";
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
+ qcom,wcn-bt = <1>;
+ qcom,ext-disp-audio-rx = <1>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic4",
+ "AMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Analog Mic5",
+ "DMIC0", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic0",
+ "DMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic1",
+ "DMIC2", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "DMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "DMIC6", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic6",
+ "DMIC7", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic7",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic4",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA DMIC4", "VA MIC BIAS4",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC0", "VA_SWR_CLK",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_ADC2", "VA_SWR_CLK",
+ "VA SWR_ADC3", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_ADC0", "ADC1_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT",
+ "VA SWR_ADC2", "ADC3_OUTPUT",
+ "VA SWR_ADC3", "ADC4_OUTPUT",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
+ qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
+ qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
+ asoc-codec = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
+ "msm-ext-disp-audio-codec-rx";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>,
+ <&wsa881x_0213>, <&wsa881x_0214>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+ "SpkrLeft", "SpkrRight";
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&wcd938x_codec>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
+ <&bolero>;
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v4";
+
+ vdda-phy-supply = <&pm8150_l5>;
+ vdda-phy-always-on;
+ vdda-pll-supply = <&pm8150_l9>;
+ vdda-phy-max-microamp = <89900>;
+ vdda-pll-max-microamp = <18800>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm8150_l17>;
+ vcc-voltage-level = <2504000 2950000>;
+ vcc-low-voltage-sup;
+ vccq-supply = <&pm8150_l6>;
+ vccq2-supply = <&pm8150_s4>;
+ vcc-max-microamp = <800000>;
+ vccq-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+
+ qcom,vddp-ref-clk-supply = <&pm8150_l6>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+
+ status = "ok";
+};
+
+&pm8150a_l11 {
+ qcom,init-voltage = <3304000>;
+};
+
+
+&vendor {
+ kona_xr_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "fg-gen4-batterydata-mlp466274-3650mah.dtsi"
+ #include "fg-gen4-batterydata-atl466274-3650mah.dtsi"
+ };
+};
+
+
+&pm8150a_amoled {
+ status = "disabled";
+};
+
+&qupv3_se1_i2c {
+ status = "disabled";
+};
+
+&pcie1 {
+ status = "disabled";
+};
+
+&pcie2 {
+ status = "disabled";
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_home_default
+ &key_vol_up_default>;
+
+ home {
+ label = "home";
+ gpios = <&pm8150_gpios 7 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_BACK>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+
+ qcom,qbt_handler {
+ status = "disabled";
+ };
+
+ qcom,xr-stdalonevwr-misc {
+ status ="ok";
+ compatible = "qcom,xr-stdalonevwr-misc";
+ /* IMU CLK Enable PM8150 GPIO 3 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&imu_clkin_default>;
+ pinctrl-1 = <&imu_clkin_sleep>;
+ };
+};
+
+&qupv3_se13_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ st_fts@49 {
+ status = "disabled";
+ };
+};
+
+&qupv3_se15_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ halo,hl6111r@25 {
+ compatible = "halo,hl6111r";
+ reg = <0x25>;
+ status = "disabled";
+ };
+};
+
+&vendor {
+ bluetooth: bt_qca6390 {
+ compatible = "qca,qca6390";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en_sleep>;
+ qca,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */
+ qca,bt-sw-ctrl-gpio = <&tlmm 124 0>; /* SW_CTRL */
+ qca,bt-vdd-aon-supply = <&pm8150_s6>;
+ qca,bt-vdd-dig-supply = <&pm8009_s2>;
+ qca,bt-vdd-rfa1-supply = <&pm8150_s5>;
+ qca,bt-vdd-rfa2-supply = <&pm8150a_s8>;
+ qca,bt-vdd-asd-supply = <&pm8150_l16>;
+
+ qca,bt-vdd-aon-voltage-level = <950000 950000>;
+ qca,bt-vdd-dig-voltage-level = <950000 952000>;
+ qca,bt-vdd-rfa1-voltage-level = <1900000 1900000>;
+ qca,bt-vdd-rfa2-voltage-level = <1350000 1350000>;
+ qca,bt-vdd-asd-voltage-level = <3024000 3304000>;
+
+ qca,bt-vdd-asd-current-level = <10000>;
+ };
+
+ extcon_usb1: extcon_usb1 {
+ compatible = "linux,extcon-usb-gpio";
+ vbus-gpio = <&pm8150_gpios 10 GPIO_ACTIVE_HIGH>;
+ id-gpio = <&tlmm 91 GPIO_ACTIVE_HIGH>;
+ vbus-out-gpio = <&pm8150_gpios 9 GPIO_ACTIVE_HIGH>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb2_vbus_det_default
+ &usb2_id_det_default
+ &usb2_vbus_boost_default>;
+ };
+};
+
+&vreg_hap_boost {
+ status = "ok";
+};
+
+&pm8150b_haptics {
+ vdd-supply = <&vreg_hap_boost>;
+};
+
+&pm8150b_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "conn_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ chg_sbux@99 {
+ reg = <ADC_SBUx>;
+ label = "chg_sbux";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ mid_chg_div6@1e {
+ reg = <ADC_MID_CHG_DIV6>;
+ label = "chg_mid";
+ qcom,pre-scaling = <1 6>;
+ };
+
+ usb_in_i_uv@7 {
+ reg = <ADC_USB_IN_I>;
+ label = "usb_in_i_uv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ usb_in_v_div_16@8 {
+ reg = <ADC_USB_IN_V_16>;
+ label = "usb_in_v_div_16";
+ qcom,pre-scaling = <1 16>;
+ };
+};
+
+&pm8150b_charger {
+ status = "ok";
+ qcom,sec-charger-config = <0>;
+ qcom,auto-recharge-soc = <98>;
+ io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>,
+ <&pm8150b_vadc ADC_USB_IN_I>,
+ <&pm8150b_vadc ADC_SBUx>,
+ <&pm8150b_vadc ADC_VPH_PWR>,
+ <&pm8150b_vadc ADC_CHG_TEMP>;
+ io-channel-names = "mid_voltage",
+ "usb_in_current",
+ "sbux_res",
+ "vph_voltage",
+ "chg_temp";
+ qcom,battery-data = <&kona_xr_batterydata>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,wd-bark-time-secs = <16>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,fcc-stepping-enable;
+};
+
+&pm8150b_fg {
+ status = "ok";
+ qcom,battery-data = <&kona_xr_batterydata>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,five-pin-battery;
+ qcom,cl-wt-enable;
+ qcom,soc-scale-mode-en;
+ /* ESR fast calibration */
+ qcom,fg-esr-timer-chg-fast = <0 7>;
+ qcom,fg-esr-timer-dischg-fast = <0 7>;
+ qcom,fg-esr-timer-chg-slow = <0 96>;
+ qcom,fg-esr-timer-dischg-slow = <0 96>;
+ qcom,fg-esr-cal-soc-thresh = <26 230>;
+ qcom,fg-esr-cal-temp-thresh = <10 40>;
+};
+
+&qupv3_se15_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+#include "smb1390.dtsi"
+
+ halo,hl6111r@25 {
+ compatible = "halo,hl6111r";
+ reg = <0x25>;
+ status = "ok";
+ };
+};
+
+&smb1390 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_stat_default>;
+ status = "ok";
+};
+
+&smb1390_charger {
+ io-channels = <&pm8150b_vadc ADC_AMUX_THM2>;
+ io-channel-names = "cp_die_temp";
+};
+
+&pm8150_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vcoin@85 {
+ reg = <ADC_VCOIN>;
+ label = "vcoin";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ xo_therm@4c {
+ reg = <ADC_XO_THERM_PU2>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "pa_therm1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150l_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ camera_flash_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "camera_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_msm_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "skin_msm_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm2@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "pa_therm2";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150b_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ io-channels = <&pm8150b_vadc ADC_AMUX_THM3_PU2>;
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ io-channels = <&pm8150_vadc ADC_XO_THERM_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM1_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM2_PU2>;
+
+ xo_therm@4c {
+ reg = <ADC_XO_THERM_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150l_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera_flash_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ skin_msm_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm2@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&spmi_debug_bus {
+ status = "ok";
+};
+
+&dsi_dual_xrsmrtvwr_jdi_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+
+ qcom,platform-bklight-en-gpio = <&tlmm 133 0>;
+ qcom,5v-boost-gpio = <&tlmm 134 0>;
+ /delete-property/ qcom,platform-en-gpio;
+};
+
+&sde_dsi {
+ avdd-supply = <&display_panel_avdd>;
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+ qcom,dsi-default-panel = <&dsi_dual_xrsmrtvwr_jdi_video>;
+};
+
+&display_panel_avdd {
+ display_panel_led1_gpio = <&tlmm 144 0>;
+ display_panel_led2_gpio = <&tlmm 140 0>;
+ enable-active-high;
+ regulator-boot-on;
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_panel_led1_default
+ &display_panel_led2_default>;
+};
+
+&dsi_panel_pwr_supply_lab_ibb {
+ qcom,panel-supply-entry@3 {
+ reg = <1>;
+ qcom,supply-name = "avdd";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+};
+
+&mdss_mdp {
+ connectors = <&sde_dp &sde_dsi &sde_dsi1 &sde_rscc>;
+};
+
+&pm8150l_lcdb {
+ status = "ok";
+};
+
+&pm8150l_wled {
+ status = "ok";
+};
+
+&thermal_zones {
+ conn-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM3_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-msm-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&sdhc_2 {
+ vdd-supply = <&pm8150a_l9>;
+ qcom,vdd-voltage-level = <2950000 2960000>;
+ qcom,vdd-current-level = <200 800000>;
+
+ vdd-io-supply = <&pm8150_s4>;
+ qcom,vdd-io-voltage-level = <1808000 2960000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>;
+
+ cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&usb1 {
+ extcon = <&extcon_usb1>;
+};
+
+&flash_led {
+ qcom,hw-strobe-option = <0>;
+ qcom,strobe-sel = <1>;
+};
+
+&pm8150l_flash0 {
+ qcom,hw-strobe-option = <0>;
+ qcom,strobe-sel = <1>;
+};
+
+&pm8150l_flash1 {
+ qcom,hw-strobe-option = <0>;
+ qcom,strobe-sel = <1>;
+};
+
+&pm8150l_flash2 {
+ qcom,hw-strobe-option = <0>;
+ qcom,strobe-sel = <1>;
+};
+
+&pm8150l_torch0 {
+ qcom,hw-strobe-option = <0>;
+ qcom,strobe-sel = <1>;
+};
+
+&pm8150l_torch1 {
+ qcom,hw-strobe-option = <0>;
+ qcom,strobe-sel = <1>;
+};
+
+&pm8150l_torch2 {
+ qcom,hw-strobe-option = <0>;
+ qcom,strobe-sel = <1>;
+};
+
+&wil6210 {
+ status = "disabled";
+};
+
+&key_home_default {
+ pins = "gpio7";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-overlay.dts
new file mode 100755
index 0000000..589db27
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-kona.h>
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "kona-xrfusion.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona XR 5G Fusion";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x1020008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-ult-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-ult-overlay.dts
new file mode 100755
index 0000000..004cd8a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-ult-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,gcc-kona.h>
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "kona-xrfusion-ult.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona XR 5G UltraSound";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x1030008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-ult.dts b/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-ult.dts
new file mode 100755
index 0000000..9ef6559
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-ult.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona.dtsi"
+#include "kona-xrfusion-ult.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona XR 5G UltraSound";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x1030008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-ult.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-ult.dtsi
new file mode 100755
index 0000000..d9c6978
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion-ult.dtsi
@@ -0,0 +1,1239 @@
+#include <dt-bindings/gpio/gpio.h>
+#include "kona-pmic-overlay.dtsi"
+#include "kona-sde-display.dtsi"
+#include "kona-audio-overlay.dtsi"
+#include "kona-audio-overlay-ar.dtsi"
+#include "kona-thermal-overlay.dtsi"
+#include "kona-xr-pinctrl-overlay.dtsi"
+#include "camera/kona-camera-sensor-xrfusion.dtsi"
+
+&tlmm {
+ mag_rst_gpio_default: mag_rst_gpio_default {
+ mux {
+ pins = "gpio125";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio125";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ output-high;
+ };
+ };
+
+ mag_rst_gpio_sleep: mag_rst_gpio_sleep {
+ mux {
+ pins = "gpio125";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio125";
+ drive-strength = <8>;
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ display_panel_led1_default: display_panel_led1_default {
+ mux {
+ pins = "gpio144";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio144";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ output-high;
+ };
+ };
+
+ display_panel_led2_default: display_panel_led2_default {
+ mux {
+ pins = "gpio140";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio140";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ output-high;
+ };
+ };
+
+ spkr_1_sd_n {
+ spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+ mux {
+ pins = "gpio127";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio127";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_1_sd_n_active: spkr_1_sd_n_active {
+ mux {
+ pins = "gpio127";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio127";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ spkr_2_sd_n {
+ spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
+ mux {
+ pins = "gpio129";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio129";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_2_sd_n_active: spkr_2_sd_n_active {
+ mux {
+ pins = "gpio129";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio129";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ cam_sensor_6dof_vana_active: cam_sensor_6dof_vana_active {
+ /* AVDD LDO */
+ mux {
+ pins = "gpio43";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio43";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vana_suspend: cam_sensor_6dof_vana_suspend {
+ /* AVDD LDO */
+ mux {
+ pins = "gpio43";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio43";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vdig_active: cam_sensor_6dof_vdig_active {
+ /* VDIG LDO */
+ mux {
+ pins = "gpio42";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio42";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vdig_suspend: cam_sensor_6dof_vdig_suspend {
+ /* VDIG LDO */
+ mux {
+ pins = "gpio42";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio42";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vio_active: cam_sensor_6dof_vio_active {
+ /* VIO LDO */
+ mux {
+ pins = "gpio41";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio41";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vio_suspend: cam_sensor_6dof_vio_suspend {
+ /* VIO LDO */
+ mux {
+ pins = "gpio41";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio41";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+};
+
+&vendor {
+ kona_xrfusion_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "fg-gen4-batterydata-goertek-6100mah.dtsi"
+ };
+};
+
+&qupv3_se12_2uart {
+ status = "okay";
+};
+
+&pm8150a_amoled {
+ status = "disabled";
+};
+
+&qupv3_se6_4uart {
+ status = "ok";
+};
+
+&dai_mi2s2 {
+ status = "disabled";
+ qcom,msm-mi2s-tx-lines = <1>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
+ &tert_mi2s_sd0_active>;
+ pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
+ &tert_mi2s_sd0_sleep>;
+};
+
+&kona_snd {
+ qcom,model = "kona-xrfusionult-snd-card";
+ qcom,mi2s-audio-intf = <0>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Analog Mic4",
+ "AMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Analog Mic5",
+ "DMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic0",
+ "DMIC2", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic1",
+ "DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "DMIC4", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "DMIC5", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic4",
+ "DMIC6", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic5",
+ "DMIC7", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic6",
+ "DMIC8", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic7",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
+ qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
+ qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
+ asoc-codec = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
+ "msm-ext-disp-audio-codec-rx";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>,
+ <&wsa881x_0213>, <&wsa881x_0214>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+ "SpkrLeft", "SpkrRight";
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&wcd938x_codec>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
+ <&bolero>;
+};
+
+&kona_snd_ar {
+ qcom,model = "kona-xrfusionult-snd-card";
+ qcom,mi2s-audio-intf = <0>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Analog Mic4",
+ "AMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Analog Mic5",
+ "DMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic0",
+ "DMIC2", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic1",
+ "DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "DMIC4", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "DMIC5", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic4",
+ "DMIC6", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic5",
+ "DMIC7", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic6",
+ "DMIC8", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic7",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT";
+};
+
+&pm8150_l10 {
+ regulator-max-microvolt = <3304000>;
+ qcom,init-voltage = <3304000>;
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ qcom,clk-freq-out = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ xrfancontroller: xrfancontroller@50 {
+ compatible = "maxim,xrfancontroller";
+ reg = <0x50>;
+ /* Manetometer gpio */
+ mag_rst_gpio = <&tlmm 125 0>;
+ enable-active-high;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mag_rst_gpio_default>;
+ pinctrl-1 = <&mag_rst_gpio_sleep>;
+ qcom,fan-pwr-en = <&tlmm 38 0x00>;
+ qcom,fan-pwr-bp = <&tlmm 39 0x00>;
+ };
+};
+
+&qupv3_se13_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v4";
+
+ vdda-phy-supply = <&pm8150_l5>;
+ vdda-phy-always-on;
+ vdda-pll-supply = <&pm8150_l9>;
+ vdda-phy-max-microamp = <89900>;
+ vdda-pll-max-microamp = <18800>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm8150_l17>;
+ vcc-voltage-level = <2504000 2950000>;
+ vcc-low-voltage-sup;
+ vccq-supply = <&pm8150_l6>;
+ vccq2-supply = <&pm8150_s4>;
+ vcc-max-microamp = <800000>;
+ vccq-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+
+ qcom,vddp-ref-clk-supply = <&pm8150_l6>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vccq-parent-supply = <&pm8150a_s8>;
+ qcom,vccq-parent-max-microamp = <210000>;
+
+ status = "ok";
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default
+ &key_confirm_default
+ &key_vol_up_default>;
+
+ home {
+ label = "home";
+ gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_BACK>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+
+ confirm {
+ label = "confirm";
+ gpios = <&pm8150_gpios 7 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_ENTER>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+
+ qcom,qbt_handler {
+ status = "disabled";
+ };
+
+ qcom,xr-stdalonevwr-misc {
+ compatible = "qcom,xr-stdalonevwr-misc";
+ /* IMU CLK Enable PM8150 GPIO 3 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&imu_clkin_default>;
+ pinctrl-1 = <&imu_clkin_sleep>;
+ };
+};
+
+&vreg_hap_boost {
+ status = "ok";
+};
+
+&pm8150b_haptics {
+ qcom,vmax-mv = <1697>;
+ qcom,play-rate-us = <5882>;
+ vdd-supply = <&vreg_hap_boost>;
+
+ wf_0 {
+ /* CLICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_1 {
+ /* DOUBLE CLICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_2 {
+ /* TICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_3 {
+ /* THUD */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_4 {
+ /* POP */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_5 {
+ /* HEAVY CLICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+};
+
+&pm8150b_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "conn_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ chg_sbux@99 {
+ reg = <ADC_SBUx>;
+ label = "chg_sbux";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ mid_chg_div6@1e {
+ reg = <ADC_MID_CHG_DIV6>;
+ label = "chg_mid";
+ qcom,pre-scaling = <1 6>;
+ };
+
+ usb_in_i_uv@7 {
+ reg = <ADC_USB_IN_I>;
+ label = "usb_in_i_uv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ usb_in_v_div_16@8 {
+ reg = <ADC_USB_IN_V_16>;
+ label = "usb_in_v_div_16";
+ qcom,pre-scaling = <1 16>;
+ };
+};
+
+&qupv3_se15_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "ok";
+ redriver: redriver@1c {
+ compatible = "onnn,redriver";
+ reg = <0x1c>;
+ extcon = <&pm8150b_pdphy>, <&pm8150b_pdphy>;
+ eq = /bits/ 8 <
+ /* Parameters for USB */
+ 0x4 0x4 0x4 0x4
+ /* Parameters for DP */
+ 0x6 0x4 0x4 0x6>;
+ flat-gain = /bits/ 8 <
+ /* Parameters for USB */
+ 0x3 0x1 0x1 0x3
+ /* Parameters for DP */
+ 0x2 0x1 0x1 0x2>;
+ output-comp = /bits/ 8 <
+ /* Parameters for USB */
+ 0x3 0x3 0x3 0x3
+ /* Parameters for DP */
+ 0x3 0x3 0x3 0x3>;
+ loss-match = /bits/ 8 <
+ /* Parameters for USB */
+ 0x1 0x3 0x3 0x1
+ /* Parameters for DP */
+ 0x3 0x3 0x3 0x3>;
+ };
+
+ #include "smb1390.dtsi"
+};
+
+&smb1390 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_stat_default>;
+ status = "ok";
+};
+
+&smb1390_charger {
+ io-channels = <&pm8150b_vadc ADC_AMUX_THM2>;
+ io-channel-names = "cp_die_temp";
+ qcom,parallel-output-mode = <2>;
+ status = "ok";
+};
+
+&smb1390_slave {
+ status = "ok";
+};
+
+&smb1390_slave_charger {
+ status = "ok";
+};
+
+&pm8150b_charger {
+ status = "ok";
+ qcom,sec-charger-config = <1>;
+ qcom,auto-recharge-soc = <98>;
+ io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>,
+ <&pm8150b_vadc ADC_USB_IN_I>,
+ <&pm8150b_vadc ADC_SBUx>,
+ <&pm8150b_vadc ADC_VPH_PWR>,
+ <&pm8150b_vadc ADC_CHG_TEMP>;
+ io-channel-names = "mid_voltage",
+ "usb_in_current",
+ "sbux_res",
+ "vph_voltage",
+ "chg_temp";
+ qcom,battery-data = <&kona_xrfusion_batterydata>;
+ qcom,sw-jeita-enable;
+ qcom,wd-bark-time-secs = <16>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,thermal-mitigation = <5325000 4500000 4000000 3500000 3000000
+ 2500000 2000000 1500000 1000000 500000>;
+};
+
+&pm8150b_fg {
+ status = "ok";
+ qcom,battery-data = <&kona_xrfusion_batterydata>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,five-pin-battery;
+ qcom,cl-wt-enable;
+ qcom,soc-scale-mode-en;
+ /* ESR fast calibration */
+ qcom,fg-esr-timer-chg-fast = <0 7>;
+ qcom,fg-esr-timer-dischg-fast = <0 7>;
+ qcom,fg-esr-timer-chg-slow = <0 96>;
+ qcom,fg-esr-timer-dischg-slow = <0 96>;
+ qcom,fg-esr-cal-soc-thresh = <26 230>;
+ qcom,fg-esr-cal-temp-thresh = <10 40>;
+};
+
+&pm8150_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vcoin@85 {
+ reg = <ADC_VCOIN>;
+ label = "vcoin";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ xo_therm@4c {
+ reg = <ADC_XO_THERM_PU2>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "pa_therm1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150l_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ camera_flash_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "camera_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_msm_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "skin_msm_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm2@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "pa_therm2";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150b_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ io-channels = <&pm8150b_vadc ADC_AMUX_THM3_PU2>;
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ io-channels = <&pm8150_vadc ADC_XO_THERM_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM1_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM2_PU2>;
+
+ xo_therm@4c {
+ reg = <ADC_XO_THERM_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150l_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera_flash_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ skin_msm_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm2@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&spmi_debug_bus {
+ status = "ok";
+};
+
+&sde_dsi {
+ avdd-supply = <&display_panel_avdd>;
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+ qcom,dsi-default-panel = <&dsi_dual_xrsmrtvwr_jdi_video>;
+};
+
+&display_panel_avdd {
+ display_panel_led1_gpio = <&tlmm 144 0>;
+ display_panel_led2_gpio = <&tlmm 140 0>;
+ enable-active-high;
+ regulator-boot-on;
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_panel_led1_default
+ &display_panel_led2_default>;
+};
+
+&dsi_panel_pwr_supply_lab_ibb {
+ qcom,panel-supply-entry@3 {
+ reg = <1>;
+ qcom,supply-name = "avdd";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+};
+
+&pm8150l_lcdb {
+ status = "ok";
+};
+
+&pm8150l_wled {
+ status = "ok";
+};
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&thermal_zones {
+ conn-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM3_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-msm-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&sdhc_2 {
+ vdd-supply = <&pm8150a_l9>;
+ qcom,vdd-voltage-level = <2950000 2960000>;
+ qcom,vdd-current-level = <200 800000>;
+
+ vdd-io-supply = <&pm8150a_l6>;
+ qcom,vdd-io-voltage-level = <1808000 2960000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>;
+
+
+ status = "ok";
+};
+
+&vendor {
+ bluetooth: bt_qca6390 {
+ compatible = "qca,qca6390";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en_sleep>;
+ qca,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */
+ qca,bt-sw-ctrl-gpio = <&tlmm 124 0>; /* SW_CTRL */
+ qca,bt-vdd-aon-supply = <&pm8150_s6>;
+ qca,bt-vdd-dig-supply = <&pm8009_s2>;
+ qca,bt-vdd-rfa1-supply = <&pm8150_s5>;
+ qca,bt-vdd-rfa2-supply = <&pm8150a_s8>;
+ qca,bt-vdd-asd-supply = <&pm8150_l16>;
+
+ qca,bt-vdd-aon-voltage-level = <950000 950000>;
+ qca,bt-vdd-dig-voltage-level = <950000 952000>;
+ qca,bt-vdd-rfa1-voltage-level = <1900000 1900000>;
+ qca,bt-vdd-rfa2-voltage-level = <1350000 1350000>;
+ qca,bt-vdd-asd-voltage-level = <3024000 3304000>;
+
+ qca,bt-vdd-asd-current-level = <10000>;
+ };
+};
+
+&usb0 {
+ dwc3@a600000 {
+ maximum-speed = "super-speed-plus";
+ };
+};
+
+&usb1 {
+ qcom,default-mode-none;
+};
+
+&wil6210 {
+ status = "ok";
+};
+
+&usb2_phy0 {
+ qcom,param-override-seq =
+ <0xc7 0x6c
+ 0x0f 0x70
+ 0x03 0x74>;
+};
+
+&mdss_mdp {
+ qcom,sde-mixer-display-pref = "primary", "primary", "primary",
+ "primary", "none", "none";
+ connectors = <&sde_dp &sde_dsi &sde_dsi1 &sde_rscc>;
+};
+
+&sde_wb {
+ status = "disabled";
+};
+
+&dsi_dual_xrsmrtvwr_jdi_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+
+ qcom,platform-bklight-en-gpio = <&tlmm 133 0>;
+ qcom,5v-boost-gpio = <&tlmm 134 0>;
+ /delete-property/ qcom,platform-en-gpio;
+
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-min-refresh-rate = <60>;
+ qcom,mdss-dsi-max-refresh-rate = <90>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <2160>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <20>;
+ qcom,mdss-dsi-h-back-porch = <20>;
+ qcom,mdss-dsi-h-pulse-width = <20>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <20>;
+ qcom,mdss-dsi-v-front-porch = <936>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-on-command = [
+ 29 01 00 00 00 00 02 B0 04
+ 29 01 00 00 00 00 02 D6 00
+ 29 01 00 00 00 00 0A B6 30 6B 80 06 33
+ 8A 00 1A 7A
+ 29 01 00 00 00 00 05 B7 54 00 00 00
+ 29 01 00 00 00 00 05 B9 10 00 01 38
+ 29 01 00 00 00 00 09 C0 51 86 64 00 08
+ 70 07 00
+ 29 01 00 00 00 00 02 F1 1E
+ 29 01 00 00 00 00 11 C6 70 08 D0 02 21
+ 6F 08 5A 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 02 CD 00
+ 29 01 00 00 00 00 08 CF 8B 00 80 46 61
+ 00 8B
+ 29 01 00 00 00 00 06 EC 02 96 00 00 00
+ 39 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 03 44 00 00
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 36 00
+ 39 01 00 00 00 00 02 3A 77
+ 05 01 00 00 02 00 02 29 00
+ 05 01 00 00 80 00 02 11 00
+ 29 01 00 00 00 00 02 D6 80
+ 29 01 00 00 00 00 02 B0 03
+ ];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 32 00 02 34 00
+ 05 01 00 00 78 00 02 10 00
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ qcom,mdss-dsi-panel-phy-timings = [00 17 05 05 20 1F
+ 06 06 03 02 04 00 13 15];
+ qcom,display-topology = <4 4 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+
+ };
+ };
+};
+
+&pcie0 {
+ qcom,target-link-speed = <0x2>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion.dts b/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion.dts
new file mode 100755
index 0000000..5ccc3ba
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "kona.dtsi"
+#include "kona-xrfusion.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona XR 5G Fusion";
+ compatible = "qcom,kona-mtp", "qcom,kona", "qcom,mtp";
+ qcom,board-id = <0x1020008 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion.dtsi
new file mode 100755
index 0000000..5d27eb9
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona-xrfusion.dtsi
@@ -0,0 +1,1175 @@
+#include <dt-bindings/gpio/gpio.h>
+#include "kona-pmic-overlay.dtsi"
+#include "kona-sde-display.dtsi"
+#include "kona-audio-overlay.dtsi"
+#include "kona-audio-overlay-ar.dtsi"
+#include "kona-thermal-overlay.dtsi"
+#include "kona-xr-pinctrl-overlay.dtsi"
+#include "camera/kona-camera-sensor-xrfusion.dtsi"
+
+&tlmm {
+ display_panel_led1_default: display_panel_led1_default {
+ mux {
+ pins = "gpio144";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio144";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ output-high;
+ };
+ };
+
+ display_panel_led2_default: display_panel_led2_default {
+ mux {
+ pins = "gpio140";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio140";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ output-high;
+ };
+ };
+
+ spkr_1_sd_n {
+ spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+ mux {
+ pins = "gpio127";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio127";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_1_sd_n_active: spkr_1_sd_n_active {
+ mux {
+ pins = "gpio127";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio127";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ spkr_2_sd_n {
+ spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
+ mux {
+ pins = "gpio129";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio129";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_2_sd_n_active: spkr_2_sd_n_active {
+ mux {
+ pins = "gpio129";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio129";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ cam_sensor_6dof_vana_active: cam_sensor_6dof_vana_active {
+ /* AVDD LDO */
+ mux {
+ pins = "gpio43";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio43";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vana_suspend: cam_sensor_6dof_vana_suspend {
+ /* AVDD LDO */
+ mux {
+ pins = "gpio43";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio43";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vdig_active: cam_sensor_6dof_vdig_active {
+ /* VDIG LDO */
+ mux {
+ pins = "gpio42";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio42";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vdig_suspend: cam_sensor_6dof_vdig_suspend {
+ /* VDIG LDO */
+ mux {
+ pins = "gpio42";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio42";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vio_active: cam_sensor_6dof_vio_active {
+ /* VIO LDO */
+ mux {
+ pins = "gpio41";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio41";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_6dof_vio_suspend: cam_sensor_6dof_vio_suspend {
+ /* VIO LDO */
+ mux {
+ pins = "gpio41";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio41";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+};
+
+&vendor {
+ kona_xrfusion_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "fg-gen4-batterydata-goertek-6100mah.dtsi"
+ };
+};
+
+&qupv3_se12_2uart {
+ status = "okay";
+};
+
+&pm8150a_amoled {
+ status = "disabled";
+};
+
+&qupv3_se6_4uart {
+ status = "ok";
+};
+
+&dai_mi2s2 {
+ status = "disabled";
+ qcom,msm-mi2s-tx-lines = <1>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&tert_mi2s_sck_active &tert_mi2s_ws_active
+ &tert_mi2s_sd0_active>;
+ pinctrl-1 = <&tert_mi2s_sck_sleep &tert_mi2s_ws_sleep
+ &tert_mi2s_sd0_sleep>;
+};
+
+&kona_snd {
+ qcom,model = "kona-xrfusion-snd-card";
+ qcom,mi2s-audio-intf = <0>;
+ qcom,audio-routing =
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "TX DMIC0", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic0",
+ "TX DMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic1",
+ "TX DMIC2", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic2",
+ "TX DMIC3", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic3",
+ "TX DMIC5", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic5",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
+ qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
+ qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
+ asoc-codec = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
+ "msm-ext-disp-audio-codec-rx";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>,
+ <&wsa881x_0213>, <&wsa881x_0214>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+ "SpkrLeft", "SpkrRight";
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&wcd938x_codec>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>,
+ <&bolero>;
+};
+
+&kona_snd_ar {
+ qcom,model = "kona-xrfusion-snd-card";
+ qcom,mi2s-audio-intf = <0>;
+ qcom,audio-routing =
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "TX DMIC0", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic0",
+ "TX DMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic1",
+ "TX DMIC2", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic2",
+ "TX DMIC3", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic3",
+ "TX DMIC5", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic5",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT";
+};
+
+&pm8150_l10 {
+ regulator-max-microvolt = <3304000>;
+ qcom,init-voltage = <3304000>;
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ qcom,clk-freq-out = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ xrfancontroller: xrfancontroller@50 {
+ compatible = "maxim,xrfancontroller";
+ reg = <0x50>;
+ qcom,fan-pwr-en = <&tlmm 38 0x00>;
+ qcom,fan-pwr-bp = <&tlmm 39 0x00>;
+ };
+};
+
+&qupv3_se13_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v4";
+
+ vdda-phy-supply = <&pm8150_l5>;
+ vdda-phy-always-on;
+ vdda-pll-supply = <&pm8150_l9>;
+ vdda-phy-max-microamp = <89900>;
+ vdda-pll-max-microamp = <18800>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm8150_l17>;
+ vcc-voltage-level = <2504000 2950000>;
+ vcc-low-voltage-sup;
+ vccq-supply = <&pm8150_l6>;
+ vccq2-supply = <&pm8150_s4>;
+ vcc-max-microamp = <800000>;
+ vccq-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+
+ qcom,vddp-ref-clk-supply = <&pm8150_l6>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vccq-parent-supply = <&pm8150a_s8>;
+ qcom,vccq-parent-max-microamp = <210000>;
+
+ status = "ok";
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default
+ &key_confirm_default
+ &key_vol_up_default>;
+
+ home {
+ label = "home";
+ gpios = <&pm8150_gpios 1 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_BACK>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+
+ confirm {
+ label = "confirm";
+ gpios = <&pm8150_gpios 7 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_ENTER>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm8150_gpios 6 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+
+ qcom,qbt_handler {
+ status = "disabled";
+ };
+
+ qcom,xr-stdalonevwr-misc {
+ status ="ok";
+ compatible = "qcom,xr-stdalonevwr-misc";
+ /* IMU CLK Enable PM8150 GPIO 3 */
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&imu_clkin_default>;
+ pinctrl-1 = <&imu_clkin_sleep>;
+ };
+};
+
+&vreg_hap_boost {
+ status = "ok";
+};
+
+&pm8150b_haptics {
+ qcom,vmax-mv = <1697>;
+ qcom,play-rate-us = <5882>;
+ vdd-supply = <&vreg_hap_boost>;
+
+ wf_0 {
+ /* CLICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_1 {
+ /* DOUBLE CLICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_2 {
+ /* TICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_3 {
+ /* THUD */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_4 {
+ /* POP */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+
+ wf_5 {
+ /* HEAVY CLICK */
+ qcom,wf-play-rate-us = <5882>;
+ qcom,wf-vmax-mv = <1697>;
+ };
+};
+
+&pm8150b_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "conn_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ chg_sbux@99 {
+ reg = <ADC_SBUx>;
+ label = "chg_sbux";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ mid_chg_div6@1e {
+ reg = <ADC_MID_CHG_DIV6>;
+ label = "chg_mid";
+ qcom,pre-scaling = <1 6>;
+ };
+
+ usb_in_i_uv@7 {
+ reg = <ADC_USB_IN_I>;
+ label = "usb_in_i_uv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ usb_in_v_div_16@8 {
+ reg = <ADC_USB_IN_V_16>;
+ label = "usb_in_v_div_16";
+ qcom,pre-scaling = <1 16>;
+ };
+};
+
+&qupv3_se15_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "ok";
+ redriver: redriver@1c {
+ compatible = "onnn,redriver";
+ reg = <0x1c>;
+ extcon = <&pm8150b_pdphy>, <&pm8150b_pdphy>;
+ eq = /bits/ 8 <
+ /* Parameters for USB */
+ 0x4 0x4 0x4 0x4
+ /* Parameters for DP */
+ 0x6 0x4 0x4 0x6>;
+ flat-gain = /bits/ 8 <
+ /* Parameters for USB */
+ 0x3 0x1 0x1 0x3
+ /* Parameters for DP */
+ 0x2 0x1 0x1 0x2>;
+ output-comp = /bits/ 8 <
+ /* Parameters for USB */
+ 0x3 0x3 0x3 0x3
+ /* Parameters for DP */
+ 0x3 0x3 0x3 0x3>;
+ loss-match = /bits/ 8 <
+ /* Parameters for USB */
+ 0x1 0x3 0x3 0x1
+ /* Parameters for DP */
+ 0x3 0x3 0x3 0x3>;
+ };
+
+ #include "smb1390.dtsi"
+};
+
+&smb1390 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_stat_default>;
+ status = "ok";
+};
+
+&smb1390_charger {
+ io-channels = <&pm8150b_vadc ADC_AMUX_THM2>;
+ io-channel-names = "cp_die_temp";
+ qcom,parallel-output-mode = <2>;
+ status = "ok";
+};
+
+&smb1390_slave {
+ status = "ok";
+};
+
+&smb1390_slave_charger {
+ status = "ok";
+};
+
+&pm8150b_charger {
+ status = "ok";
+ qcom,sec-charger-config = <1>;
+ qcom,auto-recharge-soc = <98>;
+ io-channels = <&pm8150b_vadc ADC_MID_CHG_DIV6>,
+ <&pm8150b_vadc ADC_USB_IN_I>,
+ <&pm8150b_vadc ADC_SBUx>,
+ <&pm8150b_vadc ADC_VPH_PWR>,
+ <&pm8150b_vadc ADC_CHG_TEMP>;
+ io-channel-names = "mid_voltage",
+ "usb_in_current",
+ "sbux_res",
+ "vph_voltage",
+ "chg_temp";
+ qcom,battery-data = <&kona_xrfusion_batterydata>;
+ qcom,sw-jeita-enable;
+ qcom,wd-bark-time-secs = <16>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,thermal-mitigation = <5325000 4500000 4000000 3500000 3000000
+ 2500000 2000000 1500000 1000000 500000>;
+};
+
+&pm8150b_fg {
+ status = "ok";
+ qcom,battery-data = <&kona_xrfusion_batterydata>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,five-pin-battery;
+ qcom,cl-wt-enable;
+ qcom,soc-scale-mode-en;
+ /* ESR fast calibration */
+ qcom,fg-esr-timer-chg-fast = <0 7>;
+ qcom,fg-esr-timer-dischg-fast = <0 7>;
+ qcom,fg-esr-timer-chg-slow = <0 96>;
+ qcom,fg-esr-timer-dischg-slow = <0 96>;
+ qcom,fg-esr-cal-soc-thresh = <26 230>;
+ qcom,fg-esr-cal-temp-thresh = <10 40>;
+};
+
+&pm8150_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vcoin@85 {
+ reg = <ADC_VCOIN>;
+ label = "vcoin";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ xo_therm@4c {
+ reg = <ADC_XO_THERM_PU2>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "pa_therm1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150l_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ camera_flash_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "camera_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_msm_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "skin_msm_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm2@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "pa_therm2";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150b_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ io-channels = <&pm8150b_vadc ADC_AMUX_THM3_PU2>;
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ io-channels = <&pm8150_vadc ADC_XO_THERM_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM1_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM2_PU2>;
+
+ xo_therm@4c {
+ reg = <ADC_XO_THERM_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150l_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera_flash_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ skin_msm_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm2@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&spmi_debug_bus {
+ status = "ok";
+};
+
+&sde_dsi {
+ avdd-supply = <&display_panel_avdd>;
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+ qcom,dsi-default-panel = <&dsi_dual_xrsmrtvwr_jdi_video>;
+};
+
+&display_panel_avdd {
+ display_panel_led1_gpio = <&tlmm 144 0>;
+ display_panel_led2_gpio = <&tlmm 140 0>;
+ enable-active-high;
+ regulator-boot-on;
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_panel_led1_default
+ &display_panel_led2_default>;
+};
+
+&dsi_panel_pwr_supply_lab_ibb {
+ qcom,panel-supply-entry@3 {
+ reg = <1>;
+ qcom,supply-name = "avdd";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+};
+
+&pm8150l_lcdb {
+ status = "ok";
+};
+
+&pm8150l_wled {
+ status = "ok";
+};
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,mdss-dsi-panel-test-pin = <&tlmm 46 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_sim_dsc_10b_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+};
+
+&thermal_zones {
+ conn-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150b_adc_tm ADC_AMUX_THM3_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-msm-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&sdhc_2 {
+ vdd-supply = <&pm8150a_l9>;
+ qcom,vdd-voltage-level = <2950000 2960000>;
+ qcom,vdd-current-level = <200 800000>;
+
+ vdd-io-supply = <&pm8150a_l6>;
+ qcom,vdd-io-voltage-level = <1808000 2960000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>;
+
+ cd-gpios = <&tlmm 77 GPIO_ACTIVE_HIGH>; /* Morpheus has to be HIGH */
+
+ status = "ok";
+};
+
+&vendor {
+ bluetooth: bt_qca6390 {
+ compatible = "qca,qca6390";
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_en_sleep>;
+ qca,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */
+ qca,bt-sw-ctrl-gpio = <&tlmm 124 0>; /* SW_CTRL */
+ qca,bt-vdd-aon-supply = <&pm8150_s6>;
+ qca,bt-vdd-dig-supply = <&pm8009_s2>;
+ qca,bt-vdd-rfa1-supply = <&pm8150_s5>;
+ qca,bt-vdd-rfa2-supply = <&pm8150a_s8>;
+ qca,bt-vdd-asd-supply = <&pm8150_l16>;
+
+ qca,bt-vdd-aon-voltage-level = <950000 950000>;
+ qca,bt-vdd-dig-voltage-level = <950000 952000>;
+ qca,bt-vdd-rfa1-voltage-level = <1900000 1900000>;
+ qca,bt-vdd-rfa2-voltage-level = <1350000 1350000>;
+ qca,bt-vdd-asd-voltage-level = <3024000 3304000>;
+
+ qca,bt-vdd-asd-current-level = <10000>;
+ };
+};
+
+&usb0 {
+ dwc3@a600000 {
+ maximum-speed = "super-speed-plus";
+ };
+};
+
+&usb1 {
+ qcom,default-mode-none;
+};
+
+&wil6210 {
+ status = "ok";
+};
+
+&usb2_phy0 {
+ qcom,param-override-seq =
+ <0xc7 0x6c
+ 0x0f 0x70
+ 0x03 0x74>;
+};
+
+&mdss_mdp {
+ qcom,sde-mixer-display-pref = "primary", "primary", "primary",
+ "primary", "none", "none";
+ connectors = <&sde_dp &sde_dsi &sde_dsi1 &sde_rscc>;
+};
+
+&sde_wb {
+ status = "disabled";
+};
+
+&dsi_dual_xrsmrtvwr_jdi_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_lab_ibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-reset-gpio = <&tlmm 75 0>;
+ qcom,platform-te-gpio = <&tlmm 66 0>;
+
+ qcom,platform-bklight-en-gpio = <&tlmm 133 0>;
+ qcom,5v-boost-gpio = <&tlmm 134 0>;
+ /delete-property/ qcom,platform-en-gpio;
+
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-min-refresh-rate = <60>;
+ qcom,mdss-dsi-max-refresh-rate = <90>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <2160>;
+ qcom,mdss-dsi-panel-height = <2160>;
+ qcom,mdss-dsi-h-front-porch = <20>;
+ qcom,mdss-dsi-h-back-porch = <20>;
+ qcom,mdss-dsi-h-pulse-width = <20>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <20>;
+ qcom,mdss-dsi-v-front-porch = <936>;
+ qcom,mdss-dsi-v-pulse-width = <4>;
+ qcom,mdss-dsi-panel-framerate = <90>;
+ qcom,mdss-dsi-on-command = [
+ 29 01 00 00 00 00 02 B0 04
+ 29 01 00 00 00 00 02 D6 00
+ 29 01 00 00 00 00 0A B6 30 6B 80 06 33
+ 8A 00 1A 7A
+ 29 01 00 00 00 00 05 B7 54 00 00 00
+ 29 01 00 00 00 00 05 B9 10 00 01 38
+ 29 01 00 00 00 00 09 C0 51 86 64 00 08
+ 70 07 00
+ 29 01 00 00 00 00 02 F1 1E
+ 29 01 00 00 00 00 11 C6 70 08 D0 02 21
+ 6F 08 5A 00 00 00 00 00 00 00 00
+ 29 01 00 00 00 00 02 CD 00
+ 29 01 00 00 00 00 08 CF 8B 00 80 46 61
+ 00 8B
+ 29 01 00 00 00 00 06 EC 02 96 00 00 00
+ 39 01 00 00 00 00 02 03 01
+ 39 01 00 00 00 00 03 44 00 00
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 36 00
+ 39 01 00 00 00 00 02 3A 77
+ 05 01 00 00 02 00 02 29 00
+ 05 01 00 00 80 00 02 11 00
+ 29 01 00 00 00 00 02 D6 80
+ 29 01 00 00 00 00 02 B0 03
+ ];
+ qcom,mdss-dsi-off-command = [
+ 05 01 00 00 32 00 02 28 00
+ 05 01 00 00 32 00 02 34 00
+ 05 01 00 00 78 00 02 10 00
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <2>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ qcom,mdss-dsi-panel-phy-timings = [00 17 05 05 20 1F
+ 06 06 03 02 04 00 13 15];
+ qcom,display-topology = <4 4 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona.dts b/arch/arm64/boot/dts/vendor/qcom/kona.dts
new file mode 100755
index 0000000..5fbda62
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "kona.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona v1 SoC";
+ compatible = "qcom,kona";
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/kona.dtsi b/arch/arm64/boot/dts/vendor/qcom/kona.dtsi
new file mode 100755
index 0000000..86300ed
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/kona.dtsi
@@ -0,0 +1,5076 @@
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,camcc-kona.h>
+#include <dt-bindings/clock/qcom,cpucc-kona.h>
+#include <dt-bindings/clock/qcom,dispcc-kona.h>
+#include <dt-bindings/clock/qcom,gcc-kona.h>
+#include <dt-bindings/clock/qcom,gpucc-kona.h>
+#include <dt-bindings/clock/qcom,npucc-kona.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,videocc-kona.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/soc/qcom,dcc_v2.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/gpio/gpio.h>
+
+#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
+#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
+
+#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
+ opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
+ opp-supported-hw = <ddrtype>;}
+
+#define DDR_TYPE_LPDDR4X 7
+#define DDR_TYPE_LPDDR5 8
+
+/ {
+ model = "Qualcomm Technologies, Inc. kona";
+ compatible = "qcom,kona";
+ qcom,msm-id = <356 0x10000>;
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+ mem-offline {
+ compatible = "qcom,mem-offline";
+ offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
+ <0x1 0xc0000000 0x0 0x80000000>,
+ <0x2 0xc0000000 0x1 0x40000000>;
+ granule = <512>;
+ mboxes = <&qmp_aop 0>;
+ };
+
+ aliases {
+ ufshc1 = &ufshc_mem; /* Embedded UFS slot */
+ sdhc2 = &sdhc_2; /* SDC2 SD card slot */
+ pci-domain0 = &pcie0; /* PCIe0 domain */
+ pci-domain1 = &pcie1; /* PCIe1 domain */
+ pci-domain2 = &pcie2; /* PCIe2 domain */
+ serial0 = &qupv3_se2_2uart; /* RUMI */
+ swr0 = &swr0;
+ swr1 = &swr1;
+ swr2 = &swr2;
+ swr_ar0 = &swr_ar0;
+ swr_ar1 = &swr_ar1;
+ swr_ar2 = &swr_ar2;
+ mhi-netdev0 = &mhi_netdev_0;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0 4>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ #cooling-cells = <2>;
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+
+ L3_0: l3-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <3>;
+ };
+ };
+
+ L1_I_0: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_0: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ next-level-cache = <&L2_1>;
+ qcom,freq-domain = <&cpufreq_hw 0 4>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ L2_1: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_100: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_100: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ next-level-cache = <&L2_2>;
+ qcom,freq-domain = <&cpufreq_hw 0 4>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ L2_2: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_200: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_200: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ next-level-cache = <&L2_3>;
+ qcom,freq-domain = <&cpufreq_hw 0 4>;
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ L2_3: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_300: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_300: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ next-level-cache = <&L2_4>;
+ qcom,freq-domain = <&cpufreq_hw 1 4>;
+ capacity-dmips-mhz = <1894>;
+ dynamic-power-coefficient = <514>;
+ #cooling-cells = <2>;
+ L2_4: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_400: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_400: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ next-level-cache = <&L2_5>;
+ qcom,freq-domain = <&cpufreq_hw 1 4>;
+ capacity-dmips-mhz = <1894>;
+ dynamic-power-coefficient = <514>;
+ L2_5: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_500: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_500: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ next-level-cache = <&L2_6>;
+ qcom,freq-domain = <&cpufreq_hw 1 4>;
+ capacity-dmips-mhz = <1894>;
+ dynamic-power-coefficient = <514>;
+ L2_6: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_600: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_600: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "qcom,kryo";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ next-level-cache = <&L2_7>;
+ qcom,freq-domain = <&cpufreq_hw 2 4>;
+ capacity-dmips-mhz = <1894>;
+ dynamic-power-coefficient = <598>;
+ #cooling-cells = <2>;
+ L2_7: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_700: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_700: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+ };
+
+
+ cpu_pmu: cpu-pmu {
+ compatible = "arm,armv8-pmuv3";
+ qcom,irq-is-percpu;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ soc: soc {
+ cpufreq_hw: qcom,cpufreq-hw {
+ compatible = "qcom,cpufreq-hw-epss";
+ reg = <0x18591000 0x1000>, <0x18592000 0x1000>,
+ <0x18593000 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1",
+ "freq-domain2";
+
+ clocks = <&clock_rpmh RPMH_CXO_CLK>, <&clock_gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ qcom,lut-row-size = <4>;
+ qcom,skip-enable-check;
+
+ #freq-domain-cells = <2>;
+
+ cpu7_notify: cpu7-notify {
+ qcom,cooling-cpu = <&CPU7>;
+ #cooling-cells = <2>;
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ chosen {
+ bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
+ };
+
+ firmware: firmware {
+ android {
+ compatible = "android,firmware";
+ vbmeta {
+ compatible = "android,vbmeta";
+ parts = "vbmeta,boot,system,vendor,dtbo";
+ };
+
+ fstab {
+ compatible = "android,fstab";
+ vendor {
+ compatible = "android,vendor";
+ dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,discard";
+ fsmgr_flags = "wait,slotselect,avb";
+ status = "ok";
+ };
+ };
+ };
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: hyp_region@80000000 {
+ no-map;
+ reg = <0x0 0x80000000 0x0 0x600000>;
+ };
+
+ xbl_aop_mem: xbl_aop_region@80700000 {
+ no-map;
+ reg = <0x0 0x80700000 0x0 0x160000>;
+ };
+
+ cmd_db: reserved-memory@80860000 {
+ reg = <0x0 0x80860000 0x0 0x20000>;
+ compatible = "qcom,cmd-db";
+ no-map;
+ };
+
+ reserved_xbl_uefi_log: res_xbl_uefi_log_region@80880000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x80880000 0x0 0x14000>;
+ };
+
+ smem_mem: smem_region@80900000 {
+ no-map;
+ reg = <0x0 0x80900000 0x0 0x200000>;
+ };
+
+ removed_mem: removed_region@80b00000 {
+ no-map;
+ reg = <0x0 0x80b00000 0x0 0x5300000>;
+ };
+
+ pil_camera_mem: pil_camera_region@86200000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86200000 0x0 0x500000>;
+ };
+
+ pil_wlan_fw_mem: pil_wlan_fw_region@86700000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86700000 0x0 0x100000>;
+ };
+
+ pil_ipa_fw_mem: pil_ipa_fw_region@86800000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86800000 0x0 0x10000>;
+ };
+
+ pil_ipa_gsi_mem: pil_ipa_gsi_region@86810000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86810000 0x0 0xa000>;
+ };
+
+ pil_gpu_mem: pil_gpu_region@8681a000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8681a000 0x0 0x2000>;
+ };
+
+ pil_npu_mem: pil_npu_region@86900000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86900000 0x0 0x500000>;
+ };
+
+ pil_video_mem: pil_video_region@86e00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86e00000 0x0 0x500000>;
+ };
+
+ pil_cvp_mem: pil_cvp_region@87300000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x87300000 0x0 0x500000>;
+ };
+
+ pil_cdsp_mem: pil_cdsp_region@87800000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x87800000 0x0 0x1400000>;
+ };
+
+ pil_slpi_mem: pil_slpi_region@88c00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x88c00000 0x0 0x1500000>;
+ };
+
+ pil_adsp_mem: pil_adsp_region@8a100000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8a100000 0x0 0x1d00000>;
+ };
+
+ pil_spss_mem: pil_spss_region@8be00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8be00000 0x0 0x100000>;
+ };
+
+ cdsp_secure_heap: cdsp_secure_heap@8bf00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8bf00000 0x0 0x4600000>;
+ };
+
+ adsp_mem: adsp_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0xC00000>;
+ };
+
+ sdsp_mem: sdsp_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x800000>;
+ };
+
+ cdsp_mem: cdsp_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x400000>;
+ };
+
+ cont_splash_memory: cont_splash_region@9c000000 {
+ reg = <0x0 0x9c000000 0x0 0x02300000>;
+ label = "cont_splash_region";
+ };
+
+ disp_rdump_memory: disp_rdump_region@9c000000 {
+ reg = <0x0 0x9c000000 0x0 0x00800000>;
+ label = "disp_rdump_region";
+ };
+
+ dfps_data_memory: dfps_data_region@9e300000 {
+ reg = <0x0 0x9e300000 0x0 0x0100000>;
+ label = "dfps_data_region";
+ };
+
+ dump_mem: mem_dump_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ size = <0 0x2800000>;
+ };
+ sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ user_contig_mem: user_contig_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ qseecom_mem: qseecom_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1400000>;
+ };
+
+ qseecom_ta_mem: qseecom_ta_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ secure_display_memory: secure_display_region { /* Secure UI */
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0xA400000>;
+ };
+
+ cnss_wlan_mem: cnss_wlan_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1400000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+
+ mailbox_mem: mailbox_region {
+ compatible = "shared-dma-pool";
+ no-map;
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x20000>;
+ };
+ };
+
+ vendor: vendor {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+ };
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ thermal_zones: thermal-zones {
+ };
+
+ slim_aud: slim@3ac0000 {
+ cell-index = <1>;
+ compatible = "qcom,slim-ngd";
+ reg = <0x3ac0000 0x2c000>,
+ <0x3a84000 0x2c000>;
+ reg-names = "slimbus_physical", "slimbus_bam_physical";
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "slimbus_irq", "slimbus_bam_irq";
+ qcom,apps-ch-pipes = <0x700000>;
+ qcom,ea-pc = <0x2d0>;
+ iommus = <&apps_smmu 0x1826 0x0>,
+ <&apps_smmu 0x182f 0x0>,
+ <&apps_smmu 0x1830 0x1>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+ qcom,iommu-dma = "atomic";
+ status = "ok";
+
+ /* Slimbus Slave DT for QCA6390 */
+ btfmslim_codec: qca6390 {
+ compatible = "qcom,btfmslim_slave";
+ elemental-addr = [00 01 20 02 17 02];
+ qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
+ qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
+ };
+ };
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ reg = <0x17a00000 0x10000>, /* GICD */
+ <0x17a60000 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ qcom,chd_silver {
+ compatible = "qcom,core-hang-detect";
+ label = "silver";
+ qcom,threshold-arr = <0x18000058 0x18010058
+ 0x18020058 0x18030058>;
+ qcom,config-arr = <0x18000060 0x18010060
+ 0x18020060 0x18030060>;
+ };
+
+ dsu_pmu@0 {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>,
+ <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
+ };
+
+ qcom,chd_gold {
+ compatible = "qcom,core-hang-detect";
+ label = "gold";
+ qcom,threshold-arr = <0x18040058 0x18050058
+ 0x18060058 0x18070058>;
+ qcom,config-arr = <0x18040060 0x18050060
+ 0x18060060 0x18070060>;
+ };
+
+ cache-controller@9200000 {
+ compatible = "qcom,llcc-v2";
+ reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ cap-based-alloc-and-pwr-collapse;
+ };
+
+ wdog: qcom,wdt@17c10000 {
+ compatible = "qcom,msm-watchdog";
+ reg = <0x17c10000 0x1000>;
+ reg-names = "wdt-base";
+ interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
+ <0 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bark-time = <11000>;
+ qcom,pet-time = <9360>;
+ qcom,wakeup-enable;
+ qcom,ipi-ping;
+ };
+
+ arch_timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <19200000>;
+ };
+
+ memtimer: timer@17c20000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x17c20000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@17c21000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c21000 0x1000>,
+ <0x17c22000 0x1000>;
+ };
+
+ frame@17c23000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c23000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c25000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c25000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c27000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c27000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c29000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c29000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c2b000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c2d000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ jtag_mm0: jtagmm@7040000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7040000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU0>;
+ };
+
+ jtag_mm1: jtagmm@7140000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7140000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU1>;
+ };
+
+ jtag_mm2: jtagmm@7240000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7240000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU2>;
+ };
+
+ jtag_mm3: jtagmm@7340000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7340000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU3>;
+ };
+
+ jtag_mm4: jtagmm@7440000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7440000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU4>;
+ };
+
+ jtag_mm5: jtagmm@7540000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7540000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU5>;
+ };
+
+ jtag_mm6: jtagmm@7640000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7640000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU6>;
+ };
+
+ jtag_mm7: jtagmm@7740000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7740000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU7>;
+ };
+
+ qcom,devfreq-l3 {
+ compatible = "qcom,devfreq-fw";
+ reg = <0x18590000 0x4>, <0x18590100 0xa0>, <0x18590320 0x4>;
+ reg-names = "en-base", "ftbl-base", "perf-base";
+
+ cpu0_l3: qcom,cpu0-cpu-l3-lat {
+ compatible = "qcom,devfreq-fw-voter";
+ };
+
+ cpu4_l3: qcom,cpu4-cpu-l3-lat {
+ compatible = "qcom,devfreq-fw-voter";
+ };
+
+ cpu7_l3: qcom,cpu7-cpu-l3-lat {
+ compatible = "qcom,devfreq-fw-voter";
+ };
+
+ cdsp_l3: qcom,cdsp-cdsp-l3-lat {
+ compatible = "qcom,devfreq-fw-voter";
+ };
+ };
+
+ bus_proxy_client: qcom,bus_proxy_client {
+ compatible = "qcom,bus-proxy-client";
+ qcom,msm-bus,name = "bus-proxy-client";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>, <23 512 0 0>,
+ <22 512 1500000 1500000>, <23 512 1500000 1500000>;
+ qcom,msm-bus,active-only;
+ status = "ok";
+ };
+
+ keepalive_opp_table: keepalive-opp-table {
+ compatible = "operating-points-v2";
+ opp-1 {
+ opp-hz = /bits/ 64 < 1 >;
+ };
+ };
+
+ snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive {
+ compatible = "qcom,devbw";
+ governor = "powersave";
+ qcom,src-dst-ports = <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_IMEM_CFG>;
+ qcom,active-only;
+ status = "ok";
+ operating-points-v2 = <&keepalive_opp_table>;
+ };
+
+ llcc_bw_opp_table: llcc-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
+ BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
+ BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
+ BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
+ BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
+ BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
+ BW_OPP_ENTRY( 1000, 16); /* 15258 MB/s */
+ };
+
+ suspendable_llcc_bw_opp_table: suspendable-llcc-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 0, 16); /* 0 MB/s */
+ BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
+ BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
+ BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
+ BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
+ BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
+ BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
+ BW_OPP_ENTRY( 1000, 16); /* 15258 MB/s */
+ };
+
+ ddr_bw_opp_table: ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY_DDR( 200, 4, 0x180); /* 762 MB/s */
+ BW_OPP_ENTRY_DDR( 300, 4, 0x180); /* 1144 MB/s */
+ BW_OPP_ENTRY_DDR( 451, 4, 0x180); /* 1720 MB/s */
+ BW_OPP_ENTRY_DDR( 547, 4, 0x180); /* 2086 MB/s */
+ BW_OPP_ENTRY_DDR( 681, 4, 0x180); /* 2597 MB/s */
+ BW_OPP_ENTRY_DDR( 768, 4, 0x180); /* 2929 MB/s */
+ BW_OPP_ENTRY_DDR( 1017, 4, 0x180); /* 3879 MB/s */
+ BW_OPP_ENTRY_DDR( 1353, 4, 0x80); /* 5161 MB/s */
+ BW_OPP_ENTRY_DDR( 1555, 4, 0x180); /* 5931 MB/s */
+ BW_OPP_ENTRY_DDR( 1804, 4, 0x180); /* 6881 MB/s */
+ BW_OPP_ENTRY_DDR( 2092, 4, 0x180); /* 7980 MB/s */
+ BW_OPP_ENTRY_DDR( 2736, 4, 0x100); /* 10437 MB/s */
+ };
+
+ suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY_DDR( 0, 4, 0x180); /* 0 MB/s */
+ BW_OPP_ENTRY_DDR( 200, 4, 0x180); /* 762 MB/s */
+ BW_OPP_ENTRY_DDR( 300, 4, 0x180); /* 1144 MB/s */
+ BW_OPP_ENTRY_DDR( 451, 4, 0x180); /* 1720 MB/s */
+ BW_OPP_ENTRY_DDR( 547, 4, 0x180); /* 2086 MB/s */
+ BW_OPP_ENTRY_DDR( 681, 4, 0x180); /* 2597 MB/s */
+ BW_OPP_ENTRY_DDR( 768, 4, 0x180); /* 2929 MB/s */
+ BW_OPP_ENTRY_DDR( 1017, 4, 0x180); /* 3879 MB/s */
+ BW_OPP_ENTRY_DDR( 1353, 4, 0x80); /* 5161 MB/s */
+ BW_OPP_ENTRY_DDR( 1555, 4, 0x180); /* 5931 MB/s */
+ BW_OPP_ENTRY_DDR( 1804, 4, 0x180); /* 6881 MB/s */
+ BW_OPP_ENTRY_DDR( 2092, 4, 0x180); /* 7980 MB/s */
+ BW_OPP_ENTRY_DDR( 2736, 4, 0x100); /* 10437 MB/s */
+ };
+
+ llcc_pmu: llcc-pmu@9095000 {
+ compatible = "qcom,llcc-pmu-ver2";
+ reg = <0x09095000 0x300>;
+ reg-names = "lagg-base";
+ };
+
+ cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;
+ qcom,active-only;
+ operating-points-v2 = <&llcc_bw_opp_table>;
+ };
+
+ cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {
+ compatible = "qcom,bimc-bwmon4";
+ reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
+ reg-names = "base", "global_base";
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&cpu_cpu_llcc_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@9091000 {
+ compatible = "qcom,bimc-bwmon5";
+ reg = <0x9091000 0x1000>;
+ reg-names = "base";
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&cpu_llcc_ddr_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ npu_npu_llcc_bw: qcom,npu-npu-llcc-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_LLCC>;
+ operating-points-v2 = <&suspendable_llcc_bw_opp_table>;
+ };
+
+ npu_npu_llcc_bwmon: qcom,npu-npu-llcc-bwmon@60300 {
+ compatible = "qcom,bimc-bwmon4";
+ reg = <0x00060400 0x300>, <0x00060300 0x200>;
+ reg-names = "base", "global_base";
+ qcom,msm_bus = <154 10070>;
+ qcom,msm_bus_name = "npu_bwmon_cdsp";
+ clocks = <&clock_gcc GCC_NPU_BWMON_CFG_AHB_CLK>,
+ <&clock_gcc GCC_NPU_BWMON_AXI_CLK>;
+ clock-names = "npu_bwmon_ahb", "npu_bwmon_axi";
+ qcom,bwmon_clks = "npu_bwmon_ahb", "npu_bwmon_axi";
+ interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&npu_npu_llcc_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ npu_llcc_ddr_bw: qcom,npu-llcc-ddr-bw {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports = <MSM_BUS_SLAVE_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
+ };
+
+ npu_llcc_ddr_bwmon: qcom,npu-llcc-ddr-bwmon@0x9093000 {
+ compatible = "qcom,bimc-bwmon5";
+ reg = <0x9093000 0x1000>;
+ reg-names = "base";
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&npu_llcc_ddr_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ npudsp_npu_ddr_bw: qcom,npudsp-npu-ddr-bw {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;
+ operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
+ };
+
+ npudsp_npu_ddr_bwmon: qcom,npudsp-npu-ddr-bwmon@70200 {
+ compatible = "qcom,bimc-bwmon4";
+ reg = <0x00070300 0x300>, <0x00070200 0x200>;
+ reg-names = "base", "global_base";
+ qcom,msm_bus = <154 10070>;
+ qcom,msm_bus_name = "npudsp_bwmon_cdsp";
+ clocks = <&clock_gcc GCC_NPU_BWMON_CFG_AHB_CLK>,
+ <&clock_gcc GCC_NPU_BWMON_AXI_CLK>;
+ clock-names = "npu_bwmon_ahb", "npu_bwmon_axi";
+ qcom,bwmon_clks = "npu_bwmon_ahb", "npu_bwmon_axi";
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&npudsp_npu_ddr_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ npu_npu_ddr_latfloor: qcom,npu-npu-ddr-latfloor {
+ compatible = "qcom,devbw-ddr";
+ governor = "powersave";
+ qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;
+ operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
+ };
+
+ npu_staticmap_mon: qcom,npu-staticmap-mon {
+ compatible = "qcom,static-map";
+ qcom,target-dev = <&npu_npu_ddr_latfloor>;
+ clocks = <&clock_npucc NPU_CC_CAL_HM0_CLK>;
+ clock-names = "cal_hm0_clk";
+ qcom,dev_clk = "cal_hm0_clk";
+ qcom,core-dev-table =
+ < 0 MHZ_TO_MBPS( 0, 4) >,
+ < 300000 MHZ_TO_MBPS( 451, 4) >,
+ < 406000 MHZ_TO_MBPS( 768, 4) >,
+ < 533000 MHZ_TO_MBPS( 1555, 4) >,
+ < 730000 MHZ_TO_MBPS( 1804, 4) >,
+ < 920000 MHZ_TO_MBPS( 2092, 4) >,
+ < 1000000 MHZ_TO_MBPS( 2736, 4) >;
+ };
+
+ cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;
+ qcom,active-only;
+ operating-points-v2 = <&llcc_bw_opp_table>;
+ };
+
+ cpu4_cpu_llcc_lat: qcom,cpu4-cpu-llcc-lat {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;
+ qcom,active-only;
+ operating-points-v2 = <&llcc_bw_opp_table>;
+ };
+
+ cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu4_llcc_ddr_lat: qcom,cpu4-llcc-ddr-lat {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ qoslat_opp_table: qoslat-opp-table {
+ compatible = "operating-points-v2";
+ opp-0 {
+ opp-hz = /bits/ 64 < 1 >;
+ };
+
+ opp-1 {
+ opp-hz = /bits/ 64 < 2 >;
+ };
+ };
+
+ cpu4_cpu_ddr_qoslat: qcom,cpu4-cpu-ddr-qoslat {
+ compatible = "qcom,devfreq-qoslat";
+ governor = "powersave";
+ operating-points-v2 = <&qoslat_opp_table>;
+ mboxes = <&qmp_aop 0>;
+ };
+
+ cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,target-dev = <&cpu0_l3>;
+ qcom,cachemiss-ev = <0x17>;
+ qcom,core-dev-table =
+ < 300000 300000000 >,
+ < 403200 403200000 >,
+ < 518400 518400000 >,
+ < 633600 614400000 >,
+ < 825600 729600000 >,
+ < 921600 825600000 >,
+ < 1036800 921600000 >,
+ < 1132800 1036800000 >,
+ < 1228800 1132800000 >,
+ < 1401600 1228800000 >,
+ < 1497600 1305600000 >,
+ < 1670400 1382400000 >;
+ };
+
+ cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,target-dev = <&cpu0_cpu_llcc_lat>;
+ qcom,cachemiss-ev = <0x2A>;
+ qcom,core-dev-table =
+ < 300000 MHZ_TO_MBPS( 150, 16) >,
+ < 729600 MHZ_TO_MBPS( 300, 16) >,
+ < 1497600 MHZ_TO_MBPS( 466, 16) >,
+ < 1670400 MHZ_TO_MBPS( 600, 16) >;
+ };
+
+ cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,target-dev = <&cpu0_llcc_ddr_lat>;
+ qcom,cachemiss-ev = <0x2A>;
+ ddr4-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
+ qcom,core-dev-table =
+ < 300000 MHZ_TO_MBPS( 200, 4) >,
+ < 729600 MHZ_TO_MBPS( 451, 4) >,
+ < 1132800 MHZ_TO_MBPS( 547, 4) >,
+ < 1497600 MHZ_TO_MBPS( 768, 4) >,
+ < 1670400 MHZ_TO_MBPS( 1017, 4) >;
+ };
+
+ ddr5-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR5>;
+ qcom,core-dev-table =
+ < 300000 MHZ_TO_MBPS( 200, 4) >,
+ < 729600 MHZ_TO_MBPS( 451, 4) >,
+ < 1132800 MHZ_TO_MBPS( 547, 4) >,
+ < 1497600 MHZ_TO_MBPS( 768, 4) >,
+ < 1670400 MHZ_TO_MBPS( 1017, 4) >;
+ };
+ };
+
+ };
+
+ cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+
+ cpu4_cpu_l3_latmon: qcom,cpu4-cpu-l3-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
+ qcom,target-dev = <&cpu4_l3>;
+ qcom,cachemiss-ev = <0x17>;
+ qcom,core-dev-table =
+ < 300000 300000000 >,
+ < 806400 614400000 >,
+ < 1017600 729600000 >,
+ < 1228800 921600000 >,
+ < 1689600 1228800000 >,
+ < 1804800 1305600000 >,
+ < 2227200 1382400000 >;
+ };
+
+ cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU7>;
+ qcom,target-dev = <&cpu7_l3>;
+ qcom,cachemiss-ev = <0x17>;
+ qcom,core-dev-table =
+ < 300000 300000000 >,
+ < 806400 614400000 >,
+ < 1017600 729600000 >,
+ < 1228800 921600000 >,
+ < 1689600 1228800000 >,
+ < 1804800 1305600000 >,
+ < 2227200 1382400000 >;
+ };
+
+ cpu4_cpu_llcc_latmon: qcom,cpu4-cpu-llcc-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,target-dev = <&cpu4_cpu_llcc_lat>;
+ qcom,cachemiss-ev = <0x2A>;
+ qcom,core-dev-table =
+ < 300000 MHZ_TO_MBPS( 150, 16) >,
+ < 691200 MHZ_TO_MBPS( 300, 16) >,
+ < 1017600 MHZ_TO_MBPS( 466, 16) >,
+ < 1228800 MHZ_TO_MBPS( 600, 16) >,
+ < 1804800 MHZ_TO_MBPS( 806, 16) >,
+ < 2227200 MHZ_TO_MBPS( 933, 16) >,
+ < 2476800 MHZ_TO_MBPS( 1000, 16) >;
+ };
+
+ cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+ qcom,target-dev = <&cpu4_llcc_ddr_lat>;
+ qcom,cachemiss-ev = <0x2A>;
+ ddr4-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
+ qcom,core-dev-table =
+ < 300000 MHZ_TO_MBPS( 200, 4) >,
+ < 691200 MHZ_TO_MBPS( 451, 4) >,
+ < 806400 MHZ_TO_MBPS( 547, 4) >,
+ < 1017600 MHZ_TO_MBPS( 768, 4) >,
+ < 1228800 MHZ_TO_MBPS(1017, 4) >,
+ < 1574400 MHZ_TO_MBPS(1353, 4) >,
+ < 1804800 MHZ_TO_MBPS(1555, 4) >,
+ < 2227200 MHZ_TO_MBPS(1804, 4) >,
+ < 2380800 MHZ_TO_MBPS(2092, 4) >;
+ };
+
+ ddr5-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR5>;
+ qcom,core-dev-table =
+ < 300000 MHZ_TO_MBPS( 200, 4) >,
+ < 691200 MHZ_TO_MBPS( 451, 4) >,
+ < 806400 MHZ_TO_MBPS( 547, 4) >,
+ < 1017600 MHZ_TO_MBPS( 768, 4) >,
+ < 1228800 MHZ_TO_MBPS(1017, 4) >,
+ < 1804800 MHZ_TO_MBPS(1555, 4) >,
+ < 2227200 MHZ_TO_MBPS(1804, 4) >,
+ < 2380800 MHZ_TO_MBPS(2092, 4) >,
+ < 2476800 MHZ_TO_MBPS(2736, 4) >;
+ };
+ };
+
+ cpu4_computemon: qcom,cpu4-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
+ ddr4-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
+ qcom,core-dev-table =
+ < 1804800 MHZ_TO_MBPS( 200, 4) >,
+ < 2380800 MHZ_TO_MBPS(1017, 4) >,
+ < 2500000 MHZ_TO_MBPS(2092, 4) >;
+ };
+
+ ddr5-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR5>;
+ qcom,core-dev-table =
+ < 1804800 MHZ_TO_MBPS( 200, 4) >,
+ < 2380800 MHZ_TO_MBPS(1017, 4) >,
+ < 2500000 MHZ_TO_MBPS(2736, 4) >;
+ };
+ };
+
+ cpu4_qoslatmon: qcom,cpu4-qoslatmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,target-dev = <&cpu4_cpu_ddr_qoslat>;
+ qcom,cachemiss-ev = <0x2A>;
+ qcom,core-dev-table =
+ < 300000 1 >,
+ < 3000000 2 >;
+ };
+ };
+
+ keepalive_opp_table: keepalive-opp-table {
+ compatible = "operating-points-v2";
+ opp-1 {
+ opp-hz = /bits/ 64 < 1 >;
+ };
+ };
+
+ snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive {
+ compatible = "qcom,devbw";
+ governor = "powersave";
+ qcom,src-dst-ports = <1 627>;
+ qcom,active-only;
+ status = "ok";
+ operating-points-v2 = <&keepalive_opp_table>;
+ };
+
+ qcom,msm-imem@146bf000 {
+ compatible = "qcom,msm-imem";
+ reg = <0x146bf000 0x1000>;
+ ranges = <0x0 0x146bf000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mem_dump_table@10 {
+ compatible = "qcom,msm-imem-mem_dump_table";
+ reg = <0x10 0x8>;
+ };
+
+ restart_reason@65c {
+ compatible = "qcom,msm-imem-restart_reason";
+ reg = <0x65c 0x4>;
+ };
+
+ dload_type@1c {
+ compatible = "qcom,msm-imem-dload-type";
+ reg = <0x1c 0x4>;
+ };
+
+ boot_stats@6b0 {
+ compatible = "qcom,msm-imem-boot_stats";
+ reg = <0x6b0 0x20>;
+ };
+
+ kaslr_offset@6d0 {
+ compatible = "qcom,msm-imem-kaslr_offset";
+ reg = <0x6d0 0xc>;
+ };
+
+ pil@94c {
+ compatible = "qcom,msm-imem-pil";
+ reg = <0x94c 0xc8>;
+ };
+
+ diag_dload@c8 {
+ compatible = "qcom,msm-imem-diag-dload";
+ reg = <0xc8 0xc8>;
+ };
+ };
+
+ restart@c264000 {
+ compatible = "qcom,pshold";
+ reg = <0xc264000 0x4>,
+ <0x1fd3000 0x4>;
+ reg-names = "pshold-base", "tcsr-boot-misc-detect";
+ };
+
+ dcc: dcc_v2@1023000 {
+ compatible = "qcom,dcc-v2";
+ reg = <0x1023000 0x1000>,
+ <0x103a000 0x6000>;
+ reg-names = "dcc-base", "dcc-ram-base";
+
+ dcc-ram-offset = <0x1a000>;
+
+ link_list1 {
+ qcom,curr-link-list = <3>;
+ qcom,data-sink = "sram";
+ qcom,link-list = <DCC_READ 0x18220d14 3 0>,
+ <DCC_READ 0x18220d30 4 0>,
+ <DCC_READ 0x18220d44 4 0>,
+ <DCC_READ 0x18220d58 4 0>,
+ <DCC_READ 0x18220fb4 3 0>,
+ <DCC_READ 0x18220fd0 4 0>,
+ <DCC_READ 0x18220fe4 4 0>,
+ <DCC_READ 0x18220ff8 4 0>,
+ <DCC_READ 0x18220d04 1 0>,
+ <DCC_READ 0x18220d00 1 0>,
+ <DCC_READ 0x18000024 1 0>,
+ <DCC_READ 0x18000040 4 0>,
+ <DCC_READ 0x18010024 1 0>,
+ <DCC_READ 0x18010040 4 0>,
+ <DCC_READ 0x18020024 1 0>,
+ <DCC_READ 0x18020040 4 0>,
+ <DCC_READ 0x18030024 1 0>,
+ <DCC_READ 0x18030040 4 0>,
+ <DCC_READ 0x18040024 1 0>,
+ <DCC_READ 0x18040040 4 0>,
+ <DCC_READ 0x18050024 1 0>,
+ <DCC_READ 0x18050040 4 0>,
+ <DCC_READ 0x18060024 1 0>,
+ <DCC_READ 0x18060040 4 0>,
+ <DCC_READ 0x18070024 1 0>,
+ <DCC_READ 0x18070040 4 0>,
+ <DCC_READ 0x18080104 1 0>,
+ <DCC_READ 0x18080168 1 0>,
+ <DCC_READ 0x18080198 1 0>,
+ <DCC_READ 0x18080128 1 0>,
+ <DCC_READ 0x18080024 1 0>,
+ <DCC_READ 0x18080040 3 0>,
+ <DCC_READ 0x18200400 3 0>,
+ <DCC_READ 0x0b201020 2 0>,
+ <DCC_READ 0x0b204520 1 0>,
+ <DCC_READ 0x1800005c 1 0>,
+ <DCC_READ 0x1801005c 1 0>,
+ <DCC_READ 0x1802005c 1 0>,
+ <DCC_READ 0x1803005c 1 0>,
+ <DCC_READ 0x1804005c 1 0>,
+ <DCC_READ 0x1805005c 1 0>,
+ <DCC_READ 0x1806005c 1 0>,
+ <DCC_READ 0x1807005c 1 0>,
+ <DCC_READ 0x18101908 1 0>,
+ <DCC_READ 0x18101c18 1 0>,
+ <DCC_READ 0x18390810 1 0>,
+ <DCC_READ 0x18390c50 1 0>,
+ <DCC_READ 0x18390814 1 0>,
+ <DCC_READ 0x18390c54 1 0>,
+ <DCC_READ 0x18390818 1 0>,
+ <DCC_READ 0x18390c58 1 0>,
+ <DCC_READ 0x18393a84 2 0>,
+ <DCC_READ 0x18100908 1 0>,
+ <DCC_READ 0x18100c18 1 0>,
+ <DCC_READ 0x183a0810 1 0>,
+ <DCC_READ 0x183a0c50 1 0>,
+ <DCC_READ 0x183a0814 1 0>,
+ <DCC_READ 0x183a0c54 1 0>,
+ <DCC_READ 0x183a0818 1 0>,
+ <DCC_READ 0x183a0c58 1 0>,
+ <DCC_READ 0x183a3a84 2 0>,
+ <DCC_READ 0x18393500 1 0>,
+ <DCC_READ 0x18393580 1 0>,
+ <DCC_READ 0x183a3500 1 0>,
+ <DCC_READ 0x183a3580 1 0>,
+ <DCC_READ 0x18282000 4 0>,
+ <DCC_READ 0x18282028 1 0>,
+ <DCC_READ 0x18282038 1 0>,
+ <DCC_READ 0x18282080 5 0>,
+ <DCC_READ 0x18286000 4 0>,
+ <DCC_READ 0x18286028 1 0>,
+ <DCC_READ 0x18286038 1 0>,
+ <DCC_READ 0x18286080 5 0>,
+ <DCC_READ 0x0c201244 1 0>,
+ <DCC_READ 0x0c202244 1 0>,
+ <DCC_READ 0x18300000 1 0>,
+ <DCC_READ 0x1829208c 1 0>,
+ <DCC_READ 0x18292098 1 0>,
+ <DCC_READ 0x18292098 1 0>,
+ <DCC_READ 0x1829608c 1 0>,
+ <DCC_READ 0x18296098 1 0>,
+ <DCC_READ 0x18296098 1 0>,
+ <DCC_READ 0x091a9020 1 0>,
+ <DCC_READ_WRITE 0x5 0x1 0>,
+ <DCC_READ 0x09102008 1 0>,
+ <DCC_READ_WRITE 0x2 0x2 0>,
+ <DCC_READ 0x09142008 1 0>,
+ <DCC_READ_WRITE 0x2 0x2 0>,
+ <DCC_READ 0x09102408 1 0>,
+ <DCC_READ_WRITE 0x2 0x2 0>,
+ <DCC_READ 0x09142408 1 0>,
+ <DCC_READ_WRITE 0x2 0x2 0>,
+ <DCC_READ 0x09103808 1 0>,
+ <DCC_LOOP 3 0 0>,
+ <DCC_READ 0x09103810 1 0>,
+ <DCC_READ 0x09103814 1 0>,
+ <DCC_LOOP 1 0 0>,
+ <DCC_READ 0x09103888 1 0>,
+ <DCC_LOOP 2 0 0>,
+ <DCC_READ 0x09103890 1 0>,
+ <DCC_READ 0x09103894 1 0>,
+ <DCC_LOOP 1 0 0>,
+ <DCC_READ 0x09143808 1 0>,
+ <DCC_LOOP 3 0 0>,
+ <DCC_READ 0x09143810 1 0>,
+ <DCC_READ 0x09143814 1 0>,
+ <DCC_LOOP 1 0 0>,
+ <DCC_READ 0x09143888 1 0>,
+ <DCC_LOOP 2 0 0>,
+ <DCC_READ 0x09143890 1 0>,
+ <DCC_READ 0x09143894 1 0>,
+ <DCC_LOOP 1 0 0>,
+ <DCC_READ 0x09182808 1 0>,
+ <DCC_LOOP 2 0 0>,
+ <DCC_READ 0x09182810 1 0>,
+ <DCC_READ 0x09182814 1 0>,
+ <DCC_LOOP 1 0 0>,
+ <DCC_READ 0x09182888 1 0>,
+ <DCC_LOOP 3 0 0>,
+ <DCC_READ 0x09182890 1 0>,
+ <DCC_READ 0x09182894 1 0>,
+ <DCC_LOOP 1 0 0>,
+ <DCC_READ 0x09103008 1 0>,
+ <DCC_READ 0x0910300c 1 0>,
+ <DCC_WRITE 0x09103028 0x00000001 1>,
+ <DCC_LOOP 41 0 0>,
+ <DCC_READ 0x09103010 1 0>,
+ <DCC_READ 0x09103014 1 0>,
+ <DCC_LOOP 1 0 0>,
+ <DCC_READ 0x09103408 1 0>,
+ <DCC_READ 0x0910340c 1 0>,
+ <DCC_WRITE 0x09103428 0x00000001 1>,
+ <DCC_LOOP 41 0 0>,
+ <DCC_READ 0x09103410 1 0>,
+ <DCC_READ 0x09103414 1 0>,
+ <DCC_LOOP 1 0 0>,
+ <DCC_READ 0x09143008 1 0>,
+ <DCC_READ 0x0914300c 1 0>,
+ <DCC_WRITE 0x09143028 0x00000001 1>,
+ <DCC_LOOP 41 0 0>,
+ <DCC_READ 0x09143010 1 0>,
+ <DCC_READ 0x09143014 1 0>,
+ <DCC_LOOP 1 0 0>,
+ <DCC_READ 0x09143408 1 0>,
+ <DCC_READ 0x0914340c 1 0>,
+ <DCC_WRITE 0x09143428 0x00000001 1>,
+ <DCC_LOOP 41 0 0>,
+ <DCC_READ 0x09143410 1 0>,
+ <DCC_READ 0x09143414 1 0>,
+ <DCC_LOOP 1 0 0>,
+ <DCC_READ 0x09182008 1 0>,
+ <DCC_READ 0x0918200c 1 0>,
+ <DCC_WRITE 0x09182028 0x00000001 1>,
+ <DCC_LOOP 11 0 0>,
+ <DCC_READ 0x09182010 1 0>,
+ <DCC_READ 0x09182014 1 0>,
+ <DCC_LOOP 1 0 0>,
+ <DCC_READ 0x09182408 1 0>,
+ <DCC_READ 0x0918240c 1 0>,
+ <DCC_WRITE 0x09182428 0x00000001 1>,
+ <DCC_LOOP 11 0 0>,
+ <DCC_READ 0x09182410 1 0>,
+ <DCC_READ 0x09182414 1 0>,
+ <DCC_LOOP 1 0 0>;
+ };
+
+ link_list2 {
+ qcom,curr-link-list = <6>;
+ qcom,data-sink = "sram";
+ qcom,link-list = <DCC_READ 0x9050078 1 0>,
+ <DCC_READ 0x9050110 8 0>,
+ <DCC_READ 0x9080058 2 0>,
+ <DCC_READ 0x90800c8 1 0>,
+ <DCC_READ 0x90800d4 1 0>,
+ <DCC_READ 0x90800e0 1 0>,
+ <DCC_READ 0x90800ec 1 0>,
+ <DCC_READ 0x90800f8 1 0>,
+ <DCC_READ 0x908401c 1 0>,
+ <DCC_READ 0x908403c 1 0>,
+ <DCC_READ 0x908404c 2 0>,
+ <DCC_READ 0x90840d4 1 0>,
+ <DCC_READ 0x9084204 1 0>,
+ <DCC_READ 0x908420c 1 0>,
+ <DCC_READ 0x9084250 2 0>,
+ <DCC_READ 0x9084260 3 0>,
+ <DCC_READ 0x9084280 1 0>,
+ <DCC_READ 0x90ba280 1 0>,
+ <DCC_READ 0x90ba288 7 0>,
+ <DCC_READ 0x9258610 4 0>,
+ <DCC_READ 0x92d8610 4 0>,
+ <DCC_READ 0x9358610 4 0>,
+ <DCC_READ 0x93d8610 4 0>,
+ <DCC_READ 0x9220344 8 0>,
+ <DCC_READ 0x9220370 6 0>,
+ <DCC_READ 0x9220480 1 0>,
+ <DCC_READ 0x9222400 1 0>,
+ <DCC_READ 0x922240c 1 0>,
+ <DCC_READ 0x9223214 2 0>,
+ <DCC_READ 0x9223220 3 0>,
+ <DCC_READ 0x9223308 1 0>,
+ <DCC_READ 0x9223318 1 0>,
+ <DCC_READ 0x9232100 1 0>,
+ <DCC_READ 0x9236040 6 0>,
+ <DCC_READ 0x92360b0 1 0>,
+ <DCC_READ 0x923e030 2 0>,
+ <DCC_READ 0x9241000 1 0>,
+ <DCC_READ 0x9242028 1 0>,
+ <DCC_READ 0x9242044 3 0>,
+ <DCC_READ 0x9242070 1 0>,
+ <DCC_READ 0x9248030 1 0>,
+ <DCC_READ 0x9248048 8 0>,
+ <DCC_READ 0x92a0344 8 0>,
+ <DCC_READ 0x92a0370 6 0>,
+ <DCC_READ 0x92a0480 1 0>,
+ <DCC_READ 0x92a2400 1 0>,
+ <DCC_READ 0x92a240c 1 0>,
+ <DCC_READ 0x92a3214 2 0>,
+ <DCC_READ 0x92a3220 3 0>,
+ <DCC_READ 0x92a3308 1 0>,
+ <DCC_READ 0x92a3318 1 0>,
+ <DCC_READ 0x92b2100 1 0>,
+ <DCC_READ 0x92b6040 6 0>,
+ <DCC_READ 0x92b60b0 1 0>,
+ <DCC_READ 0x92be030 2 0>,
+ <DCC_READ 0x92c1000 1 0>,
+ <DCC_READ 0x92c2028 1 0>,
+ <DCC_READ 0x92c2044 3 0>,
+ <DCC_READ 0x92c2070 1 0>,
+ <DCC_READ 0x92c8030 1 0>,
+ <DCC_READ 0x92c8048 8 0>,
+ <DCC_READ 0x9320344 8 0>,
+ <DCC_READ 0x9320370 6 0>,
+ <DCC_READ 0x9320480 1 0>,
+ <DCC_READ 0x9322400 1 0>,
+ <DCC_READ 0x932240c 1 0>,
+ <DCC_READ 0x9323214 2 0>,
+ <DCC_READ 0x9323220 3 0>,
+ <DCC_READ 0x9323308 1 0>,
+ <DCC_READ 0x9323318 1 0>,
+ <DCC_READ 0x9332100 1 0>,
+ <DCC_READ 0x9336040 6 0>,
+ <DCC_READ 0x93360b0 1 0>,
+ <DCC_READ 0x933e030 2 0>,
+ <DCC_READ 0x9341000 1 0>,
+ <DCC_READ 0x9342028 1 0>,
+ <DCC_READ 0x9342044 3 0>,
+ <DCC_READ 0x9342070 1 0>,
+ <DCC_READ 0x9348030 1 0>,
+ <DCC_READ 0x9348048 8 0>,
+ <DCC_READ 0x93a0344 8 0>,
+ <DCC_READ 0x93a0370 6 0>,
+ <DCC_READ 0x93a0480 1 0>,
+ <DCC_READ 0x93a2400 1 0>,
+ <DCC_READ 0x93a240c 1 0>,
+ <DCC_READ 0x93a3214 2 0>,
+ <DCC_READ 0x93a3220 3 0>,
+ <DCC_READ 0x93a3308 1 0>,
+ <DCC_READ 0x93a3318 1 0>,
+ <DCC_READ 0x93b2100 1 0>,
+ <DCC_READ 0x93b6040 6 0>,
+ <DCC_READ 0x93b60b0 1 0>,
+ <DCC_READ 0x93be030 2 0>,
+ <DCC_READ 0x93c1000 1 0>,
+ <DCC_READ 0x93c2028 1 0>,
+ <DCC_READ 0x93c2044 3 0>,
+ <DCC_READ 0x93c2070 1 0>,
+ <DCC_READ 0x93c8030 1 0>,
+ <DCC_READ 0x93c8048 8 0>,
+ <DCC_READ 0x9270080 1 0>,
+ <DCC_READ 0x9270400 1 0>,
+ <DCC_READ 0x9270410 6 0>,
+ <DCC_READ 0x9270430 1 0>,
+ <DCC_READ 0x9270440 1 0>,
+ <DCC_READ 0x9270448 1 0>,
+ <DCC_READ 0x92704a0 1 0>,
+ <DCC_READ 0x92704b0 1 0>,
+ <DCC_READ 0x92704b8 2 0>,
+ <DCC_READ 0x92704d0 1 0>,
+ <DCC_READ 0x9271400 1 0>,
+ <DCC_READ 0x92753b0 1 0>,
+ <DCC_READ 0x9275c1c 1 0>,
+ <DCC_READ 0x9275c2c 1 0>,
+ <DCC_READ 0x9275c38 1 0>,
+ <DCC_READ 0x9276418 2 0>,
+ <DCC_READ 0x92f0080 1 0>,
+ <DCC_READ 0x92f0400 1 0>,
+ <DCC_READ 0x92f0410 6 0>,
+ <DCC_READ 0x92f0430 1 0>,
+ <DCC_READ 0x92f0440 1 0>,
+ <DCC_READ 0x92f0448 1 0>,
+ <DCC_READ 0x92f04a0 1 0>,
+ <DCC_READ 0x92f04b0 1 0>,
+ <DCC_READ 0x92f04b8 2 0>,
+ <DCC_READ 0x92f04d0 1 0>,
+ <DCC_READ 0x92f1400 1 0>,
+ <DCC_READ 0x92f53b0 1 0>,
+ <DCC_READ 0x92f5c1c 1 0>,
+ <DCC_READ 0x92f5c2c 1 0>,
+ <DCC_READ 0x92f5c38 1 0>,
+ <DCC_READ 0x92f6418 2 0>,
+ <DCC_READ 0x9370080 1 0>,
+ <DCC_READ 0x9370400 1 0>,
+ <DCC_READ 0x9370410 6 0>,
+ <DCC_READ 0x9370430 1 0>,
+ <DCC_READ 0x9370440 1 0>,
+ <DCC_READ 0x9370448 1 0>,
+ <DCC_READ 0x93704a0 1 0>,
+ <DCC_READ 0x93704b0 1 0>,
+ <DCC_READ 0x93704b8 2 0>,
+ <DCC_READ 0x93704d0 1 0>,
+ <DCC_READ 0x9371400 1 0>,
+ <DCC_READ 0x93753b0 1 0>,
+ <DCC_READ 0x9375c1c 1 0>,
+ <DCC_READ 0x9375c2c 1 0>,
+ <DCC_READ 0x9375c38 1 0>,
+ <DCC_READ 0x9376418 2 0>,
+ <DCC_READ 0x93f0080 1 0>,
+ <DCC_READ 0x93f0400 1 0>,
+ <DCC_READ 0x93f0410 6 0>,
+ <DCC_READ 0x93f0430 1 0>,
+ <DCC_READ 0x93f0440 1 0>,
+ <DCC_READ 0x93f0448 1 0>,
+ <DCC_READ 0x93f04a0 1 0>,
+ <DCC_READ 0x93f04b0 1 0>,
+ <DCC_READ 0x93f04b8 2 0>,
+ <DCC_READ 0x93f04d0 1 0>,
+ <DCC_READ 0x93f1400 1 0>,
+ <DCC_READ 0x93f53b0 1 0>,
+ <DCC_READ 0x93f5c1c 1 0>,
+ <DCC_READ 0x93f5c2c 1 0>,
+ <DCC_READ 0x93f5c38 1 0>,
+ <DCC_READ 0x93f6418 2 0>,
+ <DCC_READ 0x9260080 1 0>,
+ <DCC_READ 0x9260400 1 0>,
+ <DCC_READ 0x9260410 3 0>,
+ <DCC_READ 0x9260420 2 0>,
+ <DCC_READ 0x9260430 1 0>,
+ <DCC_READ 0x9260440 1 0>,
+ <DCC_READ 0x9260448 1 0>,
+ <DCC_READ 0x92604a0 1 0>,
+ <DCC_READ 0x92604b0 1 0>,
+ <DCC_READ 0x92604b8 2 0>,
+ <DCC_READ 0x92604d0 2 0>,
+ <DCC_READ 0x9261400 1 0>,
+ <DCC_READ 0x9263410 1 0>,
+ <DCC_READ 0x92653b0 1 0>,
+ <DCC_READ 0x9265804 1 0>,
+ <DCC_READ 0x9265b1c 1 0>,
+ <DCC_READ 0x9265b2c 1 0>,
+ <DCC_READ 0x9265b38 1 0>,
+ <DCC_READ 0x9269100 1 0>,
+ <DCC_READ 0x9269110 1 0>,
+ <DCC_READ 0x9269120 1 0>,
+ <DCC_READ 0x92e0080 1 0>,
+ <DCC_READ 0x92e0400 1 0>,
+ <DCC_READ 0x92e0410 3 0>,
+ <DCC_READ 0x92e0420 2 0>,
+ <DCC_READ 0x92e0430 1 0>,
+ <DCC_READ 0x92e0440 1 0>,
+ <DCC_READ 0x92e0448 1 0>,
+ <DCC_READ 0x92e04a0 1 0>,
+ <DCC_READ 0x92e04b0 1 0>,
+ <DCC_READ 0x92e04b8 2 0>,
+ <DCC_READ 0x92e04d0 2 0>,
+ <DCC_READ 0x92e1400 1 0>,
+ <DCC_READ 0x92e3410 1 0>,
+ <DCC_READ 0x92e53b0 1 0>,
+ <DCC_READ 0x92e5804 1 0>,
+ <DCC_READ 0x92e5b1c 1 0>,
+ <DCC_READ 0x92e5b2c 1 0>,
+ <DCC_READ 0x92e5b38 1 0>,
+ <DCC_READ 0x92e9100 1 0>,
+ <DCC_READ 0x92e9110 1 0>,
+ <DCC_READ 0x92e9120 1 0>,
+ <DCC_READ 0x9360080 1 0>,
+ <DCC_READ 0x9360400 1 0>,
+ <DCC_READ 0x9360410 3 0>,
+ <DCC_READ 0x9360420 2 0>,
+ <DCC_READ 0x9360430 1 0>,
+ <DCC_READ 0x9360440 1 0>,
+ <DCC_READ 0x9360448 1 0>,
+ <DCC_READ 0x93604a0 1 0>,
+ <DCC_READ 0x93604b0 1 0>,
+ <DCC_READ 0x93604b8 2 0>,
+ <DCC_READ 0x93604d0 2 0>,
+ <DCC_READ 0x9361400 1 0>,
+ <DCC_READ 0x9363410 1 0>,
+ <DCC_READ 0x93653b0 1 0>,
+ <DCC_READ 0x9365804 1 0>,
+ <DCC_READ 0x9365b1c 1 0>,
+ <DCC_READ 0x9365b2c 1 0>,
+ <DCC_READ 0x9365b38 1 0>,
+ <DCC_READ 0x9369100 1 0>,
+ <DCC_READ 0x9369110 1 0>,
+ <DCC_READ 0x9369120 1 0>,
+ <DCC_READ 0x93e0080 1 0>,
+ <DCC_READ 0x93e0400 1 0>,
+ <DCC_READ 0x93e0410 3 0>,
+ <DCC_READ 0x93e0420 2 0>,
+ <DCC_READ 0x93e0430 1 0>,
+ <DCC_READ 0x93e0440 1 0>,
+ <DCC_READ 0x93e0448 1 0>,
+ <DCC_READ 0x93e04a0 1 0>,
+ <DCC_READ 0x93e04b0 1 0>,
+ <DCC_READ 0x93e04b8 2 0>,
+ <DCC_READ 0x93e04d0 2 0>,
+ <DCC_READ 0x93e1400 1 0>,
+ <DCC_READ 0x93e3410 1 0>,
+ <DCC_READ 0x93e53b0 1 0>,
+ <DCC_READ 0x93e5804 1 0>,
+ <DCC_READ 0x93e5b1c 1 0>,
+ <DCC_READ 0x93e5b2c 1 0>,
+ <DCC_READ 0x93e5b38 1 0>,
+ <DCC_READ 0x93e9100 1 0>,
+ <DCC_READ 0x93e9110 1 0>,
+ <DCC_READ 0x93e9120 1 0>,
+ <DCC_READ 0x96b0868 1 0>,
+ <DCC_READ 0x96b0870 1 0>,
+ <DCC_READ 0x96b1004 1 0>,
+ <DCC_READ 0x96b100c 1 0>,
+ <DCC_READ 0x96b1014 1 0>,
+ <DCC_READ 0x96b1204 1 0>,
+ <DCC_READ 0x96b120c 1 0>,
+ <DCC_READ 0x96b1214 1 0>,
+ <DCC_READ 0x96b1504 1 0>,
+ <DCC_READ 0x96b150c 1 0>,
+ <DCC_READ 0x96b1514 1 0>,
+ <DCC_READ 0x96b1604 1 0>,
+ <DCC_READ 0x96b8100 1 0>,
+ <DCC_READ 0x96b813c 1 0>,
+ <DCC_READ 0x96b8500 1 0>,
+ <DCC_READ 0x96b853c 1 0>,
+ <DCC_READ 0x96b8a04 1 0>,
+ <DCC_READ 0x96b8a18 1 0>,
+ <DCC_READ 0x96b8ea8 1 0>,
+ <DCC_READ 0x96b9044 1 0>,
+ <DCC_READ 0x96b904c 1 0>,
+ <DCC_READ 0x96b9054 1 0>,
+ <DCC_READ 0x96b905c 1 0>,
+ <DCC_READ 0x96b910c 2 0>,
+ <DCC_READ 0x96b9204 1 0>,
+ <DCC_READ 0x96b920c 1 0>,
+ <DCC_READ 0x96b9238 1 0>,
+ <DCC_READ 0x96b9240 1 0>,
+ <DCC_READ 0x96b926c 1 0>,
+ <DCC_READ 0x96b9394 1 0>,
+ <DCC_READ 0x96b939c 1 0>,
+ <DCC_READ 0x96b9704 1 0>,
+ <DCC_READ 0x96b970c 1 0>,
+ <DCC_READ 0x96f0868 1 0>,
+ <DCC_READ 0x96f0870 1 0>,
+ <DCC_READ 0x96f1004 1 0>,
+ <DCC_READ 0x96f100c 1 0>,
+ <DCC_READ 0x96f1014 1 0>,
+ <DCC_READ 0x96f1204 1 0>,
+ <DCC_READ 0x96f120c 1 0>,
+ <DCC_READ 0x96f1214 1 0>,
+ <DCC_READ 0x96f1504 1 0>,
+ <DCC_READ 0x96f150c 1 0>,
+ <DCC_READ 0x96f1514 1 0>,
+ <DCC_READ 0x96f1604 1 0>,
+ <DCC_READ 0x96f8100 1 0>,
+ <DCC_READ 0x96f813c 1 0>,
+ <DCC_READ 0x96f8500 1 0>,
+ <DCC_READ 0x96f853c 1 0>,
+ <DCC_READ 0x96f8a04 1 0>,
+ <DCC_READ 0x96f8a18 1 0>,
+ <DCC_READ 0x96f8ea8 1 0>,
+ <DCC_READ 0x96f9044 1 0>,
+ <DCC_READ 0x96f904c 1 0>,
+ <DCC_READ 0x96f9054 1 0>,
+ <DCC_READ 0x96f905c 1 0>,
+ <DCC_READ 0x96f910c 2 0>,
+ <DCC_READ 0x96f9204 1 0>,
+ <DCC_READ 0x96f920c 1 0>,
+ <DCC_READ 0x96f9238 1 0>,
+ <DCC_READ 0x96f9240 1 0>,
+ <DCC_READ 0x96f926c 1 0>,
+ <DCC_READ 0x96f9394 1 0>,
+ <DCC_READ 0x96f939c 1 0>,
+ <DCC_READ 0x96f9704 1 0>,
+ <DCC_READ 0x96f970c 1 0>,
+ <DCC_READ 0x9730868 1 0>,
+ <DCC_READ 0x9730870 1 0>,
+ <DCC_READ 0x9731004 1 0>,
+ <DCC_READ 0x973100c 1 0>,
+ <DCC_READ 0x9731014 1 0>,
+ <DCC_READ 0x9731204 1 0>,
+ <DCC_READ 0x973120c 1 0>,
+ <DCC_READ 0x9731214 1 0>,
+ <DCC_READ 0x9731504 1 0>,
+ <DCC_READ 0x973150c 1 0>,
+ <DCC_READ 0x9731514 1 0>,
+ <DCC_READ 0x9731604 1 0>,
+ <DCC_READ 0x9738100 1 0>,
+ <DCC_READ 0x973813c 1 0>,
+ <DCC_READ 0x9738500 1 0>,
+ <DCC_READ 0x973853c 1 0>,
+ <DCC_READ 0x9738a04 1 0>,
+ <DCC_READ 0x9738a18 1 0>,
+ <DCC_READ 0x9738ea8 1 0>,
+ <DCC_READ 0x9739044 1 0>,
+ <DCC_READ 0x973904c 1 0>,
+ <DCC_READ 0x9739054 1 0>,
+ <DCC_READ 0x973905c 1 0>,
+ <DCC_READ 0x973910c 2 0>,
+ <DCC_READ 0x9739204 1 0>,
+ <DCC_READ 0x973920c 1 0>,
+ <DCC_READ 0x9739238 1 0>,
+ <DCC_READ 0x9739240 1 0>,
+ <DCC_READ 0x973926c 1 0>,
+ <DCC_READ 0x9739394 1 0>,
+ <DCC_READ 0x973939c 1 0>,
+ <DCC_READ 0x9739704 1 0>,
+ <DCC_READ 0x973970c 1 0>,
+ <DCC_READ 0x9770868 1 0>,
+ <DCC_READ 0x9770870 1 0>,
+ <DCC_READ 0x9771004 1 0>,
+ <DCC_READ 0x977100c 1 0>,
+ <DCC_READ 0x9771014 1 0>,
+ <DCC_READ 0x9771204 1 0>,
+ <DCC_READ 0x977120c 1 0>,
+ <DCC_READ 0x9771214 1 0>,
+ <DCC_READ 0x9771504 1 0>,
+ <DCC_READ 0x977150c 1 0>,
+ <DCC_READ 0x9771514 1 0>,
+ <DCC_READ 0x9771604 1 0>,
+ <DCC_READ 0x9778100 1 0>,
+ <DCC_READ 0x977813c 1 0>,
+ <DCC_READ 0x9778500 1 0>,
+ <DCC_READ 0x977853c 1 0>,
+ <DCC_READ 0x9778a04 1 0>,
+ <DCC_READ 0x9778a18 1 0>,
+ <DCC_READ 0x9778ea8 1 0>,
+ <DCC_READ 0x9779044 1 0>,
+ <DCC_READ 0x977904c 1 0>,
+ <DCC_READ 0x9779054 1 0>,
+ <DCC_READ 0x977905c 1 0>,
+ <DCC_READ 0x977910c 2 0>,
+ <DCC_READ 0x9779204 1 0>,
+ <DCC_READ 0x977920c 1 0>,
+ <DCC_READ 0x9779238 1 0>,
+ <DCC_READ 0x9779240 1 0>,
+ <DCC_READ 0x977926c 1 0>,
+ <DCC_READ 0x9779394 1 0>,
+ <DCC_READ 0x977939c 1 0>,
+ <DCC_READ 0x9779704 1 0>,
+ <DCC_READ 0x977970c 1 0>,
+ <DCC_READ 0x910d100 3 0>,
+ <DCC_READ 0x914d100 3 0>,
+ <DCC_READ 0x918d100 4 0>,
+ <DCC_READ 0x91a5100 1 0>,
+ <DCC_READ 0x91ad100 1 0>;
+ };
+
+ link_list3 {
+ qcom,curr-link-list = <7>;
+ qcom,data-sink = "sram";
+ qcom,link-list = <DCC_READ 0x9050078 1 0>,
+ <DCC_READ 0x9050110 8 0>,
+ <DCC_READ 0x9080058 2 0>,
+ <DCC_READ 0x90800c8 1 0>,
+ <DCC_READ 0x90800d4 1 0>,
+ <DCC_READ 0x90800e0 1 0>,
+ <DCC_READ 0x90800ec 1 0>,
+ <DCC_READ 0x90800f8 1 0>,
+ <DCC_READ 0x908401c 1 0>,
+ <DCC_READ 0x908403c 1 0>,
+ <DCC_READ 0x908404c 2 0>,
+ <DCC_READ 0x90840d4 1 0>,
+ <DCC_READ 0x9084204 1 0>,
+ <DCC_READ 0x908420c 1 0>,
+ <DCC_READ 0x9084250 2 0>,
+ <DCC_READ 0x9084260 3 0>,
+ <DCC_READ 0x9084280 1 0>,
+ <DCC_READ 0x90ba280 1 0>,
+ <DCC_READ 0x90ba288 7 0>,
+ <DCC_READ 0x9258610 4 0>,
+ <DCC_READ 0x92d8610 4 0>,
+ <DCC_READ 0x9358610 4 0>,
+ <DCC_READ 0x93d8610 4 0>,
+ <DCC_READ 0x9220344 8 0>,
+ <DCC_READ 0x9220370 6 0>,
+ <DCC_READ 0x9220480 1 0>,
+ <DCC_READ 0x9222400 1 0>,
+ <DCC_READ 0x922240c 1 0>,
+ <DCC_READ 0x9223214 2 0>,
+ <DCC_READ 0x9223220 3 0>,
+ <DCC_READ 0x9223308 1 0>,
+ <DCC_READ 0x9223318 1 0>,
+ <DCC_READ 0x9232100 1 0>,
+ <DCC_READ 0x9236040 6 0>,
+ <DCC_READ 0x92360b0 1 0>,
+ <DCC_READ 0x923e030 2 0>,
+ <DCC_READ 0x9241000 1 0>,
+ <DCC_READ 0x9242028 1 0>,
+ <DCC_READ 0x9242044 3 0>,
+ <DCC_READ 0x9242070 1 0>,
+ <DCC_READ 0x9248030 1 0>,
+ <DCC_READ 0x9248048 8 0>,
+ <DCC_READ 0x92a0344 8 0>,
+ <DCC_READ 0x92a0370 6 0>,
+ <DCC_READ 0x92a0480 1 0>,
+ <DCC_READ 0x92a2400 1 0>,
+ <DCC_READ 0x92a240c 1 0>,
+ <DCC_READ 0x92a3214 2 0>,
+ <DCC_READ 0x92a3220 3 0>,
+ <DCC_READ 0x92a3308 1 0>,
+ <DCC_READ 0x92a3318 1 0>,
+ <DCC_READ 0x92b2100 1 0>,
+ <DCC_READ 0x92b6040 6 0>,
+ <DCC_READ 0x92b60b0 1 0>,
+ <DCC_READ 0x92be030 2 0>,
+ <DCC_READ 0x92c1000 1 0>,
+ <DCC_READ 0x92c2028 1 0>,
+ <DCC_READ 0x92c2044 3 0>,
+ <DCC_READ 0x92c2070 1 0>,
+ <DCC_READ 0x92c8030 1 0>,
+ <DCC_READ 0x92c8048 8 0>,
+ <DCC_READ 0x9320344 8 0>,
+ <DCC_READ 0x9320370 6 0>,
+ <DCC_READ 0x9320480 1 0>,
+ <DCC_READ 0x9322400 1 0>,
+ <DCC_READ 0x932240c 1 0>,
+ <DCC_READ 0x9323214 2 0>,
+ <DCC_READ 0x9323220 3 0>,
+ <DCC_READ 0x9323308 1 0>,
+ <DCC_READ 0x9323318 1 0>,
+ <DCC_READ 0x9332100 1 0>,
+ <DCC_READ 0x9336040 6 0>,
+ <DCC_READ 0x93360b0 1 0>,
+ <DCC_READ 0x933e030 2 0>,
+ <DCC_READ 0x9341000 1 0>,
+ <DCC_READ 0x9342028 1 0>,
+ <DCC_READ 0x9342044 3 0>,
+ <DCC_READ 0x9342070 1 0>,
+ <DCC_READ 0x9348030 1 0>,
+ <DCC_READ 0x9348048 8 0>,
+ <DCC_READ 0x93a0344 8 0>,
+ <DCC_READ 0x93a0370 6 0>,
+ <DCC_READ 0x93a0480 1 0>,
+ <DCC_READ 0x93a2400 1 0>,
+ <DCC_READ 0x93a240c 1 0>,
+ <DCC_READ 0x93a3214 2 0>,
+ <DCC_READ 0x93a3220 3 0>,
+ <DCC_READ 0x93a3308 1 0>,
+ <DCC_READ 0x93a3318 1 0>,
+ <DCC_READ 0x93b2100 1 0>,
+ <DCC_READ 0x93b6040 6 0>,
+ <DCC_READ 0x93b60b0 1 0>,
+ <DCC_READ 0x93be030 2 0>,
+ <DCC_READ 0x93c1000 1 0>,
+ <DCC_READ 0x93c2028 1 0>,
+ <DCC_READ 0x93c2044 3 0>,
+ <DCC_READ 0x93c2070 1 0>,
+ <DCC_READ 0x93c8030 1 0>,
+ <DCC_READ 0x93c8048 8 0>,
+ <DCC_READ 0x9270080 1 0>,
+ <DCC_READ 0x9270400 1 0>,
+ <DCC_READ 0x9270410 6 0>,
+ <DCC_READ 0x9270430 1 0>,
+ <DCC_READ 0x9270440 1 0>,
+ <DCC_READ 0x9270448 1 0>,
+ <DCC_READ 0x92704a0 1 0>,
+ <DCC_READ 0x92704b0 1 0>,
+ <DCC_READ 0x92704b8 2 0>,
+ <DCC_READ 0x92704d0 1 0>,
+ <DCC_READ 0x9271400 1 0>,
+ <DCC_READ 0x92753b0 1 0>,
+ <DCC_READ 0x9275c1c 1 0>,
+ <DCC_READ 0x9275c2c 1 0>,
+ <DCC_READ 0x9275c38 1 0>,
+ <DCC_READ 0x9276418 2 0>,
+ <DCC_READ 0x92f0080 1 0>,
+ <DCC_READ 0x92f0400 1 0>,
+ <DCC_READ 0x92f0410 6 0>,
+ <DCC_READ 0x92f0430 1 0>,
+ <DCC_READ 0x92f0440 1 0>,
+ <DCC_READ 0x92f0448 1 0>,
+ <DCC_READ 0x92f04a0 1 0>,
+ <DCC_READ 0x92f04b0 1 0>,
+ <DCC_READ 0x92f04b8 2 0>,
+ <DCC_READ 0x92f04d0 1 0>,
+ <DCC_READ 0x92f1400 1 0>,
+ <DCC_READ 0x92f53b0 1 0>,
+ <DCC_READ 0x92f5c1c 1 0>,
+ <DCC_READ 0x92f5c2c 1 0>,
+ <DCC_READ 0x92f5c38 1 0>,
+ <DCC_READ 0x92f6418 2 0>,
+ <DCC_READ 0x9370080 1 0>,
+ <DCC_READ 0x9370400 1 0>,
+ <DCC_READ 0x9370410 6 0>,
+ <DCC_READ 0x9370430 1 0>,
+ <DCC_READ 0x9370440 1 0>,
+ <DCC_READ 0x9370448 1 0>,
+ <DCC_READ 0x93704a0 1 0>,
+ <DCC_READ 0x93704b0 1 0>,
+ <DCC_READ 0x93704b8 2 0>,
+ <DCC_READ 0x93704d0 1 0>,
+ <DCC_READ 0x9371400 1 0>,
+ <DCC_READ 0x93753b0 1 0>,
+ <DCC_READ 0x9375c1c 1 0>,
+ <DCC_READ 0x9375c2c 1 0>,
+ <DCC_READ 0x9375c38 1 0>,
+ <DCC_READ 0x9376418 2 0>,
+ <DCC_READ 0x93f0080 1 0>,
+ <DCC_READ 0x93f0400 1 0>,
+ <DCC_READ 0x93f0410 6 0>,
+ <DCC_READ 0x93f0430 1 0>,
+ <DCC_READ 0x93f0440 1 0>,
+ <DCC_READ 0x93f0448 1 0>,
+ <DCC_READ 0x93f04a0 1 0>,
+ <DCC_READ 0x93f04b0 1 0>,
+ <DCC_READ 0x93f04b8 2 0>,
+ <DCC_READ 0x93f04d0 1 0>,
+ <DCC_READ 0x93f1400 1 0>,
+ <DCC_READ 0x93f53b0 1 0>,
+ <DCC_READ 0x93f5c1c 1 0>,
+ <DCC_READ 0x93f5c2c 1 0>,
+ <DCC_READ 0x93f5c38 1 0>,
+ <DCC_READ 0x93f6418 2 0>,
+ <DCC_READ 0x9260080 1 0>,
+ <DCC_READ 0x9260400 1 0>,
+ <DCC_READ 0x9260410 3 0>,
+ <DCC_READ 0x9260420 2 0>,
+ <DCC_READ 0x9260430 1 0>,
+ <DCC_READ 0x9260440 1 0>,
+ <DCC_READ 0x9260448 1 0>,
+ <DCC_READ 0x92604a0 1 0>,
+ <DCC_READ 0x92604b0 1 0>,
+ <DCC_READ 0x92604b8 2 0>,
+ <DCC_READ 0x92604d0 2 0>,
+ <DCC_READ 0x9261400 1 0>,
+ <DCC_READ 0x9263410 1 0>,
+ <DCC_READ 0x92653b0 1 0>,
+ <DCC_READ 0x9265804 1 0>,
+ <DCC_READ 0x9265b1c 1 0>,
+ <DCC_READ 0x9265b2c 1 0>,
+ <DCC_READ 0x9265b38 1 0>,
+ <DCC_READ 0x9269100 1 0>,
+ <DCC_READ 0x9269110 1 0>,
+ <DCC_READ 0x9269120 1 0>,
+ <DCC_READ 0x92e0080 1 0>,
+ <DCC_READ 0x92e0400 1 0>,
+ <DCC_READ 0x92e0410 3 0>,
+ <DCC_READ 0x92e0420 2 0>,
+ <DCC_READ 0x92e0430 1 0>,
+ <DCC_READ 0x92e0440 1 0>,
+ <DCC_READ 0x92e0448 1 0>,
+ <DCC_READ 0x92e04a0 1 0>,
+ <DCC_READ 0x92e04b0 1 0>,
+ <DCC_READ 0x92e04b8 2 0>,
+ <DCC_READ 0x92e04d0 2 0>,
+ <DCC_READ 0x92e1400 1 0>,
+ <DCC_READ 0x92e3410 1 0>,
+ <DCC_READ 0x92e53b0 1 0>,
+ <DCC_READ 0x92e5804 1 0>,
+ <DCC_READ 0x92e5b1c 1 0>,
+ <DCC_READ 0x92e5b2c 1 0>,
+ <DCC_READ 0x92e5b38 1 0>,
+ <DCC_READ 0x92e9100 1 0>,
+ <DCC_READ 0x92e9110 1 0>,
+ <DCC_READ 0x92e9120 1 0>,
+ <DCC_READ 0x9360080 1 0>,
+ <DCC_READ 0x9360400 1 0>,
+ <DCC_READ 0x9360410 3 0>,
+ <DCC_READ 0x9360420 2 0>,
+ <DCC_READ 0x9360430 1 0>,
+ <DCC_READ 0x9360440 1 0>,
+ <DCC_READ 0x9360448 1 0>,
+ <DCC_READ 0x93604a0 1 0>,
+ <DCC_READ 0x93604b0 1 0>,
+ <DCC_READ 0x93604b8 2 0>,
+ <DCC_READ 0x93604d0 2 0>,
+ <DCC_READ 0x9361400 1 0>,
+ <DCC_READ 0x9363410 1 0>,
+ <DCC_READ 0x93653b0 1 0>,
+ <DCC_READ 0x9365804 1 0>,
+ <DCC_READ 0x9365b1c 1 0>,
+ <DCC_READ 0x9365b2c 1 0>,
+ <DCC_READ 0x9365b38 1 0>,
+ <DCC_READ 0x9369100 1 0>,
+ <DCC_READ 0x9369110 1 0>,
+ <DCC_READ 0x9369120 1 0>,
+ <DCC_READ 0x93e0080 1 0>,
+ <DCC_READ 0x93e0400 1 0>,
+ <DCC_READ 0x93e0410 3 0>,
+ <DCC_READ 0x93e0420 2 0>,
+ <DCC_READ 0x93e0430 1 0>,
+ <DCC_READ 0x93e0440 1 0>,
+ <DCC_READ 0x93e0448 1 0>,
+ <DCC_READ 0x93e04a0 1 0>,
+ <DCC_READ 0x93e04b0 1 0>,
+ <DCC_READ 0x93e04b8 2 0>,
+ <DCC_READ 0x93e04d0 2 0>,
+ <DCC_READ 0x93e1400 1 0>,
+ <DCC_READ 0x93e3410 1 0>,
+ <DCC_READ 0x93e53b0 1 0>,
+ <DCC_READ 0x93e5804 1 0>,
+ <DCC_READ 0x93e5b1c 1 0>,
+ <DCC_READ 0x93e5b2c 1 0>,
+ <DCC_READ 0x93e5b38 1 0>,
+ <DCC_READ 0x93e9100 1 0>,
+ <DCC_READ 0x93e9110 1 0>,
+ <DCC_READ 0x93e9120 1 0>,
+ <DCC_READ 0x96b0868 1 0>,
+ <DCC_READ 0x96b0870 1 0>,
+ <DCC_READ 0x96b1004 1 0>,
+ <DCC_READ 0x96b100c 1 0>,
+ <DCC_READ 0x96b1014 1 0>,
+ <DCC_READ 0x96b1204 1 0>,
+ <DCC_READ 0x96b120c 1 0>,
+ <DCC_READ 0x96b1214 1 0>,
+ <DCC_READ 0x96b1504 1 0>,
+ <DCC_READ 0x96b150c 1 0>,
+ <DCC_READ 0x96b1514 1 0>,
+ <DCC_READ 0x96b1604 1 0>,
+ <DCC_READ 0x96b8100 1 0>,
+ <DCC_READ 0x96b813c 1 0>,
+ <DCC_READ 0x96b8500 1 0>,
+ <DCC_READ 0x96b853c 1 0>,
+ <DCC_READ 0x96b8a04 1 0>,
+ <DCC_READ 0x96b8a18 1 0>,
+ <DCC_READ 0x96b8ea8 1 0>,
+ <DCC_READ 0x96b9044 1 0>,
+ <DCC_READ 0x96b904c 1 0>,
+ <DCC_READ 0x96b9054 1 0>,
+ <DCC_READ 0x96b905c 1 0>,
+ <DCC_READ 0x96b910c 2 0>,
+ <DCC_READ 0x96b9204 1 0>,
+ <DCC_READ 0x96b920c 1 0>,
+ <DCC_READ 0x96b9238 1 0>,
+ <DCC_READ 0x96b9240 1 0>,
+ <DCC_READ 0x96b926c 1 0>,
+ <DCC_READ 0x96b9394 1 0>,
+ <DCC_READ 0x96b939c 1 0>,
+ <DCC_READ 0x96b9704 1 0>,
+ <DCC_READ 0x96b970c 1 0>,
+ <DCC_READ 0x96f0868 1 0>,
+ <DCC_READ 0x96f0870 1 0>,
+ <DCC_READ 0x96f1004 1 0>,
+ <DCC_READ 0x96f100c 1 0>,
+ <DCC_READ 0x96f1014 1 0>,
+ <DCC_READ 0x96f1204 1 0>,
+ <DCC_READ 0x96f120c 1 0>,
+ <DCC_READ 0x96f1214 1 0>,
+ <DCC_READ 0x96f1504 1 0>,
+ <DCC_READ 0x96f150c 1 0>,
+ <DCC_READ 0x96f1514 1 0>,
+ <DCC_READ 0x96f1604 1 0>,
+ <DCC_READ 0x96f8100 1 0>,
+ <DCC_READ 0x96f813c 1 0>,
+ <DCC_READ 0x96f8500 1 0>,
+ <DCC_READ 0x96f853c 1 0>,
+ <DCC_READ 0x96f8a04 1 0>,
+ <DCC_READ 0x96f8a18 1 0>,
+ <DCC_READ 0x96f8ea8 1 0>,
+ <DCC_READ 0x96f9044 1 0>,
+ <DCC_READ 0x96f904c 1 0>,
+ <DCC_READ 0x96f9054 1 0>,
+ <DCC_READ 0x96f905c 1 0>,
+ <DCC_READ 0x96f910c 2 0>,
+ <DCC_READ 0x96f9204 1 0>,
+ <DCC_READ 0x96f920c 1 0>,
+ <DCC_READ 0x96f9238 1 0>,
+ <DCC_READ 0x96f9240 1 0>,
+ <DCC_READ 0x96f926c 1 0>,
+ <DCC_READ 0x96f9394 1 0>,
+ <DCC_READ 0x96f939c 1 0>,
+ <DCC_READ 0x96f9704 1 0>,
+ <DCC_READ 0x96f970c 1 0>,
+ <DCC_READ 0x9730868 1 0>,
+ <DCC_READ 0x9730870 1 0>,
+ <DCC_READ 0x9731004 1 0>,
+ <DCC_READ 0x973100c 1 0>,
+ <DCC_READ 0x9731014 1 0>,
+ <DCC_READ 0x9731204 1 0>,
+ <DCC_READ 0x973120c 1 0>,
+ <DCC_READ 0x9731214 1 0>,
+ <DCC_READ 0x9731504 1 0>,
+ <DCC_READ 0x973150c 1 0>,
+ <DCC_READ 0x9731514 1 0>,
+ <DCC_READ 0x9731604 1 0>,
+ <DCC_READ 0x9738100 1 0>,
+ <DCC_READ 0x973813c 1 0>,
+ <DCC_READ 0x9738500 1 0>,
+ <DCC_READ 0x973853c 1 0>,
+ <DCC_READ 0x9738a04 1 0>,
+ <DCC_READ 0x9738a18 1 0>,
+ <DCC_READ 0x9738ea8 1 0>,
+ <DCC_READ 0x9739044 1 0>,
+ <DCC_READ 0x973904c 1 0>,
+ <DCC_READ 0x9739054 1 0>,
+ <DCC_READ 0x973905c 1 0>,
+ <DCC_READ 0x973910c 2 0>,
+ <DCC_READ 0x9739204 1 0>,
+ <DCC_READ 0x973920c 1 0>,
+ <DCC_READ 0x9739238 1 0>,
+ <DCC_READ 0x9739240 1 0>,
+ <DCC_READ 0x973926c 1 0>,
+ <DCC_READ 0x9739394 1 0>,
+ <DCC_READ 0x973939c 1 0>,
+ <DCC_READ 0x9739704 1 0>,
+ <DCC_READ 0x973970c 1 0>,
+ <DCC_READ 0x9770868 1 0>,
+ <DCC_READ 0x9770870 1 0>,
+ <DCC_READ 0x9771004 1 0>,
+ <DCC_READ 0x977100c 1 0>,
+ <DCC_READ 0x9771014 1 0>,
+ <DCC_READ 0x9771204 1 0>,
+ <DCC_READ 0x977120c 1 0>,
+ <DCC_READ 0x9771214 1 0>,
+ <DCC_READ 0x9771504 1 0>,
+ <DCC_READ 0x977150c 1 0>,
+ <DCC_READ 0x9771514 1 0>,
+ <DCC_READ 0x9771604 1 0>,
+ <DCC_READ 0x9778100 1 0>,
+ <DCC_READ 0x977813c 1 0>,
+ <DCC_READ 0x9778500 1 0>,
+ <DCC_READ 0x977853c 1 0>,
+ <DCC_READ 0x9778a04 1 0>,
+ <DCC_READ 0x9778a18 1 0>,
+ <DCC_READ 0x9778ea8 1 0>,
+ <DCC_READ 0x9779044 1 0>,
+ <DCC_READ 0x977904c 1 0>,
+ <DCC_READ 0x9779054 1 0>,
+ <DCC_READ 0x977905c 1 0>,
+ <DCC_READ 0x977910c 2 0>,
+ <DCC_READ 0x9779204 1 0>,
+ <DCC_READ 0x977920c 1 0>,
+ <DCC_READ 0x9779238 1 0>,
+ <DCC_READ 0x9779240 1 0>,
+ <DCC_READ 0x977926c 1 0>,
+ <DCC_READ 0x9779394 1 0>,
+ <DCC_READ 0x977939c 1 0>,
+ <DCC_READ 0x9779704 1 0>,
+ <DCC_READ 0x977970c 1 0>,
+ <DCC_READ 0x910d100 3 0>,
+ <DCC_READ 0x914d100 3 0>,
+ <DCC_READ 0x918d100 4 0>,
+ <DCC_READ 0x91a5100 1 0>,
+ <DCC_READ 0x91ad100 1 0>;
+ };
+
+ };
+
+ qcom_seecom: qseecom@82400000 {
+ compatible = "qcom,qseecom";
+ reg = <0x82400000 0x3A00000>;
+ reg-names = "secapp-region";
+ memory-region = <&qseecom_mem>;
+ qcom,hlos-num-ce-hw-instances = <1>;
+ qcom,hlos-ce-hw-instance = <0>;
+ qcom,qsee-ce-hw-instance = <0>;
+ qcom,disk-encrypt-pipe-pair = <2>;
+ qcom,support-fde;
+ qcom,no-clock-support;
+ qcom,fde-key-size;
+ qcom,appsbl-qseecom-support;
+ qcom,commonlib64-loaded-by-uefi;
+ qcom,qsee-reentrancy-support = <2>;
+ };
+
+ qcom_rng: qrng@793000 {
+ compatible = "qcom,msm-rng";
+ reg = <0x793000 0x1000>;
+ qcom,msm-rng-iface-clk;
+ qcom,no-qrng-config;
+ qcom,msm-bus,name = "msm-rng-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 618 0 0>, /* No vote */
+ <1 618 0 300000>; /* 75 MHz */
+ clocks = <&clock_gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "iface_clk";
+ };
+
+ mdm0: qcom,mdm0 {
+ compatible = "qcom,ext-sdx55m";
+ cell-index = <0>;
+ #address-cells = <0>;
+ interrupt-parent = <&mdm0>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-names =
+ "err_fatal_irq",
+ "status_irq",
+ "mdm2ap_vddmin_irq";
+ /* modem attributes */
+ qcom,ramdump-delay-ms = <3000>;
+ qcom,ramdump-timeout-ms = <120000>;
+ qcom,vddmin-modes = "normal";
+ qcom,vddmin-drive-strength = <8>;
+ qcom,sfr-query;
+ qcom,sysmon-id = <20>;
+ qcom,ssctl-instance-id = <0x10>;
+ qcom,support-shutdown;
+ qcom,pil-force-shutdown;
+ qcom,esoc-skip-restart-for-mdm-crash;
+ pinctrl-names = "mdm_active", "mdm_suspend";
+ pinctrl-0 = <&ap2mdm_active &mdm2ap_active>;
+ pinctrl-1 = <&ap2mdm_sleep &mdm2ap_sleep>;
+ interrupt-map = <0 &tlmm 1 0x3
+ 1 &tlmm 3 0x3>;
+ qcom,mdm2ap-errfatal-gpio = <&tlmm 1 0x00>;
+ qcom,ap2mdm-errfatal-gpio = <&tlmm 57 0x00>;
+ qcom,mdm2ap-status-gpio = <&tlmm 3 0x00>;
+ qcom,ap2mdm-status-gpio = <&tlmm 56 0x00>;
+ qcom,mdm-link-info = "0306_02.01.00";
+ status = "ok";
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,kona-pdc";
+ reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
+ qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 716 12>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <38400000>;
+ clock-output-names = "xo_board";
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ clock-output-names = "chip_sleep_clk";
+ #clock-cells = <1>;
+ };
+ };
+
+ clock_aop: qcom,aopclk {
+ compatible = "qcom,aop-qmp-clk";
+ #clock-cells = <1>;
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "qdss_clk";
+ qcom,clk-stop-bimc-log;
+ };
+
+ clock_gcc: qcom,gcc@100000 {
+ compatible = "qcom,gcc-kona", "syscon";
+ reg = <0x100000 0x1f0000>;
+ reg-names = "cc_base";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
+ vdd_mm-supply = <&VDD_MMCX_LEVEL>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ clock_npucc: qcom,npucc@9980000 {
+ compatible = "qcom,npucc-kona", "syscon";
+ reg = <0x9980000 0x10000>,
+ <0x9800000 0x10000>,
+ <0x9810000 0x10000>;
+ reg-names = "cc", "qdsp6ss", "qdsp6ss_pll";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ clock_videocc: qcom,videocc@abf0000 {
+ compatible = "qcom,videocc-kona", "syscon";
+ reg = <0xabf0000 0x10000>;
+ reg-names = "cc_base";
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ vdd_mm-supply = <&VDD_MMCX_LEVEL>;
+ clock-names = "cfg_ahb_clk";
+ clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ clock_camcc: qcom,camcc@ad00000 {
+ compatible = "qcom,camcc-kona", "syscon";
+ reg = <0xad00000 0x10000>;
+ reg-names = "cc_base";
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ vdd_mm-supply = <&VDD_MMCX_LEVEL>;
+ clock-names = "cfg_ahb_clk";
+ clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ clock_dispcc: qcom,dispcc@af00000 {
+ compatible = "qcom,kona-dispcc", "syscon";
+ reg = <0xaf00000 0x20000>;
+ reg-names = "cc_base";
+ vdd_mm-supply = <&VDD_MMCX_LEVEL>;
+ clock-names = "cfg_ahb_clk";
+ clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ clock_gpucc: qcom,gpucc@3d90000 {
+ compatible = "qcom,gpucc-kona", "syscon";
+ reg = <0x3d90000 0x9000>;
+ reg-names = "cc_base";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ clock_cpucc: qcom,cpucc {
+ compatible = "qcom,dummycc";
+ clock-output-names = "cpucc_clocks";
+ #clock-cells = <1>;
+ };
+
+ clock_apsscc: syscon@182a0000 {
+ compatible = "syscon";
+ reg = <0x182a0000 0x1c>;
+ };
+
+ clock_mccc: syscon@90ba000 {
+ compatible = "syscon";
+ reg = <0x90ba000 0x54>;
+ };
+
+ clock_debugcc: qcom,cc-debug {
+ compatible = "qcom,kona-debugcc";
+ qcom,gcc = <&clock_gcc>;
+ qcom,videocc = <&clock_videocc>;
+ qcom,dispcc = <&clock_dispcc>;
+ qcom,camcc = <&clock_camcc>;
+ qcom,gpucc = <&clock_gpucc>;
+ qcom,npucc = <&clock_npucc>;
+ qcom,apsscc = <&clock_apsscc>;
+ qcom,mccc = <&clock_mccc>;
+ clock-names = "xo_clk_src";
+ clocks = <&clock_rpmh RPMH_CXO_CLK>;
+ #clock-cells = <1>;
+ };
+
+ /* GCC GDSCs */
+ pcie_0_gdsc: qcom,gdsc@16b004 {
+ compatible = "qcom,gdsc";
+ reg = <0x16b004 0x4>;
+ regulator-name = "pcie_0_gdsc";
+ qcom,retain-regs;
+ };
+
+ pcie_1_gdsc: qcom,gdsc@18d004 {
+ compatible = "qcom,gdsc";
+ reg = <0x18d004 0x4>;
+ regulator-name = "pcie_1_gdsc";
+ qcom,retain-regs;
+ };
+
+ pcie_2_gdsc: qcom,gdsc@106004 {
+ compatible = "qcom,gdsc";
+ reg = <0x106004 0x4>;
+ regulator-name = "pcie_2_gdsc";
+ qcom,retain-regs;
+ };
+
+ ufs_phy_gdsc: qcom,gdsc@177004 {
+ compatible = "qcom,gdsc";
+ reg = <0x177004 0x4>;
+ regulator-name = "ufs_phy_gdsc";
+ qcom,retain-regs;
+ };
+
+ usb30_prim_gdsc: qcom,gdsc@10f004 {
+ compatible = "qcom,gdsc";
+ reg = <0x10f004 0x4>;
+ regulator-name = "usb30_prim_gdsc";
+ qcom,retain-regs;
+ };
+
+ usb30_sec_gdsc: qcom,gdsc@110004 {
+ compatible = "qcom,gdsc";
+ reg = <0x110004 0x4>;
+ regulator-name = "usb30_sec_gdsc";
+ qcom,retain-regs;
+ };
+
+ hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
+ compatible = "qcom,gdsc";
+ reg = <0x17d050 0x4>;
+ regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ };
+
+ hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
+ compatible = "qcom,gdsc";
+ reg = <0x17d058 0x4>;
+ regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ };
+
+ hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {
+ compatible = "qcom,gdsc";
+ reg = <0x17d054 0x4>;
+ regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ };
+
+ hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc: qcom,gdsc@17d06c {
+ compatible = "qcom,gdsc";
+ reg = <0x17d06c 0x4>;
+ regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc";
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ };
+
+ /* CAM_CC GDSCs */
+ bps_gdsc: qcom,gdsc@ad07004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad07004 0x4>;
+ regulator-name = "bps_gdsc";
+ clock-names = "ahb_clk";
+ clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+ parent-supply = <&VDD_MMCX_LEVEL>;
+ vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+ qcom,msm-bus,name = "bps_gdsc_ahb";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 1>;
+ qcom,support-hw-trigger;
+ qcom,retain-regs;
+ };
+
+ ife_0_gdsc: qcom,gdsc@ad0a004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad0a004 0x4>;
+ regulator-name = "ife_0_gdsc";
+ clock-names = "ahb_clk";
+ clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+ parent-supply = <&VDD_MMCX_LEVEL>;
+ vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+ qcom,msm-bus,name = "ife_0_gdsc_ahb";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 1>;
+ qcom,retain-regs;
+ };
+
+ ife_1_gdsc: qcom,gdsc@ad0b004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad0b004 0x4>;
+ regulator-name = "ife_1_gdsc";
+ clock-names = "ahb_clk";
+ clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+ parent-supply = <&VDD_MMCX_LEVEL>;
+ vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+ qcom,msm-bus,name = "ife_1_gdsc_ahb";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 1>;
+ qcom,retain-regs;
+ };
+
+ ipe_0_gdsc: qcom,gdsc@ad08004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad08004 0x4>;
+ regulator-name = "ipe_0_gdsc";
+ clock-names = "ahb_clk";
+ clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+ parent-supply = <&VDD_MMCX_LEVEL>;
+ vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+ qcom,msm-bus,name = "ipe_0_gdsc_ahb";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 1>;
+ qcom,support-hw-trigger;
+ qcom,retain-regs;
+ };
+
+ sbi_gdsc: qcom,gdsc@ad09004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad09004 0x4>;
+ regulator-name = "sbi_gdsc";
+ clock-names = "ahb_clk";
+ clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+ parent-supply = <&VDD_MMCX_LEVEL>;
+ vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+ qcom,msm-bus,name = "sbi_gdsc_ahb";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 1>;
+ qcom,retain-regs;
+ };
+
+ titan_top_gdsc: qcom,gdsc@ad0c144 {
+ compatible = "qcom,gdsc";
+ reg = <0xad0c144 0x4>;
+ regulator-name = "titan_top_gdsc";
+ clock-names = "ahb_clk";
+ clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>;
+ parent-supply = <&VDD_MMCX_LEVEL>;
+ vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+ qcom,msm-bus,name = "titan_top_gdsc_ahb";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_CAMERA_CFG 0 1>;
+ qcom,retain-regs;
+ qcom,gds-timeout = <500>;
+ };
+
+ /* DISP_CC GDSC */
+ mdss_core_gdsc: qcom,gdsc@af03000 {
+ compatible = "qcom,gdsc";
+ reg = <0xaf03000 0x4>;
+ regulator-name = "mdss_core_gdsc";
+ clock-names = "ahb_clk";
+ clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
+ parent-supply = <&VDD_MMCX_LEVEL>;
+ vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+ qcom,msm-bus,name = "mdss_core_gdsc_ahb";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_DISPLAY_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_DISPLAY_CFG 0 1>;
+ qcom,support-hw-trigger;
+ qcom,retain-regs;
+ proxy-supply = <&mdss_core_gdsc>;
+ qcom,proxy-consumer-enable;
+ };
+
+ /* GPU_CC GDSCs */
+ gpu_cx_hw_ctrl: syscon@3d91540 {
+ compatible = "syscon";
+ reg = <0x3d91540 0x4>;
+ };
+
+ gpu_cx_gdsc: qcom,gdsc@3d9106c {
+ compatible = "qcom,gdsc";
+ reg = <0x3d9106c 0x4>;
+ regulator-name = "gpu_cx_gdsc";
+ hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
+ parent-supply = <&VDD_CX_LEVEL>;
+ vdd_parent-supply = <&VDD_CX_LEVEL>;
+ qcom,no-status-check-on-disable;
+ qcom,clk-dis-wait-val = <8>;
+ qcom,gds-timeout = <500>;
+ qcom,retain-regs;
+ };
+
+ gpu_gx_domain_addr: syscon@3d91508 {
+ compatible = "syscon";
+ reg = <0x3d91508 0x4>;
+ };
+
+ gpu_gx_sw_reset: syscon@3d91008 {
+ compatible = "syscon";
+ reg = <0x3d91008 0x4>;
+ };
+
+ gpu_gx_gdsc: qcom,gdsc@3d9100c {
+ compatible = "qcom,gdsc";
+ reg = <0x3d9100c 0x4>;
+ regulator-name = "gpu_gx_gdsc";
+ domain-addr = <&gpu_gx_domain_addr>;
+ sw-reset = <&gpu_gx_sw_reset>;
+ parent-supply = <&VDD_GFX_LEVEL>;
+ vdd_parent-supply = <&VDD_GFX_LEVEL>;
+ qcom,skip-disable-before-sw-enable;
+ qcom,reset-aon-logic;
+ qcom,retain-regs;
+ };
+
+ /* NPU GDSC */
+ npu_core_gdsc: qcom,gdsc@9981004 {
+ compatible = "qcom,gdsc";
+ reg = <0x9981004 0x4>;
+ regulator-name = "npu_core_gdsc";
+ clock-names = "ahb_clk";
+ clocks = <&clock_gcc GCC_NPU_CFG_AHB_CLK>;
+ qcom,retain-regs;
+ };
+
+ qcom,sps {
+ compatible = "qcom,msm-sps-4k";
+ qcom,pipe-attr-ee;
+ };
+
+ /* VIDEO_CC GDSCs */
+ mvs0_gdsc: qcom,gdsc@abf0d18 {
+ compatible = "qcom,gdsc";
+ reg = <0xabf0d18 0x4>;
+ regulator-name = "mvs0_gdsc";
+ clock-names = "ahb_clk";
+ clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
+ parent-supply = <&VDD_MMCX_LEVEL>;
+ vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+ qcom,msm-bus,name = "mvs0_gdsc_ahb";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 1>;
+ qcom,support-hw-trigger;
+ qcom,retain-regs;
+ };
+
+ mvs0c_gdsc: qcom,gdsc@abf0bf8 {
+ compatible = "qcom,gdsc";
+ reg = <0xabf0bf8 0x4>;
+ regulator-name = "mvs0c_gdsc";
+ clock-names = "ahb_clk";
+ clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
+ parent-supply = <&VDD_MMCX_LEVEL>;
+ vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+ qcom,msm-bus,name = "mvs0c_gdsc_ahb";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 1>;
+ qcom,retain-regs;
+ };
+
+ mvs1_gdsc: qcom,gdsc@abf0d98 {
+ compatible = "qcom,gdsc";
+ reg = <0xabf0d98 0x4>;
+ regulator-name = "mvs1_gdsc";
+ clock-names = "ahb_clk";
+ clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
+ parent-supply = <&VDD_MMCX_LEVEL>;
+ vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+ qcom,msm-bus,name = "mvs1_gdsc_ahb";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 1>;
+ qcom,support-hw-trigger;
+ qcom,retain-regs;
+ };
+
+ mvs1c_gdsc: qcom,gdsc@abf0c98 {
+ compatible = "qcom,gdsc";
+ reg = <0xabf0c98 0x4>;
+ regulator-name = "mvs1c_gdsc";
+ clock-names = "ahb_clk";
+ clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>;
+ parent-supply = <&VDD_MMCX_LEVEL>;
+ vdd_parent-supply = <&VDD_MMCX_LEVEL>;
+ qcom,msm-bus,name = "mvs1c_gdsc_ahb";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VENUS_CFG 0 1>;
+ qcom,retain-regs;
+ };
+
+ spmi_bus: qcom,spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0xc440000 0x1100>,
+ <0xc600000 0x2000000>,
+ <0xe600000 0x100000>,
+ <0xe700000 0xa0000>,
+ <0xc40a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
+ spmi_debug_bus: qcom,spmi-debug@6b0f000 {
+ compatible = "qcom,spmi-pmic-arb-debug";
+ reg = <0x6b0f000 0x60>, <0x7820a8 0x4>;
+ reg-names = "core", "fuse";
+ clocks = <&clock_aop QDSS_CLK>;
+ clock-names = "core_clk";
+ qcom,fuse-disable-bit = <24>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ qcom,pm8150-debug@0 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ qcom,can-sleep;
+ };
+
+ qcom,pm8150-debug@1 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ qcom,can-sleep;
+ };
+
+ qcom,pm8150b-debug@2 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x2 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ qcom,can-sleep;
+ };
+
+ qcom,pm8150b-debug@3 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ qcom,can-sleep;
+ };
+
+ qcom,pm8150l-debug@4 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ qcom,can-sleep;
+ };
+
+ qcom,pm8150l-debug@5 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x5 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ qcom,can-sleep;
+ };
+
+ qcom,pmk8002-debug@6 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x6 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ qcom,can-sleep;
+ };
+
+ qcom,pmk8002-debug@7 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x7 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ qcom,can-sleep;
+ };
+
+ qcom,pmxprairie-debug@8 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x8 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ qcom,can-sleep;
+ };
+
+ qcom,pmxprairie-debug@9 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x9 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ qcom,can-sleep;
+ };
+
+ qcom,pm8009-debug@a {
+ compatible = "qcom,spmi-pmic";
+ reg = <0xa SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ qcom,can-sleep;
+ };
+
+ qcom,pm8009-debug@b {
+ compatible = "qcom,spmi-pmic";
+ reg = <0xb SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ qcom,can-sleep;
+ };
+ };
+
+ ufsphy_mem: ufsphy_mem@1d87000 {
+ reg = <0x1d87000 0xe00>, <0x1d90000 0x8000>; /* PHY regs */
+ reg-names = "phy_mem", "ufs_ice";
+ #phy-cells = <0>;
+
+ lanes-per-direction = <2>;
+
+ clock-names = "ref_clk_src",
+ "ref_aux_clk";
+ clocks = <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+ status = "disabled";
+ };
+
+ ufshc_mem: ufshc@1d84000 {
+ compatible = "qcom,ufshc";
+ reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;
+ reg-names = "ufs_mem", "ufs_ice";
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufsphy_mem>;
+ phy-names = "ufsphy";
+
+ lanes-per-direction = <2>;
+ dev-ref-clk-freq = <0>; /* 19.2 MHz */
+
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "core_clk_ice",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ clocks =
+ <&clock_gcc GCC_UFS_PHY_AXI_CLK>,
+ <&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&clock_gcc GCC_UFS_PHY_AHB_CLK>,
+ <&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+ <&clock_rpmh RPMH_CXO_CLK>,
+ <&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ freq-table-hz =
+ <37500000 300000000>,
+ <0 0>,
+ <0 0>,
+ <37500000 300000000>,
+ <37500000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ qcom,msm-bus,name = "ufshc_mem";
+ qcom,msm-bus,num-cases = <26>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /*
+ * During HS G3 UFS runs at nominal voltage corner, vote
+ * higher bandwidth to push other buses in the data path
+ * to run at nominal to achieve max throughput.
+ * 4GBps pushes BIMC to run at nominal.
+ * 200MBps pushes CNOC to run at nominal.
+ * Vote for half of this bandwidth for HS G3 1-lane.
+ * For max bandwidth, vote high enough to push the buses
+ * to run in turbo voltage corner.
+ */
+ <123 512 0 0>, <1 757 0 0>, /* No vote */
+ <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */
+ <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */
+ <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */
+ <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */
+ <123 512 1844 0>, <1 757 1000 0>, /* PWM G1 L2 */
+ <123 512 3688 0>, <1 757 1000 0>, /* PWM G2 L2 */
+ <123 512 7376 0>, <1 757 1000 0>, /* PWM G3 L2 */
+ <123 512 14752 0>, <1 757 1000 0>, /* PWM G4 L2 */
+ <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */
+ <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */
+ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */
+ <123 512 4194304 0>, <1 757 204800 0>, /* HS G4 RA */
+ <123 512 255591 0>, <1 757 1000 0>, /* HS G1 RA L2 */
+ <123 512 511181 0>, <1 757 1000 0>, /* HS G2 RA L2 */
+ <123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */
+ <123 512 8388608 0>, <1 757 409600 0>, /* HS G4 RA L2 */
+ <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */
+ <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */
+ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */
+ <123 512 4194304 0>, <1 757 204800 0>, /* HS G4 RB */
+ <123 512 298189 0>, <1 757 1000 0>, /* HS G1 RB L2 */
+ <123 512 596378 0>, <1 757 1000 0>, /* HS G2 RB L2 */
+ /* As UFS working in HS G3 RB L2 mode, aggregated
+ * bandwidth (AB) should take care of providing
+ * optimum throughput requested. However, as tested,
+ * in order to scale up CNOC clock, instantaneous
+ * bindwidth (IB) needs to be given a proper value too.
+ */
+ <123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */
+ <123 512 8388608 0>, <1 757 409600 409600>, /* HS G4 RB L2 */
+ <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
+
+ qcom,bus-vector-names = "MIN",
+ "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
+ "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
+ "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
+ "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
+ "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
+ "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
+
+ "MAX";
+
+ /* PM QoS */
+ qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
+ qcom,pm-qos-cpu-group-latency-us = <44 44>;
+ qcom,pm-qos-default-cpu = <0>;
+
+ pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
+ pinctrl-0 = <&ufs_dev_reset_assert>;
+ pinctrl-1 = <&ufs_dev_reset_deassert>;
+
+ resets = <&clock_gcc GCC_UFS_PHY_BCR>;
+ reset-names = "core_reset";
+
+ status = "disabled";
+ };
+
+ sdhc_2: sdhci@8804000 {
+ compatible = "qcom,sdhci-msm-v5";
+ reg = <0x8804000 0x1000>;
+ reg-names = "hc_mem";
+
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <4>;
+ qcom,large-address-bus;
+
+ qcom,msm-bus,name = "sdhc2";
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <81 512 0 0>, <1 608 0 0>,
+ /* 400 KB/s*/
+ <81 512 1046 1600>,
+ <1 608 1600 1600>,
+ /* 20 MB/s */
+ <81 512 52286 80000>,
+ <1 608 80000 80000>,
+ /* 25 MB/s */
+ <81 512 65360 100000>,
+ <1 608 100000 100000>,
+ /* 50 MB/s */
+ <81 512 130718 200000>,
+ <1 608 133320 133320>,
+ /* 100 MB/s */
+ <81 512 261438 200000>,
+ <1 608 150000 150000>,
+ /* 200 MB/s */
+ <81 512 261438 400000>,
+ <1 608 300000 300000>,
+ /* Max. bandwidth */
+ <81 512 1338562 4096000>,
+ <1 608 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100750000 200000000 4294967295>;
+
+ qcom,restore-after-cx-collapse;
+
+ qcom,clk-rates = <400000 20000000 25000000
+ 50000000 100000000 201500000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
+ "SDR104";
+
+ qcom,devfreq,freq-table = <50000000 201500000>;
+ clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
+ <&clock_gcc GCC_SDCC2_APPS_CLK>;
+ clock-names = "iface_clk", "core_clk";
+
+ /* PM QoS */
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <44 44>;
+ qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
+ qcom,pm-qos-legacy-latency-us = <44 44>, <44 44>;
+
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x0007642C 0xA800 0x10
+ 0x2C010800 0x80040868>;
+
+ status = "disabled";
+ };
+
+ ipcc_mproc: qcom,ipcc@408000 {
+ compatible = "qcom,ipcc";
+ reg = <0x408000 0x1000>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #mbox-cells = <2>;
+ };
+
+ apps_rsc: rsc@18200000 {
+ label = "apps_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x18200000 0x10000>,
+ <0x18210000 0x10000>,
+ <0x18220000 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 3>,
+ <WAKE_TCS 3>,
+ <CONTROL_TCS 1>;
+
+ msm_bus_apps_rsc {
+ compatible = "qcom,msm-bus-rsc";
+ qcom,msm-bus-id = <MSM_BUS_RSC_APPS>;
+ };
+
+ system_pm {
+ compatible = "qcom,system-pm";
+ };
+
+ clock_rpmh: qcom,rpmhclk {
+ compatible = "qcom,kona-rpmh-clk";
+ #clock-cells = <1>;
+ };
+ };
+
+ disp_rsc: rsc@af20000 {
+ label = "disp_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0xaf20000 0x10000>;
+ reg-names = "drv-0";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0x1c00>;
+ qcom,drv-id = <0>;
+ qcom,tcs-config = <ACTIVE_TCS 0>,
+ <SLEEP_TCS 1>,
+ <WAKE_TCS 1>,
+ <CONTROL_TCS 0>;
+
+ msm_bus_disp_rsc {
+ compatible = "qcom,msm-bus-rsc";
+ qcom,msm-bus-id = <MSM_BUS_RSC_DISP>;
+ };
+
+ sde_rsc_rpmh {
+ compatible = "qcom,sde-rsc-rpmh";
+ cell-index = <0>;
+ };
+ };
+
+ tcsr_mutex_block: syscon@1f40000 {
+ compatible = "syscon";
+ reg = <0x1f40000 0x20000>;
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_block 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ smem: qcom,smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ kryo-erp {
+ compatible = "arm,arm64-kryo-cpu-erp";
+ interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "l1-l2-faultirq",
+ "l3-scu-faultirq";
+ };
+
+ sp_scsr: mailbox@188501c {
+ compatible = "qcom,kona-spcs-global";
+ reg = <0x188501c 0x4>;
+
+ #mbox-cells = <1>;
+ };
+
+ sp_scsr_block: syscon@1880000 {
+ compatible = "syscon";
+ reg = <0x1880000 0x10000>;
+ };
+
+ intsp: qcom,qsee_irq {
+ compatible = "qcom,kona-qsee-irq";
+
+ syscon = <&sp_scsr_block>;
+ interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>,
+ <0 349 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "sp_ipc0",
+ "sp_ipc1";
+
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ qcom,qsee_irq_bridge {
+ compatible = "qcom,qsee-ipc-irq-bridge";
+
+ qcom,qsee-ipc-irq-spss {
+ qcom,dev-name = "qsee_ipc_irq_spss";
+ label = "spss";
+ interrupt-parent = <&intsp>;
+ interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ spss_utils: qcom,spss_utils {
+ compatible = "qcom,spss-utils";
+ /* spss fuses physical address */
+ qcom,spss-fuse1-addr = <0x00780234>;
+ qcom,spss-fuse1-bit = <27>;
+ qcom,spss-fuse2-addr = <0x00780234>;
+ qcom,spss-fuse2-bit = <26>;
+ qcom,spss-fuse3-addr = <0x007801E8>; // IAR_FEATURE_ENABLED fuse
+ qcom,spss-fuse3-bit = <10>;
+ qcom,spss-fuse4-addr = <0x00780218>; // IAR_STATE fuse
+ qcom,spss-fuse4-bit = <1>; // 0x00780214 bits 33-35
+ qcom,spss-dev-firmware-name = "spss1d"; /* 8 chars max */
+ qcom,spss-test-firmware-name = "spss1t"; /* 8 chars max */
+ qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */
+ qcom,spss-debug-reg-addr = <0x01886020>;
+ qcom,spss-emul-type-reg-addr = <0x01fc8004>;
+ pil-mem = <&pil_spss_mem>;
+ qcom,pil-addr = <0x8BE00000>; // backward compatible
+ qcom,pil-size = <0x0F0000>; // padding to 960 KB
+ status = "ok";
+ };
+
+ qcom,spcom {
+ compatible = "qcom,spcom";
+
+ /* predefined channels, remote side is server */
+ qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
+ /* rmb_err shared register physical address */
+ qcom,spcom-rmb-err-reg-addr = <0x188103c>;
+ /* sp2soc rmb shared register physical address and bmsk */
+ qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>;
+ qcom,spcom-sp2soc-rmb-initdone-bit = <24>;
+ qcom,spcom-sp2soc-rmb-pbldone-bit = <25>;
+ /* soc2sp rmb shared register physical address */
+ qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>;
+ qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>;
+ status = "ok";
+ };
+
+ qcom,msm_gsi {
+ compatible = "qcom,msm_gsi";
+ };
+
+ qcom,rmnet-ipa {
+ compatible = "qcom,rmnet-ipa3";
+ qcom,rmnet-ipa-ssr;
+ qcom,ipa-advertise-sg-support;
+ qcom,ipa-napi-enable;
+ };
+
+ qcom,ipa_fws {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <0xf>;
+ qcom,firmware-name = "ipa_fws";
+ qcom,pil-force-shutdown;
+ memory-region = <&pil_ipa_gsi_mem>;
+ };
+
+ qcom,ipa_uc {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <0x1B>;
+ qcom,firmware-name = "ipa_uc";
+ qcom,pil-force-shutdown;
+ memory-region = <&pil_ipa_fw_mem>;
+ };
+
+ qcom,ipa-mpm {
+ compatible = "qcom,ipa-mpm";
+ qcom,mhi-chdb-base = <0x64300300>;
+ qcom,mhi-erdb-base = <0x64300700>;
+ qcom,iova-mapping = <0x10000000 0x0FFFFFFF>;
+ };
+
+ ipa_hw: qcom,ipa@1e00000 {
+ compatible = "qcom,ipa";
+ mboxes = <&qmp_aop 0>;
+ reg =
+ <0x1e00000 0x84000>,
+ <0x1e04000 0x23000>;
+ reg-names = "ipa-base", "gsi-base";
+ interrupts =
+ <0 311 IRQ_TYPE_LEVEL_HIGH>,
+ <0 432 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ipa-irq", "gsi-irq";
+ qcom,ipa-hw-ver = <17>; /* IPA core version = IPAv4.5 */
+ qcom,ipa-hw-mode = <0>;
+ qcom,platform-type = <2>; /* APQ platform */
+ qcom,ee = <0>;
+ qcom,use-ipa-tethering-bridge;
+ qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */
+ qcom,modem-cfg-emb-pipe-flt;
+ qcom,ipa-wdi3-over-gsi;
+ qcom,arm-smmu;
+ qcom,smmu-fast-map;
+ qcom,bandwidth-vote-for-ipa;
+ qcom,use-64-bit-dma-mask;
+ qcom,ipa-endp-delay-wa;
+ qcom,msm-bus,name = "ipa";
+ qcom,msm-bus,num-cases = <5>;
+ qcom,msm-bus,num-paths = <5>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 0 0>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 0>,
+
+ /* SVS2 */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 150000 600000>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 150000 1804000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 75000 300000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 76800>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 150>,
+
+ /* SVS */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 625000 1200000>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 625000 3072000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 312500 700000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 150000>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 240>,
+
+ /* NOMINAL */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 1250000 2400000>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 1250000 6220800>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 625000 1500000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 400000>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 466>,
+
+ /* TURBO */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 2000000 3500000>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 2000000 7219200>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 1000000 1920000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 400000>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 533>;
+
+ qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
+ "TURBO";
+ qcom,throughput-threshold = <600 2500 5000>;
+ qcom,scaling-exceptions = "wdi", "0", "600", "1200",
+ "USB DPL", "0", "2500", "5000", "ODL", "0",
+ "2500", "5000";
+
+ qcom,entire-ipa-block-size = <0x100000>;
+ qcom,register-collection-on-crash;
+ qcom,testbus-collection-on-crash;
+ qcom,non-tn-collection-on-crash;
+ qcom,ram-collection-on-crash;
+ qcom,secure-debug-check-action = <0>;
+
+ ipa_smmu_ap: ipa_smmu_ap {
+ compatible = "qcom,ipa-smmu-ap-cb";
+ iommus = <&apps_smmu 0x5C0 0x0>;
+ qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
+ qcom,additional-mapping =
+ /* modem tables in IMEM */
+ <0x146BD000 0x146BD000 0x2000>;
+ dma-coherent;
+ qcom,iommu-dma = "fastmap";
+ };
+
+ ipa_smmu_wlan: ipa_smmu_wlan {
+ compatible = "qcom,ipa-smmu-wlan-cb";
+ iommus = <&apps_smmu 0x5C1 0x0>;
+ qcom,iommu-dma = "fastmap";
+ dma-coherent;
+ };
+
+ ipa_smmu_uc: ipa_smmu_uc {
+ compatible = "qcom,ipa-smmu-uc-cb";
+ iommus = <&apps_smmu 0x5C2 0x0>;
+ qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
+ qcom,iommu-dma = "fastmap";
+ };
+
+ ipa_smmu_11ad: ipa_smmu_11ad {
+ compatible = "qcom,ipa-smmu-11ad-cb";
+ iommus = <&apps_smmu 0x5C3 0x0>;
+ dma-coherent;
+ qcom,shared-cb;
+ qcom,iommu-group = <&wil6210_pci_iommu_group>;
+ };
+ };
+
+ qcom,glink {
+ compatible = "qcom,glink";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ glink_npu: npu {
+ qcom,remote-pid = <10>;
+ transport = "smem";
+ mboxes = <&msm_npu IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "npu_smem";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ label = "npu";
+ qcom,glink-label = "npu";
+
+ qcom,npu_qrtr {
+ qcom,net-id = <1>;
+ qcom,glink-channels = "IPCRTR";
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,npu_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_cdsp>;
+ };
+ };
+
+ glink_adsp: adsp {
+ qcom,remote-pid = <2>;
+ transport = "smem";
+ mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "adsp_smem";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ label = "adsp";
+ qcom,glink-label = "lpass";
+
+ qcom,adsp_qrtr {
+ qcom,net-id = <2>;
+ qcom,glink-channels = "IPCRTR";
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,apr_tal_rpmsg {
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,intents = <0x200 20>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,adsp_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_slpi>,
+ <&glink_cdsp>;
+ };
+ };
+
+ glink_slpi: dsps {
+ qcom,remote-pid = <3>;
+ transport = "smem";
+ mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "dsps_smem";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_SLPI
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ label = "slpi";
+ qcom,glink-label = "dsps";
+
+ qcom,slpi_qrtr {
+ qcom,net-id = <2>;
+ qcom,glink-channels = "IPCRTR";
+ qcom,low-latency;
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,slpi_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_adsp>,
+ <&glink_cdsp>;
+ };
+ };
+
+ glink_cdsp: cdsp {
+ qcom,remote-pid = <5>;
+ transport = "smem";
+ mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "dsps_smem";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ label = "cdsp";
+ qcom,glink-label = "cdsp";
+
+ qcom,cdsp_qrtr {
+ qcom,net-id = <1>;
+ qcom,glink-channels = "IPCRTR";
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,msm_cdsprm_rpmsg {
+ compatible = "qcom,msm-cdsprm-rpmsg";
+ qcom,glink-channels = "cdsprmglink-apps-dsp";
+ qcom,intents = <0x20 12>;
+
+ qcom,cdsp-cdsp-l3-gov {
+ compatible = "qcom,cdsp-l3";
+ qcom,target-dev = <&cdsp_l3>;
+ };
+
+ msm_cdsp_rm: qcom,msm_cdsp_rm {
+ compatible = "qcom,msm-cdsp-rm";
+ qcom,qos-latency-us = <44>;
+ qcom,qos-maxhold-ms = <20>;
+ qcom,compute-cx-limit-en;
+ qcom,compute-priority-mode = <2>;
+ #cooling-cells = <2>;
+ };
+
+ msm_hvx_rm: qcom,msm_hvx_rm {
+ compatible = "qcom,msm-hvx-rm";
+ #cooling-cells = <2>;
+ };
+ };
+
+ qcom,cdsp_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_adsp>,
+ <&glink_slpi>,
+ <&glink_npu>;
+ };
+ };
+
+ glink_spss: spss {
+ qcom,remote-pid = <8>;
+ transport = "spss";
+ mboxes = <&sp_scsr 0>;
+ mbox-names = "spss_spss";
+ interrupt-parent = <&intsp>;
+ interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>;
+
+ reg = <0x1885008 0x8>,
+ <0x1885010 0x4>;
+ reg-names = "qcom,spss-addr",
+ "qcom,spss-size";
+
+ label = "spss";
+ qcom,glink-label = "spss";
+ };
+ };
+
+ qmp_aop: qcom,qmp-aop@c300000 {
+ compatible = "qcom,qmp-mbox";
+ mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "aop_qmp";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ reg = <0xc300000 0x1000>;
+ reg-names = "msgram";
+
+ label = "aop";
+ qcom,early-boot;
+ priority = <0>;
+ mbox-desc-offset = <0x0>;
+ #mbox-cells = <1>;
+ };
+
+ aop-msg-client {
+ compatible = "qcom,debugfs-qmp-client";
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "aop";
+ };
+
+ eud: qcom,msm-eud@ff0000 {
+ compatible = "qcom,msm-eud";
+ interrupt-names = "eud_irq";
+ interrupt-parent = <&pdc>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x088E0000 0x2000>,
+ <0x088E2000 0x1000>;
+ reg-names = "eud_base", "eud_mode_mgr2";
+ qcom,secure-eud-en;
+ qcom,eud-clock-vote-req;
+ clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_BCR>;
+ clock-names = "eud_ahb2phy_clk";
+ status = "ok";
+ };
+
+ qcom,lpass@17300000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x17300000 0x00100>;
+
+ vdd_cx-supply = <&L11A_LEVEL>;
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ vdd_mx-supply = <&L4A_LEVEL>;
+ qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ qcom,proxy-reg-names = "vdd_cx","vdd_mx";
+
+ clocks = <&clock_rpmh RPMH_CXO_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+
+ qcom,pas-id = <1>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <423>;
+ qcom,sysmon-id = <1>;
+ qcom,ssctl-instance-id = <0x14>;
+ qcom,firmware-name = "adsp";
+ memory-region = <&pil_adsp_mem>;
+ qcom,signal-aop;
+ qcom,complete-ramdump;
+
+ /* Inputs from lpass */
+ interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&adsp_smp2p_in 0 0>,
+ <&adsp_smp2p_in 2 0>,
+ <&adsp_smp2p_in 1 0>,
+ <&adsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack";
+
+ /* Outputs to lpass */
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "adsp-pil";
+ };
+
+ qcom,turing@8300000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x8300000 0x100000>;
+
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,proxy-reg-names = "vdd_cx";
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+
+ clocks = <&clock_rpmh RPMH_CXO_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+
+ qcom,pas-id = <18>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <601>;
+ qcom,sysmon-id = <7>;
+ qcom,ssctl-instance-id = <0x17>;
+ qcom,firmware-name = "cdsp";
+ memory-region = <&pil_cdsp_mem>;
+ qcom,signal-aop;
+ qcom,complete-ramdump;
+
+ qcom,msm-bus,name = "pil-cdsp";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <154 10070 0 0>,
+ <154 10070 0 1>;
+
+ /* Inputs from turing */
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
+ <&cdsp_smp2p_in 0 0>,
+ <&cdsp_smp2p_in 2 0>,
+ <&cdsp_smp2p_in 1 0>,
+ <&cdsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack";
+
+ /* Outputs to turing */
+ qcom,smem-states = <&cdsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "cdsp-pil";
+ };
+
+ qcom,venus@aab0000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0xaab0000 0x2000>;
+
+ vdd-supply = <&mvs0c_gdsc>;
+ qcom,proxy-reg-names = "vdd";
+ qcom,complete-ramdump;
+
+ clocks = <&clock_videocc VIDEO_CC_XO_CLK>,
+ <&clock_videocc VIDEO_CC_MVS0C_CLK>,
+ <&clock_videocc VIDEO_CC_AHB_CLK>;
+ clock-names = "xo", "core", "ahb";
+ qcom,proxy-clock-names = "xo", "core", "ahb";
+
+ qcom,core-freq = <200000000>;
+ qcom,ahb-freq = <200000000>;
+
+ qcom,pas-id = <9>;
+ qcom,msm-bus,name = "pil-venus";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <63 512 0 0>,
+ <63 512 0 304000>;
+ qcom,proxy-timeout-ms = <100>;
+ qcom,firmware-name = "venus";
+ memory-region = <&pil_video_mem>;
+ };
+
+ /* PIL spss node - for loading Secure Processor */
+ qcom,spss@1880000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x188101c 0x4>,
+ <0x1881024 0x4>,
+ <0x1881028 0x4>,
+ <0x188103c 0x4>,
+ <0x1882014 0x4>;
+ reg-names = "sp2soc_irq_status", "sp2soc_irq_clr",
+ "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2";
+ interrupts = <0 352 1>;
+
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,proxy-reg-names = "vdd_cx";
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ vdd_mx-uV = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+
+ clocks = <&clock_rpmh RPMH_CXO_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+ qcom,pil-generic-irq-handler;
+ status = "ok";
+
+ qcom,signal-aop;
+ qcom,complete-ramdump;
+
+ qcom,pas-id = <14>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,firmware-name = "spss";
+ memory-region = <&pil_spss_mem>;
+ qcom,spss-scsr-bits = <24 25>;
+ /* use extra size for IAR memory */
+ qcom,extra-size = <4096>;
+
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "spss-pil";
+ };
+
+ qcom,cvpss@abb0000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0xabb0000 0x2000>;
+ status = "ok";
+ qcom,pas-id = <26>;
+ qcom,firmware-name = "cvpss";
+
+ memory-region = <&pil_cvp_mem>;
+ };
+
+ qcom,npu@9800000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x9800000 0x800000>;
+
+ status = "ok";
+ qcom,pas-id = <23>;
+ qcom,firmware-name = "npu";
+ memory-region = <&pil_npu_mem>;
+
+ /* Outputs to npu */
+ qcom,smem-states = <&npu_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+ };
+
+ qcom,smp2p_sleepstate {
+ compatible = "qcom,smp2p-sleepstate";
+ qcom,smem-states = <&sleepstate_smp2p_out 0>;
+ interrupt-parent = <&sleepstate_smp2p_in>;
+ interrupts = <0 0>;
+ interrupt-names = "smp2p-sleepstate-in";
+ };
+
+ qcom,msm-cdsp-loader {
+ compatible = "qcom,cdsp-loader";
+ qcom,proc-img-to-load = "cdsp";
+ };
+
+ qcom,msm-adsprpc-mem {
+ compatible = "qcom,msm-adsprpc-mem-region";
+ memory-region = <&adsp_mem>;
+ restrict-access;
+ };
+
+ msm_fastrpc: qcom,msm_fastrpc {
+ compatible = "qcom,msm-fastrpc-compute";
+ qcom,adsp-remoteheap-vmid = <22 37>;
+ qcom,fastrpc-adsp-audio-pdr;
+ qcom,fastrpc-adsp-sensors-pdr;
+ qcom,rpc-latency-us = <235>;
+ qcom,qos-cores = <0 1 2 3>;
+
+ qcom,msm_fastrpc_compute_cb1 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1001 0x0460>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb2 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1002 0x0460>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb3 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1003 0x0460>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb4 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1004 0x0460>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb5 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1005 0x0460>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb6 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1006 0x0460>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb7 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1007 0x0460>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb8 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1008 0x0460>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb9 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ qcom,secure-context-bank;
+ iommus = <&apps_smmu 0x1009 0x0460>;
+ qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb10 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x1803 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb11 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x1804 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb12 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x1805 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb13 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "sdsprpc-smd";
+ iommus = <&apps_smmu 0x0541 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb14 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "sdsprpc-smd";
+ iommus = <&apps_smmu 0x0542 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb15 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "sdsprpc-smd";
+ iommus = <&apps_smmu 0x0543 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ shared-cb = <4>;
+ dma-coherent;
+ };
+ };
+
+ qcom_cedev: qcedev@1de0000 {
+ compatible = "qcom,qcedev";
+ reg = <0x1de0000 0x20000>,
+ <0x1dc4000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <3>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,ce-hw-shared;
+ qcom,bam-ee = <0>;
+ qcom,msm-bus,name = "qcedev-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <125 512 0 0>,
+ <125 512 393600 393600>;
+ qcom,smmu-s1-enable;
+ qcom,no-clock-support;
+ iommus = <&apps_smmu 0x0586 0x0011>,
+ <&apps_smmu 0x0596 0x0011>;
+ qcom,iommu-dma = "atomic";
+
+ qcom_cedev_ns_cb {
+ compatible = "qcom,qcedev,context-bank";
+ label = "ns_context";
+ iommus = <&apps_smmu 0x592 0>,
+ <&apps_smmu 0x598 0>,
+ <&apps_smmu 0x599 0>,
+ <&apps_smmu 0x59F 0>;
+ };
+
+ qcom_cedev_s_cb {
+ compatible = "qcom,qcedev,context-bank";
+ label = "secure_context";
+ iommus = <&apps_smmu 0x593 0>,
+ <&apps_smmu 0x59C 0>,
+ <&apps_smmu 0x59D 0>,
+ <&apps_smmu 0x59E 0>;
+ qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
+ qcom,secure-context-bank;
+ };
+ };
+
+ qcom_crypto: qcrypto@1de0000 {
+ compatible = "qcom,qcrypto";
+ reg = <0x1de0000 0x20000>,
+ <0x1dc4000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <2>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,bam-ee = <0>;
+ qcom,ce-hw-shared;
+ qcom,clk-mgmt-sus-res;
+ qcom,msm-bus,name = "qcrypto-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <125 512 0 0>,
+ <125 512 393600 393600>;
+ qcom,use-sw-aes-cbc-ecb-ctr-algo;
+ qcom,use-sw-aes-xts-algo;
+ qcom,use-sw-aes-ccm-algo;
+ qcom,use-sw-ahash-algo;
+ qcom,use-sw-aead-algo;
+ qcom,use-sw-hmac-algo;
+ qcom,smmu-s1-enable;
+ qcom,no-clock-support;
+ iommus = <&apps_smmu 0x0584 0x0011>,
+ <&apps_smmu 0x0594 0x0011>;
+ qcom,iommu-dma = "atomic";
+ };
+
+ qcom_msmhdcp: qcom,msm_hdcp {
+ compatible = "qcom,msm-hdcp";
+ };
+
+ mem_dump {
+ compatible = "qcom,mem-dump";
+ memory-region = <&dump_mem>;
+
+ c0_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x0>;
+ };
+
+ c100_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x1>;
+ };
+
+ c200_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x2>;
+ };
+
+ c300_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x3>;
+ };
+
+ c400_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x4>;
+ };
+
+ c500_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x5>;
+ };
+
+ c600_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x6>;
+ };
+
+ c700_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x7>;
+ };
+
+ c0_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x130>;
+ };
+
+ c100_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x131>;
+ };
+
+ c200_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x132>;
+ };
+
+ c300_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x133>;
+ };
+
+ c400_scandump {
+ qcom,dump-size = <0x1a4c0>;
+ qcom,dump-id = <0x134>;
+ };
+
+ c500_scandump {
+ qcom,dump-size = <0x1a4c0>;
+ qcom,dump-id = <0x135>;
+ };
+
+ c600_scandump {
+ qcom,dump-size = <0x1a4c0>;
+ qcom,dump-id = <0x136>;
+ };
+
+ c700_scandump {
+ qcom,dump-size = <0x1a4c0>;
+ qcom,dump-id = <0x137>;
+ };
+
+ cpuss_reg {
+ qcom,dump-size = <0x30000>;
+ qcom,dump-id = <0xef>;
+ };
+
+ l1_icache0 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x60>;
+ };
+
+ l1_icache100 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x61>;
+ };
+
+ l1_icache200 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x62>;
+ };
+
+ l1_icache300 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x63>;
+ };
+
+ l1_icache400 {
+ qcom,dump-size = <0x26000>;
+ qcom,dump-id = <0x64>;
+ };
+
+ l1_icache500 {
+ qcom,dump-size = <0x26000>;
+ qcom,dump-id = <0x65>;
+ };
+
+ l1_icache600 {
+ qcom,dump-size = <0x26000>;
+ qcom,dump-id = <0x66>;
+ };
+
+ l1_icache700 {
+ qcom,dump-size = <0x26000>;
+ qcom,dump-id = <0x67>;
+ };
+
+ l1_dcache0 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x80>;
+ };
+
+ l1_dcache100 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x81>;
+ };
+
+ l1_dcache200 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x82>;
+ };
+
+ l1_dcache300 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x83>;
+ };
+
+ l1_dcache400 {
+ qcom,dump-size = <0x1A000>;
+ qcom,dump-id = <0x84>;
+ };
+
+ l1_dcache500 {
+ qcom,dump-size = <0x1A000>;
+ qcom,dump-id = <0x85>;
+ };
+
+ l1_dcache600 {
+ qcom,dump-size = <0x1A000>;
+ qcom,dump-id = <0x86>;
+ };
+
+ l1_dcache700 {
+ qcom,dump-size = <0x1A000>;
+ qcom,dump-id = <0x87>;
+ };
+
+ l1_itlb400 {
+ qcom,dump-size = <0x300>;
+ qcom,dump-id = <0x24>;
+ };
+
+ l1_itlb500 {
+ qcom,dump-size = <0x300>;
+ qcom,dump-id = <0x25>;
+ };
+
+ l1_itlb600 {
+ qcom,dump-size = <0x300>;
+ qcom,dump-id = <0x26>;
+ };
+
+ l1_itlb700 {
+ qcom,dump-size = <0x300>;
+ qcom,dump-id = <0x27>;
+ };
+
+ l1_dtlb400 {
+ qcom,dump-size = <0x480>;
+ qcom,dump-id = <0x44>;
+ };
+
+ l1_dtlb500 {
+ qcom,dump-size = <0x480>;
+ qcom,dump-id = <0x45>;
+ };
+
+ l1_dtlb600 {
+ qcom,dump-size = <0x480>;
+ qcom,dump-id = <0x46>;
+ };
+
+ l1_dtlb700 {
+ qcom,dump-size = <0x480>;
+ qcom,dump-id = <0x47>;
+ };
+
+ l2_cache400 {
+ qcom,dump-size = <0x68000>;
+ qcom,dump-id = <0xc4>;
+ };
+
+ l2_cache500 {
+ qcom,dump-size = <0x68000>;
+ qcom,dump-id = <0xc5>;
+ };
+
+ l2_cache600 {
+ qcom,dump-size = <0x68000>;
+ qcom,dump-id = <0xc6>;
+ };
+
+ l2_cache700 {
+ qcom,dump-size = <0xD0000>;
+ qcom,dump-id = <0xc7>;
+ };
+
+ l2_tlb0 {
+ qcom,dump-size = <0x6000>;
+ qcom,dump-id = <0x120>;
+ };
+
+ l2_tlb100 {
+ qcom,dump-size = <0x6000>;
+ qcom,dump-id = <0x121>;
+ };
+
+ l2_tlb200 {
+ qcom,dump-size = <0x6000>;
+ qcom,dump-id = <0x122>;
+ };
+
+ l2_tlb300 {
+ qcom,dump-size = <0x6000>;
+ qcom,dump-id = <0x123>;
+ };
+
+ l2_tlb400 {
+ qcom,dump-size = <0x7800>;
+ qcom,dump-id = <0x124>;
+ };
+
+ l2_tlb500 {
+ qcom,dump-size = <0x7800>;
+ qcom,dump-id = <0x125>;
+ };
+
+ l2_tlb600 {
+ qcom,dump-size = <0x7800>;
+ qcom,dump-id = <0x126>;
+ };
+
+ l2_tlb700 {
+ qcom,dump-size = <0x7800>;
+ qcom,dump-id = <0x127>;
+ };
+
+ gemnoc {
+ qcom,dump-size = <0x100000>;
+ qcom,dump-id = <0x162>;
+ };
+
+ mhm_scan {
+ qcom,dump-size = <0x20000>;
+ qcom,dump-id = <0x161>;
+ };
+
+ rpmh {
+ qcom,dump-size = <0x2000000>;
+ qcom,dump-id = <0xec>;
+ };
+
+ rpm_sw {
+ qcom,dump-size = <0x28000>;
+ qcom,dump-id = <0xea>;
+ };
+
+ pmic {
+ qcom,dump-size = <0x80000>;
+ qcom,dump-id = <0xe4>;
+ };
+
+ fcm {
+ qcom,dump-size = <0x8400>;
+ qcom,dump-id = <0xee>;
+ };
+
+ etf_swao {
+ qcom,dump-size = <0x10000>;
+ qcom,dump-id = <0xf1>;
+ };
+
+ etr_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x100>;
+ };
+
+ etfswao_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x102>;
+ };
+
+ misc_data {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xe8>;
+ };
+
+ etf_slpi {
+ qcom,dump-size = <0x4000>;
+ qcom,dump-id = <0xf3>;
+ };
+
+ etfslpi_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x103>;
+ };
+
+ etf_lpass {
+ qcom,dump-size = <0x4000>;
+ qcom,dump-id = <0xf4>;
+ };
+
+ etflpass_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x104>;
+ };
+
+ osm_reg {
+ qcom,dump-size = <0x400>;
+ qcom,dump-id = <0x163>;
+ };
+
+ pcu_reg {
+ qcom,dump-size = <0x400>;
+ qcom,dump-id = <0x164>;
+ };
+
+ fsm_data {
+ qcom,dump-size = <0x400>;
+ qcom,dump-id = <0x165>;
+ };
+ };
+
+ qcom_tzlog: tz-log@146bf720 {
+ compatible = "qcom,tz-log";
+ reg = <0x146bf720 0x3000>;
+ qcom,hyplog-enabled;
+ hyplog-address-offset = <0x410>;
+ hyplog-size-offset = <0x414>;
+ };
+
+ qcom,ssc@5c00000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x5c00000 0x4000>;
+
+ vdd_cx-supply = <&L11A_LEVEL>;
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ vdd_mx-supply = <&L4A_LEVEL>;
+ qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ qcom,proxy-reg-names = "vdd_cx", "vdd_mx";
+
+ clocks = <&clock_rpmh RPMH_CXO_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+
+ qcom,pas-id = <12>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <424>;
+ qcom,sysmon-id = <3>;
+ qcom,ssctl-instance-id = <0x16>;
+ qcom,firmware-name = "slpi";
+ status = "ok";
+ memory-region = <&pil_slpi_mem>;
+ qcom,complete-ramdump;
+ qcom,signal-aop;
+
+ /* Inputs from ssc */
+ interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
+ <&dsps_smp2p_in 0 0>,
+ <&dsps_smp2p_in 2 0>,
+ <&dsps_smp2p_in 1 0>,
+ <&dsps_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack";
+
+ /* Outputs to ssc */
+ qcom,smem-states = <&dsps_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "slpi-pil";
+ };
+
+ ssc_sensors: qcom,msm-ssc-sensors {
+ compatible = "qcom,msm-ssc-sensors";
+ status = "ok";
+ qcom,firmware-name = "slpi";
+ };
+
+ qcom_smcinvoke: smcinvoke@87900000 {
+ compatible = "qcom,smcinvoke";
+ reg = <0x87900000 0x2200000>;
+ reg-names = "secapp-region";
+ };
+
+ tsens0: tsens@c222000 {
+ compatible = "qcom,tsens24xx";
+ reg = <0xc222000 0x4>,
+ <0xc263000 0x1ff>;
+ reg-names = "tsens_srot_physical",
+ "tsens_tm_physical";
+ interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tsens-upper-lower", "tsens-critical";
+ tsens-reinit-wa;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: tsens@c223000 {
+ compatible = "qcom,tsens24xx";
+ reg = <0xc223000 0x4>,
+ <0xc265000 0x1ff>;
+ reg-names = "tsens_srot_physical",
+ "tsens_tm_physical";
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tsens-upper-lower", "tsens-critical";
+ tsens-reinit-wa;
+ #thermal-sensor-cells = <1>;
+ };
+
+ qcom,msm-rtb {
+ compatible = "qcom,msm-rtb";
+ qcom,rtb-size = <0x100000>;
+ };
+
+ qcom,mpm2-sleep-counter@c221000 {
+ compatible = "qcom,mpm2-sleep-counter";
+ reg = <0xc221000 0x1000>;
+ clock-frequency = <32768>;
+ };
+
+ gpi_dma0: qcom,gpi-dma@900000 {
+ #dma-cells = <5>;
+ compatible = "qcom,gpi-dma";
+ reg = <0x900000 0x70000>;
+ reg-names = "gpi-top";
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,max-num-gpii = <15>;
+ qcom,gpii-mask = <0x7ff>;
+ qcom,ev-factor = <2>;
+ qcom,gpi-ee-offset = <0x1000>;
+ iommus = <&apps_smmu 0x5b6 0x0>;
+ qcom,smmu-cfg = <0x1>;
+ qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+ status = "ok";
+ };
+
+ gpi_dma1: qcom,gpi-dma@a00000 {
+ #dma-cells = <5>;
+ compatible = "qcom,gpi-dma";
+ reg = <0xa00000 0x70000>;
+ reg-names = "gpi-top";
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,max-num-gpii = <10>;
+ qcom,gpii-mask = <0x3f>;
+ qcom,ev-factor = <2>;
+ qcom,gpi-ee-offset = <0x6000>;
+ iommus = <&apps_smmu 0x56 0x0>;
+ qcom,smmu-cfg = <0x1>;
+ qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+ status = "ok";
+ };
+
+ gpi_dma2: qcom,gpi-dma@800000 {
+ #dma-cells = <5>;
+ compatible = "qcom,gpi-dma";
+ reg = <0x800000 0x70000>;
+ reg-names = "gpi-top";
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,max-num-gpii = <10>;
+ qcom,gpii-mask = <0x3f>;
+ qcom,ev-factor = <2>;
+ qcom,gpi-ee-offset = <0x6000>;
+ iommus = <&apps_smmu 0x76 0x0>;
+ qcom,smmu-cfg = <0x1>;
+ qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+ status = "ok";
+ };
+
+ wlan: qcom,cnss-qca6390@b0000000 {
+ compatible = "qcom,cnss-qca6390";
+ reg = <0xb0000000 0x10000>,
+ <0xb2e5510 0x5c0>;
+ reg-names = "smmu_iova_ipa", "tcs_cmd";
+ wlan-en-gpio = <&tlmm 20 0>;
+ qcom,bt-en-gpio = <&tlmm 21 0>;
+ qcom,sw-ctrl-gpio = <&tlmm 124 0>;
+ pinctrl-names = "wlan_en_active", "wlan_en_sleep";
+ pinctrl-0 = <&cnss_wlan_en_active>;
+ pinctrl-1 = <&cnss_wlan_en_sleep>;
+ qcom,wlan-rc-num = <0>;
+ qcom,wlan-ramdump-dynamic = <0x420000>;
+ qcom,smmu-s1-enable;
+ qcom,converged-dt;
+ cnss-daemon-support;
+ qcom,cmd_db_name = "smpf2";
+ qcom,set-wlaon-pwr-ctrl;
+ cnss-enable-self-recovery;
+
+ qcom,msm-bus,name = "msm-cnss";
+ qcom,msm-bus,num-cases = <7>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ /* no vote */
+ <MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 0 0>,
+ /* idle: 0-18 Mbps, ddr freq: 451.2 MHz */
+ <MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 2250 1600000>,
+ /* low: 18-60 Mbps, ddr freq: 451.2 MHz*/
+ <MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 7500 1600000>,
+ /* medium: 60-240 Mbps, ddr freq: 451.2 MHz */
+ <MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 30000 1804800>,
+ /* high: 240 - 800 Mbps, ddr freq: 451.2 MHz */
+ <MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 100000 1804800>,
+ /* very high: 800 - 1400 Mbps, ddr freq: 1555.2 MHz */
+ <MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 175000 6220800>,
+ /* low (latency critical): 18 - 60 Mbps, ddr freq: 547.2 MHz */
+ <MSM_BUS_MASTER_PCIE MSM_BUS_SLAVE_FIRST 7500 2188800>;
+
+ vdd-wlan-aon-supply = <&pm8150_s6>;
+ qcom,vdd-wlan-aon-config = <950000 950000 0 0 1>;
+ vdd-wlan-dig-supply = <&pm8009_s2>;
+ qcom,vdd-wlan-dig-config = <950000 952000 0 0 1>;
+ vdd-wlan-io-supply = <&pm8150_s4>;
+ qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
+ vdd-wlan-rfa1-supply = <&pm8150_s5>;
+ qcom,vdd-wlan-rfa1-config = <1900000 1900000 0 0 1>;
+ vdd-wlan-rfa2-supply = <&pm8150a_s8>;
+ qcom,vdd-wlan-rfa2-config = <1350000 1350000 0 0 1>;
+ wlan-ant-switch-supply = <&pm8150a_l5>;
+ qcom,wlan-ant-switch-config = <1800000 1800000 0 0 0>;
+
+ mhi,max-channels = <30>;
+ mhi,timeout = <10000>;
+ mhi,buffer-len = <0x8000>;
+ mhi,m2-no-db-access;
+
+ mhi_channels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mhi_chan@0 {
+ reg = <0>;
+ label = "LOOPBACK";
+ mhi,num-elements = <32>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x14>;
+ };
+
+ mhi_chan@1 {
+ reg = <1>;
+ label = "LOOPBACK";
+ mhi,num-elements = <32>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x14>;
+ };
+
+ mhi_chan@4 {
+ reg = <4>;
+ label = "DIAG";
+ mhi,num-elements = <32>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x14>;
+ };
+
+ mhi_chan@5 {
+ reg = <5>;
+ label = "DIAG";
+ mhi,num-elements = <32>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x14>;
+ };
+
+ mhi_chan@20 {
+ reg = <20>;
+ label = "IPCR";
+ mhi,num-elements = <32>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <1>;
+ mhi,data-type = <1>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x14>;
+ mhi,auto-start;
+ };
+
+ mhi_chan@21 {
+ reg = <21>;
+ label = "IPCR";
+ mhi,num-elements = <32>;
+ mhi,event-ring = <1>;
+ mhi,chan-dir = <2>;
+ mhi,data-type = <0>;
+ mhi,doorbell-mode = <2>;
+ mhi,ee = <0x14>;
+ mhi,auto-queue;
+ mhi,auto-start;
+ };
+ };
+
+ mhi_events {
+ mhi_event@0 {
+ mhi,num-elements = <32>;
+ mhi,intmod = <0>;
+ mhi,msi = <1>;
+ mhi,priority = <1>;
+ mhi,brstmode = <2>;
+ mhi,data-type = <1>;
+ };
+
+ mhi_event@1 {
+ mhi,num-elements = <256>;
+ mhi,intmod = <0>;
+ mhi,msi = <2>;
+ mhi,priority = <1>;
+ mhi,brstmode = <2>;
+ };
+
+ mhi_event@2 {
+ mhi,num-elements = <32>;
+ mhi,intmod = <1>;
+ mhi,msi = <0>;
+ mhi,priority = <2>;
+ mhi,brstmode = <2>;
+ mhi,data-type = <3>;
+ };
+ };
+
+ mhi_devices {
+ mhi_qrtr {
+ mhi,chan = "IPCR";
+ qcom,net-id = <0>;
+ qcom,low-latency;
+ mhi,early-notify;
+ };
+ };
+ };
+
+ wil6210: qcom,wil6210 {
+ compatible = "qcom,wil6210";
+ qcom,pcie-parent = <&pcie1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wil6210_refclk_en_pin>;
+ qcom,msm-bus,name = "wil6210";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <100 512 0 0>,
+ <100 512 600000 800000>, /* ~4.6Gbps (MCS12) */
+ <100 512 1300000 1300000>; /* ~10.1Gbps */
+ qcom,use-ext-supply;
+ vdd-ldo-supply = <&pm8150_l15>;
+ vddio-supply = <&pm8150_s5>;
+ qcom,use-ext-clocks;
+ clocks = <&clock_rpmh RPMH_RF_CLK1>;
+ clock-names = "rf_clk";
+ qcom,keep-radio-on-during-sleep;
+ qcom,use-ap-power-save;
+ status = "disabled";
+ };
+
+ tspp: msm_tspp@8880000 {
+ compatible = "qcom,msm_tspp";
+ reg = <0x088a7000 0x200>, /* MSM_TSIF0_PHYS */
+ <0x088a8000 0x200>, /* MSM_TSIF1_PHYS */
+ <0x088a9000 0x1000>, /* MSM_TSPP_PHYS */
+ <0x08884000 0x23000>; /* MSM_TSPP_BAM_PHYS */
+ reg-names = "MSM_TSIF0_PHYS",
+ "MSM_TSIF1_PHYS",
+ "MSM_TSPP_PHYS",
+ "MSM_TSPP_BAM_PHYS";
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,/*TSIF_TSPP_IRQ*/
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, /* TSIF0_IRQ */
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, /* TSIF1_IRQ */
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; /* TSIF_BAM_IRQ */
+ interrupt-names = "TSIF_TSPP_IRQ",
+ "TSIF0_IRQ",
+ "TSIF1_IRQ",
+ "TSIF_BAM_IRQ";
+
+ clock-names = "iface_clk", "ref_clk";
+ clocks = <&clock_gcc GCC_TSIF_AHB_CLK>,
+ <&clock_gcc GCC_TSIF_REF_CLK>;
+
+ qcom,msm-bus,name = "tsif";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <82 512 0 0>, /* No vote */
+ <82 512 12288 24576>;
+ /* Max. bandwidth, 2xTSIF, each max of 96Mbps */
+
+ pinctrl-names = "disabled",
+ "tsif0-mode1", "tsif0-mode2",
+ "tsif1-mode1", "tsif1-mode2",
+ "dual-tsif-mode1", "dual-tsif-mode2";
+
+ pinctrl-0 = <>; /* disabled */
+ pinctrl-1 = <&tsif0_signals_active>; /* tsif0-mode1 */
+ pinctrl-2 = <&tsif0_signals_active
+ &tsif0_sync_active>; /* tsif0-mode2 */
+ pinctrl-3 = <&tsif1_signals_active>; /* tsif1-mode1 */
+ pinctrl-4 = <&tsif1_signals_active
+ &tsif1_sync_active>; /* tsif1-mode2 */
+ pinctrl-5 = <&tsif0_signals_active
+ &tsif1_signals_active>; /* dual-tsif-mode1 */
+ pinctrl-6 = <&tsif0_signals_active
+ &tsif0_sync_active
+ &tsif1_signals_active
+ &tsif1_sync_active>; /* dual-tsif-mode2 */
+
+ memory-region = <&qseecom_mem>;
+ iommus = <&apps_smmu 0xA0 0x00>;
+ qcom,iommu-dma-addr-pool = <0x10000000 0x40000000>;
+ qcom,smmu-s1-enable;
+ };
+
+ demux {
+ compatible = "qcom,demux";
+ };
+
+ qfprom: qfprom@780000 {
+ compatible = "qcom,qfprom";
+ reg = <0x00780000 0x5000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ read-only;
+ ranges;
+
+ gpu_lm_efuse: gpu_lm_efuse@45c8 {
+ reg = <0x45c8 0x4>;
+ };
+
+ gpu_speed_bin: gpu_speed_bin@419b {
+ reg = <0x419b 0x1>;
+ bits = <5 3>;
+ };
+
+ thermal_speed_bin: thermal-speed-bin@1a2 {
+ reg = <0x1a2 0x1>;
+ bits = <7 1>;
+ };
+ };
+};
+
+#include "kona-regulators.dtsi"
+#include "kona-bus.dtsi"
+#include "kona-ion.dtsi"
+#include "kona-pcie.dtsi"
+#include "kona-mhi.dtsi"
+
+&pcie0_rp {
+ #address-cells = <5>;
+ #size-cells = <0>;
+
+ cnss_pci: cnss_pci {
+ reg = <0 0 0 0 0>;
+ qcom,iommu-group = <&cnss_pci_iommu_group>;
+ memory-region = <&cnss_wlan_mem>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cnss_pci_iommu_group: cnss_pci_iommu_group {
+ qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
+ qcom,iommu-dma = "fastmap";
+ qcom,iommu-pagetable = "coherent";
+ qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
+ "non-fatal";
+ };
+ };
+};
+
+&pcie1_rp {
+ #address-cells = <5>;
+ #size-cells = <0>;
+
+ wil6210_pci: wil6210_pci {
+ reg = <0 0 0 0 0>;
+ qcom,iommu-group = <&wil6210_pci_iommu_group>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ wil6210_pci_iommu_group: wil6210_pci_iommu_group {
+ reg = <0 0>;
+ qcom,iommu-dma-addr-pool = <0x60000000 0xa0000000>;
+ qcom,iommu-dma = "fastmap";
+ qcom,iommu-pagetable = "coherent";
+ };
+ };
+};
+
+#include "msm-arm-smmu-kona.dtsi"
+#include "kona-pinctrl.dtsi"
+#include "kona-smp2p.dtsi"
+#include "kona-usb.dtsi"
+#include "kona-coresight.dtsi"
+#include "kona-sde.dtsi"
+#include "kona-sde-pll.dtsi"
+#include "msm-rdbg.dtsi"
+
+#include "kona-pm.dtsi"
+#include "camera/kona-camera.dtsi"
+#include "kona-qupv3.dtsi"
+#include "kona-audio.dtsi"
+#include "kona-audio-ar.dtsi"
+#include "kona-thermal.dtsi"
+#include "kona-vidc.dtsi"
+#include "kona-cvp.dtsi"
+#include "kona-npu.dtsi"
+#include "kona-gpu.dtsi"
+#include "msm-qvr-external.dtsi"
+#include "ipcc-test.dtsi"
+
+&qupv3_se15_i2c {
+ status = "ok";
+ nq@64 {
+ compatible = "rtc6226";
+ reg = <0x64>;
+ fmint-gpio = <&tlmm 51 0>;
+ vdd-supply = <&pm8150a_bob>;
+ rtc6226,vdd-supply-voltage = <3296000 3296000>;
+ vio-supply = <&pm8150_s4>;
+ rtc6226,vio-supply-voltage = <1800000 1800000 >;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-atp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon-atp-overlay.dts
new file mode 100755
index 0000000..f12a2d5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-atp-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lagoon-atp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lagoon ATP";
+ compatible = "qcom,lagoon-atp", "qcom,lagoon", "qcom,atp";
+ qcom,msm-id = <434 0x10000>, <459 0x10000>;
+ qcom,board-id = <33 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-atp.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon-atp.dts
new file mode 100755
index 0000000..6dfe8f3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-atp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "lagoon.dtsi"
+#include "lagoon-atp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lagoon ATP";
+ compatible = "qcom,lagoon-atp", "qcom,lagoon", "qcom,atp";
+ qcom,board-id = <33 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-atp.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-atp.dtsi
new file mode 100755
index 0000000..ad03c03
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-atp.dtsi
@@ -0,0 +1,261 @@
+#include "lagoon-audio-overlay.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include "lagoon-sde-display.dtsi"
+#include "lagoon-thermal-overlay.dtsi"
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+};
+
+&pm6350_gpios {
+ key_vol_up {
+ key_vol_up_default: key_vol_up_default {
+ pins = "gpio2";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+ };
+};
+
+&qupv3_se10_i2c {
+ status = "disabled";
+};
+
+&pm8008_8 {
+ status = "disabled";
+};
+
+&pm8008_9 {
+ status = "disabled";
+};
+
+&pm6150a_amoled {
+ status = "ok";
+};
+
+&pm7250b_charger {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+ <&pm7250b_vadc ADC_USB_IN_I>,
+ <&pm7250b_vadc ADC_CHG_TEMP>,
+ <&pm7250b_vadc ADC_DIE_TEMP>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+ <&pm7250b_vadc ADC_SBUx>,
+ <&pm7250b_vadc ADC_VPH_PWR>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp",
+ "die_temp",
+ "conn_temp",
+ "sbux_res",
+ "vph_voltage";
+ qcom,batteryless-platform;
+ qcom,sec-charger-config = <0>;
+ qcom,auto-recharge-soc = <98>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ qcom,suspend-input-on-debug-batt;
+};
+
+&pm7250b_qg {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU2>,
+ <&pm7250b_vadc ADC_BAT_ID_PU2>;
+ io-channel-names = "batt-therm",
+ "batt-id";
+ qcom,qg-iterm-ma = <150>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v3";
+
+ vdda-phy-supply = <&L18A>;
+ vdda-pll-supply = <&L22A>;
+ vdda-phy-max-microamp = <62900>;
+ vdda-pll-max-microamp = <18300>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&L7E>;
+ vcc-voltage-level = <2950000 2960000>;
+ vccq2-supply = <&L12A>;
+ vccq2-voltage-level = <1800000 1800000>;
+ vcc-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+ vccq2-pwr-collapse-sup;
+
+ qcom,vddp-ref-clk-supply = <&L22A>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vddp-ref-clk-min-uV = <1152000>;
+ qcom,vddp-ref-clk-max-uV = <1200000>;
+ status = "ok";
+};
+
+&sdhc_1 {
+ vdd-supply = <&L7E>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L12A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&L9E>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L6E>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&dsi_rm69299_visionox_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_rm69299_visionox_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>;
+};
+
+&qupv3_se0_i2c {
+ status = "ok";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 9 0x00>;
+ qcom,nq-ven = <&tlmm 6 0x00>;
+ qcom,nq-firm = <&tlmm 8 0x00>;
+ qcom,nq-clkreq = <&tlmm 7 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&qupv3_se8_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="synaptics,tcm-i2c";
+
+ synaptics_tcm@20 {
+ compatible = "synaptics,tcm-i2c";
+ reg = <0x20>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <22 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&pmx_ts_release>;
+ vdd-supply = <&L11A>;
+ avdd-supply = <&L6A>;
+ synaptics,pwr-reg-name = "avdd";
+ synaptics,bus-reg-name = "vdd";
+ synaptics,irq-gpio = <&tlmm 22 0x2008>;
+ synaptics,irq-on-state = <0>;
+ synaptics,reset-gpio = <&tlmm 21 0x00>;
+ synaptics,reset-on-state = <0>;
+ synaptics,reset-active-ms = <20>;
+ synaptics,reset-delay-ms = <200>;
+ synaptics,power-delay-ms = <200>;
+ synaptics,ubl-i2c-addr = <0x20>;
+ synaptics,extend_report;
+ synaptics,firmware-name = "synaptics_firmware.img";
+
+ panel = <&dsi_rm69299_visionox_amoled_video
+ &dsi_rm69299_visionox_amoled_cmd>;
+ };
+};
+
+&sde_dp {
+ status = "disabled";
+};
+
+&mdss_dp_pll {
+ status = "disabled";
+};
+
+&mdss_mdp {
+ connectors = <&sde_wb &sde_dsi &sde_rscc>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-audio-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-audio-overlay.dtsi
new file mode 100755
index 0000000..b232a58
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-audio-overlay.dtsi
@@ -0,0 +1,546 @@
+#include <dt-bindings/clock/qcom,audio-ext-clk.h>
+#include <dt-bindings/sound/qcom,bolero-clk-rsc.h>
+#include <dt-bindings/sound/audio-codec-port-types.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lagoon-lpi.dtsi"
+
+&bolero {
+ qcom,num-macros = <4>;
+ bolero-clk-rsc-mngr {
+ compatible = "qcom,bolero-clk-rsc-mngr";
+ qcom,fs-gen-sequence = <0x3000 0x1>,
+ <0x3004 0x1>, <0x3080 0x2>;
+ qcom,rx_mclk_mode_muxsel = <0x033240D8>;
+ qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
+ qcom,va_mclk_mode_muxsel = <0x033A0000>;
+ clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
+ "wsa_core_clk", "wsa_npl_clk", "va_core_clk", "va_npl_clk";
+ clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
+ <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
+ <&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
+ <&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
+ };
+
+ tx_macro: tx-macro@3220000 {
+ compatible = "qcom,tx-macro";
+ reg = <0x3220000 0x0>;
+ clock-names = "tx_core_clk", "tx_npl_clk";
+ clocks = <&clock_audio_tx_1 0>,
+ <&clock_audio_tx_2 0>;
+ qcom,tx-swr-gpios = <&tx_swr_gpios>;
+ qcom,tx-dmic-sample-rate = <2400000>;
+ swr2: tx_swr_master {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ qcom,swr-master-version = <0x01050001>;
+ qcom,swr_master_id = <3>;
+ qcom,mipi-sdw-block-packing-mode = <1>;
+ swrm-io-base = <0x3230000 0x0>;
+ interrupts-extended =
+ <&intc GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 144 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq", "swr_wake_irq";
+ qcom,swr-wakeup-required = <1>;
+ qcom,swr-num-ports = <5>;
+ qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,
+ <2 ADC1 0x1>, <2 ADC2 0x2>,
+ <3 ADC3 0x1>, <3 ADC4 0x2>,
+ <4 DMIC0 0x1>, <4 DMIC1 0x2>,
+ <4 DMIC2 0x4>, <4 DMIC3 0x8>,
+ <5 DMIC4 0x1>, <5 DMIC5 0x2>,
+ <5 DMIC6 0x4>, <5 DMIC7 0x8>;
+ qcom,swr-num-dev = <1>;
+ qcom,swr-clock-stop-mode0 = <1>;
+ qcom,swr-mstr-irq-wakeup-capable = <1>;
+ wcd938x_tx_slave: wcd938x-tx-slave {
+ compatible = "qcom,wcd938x-slave";
+ reg = <0x0D 0x01170223>;
+ };
+ wcd937x_tx_slave: wcd937x-tx-slave {
+ status = "disabled";
+ compatible = "qcom,wcd937x-slave";
+ reg = <0x0A 0x01170223>;
+ };
+ };
+ };
+
+ rx_macro: rx-macro@3200000 {
+ compatible = "qcom,rx-macro";
+ reg = <0x3200000 0x0>;
+ clock-names = "rx_core_clk", "rx_npl_clk";
+ clocks = <&clock_audio_rx_1 0>,
+ <&clock_audio_rx_2 0>;
+ qcom,rx-swr-gpios = <&rx_swr_gpios>;
+ qcom,rx_mclk_mode_muxsel = <0x033240D8>;
+ qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x02 0x1E>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ swr1: rx_swr_master {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ qcom,swr-master-version = <0x01050001>;
+ qcom,swr_master_id = <2>;
+ qcom,mipi-sdw-block-packing-mode = <1>;
+ swrm-io-base = <0x3210000 0x0>;
+ interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq";
+ qcom,swr-num-ports = <5>;
+ qcom,disable-div2-clk-switch = <1>;
+ qcom,swr-port-mapping = <1 HPH_L 0x1>,
+ <1 HPH_R 0x2>, <2 CLSH 0x1>,
+ <3 COMP_L 0x1>, <3 COMP_R 0x2>,
+ <4 LO 0x1>, <5 DSD_L 0x1>,
+ <5 DSD_R 0x2>;
+ qcom,swr-num-dev = <1>;
+ qcom,swr-clock-stop-mode0 = <1>;
+ wcd938x_rx_slave: wcd938x-rx-slave {
+ compatible = "qcom,wcd938x-slave";
+ reg = <0x0D 0x01170224>;
+ };
+ wcd937x_rx_slave: wcd937x_rx_slave {
+ status = "disabled";
+ compatible = "qcom,wcd937x-slave";
+ reg = <0x0A 0x01170224>;
+ };
+ };
+ };
+
+ wsa_macro: wsa-macro@3240000 {
+ compatible = "qcom,wsa-macro";
+ reg = <0x3240000 0x0>;
+ clock-names = "wsa_core_clk", "wsa_npl_clk";
+ clocks = <&clock_audio_wsa_1 0>,
+ <&clock_audio_wsa_2 0>;
+ qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
+ qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x02 0x1E>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ swr0: wsa_swr_master {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ qcom,swr-master-version = <0x01050001>;
+ qcom,swr_master_id = <1>;
+ qcom,mipi-sdw-block-packing-mode = <0>;
+ swrm-io-base = <0x3250000 0x0>;
+ interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq";
+ qcom,swr-num-ports = <8>;
+ qcom,swr-port-mapping = <1 SPKR_L 0x1>,
+ <2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
+ <4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
+ <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
+ <8 SPKR_R_VI 0x3>;
+ qcom,swr-num-dev = <2>;
+ wsa883x_0221: wsa883x@02170221 {
+ compatible = "qcom,wsa883x";
+ reg = <0x02 0x02170221>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+ qcom,bolero-handle = <&bolero>;
+
+ cdc-vdd-1p8-supply = <&L11A>;
+ qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-1p8-current = <20000>;
+ qcom,cdc-vdd-1p8-lpm-supported = <1>;
+ qcom,cdc-static-supplies = "cdc-vdd-1p8";
+ };
+
+ wsa883x_0222: wsa883x@02170222 {
+ compatible = "qcom,wsa883x";
+ reg = <0x02 0x02170222>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero>;
+
+ cdc-vdd-1p8-supply = <&L11A>;
+ qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-1p8-current = <20000>;
+ qcom,cdc-vdd-1p8-lpm-supported = <1>;
+ qcom,cdc-static-supplies = "cdc-vdd-1p8";
+ };
+ };
+
+ };
+
+ va_macro: va-macro@3370000 {
+ compatible = "qcom,va-macro";
+ reg = <0x3370000 0x0>;
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+ qcom,va-dmic-sample-rate = <600000>;
+ qcom,va-clk-mux-select = <1>;
+ qcom,va-island-mode-muxsel = <0x033A0000>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ };
+
+ wcd938x_codec: wcd938x-codec {
+ compatible = "qcom,wcd938x-codec";
+ qcom,split-codec = <1>;
+ qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
+ <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
+ <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
+ <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
+ <4 DSD_R 0x2 0 DSD_R>;
+ qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
+ <0 ADC2 0x2 0 ADC2>, <1 ADC3 0x1 0 ADC3>,
+ <1 ADC4 0x2 0 ADC4>, <2 DMIC0 0x1 0 DMIC0>,
+ <2 DMIC1 0x2 0 DMIC1>, <2 MBHC 0x4 0 DMIC2>,
+ <2 DMIC2 0x4 0 DMIC2>, <2 DMIC3 0x8 0 DMIC3>,
+ <3 DMIC4 0x1 0 DMIC4>, <3 DMIC5 0x2 0 DMIC5>,
+ <3 DMIC6 0x4 0 DMIC6>, <3 DMIC7 0x8 0 DMIC7>;
+
+ qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
+ qcom,rx-slave = <&wcd938x_rx_slave>;
+ qcom,tx-slave = <&wcd938x_tx_slave>;
+
+ cdc-vdd-rxtx-supply = <&L11A>;
+ qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-rxtx-current = <30000>;
+ qcom,cdc-vdd-rxtx-lpm-supported = <1>;
+
+ cdc-vddio-supply = <&L11A>;
+ qcom,cdc-vddio-voltage = <1800000 1800000>;
+ qcom,cdc-vddio-current = <30000>;
+ qcom,cdc-vddio-lpm-supported = <1>;
+
+ cdc-vdd-buck-supply = <&L14A>;
+ qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-buck-current = <650000>;
+
+ cdc-vdd-mic-bias-supply = <&BOB>;
+ qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
+ qcom,cdc-vdd-mic-bias-current = <30000>;
+
+ qcom,cdc-micbias1-mv = <2700>;
+ qcom,cdc-micbias2-mv = <2700>;
+ qcom,cdc-micbias3-mv = <2700>;
+ qcom,cdc-micbias4-mv = <2700>;
+
+ qcom,cdc-static-supplies = "cdc-vdd-rxtx",
+ "cdc-vddio",
+ "cdc-vdd-mic-bias";
+ qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
+ };
+
+ wcd937x_codec: wcd937x-codec {
+ status = "disabled";
+ compatible = "qcom,wcd937x-codec";
+ qcom,split-codec = <1>;
+ qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
+ <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
+ <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
+ <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
+ <4 DSD_R 0x2 0 DSD_R>;
+ qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
+ <1 ADC2 0x1 0 ADC3>, <1 ADC3 0x2 0 ADC4>,
+ <2 DMIC0 0x1 0 DMIC0>, <2 DMIC1 0x2 0 DMIC1>,
+ <2 MBHC 0x4 0 DMIC2>, <3 DMIC2 0x1 0 DMIC4>,
+ <3 DMIC3 0x2 0 DMIC5>, <3 DMIC4 0x4 0 DMIC6>,
+ <3 DMIC5 0x8 0 DMIC7>;
+
+ qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
+ qcom,rx-slave = <&wcd937x_rx_slave>;
+ qcom,tx-slave = <&wcd937x_tx_slave>;
+
+ cdc-vdd-rxtx-supply = <&L11A>;
+ qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-rxtx-current = <30000>;
+
+ cdc-vddio-supply = <&L11A>;
+ qcom,cdc-vddio-voltage = <1800000 1800000>;
+ qcom,cdc-vddio-current = <30000>;
+
+ cdc-vdd-buck-supply = <&L14A>;
+ qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-buck-current = <650000>;
+
+ cdc-vdd-mic-bias-supply = <&BOB>;
+ qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
+ qcom,cdc-vdd-mic-bias-current = <30000>;
+
+ qcom,cdc-micbias1-mv = <1800>;
+ qcom,cdc-micbias2-mv = <1800>;
+ qcom,cdc-micbias3-mv = <1800>;
+ qcom,cdc-micbias4-mv = <1800>;
+
+ qcom,cdc-static-supplies = "cdc-vdd-rxtx",
+ "cdc-vddio",
+ "cdc-vdd-mic-bias";
+ qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
+ };
+
+};
+
+&lagoon_snd {
+ qcom,model = "lito-lagoonmtp-snd-card";
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
+ qcom,wcn-btfm = <1>;
+ qcom,ext-disp-audio-rx = <1>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic4",
+ "AMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Analog Mic5",
+ "TX DMIC0", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic0",
+ "TX DMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic1",
+ "TX DMIC2", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic2",
+ "TX DMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic3",
+ "TX DMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "TX DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS1", "Digital Mic0",
+ "VA MIC BIAS1", "Digital Mic1",
+ "VA MIC BIAS3", "Digital Mic2",
+ "VA MIC BIAS3", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic4",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS1",
+ "VA DMIC1", "VA MIC BIAS1",
+ "VA DMIC2", "VA MIC BIAS3",
+ "VA DMIC3", "VA MIC BIAS3",
+ "VA DMIC4", "VA MIC BIAS4",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC0", "VA_SWR_CLK",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_ADC2", "VA_SWR_CLK",
+ "VA SWR_ADC3", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_ADC0", "ADC1_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT",
+ "VA SWR_ADC2", "ADC3_OUTPUT",
+ "VA SWR_ADC3", "ADC4_OUTPUT",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
+ qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
+ qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
+ asoc-codec = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
+ "msm-ext-disp-audio-codec-rx";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa883x_0221>, <&wsa883x_0222>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight";
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&wcd938x_codec>;
+ qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>;
+ qcom,cps_wsa_vbatt_temp_reg_addr = <0x0003429 0x0003422>;
+ qcom,cps_threshold_levels = <148 168>;
+ qcom,cps_normal_values = <0x8E 0x8F 0x8F>;
+ qcom,cps_lower1_values = <0x10 0xD0 0xD0>;
+ qcom,cps_lower2_values = <0x0F 0x0F 0x18>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>,
+ <&lpi_tlmm>, <&bolero>;
+};
+
+&q6core {
+ cdc_dmic01_gpios: cdc_dmic01_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
+ pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
+ qcom,lpi-gpios;
+ qcom,tlmm-gpio = <133 134>;
+ };
+
+ cdc_dmic23_gpios: cdc_dmic23_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
+ pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
+ qcom,lpi-gpios;
+ qcom,tlmm-gpio = <136>;
+ };
+
+ cdc_dmic45_gpios: cdc_dmic45_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
+ pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
+ qcom,lpi-gpios;
+ qcom,tlmm-gpio = <139 140>;
+ };
+
+ wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
+ pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ rx_swr_gpios: rx_swr_clk_data_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
+ &rx_swr_data1_active>;
+ pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
+ &rx_swr_data1_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ tx_swr_gpios: tx_swr_clk_data_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active
+ &tx_swr_data2_active &tx_swr_data3_active>;
+ pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep
+ &tx_swr_data2_sleep &tx_swr_data3_sleep>;
+ qcom,lpi-gpios;
+ qcom,tlmm-gpio = <128 129>;
+ };
+};
+
+&soc {
+ wsa_spkr_en1: wsa_spkr_en1_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ pinctrl-1 = <&spkr_1_sd_n_sleep>;
+ };
+
+ wsa_spkr_en2: wsa_spkr_en2_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&spkr_2_sd_n_active>;
+ pinctrl-1 = <&spkr_2_sd_n_sleep>;
+ };
+
+ wcd938x_rst_gpio: msm_cdc_pinctrl@83 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wcd938x_reset_active>;
+ pinctrl-1 = <&wcd938x_reset_sleep>;
+ };
+
+ clock_audio_wsa_1: wsa_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x309>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_wsa_2: wsa_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_3>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30A>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_rx_1: rx_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
+ qcom,codec-lpass-ext-clk-freq = <22579200>;
+ qcom,codec-lpass-clk-id = <0x30E>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_rx_2: rx_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>;
+ qcom,codec-lpass-ext-clk-freq = <22579200>;
+ qcom,codec-lpass-clk-id = <0x30F>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_tx_1: tx_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30C>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_tx_2: tx_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30D>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_va_1: va_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30B>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_va_2: va_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_8>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x310>;
+ #clock-cells = <1>;
+ };
+};
+
+&va_cdc_dma_0_tx {
+ qcom,msm-dai-is-island-supported = <1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-audio.dtsi
new file mode 100755
index 0000000..7402fb5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-audio.dtsi
@@ -0,0 +1,177 @@
+#include <dt-bindings/clock/qcom,audio-ext-clk.h>
+#include "msm-audio-lpass.dtsi"
+
+&msm_audio_ion {
+ iommus = <&apps_smmu 0x1001 0x0>;
+ qcom,smmu-sid-mask = /bits/ 64 <0xf>;
+};
+
+&soc {
+ qcom,avtimer@39ef000 {
+ compatible = "qcom,avtimer";
+ reg = <0x039f000c 0x4>,
+ <0x039f0010 0x4>;
+ reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
+ qcom,clk-div = <192>;
+ qcom,clk-mult = <10>;
+ };
+};
+
+&audio_apr {
+ q6core: qcom,q6core-audio {
+ compatible = "qcom,q6core-audio";
+
+ lpass_core_hw_vote: vote_lpass_core_hw {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_CORE_HW_VOTE>;
+ #clock-cells = <1>;
+ };
+
+ lpass_audio_hw_vote: vote_lpass_audio_hw {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_AUDIO_HW_VOTE>;
+ #clock-cells = <1>;
+ };
+
+ bolero: bolero-cdc {
+ compatible = "qcom,bolero-codec";
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ bolero-clk-rsc-mngr {
+ compatible = "qcom,bolero-clk-rsc-mngr";
+ };
+
+ tx_macro: tx-macro@3220000 {
+ swr2: tx_swr_master {
+ };
+ };
+
+ rx_macro: rx-macro@3200000 {
+ swr1: rx_swr_master {
+ };
+ };
+
+ wsa_macro: wsa-macro@3240000 {
+ swr0: wsa_swr_master {
+ };
+ };
+ };
+ };
+};
+
+&q6core {
+ lagoon_snd: sound {
+ compatible = "qcom,kona-asoc-snd";
+ qcom,mi2s-audio-intf = <1>;
+ qcom,auxpcm-audio-intf = <1>;
+ qcom,wcn-btfm = <1>;
+ qcom,ext-disp-audio-rx = <0>;
+ qcom,afe-rxtx-lb = <0>;
+
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+
+ asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
+ <&loopback>, <&compress>, <&hostless>,
+ <&afe>, <&lsm>, <&routing>, <&compr>,
+ <&pcm_noirq>;
+ asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
+ "msm-pcm-dsp.2", "msm-voip-dsp",
+ "msm-pcm-voice", "msm-pcm-loopback",
+ "msm-compress-dsp", "msm-pcm-hostless",
+ "msm-pcm-afe", "msm-lsm-client",
+ "msm-pcm-routing", "msm-compr-dsp",
+ "msm-pcm-dsp-noirq";
+ asoc-cpu = <&dai_dp>, <&dai_dp1>,
+ <&dai_mi2s0>, <&dai_mi2s1>,
+ <&dai_mi2s2>, <&dai_mi2s3>,
+ <&dai_mi2s4>, <&dai_mi2s5>, <&dai_pri_auxpcm>,
+ <&dai_sec_auxpcm>, <&dai_tert_auxpcm>,
+ <&dai_quat_auxpcm>, <&dai_quin_auxpcm>,
+ <&dai_sen_auxpcm>,
+ <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>,
+ <&afe_proxy_tx>, <&incall_record_rx>,
+ <&incall_record_tx>, <&incall_music_rx>,
+ <&incall_music_2_rx>,
+ <&proxy_rx>, <&proxy_tx>,
+ <&usb_audio_rx>, <&usb_audio_tx>,
+ <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>,
+ <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>,
+ <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>,
+ <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>,
+ <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>,
+ <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>,
+ <&dai_sen_tdm_rx_0>, <&dai_sen_tdm_tx_0>,
+ <&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>,
+ <&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>,
+ <&wsa_cdc_dma_2_tx>,
+ <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>,
+ <&va_cdc_dma_2_tx>,
+ <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>,
+ <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>,
+ <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>,
+ <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>,
+ <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>,
+ <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>,
+ <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>,
+ <&afe_loopback_tx>;
+ asoc-cpu-names = "msm-dai-q6-dp.0", "msm-dai-q6-dp.1",
+ "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",
+ "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",
+ "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5",
+ "msm-dai-q6-auxpcm.1",
+ "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3",
+ "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5",
+ "msm-dai-q6-auxpcm.6", "msm-dai-q6-dev.224",
+ "msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
+ "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
+ "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
+ "msm-dai-q6-dev.32770",
+ "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195",
+ "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673",
+ "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399",
+ "msm-dai-q6-dev.16401",
+ "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865",
+ "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881",
+ "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897",
+ "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913",
+ "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929",
+ "msm-dai-q6-tdm.36944", "msm-dai-q6-tdm.36945",
+ "msm-dai-cdc-dma-dev.45056",
+ "msm-dai-cdc-dma-dev.45057",
+ "msm-dai-cdc-dma-dev.45058",
+ "msm-dai-cdc-dma-dev.45059",
+ "msm-dai-cdc-dma-dev.45061",
+ "msm-dai-cdc-dma-dev.45089",
+ "msm-dai-cdc-dma-dev.45091",
+ "msm-dai-cdc-dma-dev.45093",
+ "msm-dai-cdc-dma-dev.45104",
+ "msm-dai-cdc-dma-dev.45105",
+ "msm-dai-cdc-dma-dev.45106",
+ "msm-dai-cdc-dma-dev.45107",
+ "msm-dai-cdc-dma-dev.45108",
+ "msm-dai-cdc-dma-dev.45109",
+ "msm-dai-cdc-dma-dev.45110",
+ "msm-dai-cdc-dma-dev.45111",
+ "msm-dai-cdc-dma-dev.45112",
+ "msm-dai-cdc-dma-dev.45113",
+ "msm-dai-cdc-dma-dev.45114",
+ "msm-dai-cdc-dma-dev.45115",
+ "msm-dai-cdc-dma-dev.45116",
+ "msm-dai-cdc-dma-dev.45118",
+ "msm-dai-q6-dev.24577";
+ fsa4480-i2c-handle = <&fsa4480>;
+ };
+};
+
+&qupv3_se10_i2c {
+ status = "ok";
+ fsa4480: fsa4480@42 {
+ compatible = "qcom,fsa4480-i2c";
+ reg = <0x42>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fsa_usbc_ana_en>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-bus.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-bus.dtsi
new file mode 100755
index 0000000..8a7fb87
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-bus.dtsi
@@ -0,0 +1,1880 @@
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ ad_hoc_bus: ad-hoc-bus {
+ compatible = "qcom,msm-bus-device";
+ reg = <0x16E0000 0x15080>,
+ <0x1700000 0x1F880>,
+ <0x1500000 0x28000>,
+ <0x9160000 0x03200>,
+ <0x9680000 0x3E200>,
+ <0x1740000 0x1C100>,
+ <0x1620000 0x17080>,
+ <0x1700000 0x1F880>,
+ <0x9990000 0x1600>,
+ <0x1620000 0x4000>;
+
+ reg-names = "aggre1_noc-base", "aggre2_noc-base",
+ "config_noc-base", "dc_noc-base",
+ "gem_noc-base", "mmss_noc-base",
+ "system_noc-base", "compute_noc-base",
+ "npu_noc-base", "clk_virt-base";
+
+ /*RSCs*/
+ rsc_apps: rsc-apps {
+ cell-id = <MSM_BUS_RSC_APPS>;
+ label = "apps_rsc";
+ qcom,rsc-dev;
+ qcom,req_state = <2>;
+ };
+
+ rsc_disp: rsc-disp {
+ cell-id = <MSM_BUS_RSC_DISP>;
+ label = "disp_rsc";
+ qcom,rsc-dev;
+ qcom,req_state = <2>;
+ };
+
+ /*BCMs*/
+ bcm_acv: bcm-acv {
+ cell-id = <MSM_BUS_BCM_ACV>;
+ label = "ACV";
+ qcom,bcm-name = "ACV";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_alc: bcm-alc {
+ cell-id = <MSM_BUS_BCM_ALC>;
+ label = "ALC";
+ qcom,bcm-name = "ALC";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_ce0: bcm-ce0 {
+ cell-id = <MSM_BUS_BCM_CE0>;
+ label = "CE0";
+ qcom,bcm-name = "CE0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_cn0: bcm-cn0 {
+ cell-id = <MSM_BUS_BCM_CN0>;
+ label = "CN0";
+ qcom,bcm-name = "CN0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_cn1: bcm-cn1 {
+ cell-id = <MSM_BUS_BCM_CN1>;
+ label = "CN1";
+ qcom,bcm-name = "CN1";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_co0: bcm-co0 {
+ cell-id = <MSM_BUS_BCM_CO0>;
+ label = "CO0";
+ qcom,bcm-name = "CO0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_co2: bcm-co2 {
+ cell-id = <MSM_BUS_BCM_CO2>;
+ label = "CO2";
+ qcom,bcm-name = "CO2";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_co3: bcm-co3 {
+ cell-id = <MSM_BUS_BCM_CO3>;
+ label = "CO3";
+ qcom,bcm-name = "CO3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_ip0: bcm-ip0 {
+ cell-id = <MSM_BUS_BCM_IP0>;
+ label = "IP0";
+ qcom,bcm-name = "IP0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mc0: bcm-mc0 {
+ cell-id = <MSM_BUS_BCM_MC0>;
+ label = "MC0";
+ qcom,bcm-name = "MC0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm0: bcm-mm0 {
+ cell-id = <MSM_BUS_BCM_MM0>;
+ label = "MM0";
+ qcom,bcm-name = "MM0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm1: bcm-mm1 {
+ cell-id = <MSM_BUS_BCM_MM1>;
+ label = "MM1";
+ qcom,bcm-name = "MM1";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm2: bcm-mm2 {
+ cell-id = <MSM_BUS_BCM_MM2>;
+ label = "MM2";
+ qcom,bcm-name = "MM2";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm3: bcm-mm3 {
+ cell-id = <MSM_BUS_BCM_MM3>;
+ label = "MM3";
+ qcom,bcm-name = "MM3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_qup0: bcm-qup0 {
+ cell-id = <MSM_BUS_BCM_QUP0>;
+ label = "QUP0";
+ qcom,bcm-name = "QUP0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh0: bcm-sh0 {
+ cell-id = <MSM_BUS_BCM_SH0>;
+ label = "SH0";
+ qcom,bcm-name = "SH0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh2: bcm-sh2 {
+ cell-id = <MSM_BUS_BCM_SH2>;
+ label = "SH2";
+ qcom,bcm-name = "SH2";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh3: bcm-sh3 {
+ cell-id = <MSM_BUS_BCM_SH3>;
+ label = "SH3";
+ qcom,bcm-name = "SH3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh4: bcm-sh4 {
+ cell-id = <MSM_BUS_BCM_SH4>;
+ label = "SH4";
+ qcom,bcm-name = "SH4";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn0: bcm-sn0 {
+ cell-id = <MSM_BUS_BCM_SN0>;
+ label = "SN0";
+ qcom,bcm-name = "SN0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn1: bcm-sn1 {
+ cell-id = <MSM_BUS_BCM_SN1>;
+ label = "SN1";
+ qcom,bcm-name = "SN1";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn2: bcm-sn2 {
+ cell-id = <MSM_BUS_BCM_SN2>;
+ label = "SN2";
+ qcom,bcm-name = "SN2";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn3: bcm-sn3 {
+ cell-id = <MSM_BUS_BCM_SN3>;
+ label = "SN3";
+ qcom,bcm-name = "SN3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn4: bcm-sn4 {
+ cell-id = <MSM_BUS_BCM_SN4>;
+ label = "SN4";
+ qcom,bcm-name = "SN4";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn5: bcm-sn5 {
+ cell-id = <MSM_BUS_BCM_SN5>;
+ label = "SN5";
+ qcom,bcm-name = "SN5";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn6: bcm-sn6 {
+ cell-id = <MSM_BUS_BCM_SN6>;
+ label = "SN6";
+ qcom,bcm-name = "SN6";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn10: bcm-sn10 {
+ cell-id = <MSM_BUS_BCM_SN10>;
+ label = "SN10";
+ qcom,bcm-name = "SN10";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_acv_display: bcm-acv_display {
+ cell-id = <MSM_BUS_BCM_ACV_DISPLAY>;
+ label = "ACV_DISPLAY";
+ qcom,bcm-name = "ACV";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_alc_display: bcm-alc_display {
+ cell-id = <MSM_BUS_BCM_ALC_DISPLAY>;
+ label = "ALC_DISPLAY";
+ qcom,bcm-name = "ALC";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mc0_display: bcm-mc0_display {
+ cell-id = <MSM_BUS_BCM_MC0_DISPLAY>;
+ label = "MC0_DISPLAY";
+ qcom,bcm-name = "MC0";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm0_display: bcm-mm0_display {
+ cell-id = <MSM_BUS_BCM_MM0_DISPLAY>;
+ label = "MM0_DISPLAY";
+ qcom,bcm-name = "MM0";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm1_display: bcm-mm1_display {
+ cell-id = <MSM_BUS_BCM_MM1_DISPLAY>;
+ label = "MM1_DISPLAY";
+ qcom,bcm-name = "MM1";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh0_display: bcm-sh0_display {
+ cell-id = <MSM_BUS_BCM_SH0_DISPLAY>;
+ label = "SH0_DISPLAY";
+ qcom,bcm-name = "SH0";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ /*Buses*/
+ fab_aggre1_noc: fab-aggre1_noc {
+ cell-id = <MSM_BUS_FAB_A1_NOC>;
+ label = "fab-aggre1_noc";
+ qcom,fab-dev;
+ qcom,base-name = "aggre1_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <16384>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_aggre2_noc: fab-aggre2_noc {
+ cell-id = <MSM_BUS_FAB_A2_NOC>;
+ label = "fab-aggre2_noc";
+ qcom,fab-dev;
+ qcom,base-name = "aggre2_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <20480>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_clk_virt: fab-clk_virt {
+ cell-id = <MSM_BUS_FAB_CLK_VIRT>;
+ label = "fab-clk_virt";
+ qcom,fab-dev;
+ qcom,base-name = "clk_virt-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ clocks = <>;
+ };
+
+ fab_compute_noc: fab-compute_noc {
+ cell-id = <MSM_BUS_FAB_COMP_NOC>;
+ label = "fab-compute_noc";
+ qcom,fab-dev;
+ qcom,base-name = "compute_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <57344>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_config_noc: fab-config_noc {
+ cell-id = <MSM_BUS_FAB_CONFIG_NOC>;
+ label = "fab-config_noc";
+ qcom,fab-dev;
+ qcom,base-name = "config_noc-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_dc_noc: fab-dc_noc {
+ cell-id = <MSM_BUS_FAB_DC_NOC>;
+ label = "fab-dc_noc";
+ qcom,fab-dev;
+ qcom,base-name = "dc_noc-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_gem_noc: fab-gem_noc {
+ cell-id = <MSM_BUS_FAB_GEM_NOC>;
+ label = "fab-gem_noc";
+ qcom,fab-dev;
+ qcom,base-name = "gem_noc-base";
+ qcom,qos-off = <128>;
+ qcom,base-offset = <188416>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_mmss_noc: fab-mmss_noc {
+ cell-id = <MSM_BUS_FAB_MMSS_NOC>;
+ label = "fab-mmss_noc";
+ qcom,fab-dev;
+ qcom,base-name = "mmss_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <36864>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_npu_noc: fab-npu_noc {
+ cell-id = <MSM_BUS_FAB_NPU_NOC>;
+ label = "fab-npu_noc";
+ qcom,fab-dev;
+ qcom,base-name = "npu_noc-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_system_noc: fab-system_noc {
+ cell-id = <MSM_BUS_FAB_SYS_NOC>;
+ label = "fab-system_noc";
+ qcom,fab-dev;
+ qcom,base-name = "system_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <45056>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_gem_noc_display: fab-gem_noc_display {
+ cell-id = <MSM_BUS_FAB_GEM_NOC_DISPLAY>;
+ label = "fab-gem_noc_display";
+ qcom,fab-dev;
+ qcom,base-name = "gem_noc-base";
+ qcom,qos-off = <128>;
+ qcom,base-offset = <188416>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+
+ fab_mmss_noc_display: fab-mmss_noc_display {
+ cell-id = <MSM_BUS_FAB_MMSS_NOC_DISPLAY>;
+ label = "fab-mmss_noc_display";
+ qcom,fab-dev;
+ qcom,base-name = "mmss_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <36864>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+
+ /*Masters*/
+ mas_qhm_a1noc_cfg: mas-qhm-a1noc-cfg {
+ cell-id = <MSM_BUS_MASTER_A1NOC_CFG>;
+ label = "mas-qhm-a1noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_aggre1_noc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ };
+
+ mas_qhm_qup_0: mas-qhm-qup-0 {
+ cell-id = <MSM_BUS_MASTER_QUP_0>;
+ label = "mas-qhm-qup-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <6>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_emmc: mas-xm-emmc {
+ cell-id = <MSM_BUS_MASTER_EMMC>;
+ label = "mas-xm-emmc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <3>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,bcms = <&bcm_cn1>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_ufs_mem: mas-xm-ufs-mem {
+ cell-id = <MSM_BUS_MASTER_UFS_MEM>;
+ label = "mas-xm-ufs-mem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <4>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,node-qos-clks {
+ clocks =
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
+ clock-names =
+ "clk-aggre-ufs-phy-axi-no-rate";
+ };
+ };
+
+ mas_qhm_a2noc_cfg: mas-qhm-a2noc-cfg {
+ cell-id = <MSM_BUS_MASTER_A2NOC_CFG>;
+ label = "mas-qhm-a2noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_aggre2_noc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ };
+
+ mas_qhm_qdss_bam: mas-qhm-qdss-bam {
+ cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
+ label = "mas-qhm-qdss-bam";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <6>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_qhm_qup_1: mas-qhm-qup-1 {
+ cell-id = <MSM_BUS_MASTER_QUP_1>;
+ label = "mas-qhm-qup-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <4>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_qxm_crypto: mas-qxm-crypto {
+ cell-id = <MSM_BUS_MASTER_CRYPTO_CORE_0>;
+ label = "mas-qxm-crypto";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <1>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,bcms = <&bcm_ce0>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_qxm_ipa: mas-qxm-ipa {
+ cell-id = <MSM_BUS_MASTER_IPA>;
+ label = "mas-qxm-ipa";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <2>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,defer-init-qos;
+ qcom,node-qos-bcms = <7035 0 1>;
+ };
+
+ mas_xm_qdss_etr: mas-xm-qdss-etr {
+ cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
+ label = "mas-xm-qdss-etr";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <7>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_sdc2: mas-xm-sdc2 {
+ cell-id = <MSM_BUS_MASTER_SDCC_2>;
+ label = "mas-xm-sdc2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <19>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,bcms = <&bcm_cn1>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_usb3_0: mas-xm-usb3-0 {
+ cell-id = <MSM_BUS_MASTER_USB3>;
+ label = "mas-xm-usb3-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <8>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,node-qos-clks {
+ clocks =
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+ clock-names =
+ "clk-aggre-usb3-prim-axi-no-rate";
+ };
+ };
+
+ mas_qxm_camnoc_hf0_uncomp: mas-qxm-camnoc-hf0-uncomp {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_HF0_UNCOMP>;
+ label = "mas-qxm-camnoc-hf0-uncomp";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,connections = <&slv_qns_camnoc_uncomp>;
+ qcom,bus-dev = <&fab_clk_virt>;
+ qcom,bcms = <&bcm_mm1>;
+ };
+
+ mas_qxm_camnoc_icp_uncomp: mas-qxm-camnoc-icp-uncomp {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_ICP_UNCOMP>;
+ label = "mas-qxm-camnoc-icp-uncomp";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_camnoc_uncomp>;
+ qcom,bus-dev = <&fab_clk_virt>;
+ qcom,bcms = <&bcm_mm1>;
+ };
+
+ mas_qxm_camnoc_sf_uncomp: mas-qxm-camnoc-sf-uncomp {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_SF_UNCOMP>;
+ label = "mas-qxm-camnoc-sf-uncomp";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_camnoc_uncomp>;
+ qcom,bus-dev = <&fab_clk_virt>;
+ qcom,bcms = <&bcm_mm1>;
+ };
+
+ mas_ipa_core_master: mas-ipa-core-master {
+ cell-id = <MSM_BUS_MASTER_IPA_CORE>;
+ label = "mas-ipa-core-master";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_ipa_core_slave>;
+ qcom,bus-dev = <&fab_clk_virt>;
+ };
+
+ mas_qup0_core_master: mas-qup0-core-master {
+ cell-id = <MSM_BUS_MASTER_QUP_CORE_0>;
+ label = "mas-qup0-core-master";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qup0_core_slave>;
+ qcom,bus-dev = <&fab_clk_virt>;
+ qcom,bcms = <&bcm_qup0>;
+ };
+
+ mas_qup1_core_master: mas-qup1-core-master {
+ cell-id = <MSM_BUS_MASTER_QUP_CORE_1>;
+ label = "mas-qup1-core-master";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qup1_core_slave>;
+ qcom,bus-dev = <&fab_clk_virt>;
+ qcom,bcms = <&bcm_qup0>;
+ };
+
+ mas_qnm_npu: mas-qnm-npu {
+ cell-id = <MSM_BUS_MASTER_NPU>;
+ label = "mas-qnm-npu";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <1 3>;
+ qcom,connections = <&slv_qns_cdsp_gemnoc>;
+ qcom,bus-dev = <&fab_compute_noc>;
+ qcom,bcms = <&bcm_co2>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_qxm_npu_dsp: mas-qxm-npu-dsp {
+ cell-id = <MSM_BUS_MASTER_NPU_PROC>;
+ label = "mas-qxm-npu-dsp";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <5>;
+ qcom,connections = <&slv_qns_cdsp_gemnoc>;
+ qcom,bus-dev = <&fab_compute_noc>;
+ qcom,bcms = <&bcm_co3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_qnm_snoc: mas-qnm-snoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_MAS>;
+ label = "mas-qnm-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_camera_cfg &slv_qhs_sdc2
+ &slv_qhs_mnoc_cfg &slv_qhs_ufs_mem_cfg
+ &slv_qhs_qm_cfg &slv_qhs_snoc_cfg
+ &slv_qhs_qm_mpu_cfg &slv_qhs_glm
+ &slv_qhs_pdm &slv_qhs_camera_nrt_throttle_cfg
+ &slv_qhs_a2_noc_cfg &slv_qhs_qdss_cfg
+ &slv_qhs_vsense_ctrl_cfg
+ &slv_qhs_camera_rt_throttle_cfg
+ &slv_qhs_display_cfg &slv_qhs_tcsr
+ &slv_qhs_dcc_cfg &slv_qhs_ddrss_cfg
+ &slv_qhs_display_throttle_cfg
+ &slv_qhs_npu_cfg &slv_qhs_ahb2phy0
+ &slv_qhs_gpuss_cfg &slv_qhs_boot_rom
+ &slv_qhs_venus_cfg &slv_qhs_ipa
+ &slv_qhs_security &slv_qhs_imem_cfg
+ &slv_qhs_mss_cfg &slv_srvc_cnoc
+ &slv_qhs_usb3_0 &slv_qhs_venus_throttle_cfg
+ &slv_qhs_cpr_cx &slv_qhs_a1_noc_cfg
+ &slv_qhs_aoss &slv_qhs_prng
+ &slv_qhs_emmc_cfg &slv_qhs_crypto0_cfg
+ &slv_qhs_pimem_cfg &slv_qhs_cpr_mx
+ &slv_qhs_qup0 &slv_qhs_qup1
+ &slv_qhs_clk_ctl>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ mas_xm_qdss_dap: mas-xm-qdss-dap {
+ cell-id = <MSM_BUS_MASTER_QDSS_DAP>;
+ label = "mas-xm-qdss-dap";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_camera_cfg &slv_qhs_sdc2
+ &slv_qhs_mnoc_cfg &slv_qhs_ufs_mem_cfg
+ &slv_qhs_qm_cfg &slv_qhs_snoc_cfg
+ &slv_qhs_qm_mpu_cfg &slv_qhs_glm
+ &slv_qhs_pdm &slv_qhs_camera_nrt_throttle_cfg
+ &slv_qhs_a2_noc_cfg &slv_qhs_qdss_cfg
+ &slv_qhs_vsense_ctrl_cfg
+ &slv_qhs_camera_rt_throttle_cfg
+ &slv_qhs_display_cfg &slv_qhs_tcsr
+ &slv_qhs_dcc_cfg &slv_qhs_ddrss_cfg
+ &slv_qhs_display_throttle_cfg
+ &slv_qhs_npu_cfg &slv_qhs_ahb2phy0
+ &slv_qhs_gpuss_cfg &slv_qhs_boot_rom
+ &slv_qhs_venus_cfg &slv_qhs_ipa
+ &slv_qhs_security &slv_qhs_imem_cfg
+ &slv_qhs_mss_cfg &slv_srvc_cnoc
+ &slv_qhs_usb3_0 &slv_qhs_venus_throttle_cfg
+ &slv_qhs_cpr_cx &slv_qhs_a1_noc_cfg
+ &slv_qhs_aoss &slv_qhs_prng
+ &slv_qhs_emmc_cfg
+ &slv_qhs_crypto0_cfg &slv_qhs_pimem_cfg
+ &slv_qhs_cpr_mx &slv_qhs_qup0
+ &slv_qhs_qup1 &slv_qhs_clk_ctl>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ mas_qhm_cnoc_dc_noc: mas-qhm-cnoc-dc-noc {
+ cell-id = <MSM_BUS_MASTER_CNOC_DC_NOC>;
+ label = "mas-qhm-cnoc-dc-noc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_llcc &slv_qhs_gemnoc>;
+ qcom,bus-dev = <&fab_dc_noc>;
+ };
+
+ mas_acm_apps: mas-acm-apps {
+ cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
+ label = "mas-acm-apps";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <34 32>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,bcms = <&bcm_sh4>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ };
+
+ mas_acm_sys_tcu: mas-acm-sys-tcu {
+ cell-id = <MSM_BUS_MASTER_SYS_TCU>;
+ label = "mas-acm-sys-tcu";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <224>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,bcms = <&bcm_sh2>;
+ qcom,ap-owned;
+ qcom,prio = <6>;
+ };
+
+ mas_qhm_gemnoc_cfg: mas-qhm-gemnoc-cfg {
+ cell-id = <MSM_BUS_MASTER_GEM_NOC_CFG>;
+ label = "mas-qhm-gemnoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_mcdma_ms_mpu_cfg
+ &slv_srvc_gemnoc &slv_qhs_mdsp_ms_mpu_cfg>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ };
+
+ mas_qnm_cmpnoc: mas-qnm-cmpnoc {
+ cell-id = <MSM_BUS_MASTER_COMPUTE_NOC>;
+ label = "mas-qnm-cmpnoc";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <0>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,bcms = <&bcm_sh3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_qnm_mnoc_hf: mas-qnm-mnoc-hf {
+ cell-id = <MSM_BUS_MASTER_MNOC_HF_MEM_NOC>;
+ label = "mas-qnm-mnoc-hf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <64>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qnm_mnoc_sf: mas-qnm-mnoc-sf {
+ cell-id = <MSM_BUS_MASTER_MNOC_SF_MEM_NOC>;
+ label = "mas-qnm-mnoc-sf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <192>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qnm_snoc_gc: mas-qnm-snoc-gc {
+ cell-id = <MSM_BUS_MASTER_SNOC_GC_MEM_NOC>;
+ label = "mas-qnm-snoc-gc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <128>;
+ qcom,connections = <&slv_qns_llcc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_qnm_snoc_sf: mas-qnm-snoc-sf {
+ cell-id = <MSM_BUS_MASTER_SNOC_SF_MEM_NOC>;
+ label = "mas-qnm-snoc-sf";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <96>;
+ qcom,connections = <&slv_qns_llcc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_qxm_gpu: mas-qxm-gpu {
+ cell-id = <MSM_BUS_MASTER_GRAPHICS_3D>;
+ label = "mas-qxm-gpu";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <160 161>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ };
+
+ mas_llcc_mc: mas-llcc-mc {
+ cell-id = <MSM_BUS_MASTER_LLCC>;
+ label = "mas-llcc-mc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,connections = <&slv_ebi>;
+ qcom,bus-dev = <&fab_clk_virt>;
+ };
+
+ mas_qhm_mnoc_cfg: mas-qhm-mnoc-cfg {
+ cell-id = <MSM_BUS_MASTER_CNOC_MNOC_CFG>;
+ label = "mas-qhm-mnoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_mnoc>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm3>;
+ };
+
+ mas_qnm_video0: mas-qnm-video0 {
+ cell-id = <MSM_BUS_MASTER_VIDEO_P0>;
+ label = "mas-qnm-video0";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <6>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qnm_video_cvp: mas-qnm-video-cvp {
+ cell-id = <MSM_BUS_MASTER_VIDEO_PROC>;
+ label = "mas-qnm-video-cvp";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <5>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <5>;
+ qcom,forwarding;
+ };
+
+ mas_qxm_camnoc_hf: mas-qxm-camnoc-hf {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_HF>;
+ label = "mas-qxm-camnoc-hf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <1 2>;
+ qcom,connections = <&slv_qns_mem_noc_hf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm1>;
+ qcom,ap-owned;
+ qcom,prio = <3>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qxm_camnoc_icp: mas-qxm-camnoc-icp {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_ICP>;
+ label = "mas-qxm-camnoc-icp";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <4>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,ap-owned;
+ qcom,prio = <5>;
+ };
+
+ mas_qxm_camnoc_sf: mas-qxm-camnoc-sf {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_SF>;
+ label = "mas-qxm-camnoc-sf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <0>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <3>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qxm_mdp0: mas-qxm-mdp0 {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT0>;
+ label = "mas-qxm-mdp0";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <3>;
+ qcom,connections = <&slv_qns_mem_noc_hf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm1>;
+ qcom,ap-owned;
+ qcom,prio = <3>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_amm_npu_sys: mas-amm-npu-sys {
+ cell-id = <MSM_BUS_MASTER_NPU_SYS>;
+ label = "mas-amm-npu-sys";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,connections = <&slv_qns_npu_sys>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ mas_qhm_npu_cfg: mas-qhm-npu-cfg {
+ cell-id = <MSM_BUS_MASTER_NPU_NOC_CFG>;
+ label = "mas-qhm-npu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_noc &slv_qhs_isense
+ &slv_qhs_llm &slv_qhs_dma_bwmon &slv_qhs_cp
+ &slv_qhs_tcm &slv_qhs_cal_dp0 &slv_qhs_dpm>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ mas_qhm_snoc_cfg: mas-qhm-snoc-cfg {
+ cell-id = <MSM_BUS_MASTER_SNOC_CFG>;
+ label = "mas-qhm-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_snoc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ mas_qnm_aggre1_noc: mas-qnm-aggre1-noc {
+ cell-id = <MSM_BUS_A1NOC_SNOC_MAS>;
+ label = "mas-qnm-aggre1-noc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_gemnoc_sf &slv_qxs_pimem
+ &slv_qxs_imem &slv_qhs_apss &slv_qns_cnoc
+ &slv_xs_qdss_stm>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn5>;
+ };
+
+ mas_qnm_aggre2_noc: mas-qnm-aggre2-noc {
+ cell-id = <MSM_BUS_A2NOC_SNOC_MAS>;
+ label = "mas-qnm-aggre2-noc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_gemnoc_sf &slv_qxs_pimem
+ &slv_qxs_imem &slv_qhs_apss &slv_qns_cnoc
+ &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn6>;
+ };
+
+ mas_qnm_gemnoc: mas-qnm-gemnoc {
+ cell-id = <MSM_BUS_MASTER_GEM_NOC_SNOC>;
+ label = "mas-qnm-gemnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qxs_pimem &slv_qxs_imem
+ &slv_qhs_apss &slv_qns_cnoc
+ &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn10>;
+ };
+
+ mas_qxm_pimem: mas-qxm-pimem {
+ cell-id = <MSM_BUS_MASTER_PIMEM>;
+ label = "mas-qxm-pimem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <2>;
+ qcom,connections = <&slv_qns_gemnoc_gc &slv_qxs_imem>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_gic: mas-xm-gic {
+ cell-id = <MSM_BUS_MASTER_GIC>;
+ label = "mas-xm-gic";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <0>;
+ qcom,connections = <&slv_qns_gemnoc_gc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,ap-owned;
+ qcom,prio = <3>;
+ };
+
+ mas_qnm_mnoc_hf_display: mas-qnm-mnoc-hf_display {
+ cell-id = <MSM_BUS_MASTER_MNOC_HF_MEM_NOC_DISPLAY>;
+ label = "mas-qnm-mnoc-hf_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <64>;
+ qcom,connections = <&slv_qns_llcc_display>;
+ qcom,bus-dev = <&fab_gem_noc_display>;
+ };
+
+ mas_qnm_mnoc_sf_display: mas-qnm-mnoc-sf_display {
+ cell-id = <MSM_BUS_MASTER_MNOC_SF_MEM_NOC_DISPLAY>;
+ label = "mas-qnm-mnoc-sf_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <192>;
+ qcom,connections = <&slv_qns_llcc_display>;
+ qcom,bus-dev = <&fab_gem_noc_display>;
+ };
+
+ mas_llcc_mc_display: mas-llcc-mc_display {
+ cell-id = <MSM_BUS_MASTER_LLCC_DISPLAY>;
+ label = "mas-llcc-mc_display";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,connections = <&slv_ebi_display>;
+ qcom,bus-dev = <&fab_clk_virt>;
+ };
+
+ mas_qxm_mdp0_display: mas-qxm-mdp0_display {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT0_DISPLAY>;
+ label = "mas-qxm-mdp0_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <3>;
+ qcom,connections = <&slv_qns_mem_noc_hf_display>;
+ qcom,bus-dev = <&fab_mmss_noc_display>;
+ qcom,bcms = <&bcm_mm1_display>;
+ };
+
+ /*Internal nodes*/
+
+ /*Slaves*/
+ slv_qns_a1noc_snoc:slv-qns-a1noc-snoc {
+ cell-id = <MSM_BUS_A1NOC_SNOC_SLV>;
+ label = "slv-qns-a1noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,connections = <&mas_qnm_aggre1_noc>;
+ };
+
+ slv_srvc_aggre1_noc:slv-srvc-aggre1-noc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_A1NOC>;
+ label = "slv-srvc-aggre1-noc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ };
+
+ slv_qns_a2noc_snoc:slv-qns-a2noc-snoc {
+ cell-id = <MSM_BUS_A2NOC_SNOC_SLV>;
+ label = "slv-qns-a2noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,connections = <&mas_qnm_aggre2_noc>;
+ };
+
+ slv_srvc_aggre2_noc:slv-srvc-aggre2-noc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_A2NOC>;
+ label = "slv-srvc-aggre2-noc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ };
+
+ slv_qns_camnoc_uncomp:slv-qns-camnoc-uncomp {
+ cell-id = <MSM_BUS_SLAVE_CAMNOC_UNCOMP>;
+ label = "slv-qns-camnoc-uncomp";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_clk_virt>;
+ };
+
+ slv_ipa_core_slave:slv-ipa-core-slave {
+ cell-id = <MSM_BUS_SLAVE_IPA_CORE>;
+ label = "slv-ipa-core-slave";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_clk_virt>;
+ qcom,bcms = <&bcm_ip0>;
+ };
+
+ slv_qup0_core_slave:slv-qup0-core-slave {
+ cell-id = <MSM_BUS_SLAVE_QUP_CORE_0>;
+ label = "slv-qup0-core-slave";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_clk_virt>;
+ qcom,bcms = <&bcm_qup0>;
+ };
+
+ slv_qup1_core_slave:slv-qup1-core-slave {
+ cell-id = <MSM_BUS_SLAVE_QUP_CORE_1>;
+ label = "slv-qup1-core-slave";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_clk_virt>;
+ qcom,bcms = <&bcm_qup0>;
+ };
+
+ slv_qns_cdsp_gemnoc:slv-qns-cdsp-gemnoc {
+ cell-id = <MSM_BUS_SLAVE_CDSP_GEM_NOC>;
+ label = "slv-qns-cdsp-gemnoc";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_compute_noc>;
+ qcom,connections = <&mas_qnm_cmpnoc>;
+ qcom,bcms = <&bcm_co0>;
+ };
+
+ slv_qhs_a1_noc_cfg:slv-qhs-a1-noc-cfg {
+ cell-id = <MSM_BUS_SLAVE_A1NOC_CFG>;
+ label = "slv-qhs-a1-noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_a1noc_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_a2_noc_cfg:slv-qhs-a2-noc-cfg {
+ cell-id = <MSM_BUS_SLAVE_A2NOC_CFG>;
+ label = "slv-qhs-a2-noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_a2noc_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ahb2phy0:slv-qhs-ahb2phy0 {
+ cell-id = <MSM_BUS_SLAVE_AHB2PHY>;
+ label = "slv-qhs-ahb2phy0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ahb2phy2:slv-qhs-ahb2phy2 {
+ cell-id = <MSM_BUS_SLAVE_AHB2PHY_2>;
+ label = "slv-qhs-ahb2phy2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn1>;
+ };
+
+ slv_qhs_aoss:slv-qhs-aoss {
+ cell-id = <MSM_BUS_SLAVE_AOSS>;
+ label = "slv-qhs-aoss";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_boot_rom:slv-qhs-boot-rom {
+ cell-id = <MSM_BUS_SLAVE_BOOT_ROM>;
+ label = "slv-qhs-boot-rom";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_camera_cfg:slv-qhs-camera-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_CFG>;
+ label = "slv-qhs-camera-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_camera_nrt_throttle_cfg:slv-qhs-camera-nrt-thrott-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_NRT_THROTTLE_CFG>;
+ label = "slv-qhs-camera-nrt-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_camera_rt_throttle_cfg:slv-qhs-camera-rt-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_RT_THROTTLE_CFG>;
+ label = "slv-qhs-camera-rt-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_clk_ctl:slv-qhs-clk-ctl {
+ cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
+ label = "slv-qhs-clk-ctl";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_cpr_cx:slv-qhs-cpr-cx {
+ cell-id = <MSM_BUS_SLAVE_RBCPR_CX_CFG>;
+ label = "slv-qhs-cpr-cx";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_cpr_mx:slv-qhs-cpr-mx {
+ cell-id = <MSM_BUS_SLAVE_RBCPR_MX_CFG>;
+ label = "slv-qhs-cpr-mx";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_crypto0_cfg:slv-qhs-crypto0-cfg {
+ cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>;
+ label = "slv-qhs-crypto0-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_dcc_cfg:slv-qhs-dcc-cfg {
+ cell-id = <MSM_BUS_SLAVE_DCC_CFG>;
+ label = "slv-qhs-dcc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ddrss_cfg:slv-qhs-ddrss-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_DDRSS>;
+ label = "slv-qhs-ddrss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_cnoc_dc_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_display_cfg:slv-qhs-display-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_CFG>;
+ label = "slv-qhs-display-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_display_throttle_cfg:slv-qhs-display-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG>;
+ label = "slv-qhs-display-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_emmc_cfg:slv-qhs-emmc-cfg {
+ cell-id = <MSM_BUS_SLAVE_EMMC_CFG>;
+ label = "slv-qhs-emmc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn1>;
+ };
+
+ slv_qhs_glm:slv-qhs-glm {
+ cell-id = <MSM_BUS_SLAVE_GLM>;
+ label = "slv-qhs-glm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_gpuss_cfg:slv-qhs-gpuss-cfg {
+ cell-id = <MSM_BUS_SLAVE_GRAPHICS_3D_CFG>;
+ label = "slv-qhs-gpuss-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_imem_cfg:slv-qhs-imem-cfg {
+ cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
+ label = "slv-qhs-imem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ipa:slv-qhs-ipa {
+ cell-id = <MSM_BUS_SLAVE_IPA_CFG>;
+ label = "slv-qhs-ipa";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_mnoc_cfg:slv-qhs-mnoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_MNOC_CFG>;
+ label = "slv-qhs-mnoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_mnoc_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_mss_cfg:slv-qhs-mss-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_MSS>;
+ label = "slv-qhs-mss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_npu_cfg:slv-qhs-npu-cfg {
+ cell-id = <MSM_BUS_SLAVE_NPU_CFG>;
+ label = "slv-qhs-npu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_npu_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_pdm:slv-qhs-pdm {
+ cell-id = <MSM_BUS_SLAVE_PDM>;
+ label = "slv-qhs-pdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn1>;
+ };
+
+ slv_qhs_pimem_cfg:slv-qhs-pimem-cfg {
+ cell-id = <MSM_BUS_SLAVE_PIMEM_CFG>;
+ label = "slv-qhs-pimem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_prng:slv-qhs-prng {
+ cell-id = <MSM_BUS_SLAVE_PRNG>;
+ label = "slv-qhs-prng";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_qdss_cfg:slv-qhs-qdss-cfg {
+ cell-id = <MSM_BUS_SLAVE_QDSS_CFG>;
+ label = "slv-qhs-qdss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_qm_cfg:slv-qhs-qm-cfg {
+ cell-id = <MSM_BUS_SLAVE_QM_CFG>;
+ label = "slv-qhs-qm-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_qm_mpu_cfg:slv-qhs-qm-mpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_QM_MPU_CFG>;
+ label = "slv-qhs-qm-mpu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_qup0:slv-qhs-qup0 {
+ cell-id = <MSM_BUS_SLAVE_QUP_0>;
+ label = "slv-qhs-qup0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_qup1:slv-qhs-qup1 {
+ cell-id = <MSM_BUS_SLAVE_QUP_1>;
+ label = "slv-qhs-qup1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_sdc2:slv-qhs-sdc2 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_2>;
+ label = "slv-qhs-sdc2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn1>;
+ };
+
+ slv_qhs_security:slv-qhs-security {
+ cell-id = <MSM_BUS_SLAVE_SECURITY>;
+ label = "slv-qhs-security";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_snoc_cfg:slv-qhs-snoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
+ label = "slv-qhs-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_snoc_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_tcsr:slv-qhs-tcsr {
+ cell-id = <MSM_BUS_SLAVE_TCSR>;
+ label = "slv-qhs-tcsr";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ufs_mem_cfg:slv-qhs-ufs-mem-cfg {
+ cell-id = <MSM_BUS_SLAVE_UFS_MEM_CFG>;
+ label = "slv-qhs-ufs-mem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_usb3_0:slv-qhs-usb3-0 {
+ cell-id = <MSM_BUS_SLAVE_USB3>;
+ label = "slv-qhs-usb3-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_venus_cfg:slv-qhs-venus-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_CFG>;
+ label = "slv-qhs-venus-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_venus_throttle_cfg:slv-qhs-venus-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_THROTTLE_CFG>;
+ label = "slv-qhs-venus-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_vsense_ctrl_cfg:slv-qhs-vsense-ctrl-cfg {
+ cell-id = <MSM_BUS_SLAVE_VSENSE_CTRL_CFG>;
+ label = "slv-qhs-vsense-ctrl-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_srvc_cnoc:slv-srvc-cnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_CNOC>;
+ label = "slv-srvc-cnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_gemnoc:slv-qhs-gemnoc {
+ cell-id = <MSM_BUS_SLAVE_GEM_NOC_CFG>;
+ label = "slv-qhs-gemnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_dc_noc>;
+ qcom,connections = <&mas_qhm_gemnoc_cfg>;
+ };
+
+ slv_qhs_llcc:slv-qhs-llcc {
+ cell-id = <MSM_BUS_SLAVE_LLCC_CFG>;
+ label = "slv-qhs-llcc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_dc_noc>;
+ };
+
+ slv_qhs_mcdma_ms_mpu_cfg:slv-qhs-mcdma-ms-mpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_MCDMA_MS_MPU_CFG>;
+ label = "slv-qhs-mcdma-ms-mpu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ };
+
+ slv_qhs_mdsp_ms_mpu_cfg:slv-qhs-mdsp-ms-mpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_MSS_PROC_MS_MPU_CFG>;
+ label = "slv-qhs-mdsp-ms-mpu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ };
+
+ slv_qns_gem_noc_snoc:slv-qns-gem-noc-snoc {
+ cell-id = <MSM_BUS_SLAVE_GEM_NOC_SNOC>;
+ label = "slv-qns-gem-noc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,connections = <&mas_qnm_gemnoc>;
+ };
+
+ slv_qns_llcc:slv-qns-llcc {
+ cell-id = <MSM_BUS_SLAVE_LLCC>;
+ label = "slv-qns-llcc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,connections = <&mas_llcc_mc>;
+ qcom,bcms = <&bcm_sh0>;
+ };
+
+ slv_srvc_gemnoc:slv-srvc-gemnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_GEM_NOC>;
+ label = "slv-srvc-gemnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ };
+
+ slv_ebi:slv-ebi {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ label = "slv-ebi";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_clk_virt>;
+ qcom,bcms = <&bcm_mc0>, <&bcm_acv>;
+ };
+
+ slv_qns_mem_noc_hf:slv-qns-mem-noc-hf {
+ cell-id = <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>;
+ label = "slv-qns-mem-noc-hf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,connections = <&mas_qnm_mnoc_hf>;
+ qcom,bcms = <&bcm_mm0>;
+ };
+
+ slv_qns_mem_noc_sf:slv-qns-mem-noc-sf {
+ cell-id = <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>;
+ label = "slv-qns-mem-noc-sf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,connections = <&mas_qnm_mnoc_sf>;
+ qcom,bcms = <&bcm_mm2>;
+ };
+
+ slv_srvc_mnoc:slv-srvc-mnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_MNOC>;
+ label = "slv-srvc-mnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ };
+
+ slv_qhs_cal_dp0:slv-qhs-cal-dp0 {
+ cell-id = <MSM_BUS_SLAVE_NPU_CAL_DP0>;
+ label = "slv-qhs-cal-dp0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_cp:slv-qhs-cp {
+ cell-id = <MSM_BUS_SLAVE_NPU_CP>;
+ label = "slv-qhs-cp";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_dma_bwmon:slv-qhs-dma-bwmon {
+ cell-id = <MSM_BUS_SLAVE_NPU_INT_DMA_BWMON_CFG>;
+ label = "slv-qhs-dma-bwmon";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_dpm:slv-qhs-dpm {
+ cell-id = <MSM_BUS_SLAVE_NPU_DPM>;
+ label = "slv-qhs-dpm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_isense:slv-qhs-isense {
+ cell-id = <MSM_BUS_SLAVE_ISENSE_CFG>;
+ label = "slv-qhs-isense";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_llm:slv-qhs-llm {
+ cell-id = <MSM_BUS_SLAVE_NPU_LLM_CFG>;
+ label = "slv-qhs-llm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_tcm:slv-qhs-tcm {
+ cell-id = <MSM_BUS_SLAVE_NPU_TCM>;
+ label = "slv-qhs-tcm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qns_npu_sys:slv-qns-npu-sys {
+ cell-id = <MSM_BUS_SLAVE_NPU_COMPUTE_NOC>;
+ label = "slv-qns-npu-sys";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_srvc_noc:slv-srvc-noc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_NPU_NOC>;
+ label = "slv-srvc-noc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_apss:slv-qhs-apss {
+ cell-id = <MSM_BUS_SLAVE_APPSS>;
+ label = "slv-qhs-apss";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ slv_qns_cnoc:slv-qns-cnoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_SLV>;
+ label = "slv-qns-cnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_snoc>;
+ };
+
+ slv_qns_gemnoc_gc:slv-qns-gemnoc-gc {
+ cell-id = <MSM_BUS_SLAVE_SNOC_GEM_NOC_GC>;
+ label = "slv-qns-gemnoc-gc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_snoc_gc>;
+ qcom,bcms = <&bcm_sn2>;
+ };
+
+ slv_qns_gemnoc_sf:slv-qns-gemnoc-sf {
+ cell-id = <MSM_BUS_SLAVE_SNOC_GEM_NOC_SF>;
+ label = "slv-qns-gemnoc-sf";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_snoc_sf>;
+ qcom,bcms = <&bcm_sn0>;
+ };
+
+ slv_qxs_imem:slv-qxs-imem {
+ cell-id = <MSM_BUS_SLAVE_OCIMEM>;
+ label = "slv-qxs-imem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn1>;
+ };
+
+ slv_qxs_pimem:slv-qxs-pimem {
+ cell-id = <MSM_BUS_SLAVE_PIMEM>;
+ label = "slv-qxs-pimem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn3>;
+ };
+
+ slv_srvc_snoc:slv-srvc-snoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_SNOC>;
+ label = "slv-srvc-snoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ slv_xs_qdss_stm:slv-xs-qdss-stm {
+ cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
+ label = "slv-xs-qdss-stm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn4>;
+ };
+
+ slv_xs_sys_tcu_cfg:slv-xs-sys-tcu-cfg {
+ cell-id = <MSM_BUS_SLAVE_TCU>;
+ label = "slv-xs-sys-tcu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ slv_qns_llcc_display:slv-qns-llcc_display {
+ cell-id = <MSM_BUS_SLAVE_LLCC_DISPLAY>;
+ label = "slv-qns-llcc_display";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc_display>;
+ qcom,connections = <&mas_llcc_mc_display>;
+ qcom,bcms = <&bcm_sh0_display>;
+ };
+
+ slv_ebi_display:slv-ebi_display {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0_DISPLAY>;
+ label = "slv-ebi_display";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_clk_virt>;
+ qcom,bcms = <&bcm_mc0_display>, <&bcm_acv_display>;
+ };
+
+ slv_qns_mem_noc_hf_display:slv-qns-mem-noc-hf_display {
+ cell-id = <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC_DISPLAY>;
+ label = "slv-qns-mem-noc-hf_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mmss_noc_display>;
+ qcom,connections = <&mas_qnm_mnoc_hf_display>;
+ qcom,bcms = <&bcm_mm0_display>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-cdp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon-cdp-overlay.dts
new file mode 100755
index 0000000..0b36c97
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-cdp-overlay.dts
@@ -0,0 +1,13 @@
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lagoon-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lagoon CDP";
+ compatible = "qcom,lagoon-cdp", "qcom,lagoon", "qcom,cdp";
+ qcom,msm-id = <434 0x10000>, <459 0x10000>;
+ qcom,board-id = <1 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon-cdp.dts
new file mode 100755
index 0000000..ef8a9a7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-cdp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "lagoon.dtsi"
+#include "lagoon-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lagoon CDP";
+ compatible = "qcom,lagoon-cdp", "qcom,lagoon", "qcom,cdp";
+ qcom,board-id = <1 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-cdp.dtsi
new file mode 100755
index 0000000..6637a13
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-cdp.dtsi
@@ -0,0 +1,421 @@
+#include "lagoon-audio-overlay.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include "lagoon-sde-display.dtsi"
+#include "camera/lagoon-camera-sensor-cdp.dtsi"
+#include "lagoon-thermal-overlay.dtsi"
+
+&soc {
+};
+
+&lagoon_snd {
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic4",
+ "AMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Analog Mic5",
+ "TX DMIC0", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic0",
+ "TX DMIC1", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic1",
+ "TX DMIC2", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "TX DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "TX DMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "TX DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic4",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA DMIC4", "VA MIC BIAS4",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC0", "VA_SWR_CLK",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_ADC2", "VA_SWR_CLK",
+ "VA SWR_ADC3", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_ADC0", "ADC1_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT",
+ "VA SWR_ADC2", "ADC3_OUTPUT",
+ "VA SWR_ADC3", "ADC4_OUTPUT",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT";
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v3";
+
+ vdda-phy-supply = <&L18A>;
+ vdda-pll-supply = <&L22A>;
+ vdda-phy-max-microamp = <62900>;
+ vdda-pll-max-microamp = <18300>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&L7E>;
+ vcc-voltage-level = <2950000 2960000>;
+ vccq2-supply = <&L12A>;
+ vccq2-voltage-level = <1800000 1800000>;
+ vcc-max-microamp = <800000>;
+ vccq2-min-microamp = <0>;
+ vccq2-max-microamp = <800000>;
+ vccq2-pwr-collapse-sup;
+
+ qcom,vddp-ref-clk-supply = <&L22A>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vddp-ref-clk-min-uV = <1152000>;
+ qcom,vddp-ref-clk-max-uV = <1200000>;
+ status = "ok";
+};
+
+&sdhc_1 {
+ vdd-supply = <&L7E>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L12A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&L9E>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L6E>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+};
+
+&pm6350_gpios {
+ key_vol_up {
+ key_vol_up_default: key_vol_up_default {
+ pins = "gpio2";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+ };
+};
+
+&pm6150a_amoled {
+ status = "ok";
+};
+
+&pm7250b_charger {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+ <&pm7250b_vadc ADC_USB_IN_I>,
+ <&pm7250b_vadc ADC_CHG_TEMP>,
+ <&pm7250b_vadc ADC_DIE_TEMP>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+ <&pm7250b_vadc ADC_SBUx>,
+ <&pm7250b_vadc ADC_VPH_PWR>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp",
+ "die_temp",
+ "conn_temp",
+ "sbux_res",
+ "vph_voltage";
+ qcom,batteryless-platform;
+ qcom,sec-charger-config = <0>;
+ qcom,auto-recharge-soc = <98>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ qcom,suspend-input-on-debug-batt;
+};
+
+&pm7250b_qg {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU2>,
+ <&pm7250b_vadc ADC_BAT_ID_PU2>;
+ io-channel-names = "batt-therm",
+ "batt-id";
+ qcom,qg-iterm-ma = <100>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+};
+
+&dsi_rm69299_visionox_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_rm69299_visionox_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_sharp_qsync_fhd_video {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+ qcom,platform-bklight-en-gpio = <&pm6350_gpios 6 0>;
+};
+
+&dsi_sharp_qsync_fhd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+ qcom,platform-bklight-en-gpio = <&pm6350_gpios 6 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_r66451_amoled_144hz_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_144>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-bl-inverted-dbv;
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>;
+};
+
+&qupv3_se0_i2c {
+ status = "ok";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 9 0x00>;
+ qcom,nq-ven = <&tlmm 6 0x00>;
+ qcom,nq-firm = <&tlmm 8 0x00>;
+ qcom,nq-clkreq = <&tlmm 7 0x00>;
+ qcom,nq-vdd-1p8-supply = <&L11A>;
+ qcom,nq-vdd-1p8-voltage = <1800000 1800000>;
+ qcom,nq-vdd-1p8-current = <157000>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&qupv3_se8_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="synaptics,tcm-i2c";
+
+ synaptics_tcm@20 {
+ compatible = "synaptics,tcm-i2c";
+ reg = <0x20>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <22 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&pmx_ts_release>;
+ vdd-supply = <&L11A>;
+ avdd-supply = <&L6A>;
+ synaptics,pwr-reg-name = "avdd";
+ synaptics,bus-reg-name = "vdd";
+ synaptics,irq-gpio = <&tlmm 22 0x2008>;
+ synaptics,irq-on-state = <0>;
+ synaptics,reset-gpio = <&tlmm 21 0x00>;
+ synaptics,reset-on-state = <0>;
+ synaptics,reset-active-ms = <20>;
+ synaptics,reset-delay-ms = <200>;
+ synaptics,power-delay-ms = <200>;
+ synaptics,ubl-i2c-addr = <0x20>;
+ synaptics,extend_report;
+ synaptics,firmware-name = "synaptics_firmware.img";
+
+ panel = <&dsi_rm69299_visionox_amoled_video
+ &dsi_rm69299_visionox_amoled_cmd>;
+ };
+
+ synaptics_dsx@22 {
+ compatible = "synaptics,dsx-i2c";
+ reg = <0x22>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <39 0x2008>;
+ vdd-supply = <&L11A>;
+ avdd-supply = <&L6A>;
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&pmx_ts_release>;
+ synaptics,pwr-reg-name = "avdd";
+ synaptics,bus-reg-name = "vdd";
+ synaptics,ub-i2c-addr = <0x22>;
+ synaptics,max-y-for-2d = <1859>;
+ synaptics,irq-gpio = <&tlmm 22 0x2008>;
+ synaptics,reset-gpio = <&tlmm 21 0x0>;
+ synaptics,irq-on-state = <0>;
+ synaptics,power-delay-ms = <200>;
+ synaptics,reset-delay-ms = <200>;
+ synaptics,reset-on-state = <0>;
+ synaptics,reset-active-ms = <20>;
+
+ panel = <&dsi_sharp_qsync_fhd_video
+ &dsi_sharp_qsync_fhd_cmd>;
+ };
+
+ focaltech@38 {
+ compatible = "focaltech,fts_ts";
+ reg = <0x38>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <22 0x2008>;
+ focaltech,reset-gpio = <&tlmm 21 0x00>;
+ focaltech,irq-gpio = <&tlmm 22 0x2008>;
+ focaltech,max-touch-number = <5>;
+ focaltech,display-coords = <0 0 1080 2340>;
+
+ vdd-supply = <&L6A>;
+
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&pmx_ts_release>;
+
+ panel = <&dsi_r66451_amoled_144hz_cmd>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-coresight.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-coresight.dtsi
new file mode 100755
index 0000000..3a4f2f6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-coresight.dtsi
@@ -0,0 +1,3042 @@
+&soc {
+ hwevent {
+ compatible = "qcom,coresight-hwevent";
+
+ coresight-name = "coresight-hwevent";
+ coresight-csr = <&csr>;
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ audio_etm0: audio_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+ coresight-name = "coresight-audio-etm0";
+
+ qcom,inst-id = <5>;
+
+ port {
+ audio_etm0_out_funnel_swao: endpoint {
+ remote-endpoint =
+ <&funnel_swao_in_audio_etm0>;
+ };
+ };
+ };
+
+ tpdm_swao_0: tpdm@6b09000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6b09000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-swao-0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_swao_0_out_tpda_swao0: endpoint {
+ remote-endpoint = <&tpda_swao0_in_tpdm_swao_0>;
+ };
+ };
+ };
+
+ tpdm_swao_1: tpdm@6b0a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6b0a000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-swao-1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_swao_1_out_tpda_swao1: endpoint {
+ remote-endpoint = <&tpda_swao1_in_tpdm_swao_1>;
+ };
+ };
+ };
+
+ tpdm_vsense: tpdm@6834000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6834000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-vsense";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_vsense_out_tpda_dl_center11: endpoint {
+ remote-endpoint =
+ <&tpda_dl_center11_in_tpdm_vsense>;
+ };
+ };
+ };
+
+ tpdm_dcc: tpdm@6870000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6870000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dcc";
+
+ qcom,hw-enable-check;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_dcc_out_tpda24: endpoint {
+ remote-endpoint =
+ <&tpda24_in_tpdm_dcc>;
+ };
+ };
+ };
+
+ tpdm_prng: tpdm@684c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x684c000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-prng";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_prng_out_tpda25: endpoint {
+ remote-endpoint =
+ <&tpda25_in_tpdm_prng>;
+ };
+ };
+ };
+
+ tpdm_pimem: tpdm@6850000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6850000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-pimem";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_pimem_out_tpda27: endpoint {
+ remote-endpoint =
+ <&tpda27_in_tpdm_pimem>;
+ };
+ };
+ };
+
+ tpdm_qm: tpdm@69d0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x69d0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-qm";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_qm_out_tpda_dl_center13: endpoint {
+ remote-endpoint =
+ <&tpda_dl_center13_in_tpdm_qm>;
+ };
+ };
+ };
+
+ tpdm_lpass: tpdm@6844000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6844000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-lpass";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_lpass_out_tpda0: endpoint {
+ remote-endpoint =
+ <&tpda0_in_tpdm_lpass>;
+ };
+ };
+ };
+
+ tpdm_lpass_lpi: tpdm@6b26000 {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-tpdm-lpass-lpi";
+ qcom,dummy-source;
+
+ port {
+ tpdm_lpass_lpi_out_funnel_swao: endpoint {
+ remote-endpoint =
+ <&funnel_swao_in_tpdm_lpass_lpi>;
+ };
+ };
+ };
+
+ tpdm_npu: tpdm@6c47000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6c47000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-npu";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_npu_out_funnel_npu: endpoint {
+ remote-endpoint =
+ <&funnel_npu_in_tpdm_npu>;
+ };
+ };
+ };
+
+ npu_etm0: npu_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+ coresight-name = "coresight-npu-etm0";
+
+ qcom,inst-id = <14>;
+
+ port {
+ npu_etm0_out_funnel_npu: endpoint {
+ remote-endpoint =
+ <&funnel_npu_in_npu_etm0>;
+ };
+ };
+ };
+
+ tpdm_mdss: tpdm@6c60000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c60000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-mdss";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_mdss_out_funnel_dl_north: endpoint {
+ remote-endpoint =
+ <&funnel_dl_north_in_tpdm_mdss>;
+ };
+ };
+ };
+
+ tpdm_dl_north: tpdm@6ac0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6ac0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dl-north";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_dl_north_out_funnel_dl_north: endpoint {
+ remote-endpoint =
+ <&funnel_dl_north_in_tpdm_dl_north>;
+ };
+ };
+ };
+
+ tpdm_dlct: tpdm@6c28000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6c28000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dlct";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_dlct0_0_out_funnel_dlct0: endpoint {
+ remote-endpoint =
+ <&funnel_dlct0_in_tpdm_dlct0_0>;
+ };
+ };
+ };
+
+ tpdm_ipcc: tpdm@6c29000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6c29000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-ipcc";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_dlct0_1_out_funnel_dlct0: endpoint {
+ remote-endpoint =
+ <&funnel_dlct0_in_tpdm_dlct0_1>;
+ };
+ };
+ };
+
+ tpdm_dlct2: tpdm@6c08000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6c08000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dlct2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_dlct2_out_funnel_dlct2: endpoint {
+ remote-endpoint =
+ <&funnel_dlct2_in_tpdm_dlct2>;
+ };
+ };
+ };
+
+ stm: stm@6002000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb962>;
+
+ reg = <0x6002000 0x1000>,
+ <0x16280000 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ coresight-name = "coresight-stm";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ stm_out_funnel_in0: endpoint {
+ remote-endpoint = <&funnel_in0_in_stm>;
+ };
+ };
+
+ };
+
+ tpdm_gpu: tpdm@6940000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6940000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-gpu";
+ status = "disabled";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_gpu_out_funnel_gpu: endpoint {
+ remote-endpoint =
+ <&funnel_gpu_in_tpdm_gpu>;
+ };
+ };
+ };
+
+ tpdm_ddr: tpdm@6f80000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6f80000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-ddr";
+
+ status = "disabled";
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_ddr_out_funnel_ddr0: endpoint {
+ remote-endpoint =
+ <&funnel_ddr0_in_tpdm_ddr>;
+ };
+ };
+ };
+
+ tpdm_turing: tpdm@6980000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6980000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-turing";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_turing_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_tpdm_turing>;
+ };
+ };
+ };
+
+ tpdm_turing_llm: tpdm@6981000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6981000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-turing-llm";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_turing_llm_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_tpdm_turing_llm>;
+ };
+ };
+ };
+
+ turing_etm0: turing_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+ coresight-name = "coresight-turing-etm0";
+
+ qcom,inst-id = <13>;
+
+ port {
+ turing_etm0_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_turing_etm0>;
+ };
+ };
+ };
+
+ tpdm_wcss: tpdm@69a4000 {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-tpdm-wcss";
+ qcom,dummy-source;
+
+ port {
+ tpdm_wcss_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_tpdm_wcss>;
+ };
+ };
+ };
+
+ etm0: etm@7040000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x7040000 0x1000>;
+ cpu = <&CPU0>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm0_out_funnel_apss: endpoint {
+ remote-endpoint =
+ <&funnel_apss_in_etm0>;
+ };
+ };
+ };
+
+ etm1: etm@7140000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x7140000 0x1000>;
+ cpu = <&CPU1>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm1_out_funnel_apss: endpoint {
+ remote-endpoint =
+ <&funnel_apss_in_etm1>;
+ };
+ };
+ };
+
+ etm2: etm@7240000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x7240000 0x1000>;
+ cpu = <&CPU2>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm2_out_funnel_apss: endpoint {
+ remote-endpoint =
+ <&funnel_apss_in_etm2>;
+ };
+ };
+ };
+
+ etm3: etm@7340000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x7340000 0x1000>;
+ cpu = <&CPU3>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm3";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm3_out_funnel_apss: endpoint {
+ remote-endpoint =
+ <&funnel_apss_in_etm3>;
+ };
+ };
+ };
+
+ etm4: etm@7440000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x7440000 0x1000>;
+ cpu = <&CPU4>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm4";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm4_out_funnel_apss: endpoint {
+ remote-endpoint =
+ <&funnel_apss_in_etm4>;
+ };
+ };
+ };
+
+ etm5: etm@7540000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x7540000 0x1000>;
+ cpu = <&CPU5>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm5";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm5_out_funnel_apss: endpoint {
+ remote-endpoint =
+ <&funnel_apss_in_etm5>;
+ };
+ };
+ };
+
+ etm6: etm@7640000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x7640000 0x1000>;
+ cpu = <&CPU6>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm6";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm6_out_funnel_apss: endpoint {
+ remote-endpoint =
+ <&funnel_apss_in_etm6>;
+ };
+ };
+ };
+
+ etm7: etm@7740000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x7740000 0x1000>;
+ cpu = <&CPU7>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm7";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm7_out_funnel_apss: endpoint {
+ remote-endpoint =
+ <&funnel_apss_in_etm7>;
+ };
+ };
+ };
+
+ tpdm_olc: tpdm@7830000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x7830000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-olc";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_olc_out_tpda_olc0: endpoint {
+ remote-endpoint =
+ <&tpda_olc0_in_tpdm_olc>;
+ };
+ };
+ };
+
+ tpdm_llm_silver: tpdm@78a0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x78a0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-llm-silver";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_llm_silver_out_tpda_llm_silver0: endpoint {
+ remote-endpoint =
+ <&tpda_llm_silver0_in_tpdm_llm_silver>;
+ };
+ };
+ };
+
+ tpdm_llm_gold: tpdm@78b0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x78b0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-llm-gold";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_llm_gold_out_tpda_llm_gold0: endpoint {
+ remote-endpoint =
+ <&tpda_llm_gold0_in_tpdm_llm_gold>;
+ };
+ };
+ };
+
+ tpdm_apss: tpdm@7860000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x7860000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-apss";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_apss_out_tpda_apss0: endpoint {
+ remote-endpoint =
+ <&tpda_apss0_in_tpdm_apss>;
+ };
+ };
+ };
+
+ tpdm_modem0: tpdm@6800000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6800000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-modem-0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_modem0_out_tpda_modem0: endpoint {
+ remote-endpoint =
+ <&tpda_modem0_in_tpdm_modem0>;
+ };
+ };
+ };
+
+ tpdm_modem1: tpdm@6801000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6801000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-modem1";
+
+ status = "disabled";
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_modem1_out_tpda_modem1: endpoint {
+ remote-endpoint =
+ <&tpda_modem1_in_tpdm_modem1>;
+ };
+ };
+ };
+
+ funnel_modem_q6: funnel@680c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x680c000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-modem-q6";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_modem_q6_out_funnel_mq6_dup: endpoint {
+ remote-endpoint =
+ <&funnel_mq6_dup_in_funnel_modem_q6>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_modem_q6_in_modem_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&modem_etm0_out_funnel_modem_q6>;
+ };
+ };
+ };
+ };
+
+ funnel_mq6_dup: funnel_1@680c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x680b000 0x1000>,
+ <0x680c000 0x1000>;
+
+ reg-names = "funnel-base-dummy", "funnel-base-real";
+
+ coresight-name = "coresight-funnel-modem-q6_dup";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ qcom,duplicate-funnel;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_mq6_dup_out_funnel_modem: endpoint {
+ remote-endpoint =
+ <&funnel_modem_in_funnel_mq6_dup>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_mq6_dup_in_funnel_modem_q6: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_modem_q6_out_funnel_mq6_dup>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_mq6_dup_in_modem_diag: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&modem_diag_out_funnel_mq6_dup>;
+ };
+ };
+ };
+ };
+
+ modem_diag: dummy_source {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-modem-diag";
+ qcom,dummy-source;
+
+ port {
+ modem_diag_out_funnel_mq6_dup: endpoint {
+ remote-endpoint =
+ <&funnel_mq6_dup_in_modem_diag>;
+ };
+ };
+ };
+
+ modem_etm0: modem_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+ coresight-name = "coresight-modem-etm0";
+
+ qcom,inst-id = <2>;
+
+ port {
+ modem_etm0_out_funnel_modem_q6: endpoint {
+ remote-endpoint =
+ <&funnel_modem_q6_in_modem_etm0>;
+ };
+ };
+ };
+
+ modem2_etm0: modem2_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+ coresight-name = "coresight-modem2-etm0";
+
+ qcom,inst-id = <11>;
+
+ port {
+ modem2_etm0_out_funnel_modem: endpoint {
+ remote-endpoint =
+ <&funnel_modem_in_modem2_etm0>;
+ };
+ };
+ };
+
+ funnel_npu: funnel@6c44000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x6c44000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-npu";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_npu_out_funnel_dlct0: endpoint {
+ remote-endpoint =
+ <&funnel_dlct0_in_funnel_npu>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_npu_in_tpdm_npu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_npu_out_funnel_npu>;
+ };
+ };
+
+ port@2 {
+ reg = <3>;
+ funnel_npu_in_npu_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&npu_etm0_out_funnel_npu>;
+ };
+ };
+
+ };
+ };
+
+ tpda_modem: tpda@6803000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b969>;
+ reg = <0x6803000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-modem";
+
+ qcom,tpda-atid = <67>;
+ qcom,dsb-elem-size = <0 32>;
+ qcom,cmb-elem-size = <0 64>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_modem_out_funnel_modem: endpoint {
+ remote-endpoint =
+ <&funnel_modem_in_tpda_modem>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_modem0_in_tpdm_modem0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_modem0_out_tpda_modem0>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ tpda_modem1_in_tpdm_modem1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_modem1_out_tpda_modem1>;
+ };
+ };
+
+ };
+ };
+
+ funnel_modem: funnel@6804000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x6804000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-modem";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_modem_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_funnel_modem>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_modem_in_tpda_modem: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_modem_out_funnel_modem>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_modem_in_modem2_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&modem2_etm0_out_funnel_modem>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_modem_in_funnel_mq6_dup: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_mq6_dup_out_funnel_modem>;
+ };
+ };
+
+ };
+ };
+
+ funnel_dl_north: funnel@6ac5000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x6ac5000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-dl-north";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_dl_north_out_funnel_dlct0: endpoint {
+ remote-endpoint =
+ <&funnel_dlct0_in_funnel_dl_north>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_dl_north_in_tpdm_mdss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_mdss_out_funnel_dl_north>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_dl_north_in_tpdm_dl_north: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dl_north_out_funnel_dl_north>;
+ };
+ };
+
+ };
+ };
+
+ funnel_dlct0: funnel@6c2d000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x6c2d000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-dlct0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_dlct0_out_tpda13: endpoint {
+ remote-endpoint =
+ <&tpda13_in_funnel_dlct0>;
+ source = <&tpdm_npu>;
+ };
+
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_dlct0_out_funnel_qatb4: endpoint {
+ remote-endpoint =
+ <&funnel_qatb4_in_funnel_dlct0>;
+ source = <&npu_etm0>;
+ };
+
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_dlct0_out_tpda16: endpoint {
+ remote-endpoint =
+ <&tpda16_in_funnel_dlct0>;
+ source = <&tpdm_mdss>;
+ };
+
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_dlct0_out_tpda17: endpoint {
+ remote-endpoint =
+ <&tpda17_in_funnel_dlct0>;
+ source = <&tpdm_dl_north>;
+ };
+
+ };
+
+ port@4 {
+ reg = <4>;
+ funnel_dlct0_out_tpda21: endpoint {
+ remote-endpoint =
+ <&tpda21_in_funnel_dlct0>;
+ source = <&tpdm_dlct>;
+ };
+
+ };
+
+ port@5 {
+ reg = <5>;
+ funnel_dlct0_out_tpda22: endpoint {
+ remote-endpoint =
+ <&tpda22_in_funnel_dlct0>;
+ source = <&tpdm_ipcc>;
+ };
+
+ };
+
+ port@6 {
+ reg = <4>;
+ funnel_dlct0_in_funnel_npu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_npu_out_funnel_dlct0>;
+ };
+ };
+
+ port@7 {
+ reg = <5>;
+ funnel_dlct0_in_funnel_dl_north: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_north_out_funnel_dlct0>;
+ };
+ };
+
+ port@8 {
+ reg = <6>;
+ funnel_dlct0_in_tpdm_dlct0_0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dlct0_0_out_funnel_dlct0>;
+ };
+ };
+
+ port@9 {
+ reg = <7>;
+ funnel_dlct0_in_tpdm_dlct0_1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dlct0_1_out_funnel_dlct0>;
+ };
+ };
+
+ };
+ };
+
+ funnel_gpu: funnel@6944000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x6944000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-gpu";
+ status = "disabled";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_gpu_out_tpda_dl_center0: endpoint {
+ remote-endpoint =
+ <&tpda_dl_center0_in_funnel_gpu>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_gpu_in_tpdm_gpu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_gpu_out_funnel_gpu>;
+ };
+ };
+
+ };
+ };
+
+ funnel_ddr0: funnel@6f85000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x6f85000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-ddr0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_ddr0_out_tpda_dl_center3: endpoint {
+ remote-endpoint =
+ <&tpda_dl_center3_in_funnel_ddr0>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_ddr0_in_tpdm_ddr: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_ddr_out_funnel_ddr0>;
+ };
+ };
+
+ };
+ };
+
+ funnel_turing: funnel@6983000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x6983000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-turing";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_turing_out_tpda_dl_center5: endpoint {
+ remote-endpoint =
+ <&tpda_dl_center5_in_funnel_turing>;
+ source = <&tpdm_turing>;
+ };
+
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_turing_out_tpda_dl_center6: endpoint {
+ remote-endpoint =
+ <&tpda_dl_center6_in_funnel_turing>;
+ source = <&tpdm_turing_llm>;
+ };
+
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_turing_out_funnel_dlct1: endpoint {
+ remote-endpoint =
+ <&funnel_dlct1_in_funnel_turing>;
+ source = <&turing_etm0>;
+ };
+
+ };
+
+ port@3 {
+ reg = <0>;
+ funnel_turing_in_tpdm_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_turing_out_funnel_turing>;
+ };
+ };
+
+ port@4 {
+ reg = <1>;
+ funnel_turing_in_tpdm_turing_llm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_turing_llm_out_funnel_turing>;
+ };
+ };
+
+ port@5 {
+ reg = <2>;
+ funnel_turing_in_turing_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&turing_etm0_out_funnel_turing>;
+ };
+ };
+
+ };
+ };
+
+ tpda_dl_center: tpda@6c38000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b969>;
+ reg = <0x6c38000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-dl-center";
+
+ qcom,tpda-atid = <78>;
+ qcom,dsb-elem-size = <0 32>,
+ <3 32>,
+ <5 32>,
+ <16 32>;
+ qcom,cmb-elem-size = <3 32>,
+ <6 32>,
+ <16 64>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_dl_center_out_funnel_dlct1: endpoint {
+ remote-endpoint =
+ <&funnel_dlct1_in_tpda_dl_center>;
+ };
+ };
+
+ port@1 {
+ reg = <11>;
+ tpda_dl_center11_in_tpdm_vsense: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_vsense_out_tpda_dl_center11>;
+ };
+ };
+
+ port@2 {
+ reg = <13>;
+ tpda_dl_center13_in_tpdm_qm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_qm_out_tpda_dl_center13>;
+ };
+ };
+
+ port@3 {
+ reg = <0>;
+ tpda_dl_center0_in_funnel_gpu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_gpu_out_tpda_dl_center0>;
+ };
+ };
+
+ port@4 {
+ reg = <3>;
+ tpda_dl_center3_in_funnel_ddr0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_ddr0_out_tpda_dl_center3>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ tpda_dl_center5_in_funnel_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_turing_out_tpda_dl_center5>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ tpda_dl_center6_in_funnel_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_turing_out_tpda_dl_center6>;
+ };
+ };
+
+ };
+ };
+
+ funnel_dlct1: funnel@6c39000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x6c39000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-dlct1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_dlct1_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_funnel_dlct1>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_dlct1_in_tpda_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_dl_center_out_funnel_dlct1>;
+ };
+ };
+
+ port@2 {
+ reg = <4>;
+ funnel_dlct1_in_funnel_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_turing_out_funnel_dlct1>;
+ };
+ };
+
+ };
+ };
+
+ funnel_dlct2: funnel@6c0d000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x6c0d000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-dlct2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_dlct2_out_tpda2: endpoint {
+ remote-endpoint =
+ <&tpda2_in_funnel_dlct2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_dlct2_in_tpdm_dlct2: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dlct2_out_funnel_dlct2>;
+ };
+ };
+
+ };
+ };
+
+ funnel_apss: funnel@7800000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x7800000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-apss";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_apss_out_funnel_apss_merge: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merge_in_funnel_apss>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_apss_in_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm0_out_funnel_apss>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_apss_in_etm1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm1_out_funnel_apss>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ funnel_apss_in_etm2: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm2_out_funnel_apss>;
+ };
+ };
+
+ port@4 {
+ reg = <3>;
+ funnel_apss_in_etm3: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm3_out_funnel_apss>;
+ };
+ };
+
+ port@5 {
+ reg = <4>;
+ funnel_apss_in_etm4: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm4_out_funnel_apss>;
+ };
+ };
+
+ port@6 {
+ reg = <5>;
+ funnel_apss_in_etm5: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm5_out_funnel_apss>;
+ };
+ };
+
+ port@7 {
+ reg = <6>;
+ funnel_apss_in_etm6: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm6_out_funnel_apss>;
+ };
+ };
+
+ port@8 {
+ reg = <7>;
+ funnel_apss_in_etm7: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm7_out_funnel_apss>;
+ };
+ };
+
+ };
+ };
+
+ tpda_olc: tpda@7832000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b969>;
+ reg = <0x7832000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-olc";
+
+ qcom,tpda-atid = <69>;
+ qcom,cmb-elem-size = <0 64>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_olc_out_funnel_apss_merge: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merge_in_tpda_olc>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_olc0_in_tpdm_olc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_olc_out_tpda_olc0>;
+ };
+ };
+
+ };
+ };
+
+ tpda_llm_silver: tpda@78c0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b969>;
+ reg = <0x78c0000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-llm-silver";
+
+ qcom,tpda-atid = <72>;
+ qcom,cmb-elem-size = <0 32>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_llm_silver_out_funnel_apss_merge: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merge_in_tpda_llm_silver>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_llm_silver0_in_tpdm_llm_silver: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_llm_silver_out_tpda_llm_silver0>;
+ };
+ };
+
+ };
+ };
+
+ tpda_llm_gold: tpda@78d0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b969>;
+ reg = <0x78d0000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-llm-gold";
+
+ qcom,tpda-atid = <73>;
+ qcom,cmb-elem-size = <0 32>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_llm_gold_out_funnel_apss_merge: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merge_in_tpda_llm_gold>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_llm_gold0_in_tpdm_llm_gold: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_llm_gold_out_tpda_llm_gold0>;
+ };
+ };
+
+ };
+ };
+
+ tpda_apss: tpda@7862000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b969>;
+ reg = <0x7862000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-apss";
+
+ qcom,tpda-atid = <66>;
+ qcom,dsb-elem-size = <3 32>;
+ qcom,cmb-elem-size = <0 32>,
+ <1 32>,
+ <2 64>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_apss_out_funnel_apss_merge: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merge_in_tpda_apss>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_apss0_in_tpdm_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_apss_out_tpda_apss0>;
+ };
+ };
+
+ };
+ };
+
+ funnel_apss_merge: funnel@7810000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x7810000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-apss-merge";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_apss_merge_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_funnel_apss_merge>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_apss_merge_in_funnel_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_apss_out_funnel_apss_merge>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_apss_merge_in_tpda_olc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_olc_out_funnel_apss_merge>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_apss_merge_in_tpda_llm_silver: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_llm_silver_out_funnel_apss_merge>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ funnel_apss_merge_in_tpda_llm_gold: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_llm_gold_out_funnel_apss_merge>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ funnel_apss_merge_in_tpda_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_apss_out_funnel_apss_merge>;
+ };
+ };
+
+ };
+ };
+
+ tpda: tpda@6004000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b969>;
+ reg = <0x6004000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda";
+
+ qcom,tpda-atid = <65>;
+ qcom,bc-elem-size = <16 32>,
+ <24 32>,
+ <25 32>;
+ qcom,tc-elem-size = <16 32>,
+ <25 32>;
+ qcom,dsb-elem-size = <1 32>,
+ <6 32>,
+ <7 32>,
+ <10 32>,
+ <11 32>,
+ <12 32>,
+ <13 32>,
+ <14 32>,
+ <16 32>,
+ <19 32>,
+ <24 32>,
+ <25 32>;
+ qcom,cmb-elem-size = <7 64>,
+ <13 32>,
+ <15 32>,
+ <16 32>,
+ <17 32>,
+ <18 64>,
+ <20 64>,
+ <21 64>,
+ <22 32>,
+ <23 32>,
+ <25 64>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_tpda>;
+ };
+ };
+
+ port@1 {
+ reg = <24>;
+ tpda24_in_tpdm_dcc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dcc_out_tpda24>;
+ };
+ };
+
+ port@2 {
+ reg = <25>;
+ tpda25_in_tpdm_prng: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_prng_out_tpda25>;
+ };
+ };
+
+ port@3 {
+ reg = <27>;
+ tpda27_in_tpdm_pimem: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_pimem_out_tpda27>;
+ };
+ };
+
+ port@4 {
+ reg = <0>;
+ tpda0_in_tpdm_lpass: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_lpass_out_tpda0>;
+ };
+ };
+
+ port@5 {
+ reg = <13>;
+ tpda13_in_funnel_dlct0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dlct0_out_tpda13>;
+ };
+ };
+
+ port@6 {
+ reg = <16>;
+ tpda16_in_funnel_dlct0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dlct0_out_tpda16>;
+ };
+ };
+
+ port@7 {
+ reg = <17>;
+ tpda17_in_funnel_dlct0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dlct0_out_tpda17>;
+ };
+ };
+
+ port@8 {
+ reg = <21>;
+ tpda21_in_funnel_dlct0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dlct0_out_tpda21>;
+ };
+ };
+
+ port@9 {
+ reg = <22>;
+ tpda22_in_funnel_dlct0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dlct0_out_tpda22>;
+ };
+ };
+
+ port@10 {
+ reg = <2>;
+ tpda2_in_funnel_dlct2: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dlct2_out_tpda2>;
+ };
+ };
+
+ };
+ };
+
+ funnel_qatb: funnel@6005000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x6005000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-qatb";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_qatb_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_funnel_qatb>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_qatb_in_tpda: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_out_funnel_qatb>;
+ };
+ };
+
+ port@2 {
+ reg = <4>;
+ funnel_qatb4_in_funnel_dlct0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dlct0_out_funnel_qatb4>;
+ };
+ };
+
+ };
+ };
+
+ csr: csr@6001000 {
+ compatible = "qcom,coresight-csr";
+ reg = <0x6001000 0x1000>;
+ reg-names = "csr-base";
+
+ coresight-name = "coresight-csr";
+ qcom,perflsheot-set-support;
+ qcom,usb-bam-support;
+ qcom,hwctrl-set-support;
+ qcom,set-byte-cntr-support;
+
+ qcom,blk-size = <1>;
+ };
+
+ swao_csr: csr@6b0c000 {
+ compatible = "qcom,coresight-csr";
+ reg = <0x6b0c000 0x1000>;
+ reg-names = "csr-base";
+
+ coresight-name = "coresight-swao-csr";
+ qcom,timestamp-support;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,blk-size = <1>;
+ };
+
+ funnel_in0: funnel@6041000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x6041000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-in0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_in0_out_funnel_merge: endpoint {
+ remote-endpoint =
+ <&funnel_merge_in_funnel_in0>;
+ };
+ };
+
+ port@1 {
+ reg = <6>;
+ funnel_in0_in_funnel_qatb: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_qatb_out_funnel_in0>;
+ };
+ };
+
+ port@2 {
+ reg = <7>;
+ funnel_in0_in_stm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&stm_out_funnel_in0>;
+ };
+ };
+
+ };
+ };
+
+ funnel_in1: funnel@6042000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x6042000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-in1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_in1_out_funnel_merge: endpoint {
+ remote-endpoint =
+ <&funnel_merge_in_funnel_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <2>;
+ funnel_in1_in_funnel_dlct1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dlct1_out_funnel_in1>;
+ };
+ };
+
+ port@2 {
+ reg = <3>;
+ funnel_in1_in_tpdm_wcss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_wcss_out_funnel_in1>;
+ };
+ };
+
+ port@3 {
+ reg = <4>;
+ funnel_in1_in_funnel_apss_merge: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_apss_merge_out_funnel_in1>;
+ };
+ };
+
+ port@4 {
+ reg = <6>;
+ funnel_in1_in_funnel_modem: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_modem_out_funnel_in1>;
+ };
+ };
+
+ };
+ };
+
+ funnel_merge: funnel@6045000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x6045000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-merge";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_merge_out_funnel_swao: endpoint {
+ remote-endpoint =
+ <&funnel_swao_in_funnel_merge>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_merge_in_funnel_in1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_in1_out_funnel_merge>;
+ };
+ };
+
+ port@2 {
+ reg = <0>;
+ funnel_merge_in_funnel_in0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_in0_out_funnel_merge>;
+ };
+ };
+
+ };
+ };
+
+ tpda_swao: tpda@6b08000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b969>;
+ reg = <0x6b08000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-swao";
+
+ qcom,tpda-atid = <71>;
+ qcom,dsb-elem-size = <1 32>;
+ qcom,cmb-elem-size = <0 64>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_swao_out_funnel_swao: endpoint {
+ remote-endpoint =
+ <&funnel_swao_in_tpda_swao>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_swao0_in_tpdm_swao_0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_swao_0_out_tpda_swao0>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ tpda_swao1_in_tpdm_swao_1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_swao_1_out_tpda_swao1>;
+ };
+ };
+
+ };
+ };
+
+ funnel_swao: funnel@6b04000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x6b04000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-swao";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_swao_out_tmc_etf: endpoint {
+ remote-endpoint =
+ <&tmc_etf_in_funnel_swao>;
+ };
+ };
+
+ port@1 {
+ reg = <5>;
+ funnel_swao_in_audio_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&audio_etm0_out_funnel_swao>;
+ };
+ };
+
+ port@2 {
+ reg = <5>;
+ funnel_swao_in_tpdm_lpass_lpi: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_lpass_lpi_out_funnel_swao>;
+ };
+ };
+
+ port@3 {
+ reg = <6>;
+ funnel_swao_in_tpda_swao: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_swao_out_funnel_swao>;
+ };
+ };
+
+ port@4 {
+ reg = <7>;
+ funnel_swao_in_funnel_merge: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_merge_out_funnel_swao>;
+ };
+ };
+
+ };
+ };
+
+ tmc_etf: tmc@6b05000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+ reg = <0x6b05000 0x1000>;
+ reg-names = "tmc-base";
+
+ coresight-name = "coresight-tmc-etf";
+ coresight-ctis = <&cti_swao_cti0 &cti_swao_cti3>;
+ coresight-csr = <&swao_csr>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tmc_etf_out_replicator_swao: endpoint {
+ remote-endpoint =
+ <&replicator_swao_in_tmc_etf>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tmc_etf_in_funnel_swao: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_swao_out_tmc_etf>;
+ };
+ };
+
+ };
+ };
+
+ replicator_swao: replicator@6b06000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x6b06000 0x1000>;
+ reg-names = "replicator-base";
+
+ coresight-name = "coresight-replicator-swao";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ replicator_swao_out_replicator_qdss: endpoint {
+ remote-endpoint =
+ <&replicator_qdss_in_replicator_swao>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ replicator_swao_in_tmc_etf: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tmc_etf_out_replicator_swao>;
+ };
+ };
+
+ };
+ };
+
+ replicator_qdss: replicator@6046000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x6046000 0x1000>;
+ reg-names = "replicator-base";
+
+ coresight-name = "coresight-replicator-qdss";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ replicator_qdss_out_tmc_etr: endpoint {
+ remote-endpoint =
+ <&tmc_etr_in_replicator_qdss>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ replicator_qdss_in_replicator_swao: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&replicator_swao_out_replicator_qdss>;
+ };
+ };
+
+ };
+ };
+
+ tmc_etr: tmc@6048000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+ reg = <0x6048000 0x1000>,
+ <0x6064000 0x15000>;
+ reg-names = "tmc-base", "bam-base";
+ qcom,iommu-dma = "bypass";
+ iommus = <&apps_smmu 0x0480 0x20>,
+ <&apps_smmu 0x04a0 0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ arm,buffer-size = <0x400000>;
+ arm,scatter-gather;
+
+ qcom,sw-usb;
+ coresight-name = "coresight-tmc-etr";
+ coresight-ctis = <&cti0 &cti_swao_cti3>;
+ coresight-csr = <&csr>;
+
+ interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "byte-cntr-irq";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tmc_etr_in_replicator_qdss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&replicator_qdss_out_tmc_etr>;
+ };
+ };
+
+ };
+ };
+
+ cti_apss_cti0: cti@78e0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x78e0000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss_cti0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_apss_cti1: cti@78f0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x78f0000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss_cti1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_apss_cti2: cti@7900000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7900000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss_cti2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0: cti@6010000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6010000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1: cti@6011000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6011000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti10: cti@601a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601a000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti10";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti11: cti@601b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti11";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti12: cti@601c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601c000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti12";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti13: cti@601d000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601d000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti13";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti14: cti@601e000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601e000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti14";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti15: cti@601f000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601f000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti15";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2: cti@6012000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6012000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,cti-gpio-trigout = <0>;
+ pinctrl-names = "cti-trigout-pctrl";
+ pinctrl-0 = <&trigout_a>;
+ };
+
+ cti3: cti@6013000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6013000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti3";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti4: cti@6014000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6014000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti4";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti5: cti@6015000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6015000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti5";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti6: cti@6016000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6016000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti6";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti7: cti@6017000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6017000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti7";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti8: cti@6018000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6018000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti8";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti9: cti@6019000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6019000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti9";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_mss: cti@680b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x680b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-mss";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_lpass_dl_cti: cti@6845000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6845000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-lpass_dl_cti";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_gpu_isdb_cti: cti@6941000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6941000 0x1000>;
+ reg-names = "cti-base";
+
+ status = "disabled";
+ coresight-name = "coresight-cti-gpu_isdb_cti";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_gpu_cortex_m3: cti@6942000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6942000 0x1000>;
+ reg-names = "cti-base";
+
+ status = "disabled";
+ coresight-name = "coresight-cti-gpu_cortex_m3";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_turing_dl_cti: cti@6982000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6982000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-turing_dl_cti";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_turing_q6_cti: cti@698b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x698b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-turing_q6_cti";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dl_north_cti0: cti@6ac1000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6ac1000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dl-north_cti0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dl_north_cti1: cti@6ac2000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6ac2000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dl-north_cti1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dl_north_cti2: cti@6ac3000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6ac3000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dl-north_cti2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dl_north_cti3: cti@6ac4000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6ac4000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dl-north_cti3";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_swao_cti0: cti@6b00000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b00000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-swao_cti0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_swao_cti1: cti@6b01000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b01000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-swao_cti1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_swao_cti2: cti@6b02000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b02000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-swao_cti2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_swao_cti3: cti@6b03000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b03000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-swao_cti3";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_aop_m3: cti@6b0e000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b0e000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-aop-m3";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_lpass_lpi_cti: cti@6b21000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b21000 0x1000>;
+ reg-names = "cti-base";
+
+ status = "disabled";
+ coresight-name = "coresight-cti-lpass_lpi_cti";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_lpass_q6_cti: cti@6b2B000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b2B000 0x1000>;
+ reg-names = "cti-base";
+
+ status = "disabled";
+ coresight-name = "coresight-cti-lpass_q6_cti";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct2_cti0: cti@6c09000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c09000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct2_cti0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct2_cti1: cti@6c0a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c0a000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct2_cti1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct2_cti2: cti@6c0b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c0b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct2_cti2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct2_cti3: cti@6c0c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c0c000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct2_cti3";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct0_cti0: cti@6c2a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c2a000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct0_cti0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct0_cti1: cti@6c2b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c2b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct0_cti1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct0_cti2: cti@6c2c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c2c000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct0_cti2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_npu_dl_cti_0: cti@6c42000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c42000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-npu_dl_cti_0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_npu_dl_cti_1: cti@6c43000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c43000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-npu_dl_cti_1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_npu_q6_cti: cti@6c4b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c4b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-npu_q6_cti";
+ status = "disabled";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_sierra_a6_cti: cti@6c13000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c13000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-sierra_a6_cti";
+ status = "disabled";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_mdss_dl_cti: cti@6c61000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c61000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-mdss_dl_cti";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_ddr_dl_0_cti_0: cti@6f82000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6f82000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_0_cti_0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_ddr_dl_0_cti_1: cti@6f83000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6f83000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_0_cti_1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_ddr_dl_0_cti_2: cti@6f84000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6f84000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_0_cti_2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_ddr_dl_1_cti_0: cti@6f90000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6f90000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_1_cti_0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_ddr_dl_1_cti_1: cti@6f91000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6f91000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_1_cti_1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_ddr_dl_1_cti_2: cti@6f92000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6f92000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_1_cti_2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_olc: cti@7831000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7831000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-olc";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dl_apss: cti@7861000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7861000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dl-apss";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ ipcb_tgu: tgu@6b0b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb999>;
+ reg = <0x06b0b000 0x1000>;
+ reg-names = "tgu-base";
+ tgu-steps = <3>;
+ tgu-conditions = <4>;
+ tgu-regs = <4>;
+ tgu-timer-counters = <8>;
+
+ coresight-name = "coresight-tgu-ipcb";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-fp4.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-fp4.dtsi
new file mode 100644
index 0000000..c77a080
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-fp4.dtsi
@@ -0,0 +1,643 @@
+#include "lagoon-mtp.dtsi"
+#include "dsi-panel-ft8716u-1080p-video.dtsi"
+#include "dsi-panel-hx83112a-auo-1080p-video.dtsi"
+#include "pxlw/pxlw-iris6.dtsi"
+
+&mtp_batterydata {
+ #include "qg-batterydata-fp4-veken-4360mah.dtsi"
+};
+
+&thermal_zones {
+ quiet-therm-usr {
+ trips {
+ active-config0 {
+ temperature = <43000>;
+ hysteresis = <7000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&pm7250b_charger {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+ <&pm7250b_vadc ADC_USB_IN_I>,
+ <&pm7250b_vadc ADC_CHG_TEMP>,
+ <&pm7250b_vadc ADC_DIE_TEMP>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+ <&pm7250b_vadc ADC_SBUx>,
+ <&pm7250b_vadc ADC_VPH_PWR>,
+ <&pm7250b_vadc ADC_AMUX_THM1_PU2>,
+ <&pm7250b_vadc ADC_INT_EXT_ISENSE_VBAT_VDATA>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp",
+ "die_temp",
+ "conn_temp",
+ "sbux_res",
+ "vph_voltage",
+ "skin_temp",
+ "v_i_int_ext";
+ qcom,battery-data = <&mtp_batterydata>;
+ qcom,fv-max-uv = <4400000>;
+ qcom,fcc-max-ua = <4296000>;
+ qcom,otg-cl-ua = <1500000>;
+ qcom,wls-current-max-ua = <1300000>;
+ qcom,hvdcp2-max-icl-ua = <3000000>;
+ qcom,hvdcp3-max-icl-ua = <3000000>;
+ qcom,qc4-max-icl-ua = <3000000>;
+ qcom,chg-term-src = <1>;
+ qcom,chg-term-current-ma = <(-195)>;
+ qcom,sec-charger-config = <1>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,lpd-disable;
+ qcom,thermal-mitigation = <2000000 2000000 2000000 2000000
+ 1500000 1000000 500000>;
+ qcom,thermal-mitigation-lcdon = <2000000 2000000 2000000 2000000
+ 1500000 1000000 500000>;
+ qcom,disable-suspend-on-collapse;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ qcom,float-option = <2>;
+ qcom,auto-recharge-soc = <99>;
+ qcom,suspend-input-on-debug-batt;
+ //qcom,en-skin-therm-mitigation;
+ qcom,smb-internal-pull-kohm = <0>;
+};
+
+&pm7250b_qg {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU1>,
+ <&pm7250b_vadc ADC_BAT_ID_PU2>;
+ qcom,battery-data = <&mtp_batterydata>;
+ qcom,vbatt-empty-mv = <3200>;
+ qcom,vbatt-low-mv = <3500>;
+ qcom,vbatt-cutoff-mv = <3400>;
+ qcom,fvss-vbatt-mv = <3500>;
+ qcom,qg-iterm-ma = <350>;
+ qcom,ignore-shutdown-soc-secs = <604800>;
+ qcom,shutdown-temp-diff = <150>;
+ qcom,shutdown_soc_threshold = <50>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ //qcom,rbat-conn-mohm = <35>;
+ qcom,use-cp-iin-sns;
+};
+
+&smb1396_div2_cp_master {
+ qcom,max-cutoff-soc = <85>;
+};
+
+&smb1396_slave {
+ status = "disabled";
+};
+
+&smb1396_div2_cp_slave {
+ status = "disabled";
+};
+
+&eud {
+ status = "disabled";
+};
+
+
+&pm7250b_pdphy {
+ qcom,default-sink-caps = <5000 2000>, /* 5V @ 2A */
+ <9000 1500>, /* 9V @ 1.5A */
+ <10000 1500>; /* 10V @ 1.5A */
+};
+
+&usb0 {
+ extcon = <&pm7250b_pdphy>, <&pm7250b_charger>;
+};
+
+&qusb_phy0 {
+ qcom,qusb-phy-init-seq =
+ /* <value reg_offset> */
+ <0x23 0x210 /* PWR_CTRL1 */
+ 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
+ 0x7c 0x18c /* PLL_CLOCK_INVERTERS */
+ 0x80 0x2c /* PLL_CMODE */
+ 0x0a 0x184 /* PLL_LOCK_DELAY */
+ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
+ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */
+ 0x1a 0x198 /* PLL_BIAS_CONTROL_2 tianlang.zhou update on 2021.4.27 */
+ 0x21 0x214 /* PWR_CTRL2 */
+ 0x08 0x220 /* IMP_CTRL1 */
+ 0x58 0x224 /* IMP_CTRL2 */
+ 0x86 0x240 /* TUNE1 tianlang.zhou update on 2021.4.27 */
+ 0x29 0x244 /* TUNE2 */
+ 0xca 0x248 /* TUNE3 */
+ 0x04 0x24c /* TUNE4 */
+ 0x03 0x250 /* TUNE5 */
+ 0x30 0x23c /* CHG_CTRL2 */
+ 0x22 0x210>; /* PWR_CTRL1 */
+
+ qcom,qusb-phy-host-init-seq =
+ /* <value reg_offset> */
+ <0x23 0x210 /* PWR_CTRL1 */
+ 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
+ 0x7c 0x18c /* PLL_CLOCK_INVERTERS */
+ 0x80 0x2c /* PLL_CMODE */
+ 0x0a 0x184 /* PLL_LOCK_DELAY */
+ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
+ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */
+ 0x1a 0x198 /* PLL_BIAS_CONTROL_2 tianlang.zhou update on 2021.4.27 */
+ 0x21 0x214 /* PWR_CTRL2 */
+ 0x08 0x220 /* IMP_CTRL1 */
+ 0x58 0x224 /* IMP_CTRL2 */
+ 0x86 0x240 /* TUNE1 tianlang.zhou update on 2021.4.27 */
+ 0x29 0x244 /* TUNE2 */
+ 0xca 0x248 /* TUNE3 */
+ 0x04 0x24c /* TUNE4 */
+ 0x03 0x250 /* TUNE5 */
+ 0x30 0x23c /* CHG_CTRL2 */
+ 0x22 0x210>; /* PWR_CTRL1 */
+};
+
+&pm6150l_wled {
+ qcom,string-cfg = <3>;
+ qcom,fs-current-limit = <20000>;
+ status = "okay";
+};
+
+&pm6150l_lcdb {
+ status = "okay";
+};
+
+&pm6150a_amoled {
+ status = "disabled";
+};
+
+&dsi_hx83112a_auo_1080_video{
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,mdss-brightness-default-level = <167>;
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+ qcom,mdss-dsi-t-clk-post = <0x0E>;
+ qcom,mdss-dsi-t-clk-pre = <0x37>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 21 08 08 25 23 08 0a 09 02 04 00];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_ft8716u_1080_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,mdss-brightness-default-level = <167>;
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+ qcom,mdss-dsi-t-clk-post = <0x0e>;
+ qcom,mdss-dsi-t-clk-pre = <0x35>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 23 21 07 07 05 03 04 00];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+
+&sde_dsi {
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+ qcom,dsi-default-panel = <&dsi_hx83112a_auo_1080_video>;
+};
+
+&sde_dp {
+ pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
+ pinctrl-0 = <&mdss_dp_aux_active &mdss_dp_usbplug_cc_active>;
+ pinctrl-1 = <&mdss_dp_aux_suspend &mdss_dp_usbplug_cc_suspend>;
+ qcom,aux-en-gpio = <&tlmm 54 0>;
+ qcom,aux-sel-gpio = <&tlmm 93 0>;
+ qcom,usbplug-cc-gpio = <&tlmm 124 0>;
+ qcom,dp-gpio-aux-switch;
+};
+
+&qupv3_se8_i2c {
+
+ qcom,i2c-touch-active = "himax,hxcommon";
+ status = "okay";
+ synaptics_tcm@20 {
+ status = "disabled";
+ };
+
+ himax_ts@48 {
+ compatible = "himax,hxcommon";
+ reg = <0x48>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <22 0x2>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_active &ts_rst_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&pmx_ts_release>;
+ himax,panel-coords = <0 1080 0 2340>;
+ himax,display-coords = <0 1080 0 2340>;
+ himax,irq-gpio = <&tlmm 22 0x00>;
+ himax,rst-gpio = <&tlmm 21 0x00>;
+ report_type = <1>;
+
+ panel = <&dsi_hx83112a_auo_1080_video>;
+ };
+};
+
+&lagoon_snd {
+ qcom,model = "lito-lagoon-fp4-snd-card";
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
+ qcom,wcn-btfm = <1>;
+ qcom,ext-disp-audio-rx = <1>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic3",
+ "AMIC4", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic4",
+ "AMIC5", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic5",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA SWR_ADC0", "VA_SWR_CLK",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_ADC2", "VA_SWR_CLK",
+ "VA SWR_ADC3", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_ADC0", "ADC1_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT",
+ "VA SWR_ADC2", "ADC3_OUTPUT",
+ "VA SWR_ADC3", "ADC4_OUTPUT",
+ "EAR","HAC_RX";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+ /delete-property/ qcom,cdc-dmic01-gpios;
+ /delete-property/ qcom,cdc-dmic23-gpios;
+ /delete-property/ qcom,cdc-dmic45-gpios;
+ asoc-codec = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
+ "msm-ext-disp-audio-codec-rx";
+ qcom,wsa-max-devs = <0>;
+ /delete-property/ qcom,wsa-devs;
+ /delete-property/ qcom,wsa-aux-dev-prefix;
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&wcd938x_codec>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>,
+ <&lpi_tlmm>, <&bolero>;
+ qcom,msm-hac-pa-gpios = <&cdc_hac_pa_gpio>;
+};
+
+&wcd937x_codec{
+ status = "disabled";
+};
+&wcd938x_codec{
+ status = "ok";
+};
+&wcd937x_rx_slave {
+ status = "disabled";
+};
+
+&wcd937x_tx_slave {
+ status = "disabled";
+};
+
+&wcd938x_tx_slave {
+ status = "ok";
+};
+
+&wcd938x_rx_slave {
+ status = "ok";
+};
+&cdc_dmic01_gpios{
+ status = "disabled";
+};
+
+&cdc_dmic23_gpios{
+ status = "disabled";
+};
+&cdc_dmic45_gpios{
+ status = "disabled";
+};
+&wsa883x_0221{
+ status = "disabled";
+};
+&wsa883x_0222{
+ status = "disabled";
+};
+
+/*aw881xx I2c is used gpio0 &gpio1 same as nfc in lagoon-pinctrl.dtsi */
+&qupv3_se0_i2c {
+ status = "ok";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ aw882xx_smartpa@34 {
+ compatible = "awinic,aw882xx_smartpa";
+ reg = <0x34>;
+ reset-gpio = <&tlmm 12 0>;
+ irq-gpio = <&tlmm 48 0x2008>;
+ monitor-flag = <1>;
+ sync-flag = <0>;
+ monitor-timer-val = <3000>;
+ aw-cali-mode = "aw_misc";
+ sound-channel = "left";
+ aw-stereo-cali;
+ status = "okay";
+ pinctrl-names = "aw_reset_low",
+ "aw_reset_high",
+ "aw_irq_active";
+ pinctrl-0 = <&aw_reset1_low>;
+ pinctrl-1 = <&aw_reset1_high>;
+ pinctrl-2 = <&aw_int1_low>;
+ };
+ aw882xx_smartpa@35 {
+ compatible = "awinic,aw882xx_smartpa";
+ reg = <0x35>;
+ reset-gpio = <&tlmm 47 0>;
+ irq-gpio = <&tlmm 11 0x2008>;
+ monitor-flag = <1>;
+ sync-flag = <0>;
+ monitor-timer-val = <3000>;
+ aw-cali-mode = "aw_misc";
+ sound-channel = "right";
+ aw-stereo-cali;
+ status = "okay";
+ pinctrl-names = "aw_reset_low",
+ "aw_reset_high",
+ "aw_irq_active";
+ pinctrl-0 = <&aw_reset2_low>;
+ pinctrl-1 = <&aw_reset2_high>;
+ pinctrl-2 = <&aw_int2_low>;
+ };
+};
+&dai_mi2s4 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&lpi_i2s1_sck_active &lpi_i2s1_ws_active
+ &lpi_i2s1_sd0_active &lpi_i2s1_sd1_active>;
+ pinctrl-1 = <&lpi_i2s1_sck_sleep &lpi_i2s1_ws_sleep
+ &lpi_i2s1_sd0_sleep &lpi_i2s1_sd1_sleep>;
+};
+
+&tlmm {
+
+ fp4_board_id {
+ fp4_board_id_default: fp4_board_id_default{
+ mux {
+ pins = "gpio2", "gpio45", "gpio74";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio2", "gpio45", "gpio74";
+ drive-strength = <2>; /* 2 mA */
+ input-enable;
+ bias-disable;
+ };
+ };
+ };
+
+ aw_reset_int1: aw_reset_int1 {
+ aw_reset1_low: reset_low {
+ mux {
+ pins = "gpio12";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio12";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+ aw_reset1_high: reset_high {
+ mux {
+ pins = "gpio12";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio12";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+ aw_int1_low: int_low {
+ mux {
+ pins = "gpio48";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio48";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+ };
+ };
+ aw_reset_int2: aw_reset_int2 {
+ aw_reset2_low: reset_low {
+ mux {
+ pins = "gpio47";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio47";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+ aw_reset2_high: reset_high {
+ mux {
+ pins = "gpio47";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio47";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+ aw_int2_low: int_low {
+ mux {
+ pins = "gpio11";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio11";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+ };
+ };
+
+ /* hac pa enable pins*/
+ cdc_hac_pa_enable_gpio {
+ hac_pa_active:hac_pa_active {
+ mux {
+ pins = "gpio91";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio91";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ hac_pa_sleep: hac_pa_sleep {
+ mux {
+ pins = "gpio91";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio91";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+ };
+ npi_down_default: npi_down_default {
+ mux {
+ pins = "gpio87";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio87";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-up;
+ };
+ };
+};
+
+&soc {
+
+ fp4_board_id{
+ compatible = "qcom,fp4-board-id";
+ qcom,board-id0-gpio = <&tlmm 2 0>;
+ qcom,board-id1-gpio = <&tlmm 45 0>;
+ qcom,board-id2-gpio = <&tlmm 74 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fp4_board_id_default>;
+ };
+
+ cdc_hac_pa_gpio: msm_cdc_pinctrl_hac_pa_gpio {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&hac_pa_active>;
+ pinctrl-1 = <&hac_pa_sleep>;
+ };
+
+
+ esim-power{
+ compatible = "qcom,esim-power";
+ esim-power {
+ esim_regulator-supply = <&L5E>;
+ };
+ };
+
+ fingerprint_gpio {
+ compatible = "qcom,fingerprint-gpio";
+ interrupt-parent = <&tlmm>;
+ interrupts = <17 0x0>;
+ fp-gpio-reset = <&tlmm 18 0x00>;
+ fp-gpio-int = <&tlmm 17 0x00>;
+ fp-gpio-power = <&tlmm 84 0x00>;
+ };
+ npi_down{
+ compatible = "qcom,npi-down-status";
+ qcom,npi-down-en-pin = <&pm6350_gpios 6 0>;
+ qcom,npi-down-gpio = <&tlmm 87 0x0>;
+ pinctrl-names = "default", "suspend";
+ pinctrl-0 = <&npi_down_default &npi_down_en_pin_default>;
+ pinctrl-1 = <&npi_down_default &npi_down_en_pin_suspend>;
+ };
+};
+
+&pm6350_gpios{
+ npi_down {
+ npi_down_en_pin_default: npi_down_en_pin_default {
+ pins = "gpio6";
+ function = "normal";
+ output-high;
+ power-source = <0>;
+ };
+
+ npi_down_en_pin_suspend: npi_down_en_pin_suspend {
+ pins = "gpio6";
+ function = "normal";
+ input-enable;
+ power-source = <0>;
+ };
+ };
+};
+
+&qupv3_se10_i2c
+{
+ status = "ok";
+
+ aw8695_haptic@5A {
+ compatible = "awinic,aw8695_haptic";
+ reg = <0x5A>;
+ reset-gpio = <&tlmm 90 0>;
+ irq-gpio = <&tlmm 85 0>;
+ vib_mode = < 0 >; /*mode: RAM mode->0; CONT mode -> 1*/
+ vib_f0_pre = < 2350 >;
+ vib_f0_cali_percen = < 7 >;
+ vib_cont_drv_lev = < 125 >;
+ vib_cont_drv_lvl_ov = < 155 >;
+ vib_cont_td = < 0x006c >;
+ vib_cont_zc_thr = < 0x0ff1 >; /*hq 0x08F8 */
+ vib_cont_num_brk = < 3 >;
+ vib_f0_coeff = < 260 >; /*Don't modify it 2.604167*/
+ vib_f0_trace_parameter = < 0x05 0x03 0x02 0x0f >;
+ vib_bemf_config = < 0x10 0x08 0x03 0xf8 >;
+ vib_sw_brake = < 0x2c >;
+ vib_tset = < 0x12 >;
+ vib_r_spare = < 0x68 >;
+ vib_bstdbg = < 0x30 0xeb 0xd4 0 0 0 >;
+ status = "okay";
+ };
+};
+
+//qupv3_se2_spi
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-gdsc.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-gdsc.dtsi
new file mode 100755
index 0000000..622945e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-gdsc.dtsi
@@ -0,0 +1,148 @@
+&soc {
+ /* GDSCs in GCC */
+ gcc_ufs_phy_gdsc: qcom,gdsc@13a004 {
+ compatible = "qcom,gdsc";
+ reg = <0x13a004 0x4>;
+ regulator-name = "gcc_ufs_phy_gdsc";
+ status = "disabled";
+ };
+
+ gcc_usb30_prim_gdsc: qcom,gdsc@11a004 {
+ compatible = "qcom,gdsc";
+ reg = <0x11a004 0x4>;
+ regulator-name = "gcc_usb30_prim_gdsc";
+ status = "disabled";
+ };
+
+ hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@1b7040 {
+ compatible = "qcom,gdsc";
+ reg = <0x1b7040 0x4>;
+ regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ hlos1_vote_mmnoc_mmu_tbu_sf_gdsc: qcom,gdsc@1b7044 {
+ compatible = "qcom,gdsc";
+ reg = <0x1b7044 0x4>;
+ regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf_gdsc";
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ /* GDSCs in CAMCC */
+ cam_cc_bps_gdsc: qcom,gdsc@ad06004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad06004 0x4>;
+ regulator-name = "cam_cc_bps_gdsc";
+ status = "disabled";
+ };
+
+ cam_cc_ife_0_gdsc: qcom,gdsc@ad09004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad09004 0x4>;
+ regulator-name = "cam_cc_ife_0_gdsc";
+ status = "disabled";
+ };
+
+ cam_cc_ife_1_gdsc: qcom,gdsc@ad0a004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad0a004 0x4>;
+ regulator-name = "cam_cc_ife_1_gdsc";
+ status = "disabled";
+ };
+
+ cam_cc_ife_2_gdsc: qcom,gdsc@ad0b004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad0b004 0x4>;
+ regulator-name = "cam_cc_ife_2_gdsc";
+ status = "disabled";
+ };
+
+ cam_cc_ipe_0_gdsc: qcom,gdsc@ad07004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad07004 0x4>;
+ regulator-name = "cam_cc_ipe_0_gdsc";
+ status = "disabled";
+ };
+
+ cam_cc_titan_top_gdsc: qcom,gdsc@ad14004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad14004 0x4>;
+ regulator-name = "cam_cc_titan_top_gdsc";
+ status = "disabled";
+ };
+
+ /* GDSCs in DISPCC */
+ mdss_core_gdsc: qcom,gdsc@af01004 {
+ compatible = "qcom,gdsc";
+ reg = <0xaf01004 0x4>;
+ regulator-name = "mdss_core_gdsc";
+ qcom,support-hw-trigger;
+ proxy-supply = <&mdss_core_gdsc>;
+ qcom,proxy-consumer-enable;
+ status = "disabled";
+ };
+
+ /* GDSCs in GPUCC */
+ gpu_gx_domain_addr: syscon@3d91508 {
+ compatible = "syscon";
+ reg = <0x3d91508 0x4>;
+ };
+
+ gpu_gx_sw_reset: syscon@3d91008 {
+ compatible = "syscon";
+ reg = <0x3d91008 0x4>;
+ };
+
+ gpu_cx_hw_ctrl: syscon@3d91540 {
+ compatible = "syscon";
+ reg = <0x3d91540 0x4>;
+ };
+
+ gpu_cx_gdsc: qcom,gdsc@3d9106c {
+ compatible = "qcom,gdsc";
+ reg = <0x3d9106c 0x4>;
+ regulator-name = "gpu_cx_gdsc";
+ hw-ctl-addr = <&gpu_cx_hw_ctrl>;
+ qcom,no-status-check-on-disable;
+ qcom,clk-dis-wait-val = <8>;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ gpu_gx_gdsc: qcom,gdsc@3d9100c {
+ compatible = "qcom,gdsc";
+ reg = <0x3d9100c 0x4>;
+ regulator-name = "gpu_gx_gdsc";
+ sw-reset = <&gpu_gx_sw_reset>;
+ domain-addr = <&gpu_gx_domain_addr>;
+ qcom,skip-disable-before-sw-enable;
+ status = "disabled";
+ };
+
+ /* GDSCs in NPUCC */
+ npu_cc_core_gdsc: qcom,gdsc@9981004 {
+ compatible = "qcom,gdsc";
+ reg = <0x9981004 0x4>;
+ regulator-name = "npu_cc_core_gdsc";
+ status = "disabled";
+ };
+
+ /* GDSCs in VIDEOCC */
+ video_cc_mvs0_gdsc: qcom,gdsc@aaf3004 {
+ compatible = "qcom,gdsc";
+ reg = <0xaaf3004 0x4>;
+ regulator-name = "video_cc_mvs0_gdsc";
+ status = "disabled";
+ };
+
+ video_cc_mvsc_gdsc: qcom,gdsc@aaf2004 {
+ compatible = "qcom,gdsc";
+ reg = <0xaaf2004 0x4>;
+ regulator-name = "video_cc_mvsc_gdsc";
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-gpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-gpu.dtsi
new file mode 100755
index 0000000..1664a4d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-gpu.dtsi
@@ -0,0 +1,630 @@
+#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
+#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
+
+&soc {
+
+ pil_gpu: qcom,kgsl-hyp {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <13>;
+ qcom,firmware-name = "a615_zap";
+ };
+
+ msm_bus: qcom,kgsl-busmon {
+ label = "kgsl-busmon";
+ compatible = "qcom,kgsl-busmon";
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
+ gpubw: qcom,gpubw {
+ compatible = "qcom,devbw";
+ governor = "bw_vbif";
+ qcom,src-dst-ports = <26 512>;
+ operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-850000000 {
+ opp-hz = /bits/ 64 <850000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-565000000 {
+ opp-hz = /bits/ 64 <565000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-430000000 {
+ opp-hz = /bits/ 64 <430000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-355000000 {
+ opp-hz = /bits/ 64 <355000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-253000000 {
+ opp-hz = /bits/ 64 <253000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+
+ msm_gpu: qcom,kgsl-3d0@3d00000 {
+ label = "kgsl-3d0";
+ compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
+ status = "ok";
+ reg = <0x3d00000 0x40000>,
+ <0x3d61000 0x800>,
+ <0x3d9e000 0x1000>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_dbgc", "cx_misc";
+ interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+ qcom,id = <0>;
+
+ qcom,chipid = <0x06010900>;
+
+ qcom,gpu-quirk-hfi-use-reg;
+ qcom,gpu-quirk-secvid-set-once;
+
+ /* <HZ/12> */
+ qcom,idle-timeout = <80>;
+ qcom,no-nap;
+
+ qcom,highest-bank-bit = <14>;
+ qcom,min-access-length = <32>;
+ qcom,ubwc-mode = <2>;
+
+ /* size in bytes */
+ qcom,snapshot-size = <0x200000>;
+
+ clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>;
+
+ clock-names = "core_clk", "rbbmtimer_clk", "mem_clk",
+ "mem_iface_clk", "gmu_clk";
+
+ /* QDSS_STM base addr, size */
+ qcom,gpu-qdss-stm = <0x161c0000 0x40000>;
+
+ #cooling-cells = <2>;
+ qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";
+
+ /* Bus Scale Settings */
+ qcom,gpubw-dev = <&gpubw>;
+ qcom,bus-control;
+ qcom,msm-bus,name = "grp3d";
+ qcom,msm-bus,num-cases = <13>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <26 512 0 0>,
+ <26 512 0 400000>, /* 1 bus=100 */
+ <26 512 0 800000>, /* 2 bus=200 */
+ <26 512 0 1200000>, /* 3 bus=300 */
+ <26 512 0 1804800>, /* 4 bus=451 */
+ <26 512 0 2188000>, /* 5 bus=547 */
+ <26 512 0 2724000>, /* 6 bus=681 */
+ <26 512 0 3072000>, /* 7 bus=768 */
+ <26 512 0 4068000>, /* 8 bus=1017 */
+ <26 512 0 5412000>, /* 9 bus=1353 */
+ <26 512 0 6220000>, /* 10 bus=1555 */
+ <26 512 0 7216000>, /* 11 bus=1804 */
+ <26 512 0 8371200>; /* 12 bus=2092 */
+
+ /* GDSC regulator names */
+ regulator-names = "vddcx", "vdd";
+ /* GDSC oxili regulators */
+ vddcx-supply = <&gpu_cx_gdsc>;
+ vdd-supply = <&gpu_gx_gdsc>;
+
+ nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>;
+ nvmem-cell-names = "speed_bin", "gaming_bin";
+
+ /* CPU latency parameter */
+ qcom,pm-qos-active-latency = <67>;
+ qcom,pm-qos-wakeup-latency = <67>;
+
+ /* Enable context aware freq. scaling */
+ qcom,enable-ca-jump;
+ /* Context aware jump busy penalty in us */
+ qcom,ca-busy-penalty = <12000>;
+
+ /* GPU OPP data */
+ operating-points-v2 = <&gpu_opp_table>;
+
+ /* GPU Mempools */
+ qcom,gpu-mempools {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,gpu-mempools";
+
+ /* 4K Page Pool configuration */
+ qcom,gpu-mempool@0 {
+ reg = <0>;
+ qcom,mempool-page-size = <4096>;
+ qcom,mempool-allocate;
+ };
+ /* 8K Page Pool configuration */
+ qcom,gpu-mempool@1 {
+ reg = <1>;
+ qcom,mempool-page-size = <8192>;
+ qcom,mempool-allocate;
+ };
+ /* 64K Page Pool configuration */
+ qcom,gpu-mempool@2 {
+ reg = <2>;
+ qcom,mempool-page-size = <65536>;
+ qcom,mempool-reserved = <256>;
+ };
+ /* 1M Page Pool configuration */
+ qcom,gpu-mempool@3 {
+ reg = <3>;
+ qcom,mempool-page-size = <1048576>;
+ qcom,mempool-reserved = <32>;
+ };
+ };
+
+ /*
+ * Speed-bin zero is default speed bin.
+ * For rest of the speed bins, speed-bin value
+ * is calulated as FMAX/4.8 MHz (round up to zero
+ * decimal places) + 2.
+ */
+ qcom,gpu-pwrlevel-bins {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible="qcom,gpu-pwrlevel-bins";
+
+ qcom,gpu-pwrlevels-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,speed-bin = <0>;
+ qcom,ca-target-pwrlevel = <5>;
+ qcom,initial-pwrlevel = <6>;
+
+ /* TURBO_L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <850000000>;
+ qcom,bus-freq = <12>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <12>;
+ };
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <800000000>;
+ qcom,bus-freq = <12>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <12>;
+ };
+
+ /* NOM_L1 */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <650000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <10>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <565000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <430000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <355000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <253000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <7>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,speed-bin = <180>;
+ qcom,ca-target-pwrlevel = <5>;
+ qcom,initial-pwrlevel = <6>;
+
+ /* TURBO_L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <850000000>;
+ qcom,bus-freq = <12>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <12>;
+ };
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <800000000>;
+ qcom,bus-freq = <12>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <12>;
+ };
+
+ /* NOM_L1 */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <650000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <10>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <565000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <430000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <355000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <253000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <7>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,speed-bin = <169>;
+ qcom,ca-target-pwrlevel = <4>;
+ qcom,initial-pwrlevel = <5>;
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <800000000>;
+ qcom,bus-freq = <12>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <12>;
+ };
+
+ /* NOM_L1 */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <650000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <10>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <565000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <430000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <355000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <253000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <7>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+
+ qcom,gpu-pwrlevels-3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,speed-bin = <120>;
+ qcom,ca-target-pwrlevel = <2>;
+ qcom,initial-pwrlevel = <3>;
+
+ /* NOM */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <565000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <11>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <430000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <355000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <253000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <7>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,speed-bin = <138>;
+ qcom,ca-target-pwrlevel = <3>;
+ qcom,initial-pwrlevel = <4>;
+
+ /* NOM_L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <650000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <12>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <565000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <11>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <430000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <355000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <253000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <7>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+ };
+
+ qcom,cpu-to-gpu-cfg-path {
+ qcom,msm-bus,name = "gpu_cfg";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 598 0 0>, // off
+ <1 598 0 100>, // min freq
+ <1 598 0 9999999>; // max freq
+ };
+ };
+
+ kgsl_msm_iommu: qcom,kgsl-iommu@3d40000 {
+ compatible = "qcom,kgsl-smmu-v2";
+
+ reg = <0x3d40000 0x10000>;
+ qcom,protect = <0x40000 0x10000>;
+ qcom,micro-mmu-control = <0x6000>;
+
+ clocks = <&gcc GCC_GPU_CFG_AHB_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+
+ clock-names = "iface_clk", "mem_clk", "mem_iface_clk";
+
+ qcom,secure_align_mask = <0xfff>;
+ qcom,retention;
+ qcom,hyp_secure_alloc;
+
+ gfx3d_user: gfx3d_user {
+ compatible = "qcom,smmu-kgsl-cb";
+ label = "gfx3d_user";
+ iommus = <&kgsl_smmu 0>;
+ qcom,iommu-dma = "disabled";
+ qcom,gpu-offset = <0x48000>;
+ };
+
+ gfx3d_secure: gfx3d_secure {
+ compatible = "qcom,smmu-kgsl-cb";
+ qcom,iommu-dma = "disabled";
+ iommus = <&kgsl_smmu 2>;
+ };
+ };
+
+ gmu: qcom,gmu@3d6a000 {
+ label = "kgsl-gmu";
+ compatible = "qcom,gpu-gmu";
+
+ reg = <0x3d6a000 0x31000>,
+ <0xb290000 0x10000>,
+ <0xb490000 0x10000>;
+ reg-names = "kgsl_gmu_reg",
+ "kgsl_gmu_pdc_cfg",
+ "kgsl_gmu_pdc_seq";
+
+ interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
+ <0 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";
+
+ qcom,msm-bus,name = "cnoc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <26 10036 0 0>, /* CNOC off */
+ <26 10036 0 100>; /* CNOC on */
+
+ regulator-names = "vddcx", "vdd";
+ vddcx-supply = <&gpu_cx_gdsc>;
+ vdd-supply = <&gpu_gx_gdsc>;
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+
+ clock-names = "gmu_clk", "cxo_clk", "axi_clk",
+ "memnoc_clk";
+
+ gmu_user: gmu_user {
+ compatible = "qcom,smmu-gmu-user-cb";
+ iommus = <&kgsl_smmu 4>;
+ qcom,iommu-dma = "disabled";
+ };
+
+ gmu_kernel: gmu_kernel {
+ compatible = "qcom,smmu-gmu-kernel-cb";
+ iommus = <&kgsl_smmu 5>;
+ qcom,iommu-dma = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-ion.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-ion.dtsi
new file mode 100755
index 0000000..9942c82
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-ion.dtsi
@@ -0,0 +1,44 @@
+&soc {
+ qcom,ion {
+ compatible = "qcom,msm-ion";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ system_heap: qcom,ion-heap@25 {
+ reg = <25>;
+ qcom,ion-heap-type = "SYSTEM";
+ };
+
+ system_secure_heap: qcom,ion-heap@9 {
+ reg = <9>;
+ qcom,ion-heap-type = "SYSTEM_SECURE";
+ };
+
+ qcom,ion-heap@27 { /* QSEECOM HEAP */
+ reg = <27>;
+ memory-region = <&qseecom_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@19 { /* QSEECOM TA HEAP */
+ reg = <19>;
+ memory-region = <&qseecom_ta_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */
+ reg = <14>;
+ qcom,ion-heap-type = "SECURE_CARVEOUT";
+ cdsp {
+ memory-region = <&cdsp_sec_mem>;
+ token = <0x20000000>;
+ };
+ };
+
+ qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */
+ reg = <10>;
+ memory-region = <&secure_display_memory>;
+ qcom,ion-heap-type = "HYP_CMA";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-lpi.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-lpi.dtsi
new file mode 100755
index 0000000..d7b1af6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-lpi.dtsi
@@ -0,0 +1,1717 @@
+&q6core {
+ lpi_tlmm: lpi_pinctrl@33c0000 {
+ compatible = "qcom,lpi-pinctrl";
+ reg = <0x33c0000 0x0>;
+ qcom,slew-reg = <0x355a000 0x0>;
+ qcom,num-gpios = <15>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
+ <0x00002000>, <0x00003000>,
+ <0x00004000>, <0x00005000>,
+ <0x00006000>, <0x00007000>,
+ <0x00008000>, <0x00009000>,
+ <0x0000A000>, <0x0000B000>,
+ <0x0000C000>, <0x0000D000>,
+ <0x0000E000>;
+ qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>,
+ <0x00000004>, <0x00000008>,
+ <0x0000000A>, <0x0000000C>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000010>, <0x00000012>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>;
+ qcom,lpi-slew-base-tbl = <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x0355C000>;
+
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+
+ quat_mi2s_sck {
+ quat_mi2s_sck_sleep: quat_mi2s_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sck_active: quat_mi2s_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_ws {
+ quat_mi2s_ws_sleep: quat_mi2s_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_ws_active: quat_mi2s_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd0 {
+ quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd0_active: quat_mi2s_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd1 {
+ quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd1_active: quat_mi2s_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd2 {
+ quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd2_active: quat_mi2s_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd3 {
+ quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd3_active: quat_mi2s_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sck {
+ lpi_i2s1_sck_sleep: lpi_i2s1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sck_active: lpi_i2s1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_ws {
+ lpi_i2s1_ws_sleep: lpi_i2s1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_ws_active: lpi_i2s1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sd0 {
+ lpi_i2s1_sd0_sleep: lpi_i2s1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sd0_active: lpi_i2s1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sd1 {
+ lpi_i2s1_sd1_sleep: lpi_i2s1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sd1_active: lpi_i2s1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sck {
+ lpi_i2s2_sck_sleep: lpi_i2s2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sck_active: lpi_i2s2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_ws {
+ lpi_i2s2_ws_sleep: lpi_i2s2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_ws_active: lpi_i2s2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sd0 {
+ lpi_i2s2_sd0_sleep: lpi_i2s2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sd0_active: lpi_i2s2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sd1 {
+ lpi_i2s2_sd1_sleep: lpi_i2s2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sd1_active: lpi_i2s2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sck {
+ quat_tdm_sck_sleep: quat_tdm_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sck_active: quat_tdm_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_ws {
+ quat_tdm_ws_sleep: quat_tdm_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_ws_active: quat_tdm_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd0 {
+ quat_tdm_sd0_sleep: quat_tdm_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd0_active: quat_tdm_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd1 {
+ quat_tdm_sd1_sleep: quat_tdm_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd1_active: quat_tdm_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd2 {
+ quat_tdm_sd2_sleep: quat_tdm_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd2_active: quat_tdm_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd3 {
+ quat_tdm_sd3_sleep: quat_tdm_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd3_active: quat_tdm_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sck {
+ lpi_tdm1_sck_sleep: lpi_tdm1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sck_active: lpi_tdm1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_ws {
+ lpi_tdm1_ws_sleep: lpi_tdm1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_ws_active: lpi_tdm1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sd0 {
+ lpi_tdm1_sd0_sleep: lpi_tdm1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sd0_active: lpi_tdm1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sd1 {
+ lpi_tdm1_sd1_sleep: lpi_tdm1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sd1_active: lpi_tdm1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sck {
+ lpi_tdm2_sck_sleep: lpi_tdm2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sck_active: lpi_tdm2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_ws {
+ lpi_tdm2_ws_sleep: lpi_tdm2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_ws_active: lpi_tdm2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sd0 {
+ lpi_tdm2_sd0_sleep: lpi_tdm2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sd0_active: lpi_tdm2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sd1 {
+ lpi_tdm2_sd1_sleep: lpi_tdm2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sd1_active: lpi_tdm2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sck {
+ quat_aux_sck_sleep: quat_aux_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sck_active: quat_aux_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_ws {
+ quat_aux_ws_sleep: quat_aux_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_ws_active: quat_aux_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd0 {
+ quat_aux_sd0_sleep: quat_aux_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd0_active: quat_aux_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd1 {
+ quat_aux_sd1_sleep: quat_aux_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd1_active: quat_aux_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd2 {
+ quat_aux_sd2_sleep: quat_aux_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd2_active: quat_aux_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd3 {
+ quat_aux_sd3_sleep: quat_aux_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd3_active: quat_aux_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sck {
+ lpi_aux1_sck_sleep: lpi_aux1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sck_active: lpi_aux1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_ws {
+ lpi_aux1_ws_sleep: lpi_aux1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_ws_active: lpi_aux1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sd0 {
+ lpi_aux1_sd0_sleep: lpi_aux1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sd0_active: lpi_aux1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sd1 {
+ lpi_aux1_sd1_sleep: lpi_aux1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sd1_active: lpi_aux1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sck {
+ lpi_aux2_sck_sleep: lpi_aux2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sck_active: lpi_aux2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_ws {
+ lpi_aux2_ws_sleep: lpi_aux2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_ws_active: lpi_aux2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sd0 {
+ lpi_aux2_sd0_sleep: lpi_aux2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sd0_active: lpi_aux2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sd1 {
+ lpi_aux2_sd1_sleep: lpi_aux2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sd1_active: lpi_aux2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ wsa_swr_clk_pin {
+ wsa_swr_clk_sleep: wsa_swr_clk_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ wsa_swr_clk_active: wsa_swr_clk_active {
+ mux {
+ pins = "gpio10";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-disable;
+ };
+ };
+ };
+
+ wsa_swr_data_pin {
+ wsa_swr_data_sleep: wsa_swr_data_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ wsa_swr_data_active: wsa_swr_data_active {
+ mux {
+ pins = "gpio11";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+ };
+
+ tx_swr_clk_sleep: tx_swr_clk_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func1";
+ input-enable;
+ bias-pull-down;
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>;
+ };
+ };
+
+ tx_swr_clk_active: tx_swr_clk_active {
+ mux {
+ pins = "gpio0";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-disable;
+ };
+ };
+
+ tx_swr_data1_sleep: tx_swr_data1_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>;
+ input-enable;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_data1_active: tx_swr_data1_active {
+ mux {
+ pins = "gpio1";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_data2_sleep: tx_swr_data2_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ tx_swr_data2_active: tx_swr_data2_active {
+ mux {
+ pins = "gpio2";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_data3_sleep: tx_swr_data3_sleep {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ tx_swr_data3_active: tx_swr_data3_active {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_clk_sleep: rx_swr_clk_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_clk_active: rx_swr_clk_active {
+ mux {
+ pins = "gpio3";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-disable;
+ };
+ };
+
+ rx_swr_data_sleep: rx_swr_data_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_data_active: rx_swr_data_active {
+ mux {
+ pins = "gpio4";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_data1_sleep: rx_swr_data1_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_data1_active: rx_swr_data1_active {
+ mux {
+ pins = "gpio5";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ cdc_dmic01_clk_active: dmic01_clk_active {
+ mux {
+ pins = "gpio6";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic01_clk_sleep: dmic01_clk_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic01_data_active: dmic01_data_active {
+ mux {
+ pins = "gpio7";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic01_data_sleep: dmic01_data_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ cdc_dmic23_clk_active: dmic23_clk_active {
+ mux {
+ pins = "gpio8";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic23_clk_sleep: dmic23_clk_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic23_data_active: dmic23_data_active {
+ mux {
+ pins = "gpio9";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic23_data_sleep: dmic23_data_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ cdc_dmic45_clk_active: dmic45_clk_active {
+ mux {
+ pins = "gpio12";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic45_clk_sleep: dmic45_clk_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic45_data_active: dmic45_data_active {
+ mux {
+ pins = "gpio13";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic45_data_sleep: dmic45_data_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-overlay.dts
new file mode 100755
index 0000000..51c01cf
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lagoon-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lagoon MTP";
+ compatible = "qcom,lagoon-mtp", "qcom,lagoon", "qcom,mtp";
+ qcom,msm-id = <434 0x10000>, <459 0x10000>;
+ qcom,board-id = <8 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-overlay_fp4.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-overlay_fp4.dts
new file mode 100755
index 0000000..6c779af
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-overlay_fp4.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lagoon-fp4.dtsi"
+/ {
+ model = "fp4";
+ compatible = "qcom,lagoon-mtp", "qcom,lagoon", "qcom,mtp";
+ qcom,msm-id = <434 0x10000>, <459 0x10000>;
+ qcom,board-id = <8 0x20>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-overlay_n10.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-overlay_n10.dts
new file mode 100755
index 0000000..6ce97b2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-overlay_n10.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lagoon-n10.dtsi"
+/ {
+ model = "n10";
+ compatible = "qcom,lagoon-mtp", "qcom,lagoon", "qcom,mtp";
+ qcom,msm-id = <434 0x10000>, <459 0x10000>;
+ qcom,board-id = <8 0x10>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-usbc-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-usbc-overlay.dts
new file mode 100755
index 0000000..7eb0528
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-usbc-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lagoon-mtp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lagoon MTP USBC audio";
+ compatible = "qcom,lagoon-mtp", "qcom,lagoon", "qcom,mtp";
+ qcom,msm-id = <434 0x10000>, <459 0x10000>;
+ qcom,board-id = <8 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-usbc.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-usbc.dts
new file mode 100755
index 0000000..bd83392
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-usbc.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "lagoon.dtsi"
+#include "lagoon-mtp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lagoon MTP USBC audio";
+ compatible = "qcom,lagoon-mtp", "qcom,lagoon", "qcom,mtp";
+ qcom,board-id = <8 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-usbc.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-usbc.dtsi
new file mode 100755
index 0000000..464143a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp-usbc.dtsi
@@ -0,0 +1,11 @@
+#include "lagoon-mtp.dtsi"
+
+&soc {
+
+};
+
+&lagoon_snd {
+ qcom,msm-mbhc-usbc-audio-supported = <1>;
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp.dts
new file mode 100755
index 0000000..1f288e8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "lagoon.dtsi"
+#include "lagoon-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lagoon MTP";
+ compatible = "qcom,lagoon-mtp", "qcom,lagoon", "qcom,mtp";
+ qcom,board-id = <8 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp.dtsi
new file mode 100755
index 0000000..720d56e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-mtp.dtsi
@@ -0,0 +1,316 @@
+#include "lagoon-audio-overlay.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include "lagoon-sde-display.dtsi"
+#include "camera/lagoon-camera-sensor-mtp.dtsi"
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include "lagoon-thermal-overlay.dtsi"
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+
+ mtp_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ //#include "qg-batterydata-alium-3600mah.dtsi"
+ //#include "qg-batterydata-atl466271_3300mAh.dtsi"
+ //#include "qg-batterydata-atl436186020H_3780mAh.dtsi"
+ };
+};
+
+&pm6350_gpios {
+ key_vol_up {
+ key_vol_up_default: key_vol_up_default {
+ pins = "gpio2";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+ };
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v3";
+
+ vdda-phy-supply = <&L18A>;
+ vdda-pll-supply = <&L22A>;
+ vdda-phy-max-microamp = <62900>;
+ vdda-pll-max-microamp = <18300>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&L7E>;
+ vcc-voltage-level = <2950000 2960000>;
+ vccq2-supply = <&L12A>;
+ vccq2-voltage-level = <1800000 1800000>;
+ vcc-max-microamp = <800000>;
+ vccq2-min-microamp = <0>;
+ vccq2-max-microamp = <800000>;
+ vccq2-pwr-collapse-sup;
+
+ qcom,vddp-ref-clk-supply = <&L22A>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vddp-ref-clk-min-uV = <1152000>;
+ qcom,vddp-ref-clk-max-uV = <1200000>;
+ status = "ok";
+};
+
+&sdhc_1 {
+ vdd-supply = <&L7E>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L12A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&L9E>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L6E>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&pm6150a_amoled {
+ status = "ok";
+};
+
+&pm7250b_charger {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+ <&pm7250b_vadc ADC_USB_IN_I>,
+ <&pm7250b_vadc ADC_CHG_TEMP>,
+ <&pm7250b_vadc ADC_DIE_TEMP>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+ <&pm7250b_vadc ADC_SBUx>,
+ <&pm7250b_vadc ADC_VPH_PWR>,
+ <&pm7250b_vadc ADC_AMUX_THM1_PU2>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp",
+ "die_temp",
+ "conn_temp",
+ "sbux_res",
+ "vph_voltage",
+ "skin_temp";
+ qcom,battery-data = <&mtp_batterydata>;
+ qcom,sec-charger-config = <1>;
+ qcom,auto-recharge-soc = <98>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ qcom,suspend-input-on-debug-batt;
+ /delete-property/ qcom,fcc-stepping-enable;
+ qcom,fcc-step-delay-ms = <100>;
+ qcom,fcc-step-size-ua = <100000>;
+ qcom,smb-internal-pull-kohm = <0>;
+ qcom,en-skin-therm-mitigation;
+ qcom,hvdcp3-standalone-config;
+};
+
+&pm7250b_qg {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU2>,
+ <&pm7250b_vadc ADC_BAT_ID_PU2>;
+ io-channel-names = "batt-therm",
+ "batt-id";
+ qcom,battery-data = <&mtp_batterydata>;
+ qcom,qg-iterm-ma = <150>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+ qcom,tcss-enable;
+ qcom,fvss-enable;
+ qcom,fvss-vbatt-mv = <3300>;
+ qcom,bass-enable;
+ qcom,use-cp-iin-sns;
+};
+
+&dsi_rm69299_visionox_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_rm69299_visionox_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>;
+};
+
+#include <dt-bindings/clock/qcom,rpmh.h>
+&qupv3_se0_i2c {
+ status = "ok";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ st21nfc@28 {
+ compatible = "st,st21nfc";
+ reg = <0x08>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 0>;
+ reset-gpios = <&tlmm 6 0x00>;
+ irq-gpios = <&tlmm 9 0x00>;
+ clkreq-gpios = <&tlmm 7 0x00>;
+ clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
+ clock-names = "nfc_ref_clk";
+ st,clk_pinctrl;
+ status = "ok";
+ };
+};
+
+&qupv3_se8_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="synaptics,tcm-i2c";
+
+ synaptics_tcm@20 {
+ compatible = "synaptics,tcm-i2c";
+ reg = <0x20>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <22 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&pmx_ts_release>;
+ vdd-supply = <&L11A>;
+ avdd-supply = <&L6A>;
+ synaptics,pwr-reg-name = "avdd";
+ synaptics,bus-reg-name = "vdd";
+ synaptics,irq-gpio = <&tlmm 22 0x2008>;
+ synaptics,irq-on-state = <0>;
+ synaptics,reset-gpio = <&tlmm 21 0x00>;
+ synaptics,reset-on-state = <0>;
+ synaptics,reset-active-ms = <20>;
+ synaptics,reset-delay-ms = <200>;
+ synaptics,power-delay-ms = <200>;
+ synaptics,ubl-i2c-addr = <0x20>;
+ synaptics,extend_report;
+ synaptics,firmware-name = "synaptics_firmware.img";
+
+ panel = <&dsi_rm69299_visionox_amoled_video
+ &dsi_rm69299_visionox_amoled_cmd>;
+ };
+};
+
+&pm7250b_vadc {
+ smb1390_therm@e {
+ qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_SMB1398_TEMP>;
+ };
+};
+
+&pm7250b_gpios {
+ smb_stat {
+ smb_stat_default: smb_stat_default {
+ pins = "gpio6";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+ power-source = <0>;
+ };
+ };
+};
+
+&thermal_zones {
+ quiet-therm-step {
+ status = "disabled";
+ };
+};
+
+&qupv3_se10_i2c {
+ qcom,clk-freq-out = <400000>;
+ status = "ok";
+ #include "smb1398.dtsi"
+};
+
+&smb1396 {
+ interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&spmi_bus>;
+ interrupt-names = "smb1396";
+ pinctrl-names = "default";
+ qcom,enable-toggle-stat;
+ pinctrl-0 = <&smb_stat_default>;
+ status = "ok";
+};
+
+&smb1396_div2_cp_master {
+ io-channels = <&pm7250b_vadc ADC_AMUX_THM2>;
+ qcom,parallel-input-mode = <1>; /* USBIN */
+ qcom,parallel-output-mode = <2>; /* VBAT */
+ qcom,div2-cp-min-ilim-ua = <750000>;
+ status = "ok";
+};
+
+&smb1396_slave {
+ status = "ok";
+};
+
+&smb1396_div2_cp_slave {
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-n10.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-n10.dtsi
new file mode 100644
index 0000000..086fcdc
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-n10.dtsi
@@ -0,0 +1,367 @@
+#include "lagoon-mtp.dtsi"
+#include "dsi-panel-ft8716u-1080p-video.dtsi"
+
+&mtp_batterydata {
+ #include "qg-batterydata-n10-veken-4360mah.dtsi"
+};
+
+
+
+
+&pm7250b_charger {
+ /delete-property/ qcom,fcc-stepping-enable;
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+ <&pm7250b_vadc ADC_USB_IN_I>,
+ <&pm7250b_vadc ADC_CHG_TEMP>,
+ <&pm7250b_vadc ADC_DIE_TEMP>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+ <&pm7250b_vadc ADC_SBUx>,
+ <&pm7250b_vadc ADC_VPH_PWR>,
+ <&pm7250b_vadc ADC_AMUX_THM1_PU2>,
+ <&pm7250b_vadc ADC_INT_EXT_ISENSE_VBAT_VDATA>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp",
+ "die_temp",
+ "conn_temp",
+ "sbux_res",
+ "vph_voltage",
+ "skin_temp",
+ "v_i_int_ext";
+ qcom,battery-data = <&mtp_batterydata>;
+ qcom,fv-max-uv = <4400000>;
+ qcom,fcc-max-ua = <3500000>;
+ qcom,otg-cl-ua = <1500000>;
+ qcom,wls-current-max-ua = <1300000>;
+ qcom,hvdcp2-max-icl-ua = <2000000>;
+ qcom,hvdcp3-max-icl-ua = <2200000>;
+ qcom,qc4-max-icl-ua = <2050000>;
+ qcom,chg-term-src = <1>;
+ qcom,chg-term-current-ma = <(-150)>;
+ qcom,sec-charger-config = <1>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,lpd-disable;
+ qcom,thermal-mitigation = <2000000 2000000 2000000 2000000
+ 1500000 1000000 500000>;
+ qcom,thermal-mitigation-lcdon = <2000000 2000000 2000000 2000000
+ 1500000 1000000 500000>;
+ qcom,disable-suspend-on-collapse;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ qcom,float-option = <2>;
+ qcom,auto-recharge-soc = <99>;
+ qcom,suspend-input-on-debug-batt;
+ //qcom,en-skin-therm-mitigation;
+ qcom,smb-internal-pull-kohm = <0>;
+ qcom,hvdcp-disable;//zxzadd because vbus have ovp ic ,if over 6v vbus will be cut off
+};
+
+&pm7250b_qg {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU1>,
+ <&pm7250b_vadc ADC_BAT_ID_PU2>;
+ qcom,battery-data = <&mtp_batterydata>;
+ qcom,vbatt-empty-mv = <3200>;
+ qcom,vbatt-low-mv = <3500>;
+ qcom,vbatt-cutoff-mv = <3400>;
+ qcom,fvss-vbatt-mv = <3500>;
+ qcom,qg-iterm-ma = <350>;
+ qcom,ignore-shutdown-soc-secs = <604800>;
+ qcom,shutdown-temp-diff = <150>;
+ qcom,shutdown_soc_threshold = <50>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ //qcom,rbat-conn-mohm = <35>;
+ qcom,use-cp-iin-sns;
+};
+
+&smb1396_div2_cp_master {
+ qcom,max-cutoff-soc = <85>;
+};
+
+&smb1396_slave {
+ status = "disabled";
+};
+
+&smb1396_div2_cp_slave {
+ status = "disabled";
+};
+
+&eud {
+ status = "disabled";
+};
+
+&usb_qmp_dp_phy {
+ status = "disabled";
+};
+
+&pm7250b_pdphy {
+ qcom,default-sink-caps = <5000 2000>, /* 5V @ 2A */
+ <9000 1500>, /* 9V @ 1.5A */
+ <10000 1500>; /* 10V @ 1.5A */
+};
+
+&usb0 {
+ extcon = <&pm7250b_pdphy>, <&pm7250b_charger>;
+ dwc3@a600000 {
+ maximum-speed = "high-speed";
+ usb-phy = <&qusb_phy0>, <&usb_nop_phy>;
+ };
+};
+
+&qusb_phy0 {
+ qcom,qusb-phy-init-seq =
+ /* <value reg_offset> */
+ <0x23 0x210 /* PWR_CTRL1 */
+ 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
+ 0x7c 0x18c /* PLL_CLOCK_INVERTERS */
+ 0x80 0x2c /* PLL_CMODE */
+ 0x0a 0x184 /* PLL_LOCK_DELAY */
+ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
+ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */
+ 0x16 0x198 /* PLL_BIAS_CONTROL_2 */
+ 0x21 0x214 /* PWR_CTRL2 */
+ 0x08 0x220 /* IMP_CTRL1 */
+ 0x58 0x224 /* IMP_CTRL2 */
+ 0x47 0x240 /* TUNE1 */
+ 0x29 0x244 /* TUNE2 */
+ 0xca 0x248 /* TUNE3 */
+ 0x04 0x24c /* TUNE4 */
+ 0x03 0x250 /* TUNE5 */
+ 0x30 0x23c /* CHG_CTRL2 */
+ 0x22 0x210>; /* PWR_CTRL1 */
+
+ qcom,qusb-phy-host-init-seq =
+ /* <value reg_offset> */
+ <0x23 0x210 /* PWR_CTRL1 */
+ 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
+ 0x7c 0x18c /* PLL_CLOCK_INVERTERS */
+ 0x80 0x2c /* PLL_CMODE */
+ 0x0a 0x184 /* PLL_LOCK_DELAY */
+ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
+ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */
+ 0x16 0x198 /* PLL_BIAS_CONTROL_2 */
+ 0x21 0x214 /* PWR_CTRL2 */
+ 0x08 0x220 /* IMP_CTRL1 */
+ 0x58 0x224 /* IMP_CTRL2 */
+ 0x47 0x240 /* TUNE1 */
+ 0x29 0x244 /* TUNE2 */
+ 0xca 0x248 /* TUNE3 */
+ 0x04 0x24c /* TUNE4 */
+ 0x03 0x250 /* TUNE5 */
+ 0x30 0x23c /* CHG_CTRL2 */
+ 0x22 0x210>; /* PWR_CTRL1 */
+};
+
+&pm6150l_wled {
+ qcom,string-cfg = <3>;
+ qcom,fs-current-limit = <20000>;
+ status = "okay";
+};
+
+&pm6150l_lcdb {
+ status = "okay";
+};
+
+&pm6150a_amoled {
+ status = "disabled";
+};
+&dsi_ft8716u_1080_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,mdss-brightness-default-level = <167>;
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+ qcom,mdss-dsi-t-clk-post = <0x0e>;
+ qcom,mdss-dsi-t-clk-pre = <0x35>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1C 07 07 23 21 07 07 05 03 04 00];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+
+&sde_dsi {
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+ qcom,dsi-default-panel = <&dsi_ft8716u_1080_video>;
+};
+
+
+&qupv3_se8_i2c {
+
+ qcom,i2c-touch-active = "focaltech,fts";
+ status = "okay";
+ synaptics_tcm@20 {
+ status = "disabled";
+ };
+
+ focaltech@38 {
+ compatible = "focaltech,fts";
+ reg = <0x38>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <22 0x02>;
+ focaltech,reset-gpio = <&tlmm 21 0x01>;
+ focaltech,irq-gpio = <&tlmm 22 0x02>;
+ //vcc_i2c-supply = <&L11A>;
+ //vdd-supply = <&L6A>;
+ //focaltech,irq-on-state = <0>;
+ focaltech,max-touch-number = <10>;
+ focaltech,display-coords = <0 0 1080 1920>;
+ //focaltech,have-key;
+ //focaltech,key-number = <3>;
+ focaltech,keys = <139 102 158>;
+ focaltech,key-y-coord = <2000>;
+ focaltech,key-x-coords = <200 600 800>;
+ //pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ //pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ //pinctrl-2 = <&ts_release>;
+ //focaltech,i2c-pull-up;
+
+ panel = <&dsi_ft8716u_1080_video>;
+
+ };
+};
+
+&lagoon_snd {
+ qcom,model = "lito-lagoon-n10-snd-card";
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
+ qcom,wcn-btfm = <1>;
+ qcom,ext-disp-audio-rx = <0>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic3",
+ "AMIC4", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic4",
+ "TX DMIC0", "MIC BIAS1",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC2", "ADC2_OUTPUT",
+ "TX SWR_ADC3", "ADC3_OUTPUT",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA SWR_ADC0", "VA_SWR_CLK",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_ADC2", "VA_SWR_CLK",
+ "VA SWR_ADC3", "VA_SWR_CLK",
+ "VA SWR_ADC0", "ADC1_OUTPUT",
+ "VA SWR_ADC2", "ADC2_OUTPUT",
+ "VA SWR_ADC3", "ADC3_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ /delete-property/ qcom,cdc-dmic01-gpios;
+ /delete-property/ qcom,cdc-dmic23-gpios;
+ /delete-property/ qcom,cdc-dmic45-gpios;
+ asoc-codec = <&stub_codec>, <&bolero>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec";
+ qcom,wsa-max-devs = <0>;
+ /delete-property/ qcom,wsa-devs;
+ /delete-property/ qcom,wsa-aux-dev-prefix;
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&wcd937x_codec>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>,
+ <&lpi_tlmm>, <&bolero>;
+};
+&wcd937x_codec{
+ status = "ok";
+};
+&wcd938x_codec{
+ status = "disabled";
+};
+&wcd937x_rx_slave {
+ status = "ok";
+};
+
+&wcd937x_tx_slave {
+ status = "ok";
+};
+
+&wcd938x_tx_slave {
+ status = "disabled";
+};
+
+&wcd938x_rx_slave {
+ status = "disabled";
+};
+&cdc_dmic01_gpios{
+ status = "disabled";
+};
+
+&cdc_dmic23_gpios{
+ status = "disabled";
+};
+&cdc_dmic45_gpios{
+ status = "disabled";
+};
+&wsa883x_0221{
+ status = "disabled";
+};
+&wsa883x_0222{
+ status = "disabled";
+};
+
+/*aw881xx I2c is used gpio0 &gpio1 same as nfc in lagoon-pinctrl.dtsi */
+&qupv3_se0_i2c {
+ status = "ok";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ aw881xx_smartpa@34{
+ compatible = "awinic,aw881xx_smartpa";
+ reg = <0x43>;/*Virtual address, real address is 0x34*/
+ reset-gpio = <&tlmm 10 0>;
+ irq-gpio = <&tlmm 11 0>;
+ monitor-flag = <1>;
+ monitor-timer-val = <30000>;
+ status = "okay";
+ };
+};
+&dai_mi2s4 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&lpi_i2s1_sck_active &lpi_i2s1_ws_active
+ &lpi_i2s1_sd0_active &lpi_i2s1_sd1_active>;
+ pinctrl-1 = <&lpi_i2s1_sck_sleep &lpi_i2s1_ws_sleep
+ &lpi_i2s1_sd0_sleep &lpi_i2s1_sd1_sleep>;
+};
+
+&tlmm {
+ bq27541_hdq_active: bq27541_hdq_active{
+ mux {
+ pins = "gpio33";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio33";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+};
+
+&soc {
+ bq27541 {
+ compatible = "qcom,bq27541-fuel-hdq";
+ qcom,hdq-gpio = <&tlmm 33 0>;
+ pinctrl-names = "bq27541_hdq";
+ pinctrl-0 = <&bq27541_hdq_active>;
+ };
+};
\ No newline at end of file
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-npu.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-npu.dtsi
new file mode 100755
index 0000000..e458666
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-npu.dtsi
@@ -0,0 +1,165 @@
+&soc {
+ msm_npu: qcom,msm_npu@9800000 {
+ compatible = "qcom,msm-npu";
+ status = "ok";
+ reg = <0x9900000 0x20000>,
+ <0x99F0000 0x10000>,
+ <0x9980000 0x10000>,
+ <0x17c00000 0x10000>,
+ <0x01F40000 0x40000>,
+ <0x780000 0x7000>;
+ reg-names = "tcm", "core", "cc", "apss_shared", "tcsr",
+ "qfprom_physical";
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 585 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq",
+ "general_irq";
+ iommus = <&apps_smmu 0x1441 0x00>, <&apps_smmu 0x1442 0x00>,
+ <&apps_smmu 0x1461 0x00>, <&apps_smmu 0x1462 0x00>,
+ <&apps_smmu 0x1481 0x00>, <&apps_smmu 0x1482 0x00>;
+ qcom,npu-dsp-sid-mapped;
+
+ clocks = <&npucc NPU_CC_XO_CLK>,
+ <&npucc NPU_CC_CORE_CLK>,
+ <&npucc NPU_CC_CAL_HM0_CLK>,
+ <&npucc NPU_CC_CAL_HM0_CDC_CLK>,
+ <&npucc NPU_CC_NOC_AXI_CLK>,
+ <&npucc NPU_CC_NOC_AHB_CLK>,
+ <&npucc NPU_CC_NOC_DMA_CLK>,
+ <&npucc NPU_CC_RSC_XO_CLK>,
+ <&npucc NPU_CC_S2P_CLK>,
+ <&npucc NPU_CC_BWMON_CLK>,
+ <&npucc NPU_CC_CAL_HM0_PERF_CNT_CLK>,
+ <&npucc NPU_CC_BTO_CORE_CLK>,
+ <&npucc NPU_DSP_CORE_CLK_SRC>;
+ clock-names = "xo_clk",
+ "npu_core_clk",
+ "cal_hm0_clk",
+ "cal_hm0_cdc_clk",
+ "axi_clk",
+ "ahb_clk",
+ "dma_clk",
+ "rsc_xo_clk",
+ "s2p_clk",
+ "bwmon_clk",
+ "cal_hm0_perf_cnt_clk",
+ "bto_core_clk",
+ "dsp_core_clk_src";
+
+ vdd-supply = <&npu_cc_core_gdsc>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,proxy-reg-names ="vdd", "vdd_cx";
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+ #cooling-cells = <2>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_GLINK_QMP>,
+ <&ipcc_mproc IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_SMP2P>,
+ <&ipcc_mproc IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_PING>;
+ mbox-names = "ipcc-glink", "ipcc-smp2p", "ipcc-ping";
+ #mbox-cells = <2>;
+ qcom,npubw-devs = <&npu_npu_llcc_bw &npu_llcc_ddr_bw &npudsp_npu_ddr_bw>;
+ qcom,npubw-dev-names = "npu_llcc_bw", "llcc_ddr_bw", "dsp_ddr_bw";
+ qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>,
+ <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_CLK_CTL>;
+ qcom,npu-cxlimit-enable;
+ qcom,npu-pwrlevels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,npu-pwrlevels";
+ initial-pwrlevel = <4>;
+ qcom,npu-pwrlevel@0 {
+ reg = <0>;
+ vreg = <1>;
+ clk-freq = <19200000
+ 100000000
+ 192000000
+ 192000000
+ 150000000
+ 30000000
+ 200000000
+ 19200000
+ 50000000
+ 19200000
+ 192000000
+ 19200000
+ 300000000>;
+ };
+
+ qcom,npu-pwrlevel@1 {
+ reg = <1>;
+ vreg = <2>;
+ clk-freq = <19200000
+ 200000000
+ 268800000
+ 268800000
+ 200000000
+ 37500000
+ 300000000
+ 19200000
+ 50000000
+ 19200000
+ 268800000
+ 19200000
+ 400000000>;
+ };
+
+ qcom,npu-pwrlevel@2 {
+ reg = <2>;
+ vreg = <3>;
+ clk-freq = <19200000
+ 333000000
+ 403200000
+ 403200000
+ 300000000
+ 37500000
+ 403000000
+ 19200000
+ 50000000
+ 19200000
+ 403200000
+ 19200000
+ 500000000>;
+ };
+
+ qcom,npu-pwrlevel@3 {
+ reg = <3>;
+ vreg = <4>;
+ clk-freq = <19200000
+ 428000000
+ 515000000
+ 515000000
+ 403000000
+ 75000000
+ 600000000
+ 19200000
+ 100000000
+ 19200000
+ 515000000
+ 19200000
+ 660000000>;
+ };
+
+ qcom,npu-pwrlevel@4 {
+ reg = <4>;
+ vreg = <6>;
+ clk-freq = <19200000
+ 500000000
+ 748800000
+ 748800000
+ 533000000
+ 75000000
+ 710000000
+ 19200000
+ 100000000
+ 19200000
+ 748800000
+ 19200000
+ 800000000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-pinctrl.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-pinctrl.dtsi
new file mode 100755
index 0000000..284bc90
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-pinctrl.dtsi
@@ -0,0 +1,1571 @@
+&soc {
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,lagoon-pinctrl";
+ reg = <0x0f100000 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ wakeup-parent = <&pdc>;
+ irqdomain-map = <3 0 &pdc 126 0>,
+ <4 0 &pdc 151 0>,
+ <7 0 &pdc 58 0>,
+ <8 0 &pdc 113 0>,
+ <9 0 &pdc 66 0>,
+ <11 0 &pdc 106 0>,
+ <12 0 &pdc 59 0>,
+ <13 0 &pdc 112 0>,
+ <16 0 &pdc 73 0>,
+ <17 0 &pdc 74 0>,
+ <18 0 &pdc 75 0>,
+ <19 0 &pdc 76 0>,
+ <21 0 &pdc 130 0>,
+ <22 0 &pdc 96 0>,
+ <23 0 &pdc 146 0>,
+ <24 0 &pdc 114 0>,
+ <25 0 &pdc 83 0>,
+ <27 0 &pdc 84 0>,
+ <28 0 &pdc 85 0>,
+ <34 0 &pdc 147 0>,
+ <35 0 &pdc 92 0>,
+ <36 0 &pdc 93 0>,
+ <37 0 &pdc 94 0>,
+ <38 0 &pdc 68 0>,
+ <48 0 &pdc 100 0>,
+ <50 0 &pdc 57 0>,
+ <51 0 &pdc 81 0>,
+ <52 0 &pdc 80 0>,
+ <53 0 &pdc 69 0>,
+ <54 0 &pdc 71 0>,
+ <55 0 &pdc 70 0>,
+ <57 0 &pdc 152 0>,
+ <58 0 &pdc 115 0>,
+ <59 0 &pdc 116 0>,
+ <60 0 &pdc 117 0>,
+ <61 0 &pdc 118 0>,
+ <62 0 &pdc 119 0>,
+ <64 0 &pdc 121 0>,
+ <66 0 &pdc 127 0>,
+ <67 0 &pdc 128 0>,
+ <69 0 &pdc 60 0>,
+ <73 0 &pdc 78 0>,
+ <78 0 &pdc 135 0>,
+ <82 0 &pdc 138 0>,
+ <83 0 &pdc 140 0>,
+ <84 0 &pdc 141 0>,
+ <85 0 &pdc 98 0>,
+ <87 0 &pdc 88 0>,
+ <88 0 &pdc 107 0>,
+ <89 0 &pdc 109 0>,
+ <90 0 &pdc 110 0>,
+ <91 0 &pdc 111 0>,
+ <92 0 &pdc 149 0>,
+ <93 0 &pdc 101 0>,
+ <94 0 &pdc 61 0>,
+ <95 0 &pdc 65 0>,
+ <96 0 &pdc 95 0>,
+ <97 0 &pdc 72 0>,
+ <98 0 &pdc 145 0>,
+ <99 0 &pdc 150 0>,
+ <100 0 &pdc 108 0>,
+ <104 0 &pdc 129 0>,
+ <107 0 &pdc 131 0>,
+ <110 0 &pdc 132 0>,
+ <112 0 &pdc 133 0>,
+ <114 0 &pdc 134 0>,
+ <116 0 &pdc 136 0>,
+ <118 0 &pdc 137 0>,
+ <122 0 &pdc 97 0>,
+ <123 0 &pdc 99 0>,
+ <124 0 &pdc 148 0>,
+ <125 0 &pdc 82 0>,
+ <128 0 &pdc 144 0>,
+ <129 0 &pdc 86 0>,
+ <131 0 &pdc 87 0>,
+ <133 0 &pdc 142 0>,
+ <134 0 &pdc 143 0>,
+ <136 0 &pdc 102 0>,
+ <137 0 &pdc 91 0>,
+ <138 0 &pdc 77 0>,
+ <139 0 &pdc 79 0>,
+ <140 0 &pdc 90 0>,
+ <142 0 &pdc 103 0>,
+ <144 0 &pdc 105 0>,
+ <147 0 &pdc 104 0>,
+ <153 0 &pdc 120 0>,
+ <155 0 &pdc 67 0>;
+ irqdomain-map-mask = <0xff 0>;
+ irqdomain-map-pass-thru = <0 0xff>;
+
+ trigout_a: trigout_a {
+ mux {
+ pins = "gpio87";
+ function = "qdss_cti";
+ };
+
+ config {
+ pins = "gpio87";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ ufs_dev_reset_assert: ufs_dev_reset_assert {
+ config {
+ pins = "ufs_reset";
+ bias-pull-down; /* default: pull down */
+ /*
+ * UFS_RESET driver strengths are having
+ * different values/steps compared to typical
+ * GPIO drive strengths.
+ *
+ * Following table clarifies:
+ *
+ * HDRV value | UFS_RESET | Typical GPIO
+ * (dec) | (mA) | (mA)
+ * 0 | 0.8 | 2
+ * 1 | 1.55 | 4
+ * 2 | 2.35 | 6
+ * 3 | 3.1 | 8
+ * 4 | 3.9 | 10
+ * 5 | 4.65 | 12
+ * 6 | 5.4 | 14
+ * 7 | 6.15 | 16
+ *
+ * POR value for UFS_RESET HDRV is 3 which means
+ * 3.1mA and we want to use that. Hence just
+ * specify 8mA to "drive-strength" binding and
+ * that should result into writing 3 to HDRV
+ * field.
+ */
+ drive-strength = <8>; /* default: 3.1 mA */
+ output-low; /* active low reset */
+ };
+ };
+
+ ufs_dev_reset_deassert: ufs_dev_reset_deassert {
+ config {
+ pins = "ufs_reset";
+ bias-pull-down; /* default: pull down */
+ /*
+ * default: 3.1 mA
+ * check comments under ufs_dev_reset_assert
+ */
+ drive-strength = <8>;
+ output-high; /* active low reset */
+ };
+ };
+#if 0 // MODIFIED by yixiang.wu, 2021-01-05,BUG-10277816
+ qupv3_se7_2uart_pins: qupv3_se7_2uart_pins {
+ qupv3_se7_2uart_active: qupv3_se7_2uart_active {
+ mux {
+ pins = "gpio27", "gpio28";
+ function = "qup11";
+ };
+
+ config {
+ pins = "gpio27", "gpio28";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se7_2uart_sleep: qupv3_se7_2uart_sleep {
+ mux {
+ pins = "gpio27", "gpio28";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio27", "gpio28";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+#endif // MODIFIED by yixiang.wu, 2021-01-05,BUG-10277816
+ qupv3_se9_2uart_pins: qupv3_se9_2uart_pins {
+ qupv3_se9_2uart_active: qupv3_se9_2uart_active {
+ mux {
+ pins = "gpio25", "gpio26";
+ function = "qup13_f2";
+ };
+
+ config {
+ pins = "gpio25", "gpio26";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep {
+ mux {
+ pins = "gpio25", "gpio26";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio25", "gpio26";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ qupv3_se1_4uart_pins: qupv3_se1_4uart_pins {
+ qupv3_se1_default_ctsrtsrx: qupv3_se1_default_ctsrtsrx {
+ mux {
+ pins = "gpio61", "gpio62", "gpio64";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio61", "gpio62", "gpio64";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ qupv3_se1_default_tx: qupv3_se1_default_tx {
+ mux {
+ pins = "gpio63";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio63";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se1_ctsrx: qupv3_se1_ctsrx {
+ mux {
+ pins = "gpio61", "gpio64";
+ function = "qup01";
+ };
+
+ config {
+ pins = "gpio61", "gpio64";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se1_rts: qupv3_se1_rts {
+ mux {
+ pins = "gpio62";
+ function = "qup01";
+ };
+
+ config {
+ pins = "gpio62";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ qupv3_se1_tx: qupv3_se1_tx {
+ mux {
+ pins = "gpio63";
+ function = "qup01";
+ };
+
+ config {
+ pins = "gpio63";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
+ qupv3_se0_i2c_active: qupv3_se0_i2c_active {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "qup00";
+ };
+
+ config {
+ pins = "gpio0", "gpio1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio0", "gpio1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ nfc {
+ nfc_int_active: nfc_int_active {
+ /* active state */
+ mux {
+ /* GPIO 9 NFC Read Interrupt */
+ pins = "gpio9";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_int_suspend: nfc_int_suspend {
+ /* sleep state */
+ mux {
+ /* GPIO 9 NFC Read Interrupt */
+ pins = "gpio9";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_enable_active: nfc_enable_active {
+ /* active state */
+ mux {
+ /* 6: Enable 8: Firmware */
+ pins = "gpio6", "gpio8";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6", "gpio8";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_enable_suspend: nfc_enable_suspend {
+ /* sleep state */
+ mux {
+ /* 6: Enable 8: Firmware */
+ pins = "gpio6", "gpio8";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6", "gpio8";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable;
+ };
+ };
+
+ nfc_clk_req_active: nfc_clk_req_active {
+ /* active state */
+ mux {
+ /* GPIO 7: NFC CLOCK REQUEST */
+ pins = "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_clk_req_suspend: nfc_clk_req_suspend {
+ /* sleep state */
+ mux {
+ /* GPIO 7: NFC CLOCK REQUEST */
+ pins = "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
+ qupv3_se2_i2c_active: qupv3_se2_i2c_active {
+ mux {
+ pins = "gpio45", "gpio46";
+ function = "qup02";
+ };
+
+ config {
+ pins = "gpio45", "gpio46";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
+ mux {
+ pins = "gpio45", "gpio46";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio45", "gpio46";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
+ qupv3_se6_i2c_active: qupv3_se6_i2c_active {
+ mux {
+ pins = "gpio13", "gpio14";
+ function = "qup10";
+ };
+
+ config {
+ pins = "gpio13", "gpio14";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
+ mux {
+ pins = "gpio13", "gpio14";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio13", "gpio14";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
+ qupv3_se7_i2c_active: qupv3_se7_i2c_active {
+ mux {
+ pins = "gpio27", "gpio28";
+ function = "qup11";
+ };
+
+ config {
+ pins = "gpio27", "gpio28";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
+ mux {
+ pins = "gpio27", "gpio28";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio27", "gpio28";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
+ qupv3_se8_i2c_active: qupv3_se8_i2c_active {
+ mux {
+ pins = "gpio19", "gpio20";
+ function = "qup12";
+ };
+
+ config {
+ pins = "gpio19", "gpio20";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
+ mux {
+ pins = "gpio19", "gpio20";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio19", "gpio20";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
+ qupv3_se10_i2c_active: qupv3_se10_i2c_active {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "qup14";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se0_spi_pins: qupv3_se0_spi_pins {
+ qupv3_se0_spi_active: qupv3_se0_spi_active {
+ mux {
+ pins = "gpio2";
+ function = "qup00";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
+ mux {
+ pins = "gpio2";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se2_spi_pins: qupv3_se2_spi_pins {
+ qupv3_se2_spi_active: qupv3_se2_spi_active {
+ mux {
+ pins = "gpio45", "gpio46",
+ "gpio56", "gpio57";
+ function = "qup02";
+ };
+
+ config {
+ pins = "gpio45", "gpio46",
+ "gpio56", "gpio57";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
+ mux {
+ pins = "gpio45", "gpio46",
+ "gpio56", "gpio57";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio45", "gpio46",
+ "gpio56", "gpio57";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se6_spi_pins: qupv3_se6_spi_pins {
+ qupv3_se6_spi_active: qupv3_se6_spi_active {
+ mux {
+ pins = "gpio13", "gpio14",
+ "gpio15", "gpio16";
+ function = "qup10";
+ };
+
+ config {
+ pins = "gpio13", "gpio14",
+ "gpio15", "gpio16";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
+ mux {
+ pins = "gpio13", "gpio14",
+ "gpio15", "gpio16";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio13", "gpio14",
+ "gpio15", "gpio16";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ /* WSA speaker reset pins */
+ spkr_1_sd_n {
+ spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+ mux {
+ pins = "gpio86";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio86";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_1_sd_n_active: spkr_1_sd_n_active {
+ mux {
+ pins = "gpio86";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio86";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ spkr_2_sd_n {
+ spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
+ mux {
+ pins = "gpio11";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_2_sd_n_active: spkr_2_sd_n_active {
+ mux {
+ pins = "gpio11";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ wcd938x_reset_active: wcd938x_reset_active {
+ mux {
+ pins = "gpio83";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio83";
+ drive-strength = <16>;
+ output-high;
+ };
+ };
+
+ wcd938x_reset_sleep: wcd938x_reset_sleep {
+ mux {
+ pins = "gpio83";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio83";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ fsa_usbc_ana_en_n@84 {
+ fsa_usbc_ana_en: fsa_usbc_ana_en {
+ mux {
+ pins = "gpio84";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio84";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+ };
+
+ /* SDC pin type */
+ sdc1_clk_on: sdc1_clk_on {
+ config {
+ pins = "sdc1_clk";
+ bias-disable; /* No pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc1_clk_off: sdc1_clk_off {
+ config {
+ pins = "sdc1_clk";
+ bias-disable; /* No Pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_cmd_on: sdc1_cmd_on {
+ config {
+ pins = "sdc1_cmd";
+ bias-pull-up; /* Pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc1_cmd_off: sdc1_cmd_off {
+ config {
+ pins = "sdc1_cmd";
+ bias-pull-up; /* Pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_data_on: sdc1_data_on {
+ config {
+ pins = "sdc1_data";
+ bias-pull-up; /* Pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc1_data_off: sdc1_data_off {
+ config {
+ pins = "sdc1_data";
+ bias-pull-up; /* Pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_rclk_on: sdc1_rclk_on {
+ config {
+ pins = "sdc1_rclk";
+ bias-pull-down; /* Pull down */
+ };
+ };
+
+ sdc1_rclk_off: sdc1_rclk_off {
+ config {
+ pins = "sdc1_rclk";
+ bias-pull-down; /* Pull down */
+ };
+ };
+
+ sdc2_clk_on: sdc2_clk_on {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* No pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_clk_off: sdc2_clk_off {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* No pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_cmd_on: sdc2_cmd_on {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* Pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_cmd_off: sdc2_cmd_off {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* Pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_data_on: sdc2_data_on {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* Pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_data_off: sdc2_data_off {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* Pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_cd_on: cd_on {
+ mux {
+ pins = "gpio94";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio94";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_cd_off: cd_off {
+ mux {
+ pins = "gpio94";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio94";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ pm8008_interrupt: pm8008_interrupt {
+ mux {
+ pins = "gpio59";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio59";
+ bias-disable;
+ input-enable;
+ };
+ };
+
+ pm8008_active: pm8008_active {
+ mux {
+ pins = "gpio58";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio58";
+ bias-pull-up;
+ output-high;
+ drive-strength = <2>;
+ };
+ };
+
+ /* Camera GPIOs CCI*/
+ cci0_active: cci0_active {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio39", "gpio40";
+ function = "CCI_I2C";
+ };
+
+ config {
+ pins = "gpio39", "gpio40";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci0_suspend: cci0_suspend {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio39", "gpio40";
+ function = "CCI_I2C";
+ };
+
+ config {
+ pins = "gpio39", "gpio40";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci1_active: cci1_active {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio41", "gpio42";
+ function = "CCI_I2C";
+ };
+
+ config {
+ pins = "gpio41", "gpio42";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci1_suspend: cci1_suspend {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio41", "gpio42";
+ function = "CCI_I2C";
+ };
+
+ config {
+ pins = "gpio41", "gpio42";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci2_active: cci2_active {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio43", "gpio44";
+ function = "CCI_I2C";
+ };
+
+ config {
+ pins = "gpio43", "gpio44";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci2_suspend: cci2_suspend {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio43", "gpio44";
+ function = "CCI_I2C";
+ };
+
+ config {
+ pins = "gpio43", "gpio44";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci3_active: cci3_active {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio2";
+ function = "CCI_I2C";
+ };
+
+ config {
+ pins = "gpio2";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci3_suspend: cci3_suspend {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio2";
+ function = "CCI_I2C";
+ };
+
+ config {
+ pins = "gpio2";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ /* Camera GPIOs CCI*/
+ cam_sensor_mclk0_active: cam_sensor_mclk0_active {
+ /* MCLK0 */
+ mux {
+ pins = "gpio29";
+ function = "CAM_MCLK0";
+ };
+
+ config {
+ pins = "gpio29";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
+ /* MCLK0 */
+ mux {
+ pins = "gpio29";
+ function = "CAM_MCLK0";
+ };
+
+ config {
+ pins = "gpio29";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk1_active: cam_sensor_mclk1_active {
+ /* MCLK1 */
+ mux {
+ pins = "gpio30";
+ function = "CAM_MCLK1";
+ };
+
+ config {
+ pins = "gpio30";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
+ /* MCLK1 */
+ mux {
+ pins = "gpio30";
+ function = "CAM_MCLK1";
+ };
+
+ config {
+ pins = "gpio30";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk2_active: cam_sensor_mclk2_active {
+ /* MCLK2 */
+ mux {
+ pins = "gpio31";
+ function = "CAM_MCLK2";
+ };
+
+ config {
+ pins = "gpio31";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
+ /* MCLK2 */
+ mux {
+ pins = "gpio31";
+ function = "CAM_MCLK2";
+ };
+
+ config {
+ pins = "gpio31";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk3_active: cam_sensor_mclk3_active {
+ /* MCLK3 */
+ mux {
+ pins = "gpio30";
+ function = "CAM_MCLK3";
+ };
+
+ config {
+ pins = "gpio30";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend {
+ /* MCLK3 */
+ mux {
+ pins = "gpio30";
+ function = "CAM_MCLK3";
+ };
+
+ config {
+ pins = "gpio30";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk4_active: cam_sensor_mclk4_active {
+ /* MCLK4 */
+ mux {
+ pins = "gpio33";
+ function = "CAM_MCLK4";
+ };
+
+ config {
+ pins = "gpio33";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend {
+ /* MCLK4 */
+ mux {
+ pins = "gpio33";
+ function = "CAM_MCLK4";
+ };
+
+ config {
+ pins = "gpio33";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_active_rear: cam_sensor_active_rear {
+ /* RESET REAR, AVDD eLDO */
+ mux {
+ pins = "gpio34", "gpio50";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio34", "gpio50";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_rear: cam_sensor_suspend_rear {
+ /* RESET REAR, AVDD eLDO */
+ mux {
+ pins = "gpio34", "gpio50";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio34", "gpio50";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_rear_aux: cam_sensor_active_rear_aux {
+ /* RESET REARAUX */
+ mux {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio35";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_rear_aux: cam_sensor_suspend_rear_aux {
+ /* RESET REARAUX */
+ mux {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio35";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_rear1_reset_active: cam_sensor_rear1_reset_active {
+ /* RESET1 */
+ mux {
+ pins = "gpio36", "gpio38";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio36", "gpio38";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear1_reset_suspend: cam_sensor_rear1_reset_suspend {
+ /* RESET1 */
+ mux {
+ pins = "gpio36", "gpio38";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio36", "gpio38";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_rear_aux2: cam_sensor_active_rear_aux2 {
+ /* RESET REARAUX2 */
+ mux {
+ pins = "gpio73";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio73";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_rear_aux2: cam_sensor_suspend_rear_aux2 {
+ /* RESET REARAUX2 */
+ mux {
+ pins = "gpio73";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio73";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_rear0_reset_active: cam_sensor_rear0_reset_active {
+ /* RESET0 */
+ mux {
+ pins = "gpio34";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio34";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear0_reset_suspend: cam_sensor_rear0_reset_suspend {
+ /* RESET0 */
+ mux {
+ pins = "gpio34";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio34";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_front: cam_sensor_active_front {
+ /* RESET FRONT */
+ mux {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio35";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_front: cam_sensor_suspend_front {
+ /* RESET FRONT */
+ mux {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio35";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ pmx_sde_te {
+ sde_te_active: sde_te_active {
+ mux {
+ pins = "gpio23";
+ function = "MDP_VSYNC";
+ };
+
+ config {
+ pins = "gpio23";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ sde_te_suspend: sde_te_suspend {
+ mux {
+ pins = "gpio23";
+ function = "MDP_VSYNC";
+ };
+
+ config {
+ pins = "gpio23";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+ mdss_dp_aux_active: mdss_dp_aux_active {
+ mux {
+ pins = "gpio54", "gpio93";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio54", "gpio93";
+ bias-disable = <0>; /* no pull */
+ drive-strength = <8>;
+ };
+ };
+
+ mdss_dp_aux_suspend: mdss_dp_aux_suspend {
+ mux {
+ pins = "gpio54", "gpio93";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio54", "gpio93";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+ };
+
+ mdss_dp_usbplug_cc_active: mdss_dp_usbplug_cc_active {
+ mux {
+ pins = "gpio124";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio124";
+ bias-disable;
+ drive-strength = <16>;
+ };
+ };
+
+ mdss_dp_usbplug_cc_suspend: mdss_dp_usbplug_cc_suspend {
+ mux {
+ pins = "gpio124";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio124";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+ };
+
+ pmx_ts_int_active {
+ ts_active: ts_active {
+ mux {
+ pins = "gpio22";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio22";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_rst_active {
+ ts_rst_active: ts_rst_active {
+ mux {
+ pins = "gpio21";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio21";
+ drive-strength = <8>;
+ bias-pull-up;
+ output-high;
+ };
+ };
+ };
+
+ pmx_ts_int_suspend {
+ ts_int_suspend: ts_int_suspend {
+ mux {
+ pins = "gpio22";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio22";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_reset_suspend {
+ ts_reset_suspend: ts_reset_suspend {
+ mux {
+ pins = "gpio21";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio21";
+ drive-strength = <2>;
+ bias-pull-down;
+ output-low;
+ };
+ };
+ };
+
+ pmx_ts_release {
+ pmx_ts_release: pmx_ts_release {
+ mux {
+ pins = "gpio21", "gpio22";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio21", "gpio22";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ vsync_default {
+ vsync_default: vsync_default {
+ mux {
+ pins = "gpio24";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio24";
+ drive-strength = <2>;
+ bias-disable;
+ input-enable;
+ };
+ };
+ };
+
+ stmvl53l1_active {
+ stmvl53l1_active: stmvl53l1_active {
+ mux {
+ pins = "gpio102", "gpio3";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio102", "gpio3";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ stmvl53l1_int_suspend {
+ stmvl53l1_int_suspend: stmvl53l1_int_suspend {
+ mux {
+ pins = "gpio3";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ stmvl53l1_reset_suspend {
+ stmvl53l1_reset_suspend: stmvl53l1_reset_suspend {
+ mux {
+ pins = "gpio102";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio102";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ stmvl53l1_release {
+ stmvl53l1_release: stmvl53l1_release {
+ mux {
+ pins = "gpio102", "gpio3";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio102", "gpio3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-pm.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-pm.dtsi
new file mode 100755
index 0000000..2db850c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-pm.dtsi
@@ -0,0 +1,167 @@
+&soc {
+ qcom,lpm-levels {
+ compatible = "qcom,lpm-levels";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,pm-cluster@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "L3";
+ qcom,clstr-tmr-add = <1000>;
+ qcom,psci-mode-shift = <4>;
+ qcom,psci-mode-mask = <0xfff>;
+
+ qcom,pm-cluster-level@0 { /* D1 */
+ reg = <0>;
+ label = "l3-wfi";
+ qcom,psci-mode = <0x1>;
+ qcom,entry-latency-us = <660>;
+ qcom,exit-latency-us = <600>;
+ qcom,min-residency-us = <1260>;
+ };
+
+ qcom,pm-cluster-level@1 { /* D4 */
+ reg = <1>;
+ label = "l3-pc";
+ qcom,psci-mode = <0x4>;
+ qcom,entry-latency-us = <2752>;
+ qcom,exit-latency-us = <3048>;
+ qcom,min-residency-us = <6118>;
+ qcom,min-child-idx = <2>;
+ qcom,is-reset;
+ };
+
+ qcom,pm-cluster-level@2 { /* Cx Off */
+ reg = <2>;
+ label = "cx-ret";
+ qcom,psci-mode = <0x124>;
+ qcom,entry-latency-us = <3638>;
+ qcom,exit-latency-us = <4562>;
+ qcom,min-residency-us = <8467>;
+ qcom,min-child-idx = <2>;
+ qcom,is-reset;
+ qcom,notify-rpm;
+ };
+
+ qcom,pm-cluster-level@3 { /* LLCC off, AOSS sleep */
+ reg = <3>;
+ label = "llcc-off";
+ qcom,psci-mode = <0xB24>;
+ qcom,entry-latency-us = <3263>;
+ qcom,exit-latency-us = <6562>;
+ qcom,min-residency-us = <9826>;
+ qcom,min-child-idx = <2>;
+ qcom,is-reset;
+ qcom,notify-rpm;
+ };
+
+ qcom,pm-cpu@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+ qcom,ref-stddev = <500>;
+ qcom,tmr-add = <1000>;
+ qcom,ref-premature-cnt = <1>;
+ qcom,disable-ipi-prediction;
+ qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4
+ &CPU5>;
+
+ qcom,pm-cpu-level@0 { /* C1 */
+ reg = <0>;
+ label = "wfi";
+ qcom,psci-cpu-mode = <0x1>;
+ qcom,entry-latency-us = <61>;
+ qcom,exit-latency-us = <60>;
+ qcom,min-residency-us = <121>;
+ };
+
+ qcom,pm-cpu-level@1 { /* C3 */
+ reg = <1>;
+ label = "pc";
+ qcom,psci-cpu-mode = <0x3>;
+ qcom,entry-latency-us = <549>;
+ qcom,exit-latency-us = <901>;
+ qcom,min-residency-us = <1774>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+
+ qcom,pm-cpu-level@2 { /* C4 */
+ reg = <2>;
+ label = "rail-pc";
+ qcom,psci-cpu-mode = <0x4>;
+ qcom,entry-latency-us = <702>;
+ qcom,exit-latency-us = <915>;
+ qcom,min-residency-us = <4001>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+ };
+
+ qcom,pm-cpu@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+ qcom,ref-stddev = <100>;
+ qcom,tmr-add = <100>;
+ qcom,ref-premature-cnt = <3>;
+ qcom,cpu = <&CPU6 &CPU7>;
+
+ qcom,pm-cpu-level@0 { /* C1 */
+ reg = <0>;
+ label = "wfi";
+ qcom,psci-cpu-mode = <0x1>;
+ qcom,entry-latency-us = <55>;
+ qcom,exit-latency-us = <66>;
+ qcom,min-residency-us = <121>;
+ };
+
+ qcom,pm-cpu-level@1 { /* C3 */
+ reg = <1>;
+ label = "pc";
+ qcom,psci-cpu-mode = <0x3>;
+ qcom,entry-latency-us = <523>;
+ qcom,exit-latency-us = <1244>;
+ qcom,min-residency-us = <2207>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+
+ qcom,pm-cpu-level@2 { /* C4 */
+ reg = <2>;
+ label = "rail-pc";
+ qcom,psci-cpu-mode = <0x4>;
+ qcom,entry-latency-us = <526>;
+ qcom,exit-latency-us = <1854>;
+ qcom,min-residency-us = <5555>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+ };
+ };
+ };
+
+ qcom,rpm-stats@c300000 {
+ compatible = "qcom,rpm-stats";
+ reg = <0xc300000 0x1000>, <0xc3f0004 0x4>;
+ reg-names = "phys_addr_base", "offset_addr";
+ qcom,num-records = <3>;
+ };
+
+ qcom,rpmh-master-stats@b221200 {
+ compatible = "qcom,rpmh-master-stats-v1";
+ reg = <0xb221200 0x60>;
+ };
+
+ qcom,ddr-stats@c3f001c {
+ compatible = "qcom,ddr-stats";
+ reg = <0xc300000 0x1000>, <0xc3f001c 0x4>;
+ reg-names = "phys_addr_base", "offset_addr";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-qrd-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon-qrd-overlay.dts
new file mode 100755
index 0000000..94b7538
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-qrd-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lagoon-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lagoon QRD";
+ compatible = "qcom,lagoon-qrd", "qcom,lagoon", "qcom,qrd";
+ qcom,msm-id = <434 0x10000>, <459 0x10000>;
+ qcom,board-id = <0x1000B 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon-qrd.dts
new file mode 100755
index 0000000..a920fda
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-qrd.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "lagoon.dtsi"
+#include "lagoon-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lagoon QRD";
+ compatible = "qcom,lagoon-qrd", "qcom,lagoon", "qcom,qrd";
+ qcom,board-id = <0x1000B 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-qrd.dtsi
new file mode 100755
index 0000000..018bf54
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-qrd.dtsi
@@ -0,0 +1,576 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include "lagoon-audio-overlay.dtsi"
+#include "lagoon-sde-display.dtsi"
+#include "camera/lagoon-camera-sensor-mtp.dtsi"
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include "lagoon-thermal-overlay.dtsi"
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm6350_gpios 2 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+
+ qrd_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ //#include "qg-batterydata-atl436186020H_3780mAh.dtsi"
+ //#include "qg-batterydata-atl466271_3300mAh.dtsi"
+ };
+};
+
+&pm6150a_l1 {
+ qcom,init-voltage = <1800000>;
+};
+
+&pm6350_gpios {
+ key_vol_up {
+ key_vol_up_default: key_vol_up_default {
+ pins = "gpio2";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+ };
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v3";
+
+ vdda-phy-supply = <&L18A>;
+ vdda-pll-supply = <&L22A>;
+ vdda-phy-max-microamp = <62900>;
+ vdda-pll-max-microamp = <18300>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&L7E>;
+ vcc-voltage-level = <2950000 2960000>;
+ vccq2-supply = <&L12A>;
+ vccq2-voltage-level = <1800000 1800000>;
+ vcc-max-microamp = <800000>;
+ vccq2-min-microamp = <0>;
+ vccq2-max-microamp = <800000>;
+ vccq2-pwr-collapse-sup;
+
+ qcom,vddp-ref-clk-supply = <&L22A>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vddp-ref-clk-min-uV = <1152000>;
+ qcom,vddp-ref-clk-max-uV = <1200000>;
+ status = "ok";
+};
+
+&sdhc_1 {
+ vdd-supply = <&L7E>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L12A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&L9E>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L6E>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&pm6150a_amoled {
+ status = "ok";
+};
+
+&dsi_r66451_amoled_60hz_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_r66451_amoled_90hz_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_r66451_amoled_120hz_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,mdss-dsi-bl-inverted-dbv;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_r66451_amoled_60hz_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_r66451_amoled_90hz_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&dsi_r66451_amoled_120hz_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-bl-inverted-dbv;
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,platform-reset-gpio = <&pm6150l_gpios 9 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_r66451_amoled_120hz_video>;
+};
+
+&qupv3_se0_i2c {
+ status = "ok";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 9 0x00>;
+ qcom,nq-ven = <&tlmm 6 0x00>;
+ qcom,nq-firm = <&tlmm 8 0x00>;
+ qcom,nq-clkreq = <&tlmm 7 0x00>;
+ qcom,nq-vdd-1p8-supply = <&L11A>;
+ qcom,nq-vdd-1p8-voltage = <1800000 1800000>;
+ qcom,nq-vdd-1p8-current = <157000>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&pm7250b_charger {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+ <&pm7250b_vadc ADC_USB_IN_I>,
+ <&pm7250b_vadc ADC_CHG_TEMP>,
+ <&pm7250b_vadc ADC_DIE_TEMP>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+ <&pm7250b_vadc ADC_SBUx>,
+ <&pm7250b_vadc ADC_VPH_PWR>,
+ <&pm7250b_vadc ADC_AMUX_THM1_PU2>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp",
+ "die_temp",
+ "conn_temp",
+ "sbux_res",
+ "vph_voltage",
+ "skin_temp";
+ qcom,battery-data = <&qrd_batterydata>;
+ qcom,sec-charger-config = <1>;
+ qcom,auto-recharge-soc = <98>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,fcc-stepping-enable;
+ qcom,fcc-step-delay-ms = <100>;
+ qcom,fcc-step-size-ua = <100000>;
+ qcom,smb-internal-pull-kohm = <0>;
+ qcom,en-skin-therm-mitigation;
+ qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000
+ 7500000 7000000 6500000 6000000 5500000 5000000 4500000
+ 4000000 3500000 3000000 2500000 2000000 1500000 1000000
+ 500000>;
+};
+
+&pm7250b_qg {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU2>,
+ <&pm7250b_vadc ADC_BAT_ID_PU2>;
+ io-channel-names = "batt-therm",
+ "batt-id";
+ qcom,qg-iterm-ma = <150>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+ qcom,tcss-enable;
+ qcom,fvss-enable;
+ qcom,fvss-vbatt-mv = <3300>;
+ qcom,bass-enable;
+ qcom,use-cp-iin-sns;
+};
+
+&wcd937x_codec {
+ status = "ok";
+};
+
+&wcd938x_codec {
+ status = "disabled";
+};
+
+&wcd937x_rx_slave {
+ status = "ok";
+};
+
+&wcd937x_tx_slave {
+ status = "ok";
+};
+
+&wcd938x_tx_slave {
+ status = "disabled";
+};
+
+&wcd938x_rx_slave {
+ status = "disabled";
+};
+
+&lagoon_snd {
+ qcom,model = "lito-lagoonqrd-snd-card";
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
+ qcom,wcn-btfm = <1>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic4",
+ "TX DMIC0", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic0",
+ "TX DMIC1", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic1",
+ "TX DMIC2", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "TX DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "TX DMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "TX DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC2", "ADC2_OUTPUT",
+ "TX SWR_ADC3", "ADC3_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrLeft IN", "WSA_SPK1 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic4",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA DMIC4", "VA MIC BIAS4",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC0", "VA_SWR_CLK",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_ADC2", "VA_SWR_CLK",
+ "VA SWR_ADC3", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_ADC0", "ADC1_OUTPUT",
+ "VA SWR_ADC2", "ADC2_OUTPUT",
+ "VA SWR_ADC3", "ADC3_OUTPUT",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+ qcom,wsa-max-devs = <1>;
+ qcom,wsa-devs = <&wsa883x_0221>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft";
+ qcom,codec-max-aux-devs = <1>;
+ qcom,msm-mbhc-usbc-audio-supported = <1>;
+ qcom,codec-aux-devs = <&wcd937x_codec>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>,
+ <&lpi_tlmm>, <&bolero>;
+};
+
+&qupv3_se8_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "ok";
+ qcom,i2c-touch-active = "focaltech,fts_ts";
+
+ focaltech@38 {
+ compatible = "focaltech,fts_ts";
+ reg = <0x38>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <22 0x2008>;
+ focaltech,reset-gpio = <&tlmm 21 0x00>;
+ focaltech,irq-gpio = <&tlmm 22 0x2008>;
+ focaltech,max-touch-number = <5>;
+ focaltech,display-coords = <0 0 1080 2340>;
+
+ vdd-supply = <&L6A>;
+
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend","pmx_ts_release";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&pmx_ts_release>;
+
+ panel = <&dsi_r66451_amoled_60hz_cmd
+ &dsi_r66451_amoled_90hz_cmd
+ &dsi_r66451_amoled_120hz_cmd
+ &dsi_r66451_amoled_60hz_video
+ &dsi_r66451_amoled_90hz_video
+ &dsi_r66451_amoled_120hz_video>;
+ };
+};
+
+&pm7250b_vadc {
+ smb1390_therm@e {
+ qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_SMB1398_TEMP>;
+ };
+};
+
+&pm7250b_gpios {
+ smb_stat {
+ smb_stat_default: smb_stat_default {
+ pins = "gpio6";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+ power-source = <0>;
+ };
+ };
+};
+
+&qupv3_se10_i2c {
+ qcom,clk-freq-out = <100000>;
+ status = "ok";
+ #include "smb1398.dtsi"
+};
+
+&smb1396 {
+ interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&spmi_bus>;
+ interrupt-names = "smb1396";
+ pinctrl-names = "default";
+ qcom,enable-toggle-stat;
+ pinctrl-0 = <&smb_stat_default>;
+ status = "ok";
+};
+
+&smb1396_div2_cp_master {
+ io-channels = <&pm7250b_vadc ADC_AMUX_THM2>;
+ qcom,parallel-input-mode = <1>; /* USBIN */
+ qcom,parallel-output-mode = <2>; /* VBAT */
+ qcom,div2-cp-min-ilim-ua = <750000>;
+ status = "ok";
+};
+
+&smb1396_slave {
+ status = "ok";
+};
+
+&smb1396_div2_cp_slave {
+ status = "ok";
+};
+
+&qusb_phy0 {
+ qcom,qusb-phy-init-seq =
+ /* <value reg_offset> */
+ <0x23 0x210 /* PWR_CTRL1 */
+ 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
+ 0x7c 0x18c /* PLL_CLOCK_INVERTERS */
+ 0x80 0x2c /* PLL_CMODE */
+ 0x0a 0x184 /* PLL_LOCK_DELAY */
+ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
+ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */
+ 0x16 0x198 /* PLL_BIAS_CONTROL_2 */
+ 0x21 0x214 /* PWR_CTRL2 */
+ 0x08 0x220 /* IMP_CTRL1 */
+ 0x58 0x224 /* IMP_CTRL2 */
+ 0x47 0x240 /* TUNE1 */
+ 0x29 0x244 /* TUNE2 */
+ 0xca 0x248 /* TUNE3 */
+ 0x04 0x24c /* TUNE4 */
+ 0x03 0x250 /* TUNE5 */
+ 0x30 0x23c /* CHG_CTRL2 */
+ 0x22 0x210>; /* PWR_CTRL1 */
+
+ qcom,qusb-phy-host-init-seq =
+ /* <value reg_offset> */
+ <0x23 0x210 /* PWR_CTRL1 */
+ 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
+ 0x7c 0x18c /* PLL_CLOCK_INVERTERS */
+ 0x80 0x2c /* PLL_CMODE */
+ 0x0a 0x184 /* PLL_LOCK_DELAY */
+ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
+ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */
+ 0x16 0x198 /* PLL_BIAS_CONTROL_2 */
+ 0x21 0x214 /* PWR_CTRL2 */
+ 0x08 0x220 /* IMP_CTRL1 */
+ 0x58 0x224 /* IMP_CTRL2 */
+ 0x47 0x240 /* TUNE1 */
+ 0x29 0x244 /* TUNE2 */
+ 0xca 0x248 /* TUNE3 */
+ 0x04 0x24c /* TUNE4 */
+ 0x03 0x250 /* TUNE5 */
+ 0x30 0x23c /* CHG_CTRL2 */
+ 0x22 0x210>; /* PWR_CTRL1 */
+};
+
+&tlmm {
+ fpc_reset_int: fpc_reset_int {
+ fpc_reset_low: reset_low {
+ mux {
+ pins = "gpio18";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio18";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ fpc_reset_high: reset_high {
+ mux {
+ pins = "gpio18";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio18";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ fpc_int_low: int_low {
+ mux {
+ pins = "gpio17";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+ };
+ };
+};
+
+&soc {
+ fingerprint: fpc1020 {
+ compatible = "fpc,fpc1020";
+ interrupt-parent = <&tlmm>;
+ interrupts = <17 0>;
+ fpc,gpio_rst = <&tlmm 18 0>;
+ fpc,gpio_irq = <&tlmm 17 0>;
+ fpc,enable-on-boot;
+ pinctrl-names = "fpc1020_reset_reset",
+ "fpc1020_reset_active",
+ "fpc1020_irq_active";
+ pinctrl-0 = <&fpc_reset_low>;
+ pinctrl-1 = <&fpc_reset_high>;
+ pinctrl-2 = <&fpc_int_low>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-qupv3.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-qupv3.dtsi
new file mode 100755
index 0000000..db921ab
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-qupv3.dtsi
@@ -0,0 +1,329 @@
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ /* QUPv3 SE Instances
+ * North 0 : SE 0
+ * North 1 : SE 1
+ * North 2 : SE 2
+ * South 0 : SE 6
+ * South 1 : SE 7
+ * South 2 : SE 8
+ * South 3 : SE 9
+ * South 4 : SE 10
+ */
+
+ /* QUPv3_0 wrapper instance : North QUP */
+ qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
+ compatible = "qcom,qupv3-geni-se";
+ reg = <0x8c0000 0x2000>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-bus-ids =
+ <MSM_BUS_MASTER_QUP_CORE_0 MSM_BUS_SLAVE_QUP_CORE_0>,
+ <MSM_BUS_MASTER_QUP_0 MSM_BUS_SLAVE_EBI_CH0>;
+ iommus = <&apps_smmu 0x43 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+ qcom,iommu-dma = "fastmap";
+ };
+
+ gpi_dma0: qcom,gpi-dma@800000 {
+ compatible = "qcom,gpi-dma";
+ #dma-cells = <5>;
+ reg = <0x800000 0x60000>;
+ reg-names = "gpi-top";
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,max-num-gpii = <10>;
+ qcom,gpii-mask = <0x1f>;
+ qcom,ev-factor = <2>;
+ iommus = <&apps_smmu 0x56 0x0>;
+ qcom,gpi-ee-offset = <0x10000>;
+ qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+ status = "ok";
+ };
+
+ qupv3_se0_i2c: i2c@880000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x880000 0x4000>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 0 3 64 0>,
+ <&gpi_dma0 1 0 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se0_i2c_active>;
+ pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se0_spi: spi@880000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x880000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se0_spi_active>;
+ pinctrl-1 = <&qupv3_se0_spi_sleep>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 0 1 64 0>,
+ <&gpi_dma0 1 0 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se1_4uart: qcom,qup_uart@884000 {
+ compatible = "qcom,msm-geni-serial-hs";
+ reg = <0x884000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "active", "sleep";
+ pinctrl-0 = <&qupv3_se1_default_ctsrtsrx>,
+ <&qupv3_se1_default_tx>;
+ pinctrl-1 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>,
+ <&qupv3_se1_tx>;
+ pinctrl-2 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>,
+ <&qupv3_se1_tx>;
+ interrupts-extended = <&intc GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 64 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,wrapper-core = <&qupv3_0>;
+ qcom,wakeup-byte = <0xFD>;
+ status = "disabled";
+ };
+
+ qupv3_se2_i2c: i2c@888000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x888000 0x4000>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 2 3 64 0>,
+ <&gpi_dma0 1 2 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se2_i2c_active>;
+ pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se2_spi: spi@888000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x888000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se2_spi_active>;
+ pinctrl-1 = <&qupv3_se2_spi_sleep>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 2 1 64 0>,
+ <&gpi_dma0 1 2 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ /* QUPv3_1 wrapper instance : South QUP */
+ qupv3_1: qcom,qupv3_1_geni_se@9c0000 {
+ compatible = "qcom,qupv3-geni-se";
+ reg = <0x9c0000 0x2000>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-bus-ids =
+ <MSM_BUS_MASTER_QUP_CORE_1 MSM_BUS_SLAVE_QUP_CORE_1>,
+ <MSM_BUS_MASTER_QUP_1 MSM_BUS_SLAVE_EBI_CH0>;
+ iommus = <&apps_smmu 0x4c3 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+ qcom,iommu-dma = "fastmap";
+ };
+
+ gpi_dma1: qcom,gpi-dma@900000 {
+ compatible = "qcom,gpi-dma";
+ #dma-cells = <5>;
+ reg = <0x900000 0x60000>;
+ reg-names = "gpi-top";
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,max-num-gpii = <10>;
+ qcom,gpii-mask = <0x3f>;
+ qcom,ev-factor = <2>;
+ iommus = <&apps_smmu 0x4d6 0x0>;
+ qcom,gpi-ee-offset = <0x10000>;
+ qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+ status = "ok";
+ };
+
+ qupv3_se6_i2c: i2c@980000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x980000 0x4000>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 0 3 64 0>,
+ <&gpi_dma1 1 0 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se6_i2c_active>;
+ pinctrl-1 = <&qupv3_se6_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ qupv3_se6_spi: spi@980000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x980000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se6_spi_active>;
+ pinctrl-1 = <&qupv3_se6_spi_sleep>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
+ dmas = <&gpi_dma1 0 0 1 64 0>,
+ <&gpi_dma1 1 0 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+#if 0 // MODIFIED by yixiang.wu, 2021-01-05,BUG-10277816
+ qupv3_se7_2uart: qcom,qup_uart@984000 {
+ compatible = "qcom,msm-geni-console";
+ reg = <0x984000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se7_2uart_active>;
+ pinctrl-1 = <&qupv3_se7_2uart_sleep>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+#endif // MODIFIED by yixiang.wu, 2021-01-05,BUG-10277816
+ qupv3_se7_i2c: i2c@984000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x984000 0x4000>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 1 3 64 0>,
+ <&gpi_dma1 1 1 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se7_i2c_active>;
+ pinctrl-1 = <&qupv3_se7_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ qupv3_se8_i2c: i2c@988000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x988000 0x4000>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 2 3 64 0>,
+ <&gpi_dma1 1 2 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se8_i2c_active>;
+ pinctrl-1 = <&qupv3_se8_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ qupv3_se9_2uart: qcom,qup_uart@98c000 {
+ compatible = "qcom,msm-geni-console";
+ reg = <0x98c000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se9_2uart_active>;
+ pinctrl-1 = <&qupv3_se9_2uart_sleep>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "ok";
+ };
+
+ qupv3_se10_i2c: i2c@990000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x990000 0x4000>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 4 3 64 0>,
+ <&gpi_dma1 1 4 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se10_i2c_active>;
+ pinctrl-1 = <&qupv3_se10_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ qcom,shared;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-regulators.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-regulators.dtsi
new file mode 100755
index 0000000..c89dd65
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-regulators.dtsi
@@ -0,0 +1,779 @@
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+
+&apps_rsc {
+ rpmh-regulator-smpa1 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpa1";
+ S1A:
+ pm6350_s1: regulator-pm6350-s1 {
+ regulator-name = "pm6350_s1";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ qcom,init-voltage = <1000000>;
+ };
+ };
+
+ rpmh-regulator-smpa2 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpa2";
+ S2A:
+ pm6350_s2: regulator-pm6350-s2 {
+ regulator-name = "pm6350_s2";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1503000>;
+ regulator-max-microvolt = <2048000>;
+ qcom,init-voltage = <1503000>;
+ };
+ };
+
+ rpmh-regulator-gfxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "gfx.lvl";
+ VDD_GFX_LEVEL:
+ S3A_LEVEL:
+ pm6350_s3_level: regulator-pm6350-s3-level {
+ regulator-name = "pm6350_s3_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ rpmh-regulator-mxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "mx.lvl";
+ VDD_MX_LEVEL:
+ S5A_LEVEL:
+ pm6350_s5_level: regulator-pm6350-s5-level {
+ regulator-name = "pm6350_s5_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ VDD_MX_LEVEL_AO:
+ S5A_LEVEL_AO:
+ pm6350_s5_level_ao: regulator-pm6350-s5-level-ao {
+ regulator-name = "pm6350_s5_level_ao";
+ qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ rpmh-regulator-lcxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "lcx.lvl";
+ L1A_LEVEL:
+ pm6350_l1_level: regulator-pm6350-l1-level {
+ regulator-name = "pm6350_l1_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ rpmh-regulator-ldoa2 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa2";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L2A:
+ pm6350_l2: regulator-pm6350-l2 {
+ regulator-name = "pm6350_l2";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1503000>;
+ regulator-max-microvolt = <1980000>;
+ qcom,init-voltage = <1503000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa3 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa3";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L3A:
+ pm6350_l3: regulator-pm6350-l3 {
+ regulator-name = "pm6350_l3";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <2700000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa4 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa4";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L4A:
+ pm6350_l4: regulator-pm6350-l4 {
+ regulator-name = "pm6350_l4";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <352000>;
+ regulator-max-microvolt = <801000>;
+ qcom,init-voltage = <352000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa5 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa5";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L5A:
+ pm6350_l5: regulator-pm6350-l5 {
+ regulator-name = "pm6350_l5";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1503000>;
+ regulator-max-microvolt = <1980000>;
+ qcom,init-voltage = <1503000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa6 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa6";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L6A:
+ pm6350_l6: regulator-pm6350-l6 {
+ regulator-name = "pm6350_l6";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <3544000>;
+ qcom,init-voltage = <1710000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa7 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa7";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L7A:
+ pm6350_l7: regulator-pm6350-l7 {
+ regulator-name = "pm6350_l7";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ qcom,init-voltage = <1620000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa8 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa8";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L8A:
+ pm6350_l8: regulator-pm6350-l8 {
+ regulator-name = "pm6350_l8";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ qcom,init-voltage = <2800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa9 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa9";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L9A:
+ pm6350_l9: regulator-pm6350-l9 {
+ regulator-name = "pm6350_l9";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3401000>;
+ qcom,init-voltage = <1650000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa11 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa11";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L11A:
+ pm6350_l11: regulator-pm6350-l11 {
+ regulator-name = "pm6350_l11";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2000000>;
+ qcom,init-voltage = <1800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa12 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa12";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L12A:
+ pm6350_l12: regulator-pm6350-l12 {
+ regulator-name = "pm6350_l12";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ qcom,init-voltage = <1800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa13 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa13";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L13A:
+ pm6350_l13: regulator-pm6350-l13 {
+ regulator-name = "pm6350_l13";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <570000>;
+ regulator-max-microvolt = <650000>;
+ qcom,init-voltage = <570000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa14 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa14";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L14A:
+ pm6350_l14: regulator-pm6350-l14 {
+ regulator-name = "pm6350_l14";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ qcom,init-voltage = <1700000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa15 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa15";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L15A:
+ pm6350_l15: regulator-pm6350-l15 {
+ regulator-name = "pm6350_l15";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1305000>;
+ qcom,init-voltage = <1100000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa16 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa16";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L16A:
+ pm6350_l16: regulator-pm6350-l16 {
+ regulator-name = "pm6350_l16";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <830000>;
+ regulator-max-microvolt = <921000>;
+ qcom,init-voltage = <830000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-lmxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "lmx.lvl";
+ L17A_LEVEL:
+ pm6350_l17_level: regulator-pm6350-l17-level {
+ regulator-name = "pm6350_l17_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ rpmh-regulator-ldoa18 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa18";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L18A:
+ pm6350_l18: regulator-pm6350-l18 {
+ regulator-name = "pm6350_l18";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <788000>;
+ regulator-max-microvolt = <1049000>;
+ qcom,init-voltage = <788000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa19 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa19";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L19A:
+ pm6350_l19: regulator-pm6350-l19 {
+ regulator-name = "pm6350_l19";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1305000>;
+ qcom,init-voltage = <1080000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa20 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa20";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L20A:
+ pm6350_l20: regulator-pm6350-l20 {
+ regulator-name = "pm6350_l20";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <530000>;
+ regulator-max-microvolt = <801000>;
+ qcom,init-voltage = <530000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa21 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa21";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L21A:
+ pm6350_l21: regulator-pm6350-l21 {
+ regulator-name = "pm6350_l21";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <751000>;
+ regulator-max-microvolt = <825000>;
+ qcom,init-voltage = <751000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa22 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa22";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L22A:
+ pm6350_l22: regulator-pm6350-l22 {
+ regulator-name = "pm6350_l22";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1305000>;
+ qcom,init-voltage = <1080000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-cxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "cx.lvl";
+ VDD_CX_LEVEL:
+ S1E_LEVEL:
+ pm6150a_s1_level: regulator-pm6150a-s1-level {
+ regulator-name = "pm6150a_s1_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ qcom,min-dropout-voltage-level = <(-1)>;
+ };
+
+ VDD_CX_LEVEL_AO:
+ S1E_LEVEL_AO:
+ pm6150a_s1_level_ao: regulator-pm6150a-s1-level-ao {
+ regulator-name = "pm6150a_s1_level_ao";
+ qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ qcom,min-dropout-voltage-level = <(-1)>;
+ };
+
+ cx_cdev: regulator-cdev {
+ compatible = "qcom,rpmh-reg-cdev";
+ mboxes = <&qmp_aop 0>;
+ qcom,reg-resource-name = "cx";
+ #cooling-cells = <2>;
+ };
+ };
+
+ rpmh-regulator-msslvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "mss.lvl";
+ VDD_MSS_LEVEL:
+ S6E_LEVEL:
+ pm6150a_s6_level: regulator-pm6150a-s6-level {
+ regulator-name = "pm6150a_s6_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ rpmh-regulator-smpe8 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpe8";
+ S8E:
+ pm6150a_s8: regulator-pm6150a-s8 {
+ regulator-name = "pm6150a_s8";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <313000>;
+ regulator-max-microvolt = <1395000>;
+ qcom,init-voltage = <313000>;
+ };
+ };
+
+ rpmh-regulator-ldoe1 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoe1";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L1E:
+ pm6150a_l1: regulator-pm6150a-l1 {
+ regulator-name = "pm6150a_l1";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ qcom,init-voltage = <1620000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoe2 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoe2";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L2E:
+ pm6150a_l2: regulator-pm6150a-l2 {
+ regulator-name = "pm6150a_l2";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1170000>;
+ regulator-max-microvolt = <1305000>;
+ qcom,init-voltage = <1170000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoe3 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoe3";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L3E:
+ pm6150a_l3: regulator-pm6150a-l3 {
+ regulator-name = "pm6150a_l3";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1299000>;
+ qcom,init-voltage = <1100000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoe4 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoe4";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L4E:
+ pm6150a_l4: regulator-pm6150a-l4 {
+ regulator-name = "pm6150a_l4";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <1620000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoe5 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoe5";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L5E:
+ pm6150a_l5: regulator-pm6150a-l5 {
+ regulator-name = "pm6150a_l5";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <1620000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoe6 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoe6";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L6E:
+ pm6150a_l6: regulator-pm6150a-l6 {
+ regulator-name = "pm6150a_l6";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3544000>;
+ qcom,init-voltage = <1700000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoe7 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoe7";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L7E:
+ pm6150a_l7: regulator-pm6150a-l7 {
+ regulator-name = "pm6150a_l7";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ qcom,init-voltage = <2700000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoe8 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoe8";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L8E:
+ pm6150a_l8: regulator-pm6150a-l8 {
+ regulator-name = "pm6150a_l8";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <2000000>;
+ qcom,init-voltage = <1620000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoe9 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoe9";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L9E:
+ pm6150a_l9: regulator-pm6150a-l9 {
+ regulator-name = "pm6150a_l9";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ qcom,init-voltage = <2700000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoe10 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoe10";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L10E:
+ pm6150a_l10: regulator-pm6150a-l10 {
+ regulator-name = "pm6150a_l10";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3401000>;
+ qcom,init-voltage = <3000000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoe11 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoe11";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L11E:
+ pm6150a_l11: regulator-pm6150a-l11 {
+ regulator-name = "pm6150a_l11";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3401000>;
+ qcom,init-voltage = <3000000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-bobe1 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "bobe1";
+ qcom,regulator-type = "pmic5-bob";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_PASS
+ RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1000000 2000000>;
+ qcom,send-defaults;
+ BOB:
+ pm6150a_bob: regulator-pm6150a-bob {
+ regulator-name = "pm6150a_bob";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <5492000>;
+ qcom,init-voltage = <1620000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_PASS>;
+ };
+
+ BOB_AO:
+ pm6150a_bob_ao: regulator-pm6150a-bob-ao {
+ regulator-name = "pm6150a_bob_ao";
+ qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <5492000>;
+ qcom,init-voltage = <1620000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+};
+
+&soc {
+ refgen: refgen-regulator@88e7000 {
+ compatible = "qcom,refgen-kona-regulator";
+ reg = <0x88e7000 0x60>;
+ regulator-name = "refgen";
+ regulator-enable-ramp-delay = <5>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-rumi-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon-rumi-overlay.dts
new file mode 100755
index 0000000..d6c83f5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-rumi-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lagoon-rumi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lagoon RUMI";
+ compatible = "qcom,lagoon-rumi", "qcom,lagoon", "qcom,rumi";
+ qcom,msm-id = <434 0x10000>;
+ qcom,board-id = <15 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-rumi.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon-rumi.dts
new file mode 100755
index 0000000..45b21fd
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-rumi.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/memreserve/ 0xc0000000 0x00000100;
+
+#include "lagoon.dtsi"
+#include "lagoon-rumi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lagoon RUMI";
+ compatible = "qcom,lagoon-rumi", "qcom,lagoon", "qcom,rumi";
+ qcom,board-id = <15 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-rumi.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-rumi.dtsi
new file mode 100755
index 0000000..96fe4a5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-rumi.dtsi
@@ -0,0 +1,153 @@
+&soc {
+ timer {
+ clock-frequency = <500000>;
+ };
+
+ timer@17c20000 {
+ clock-frequency = <500000>;
+ };
+
+ usb_emu_phy: usb_emu_phy@a720000 {
+ compatible = "qcom,usb-emu-phy";
+ reg = <0x0a720000 0x9500>,
+ <0x0a6f8800 0x100>;
+ reg-names = "base", "qscratch_base";
+
+ qcom,emu-init-seq = <0xfff0 0x4
+ 0xfff3 0x4
+ 0x40 0x4
+ 0xfff3 0x4
+ 0xfff0 0x4
+ 0x100000 0x20
+ 0x0 0x20
+ 0x1a0 0x20
+ 0x100000 0x3c
+ 0x0 0x3c
+ 0x10060 0x3c
+ 0x0 0x4>;
+ };
+
+ bi_tcxo: bi_tcxo {
+ compatible = "fixed-factor-clock";
+ clock-mult = <1>;
+ clock-div = <4>;
+ clocks = <&xo_board>;
+ #clock-cells = <0>;
+ };
+
+ bi_tcxo_ao: bi_tcxo_ao {
+ compatible = "fixed-factor-clock";
+ clock-mult = <1>;
+ clock-div = <4>;
+ clocks = <&xo_board>;
+ #clock-cells = <0>;
+ };
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qrbtc-sdm845";
+
+ vdda-phy-supply = <&L18A>;
+ vdda-pll-supply = <&L22A>;
+ vdda-phy-max-microamp = <62900>;
+ vdda-pll-max-microamp = <18300>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ limit-tx-hs-gear = <1>;
+ limit-rx-hs-gear = <1>;
+ scsi-cmd-timeout = <300000>;
+
+ vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&L7E>;
+ vccq2-supply = <&L12A>;
+ vcc-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+
+ qcom,vddp-ref-clk-supply = <&L22A>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+
+ qcom,disable-lpm;
+ status = "ok";
+};
+
+&wdog {
+ status = "disabled";
+};
+
+&usb0 {
+ /delete-property/ extcon;
+
+ dwc3@a600000 {
+ usb-phy = <&usb_emu_phy>, <&usb_nop_phy>;
+ maximum-speed = "high-speed";
+ };
+};
+
+&rpmhcc {
+ compatible = "qcom,dummycc";
+ clock-output-names = "rpmh_clocks";
+};
+
+&aopcc {
+ compatible = "qcom,dummycc";
+ clock-output-names = "qdss_clocks";
+};
+
+&sdhc_1 {
+ vdd-supply = <&L7E>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L12A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ qcom,clk-rates = <400000 25000000 50000000>;
+ qcom,bus-speed-mode = "DDR_1p8v";
+
+ /delete-property/qcom,devfreq,freq-table;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&L9E>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L6E>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
+
+ qcom,clk-rates = <400000 25000000 50000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50";
+
+ /delete-property/qcom,devfreq,freq-table;
+
+ status = "ok";
+};
+
+&qupv3_se10_i2c {
+ status = "disabled";
+};
+
+/* Debug UART Console */
+&qupv3_se9_2uart {
+ qcom,rumi_platform;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-sde-display.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-sde-display.dtsi
new file mode 100755
index 0000000..bd7769e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-sde-display.dtsi
@@ -0,0 +1,908 @@
+#include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi"
+#include "dsi-panel-rm69299-visionox-fhd-plus-cmd.dtsi"
+#include "dsi-panel-r66451-dsc-fhd-plus-60hz-cmd.dtsi"
+#include "dsi-panel-r66451-dsc-fhd-plus-90hz-cmd.dtsi"
+#include "dsi-panel-r66451-dsc-fhd-plus-120hz-cmd.dtsi"
+#include "dsi-panel-r66451-dsc-fhd-plus-60hz-video.dtsi"
+#include "dsi-panel-r66451-dsc-fhd-plus-90hz-video.dtsi"
+#include "dsi-panel-r66451-dsc-fhd-plus-120hz-video.dtsi"
+#include "dsi-panel-sharp-qsync-fhd-video.dtsi"
+#include "dsi-panel-sharp-qsync-fhd-cmd.dtsi"
+#include "dsi-panel-sim-cmd.dtsi"
+#include "dsi-panel-sim-video.dtsi"
+#include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi"
+
+#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
+
+&pm6150l_gpios {
+ disp_pins {
+ disp_pins_default: disp_pins_default {
+ pins = "gpio9";
+ function = "func1";
+ qcom,drive-strength = <2>;
+ power-source = <1>;
+ bias-disable;
+ output-low;
+ };
+ };
+};
+
+&soc {
+ dsi_panel_pwr_supply: dsi_panel_pwr_supply {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "vdd";
+ qcom,supply-min-voltage = <3000000>;
+ qcom,supply-max-voltage = <3000000>;
+ qcom,supply-enable-load = <857000>;
+ qcom,supply-disable-load = <0>;
+ qcom,supply-post-on-sleep = <0>;
+ };
+
+ qcom,panel-supply-entry@2 {
+ reg = <2>;
+ qcom,supply-name = "lab";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <363000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@3 {
+ reg = <2>;
+ qcom,supply-name = "ibb";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <363000>;
+ qcom,supply-disable-load = <20>;
+ };
+ };
+
+ dsi_panel_pwr_supply_144: dsi_panel_pwr_supply_144 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1980000>;
+ qcom,supply-max-voltage = <1980000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "vdd";
+ qcom,supply-min-voltage = <3000000>;
+ qcom,supply-max-voltage = <3000000>;
+ qcom,supply-enable-load = <857000>;
+ qcom,supply-disable-load = <0>;
+ qcom,supply-post-on-sleep = <0>;
+ };
+
+ qcom,panel-supply-entry@2 {
+ reg = <2>;
+ qcom,supply-name = "lab";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <363000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@3 {
+ reg = <2>;
+ qcom,supply-name = "ibb";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <363000>;
+ qcom,supply-disable-load = <20>;
+ };
+ };
+
+ dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "avdd";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@2 {
+ reg = <2>;
+ qcom,supply-name = "lab";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <363000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@3 {
+ reg = <2>;
+ qcom,supply-name = "ibb";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <363000>;
+ qcom,supply-disable-load = <20>;
+ };
+ };
+
+ dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+ };
+
+ sde_dsi: qcom,dsi-display-primary {
+ compatible = "qcom,dsi-display";
+ label = "primary";
+
+ qcom,dsi-ctrl = <&mdss_dsi0>;
+ qcom,dsi-phy = <&mdss_dsi_phy0>;
+
+ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll PCLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll PCLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>;
+ clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+
+ pinctrl-names = "panel_active", "panel_suspend";
+ pinctrl-0 = <&sde_te_active &disp_pins_default>;
+ pinctrl-1 = <&sde_te_suspend>;
+
+ qcom,platform-te-gpio = <&tlmm 23 0>;
+ qcom,panel-te-source = <0>;
+
+ vddio-supply = <&L1E>;
+ //vdd-supply = <&L8A>;
+ lab-supply = <&ab_vreg>;
+ ibb-supply = <&ibb_vreg>;
+
+ qcom,mdp = <&mdss_mdp>;
+ qcom,dsi-default-panel = <&dsi_rm69299_visionox_amoled_video>;
+ };
+
+ sde_wb: qcom,wb-display@0 {
+ compatible = "qcom,wb-display";
+ cell-index = <0>;
+ label = "wb_display";
+ };
+
+ msm_notifier: qcom,msm_notifier@0 {
+ compatible = "qcom,msm-notifier";
+ panel = <&dsi_rm69299_visionox_amoled_video
+ &dsi_rm69299_visionox_amoled_cmd
+ &dsi_r66451_amoled_120hz_video
+ &dsi_r66451_amoled_120hz_cmd
+ &dsi_r66451_amoled_144hz_cmd>;
+ };
+
+ ext_disp: qcom,msm-ext-disp {
+ compatible = "qcom,msm-ext-disp";
+
+ ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
+ compatible = "qcom,msm-ext-disp-audio-codec-rx";
+ };
+ };
+
+};
+
+&sde_dp {
+ qcom,dp-usbpd-detection = <&pm7250b_pdphy>;
+ qcom,ext-disp = <&ext_disp>;
+ qcom,dp-aux-switch = <&fsa4480>;
+
+ extcon = <&pm7250b_pdphy>;
+};
+
+&mdss_mdp {
+ connectors = <&sde_wb &sde_dsi &sde_rscc &sde_dp>;
+};
+
+&dsi_rm69299_visionox_amoled_video {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-supported-dfps-list = <60 55 48>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+ qcom,dsi-dyn-clk-enable;
+ qcom,dsi-dyn-clk-list =
+ <952174080 948206688 956141472>;
+ qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp";
+ qcom,mdss-dsi-t-clk-post = <0x0E>;
+ qcom,mdss-dsi-t-clk-pre = <0x31>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08
+ 08 05 02 04 00];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_rm69299_visionox_amoled_cmd {
+ qcom,ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,dsi-dyn-clk-enable;
+ qcom,dsi-dyn-clk-list =
+ <929813440 925939216 922064992>;
+ qcom,mdss-dsi-t-clk-post = <0x0E>;
+ qcom,mdss-dsi-t-clk-pre = <0x31>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08
+ 08 05 02 04 00];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_r66451_amoled_144hz_cmd {
+ qcom,mdss-dsi-t-clk-post = <0x0e>;
+ qcom,mdss-dsi-t-clk-pre = <0x1d>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 17 09
+ 09 09 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_r66451_amoled_60hz_video {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-t-clk-post = <0x0A>;
+ qcom,mdss-dsi-t-clk-pre = <0x1D>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04
+ 04 03 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_r66451_amoled_90hz_video {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-t-clk-post = <0x0B>;
+ qcom,mdss-dsi-t-clk-pre = <0x27>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06
+ 06 06 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_r66451_amoled_120hz_video {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x1c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-t-clk-post = <0x0D>;
+ qcom,mdss-dsi-t-clk-pre = <0x32>;
+ qcom,dsi-supported-dfps-list = <120 90 60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+ qcom,mdss-dsi-min-refresh-rate = <60>;
+ qcom,mdss-dsi-max-refresh-rate = <120>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1E 08 08 24 22 08
+ 08 08 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_r66451_amoled_60hz_cmd {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-t-clk-post = <0x0A>;
+ qcom,mdss-dsi-t-clk-pre = <0x1D>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04
+ 04 03 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_r66451_amoled_90hz_cmd {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-t-clk-post = <0x0B>;
+ qcom,mdss-dsi-t-clk-pre = <0x27>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06
+ 06 06 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_r66451_amoled_120hz_cmd {
+ qcom,ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x1c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-t-clk-post = <0x0D>;
+ qcom,mdss-dsi-t-clk-pre = <0x30>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1C 08 07 23 22 07
+ 07 08 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1F 06
+ 06 06 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1E 1E 04
+ 04 03 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sharp_qsync_fhd_video {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-t-clk-post = <0x0c>;
+ qcom,mdss-dsi-t-clk-pre = <0x2c>;
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,mdss-dsi-panel-mode-switch;
+ qcom,mdss-dsi-te-pin-select = <1>;
+ qcom,mdss-dsi-wr-mem-start = <0x2c>;
+ qcom,mdss-dsi-wr-mem-continue = <0x3c>;
+ qcom,mdss-dsi-te-dcs-command = <1>;
+ qcom,mdss-dsi-te-check-enable;
+ qcom,mdss-dsi-te-using-te-pin;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-video-mode;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07
+ 07 07 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 07
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 03
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 05 be 00 10 00 10
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 14 00
+ 39 01 00 00 00 00 02 15 10
+ 39 01 00 00 00 00 02 16 0a
+ 39 01 00 00 00 00 02 17 30
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,cmd-to-video-mode-post-switch-commands = [
+ 39 00 00 00 00 00 02 ff 10
+ 39 00 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 bb 03
+ ];
+ qcom,cmd-to-video-mode-post-switch-commands-state =
+ "dsi_lp_mode";
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-cmd-mode;
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <20>;
+ qcom,mdss-dsi-h-back-porch = <12>;
+ qcom,mdss-dsi-h-pulse-width = <8>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <14>;
+ qcom,mdss-dsi-v-front-porch = <16>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-panel-jitter = <0x3 0x1>;
+ qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 1d 1d 03
+ 03 02 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 07
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 10
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 05 be 00 10 00 10
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 14 00
+ 39 01 00 00 00 00 02 15 10
+ 39 01 00 00 00 00 02 16 0a
+ 39 01 00 00 00 00 02 17 30
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command = [
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bc 00
+ 05 01 00 00 10 00 01 28
+ 05 01 00 00 32 00 01 10
+ ];
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,video-to-cmd-mode-post-switch-commands = [
+ 39 00 00 00 00 00 02 ff 10
+ 39 00 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 bb 10
+ ];
+ qcom,video-to-cmd-mode-post-switch-commands-state =
+ "dsi_lp_mode";
+ qcom,compression-mode = "dsc";
+ qcom,mdss-dsc-slice-height = <8>;
+ qcom,mdss-dsc-slice-width = <540>;
+ qcom,mdss-dsc-slice-per-pkt = <1>;
+ qcom,mdss-dsc-bit-per-component = <8>;
+ qcom,mdss-dsc-bit-per-pixel = <8>;
+ qcom,mdss-dsc-block-prediction-enable;
+ };
+ };
+};
+
+&dsi_sharp_qsync_fhd_cmd {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-t-clk-post = <0x09>;
+ qcom,mdss-dsi-t-clk-pre = <0x18>;
+ qcom,dsi-ctrl-num = <0>;
+ qcom,dsi-phy-num = <0>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-phy-timings = [00 0c 03 03 1d 1d 03
+ 03 02 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 07
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 10
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 14 00
+ 39 01 00 00 00 00 02 15 10
+ 39 01 00 00 00 00 02 16 0a
+ 39 01 00 00 00 00 02 17 30
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
+ 05 06 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 07
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 10
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 14 00
+ 39 01 00 00 00 00 02 15 10
+ 39 01 00 00 00 00 02 16 00
+ 39 01 00 00 00 00 02 17 10
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 00
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-phy-timings = [00 10 04 04 1e 1e 04
+ 04 03 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
+ qcom,mdss-dsi-on-command = [
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 40
+ 39 01 00 00 10 00 02 f1 40
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 10 00 06 2c 01 02 04 08 10
+ 39 01 00 00 00 00 02 ff d0
+ 39 01 00 00 00 00 02 75 00
+ 39 01 00 00 10 00 02 f1 00
+ /* Initial Setting */
+ 39 01 00 00 00 00 02 ff 10
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 ba 07
+ 39 01 00 00 00 00 02 bc 08
+ 39 01 00 00 00 00 02 c0 85
+ 39 01 00 00 00 00 11 c1 89 28 00 08 02
+ 00 02 0e 00 bb 00 07 0d b7 0c b7
+ 39 01 00 00 00 00 03 c2 10 f0
+ 39 01 00 00 00 00 02 d5 00
+ 39 01 00 00 00 00 02 d6 00
+ 39 01 00 00 00 00 02 de 00
+ 39 01 00 00 00 00 02 e1 00
+ 39 01 00 00 00 00 02 e5 01
+ 39 01 00 00 00 00 02 bb 10
+ 39 01 00 00 00 00 02 f6 70
+ 39 01 00 00 00 00 02 f7 80
+ 39 01 00 00 00 00 02 35 00
+ 39 01 00 00 00 00 02 44 00
+ 39 01 00 00 00 00 02 ff 20
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 87 02
+ 39 01 00 00 00 00 02 5d 00
+ 39 01 00 00 00 00 02 5e 14
+ 39 01 00 00 00 00 02 5f eb
+ 39 01 00 00 00 00 02 ff 24
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 14 00
+ 39 01 00 00 00 00 02 15 10
+ 39 01 00 00 00 00 02 16 03
+ 39 01 00 00 00 00 02 17 70
+ 39 01 00 00 00 00 02 ff 26
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 60 00
+ 39 01 00 00 00 00 02 62 01
+ 39 01 00 00 00 00 02 40 00
+ 39 01 00 00 00 00 02 ff 28
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 91 02
+ 39 01 00 00 00 00 02 ff e0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 48 81
+ 39 01 00 00 00 00 02 8e 09
+ 39 01 00 00 00 00 02 ff f0
+ 39 01 00 00 00 00 02 fb 01
+ 39 01 00 00 00 00 02 33 20
+ 39 01 00 00 00 00 02 34 35
+ 39 01 00 00 00 00 02 ff 10
+ 05 01 00 00 78 00 01 11
+ 05 01 00 00 78 00 01 29
+ ];
+ };
+ };
+};
+
+&dsi_sim_vid {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-t-clk-post = <0x0d>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
+ 07 05 02 04 00];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-t-clk-post = <0x0c>;
+ qcom,mdss-dsi-t-clk-pre = <0x29>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
+ 07 04 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ qcom,panel-roi-alignment = <720 40 720 40 720 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
+ 07 04 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ qcom,panel-roi-alignment = <720 40 720 40 720 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
+ 07 04 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ qcom,panel-roi-alignment = <720 40 720 40 720 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+
+ timing@3 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
+ 07 04 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ qcom,panel-roi-alignment = <540 40 540 40 540 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+
+ timing@4 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
+ 07 04 02 04 00];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ qcom,panel-roi-alignment = <360 40 360 40 360 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-sde-pll.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-sde-pll.dtsi
new file mode 100755
index 0000000..98454ad
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-sde-pll.dtsi
@@ -0,0 +1,44 @@
+&soc {
+ mdss_dsi0_pll: qcom,mdss_dsi0_pll {
+ compatible = "qcom,mdss_dsi_pll_10nm";
+ label = "MDSS DSI 0 PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+ reg = <0xae94a00 0x1e0>,
+ <0xae94400 0x800>,
+ <0xaf03000 0x8>,
+ <0xae94200 0x100>;
+ reg-names = "pll_base", "phy_base", "gdsc_base",
+ "dynamic_pll_base";
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ memory-region = <&dfps_data_memory>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ };
+
+ mdss_dp_pll: qcom,mdss_dp_pll@ae90000 {
+ compatible = "qcom,mdss_dp_pll_10nm";
+ label = "MDSS DP PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+
+ reg = <0x088ea000 0x200>,
+ <0x088eaa00 0x200>,
+ <0x088ea200 0x200>,
+ <0x088ea600 0x200>,
+ <0xaf03000 0x8>;
+ reg-names = "pll_base", "phy_base", "ln_tx0_base",
+ "ln_tx1_base", "gdsc_base";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_QLINK_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "iface_clk", "ref_clk_src", "ref_clk",
+ "pipe_clk";
+ clock-rate = <0>;
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-sde.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-sde.dtsi
new file mode 100755
index 0000000..19fc311
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-sde.dtsi
@@ -0,0 +1,536 @@
+#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
+&soc {
+ mdss_mdp: qcom,mdss_mdp {
+ compatible = "qcom,sde-kms";
+ reg = <0xae00000 0x84208>,
+ <0xaeb0000 0x2008>,
+ <0xaeac000 0x214>,
+ <0xae8f000 0x030>,
+ <0xaf50000 0x054>;
+ reg-names = "mdp_phys",
+ "vbif_phys",
+ "regdma_phys",
+ "sid_phys",
+ "swfuse_phys";
+
+ clocks =
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
+ clock-names = "gcc_iface", "gcc_bus",
+ "iface_clk", "core_clk", "vsync_clk",
+ "lut_clk";
+ clock-rate = <0 0 0 373333333 19200000 373333333>;
+ clock-max-rate = <0 0 0 560000000 19200000 560000000>;
+ qcom,dss-cx-ipeak = <&cx_ipeak_lm 4>;
+
+ /* interrupt config */
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ /* hw blocks */
+ qcom,sde-off = <0x1000>;
+ qcom,sde-len = <0x494>;
+
+ qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>;
+ qcom,sde-ctl-size = <0x1dc>;
+ qcom,sde-ctl-display-pref = "primary", "none", "none", "none";
+
+ qcom,sde-mixer-off = <0x45000 0x46000>;
+ qcom,sde-mixer-size = <0x320>;
+ qcom,sde-mixer-display-pref = "primary", "none";
+ qcom,sde-mixer-cwb-pref = "none", "cwb";
+
+ qcom,sde-dspp-top-off = <0x1300>;
+ qcom,sde-dspp-top-size = <0x80>;
+ qcom,sde-dspp-off = <0x55000>;
+ qcom,sde-dspp-size = <0x1800>;
+
+ qcom,sde-wb-off = <0x66000>;
+ qcom,sde-wb-size = <0x2c8>;
+ qcom,sde-wb-xin-id = <6>;
+ qcom,sde-wb-id = <2>;
+ qcom,sde-wb-clk-ctrl = <0x2bc 16>;
+
+ qcom,sde-intf-off = <0x6b000 0x6b800>;
+ qcom,sde-intf-size = <0x2c0>;
+ qcom,sde-intf-type = "dp", "dsi";
+
+ qcom,sde-pp-off = <0x71000 0x71800>;
+ qcom,sde-pp-slave = <0x0 0x0>;
+ qcom,sde-pp-size = <0xd4>;
+
+ qcom,sde-cdm-off = <0x7a200>;
+ qcom,sde-cdm-size = <0x224>;
+
+ qcom,sde-dsc-off = <0x81000>;
+ qcom,sde-dsc-size = <0x140>;
+ qcom,sde-dsc-pair-mask = <0>;
+
+ qcom,sde-dither-off = <0x30e0 0x30e0>;
+ qcom,sde-dither-version = <0x00010000>;
+ qcom,sde-dither-size = <0x20>;
+
+ qcom,sde-sspp-type = "vig", "dma", "dma", "dma";
+ qcom,sde-sspp-off = <0x5000 0x25000 0x27000 0x29000>;
+ qcom,sde-sspp-src-size = <0x1f8>;
+ qcom,sde-sspp-xin-id = <0 1 5 9>;
+ qcom,sde-sspp-excl-rect = <1 1 1 1>;
+ qcom,sde-sspp-smart-dma-priority = <4 1 2 3>;
+ qcom,sde-smart-dma-rev = "smart_dma_v2p5";
+
+ qcom,sde-mixer-pair-mask = <2 1>;
+
+ qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
+ 0xb0 0xc8 0xe0 0xf8 0x110>;
+
+ qcom,sde-max-per-pipe-bw-kbps = <3200000 3200000
+ 3200000 3200000>;
+
+ qcom,sde-max-per-pipe-bw-high-kbps = <3200000 3200000
+ 3200000 3200000>;
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+ qcom,sde-sspp-clk-ctrl = <0x2ac 0>,
+ <0x2ac 8>, <0x2b4 8>, <0x2c4 8>;
+ qcom,sde-sspp-csc-off = <0x1a00>;
+ qcom,sde-csc-type = "csc-10bit";
+ qcom,sde-qseed-type = "qseedv3lite";
+ qcom,sde-sspp-qseed-off = <0xa00>;
+ qcom,sde-mixer-linewidth = <2560>;
+ qcom,sde-wb-linewidth = <1920>;
+ qcom,sde-mixer-blendstages = <0x7>;
+ qcom,sde-highest-bank-bit = <0x1>;
+ qcom,sde-ubwc-version = <0x200>;
+ qcom,sde-ubwc-swizzle = <0x6>;
+ qcom,sde-ubwc-bw-calc-version = <0x1>;
+ qcom,sde-ubwc-static = <0x1e>;
+ qcom,sde-macrotile-mode = <0x0>;
+ qcom,sde-smart-panel-align-mode = <0xc>;
+ qcom,sde-panic-per-pipe;
+ qcom,sde-has-cdp;
+ qcom,sde-has-src-split;
+ qcom,sde-pipe-order-version = <0x1>;
+ qcom,sde-has-dim-layer;
+ qcom,sde-has-idle-pc;
+ qcom,sde-max-bw-low-kbps = <4400000>;
+ qcom,sde-max-bw-high-kbps = <5900000>;
+ qcom,sde-min-core-ib-kbps = <2500000>;
+ qcom,sde-min-llcc-ib-kbps = <0>;
+ qcom,sde-min-dram-ib-kbps = <1600000>;
+ qcom,sde-dram-channels = <2>;
+ qcom,sde-num-nrt-paths = <0>;
+ qcom,sde-dspp-ltm-version = <0x00010000>;
+ /* offsets are based off dspp 0 */
+ qcom,sde-dspp-ltm-off = <0x2a000>;
+
+ qcom,sde-vbif-off = <0>;
+ qcom,sde-vbif-size = <0x1044>;
+ qcom,sde-vbif-id = <0>;
+ qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
+
+ qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
+ qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 3>;
+ qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>;
+
+ /* macrotile & macrotile-qseed has the same configs */
+ qcom,sde-danger-lut = <0x0000ffff 0x0000ffff
+ 0x00000000 0x00000000 0x0000ffff>, <0x0003ffff
+ 0x0003ffff 0x00000000 0x00000000 0x0003ffff>;
+
+ qcom,sde-safe-lut-linear = <0 0xff00>, <0 0xfe00>;
+ qcom,sde-safe-lut-macrotile = <0 0xff00>, <0 0xfe00>;
+ /* same as safe-lut-macrotile */
+ qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>, <0 0xfe00>;
+ qcom,sde-safe-lut-nrt = <0 0xffff>, <0 0xffff>;
+ qcom,sde-safe-lut-cwb = <0 0x3ff>, <0x3ff>;
+
+ /* creq LUTs */
+ qcom,sde-qos-lut-linear = <0 0x00112233 0x44556677>,
+ <0 0x00112234 0x45566777>;
+ qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>,
+ <0 0x00112234 0x45566777>;
+ qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>,
+ <0 0x00112236 0x67777777>;
+ qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>,
+ <0 0x00000000 0x00000000>;
+ qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>,
+ <0 0x66666541 0x00000000>;
+ qcom,sde-qos-refresh-rates = <60 120>;
+
+ qcom,sde-cdp-setting = <1 1>, <1 0>;
+
+ qcom,sde-qos-cpu-mask = <0x3>;
+ qcom,sde-qos-cpu-dma-latency = <300>;
+ qcom,sde-qos-cpu-irq-latency = <300>;
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+
+ qcom,sde-reg-dma-off = <0>;
+ qcom,sde-reg-dma-version = <0x00010002>;
+ qcom,sde-reg-dma-trigger-off = <0x119c>;
+ qcom,sde-reg-dma-xin-id = <7>;
+ qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
+
+ qcom,sde-secure-sid-mask = <0x801>;
+
+ qcom,sde-sspp-vig-blocks {
+ qcom,sde-vig-csc-off = <0x1a00>;
+ qcom,sde-vig-qseed-off = <0xa00>;
+ qcom,sde-vig-qseed-size = <0xa0>;
+ qcom,sde-vig-gamut = <0x1d00 0x00060000>;
+ qcom,sde-vig-igc = <0x1d00 0x00060000>;
+ qcom,sde-vig-inverse-pma;
+ };
+
+ qcom,sde-sspp-dma-blocks {
+ dgm@0 {
+ qcom,sde-dma-igc = <0x400 0x00050000>;
+ qcom,sde-dma-gc = <0x600 0x00050000>;
+ qcom,sde-dma-inverse-pma;
+ qcom,sde-dma-csc-off = <0x200>;
+ };
+
+ dgm@1 {
+ qcom,sde-dma-igc = <0x1400 0x00050000>;
+ qcom,sde-dma-gc = <0x600 0x00050000>;
+ qcom,sde-dma-inverse-pma;
+ qcom,sde-dma-csc-off = <0x1200>;
+ };
+ };
+
+ qcom,sde-dspp-blocks {
+ qcom,sde-dspp-igc = <0x0 0x00030001>;
+ qcom,sde-dspp-hsic = <0x800 0x00010007>;
+ qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+ qcom,sde-dspp-hist = <0x800 0x00010007>;
+ qcom,sde-dspp-sixzone= <0x900 0x00010007>;
+ qcom,sde-dspp-vlut = <0xa00 0x00010008>;
+ qcom,sde-dspp-gamut = <0x1000 0x00040002>;
+ qcom,sde-dspp-pcc = <0x1700 0x00040000>;
+ qcom,sde-dspp-gc = <0x17c0 0x00010008>;
+ qcom,sde-dspp-dither = <0x82c 0x00010007>;
+ };
+
+ smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
+ compatible = "qcom,smmu_sde_unsec";
+ iommus = <&apps_smmu 0x800 0x2>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-earlymap; /* for cont-splash */
+ };
+
+ smmu_sde_sec: qcom,smmu_sde_sec_cb {
+ compatible = "qcom,smmu_sde_sec";
+ iommus = <&apps_smmu 0x801 0x0>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xa>;
+ };
+
+ /* data and reg bus scale settings */
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "mdss_sde";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>,
+ <22 512 0 6400000>,
+ <22 512 0 6400000>;
+ };
+
+ qcom,sde-reg-bus {
+ qcom,msm-bus,name = "mdss_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 150000>,
+ <1 590 0 300000>;
+ };
+
+ qcom,sde-limits {
+ qcom,sde-linewidth-limits {
+ qcom,sde-limit-name = "sspp_linewidth_usecases";
+ qcom,sde-limit-cases = "vig", "dma",
+ "scale", "inline_rot";
+ qcom,sde-limit-ids= <0x1 0x2 0x4 0x8>;
+ qcom,sde-limit-values = <0x1 4096>,
+ <0x5 2560>,
+ <0x2 2160>,
+ <0x9 1088>;
+ };
+
+ qcom,sde-bw-limits {
+ qcom,sde-limit-name = "sde_bwlimit_usecases";
+ qcom,sde-limit-cases = "per_vig_pipe",
+ "per_dma_pipe",
+ "total_max_bw",
+ "camera_concurrency",
+ "cwb_concurrency";
+ qcom,sde-limit-ids = <0x1 0x2 0x4 0x8 0x10>;
+ qcom,sde-limit-values = <0x1 3200000>,
+ <0x11 3200000>,
+ <0x9 3200000>,
+ <0x19 3200000>,
+ <0x2 3200000>,
+ <0x12 3200000>,
+ <0xa 3200000>,
+ <0x1a 3200000>,
+ <0x4 5900000>,
+ <0x14 5900000>,
+ <0xc 4400000>,
+ <0x1c 4400000>;
+ };
+ };
+ };
+
+ sde_rscc: qcom,sde_rscc {
+ cell-index = <0>;
+ compatible = "qcom,sde-rsc";
+ reg = <0xaf20000 0x3c50>,
+ <0xaf30000 0x3fd4>;
+ reg-names = "drv", "wrapper";
+ qcom,sde-rsc-version = <3>;
+
+ qcom,sde-dram-channels = <2>;
+
+ vdd-supply = <&mdss_core_gdsc>;
+ clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
+ clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
+
+ /* data and reg bus scale settings */
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "disp_rsc_mnoc_llcc";
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <20003 20513 0 0>,
+ <20003 20513 0 6400000>,
+ <20003 20513 0 6400000>;
+ };
+
+ qcom,sde-ebi-bus {
+ qcom,msm-bus,name = "disp_rsc_ebi";
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <20000 20512 0 0>,
+ <20000 20512 0 6400000>,
+ <20000 20512 0 6400000>;
+ };
+
+ qcom,sde-reg-bus {
+ qcom,msm-bus,name = "disp_rsc_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 150000>,
+ <1 590 0 300000>;
+ };
+ };
+
+ mdss_dsi0: qcom,mdss_dsi0_ctrl {
+ compatible = "qcom,dsi-ctrl-hw-v2.4";
+ label = "dsi-ctrl-0";
+ cell-index = <0>;
+ frame-threshold-time-us = <1000>;
+ reg = <0xae94000 0x400>,
+ <0xaf08000 0x4>;
+ reg-names = "dsi_ctrl", "disp_cc_base";
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <4 0>;
+ vdda-1p2-supply = <&L22A>;
+ refgen-supply = <&refgen>;
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>;
+ clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+ "pixel_clk", "pixel_clk_rcg", "esc_clk";
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1200000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <21800>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi_phy0: qcom,mdss_dsi_phy0 {
+ compatible = "qcom,dsi-phy-v3.0";
+ label = "dsi-phy-0";
+ cell-index = <0>;
+ reg = <0xae94400 0x800>,
+ <0xae94200 0x100>;
+ reg-names = "dsi_phy", "dyn_refresh_base";
+ vdda-0p9-supply = <&S5A_LEVEL>;
+ qcom,platform-strength-ctrl = [55 03
+ 55 03
+ 55 03
+ 55 03
+ 55 00];
+ qcom,platform-lane-config = [00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 00
+ 00 00 00 80];
+ qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+ qcom,panel-allow-phy-poweroff;
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage =
+ <RPMH_REGULATOR_LEVEL_NOM>;
+ qcom,supply-max-voltage =
+ <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ qcom,supply-off-min-voltage =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+ sde_dp: qcom,dp_display@ae90000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,dp-display";
+
+ vdda-1p2-supply = <&L22A>;
+ vdda-0p9-supply = <&L16A>;
+
+ reg = <0xae90000 0x200>,
+ <0xae90200 0x200>,
+ <0xae90400 0xc00>,
+ <0xae91000 0x400>,
+ <0x88eaa00 0x200>,
+ <0x88ea200 0x200>,
+ <0x88ea600 0x200>,
+ <0xaf01000 0x2d0>,
+ <0x780000 0x6228>,
+ <0x88ea030 0x10>,
+ <0x88e8000 0x20>,
+ <0x0aee1000 0x2a>,
+ <0xae91400 0x400>;
+ reg-names = "dp_ahb", "dp_aux", "dp_link",
+ "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
+ "dp_mmss_cc", "qfprom_physical", "dp_pll",
+ "usb3_dp_com", "hdcp_physical", "dp_p1";
+
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <12 0>;
+
+ qcom,aux-cfg0-settings = [20 00];
+ qcom,aux-cfg1-settings = [24 13 23 1d];
+ qcom,aux-cfg2-settings = [28 24];
+ qcom,aux-cfg3-settings = [2c 00];
+ qcom,aux-cfg4-settings = [30 0a];
+ qcom,aux-cfg5-settings = [34 26];
+ qcom,aux-cfg6-settings = [38 0a];
+ qcom,aux-cfg7-settings = [3c 03];
+ qcom,aux-cfg8-settings = [40 bb];
+ qcom,aux-cfg9-settings = [44 03];
+
+ qcom,max-pclk-frequency-khz = <337500>;
+ qcom,no-mst-encoder;
+
+ clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&rpmhcc RPMH_QLINK_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&mdss_dp_pll DP_PHY_PLL_VCO_DIV_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+
+ clock-names = "core_aux_clk", "core_usb_pipe_clk",
+ "core_usb_ref_clk_src",
+ "core_usb_ref_clk", "core_usb_pipe_clk",
+ "link_clk", "link_iface_clk",
+ "pixel_clk_rcg", "pixel_parent",
+ "strm0_pixel_clk";
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1200000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <21800>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <880000>;
+ qcom,supply-max-voltage = <928000>;
+ qcom,supply-enable-load = <36000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-stub-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-stub-regulator.dtsi
new file mode 100755
index 0000000..d0ed0ea
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-stub-regulator.dtsi
@@ -0,0 +1,433 @@
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+
+/ {
+ S1A:
+ pm6350_s1: regulator-pm6350-s1 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_s1";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ S2A:
+ pm6350_s2: regulator-pm6350-s2 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_s2";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <100000>;
+ regulator-max-microvolt = <3900000>;
+ };
+
+ VDD_GFX_LEVEL:
+ S3A_LEVEL:
+ pm6350_s3_level: regulator-pm6350-s3-level {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_s3_level";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ VDD_MX_LEVEL:
+ S5A_LEVEL:
+ pm6350_s5_level: regulator-pm6350-s5-level {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_s5_level";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ VDD_MX_LEVEL_AO:
+ S5A_LEVEL_AO:
+ pm6350_s5_level_ao: regulator-pm6350-s5-level-ao {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_s5_level_ao";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ S6A:
+ pm6350_s6: regulator-pm6350-s6 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_s6";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <647000>;
+ regulator-max-microvolt = <1290000>;
+ };
+
+ L1A_LEVEL:
+ pm6350_l1_level: regulator-pm6350-l1-level {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l1_level";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ L2A:
+ pm6350_l2: regulator-pm6350-l2 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l2";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ };
+
+ L3A:
+ pm6350_l3: regulator-pm6350-l3 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l3";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+ L4A:
+ pm6350_l4: regulator-pm6350-l4 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l4";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <488000>;
+ regulator-max-microvolt = <950000>;
+ };
+
+ L5A:
+ pm6350_l5: regulator-pm6350-l5 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l5";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <0>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ L6A:
+ pm6350_l6: regulator-pm6350-l6 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l6";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ L7A:
+ pm6350_l7: regulator-pm6350-l7 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l7";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ };
+
+ L8A:
+ pm6350_l8: regulator-pm6350-l8 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l8";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <4400000>;
+ };
+
+ L9A:
+ pm6350_l9: regulator-pm6350-l9 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l9";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <0>;
+ regulator-max-microvolt = <0>;
+ };
+
+ L10A:
+ pm6350_l10: regulator-pm6350-l10 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l10";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <0>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ L11A:
+ pm6350_l11: regulator-pm6350-l11 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l11";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <0>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ L12A:
+ pm6350_l12: regulator-pm6350-l12 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l12";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <1980000>;
+ };
+
+ L13A:
+ pm6350_l13: regulator-pm6350-l13 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l13";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <550000>;
+ regulator-max-microvolt = <650000>;
+ };
+
+ L14A:
+ pm6350_l14: regulator-pm6350-l14 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l14";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1900000>;
+ };
+
+ L15A:
+ pm6350_l15: regulator-pm6350-l15 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l15";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1400000>;
+ };
+
+ L16A:
+ pm6350_l16: regulator-pm6350-l16 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l16";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <830000>;
+ regulator-max-microvolt = <920000>;
+ };
+
+ L17A_LEVEL:
+ pm6350_l17_level: regulator-pm6350-l17-level {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l17_level";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ L18A:
+ pm6350_l18: regulator-pm6350-l18 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l18";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <348000>;
+ regulator-max-microvolt = <990000>;
+ };
+
+ L19A:
+ pm6350_l19: regulator-pm6350-l19 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l19";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <0>;
+ regulator-max-microvolt = <1236000>;
+ };
+
+ L20A:
+ pm6350_l20: regulator-pm6350-l20 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l20";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <530000>;
+ regulator-max-microvolt = <800000>;
+ };
+
+ L21A:
+ pm6350_l21: regulator-pm6350-l21 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l21";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <751000>;
+ regulator-max-microvolt = <824000>;
+ };
+
+ L22A:
+ pm6350_l22: regulator-pm6350-l22 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6350_l22";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1980000>;
+ };
+
+ BOB: pm6150a_bob: regulator-pm6150a-bob {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_bob";
+ regulator-min-microvolt = <100000>;
+ regulator-max-microvolt = <5500000>;
+ };
+
+ BOB_AO: pm6150a_bob_ao: regulator-pm6150a-bob-ao {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_bob_ao";
+ regulator-min-microvolt = <100000>;
+ regulator-max-microvolt = <5500000>;
+ };
+
+ VDD_CX_LEVEL:
+ S1E_LEVEL:
+ pm6150a_s1_level: regulator-pm6150a-s1-level {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_s1_level";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ VDD_CX_LEVEL_AO:
+ S1E_LEVEL_AO:
+ pm6150a_s1_level_ao: regulator-pm6150a-s1-level-ao {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_s1_level_ao";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ cx_cdev: regulator-cdev {
+ compatible = "qcom,rpmh-reg-cdev";
+ mboxes = <&qmp_aop 0>;
+ qcom,reg-resource-name = "cx";
+ #cooling-cells = <2>;
+ };
+
+ VDD_MSS_LEVEL:
+ S6E_LEVEL:
+ pm6150a_s6_level: regulator-pm6150a-s6-level {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_s6_level";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ S8E:
+ pm6150a_s8: regulator-pm6150a-s8 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_s8";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <2050000>;
+ };
+
+ L1E:
+ pm6150a_l1: regulator-pm6150a-l1 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_l1";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ };
+
+ L2E:
+ pm6150a_l2: regulator-pm6150a-l2 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_l2";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1170000>;
+ regulator-max-microvolt = <1430000>;
+ };
+
+ L3E:
+ pm6150a_l3: regulator-pm6150a-l3 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_l3";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ L4E:
+ pm6150a_l4: regulator-pm6150a-l4 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_l4";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ L5E:
+ pm6150a_l5: regulator-pm6150a-l5 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_l5";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ L6E:
+ pm6150a_l6: regulator-pm6150a-l6 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_l6";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ L7E:
+ pm6150a_l7: regulator-pm6150a-l7 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_l7";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3599000>;
+ };
+
+ L8E:
+ pm6150a_l8: regulator-pm6150a-l8 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_l8";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ L9E:
+ pm6150a_l9: regulator-pm6150a-l9 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_l9";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ L10E:
+ pm6150a_l10: regulator-pm6150a-l10 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_l10";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ L11E:
+ pm6150a_l11: regulator-pm6150a-l11 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm6150a_l11";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3600000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-thermal-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-thermal-overlay.dtsi
new file mode 100755
index 0000000..11cc348
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-thermal-overlay.dtsi
@@ -0,0 +1,179 @@
+#include <dt-bindings/thermal/thermal.h>
+
+&mdss_mdp {
+ #cooling-cells = <2>;
+};
+
+&thermal_zones {
+ pm7250b-tz {
+ cooling-maps {
+ trip0_bat {
+ trip = <&pm7250b_trip0>;
+ cooling-device =
+ <&pm7250b_charger (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ trip1_bat {
+ trip = <&pm7250b_trip1>;
+ cooling-device =
+ <&pm7250b_charger THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+
+ pm6150l-tz {
+ cooling-maps {
+ trip0_cpu0 {
+ trip = <&pm6150l_trip0>;
+ cooling-device =
+ <&CPU0 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ trip0_cpu6 {
+ trip = <&pm6150l_trip0>;
+ cooling-device =
+ <&CPU6 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ trip1_cpu1 {
+ trip = <&pm6150l_trip1>;
+ cooling-device = <&cpu1_isolate 1 1>;
+ };
+
+ trip1_cpu2 {
+ trip = <&pm6150l_trip1>;
+ cooling-device = <&cpu2_isolate 1 1>;
+ };
+
+ trip1_cpu3 {
+ trip = <&pm6150l_trip1>;
+ cooling-device = <&cpu3_isolate 1 1>;
+ };
+
+ trip1_cpu4 {
+ trip = <&pm6150l_trip1>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+
+ trip1_cpu5 {
+ trip = <&pm6150l_trip1>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+
+ trip1_cpu6 {
+ trip = <&pm6150l_trip1>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ trip1_cpu7 {
+ trip = <&pm6150l_trip1>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ soc {
+ cooling-maps {
+ soc_cpu6 {
+ trip = <&soc_trip>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ soc_cpu7 {
+ trip = <&soc_trip>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pm7250b-bcl-lvl0 {
+ cooling-maps {
+ lbat0_cpu6 {
+ trip = <&b_bcl_lvl0>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ lbat0_cpu7 {
+ trip = <&b_bcl_lvl0>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pm7250b-bcl-lvl1 {
+ cooling-maps {
+ lbat1_cpu6 {
+ trip = <&b_bcl_lvl1>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ lbat1_cpu7 {
+ trip = <&b_bcl_lvl1>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pm7250b-bcl-lvl2 {
+ cooling-maps {
+ lbat2_cpu6 {
+ trip = <&b_bcl_lvl2>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ lbat2_cpu7 {
+ trip = <&b_bcl_lvl2>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pm6150l-bcl-lvl0 {
+ disable-thermal-zone;
+ cooling-maps {
+ vph_cpu6 {
+ trip = <&l_bcl_lvl0>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ vph_cpu7 {
+ trip = <&l_bcl_lvl0>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pm6150l-bcl-lvl1 {
+ disable-thermal-zone;
+ cooling-maps {
+ vph_cpu6 {
+ trip = <&l_bcl_lvl1>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ vph_cpu7 {
+ trip = <&l_bcl_lvl1>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pm6150l-bcl-lvl2 {
+ disable-thermal-zone;
+ cooling-maps {
+ vph_cpu6 {
+ trip = <&l_bcl_lvl2>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ vph_cpu7 {
+ trip = <&l_bcl_lvl2>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-thermal.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-thermal.dtsi
new file mode 100755
index 0000000..cc536ca
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-thermal.dtsi
@@ -0,0 +1,1621 @@
+#include <dt-bindings/thermal/thermal.h>
+#include "sdxprairie-thermal-integrated.dtsi"
+
+&cpufreq_hw {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,cpu-isolation {
+ compatible = "qcom,cpu-isolate";
+ cpu0_isolate: cpu0-isolate {
+ qcom,cpu = <&CPU0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1_isolate: cpu1-isolate {
+ qcom,cpu = <&CPU1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2_isolate: cpu2-isolate {
+ qcom,cpu = <&CPU2>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3_isolate: cpu3-isolate {
+ qcom,cpu = <&CPU3>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4_isolate: cpu4-isolate {
+ qcom,cpu = <&CPU4>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5_isolate: cpu5-isolate {
+ qcom,cpu = <&CPU5>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6_isolate: cpu6-isolate {
+ qcom,cpu = <&CPU6>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7_isolate: cpu7-isolate {
+ qcom,cpu = <&CPU7>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ lmh_dcvs0: qcom,limits-dcvs@18358800 {
+ compatible = "qcom,msm-hw-limits";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,affinity = <0>;
+ reg = <0x18358800 0x1000>,
+ <0x18323000 0x1000>;
+ qcom,no-cooling-device-register;
+ };
+
+ lmh_dcvs1: qcom,limits-dcvs@18350800 {
+ compatible = "qcom,msm-hw-limits";
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,affinity = <1>;
+ reg = <0x18350800 0x1000>,
+ <0x18325800 0x1000>;
+ qcom,no-cooling-device-register;
+ };
+};
+
+&soc {
+ lmh_cpu_vdd0: qcom,lmh-cpu-vdd@18358800 {
+ compatible = "qcom,lmh-cpu-vdd";
+ reg = <0x18358800 0x1000>;
+ #cooling-cells = <2>;
+ };
+
+ lmh_cpu_vdd1: qcom,lmh-cpu-vdd@18350800 {
+ compatible = "qcom,lmh-cpu-vdd";
+ reg = <0x18350800 0x1000>;
+ #cooling-cells = <2>;
+ };
+
+ qmi-tmd-devices {
+ cdsp {
+ qcom,instance-id = <QMI_CDSP_INST_ID>;
+
+ cdsp_sw: cdsp {
+ qcom,qmi-dev-name = "cdsp_sw";
+ #cooling-cells = <2>;
+ };
+
+ cdsp_hw: hvx {
+ qcom,qmi-dev-name = "cdsp_hw";
+ #cooling-cells = <2>;
+ };
+ };
+ };
+
+ cxip_cdev: cxip-cdev@1fed000 {
+ status = "disabled";
+
+ compatible = "qcom,cxip-lm-cooling-device";
+ reg = <0x1fed000 0x10060>;
+ qcom,thermal-client-offset = <0x8000>;
+ qcom,bypass-client-list = <0xe00c 0xf00c 0x1000c 0x1001c
+ 0x1002c 0x1003c 0x1004c 0x1005c>;
+ #cooling-cells = <2>;
+ };
+};
+
+&thermal_zones {
+ aoss-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 0>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 1>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 3>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 4>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-4-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 5>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-5-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 6>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 7>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 8>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 9>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 10>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 11>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 12>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 13>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 14>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ aoss-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens1 0>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cwlan-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens1 1>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ audio-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens1 2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ ddr-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens1 3>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ q6-hvx-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens1 4>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens1 5>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-core-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens1 6>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-core-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens1 7>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-vec-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens1 8>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-scl-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens1 9>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ npu-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens1 10>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ video-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens1 11>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-max-step {
+ polling-delay-passive = <10>;
+ polling-delay = <100>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ gpu_trip0: gpu-trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ gpu_cdev {
+ trip = <&gpu_trip0>;
+ cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu-0-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 1>;
+ wake-capable-sensor;
+ trips {
+ cpu00_config: cpu00-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu00_cdev {
+ trip = <&cpu00_config>;
+ cooling-device = <&cpu0_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 2>;
+ wake-capable-sensor;
+ trips {
+ cpu01_config: cpu01-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu01_cdev {
+ trip = <&cpu01_config>;
+ cooling-device = <&cpu1_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-2-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 3>;
+ wake-capable-sensor;
+ trips {
+ cpu02_config: cpu02-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu02_cdev {
+ trip = <&cpu02_config>;
+ cooling-device = <&cpu2_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-3-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 4>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu03_config: cpu03-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu03_cdev {
+ trip = <&cpu03_config>;
+ cooling-device = <&cpu3_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-4-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 5>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu04_config: cpu04-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu04_cdev {
+ trip = <&cpu04_config>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-5-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 6>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu05_config: cpu05-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu05_cdev {
+ trip = <&cpu05_config>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 9>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu10_config: cpu10-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu10_cdev {
+ trip = <&cpu10_config>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 10>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu11_config: cpu11-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu11_cdev {
+ trip = <&cpu11_config>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-2-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 11>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu12_config: cpu12-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu12_cdev {
+ trip = <&cpu12_config>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-3-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 12>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu13_config: cpu13-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu13_cdev {
+ trip = <&cpu13_config>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ q6-hvx-step {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 4>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cxip_trip: cxip-trip {
+ temperature = <95000>;
+ hysteresis = <20000>;
+ type = "passive";
+ };
+
+ q6_hvx_trip0: q6-hvx-trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ q6_hvx_trip1: q6-hvx-trip1 {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cxip-cdev {
+ trip = <&cxip_trip>;
+ cooling-device = <&cxip_cdev 1 1>;
+ };
+
+ cdsp-cdev0 {
+ trip = <&q6_hvx_trip0>;
+ cooling-device = <&cdsp_sw THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+
+ cdsp-cdev1 {
+ trip = <&q6_hvx_trip1>;
+ cooling-device = <&cdsp_sw 4 4>;
+ };
+
+ modem-pa-cdev {
+ trip = <&q6_hvx_trip1>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&q6_hvx_trip1>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&q6_hvx_trip1>;
+ cooling-device = <&msm_npu THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ gpu-cdev {
+ trip = <&q6_hvx_trip1>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-2)
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+ };
+ };
+
+ chg-skin-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm7250b_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ conn-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm7250b_adc_tm ADC_AMUX_THM3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ sdm-skin-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm6150l_adc_tm_iio ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ rfc-cam-pa3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm6150l_adc_tm_iio ADC_GPIO2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm6150l_adc_tm ADC_GPIO3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ quiet-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm6150l_adc_tm ADC_GPIO4_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa-therm0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm6150l_adc_tm ADC_AMUX_THM3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa-therm1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm6150l_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pmk8350_adc_tm PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ active-config1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ npu-step {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 10>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ npu_trip0: npu-trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ npu_cdev {
+ trip = <&npu_trip0>;
+ cooling-device =
+ <&msm_npu THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ mdm-core-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 6>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ modem_core_0_trip0: modem-core-0-trip0 {
+ temperature = <95000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_core_0_trip1: modem-core-0-trip1 {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_core_0_trip2: modem-core-0-trip2 {
+ temperature = <115000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ modem_tj1_cdev {
+ trip = <&modem_core_0_trip0>;
+ cooling-device = <&modem_tj 1 1>;
+ };
+
+ modem_tj2_cdev {
+ trip = <&modem_core_0_trip1>;
+ cooling-device = <&modem_tj 2 2>;
+ };
+
+ modem_tj3_cdev {
+ trip = <&modem_core_0_trip2>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+ };
+ };
+
+ mdm-core-1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 7>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ modem_core_1_trip0: modem-core-1-trip0 {
+ temperature = <95000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_core_1_trip1: modem-core-1-trip1 {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_core_1_trip2: modem-core-1-trip2 {
+ temperature = <115000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ modem_tj1_cdev {
+ trip = <&modem_core_1_trip0>;
+ cooling-device = <&modem_tj 1 1>;
+ };
+
+ modem_tj2_cdev {
+ trip = <&modem_core_1_trip1>;
+ cooling-device = <&modem_tj 2 2>;
+ };
+
+ modem_tj3_cdev {
+ trip = <&modem_core_1_trip2>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+ };
+ };
+
+ mdm-vec-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 8>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ modem_vec_trip0: modem-vec-trip0 {
+ temperature = <95000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_vec_trip1: modem-vec-trip1 {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_vec_trip2: modem-vec-trip2 {
+ temperature = <115000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ modem_tj1_cdev {
+ trip = <&modem_vec_trip0>;
+ cooling-device = <&modem_tj 1 1>;
+ };
+
+ modem_tj2_cdev {
+ trip = <&modem_vec_trip1>;
+ cooling-device = <&modem_tj 2 2>;
+ };
+
+ modem_tj3_cdev {
+ trip = <&modem_vec_trip2>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+ };
+ };
+
+ mdm-scl-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 9>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ modem_scl_trip0: modem-scl-trip0 {
+ temperature = <95000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_scl_trip1: modem-scl-trip1 {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_scl_trip2: modem-scl-trip2 {
+ temperature = <115000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ modem_tj1_cdev {
+ trip = <&modem_scl_trip0>;
+ cooling-device = <&modem_tj 1 1>;
+ };
+
+ modem_tj2_cdev {
+ trip = <&modem_scl_trip1>;
+ cooling-device = <&modem_tj 2 2>;
+ };
+
+ modem_tj3_cdev {
+ trip = <&modem_scl_trip2>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+ };
+ };
+
+ min-temp-0-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 16>;
+ thermal-governor = "low_limits_floor";
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ min_temp_0_lowf: active-config0 {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ wcss_cx_vdd_cdev {
+ trip = <&min_temp_0_lowf>;
+ cooling-device = <&cx_cdev 0 0>;
+ };
+ };
+ };
+
+ min-temp-0-lowc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 16>;
+ thermal-governor = "low_limits_cap";
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ min_temp_0_lowc: active-config0 {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ lmh_cpu0_cdev {
+ trip = <&min_temp_0_lowc>;
+ cooling-device = <&lmh_cpu_vdd0 1 1>;
+ };
+
+ lmh_cpu6_cdev {
+ trip = <&min_temp_0_lowc>;
+ cooling-device = <&lmh_cpu_vdd1 1 1>;
+ };
+ };
+ };
+
+ min-temp-1-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 16>;
+ thermal-governor = "low_limits_floor";
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ min_temp_1_lowf: active-config0 {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ wcss_cx_vdd_cdev {
+ trip = <&min_temp_1_lowf>;
+ cooling-device = <&cx_cdev 0 0>;
+ };
+ };
+ };
+
+ min-temp-1-lowc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 16>;
+ thermal-governor = "low_limits_cap";
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ min_temp_1_lowc: active-config0 {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ lmh_cpu0_cdev {
+ trip = <&min_temp_1_lowc>;
+ cooling-device = <&lmh_cpu_vdd0 1 1>;
+ };
+
+ lmh_cpu6_cdev {
+ trip = <&min_temp_1_lowc>;
+ cooling-device = <&lmh_cpu_vdd1 1 1>;
+ };
+ };
+ };
+
+ quiet-therm-step {
+ polling-delay-passive = <2000>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm6150l_adc_tm ADC_GPIO4_PU2>;
+ wake-capable-sensor;
+
+ trips {
+ modem_skin_trip0: modem-skin-trip0 {
+ temperature = <40000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ modem_skin_trip1: modem-skin-trip1 {
+ temperature = <41000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ skin_batt_trip0: batt-skin-trip0 {
+ temperature = <41000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ modem_skin_trip2: modem-skin-trip2 {
+ temperature = <42000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ gold_trip: gold-trip {
+ temperature = <43000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ skin_batt_modem_trip: batt-modem-skin-trip {
+ temperature = <43000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ skin_batt_trip2: batt-skin-trip2 {
+ temperature = <45000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu_skin_trip: gpu-skin-trip {
+ temperature = <45000>;
+ hysteresis = <3000>;
+ type = "passive";
+ };
+
+ skin_batt_trip3: batt-skin-trip3 {
+ temperature = <47000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ silver_trip: silver-trip {
+ temperature = <48000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ skin_batt_trip4: batt-skin-trip4 {
+ temperature = <48000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ cx_emer_trip: cx-emer-trip {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ skin_cpu6 {
+ trip = <&gold_trip>;
+ /* throttle from fmax to 1555200KHz */
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-6)>;
+ };
+
+ skin_cpu0 {
+ trip = <&silver_trip>;
+ /* throttle from fmax to 1516800KHz */
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-6)>;
+ };
+
+ skin_gpu {
+ trip = <&gpu_skin_trip>;
+ /* throttle to 650000000Hz */
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-4)
+ (THERMAL_MAX_LIMIT-4)>;
+ };
+
+ skin_gpu_emrg {
+ trip = <&cx_emer_trip>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-2)
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ skin_cdsp {
+ trip = <&cx_emer_trip>;
+ cooling-device = <&cdsp_sw 4 4>;
+ };
+
+ skin_npu {
+ trip = <&cx_emer_trip>;
+ cooling-device = <&msm_npu THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ skin_modem_skin_cdev0 {
+ trip = <&modem_skin_trip0>;
+ cooling-device = <&modem_skin 1 1>;
+ };
+
+ skin_modem_skin_cdev1 {
+ trip = <&modem_skin_trip1>;
+ cooling-device = <&modem_skin 2 2>;
+ };
+
+ skin_modem_skin_cdev2 {
+ trip = <&cx_emer_trip>;
+ cooling-device = <&modem_skin 3 3>;
+ };
+
+ skin_modem_cdev0 {
+ trip = <&modem_skin_trip2>;
+ cooling-device = <&modem_pa 1 1>;
+ };
+
+ skin_modem_cdev1 {
+ trip = <&skin_batt_modem_trip>;
+ cooling-device = <&modem_pa 2 2>;
+ };
+
+ skin_modem_cdev2 {
+ trip = <&cx_emer_trip>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem_pa_fr1_cdev0 {
+ trip = <&modem_skin_trip2>;
+ cooling-device = <&modem_pa_fr1 1 1>;
+ };
+
+ modem_pa_fr1_cdev1 {
+ trip = <&skin_batt_modem_trip>;
+ cooling-device = <&modem_pa_fr1 2 2>;
+ };
+
+ modem_pa_fr1_cdev2 {
+ trip = <&cx_emer_trip>;
+ cooling-device = <&modem_pa_fr1 3 3>;
+ };
+
+ batt_cdev0 {
+ trip = <&skin_batt_trip0>;
+ cooling-device = <&pm7250b_charger 8 8>;
+ };
+
+ batt_cdev1 {
+ trip = <&skin_batt_modem_trip>;
+ cooling-device = <&pm7250b_charger 12 12>;
+ };
+
+ batt_cdev2 {
+ trip = <&skin_batt_trip2>;
+ cooling-device = <&pm7250b_charger 14 14>;
+ };
+
+ batt_cdev3 {
+ trip = <&skin_batt_trip3>;
+ cooling-device = <&pm7250b_charger 16 16>;
+ };
+
+ batt_cdev4 {
+ trip = <&skin_batt_trip4>;
+ cooling-device = <&pm7250b_charger 18 18>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-usb.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-usb.dtsi
new file mode 100755
index 0000000..be23fe3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-usb.dtsi
@@ -0,0 +1,376 @@
+#include <dt-bindings/clock/qcom,gcc-lagoon.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/phy/qcom,lagoon-qmp-usb3.h>
+
+&soc {
+ usb0: ssusb@a600000 {
+ compatible = "qcom,dwc-usb3-msm";
+ reg = <0x0a600000 0x200000>;
+ reg-names = "core_base";
+
+ iommus = <&apps_smmu 0x540 0x0>;
+ qcom,iommu-dma = "atomic";
+ qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupts-extended = <&pdc 14 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 15 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+ "ss_phy_irq", "dm_hs_phy_irq";
+ qcom,use-pdc-interrupts;
+
+ USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
+ dpdm-supply = <&qusb_phy0>;
+
+ clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
+ clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+ "utmi_clk", "sleep_clk", "xo";
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+ reset-names = "core_reset";
+
+ qcom,core-clk-rate = <133333333>;
+ qcom,core-clk-rate-hs = <66666667>;
+ qcom,num-gsi-evt-buffs = <0x3>;
+ qcom,gsi-reg-offset =
+ <0x0fc /* GSI_GENERAL_CFG */
+ 0x110 /* GSI_DBL_ADDR_L */
+ 0x120 /* GSI_DBL_ADDR_H */
+ 0x130 /* GSI_RING_BASE_ADDR_L */
+ 0x144 /* GSI_RING_BASE_ADDR_H */
+ 0x1a4>; /* GSI_IF_STS */
+ qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
+ qcom,pm-qos-latency = <61>; /* CPU0-WFI-LVL latency +1 */
+
+ qcom,gsi-disable-io-coherency;
+
+ qcom,msm-bus,name = "usb0";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ /* suspend vote */
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>,
+
+ /* nominal vote */
+ <MSM_BUS_MASTER_USB3
+ MSM_BUS_SLAVE_EBI_CH0 1000000 2500000>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+ /* svs vote */
+ <MSM_BUS_MASTER_USB3
+ MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+ /* min vote */
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 1 1>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 1 1>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 1 1>;
+
+ dwc3@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0a600000 0xe000>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ usb-phy = <&qusb_phy0>, <&usb_qmp_dp_phy>;
+ linux,sysdev_is_parent;
+ snps,disable-clk-gating;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3-u1u2-disable;
+ usb-core-id = <0>;
+ tx-fifo-resize;
+ maximum-speed = "super-speed";
+ dr_mode = "drd";
+ };
+ qcom,usbbam@a704000 {
+ compatible = "qcom,usb-bam-msm";
+ reg = <0xa704000 0x17000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,usb-bam-fifo-baseaddr = <0x146a6000>;
+ qcom,usb-bam-num-pipes = <4>;
+ qcom,disable-clk-gating;
+ qcom,usb-bam-override-threshold = <0x4001>;
+ qcom,usb-bam-max-mbps-highspeed = <400>;
+ qcom,usb-bam-max-mbps-superspeed = <3600>;
+ qcom,reset-bam-on-connect;
+
+ qcom,pipe0 {
+ label = "ssusb-qdss-in-0";
+ qcom,usb-bam-mem-type = <2>;
+ qcom,dir = <1>;
+ qcom,pipe-num = <0>;
+ qcom,peer-bam = <0>;
+ qcom,peer-bam-physical-address = <0x6064000>;
+ qcom,src-bam-pipe-index = <0>;
+ qcom,dst-bam-pipe-index = <0>;
+ qcom,data-fifo-offset = <0x0>;
+ qcom,data-fifo-size = <0x1800>;
+ qcom,descriptor-fifo-offset = <0x1800>;
+ qcom,descriptor-fifo-size = <0x800>;
+ };
+ };
+
+ };
+
+ usb_nop_phy: usb_nop_phy {
+ compatible = "usb-nop-xceiv";
+ };
+
+ /* Primary USB port related QUSB2 PHY */
+ qusb_phy0: qusb@88e3000 {
+ compatible = "qcom,qusb2phy-v2";
+ reg = <0x088e3000 0x400>,
+ <0x00780268 0x4>,
+ <0x088e7014 0x4>,
+ <0x088e2000 0x4>;
+ reg-names = "qusb_phy_base", "efuse_addr",
+ "refgen_north_bg_reg_addr",
+ "eud_enable_reg";
+
+ qcom,efuse-bit-pos = <25>;
+ qcom,efuse-num-bits = <3>;
+ vdd-supply = <&L18A>;
+ vdda18-supply = <&L2A>;
+ vdda33-supply = <&L3A>;
+ refgen-supply = <&L22A>;
+ qcom,vdd-voltage-level = <0 880000 880000>;
+ qcom,qusb-phy-reg-offset =
+ <0x240 /* QUSB2PHY_PORT_TUNE1 */
+ 0x1a0 /* QUSB2PHY_PLL_COMMON_STATUS_ONE */
+ 0x210 /* QUSB2PHY_PWR_CTRL1 */
+ 0x230 /* QUSB2PHY_INTR_CTRL */
+ 0x0a8 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE */
+ 0x254 /* QUSB2PHY_TEST1 */
+ 0x198 /* PLL_BIAS_CONTROL_2 */
+ 0x27c /* QUSB2PHY_DEBUG_CTRL1 */
+ 0x280 /* QUSB2PHY_DEBUG_CTRL2 */
+ 0x284 /* QUSB2PHY_DEBUG_CTRL3 */
+ 0x288 /* QUSB2PHY_DEBUG_CTRL4 */
+ 0x2a0>; /* QUSB2PHY_STAT5 */
+
+ qcom,qusb-phy-init-seq =
+ /* <value reg_offset> */
+ <0x23 0x210 /* PWR_CTRL1 */
+ 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
+ 0x7c 0x18c /* PLL_CLOCK_INVERTERS */
+ 0x80 0x2c /* PLL_CMODE */
+ 0x0a 0x184 /* PLL_LOCK_DELAY */
+ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
+ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */
+ 0x1f 0x198 /* PLL_BIAS_CONTROL_2 */ //tianlang modify for pf4
+ 0x21 0x214 /* PWR_CTRL2 */
+ 0x08 0x220 /* IMP_CTRL1 */
+ 0x58 0x224 /* IMP_CTRL2 */
+ 0x00 0x240 /* TUNE1 */ //tianlang modify for pf4
+ 0x29 0x244 /* TUNE2 */
+ 0xca 0x248 /* TUNE3 */
+ 0x04 0x24c /* TUNE4 */
+ 0x03 0x250 /* TUNE5 */
+ 0x30 0x23c /* CHG_CTRL2 */
+ 0x22 0x210>; /* PWR_CTRL1 */
+
+ qcom,qusb-phy-host-init-seq =
+ /* <value reg_offset> */
+ <0x23 0x210 /* PWR_CTRL1 */
+ 0x03 0x04 /* PLL_ANALOG_CONTROLS_TWO */
+ 0x7c 0x18c /* PLL_CLOCK_INVERTERS */
+ 0x80 0x2c /* PLL_CMODE */
+ 0x0a 0x184 /* PLL_LOCK_DELAY */
+ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */
+ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */
+ 0x1f 0x198 /* PLL_BIAS_CONTROL_2 */ //tianlang modify for pf4
+ 0x21 0x214 /* PWR_CTRL2 */
+ 0x08 0x220 /* IMP_CTRL1 */
+ 0x58 0x224 /* IMP_CTRL2 */
+ 0x00 0x240 /* TUNE1 */ //tianlang modify for pf4
+ 0x29 0x244 /* TUNE2 */
+ 0xca 0x248 /* TUNE3 */
+ 0x04 0x24c /* TUNE4 */
+ 0x03 0x250 /* TUNE5 */
+ 0x30 0x23c /* CHG_CTRL2 */
+ 0x22 0x210>; /* PWR_CTRL1 */
+
+ phy_type= "utmi";
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref_clk_src";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ reset-names = "phy_reset";
+ };
+
+ /* Primary USB port related QMP USB DP Combo PHY */
+ usb_qmp_dp_phy: ssphy@88e8000 {
+ compatible = "qcom,usb-ssphy-qmp-dp-combo";
+ reg = <0x88e8000 0x3000>;
+ reg-names = "qmp_phy_base";
+ vdd-supply = <&L16A>;
+ qcom,vdd-voltage-level = <0 880000 880000>;
+ core-supply = <&L22A>;
+ qcom,vbus-valid-override;
+ qcom,qmp-phy-init-seq =
+ /* <reg_offset, value, delay> */
+ <USB3_DP_QSERDES_COM_PLL_IVCO 0x07 0
+ USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x14 0
+ USB3_DP_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x08 0
+ USB3_DP_QSERDES_COM_CLK_SELECT 0x30 0
+ USB3_DP_QSERDES_COM_SYS_CLK_CTRL 0x02 0
+ USB3_DP_QSERDES_COM_RESETSM_CNTRL2 0x08 0
+ USB3_DP_QSERDES_COM_CMN_CONFIG 0x16 0
+ USB3_DP_QSERDES_COM_SVS_MODE_CLK_SEL 0x01 0
+ USB3_DP_QSERDES_COM_HSCLK_SEL 0x80 0
+ USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
+ USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
+ USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
+ USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
+ USB3_DP_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00 0
+ USB3_DP_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x3f 0
+ USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0 0x01 0
+ USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0xc9 0
+ USB3_DP_QSERDES_COM_CORECLK_DIV_MODE0 0x0a 0
+ USB3_DP_QSERDES_COM_LOCK_CMP3_MODE0 0x00 0
+ USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
+ USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x15 0
+ USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
+ USB3_DP_QSERDES_COM_CORE_CLK_EN 0x00 0
+ USB3_DP_QSERDES_COM_LOCK_CMP_CFG 0x00 0
+ USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x00 0
+ USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a 0
+ USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
+ USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
+ USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
+ USB3_DP_QSERDES_COM_SSC_ADJ_PER1 0x00 0
+ USB3_DP_QSERDES_COM_SSC_ADJ_PER2 0x00 0
+ USB3_DP_QSERDES_COM_SSC_STEP_SIZE1 0x85 0
+ USB3_DP_QSERDES_COM_SSC_STEP_SIZE2 0x07 0
+ USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x0b 0
+ USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
+ USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4e 0
+ USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x18 0
+ USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
+ USB3_DP_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
+ USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x03 0
+ USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x16 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00 0x05 0
+ USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x03 0
+ USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x0b 0
+ USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0f 0
+ USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4e 0
+ USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18 0
+ USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
+ USB3_DP_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0
+ USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x03 0
+ USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x16 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00 0x05 0
+ USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x03 0
+ USB3_DP_QSERDES_TXA_HIGHZ_DRVR_EN 0x10 0
+ USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
+ USB3_DP_QSERDES_TXA_LANE_MODE_1 0x16 0
+ USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x09 0
+ USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x06 0
+ USB3_DP_QSERDES_TXB_HIGHZ_DRVR_EN 0x10 0
+ USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
+ USB3_DP_QSERDES_TXB_LANE_MODE_1 0x16 0
+ USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x09 0
+ USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x06 0
+ USB3_DP_PCS_FLL_CNTRL2 0x83 0
+ USB3_DP_PCS_FLL_CNT_VAL_L 0x09 0
+ USB3_DP_PCS_FLL_CNT_VAL_H_TOL 0xa2 0
+ USB3_DP_PCS_FLL_MAN_CODE 0x40 0
+ USB3_DP_PCS_FLL_CNTRL1 0x02 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xd1 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x1f 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x47 0
+ USB3_DP_PCS_POWER_STATE_CONFIG2 0x1b 0
+ USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x75 0
+ USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x75 0
+ USB3_DP_PCS_RX_SIGDET_LVL 0xcc 0
+ USB3_DP_PCS_TXMGN_V0 0x9f 0
+ USB3_DP_PCS_TXMGN_V1 0x9f 0
+ USB3_DP_PCS_TXMGN_V2 0xb7 0
+ USB3_DP_PCS_TXMGN_V3 0x4e 0
+ USB3_DP_PCS_TXMGN_V4 0x65 0
+ USB3_DP_PCS_TXMGN_LS 0x6b 0
+ USB3_DP_PCS_TXDEEMPH_M6DB_V0 0x15 0
+ USB3_DP_PCS_TXDEEMPH_M3P5DB_V0 0x0d 0
+ USB3_DP_PCS_TXDEEMPH_M6DB_V1 0x15 0
+ USB3_DP_PCS_TXDEEMPH_M3P5DB_V1 0x0d 0
+ USB3_DP_PCS_TXDEEMPH_M6DB_V2 0x15 0
+ USB3_DP_PCS_TXDEEMPH_M3P5DB_V2 0x0d 0
+ USB3_DP_PCS_TXDEEMPH_M6DB_V3 0x15 0
+ USB3_DP_PCS_TXDEEMPH_M3P5DB_V3 0x1d 0
+ USB3_DP_PCS_TXDEEMPH_M6DB_V4 0x15 0
+ USB3_DP_PCS_TXDEEMPH_M3P5DB_V4 0x0d 0
+ USB3_DP_PCS_TXDEEMPH_M6DB_LS 0x15 0
+ USB3_DP_PCS_TXDEEMPH_M3P5DB_LS 0x0d 0
+ USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
+ USB3_DP_PCS_REFGEN_REQ_CONFIG2 0x60 0
+ USB3_DP_PCS_RATE_SLEW_CNTRL 0x02 0
+ USB3_DP_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x04 0
+ USB3_DP_PCS_TSYNC_RSYNC_TIME 0x44 0
+ USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0
+ USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
+ USB3_DP_PCS_RCVR_DTCT_DLY_U3_L 0x40 0
+ USB3_DP_PCS_RCVR_DTCT_DLY_U3_H 0x00 0
+ USB3_DP_PCS_RXEQTRAINING_WAIT_TIME 0x75 0
+ USB3_DP_PCS_LFPS_TX_ECSTART_EQTLOCK 0x86 0
+ USB3_DP_PCS_RXEQTRAINING_RUN_TIME 0x13 0
+ USB3_DP_PCS_LFPS_DET_HIGH_COUNT_VAL 0x04 0
+ 0xffffffff 0xffffffff 0>;
+
+ qcom,qmp-phy-reg-offset =
+ <USB3_DP_PCS_PCS_STATUS
+ USB3_DP_PCS_AUTONOMOUS_MODE_CTRL
+ USB3_DP_PCS_LFPS_RXTERM_IRQ_CLEAR
+ USB3_DP_PCS_POWER_DOWN_CONTROL
+ USB3_DP_PCS_SW_RESET
+ USB3_DP_PCS_START_CONTROL
+ USB3_DP_PCS_MISC_TYPEC_CTRL
+ USB3_DP_PHY_DP_DP_PHY_PD_CTL
+ USB3_DP_COM_POWER_DOWN_CTRL
+ USB3_DP_COM_SW_RESET
+ USB3_DP_COM_RESET_OVRD_CTRL
+ USB3_DP_COM_PHY_MODE_CTRL
+ USB3_DP_COM_TYPEC_CTRL
+ USB3_DP_COM_SWI_CTRL
+ USB3_DP_PCS_MISC_CLAMP_ENABLE>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&rpmhcc RPMH_QLINK_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
+ "ref_clk", "com_aux_clk";
+
+ resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_PHY_PRIM_BCR>;
+ reset-names = "global_phy_reset", "phy_reset";
+ };
+
+ usb_audio_qmi_dev {
+ compatible = "qcom,usb-audio-qmi-dev";
+ iommus = <&apps_smmu 0x100f 0x0>;
+ qcom,iommu-dma = "disabled";
+ qcom,usb-audio-stream-id = <0xf>;
+ qcom,usb-audio-intr-num = <2>;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon-vidc.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon-vidc.dtsi
new file mode 100755
index 0000000..a70fec6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon-vidc.dtsi
@@ -0,0 +1,221 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/clock/qcom,videocc-lagoon.h>
+
+&soc {
+ msm_vidc0: qcom,vidc0 {
+ compatible = "qcom,msm-vidc", "qcom,lagoon-vidc";
+ status = "ok";
+ sku-index = <0>;
+ reg = <0xaa00000 0x0100000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ /* Supply */
+ iris-ctl-supply = <&video_cc_mvsc_gdsc>;
+ vcodec-supply = <&video_cc_mvs0_gdsc>;
+
+ /* Clocks */
+ clock-names = "video_cc_mvsc_ctl_axi",
+ "video_cc_mvs0_ctl_axi", "core_clk",
+ "vcodec_clk", "iface_clk";
+ clocks = <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
+ <&videocc VIDEO_CC_MVS0_AXI_CLK>,
+ <&videocc VIDEO_CC_MVSC_CORE_CLK>,
+ <&videocc VIDEO_CC_MVS0_CORE_CLK>,
+ <&videocc VIDEO_CC_VENUS_AHB_CLK>;
+
+ qcom,proxy-clock-names = "video_cc_mvsc_ctl_axi",
+ "video_cc_mvs0_ctl_axi", "core_clk",
+ "vcodec_clk", "iface_clk";
+
+ qcom,clock-configs = <0x0 0x0 0x1 0x1 0x0>;
+ qcom,allowed-clock-rates = <133250000 240000000
+ 300000000 380000000 460000000>;
+
+ qcom,reg-presets = <0xB0084 0x0>,
+ <0xB0088 0x0>;
+
+ /* Buses */
+ bus_cnoc {
+ compatible = "qcom,msm-vidc,bus";
+ label = "cnoc";
+ qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <762 762>;
+ };
+
+ venus_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "venus-ddr";
+ qcom,bus-range-kbps = <762 15000000>;
+ };
+
+ arm9_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-arm9-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <1000 1000>;
+ };
+
+ /* MMUs */
+ non_secure_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_ns";
+ iommus = <&apps_smmu 0xc00 0x20>;
+ qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
+ qcom,iommu-faults = "non-fatal";
+ buffer-types = <0xfff>;
+ virtual-addr-pool = <0x25800000 0xba800000>;
+ };
+
+ secure_non_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_non_pixel";
+ iommus = <&apps_smmu 0xc04 0x20>;
+ qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
+ buffer-types = <0x480>;
+ virtual-addr-pool = <0x1000000 0x24800000>;
+ qcom,secure-context-bank;
+ };
+
+ secure_bitstream_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_bitstream";
+ iommus = <&apps_smmu 0xc01 0x04>;
+ qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
+ buffer-types = <0x241>;
+ virtual-addr-pool = <0x500000 0xdfb00000>;
+ qcom,secure-context-bank;
+ };
+
+ secure_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_pixel";
+ iommus = <&apps_smmu 0xc03 0x00>;
+ qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
+ buffer-types = <0x106>;
+ virtual-addr-pool = <0x500000 0xdfb00000>;
+ qcom,secure-context-bank;
+ };
+ };
+
+ msm_vidc1: qcom,vidc1 {
+ compatible = "qcom,msm-vidc", "qcom,lagoon-vidc";
+ status = "ok";
+ sku-index = <1>;
+ reg = <0xaa00000 0x0100000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ /* Supply */
+ iris-ctl-supply = <&video_cc_mvsc_gdsc>;
+ vcodec-supply = <&video_cc_mvs0_gdsc>;
+
+ /* Clocks */
+ clock-names = "video_cc_mvsc_ctl_axi",
+ "video_cc_mvs0_ctl_axi", "core_clk",
+ "vcodec_clk", "iface_clk";
+ clocks = <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
+ <&videocc VIDEO_CC_MVS0_AXI_CLK>,
+ <&videocc VIDEO_CC_MVSC_CORE_CLK>,
+ <&videocc VIDEO_CC_MVS0_CORE_CLK>,
+ <&videocc VIDEO_CC_VENUS_AHB_CLK>;
+
+ qcom,proxy-clock-names = "video_cc_mvsc_ctl_axi",
+ "video_cc_mvs0_ctl_axi", "core_clk",
+ "vcodec_clk", "iface_clk";
+
+ qcom,clock-configs = <0x0 0x0 0x1 0x1 0x0>;
+ qcom,allowed-clock-rates = <133250000 240000000
+ 300000000 380000000>;
+
+ qcom,reg-presets = <0xB0084 0x0>,
+ <0xB0088 0x0>;
+
+ /* Buses */
+ bus_cnoc {
+ compatible = "qcom,msm-vidc,bus";
+ label = "cnoc";
+ qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <762 762>;
+ };
+
+ venus_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "venus-ddr";
+ qcom,bus-range-kbps = <762 15000000>;
+ };
+
+ arm9_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-arm9-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <1000 1000>;
+ };
+
+ /* MMUs */
+ non_secure_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_ns";
+ iommus = <&apps_smmu 0xc00 0x20>;
+ qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
+ qcom,iommu-faults = "non-fatal";
+ buffer-types = <0xfff>;
+ virtual-addr-pool = <0x25800000 0xba800000>;
+ };
+
+ secure_non_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_non_pixel";
+ iommus = <&apps_smmu 0xc04 0x20>;
+ qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
+ buffer-types = <0x480>;
+ virtual-addr-pool = <0x1000000 0x24800000>;
+ qcom,secure-context-bank;
+ };
+
+ secure_bitstream_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_bitstream";
+ iommus = <&apps_smmu 0xc01 0x04>;
+ qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
+ buffer-types = <0x241>;
+ virtual-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,secure-context-bank;
+ };
+
+ secure_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_pixel";
+ iommus = <&apps_smmu 0xc03 0x00>;
+ qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
+ buffer-types = <0x106>;
+ virtual-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,secure-context-bank;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon.dts b/arch/arm64/boot/dts/vendor/qcom/lagoon.dts
new file mode 100755
index 0000000..72a3de3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "lagoon.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lagoon SoC";
+ compatible = "qcom,lagoon";
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lagoon.dtsi b/arch/arm64/boot/dts/vendor/qcom/lagoon.dtsi
new file mode 100755
index 0000000..b3bc355
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lagoon.dtsi
@@ -0,0 +1,4098 @@
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,camcc-lagoon.h>
+#include <dt-bindings/clock/qcom,dispcc-lagoon.h>
+#include <dt-bindings/clock/qcom,gcc-lagoon.h>
+#include <dt-bindings/clock/qcom,gpucc-lagoon.h>
+#include <dt-bindings/clock/qcom,npucc-lagoon.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/clock/qcom,videocc-lagoon.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/soc/qcom,dcc_v2.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
+#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lagoon";
+ compatible = "qcom,lagoon";
+ qcom,msm-id = <434 0x10000>, <459 0x10000>;
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+ mem-offline {
+ compatible = "qcom,mem-offline";
+ offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
+ <0x1 0xc0000000 0x0 0x80000000>,
+ <0x2 0xc0000000 0x1 0x40000000>;
+ granule = <512>;
+ mboxes = <&qmp_aop 0>;
+ };
+
+ aliases {
+ ufshc1 = &ufshc_mem; /* Embedded UFS slot */
+ serial0 = &qupv3_se9_2uart; /* Debug Console */
+ sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
+ sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
+ swr0 = &swr0;
+ swr1 = &swr1;
+ swr2 = &swr2;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ qcom,freq-domain = <&cpufreq_hw 0 6>;
+ next-level-cache = <&L2_0>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ #cooling-cells = <2>;
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+
+ L3_0: l3-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <3>;
+ };
+ };
+
+ L1_I_0: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_0: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ qcom,freq-domain = <&cpufreq_hw 0 6>;
+ next-level-cache = <&L2_100>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ L2_100: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_100: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_100: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ qcom,freq-domain = <&cpufreq_hw 0 6>;
+ next-level-cache = <&L2_200>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ L2_200: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_200: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_200: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ qcom,freq-domain = <&cpufreq_hw 0 6>;
+ next-level-cache = <&L2_300>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ L2_300: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_300: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_300: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ qcom,freq-domain = <&cpufreq_hw 0 6>;
+ next-level-cache = <&L2_400>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ L2_400: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_400: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_400: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ qcom,freq-domain = <&cpufreq_hw 0 6>;
+ next-level-cache = <&L2_500>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ L2_500: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_500: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_500: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1894>;
+ dynamic-power-coefficient = <703>;
+ qcom,freq-domain = <&cpufreq_hw 1 2>;
+ next-level-cache = <&L2_600>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+ #cooling-cells = <2>;
+ L2_600: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_600: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_600: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1894>;
+ dynamic-power-coefficient = <703>;
+ qcom,freq-domain = <&cpufreq_hw 1 2>;
+ next-level-cache = <&L2_700>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+ L2_700: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_700: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_700: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+
+ core4 {
+ cpu = <&CPU4>;
+ };
+
+ core5 {
+ cpu = <&CPU5>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU6>;
+ };
+
+ core1 {
+ cpu = <&CPU7>;
+ };
+ };
+
+ };
+ };
+
+ firmware: firmware {
+ android {
+ compatible = "android,firmware";
+ vbmeta {
+ compatible = "android,vbmeta";
+ parts = "vbmeta,boot,system,vendor,dtbo";
+ };
+
+ fstab {
+ compatible = "android,fstab";
+ vendor {
+ compatible = "android,vendor";
+ dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,discard";
+ fsmgr_flags = "wait,slotselect,avb";
+ status = "ok";
+ };
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ chosen {
+ bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 earlycon=msm_geni_serial,0x98c000 kpti=off";
+ };
+
+ soc: soc { };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_region: hyp_region@80000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x80000000 0x0 0x600000>;
+ };
+
+ xbl_aop_mem: xbl_aop_mem@80700000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x80700000 0x0 0x160000>;
+ };
+
+ sec_apps_mem: sec_apps_region@808ff000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x808ff000 0x0 0x1000>;
+ };
+
+ smem_region: smem@80900000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x80900000 0x0 0x200000>;
+ };
+
+ cdsp_sec_mem: cdsp_sec_regions@80b00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x80b00000 0x0 0x1e00000>;
+ };
+
+ pil_camera_mem: camera_region@86000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86000000 0x0 0x500000>;
+ };
+
+ pil_npu_mem: pil_npu_region@86500000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86500000 0x0 0x500000>;
+ };
+
+ pil_video_mem: pil_video_region@86a00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86a00000 0x0 0x500000>;
+ };
+
+ pil_cdsp_mem: cdsp_regions@86f00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86f00000 0x0 0x1e00000>;
+ };
+
+ pil_adsp_mem: pil_adsp_region@88d00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x88d00000 0x0 0x2800000>;
+ };
+
+ wlan_fw_mem: wlan_fw_region@8b500000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8b500000 0x0 0x200000>;
+ };
+
+ pil_ipa_fw_mem: ipa_fw_region@8b700000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8b700000 0x0 0x10000>;
+ };
+
+ pil_ipa_gsi_mem: ipa_gsi_region@8b710000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8b710000 0x0 0x5400>;
+ };
+
+ pil_gpu_mem: gpu_region@8b715400 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8b715400 0x0 0x2000>;
+ };
+
+ pil_modem_mem: modem_region@8b800000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8b800000 0x0 0xf800000>;
+ };
+
+ removed_region: removed_region@c0000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0xc0000000 0x0 0x3900000>;
+ };
+
+ qseecom_mem: qseecom_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1400000>;
+ };
+
+ qseecom_ta_mem: qseecom_ta_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ secure_display_memory: secure_display_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x00000000 0 0xffffffff>;
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x8c00000>;
+ };
+
+ cont_splash_memory: cont_splash_region {
+ reg = <0x0 0xA0000000 0x0 0x02300000>;
+ label = "cont_splash_region";
+ };
+
+ disp_rdump_memory: disp_rdump_region@0xa0000000 {
+ reg = <0x0 0xA0000000 0x0 0x02300000>;
+ label = "disp_rdump_region";
+ };
+
+ dfps_data_memory: dfps_data_region {
+ reg = <0x0 0xA2300000 0x0 0x0100000>;
+ label = "dfps_data_region";
+ };
+
+ dump_mem: mem_dump_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ size = <0 0x2800000>;
+ };
+
+ cmd_db: reserved-memory@80860000 {
+ reg = <0x0 0x80860000 0x0 0x20000>;
+ compatible = "qcom,cmd-db";
+ no-map;
+ };
+
+ adsp_mem: adsp_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x00000000 0 0xffffffff>;
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x800000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ slim_aud: slim@3ac0000 {
+ cell-index = <1>;
+ compatible = "qcom,slim-ngd";
+ reg = <0x3ac0000 0x2c000>,
+ <0x3a84000 0x2a000>;
+ reg-names = "slimbus_physical", "slimbus_bam_physical";
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "slimbus_irq", "slimbus_bam_irq";
+ qcom,apps-ch-pipes = <0x0>;
+ qcom,ea-pc = <0x380>;
+ iommus = <&apps_smmu 0x1026 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+ qcom,iommu-dma = "fastmap";
+ status = "ok";
+
+ /* Slimbus Slave DT for WCN3990 */
+ btfmslim_codec: wcn3990 {
+ compatible = "qcom,btfmslim_slave";
+ elemental-addr = [00 01 20 02 17 02];
+ qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
+ qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
+ };
+ };
+
+ bluetooth: bt_wcn3990 {
+ compatible = "qca,wcn3990";
+ qca,bt-sw-ctrl-gpio = <&tlmm 69 0>; /* SW_CTRL */
+ qca,bt-vdd-io-supply = <&L11A>; /* IO */
+ qca,bt-vdd-core-supply = <&L2E>; /* RFA */
+ qca,bt-vdd-pa-supply = <&L10E>; /* CH0 */
+ qca,bt-vdd-xtal-supply = <&L7A>; /* XO */
+
+ qca,bt-vdd-io-voltage-level = <1700000 1900000>;
+ qca,bt-vdd-core-voltage-level = <1304000 1304000>;
+ qca,bt-vdd-pa-voltage-level = <3000000 3312000>;
+ qca,bt-vdd-xtal-voltage-level = <1700000 1900000>;
+
+ qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */
+ };
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ reg = <0x17a00000 0x10000>, /* GICD */
+ <0x17a60000 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
+ };
+
+ jtag_mm0: jtagmm@7040000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7040000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU0>;
+ };
+
+ jtag_mm1: jtagmm@7140000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7140000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU1>;
+ };
+
+ jtag_mm2: jtagmm@7240000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7240000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU2>;
+ };
+
+ jtag_mm3: jtagmm@7340000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7340000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU3>;
+ };
+
+ jtag_mm4: jtagmm@7440000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7440000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU4>;
+ };
+
+ jtag_mm5: jtagmm@7540000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7540000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU5>;
+ };
+
+ jtag_mm6: jtagmm@7640000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7640000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU6>;
+ };
+
+ jtag_mm7: jtagmm@7740000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7740000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU7>;
+ };
+
+ ufsphy_mem: ufsphy_mem@1d87000 {
+ reg = <0x1d87000 0xe00>; /* PHY regs */
+ reg-names = "phy_mem";
+ #phy-cells = <0>;
+
+ lanes-per-direction = <2>;
+
+ clock-names = "ref_clk_src",
+ "ref_clk",
+ "ref_aux_clk";
+ clocks = <&rpmhcc RPMH_QLINK_CLK>,
+ <&gcc GCC_UFS_MEM_CLKREF_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+ status = "disabled";
+ };
+
+ ufshc_mem: ufshc@1d84000 {
+ compatible = "qcom,ufshc";
+ reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;
+ reg-names = "ufs_mem", "ufs_ice";
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufsphy_mem>;
+ phy-names = "ufsphy";
+
+ lanes-per-direction = <2>;
+ dev-ref-clk-freq = <0>; /* 19.2 MHz */
+ spm-level = <5>;
+
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "core_clk_ice",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ clocks =
+ <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+ <&rpmhcc RPMH_QLINK_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ freq-table-hz =
+ <50000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <37500000 150000000>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ qcom,msm-bus,name = "ufshc_mem";
+ qcom,msm-bus,num-cases = <22>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /*
+ * During HS G3 UFS runs at nominal voltage corner, vote
+ * higher bandwidth to push other buses in the data path
+ * to run at nominal to achieve max throughput.
+ * 4GBps pushes BIMC to run at nominal.
+ * 200MBps pushes CNOC to run at nominal.
+ * Vote for half of this bandwidth for HS G3 1-lane.
+ * For max bandwidth, vote high enough to push the buses
+ * to run in turbo voltage corner.
+ */
+ <123 512 0 0>, <1 757 0 0>, /* No vote */
+ <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */
+ <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */
+ <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */
+ <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */
+ <123 512 1844 0>, <1 757 1000 0>, /* PWM G1 L2 */
+ <123 512 3688 0>, <1 757 1000 0>, /* PWM G2 L2 */
+ <123 512 7376 0>, <1 757 1000 0>, /* PWM G3 L2 */
+ <123 512 14752 0>, <1 757 1000 0>, /* PWM G4 L2 */
+ <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */
+ <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */
+ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */
+ <123 512 255591 0>, <1 757 1000 0>, /* HS G1 RA L2 */
+ <123 512 511181 0>, <1 757 1000 0>, /* HS G2 RA L2 */
+ <123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */
+ <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */
+ <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */
+ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */
+ <123 512 298189 0>, <1 757 1000 0>, /* HS G1 RB L2 */
+ <123 512 596378 0>, <1 757 1000 0>, /* HS G2 RB L2 */
+ /* As UFS working in HS G3 RB L2 mode, aggregated
+ * bandwidth (AB) should take care of providing
+ * optimum throughput requested. However, as tested,
+ * in order to scale up CNOC clock, instantaneous
+ * bindwidth (IB) needs to be given a proper value too.
+ */
+ <123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */
+ <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
+
+ qcom,bus-vector-names = "MIN",
+ "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
+ "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
+ "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
+ "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",
+ "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
+ "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",
+ "MAX";
+
+ /* PM QoS */
+ qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
+ qcom,pm-qos-cpu-group-latency-us = <67 67>;
+ qcom,pm-qos-default-cpu = <0>;
+
+ pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
+ pinctrl-0 = <&ufs_dev_reset_assert>;
+ pinctrl-1 = <&ufs_dev_reset_deassert>;
+
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "core_reset";
+ non-removable;
+
+ status = "disabled";
+ };
+
+ qcom,rmtfs_sharedmem@0 {
+ compatible = "qcom,sharedmem-uio";
+ /* FP4-917, change size 0x280000 (2.5MB) to 0x600000 (6MB), liquan.zhou.t2m */
+ reg = <0x0 0x600000>;
+ reg-names = "rmtfs";
+ qcom,client-id = <0x00000001>;
+ qcom,guard-memory;
+ };
+
+ qcom,memshare {
+ compatible = "qcom,memshare";
+
+ qcom,client_1 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x0>;
+ qcom,client-id = <0>;
+ qcom,allocate-boot-time;
+ label = "modem";
+ };
+
+ qcom,client_2 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x0>;
+ qcom,client-id = <2>;
+ label = "modem";
+ };
+
+ mem_client_3_size: qcom,client_3 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x500000>;
+ qcom,client-id = <1>;
+ qcom,allocate-on-request;
+ label = "modem";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <19200000>;
+ };
+
+ timer@17c20000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x17c20000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@17c21000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c21000 0x1000>,
+ <0x17c22000 0x1000>;
+ };
+
+ frame@17c23000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c23000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c25000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c25000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c27000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c27000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c29000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c29000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c2b000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c2d000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ ipcc_mproc: qcom,ipcc@408000 {
+ compatible = "qcom,ipcc";
+ reg = <0x408000 0x1000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #mbox-cells = <2>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,lagoon-pdc";
+ reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
+ qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>,
+ <126 655 12>, <138 139 15>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ apps_rsc: rsc@18200000 {
+ label = "apps_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x18200000 0x10000>,
+ <0x18210000 0x10000>,
+ <0x18220000 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 3>,
+ <WAKE_TCS 3>,
+ <CONTROL_TCS 1>;
+
+ system_pm {
+ compatible = "qcom,system-pm";
+ };
+
+ msm_bus_apps_rsc {
+ compatible = "qcom,msm-bus-rsc";
+ qcom,msm-bus-id = <MSM_BUS_RSC_APPS>;
+ };
+
+ rpmhcc: qcom,rpmhclk {
+ compatible = "qcom,lagoon-rpmh-clk";
+ #clock-cells = <1>;
+ };
+ };
+
+ disp_rsc: rsc@af20000 {
+ label = "disp_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0xaf20000 0x10000>;
+ reg-names = "drv-0";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0x1c00>;
+ qcom,drv-id = <0>;
+ qcom,tcs-config = <ACTIVE_TCS 0>,
+ <SLEEP_TCS 1>,
+ <WAKE_TCS 1>,
+ <CONTROL_TCS 0>;
+
+ msm_bus_disp_rsc {
+ compatible = "qcom,msm-bus-rsc";
+ qcom,msm-bus-id = <MSM_BUS_RSC_DISP>;
+ };
+
+ sde_rsc_rpmh {
+ compatible = "qcom,sde-rsc-rpmh";
+ cell-index = <0>;
+ };
+ };
+
+ cpu_pmu: cpu-pmu {
+ compatible = "arm,armv8-pmuv3";
+ qcom,irq-is-percpu;
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cache-controller@9200000 {
+ compatible = "lagoon-llcc-v1";
+ reg = <0x9200000 0x50000> , <0x9600000 0x50000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ cap-based-alloc-and-pwr-collapse;
+ };
+
+ qcom,msm-imem@146aa000 {
+ compatible = "qcom,msm-imem";
+ reg = <0x146aa000 0x1000>;
+ ranges = <0x0 0x146aa000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mem_dump_table@10 {
+ compatible = "qcom,msm-imem-mem_dump_table";
+ reg = <0x10 0x8>;
+ };
+
+ restart_reason@65c {
+ compatible = "qcom,msm-imem-restart_reason";
+ reg = <0x65c 0x4>;
+ };
+
+ dload_type@1c {
+ compatible = "qcom,msm-imem-dload-type";
+ reg = <0x1c 0x4>;
+ };
+
+ boot_stats@6b0 {
+ compatible = "qcom,msm-imem-boot_stats";
+ reg = <0x6b0 0x20>;
+ };
+
+ kaslr_offset@6d0 {
+ compatible = "qcom,msm-imem-kaslr_offset";
+ reg = <0x6d0 0xc>;
+ };
+
+ pil@94c {
+ compatible = "qcom,msm-imem-pil";
+ reg = <0x94c 0xc8>;
+ };
+
+ diag_dload@c8 {
+ compatible = "qcom,msm-imem-diag-dload";
+ reg = <0xc8 0xc8>;
+ };
+ };
+
+ dcc: dcc_v2@109f000 {
+ compatible = "qcom,dcc-v2";
+ reg = <0x109f000 0x1000>,
+ <0x1026000 0x2000>;
+ reg-names = "dcc-base", "dcc-ram-base";
+ dcc-ram-offset = <0x6000>;
+
+ qcom,curr-link-list = <4>;
+ qcom,data-sink = "sram";
+ qcom,link-list = <DCC_READ 0x18000024 1 0>,
+ <DCC_READ 0x18000040 1 0>,
+ <DCC_READ 0x18010024 1 0>,
+ <DCC_READ 0x18010040 1 0>,
+ <DCC_READ 0x18020024 1 0>,
+ <DCC_READ 0x18020040 1 0>,
+ <DCC_READ 0x18030024 1 0>,
+ <DCC_READ 0x18030040 1 0>,
+ <DCC_READ 0x18040024 1 0>,
+ <DCC_READ 0x18040040 1 0>,
+ <DCC_READ 0x18050024 1 0>,
+ <DCC_READ 0x18050040 1 0>,
+ <DCC_READ 0x18060024 1 0>,
+ <DCC_READ 0x18060040 1 0>,
+ <DCC_READ 0x18070024 1 0>,
+ <DCC_READ 0x18070040 1 0>,
+ <DCC_READ 0x18080024 1 0>,
+ <DCC_READ 0x18080040 1 0>,
+ <DCC_READ 0x18080044 1 0>,
+ <DCC_READ 0x18080048 1 0>,
+ <DCC_READ 0x1808004c 1 0>,
+ <DCC_READ 0x18080054 1 0>,
+ <DCC_READ 0x1808006c 1 0>,
+ <DCC_READ 0x18080070 1 0>,
+ <DCC_READ 0x18080074 1 0>,
+ <DCC_READ 0x18080078 1 0>,
+ <DCC_READ 0x1808007c 1 0>,
+ <DCC_READ 0x180800f4 1 0>,
+ <DCC_READ 0x180800f8 1 0>,
+ <DCC_READ 0x18080104 1 0>,
+ <DCC_READ 0x18080118 1 0>,
+ <DCC_READ 0x1808011c 1 0>,
+ <DCC_READ 0x18080128 1 0>,
+ <DCC_READ 0x1808012c 1 0>,
+ <DCC_READ 0x18080130 1 0>,
+ <DCC_READ 0x18080134 1 0>,
+ <DCC_READ 0x18080138 1 0>,
+ <DCC_READ 0x180801b4 1 0>,
+ <DCC_READ 0x180801b8 1 0>,
+ <DCC_READ 0x180801bc 1 0>,
+ <DCC_READ 0x180801f0 1 0>,
+ <DCC_READ 0x18280000 1 0>,
+ <DCC_READ 0x18282000 1 0>,
+ <DCC_READ 0x18284000 1 0>,
+ <DCC_READ 0x18200010 1 0>,
+ <DCC_READ 0x18200030 1 0>,
+ <DCC_READ 0x18200038 1 0>,
+ <DCC_READ 0x18200048 1 0>,
+ <DCC_READ 0x18220038 1 0>,
+ <DCC_READ 0x18220040 1 0>,
+ <DCC_READ 0x182200d0 1 0>,
+ <DCC_READ 0x18220010 1 0>,
+ <DCC_READ 0x18220030 1 0>,
+ <DCC_READ 0x18200400 1 0>,
+ <DCC_READ 0x18200404 1 0>,
+ <DCC_READ 0x18200408 1 0>,
+ <DCC_READ 0xb201020 1 0>,
+ <DCC_READ 0xb201024 1 0>,
+ <DCC_READ 0xb20103c 1 0>,
+ <DCC_READ 0xb204510 1 0>,
+ <DCC_READ 0xb204514 1 0>,
+ <DCC_READ 0xb204520 1 0>,
+ <DCC_READ 0x1800005c 1 0>,
+ <DCC_READ 0x1801005c 1 0>,
+ <DCC_READ 0x1802005c 1 0>,
+ <DCC_READ 0x1803005c 1 0>,
+ <DCC_READ 0x1804005c 1 0>,
+ <DCC_READ 0x1805005c 1 0>,
+ <DCC_READ 0x1806005c 1 0>,
+ <DCC_READ 0x1807005c 1 0>,
+ <DCC_READ 0x17c0003c 1 0>,
+ <DCC_READ 0x18101908 1 0>,
+ <DCC_READ 0x18101c18 1 0>,
+ <DCC_READ 0x18390810 1 0>,
+ <DCC_READ 0x18390814 1 0>,
+ <DCC_READ 0x18390818 1 0>,
+ <DCC_READ 0x18393a84 1 0>,
+ <DCC_READ 0x18100908 1 0>,
+ <DCC_READ 0x18100c18 1 0>,
+ <DCC_READ 0x183a0810 1 0>,
+ <DCC_READ 0x183a0814 1 0>,
+ <DCC_READ 0x183a0818 1 0>,
+ <DCC_READ 0x183a3a84 2 0>,
+ <DCC_READ 0x18393500 1 0>,
+ <DCC_READ 0x183a3500 1 0>,
+ <DCC_READ 0x18280000 4 0>,
+ <DCC_READ 0x18284000 4 0>,
+ <DCC_READ 0x18280084 1 0>,
+ <DCC_READ 0x18282000 4 0>,
+ <DCC_READ 0x18282028 1 0>,
+ <DCC_READ 0x18282038 1 0>,
+ <DCC_READ 0x18282080 5 0>,
+ <DCC_READ 0x0c201244 1 0>,
+ <DCC_READ 0x0c202244 1 0>,
+ <DCC_READ 0x18300000 1 0>,
+ <DCC_READ 0x1829208c 1 0>,
+ <DCC_READ 0x1832102c 1 0>,
+ <DCC_READ 0x18321044 1 0>,
+ <DCC_READ 0x18321700 1 0>,
+ <DCC_READ 0x18321710 1 0>,
+ <DCC_READ 0x1832176c 1 0>,
+ <DCC_READ 0x18321818 1 0>,
+ <DCC_READ 0x1832181c 1 0>,
+ <DCC_READ 0x18321824 1 0>,
+ <DCC_READ 0x18321920 1 0>,
+ <DCC_READ 0x18322c14 1 0>,
+ <DCC_READ 0x18322c18 1 0>,
+ <DCC_READ 0x1832302c 1 0>,
+ <DCC_READ 0x18323044 1 0>,
+ <DCC_READ 0x18323710 1 0>,
+ <DCC_READ 0x1832376c 1 0>,
+ <DCC_READ 0x18323818 1 0>,
+ <DCC_READ 0x1832381c 1 0>,
+ <DCC_READ 0x18323824 1 0>,
+ <DCC_READ 0x18323920 1 0>,
+ <DCC_READ 0x18324c18 1 0>,
+ <DCC_READ 0x1832582c 1 0>,
+ <DCC_READ 0x18325844 1 0>,
+ <DCC_READ 0x18325f10 1 0>,
+ <DCC_READ 0x18325f6c 1 0>,
+ <DCC_READ 0x18326018 1 0>,
+ <DCC_READ 0x1832601c 1 0>,
+ <DCC_READ 0x18326024 1 0>,
+ <DCC_READ 0x18326120 1 0>,
+ <DCC_READ 0x18327414 1 0>,
+ <DCC_READ 0x18327418 1 0>,
+ <DCC_READ 0x1837103c 1 0>,
+ <DCC_READ 0x18371034 1 0>,
+ <DCC_READ 0x18371810 1 0>,
+ <DCC_READ 0x18371814 1 0>,
+ <DCC_READ 0x18200040 1 0>,
+ <DCC_READ 0x18371820 1 0>,
+ <DCC_READ 0x18325f04 1 0>,
+ <DCC_READ 0x18325f00 1 0>,
+ <DCC_READ 0x18325f2c 1 0>,
+ <DCC_READ 0x1837903c 1 0>,
+ <DCC_READ 0x18379034 1 0>,
+ <DCC_READ 0x18379810 1 0>,
+ <DCC_READ 0x18379814 1 0>,
+ <DCC_READ 0x1837981c 1 0>,
+ <DCC_READ 0x18379820 1 0>,
+ <DCC_READ 0x18323700 1 0>,
+ <DCC_READ 0x18323704 1 0>,
+ <DCC_READ 0x1832372c 1 0>,
+ <DCC_READ 0x9680000 3 0>,
+ <DCC_LOOP 8 0 0>,
+ <DCC_READ 0x9681000 3 0>,
+ <DCC_LOOP 1 0 0>,
+ <DCC_READ 0x09680078 1 0>,
+ <DCC_READ 0x9681008 121 0>,
+ <DCC_LOOP 0xa6 0 0>,
+ <DCC_READ 0x9681008 1 0>,
+ <DCC_READ 0x968100c 1 0>,
+ <DCC_LOOP 1 0 0>,
+ <DCC_READ 0x968103c 1 0>,
+ <DCC_READ 0x9698100 1 0>,
+ <DCC_READ 0x9698104 1 0>,
+ <DCC_READ 0x9698108 1 0>,
+ <DCC_READ 0x9698110 1 0>,
+ <DCC_READ 0x9698120 1 0>,
+ <DCC_READ 0x9698124 1 0>,
+ <DCC_READ 0x9698128 1 0>,
+ <DCC_READ 0x969812c 1 0>,
+ <DCC_READ 0x9698130 1 0>,
+ <DCC_READ 0x9698134 1 0>,
+ <DCC_READ 0x9698138 1 0>,
+ <DCC_READ 0x969813c 1 0>,
+ <DCC_WRITE 0x11100c 1 0>,
+ <DCC_WRITE 0x110144 1 0>,
+ <DCC_WRITE 0x11102c 1 0>,
+ <DCC_READ 0x16e0300 1 0>,
+ <DCC_READ 0x16e0400 1 0>,
+ <DCC_READ 0x16e0408 1 0>,
+ <DCC_READ 0x16e0410 1 0>,
+ <DCC_READ 0x16e0420 1 0>,
+ <DCC_READ 0x16e0424 1 0>,
+ <DCC_READ 0x16e0428 1 0>,
+ <DCC_READ 0x16e042c 1 0>,
+ <DCC_READ 0x16e0430 1 0>,
+ <DCC_READ 0x16e0434 1 0>,
+ <DCC_READ 0x16e0438 1 0>,
+ <DCC_READ 0x16e043c 1 0>,
+ <DCC_READ 0x16e0688 1 0>,
+ <DCC_READ 0x16e0690 1 0>,
+ <DCC_READ 0x16e0700 1 0>,
+ <DCC_READ 0x1700204 1 0>,
+ <DCC_READ 0x1700240 1 0>,
+ <DCC_READ 0x1700248 1 0>,
+ <DCC_READ 0x1700288 1 0>,
+ <DCC_READ 0x1700290 1 0>,
+ <DCC_READ 0x1700300 1 0>,
+ <DCC_READ 0x1700304 1 0>,
+ <DCC_READ 0x1700308 1 0>,
+ <DCC_READ 0x170030c 1 0>,
+ <DCC_READ 0x1700310 1 0>,
+ <DCC_READ 0x1700400 1 0>,
+ <DCC_READ 0x1700404 1 0>,
+ <DCC_READ 0x1700488 1 0>,
+ <DCC_READ 0x1700490 1 0>,
+ <DCC_READ 0x1700500 1 0>,
+ <DCC_READ 0x1700504 1 0>,
+ <DCC_READ 0x1700508 1 0>,
+ <DCC_READ 0x170050c 1 0>,
+ <DCC_READ 0x1700c00 1 0>,
+ <DCC_READ 0x1700c04 1 0>,
+ <DCC_READ 0x1700c08 1 0>,
+ <DCC_READ 0x1700c10 1 0>,
+ <DCC_READ 0x1700c20 1 0>,
+ <DCC_READ 0x1700c24 1 0>,
+ <DCC_READ 0x1700c28 1 0>,
+ <DCC_READ 0x1700c2c 1 0>,
+ <DCC_READ 0x1700c30 1 0>,
+ <DCC_READ 0x1700c34 1 0>,
+ <DCC_READ 0x1700c38 1 0>,
+ <DCC_READ 0x1700c3c 1 0>,
+ <DCC_READ 0x1620000 1 0>,
+ <DCC_READ 0x1620004 1 0>,
+ <DCC_READ 0x1620008 1 0>,
+ <DCC_READ 0x1620010 1 0>,
+ <DCC_READ 0x1620020 1 0>,
+ <DCC_READ 0x1620024 1 0>,
+ <DCC_READ 0x1620028 1 0>,
+ <DCC_READ 0x162002c 1 0>,
+ <DCC_READ 0x1620030 1 0>,
+ <DCC_READ 0x1620034 1 0>,
+ <DCC_READ 0x1620038 1 0>,
+ <DCC_READ 0x162003c 1 0>,
+ <DCC_READ 0x1620200 1 0>,
+ <DCC_READ 0x1620204 1 0>,
+ <DCC_READ 0x1620240 1 0>,
+ <DCC_READ 0x1620248 1 0>,
+ <DCC_READ 0x1620288 1 0>,
+ <DCC_READ 0x162028c 1 0>,
+ <DCC_READ 0x1620290 1 0>,
+ <DCC_READ 0x1620294 1 0>,
+ <DCC_READ 0x16202a8 1 0>,
+ <DCC_READ 0x16202ac 1 0>,
+ <DCC_READ 0x16202b0 1 0>,
+ <DCC_READ 0x16202b4 1 0>,
+ <DCC_READ 0x1620300 1 0>,
+ <DCC_READ 0x1620400 1 0>,
+ <DCC_READ 0x1620404 1 0>,
+ <DCC_READ 0x1620488 1 0>,
+ <DCC_READ 0x1620490 1 0>,
+ <DCC_READ 0x1620500 1 0>,
+ <DCC_READ 0x1620504 1 0>,
+ <DCC_READ 0x1620508 1 0>,
+ <DCC_READ 0x162050c 1 0>,
+ <DCC_READ 0x1620510 1 0>,
+ <DCC_READ 0x1620600 1 0>,
+ <DCC_READ 0x1620604 1 0>,
+ <DCC_READ 0x1620688 1 0>,
+ <DCC_READ 0x1620690 1 0>,
+ <DCC_READ 0x1620700 1 0>,
+ <DCC_READ 0x1620704 1 0>,
+ <DCC_READ 0x1620708 1 0>,
+ <DCC_READ 0x162070c 1 0>,
+ <DCC_READ 0x1620710 1 0>,
+ <DCC_READ 0x1620800 1 0>,
+ <DCC_READ 0x1620804 1 0>,
+ <DCC_READ 0x1620900 1 0>,
+ <DCC_READ 0x1620a00 1 0>,
+ <DCC_READ 0x1620a04 1 0>,
+ <DCC_READ 0x1620b00 1 0>,
+ <DCC_READ 0x1620b04 1 0>,
+ <DCC_READ 0x1639000 1 0>,
+ <DCC_READ 0x1639004 1 0>,
+ <DCC_READ 0x3c41800 1 0>,
+ <DCC_READ 0x3c41804 1 0>,
+ <DCC_READ 0x3c41880 1 0>,
+ <DCC_READ 0x3c41888 1 0>,
+ <DCC_READ 0x3c41890 1 0>,
+ <DCC_READ 0x3c41900 1 0>,
+ <DCC_READ 0x3c41a00 1 0>,
+ <DCC_READ 0x3c41a04 1 0>,
+ <DCC_READ 0x3c41a40 1 0>,
+ <DCC_READ 0x3c41a48 1 0>,
+ <DCC_READ 0x3c41c00 1 0>,
+ <DCC_READ 0x3c41c04 1 0>,
+ <DCC_READ 0x3c41d00 1 0>,
+ <DCC_READ 0x3c42680 1 0>,
+ <DCC_READ 0x3c42684 1 0>,
+ <DCC_READ 0x3c42688 1 0>,
+ <DCC_READ 0x3c42690 1 0>,
+ <DCC_READ 0x3c42698 1 0>,
+ <DCC_READ 0x3c426a0 1 0>,
+ <DCC_READ 0x3c426a4 1 0>,
+ <DCC_READ 0x3c426a8 1 0>,
+ <DCC_READ 0x3c426ac 1 0>,
+ <DCC_READ 0x3c426b0 1 0>,
+ <DCC_READ 0x3c426b4 1 0>,
+ <DCC_READ 0x3c426b8 1 0>,
+ <DCC_READ 0x3c426bc 1 0>,
+ <DCC_READ 0x9681010 1 0>,
+ <DCC_READ 0x9681014 1 0>,
+ <DCC_READ 0x9681018 1 0>,
+ <DCC_READ 0x968101c 1 0>,
+ <DCC_READ 0x9681020 1 0>,
+ <DCC_READ 0x9681024 1 0>,
+ <DCC_READ 0x9681028 1 0>,
+ <DCC_READ 0x968102c 1 0>,
+ <DCC_READ 0x9681030 1 0>,
+ <DCC_READ 0x9681034 1 0>,
+ <DCC_READ 0x968103c 1 0>,
+ <DCC_READ 0x9692000 1 0>,
+ <DCC_READ 0x9692004 1 0>,
+ <DCC_READ 0x9692008 1 0>,
+ <DCC_READ 0x9692040 1 0>,
+ <DCC_READ 0x9692048 1 0>,
+ <DCC_READ 0x9695000 1 0>,
+ <DCC_READ 0x9695004 1 0>,
+ <DCC_READ 0x9695080 1 0>,
+ <DCC_READ 0x9695084 1 0>,
+ <DCC_READ 0x9695088 1 0>,
+ <DCC_READ 0x969508c 1 0>,
+ <DCC_READ 0x9695090 1 0>,
+ <DCC_READ 0x9695094 1 0>,
+ <DCC_READ 0x96950a0 1 0>,
+ <DCC_READ 0x96950a8 1 0>,
+ <DCC_READ 0x96950b0 1 0>,
+ <DCC_READ 0x9695100 1 0>,
+ <DCC_READ 0x9695104 1 0>,
+ <DCC_READ 0x9695108 1 0>,
+ <DCC_READ 0x969510c 1 0>,
+ <DCC_READ 0x9695110 1 0>,
+ <DCC_READ 0x9695114 1 0>,
+ <DCC_READ 0x9695118 1 0>,
+ <DCC_READ 0x969511c 1 0>,
+ <DCC_READ 0x9696000 1 0>,
+ <DCC_READ 0x9696004 1 0>,
+ <DCC_READ 0x9696080 1 0>,
+ <DCC_READ 0x9696088 1 0>,
+ <DCC_READ 0x9696090 1 0>,
+ <DCC_READ 0x9696100 1 0>,
+ <DCC_READ 0x9696104 1 0>,
+ <DCC_READ 0x9696108 1 0>,
+ <DCC_READ 0x969610c 1 0>,
+ <DCC_READ 0x9696114 1 0>,
+ <DCC_READ 0x9696118 1 0>,
+ <DCC_READ 0x969611c 1 0>,
+ <DCC_READ 0x9698000 1 0>,
+ <DCC_READ 0x9698004 1 0>,
+ <DCC_READ 0x9698008 1 0>,
+ <DCC_READ 0x9698010 1 0>,
+ <DCC_READ 0x9698100 1 0>,
+ <DCC_READ 0x9698104 1 0>,
+ <DCC_READ 0x9698108 1 0>,
+ <DCC_READ 0x9698110 1 0>,
+ <DCC_READ 0x9698118 1 0>,
+ <DCC_READ 0x9698120 1 0>,
+ <DCC_READ 0x9698124 1 0>,
+ <DCC_READ 0x9698128 1 0>,
+ <DCC_READ 0x969812c 1 0>,
+ <DCC_READ 0x9698130 1 0>,
+ <DCC_READ 0x9698134 1 0>,
+ <DCC_READ 0x9698138 1 0>,
+ <DCC_READ 0x969813c 1 0>,
+ <DCC_READ 0x9698200 1 0>,
+ <DCC_READ 0x9698204 1 0>,
+ <DCC_READ 0x9698240 1 0>,
+ <DCC_READ 0x9698244 1 0>,
+ <DCC_READ 0x9698248 1 0>,
+ <DCC_READ 0x969824c 1 0>,
+ <DCC_READ 0x1b9064 1 0>,
+ <DCC_READ 0x1b906c 1 0>,
+ <DCC_READ 0x610100 11 0>,
+ <DCC_READ 0x9220480 1 0>,
+ <DCC_READ 0x9232100 1 0>,
+ <DCC_READ 0x92360b0 1 0>,
+ <DCC_READ 0x9236044 1 0>,
+ <DCC_READ 0x9236048 1 0>,
+ <DCC_READ 0x923604c 1 0>,
+ <DCC_READ 0x9236050 1 0>,
+ <DCC_READ 0x923e030 1 0>,
+ <DCC_READ 0x9241000 1 0>,
+ <DCC_READ 0x9248048 1 0>,
+ <DCC_READ 0x9248058 1 0>,
+ <DCC_READ 0x924805c 1 0>,
+ <DCC_READ 0x9248060 1 0>,
+ <DCC_READ 0x9248064 1 0>,
+ <DCC_READ 0x9222408 1 0>,
+ <DCC_READ 0x9220344 1 0>,
+ <DCC_READ 0x9220348 1 0>,
+ <DCC_READ 0x922358c 1 0>,
+ <DCC_READ 0x9222398 1 0>,
+ <DCC_READ 0x92223a4 1 0>,
+ <DCC_READ 0x923201c 1 0>,
+ <DCC_READ 0x9232020 1 0>,
+ <DCC_READ 0x9232024 1 0>,
+ <DCC_READ 0x9232028 1 0>,
+ <DCC_READ 0x923202c 1 0>,
+ <DCC_READ 0x9232050 1 0>,
+ <DCC_READ 0x9236028 1 0>,
+ <DCC_READ 0x923602c 1 0>,
+ <DCC_READ 0x9236030 1 0>,
+ <DCC_READ 0x9236034 1 0>,
+ <DCC_READ 0x9236038 1 0>,
+ <DCC_READ 0x9236040 1 0>,
+ <DCC_READ 0x9236054 1 0>,
+ <DCC_READ 0x9236060 1 0>,
+ <DCC_READ 0x9260400 1 0>,
+ <DCC_READ 0x9260410 1 0>,
+ <DCC_READ 0x9260414 1 0>,
+ <DCC_READ 0x9260418 1 0>,
+ <DCC_READ 0x9260420 1 0>,
+ <DCC_READ 0x9260424 1 0>,
+ <DCC_READ 0x9260430 1 0>,
+ <DCC_READ 0x9260440 1 0>,
+ <DCC_READ 0x9260448 1 0>,
+ <DCC_READ 0x92604a0 1 0>,
+ <DCC_READ 0x92604b8 1 0>,
+ <DCC_READ 0x9265804 1 0>,
+ <DCC_READ 0x9266418 1 0>,
+ <DCC_READ 0x92e0400 1 0>,
+ <DCC_READ 0x92e0410 1 0>,
+ <DCC_READ 0x92e0414 1 0>,
+ <DCC_READ 0x92e0418 1 0>,
+ <DCC_READ 0x92e0420 1 0>,
+ <DCC_READ 0x92e0424 1 0>,
+ <DCC_READ 0x92e0430 1 0>,
+ <DCC_READ 0x92e0440 1 0>,
+ <DCC_READ 0x92e0448 1 0>,
+ <DCC_READ 0x92e04a0 1 0>,
+ <DCC_READ 0x92e04b8 1 0>,
+ <DCC_READ 0x92e5804 1 0>,
+ <DCC_READ 0x92e6418 1 0>,
+ <DCC_READ 0x92e5b1c 1 0>,
+ <DCC_READ 0x92e6420 1 0>,
+ <DCC_READ 0x92e04d4 1 0>,
+ <DCC_READ 0x92604b0 1 0>,
+ <DCC_READ 0x92e0404 1 0>,
+ <DCC_READ 0x92e04b0 1 0>,
+ <DCC_READ 0x92e04d0 1 0>,
+ <DCC_READ 0x9260404 1 0>,
+ <DCC_READ 0x9265840 1 0>,
+ <DCC_READ 0x9265b18 1 0>,
+ <DCC_READ 0x9600000 1 0>,
+ <DCC_READ 0x9600004 1 0>,
+ <DCC_READ 0x9601000 1 0>,
+ <DCC_READ 0x9601004 1 0>,
+ <DCC_READ 0x9602000 1 0>,
+ <DCC_READ 0x9602004 1 0>,
+ <DCC_READ 0x9603000 1 0>,
+ <DCC_READ 0x9603004 1 0>,
+ <DCC_READ 0x9604000 1 0>,
+ <DCC_READ 0x9604004 1 0>,
+ <DCC_READ 0x9605000 1 0>,
+ <DCC_READ 0x9605004 1 0>,
+ <DCC_READ 0x9606000 1 0>,
+ <DCC_READ 0x9606004 1 0>,
+ <DCC_READ 0x9607000 1 0>,
+ <DCC_READ 0x9607004 1 0>,
+ <DCC_READ 0x9608000 1 0>,
+ <DCC_READ 0x9608004 1 0>,
+ <DCC_READ 0x9609000 1 0>,
+ <DCC_READ 0x9609004 1 0>,
+ <DCC_READ 0x960a000 1 0>,
+ <DCC_READ 0x960a004 1 0>,
+ <DCC_READ 0x960b000 1 0>,
+ <DCC_READ 0x960b004 1 0>,
+ <DCC_READ 0x960c000 1 0>,
+ <DCC_READ 0x960c004 1 0>,
+ <DCC_READ 0x960d000 1 0>,
+ <DCC_READ 0x960d004 1 0>,
+ <DCC_READ 0x960e000 1 0>,
+ <DCC_READ 0x960e004 1 0>,
+ <DCC_READ 0x960f000 1 0>,
+ <DCC_READ 0x960f004 1 0>,
+ <DCC_READ 0x9610000 1 0>,
+ <DCC_READ 0x9610004 1 0>,
+ <DCC_READ 0x9611000 1 0>,
+ <DCC_READ 0x9611004 1 0>,
+ <DCC_READ 0x9612000 1 0>,
+ <DCC_READ 0x9612004 1 0>,
+ <DCC_READ 0x9613000 1 0>,
+ <DCC_READ 0x9613004 1 0>,
+ <DCC_READ 0x9614000 1 0>,
+ <DCC_READ 0x9614004 1 0>,
+ <DCC_READ 0x9615000 1 0>,
+ <DCC_READ 0x9615004 1 0>,
+ <DCC_READ 0x9616000 1 0>,
+ <DCC_READ 0x9616004 1 0>,
+ <DCC_READ 0x9617000 1 0>,
+ <DCC_READ 0x9617004 1 0>,
+ <DCC_READ 0x9618000 1 0>,
+ <DCC_READ 0x9618004 1 0>,
+ <DCC_READ 0x9619000 1 0>,
+ <DCC_READ 0x9619004 1 0>,
+ <DCC_READ 0x961a000 1 0>,
+ <DCC_READ 0x961a004 1 0>,
+ <DCC_READ 0x961b000 1 0>,
+ <DCC_READ 0x961b004 1 0>,
+ <DCC_READ 0x961c000 1 0>,
+ <DCC_READ 0x961c004 1 0>,
+ <DCC_READ 0x961d000 1 0>,
+ <DCC_READ 0x961d004 1 0>,
+ <DCC_READ 0x961e000 1 0>,
+ <DCC_READ 0x961e004 1 0>,
+ <DCC_READ 0x961f000 1 0>,
+ <DCC_READ 0x961f004 1 0>,
+ <DCC_READ 0x9050008 1 0>,
+ <DCC_READ 0x9050068 1 0>,
+ <DCC_READ 0x9050078 1 0>,
+ <DCC_READ 0x90b0280 1 0>,
+ <DCC_READ 0x90b0288 1 0>,
+ <DCC_READ 0x90b028c 1 0>,
+ <DCC_READ 0x90b0290 1 0>,
+ <DCC_READ 0x90b0294 1 0>,
+ <DCC_READ 0x90b0298 1 0>,
+ <DCC_READ 0x90b029c 1 0>,
+ <DCC_READ 0x90b02a0 1 0>,
+ <DCC_READ 0x90b0004 1 0>,
+ <DCC_READ 0x90c012c 1 0>,
+ <DCC_READ 0x90c8040 1 0>,
+ <DCC_READ 0x9186048 1 0>,
+ <DCC_READ 0x9186054 1 0>,
+ <DCC_READ 0x9186164 1 0>,
+ <DCC_READ 0x9186170 1 0>,
+ <DCC_READ 0x9186078 1 0>,
+ <DCC_READ 0x9186264 1 0>,
+ <DCC_READ 0x9250110 1 0>,
+ <DCC_READ 0x9223318 1 0>;
+ };
+
+ restart@c264000 {
+ compatible = "qcom,pshold";
+ reg = <0xc264000 0x4>,
+ <0x1fd3000 0x4>;
+ reg-names = "pshold-base", "tcsr-boot-misc-detect";
+ };
+
+ qcom_seecom: qseecom@c1700000 {
+ compatible = "qcom,qseecom";
+ reg = <0xc1700000 0x2200000>;
+ reg-names = "secapp-region";
+ memory-region = <&qseecom_mem>;
+ qcom,hlos-num-ce-hw-instances = <1>;
+ qcom,hlos-ce-hw-instance = <0>;
+ qcom,qsee-ce-hw-instance = <0>;
+ qcom,disk-encrypt-pipe-pair = <2>;
+ qcom,support-fde;
+ qcom,no-clock-support;
+ qcom,fde-key-size;
+ qcom,commonlib64-loaded-by-uefi;
+ qcom,qsee-reentrancy-support = <2>;
+ };
+
+ qcom_smcinvoke: smcinvoke@c1700000 {
+ compatible = "qcom,smcinvoke";
+ reg = <0xc1700000 0x2200000>;
+ reg-names = "secapp-region";
+ };
+
+ qcom_rng: qrng@793000 {
+ compatible = "qcom,msm-rng";
+ reg = <0x793000 0x1000>;
+ qcom,msm-rng-iface-clk;
+ qcom,no-qrng-config;
+ qcom,msm-bus,name = "msm-rng-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_PRNG 0 0>, /* No vote */
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_PRNG 0 300000>; /* 75 MHz */
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "iface_clk";
+ };
+
+ qcom_tzlog: tz-log@146aa720 {
+ compatible = "qcom,tz-log";
+ reg = <0x146aa720 0x3000>;
+ qcom,hyplog-enabled;
+ hyplog-address-offset = <0x410>;
+ hyplog-size-offset = <0x414>;
+ };
+
+ qcom_crypto: qcrypto@1de0000 {
+ compatible = "qcom,qcrypto";
+ reg = <0x1de0000 0x20000>,
+ <0x1dc4000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <2>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,bam-ee = <0>;
+ qcom,ce-hw-shared;
+ qcom,clk-mgmt-sus-res;
+ qcom,msm-bus,name = "qcrypto-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CRYPTO_CORE_0 MSM_BUS_SLAVE_FIRST 0 0>,
+ <MSM_BUS_MASTER_CRYPTO_CORE_0
+ MSM_BUS_SLAVE_FIRST 393600 393600>;
+ qcom,use-sw-aes-cbc-ecb-ctr-algo;
+ qcom,use-sw-aes-xts-algo;
+ qcom,use-sw-aes-ccm-algo;
+ qcom,use-sw-ahash-algo;
+ qcom,use-sw-aead-algo;
+ qcom,use-sw-hmac-algo;
+ qcom,smmu-s1-enable;
+ qcom,no-clock-support;
+ iommus = <&apps_smmu 0x0424 0x0011>,
+ <&apps_smmu 0x0434 0x0011>;
+ qcom,iommu-dma = "atomic";
+ };
+
+ qcom_cedev: qcedev@1de0000 {
+ compatible = "qcom,qcedev";
+ reg = <0x1de0000 0x20000>,
+ <0x1dc4000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <3>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,ce-hw-shared;
+ qcom,bam-ee = <0>;
+ qcom,msm-bus,name = "qcedev-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CRYPTO_CORE_0
+ MSM_BUS_SLAVE_FIRST 0 0>,
+ <MSM_BUS_MASTER_CRYPTO_CORE_0
+ MSM_BUS_SLAVE_FIRST 393600 393600>;
+ qcom,smmu-s1-enable;
+ qcom,no-clock-support;
+ iommus = <&apps_smmu 0x0426 0x0011>,
+ <&apps_smmu 0x0436 0x0011>;
+ qcom,iommu-dma = "atomic";
+
+ qcom_cedev_ns_cb {
+ compatible = "qcom,qcedev,context-bank";
+ label = "ns_context";
+ iommus = <&apps_smmu 0x432 0>,
+ <&apps_smmu 0x438 0x1>,
+ <&apps_smmu 0x43F 0>;
+ };
+
+ qcom_cedev_s_cb {
+ compatible = "qcom,qcedev,context-bank";
+ label = "secure_context";
+ iommus = <&apps_smmu 0x433 0>,
+ <&apps_smmu 0x43C 0x1>,
+ <&apps_smmu 0x43E 0>;
+ qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
+ qcom,secure-context-bank;
+ };
+ };
+
+ qcom_msmhdcp: qcom,msm_hdcp {
+ compatible = "qcom,msm-hdcp";
+ };
+
+ qcom,mpm2-sleep-counter@0xc221000 {
+ compatible = "qcom,mpm2-sleep-counter";
+ reg = <0xc221000 0x1000>;
+ clock-frequency = <32768>;
+ };
+
+ qcom,msm-rtb {
+ compatible = "qcom,msm-rtb";
+ qcom,rtb-size = <0x100000>;
+ };
+
+ wdog: qcom,wdt@17c10000 {
+ compatible = "qcom,msm-watchdog";
+ reg = <0x17c10000 0x1000>;
+ reg-names = "wdt-base";
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bark-time = <11000>;
+ qcom,pet-time = <9360>;
+ qcom,ipi-ping;
+ qcom,wakeup-enable;
+ qcom,scandump-sizes = <0x10100 0x10100 0x10100 0x10100
+ 0x10100 0x10100 0x25900 0x25900>;
+ };
+
+ qcom,sps {
+ compatible = "qcom,msm-sps-4k";
+ qcom,pipe-attr-ee;
+ };
+
+ qcom,chd_sliver {
+ compatible = "qcom,core-hang-detect";
+ label = "silver";
+ qcom,threshold-arr = <0x18000058 0x18010058
+ 0x18020058 0x18030058
+ 0x18040058 0x18050058>;
+ qcom,config-arr = <0x18000060 0x18010060
+ 0x18020060 0x18030060
+ 0x18040060 0x18050060>;
+ };
+
+ qcom,chd_gold {
+ compatible = "qcom,core-hang-detect";
+ label = "gold";
+ qcom,threshold-arr = <0x18060058 0x18070058>;
+ qcom,config-arr = <0x18060060 0x18070060>;
+ };
+
+ kryo-erp {
+ compatible = "arm,arm64-kryo-cpu-erp";
+ interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "l1-l2-faultirq",
+ "l3-scu-faultirq";
+ };
+
+ qcom,lpass@3000000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x03000000 0x00100>;
+
+ vdd_lpi_cx-supply = <&L1A_LEVEL>;
+ qcom,vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ vdd_lpi_mx-supply = <&L17A_LEVEL>;
+ qcom,vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+
+ qcom,pas-id = <1>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <423>;
+ qcom,minidump-id = <5>;
+ qcom,sysmon-id = <1>;
+ qcom,ssctl-instance-id = <0x14>;
+ qcom,firmware-name = "adsp";
+ memory-region = <&pil_adsp_mem>;
+ qcom,signal-aop;
+ qcom,complete-ramdump;
+ qcom,minidump-as-elf32;
+
+ /* Inputs from lpass */
+ interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ <&adsp_smp2p_in 0 0>,
+ <&adsp_smp2p_in 1 0>,
+ <&adsp_smp2p_in 2 0>,
+ <&adsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,err-ready",
+ "qcom,proxy-unvote",
+ "qcom,stop-ack";
+
+ /* Outputs to lpass */
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "adsp-pil";
+ };
+
+ qcom,turing@8300000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x8300000 0x100000>;
+
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ qcom,vdd_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+ qcom,proxy-reg-names = "vdd_cx", "vdd_mx";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+
+ qcom,pas-id = <18>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <601>;
+ qcom,minidump-id = <7>;
+ qcom,sysmon-id = <7>;
+ qcom,ssctl-instance-id = <0x17>;
+ qcom,firmware-name = "cdsp";
+ memory-region = <&pil_cdsp_mem>;
+ qcom,signal-aop;
+ qcom,complete-ramdump;
+ qcom,minidump-as-elf32;
+
+ qcom,msm-bus,name = "pil-cdsp";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_CDSP_GEM_NOC 0 0>,
+ <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_CDSP_GEM_NOC 0 1>;
+
+ /* Inputs from turing */
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 0 0>,
+ <&cdsp_smp2p_in 1 0>,
+ <&cdsp_smp2p_in 2 0>,
+ <&cdsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,err-ready",
+ "qcom,proxy-unvote",
+ "qcom,stop-ack";
+
+ /* Outputs to turing */
+ qcom,smem-states = <&cdsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "cdsp-pil";
+ };
+
+ pil_modem: qcom,mss@4080000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x4080000 0x100>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+ vdd_mss-supply = <&VDD_MSS_LEVEL>;
+ qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+ qcom,proxy-reg-names = "vdd_cx", "vdd_mss";
+
+ qcom,firmware-name = "modem";
+ memory-region = <&pil_modem_mem>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,sysmon-id = <0>;
+ qcom,ssctl-instance-id = <0x12>;
+ qcom,pas-id = <4>;
+ qcom,smem-id = <421>;
+ qcom,signal-aop;
+ qcom,minidump-id = <3>;
+ qcom,aux-minidump-ids = <4>;
+ qcom,complete-ramdump;
+
+ /* Inputs from mss */
+ interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <&mpss_smp2p_in 0 IRQ_TYPE_NONE>,
+ <&mpss_smp2p_in 1 IRQ_TYPE_NONE>,
+ <&mpss_smp2p_in 2 IRQ_TYPE_NONE>,
+ <&mpss_smp2p_in 3 IRQ_TYPE_NONE>,
+ <&mpss_smp2p_in 7 IRQ_TYPE_NONE>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,err-ready",
+ "qcom,proxy-unvote",
+ "qcom,stop-ack",
+ "qcom,shutdown-ack";
+
+ qcom,msm-bus,name = "pil-modem";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <129 512 0 0>,
+ <129 512 0 8171520>;
+
+ /* Outputs to mss */
+ qcom,smem-states = <&mpss_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "mss-pil";
+ };
+
+ thermal_zones: thermal-zones {};
+
+ tsens0:tsens@c222000 {
+ compatible = "qcom,tsens24xx";
+ reg = <0x0C222000 0x8>,
+ <0x0C263000 0x1ff>;
+ reg-names = "tsens_srot_physical",
+ "tsens_tm_physical";
+ interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 20 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tsens-upper-lower", "tsens-critical",
+ "tsens-0C";
+ 0C-sensor-num = <16>;
+ tsens-reinit-wa;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1:tsens@c223000 {
+ compatible = "qcom,tsens24xx";
+ reg = <0x0C223000 0x8>,
+ <0x0C265000 0x1ff>;
+ reg-names = "tsens_srot_physical",
+ "tsens_tm_physical";
+ interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tsens-upper-lower", "tsens-critical",
+ "tsens-0C";
+ 0C-sensor-num = <16>;
+ tsens-reinit-wa;
+ #thermal-sensor-cells = <1>;
+ };
+
+ spmi_bus: qcom,spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0xc440000 0x1100>,
+ <0xc600000 0x2000000>,
+ <0xe600000 0x100000>,
+ <0xe700000 0xa0000>,
+ <0xc40a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
+ qcom,ghd {
+ compatible = "qcom,gladiator-hang-detect-v3";
+ qcom,threshold-arr = <0x17e0041c>;
+ qcom,config-reg = <0x17e00434>;
+ };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <76800000>;
+ clock-output-names = "xo_board";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ clock-output-names = "chip_sleep_clk";
+ #clock-cells = <0>;
+ };
+ };
+
+ aopcc: qcom,aopcc {
+ compatible = "qcom,aop-qmp-clk";
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "qdss_clk";
+ #clock-cells = <1>;
+ };
+
+ gcc: qcom,gcc@100000 {
+ compatible = "qcom,lagoon-gcc", "syscon";
+ reg = <0x100000 0x1f0000>;
+ reg-names = "cc_base";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ camcc: qcom,camcc@ad00000 {
+ compatible = "qcom,lagoon-camcc", "syscon";
+ reg = <0xad00000 0x16000>;
+ reg-names = "cc_base";
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ dispcc: qcom,dispcc@af00000 {
+ compatible = "qcom,lagoon-dispcc", "syscon";
+ reg = <0xaf00000 0x20000>;
+ reg-names = "cc_base";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gpucc: qcom,gpucc@3d90000 {
+ compatible = "qcom,lagoon-gpucc", "syscon";
+ reg = <0x3d90000 0x9000>;
+ reg-names = "cc_base";
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ vdd_gx-supply = <&VDD_GFX_LEVEL>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ npucc: qcom,npucc@9980000 {
+ compatible = "qcom,lagoon-npucc", "syscon";
+ reg = <0x9980000 0x10000>,
+ <0x9800000 0x10000>,
+ <0x9810000 0x10000>,
+ <0x007841e0 0x8>;
+ reg-names = "cc", "qdsp6ss", "qdsp6ss_pll", "efuse";
+ npu_gdsc-supply = <&npu_cc_core_gdsc>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ aop-msg-client {
+ compatible = "qcom,debugfs-qmp-client";
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "aop";
+ };
+
+ videocc: qcom,videocc@aaf0000 {
+ compatible = "qcom,lagoon-videocc", "syscon";
+ reg = <0x0aaf0000 0x10000>;
+ reg-names = "cc_base";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ clock-names = "cfg_ahb_clk";
+ clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cpucc: syscon@182a0018 {
+ compatible = "syscon";
+ reg = <0x182a0000 0x1000>;
+ };
+
+ mccc: syscon@90b0000 {
+ compatible = "syscon";
+ reg = <0x90b0000 0x1000>;
+ };
+
+ debugcc: qcom,cc-debug {
+ compatible = "qcom,lagoon-debugcc";
+ qcom,gcc = <&gcc>;
+ qcom,videocc = <&videocc>;
+ qcom,camcc = <&camcc>;
+ qcom,dispcc = <&dispcc>;
+ qcom,gpucc = <&gpucc>;
+ qcom,npucc = <&npucc>;
+ qcom,cpucc = <&cpucc>;
+ qcom,mccc = <&mccc>;
+ clock-names = "xo_clk_src";
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ #clock-cells = <1>;
+ };
+
+ cpufreq_hw: qcom,cpufreq-hw {
+ compatible = "qcom,cpufreq-hw";
+ reg = <0x18323000 0x1000>, <0x18325800 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1";
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+ qcom,no-accumulative-counter;
+ #freq-domain-cells = <2>;
+ };
+
+ qcom,cpufreq-hw-debug@18320000 {
+ compatible = "qcom,cpufreq-hw-debug";
+ reg = <0x18320000 0x800>;
+ reg-names = "domain-top";
+ qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;
+ };
+
+ qcom,devfreq-l3 {
+ compatible = "qcom,devfreq-fw";
+ reg = <0x18321000 0x4>, <0x18321110 0x500>, <0x18321920 0x4>;
+ reg-names = "en-base", "ftbl-base", "perf-base";
+
+ qcom,ftbl-row-size = <32>;
+
+ cpu0_l3: qcom,cpu0-cpu-l3-lat {
+ compatible = "qcom,devfreq-fw-voter";
+ };
+
+ cpu6_l3: qcom,cpu6-cpu-l3-lat {
+ compatible = "qcom,devfreq-fw-voter";
+ };
+
+ cdsp_l3: qcom,cdsp-cdsp-l3-lat {
+ compatible = "qcom,devfreq-fw-voter";
+ };
+ };
+
+
+ tcsr_mutex_block: syscon@1f40000 {
+ compatible = "syscon";
+ reg = <0x1f40000 0x20000>;
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_block 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ smem: qcom,smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_region>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ qcom,smp2p_sleepstate {
+ compatible = "qcom,smp2p-sleepstate";
+ qcom,smem-states = <&sleepstate_smp2p_out 0>;
+ interrupt-parent = <&sleepstate_smp2p_in>;
+ interrupts = <0 0>;
+ interrupt-names = "smp2p-sleepstate-in";
+ };
+
+ qcom,msm-cdsp-loader {
+ compatible = "qcom,cdsp-loader";
+ qcom,proc-img-to-load = "cdsp";
+ };
+
+ qcom,msm-adsprpc-mem {
+ compatible = "qcom,msm-adsprpc-mem-region";
+ memory-region = <&adsp_mem>;
+ restrict-access;
+ };
+
+ qcom,msm_fastrpc {
+ compatible = "qcom,msm-fastrpc-compute";
+ qcom,adsp-remoteheap-vmid = <22 37>;
+ qcom,fastrpc-adsp-audio-pdr;
+ qcom,fastrpc-adsp-sensors-pdr;
+ qcom,rpc-latency-us = <235>;
+ qcom,qos-cores = <0 1 2 3 4 5>;
+
+ qcom,msm_fastrpc_compute_cb1 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1401 0x0020>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb2 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1402 0x0020>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb3 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1403 0x0020>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb4 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1404 0x0020>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb5 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1405 0x0020>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb6 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1406 0x0020>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb7 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1407 0x0020>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb8 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1408 0x0020>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb9 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ qcom,secure-context-bank;
+ iommus = <&apps_smmu 0x1409 0x0020>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ qcom,iommu-vmid = <0xA>;
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb10 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x1003 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb11 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x1004 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb12 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x1005 0x0>;
+ shared-cb = <5>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+ };
+
+ qcom,glink {
+ compatible = "qcom,glink";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ glink_modem: modem {
+ qcom,remote-pid = <1>;
+ transport = "smem";
+ mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "modem_smem";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ label = "modem";
+ qcom,glink-label = "mpss";
+
+ qcom,modem_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,low-latency;
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,modem_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_adsp>,
+ <&glink_cdsp>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,modem_ds {
+ qcom,glink-channels = "DS";
+ qcom,intents = <0x4000 0x2>;
+ };
+ };
+
+ glink_adsp: adsp {
+ qcom,remote-pid = <2>;
+ transport = "smem";
+ mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "adsp_smem";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ label = "adsp";
+ qcom,glink-label = "lpass";
+
+ qcom,adsp_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,low-latency;
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,apr_tal_rpmsg {
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,intents = <0x200 20>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,adsp_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_cdsp>;
+ };
+ };
+
+ glink_cdsp: cdsp {
+ qcom,remote-pid = <5>;
+ transport = "smem";
+ mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "dsps_smem";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ label = "cdsp";
+ qcom,glink-label = "cdsp";
+
+ qcom,cdsp_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,msm_cdsprm_rpmsg {
+ compatible = "qcom,msm-cdsprm-rpmsg";
+ qcom,glink-channels = "cdsprmglink-apps-dsp";
+ qcom,intents = <0x20 12>;
+
+ qcom,cdsp-cdsp-l3-gov {
+ compatible = "qcom,cdsp-l3";
+ qcom,target-dev = <&cdsp_l3>;
+ };
+
+ msm_cdsp_rm: qcom,msm_cdsp_rm {
+ compatible = "qcom,msm-cdsp-rm";
+ qcom,qos-latency-us = <70>;
+ qcom,qos-maxhold-ms = <20>;
+ qcom,compute-cx-limit-en;
+ qcom,compute-priority-mode = <2>;
+ };
+ };
+
+ qcom,cdsp_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_adsp>,
+ <&glink_npu>;
+ };
+ };
+
+ glink_npu: npu {
+ qcom,remote-pid = <10>;
+ transport = "smem";
+ mboxes = <&msm_npu IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "npu_smem";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ label = "npu";
+ qcom,glink-label = "npu";
+
+ qcom,npu_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,npu_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_adsp>,
+ <&glink_cdsp>;
+ };
+ };
+ };
+
+ qcom,glinkpkt {
+ compatible = "qcom,glinkpkt";
+
+ qcom,glinkpkt-at-mdm0 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DS";
+ qcom,glinkpkt-dev-name = "at_mdm0";
+ };
+
+ qcom,glinkpkt-apr-apps2 {
+ qcom,glinkpkt-edge = "adsp";
+ qcom,glinkpkt-ch-name = "apr_apps2";
+ qcom,glinkpkt-dev-name = "apr_apps2";
+ };
+
+ qcom,glinkpkt-data40-cntl {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA40_CNTL";
+ qcom,glinkpkt-dev-name = "smdcntl8";
+ };
+
+ qcom,glinkpkt-data1 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA1";
+ qcom,glinkpkt-dev-name = "smd7";
+ };
+
+ qcom,glinkpkt-data4 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA4";
+ qcom,glinkpkt-dev-name = "smd8";
+ };
+
+ qcom,glinkpkt-data11 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA11";
+ qcom,glinkpkt-dev-name = "smd11";
+ };
+ };
+
+ qcom,smp2p-mpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ mpss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ mpss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ /* ipa - inbound entry from mss */
+ smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
+ qcom,entry-name = "wlan";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sleepstate_smp2p_out: sleepstate-out {
+ qcom,entry-name = "sleepstate";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ sleepstate_smp2p_in: qcom,sleepstate-in {
+ qcom,entry-name = "sleepstate_see";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
+ qcom,entry-name = "rdbg";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
+ qcom,entry-name = "rdbg";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
+ qcom,entry-name = "rdbg";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
+ qcom,entry-name = "rdbg";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p-npu {
+ compatible = "qcom,smp2p";
+ qcom,smem = <617>, <616>;
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&msm_npu IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <10>;
+
+ npu_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ npu_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qmp_aop: qcom,qmp-aop@c300000 {
+ compatible = "qcom,qmp-mbox";
+ reg = <0xc300000 0x1000>;
+ reg-names = "msgram";
+ mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "aop_qmp";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ label = "aop";
+ qcom,early-boot;
+ priority = <0>;
+ mbox-desc-offset = <0x0>;
+ #mbox-cells = <1>;
+ };
+
+ qcom,venus@aab0000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0xaab0000 0x2000>;
+
+ vdd-supply = <&video_cc_mvsc_gdsc>;
+ qcom,proxy-reg-names = "vdd";
+ qcom,complete-ramdump;
+
+ clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
+ <&videocc VIDEO_CC_VENUS_AHB_CLK>;
+ clock-names = "core", "ahb";
+ qcom,proxy-clock-names = "core", "ahb";
+
+ qcom,core-freq = <200000000>;
+ qcom,ahb-freq = <200000000>;
+
+ qcom,pas-id = <9>;
+ qcom,msm-bus,name = "pil-venus";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <63 512 0 0>,
+ <63 512 0 304000>;
+ qcom,proxy-timeout-ms = <100>;
+ qcom,firmware-name = "venus";
+ memory-region = <&pil_video_mem>;
+ };
+
+ cx_ipeak_lm: cx_ipeak@1fed000 {
+ compatible = "qcom,cx-ipeak-v2";
+ reg = <0x1fed000 0x9000>;
+ };
+
+ qcom,npu@9800000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x9800000 0x800000>;
+ status = "ok";
+ qcom,pas-id = <23>;
+ qcom,firmware-name = "npu";
+ memory-region = <&pil_npu_mem>;
+
+ /* Outputs to npu */
+ qcom,smem-states = <&npu_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+ };
+
+ eud: qcom,msm-eud@88e0000 {
+ compatible = "qcom,msm-eud";
+ interrupt-names = "eud_irq";
+ interrupt-parent = <&pdc>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x088e0000 0x2000>,
+ <0x088e2000 0x1000>;
+ reg-names = "eud_base", "eud_mode_mgr2";
+ qcom,secure-eud-en;
+ status = "ok";
+ };
+
+ llcc_pmu: llcc-pmu@90cc000 {
+ compatible = "qcom,llcc-pmu-ver1";
+ reg = <0x090cc000 0x300>;
+ reg-names = "lagg-base";
+ };
+
+ llcc_bw_opp_table: llcc-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
+ BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
+ BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
+ BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
+ BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
+ BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
+ };
+
+ suspendable_llcc_bw_opp_table: suspendable-llcc-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 0, 16); /* 0 MB/s */
+ BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
+ BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
+ BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
+ BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
+ BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
+ BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
+ };
+
+ cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;
+ qcom,active-only;
+ operating-points-v2 = <&llcc_bw_opp_table>;
+ };
+
+ cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {
+ compatible = "qcom,bimc-bwmon4";
+ reg = <0x90B6300 0x300>, <0x090B6200 0x200>;
+ reg-names = "base", "global_base";
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&cpu_cpu_llcc_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ ddr_bw_opp_table: ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 200, 4); /* 762 MB/s */
+ BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */
+ BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */
+ BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */
+ BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */
+ BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */
+ BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */
+ BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */
+ BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */
+ BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */
+ BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */
+ };
+
+ cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 {
+ compatible = "qcom,bimc-bwmon5";
+ reg = <0x90cd000 0x1000>;
+ reg-names = "base";
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&cpu_llcc_ddr_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 0, 4); /* 0 MB/s */
+ BW_OPP_ENTRY( 200, 4); /* 762 MB/s */
+ BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */
+ BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */
+ BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */
+ BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */
+ BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */
+ BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */
+ BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */
+ BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */
+ BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */
+ BW_OPP_ENTRY(2092, 4); /* 8136 MB/s */
+ };
+
+ npu_npu_llcc_bw: qcom,npu-npu-llcc-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_LLCC>;
+ operating-points-v2 = <&suspendable_llcc_bw_opp_table>;
+ };
+
+ npu_npu_llcc_bwmon: qcom,npu-npu-llcc-bwmon@9960300 {
+ compatible = "qcom,bimc-bwmon4";
+ reg = <0x00060400 0x300>, <0x00060300 0x200>;
+ reg-names = "base", "global_base";
+ clocks = <&gcc RPMH_CXO_CLK>,
+ <&gcc GCC_NPU_BWMON_DMA_CFG_AHB_CLK>,
+ <&gcc GCC_NPU_BWMON_AXI_CLK>;
+ clock-names = "npu_bwmon_ahb", "npu_bwmon_axi",
+ "npu_bwmon2_axi";
+ qcom,bwmon_clks = "npu_bwmon_ahb", "npu_bwmon_axi",
+ "npu_bwmon2_axi";
+ qcom,msm_bus = <154 512>;
+ qcom,msm_bus_name = "npu_bwmon_cdsp";
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&npu_npu_llcc_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ npu_llcc_ddr_bw: qcom,npu-llcc-ddr-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports = <MSM_BUS_SLAVE_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
+ };
+
+ npu_llcc_ddr_bwmon: qcom,npu-llcc-ddr-bwmon@90CE000 {
+ compatible = "qcom,bimc-bwmon5";
+ reg = <0x90CE000 0x1000>;
+ reg-names = "base";
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&npu_llcc_ddr_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ npudsp_npu_ddr_bw: qcom,npudsp-npu-ddr-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;
+ operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
+ };
+
+ npudsp_npu_ddr_bwmon: qcom,npudsp-npu-ddr-bwmon@70200 {
+ compatible = "qcom,bimc-bwmon4";
+ reg = <0x00070300 0x300>, <0x00070200 0x200>;
+ reg-names = "base", "global_base";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc RPMH_CXO_CLK>,
+ <&gcc GCC_NPU_BWMON_DSP_CFG_AHB_CLK>,
+ <&gcc GCC_NPU_BWMON_AXI_CLK>;
+ clock-names = "npu_bwmon_ahb", "npu_bwmon_axi",
+ "npu_bwmon2_axi";
+ qcom,bwmon_clks = "npu_bwmon_ahb", "npu_bwmon_axi",
+ "npu_bwmon2_axi";
+ qcom,msm_bus = <154 512>;
+ qcom,msm_bus_name = "npu_bwmon_cdsp";
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&npudsp_npu_ddr_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;
+ qcom,active-only;
+ operating-points-v2 = <&llcc_bw_opp_table>;
+ };
+
+ cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
+
+ cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
+ qcom,target-dev = <&cpu0_l3>;
+ qcom,cachemiss-ev = <0x17>;
+ qcom,core-dev-table =
+ < 768000 300000000 >,
+ < 1017600 556800000 >,
+ < 1248000 806400000 >,
+ < 1516800 940800000 >,
+ < 1612800 1209600000 >,
+ < 1804800 1459000000 >;
+ };
+
+ cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
+ qcom,target-dev = <&cpu0_cpu_llcc_lat>;
+ qcom,cachemiss-ev = <0x2A>;
+ qcom,core-dev-table =
+ < 1248000 MHZ_TO_MBPS(300, 16) >,
+ < 1516800 MHZ_TO_MBPS(466, 16) >,
+ < 1804800 MHZ_TO_MBPS(600, 16) >;
+ };
+
+ cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
+ qcom,target-dev = <&cpu0_llcc_ddr_lat>;
+ qcom,cachemiss-ev = <0x1000>;
+ qcom,core-dev-table =
+ < 768000 MHZ_TO_MBPS( 300, 4) >,
+ < 1017600 MHZ_TO_MBPS( 451, 4) >,
+ < 1248000 MHZ_TO_MBPS( 547, 4) >,
+ < 1516800 MHZ_TO_MBPS( 768, 4) >,
+ < 1804800 MHZ_TO_MBPS(1017, 4) >;
+ };
+
+ cpu0_computemon: qcom,cpu0-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
+ qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 768000 MHZ_TO_MBPS( 300, 4) >,
+ < 1248000 MHZ_TO_MBPS( 451, 4) >,
+ < 1516800 MHZ_TO_MBPS( 547, 4) >,
+ < 1804800 MHZ_TO_MBPS( 768, 4) >;
+ };
+ };
+
+ cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;
+ qcom,active-only;
+ operating-points-v2 = <&llcc_bw_opp_table>;
+ };
+
+ cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu6_memlat_cpugrp: qcom,cpu6-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU6 &CPU7>;
+
+ cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU6 &CPU7>;
+ qcom,target-dev = <&cpu6_l3>;
+ qcom,cachemiss-ev = <0x17>;
+ qcom,access-ev = <0x2B>;
+ qcom,wb-ev = <0x18>;
+ qcom,core-dev-table =
+ < 1036800 556800000 >,
+ < 1248000 806400000 >,
+ < 1555400 940800000 >,
+ < 1766400 1209600000 >,
+ < 1900800 1401600000 >,
+ < 2246000 1459000000 >;
+ };
+
+ cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU6 &CPU7>;
+ qcom,target-dev = <&cpu6_cpu_llcc_lat>;
+ qcom,cachemiss-ev = <0x2A>;
+ qcom,core-dev-table =
+ < 787200 MHZ_TO_MBPS(300, 16) >,
+ < 1036800 MHZ_TO_MBPS(466, 16) >,
+ < 1248000 MHZ_TO_MBPS(600, 16) >,
+ < 1555200 MHZ_TO_MBPS(806, 16) >,
+ < 2246000 MHZ_TO_MBPS(933, 16) >;
+ };
+
+ cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU6 &CPU7>;
+ qcom,target-dev = <&cpu6_llcc_ddr_lat>;
+ qcom,cachemiss-ev = <0x1000>;
+ qcom,core-dev-table =
+ < 1036800 MHZ_TO_MBPS( 547, 4) >,
+ < 1248000 MHZ_TO_MBPS(1017, 4) >,
+ < 1555200 MHZ_TO_MBPS(1555, 4) >,
+ < 1900800 MHZ_TO_MBPS(1804, 4) >,
+ < 2246000 MHZ_TO_MBPS(2092, 4) >;
+ };
+
+ cpu6_computemon: qcom,cpu6-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU6 &CPU7>;
+ qcom,target-dev = <&cpu6_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 1248800 MHZ_TO_MBPS( 547, 4) >,
+ < 1401600 MHZ_TO_MBPS( 768, 4) >,
+ < 1555200 MHZ_TO_MBPS(1017, 4) >,
+ < 1766400 MHZ_TO_MBPS(1555, 4) >,
+ < 1900800 MHZ_TO_MBPS(1804, 4) >,
+ < 2246000 MHZ_TO_MBPS(2092, 4) >;
+ };
+ };
+
+ keepalive_opp_table: keepalive-opp-table {
+ compatible = "operating-points-v2";
+ opp-1 {
+ opp-hz = /bits/ 64 < 1 >;
+ };
+ };
+
+ snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive {
+ compatible = "qcom,devbw";
+ governor = "powersave";
+ qcom,src-dst-ports = <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_IMEM_CFG>;
+ qcom,active-only;
+ status = "ok";
+ operating-points-v2 = <&keepalive_opp_table>;
+ };
+
+ bus_proxy_client: qcom,bus_proxy_client {
+ compatible = "qcom,bus-proxy-client";
+ qcom,msm-bus,name = "bus-proxy-client";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_MDP_PORT0 MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_MDP_PORT0
+ MSM_BUS_SLAVE_EBI_CH0 0 5000000>;
+ qcom,msm-bus,active-only;
+ status = "ok";
+ };
+
+ sdhc_1: sdhci@7c4000 {
+ compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe";
+ reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7c8000 0x8000>;
+ reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";
+
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <8>;
+ qcom,large-address-bus;
+
+ qcom,clk-rates = <400000 25000000 50000000 100000000
+ 192000000 384000000>;
+ qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+
+ qcom,devfreq,freq-table = <50000000 200000000>;
+
+ qcom,scaling-lower-bus-speed-mode = "DDR52";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface_clk", "core_clk", "ice_core_clk";
+
+ qcom,ice-clk-rates = <300000000 100000000>;
+
+ qcom,msm-bus,name = "sdhc1";
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <150 10073 0 0>,
+ <135 512 0 0>,
+ <1 825 0 0>,
+ /* 400 KB/s */
+ <150 10073 1000 790000>,
+ <135 512 1000 1800000>,
+ <1 825 2000 131000>,
+ /* 25 MB/s */
+ <150 10073 50000 790000>,
+ <135 512 50000 1800000>,
+ <1 825 30000 131000>,
+ /* 50 MB/s */
+ <150 10073 50000 790000>,
+ <135 512 80000 1800000>,
+ <1 825 40000 131000>,
+ /* 100 MB/s */
+ <150 10073 50000 790000>,
+ <135 512 100000 1800000>,
+ <1 825 50000 131000>,
+ /* 200 MB/s */
+ <150 10073 50000 790000>,
+ <135 512 150000 1800000>,
+ <1 825 80000 131000>,
+ /* 400 MB/s */
+ <150 10073 261438 3190000>,
+ <135 512 261438 4000000>,
+ <1 825 300000 294000>,
+ /* Max. bandwidth */
+ <150 10073 1338562 4290000>,
+ <135 512 1338562 7200000>,
+ <1 825 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
+ 100000000 200000000 400000000 4294967295>;
+
+ /* PM QoS */
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <59 59>;
+ qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
+ qcom,pm-qos-cmdq-latency-us = <65 65>, <65 65>;
+ qcom,pm-qos-legacy-latency-us = <65 65>, <65 65>;
+
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>;
+
+ qcom,nonremovable;
+ status = "disabled";
+ };
+
+ sdhc_2: sdhci@8804000 {
+ compatible = "qcom,sdhci-msm-v5";
+ reg = <0x8804000 0x1000>;
+ reg-names = "hc_mem";
+
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <4>;
+ qcom,large-address-bus;
+
+ qcom,clk-rates = <400000 25000000
+ 50000000 100000000 202000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
+ "SDR104";
+
+ qcom,devfreq,freq-table = <50000000 202000000>;
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>;
+ clock-names = "iface_clk", "core_clk";
+
+ qcom,msm-bus,name = "sdhc2";
+ qcom,msm-bus,num-cases = <7>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <81 10073 0 0>,
+ <135 512 0 0>,
+ <1 608 0 0>,
+ /* 400 KB/s*/
+ <81 10073 1000 790000>,
+ <135 512 1000 1800000>,
+ <1 608 2000 131000>,
+ /* 25 MB/s */
+ <81 10073 50000 790000>,
+ <135 512 50000 1800000>,
+ <1 608 30000 131000>,
+ /* 50 MB/s */
+ <81 10073 50000 790000>,
+ <135 512 80000 1800000>,
+ <1 608 40000 131000>,
+ /* 100 MB/s */
+ <81 10073 50000 790000>,
+ <135 512 100000 1800000>,
+ <1 608 50000 131000>,
+ /* 200 MB/s */
+ <81 10073 261438 3190000>,
+ <135 512 261438 4000000>,
+ <1 608 300000 294000>,
+ /* Max. bandwidth */
+ <81 10073 1338562 4290000>,
+ <135 512 1338562 7200000>,
+ <1 608 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 25000000 50000000
+ 100000000 200000000 4294967295>;
+
+ /* PM QoS */
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <59 59>;
+ qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
+ qcom,pm-qos-legacy-latency-us = <65 65>, <65 65>;
+
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>;
+
+ status = "disabled";
+ };
+
+ icnss: qcom,icnss@18800000 {
+ compatible = "qcom,icnss";
+ reg = <0x18800000 0x800000>,
+ <0xb0000000 0x10000>;
+ reg-names = "membase", "smmu_iova_ipa";
+ iommus = <&apps_smmu 0x20 0x1>;
+ interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
+ <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
+ <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */ >,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */ >;
+ qcom,iommu-dma = "fastmap";
+ qcom,iommu-faults = "stall-disable", "non-fatal";
+ qcom,wlan-msa-fixed-region = <&wlan_fw_mem>;
+ qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
+ vdd-cx-mx-supply = <&L4A>;
+ vdd-1.8-xo-supply = <&L7A>;
+ vdd-1.3-rfa-supply = <&L2E>;
+ vdd-3.3-ch1-supply = <&L11E>;
+ vdd-3.3-ch0-supply = <&L10E>;
+ qcom,vdd-cx-mx-config = <0 0>;
+ qcom,vdd-1.3-rfa-config = <1224000 1304000>;
+ qcom,vdd-3.3-ch1-config = <3000000 3312000>;
+ qcom,vdd-3.3-ch0-config = <3000000 3312000>;
+ qcom,smp2p_map_wlan_1_in {
+ interrupts-extended = <&smp2p_wlan_1_in 0 0>,
+ <&smp2p_wlan_1_in 1 0>;
+ interrupt-names = "qcom,smp2p-force-fatal-error",
+ "qcom,smp2p-early-crash-ind";
+ };
+ };
+
+ qfprom: qfprom@780000 {
+ compatible = "qcom,qfprom";
+ reg = <0x00780000 0x7000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ read-only;
+ ranges;
+
+ gpu_speed_bin: gpu_speed_bin@6015 {
+ reg = <0x6015 0x1>;
+ bits = <0 8>;
+ };
+
+ feat_conf8: feat_conf8@6024 {
+ reg = <0x6024 0x4>;
+ };
+
+ gpu_gaming_bin: gpu_gaming_bin@6026 {
+ reg = <0x6026 0x1>;
+ bits = <5 1>;
+ };
+ };
+
+ mem_dump {
+ compatible = "qcom,mem-dump";
+ memory-region = <&dump_mem>;
+
+ rpmh {
+ qcom,dump-size = <0x2000000>;
+ qcom,dump-id = <0xec>;
+ };
+
+ rpm_sw {
+ qcom,dump-size = <0x28000>;
+ qcom,dump-id = <0xea>;
+ };
+
+ pmic {
+ qcom,dump-size = <0x80000>;
+ qcom,dump-id = <0xe4>;
+ };
+
+ fcm {
+ qcom,dump-size = <0x8400>;
+ qcom,dump-id = <0xee>;
+ };
+
+ etf_swao {
+ qcom,dump-size = <0x10000>;
+ qcom,dump-id = <0xf1>;
+ };
+
+ etr_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x100>;
+ };
+
+ etfswao_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x102>;
+ };
+
+ misc_data {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xe8>;
+ };
+
+ ipa {
+ qcom,dump-size = <0x11000>;
+ qcom,dump-id = <0x150>;
+ };
+
+ etf_lpass {
+ qcom,dump-size = <0x4000>;
+ qcom,dump-id = <0xf4>;
+ };
+
+ etflpass_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x104>;
+ };
+
+ c0_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x0>;
+ };
+
+ c100_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x1>;
+ };
+
+ c200_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x2>;
+ };
+
+ c300_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x3>;
+ };
+
+ c400_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x4>;
+ };
+
+ c500_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x5>;
+ };
+
+ c600_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x6>;
+ };
+
+ c700_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x7>;
+ };
+
+ c0_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x130>;
+ };
+
+ c100_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x131>;
+ };
+
+ c200_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x132>;
+ };
+
+ c300_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x133>;
+ };
+
+ c400_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x134>;
+ };
+
+ c500_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x135>;
+ };
+
+ c600_scandump {
+ qcom,dump-size = <0x25900>;
+ qcom,dump-id = <0x136>;
+ };
+
+ c700_scandump {
+ qcom,dump-size = <0x25900>;
+ qcom,dump-id = <0x137>;
+ };
+
+ l1_i_cache0 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x60>;
+ };
+
+ l1_icache100 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x61>;
+ };
+
+ l1_icache200 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x62>;
+ };
+
+ l1_icache300 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x63>;
+ };
+
+ l1_icache400 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x64>;
+ };
+
+ l1_icache500 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x65>;
+ };
+
+ l1_icache600 {
+ qcom,dump-size = <0x21000>;
+ qcom,dump-id = <0x66>;
+ };
+
+ l1_icache700 {
+ qcom,dump-size = <0x21000>;
+ qcom,dump-id = <0x67>;
+ };
+
+ l1_dcache0 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x80>;
+ };
+
+ l1_dcache100 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x81>;
+ };
+
+ l1_dcache200 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x82>;
+ };
+
+ l1_dcache300 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x83>;
+ };
+
+ l1_dcache400 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x84>;
+ };
+
+ l1_dcache500 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x85>;
+ };
+
+ l1_dcache600 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x86>;
+ };
+
+ l1_dcache700 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x87>;
+ };
+
+ l1_itlb600 {
+ qcom,dump-size = <0x300>;
+ qcom,dump-id = <0x26>;
+ };
+
+ l1_itlb700 {
+ qcom,dump-size = <0x300>;
+ qcom,dump-id = <0x27>;
+ };
+
+ l1_dtlb600 {
+ qcom,dump-size = <0x480>;
+ qcom,dump-id = <0x46>;
+ };
+
+ l1_dtlb700 {
+ qcom,dump-size = <0x480>;
+ qcom,dump-id = <0x47>;
+ };
+
+ l2_cache600 {
+ qcom,dump-size = <0x48000>;
+ qcom,dump-id = <0xc6>;
+ };
+
+ l2_cache700 {
+ qcom,dump-size = <0x48000>;
+ qcom,dump-id = <0xc7>;
+ };
+
+ l2_tlb0 {
+ qcom,dump-size = <0x5a00>;
+ qcom,dump-id = <0x120>;
+ };
+
+ l2_tlb100 {
+ qcom,dump-size = <0x5a00>;
+ qcom,dump-id = <0x121>;
+ };
+
+ l2_tlb200 {
+ qcom,dump-size = <0x5a00>;
+ qcom,dump-id = <0x122>;
+ };
+
+ l2_tlb300 {
+ qcom,dump-size = <0x5a00>;
+ qcom,dump-id = <0x123>;
+ };
+
+ l2_tlb400 {
+ qcom,dump-size = <0x5a00>;
+ qcom,dump-id = <0x124>;
+ };
+
+ l2_tlb500 {
+ qcom,dump-size = <0x5a00>;
+ qcom,dump-id = <0x125>;
+ };
+
+ l2_tlb600 {
+ qcom,dump-size = <0x7800>;
+ qcom,dump-id = <0x126>;
+ };
+
+ l2_tlb700 {
+ qcom,dump-size = <0x7800>;
+ qcom,dump-id = <0x127>;
+ };
+
+ llcc1_d_cache {
+ qcom,dump-size = <0x1141c0>;
+ qcom,dump-id = <0x140>;
+ };
+ };
+
+ qcom,msm_gsi {
+ compatible = "qcom,msm_gsi";
+ };
+
+ qcom,rmnet-ipa {
+ compatible = "qcom,rmnet-ipa3";
+ qcom,rmnet-ipa-ssr;
+ qcom,ipa-platform-type-msm;
+ qcom,ipa-advertise-sg-support;
+ qcom,ipa-napi-enable;
+ };
+
+ qcom,ipa_fws {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <0xf>;
+ qcom,firmware-name = "lagoon_ipa_fws";
+ qcom,pil-force-shutdown;
+ memory-region = <&pil_ipa_fw_mem>;
+ };
+
+ ipa_hw: qcom,ipa@1e00000 {
+ compatible = "qcom,ipa";
+ reg = <0x1e00000 0x84000>,
+ <0x1e04000 0x23000>;
+ reg-names = "ipa-base", "gsi-base";
+ interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ipa-irq", "gsi-irq";
+ qcom,ipa-hw-ver = <18>; /* IPA core version = IPAv4.7 */
+ qcom,ipa-hw-mode = <0>;
+ qcom,platform-type = <1>; /* MSM platform */
+ qcom,ee = <0>;
+ qcom,use-ipa-tethering-bridge;
+ qcom,modem-cfg-emb-pipe-flt;
+ qcom,ipa-wdi2;
+ qcom,ipa-wdi2_over_gsi;
+ qcom,use-ipa-pm;
+ qcom,arm-smmu;
+ qcom,smmu-fast-map;
+ qcom,bandwidth-vote-for-ipa;
+ qcom,ipa-endp-delay-wa;
+ qcom,use-64-bit-dma-mask;
+ qcom,msm-bus,name = "ipa";
+ qcom,use-gsi-ipa-fw = "lagoon_ipa_fws";
+ qcom,wan-use-skb-page;
+ qcom,msm-bus,num-cases = <5>;
+ qcom,msm-bus,num-paths = <5>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 0 0>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 0>,
+
+ /* SVS2 */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 150000 500000>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 150000 700000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 75000 700000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 55000>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 100>,
+
+ /* SVS */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 625000 1200000>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 625000 1100000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 312500 1500000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 134000>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 180>,
+
+ /* NOMINAL */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 1250000 2400000>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 1250000 1800000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 625000 3100000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 223000>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 450>,
+
+ /* TURBO */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 2000000 3500000>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 2000000 2000000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 1000000 4100000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 358000>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 550>;
+
+
+ qcom,bus-vector-names =
+ "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
+ qcom,throughput-threshold = <310 600 1000>;
+ qcom,scaling-exceptions = <>;
+
+ /* smp2p information */
+ qcom,smp2p_map_ipa_1_out {
+ compatible = "qcom,smp2p-map-ipa-1-out";
+ qcom,smem-states = <&smp2p_ipa_1_out 0>;
+ qcom,smem-state-names = "ipa-smp2p-out";
+ };
+
+ qcom,smp2p_map_ipa_1_in {
+ compatible = "qcom,smp2p-map-ipa-1-in";
+ interrupts-extended = <&smp2p_ipa_1_in 0 0>;
+ interrupt-names = "ipa-smp2p-in";
+ };
+ };
+
+ ipa_smmu_ap: ipa_smmu_ap {
+ compatible = "qcom,ipa-smmu-ap-cb";
+ iommus = <&apps_smmu 0x0440 0x0>;
+ qcom,iommu-dma-addr-pool = <0x20000000 0x40000000>;
+ /* modem tables in IMEM */
+ qcom,additional-mapping = <0x146a8000 0x146a8000 0x2000>;
+ qcom,iommu-dma = "fastmap";
+ qcom,ipa-q6-smem-size = <26624>;
+ qcom,geometry-mapping = <0x0 0xF0000000>;
+ };
+
+ ipa_smmu_wlan: ipa_smmu_wlan {
+ compatible = "qcom,ipa-smmu-wlan-cb";
+ iommus = <&apps_smmu 0x0441 0x0>;
+ /* ipa-uc ram */
+ qcom,additional-mapping = <0x1ea0000 0x1ea0000 0x80000>;
+ qcom,iommu-dma = "atomic";
+ };
+
+ ipa_smmu_uc: ipa_smmu_uc {
+ compatible = "qcom,ipa-smmu-uc-cb";
+ iommus = <&apps_smmu 0x0442 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0x20000000>;
+ };
+};
+
+#include "lagoon-gdsc.dtsi"
+#include "lagoon-usb.dtsi"
+#include "lagoon-gpu.dtsi"
+#include "lagoon-npu.dtsi"
+#include "camera/lagoon-camera.dtsi"
+
+&gcc_ufs_phy_gdsc {
+ status = "ok";
+};
+
+&gcc_usb30_prim_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
+ status = "ok";
+};
+
+&cam_cc_bps_gdsc {
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&cam_cc_ife_0_gdsc {
+ status = "ok";
+};
+
+&cam_cc_ife_1_gdsc {
+ status = "ok";
+};
+
+&cam_cc_ife_2_gdsc {
+ status = "ok";
+};
+
+&cam_cc_ipe_0_gdsc {
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&cam_cc_titan_top_gdsc {
+ status = "ok";
+};
+
+&mdss_core_gdsc {
+ status = "ok";
+};
+
+&gpu_gx_gdsc {
+ parent-supply = <&VDD_GFX_LEVEL>;
+ status = "ok";
+};
+
+&gpu_cx_gdsc {
+ parent-supply = <&VDD_CX_LEVEL>;
+ vdd_parent-supply = <&VDD_CX_LEVEL>;
+ status = "ok";
+};
+
+&npu_cc_core_gdsc {
+ status = "ok";
+};
+
+&video_cc_mvs0_gdsc {
+ clock-names = "ahb_clk";
+ clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&video_cc_mvsc_gdsc {
+ clock-names = "ahb_clk";
+ clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+ status = "ok";
+};
+
+#include "msm-arm-smmu-lagoon.dtsi"
+#include "lagoon-pinctrl.dtsi"
+#include "lagoon-pm.dtsi"
+#include "lagoon-regulators.dtsi"
+#include "lagoon-coresight.dtsi"
+#include "pm6350.dtsi"
+#include "pm7250b.dtsi"
+#include "pm6150l.dtsi"
+#include "pmk8350.dtsi"
+#include "lagoon-ion.dtsi"
+#include "lagoon-qupv3.dtsi"
+#include "lagoon-audio.dtsi"
+#include "ipcc-test-lagoon.dtsi"
+#include "lagoon-vidc.dtsi"
+
+&qupv3_se10_i2c {
+ status = "ok";
+ #include "pm8008.dtsi"
+};
+
+&pm8008_8 {
+ /* PM8008 IRQ STAT */
+ interrupt-parent = <&tlmm>;
+ interrupts = <59 IRQ_TYPE_EDGE_RISING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm8008_active &pm8008_interrupt>;
+};
+
+&pm8008_regulators {
+ vdd_l1_l2-supply = <&S8E>;
+ vdd_l3_l4-supply = <&BOB>;
+ vdd_l5-supply = <&BOB>;
+ vdd_l6-supply = <&S2A>;
+ vdd_l7-supply = <&BOB>;
+};
+
+&L1P {
+ regulator-max-microvolt = <1200000>;
+ /* Reduced the headroom by 16mV for AHC */
+ qcom,min-dropout-voltage = <110000>;
+};
+
+&L2P {
+ regulator-max-microvolt = <1200000>;
+ /* Reduced the headroom by 16mV for AHC */
+ qcom,min-dropout-voltage = <110000>;
+};
+
+&L3P {
+ regulator-max-microvolt = <2800000>;
+ qcom,min-dropout-voltage = <128000>;
+};
+
+&L4P {
+ regulator-max-microvolt = <2904000>;
+ qcom,min-dropout-voltage = <96000>;
+};
+
+&L5P {
+ regulator-max-microvolt = <2900000>;
+ qcom,min-dropout-voltage = <300000>;
+};
+
+&L6P {
+ regulator-max-microvolt = <1800000>;
+ /* Reduced the headroom by 16mV for AHC */
+ qcom,min-dropout-voltage = <56000>;
+};
+
+&L7P {
+ regulator-max-microvolt = <3140000>;
+ qcom,min-dropout-voltage = <120000>;
+};
+
+&pm7250b_charger {
+ dpdm-supply = <&qusb_phy0>;
+
+ smb5_vbus: qcom,smb5-vbus {
+ regulator-name = "smb5-vbus";
+ };
+
+ smb5_vconn: qcom,smb5-vconn {
+ regulator-name = "smb5-vconn";
+ };
+};
+
+/*Debug UART*/
+&qupv3_se9_2uart {
+ status = "ok";
+};
+
+/* HS UART */
+&qupv3_se1_4uart {
+ status = "ok";
+};
+
+#include "lagoon-bus.dtsi"
+#include "lagoon-thermal.dtsi"
+
+&pm7250b_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ charger_skin_therm {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "charger_skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ conn_therm {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "conn_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm7250b_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ io-channels = <&pm7250b_vadc ADC_AMUX_THM1_PU2>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>;
+
+ /* Channel nodes */
+ charger_skin_therm {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ conn_therm {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm6150l_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &rfc_cam_therm_default
+ &rear_cam_flash_therm_default
+ &quiet_therm_default
+ >;
+
+ pa_therm2 {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "pa_therm2";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ msm_therm {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "msm_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1 {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "pa_therm1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ rfc_cam_therm {
+ reg = <ADC_GPIO2_PU2>;
+ label = "rfc_cam_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ rear_cam_flash_therm {
+ reg = <ADC_GPIO3_PU2>;
+ label = "rear_cam_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ quiet_therm {
+ reg = <ADC_GPIO4_PU2>;
+ label = "quiet_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm6150l_gpios {
+ rfc_cam_therm {
+ rfc_cam_therm_default: rfc_cam_therm_default {
+ pins = "gpio6";
+ bias-high-impedance;
+ };
+ };
+
+ rear_cam_flash_therm {
+ rear_cam_flash_therm_default: rear_cam_flash_therm_default {
+ pins = "gpio7";
+ bias-high-impedance;
+ };
+ };
+
+ quiet_therm {
+ quiet_therm_default: quiet_therm_default {
+ pins = "gpio10";
+ bias-high-impedance;
+ };
+ };
+};
+
+&pm6150l_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ io-channels = <&pm6150l_vadc ADC_AMUX_THM1_PU2>,
+ <&pm6150l_vadc ADC_AMUX_THM3_PU2>,
+ <&pm6150l_vadc ADC_GPIO3_PU2>,
+ <&pm6150l_vadc ADC_GPIO4_PU2>;
+
+ /* Channel nodes */
+
+ pa_therm1 {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm0 {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ rear_cam_flash_therm {
+ reg = <ADC_GPIO3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ quiet_therm {
+ reg = <ADC_GPIO4_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pmk8350_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>;
+
+ xo_therm {
+ reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&spmi_bus {
+ qcom,pm6150l@4 {
+ pm6150l_adc_tm_iio: adc_tm@3400 {
+ compatible = "qcom,adc-tm5-iio";
+ reg = <0x3400 0x100>;
+ #thermal-sensor-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ io-channels = <&pm6150l_vadc ADC_AMUX_THM2_PU2>,
+ <&pm6150l_vadc ADC_GPIO2_PU2>;
+
+ msm_therm {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ rfc_cam_therm {
+ reg = <ADC_GPIO2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+ };
+ };
+};
+
+&pm7250b_pdphy {
+ vdd-pdphy-supply = <&L3A>;
+ vbus-supply = <&smb5_vbus>;
+ vconn-supply = <&smb5_vconn>;
+};
+
+&usb0 {
+ extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>;
+};
+
+&usb_qmp_dp_phy {
+ extcon = <&pm7250b_pdphy>;
+};
+
+&msm_vidc0 {
+ qcom,cx-ipeak-data = <&cx_ipeak_lm 5>;
+ qcom,clock-freq-threshold = <460000000>;
+};
+
+&msm_vidc1 {
+ qcom,cx-ipeak-data = <&cx_ipeak_lm 5>;
+ qcom,clock-freq-threshold = <380000000>;
+};
+
+#include "lagoon-sde.dtsi"
+#include "lagoon-sde-pll.dtsi"
+#include "msm-rdbg.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-atp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lito-atp-overlay.dts
new file mode 100755
index 0000000..99e6f63
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-atp-overlay.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lito-atp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito ATP";
+ compatible = "qcom,lito-atp", "qcom,lito", "qcom,atp";
+ qcom,msm-id = <400 0x10000>, <440 0x10000>;
+ qcom,board-id = <33 0>;
+};
+
+&ufsphy_mem {
+ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-atp.dts b/arch/arm64/boot/dts/vendor/qcom/lito-atp.dts
new file mode 100755
index 0000000..8828a8487
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-atp.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+#include "lito.dtsi"
+#include "lito-atp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito ATP";
+ compatible = "qcom,lito-atp", "qcom,lito", "qcom,atp";
+ qcom,board-id = <33 0>;
+};
+
+&ufsphy_mem {
+ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-atp.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-atp.dtsi
new file mode 100755
index 0000000..895d317
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-atp.dtsi
@@ -0,0 +1,277 @@
+#include <dt-bindings/gpio/gpio.h>
+#include "lito-audio-overlay.dtsi"
+#include "lito-pmic-overlay.dtsi"
+#include "lito-sde-display.dtsi"
+#include "lito-thermal-overlay.dtsi"
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm8150l_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+
+ vdda_usb_ss_dp_core: vdda_usb_ss_dp_core {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_supply";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ enable-active-high;
+ gpio = <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_eldo13>;
+ };
+
+};
+
+&usb_qmp_dp_phy {
+ vdd-supply = <&vdda_usb_ss_dp_core>;
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v4-lito";
+
+ vdda-phy-supply = <&pm8150_l5>;
+ vdda-pll-supply = <&pm8150_l9>;
+ vdda-phy-max-microamp = <90200>;
+ vdda-pll-max-microamp = <19000>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm8150a_l7>;
+ vcc-voltage-level = <2950000 2960000>;
+ vccq2-supply = <&pm8150_s4>;
+ vcc-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+
+ qcom,vddp-ref-clk-supply = <&pm8150_l9>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vddp-ref-clk-min-microamp = <0>;
+ qcom,vddp-ref-clk-min-uV = <1152000>;
+ qcom,vddp-ref-clk-max-uV = <1200000>;
+ status = "ok";
+};
+
+&sdhc_1 {
+ vdd-supply = <&pm8150a_l7>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&pm8150_s4>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&pm8150a_l9>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&pm8150a_l6>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&pm8150a_amoled {
+ status = "ok";
+};
+
+&pm7250b_charger {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+ <&pm7250b_vadc ADC_USB_IN_I>,
+ <&pm7250b_vadc ADC_CHG_TEMP>,
+ <&pm7250b_vadc ADC_DIE_TEMP>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+ <&pm7250b_vadc ADC_SBUx>,
+ <&pm7250b_vadc ADC_VPH_PWR>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp",
+ "die_temp",
+ "conn_temp",
+ "sbux_res",
+ "vph_voltage";
+ qcom,batteryless-platform;
+ qcom,sec-charger-config = <1>;
+ qcom,auto-recharge-soc = <98>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ qcom,suspend-input-on-debug-batt;
+};
+
+&pm7250b_qg {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU2>,
+ <&pm7250b_vadc ADC_BAT_ID_PU2>;
+ io-channel-names = "batt-therm",
+ "batt-id";
+ qcom,qg-iterm-ma = <100>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+};
+
+&qupv3_se7_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "ok";
+ qcom,i2c-touch-active = "st,fts";
+
+ st_fts@49 {
+ compatible = "st,fts";
+ reg = <0x49>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 0x2008>;
+ vdd-supply = <&pm8150_s4>;
+ avdd-supply = <&pm8150_l13>;
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ st,irq-gpio = <&tlmm 9 0x2008>;
+ st,reset-gpio = <&tlmm 8 0x00>;
+ st,regulator_dvdd = "vdd";
+ st,regulator_avdd = "avdd";
+ };
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_dual_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_sim_sec_hd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+ qcom,platform-sec-reset-gpio = <&tlmm 128 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_video>;
+};
+
+&qupv3_se0_i2c {
+ status = "ok";
+ qcom,clk-freq-out = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 34 0x00>;
+ qcom,nq-ven = <&tlmm 12 0x00>;
+ qcom,nq-firm = <&tlmm 35 0x00>;
+ qcom,nq-clkreq = <&tlmm 31 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <34 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-audio-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-audio-overlay.dtsi
new file mode 100755
index 0000000..d40caaf
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-audio-overlay.dtsi
@@ -0,0 +1,492 @@
+#include <dt-bindings/clock/qcom,audio-ext-clk.h>
+#include <dt-bindings/sound/qcom,bolero-clk-rsc.h>
+#include <dt-bindings/sound/audio-codec-port-types.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lito-lpi.dtsi"
+
+&bolero {
+ qcom,num-macros = <4>;
+ bolero-clk-rsc-mngr {
+ compatible = "qcom,bolero-clk-rsc-mngr";
+ qcom,fs-gen-sequence = <0x3000 0x1>,
+ <0x3004 0x1>, <0x3080 0x2>;
+ qcom,rx_mclk_mode_muxsel = <0x033240D8>;
+ qcom,wsa_mclk_mode_muxsel = <0x033220D8>;
+ qcom,va_mclk_mode_muxsel = <0x033A0000>;
+ clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
+ "wsa_core_clk", "wsa_npl_clk", "va_core_clk", "va_npl_clk";
+ clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
+ <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
+ <&clock_audio_wsa_1 0>, <&clock_audio_wsa_2 0>,
+ <&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
+ };
+
+ tx_macro: tx-macro@3220000 {
+ compatible = "qcom,tx-macro";
+ reg = <0x3220000 0x0>;
+ clock-names = "tx_core_clk", "tx_npl_clk";
+ clocks = <&clock_audio_tx_1 0>,
+ <&clock_audio_tx_2 0>;
+ qcom,tx-swr-gpios = <&tx_swr_gpios>;
+ qcom,tx-dmic-sample-rate = <2400000>;
+ swr2: tx_swr_master {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ qcom,swr-master-version = <0x01050001>;
+ qcom,swr_master_id = <3>;
+ qcom,mipi-sdw-block-packing-mode = <1>;
+ swrm-io-base = <0x3230000 0x0>;
+ interrupts-extended =
+ <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq", "swr_wake_irq";
+ qcom,swr-wakeup-required = <1>;
+ qcom,swr-num-ports = <5>;
+ qcom,swr-port-mapping = <1 PCM_OUT1 0xF>,
+ <2 ADC1 0x1>, <2 ADC2 0x2>,
+ <3 ADC3 0x1>, <3 ADC4 0x2>,
+ <4 DMIC0 0x1>, <4 DMIC1 0x2>,
+ <4 DMIC2 0x4>, <4 DMIC3 0x8>,
+ <5 DMIC4 0x1>, <5 DMIC5 0x2>,
+ <5 DMIC6 0x4>, <5 DMIC7 0x8>;
+ qcom,swr-num-dev = <1>;
+ qcom,swr-clock-stop-mode0 = <1>;
+ qcom,swr-mstr-irq-wakeup-capable = <1>;
+ wcd938x_tx_slave: wcd938x-tx-slave {
+ compatible = "qcom,wcd938x-slave";
+ reg = <0x0D 0x01170223>;
+ };
+ };
+ };
+
+ rx_macro: rx-macro@3200000 {
+ compatible = "qcom,rx-macro";
+ reg = <0x3200000 0x0>;
+ clock-names = "rx_core_clk", "rx_npl_clk";
+ clocks = <&clock_audio_rx_1 0>,
+ <&clock_audio_rx_2 0>;
+ qcom,rx-swr-gpios = <&rx_swr_gpios>;
+ qcom,rx_mclk_mode_muxsel = <0x033240D8>;
+ qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ swr1: rx_swr_master {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ qcom,swr-master-version = <0x01050001>;
+ qcom,swr_master_id = <2>;
+ qcom,mipi-sdw-block-packing-mode = <1>;
+ swrm-io-base = <0x3210000 0x0>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq";
+ qcom,swr-num-ports = <5>;
+ qcom,disable-div2-clk-switch = <1>;
+ qcom,swr-port-mapping = <1 HPH_L 0x1>,
+ <1 HPH_R 0x2>, <2 CLSH 0x1>,
+ <3 COMP_L 0x1>, <3 COMP_R 0x2>,
+ <4 LO 0x1>, <5 DSD_L 0x1>,
+ <5 DSD_R 0x2>;
+ qcom,swr-num-dev = <1>;
+ qcom,swr-clock-stop-mode0 = <1>;
+ wcd938x_rx_slave: wcd938x-rx-slave {
+ compatible = "qcom,wcd938x-slave";
+ reg = <0x0D 0x01170224>;
+ };
+ };
+ };
+
+ wsa_macro: wsa-macro@3240000 {
+ compatible = "qcom,wsa-macro";
+ reg = <0x3240000 0x0>;
+ clock-names = "wsa_core_clk", "wsa_npl_clk";
+ clocks = <&clock_audio_wsa_1 0>,
+ <&clock_audio_wsa_2 0>;
+ qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
+ qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ swr0: wsa_swr_master {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ qcom,swr-master-version = <0x01050001>;
+ qcom,swr_master_id = <1>;
+ qcom,mipi-sdw-block-packing-mode = <0>;
+ swrm-io-base = <0x3250000 0x0>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq";
+ qcom,swr-num-ports = <8>;
+ qcom,swr-port-mapping = <1 SPKR_L 0x1>,
+ <2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
+ <4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
+ <6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
+ <8 SPKR_R_VI 0x3>;
+ qcom,swr-num-dev = <2>;
+ wsa881x_0211: wsa881x@20170211 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x20170211>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+ qcom,bolero-handle = <&bolero>;
+ };
+
+ wsa881x_0212: wsa881x@20170212 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x20170212>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero>;
+ };
+
+ wsa881x_0213: wsa881x@21170213 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x21170213>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+ qcom,bolero-handle = <&bolero>;
+ };
+
+ wsa881x_0214: wsa881x@21170214 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x21170214>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero>;
+ };
+ };
+
+ };
+
+ va_macro: va-macro@3370000 {
+ compatible = "qcom,va-macro";
+ reg = <0x3370000 0x0>;
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+ qcom,va-dmic-sample-rate = <600000>;
+ qcom,va-clk-mux-select = <1>;
+ qcom,va-island-mode-muxsel = <0x033A0000>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ };
+
+ wcd938x_codec: wcd938x-codec {
+ compatible = "qcom,wcd938x-codec";
+ qcom,split-codec = <1>;
+ qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
+ <0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
+ <2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
+ <3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
+ <4 DSD_R 0x2 0 DSD_R>;
+ qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
+ <0 ADC2 0x2 0 ADC2>, <1 ADC3 0x1 0 ADC3>,
+ <1 ADC4 0x2 0 ADC4>, <2 DMIC0 0x1 0 DMIC0>,
+ <2 DMIC1 0x2 0 DMIC1>, <2 MBHC 0x4 0 DMIC2>,
+ <2 DMIC2 0x4 0 DMIC2>, <2 DMIC3 0x8 0 DMIC3>,
+ <3 DMIC4 0x1 0 DMIC4>, <3 DMIC5 0x2 0 DMIC5>,
+ <3 DMIC6 0x4 0 DMIC6>, <3 DMIC7 0x8 0 DMIC7>;
+
+ qcom,wcd-rst-gpio-node = <&wcd938x_rst_gpio>;
+ qcom,rx-slave = <&wcd938x_rx_slave>;
+ qcom,tx-slave = <&wcd938x_tx_slave>;
+
+ cdc-vdd-rxtx-supply = <&S4A>;
+ qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-rxtx-current = <30000>;
+
+ cdc-vddio-supply = <&S4A>;
+ qcom,cdc-vddio-voltage = <1800000 1800000>;
+ qcom,cdc-vddio-current = <30000>;
+
+ cdc-vdd-buck-supply = <&S4A>;
+ qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-buck-current = <650000>;
+
+ cdc-vdd-mic-bias-supply = <&BOB>;
+ qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
+ qcom,cdc-vdd-mic-bias-current = <30000>;
+
+ qcom,cdc-micbias1-mv = <1800>;
+ qcom,cdc-micbias2-mv = <1800>;
+ qcom,cdc-micbias3-mv = <1800>;
+ qcom,cdc-micbias4-mv = <1800>;
+
+ qcom,cdc-static-supplies = "cdc-vdd-rxtx",
+ "cdc-vddio",
+ "cdc-vdd-buck",
+ "cdc-vdd-mic-bias";
+ };
+
+};
+
+&lito_snd {
+ qcom,model = "lito-mtp-snd-card";
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
+ qcom,wcn-btfm = <1>;
+ qcom,ext-disp-audio-rx = <1>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic4",
+ "AMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Analog Mic5",
+ "TX DMIC0", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic0",
+ "TX DMIC1", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic1",
+ "TX DMIC2", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "TX DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "TX DMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "TX DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic4",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA DMIC4", "VA MIC BIAS4",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC0", "VA_SWR_CLK",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_ADC2", "VA_SWR_CLK",
+ "VA SWR_ADC3", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_ADC0", "ADC1_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT",
+ "VA SWR_ADC2", "ADC3_OUTPUT",
+ "VA SWR_ADC3", "ADC4_OUTPUT",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
+ qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
+ qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
+ asoc-codec = <&stub_codec>, <&bolero>, <&ext_disp_audio_codec>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec",
+ "msm-ext-disp-audio-codec-rx";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>,
+ <&wsa881x_0213>, <&wsa881x_0214>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+ "SpkrLeft", "SpkrRight";
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&wcd938x_codec>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>,
+ <&lpi_tlmm>, <&bolero>;
+};
+
+&q6core {
+ cdc_dmic01_gpios: cdc_dmic01_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
+ pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
+ qcom,lpi-gpios;
+ qcom,tlmm-gpio = <121 122>;
+ };
+
+ cdc_dmic23_gpios: cdc_dmic23_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
+ pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
+ qcom,lpi-gpios;
+ qcom,tlmm-gpio = <124>;
+ };
+
+ cdc_dmic45_gpios: cdc_dmic45_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
+ pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
+ qcom,lpi-gpios;
+ qcom,tlmm-gpio = <127 128>;
+ };
+
+ wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
+ pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ rx_swr_gpios: rx_swr_clk_data_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
+ &rx_swr_data1_active>;
+ pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
+ &rx_swr_data1_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ tx_swr_gpios: tx_swr_clk_data_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active
+ &tx_swr_data2_active &tx_swr_data3_active>;
+ pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep
+ &tx_swr_data2_sleep &tx_swr_data3_sleep>;
+ qcom,lpi-gpios;
+ qcom,tlmm-gpio = <115 116 117>;
+ };
+};
+
+&soc {
+ wsa_spkr_en1: wsa_spkr_en1_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ pinctrl-1 = <&spkr_1_sd_n_sleep>;
+ };
+
+ wsa_spkr_en2: wsa_spkr_en2_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&spkr_2_sd_n_active>;
+ pinctrl-1 = <&spkr_2_sd_n_sleep>;
+ };
+
+ wcd938x_rst_gpio: msm_cdc_pinctrl@57 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wcd938x_reset_active>;
+ pinctrl-1 = <&wcd938x_reset_sleep>;
+ };
+
+ clock_audio_wsa_1: wsa_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x309>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_wsa_2: wsa_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_3>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30A>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_rx_1: rx_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
+ qcom,codec-lpass-ext-clk-freq = <22579200>;
+ qcom,codec-lpass-clk-id = <0x30E>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_rx_2: rx_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>;
+ qcom,codec-lpass-ext-clk-freq = <22579200>;
+ qcom,codec-lpass-clk-id = <0x30F>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_tx_1: tx_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30C>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_tx_2: tx_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30D>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_va_1: va_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30B>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_va_2: va_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_8>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x310>;
+ #clock-cells = <1>;
+ };
+};
+
+&va_cdc_dma_0_tx {
+ qcom,msm-dai-is-island-supported = <1>;
+};
+
+&adsp_loader {
+ nvmem-cells = <&adsp_variant>;
+ nvmem-cell-names = "adsp_variant";
+ adsp-fw-names = "adsp2";
+ adsp-fw-bit-values = <0x2>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-audio.dtsi
new file mode 100755
index 0000000..b0c71b6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-audio.dtsi
@@ -0,0 +1,176 @@
+#include <dt-bindings/clock/qcom,audio-ext-clk.h>
+#include "msm-audio-lpass.dtsi"
+
+&msm_audio_ion {
+ iommus = <&apps_smmu 0x1401 0x0>;
+ qcom,smmu-sid-mask = /bits/ 64 <0xf>;
+};
+
+&soc {
+ qcom,avtimer@39f0000 {
+ compatible = "qcom,avtimer";
+ reg = <0x039f000c 0x4>,
+ <0x039f0010 0x4>;
+ reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
+ qcom,clk-div = <192>;
+ qcom,clk-mult = <10>;
+ };
+};
+
+&audio_apr {
+ q6core: qcom,q6core-audio {
+ compatible = "qcom,q6core-audio";
+
+ lpass_core_hw_vote: vote_lpass_core_hw {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_CORE_HW_VOTE>;
+ #clock-cells = <1>;
+ };
+
+ lpass_audio_hw_vote: vote_lpass_audio_hw {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_AUDIO_HW_VOTE>;
+ #clock-cells = <1>;
+ };
+
+ bolero: bolero-cdc {
+ compatible = "qcom,bolero-codec";
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+ bolero-clk-rsc-mngr {
+ compatible = "qcom,bolero-clk-rsc-mngr";
+ };
+
+ tx_macro: tx-macro@3220000 {
+ swr2: tx_swr_master {
+ };
+ };
+
+ rx_macro: rx-macro@3200000 {
+ swr1: rx_swr_master {
+ };
+ };
+
+ wsa_macro: wsa-macro@3240000 {
+ swr0: wsa_swr_master {
+ };
+ };
+ };
+ };
+};
+
+&q6core {
+ lito_snd: sound {
+ compatible = "qcom,kona-asoc-snd";
+ qcom,mi2s-audio-intf = <0>;
+ qcom,auxpcm-audio-intf = <0>;
+ qcom,tdm-audio-intf = <0>;
+ qcom,wcn-btfm = <1>;
+ qcom,ext-disp-audio-rx = <0>;
+ qcom,afe-rxtx-lb = <0>;
+
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+
+ asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
+ <&loopback>, <&compress>, <&hostless>,
+ <&afe>, <&lsm>, <&routing>, <&compr>,
+ <&pcm_noirq>;
+ asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
+ "msm-pcm-dsp.2", "msm-voip-dsp",
+ "msm-pcm-voice", "msm-pcm-loopback",
+ "msm-compress-dsp", "msm-pcm-hostless",
+ "msm-pcm-afe", "msm-lsm-client",
+ "msm-pcm-routing", "msm-compr-dsp",
+ "msm-pcm-dsp-noirq";
+ asoc-cpu = <&dai_dp>, <&dai_dp1>,
+ <&dai_mi2s0>, <&dai_mi2s1>,
+ <&dai_mi2s2>, <&dai_mi2s3>,
+ <&dai_mi2s4>, <&dai_mi2s5>, <&dai_pri_auxpcm>,
+ <&dai_sec_auxpcm>, <&dai_tert_auxpcm>,
+ <&dai_quat_auxpcm>, <&dai_quin_auxpcm>,
+ <&dai_sen_auxpcm>,
+ <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>,
+ <&afe_proxy_tx>, <&incall_record_rx>,
+ <&incall_record_tx>, <&incall_music_rx>,
+ <&incall_music_2_rx>,
+ <&proxy_rx>, <&proxy_tx>,
+ <&usb_audio_rx>, <&usb_audio_tx>,
+ <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>,
+ <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>,
+ <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>,
+ <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>,
+ <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>,
+ <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>,
+ <&dai_sen_tdm_rx_0>, <&dai_sen_tdm_tx_0>,
+ <&wsa_cdc_dma_0_rx>, <&wsa_cdc_dma_0_tx>,
+ <&wsa_cdc_dma_1_rx>, <&wsa_cdc_dma_1_tx>,
+ <&wsa_cdc_dma_2_tx>,
+ <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>,
+ <&va_cdc_dma_2_tx>,
+ <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>,
+ <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>,
+ <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>,
+ <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>,
+ <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>,
+ <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>,
+ <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>,
+ <&afe_loopback_tx>;
+ asoc-cpu-names = "msm-dai-q6-dp.0", "msm-dai-q6-dp.1",
+ "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",
+ "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",
+ "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.5",
+ "msm-dai-q6-auxpcm.1",
+ "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3",
+ "msm-dai-q6-auxpcm.4", "msm-dai-q6-auxpcm.5",
+ "msm-dai-q6-auxpcm.6", "msm-dai-q6-dev.224",
+ "msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
+ "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
+ "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
+ "msm-dai-q6-dev.32770",
+ "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195",
+ "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673",
+ "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399",
+ "msm-dai-q6-dev.16401",
+ "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865",
+ "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881",
+ "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897",
+ "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913",
+ "msm-dai-q6-tdm.36928", "msm-dai-q6-tdm.36929",
+ "msm-dai-q6-tdm.36944", "msm-dai-q6-tdm.36945",
+ "msm-dai-cdc-dma-dev.45056",
+ "msm-dai-cdc-dma-dev.45057",
+ "msm-dai-cdc-dma-dev.45058",
+ "msm-dai-cdc-dma-dev.45059",
+ "msm-dai-cdc-dma-dev.45061",
+ "msm-dai-cdc-dma-dev.45089",
+ "msm-dai-cdc-dma-dev.45091",
+ "msm-dai-cdc-dma-dev.45093",
+ "msm-dai-cdc-dma-dev.45104",
+ "msm-dai-cdc-dma-dev.45105",
+ "msm-dai-cdc-dma-dev.45106",
+ "msm-dai-cdc-dma-dev.45107",
+ "msm-dai-cdc-dma-dev.45108",
+ "msm-dai-cdc-dma-dev.45109",
+ "msm-dai-cdc-dma-dev.45110",
+ "msm-dai-cdc-dma-dev.45111",
+ "msm-dai-cdc-dma-dev.45112",
+ "msm-dai-cdc-dma-dev.45113",
+ "msm-dai-cdc-dma-dev.45114",
+ "msm-dai-cdc-dma-dev.45115",
+ "msm-dai-cdc-dma-dev.45116",
+ "msm-dai-cdc-dma-dev.45118",
+ "msm-dai-q6-dev.24577";
+ fsa4480-i2c-handle = <&fsa4480>;
+ };
+};
+
+&qupv3_se9_i2c {
+ status = "ok";
+ fsa4480: fsa4480@43 {
+ compatible = "qcom,fsa4480-i2c";
+ reg = <0x43>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-bus.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-bus.dtsi
new file mode 100755
index 0000000..b361373
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-bus.dtsi
@@ -0,0 +1,1968 @@
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ ad_hoc_bus: ad-hoc-bus {
+ compatible = "qcom,msm-bus-device";
+ reg = <0x016E0000 0x15080>,
+ <0x1700000 0x23080>,
+ <0x1500000 0x28000>,
+ <0x9160000 0x3200>,
+ <0x9680000 0x3e200>,
+ <0x9680000 0x3e200>,
+ <0x1740000 0x1c100>,
+ <0x1620000 0x19200>,
+ <0x1620000 0x19200>,
+ <0x1700000 0x3d180>,
+ <0x9990000 0x1600>,
+ <0x1620000 0x19200>,
+ <0x1620000 0x19200>;
+
+ reg-names = "aggre1_noc-base", "aggre2_noc-base",
+ "config_noc-base", "dc_noc-base",
+ "mc_virt-base", "gem_noc-base",
+ "mmss_noc-base", "system_noc-base",
+ "ipa_virt-base", "compute_noc-base",
+ "npu_noc-base", "camnoc_virt-base",
+ "qup_virt-base";
+
+ /*RSCs*/
+ rsc_apps: rsc-apps {
+ cell-id = <MSM_BUS_RSC_APPS>;
+ label = "apps_rsc";
+ qcom,rsc-dev;
+ qcom,req_state = <2>;
+ };
+
+ rsc_disp: rsc-disp {
+ cell-id = <MSM_BUS_RSC_DISP>;
+ label = "disp_rsc";
+ qcom,rsc-dev;
+ qcom,req_state = <2>;
+ };
+
+ /*BCMs*/
+ bcm_mc0: bcm-mc0 {
+ cell-id = <MSM_BUS_BCM_MC0>;
+ label = "MC0";
+ qcom,bcm-name = "MC0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh0: bcm-sh0 {
+ cell-id = <MSM_BUS_BCM_SH0>;
+ label = "SH0";
+ qcom,bcm-name = "SH0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_acv: bcm-acv {
+ cell-id = <MSM_BUS_BCM_ACV>;
+ label = "ACV";
+ qcom,bcm-name = "ACV";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_alc: bcm-alc {
+ cell-id = <MSM_BUS_BCM_ALC>;
+ label = "ALC";
+ qcom,bcm-name = "ALC";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm0: bcm-mm0 {
+ cell-id = <MSM_BUS_BCM_MM0>;
+ label = "MM0";
+ qcom,bcm-name = "MM0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_co0: bcm-co0 {
+ cell-id = <MSM_BUS_BCM_CO0>;
+ label = "CO0";
+ qcom,bcm-name = "CO0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_ce0: bcm-ce0 {
+ cell-id = <MSM_BUS_BCM_CE0>;
+ label = "CE0";
+ qcom,bcm-name = "CE0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_ip0: bcm-ip0 {
+ cell-id = <MSM_BUS_BCM_IP0>;
+ label = "IP0";
+ qcom,bcm-name = "IP0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_cn0: bcm-cn0 {
+ cell-id = <MSM_BUS_BCM_CN0>;
+ label = "CN0";
+ qcom,bcm-name = "CN0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm1: bcm-mm1 {
+ cell-id = <MSM_BUS_BCM_MM1>;
+ label = "MM1";
+ qcom,bcm-name = "MM1";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_cn1: bcm-cn1 {
+ cell-id = <MSM_BUS_BCM_CN1>;
+ label = "CN1";
+ qcom,bcm-name = "CN1";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh2: bcm-sh2 {
+ cell-id = <MSM_BUS_BCM_SH2>;
+ label = "SH2";
+ qcom,bcm-name = "SH2";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm2: bcm-mm2 {
+ cell-id = <MSM_BUS_BCM_MM2>;
+ label = "MM2";
+ qcom,bcm-name = "MM2";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_co2: bcm-co2 {
+ cell-id = <MSM_BUS_BCM_CO2>;
+ label = "CO2";
+ qcom,bcm-name = "CO2";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh3: bcm-sh3 {
+ cell-id = <MSM_BUS_BCM_SH3>;
+ label = "SH3";
+ qcom,bcm-name = "SH3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm3: bcm-mm3 {
+ cell-id = <MSM_BUS_BCM_MM3>;
+ label = "MM3";
+ qcom,bcm-name = "MM3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_co3: bcm-co3 {
+ cell-id = <MSM_BUS_BCM_CO3>;
+ label = "CO3";
+ qcom,bcm-name = "CO3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_qup0: bcm-qup0 {
+ cell-id = <MSM_BUS_BCM_QUP0>;
+ label = "QUP0";
+ qcom,bcm-name = "QUP0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh4: bcm-sh4 {
+ cell-id = <MSM_BUS_BCM_SH4>;
+ label = "SH4";
+ qcom,bcm-name = "SH4";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn0: bcm-sn0 {
+ cell-id = <MSM_BUS_BCM_SN0>;
+ label = "SN0";
+ qcom,bcm-name = "SN0";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn1: bcm-sn1 {
+ cell-id = <MSM_BUS_BCM_SN1>;
+ label = "SN1";
+ qcom,bcm-name = "SN1";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn2: bcm-sn2 {
+ cell-id = <MSM_BUS_BCM_SN2>;
+ label = "SN2";
+ qcom,bcm-name = "SN2";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn3: bcm-sn3 {
+ cell-id = <MSM_BUS_BCM_SN3>;
+ label = "SN3";
+ qcom,bcm-name = "SN3";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn4: bcm-sn4 {
+ cell-id = <MSM_BUS_BCM_SN4>;
+ label = "SN4";
+ qcom,bcm-name = "SN4";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn5: bcm-sn5 {
+ cell-id = <MSM_BUS_BCM_SN5>;
+ label = "SN5";
+ qcom,bcm-name = "SN5";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn6: bcm-sn6 {
+ cell-id = <MSM_BUS_BCM_SN6>;
+ label = "SN6";
+ qcom,bcm-name = "SN6";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sn10: bcm-sn10 {
+ cell-id = <MSM_BUS_BCM_SN10>;
+ label = "SN10";
+ qcom,bcm-name = "SN10";
+ qcom,rscs = <&rsc_apps>;
+ qcom,bcm-dev;
+ };
+
+ bcm_acv_display: bcm-acv_display {
+ cell-id = <MSM_BUS_BCM_ACV_DISPLAY>;
+ label = "ACV_DISPLAY";
+ qcom,bcm-name = "ACV";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_alc_display: bcm-alc_display {
+ cell-id = <MSM_BUS_BCM_ALC_DISPLAY>;
+ label = "ALC_DISPLAY";
+ qcom,bcm-name = "ALC";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mc0_display: bcm-mc0_display {
+ cell-id = <MSM_BUS_BCM_MC0_DISPLAY>;
+ label = "MC0_DISPLAY";
+ qcom,bcm-name = "MC0";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_sh0_display: bcm-sh0_display {
+ cell-id = <MSM_BUS_BCM_SH0_DISPLAY>;
+ label = "SH0_DISPLAY";
+ qcom,bcm-name = "SH0";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm0_display: bcm-mm0_display {
+ cell-id = <MSM_BUS_BCM_MM0_DISPLAY>;
+ label = "MM0_DISPLAY";
+ qcom,bcm-name = "MM0";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm1_display: bcm-mm1_display {
+ cell-id = <MSM_BUS_BCM_MM1_DISPLAY>;
+ label = "MM1_DISPLAY";
+ qcom,bcm-name = "MM1";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ bcm_mm2_display: bcm-mm2_display {
+ cell-id = <MSM_BUS_BCM_MM2_DISPLAY>;
+ label = "MM2_DISPLAY";
+ qcom,bcm-name = "MM2";
+ qcom,rscs = <&rsc_disp>;
+ qcom,bcm-dev;
+ };
+
+ /*Buses*/
+ fab_aggre1_noc: fab-aggre1_noc {
+ cell-id = <MSM_BUS_FAB_A1_NOC>;
+ label = "fab-aggre1_noc";
+ qcom,fab-dev;
+ qcom,base-name = "aggre1_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <12288>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_aggre2_noc: fab-aggre2_noc {
+ cell-id = <MSM_BUS_FAB_A2_NOC>;
+ label = "fab-aggre2_noc";
+ qcom,fab-dev;
+ qcom,base-name = "aggre2_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <20480>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_compute_noc: fab-compute_noc {
+ cell-id = <MSM_BUS_FAB_COMP_NOC>;
+ label = "fab-compute_noc";
+ qcom,fab-dev;
+ qcom,base-name = "compute_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <36864>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_config_noc: fab-config_noc {
+ cell-id = <MSM_BUS_FAB_CONFIG_NOC>;
+ label = "fab-config_noc";
+ qcom,fab-dev;
+ qcom,base-name = "config_noc-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_dc_noc: fab-dc_noc {
+ cell-id = <MSM_BUS_FAB_DC_NOC>;
+ label = "fab-dc_noc";
+ qcom,fab-dev;
+ qcom,base-name = "dc_noc-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_gem_noc: fab-gem_noc {
+ cell-id = <MSM_BUS_FAB_GEM_NOC>;
+ label = "fab-gem_noc";
+ qcom,fab-dev;
+ qcom,base-name = "gem_noc-base";
+ qcom,qos-off = <128>;
+ qcom,base-offset = <184320>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_ipa_virt: fab-ipa_virt {
+ cell-id = <MSM_BUS_FAB_IPA_VIRT>;
+ label = "fab-ipa_virt";
+ qcom,fab-dev;
+ qcom,base-name = "ipa_virt-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ clocks = <>;
+ };
+
+ fab_mc_virt: fab-mc_virt {
+ cell-id = <MSM_BUS_FAB_MC_VIRT>;
+ label = "fab-mc_virt";
+ qcom,fab-dev;
+ qcom,base-name = "mc_virt-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ clocks = <>;
+ };
+
+ fab_mmss_noc: fab-mmss_noc {
+ cell-id = <MSM_BUS_FAB_MMSS_NOC>;
+ label = "fab-mmss_noc";
+ qcom,fab-dev;
+ qcom,base-name = "mmss_noc-base";
+ qcom,qos-off = <128>;
+ qcom,base-offset = <36864>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_npu_noc: fab-npu_noc {
+ cell-id = <MSM_BUS_FAB_NPU_NOC>;
+ label = "fab-npu_noc";
+ qcom,fab-dev;
+ qcom,base-name = "npu_noc-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_qup_virt: fab-qup_virt {
+ cell-id = <MSM_BUS_FAB_QUP_VIRT>;
+ label = "fab-qup_virt";
+ qcom,fab-dev;
+ qcom,base-name = "qup_virt-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ clocks = <>;
+ };
+
+ fab_system_noc: fab-system_noc {
+ cell-id = <MSM_BUS_FAB_SYS_NOC>;
+ label = "fab-system_noc";
+ qcom,fab-dev;
+ qcom,base-name = "system_noc-base";
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <49152>;
+ qcom,sbm-offset = <0>;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_gem_noc_display: fab-gem_noc_display {
+ cell-id = <MSM_BUS_FAB_GEM_NOC_DISPLAY>;
+ label = "fab-gem_noc_display";
+ qcom,fab-dev;
+ qcom,base-name = "gem_noc-base";
+ qcom,qos-off = <128>;
+ qcom,base-offset = <184320>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ fab_mc_virt_display: fab-mc_virt_display {
+ cell-id = <MSM_BUS_FAB_MC_VIRT_DISPLAY>;
+ label = "fab-mc_virt_display";
+ qcom,fab-dev;
+ qcom,base-name = "mc_virt-base";
+ qcom,qos-off = <0>;
+ qcom,base-offset = <0>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ clocks = <>;
+ };
+
+ fab_mmss_noc_display: fab-mmss_noc_display {
+ cell-id = <MSM_BUS_FAB_MMSS_NOC_DISPLAY>;
+ label = "fab-mmss_noc_display";
+ qcom,fab-dev;
+ qcom,base-name = "mmss_noc-base";
+ qcom,qos-off = <128>;
+ qcom,base-offset = <36864>;
+ qcom,sbm-offset = <0>;
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clocks = <>;
+ };
+
+ /*Masters*/
+
+ mas_qhm_a1noc_cfg: mas-qhm-a1noc-cfg {
+ cell-id = <MSM_BUS_MASTER_A1NOC_CFG>;
+ label = "mas-qhm-a1noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_aggre1_noc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ };
+
+ mas_qhm_qup_1: mas-qhm-qup-1 {
+ cell-id = <MSM_BUS_MASTER_QUP_1>;
+ label = "mas-qhm-qup-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <6>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_sdc2: mas-xm-sdc2 {
+ cell-id = <MSM_BUS_MASTER_SDCC_2>;
+ label = "mas-xm-sdc2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <2>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,bcms = <&bcm_cn1>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_sdc4: mas-xm-sdc4 {
+ cell-id = <MSM_BUS_MASTER_SDCC_4>;
+ label = "mas-xm-sdc4";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <3>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,bcms = <&bcm_cn1>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_emmc: mas-xm-emmc {
+ cell-id = <MSM_BUS_MASTER_EMMC>;
+ label = "mas-xm-emmc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <4>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,bcms = <&bcm_cn1>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_xm_ufs_mem: mas-xm-ufs-mem {
+ cell-id = <MSM_BUS_MASTER_UFS_MEM>;
+ label = "mas-xm-ufs-mem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <5>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,node-qos-clks {
+ clocks =
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>;
+ clock-names =
+ "clk-aggre-ufs-phy-axi-no-rate";
+ };
+ };
+
+ mas_xm_usb3_0: mas-xm-usb3-0 {
+ cell-id = <MSM_BUS_MASTER_USB3>;
+ label = "mas-xm-usb3-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <0>;
+ qcom,connections = <&slv_qns_a1noc_snoc>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,node-qos-clks {
+ clocks =
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
+ clock-names =
+ "clk-usb3-prim-axi-no-rate";
+ };
+ };
+
+ mas_qhm_a2noc_cfg: mas-qhm-a2noc-cfg {
+ cell-id = <MSM_BUS_MASTER_A2NOC_CFG>;
+ label = "mas-qhm-a2noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_aggre2_noc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ };
+
+ mas_qhm_qdss_bam: mas-qhm-qdss-bam {
+ cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
+ label = "mas-qhm-qdss-bam";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <8>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_qhm_qup_0: mas-qhm-qup-0 {
+ cell-id = <MSM_BUS_MASTER_QUP_0>;
+ label = "mas-qhm-qup-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <0>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_qxm_crypto: mas-qxm-crypto {
+ cell-id = <MSM_BUS_MASTER_CRYPTO_CORE_0>;
+ label = "mas-qxm-crypto";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <1>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,bcms = <&bcm_ce0>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,forwarding;
+ };
+
+ mas_qxm_ipa: mas-qxm-ipa {
+ cell-id = <MSM_BUS_MASTER_IPA>;
+ label = "mas-qxm-ipa";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <2>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,forwarding;
+ qcom,defer-init-qos;
+ qcom,node-qos-bcms = <7035 0 1>;
+ };
+
+ mas_xm_qdss_etr: mas-xm-qdss-etr {
+ cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
+ label = "mas-xm-qdss-etr";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <9>;
+ qcom,connections = <&slv_qns_a2noc_snoc>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_qnm_npu: mas-qnm-npu {
+ cell-id = <MSM_BUS_MASTER_NPU>;
+ label = "mas-qnm-npu";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <6 8>;
+ qcom,connections = <&slv_qns_cdsp_gem_noc>;
+ qcom,bus-dev = <&fab_compute_noc>;
+ qcom,bcms = <&bcm_co2>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_qxm_npu_dsp: mas-qxm-npu-dsp {
+ cell-id = <MSM_BUS_MASTER_NPU_CDP>;
+ label = "mas-qxm-npu-dsp";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <7>;
+ qcom,connections = <&slv_qns_cdsp_gem_noc>;
+ qcom,bus-dev = <&fab_compute_noc>;
+ qcom,bcms = <&bcm_co3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_qnm_snoc: mas-qnm-snoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_MAS>;
+ label = "mas-qnm-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_compute_dsp
+ &slv_qhs_tlmm_2 &slv_qhs_camera_cfg
+ &slv_qhs_tlmm_0 &slv_qhs_sdc4
+ &slv_qhs_sdc2 &slv_qhs_mnoc_cfg
+ &slv_qhs_ufs_mem_cfg &slv_qhs_snoc_cfg
+ &slv_qhs_pdm &slv_qhs_cx_rdpm
+ &slv_qhs_tlmm_1 &slv_qhs_a2_noc_cfg
+ &slv_qhs_qdss_cfg &slv_qhs_display_cfg
+ &slv_qhs_tcsr &slv_qhs_dcc_cfg
+ &slv_qhs_ddrss_cfg &slv_qhs_ipc_router
+ &slv_qhs_ahb2phy2 &slv_qhs_npu_cfg
+ &slv_qhs_ahb2phy0 &slv_qhs_gpuss_cfg
+ &slv_qhs_venus_cfg &slv_qhs_ipa
+ &slv_qhs_imem_cfg &slv_srvc_cnoc
+ &slv_qhs_usb3_0 &slv_qhs_lpass_cfg
+ &slv_qhs_cpr_cx &slv_qhs_a1_noc_cfg
+ &slv_qhs_aoss &slv_qhs_prng
+ &slv_qhs_vsense_ctrl_cfg &slv_qhs_crypto0_cfg
+ &slv_qhs_pimem_cfg &slv_qhs_cpr_mx
+ &slv_qhs_qup0 &slv_qhs_qup1
+ &slv_qhs_clk_ctl &slv_qhs_emmc_cfg>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ mas_xm_qdss_dap: mas-xm-qdss-dap {
+ cell-id = <MSM_BUS_MASTER_QDSS_DAP>;
+ label = "mas-xm-qdss-dap";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_compute_dsp
+ &slv_qhs_tlmm_2 &slv_qhs_camera_cfg
+ &slv_qhs_tlmm_0 &slv_qhs_sdc4
+ &slv_qhs_sdc2 &slv_qhs_mnoc_cfg
+ &slv_qhs_ufs_mem_cfg &slv_qhs_snoc_cfg
+ &slv_qhs_pdm &slv_qhs_cx_rdpm
+ &slv_qhs_tlmm_1 &slv_qhs_a2_noc_cfg
+ &slv_qhs_qdss_cfg &slv_qhs_display_cfg
+ &slv_qhs_tcsr &slv_qhs_dcc_cfg
+ &slv_qhs_ddrss_cfg &slv_qhs_ipc_router
+ &slv_qhs_ahb2phy2 &slv_qhs_npu_cfg
+ &slv_qhs_ahb2phy0 &slv_qhs_gpuss_cfg
+ &slv_qhs_venus_cfg &slv_qhs_ipa
+ &slv_qhs_imem_cfg &slv_srvc_cnoc
+ &slv_qhs_usb3_0 &slv_qhs_lpass_cfg
+ &slv_qhs_cpr_cx &slv_qhs_a1_noc_cfg
+ &slv_qhs_aoss &slv_qhs_prng
+ &slv_qhs_vsense_ctrl_cfg &slv_qhs_crypto0_cfg
+ &slv_qhs_pimem_cfg &slv_qhs_cpr_mx
+ &slv_qhs_qup0 &slv_qhs_qup1
+ &slv_qhs_clk_ctl &slv_qhs_emmc_cfg>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ mas_qhm_cnoc_dc_noc: mas-qhm-cnoc-dc-noc {
+ cell-id = <MSM_BUS_MASTER_CNOC_DC_NOC>;
+ label = "mas-qhm-cnoc-dc-noc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_llcc &slv_qhs_gemnoc>;
+ qcom,bus-dev = <&fab_dc_noc>;
+ };
+
+ mas_acm_apps0: mas-acm-apps0 {
+ cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
+ label = "mas-acm-apps0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,bcms = <&bcm_sh4>;
+ };
+
+ mas_acm_sys_tcu: mas-acm-sys-tcu {
+ cell-id = <MSM_BUS_MASTER_SYS_TCU>;
+ label = "mas-acm-sys-tcu";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <224>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,bcms = <&bcm_sh2>;
+ qcom,ap-owned;
+ qcom,prio = <6>;
+ };
+
+ mas_alm_gpu_tcu: mas-alm-gpu-tcu {
+ cell-id = <MSM_BUS_MASTER_GPU_TCU>;
+ label = "mas-alm-gpu-tcu";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <0>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,bcms = <&bcm_sh2>;
+ qcom,ap-owned;
+ qcom,prio = <1>;
+ };
+
+ mas_qhm_gemnoc_cfg: mas-qhm-gemnoc-cfg {
+ cell-id = <MSM_BUS_MASTER_GEM_NOC_CFG>;
+ label = "mas-qhm-gemnoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qhs_mcdma_ms_mpu_cfg
+ &slv_srvc_gemnoc &slv_qhs_mdsp_ms_mpu_cfg>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ };
+
+ mas_qnm_cmpnoc: mas-qnm-cmpnoc {
+ cell-id = <MSM_BUS_MASTER_COMPUTE_NOC>;
+ label = "mas-qnm-cmpnoc";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,bcms = <&bcm_sh3>;
+ qcom,ap-owned;
+ };
+
+ mas_qnm_gpu: mas-qnm-gpu {
+ cell-id = <MSM_BUS_MASTER_GRAPHICS_3D>;
+ label = "mas-qnm-gpu";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <256 257>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_qnm_mnoc_hf: mas-qnm-mnoc-hf {
+ cell-id = <MSM_BUS_MASTER_MNOC_HF_MEM_NOC>;
+ label = "mas-qnm-mnoc-hf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <128 129>;
+ qcom,connections = <&slv_qns_llcc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qnm_mnoc_sf: mas-qnm-mnoc-sf {
+ cell-id = <MSM_BUS_MASTER_MNOC_SF_MEM_NOC>;
+ label = "mas-qnm-mnoc-sf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <288>;
+ qcom,connections = <&slv_qns_llcc
+ &slv_qns_gem_noc_snoc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qnm_snoc_gc: mas-qnm-snoc-gc {
+ cell-id = <MSM_BUS_MASTER_SNOC_GC_MEM_NOC>;
+ label = "mas-qnm-snoc-gc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <192>;
+ qcom,connections = <&slv_qns_llcc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_qnm_snoc_sf: mas-qnm-snoc-sf {
+ cell-id = <MSM_BUS_MASTER_SNOC_SF_MEM_NOC>;
+ label = "mas-qnm-snoc-sf";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <160>;
+ qcom,connections = <&slv_qns_llcc>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ };
+
+ mas_ipa_core_master: mas-ipa-core-master {
+ cell-id = <MSM_BUS_MASTER_IPA_CORE>;
+ label = "mas-ipa-core-master";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_ipa_core_slave>;
+ qcom,bus-dev = <&fab_ipa_virt>;
+ };
+
+ mas_llcc_mc: mas-llcc-mc {
+ cell-id = <MSM_BUS_MASTER_LLCC>;
+ label = "mas-llcc-mc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,connections = <&slv_ebi>;
+ qcom,bus-dev = <&fab_mc_virt>;
+ };
+
+ mas_qhm_mnoc_cfg: mas-qhm-mnoc-cfg {
+ cell-id = <MSM_BUS_MASTER_CNOC_MNOC_CFG>;
+ label = "mas-qhm-mnoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_mnoc>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ };
+
+ mas_qxm_camnoc_icp: mas-qxm-camnoc-icp {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_ICP>;
+ label = "mas-qxm-camnoc-icp";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <258>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <5>;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qxm_camnoc_hf0: mas-qxm-camnoc-hf0 {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_HF0>;
+ label = "mas-qxm-camnoc-hf0";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <32 64>;
+ qcom,connections = <&slv_qns_mem_noc_hf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm1>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qxm_camnoc_hf1: mas-qxm-camnoc-hf1 {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_HF1>;
+ label = "mas-qxm-camnoc-hf1";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <257>;
+ qcom,connections = <&slv_qns_mem_noc_hf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm1>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qxm_camnoc_sf: mas-qxm-camnoc-sf {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_SF>;
+ label = "mas-qxm-camnoc-sf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <0>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qxm_mdp0: mas-qxm-mdp0 {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT0>;
+ label = "mas-qxm-mdp0";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <96>;
+ qcom,connections = <&slv_qns_mem_noc_hf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm1>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qxm_mdp1: mas-qxm-mdp1 {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT1>;
+ label = "mas-qxm-mdp1";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <128>;
+ qcom,connections = <&slv_qns_mem_noc_hf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm1>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qxm_rot: mas-qxm-rot {
+ cell-id = <MSM_BUS_MASTER_ROTATOR>;
+ label = "mas-qxm-rot";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <160>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qxm_venus0: mas-qxm-venus0 {
+ cell-id = <MSM_BUS_MASTER_VIDEO_P0>;
+ label = "mas-qxm-venus0";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <192>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qxm_venus1: mas-qxm-venus1 {
+ cell-id = <MSM_BUS_MASTER_VIDEO_P1>;
+ label = "mas-qxm-venus1";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <224>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <0>;
+ qcom,forwarding;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_qxm_venus_arm9: mas-qxm-venus-arm9 {
+ cell-id = <MSM_BUS_MASTER_VIDEO_PROC>;
+ label = "mas-qxm-venus-arm9";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <256>;
+ qcom,connections = <&slv_qns_mem_noc_sf>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,bcms = <&bcm_mm3>;
+ qcom,ap-owned;
+ qcom,prio = <5>;
+ qcom,node-qos-bcms = <7012 0 1>;
+ };
+
+ mas_amm_npu_sys: mas-amm-npu-sys {
+ cell-id = <MSM_BUS_MASTER_NPU_SYS>;
+ label = "mas-amm-npu-sys";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,connections = <&slv_qns_npu_sys>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ mas_qhm_cfg: mas-qhm-cfg {
+ cell-id = <MSM_BUS_MASTER_NPU_NOC_CFG>;
+ label = "mas-qhm-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_noc &slv_qhs_isense
+ &slv_qhs_llm &slv_qhs_dma_bwmon &slv_qhs_cp
+ &slv_qhs_tcm &slv_qhs_cal_dp0 &slv_qhs_dpm>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ mas_qup_core_master_1: mas-qup-core-master-1 {
+ cell-id = <MSM_BUS_MASTER_QUP_CORE_0>;
+ label = "mas-qup-core-master-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qup_core_slave_1>;
+ qcom,bus-dev = <&fab_qup_virt>;
+ qcom,bcms = <&bcm_qup0>;
+ };
+
+ mas_qup_core_master_2: mas-qup-core-master-2 {
+ cell-id = <MSM_BUS_MASTER_QUP_CORE_1>;
+ label = "mas-qup-core-master-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qup_core_slave_2>;
+ qcom,bus-dev = <&fab_qup_virt>;
+ qcom,bcms = <&bcm_qup0>;
+ };
+
+ mas_qhm_snoc_cfg: mas-qhm-snoc-cfg {
+ cell-id = <MSM_BUS_MASTER_SNOC_CFG>;
+ label = "mas-qhm-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_snoc>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ mas_qnm_aggre1_noc: mas-qnm-aggre1-noc {
+ cell-id = <MSM_BUS_A1NOC_SNOC_MAS>;
+ label = "mas-qnm-aggre1-noc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_gemnoc_sf &slv_qxs_pimem
+ &slv_qxs_imem &slv_qhs_apss
+ &slv_qns_cnoc &slv_xs_qdss_stm>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn5>;
+ };
+
+ mas_qnm_aggre2_noc: mas-qnm-aggre2-noc {
+ cell-id = <MSM_BUS_A2NOC_SNOC_MAS>;
+ label = "mas-qnm-aggre2-noc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qns_gemnoc_sf &slv_qxs_pimem
+ &slv_qxs_imem &slv_qhs_apss &slv_qns_cnoc
+ &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn6>;
+ };
+
+ mas_qnm_gemnoc: mas-qnm-gemnoc {
+ cell-id = <MSM_BUS_MASTER_GEM_NOC_SNOC>;
+ label = "mas-qnm-gemnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qxs_pimem &slv_qxs_imem
+ &slv_qhs_apss &slv_qns_cnoc
+ &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn10>;
+ };
+
+ mas_qxm_pimem: mas-qxm-pimem {
+ cell-id = <MSM_BUS_MASTER_PIMEM>;
+ label = "mas-qxm-pimem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <1>;
+ qcom,connections = <&slv_qns_gemnoc_gc &slv_qxs_imem>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ };
+
+ mas_qnm_mnoc_hf_display: mas-qnm-mnoc-hf_display {
+ cell-id = <MSM_BUS_MASTER_MNOC_HF_MEM_NOC_DISPLAY>;
+ label = "mas-qnm-mnoc-hf_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,qport = <128 129>;
+ qcom,connections = <&slv_qns_llcc_display>;
+ qcom,bus-dev = <&fab_gem_noc_display>;
+ };
+
+ mas_qnm_mnoc_sf_display: mas-qnm-mnoc-sf_display {
+ cell-id = <MSM_BUS_MASTER_MNOC_SF_MEM_NOC_DISPLAY>;
+ label = "mas-qnm-mnoc-sf_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <288>;
+ qcom,connections = <&slv_qns_llcc_display>;
+ qcom,bus-dev = <&fab_gem_noc_display>;
+ };
+
+ mas_llcc_mc_display: mas-llcc-mc_display {
+ cell-id = <MSM_BUS_MASTER_LLCC_DISPLAY>;
+ label = "mas-llcc-mc_display";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,connections = <&slv_ebi_display>;
+ qcom,bus-dev = <&fab_mc_virt_display>;
+ };
+
+ mas_qxm_mdp0_display: mas-qxm-mdp0_display {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT0_DISPLAY>;
+ label = "mas-qxm-mdp0_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <96>;
+ qcom,connections = <&slv_qns_mem_noc_hf_display>;
+ qcom,bus-dev = <&fab_mmss_noc_display>;
+ qcom,bcms = <&bcm_mm1_display>;
+ };
+
+ mas_qxm_mdp1_display: mas-qxm-mdp1_display {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT1_DISPLAY>;
+ label = "mas-qxm-mdp1_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <128>;
+ qcom,connections = <&slv_qns_mem_noc_hf_display>;
+ qcom,bus-dev = <&fab_mmss_noc_display>;
+ qcom,bcms = <&bcm_mm1_display>;
+ };
+
+ mas_qxm_rot_display: mas-qxm-rot_display {
+ cell-id = <MSM_BUS_MASTER_ROTATOR_DISPLAY>;
+ label = "mas-qxm-rot_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <160>;
+ qcom,connections = <&slv_qns_mem_noc_sf_display>;
+ qcom,bus-dev = <&fab_mmss_noc_display>;
+ };
+
+ /*Slaves*/
+
+ slv_qns_a1noc_snoc:slv-qns-a1noc-snoc {
+ cell-id = <MSM_BUS_A1NOC_SNOC_SLV>;
+ label = "slv-qns-a1noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ qcom,connections = <&mas_qnm_aggre1_noc>;
+ };
+
+ slv_srvc_aggre1_noc:slv-srvc-aggre1-noc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_A1NOC>;
+ label = "slv-srvc-aggre1-noc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_aggre1_noc>;
+ };
+
+ slv_qns_a2noc_snoc:slv-qns-a2noc-snoc {
+ cell-id = <MSM_BUS_A2NOC_SNOC_SLV>;
+ label = "slv-qns-a2noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ qcom,connections = <&mas_qnm_aggre2_noc>;
+ };
+
+ slv_srvc_aggre2_noc:slv-srvc-aggre2-noc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_A2NOC>;
+ label = "slv-srvc-aggre2-noc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_aggre2_noc>;
+ };
+
+ slv_qns_cdsp_gem_noc:slv-qns-cdsp-gem-noc {
+ cell-id = <MSM_BUS_SLAVE_CDSP_GEM_NOC>;
+ label = "slv-qns-cdsp-gem-noc";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_compute_noc>;
+ qcom,connections = <&mas_qnm_cmpnoc>;
+ qcom,bcms = <&bcm_co0>;
+ };
+
+ slv_qhs_a1_noc_cfg:slv-qhs-a1-noc-cfg {
+ cell-id = <MSM_BUS_SLAVE_A1NOC_CFG>;
+ label = "slv-qhs-a1-noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_a1noc_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_a2_noc_cfg:slv-qhs-a2-noc-cfg {
+ cell-id = <MSM_BUS_SLAVE_A2NOC_CFG>;
+ label = "slv-qhs-a2-noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_a2noc_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ahb2phy0:slv-qhs-ahb2phy0 {
+ cell-id = <MSM_BUS_SLAVE_AHB2PHY_SOUTH>;
+ label = "slv-qhs-ahb2phy0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ahb2phy2:slv-qhs-ahb2phy2 {
+ cell-id = <MSM_BUS_SLAVE_AHB2PHY_CENTER>;
+ label = "slv-qhs-ahb2phy2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn1>;
+ };
+
+ slv_qhs_aoss:slv-qhs-aoss {
+ cell-id = <MSM_BUS_SLAVE_AOSS>;
+ label = "slv-qhs-aoss";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_camera_cfg:slv-qhs-camera-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_CFG>;
+ label = "slv-qhs-camera-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_clk_ctl:slv-qhs-clk-ctl {
+ cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
+ label = "slv-qhs-clk-ctl";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_compute_dsp:slv-qhs-compute-dsp {
+ cell-id = <MSM_BUS_SLAVE_CDSP_CFG>;
+ label = "slv-qhs-compute-dsp";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_cpr_cx:slv-qhs-cpr-cx {
+ cell-id = <MSM_BUS_SLAVE_RBCPR_CX_CFG>;
+ label = "slv-qhs-cpr-cx";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_cpr_mx:slv-qhs-cpr-mx {
+ cell-id = <MSM_BUS_SLAVE_RBCPR_MX_CFG>;
+ label = "slv-qhs-cpr-mx";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_crypto0_cfg:slv-qhs-crypto0-cfg {
+ cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>;
+ label = "slv-qhs-crypto0-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_cx_rdpm:slv-qhs-cx-rdpm {
+ cell-id = <MSM_BUS_SLAVE_CX_RDPM>;
+ label = "slv-qhs-cx-rdpm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_dcc_cfg:slv-qhs-dcc-cfg {
+ cell-id = <MSM_BUS_SLAVE_DCC_CFG>;
+ label = "slv-qhs-dcc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ddrss_cfg:slv-qhs-ddrss-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_DDRSS>;
+ label = "slv-qhs-ddrss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_cnoc_dc_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_display_cfg:slv-qhs-display-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_CFG>;
+ label = "slv-qhs-display-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_gpuss_cfg:slv-qhs-gpuss-cfg {
+ cell-id = <MSM_BUS_SLAVE_GRAPHICS_3D_CFG>;
+ label = "slv-qhs-gpuss-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_imem_cfg:slv-qhs-imem-cfg {
+ cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
+ label = "slv-qhs-imem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ipa:slv-qhs-ipa {
+ cell-id = <MSM_BUS_SLAVE_IPA_CFG>;
+ label = "slv-qhs-ipa";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ipc_router:slv-qhs-ipc-router {
+ cell-id = <MSM_BUS_SLAVE_IPC_ROUTER_CFG>;
+ label = "slv-qhs-ipc-router";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_lpass_cfg:slv-qhs-lpass-cfg {
+ cell-id = <MSM_BUS_SLAVE_LPASS>;
+ label = "slv-qhs-lpass-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_mnoc_cfg:slv-qhs-mnoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_MNOC_CFG>;
+ label = "slv-qhs-mnoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_mnoc_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_npu_cfg:slv-qhs-npu-cfg {
+ cell-id = <MSM_BUS_SLAVE_NPU_CFG>;
+ label = "slv-qhs-npu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_pdm:slv-qhs-pdm {
+ cell-id = <MSM_BUS_SLAVE_PDM>;
+ label = "slv-qhs-pdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn1>;
+ };
+
+ slv_qhs_pimem_cfg:slv-qhs-pimem-cfg {
+ cell-id = <MSM_BUS_SLAVE_PIMEM_CFG>;
+ label = "slv-qhs-pimem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_prng:slv-qhs-prng {
+ cell-id = <MSM_BUS_SLAVE_PRNG>;
+ label = "slv-qhs-prng";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_qdss_cfg:slv-qhs-qdss-cfg {
+ cell-id = <MSM_BUS_SLAVE_QDSS_CFG>;
+ label = "slv-qhs-qdss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_qup0:slv-qhs-qup0 {
+ cell-id = <MSM_BUS_SLAVE_QUP_0>;
+ label = "slv-qhs-qup0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_qup1:slv-qhs-qup1 {
+ cell-id = <MSM_BUS_SLAVE_QUP_1>;
+ label = "slv-qhs-qup1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_sdc2:slv-qhs-sdc2 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_2>;
+ label = "slv-qhs-sdc2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn1>;
+ };
+
+ slv_qhs_sdc4:slv-qhs-sdc4 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_4>;
+ label = "slv-qhs-sdc4";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn1>;
+ };
+
+ slv_qhs_snoc_cfg:slv-qhs-snoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
+ label = "slv-qhs-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_qhm_snoc_cfg>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_tcsr:slv-qhs-tcsr {
+ cell-id = <MSM_BUS_SLAVE_TCSR>;
+ label = "slv-qhs-tcsr";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_tlmm_0:slv-qhs-tlmm-0 {
+ cell-id = <MSM_BUS_SLAVE_TLMM_NORTH>;
+ label = "slv-qhs-tlmm-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_tlmm_1:slv-qhs-tlmm-1 {
+ cell-id = <MSM_BUS_SLAVE_TLMM_SOUTH>;
+ label = "slv-qhs-tlmm-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_tlmm_2:slv-qhs-tlmm-2 {
+ cell-id = <MSM_BUS_SLAVE_TLMM_WEST>;
+ label = "slv-qhs-tlmm-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_ufs_mem_cfg:slv-qhs-ufs-mem-cfg {
+ cell-id = <MSM_BUS_SLAVE_UFS_MEM_CFG>;
+ label = "slv-qhs-ufs-mem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_emmc_cfg:slv-qhs-emmc-cfg {
+ cell-id = <MSM_BUS_SLAVE_EMMC_CFG>;
+ label = "slv-qhs-emmc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn1>;
+ };
+
+ slv_qhs_usb3_0:slv-qhs-usb3-0 {
+ cell-id = <MSM_BUS_SLAVE_USB3>;
+ label = "slv-qhs-usb3-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_venus_cfg:slv-qhs-venus-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_CFG>;
+ label = "slv-qhs-venus-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_vsense_ctrl_cfg:slv-qhs-vsense-ctrl-cfg {
+ cell-id = <MSM_BUS_SLAVE_VSENSE_CTRL_CFG>;
+ label = "slv-qhs-vsense-ctrl-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_srvc_cnoc:slv-srvc-cnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_CNOC>;
+ label = "slv-srvc-cnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,bcms = <&bcm_cn0>;
+ };
+
+ slv_qhs_gemnoc:slv-qhs-gemnoc {
+ cell-id = <MSM_BUS_SLAVE_GEM_NOC_CFG>;
+ label = "slv-qhs-gemnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_dc_noc>;
+ qcom,connections = <&mas_qhm_gemnoc_cfg>;
+ };
+
+ slv_qhs_llcc:slv-qhs-llcc {
+ cell-id = <MSM_BUS_SLAVE_LLCC_CFG>;
+ label = "slv-qhs-llcc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_dc_noc>;
+ };
+
+ slv_qhs_mcdma_ms_mpu_cfg:slv-qhs-mcdma-ms-mpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_MCDMA_MS_MPU_CFG>;
+ label = "slv-qhs-mcdma-ms-mpu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ };
+
+ slv_qhs_mdsp_ms_mpu_cfg:slv-qhs-mdsp-ms-mpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_MSS_PROC_MS_MPU_CFG>;
+ label = "slv-qhs-mdsp-ms-mpu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ };
+
+ slv_qns_gem_noc_snoc:slv-qns-gem-noc-snoc {
+ cell-id = <MSM_BUS_SLAVE_GEM_NOC_SNOC>;
+ label = "slv-qns-gem-noc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,connections = <&mas_qnm_gemnoc>;
+ };
+
+ slv_qns_llcc:slv-qns-llcc {
+ cell-id = <MSM_BUS_SLAVE_LLCC>;
+ label = "slv-qns-llcc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ qcom,connections = <&mas_llcc_mc>;
+ qcom,bcms = <&bcm_sh0>;
+ };
+
+ slv_srvc_gemnoc:slv-srvc-gemnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_GEM_NOC>;
+ label = "slv-srvc-gemnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_gem_noc>;
+ };
+
+ slv_ipa_core_slave:slv-ipa-core-slave {
+ cell-id = <MSM_BUS_SLAVE_IPA_CORE>;
+ label = "slv-ipa-core-slave";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_ipa_virt>;
+ qcom,bcms = <&bcm_ip0>;
+ };
+
+ slv_ebi:slv-ebi {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ label = "slv-ebi";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_mc_virt>;
+ qcom,bcms = <&bcm_mc0>, <&bcm_acv>;
+ };
+
+ slv_qns_mem_noc_hf:slv-qns-mem-noc-hf {
+ cell-id = <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>;
+ label = "slv-qns-mem-noc-hf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,connections = <&mas_qnm_mnoc_hf>;
+ qcom,bcms = <&bcm_mm0>;
+ };
+
+ slv_qns_mem_noc_sf:slv-qns-mem-noc-sf {
+ cell-id = <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>;
+ label = "slv-qns-mem-noc-sf";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ qcom,connections = <&mas_qnm_mnoc_sf>;
+ qcom,bcms = <&bcm_mm2>;
+ };
+
+ slv_srvc_mnoc:slv-srvc-mnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_MNOC>;
+ label = "slv-srvc-mnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mmss_noc>;
+ };
+
+ slv_qhs_cal_dp0:slv-qhs-cal-dp0 {
+ cell-id = <MSM_BUS_SLAVE_NPU_CAL_DP0>;
+ label = "slv-qhs-cal-dp0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_cp:slv-qhs-cp {
+ cell-id = <MSM_BUS_SLAVE_NPU_CP>;
+ label = "slv-qhs-cp";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_dma_bwmon:slv-qhs-dma-bwmon {
+ cell-id = <MSM_BUS_SLAVE_NPU_INT_DMA_BWMON_CFG>;
+ label = "slv-qhs-dma-bwmon";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_dpm:slv-qhs-dpm {
+ cell-id = <MSM_BUS_SLAVE_NPU_DPM>;
+ label = "slv-qhs-dpm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_isense:slv-qhs-isense {
+ cell-id = <MSM_BUS_SLAVE_ISENSE_CFG>;
+ label = "slv-qhs-isense";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_llm:slv-qhs-llm {
+ cell-id = <MSM_BUS_SLAVE_NPU_LLM_CFG>;
+ label = "slv-qhs-llm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qhs_tcm:slv-qhs-tcm {
+ cell-id = <MSM_BUS_SLAVE_NPU_TCM>;
+ label = "slv-qhs-tcm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qns_npu_sys:slv-qns-npu-sys {
+ cell-id = <MSM_BUS_SLAVE_NPU_COMPUTE_NOC>;
+ label = "slv-qns-npu-sys";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_srvc_noc:slv-srvc-noc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_NPU_NOC>;
+ label = "slv-srvc-noc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_npu_noc>;
+ };
+
+ slv_qup_core_slave_1:slv-qup-core-slave-1 {
+ cell-id = <MSM_BUS_SLAVE_QUP_CORE_0>;
+ label = "slv-qup-core-slave-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_qup_virt>;
+ };
+
+ slv_qup_core_slave_2:slv-qup-core-slave-2 {
+ cell-id = <MSM_BUS_SLAVE_QUP_CORE_1>;
+ label = "slv-qup-core-slave-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_qup_virt>;
+ };
+
+ slv_qhs_apss:slv-qhs-apss {
+ cell-id = <MSM_BUS_SLAVE_APPSS>;
+ label = "slv-qhs-apss";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ slv_qns_cnoc:slv-qns-cnoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_SLV>;
+ label = "slv-qns-cnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_snoc>;
+ };
+
+ slv_qns_gemnoc_gc:slv-qns-gemnoc-gc {
+ cell-id = <MSM_BUS_SLAVE_SNOC_GEM_NOC_GC>;
+ label = "slv-qns-gemnoc-gc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_snoc_gc>;
+ qcom,bcms = <&bcm_sn2>;
+ };
+
+ slv_qns_gemnoc_sf:slv-qns-gemnoc-sf {
+ cell-id = <MSM_BUS_SLAVE_SNOC_GEM_NOC_SF>;
+ label = "slv-qns-gemnoc-sf";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,connections = <&mas_qnm_snoc_sf>;
+ qcom,bcms = <&bcm_sn0>;
+ };
+
+ slv_qxs_imem:slv-qxs-imem {
+ cell-id = <MSM_BUS_SLAVE_OCIMEM>;
+ label = "slv-qxs-imem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn1>;
+ };
+
+ slv_qxs_pimem:slv-qxs-pimem {
+ cell-id = <MSM_BUS_SLAVE_PIMEM>;
+ label = "slv-qxs-pimem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn3>;
+ };
+
+ slv_srvc_snoc:slv-srvc-snoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_SNOC>;
+ label = "slv-srvc-snoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ slv_xs_qdss_stm:slv-xs-qdss-stm {
+ cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
+ label = "slv-xs-qdss-stm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ qcom,bcms = <&bcm_sn4>;
+ };
+
+ slv_xs_sys_tcu_cfg:slv-xs-sys-tcu-cfg {
+ cell-id = <MSM_BUS_SLAVE_TCU>;
+ label = "slv-xs-sys-tcu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_system_noc>;
+ };
+
+ slv_qns_llcc_display:slv-qns-llcc_display {
+ cell-id = <MSM_BUS_SLAVE_LLCC_DISPLAY>;
+ label = "slv-qns-llcc_display";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_gem_noc_display>;
+ qcom,connections = <&mas_llcc_mc_display>;
+ qcom,bcms = <&bcm_sh0_display>;
+ };
+
+ slv_ebi_display:slv-ebi_display {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0_DISPLAY>;
+ label = "slv-ebi_display";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_mc_virt_display>;
+ qcom,bcms = <&bcm_mc0_display>, <&bcm_acv_display>;
+ };
+
+ slv_qns_mem_noc_hf_display:slv-qns-mem-noc-hf_display {
+ cell-id = <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC_DISPLAY>;
+ label = "slv-qns-mem-noc-hf_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_mmss_noc_display>;
+ qcom,connections = <&mas_qnm_mnoc_hf_display>;
+ qcom,bcms = <&bcm_mm0_display>;
+ };
+
+ slv_qns_mem_noc_sf_display:slv-qns-mem-noc-sf_display {
+ cell-id = <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC_DISPLAY>;
+ label = "slv-qns-mem-noc-sf_display";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_mmss_noc_display>;
+ qcom,connections = <&mas_qnm_mnoc_sf_display>;
+ qcom,bcms = <&bcm_mm2_display>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-cdp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lito-cdp-overlay.dts
new file mode 100755
index 0000000..eefff2d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-cdp-overlay.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lito-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito CDP";
+ compatible = "qcom,lito-cdp", "qcom,lito", "qcom,cdp";
+ qcom,msm-id = <400 0x10000>, <440 0x10000>;
+ qcom,board-id = <1 0>;
+};
+
+&ufsphy_mem {
+ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/lito-cdp.dts
new file mode 100755
index 0000000..22526f0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-cdp.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+#include "lito.dtsi"
+#include "lito-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito CDP";
+ compatible = "qcom,lito-cdp", "qcom,lito", "qcom,cdp";
+ qcom,board-id = <1 0>;
+};
+
+&ufsphy_mem {
+ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-cdp.dtsi
new file mode 100755
index 0000000..c923cee
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-cdp.dtsi
@@ -0,0 +1,591 @@
+#include <dt-bindings/gpio/gpio.h>
+#include "lito-audio-overlay.dtsi"
+#include "lito-pmic-overlay.dtsi"
+#include "camera/lito-camera-sensor-cdp.dtsi"
+#include "lito-sde-display.dtsi"
+#include "lito-thermal-overlay.dtsi"
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm8150l_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+
+ vdda_usb_ss_dp_core: vdda_usb_ss_dp_core {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_supply";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ enable-active-high;
+ gpio = <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_eldo13>;
+ };
+};
+
+&usb_qmp_dp_phy {
+ vdd-supply = <&vdda_usb_ss_dp_core>;
+};
+
+&sde_dp {
+ vdda-0p9-supply = <&vdda_usb_ss_dp_core>;
+};
+
+&pm7250b_vadc {
+ pinctrl-0 = <
+ &bmr_w_therm_default
+ &camera_therm_default
+ &bmr_s_therm_default
+ >;
+
+ bmr_s_therm {
+ reg = <ADC_GPIO3_PU2>;
+ label = "bmr_s_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm7250b_gpios {
+ bmr_s_therm {
+ bmr_s_therm_default: bmr_s_therm_default {
+ pins = "gpio5";
+ bias-high-impedance;
+ };
+ };
+};
+
+&pm7250b_adc_tm {
+ io-channels = <&pm7250b_vadc ADC_AMUX_THM1_PU2>,
+ <&pm7250b_vadc ADC_GPIO2_PU2>,
+ <&pm7250b_vadc ADC_GPIO3_PU2>,
+ <&pm7250b_vadc ADC_GPIO4_PU2>;
+
+ bmr_s_therm@54 {
+ reg = <ADC_GPIO3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&thermal_zones {
+ mmw-pa4-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm7250b_adc_tm ADC_GPIO3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&qupv3_se0_i2c {
+ status = "ok";
+ qcom,clk-freq-out = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 34 0x00>;
+ qcom,nq-ven = <&tlmm 12 0x00>;
+ qcom,nq-firm = <&tlmm 35 0x00>;
+ qcom,nq-clkreq = <&tlmm 31 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <34 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&lito_snd {
+ qcom,model = "lito-cdp-snd-card";
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic4",
+ "AMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Analog Mic5",
+ "TX DMIC0", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic0",
+ "TX DMIC1", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic1",
+ "TX DMIC2", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "TX DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "TX DMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "TX DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "DMIC1", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic0",
+ "DMIC2", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic1",
+ "DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "DMIC4", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "DMIC6", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "DMIC7", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic6",
+ "DMIC8", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic7",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrLeft IN", "WSA_SPK1 OUT",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic4",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA DMIC4", "VA MIC BIAS4",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC0", "VA_SWR_CLK",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_ADC2", "VA_SWR_CLK",
+ "VA SWR_ADC3", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_ADC0", "ADC1_OUTPUT",
+ "VA SWR_ADC1", "ADC2_OUTPUT",
+ "VA SWR_ADC2", "ADC3_OUTPUT",
+ "VA SWR_ADC3", "ADC4_OUTPUT",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT";
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v4-lito";
+
+ vdda-phy-supply = <&pm8150_l5>;
+ vdda-pll-supply = <&pm8150_l9>;
+ vdda-phy-max-microamp = <90200>;
+ vdda-pll-max-microamp = <19000>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm8150a_l7>;
+ vcc-voltage-level = <2950000 2960000>;
+ vccq2-supply = <&pm8150_s4>;
+ vcc-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+ vccq2-min-microamp = <0>;
+
+ qcom,vddp-ref-clk-supply = <&pm8150_l9>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vddp-ref-clk-min-microamp = <0>;
+ qcom,vddp-ref-clk-min-uV = <1152000>;
+ qcom,vddp-ref-clk-max-uV = <1200000>;
+ status = "ok";
+};
+
+&sdhc_1 {
+ vdd-supply = <&pm8150a_l7>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&pm8150_s4>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&pm8150a_l9>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&pm8150a_l6>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&pm8150a_amoled {
+ status = "ok";
+};
+
+&pm7250b_charger {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+ <&pm7250b_vadc ADC_USB_IN_I>,
+ <&pm7250b_vadc ADC_CHG_TEMP>,
+ <&pm7250b_vadc ADC_DIE_TEMP>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+ <&pm7250b_vadc ADC_SBUx>,
+ <&pm7250b_vadc ADC_VPH_PWR>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp",
+ "die_temp",
+ "conn_temp",
+ "sbux_res",
+ "vph_voltage";
+ qcom,batteryless-platform;
+ qcom,sec-charger-config = <1>;
+ qcom,auto-recharge-soc = <98>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ qcom,suspend-input-on-debug-batt;
+};
+
+&pm7250b_qg {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU2>,
+ <&pm7250b_vadc ADC_BAT_ID_PU2>;
+ io-channel-names = "batt-therm",
+ "batt-id";
+ qcom,qg-iterm-ma = <100>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+};
+
+&qupv3_se7_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "ok";
+ qcom,i2c-touch-active = "st,fts";
+
+ st_fts@49 {
+ compatible = "st,fts";
+ reg = <0x49>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 0x2008>;
+ vdd-supply = <&pm8150_s4>;
+ avdd-supply = <&pm8150_l13>;
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ st,irq-gpio = <&tlmm 9 0x2008>;
+ st,reset-gpio = <&tlmm 8 0x00>;
+ st,regulator_dvdd = "vdd";
+ st,regulator_avdd = "avdd";
+ panel = <&dsi_sw43404_amoled_cmd &dsi_sw43404_amoled_video
+ &dsi_sw43404_amoled_fhd_plus_cmd>;
+ };
+
+ synaptics_dsx@22 {
+ compatible = "synaptics,dsx-i2c";
+ reg = <0x22>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <39 0x2008>;
+ vdd-supply = <&pm8150_s4>;
+ avdd-supply = <&pm8150_l13>;
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&pmx_ts_release>;
+ synaptics,pwr-reg-name = "avdd";
+ synaptics,bus-reg-name = "vdd";
+ synaptics,ub-i2c-addr = <0x22>;
+ synaptics,max-y-for-2d = <1859>;
+ synaptics,irq-gpio = <&tlmm 9 0x2008>;
+ synaptics,reset-gpio = <&tlmm 8 0x0>;
+ synaptics,irq-on-state = <0>;
+ synaptics,power-delay-ms = <200>;
+ synaptics,reset-delay-ms = <200>;
+ synaptics,reset-on-state = <0>;
+ synaptics,reset-active-ms = <20>;
+
+ panel = <&dsi_sharp_qsync_wqhd_cmd &dsi_sharp_qsync_wqhd_video
+ &dsi_sharp_qsync_fhd_video &dsi_sharp_qsync_fhd_cmd>;
+ };
+
+ focaltech@38 {
+ compatible = "focaltech,fts_ts";
+ reg = <0x38>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <39 0x2008>;
+ focaltech,irq-gpio = <&tlmm 9 0x2008>;
+ focaltech,reset-gpio = <&tlmm 8 0x00>;
+ focaltech,max-touch-number = <5>;
+ focaltech,display-coords = <0 0 1080 2340>;
+
+ vdd-supply = <&pm8150_l13>;
+
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&pmx_ts_release>;
+
+ panel = <&dsi_r66451_amoled_144hz_cmd>;
+ };
+
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_dual_sharp_wqhd_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+ qcom,platform-en-gpio = <&pm8150l_gpios 9 0>;
+ qcom,platform-bklight-en-gpio = <&pm8150l_gpios 10 0>;
+};
+
+&dsi_dual_sharp_wqhd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+ qcom,platform-en-gpio = <&pm8150l_gpios 9 0>;
+ qcom,platform-bklight-en-gpio = <&pm8150l_gpios 10 0>;
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+ qcom,platform-en-gpio = <&pm8150l_gpios 9 0>;
+ qcom,platform-bklight-en-gpio = <&pm8150l_gpios 10 0>;
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+ qcom,platform-en-gpio = <&pm8150l_gpios 9 0>;
+ qcom,platform-bklight-en-gpio = <&pm8150l_gpios 10 0>;
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+ qcom,platform-sec-reset-gpio = <&pm8150l_gpios 11 0>;
+ qcom,platform-en-gpio = <&pm8150l_gpios 9 0>;
+ qcom,platform-bklight-en-gpio = <&pm8150l_gpios 10 0>;
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,panel-sec-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-sec-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+ qcom,platform-sec-reset-gpio = <&pm8150l_gpios 11 0>;
+ qcom,platform-en-gpio = <&pm8150l_gpios 9 0>;
+ qcom,platform-bklight-en-gpio = <&pm8150l_gpios 10 0>;
+};
+
+&dsi_sharp_qsync_wqhd_video {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+ qcom,platform-en-gpio = <&pm8150l_gpios 9 0>;
+ qcom,platform-bklight-en-gpio = <&pm8150l_gpios 10 0>;
+};
+
+&dsi_sharp_qsync_wqhd_cmd {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+ qcom,platform-en-gpio = <&pm8150l_gpios 9 0>;
+ qcom,platform-bklight-en-gpio = <&pm8150l_gpios 10 0>;
+};
+
+&dsi_sharp_qsync_fhd_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+ qcom,platform-en-gpio = <&pm8150l_gpios 9 0>;
+ qcom,platform-bklight-en-gpio = <&pm8150l_gpios 10 0>;
+};
+
+&dsi_sharp_qsync_fhd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_external";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+ qcom,platform-en-gpio = <&pm8150l_gpios 9 0>;
+ qcom,platform-bklight-en-gpio = <&pm8150l_gpios 10 0>;
+
+};
+
+&dsi_rm69299_visionox_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_r66451_amoled_144hz_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,mdss-dsi-bl-inverted-dbv;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_video>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-coresight.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-coresight.dtsi
new file mode 100755
index 0000000..8edd526
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-coresight.dtsi
@@ -0,0 +1,3363 @@
+&soc {
+ replicator_qdss: replicator@6046000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+
+ reg = <0x6046000 0x1000>;
+ reg-names = "replicator-base";
+
+ coresight-name = "coresight-replicator-qdss";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ replicator0_out_tmc_etr: endpoint {
+ remote-endpoint=
+ <&tmc_etr_in_replicator0>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ replicator_cx_in_swao_out: endpoint {
+ slave-mode;
+ remote-endpoint=
+ <&replicator_swao_out_cx_in>;
+ };
+ };
+ };
+ };
+
+ replicator_swao: replicator@6b06000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+
+ reg = <0x6b06000 0x1000>;
+ reg-names = "replicator-base";
+
+ coresight-name = "coresight-replicator-swao";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Always have EUD before funnel leading to ETR. If both
+ * sink are active we need to give preference to EUD
+ * over ETR
+ */
+ port@0 {
+ reg = <1>;
+ replicator_swao_out_eud: endpoint {
+ remote-endpoint =
+ <&eud_in_replicator_swao>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ replicator_swao_out_cx_in: endpoint {
+ remote-endpoint =
+ <&replicator_cx_in_swao_out>;
+ };
+ };
+
+ port@2 {
+ reg = <0>;
+ replicator_swao_in_tmc_etf_swao: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tmc_etf_swao_out_replicator_swao>;
+ };
+ };
+ };
+ };
+
+ dummy_eud: dummy_sink {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-eud";
+
+ qcom,dummy-sink;
+ port {
+ eud_in_replicator_swao: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&replicator_swao_out_eud>;
+ };
+ };
+ };
+
+ tmc_etf_swao: tmc@6b05000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+
+ reg = <0x6b05000 0x1000>;
+ reg-names = "tmc-base";
+
+ coresight-name = "coresight-tmc-etf";
+ coresight-ctis = <&cti0_swao &cti3_swao>;
+ coresight-csr = <&swao_csr>;
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ tmc_etf_swao_out_replicator_swao: endpoint {
+ remote-endpoint=
+ <&replicator_swao_in_tmc_etf_swao>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tmc_etf_swao_in_funnel_swao: endpoint {
+ slave-mode;
+ remote-endpoint=
+ <&funnel_swao_out_tmc_etf_swao>;
+ };
+ };
+ };
+ };
+
+ funnel_swao: funnel@6b04000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6b04000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-swao";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_swao_out_tmc_etf_swao: endpoint {
+ remote-endpoint =
+ <&tmc_etf_swao_in_funnel_swao>;
+ };
+ };
+
+ port@1 {
+ reg = <5>;
+ funnel_swao_in_audio_etm0: endpoint {
+ slave-mode;
+ remote-endpoint=
+ <&audio_etm0_out_funnel_swao>;
+ };
+ };
+
+ port@2 {
+ reg = <5>;
+ funnel_swao_in_lpass_lpi: endpoint {
+ slave-mode;
+ remote-endpoint=
+ <&lpass_lpi_out_funnel_swao>;
+ };
+ };
+
+ port@3 {
+ reg = <6>;
+ funnel_swao_in_tpda_swao: endpoint {
+ slave-mode;
+ remote-endpoint=
+ <&tpda_swao_out_funnel_swao>;
+ };
+ };
+
+ port@4 {
+ reg = <7>;
+ funnel_swao_in_funnel_merg: endpoint {
+ slave-mode;
+ remote-endpoint=
+ <&funnel_merg_out_funnel_swao>;
+ };
+ };
+ };
+ };
+
+ tpda_swao: tpda@6b08000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x6b08000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-swao";
+
+ qcom,tpda-atid = <71>;
+ qcom,dsb-elem-size = <1 32>;
+ qcom,cmb-elem-size = <0 64>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ tpda_swao_out_funnel_swao: endpoint {
+ remote-endpoint =
+ <&funnel_swao_in_tpda_swao>;
+ };
+
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_swao_in_tpdm_swao0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_swao0_out_tpda_swao>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ tpda_swao_in_tpdm_swao1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_swao1_out_tpda_swao>;
+ };
+ };
+ };
+ };
+
+ tpdm_swao0: tpdm@6b09000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+
+ reg = <0x6b09000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-swao-0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_swao0_out_tpda_swao: endpoint {
+ remote-endpoint = <&tpda_swao_in_tpdm_swao0>;
+ };
+ };
+ };
+
+ tpdm_swao1: tpdm@6b0a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6b0a000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name="coresight-tpdm-swao-1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_swao1_out_tpda_swao: endpoint {
+ remote-endpoint = <&tpda_swao_in_tpdm_swao1>;
+ };
+ };
+ };
+
+ tmc_etr: tmc@6048000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+
+ reg = <0x6048000 0x1000>,
+ <0x6064000 0x15000>;
+ reg-names = "tmc-base", "bam-base";
+
+ qcom,iommu-dma = "bypass";
+ iommus = <&apps_smmu 0x04c0 0>,
+ <&apps_smmu 0x04a0 0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ arm,buffer-size = <0x400000>;
+ arm,scatter-gather;
+
+ qcom,sw-usb;
+ coresight-name = "coresight-tmc-etr";
+ coresight-ctis = <&cti0 &cti3_swao>;
+ coresight-csr = <&csr>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "byte-cntr-irq";
+
+ port {
+ tmc_etr_in_replicator0: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator0_out_tmc_etr>;
+ };
+ };
+ };
+
+ funnel_merg: funnel@6045000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6045000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-merg";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_merg_out_funnel_swao: endpoint {
+ remote-endpoint =
+ <&funnel_swao_in_funnel_merg>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_merg_in_funnel_in0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_in0_out_funnel_merg>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_merg_in_funnel_in1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_in1_out_funnel_merg>;
+ };
+ };
+ };
+ };
+
+ stm: stm@6002000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb962>;
+
+ reg = <0x6002000 0x1000>,
+ <0x16280000 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ coresight-name = "coresight-stm";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ nvmem-cells = <&stm_debug_fuse>;
+ nvmem-cell-names = "debug_fuse";
+
+ port {
+ stm_out_funnel_in0: endpoint {
+ remote-endpoint = <&funnel_in0_in_stm>;
+ };
+ };
+ };
+
+ csr: csr@6001000 {
+ compatible = "qcom,coresight-csr";
+ reg = <0x6001000 0x1000>;
+ reg-names = "csr-base";
+
+ coresight-name = "coresight-csr";
+ qcom,usb-bam-support;
+ qcom,hwctrl-set-support;
+ qcom,set-byte-cntr-support;
+
+ qcom,blk-size = <1>;
+ };
+
+ swao_csr: csr@6b0c000 {
+ compatible = "qcom,coresight-csr";
+ reg = <0x6b0c000 0x1000>;
+ reg-names = "csr-base";
+
+ coresight-name = "coresight-swao-csr";
+ qcom,timestamp-support;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,blk-size = <1>;
+ };
+
+ funnel_in0: funnel@6041000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6041000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-in0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_in0_out_funnel_merg: endpoint {
+ remote-endpoint =
+ <&funnel_merg_in_funnel_in0>;
+ };
+ };
+
+ port@1 {
+ reg = <6>;
+ funnel_in0_in_funnel_qatb: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_qatb_out_funnel_in0>;
+ };
+ };
+
+ port@2 {
+ reg = <7>;
+ funnel_in0_in_stm: endpoint {
+ slave-mode;
+ remote-endpoint = <&stm_out_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel_qatb: funnel@6005000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6005000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-qatb";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_qatb_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_funnel_qatb>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_qatb_in_tpda: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_out_funnel_qatb>;
+ };
+ };
+
+ port@2 {
+ reg = <3>;
+ qatb3_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_qatb3>;
+ };
+ };
+
+ };
+ };
+
+ tpda: tpda@6004000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x6004000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda";
+
+ qcom,tpda-atid = <65>;
+ qcom,bc-elem-size = <10 64>,
+ <24 32>,
+ <25 64>;
+ qcom,tc-elem-size = <10 64>,
+ <25 64>;
+ qcom,dsb-elem-size = <1 32>,
+ <2 32>,
+ <4 32>,
+ <6 32>,
+ <9 32>,
+ <10 32>,
+ <13 32>,
+ <14 32>,
+ <15 32>,
+ <19 32>,
+ <24 32>,
+ <25 32>;
+ qcom,cmb-elem-size = <4 32>,
+ <6 32>,
+ <10 32>,
+ <11 32>,
+ <12 64>,
+ <14 64>,
+ <16 32>,
+ <20 64>,
+ <21 32>,
+ <22 32>,
+ <23 32>,
+ <25 64>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_tpda>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ tpda_in_funnel_gpu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_gpu_out_tpda>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ tpda2_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_tpda2>;
+ };
+ };
+
+ port@3 {
+ reg = <4>;
+ tpda4_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_tpda4>;
+ };
+ };
+
+ port@4 {
+ reg = <6>;
+ tpda6_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_tpda6>;
+ };
+ };
+
+ port@5 {
+ reg = <9>;
+ tpda9_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_tpda9>;
+ };
+ };
+
+ port@6 {
+ reg = <10>;
+ tpda10_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_tpda10>;
+ };
+ };
+
+ port@7 {
+ reg = <11>;
+ tpda11_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_tpda11>;
+ };
+ };
+
+ port@8 {
+ reg = <12>;
+ tpda12_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_tpda12>;
+ };
+ };
+
+ port@9 {
+ reg = <13>;
+ tpda13_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_tpda13>;
+ };
+ };
+
+ port@10 {
+ reg = <14>;
+ tpda14_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_tpda14>;
+ };
+ };
+
+ port@11 {
+ reg = <15>;
+ tpda15_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_tpda15>;
+ };
+ };
+
+ port@12 {
+ reg = <16>;
+ tpda16_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_tpda16>;
+ };
+ };
+
+ port@13 {
+ reg = <19>;
+ tpda19_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_tpda19>;
+ };
+ };
+
+ port@14 {
+ reg = <20>;
+ tpda20_in_funnel_dl_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_center_out_tpda20>;
+ };
+ };
+
+ port@15 {
+ reg = <21>;
+ tpda_in_tpdm_vsense: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_vsense_out_tpda>;
+ };
+ };
+
+ port@16 {
+ reg = <22>;
+ tpda_in_tpdm_dcc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dcc_out_tpda>;
+ };
+ };
+
+ port@17 {
+ reg = <23>;
+ tpda_in_tpdm_prng: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_prng_out_tpda>;
+ };
+ };
+
+ port@18 {
+ reg = <24>;
+ tpda_in_tpdm_qm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_qm_out_tpda>;
+ };
+ };
+
+ port@19 {
+ reg = <25>;
+ tpda_in_tpdm_pimem: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_pimem_out_tpda>;
+ };
+ };
+ };
+ };
+
+ tpdm_dcc: tpdm@6870000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6870000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dcc";
+
+ qcom,hw-enable-check;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_dcc_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_dcc>;
+ };
+ };
+ };
+
+ tpdm_vsense: tpdm@6840000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6840000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-vsense";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_vsense_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_vsense>;
+ };
+ };
+ };
+
+ tpdm_prng: tpdm@684c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x684c000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-prng";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_prng_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_prng>;
+ };
+ };
+ };
+
+ tpdm_pimem: tpdm@6850000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6850000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-pimem";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_pimem_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_pimem>;
+ };
+ };
+ };
+
+ tpdm_qm: tpdm@69d0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x69d0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-qm";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_qm_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_qm>;
+ };
+ };
+ };
+
+ funnel_dl_center: funnel@6c2d000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6c2d000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-dl-center";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_dl_center_out_tpda2: endpoint {
+ remote-endpoint =
+ <&tpda2_in_funnel_dl_center>;
+ source = <&tpdm_dl_mm>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_dl_center_out_tpda4: endpoint {
+ remote-endpoint =
+ <&tpda4_in_funnel_dl_center>;
+ source = <&tpdm_mdss>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_dl_center_out_tpda6: endpoint {
+ remote-endpoint =
+ <&tpda6_in_funnel_dl_center>;
+ source = <&tpdm_ddr>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_dl_center_out_tpda9: endpoint {
+ remote-endpoint =
+ <&tpda9_in_funnel_dl_center>;
+ source = <&tpdm_lpass>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ funnel_dl_center_out_tpda10: endpoint {
+ remote-endpoint =
+ <&tpda10_in_funnel_dl_center>;
+ source = <&tpdm_npu>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ funnel_dl_center_out_tpda11: endpoint {
+ remote-endpoint =
+ <&tpda11_in_funnel_dl_center>;
+ source = <&tpdm_npu_llm>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ funnel_dl_center_out_tpda12: endpoint {
+ remote-endpoint =
+ <&tpda12_in_funnel_dl_center>;
+ source = <&tpdm_npu_dpm>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ funnel_dl_center_out_tpda13: endpoint {
+ remote-endpoint =
+ <&tpda13_in_funnel_dl_center>;
+ source = <&tpdm_compute0>;
+ };
+ };
+
+ port@8 {
+ reg = <8>;
+ funnel_dl_center_out_tpda14: endpoint {
+ remote-endpoint =
+ <&tpda14_in_funnel_dl_center>;
+ source = <&tpdm_compute1>;
+ };
+ };
+
+ port@9 {
+ reg = <9>;
+ funnel_dl_center_out_tpda15: endpoint {
+ remote-endpoint =
+ <&tpda15_in_funnel_dl_center>;
+ source = <&tpdm_turing>;
+ };
+ };
+
+ port@10 {
+ reg = <10>;
+ funnel_dl_center_out_tpda16: endpoint {
+ remote-endpoint =
+ <&tpda16_in_funnel_dl_center>;
+ source = <&tpdm_llm_turing>;
+ };
+ };
+
+ port@11 {
+ reg = <11>;
+ funnel_dl_center_out_tpda19: endpoint {
+ remote-endpoint =
+ <&tpda19_in_funnel_dl_center>;
+ source = <&tpdm_dlct>;
+ };
+ };
+
+ port@12 {
+ reg = <12>;
+ funnel_dl_center_out_tpda20: endpoint {
+ remote-endpoint =
+ <&tpda20_in_funnel_dl_center>;
+ source = <&tpdm_ipcc>;
+ };
+ };
+
+ port@13 {
+ reg = <13>;
+ funnel_dl_center_out_qatb3: endpoint {
+ remote-endpoint =
+ <&qatb3_in_funnel_dl_center>;
+ };
+ };
+
+ port@14 {
+ reg = <0>;
+ funnel_dl_center_in_funnel_dl_mm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dl_mm_out_funnel_dl_center>;
+ };
+ };
+
+ port@15 {
+ reg = <1>;
+ funnel_dl_center_in_tpdm_mdss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_mdss_out_funnel_dl_center>;
+ };
+ };
+
+ port@16 {
+ reg = <2>;
+ funnel_dl_center_in_funnel_ddr_0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_ddr_0_out_funnel_dl_center>;
+ };
+ };
+
+ port@17 {
+ reg = <3>;
+ funnel_center_in_funnel_compute: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_compute_out_funnel_center>;
+ };
+ };
+
+ port@18 {
+ reg = <4>;
+ funnel_dl_center_in_funnel_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_turing_out_funnel_dl_center>;
+ };
+ };
+
+ port@19 {
+ reg = <5>;
+ funnel_dl_center_in_tpdm_dlct: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dlct_out_funnel_dl_center>;
+ };
+ };
+
+ port@20 {
+ reg = <6>;
+ funnel_dl_center_in_tpdm_ipcc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_ipcc_out_funnel_dl_center>;
+ };
+ };
+ };
+ };
+
+ tpdm_dlct: tpdm@6c28000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c28000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dlct";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_dlct_out_funnel_dl_center: endpoint {
+ remote-endpoint =
+ <&funnel_dl_center_in_tpdm_dlct>;
+ };
+ };
+ };
+
+ tpdm_ipcc: tpdm@6c29000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c29000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-ipcc";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_ipcc_out_funnel_dl_center: endpoint {
+ remote-endpoint =
+ <&funnel_dl_center_in_tpdm_ipcc>;
+ };
+ };
+ };
+
+ tpda_nav: tpda@6843000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x6843000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-nav";
+ qcom,tpda-atid = <68>;
+ qcom,cmb-elem-size = <0 32>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_nav_out_funnel_dl_compute: endpoint {
+ remote-endpoint =
+ <&funnel_dl_compute_in_tpda_nav>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_nav0_in_tpdm_nav: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_nav_out_tpda_nav0>;
+ };
+ };
+
+ };
+ };
+
+ tpdm_nav: tpdm@6842000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6842000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-nav";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_nav_out_tpda_nav0: endpoint {
+ remote-endpoint =
+ <&tpda_nav0_in_tpdm_nav>;
+ };
+ };
+ };
+
+ funnel_turing: funnel@6983000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6983000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-turing";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_turing_out_funnel_dl_center: endpoint {
+ remote-endpoint =
+ <&funnel_dl_center_in_funnel_turing>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_turing_in_tpdm_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_turing_out_funnel_turing>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_turing_in_tpdm_llm_turing: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_llm_turing_out_funnel_turing>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ funnel_turing_in_turing_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&turing_etm0_out_funnel_turing>;
+ };
+ };
+ };
+ };
+
+ tpdm_turing: tpdm@6980000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6980000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-turing";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_turing_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_tpdm_turing>;
+ };
+ };
+ };
+
+ tpdm_llm_turing: tpdm@69810000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6981000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-turing-llm";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_llm_turing_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_tpdm_llm_turing>;
+ };
+ };
+ };
+
+ etm_turing: turing_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-turing-etm0";
+ qcom,inst-id = <13>;
+
+ port {
+ turing_etm0_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_turing_etm0>;
+ };
+ };
+ };
+
+ funnel_dl_compute: funnel@6c3b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6c3b000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-dl-compute";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_compute_out_funnel_center: endpoint {
+ remote-endpoint =
+ <&funnel_center_in_funnel_compute>;
+ };
+ };
+
+ port@1 {
+ reg = <2>;
+ funnel_dl_compute_in_funnel_lpass: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_lpass_out_funnel_dl_compute>;
+ };
+ };
+
+ port@2 {
+ reg = <4>;
+ funnel_dl_compute_in_funnel_npu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_npu_out_funnel_dl_compute>;
+ };
+ };
+
+ port@3 {
+ reg = <5>;
+ funnel_dl_compute_in_tpdm_compute0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_compute0_out_funnel_dl_compute>;
+ };
+ };
+
+ port@4 {
+ reg = <6>;
+ funnel_dl_compute_in_tpdm_compute1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_compute1_out_funnel_dl_compute>;
+ };
+ };
+
+ port@5 {
+ reg = <7>;
+ funnel_dl_compute_in_tpda_nav: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_nav_out_funnel_dl_compute>;
+ };
+ };
+ };
+ };
+
+ tpdm_compute0: tpdm@6c38000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c38000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dl-compute0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_compute0_out_funnel_dl_compute: endpoint {
+ remote-endpoint =
+ <&funnel_dl_compute_in_tpdm_compute0>;
+ };
+ };
+ };
+
+ tpdm_compute1: tpdm@6c39000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c39000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dl-compute1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_compute1_out_funnel_dl_compute: endpoint {
+ remote-endpoint =
+ <&funnel_dl_compute_in_tpdm_compute1>;
+ };
+ };
+ };
+
+ tpdm_npu: tpdm@6c47000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c47000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-npu";
+
+ clocks = <&aopcc QDSS_CLK>;
+
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_npu_out_funnel_npu: endpoint {
+ remote-endpoint = <&funnel_npu_in_tpdm_npu>;
+ };
+ };
+ };
+
+ tpdm_npu_llm: tpdm@6c40000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c40000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-npu-llm";
+
+ clocks = <&aopcc QDSS_CLK>,
+ <&gcc GCC_NPU_AXI_CLK>,
+ <&gcc GCC_NPU_CFG_AHB_CLK>,
+ <&npucc NPU_CC_XO_CLK>,
+ <&npucc NPU_CC_CORE_CLK>,
+ <&npucc NPU_CC_CORE_CLK_SRC>,
+ <&npucc NPU_CC_DL_LLM_CLK>,
+ <&npucc NPU_CC_LLM_CLK>,
+ <&npucc NPU_CC_LLM_CURR_CLK>,
+ <&npucc NPU_CC_LLM_TEMP_CLK>,
+ <&npucc NPU_CC_LLM_XO_CLK>;
+
+ clock-names = "apb_pclk",
+ "npu_axi_clk",
+ "npu_cfg_ahb_clk",
+ "npu_cc_xo_clk",
+ "npu_core_clk",
+ "npu_core_clk_src",
+ "dl_llm_clk",
+ "llm_clk",
+ "llm_curr_clk",
+ "llm_temp_clk",
+ "llm_xo_clk";
+
+ qcom,proxy-clks = "npu_axi_clk",
+ "npu_cfg_ahb_clk",
+ "npu_cc_xo_clk",
+ "npu_core_clk",
+ "npu_core_clk_src",
+ "dl_llm_clk",
+ "llm_clk",
+ "llm_curr_clk",
+ "llm_temp_clk",
+ "llm_xo_clk";
+
+ vdd-supply = <&npu_core_gdsc>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,proxy-regs ="vdd", "vdd_cx";
+
+ port {
+ tpdm_npu_llm_out_funnel_npu: endpoint {
+ remote-endpoint = <&funnel_npu_in_tpdm_npu_llm>;
+ };
+ };
+ };
+
+ tpdm_npu_dpm: tpdm@6c41000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c41000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-npu-dpm";
+
+ clocks = <&aopcc QDSS_CLK>,
+ <&npucc NPU_CC_DL_DPM_CLK>,
+ <&npucc NPU_CC_DPM_CLK>,
+ <&npucc NPU_CC_DPM_TEMP_CLK>,
+ <&npucc NPU_CC_DPM_XO_CLK>;
+
+ clock-names = "apb_pclk",
+ "dl_dpm_clk",
+ "dpm_clk",
+ "dpm_temp_clk",
+ "dpm_xo_clk";
+
+ qcom,proxy-clks = "dl_dpm_clk",
+ "dpm_clk",
+ "dpm_temp_clk",
+ "dpm_xo_clk";
+
+ vdd-supply = <&npu_core_gdsc>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,proxy-regs ="vdd", "vdd_cx";
+
+
+ port {
+ tpdm_npu_dpm_out_funnel_npu: endpoint {
+ remote-endpoint = <&funnel_npu_in_tpdm_npu_dpm>;
+ };
+ };
+ };
+
+ funnel_npu: funnel@6c44000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6c44000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-npu";
+
+ clocks = <&aopcc QDSS_CLK>;
+
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_npu_out_funnel_dl_compute: endpoint {
+ remote-endpoint =
+ <&funnel_dl_compute_in_funnel_npu>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_npu_in_tpdm_npu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_npu_out_funnel_npu>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_npu_in_tpdm_npu_llm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_npu_llm_out_funnel_npu>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ funnel_npu_in_tpdm_npu_dpm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_npu_dpm_out_funnel_npu>;
+ };
+ };
+
+ port@4 {
+ reg = <3>;
+ funnel_npu_in_npu_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&npu_etm0_out_funnel_npu>;
+ };
+ };
+ };
+ };
+
+ etm_npu: npu_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-npu-etm0";
+ qcom,inst-id = <14>;
+
+ port {
+ npu_etm0_out_funnel_npu: endpoint {
+ remote-endpoint =
+ <&funnel_npu_in_npu_etm0>;
+ };
+ };
+ };
+
+ funnel_lpass: funnel@6846000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6846000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-lpass";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_lpass_out_funnel_dl_compute: endpoint {
+ remote-endpoint =
+ <&funnel_dl_compute_in_funnel_lpass>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_lpass_in_tpdm_lpass: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_lpass_out_funnel_lpass>;
+ };
+ };
+ };
+ };
+
+ tpdm_lpass: tpdm@6844000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6844000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-lpass";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_lpass_out_funnel_lpass: endpoint {
+ remote-endpoint = <&funnel_lpass_in_tpdm_lpass>;
+ };
+ };
+ };
+
+ funnel_ddr_0: funnel@6e05000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6e05000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-ddr-0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_ddr_0_out_funnel_dl_center: endpoint {
+ remote-endpoint =
+ <&funnel_dl_center_in_funnel_ddr_0>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_ddr_0_in_tpdm_ddr: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_ddr_out_funnel_ddr_0>;
+ };
+ };
+ };
+ };
+
+ tpdm_ddr: tpdm@6e00000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x06e00000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-ddr";
+
+ status = "disabled";
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_ddr_out_funnel_ddr_0: endpoint {
+ remote-endpoint = <&funnel_ddr_0_in_tpdm_ddr>;
+ };
+ };
+ };
+
+ tpdm_mdss: tpdm@6c60000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c60000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-mdss";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_mdss_out_funnel_dl_center: endpoint {
+ remote-endpoint =
+ <&funnel_dl_center_in_tpdm_mdss>;
+ };
+ };
+ };
+
+ funnel_dl_mm: funnel@6c0b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6c0b000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-dl-mm";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_dl_mm_out_funnel_dl_center: endpoint {
+ remote-endpoint =
+ <&funnel_dl_center_in_funnel_dl_mm>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_dl_mm_in_tpdm_dl_mm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dl_mm_out_funnel_dl_mm>;
+ };
+ };
+ };
+ };
+
+ tpdm_dl_mm: tpdm@6c08000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6c08000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-mm";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_dl_mm_out_funnel_dl_mm: endpoint {
+ remote-endpoint =
+ <&funnel_dl_mm_in_tpdm_dl_mm>;
+ };
+ };
+ };
+
+ funnel_gpu: funnel@6902000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6902000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-gpu";
+
+ status = "disabled";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_gpu_out_tpda: endpoint {
+ remote-endpoint =
+ <&tpda_in_funnel_gpu>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_gpu_in_tpdm_gpu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_gpu_out_funnel_gpu>;
+ };
+ };
+ };
+ };
+
+ tpdm_gpu: tpdm@6900000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b968>;
+ reg = <0x6900000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-gpu";
+ status = "disabled";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_gpu_out_funnel_gpu: endpoint {
+ remote-endpoint = <&funnel_gpu_in_tpdm_gpu>;
+ };
+ };
+ };
+
+ funnel_in1: funnel@6042000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6042000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-in1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_in1_out_funnel_merg: endpoint {
+ remote-endpoint =
+ <&funnel_merg_in_funnel_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_in1_in_tpdm_wcss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_wcss_out_funnel_in1>;
+ };
+ };
+
+ port@2 {
+ reg = <4>;
+ funnel_in1_in_funnel_modem: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_modem_out_funnel_in1>;
+ };
+ };
+
+ port@3 {
+ reg = <5>;
+ funnel_in1_in_funnel_apss_merg: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_apss_merg_out_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ funnel_modem: funnel@6804000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6804000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-modem";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_modem_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_funnel_modem>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_modem_in_tpda_modem: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_modem_out_funnel_modem>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_modem_in_modem2_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&modem2_etm0_out_funnel_modem>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_modem_in_funnel_mq6_dup: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_mq6_dup_out_funnel_modem>;
+ };
+ };
+ };
+ };
+
+ modem2_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-modem2-etm0";
+ qcom,inst-id = <11>;
+
+ port {
+ modem2_etm0_out_funnel_modem: endpoint {
+ remote-endpoint =
+ <&funnel_modem_in_modem2_etm0>;
+ };
+ };
+ };
+
+ funnel_modem_q6: funnel@680c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x680c000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-modem-q6";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_modem_q6_out_funnel_mq6_dup: endpoint {
+ remote-endpoint =
+ <&funnel_mq6_dup_in_funnel_modem_q6>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_modem_q6_in_modem_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&modem_etm0_out_funnel_modem_q6>;
+ };
+ };
+ };
+ };
+
+ funnel_mq6_dup: funnel_1@680c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x680b000 0x1000>,
+ <0x680c000 0x1000>;
+
+ reg-names = "funnel-base-dummy", "funnel-base-real";
+
+ coresight-name = "coresight-funnel-modem-q6_dup";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ qcom,duplicate-funnel;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_mq6_dup_out_funnel_modem: endpoint {
+ remote-endpoint =
+ <&funnel_modem_in_funnel_mq6_dup>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_mq6_dup_in_funnel_modem_q6: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_modem_q6_out_funnel_mq6_dup>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_mq6_dup_in_modem_diag: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&modem_diag_out_funnel_mq6_dup>;
+ };
+ };
+ };
+ };
+
+ modem_diag: dummy_source {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-modem-diag";
+ qcom,dummy-source;
+
+ port {
+ modem_diag_out_funnel_mq6_dup: endpoint {
+ remote-endpoint =
+ <&funnel_mq6_dup_in_modem_diag>;
+ };
+ };
+ };
+
+ modem_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-modem-etm0";
+ qcom,inst-id = <2>;
+
+ port {
+ modem_etm0_out_funnel_modem_q6: endpoint {
+ remote-endpoint =
+ <&funnel_modem_q6_in_modem_etm0>;
+ };
+ };
+ };
+
+ tpda_modem: tpda@6803000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x6803000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-modem";
+
+ qcom,tpda-atid = <67>;
+ qcom,dsb-elem-size = <0 32>;
+ qcom,cmb-elem-size = <0 64>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_modem_out_funnel_modem: endpoint {
+ remote-endpoint =
+ <&funnel_modem_in_tpda_modem>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_modem_in_tpdm_modem_0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_modem_0_out_tpda_modem>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ tpda_modem_in_tpdm_modem_1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_modem_1_out_tpda_modem>;
+ };
+ };
+ };
+ };
+
+ tpdm_modem_0: tpdm@6800000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6800000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name="coresight-tpdm-modem-0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_modem_0_out_tpda_modem: endpoint {
+ remote-endpoint = <&tpda_modem_in_tpdm_modem_0>;
+ };
+ };
+ };
+
+ tpdm_modem_1: tpdm@6801000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6801000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name="coresight-tpdm-modem-1";
+
+ status = "disabled";
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_modem_1_out_tpda_modem: endpoint {
+ remote-endpoint = <&tpda_modem_in_tpdm_modem_1>;
+ };
+ };
+ };
+
+ tpdm_swao1: tpdm@6b0a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x6b0a000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name="coresight-tpdm-swao-1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,msr-fix-req;
+
+ port {
+ tpdm_swao1_out_tpda_swao: endpoint {
+ remote-endpoint = <&tpda_swao_in_tpdm_swao1>;
+ };
+ };
+ };
+
+ funnel_apss_merg: funnel@7810000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x7810000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-apss-merg";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_apss_merg_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_funnel_apss_merg>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_apss_merg_in_funnel_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_apss_out_funnel_apss_merg>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_apss_merg_in_tpda_olc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_olc_out_funnel_apss_merg>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_apss_merg_in_tpda_llm_silver: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_llm_silver_out_funnel_apss_merg>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ funnel_apss_merg_in_tpda_llm_gold: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_llm_gold_out_funnel_apss_merg>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ funnel_apss_merg_in_tpda_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_apss_out_funnel_apss_merg>;
+ };
+ };
+ };
+ };
+
+ tpda_olc: tpda@7832000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x7832000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-olc";
+
+ qcom,tpda-atid = <69>;
+ qcom,cmb-elem-size = <0 64>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_olc_out_funnel_apss_merg: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merg_in_tpda_olc>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_olc_in_tpdm_olc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_olc_out_tpda_olc>;
+ };
+ };
+ };
+ };
+
+ tpdm_olc: tpdm@7830000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x7830000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-olc";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_olc_out_tpda_olc: endpoint {
+ remote-endpoint = <&tpda_olc_in_tpdm_olc>;
+ };
+ };
+ };
+
+ tpda_apss: tpda@7862000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x7862000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-apss";
+
+ qcom,tpda-atid = <66>;
+ qcom,dsb-elem-size = <0 32>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_apss_out_funnel_apss_merg: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merg_in_tpda_apss>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_apss_in_tpdm_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_apss_out_tpda_apss>;
+ };
+ };
+ };
+ };
+
+ tpdm_apss: tpdm@7860000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x7860000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-apss";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_apss_out_tpda_apss: endpoint {
+ remote-endpoint = <&tpda_apss_in_tpdm_apss>;
+ };
+ };
+ };
+
+ tpda_llm_silver: tpda@78c0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x78c0000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-llm-silver";
+
+ qcom,tpda-atid = <72>;
+ qcom,cmb-elem-size = <0 32>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_llm_silver_out_funnel_apss_merg: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merg_in_tpda_llm_silver>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_llm_silver_in_tpdm_llm_silver: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_llm_silver_out_tpda_llm_silver>;
+ };
+ };
+ };
+ };
+
+ tpdm_llm_silver: tpdm@78a0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x78a0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-llm-silver";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_llm_silver_out_tpda_llm_silver: endpoint {
+ remote-endpoint =
+ <&tpda_llm_silver_in_tpdm_llm_silver>;
+ };
+ };
+ };
+
+ tpda_llm_gold: tpda@78d0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x78d0000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-llm-gold";
+
+ qcom,tpda-atid = <73>;
+ qcom,cmb-elem-size = <0 32>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_llm_gold_out_funnel_apss_merg: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merg_in_tpda_llm_gold>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_llm_gold_in_tpdm_llm_gold: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_llm_gold_out_tpda_llm_gold>;
+ };
+ };
+ };
+ };
+
+ tpdm_llm_gold: tpdm@78b0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x78b0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-llm-gold";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_llm_gold_out_tpda_llm_gold: endpoint {
+ remote-endpoint =
+ <&tpda_llm_gold_in_tpdm_llm_gold>;
+ };
+ };
+ };
+
+ funnel_apss: funnel@7800000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x7800000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-apss";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_apss_out_funnel_apss_merg: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merg_in_funnel_apss>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_apss_in_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm0_out_funnel_apss>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_apss_in_etm1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm1_out_funnel_apss>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ funnel_apss_in_etm2: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm2_out_funnel_apss>;
+ };
+ };
+
+ port@4 {
+ reg = <3>;
+ funnel_apss_in_etm3: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm3_out_funnel_apss>;
+ };
+ };
+
+ port@5 {
+ reg = <4>;
+ funnel_apss_in_etm4: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm4_out_funnel_apss>;
+ };
+ };
+
+ port@6 {
+ reg = <5>;
+ funnel_apss_in_etm5: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm5_out_funnel_apss>;
+ };
+ };
+
+ port@7 {
+ reg = <6>;
+ funnel_apss_in_etm6: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm6_out_funnel_apss>;
+ };
+ };
+
+ port@8 {
+ reg = <7>;
+ funnel_apss_in_etm7: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm7_out_funnel_apss>;
+ };
+ };
+ };
+ };
+
+ etm0: etm@7040000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7040000 0x1000>;
+ cpu = <&CPU0>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm0_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm0>;
+ };
+ };
+ };
+
+ etm1: etm@7140000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7140000 0x1000>;
+ cpu = <&CPU1>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm1_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm1>;
+ };
+ };
+ };
+
+ etm2: etm@7240000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7240000 0x1000>;
+ cpu = <&CPU2>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm2_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm2>;
+ };
+ };
+ };
+
+ etm3: etm@7340000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7340000 0x1000>;
+ cpu = <&CPU3>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm3";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm3_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm3>;
+ };
+ };
+ };
+
+ etm4: etm@7440000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7440000 0x1000>;
+ cpu = <&CPU4>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm4";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm4_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm4>;
+ };
+ };
+ };
+
+ etm5: etm@7540000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7540000 0x1000>;
+ cpu = <&CPU5>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm5";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm5_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm5>;
+ };
+ };
+ };
+
+ etm6: etm@7640000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7640000 0x1000>;
+ cpu = <&CPU6>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm6";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm6_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm6>;
+ };
+ };
+ };
+
+ etm7: etm@7740000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7740000 0x1000>;
+ cpu = <&CPU7>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm7";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm7_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm7>;
+ };
+ };
+ };
+
+ cti0_apss: cti@78e0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x78e0000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss_cti0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1_apss: cti@78f0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x78f0000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss_cti1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2_apss: cti@7900000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7900000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss_cti2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_iris: cti@6830000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6830000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-iris_dl_cti";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0: cti@6010000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6010000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti1: cti@6011000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6011000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti2: cti@6012000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6012000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,cti-gpio-trigout = <4>;
+ pinctrl-names = "cti-trigout-pctrl";
+ pinctrl-0 = <&trigout_a>;
+ };
+
+ cti3: cti@6013000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6013000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti3";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti4: cti@6014000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6014000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti4";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti5: cti@6015000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6015000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti5";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti6: cti@6016000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6016000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti6";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti7: cti@6017000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6017000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti7";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti8: cti@6018000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6018000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti8";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti9: cti@6019000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6019000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti9";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti10: cti@601a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601a000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti10";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti11: cti@601b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti11";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti12: cti@601c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601c000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti12";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti13: cti@601d000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601d000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti13";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti14: cti@601e000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601e000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti14";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti15: cti@601f000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601f000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti15";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti_cpu0: cti@7020000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7020000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu0";
+ cpu = <&CPU0>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ };
+
+ cti_cpu1: cti@7120000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7120000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu1";
+ cpu = <&CPU1>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu2: cti@7220000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7220000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu2";
+ cpu = <&CPU2>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu3: cti@7320000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7320000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu3";
+ cpu = <&CPU3>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu4: cti@7420000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7420000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu4";
+ cpu = <&CPU4>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu5: cti@7520000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7520000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu5";
+ cpu = <&CPU5>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu6: cti@7620000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7620000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu6";
+ cpu = <&CPU6>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu7: cti@7720000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7720000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu7";
+ cpu = <&CPU7>;
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0_swao:cti@6b00000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b00000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-swao_cti0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1_swao:cti@6b01000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b01000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-swao_cti1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2_swao:cti@6b02000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b02000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-swao_cti2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti3_swao:cti@6b03000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6b03000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-swao_cti3";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0_dlct: cti@6c2a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c2a000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct_cti0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1_dlct: cti@6c2b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c2b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct_cti1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2_dlct: cti@6c2c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c2c000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct_cti2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0_dlmm: cti@6c09000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c09000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlmm_cti0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1_dlmm: cti@6c0a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c0a000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlmm_cti1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0_dlcompute: cti@6c3a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c3a000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlcompute_cti0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0_ddr0: cti@6e02000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6e02000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_0_cti_0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1_ddr0: cti@6e03000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6e03000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_0_cti_1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2_ddr0: cti@6e04000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6e04000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_0_cti_2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0_ddr1: cti@6e10000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6e10000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_1_cti_0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1_ddr1: cti@6e11000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6e11000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_1_cti_1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2_ddr1: cti@6e12000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6e12000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-ddr_dl_1_cti_2";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_gpu_m3: cti@6962000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6962000 0x1000>;
+ reg-names = "cti-base";
+
+ status = "disabled";
+ coresight-name = "coresight-cti-gpu_cortex_m3";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_gpu_isdb: cti@6961000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6961000 0x1000>;
+ reg-names = "cti-base";
+
+ status = "disabled";
+ coresight-name = "coresight-cti-gpu_isdb_cti";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_lpass: cti@6845000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6845000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-lpass_dl_cti";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_npu_dl0: cti@6c42000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c42000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-npu_dl_cti_0";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_npu_dl1: cti@6c43000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c43000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-npu_dl_cti_1";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_npu: cti@6c4b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6c4b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-npu_q6_cti";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_turing:cti@6982000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6982000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-turing_dl_cti";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_turing_q6:cti@698b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x698b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-turing_q6_cti";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ tpdm_lpass_lpi: tpdm@6b26000 {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-tpdm-lpass-lpi";
+ qcom,dummy-source;
+
+ port {
+ lpass_lpi_out_funnel_swao: endpoint {
+ remote-endpoint =
+ <&funnel_swao_in_lpass_lpi>;
+ };
+ };
+ };
+
+ tpdm_wcss: tpdm@069a4000 {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-tpdm-wcss";
+ qcom,dummy-source;
+
+ port {
+ tpdm_wcss_out_funnel_in1: endpoint {
+ remote-endpoint = <&funnel_in1_in_tpdm_wcss>;
+ };
+ };
+ };
+
+ audio_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-audio-etm0";
+ qcom,inst-id = <5>;
+
+ port {
+ audio_etm0_out_funnel_swao: endpoint {
+ remote-endpoint =
+ <&funnel_swao_in_audio_etm0>;
+ };
+ };
+ };
+
+ ipcb_tgu: tgu@6b0b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb999>;
+ reg = <0x06b0b000 0x1000>;
+ reg-names = "tgu-base";
+ tgu-steps = <3>;
+ tgu-conditions = <4>;
+ tgu-regs = <4>;
+ tgu-timer-counters = <8>;
+
+ coresight-name = "coresight-tgu-ipcb";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ hwevent {
+ compatible = "qcom,coresight-hwevent";
+ coresight-name = "coresight-hwevent";
+ coresight-csr = <&csr>;
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-gdsc.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-gdsc.dtsi
new file mode 100755
index 0000000..fff09af
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-gdsc.dtsi
@@ -0,0 +1,165 @@
+&soc {
+ /* GCC GDSCs */
+ ufs_phy_gdsc: qcom,gdsc@177004 {
+ compatible = "qcom,gdsc";
+ reg = <0x177004 0x4>;
+ regulator-name = "ufs_phy_gdsc";
+ status = "disabled";
+ };
+
+ usb30_prim_gdsc: qcom,gdsc@10f004 {
+ compatible = "qcom,gdsc";
+ reg = <0x10f004 0x4>;
+ regulator-name = "usb30_prim_gdsc";
+ status = "disabled";
+ };
+
+ hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc: qcom,gdsc@17d050 {
+ compatible = "qcom,gdsc";
+ reg = <0x17d050 0x4>;
+ regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc";
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc: qcom,gdsc@17d058 {
+ compatible = "qcom,gdsc";
+ reg = <0x17d058 0x4>;
+ regulator-name = "hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc";
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc: qcom,gdsc@17d054 {
+ compatible = "qcom,gdsc";
+ reg = <0x17d054 0x4>;
+ regulator-name = "hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc";
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ /* CAM_CC GDSCs */
+ bps_gdsc: qcom,gdsc@ad07004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad07004 0x4>;
+ regulator-name = "bps_gdsc";
+ status = "disabled";
+ };
+
+ ipe_0_gdsc: qcom,gdsc@ad08004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad08004 0x4>;
+ regulator-name = "ipe_0_gdsc";
+ status = "disabled";
+ };
+
+ ipe_1_gdsc: qcom,gdsc@ad09004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad09004 0x4>;
+ regulator-name = "ipe_1_gdsc";
+ status = "disabled";
+ };
+
+ ife_0_gdsc: qcom,gdsc@ad0a004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad0a004 0x4>;
+ regulator-name = "ife_0_gdsc";
+ status = "disabled";
+ };
+
+ ife_1_gdsc: qcom,gdsc@ad0b004 {
+ compatible = "qcom,gdsc";
+ reg = <0xad0b004 0x4>;
+ regulator-name = "ife_1_gdsc";
+ status = "disabled";
+ };
+
+ titan_top_gdsc: qcom,gdsc@ad0c1c4 {
+ compatible = "qcom,gdsc";
+ reg = <0xad0c1c4 0x4>;
+ regulator-name = "titan_top_gdsc";
+ status = "disabled";
+ };
+
+ /* DISP_CC GDSC */
+ mdss_core_gdsc: qcom,gdsc@af03000 {
+ compatible = "qcom,gdsc";
+ reg = <0xaf03000 0x4>;
+ regulator-name = "mdss_core_gdsc";
+ qcom,support-hw-trigger;
+ proxy-supply = <&mdss_core_gdsc>;
+ qcom,proxy-consumer-enable;
+ status = "disabled";
+ };
+
+ /* GPU_CC GDSCs */
+ gpu_cx_hw_ctrl: syscon@3d91540 {
+ compatible = "syscon";
+ reg = <0x3d91540 0x4>;
+ };
+
+ gpu_cx_gdsc: qcom,gdsc@3d9106c {
+ compatible = "qcom,gdsc";
+ reg = <0x3d9106c 0x4>;
+ regulator-name = "gpu_cx_gdsc";
+ hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
+ qcom,no-status-check-on-disable;
+ qcom,clk-dis-wait-val = <8>;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ gpu_gx_domain_addr: syscon@3d91508 {
+ compatible = "syscon";
+ reg = <0x3d91508 0x4>;
+ };
+
+ gpu_gx_sw_reset: syscon@3d91008 {
+ compatible = "syscon";
+ reg = <0x3d91008 0x4>;
+ };
+
+ gpu_gx_gdsc: qcom,gdsc@3d9100c {
+ compatible = "qcom,gdsc";
+ reg = <0x3d9100c 0x4>;
+ regulator-name = "gpu_gx_gdsc";
+ domain-addr = <&gpu_gx_domain_addr>;
+ sw-reset = <&gpu_gx_sw_reset>;
+ qcom,skip-disable-before-sw-enable;
+ qcom,reset-aon-logic;
+ status = "disabled";
+ };
+
+ /* NPU GDSC */
+ npu_core_gdsc: qcom,gdsc@9981004 {
+ compatible = "qcom,gdsc";
+ reg = <0x9981004 0x4>;
+ regulator-name = "npu_core_gdsc";
+ status = "disabled";
+ };
+
+ /* VIDEO_CC GDSCs */
+ mvsc_gdsc: qcom,gdsc@ab00814 {
+ compatible = "qcom,gdsc";
+ reg = <0xab00814 0x4>;
+ regulator-name = "mvsc_gdsc";
+ status = "disabled";
+ };
+
+ mvs0_gdsc: qcom,gdsc@ab00874 {
+ compatible = "qcom,gdsc";
+ reg = <0xab00874 0x4>;
+ regulator-name = "mvs0_gdsc";
+ status = "disabled";
+ };
+
+ mvs1_gdsc: qcom,gdsc@ab008b4 {
+ compatible = "qcom,gdsc";
+ reg = <0xab008b4 0x4>;
+ regulator-name = "mvs1_gdsc";
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-gpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-gpu.dtsi
new file mode 100755
index 0000000..76c7a7d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-gpu.dtsi
@@ -0,0 +1,457 @@
+&soc {
+ pil_gpu: qcom,kgsl-hyp {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <13>;
+ qcom,firmware-name = "a620_zap";
+ };
+
+ msm_bus: qcom,kgsl-busmon {
+ label = "kgsl-busmon";
+ compatible = "qcom,kgsl-busmon";
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
+ gpubw: qcom,gpubw {
+ compatible = "qcom,devbw";
+ governor = "bw_vbif";
+ qcom,src-dst-ports = <26 512>;
+ operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-750000000 {
+ opp-hz = /bits/ 64 <750000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-670000000 {
+ opp-hz = /bits/ 64 <670000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-625000000 {
+ opp-hz = /bits/ 64 <625000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-275000000 {
+ opp-hz = /bits/ 64 <275000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+
+ msm_gpu: qcom,kgsl-3d0@3d00000 {
+ label = "kgsl-3d0";
+ compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
+ status = "ok";
+ reg = <0x3d00000 0x40000>, <0x3d61000 0x800>,
+ <0x3de0000 0x1000>, <0x3d8b000 0x2000>;
+ reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "rscc",
+ "isense_cntl";
+ interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+ qcom,id = <0>;
+
+ qcom,chipid = <0x06020000>;
+
+ qcom,initial-pwrlevel = <3>;
+
+ qcom,idle-timeout = <80>; /* msecs */
+
+ qcom,highest-bank-bit = <14>;
+
+ qcom,min-access-length = <32>;
+
+ qcom,ubwc-mode = <3>;
+ qcom,no-nap;
+ qcom,snapshot-size = <2048576>; /* bytes */
+ qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */
+
+ #cooling-cells = <2>;
+ qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr";
+
+ /* CPU latency parameter */
+ qcom,pm-qos-active-latency = <67>;
+ qcom,pm-qos-wakeup-latency = <67>;
+
+ /* Enable context aware freq. scaling */
+ qcom,enable-ca-jump;
+ /* Context aware jump busy penalty in us */
+ qcom,ca-busy-penalty = <12000>;
+
+ clocks = <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+
+ clock-names = "rbbmtimer_clk", "mem_clk",
+ "mem_iface_clk", "gmu_clk",
+ "gpu_cc_ahb", "smmu_vote";
+
+ qcom,gpubw-dev = <&gpubw>;
+ qcom,bus-control;
+ qcom,msm-bus,name = "grp3d";
+ qcom,msm-bus,num-cases = <13>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <26 512 0 0>,
+ <26 512 0 400000>, /* 1 bus=100 */
+ <26 512 0 800000>, /* 2 bus=200 */
+ <26 512 0 1200000>, /* 3 bus=300 */
+ <26 512 0 1804800>, /* 4 bus=451 */
+ <26 512 0 2188000>, /* 5 bus=547 */
+ <26 512 0 2724000>, /* 6 bus=681 */
+ <26 512 0 3072000>, /* 7 bus=768 */
+ <26 512 0 4068000>, /* 8 bus=1017 */
+ <26 512 0 5412000>, /* 9 bus=1353 */
+ <26 512 0 6220000>, /* 10 bus=1555 */
+ <26 512 0 7216000>, /* 11 bus=1804 */
+ <26 512 0 8371200>; /* 12 bus=2092 */
+
+ /* GDSC regulator names */
+ regulator-names = "vddcx", "vdd";
+ /* GDSC oxili regulators */
+ vddcx-supply = <&gpu_cx_gdsc>;
+ vdd-supply = <&gpu_gx_gdsc>;
+
+ nvmem-cells = <&gpu_speed_bin>, <&gpu_gaming_bin>, <&gpu_lm_efuse>;
+ nvmem-cell-names = "speed_bin", "gaming_bin", "isense_slope";
+
+ /* GPU OPP data */
+ operating-points-v2 = <&gpu_opp_table>;
+
+ /* GPU Mempools */
+ qcom,gpu-mempools {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,gpu-mempools";
+
+ /* 4K Page Pool configuration */
+ qcom,gpu-mempool@0 {
+ reg = <0>;
+ qcom,mempool-page-size = <4096>;
+ qcom,mempool-reserved = <2048>;
+ qcom,mempool-allocate;
+ };
+ /* 8K Page Pool configuration */
+ qcom,gpu-mempool@1 {
+ reg = <1>;
+ qcom,mempool-page-size = <8192>;
+ qcom,mempool-reserved = <1024>;
+ qcom,mempool-allocate;
+ };
+ /* 64K Page Pool configuration */
+ qcom,gpu-mempool@2 {
+ reg = <2>;
+ qcom,mempool-page-size = <65536>;
+ qcom,mempool-reserved = <256>;
+ };
+ /* 1M Page Pool configuration */
+ qcom,gpu-mempool@3 {
+ reg = <3>;
+ qcom,mempool-page-size = <1048576>;
+ qcom,mempool-reserved = <32>;
+ };
+ };
+
+ /*
+ * Speed-bin zero is default speed bin.
+ * For rest of the speed bins, speed-bin value
+ * is calulated as FMAX/4.8 MHz round up to zero
+ * decimal places.
+ */
+ qcom,gpu-pwrlevel-bins {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible="qcom,gpu-pwrlevel-bins";
+
+ qcom,gpu-pwrlevels-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <0>;
+ qcom,ca-target-pwrlevel = <2>;
+ qcom,initial-pwrlevel = <3>;
+
+ /* NOM */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <625000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <12>;
+ qcom,acd-level = <0x802C5FFD>;
+ };
+
+ /* SVS L1 */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <500000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <10>;
+ qcom,acd-level = <0xA02C5FFD>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ qcom,acd-level = <0xA02C5FFD>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <275000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ qcom,acd-level = <0x802F5FFD>;
+ };
+
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <132>;
+
+ qcom,initial-pwrlevel = <3>;
+ qcom,ca-target-pwrlevel = <2>;
+
+ /* NOM */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <625000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <12>;
+ qcom,acd-level = <0x802C5FFD>;
+ };
+
+ /* SVS L1 */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <500000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <10>;
+ qcom,acd-level = <0xA02C5FFD>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ qcom,acd-level = <0xA02C5FFD>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <275000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ qcom,acd-level = <0x802F5FFD>;
+ };
+
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <115>;
+ qcom,initial-pwrlevel = <2>;
+ qcom,ca-target-pwrlevel = <1>;
+
+ /* SVS L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <540000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <12>;
+ qcom,acd-level = <0x802C5FFD>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ qcom,acd-level = <0xA02C5FFD>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <275000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ qcom,acd-level = <0x802F5FFD>;
+ };
+
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+ };
+
+ qcom,cpu-to-gpu-cfg-path {
+ qcom,msm-bus,name = "gpu_cfg";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 598 0 0>, // off
+ <1 598 0 100>, // min freq
+ <1 598 0 9999999>; // max freq
+ };
+ };
+
+ kgsl_msm_iommu: qcom,kgsl-iommu@3da0000 {
+ compatible = "qcom,kgsl-smmu-v2";
+
+ reg = <0x03da0000 0x10000>;
+ /* CB5(ATOS) & CB5/6/7 are protected by HYP */
+ qcom,protect = <0xa0000 0xc000>;
+
+ clocks =<&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+
+ clock-names = "gcc_gpu_memnoc_gfx",
+ "gcc_gpu_snoc_dvm_gfx",
+ "gpu_cc_ahb", "smmu_vote";
+
+ qcom,secure_align_mask = <0xfff>;
+ qcom,retention;
+ qcom,hyp_secure_alloc;
+
+ gfx3d_user: gfx3d_user {
+ compatible = "qcom,smmu-kgsl-cb";
+ label = "gfx3d_user";
+ iommus = <&kgsl_smmu 0x0 0x401>;
+ qcom,iommu-dma = "disabled";
+ qcom,gpu-offset = <0xa8000>;
+ };
+
+ gfx3d_secure: gfx3d_secure {
+ compatible = "qcom,smmu-kgsl-cb";
+ label = "gfx3d_secure";
+ iommus = <&kgsl_smmu 0x2 0x400>;
+ qcom,iommu-dma = "disabled";
+ };
+ };
+
+ gmu: qcom,gmu@3d6a000 {
+ label = "kgsl-gmu";
+ compatible = "qcom,gpu-gmu";
+
+ reg = <0x3d6a000 0x30000>,
+ <0xb290000 0x10000>,
+ <0xb490000 0x10000>;
+ reg-names = "kgsl_gmu_reg",
+ "kgsl_gmu_pdc_cfg",
+ "kgsl_gmu_pdc_seq";
+
+ interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>,
+ <0 305 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_hfi_irq", "kgsl_gmu_irq";
+
+ qcom,msm-bus,name = "cnoc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <26 10036 0 0>, /* CNOC off */
+ <26 10036 0 100>; /* CNOC on */
+
+ regulator-names = "vddcx", "vdd";
+ vddcx-supply = <&gpu_cx_gdsc>;
+ vdd-supply = <&gpu_gx_gdsc>;
+
+ clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&aopcc QDSS_CLK>;
+
+ clock-names = "gmu_clk", "cxo_clk", "axi_clk",
+ "memnoc_clk", "gpu_cc_ahb", "smmu_vote",
+ "apb_pclk";
+
+ /* AOP mailbox for sending ACD enable and disable messages */
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "aop";
+
+ gmu_user: gmu_user {
+ compatible = "qcom,smmu-gmu-user-cb";
+ iommus = <&kgsl_smmu 0x4 0x400>;
+ qcom,iommu-dma = "disabled";
+ };
+
+ gmu_kernel: gmu_kernel {
+ compatible = "qcom,smmu-gmu-kernel-cb";
+ iommus = <&kgsl_smmu 0x5 0x400>;
+ qcom,iommu-dma = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-ion.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-ion.dtsi
new file mode 100755
index 0000000..6a4835b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-ion.dtsi
@@ -0,0 +1,50 @@
+&soc {
+ qcom,ion {
+ compatible = "qcom,msm-ion";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ system_heap: qcom,ion-heap@25 {
+ reg = <25>;
+ qcom,ion-heap-type = "SYSTEM";
+ };
+
+ system_secure_heap: qcom,ion-heap@9 {
+ reg = <9>;
+ qcom,ion-heap-type = "SYSTEM_SECURE";
+ };
+
+ qcom,ion-heap@22 { /* ADSP HEAP */
+ reg = <22>;
+ memory-region = <&sdsp_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@27 { /* QSEECOM HEAP */
+ reg = <27>;
+ memory-region = <&qseecom_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@19 { /* QSEECOM TA HEAP */
+ reg = <19>;
+ memory-region = <&qseecom_ta_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */
+ reg = <10>;
+ memory-region = <&secure_display_memory>;
+ qcom,ion-heap-type = "HYP_CMA";
+ };
+
+ qcom,ion-heap@14 { /* SECURE CARVEOUT HEAP */
+ reg = <14>;
+ qcom,ion-heap-type = "SECURE_CARVEOUT";
+ cdsp {
+ memory-region = <&cdsp_sec_mem>;
+ token = <0x20000000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-lpi.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-lpi.dtsi
new file mode 100755
index 0000000..d1628d5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-lpi.dtsi
@@ -0,0 +1,1709 @@
+&q6core {
+ lpi_tlmm: lpi_pinctrl@33c0000 {
+ compatible = "qcom,lpi-pinctrl";
+ reg = <0x33c0000 0x0>;
+ qcom,slew-reg = <0x355a000 0x0>;
+ qcom,num-gpios = <15>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
+ <0x00002000>, <0x00003000>,
+ <0x00004000>, <0x00005000>,
+ <0x00006000>, <0x00007000>,
+ <0x00008000>, <0x00009000>,
+ <0x0000A000>, <0x0000B000>,
+ <0x0000C000>, <0x0000D000>,
+ <0x0000E000>;
+ qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>,
+ <0x00000004>, <0x00000008>,
+ <0x0000000A>, <0x0000000C>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000010>, <0x00000012>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>;
+
+ clock-names = "lpass_core_hw_vote",
+ "lpass_audio_hw_vote";
+ clocks = <&lpass_core_hw_vote 0>,
+ <&lpass_audio_hw_vote 0>;
+
+ quat_mi2s_sck {
+ quat_mi2s_sck_sleep: quat_mi2s_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sck_active: quat_mi2s_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_ws {
+ quat_mi2s_ws_sleep: quat_mi2s_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_ws_active: quat_mi2s_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd0 {
+ quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd0_active: quat_mi2s_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd1 {
+ quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd1_active: quat_mi2s_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd2 {
+ quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd2_active: quat_mi2s_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd3 {
+ quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd3_active: quat_mi2s_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sck {
+ lpi_i2s1_sck_sleep: lpi_i2s1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sck_active: lpi_i2s1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_ws {
+ lpi_i2s1_ws_sleep: lpi_i2s1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_ws_active: lpi_i2s1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sd0 {
+ lpi_i2s1_sd0_sleep: lpi_i2s1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sd0_active: lpi_i2s1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sd1 {
+ lpi_i2s1_sd1_sleep: lpi_i2s1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sd1_active: lpi_i2s1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sck {
+ lpi_i2s2_sck_sleep: lpi_i2s2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sck_active: lpi_i2s2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_ws {
+ lpi_i2s2_ws_sleep: lpi_i2s2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_ws_active: lpi_i2s2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sd0 {
+ lpi_i2s2_sd0_sleep: lpi_i2s2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sd0_active: lpi_i2s2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sd1 {
+ lpi_i2s2_sd1_sleep: lpi_i2s2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sd1_active: lpi_i2s2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sck {
+ quat_tdm_sck_sleep: quat_tdm_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sck_active: quat_tdm_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_ws {
+ quat_tdm_ws_sleep: quat_tdm_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_ws_active: quat_tdm_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd0 {
+ quat_tdm_sd0_sleep: quat_tdm_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd0_active: quat_tdm_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd1 {
+ quat_tdm_sd1_sleep: quat_tdm_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd1_active: quat_tdm_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd2 {
+ quat_tdm_sd2_sleep: quat_tdm_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd2_active: quat_tdm_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd3 {
+ quat_tdm_sd3_sleep: quat_tdm_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd3_active: quat_tdm_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sck {
+ lpi_tdm1_sck_sleep: lpi_tdm1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sck_active: lpi_tdm1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_ws {
+ lpi_tdm1_ws_sleep: lpi_tdm1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_ws_active: lpi_tdm1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sd0 {
+ lpi_tdm1_sd0_sleep: lpi_tdm1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sd0_active: lpi_tdm1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sd1 {
+ lpi_tdm1_sd1_sleep: lpi_tdm1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sd1_active: lpi_tdm1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sck {
+ lpi_tdm2_sck_sleep: lpi_tdm2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sck_active: lpi_tdm2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_ws {
+ lpi_tdm2_ws_sleep: lpi_tdm2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_ws_active: lpi_tdm2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sd0 {
+ lpi_tdm2_sd0_sleep: lpi_tdm2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sd0_active: lpi_tdm2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sd1 {
+ lpi_tdm2_sd1_sleep: lpi_tdm2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sd1_active: lpi_tdm2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sck {
+ quat_aux_sck_sleep: quat_aux_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sck_active: quat_aux_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_ws {
+ quat_aux_ws_sleep: quat_aux_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_ws_active: quat_aux_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd0 {
+ quat_aux_sd0_sleep: quat_aux_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd0_active: quat_aux_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd1 {
+ quat_aux_sd1_sleep: quat_aux_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd1_active: quat_aux_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd2 {
+ quat_aux_sd2_sleep: quat_aux_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd2_active: quat_aux_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd3 {
+ quat_aux_sd3_sleep: quat_aux_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd3_active: quat_aux_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sck {
+ lpi_aux1_sck_sleep: lpi_aux1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sck_active: lpi_aux1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_ws {
+ lpi_aux1_ws_sleep: lpi_aux1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_ws_active: lpi_aux1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sd0 {
+ lpi_aux1_sd0_sleep: lpi_aux1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sd0_active: lpi_aux1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sd1 {
+ lpi_aux1_sd1_sleep: lpi_aux1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sd1_active: lpi_aux1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sck {
+ lpi_aux2_sck_sleep: lpi_aux2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sck_active: lpi_aux2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_ws {
+ lpi_aux2_ws_sleep: lpi_aux2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_ws_active: lpi_aux2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sd0 {
+ lpi_aux2_sd0_sleep: lpi_aux2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sd0_active: lpi_aux2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sd1 {
+ lpi_aux2_sd1_sleep: lpi_aux2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sd1_active: lpi_aux2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ wsa_swr_clk_pin {
+ wsa_swr_clk_sleep: wsa_swr_clk_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ wsa_swr_clk_active: wsa_swr_clk_active {
+ mux {
+ pins = "gpio10";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+ };
+ };
+
+ wsa_swr_data_pin {
+ wsa_swr_data_sleep: wsa_swr_data_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ wsa_swr_data_active: wsa_swr_data_active {
+ mux {
+ pins = "gpio11";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+ };
+
+ tx_swr_clk_sleep: tx_swr_clk_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func1";
+ input-enable;
+ bias-pull-down;
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>;
+ };
+ };
+
+ tx_swr_clk_active: tx_swr_clk_active {
+ mux {
+ pins = "gpio0";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+ };
+
+ tx_swr_data1_sleep: tx_swr_data1_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>;
+ input-enable;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_data1_active: tx_swr_data1_active {
+ mux {
+ pins = "gpio1";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_data2_sleep: tx_swr_data2_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ tx_swr_data2_active: tx_swr_data2_active {
+ mux {
+ pins = "gpio2";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_data3_sleep: tx_swr_data3_sleep {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ tx_swr_data3_active: tx_swr_data3_active {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_clk_sleep: rx_swr_clk_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_clk_active: rx_swr_clk_active {
+ mux {
+ pins = "gpio3";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-disable;
+ };
+ };
+
+ rx_swr_data_sleep: rx_swr_data_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_data_active: rx_swr_data_active {
+ mux {
+ pins = "gpio4";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_data1_sleep: rx_swr_data1_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_data1_active: rx_swr_data1_active {
+ mux {
+ pins = "gpio5";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>;
+ slew-rate = <1>;
+ bias-bus-hold;
+ };
+ };
+
+ cdc_dmic01_clk_active: dmic01_clk_active {
+ mux {
+ pins = "gpio6";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic01_clk_sleep: dmic01_clk_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic01_data_active: dmic01_data_active {
+ mux {
+ pins = "gpio7";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic01_data_sleep: dmic01_data_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ cdc_dmic23_clk_active: dmic23_clk_active {
+ mux {
+ pins = "gpio8";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic23_clk_sleep: dmic23_clk_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic23_data_active: dmic23_data_active {
+ mux {
+ pins = "gpio9";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic23_data_sleep: dmic23_data_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ cdc_dmic45_clk_active: dmic45_clk_active {
+ mux {
+ pins = "gpio12";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic45_clk_sleep: dmic45_clk_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic45_data_active: dmic45_data_active {
+ mux {
+ pins = "gpio13";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic45_data_sleep: dmic45_data_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-mtp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lito-mtp-overlay.dts
new file mode 100755
index 0000000..249ab6f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-mtp-overlay.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lito-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito MTP";
+ compatible = "qcom,lito-mtp", "qcom,lito", "qcom,mtp";
+ qcom,msm-id = <400 0x10000>, <440 0x10000>;
+ qcom,board-id = <8 0>;
+};
+
+&ufsphy_mem {
+ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/lito-mtp.dts
new file mode 100755
index 0000000..f62ee55
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-mtp.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+#include "lito.dtsi"
+#include "lito-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito MTP";
+ compatible = "qcom,lito-mtp", "qcom,lito", "qcom,mtp";
+ qcom,board-id = <8 0>;
+};
+
+&ufsphy_mem {
+ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-mtp.dtsi
new file mode 100755
index 0000000..7af7be2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-mtp.dtsi
@@ -0,0 +1,339 @@
+#include <dt-bindings/gpio/gpio.h>
+#include "lito-audio-overlay.dtsi"
+#include "lito-pmic-overlay.dtsi"
+#include "camera/lito-camera-sensor-mtp.dtsi"
+#include "lito-sde-display.dtsi"
+#include "lito-thermal-overlay.dtsi"
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm8150l_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+
+ vdda_usb_ss_dp_core: vdda_usb_ss_dp_core {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_supply";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ enable-active-high;
+ gpio = <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_eldo13>;
+ };
+
+ mtp_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "qg-batterydata-alium-3600mah.dtsi"
+ #include "qg-batterydata-atl466271_3300mAh.dtsi"
+ };
+};
+
+&usb_qmp_dp_phy {
+ vdd-supply = <&vdda_usb_ss_dp_core>;
+};
+
+&sde_dp {
+ vdda-0p9-supply = <&vdda_usb_ss_dp_core>;
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v4-lito";
+
+ vdda-phy-supply = <&pm8150_l5>;
+ vdda-pll-supply = <&pm8150_l9>;
+ vdda-phy-max-microamp = <90200>;
+ vdda-pll-max-microamp = <19000>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm8150a_l7>;
+ vcc-voltage-level = <2950000 2960000>;
+ vccq2-supply = <&pm8150_s4>;
+ vcc-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+ vccq2-min-microamp = <0>;
+
+ qcom,vddp-ref-clk-supply = <&pm8150_l9>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vddp-ref-clk-min-microamp = <0>;
+ qcom,vddp-ref-clk-min-uV = <1152000>;
+ qcom,vddp-ref-clk-max-uV = <1200000>;
+ status = "ok";
+};
+
+&sdhc_1 {
+ vdd-supply = <&pm8150a_l7>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&pm8150_s4>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&pm8150a_l9>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&pm8150a_l6>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 69 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&pm8150a_amoled {
+ status = "ok";
+};
+
+&pm7250b_vadc {
+ pinctrl-0 = <
+ &bmr_w_therm_default
+ &camera_therm_default
+ &bmr_s_therm_default
+ >;
+
+ bmr_s_therm {
+ reg = <ADC_GPIO3_PU2>;
+ label = "bmr_s_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm7250b_gpios {
+ bmr_s_therm {
+ bmr_s_therm_default: bmr_s_therm_default {
+ pins = "gpio5";
+ bias-high-impedance;
+ };
+ };
+};
+
+&pm7250b_adc_tm {
+ io-channels = <&pm7250b_vadc ADC_AMUX_THM1_PU2>,
+ <&pm7250b_vadc ADC_GPIO2_PU2>,
+ <&pm7250b_vadc ADC_GPIO3_PU2>,
+ <&pm7250b_vadc ADC_GPIO4_PU2>;
+
+ bmr_s_therm@54 {
+ reg = <ADC_GPIO3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&thermal_zones {
+ mmw-pa4-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm7250b_adc_tm ADC_GPIO3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&pm7250b_charger {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+ <&pm7250b_vadc ADC_USB_IN_I>,
+ <&pm7250b_vadc ADC_CHG_TEMP>,
+ <&pm7250b_vadc ADC_DIE_TEMP>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+ <&pm7250b_vadc ADC_SBUx>,
+ <&pm7250b_vadc ADC_VPH_PWR>,
+ <&pm7250b_vadc ADC_AMUX_THM1_PU2>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp",
+ "die_temp",
+ "conn_temp",
+ "sbux_res",
+ "vph_voltage",
+ "skin_temp";
+ qcom,battery-data = <&mtp_batterydata>;
+ qcom,sec-charger-config = <1>;
+ qcom,auto-recharge-soc = <98>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,fcc-stepping-enable;
+ qcom,fcc-step-delay-ms = <100>;
+ qcom,fcc-step-size-ua = <100000>;
+ qcom,smb-internal-pull-kohm = <0>;
+ qcom,en-skin-therm-mitigation;
+ qcom,hvdcp3-standalone-config;
+};
+
+&pm7250b_qg {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU2>,
+ <&pm7250b_vadc ADC_BAT_ID_PU2>;
+ io-channel-names = "batt-therm",
+ "batt-id";
+ qcom,battery-data = <&mtp_batterydata>;
+ qcom,qg-iterm-ma = <100>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+ qcom,tcss-enable;
+ qcom,fvss-enable;
+ qcom,fvss-vbatt-mv = <3300>;
+ qcom,bass-enable;
+};
+
+&qupv3_se7_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "ok";
+ qcom,i2c-touch-active = "st,fts";
+
+ st_fts@49 {
+ compatible = "st,fts";
+ reg = <0x49>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 0x2008>;
+ vdd-supply = <&pm8150_s4>;
+ avdd-supply = <&pm8150_l13>;
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ st,irq-gpio = <&tlmm 9 0x2008>;
+ st,reset-gpio = <&tlmm 8 0x00>;
+ st,regulator_dvdd = "vdd";
+ st,regulator_avdd = "avdd";
+ st,x-flip = <1>;
+ st,y-flip = <1>;
+ st,power_on_suspend;
+ panel = <&dsi_sw43404_amoled_cmd &dsi_sw43404_amoled_video
+ &dsi_sw43404_amoled_fhd_plus_cmd>;
+ };
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_video>;
+};
+
+&qupv3_se0_i2c {
+ status = "ok";
+ qcom,clk-freq-out = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 34 0x00>;
+ qcom,nq-ven = <&tlmm 12 0x00>;
+ qcom,nq-firm = <&tlmm 35 0x00>;
+ qcom,nq-clkreq = <&tlmm 31 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <34 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_dual_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-npu.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-npu.dtsi
new file mode 100755
index 0000000..4ff1ec3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-npu.dtsi
@@ -0,0 +1,273 @@
+&soc {
+ msm_npu: qcom,msm_npu@9800000 {
+ compatible = "qcom,msm-npu";
+ status = "ok";
+ reg = <0x9900000 0x20000>,
+ <0x99F0000 0x10000>,
+ <0x9980000 0x10000>,
+ <0x17c00000 0x10000>,
+ <0x01F40000 0x40000>,
+ <0x780000 0x7000>;
+ reg-names = "tcm", "core", "cc", "apss_shared", "tcsr",
+ "qfprom_physical";
+ interrupts = <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error_irq", "wdg_bite_irq", "ipc_irq",
+ "general_irq";
+ iommus = <&apps_smmu 0x1861 0x400>, <&apps_smmu 0x1862 0x400>,
+ <&apps_smmu 0x1881 0x400>, <&apps_smmu 0x1882 0x400>;
+ qcom,npu-dsp-sid-mapped;
+
+ clocks = <&npucc NPU_CC_XO_CLK>,
+ <&npucc NPU_CC_CORE_CLK>,
+ <&npucc NPU_CC_CAL_HM0_CLK>,
+ <&npucc NPU_CC_CAL_HM0_CDC_CLK>,
+ <&npucc NPU_CC_NOC_AXI_CLK>,
+ <&npucc NPU_CC_NOC_AHB_CLK>,
+ <&npucc NPU_CC_NOC_DMA_CLK>,
+ <&npucc NPU_CC_LLM_CLK>,
+ <&npucc NPU_CC_LLM_XO_CLK>,
+ <&npucc NPU_CC_LLM_TEMP_CLK>,
+ <&npucc NPU_CC_LLM_CURR_CLK>,
+ <&npucc NPU_CC_DL_LLM_CLK>,
+ <&npucc NPU_CC_ISENSE_CLK>,
+ <&npucc NPU_CC_DPM_CLK>,
+ <&npucc NPU_CC_DPM_XO_CLK>,
+ <&npucc NPU_CC_DL_DPM_CLK>,
+ <&npucc NPU_CC_RSC_XO_CLK>,
+ <&npucc NPU_CC_DPM_TEMP_CLK>,
+ <&npucc NPU_CC_CAL_HM0_DPM_IP_CLK>,
+ <&npucc NPU_CC_S2P_CLK>,
+ <&npucc NPU_CC_BWMON_CLK>,
+ <&npucc NPU_CC_CAL_HM0_PERF_CNT_CLK>,
+ <&npucc NPU_CC_BTO_CORE_CLK>,
+ <&npucc NPU_DSP_CORE_CLK_SRC>;
+ clock-names = "xo_clk",
+ "npu_core_clk",
+ "cal_hm0_clk",
+ "cal_hm0_cdc_clk",
+ "axi_clk",
+ "ahb_clk",
+ "dma_clk",
+ "llm_clk",
+ "llm_xo_clk",
+ "llm_temp_clk",
+ "llm_curr_clk",
+ "dl_llm_clk",
+ "isense_clk",
+ "dpm_clk",
+ "dpm_xo_clk",
+ "dl_dpm_clk",
+ "rsc_xo_clk",
+ "dpm_temp_clk",
+ "cal_hm0_dpm_ip_clk",
+ "s2p_clk",
+ "bwmon_clk",
+ "cal_hm0_perf_cnt_clk",
+ "bto_core_clk",
+ "dsp_core_clk_src";
+
+ vdd-supply = <&npu_core_gdsc>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,proxy-reg-names ="vdd", "vdd_cx";
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+ resets = <&npucc NPU_CC_DPM_TEMP_CLK_ARES>,
+ <&npucc NPU_CC_LLM_CURR_CLK_ARES>,
+ <&npucc NPU_CC_LLM_TEMP_CLK_ARES>;
+ reset-names = "dpm_temp_clk", "llm_curr_clk", "llm_temp_clk";
+ #cooling-cells = <2>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_GLINK_QMP>,
+ <&ipcc_mproc IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_SMP2P>,
+ <&ipcc_mproc IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_PING>;
+ mbox-names = "ipcc-glink", "ipcc-smp2p", "ipcc-ping";
+ #mbox-cells = <2>;
+ qcom,npubw-devs = <&npu_npu_llcc_bw &npu_llcc_ddr_bw &npudsp_npu_ddr_bw>;
+ qcom,npubw-dev-names = "npu_llcc_bw", "llcc_ddr_bw", "dsp_ddr_bw";
+ qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>,
+ <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_CLK_CTL>;
+ qcom,npu-pwrlevels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,npu-pwrlevels";
+ initial-pwrlevel = <5>;
+ qcom,npu-pwrlevel@0 {
+ reg = <0>;
+ vreg = <1>;
+ clk-freq = <19200000
+ 100000000
+ 230000000
+ 230000000
+ 150000000
+ 40000000
+ 300000000
+ 100000000
+ 19200000
+ 50000000
+ 50000000
+ 100000000
+ 100000000
+ 100000000
+ 19200000
+ 100000000
+ 19200000
+ 50000000
+ 230000000
+ 50000000
+ 19200000
+ 230000000
+ 19200000
+ 300000000>;
+ };
+
+ qcom,npu-pwrlevel@1 {
+ reg = <1>;
+ vreg = <2>;
+ clk-freq = <19200000
+ 200000000
+ 422000000
+ 422000000
+ 207000000
+ 40000000
+ 403000000
+ 200000000
+ 19200000
+ 50000000
+ 50000000
+ 200000000
+ 200000000
+ 200000000
+ 19200000
+ 200000000
+ 19200000
+ 50000000
+ 422000000
+ 50000000
+ 19200000
+ 422000000
+ 19200000
+ 400000000>;
+ };
+
+ qcom,npu-pwrlevel@2 {
+ reg = <2>;
+ vreg = <3>;
+ clk-freq = <19200000
+ 333000000
+ 557000000
+ 557000000
+ 300000000
+ 75000000
+ 533000000
+ 214000000
+ 19200000
+ 50000000
+ 100000000
+ 214000000
+ 214000000
+ 214000000
+ 19200000
+ 214000000
+ 19200000
+ 50000000
+ 557000000
+ 50000000
+ 19200000
+ 557000000
+ 19200000
+ 500000000>;
+ };
+
+ qcom,npu-pwrlevel@3 {
+ reg = <3>;
+ vreg = <4>;
+ clk-freq = <19200000
+ 428000000
+ 729000000
+ 729000000
+ 403000000
+ 75000000
+ 700000000
+ 300000000
+ 19200000
+ 100000000
+ 200000000
+ 300000000
+ 300000000
+ 300000000
+ 19200000
+ 300000000
+ 19200000
+ 100000000
+ 729000000
+ 100000000
+ 19200000
+ 729000000
+ 19200000
+ 660000000>;
+ };
+
+ qcom,npu-pwrlevel@4 {
+ reg = <4>;
+ vreg = <6>;
+ clk-freq = <19200000
+ 500000000
+ 844000000
+ 844000000
+ 533000000
+ 75000000
+ 806000000
+ 300000000
+ 19200000
+ 100000000
+ 200000000
+ 300000000
+ 300000000
+ 300000000
+ 19200000
+ 300000000
+ 19200000
+ 100000000
+ 844000000
+ 100000000
+ 19200000
+ 844000000
+ 19200000
+ 800000000>;
+ };
+
+ qcom,npu-pwrlevel@5 {
+ reg = <5>;
+ vreg = <7>;
+ clk-freq = <19200000
+ 500000000
+ 1000000000
+ 1000000000
+ 533000000
+ 75000000
+ 806000000
+ 300000000
+ 19200000
+ 100000000
+ 200000000
+ 300000000
+ 300000000
+ 300000000
+ 19200000
+ 300000000
+ 19200000
+ 100000000
+ 1000000000
+ 100000000
+ 19200000
+ 1000000000
+ 19200000
+ 800000000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-pinctrl.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-pinctrl.dtsi
new file mode 100755
index 0000000..8beb70e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-pinctrl.dtsi
@@ -0,0 +1,1873 @@
+&soc {
+ tlmm: pinctrl@f000000 {
+ compatible = "qcom,lito-pinctrl";
+ reg = <0x0f000000 0x1000000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ wakeup-parent = <&pdc>;
+ irqdomain-map = <0 0 &pdc 58 0>,
+ <3 0 &pdc 44 0>,
+ <4 0 &pdc 80 0>,
+ <5 0 &pdc 89 0>,
+ <6 0 &pdc 52 0>,
+ <9 0 &pdc 104 0>,
+ <10 0 &pdc 54 0>,
+ <11 0 &pdc 62 0>,
+ <22 0 &pdc 64 0>,
+ <24 0 &pdc 82 0>,
+ <26 0 &pdc 56 0>,
+ <30 0 &pdc 84 0>,
+ <31 0 &pdc 43 0>,
+ <32 0 &pdc 79 0>,
+ <33 0 &pdc 66 0>,
+ <34 0 &pdc 53 0>,
+ <36 0 &pdc 92 0>,
+ <37 0 &pdc 63 0>,
+ <38 0 &pdc 73 0>,
+ <39 0 &pdc 76 0>,
+ <41 0 &pdc 81 0>,
+ <42 0 &pdc 94 0>,
+ <43 0 &pdc 55 0>,
+ <45 0 &pdc 83 0>,
+ <46 0 &pdc 57 0>,
+ <47 0 &pdc 86 0>,
+ <48 0 &pdc 121 0>,
+ <49 0 &pdc 87 0>,
+ <50 0 &pdc 90 0>,
+ <52 0 &pdc 72 0>,
+ <53 0 &pdc 96 0>,
+ <55 0 &pdc 91 0>,
+ <56 0 &pdc 135 0>,
+ <57 0 &pdc 137 0>,
+ <58 0 &pdc 93 0>,
+ <59 0 &pdc 136 0>,
+ <62 0 &pdc 97 0>,
+ <64 0 &pdc 65 0>,
+ <65 0 &pdc 75 0>,
+ <66 0 &pdc 98 0>,
+ <67 0 &pdc 99 0>,
+ <68 0 &pdc 100 0>,
+ <69 0 &pdc 46 0>,
+ <70 0 &pdc 85 0>,
+ <72 0 &pdc 50 0>,
+ <73 0 &pdc 45 0>,
+ <74 0 &pdc 101 0>,
+ <78 0 &pdc 42 0>,
+ <82 0 &pdc 88 0>,
+ <83 0 &pdc 51 0>,
+ <84 0 &pdc 102 0>,
+ <85 0 &pdc 113 0>,
+ <86 0 &pdc 95 0>,
+ <87 0 &pdc 103 0>,
+ <88 0 &pdc 114 0>,
+ <90 0 &pdc 105 0>,
+ <97 0 &pdc 70 0>,
+ <98 0 &pdc 106 0>,
+ <100 0 &pdc 59 0>,
+ <103 0 &pdc 60 0>,
+ <105 0 &pdc 71 0>,
+ <107 0 &pdc 78 0>,
+ <108 0 &pdc 61 0>,
+ <109 0 &pdc 134 0>,
+ <110 0 &pdc 48 0>,
+ <111 0 &pdc 67 0>,
+ <112 0 &pdc 68 0>,
+ <113 0 &pdc 77 0>,
+ <114 0 &pdc 69 0>,
+ <115 0 &pdc 133 0>,
+ <116 0 &pdc 109 0>,
+ <117 0 &pdc 120 0>,
+ <119 0 &pdc 110 0>,
+ <121 0 &pdc 119 0>,
+ <122 0 &pdc 112 0>,
+ <124 0 &pdc 107 0>,
+ <126 0 &pdc 111 0>,
+ <127 0 &pdc 116 0>,
+ <128 0 &pdc 132 0>,
+ <133 0 &pdc 131 0>,
+ <135 0 &pdc 130 0>,
+ <138 0 &pdc 129 0>,
+ <139 0 &pdc 128 0>,
+ <140 0 &pdc 127 0>,
+ <141 0 &pdc 126 0>,
+ <142 0 &pdc 125 0>,
+ <144 0 &pdc 122 0>;
+ irqdomain-map-mask = <0xff 0>;
+ irqdomain-map-pass-thru = <0 0xff>;
+
+
+ trigout_a: trigout_a {
+ mux {
+ pins = "gpio63";
+ function = "qdss_cti";
+ };
+
+ config {
+ pins = "gpio63";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se2_2uart_pins: qupv3_se2_2uart_pins {
+ qupv3_se2_2uart_active: qupv3_se2_2uart_active {
+ mux {
+ pins = "gpio36", "gpio37";
+ function = "qup02";
+ };
+
+ config {
+ pins = "gpio36", "gpio37";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se2_2uart_sleep: qupv3_se2_2uart_sleep {
+ mux {
+ pins = "gpio36", "gpio37";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio36", "gpio37";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ qupv3_se5_4uart_pins: qupv3_se5_4uart_pins {
+ qupv3_se5_ctsrx: qupv3_se5_ctsrx {
+ mux {
+ pins = "gpio38", "gpio41";
+ function = "qup05";
+ };
+
+ config {
+ pins = "gpio38", "gpio41";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se5_rts: qupv3_se5_rts {
+ mux {
+ pins = "gpio39";
+ function = "qup05";
+ };
+
+ config {
+ pins = "gpio39";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ qupv3_se5_tx: qupv3_se5_tx {
+ mux {
+ pins = "gpio40";
+ function = "qup05";
+ };
+
+ config {
+ pins = "gpio40";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ qupv3_se8_2uart_pins: qupv3_se8_2uart_pins {
+ qupv3_se8_2uart_active: qupv3_se8_2uart_active {
+ mux {
+ pins = "gpio51", "gpio52";
+ function = "qup12";
+ };
+
+ config {
+ pins = "gpio51", "gpio52";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se8_2uart_sleep: qupv3_se8_2uart_sleep {
+ mux {
+ pins = "gpio51", "gpio52";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio51", "gpio52";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ qupv3_se0_i3c_pins: qupv3_se0_i3c_pins {
+ qupv3_se0_i3c_active: qupv3_se0_i3c_active {
+ mux {
+ pins = "gpio42", "gpio43";
+ function = "ibi_i3c";
+ };
+
+ config {
+ pins = "gpio42", "gpio43";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se0_i3c_sleep: qupv3_se0_i3c_sleep {
+ mux {
+ pins = "gpio42", "gpio43";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio42", "gpio43";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se6_i3c_pins: qupv3_se6_i3c_pins {
+ qupv3_se6_i3c_active: qupv3_se6_i3c_active {
+ mux {
+ pins = "gpio59", "gpio60";
+ function = "ibi_i3c";
+ };
+
+ config {
+ pins = "gpio59", "gpio60";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se6_i3c_sleep: qupv3_se6_i3c_sleep {
+ mux {
+ pins = "gpio59", "gpio60";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio59", "gpio60";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ ufs_dev_reset_assert: ufs_dev_reset_assert {
+ config {
+ pins = "ufs_reset";
+ bias-pull-down; /* default: pull down */
+ /*
+ * UFS_RESET driver strengths are having
+ * different values/steps compared to typical
+ * GPIO drive strengths.
+ *
+ * Following table clarifies:
+ *
+ * HDRV value | UFS_RESET | Typical GPIO
+ * (dec) | (mA) | (mA)
+ * 0 | 0.8 | 2
+ * 1 | 1.55 | 4
+ * 2 | 2.35 | 6
+ * 3 | 3.1 | 8
+ * 4 | 3.9 | 10
+ * 5 | 4.65 | 12
+ * 6 | 5.4 | 14
+ * 7 | 6.15 | 16
+ *
+ * POR value for UFS_RESET HDRV is 3 which means
+ * 3.1mA and we want to use that. Hence just
+ * specify 8mA to "drive-strength" binding and
+ * that should result into writing 3 to HDRV
+ * field.
+ */
+ drive-strength = <8>; /* default: 3.1 mA */
+ output-low; /* active low reset */
+ };
+ };
+
+ ufs_dev_reset_deassert: ufs_dev_reset_deassert {
+ config {
+ pins = "ufs_reset";
+ bias-pull-down; /* default: pull down */
+ /*
+ * default: 3.1 mA
+ * check comments under ufs_dev_reset_assert
+ */
+ drive-strength = <8>;
+ output-high; /* active low reset */
+ };
+ };
+
+ /* SDC pin type */
+ sdc1_clk_on: sdc1_clk_on {
+ config {
+ pins = "sdc1_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc1_clk_off: sdc1_clk_off {
+ config {
+ pins = "sdc1_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_cmd_on: sdc1_cmd_on {
+ config {
+ pins = "sdc1_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc1_cmd_off: sdc1_cmd_off {
+ config {
+ pins = "sdc1_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_data_on: sdc1_data_on {
+ config {
+ pins = "sdc1_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc1_data_off: sdc1_data_off {
+ config {
+ pins = "sdc1_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_rclk_on: sdc1_rclk_on {
+ config {
+ pins = "sdc1_rclk";
+ bias-pull-down; /* pull down */
+ };
+ };
+
+ sdc1_rclk_off: sdc1_rclk_off {
+ config {
+ pins = "sdc1_rclk";
+ bias-pull-down; /* pull down */
+ };
+ };
+
+ sdc2_clk_on: sdc2_clk_on {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_clk_off: sdc2_clk_off {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_cmd_on: sdc2_cmd_on {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_cmd_off: sdc2_cmd_off {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_data_on: sdc2_data_on {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_data_off: sdc2_data_off {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_cd_on: cd_on {
+ mux {
+ pins = "gpio69";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio69";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_cd_off: cd_off {
+ mux {
+ pins = "gpio69";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio69";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ /* WSA speaker reset pins */
+ spkr_1_sd_n {
+ spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+ mux {
+ pins = "gpio58";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio58";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_1_sd_n_active: spkr_1_sd_n_active {
+ mux {
+ pins = "gpio58";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio58";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ spkr_2_sd_n {
+ spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
+ mux {
+ pins = "gpio65";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio65";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_2_sd_n_active: spkr_2_sd_n_active {
+ mux {
+ pins = "gpio65";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio65";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ wcd938x_reset_active: wcd938x_reset_active {
+ mux {
+ pins = "gpio57";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio57";
+ drive-strength = <16>;
+ output-high;
+ };
+ };
+
+ wcd938x_reset_sleep: wcd938x_reset_sleep {
+ mux {
+ pins = "gpio57";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio57";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ /* Camera GPIOs CCI*/
+ cci0_active: cci0_active {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio17", "gpio18";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio17", "gpio18";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci0_suspend: cci0_suspend {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio17", "gpio18";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio17", "gpio18";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci1_active: cci1_active {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio19", "gpio20";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci1_suspend: cci1_suspend {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio19", "gpio20";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio19", "gpio20";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci2_active: cci2_active {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio27", "gpio28";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio27", "gpio28";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci2_suspend: cci2_suspend {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio27", "gpio28";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio27", "gpio28";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ /* Camera GPIOs CCI*/
+ cam_sensor_mclk0_active: cam_sensor_mclk0_active {
+ /* MCLK0 */
+ mux {
+ pins = "gpio13";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio13";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
+ /* MCLK0 */
+ mux {
+ pins = "gpio13";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio13";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk1_active: cam_sensor_mclk1_active {
+ /* MCLK1 */
+ mux {
+ pins = "gpio14";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio14";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
+ /* MCLK1 */
+ mux {
+ pins = "gpio14";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio14";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk2_active: cam_sensor_mclk2_active {
+ /* MCLK2 */
+ mux {
+ pins = "gpio15";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio15";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
+ /* MCLK2 */
+ mux {
+ pins = "gpio15";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio15";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk3_active: cam_sensor_mclk3_active {
+ /* MCLK3 */
+ mux {
+ pins = "gpio16";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio16";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend {
+ /* MCLK3 */
+ mux {
+ pins = "gpio16";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio16";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk4_active: cam_sensor_mclk4_active {
+ /* MCLK4 */
+ mux {
+ pins = "gpio25";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio25";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend {
+ /* MCLK4 */
+ mux {
+ pins = "gpio25";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio25";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_active_rear: cam_sensor_active_rear {
+ /* RESET REAR2 */
+ mux {
+ pins = "gpio30";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio30";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_rear: cam_sensor_suspend_rear {
+ /* RESET REAR2 */
+ mux {
+ pins = "gpio30";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio30";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_rear_aux: cam_sensor_active_rear_aux {
+ /* RESET REARAUX,DVDD ELDO */
+ mux {
+ pins = "gpio29", "gpio71";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio29", "gpio71";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_rear_aux: cam_sensor_suspend_rear_aux {
+ /* RESET REARAUX,DVDD ELDO */
+ mux {
+ pins = "gpio29", "gpio71";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio29", "gpio71";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_triple_rear_aux:
+ cam_sensor_active_triple_rear_aux {
+ /* RESET REARAUX,AVDD ELDO */
+ mux {
+ pins = "gpio29", "gpio70";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio29", "gpio70";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_triple_rear_aux:
+ cam_sensor_suspend_triple_rear_aux {
+ /* RESET REARAUX,AVDD ELDO */
+ mux {
+ pins = "gpio29", "gpio70";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio29", "gpio70";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_rear_aux2: cam_sensor_active_rear_aux2 {
+ /* RESET REARAUX2,CSI MUX Sel */
+ mux {
+ pins = "gpio21", "gpio51";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio21", "gpio51";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_rear_aux2: cam_sensor_suspend_rear_aux2 {
+ /* RESET REARAUX2, CSI MUX Sel */
+ mux {
+ pins = "gpio21", "gpio51";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio21", "gpio51";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_3: cam_sensor_active_3 {
+ /* RESET TOF */
+ mux {
+ pins = "gpio23";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio23";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_3: cam_sensor_suspend_3 {
+ /* RESET TOF */
+ mux {
+ pins = "gpio23";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio23";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_active_front: cam_sensor_active_front {
+ /* RESET FRONT */
+ mux {
+ pins = "gpio32";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio32";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_suspend_front: cam_sensor_suspend_front {
+ /* RESET FRONT */
+ mux {
+ pins = "gpio32";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio32";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ /* QUPv3_0 North SE mappings */
+ /* SE 0 pin mappings */
+ qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
+ qupv3_se0_i2c_active: qupv3_se0_i2c_active {
+ mux {
+ pins = "gpio42", "gpio43";
+ function = "qup00";
+ };
+
+ config {
+ pins = "gpio42", "gpio43";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
+ mux {
+ pins = "gpio42", "gpio43";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio42", "gpio43";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ nfc {
+ nfc_int_active: nfc_int_active {
+ /* active state */
+ mux {
+ /* GPIO 34 NFC Read Interrupt */
+ pins = "gpio34";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio34";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_int_suspend: nfc_int_suspend {
+ /* sleep state */
+ mux {
+ /* GPIO 34 NFC Read Interrupt */
+ pins = "gpio34";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio34";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_enable_active: nfc_enable_active {
+ /* active state */
+ mux {
+ /* 12: Enable 35: Firmware */
+ pins = "gpio12", "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio12", "gpio35";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_enable_suspend: nfc_enable_suspend {
+ /* sleep state */
+ mux {
+ /* 12: Enable 35: Firmware */
+ pins = "gpio12", "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio12", "gpio35";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable;
+ };
+ };
+
+ nfc_clk_req_active: nfc_clk_req_active {
+ /* active state */
+ mux {
+ /* GPIO 31: NFC CLOCK REQUEST */
+ pins = "gpio31";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio31";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_clk_req_suspend: nfc_clk_req_suspend {
+ /* sleep state */
+ mux {
+ /* GPIO 31: NFC CLOCK REQUEST */
+ pins = "gpio31";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio31";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable;
+ };
+ };
+ };
+
+ /* SE 1 pin mappings */
+ qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
+ qupv3_se1_i2c_active: qupv3_se1_i2c_active {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "qup01";
+ };
+
+ config {
+ pins = "gpio0", "gpio1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio0", "gpio1";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 2 pin mappings */
+ qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
+ qupv3_se2_i2c_active: qupv3_se2_i2c_active {
+ mux {
+ pins = "gpio34", "gpio35";
+ function = "qup02";
+ };
+
+ config {
+ pins = "gpio34", "gpio35";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
+ mux {
+ pins = "gpio34", "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio34", "gpio35";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 4 pin mappings */
+ qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
+ qupv3_se4_i2c_active: qupv3_se4_i2c_active {
+ mux {
+ pins = "gpio31", "gpio32";
+ function = "qup04";
+ };
+
+ config {
+ pins = "gpio31", "gpio32";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
+ mux {
+ pins = "gpio31", "gpio32";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio31", "gpio32";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 5 pin mappings */
+ qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
+ qupv3_se5_i2c_active: qupv3_se5_i2c_active {
+ mux {
+ pins = "gpio38", "gpio39";
+ function = "qup05";
+ };
+
+ config {
+ pins = "gpio38", "gpio39";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
+ mux {
+ pins = "gpio38", "gpio39";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio38", "gpio39";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* QUPv3_1 South_1 SE mappings */
+ /* SE 6 pin mappings */
+ qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
+ qupv3_se6_i2c_active: qupv3_se6_i2c_active {
+ mux {
+ pins = "gpio59", "gpio60";
+ function = "qup10";
+ };
+
+ config {
+ pins = "gpio59", "gpio60";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
+ mux {
+ pins = "gpio59", "gpio60";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio59", "gpio60";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 7 pin mappings */
+ qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
+ qupv3_se7_i2c_active: qupv3_se7_i2c_active {
+ mux {
+ pins = "gpio6", "gpio7";
+ function = "qup11";
+ };
+
+ config {
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
+ mux {
+ pins = "gpio6", "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 8 pin mappings */
+ qupv3_se8_i2c_pins: qupv3_se8_i2c_pins {
+ qupv3_se8_i2c_active: qupv3_se8_i2c_active {
+ mux {
+ pins = "gpio49", "gpio50";
+ function = "qup12";
+ };
+
+ config {
+ pins = "gpio49", "gpio50";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep {
+ mux {
+ pins = "gpio49", "gpio50";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio49", "gpio50";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 9 pin mappings */
+ qupv3_se9_i2c_pins: qupv3_se9_i2c_pins {
+ qupv3_se9_i2c_active: qupv3_se9_i2c_active {
+ mux {
+ pins = "gpio46", "gpio47";
+ function = "qup13";
+ };
+
+ config {
+ pins = "gpio46", "gpio47";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se9_i2c_sleep: qupv3_se9_i2c_sleep {
+ mux {
+ pins = "gpio46", "gpio47";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio46", "gpio47";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 10 pin mappings */
+ qupv3_se10_i2c_pins: qupv3_se10_i2c_pins {
+ qupv3_se10_i2c_active: qupv3_se10_i2c_active {
+ mux {
+ pins = "gpio53", "gpio54";
+ function = "qup14";
+ };
+
+ config {
+ pins = "gpio53", "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep {
+ mux {
+ pins = "gpio53", "gpio54";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio53", "gpio54";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ /* SE 11 pin mappings */
+ qupv3_se11_i2c_pins: qupv3_se11_i2c_pins {
+ qupv3_se11_i2c_active: qupv3_se11_i2c_active {
+ mux {
+ pins = "gpio108", "gpio109";
+ function = "qup15";
+ };
+
+ config {
+ pins = "gpio108", "gpio109";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se11_i2c_sleep: qupv3_se11_i2c_sleep {
+ mux {
+ pins = "gpio108", "gpio109";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio108", "gpio109";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ qupv3_se0_spi_pins: qupv3_se0_spi_pins {
+ qupv3_se0_spi_active: qupv3_se0_spi_active {
+ mux {
+ pins = "gpio42", "gpio43", "gpio44",
+ "gpio45";
+ function = "qup00";
+ };
+
+ config {
+ pins = "gpio42", "gpio43", "gpio44",
+ "gpio45";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
+ mux {
+ pins = "gpio42", "gpio43", "gpio44",
+ "gpio45";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio42", "gpio43", "gpio44",
+ "gpio45";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se1_spi_pins: qupv3_se1_spi_pins {
+ qupv3_se1_spi_active: qupv3_se1_spi_active {
+ mux {
+ pins = "gpio0", "gpio1", "gpio2",
+ "gpio3";
+ function = "qup01";
+ };
+
+ config {
+ pins = "gpio0", "gpio1", "gpio2",
+ "gpio3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
+ mux {
+ pins = "gpio0", "gpio1", "gpio2",
+ "gpio3";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio0", "gpio1", "gpio2",
+ "gpio3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se2_spi_pins: qupv3_se2_spi_pins {
+ qupv3_se2_spi_active: qupv3_se2_spi_active {
+ mux {
+ pins = "gpio34", "gpio35", "gpio36",
+ "gpio37";
+ function = "qup02";
+ };
+
+ config {
+ pins = "gpio34", "gpio35", "gpio36",
+ "gpio37";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
+ mux {
+ pins = "gpio34", "gpio35", "gpio36",
+ "gpio37";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio34", "gpio35", "gpio36",
+ "gpio37";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se4_spi_pins: qupv3_se4_spi_pins {
+ qupv3_se4_spi_active: qupv3_se4_spi_active {
+ mux {
+ pins = "gpio31", "gpio32", "gpio29",
+ "gpio30";
+ function = "qup04";
+ };
+
+ config {
+ pins = "gpio31", "gpio32", "gpio29",
+ "gpio30";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
+ mux {
+ pins = "gpio31", "gpio32", "gpio29",
+ "gpio30";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio31", "gpio32", "gpio29",
+ "gpio30";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se5_spi_pins: qupv3_se5_spi_pins {
+ qupv3_se5_spi_active: qupv3_se5_spi_active {
+ mux {
+ pins = "gpio38", "gpio39", "gpio40",
+ "gpio41";
+ function = "qup05";
+ };
+
+ config {
+ pins = "gpio38", "gpio39", "gpio40",
+ "gpio41";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
+ mux {
+ pins = "gpio38", "gpio39", "gpio40",
+ "gpio41";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio38", "gpio39", "gpio40",
+ "gpio41";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se6_spi_pins: qupv3_se6_spi_pins {
+ qupv3_se6_spi_active: qupv3_se6_spi_active {
+ mux {
+ pins = "gpio59", "gpio60", "gpio61",
+ "gpio62";
+ function = "qup10";
+ };
+
+ config {
+ pins = "gpio59", "gpio60", "gpio61",
+ "gpio62";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
+ mux {
+ pins = "gpio59", "gpio60", "gpio61",
+ "gpio62";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio59", "gpio60", "gpio61",
+ "gpio62";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se7_spi_pins: qupv3_se7_spi_pins {
+ qupv3_se7_spi_active: qupv3_se7_spi_active {
+ mux {
+ pins = "gpio6", "gpio7", "gpio8",
+ "gpio9";
+ function = "qup11";
+ };
+
+ config {
+ pins = "gpio6", "gpio7", "gpio8",
+ "gpio9";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
+ mux {
+ pins = "gpio6", "gpio7", "gpio8",
+ "gpio9";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6", "gpio7", "gpio8",
+ "gpio9";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se8_spi_pins: qupv3_se8_spi_pins {
+ qupv3_se8_spi_active: qupv3_se8_spi_active {
+ mux {
+ pins = "gpio49", "gpio50", "gpio51",
+ "gpio52";
+ function = "qup12";
+ };
+
+ config {
+ pins = "gpio49", "gpio50", "gpio51",
+ "gpio52";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se8_spi_sleep: qupv3_se8_spi_sleep {
+ mux {
+ pins = "gpio49", "gpio50", "gpio51",
+ "gpio52";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio49", "gpio50", "gpio51",
+ "gpio52";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se9_spi_pins: qupv3_se9_spi_pins {
+ qupv3_se9_spi_active: qupv3_se9_spi_active {
+ mux {
+ pins = "gpio46", "gpio47", "gpio48",
+ "gpio63";
+ function = "qup13";
+ };
+
+ config {
+ pins = "gpio46", "gpio47", "gpio48",
+ "gpio63";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se9_spi_sleep: qupv3_se9_spi_sleep {
+ mux {
+ pins = "gpio46", "gpio47", "gpio48",
+ "gpio63";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio46", "gpio47", "gpio48",
+ "gpio63";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se10_spi_pins: qupv3_se10_spi_pins {
+ qupv3_se10_spi_active: qupv3_se10_spi_active {
+ mux {
+ pins = "gpio53", "gpio54", "gpio55",
+ "gpio56";
+ function = "qup14";
+ };
+
+ config {
+ pins = "gpio53", "gpio54", "gpio55",
+ "gpio56";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se10_spi_sleep: qupv3_se10_spi_sleep {
+ mux {
+ pins = "gpio53", "gpio54", "gpio55",
+ "gpio56";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio53", "gpio54", "gpio55",
+ "gpio56";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se11_spi_pins: qupv3_se11_spi_pins {
+ qupv3_se11_spi_active: qupv3_se11_spi_active {
+ mux {
+ pins = "gpio108", "gpio109", "gpio112",
+ "gpio113";
+ function = "qup15";
+ };
+
+ config {
+ pins = "gpio108", "gpio109", "gpio112",
+ "gpio113";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se11_spi_sleep: qupv3_se11_spi_sleep {
+ mux {
+ pins = "gpio108", "gpio109", "gpio112",
+ "gpio113";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio108", "gpio109", "gpio112",
+ "gpio113";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ pmx_ts_active {
+ ts_active: ts_active {
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8", "gpio9";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_int_suspend {
+ ts_int_suspend: ts_int_suspend {
+ mux {
+ pins = "gpio9";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_reset_suspend {
+ ts_reset_suspend: ts_reset_suspend {
+ mux {
+ pins = "gpio8";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_release {
+ pmx_ts_release: pmx_ts_release {
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8", "gpio9";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ pmx_sde_te {
+ sde_te_active: sde_te_active {
+ mux {
+ pins = "gpio10";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+
+ sde_te_suspend: sde_te_suspend {
+ mux {
+ pins = "gpio10";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+
+ sde_te1_active: sde_te1_active {
+ mux {
+ pins = "gpio11";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+
+ sde_te1_suspend: sde_te1_suspend {
+ mux {
+ pins = "gpio11";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+ };
+
+ sde_dp_usbplug_cc_suspend: sde_dp_usbplug_cc_susppend {
+ mux {
+ pins = "gpio114";
+ function = "";
+ };
+
+ config {
+ pins = "gpio114";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+ };
+
+ sde_dp_usbplug_cc_active: sde_dp_usbplug_cc_active {
+ mux {
+ pins = "gpio114";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio114";
+ bias-disable;
+ drive-strenght = <16>;
+ };
+ };
+
+ pm8008_interrupt: pm8008_interrupt {
+ mux {
+ pins = "gpio45";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio45";
+ bias-disable;
+ input-enable;
+ };
+ };
+
+ pm8008_active: pm8008_active {
+ mux {
+ pins = "gpio44";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio44";
+ bias-pull-up;
+ output-high;
+ drive-strength = <2>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-pm.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-pm.dtsi
new file mode 100755
index 0000000..a7d72b4
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-pm.dtsi
@@ -0,0 +1,164 @@
+&soc {
+ qcom,lpm-levels {
+ compatible = "qcom,lpm-levels";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,pm-cluster@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "L3";
+ qcom,clstr-tmr-add = <1000>;
+ qcom,psci-mode-shift = <4>;
+ qcom,psci-mode-mask = <0xfff>;
+
+ qcom,pm-cluster-level@0 { /* D1 */
+ reg = <0>;
+ label = "l3-wfi";
+ qcom,psci-mode = <0x1>;
+ qcom,entry-latency-us = <660>;
+ qcom,exit-latency-us = <600>;
+ qcom,min-residency-us = <1260>;
+ };
+
+ qcom,pm-cluster-level@1 { /* D4 */
+ reg = <1>;
+ label = "l3-pc";
+ qcom,psci-mode = <0x4>;
+ qcom,entry-latency-us = <2752>;
+ qcom,exit-latency-us = <3048>;
+ qcom,min-residency-us = <6118>;
+ qcom,min-child-idx = <2>;
+ qcom,is-reset;
+ };
+
+ qcom,pm-cluster-level@2 { /* Cx Off */
+ reg = <2>;
+ label = "cx-off";
+ qcom,psci-mode = <0x224>;
+ qcom,entry-latency-us = <3638>;
+ qcom,exit-latency-us = <4562>;
+ qcom,min-residency-us = <8467>;
+ qcom,min-child-idx = <2>;
+ qcom,is-reset;
+ qcom,notify-rpm;
+ };
+
+ qcom,pm-cluster-level@3 { /* LLCC off, AOSS sleep */
+ reg = <3>;
+ label = "llcc-off";
+ qcom,psci-mode = <0xC24>;
+ qcom,entry-latency-us = <3263>;
+ qcom,exit-latency-us = <6562>;
+ qcom,min-residency-us = <9826>;
+ qcom,min-child-idx = <2>;
+ qcom,is-reset;
+ qcom,notify-rpm;
+ };
+
+ qcom,pm-cpu@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+ qcom,ref-stddev = <500>;
+ qcom,tmr-add = <1000>;
+ qcom,ref-premature-cnt = <1>;
+ qcom,disable-ipi-prediction;
+ qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4
+ &CPU5>;
+
+ qcom,pm-cpu-level@0 { /* C1 */
+ reg = <0>;
+ label = "wfi";
+ qcom,psci-cpu-mode = <0x1>;
+ qcom,entry-latency-us = <61>;
+ qcom,exit-latency-us = <60>;
+ qcom,min-residency-us = <121>;
+ };
+
+ qcom,pm-cpu-level@1 { /* C3 */
+ reg = <1>;
+ label = "pc";
+ qcom,psci-cpu-mode = <0x3>;
+ qcom,entry-latency-us = <549>;
+ qcom,exit-latency-us = <901>;
+ qcom,min-residency-us = <1774>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+
+ qcom,pm-cpu-level@2 { /* C4 */
+ reg = <2>;
+ label = "rail-pc";
+ qcom,psci-cpu-mode = <0x4>;
+ qcom,entry-latency-us = <702>;
+ qcom,exit-latency-us = <915>;
+ qcom,min-residency-us = <4001>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+ };
+
+ qcom,pm-cpu@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+ qcom,cpu = <&CPU6 &CPU7>;
+
+ qcom,pm-cpu-level@0 { /* C1 */
+ reg = <0>;
+ label = "wfi";
+ qcom,psci-cpu-mode = <0x1>;
+ qcom,entry-latency-us = <55>;
+ qcom,exit-latency-us = <66>;
+ qcom,min-residency-us = <121>;
+ };
+
+ qcom,pm-cpu-level@1 { /* C3 */
+ reg = <1>;
+ label = "pc";
+ qcom,psci-cpu-mode = <0x3>;
+ qcom,entry-latency-us = <523>;
+ qcom,exit-latency-us = <1244>;
+ qcom,min-residency-us = <2207>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+
+ qcom,pm-cpu-level@2 { /* C4 */
+ reg = <2>;
+ label = "rail-pc";
+ qcom,psci-cpu-mode = <0x4>;
+ qcom,entry-latency-us = <526>;
+ qcom,exit-latency-us = <1854>;
+ qcom,min-residency-us = <5555>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+ };
+ };
+ };
+
+ qcom,rpm-stats@c300000 {
+ compatible = "qcom,rpm-stats";
+ reg = <0xc300000 0x1000>, <0xc3f0004 0x4>;
+ reg-names = "phys_addr_base", "offset_addr";
+ qcom,num-records = <3>;
+ };
+
+ qcom,ddr-stats@c3f001c {
+ compatible = "qcom,ddr-stats";
+ reg = <0xc300000 0x1000>, <0xc3f001c 0x4>;
+ reg-names = "phys_addr_base", "offset_addr";
+ };
+
+ qcom,rpmh-master-stats@b221200 {
+ compatible = "qcom,rpmh-master-stats-v1";
+ reg = <0xb221200 0x60>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-pmic-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-pmic-overlay.dtsi
new file mode 100755
index 0000000..e38809b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-pmic-overlay.dtsi
@@ -0,0 +1,446 @@
+#include "pm8150.dtsi"
+#include "pm7250b.dtsi"
+#include "pm8150l.dtsi"
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+&pm8150_clkdiv {
+ /delete-property/ clocks;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+};
+
+&pm8150_gpios {
+ interrupts = <0x0 0xc3 0x0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm8150_gpio4";
+ qcom,gpios-disallowed = <1 2 3 5 6 7 8 9 10>;
+};
+
+&pm8150l_gpios {
+ /delete-property/ qcom,gpios-disallowed;
+ interrupts = <0x4 0xc0 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc1 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc2 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc3 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc4 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc5 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc6 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc7 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc8 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc9 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xca 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xcb 0x0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm8150l_gpio1", "pm8150l_gpio2",
+ "pm8150l_gpio3", "pm8150l_gpio4",
+ "pm8150l_gpio5", "pm8150l_gpio6",
+ "pm8150l_gpio7", "pm8150l_gpio8",
+ "pm8150l_gpio9", "pm8150l_gpio10",
+ "pm8150l_gpio11", "pm8150l_gpio12";
+
+ key_vol_up {
+ key_vol_up_default: key_vol_up_default {
+ pins = "gpio5";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+ };
+};
+
+&pm8150l_clkdiv {
+ /delete-property/ clocks;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+};
+
+&pm7250b_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bmr_w_therm_default &camera_therm_default>;
+
+ charger_skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "charger_skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "conn_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bmr_w_therm@53 {
+ reg = <ADC_GPIO2_PU2>;
+ label = "bmr_w_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ camera_flash_therm@55 {
+ reg = <ADC_GPIO4_PU2>;
+ label = "camera_flash_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm7250b_gpios {
+ bmr_w_therm {
+ bmr_w_therm_default: bmr_w_therm_default {
+ pins = "gpio12";
+ bias-high-impedance;
+ };
+ };
+
+ camera_therm {
+ camera_therm_default: camera_therm_default {
+ pins = "gpio8";
+ bias-high-impedance;
+ };
+ };
+};
+
+&pm8150_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vcoin@85 {
+ reg = <ADC_VCOIN>;
+ label = "vcoin";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ xo_therm@4c {
+ reg = <ADC_XO_THERM_PU2>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "pa_therm1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bmr_e_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "bmr_e_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8150l_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ pa_therm2@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "pa_therm2";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ msm_skin_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "msm_skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bmr_n_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "bmr_n_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm7250b_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ io-channels = <&pm7250b_vadc ADC_AMUX_THM1_PU2>,
+ <&pm7250b_vadc ADC_GPIO2_PU2>,
+ <&pm7250b_vadc ADC_GPIO4_PU2>;
+
+ /* Channel nodes */
+ charger_skin_therm@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ bmr_w_therm@53 {
+ reg = <ADC_GPIO2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ camera_flash_therm@55 {
+ reg = <ADC_GPIO4_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ io-channels = <&pm8150_vadc ADC_XO_THERM_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM1_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM2_PU2>;
+
+ /* Channel nodes */
+ xo_therm@4c {
+ reg = <ADC_XO_THERM_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm1@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ bmr_e_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm8150l_adc_tm {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ io-channels = <&pm8150l_vadc ADC_AMUX_THM1_PU2>,
+ <&pm8150l_vadc ADC_AMUX_THM2_PU2>,
+ <&pm8150l_vadc ADC_AMUX_THM3_PU2>;
+
+ /* Channel nodes */
+ pa_therm2@4d {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ msm_skin_therm1@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ bmr_n_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&thermal_zones {
+ charger-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm7250b_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm7250b_adc_tm ADC_GPIO2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm7250b_adc_tm ADC_GPIO4_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ active-config1 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa-therm1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa-therm2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ msm-s-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mmw-pa1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&pm7250b_charger {
+ dpdm-supply = <&usb2_phy0>;
+
+ smb5_vbus: qcom,smb5-vbus {
+ regulator-name = "smb5-vbus";
+ };
+
+ smb5_vconn: qcom,smb5-vconn {
+ regulator-name = "smb5-vconn";
+ };
+};
+
+&pm8150l_gpios {
+ eldo13_pin {
+ usb_eldo13:gpio@cb00 {
+ pins = "gpio12";
+ function = "normal";
+ qcom,drive-strength = <2>;
+ power-source = <0>;
+ bias-disable;
+ output-high;
+ };
+ };
+};
+
+&pm7250b_pdphy {
+ vdd-pdphy-supply = <&pm8150_l2>;
+ vbus-supply = <&smb5_vbus>;
+ vconn-supply = <&smb5_vconn>;
+};
+
+&usb0 {
+ extcon = <&pm7250b_pdphy>, <&pm7250b_charger>, <&eud>;
+};
+
+&usb_qmp_dp_phy {
+ extcon = <&pm7250b_pdphy>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-qrd-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lito-qrd-overlay.dts
new file mode 100755
index 0000000..4d994c3d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-qrd-overlay.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+/plugin/;
+
+#include "lito-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito QRD";
+ compatible = "qcom,lito-qrd", "qcom,lito", "qcom,qrd";
+ qcom,msm-id = <400 0x10000>, <440 0x10000>;
+ qcom,board-id = <11 0>;
+};
+
+&ufsphy_mem {
+ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/lito-qrd.dts
new file mode 100755
index 0000000..b1c9419
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-qrd.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+#include "lito.dtsi"
+#include "lito-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito QRD";
+ compatible = "qcom,lito-qrd", "qcom,lito", "qcom,qrd";
+ qcom,board-id = <11 0>;
+};
+
+&ufsphy_mem {
+ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-qrd.dtsi
new file mode 100755
index 0000000..1ca66c2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-qrd.dtsi
@@ -0,0 +1,855 @@
+#include "lito-pmic-overlay.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include "lito-audio-overlay.dtsi"
+#include "lito-thermal-overlay.dtsi"
+#include "camera/lito-camera-sensor-qrd.dtsi"
+#include "lito-sde-display.dtsi"
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm8150l_gpios 5 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+
+ qrd_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "qg-batterydata-atl466271_3300mAh.dtsi"
+ };
+ vdda_usb_ss_dp_core: vdda_usb_ss_dp_core {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_supply";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ enable-active-high;
+ gpio = <&pm8150l_gpios 12 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_eldo13>;
+ };
+};
+
+&usb_qmp_dp_phy {
+ vdd-supply = <&vdda_usb_ss_dp_core>;
+};
+
+&usb2_phy0 {
+ qcom,param-override-seq = <0x63 0x6c>,
+ <0xc8 0x70>,
+ <0x17 0x74>;
+};
+
+&sde_dp {
+ vdda-0p9-supply = <&vdda_usb_ss_dp_core>;
+};
+
+&qupv3_se7_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "ok";
+ qcom,i2c-touch-active = "st,fts";
+
+ st_fts@49 {
+ compatible = "st,fts";
+ reg = <0x49>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <9 0x2008>;
+ vdd-supply = <&pm8150_s4>;
+ avdd-supply = <&pm8150_l13>;
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
+ pinctrl-0 = <&ts_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ st,irq-gpio = <&tlmm 9 0x2008>;
+ st,reset-gpio = <&tlmm 8 0x00>;
+ st,regulator_dvdd = "vdd";
+ st,regulator_avdd = "avdd";
+ st,x-flip;
+ st,y-flip;
+ st,power_on_suspend;
+ panel = <&dsi_sw43404_amoled_cmd &dsi_sw43404_amoled_video
+ &dsi_sw43404_amoled_fhd_plus_cmd>;
+ };
+};
+
+&tlmm {
+ pmx_ts_active {
+ ts_active: ts_active {
+ mux {
+ pins = "gpio8", "gpio9";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8", "gpio9";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_int_suspend {
+ ts_int_suspend: ts_int_suspend {
+ mux {
+ pins = "gpio9";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_reset_suspend {
+ ts_reset_suspend: ts_reset_suspend {
+ mux {
+ pins = "gpio8";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qmp-v4-lito";
+
+ vdda-phy-supply = <&pm8150_l5>;
+ vdda-pll-supply = <&pm8150_l9>;
+ vdda-phy-max-microamp = <90200>;
+ vdda-pll-max-microamp = <19000>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm8150a_l7>;
+ vcc-voltage-level = <2950000 2960000>;
+ vccq2-supply = <&pm8150_s4>;
+ vcc-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+ vccq2-min-microamp = <0>;
+
+ qcom,vddp-ref-clk-supply = <&pm8150_l9>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+ qcom,vddp-ref-clk-min-microamp = <0>;
+ qcom,vddp-ref-clk-min-uV = <1152000>;
+ qcom,vddp-ref-clk-max-uV = <1200000>;
+ status = "ok";
+};
+
+&sdhc_1 {
+ vdd-supply = <&pm8150a_l7>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&pm8150_s4>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&pm8150a_l9>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&pm8150a_l6>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 69 GPIO_ACTIVE_HIGH>;
+
+ status = "ok";
+};
+
+&pm8150a_amoled {
+ status = "ok";
+};
+
+&pm7250b_adc_tm {
+ io-channels = <&pm7250b_vadc ADC_AMUX_THM1_PU2>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+ <&pm7250b_vadc ADC_GPIO2_PU2>,
+ <&pm7250b_vadc ADC_GPIO4_PU2>;
+
+ conn_therm@4f {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+&pm7250b_charger {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_USB_IN_V_16>,
+ <&pm7250b_vadc ADC_USB_IN_I>,
+ <&pm7250b_vadc ADC_CHG_TEMP>,
+ <&pm7250b_vadc ADC_DIE_TEMP>,
+ <&pm7250b_vadc ADC_AMUX_THM3_PU2>,
+ <&pm7250b_vadc ADC_SBUx>,
+ <&pm7250b_vadc ADC_VPH_PWR>,
+ <&pm7250b_vadc ADC_AMUX_THM1_PU2>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp",
+ "die_temp",
+ "conn_temp",
+ "sbux_res",
+ "vph_voltage",
+ "skin_temp";
+ qcom,battery-data = <&qrd_batterydata>;
+ qcom,sec-charger-config = <1>;
+ qcom,auto-recharge-soc = <98>;
+ qcom,step-charging-enable;
+ qcom,sw-jeita-enable;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,fcc-stepping-enable;
+ qcom,fcc-step-delay-ms = <100>;
+ qcom,fcc-step-size-ua = <100000>;
+ qcom,smb-internal-pull-kohm = <0>;
+ qcom,en-skin-therm-mitigation;
+ qcom,thermal-mitigation = <8000000 7500000 7000000 6500000 6000000
+ 5500000 4500000 4000000 3500000 3000000 2500000
+ 2000000 1500000 1000000 500000>;
+};
+
+&pm7250b_qg {
+ status = "ok";
+ io-channels = <&pm7250b_vadc ADC_BAT_THERM_PU2>,
+ <&pm7250b_vadc ADC_BAT_ID_PU2>;
+ io-channel-names = "batt-therm",
+ "batt-id";
+ qcom,qg-iterm-ma = <100>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+ qcom,tcss-enable;
+ qcom,fvss-enable;
+ qcom,fvss-vbatt-mv = <3300>;
+ qcom,bass-enable;
+};
+
+&thermal_zones {
+ conn-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm7250b_adc_tm ADC_AMUX_THM3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-step {
+ polling-delay-passive = <2000>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150_adc_tm ADC_XO_THERM_PU2>;
+ wake-capable-sensor;
+ trips {
+ skin_batt_trip0: skin-batt-trip0 {
+ temperature = <42000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ skin_batt_trip1: skin-batt-trip1 {
+ temperature = <44000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ skin_batt_trip2: skin-batt-trip2 {
+ temperature = <48000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ modem0_skin_trip: modem0-skin-trip {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ skin_batt_trip3: skin-batt-trip3 {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gold_plus_trip: gold-plus-trip {
+ temperature = <50000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ modem1_skin_trip: modem1-skin-trip {
+ temperature = <52000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ skin_batt_trip4: skin-batt-trip4 {
+ temperature = <52000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gold_trip: gold-trip {
+ temperature = <52000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ cx_emer_trip: cx-emer-trip {
+ temperature = <54000>;
+ hysteresis = <6000>;
+ type = "passive";
+ };
+
+ silver_trip: silver-trip {
+ temperature = <54000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ gpu_modem2_skin_trip: gpu-modem-skin-trip {
+ temperature = <56000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ skin_cpu7 {
+ trip = <&gold_plus_trip>;
+ /* throttle from fmax to 1516800KHz */
+ cooling-device =
+ <&CPU7 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+
+ skin_cpu6 {
+ trip = <&gold_trip>;
+ /* throttle from fmax to 1478400KHz */
+ cooling-device =
+ <&CPU6 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+
+ skin_cpu0 {
+ trip = <&silver_trip>;
+ /* throttle from fmax to 1459200KHz */
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-5)>;
+ };
+
+ skin_gpu {
+ trip = <&gpu_modem2_skin_trip>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ skin_modem_pa1 {
+ trip = <&modem0_skin_trip>;
+ cooling-device = <&modem_pa 1 1>;
+ };
+
+ skin_modem_pa2 {
+ trip = <&modem1_skin_trip>;
+ cooling-device = <&modem_pa 2 2>;
+ };
+
+ skin_modem_pa3 {
+ trip = <&gpu_modem2_skin_trip>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ skin_modem_pa_fr1_1 {
+ trip = <&modem0_skin_trip>;
+ cooling-device = <&modem_pa_fr1 1 1>;
+ };
+
+ skin_modem_pa_fr1_2 {
+ trip = <&modem1_skin_trip>;
+ cooling-device = <&modem_pa_fr1 2 2>;
+ };
+
+ skin_modem_pa_fr1_3 {
+ trip = <&gpu_modem2_skin_trip>;
+ cooling-device = <&modem_pa_fr1 3 3>;
+ };
+
+ skin_cdsp {
+ trip = <&cx_emer_trip>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ skin_npu {
+ trip = <&cx_emer_trip>;
+ cooling-device = <&msm_npu THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ skin_batt_cdev0 {
+ trip = <&skin_batt_trip0>;
+ cooling-device = <&pm7250b_charger 1 1>;
+ };
+
+ skin_batt_cdev1 {
+ trip = <&skin_batt_trip1>;
+ cooling-device = <&pm7250b_charger 5 5>;
+ };
+
+ skin_batt_cdev2 {
+ trip = <&skin_batt_trip2>;
+ cooling-device = <&pm7250b_charger 7 7>;
+ };
+
+ skin_batt_cdev3 {
+ trip = <&skin_batt_trip3>;
+ cooling-device = <&pm7250b_charger 9 9>;
+ };
+
+ skin_batt_cdev4 {
+ trip = <&skin_batt_trip4>;
+ cooling-device = <&pm7250b_charger 11 11>;
+ };
+ };
+ };
+
+ mmw-pa1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM3_PU2>;
+ wake-capable-sensor;
+
+ trips {
+ mmw_pa1_trip0: mmw-pa1-trip0 {
+ temperature = <46000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ mmw_pa1_trip1: mmw-pa1-trip1 {
+ temperature = <49000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ mmw_pa1_trip2: mmw-pa1-trip2 {
+ temperature = <56000>;
+ hysteresis = <6000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ mdm_mmw_skin1_cdev0 {
+ trip = <&mmw_pa1_trip0>;
+ cooling-device = <&modem_mmw_skin1 1 1>;
+ };
+
+ mdm_mmw_skin1_cdev1 {
+ trip = <&mmw_pa1_trip1>;
+ cooling-device = <&modem_mmw_skin1 2 2>;
+ };
+
+ mdm_mmw_skin1_cdev2 {
+ trip = <&mmw_pa1_trip2>;
+ cooling-device = <&modem_mmw_skin1 3 3>;
+ };
+ };
+ };
+
+ mmw-pa3-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+
+ trips {
+ mmw_pa3_trip0: mmw-pa3-trip0 {
+ temperature = <43000>;
+ hysteresis = <3000>;
+ type = "passive";
+ };
+
+ mmw_pa3_trip1: mmw-pa3-trip1 {
+ temperature = <45000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ mmw_pa3_trip2: mmw-pa3-trip2 {
+ temperature = <56000>;
+ hysteresis = <6000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ mdm_mmw_skin0_cdev0 {
+ trip = <&mmw_pa3_trip0>;
+ cooling-device = <&modem_mmw_skin0 1 1>;
+ };
+
+ mdm_mmw_skin0_cdev1 {
+ trip = <&mmw_pa3_trip1>;
+ cooling-device = <&modem_mmw_skin0 2 2>;
+ };
+
+ mdm_mmw_skin0_cdev2 {
+ trip = <&mmw_pa3_trip2>;
+ cooling-device = <&modem_mmw_skin0 3 3>;
+ };
+ };
+ };
+
+ mmw-pa2-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm7250b_adc_tm ADC_GPIO2_PU2>;
+ wake-capable-sensor;
+
+ trips {
+ mmw_pa2_trip0: mmw-pa2-trip0 {
+ temperature = <43000>;
+ hysteresis = <3000>;
+ type = "passive";
+ };
+
+ mmw_pa2_trip1: mmw-pa2-trip1 {
+ temperature = <46000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ mmw_pa2_trip2: mmw-pa2-trip2 {
+ temperature = <56000>;
+ hysteresis = <6000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ mdm_mmw_skin2_cdev0 {
+ trip = <&mmw_pa2_trip0>;
+ cooling-device = <&modem_mmw_skin2 1 1>;
+ };
+
+ mdm_mmw_skin2_cdev1 {
+ trip = <&mmw_pa2_trip1>;
+ cooling-device = <&modem_mmw_skin2 2 2>;
+ };
+
+ mdm_mmw_skin2_cdev2 {
+ trip = <&mmw_pa2_trip2>;
+ cooling-device = <&modem_mmw_skin2 3 3>;
+ };
+ };
+ };
+
+ msm-s-therm-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150l_adc_tm ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+
+ trips {
+ skin_msm_trip0: skin-msm-trip0 {
+ temperature = <50000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ skin_msm_trip1: skin-msm-trip1 {
+ temperature = <56000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ mdm_skin_cdev0 {
+ trip = <&skin_msm_trip0>;
+ cooling-device = <&modem_tj 1 1>;
+ };
+
+ mdm_skin_cdev1 {
+ trip = <&skin_msm_trip1>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+ };
+ };
+};
+
+&wsa881x_0212 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x20170212>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+};
+
+&wsa881x_0214 {
+ compatible = "qcom,wsa881x";
+ reg = <0x10 0x21170214>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+};
+
+&lito_snd {
+ qcom,model = "lito-qrd-snd-card";
+ qcom,audio-routing =
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "TX DMIC0", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic0",
+ "TX DMIC1", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic1",
+ "TX DMIC2", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "TX DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "TX DMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "TX DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "TX SWR_ADC0", "ADC1_OUTPUT",
+ "TX SWR_ADC1", "ADC2_OUTPUT",
+ "TX SWR_ADC2", "ADC3_OUTPUT",
+ "TX SWR_ADC3", "ADC4_OUTPUT",
+ "TX SWR_DMIC0", "DMIC1_OUTPUT",
+ "TX SWR_DMIC1", "DMIC2_OUTPUT",
+ "TX SWR_DMIC2", "DMIC3_OUTPUT",
+ "TX SWR_DMIC3", "DMIC4_OUTPUT",
+ "TX SWR_DMIC4", "DMIC5_OUTPUT",
+ "TX SWR_DMIC5", "DMIC6_OUTPUT",
+ "TX SWR_DMIC6", "DMIC7_OUTPUT",
+ "TX SWR_DMIC7", "DMIC8_OUTPUT",
+ "WSA SRC0_INP", "SRC0",
+ "WSA_TX DEC0_INP", "TX DEC0 MUX",
+ "WSA_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "SpkrRight IN", "WSA_SPK2 OUT",
+ "VA_AIF1 CAP", "VA_SWR_CLK",
+ "VA_AIF2 CAP", "VA_SWR_CLK",
+ "VA_AIF3 CAP", "VA_SWR_CLK",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA MIC BIAS4", "Digital Mic4",
+ "VA MIC BIAS4", "Digital Mic5",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA DMIC4", "VA MIC BIAS4",
+ "VA DMIC5", "VA MIC BIAS4",
+ "VA SWR_ADC0", "VA_SWR_CLK",
+ "VA SWR_ADC1", "VA_SWR_CLK",
+ "VA SWR_ADC2", "VA_SWR_CLK",
+ "VA SWR_ADC3", "VA_SWR_CLK",
+ "VA SWR_MIC0", "VA_SWR_CLK",
+ "VA SWR_MIC1", "VA_SWR_CLK",
+ "VA SWR_MIC2", "VA_SWR_CLK",
+ "VA SWR_MIC3", "VA_SWR_CLK",
+ "VA SWR_MIC4", "VA_SWR_CLK",
+ "VA SWR_MIC5", "VA_SWR_CLK",
+ "VA SWR_MIC6", "VA_SWR_CLK",
+ "VA SWR_MIC7", "VA_SWR_CLK",
+ "VA SWR_ADC1", "ADC2_OUTPUT",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC0", "DMIC1_OUTPUT",
+ "VA SWR_MIC1", "DMIC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC3_OUTPUT",
+ "VA SWR_MIC3", "DMIC4_OUTPUT",
+ "VA SWR_MIC4", "DMIC5_OUTPUT",
+ "VA SWR_MIC5", "DMIC6_OUTPUT",
+ "VA SWR_MIC6", "DMIC7_OUTPUT",
+ "VA SWR_MIC7", "DMIC8_OUTPUT";
+ qcom,wsa-max-devs = <1>;
+ qcom,wsa-devs = <&wsa881x_0212>, <&wsa881x_0214>;
+ qcom,wsa-aux-dev-prefix = "SpkrRight", "SpkrRight";
+ qcom,msm-mbhc-usbc-audio-supported = <1>;
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_sw43404_amoled_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <1023>;
+ qcom,mdss-brightness-max-level = <255>;
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_video>;
+};
+
+&qupv3_se0_i2c {
+ status = "ok";
+ qcom,clk-freq-out = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 34 0x00>;
+ qcom,nq-ven = <&tlmm 12 0x00>;
+ qcom,nq-firm = <&tlmm 35 0x00>;
+ qcom,nq-clkreq = <&tlmm 31 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <34 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&dsi_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_sim_vid {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&dsi_dual_sim_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,platform-reset-gpio = <&pm8150l_gpios 3 0>;
+};
+
+&pm7250b_gpios {
+ smb_stat {
+ smb_stat_default: smb_stat_default {
+ pins = "gpio6";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+ power-source = <0>;
+ };
+ };
+};
+
+&qupv3_se9_i2c {
+ status = "ok";
+ #include "smb1390.dtsi"
+};
+
+&smb1390 {
+ /delete-property/ interrupts;
+ interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_stat_default>;
+ status = "ok";
+};
+
+&smb1390_charger {
+ compatible = "qcom,smb1390-charger-psy";
+ io-channels = <&pm7250b_vadc ADC_AMUX_THM2>;
+ io-channel-names = "cp_die_temp";
+ qcom,parallel-input-mode = <1>; /* USBIN */
+ qcom,parallel-output-mode = <2>; /* VBAT */
+ qcom,min-ilim-ua = <750000>;
+ status = "ok";
+};
+
+&smb1390_slave {
+ status = "ok";
+};
+
+&smb1390_slave_charger {
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-qupv3.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-qupv3.dtsi
new file mode 100755
index 0000000..eb82ef3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-qupv3.dtsi
@@ -0,0 +1,603 @@
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ /* QUPv3 North Instances
+ * North 0 : SE 0
+ * North 1 : SE 1
+ * North 2 : SE 2
+ * North 4 : SE 4
+ * North 5 : SE 5
+ */
+
+ qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
+ compatible = "qcom,qupv3-geni-se";
+ reg = <0x8c0000 0x2000>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-bus-ids =
+ <MSM_BUS_MASTER_QUP_CORE_0 MSM_BUS_SLAVE_QUP_CORE_0>,
+ <MSM_BUS_MASTER_QUP_0 MSM_BUS_SLAVE_EBI_CH0>;
+ iommus = <&apps_smmu 0x4e3 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+ qcom,iommu-dma = "fastmap";
+ };
+
+ /* Debug UART Instance for RUMI platform */
+ qupv3_se2_2uart: qcom,qup_uart@888000 {
+ compatible = "qcom,msm-geni-console";
+ reg = <0x888000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se2_2uart_active>;
+ pinctrl-1 = <&qupv3_se2_2uart_sleep>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ /* 4-wire UART */
+ qupv3_se5_4uart: qcom,qup_uart@894000 {
+ compatible = "qcom,msm-geni-serial-hs";
+ reg = <0x894000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se5_ctsrx>, <&qupv3_se5_rts>,
+ <&qupv3_se5_tx>;
+ pinctrl-1 = <&qupv3_se5_ctsrx>, <&qupv3_se5_rts>,
+ <&qupv3_se5_tx>;
+ interrupts-extended = <&intc GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 41 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,wrapper-core = <&qupv3_0>;
+ qcom,wakeup-byte = <0xFD>;
+ status = "disabled";
+ };
+
+ /* QUPV3_0_SE0 */
+ i3c0: i3c-master@880000 {
+ compatible = "qcom,geni-i3c";
+ reg = <0x880000 0x4000>,
+ <0xec30000 0x10000>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se0_i3c_active>;
+ pinctrl-1 = <&qupv3_se0_i3c_sleep>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ /* I2C */
+ qupv3_se0_i2c: i2c@880000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x880000 0x4000>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 0 3 64 0>,
+ <&gpi_dma0 1 0 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se0_i2c_active>;
+ pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se1_i2c: i2c@884000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x884000 0x4000>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 1 3 64 0>,
+ <&gpi_dma0 1 1 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se1_i2c_active>;
+ pinctrl-1 = <&qupv3_se1_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se2_i2c: i2c@888000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x888000 0x4000>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 2 3 64 0>,
+ <&gpi_dma0 1 2 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se2_i2c_active>;
+ pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se4_i2c: i2c@890000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x890000 0x4000>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 4 3 64 0>,
+ <&gpi_dma0 1 4 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se4_i2c_active>;
+ pinctrl-1 = <&qupv3_se4_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se5_i2c: i2c@894000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x894000 0x4000>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ dmas = <&gpi_dma0 0 5 3 64 0>,
+ <&gpi_dma0 1 5 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se5_i2c_active>;
+ pinctrl-1 = <&qupv3_se5_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ /* SPI */
+ qupv3_se0_spi: spi@880000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x880000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se0_spi_active>;
+ pinctrl-1 = <&qupv3_se0_spi_sleep>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 0 1 64 0>,
+ <&gpi_dma0 1 0 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se1_spi: spi@884000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x884000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se1_spi_active>;
+ pinctrl-1 = <&qupv3_se1_spi_sleep>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 1 1 64 0>,
+ <&gpi_dma0 1 1 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se2_spi: spi@888000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x888000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se2_spi_active>;
+ pinctrl-1 = <&qupv3_se2_spi_sleep>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 2 1 64 0>,
+ <&gpi_dma0 1 2 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se4_spi: spi@890000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x890000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se4_spi_active>;
+ pinctrl-1 = <&qupv3_se4_spi_sleep>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 4 1 64 0>,
+ <&gpi_dma0 1 4 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se5_spi: spi@894000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x894000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se5_spi_active>;
+ pinctrl-1 = <&qupv3_se5_spi_sleep>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ dmas = <&gpi_dma0 0 5 1 64 0>,
+ <&gpi_dma0 1 5 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ /* QUPv3 South_1 Instances
+ * South_1 0 : SE 6
+ * South_1 1 : SE 7
+ * South_1 2 : SE 8
+ * South_1 3 : SE 9
+ * South_1 4 : SE 10
+ * South_1 5 : SE 11
+ */
+ qupv3_1: qcom,qupv3_1_geni_se@9c0000 {
+ compatible = "qcom,qupv3-geni-se";
+ reg = <0x9c0000 0x2000>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-bus-ids =
+ <MSM_BUS_MASTER_QUP_CORE_1 MSM_BUS_SLAVE_QUP_CORE_1>,
+ <MSM_BUS_MASTER_QUP_1 MSM_BUS_SLAVE_EBI_CH0>;
+ iommus = <&apps_smmu 0x023 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+ qcom,iommu-dma = "fastmap";
+ };
+
+ /* 2-wire UART */
+ qupv3_se8_2uart: qcom,qup_uart@988000 {
+ compatible = "qcom,msm-geni-console";
+ reg = <0x988000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se8_2uart_active>;
+ pinctrl-1 = <&qupv3_se8_2uart_sleep>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ /* QUPV3_1_SE0 */
+ i3c1: i3c-master@980000 {
+ compatible = "qcom,geni-i3c";
+ reg = <0x980000 0x4000>,
+ <0xec40000 0x10000>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se6_i3c_active>;
+ pinctrl-1 = <&qupv3_se6_i3c_sleep>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ /* I2C */
+ qupv3_se6_i2c: i2c@980000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x980000 0x4000>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 0 3 64 0>,
+ <&gpi_dma1 1 0 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se6_i2c_active>;
+ pinctrl-1 = <&qupv3_se6_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ qupv3_se7_i2c: i2c@984000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x984000 0x4000>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 1 3 64 0>,
+ <&gpi_dma1 1 1 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se7_i2c_active>;
+ pinctrl-1 = <&qupv3_se7_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ qupv3_se8_i2c: i2c@988000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x988000 0x4000>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 2 3 64 0>,
+ <&gpi_dma1 1 2 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se8_i2c_active>;
+ pinctrl-1 = <&qupv3_se8_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ qupv3_se9_i2c: i2c@98c000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x98c000 0x4000>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 3 3 64 0>,
+ <&gpi_dma1 1 3 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se9_i2c_active>;
+ pinctrl-1 = <&qupv3_se9_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ qcom,shared;
+ status = "disabled";
+ };
+
+ qupv3_se10_i2c: i2c@990000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x990000 0x4000>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 4 3 64 0>,
+ <&gpi_dma1 1 4 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se10_i2c_active>;
+ pinctrl-1 = <&qupv3_se10_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ qupv3_se11_i2c: i2c@994000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x994000 0x4000>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ dmas = <&gpi_dma1 0 5 3 64 0>,
+ <&gpi_dma1 1 5 3 64 0>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se11_i2c_active>;
+ pinctrl-1 = <&qupv3_se11_i2c_sleep>;
+ qcom,wrapper-core = <&qupv3_1>;
+ status = "disabled";
+ };
+
+ /* SPI */
+ qupv3_se6_spi: spi@980000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x980000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se6_spi_active>;
+ pinctrl-1 = <&qupv3_se6_spi_sleep>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
+ dmas = <&gpi_dma1 0 0 1 64 0>,
+ <&gpi_dma1 1 0 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se7_spi: spi@984000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x984000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se7_spi_active>;
+ pinctrl-1 = <&qupv3_se7_spi_sleep>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
+ dmas = <&gpi_dma1 0 1 1 64 0>,
+ <&gpi_dma1 1 1 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se8_spi: spi@988000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x988000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se8_spi_active>;
+ pinctrl-1 = <&qupv3_se8_spi_sleep>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
+ dmas = <&gpi_dma1 0 2 1 64 0>,
+ <&gpi_dma1 1 2 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se9_spi: spi@98c000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x98c000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se9_spi_active>;
+ pinctrl-1 = <&qupv3_se9_spi_sleep>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
+ dmas = <&gpi_dma1 0 3 1 64 0>,
+ <&gpi_dma1 1 3 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se10_spi: spi@990000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x990000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se10_spi_active>;
+ pinctrl-1 = <&qupv3_se10_spi_sleep>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
+ dmas = <&gpi_dma1 0 4 1 64 0>,
+ <&gpi_dma1 1 4 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ qupv3_se11_spi: spi@994000 {
+ compatible = "qcom,spi-geni";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x994000 0x4000>;
+ reg-names = "se_phys";
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se11_spi_active>;
+ pinctrl-1 = <&qupv3_se11_spi_sleep>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_1>;
+ dmas = <&gpi_dma1 0 5 1 64 0>,
+ <&gpi_dma1 1 5 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-regulators.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-regulators.dtsi
new file mode 100755
index 0000000..264e493
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-regulators.dtsi
@@ -0,0 +1,806 @@
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+
+&apps_rsc {
+ /* PM8150 S1 + S9 + s10 = VDD_CX supply */
+ rpmh-regulator-cxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "cx.lvl";
+ VDD_CX_LEVEL: S1A_LEVEL:
+ pm8150_s1_level: regulator-pm8150-s1-level {
+ regulator-name = "pm8150_s1_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt
+ = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ qcom,min-dropout-voltage-level = <(-1)>;
+ };
+
+ VDD_CX_LEVEL_AO: S1A_LEVEL_AO:
+ pm8150_s1_level_ao: regulator-pm8150-s1-level-ao {
+ regulator-name = "pm8150_s1_level_ao";
+ qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+ regulator-min-microvolt
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt
+ = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ qcom,min-dropout-voltage-level = <(-1)>;
+ };
+ };
+
+ rpmh-regulator-smpa4 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpa4";
+ qcom,regulator-type = "pmic5-hfsmps";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_RET
+ RPMH_REGULATOR_MODE_AUTO>;
+ qcom,mode-threshold-currents = <0 1>;
+ S4A: pm8150_s4: regulator-pm8150-s4 {
+ regulator-name = "pm8150_s4";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ };
+ };
+
+ rpmh-regulator-smpa5 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpa5";
+ S5A: pm8150_s5: regulator-pm8150-s5 {
+ regulator-name = "pm8150_s5";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1664000>;
+ regulator-max-microvolt = <2040000>;
+ qcom,init-voltage = <1664000>;
+ };
+ };
+
+ rpmh-regulator-smpa6 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpa6";
+ S6A: pm8150_s6: regulator-pm8150-s6 {
+ regulator-name = "pm8150_s6";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <408000>;
+ regulator-max-microvolt = <1128000>;
+ qcom,init-voltage = <408000>;
+ };
+ };
+
+ /* PM8150 S8 + S7 = VDD_MODEM supply */
+ rpmh-regulator-msslvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "mss.lvl";
+ VDD_MSS_LEVEL: S8A_LEVEL:
+ pm8150_s8_level: regulator-pm8150-s8 {
+ regulator-name = "pm8150_s8_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt
+ = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ rpmh-regulator-ldoa1 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa1";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L1A: pm8150_l1: regulator-pm8150-l1 {
+ regulator-name = "pm8150_l1";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <352000>;
+ regulator-max-microvolt = <952000>;
+ qcom,init-voltage = <352000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa2 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa2";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L2A: pm8150_l2: regulator-pm8150-l2 {
+ regulator-name = "pm8150_l2";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <2700000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa3 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa3";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L3A: pm8150_l3: regulator-pm8150-l3 {
+ regulator-name = "pm8150_l3";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <824000>;
+ qcom,init-voltage = <312000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ /* PM8150 L4 = VDD_LPI_MX supply */
+ rpmh-regulator-lmxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "lmx.lvl";
+ L4A_LEVEL: pm8150_l4_level: regulator-pm8150-l4-level {
+ regulator-name = "pm8150_l4_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt =
+ <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ rpmh-regulator-ldoa5 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa5";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ proxy-supply = <&pm8150_l5>;
+ L5A: pm8150_l5: regulator-pm8150-l5 {
+ regulator-name = "pm8150_l5";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1056000>;
+ qcom,proxy-consumer-enable;
+ qcom,proxy-consumer-current = <23800>;
+ qcom,init-voltage = <720000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ L5A_AO: pm8150_l5_ao: regulator-pm8150-l5-ao {
+ regulator-name = "pm8150_l5_ao";
+ qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1056000>;
+ qcom,init-voltage = <720000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ regulator-pm8150-l5-so {
+ regulator-name = "pm8150_l5_so";
+ qcom,set = <RPMH_REGULATOR_SET_SLEEP>;
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <1056000>;
+ qcom,init-voltage = <720000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ qcom,init-enable = <0>;
+ };
+ };
+
+ rpmh-regulator-ldoa6 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa6";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L6A: pm8150_l6: regulator-pm8150-l6 {
+ regulator-name = "pm8150_l6";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1096000>;
+ regulator-max-microvolt = <1248000>;
+ qcom,init-voltage = <1096000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa7 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa7";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L7A: pm8150_l7: regulator-pm8150-l7 {
+ regulator-name = "pm8150_l7";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1648000>;
+ regulator-max-microvolt = <1904000>;
+ qcom,init-voltage = <1648000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa8 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa8";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L8A: pm8150_l8: regulator-pm8150-l8 {
+ regulator-name = "pm8150_l8";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <824000>;
+ qcom,init-voltage = <720000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa9 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa9";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ proxy-supply = <&pm8150_l9>;
+ L9A: pm8150_l9: regulator-pm8150-l9 {
+ regulator-name = "pm8150_l9";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1152000>;
+ regulator-max-microvolt = <1320000>;
+ qcom,proxy-consumer-enable;
+ qcom,proxy-consumer-current = <51800>;
+ qcom,init-voltage = <1152000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa10 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa10";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L10A: pm8150_l10: regulator-pm8150-l10 {
+ regulator-name = "pm8150_l10";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3304000>;
+ qcom,init-voltage = <3000000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa11 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa11";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L11A: pm8150_l11: regulator-pm8150-l11 {
+ regulator-name = "pm8150_l11";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <696000>;
+ regulator-max-microvolt = <880000>;
+ qcom,init-voltage = <696000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa12 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa12";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L12A: pm8150_l12: regulator-pm8150-l12 {
+ regulator-name = "pm8150_l12";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1890000>;
+ qcom,init-voltage = <1710000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ L12A_AO: pm8150_l12_ao: regulator-pm8150-l12-ao {
+ regulator-name = "pm8150_l12_ao";
+ qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1890000>;
+ qcom,init-voltage = <1710000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ L12A_SO: pm8150_l12_so: regulator-pm8150-l12-so {
+ regulator-name = "pm8150_l12_so";
+ qcom,set = <RPMH_REGULATOR_SET_SLEEP>;
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1890000>;
+ qcom,init-voltage = <1710000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ qcom,init-enable = <0>;
+ };
+ };
+
+ rpmh-regulator-ldoa13 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa13";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L13A: pm8150_l13: regulator-pm8150-l13 {
+ regulator-name = "pm8150_l13";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3304000>;
+ qcom,init-voltage = <3008000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa14 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa14";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L14A: pm8150_l14: regulator-pm8150-l14 {
+ regulator-name = "pm8150_l14";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1616000>;
+ regulator-max-microvolt = <1984000>;
+ qcom,init-voltage = <1616000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa15 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa15";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L15A: pm8150_l15: regulator-pm8150-l15 {
+ regulator-name = "pm8150_l15";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <1900000>;
+ qcom,init-voltage = <1600000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa16 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa16";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ proxy-supply = <&pm8150_l16>;
+ L16A: pm8150_l16: regulator-pm8150-l16 {
+ regulator-name = "pm8150_l16";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <3304000>;
+ qcom,proxy-consumer-enable;
+ qcom,proxy-consumer-current = <857000>;
+ qcom,init-voltage = <2600000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoa17 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoa17";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L17A: pm8150_l17: regulator-pm8150-l17 {
+ regulator-name = "pm8150_l17";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ /* PM8150 L18 = VDD_LPI_CX supply */
+ rpmh-regulator-lcxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "lcx.lvl";
+ L18A_LEVEL: pm8150_l18_level: regulator-pm8150-l18-level {
+ regulator-name = "pm8150_l18_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt
+ = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ lpi_cx_cdev: regulator-cdev {
+ compatible = "qcom,rpmh-reg-cdev";
+ mboxes = <&qmp_aop 0>;
+ qcom,reg-resource-name = "cx";
+ #cooling-cells = <2>;
+ };
+ };
+
+ rpmh-regulator-smpc2 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpc2";
+ S2C: pm8150a_s2: regulator-pm8150a-s2 {
+ regulator-name = "pm8150a_s2";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <800000>;
+ qcom,init-voltage = <600000>;
+ };
+ };
+
+ /* PM8150A S3 = VDD_EBI supply */
+ rpmh-regulator-ebilvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "ebi.lvl";
+ S3C_LEVEL: pm8150a_s3_level: regulator-pm8150a-s3 {
+ regulator-name = "pm8150a_s3_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt
+ = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ /* PM8150A S4 + S5 = VDD_MX supply */
+ rpmh-regulator-mxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "mx.lvl";
+ VDD_MX_LEVEL: S4C_LEVEL:
+ pm8150a_s4_level: regulator-pm8150a-s4-level {
+ regulator-name = "pm8150a_s4_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt
+ = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ VDD_MX_LEVEL_AO: S4C_LEVEL_AO:
+ pm8150a_s4_level_ao: regulator-pm8150a-s4-level-ao {
+ regulator-name = "pm8150a_s4_level_ao";
+ qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+ regulator-min-microvolt
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt
+ = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ /* PM8150A S6 = VDD_GX supply */
+ rpmh-regulator-gfxlvl {
+ compatible = "qcom,rpmh-arc-regulator";
+ qcom,resource-name = "gfx.lvl";
+ VDD_GFX_LEVEL: S6C_LEVEL:
+ pm8150a_s6_level: regulator-pm8150a-s6-level {
+ regulator-name = "pm8150a_s6_level";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt
+ = <RPMH_REGULATOR_LEVEL_MAX>;
+ qcom,init-voltage-level
+ = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ rpmh-regulator-smpc7 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpc7";
+ S7C: pm8150a_s7: regulator-pm8150a-s7 {
+ regulator-name = "pm8150a_s7";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1128000>;
+ regulator-max-microvolt = <1128000>;
+ qcom,init-voltage = <1128000>;
+ };
+ };
+
+ rpmh-regulator-smpc8 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "smpc8";
+ S8C: pm8150a_s8: regulator-pm8150a-s8 {
+ regulator-name = "pm8150a_s8";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <696000>;
+ regulator-max-microvolt = <1416000>;
+ qcom,init-voltage = <696000>;
+ };
+ };
+
+ rpmh-regulator-ldoc1 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc1";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ proxy-supply = <&pm8150a_l1>;
+ L1C: pm8150a_l1: regulator-pm8150a-l1 {
+ regulator-name = "pm8150a_l1";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1896000>;
+ qcom,proxy-consumer-enable;
+ qcom,proxy-consumer-current = <62000>;
+ qcom,init-voltage = <1800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc2 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc2";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L2C: pm8150a_l2: regulator-pm8150a-l2 {
+ regulator-name = "pm8150a_l2";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1144000>;
+ regulator-max-microvolt = <1328000>;
+ qcom,init-voltage = <1144000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc3 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc3";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L3C: pm8150a_l3: regulator-pm8150a-l3 {
+ regulator-name = "pm8150a_l3";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1136000>;
+ regulator-max-microvolt = <1264000>;
+ qcom,init-voltage = <1136000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc4 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc4";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L4C: pm8150a_l4: regulator-pm8150a-l4 {
+ regulator-name = "pm8150a_l4";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1712000>;
+ regulator-max-microvolt = <3304000>;
+ qcom,init-voltage = <1712000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc5 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc5";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L5C: pm8150a_l5: regulator-pm8150a-l5 {
+ regulator-name = "pm8150a_l5";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1712000>;
+ regulator-max-microvolt = <3304000>;
+ qcom,init-voltage = <1712000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc6 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc6";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L6C: pm8150a_l6: regulator-pm8150a-l6 {
+ regulator-name = "pm8150a_l6";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2960000>;
+ qcom,init-voltage = <1800000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc7 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc7";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L7C: pm8150a_l7: regulator-pm8150a-l7 {
+ regulator-name = "pm8150a_l7";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3304000>;
+ qcom,init-voltage = <2704000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc8 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc8";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L8C: pm8150a_l8: regulator-pm8150a-l8 {
+ regulator-name = "pm8150a_l8";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <1704000>;
+ regulator-max-microvolt = <1952000>;
+ qcom,init-voltage = <1704000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc9 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc9";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 10000>;
+ L9C: pm8150a_l9: regulator-pm8150a-l9 {
+ regulator-name = "pm8150a_l9";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3304000>;
+ qcom,init-voltage = <2704000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc10 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc10";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L10C: pm8150a_l10: regulator-pm8150a-l10 {
+ regulator-name = "pm8150a_l10";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ qcom,init-voltage = <3000000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-ldoc11 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "ldoc11";
+ qcom,regulator-type = "pmic5-ldo";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1>;
+ L11C: pm8150a_l11: regulator-pm8150a-l11 {
+ regulator-name = "pm8150a_l11";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3312000>;
+ qcom,init-voltage = <3000000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
+
+ rpmh-regulator-bobc1 {
+ compatible = "qcom,rpmh-vrm-regulator";
+ qcom,resource-name = "bobc1";
+ qcom,regulator-type = "pmic5-bob";
+ qcom,supported-modes =
+ <RPMH_REGULATOR_MODE_PASS
+ RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
+ qcom,mode-threshold-currents = <0 1000000 2000000>;
+ qcom,send-defaults;
+
+ BOB: pm8150a_bob: regulator-pm8150a-bob {
+ regulator-name = "pm8150a_bob";
+ qcom,set = <RPMH_REGULATOR_SET_ALL>;
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ qcom,init-voltage = <3008000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_PASS>;
+ };
+
+ BOB_AO: pm8150a_bob_ao: regulator-pm8150a-bob-ao {
+ regulator-name = "pm8150a_bob_ao";
+ qcom,set = <RPMH_REGULATOR_SET_ACTIVE>;
+ regulator-min-microvolt = <3008000>;
+ regulator-max-microvolt = <3960000>;
+ qcom,init-voltage = <3008000>;
+ qcom,init-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+ };
+};
+
+&soc {
+ refgen: refgen-regulator@ff1000 {
+ compatible = "qcom,refgen-kona-regulator";
+ reg = <0xff1000 0x84>;
+ regulator-name = "refgen";
+ regulator-enable-ramp-delay = <5>;
+ proxy-supply = <&refgen>;
+ qcom,proxy-consumer-enable;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-rumi-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lito-rumi-overlay.dts
new file mode 100755
index 0000000..6e4bbd4
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-rumi-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lito-rumi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito RUMI";
+ compatible = "qcom,lito-rumi", "qcom,lito", "qcom,rumi";
+ qcom,msm-id = <400 0x10000>;
+ qcom,board-id = <15 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-rumi.dts b/arch/arm64/boot/dts/vendor/qcom/lito-rumi.dts
new file mode 100755
index 0000000..bc3b6b1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-rumi.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/memreserve/ 0x90000000 0x00000100;
+
+#include "lito.dtsi"
+#include "lito-rumi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito RUMI";
+ compatible = "qcom,lito-rumi", "qcom,lito", "qcom,rumi";
+ qcom,board-id = <15 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-rumi.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-rumi.dtsi
new file mode 100755
index 0000000..a9934b1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-rumi.dtsi
@@ -0,0 +1,162 @@
+&soc {
+ timer {
+ clock-frequency = <500000>;
+ };
+
+ timer@17c20000 {
+ clock-frequency = <500000>;
+ };
+
+ usb_emu_phy: usb_emu_phy@a720000 {
+ compatible = "qcom,usb-emu-phy";
+ reg = <0x0a720000 0x9500>,
+ <0x0a6f8800 0x100>;
+ reg-names = "base", "qscratch_base";
+
+ qcom,emu-init-seq = <0xfff0 0x4
+ 0xfff3 0x4
+ 0x40 0x4
+ 0xfff3 0x4
+ 0xfff0 0x4
+ 0x100000 0x20
+ 0x0 0x20
+ 0x1a0 0x20
+ 0x100000 0x3c
+ 0x0 0x3c
+ 0x10060 0x3c
+ 0x0 0x4>;
+ };
+
+ cxo: bi_tcxo {
+ compatible = "fixed-factor-clock";
+ clocks = <&xo_board>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ #clock-cells = <0>;
+ };
+
+ cxo_a: bi_tcxo_ao {
+ compatible = "fixed-factor-clock";
+ clocks = <&xo_board>;
+ clock-mult = <1>;
+ clock-div = <2>;
+ #clock-cells = <0>;
+ };
+};
+
+&rpmhcc {
+ compatible = "qcom,dummycc";
+ clock-output-names = "rpmh_clocks";
+};
+
+&aopcc {
+ compatible = "qcom,dummycc";
+ clock-output-names = "qdss_clocks";
+};
+
+&usb0 {
+ dwc3@a600000 {
+ usb-phy = <&usb_emu_phy>, <&usb_nop_phy>;
+ maximum-speed = "high-speed";
+ };
+};
+
+&usb2_phy0 {
+ hsphy@88e3000 {
+ status = "disabled";
+ };
+};
+
+&qupv3_se8_2uart {
+ status = "disabled";
+};
+
+/*RUMI UART console*/
+&qupv3_se2_2uart {
+ status = "ok";
+};
+
+&wdog {
+ status = "disabled";
+};
+
+&ufsphy_mem {
+ compatible = "qcom,ufs-phy-qrbtc-sdm845";
+
+ vdda-phy-supply = <&pm8150_l5>;
+ vdda-pll-supply = <&pm8150_l6>;
+ vdda-phy-max-microamp = <90200>;
+ vdda-pll-max-microamp = <19000>;
+
+ status = "ok";
+};
+
+&ufshc_mem {
+ limit-tx-hs-gear = <1>;
+ limit-rx-hs-gear = <1>;
+
+ vdd-hba-supply = <&ufs_phy_gdsc>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm8150a_l7>;
+ vccq2-supply = <&pm8150_s4>;
+ vcc-max-microamp = <800000>;
+ vccq2-max-microamp = <800000>;
+
+ qcom,vddp-ref-clk-supply = <&pm8150_l6>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+
+ qcom,disable-lpm;
+ rpm-level = <0>;
+ spm-level = <0>;
+ status = "ok";
+};
+
+&sdhc_1 {
+ vdd-supply = <&pm8150a_l7>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&pm8150_s4>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000>;
+ qcom,bus-speed-mode = "DDR_1p8v";
+
+ /delete-property/qcom,devfreq,freq-table;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&pm8150a_l9>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&pm8150a_l6>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50";
+
+ /delete-property/qcom,devfreq,freq-table;
+
+ status = "ok";
+};
+
+&qupv3_se9_i2c {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-sde-display.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-sde-display.dtsi
new file mode 100755
index 0000000..3e85d3e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-sde-display.dtsi
@@ -0,0 +1,764 @@
+#include "dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi"
+#include "dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi"
+#include "dsi-panel-sw43404-amoled-dsc-fhd-plus-cmd.dtsi"
+#include "dsi-panel-sharp-dualdsi-wqhd-video.dtsi"
+#include "dsi-panel-sharp-dualdsi-wqhd-cmd.dtsi"
+#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
+#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
+#include "dsi-panel-sharp-qsync-wqhd-cmd.dtsi"
+#include "dsi-panel-sharp-qsync-wqhd-video.dtsi"
+#include "dsi-panel-sharp-qsync-fhd-cmd.dtsi"
+#include "dsi-panel-sharp-qsync-fhd-video.dtsi"
+#include "dsi-panel-sharp-dsc-4k-cmd.dtsi"
+#include "dsi-panel-sharp-dsc-4k-video.dtsi"
+#include "dsi-panel-sim-cmd.dtsi"
+#include "dsi-panel-sim-video.dtsi"
+#include "dsi-panel-sim-dsc375-cmd.dtsi"
+#include "dsi-panel-sim-dualmipi-cmd.dtsi"
+#include "dsi-panel-sim-dualmipi-video.dtsi"
+#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
+#include "dsi-panel-sim-sec-hd-cmd.dtsi"
+#include "dsi-panel-rm69299-visionox-fhd-plus-video.dtsi"
+#include "dsi-panel-r66451-dsc-fhd-plus-144hz-cmd.dtsi"
+#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
+
+&pm8150l_gpios {
+ disp_pins {
+ disp_pins_default: disp_pins_default {
+ pins = "gpio3";
+ function = "func1";
+ qcom,drive-strength = <2>;
+ power-source = <0>;
+ bias-disable;
+ output-low;
+ };
+ };
+};
+
+&soc {
+ ext_disp: qcom,msm-ext-disp {
+ compatible = "qcom,msm-ext-disp";
+
+ ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
+ compatible = "qcom,msm-ext-disp-audio-codec-rx";
+ };
+ };
+
+ dsi_panel_pwr_supply: dsi_panel_pwr_supply {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "vdd";
+ qcom,supply-min-voltage = <3000000>;
+ qcom,supply-max-voltage = <3000000>;
+ qcom,supply-enable-load = <857000>;
+ qcom,supply-disable-load = <0>;
+ qcom,supply-post-on-sleep = <0>;
+ };
+
+ qcom,panel-supply-entry@2 {
+ reg = <2>;
+ qcom,supply-name = "lab";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@3 {
+ reg = <3>;
+ qcom,supply-name = "ibb";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+ };
+
+ dsi_panel_pwr_supply_avdd: dsi_panel_pwr_supply_avdd {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "avdd";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+ };
+
+ dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+ };
+
+ sde_dsi: qcom,dsi-display-primary {
+ compatible = "qcom,dsi-display";
+ label = "primary";
+
+ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+ qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+
+ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll PCLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll PCLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll SHADOW_BYTECLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll SHADOW_PCLK_SRC_0_CLK>,
+ <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
+ <&mdss_dsi1_pll PCLK_MUX_1_CLK>,
+ <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>,
+ <&mdss_dsi1_pll PCLK_SRC_1_CLK>,
+ <&mdss_dsi1_pll SHADOW_BYTECLK_SRC_1_CLK>,
+ <&mdss_dsi1_pll SHADOW_PCLK_SRC_1_CLK>;
+ clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0",
+ "mux_byte_clk1", "mux_pixel_clk1",
+ "src_byte_clk1", "src_pixel_clk1",
+ "shadow_byte_clk1", "shadow_pixel_clk1";
+
+ pinctrl-names = "panel_active", "panel_suspend";
+ pinctrl-0 = <&sde_te_active &disp_pins_default>;
+ pinctrl-1 = <&sde_te_suspend>;
+
+ qcom,platform-te-gpio = <&tlmm 10 0>;
+ qcom,panel-te-source = <0>;
+
+ vddio-supply = <&L1C>;
+ vdd-supply = <&L16A>;
+ lab-supply = <&ab_vreg>;
+ ibb-supply = <&ibb_vreg>;
+
+ qcom,mdp = <&mdss_mdp>;
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_video>;
+ };
+
+ sde_dsi1: qcom,dsi-display-secondary {
+ compatible = "qcom,dsi-display";
+ label = "secondary";
+
+ qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
+ qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
+
+ clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
+ <&mdss_dsi0_pll PCLK_MUX_0_CLK>,
+ <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
+ <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
+ clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+ "mux_byte_clk1", "mux_pixel_clk1";
+
+ pinctrl-names = "panel_active", "panel_suspend";
+ pinctrl-0 = <&sde_te1_active>;
+ pinctrl-1 = <&sde_te1_suspend>;
+
+ qcom,platform-te-gpio = <&tlmm 11 0>;
+ qcom,panel-te-source = <1>;
+
+ vddio-supply = <&L1C>;
+ vdd-supply = <&L16A>;
+
+ qcom,mdp = <&mdss_mdp>;
+ };
+
+ sde_wb: qcom,wb-display@0 {
+ compatible = "qcom,wb-display";
+ cell-index = <0>;
+ label = "wb_display";
+ };
+
+ msm_notifier: qcom,msm_notifier@0 {
+ compatible = "qcom,msm-notifier";
+ panel = <&dsi_sw43404_amoled_cmd &dsi_sharp_qsync_wqhd_cmd
+ &dsi_dual_sim_dsc_375_cmd &dsi_sw43404_amoled_video
+ &dsi_sharp_qsync_wqhd_video &dsi_sharp_qsync_fhd_cmd
+ &dsi_sharp_qsync_fhd_video>;
+ };
+};
+
+&sde_dp {
+ qcom,dp-usbpd-detection = <&pm7250b_pdphy>;
+ qcom,ext-disp = <&ext_disp>;
+ qcom,dp-aux-switch = <&fsa4480>;
+ extcon = <&pm7250b_pdphy>;
+
+ qcom,usbplug-cc-gpio = <&tlmm 114 0>;
+
+ pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
+ pinctrl-0 = <&sde_dp_usbplug_cc_active>;
+ pinctrl-1 = <&sde_dp_usbplug_cc_suspend>;
+};
+
+&mdss_mdp {
+ connectors = <&sde_wb &sde_dsi &sde_dsi1 &sde_dp &sde_rscc>;
+};
+
+&dsi_rm69299_visionox_amoled_video {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 20 08 08 24 23 08
+ 08 05 02 04 00 1a 18];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+/* PHY TIMINGS REVISION W */
+&dsi_sw43404_amoled_cmd {
+ qcom,ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+
+ qcom,dsi-dyn-clk-enable;
+ qcom,dsi-dyn-clk-list = <552424501 549895420 547366339>;
+
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
+ 05 03 02 04 00 12 15];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 1f 1e 05
+ 05 03 02 04 00 12 14];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-phy-timings = [00 11 03 04 1e 1e 04
+ 04 02 02 04 00 10 14];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 180 180 180 1440 180>;
+ };
+ };
+};
+
+&dsi_sw43404_amoled_video {
+ qcom,dsi-supported-dfps-list = <60 57 55>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_hfp";
+ qcom,mdss-dsi-min-refresh-rate = <55>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-qsync-min-refresh-rate = <55>;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+
+ qcom,dsi-dyn-clk-enable;
+ qcom,dsi-dyn-clk-list =
+ <534712320 536940288 539168256>;
+ qcom,dsi-dyn-clk-type = "constant-fps-adjust-hfp";
+
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 14 05 05 1f 1e 05
+ 05 03 02 04 00 12 15];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sw43404_amoled_fhd_plus_cmd {
+ qcom,ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 12 04 04 1e 1e 04
+ 05 02 03 04 00 11 14];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 270 270 270 1080 270>;
+ qcom,mdss-dsi-panel-clockrate = <380000000>;
+ };
+ };
+};
+
+&dsi_sim_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ qcom,panel-roi-alignment = <720 40 720 40 720 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+
+ timing@3 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ qcom,panel-roi-alignment = <540 40 540 40 540 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+
+ timing@4 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>;
+ qcom,default-topology-index = <1>;
+ qcom,panel-roi-alignment = <360 40 360 40 360 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+ };
+};
+
+&dsi_sim_vid {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 0 1>,
+ <2 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_dsc_375_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 { /* 1080p */
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <1 1 1>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 { /* qhd */
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <1 1 1>,
+ <2 2 1>, /* dsc merge */
+ <2 1 1>; /* 3d mux */
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_sim_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
+ 09 06 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_sim_vid {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 0 2>,
+ <1 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_sim_dsc_375_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 { /* qhd */
+ qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22 07
+ 07 05 02 04 00 18 17];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 { /* 4k */
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 { /* 5k */
+ qcom,mdss-dsi-panel-phy-timings = [00 46 13 14 33 30 12
+ 14 0e 02 04 00 37 22];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sim_sec_hd_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
+ 08 08 05 02 04 00 19 17];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ qcom,panel-roi-alignment = <720 40 720 40 720 40>;
+ qcom,partial-update-enabled = "single_roi";
+ };
+ };
+};
+
+&dsi_dual_sharp_wqhd_video {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21
+ 07 07 04 02 04 00 17 16];
+ qcom,display-topology = <2 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_dual_sharp_wqhd_cmd {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1b 07 06 22 21
+ 07 07 04 02 04 00 17 16];
+ qcom,display-topology = <2 0 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sharp_4k_dsc_cmd {
+ qcom,ulps-enabled;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sharp_4k_dsc_video {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22 08
+ 08 05 02 04 00 19 18];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
+ 08 08 05 02 04 00 19 17];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-supported-dfps-list = <60 55 48>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+ qcom,mdss-dsi-min-refresh-rate = <48>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,dsi-select-sec-clocks = "mux_byte_clk1", "mux_pixel_clk1";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 1e 08 07 24 22
+ 08 08 05 02 04 00 19 17];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sharp_qsync_wqhd_cmd {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 { /* WQHD 60FPS CMD */
+ qcom,mdss-dsi-panel-phy-timings = [00 0b 03 02 1d 1c 03
+ 03 01 02 04 00 0c 12];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
+ };
+
+ timing@1 { /* WQHD 60FPS VID */
+ qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06
+ 06 03 02 04 00 13 15];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@2 { /* FHD 60FPS CMD */
+ qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 1b 1c 02
+ 02 00 02 04 00 0a 12];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
+ };
+
+ timing@3 { /* WQHD 90FPS CMD */
+ qcom,mdss-dsi-panel-phy-timings = [00 10 03 03 1e 1e 04
+ 04 02 02 04 00 0f 13];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
+ };
+
+ timing@4 { /* WQHD 120FPS CMD */
+ qcom,mdss-dsi-panel-phy-timings = [00 13 05 04 1f 1e 05
+ 05 03 02 04 00 12 14];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 8 8 8 1440 8>;
+ };
+
+ timing@5 { /* WQHD 120FPS VID */
+ qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06
+ 06 03 02 04 00 13 15];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@6 { /* FHD 120FPS CMD */
+ qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04
+ 04 02 02 04 00 0e 13];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
+ };
+
+ timing@7 { /* FHD 90FPS CMD */
+ qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03
+ 02 01 02 04 00 0c 12];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
+ };
+ };
+};
+
+
+&dsi_sharp_qsync_wqhd_video {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,dsi-supported-dfps-list = <120 90 60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+ qcom,mdss-dsi-min-refresh-rate = <60>;
+ qcom,mdss-dsi-max-refresh-rate = <120>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 16 06 05 20 1f 06
+ 06 03 02 04 00 13 15];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sharp_qsync_fhd_video {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,dsi-supported-dfps-list = <120 90 60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+ qcom,mdss-dsi-min-refresh-rate = <60>;
+ qcom,mdss-dsi-max-refresh-rate = <120>;
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 13 04 04 1f 1f 04
+ 05 03 02 04 00 12 14];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_sharp_qsync_fhd_cmd {
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 0a 01 02 1b 1c 02
+ 02 00 02 04 00 0a 12];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings = [00 0e 03 03 1e 1d 04
+ 04 02 02 04 00 0e 13];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
+ };
+
+ timing@2 {
+ qcom,mdss-dsi-panel-phy-timings = [00 0b 02 02 1c 1c 03
+ 02 01 02 04 00 0c 12];
+ qcom,display-topology = <2 2 2>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <540 8 8 8 1080 8>;
+ };
+ };
+};
+
+&dsi_r66451_amoled_144hz_cmd {
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x1c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings = [00 22 09 09 19 17 09
+ 09 09 02 04 00 1d 0e];
+ qcom,display-topology = <2 2 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-sde-pll.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-sde-pll.dtsi
new file mode 100755
index 0000000..9bbeb99
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-sde-pll.dtsi
@@ -0,0 +1,67 @@
+&soc {
+ mdss_dsi0_pll: qcom,mdss_dsi0_pll {
+ compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
+ label = "MDSS DSI 0 PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+ reg = <0xae94900 0x280>,
+ <0xae94400 0x800>,
+ <0xaf03000 0x8>,
+ <0xae94200 0x100>;
+ reg-names = "pll_base", "phy_base", "gdsc_base",
+ "dynamic_pll_base";
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ memory-region = <&dfps_data_memory>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ };
+
+ mdss_dsi1_pll: qcom,mdss_dsi1_pll {
+ compatible = "qcom,mdss_dsi_pll_7nm_v4_1";
+ label = "MDSS DSI 1 PLL";
+ cell-index = <1>;
+ #clock-cells = <1>;
+ reg = <0xae96900 0x280>,
+ <0xae96400 0x800>,
+ <0xaf03000 0x8>,
+ <0xae96200 0x100>;
+ reg-names = "pll_base", "phy_base", "gdsc_base",
+ "dynamic_pll_base";
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ };
+ mdss_dp_pll: qcom,mdss_dp_pll@c011000 {
+ compatible = "qcom,mdss_dp_pll_7nm_v2";
+ label = "MDSS DP PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+
+ reg = <0x088ea000 0x200>,
+ <0x088eaa00 0x200>,
+ <0x088ea200 0x200>,
+ <0x088ea2c0 0x8>,
+ <0x088ea2c8 0x4>,
+ <0x088ea600 0x200>,
+ <0x088ea6c0 0x8>,
+ <0x088ea6c8 0x4>,
+ <0xaf03000 0x8>;
+ reg-names = "pll_base", "phy_base",
+ "ln_tx0_base", "ln_tx0_tran_base", "ln_tx0_vmode_base",
+ "ln_tx1_base", "ln_tx1_tran_base", "ln_tx1_vmode_base",
+ "gdsc_base";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "iface_clk", "ref_clk_src",
+ "gcc_iface", "pipe_clk";
+ clock-rate = <0>;
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-sde.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-sde.dtsi
new file mode 100755
index 0000000..a5b8501
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-sde.dtsi
@@ -0,0 +1,706 @@
+#include <dt-bindings/clock/mdss-7nm-pll-clk.h>
+
+&soc {
+ mdss_mdp: qcom,mdss_mdp {
+ compatible = "qcom,sde-kms";
+ reg = <0xae00000 0x84208>,
+ <0xaeb0000 0x2008>,
+ <0xaeac000 0x214>,
+ <0xae8f000 0x02c>,
+ <0xaf50000 0x038>;
+ reg-names = "mdp_phys",
+ "vbif_phys",
+ "regdma_phys",
+ "sid_phys",
+ "swfuse_phys";
+
+ clocks =
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>;
+ clock-names = "gcc_iface", "gcc_bus", "gcc_nrt_bus",
+ "iface_clk", "core_clk", "vsync_clk",
+ "lut_clk", "rot_clk";
+ clock-rate = <0 0 0 0 460000000 19200000 460000000
+ 200000000>;
+ clock-max-rate = <0 0 0 0 460000000 19200000 460000000
+ 460000000>;
+
+ /* interrupt config */
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #power-domain-cells = <0>;
+
+ /* hw blocks */
+ qcom,sde-off = <0x1000>;
+ qcom,sde-len = <0x494>;
+
+ qcom,sde-ctl-off = <0x2000 0x2200 0x2400 0x2600>;
+ qcom,sde-ctl-size = <0x1dc>;
+ qcom,sde-ctl-display-pref = "primary", "none", "none", "none";
+
+ qcom,sde-mixer-off = <0x45000 0x46000 0x47000 0x48000>;
+ qcom,sde-mixer-size = <0x320>;
+ qcom,sde-mixer-display-pref = "primary", "primary", "none",
+ "none";
+ qcom,sde-mixer-cwb-pref = "none", "none", "cwb", "cwb";
+
+ qcom,sde-dspp-top-off = <0x1300>;
+ qcom,sde-dspp-top-size = <0x80>;
+ qcom,sde-dspp-off = <0x55000 0x57000>;
+ qcom,sde-dspp-size = <0x1800>;
+
+ qcom,sde-dest-scaler-top-off = <0x00061000>;
+ qcom,sde-dest-scaler-top-size = <0x1c>;
+ qcom,sde-dest-scaler-off = <0x800 0x1000>;
+ qcom,sde-dest-scaler-size = <0x800>;
+
+ qcom,sde-wb-off = <0x66000>;
+ qcom,sde-wb-size = <0x2c8>;
+ qcom,sde-wb-xin-id = <6>;
+ qcom,sde-wb-id = <2>;
+ qcom,sde-wb-clk-ctrl = <0x2bc 16>;
+
+ qcom,sde-intf-off = <0x6b000 0x6b800
+ 0x6c000 0x6c800>;
+ qcom,sde-intf-size = <0x2b8>;
+ qcom,sde-intf-type = "dp", "dsi", "dsi", "dp";
+
+ qcom,sde-pp-off = <0x71000 0x71800 0x72000 0x72800>;
+ qcom,sde-pp-slave = <0x0 0x0 0x0 0x1>;
+ qcom,sde-pp-size = <0xd4>;
+ qcom,sde-pp-merge-3d-id = <0x0 0x0 0x1 0x1>;
+
+ qcom,sde-merge-3d-off = <0x84000 0x84100>;
+ qcom,sde-merge-3d-size = <0x100>;
+
+ qcom,sde-te2-off = <0x2000 0x2000 0x0 0x0>;
+
+ qcom,sde-cdm-off = <0x7a200>;
+ qcom,sde-cdm-size = <0x224>;
+
+ qcom,sde-dsc-off = <0x81000 0x81400>;
+ qcom,sde-dsc-size = <0x140>;
+ qcom,sde-dsc-pair-mask = <2 1>;
+
+ qcom,sde-dither-off = <0x30e0 0x30e0 0x30e0
+ 0x30e0>;
+ qcom,sde-dither-version = <0x00010000>;
+ qcom,sde-dither-size = <0x20>;
+
+ qcom,sde-sspp-type = "vig", "vig",
+ "dma", "dma", "dma";
+ qcom,sde-sspp-off = <0x5000 0x7000 0x25000 0x27000 0x29000>;
+ qcom,sde-sspp-src-size = <0x1f8>;
+ qcom,sde-sspp-xin-id = <0 4 1 5 9>;
+ qcom,sde-sspp-excl-rect = <1 1 1 1 1>;
+ qcom,sde-sspp-smart-dma-priority = <4 5 1 2 3>;
+ qcom,sde-smart-dma-rev = "smart_dma_v2p5";
+
+ qcom,sde-mixer-pair-mask = <2 1 4 3>;
+
+ qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
+ 0xb0 0xc8 0xe0>;
+
+ qcom,sde-max-per-pipe-bw-kbps = <4700000 4700000
+ 4700000 4700000
+ 4700000>;
+
+ qcom,sde-max-per-pipe-bw-high-kbps = <4700000 4700000
+ 4700000 4700000
+ 4700000>;
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+ qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2b4 0>,
+ <0x2ac 8>, <0x2b4 8>, <0x2c4 8>;
+ qcom,sde-sspp-csc-off = <0x1a00>;
+ qcom,sde-csc-type = "csc-10bit";
+ qcom,sde-qseed-type = "qseedv3lite";
+ qcom,sde-sspp-qseed-off = <0xa00>;
+ qcom,sde-mixer-linewidth = <2560>;
+ qcom,sde-sspp-linewidth = <2880>;
+ qcom,sde-vig-sspp-linewidth = <4096>;
+ qcom,sde-wb-linewidth = <4096>;
+ qcom,sde-mixer-blendstages = <0x9>;
+ qcom,sde-highest-bank-bit = <0x1>;
+ qcom,sde-ubwc-version = <0x300>;
+ qcom,sde-ubwc-swizzle = <0x6>;
+ qcom,sde-ubwc-bw-calc-version = <0x1>;
+ qcom,sde-ubwc-static = <0x1>;
+ qcom,sde-macrotile-mode = <0x1>;
+ qcom,sde-smart-panel-align-mode = <0xc>;
+ qcom,sde-panic-per-pipe;
+ qcom,sde-has-cdp;
+ qcom,sde-has-src-split;
+ qcom,sde-pipe-order-version = <0x1>;
+ qcom,sde-has-dim-layer;
+ qcom,sde-has-dest-scaler;
+ qcom,sde-has-idle-pc;
+ qcom,sde-max-dest-scaler-input-linewidth = <2048>;
+ qcom,sde-max-dest-scaler-output-linewidth = <2560>;
+ qcom,sde-max-bw-low-kbps = <5800000>;
+ qcom,sde-max-bw-high-kbps = <8600000>;
+ qcom,sde-min-core-ib-kbps = <4800000>;
+ qcom,sde-min-llcc-ib-kbps = <0>;
+ qcom,sde-min-dram-ib-kbps = <800000>;
+ qcom,sde-dram-channels = <2>;
+ qcom,sde-num-nrt-paths = <0>;
+ qcom,sde-dspp-ltm-version = <0x00010000>;
+ /* offsets are based off dspp 0 and dspp 1 */
+ qcom,sde-dspp-ltm-off = <0x2a000 0x28100>;
+
+ qcom,sde-vbif-off = <0>;
+ qcom,sde-vbif-size = <0x1040>;
+ qcom,sde-vbif-id = <0>;
+ qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
+
+ qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
+ qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-qos-cwb-remap = <3 3 4 4 5 5 6 6>;
+ qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 4>;
+
+ /* macrotile & macrotile-qseed has the same configs */
+ qcom,sde-danger-lut = <0x000000ff 0x0000ffff
+ 0x00000000 0x00000000 0x0000ffff>;
+
+ qcom,sde-safe-lut-linear = <0 0xfffc>;
+ qcom,sde-safe-lut-macrotile = <0 0xff00>;
+ /* same as safe-lut-macrotile */
+ qcom,sde-safe-lut-macrotile-qseed = <0 0xff00>;
+ qcom,sde-safe-lut-nrt = <0 0xffff>;
+ qcom,sde-safe-lut-cwb = <0 0x3ff>;
+
+ /* creq LUTs */
+ qcom,sde-qos-lut-linear = <0 0x00112222 0x22223357>;
+ qcom,sde-qos-lut-macrotile = <0 0x00112233 0x44556677>;
+ qcom,sde-qos-lut-macrotile-qseed = <0 0x00112233 0x66777777>;
+ qcom,sde-qos-lut-nrt = <0 0x00000000 0x00000000>;
+ qcom,sde-qos-lut-cwb = <0 0x66666541 0x00000000>;
+
+ qcom,sde-cdp-setting = <1 1>, <1 0>;
+
+ qcom,sde-qos-cpu-mask = <0x3>;
+ qcom,sde-qos-cpu-dma-latency = <300>;
+ qcom,sde-qos-cpu-irq-latency = <300>;
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+
+ qcom,sde-reg-dma-off = <0>;
+ qcom,sde-reg-dma-version = <0x00010002>;
+ qcom,sde-reg-dma-trigger-off = <0x119c>;
+ qcom,sde-reg-dma-xin-id = <7>;
+ qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;
+
+ qcom,sde-secure-sid-mask = <0xb41 0xf41>;
+
+ qcom,sde-sspp-vig-blocks {
+ qcom,sde-vig-csc-off = <0x1a00>;
+ qcom,sde-vig-qseed-off = <0xa00>;
+ qcom,sde-vig-qseed-size = <0xa0>;
+ qcom,sde-vig-gamut = <0x1d00 0x00060000>;
+ qcom,sde-vig-igc = <0x1d00 0x00060000>;
+ qcom,sde-vig-inverse-pma;
+ };
+
+ qcom,sde-sspp-dma-blocks {
+ dgm@0 {
+ qcom,sde-dma-igc = <0x400 0x00050000>;
+ qcom,sde-dma-gc = <0x600 0x00050000>;
+ qcom,sde-dma-inverse-pma;
+ qcom,sde-dma-csc-off = <0x200>;
+ };
+
+ dgm@1 {
+ qcom,sde-dma-igc = <0x1400 0x00050000>;
+ qcom,sde-dma-gc = <0x600 0x00050000>;
+ qcom,sde-dma-inverse-pma;
+ qcom,sde-dma-csc-off = <0x1200>;
+ };
+ };
+
+ qcom,sde-dspp-blocks {
+ qcom,sde-dspp-igc = <0x0 0x00030001>;
+ qcom,sde-dspp-hsic = <0x800 0x00010007>;
+ qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+ qcom,sde-dspp-hist = <0x800 0x00010007>;
+ qcom,sde-dspp-sixzone= <0x900 0x00010007>;
+ qcom,sde-dspp-vlut = <0xa00 0x00010008>;
+ qcom,sde-dspp-gamut = <0x1000 0x00040002>;
+ qcom,sde-dspp-pcc = <0x1700 0x00040000>;
+ qcom,sde-dspp-gc = <0x17c0 0x00010008>;
+ qcom,sde-dspp-dither = <0x82c 0x00010007>;
+ };
+
+ smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
+ compatible = "qcom,smmu_sde_unsec";
+ iommus = <&apps_smmu 0xb40 0x402>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-earlymap; /* for cont-splash */
+ };
+
+ smmu_sde_sec: qcom,smmu_sde_sec_cb {
+ compatible = "qcom,smmu_sde_sec";
+ iommus = <&apps_smmu 0xb41 0x0>,
+ <&apps_smmu 0xf41 0x0>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xa>;
+ };
+
+ /* data and reg bus scale settings */
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "mdss_sde";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>, <23 512 0 0>,
+ <22 512 0 6400000>, <23 512 0 6400000>,
+ <22 512 0 6400000>, <23 512 0 6400000>;
+ };
+
+ qcom,sde-reg-bus {
+ qcom,msm-bus,name = "mdss_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 150000>,
+ <1 590 0 300000>;
+ };
+
+ qcom,sde-limits {
+ qcom,sde-linewidth-limits {
+ qcom,sde-limit-name = "sspp_linewidth_usecases";
+ qcom,sde-limit-cases = "vig", "dma", "scale", "inline_rot";
+ qcom,sde-limit-ids= <0x1 0x2 0x4 0x8>;
+ qcom,sde-limit-values = <0x1 4096>,
+ <0x5 2560>,
+ <0x2 2880>,
+ <0x9 1088>;
+ };
+
+ qcom,sde-bw-limits {
+ qcom,sde-limit-name = "sde_bwlimit_usecases";
+ qcom,sde-limit-cases = "per_vig_pipe",
+ "per_dma_pipe",
+ "total_max_bw",
+ "camera_concurrency",
+ "cwb_concurrency";
+ qcom,sde-limit-ids = <0x1 0x2 0x4 0x8 0x10>;
+ qcom,sde-limit-values = <0x1 4700000>,
+ <0x11 4700000>,
+ <0x9 4700000>,
+ <0x19 4700000>,
+ <0x2 4700000>,
+ <0x12 4700000>,
+ <0xa 4700000>,
+ <0x1a 4700000>,
+ <0x4 8600000>,
+ <0x14 8600000>,
+ <0xc 5800000>,
+ <0x1c 5800000>;
+ };
+ };
+ };
+
+ sde_rscc: qcom,sde_rscc {
+ cell-index = <0>;
+ compatible = "qcom,sde-rsc";
+ reg = <0xaf20000 0x3c50>,
+ <0xaf30000 0x3fd4>;
+ reg-names = "drv", "wrapper";
+ qcom,sde-rsc-version = <3>;
+
+ qcom,sde-dram-channels = <2>;
+
+ vdd-supply = <&mdss_core_gdsc>;
+ clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
+ clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
+
+ /* data and reg bus scale settings */
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "disp_rsc_mnoc_llcc";
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <20003 20513 0 0>, <20004 20513 0 0>,
+ <20003 20513 0 6400000>, <20004 20513 0 6400000>,
+ <20003 20513 0 6400000>, <20004 20513 0 6400000>;
+ };
+
+ qcom,sde-ebi-bus {
+ qcom,msm-bus,name = "disp_rsc_ebi";
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <20000 20512 0 0>,
+ <20000 20512 0 6400000>,
+ <20000 20512 0 6400000>;
+ };
+ qcom,sde-reg-bus {
+ qcom,msm-bus,name = "disp_rsc_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 150000>,
+ <1 590 0 300000>;
+ };
+ };
+
+ mdss_rotator: qcom,mdss_rotator {
+ status = "disabled";
+ compatible = "qcom,sde_rotator";
+ reg = <0xae00000 0xac000>,
+ <0xaeb8000 0x3000>;
+ reg-names = "mdp_phys",
+ "rot_vbif_phys";
+
+ #list-cells = <1>;
+
+ qcom,mdss-rot-mode = <1>;
+ qcom,mdss-highest-bank-bit = <0x3>;
+
+ /* Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_rotator";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <25 512 0 0>,
+ <25 512 0 6400000>,
+ <25 512 0 6400000>;
+
+ rot-vdd-supply = <&mdss_core_gdsc>;
+ qcom,supply-names = "rot-vdd";
+
+ clocks =
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_SF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>;
+ clock-names = "gcc_iface", "gcc_bus",
+ "iface_clk", "rot_clk";
+
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <2 0>;
+
+ power-domains = <&mdss_mdp>;
+
+ /* Offline rotator QoS setting */
+ qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
+ qcom,mdss-rot-vbif-memtype = <3 3>;
+ qcom,mdss-rot-cdp-setting = <1 1>;
+ qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
+ qcom,mdss-rot-danger-lut = <0x0 0x0>;
+ qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
+
+ qcom,mdss-default-ot-rd-limit = <32>;
+ qcom,mdss-default-ot-wr-limit = <32>;
+
+ qcom,mdss-sbuf-headroom = <20>;
+
+ /* reg bus scale settings */
+ rot_reg: qcom,rot-reg-bus {
+ qcom,msm-bus,name = "mdss_rot_reg";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>;
+ };
+
+ smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
+ compatible = "qcom,smmu_sde_rot_unsec";
+ iommus = <&apps_smmu 0x135C 0x0>;
+ };
+
+ smmu_rot_sec: qcom,smmu_rot_sec_cb {
+ compatible = "qcom,smmu_sde_rot_sec";
+ iommus = <&apps_smmu 0x135d 0x0>;
+ };
+ };
+
+ mdss_dsi0: qcom,mdss_dsi0_ctrl {
+ compatible = "qcom,dsi-ctrl-hw-v2.4";
+ label = "dsi-ctrl-0";
+ cell-index = <0>;
+ frame-threshold-time-us = <1000>;
+ reg = <0xae94000 0x400>,
+ <0xaf08000 0x4>;
+ reg-names = "dsi_ctrl", "disp_cc_base";
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <4 0>;
+ vdda-1p2-supply = <&L9A>;
+ refgen-supply = <&refgen>;
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>;
+ clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+ "pixel_clk", "pixel_clk_rcg", "esc_clk";
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1152000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <21800>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi1: qcom,mdss_dsi1_ctrl {
+ compatible = "qcom,dsi-ctrl-hw-v2.4";
+ label = "dsi-ctrl-1";
+ frame-threshold-time-us = <1000>;
+ cell-index = <1>;
+ reg = <0xae96000 0x400>,
+ <0xaf08000 0x4>;
+ reg-names = "dsi_ctrl", "disp_cc_base";
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <5 0>;
+ vdda-1p2-supply = <&L9A>;
+ refgen-supply = <&refgen>;
+ clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_ESC1_CLK>;
+ clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+ "pixel_clk", "pixel_clk_rcg", "esc_clk";
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1152000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <21800>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ sde_dp: qcom,dp_display@ae90000 {
+ cell-index = <0>;
+ compatible = "qcom,dp-display";
+
+ vdda-1p2-supply = <&L9A>;
+ reg = <0xae90000 0x0dc>,
+ <0xae90200 0x0c0>,
+ <0xae90400 0x508>,
+ <0xae91000 0x094>,
+ <0x88eaa00 0x198>,
+ <0x88ea200 0x150>,
+ <0x88ea600 0x150>,
+ <0xaf02000 0x2c4>,
+ <0x88ea040 0x10>,
+ <0x88e8000 0x20>,
+ <0x0aee1000 0x2a>,
+ <0xae91400 0x095>;
+ reg-names = "dp_ahb", "dp_aux", "dp_link",
+ "dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
+ "dp_mmss_cc", "dp_pll",
+ "usb3_dp_com", "hdcp_physical", "dp_p1";
+
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <12 0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>,
+ <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK_SRC>,
+ <&mdss_dp_pll DP_VCO_DIVIDED_CLK_SRC_MUX>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
+ clock-names = "core_aux_clk", "core_usb_pipe_clk",
+ "core_usb_ref_clk_src",
+ "link_clk", "link_iface_clk",
+ "pixel_clk_rcg", "pixel_parent",
+ "pixel1_clk_rcg", "pixel1_parent",
+ "strm0_pixel_clk", "strm1_pixel_clk";
+
+ qcom,phy-version = <0x420>;
+ qcom,aux-cfg0-settings = [20 00];
+ qcom,aux-cfg1-settings = [24 13];
+ qcom,aux-cfg2-settings = [28 A4];
+ qcom,aux-cfg3-settings = [2c 00];
+ qcom,aux-cfg4-settings = [30 0a];
+ qcom,aux-cfg5-settings = [34 26];
+ qcom,aux-cfg6-settings = [38 0a];
+ qcom,aux-cfg7-settings = [3c 03];
+ qcom,aux-cfg8-settings = [40 b7];
+ qcom,aux-cfg9-settings = [44 03];
+
+ qcom,max-pclk-frequency-khz = <675000>;
+
+ qcom,mst-enable;
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1152000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <21800>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <880000>;
+ qcom,supply-max-voltage = <880000>;
+ qcom,supply-enable-load = <36000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+
+ mdss_dsi_phy0: qcom,mdss_dsi_phy0 {
+ compatible = "qcom,dsi-phy-v4.1";
+ label = "dsi-phy-0";
+ cell-index = <0>;
+ reg = <0xae94400 0x800>,
+ <0xae94200 0x100>;
+ reg-names = "dsi_phy", "dyn_refresh_base";
+ vdda-0p9-supply = <&L5A>;
+ qcom,platform-strength-ctrl = [55 03
+ 55 03
+ 55 03
+ 55 03
+ 55 00];
+ qcom,platform-lane-config = [00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 8a 8a];
+ qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <880000>;
+ qcom,supply-max-voltage = <880000>;
+ qcom,supply-enable-load = <36000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi_phy1: qcom,mdss_dsi_phy1 {
+ compatible = "qcom,dsi-phy-v4.1";
+ label = "dsi-phy-1";
+ cell-index = <1>;
+ reg = <0xae96400 0x800>,
+ <0xae96200 0x100>;
+ reg-names = "dsi_phy", "dyn_refresh_base";
+ vdda-0p9-supply = <&L5A>;
+ qcom,platform-strength-ctrl = [55 03
+ 55 03
+ 55 03
+ 55 03
+ 55 00];
+ qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+ qcom,platform-lane-config = [00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 0a 0a
+ 00 00 8a 8a];
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <880000>;
+ qcom,supply-max-voltage = <880000>;
+ qcom,supply-enable-load = <36000>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-smp2p.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-smp2p.dtsi
new file mode 100755
index 0000000..9a7ba15
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-smp2p.dtsi
@@ -0,0 +1,145 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
+
+&soc {
+
+ qcom,smp2p-mpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ mpss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ mpss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ /* ipa - inbound entry from mss */
+ smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
+ qcom,entry-name = "wlan";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sleepstate_smp2p_out: sleepstate-out {
+ qcom,entry-name = "sleepstate";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ sleepstate_smp2p_in: qcom,sleepstate-in {
+ qcom,entry-name = "sleepstate_see";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
+ qcom,entry-name = "rdbg";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
+ qcom,entry-name = "rdbg";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
+ qcom,entry-name = "rdbg";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
+ qcom,entry-name = "rdbg";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p-npu {
+ compatible = "qcom,smp2p";
+ qcom,smem = <617>, <616>;
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&msm_npu IPCC_CLIENT_NPU IPCC_MPROC_SIGNAL_SMP2P>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <10>;
+
+ npu_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ npu_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-thermal-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-thermal-overlay.dtsi
new file mode 100755
index 0000000..299d4b6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-thermal-overlay.dtsi
@@ -0,0 +1,186 @@
+#include <dt-bindings/thermal/thermal.h>
+
+&mdss_mdp {
+ #cooling-cells = <2>;
+};
+
+&thermal_zones {
+ pm7250b-tz {
+ cooling-maps {
+ trip0_bat {
+ trip = <&pm7250b_trip0>;
+ cooling-device =
+ <&pm7250b_charger (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ trip1_bat {
+ trip = <&pm7250b_trip1>;
+ cooling-device =
+ <&pm7250b_charger THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+
+ pm8150_tz {
+ cooling-maps {
+ trip0_cpu0 {
+ trip = <&pm8150_trip0>;
+ cooling-device =
+ <&CPU0 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ trip0_cpu6 {
+ trip = <&pm8150_trip0>;
+ cooling-device =
+ <&CPU6 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ trip0_cpu7 {
+ trip = <&pm8150_trip0>;
+ cooling-device =
+ <&CPU7 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ trip1_cpu1 {
+ trip = <&pm8150_trip1>;
+ cooling-device = <&cpu1_isolate 1 1>;
+ };
+
+ trip1_cpu2 {
+ trip = <&pm8150_trip1>;
+ cooling-device = <&cpu2_isolate 1 1>;
+ };
+
+ trip1_cpu3 {
+ trip = <&pm8150_trip1>;
+ cooling-device = <&cpu3_isolate 1 1>;
+ };
+
+ trip1_cpu4 {
+ trip = <&pm8150_trip1>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+
+ trip1_cpu5 {
+ trip = <&pm8150_trip1>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+
+ trip1_cpu6 {
+ trip = <&pm8150_trip1>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ trip1_cpu7 {
+ trip = <&pm8150_trip1>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ soc {
+ cooling-maps {
+ soc_cpu6 {
+ trip = <&soc_trip>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ soc_cpu7 {
+ trip = <&soc_trip>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pm7250b-bcl-lvl0 {
+ cooling-maps {
+ lbat0_cpu6 {
+ trip = <&b_bcl_lvl0>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ lbat0_cpu7 {
+ trip = <&b_bcl_lvl0>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pm7250b-bcl-lvl1 {
+ cooling-maps {
+ lbat1_cpu6 {
+ trip = <&b_bcl_lvl1>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ lbat1_cpu7 {
+ trip = <&b_bcl_lvl1>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pm7250b-bcl-lvl2 {
+ cooling-maps {
+ lbat2_cpu6 {
+ trip = <&b_bcl_lvl2>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ lbat2_cpu7 {
+ trip = <&b_bcl_lvl2>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pm8150l-bcl-lvl0 {
+ disable-thermal-zone;
+ cooling-maps {
+ vph_cpu6 {
+ trip = <&l_bcl_lvl0>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ vph_cpu7 {
+ trip = <&l_bcl_lvl0>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pm8150l-bcl-lvl1 {
+ disable-thermal-zone;
+ cooling-maps {
+ vph_cpu6 {
+ trip = <&l_bcl_lvl1>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ vph_cpu7 {
+ trip = <&l_bcl_lvl1>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ pm8150l-bcl-lvl2 {
+ disable-thermal-zone;
+ cooling-maps {
+ vph_cpu6 {
+ trip = <&l_bcl_lvl2>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+
+ vph_cpu7 {
+ trip = <&l_bcl_lvl2>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-thermal.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-thermal.dtsi
new file mode 100755
index 0000000..51fc50c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-thermal.dtsi
@@ -0,0 +1,1287 @@
+#include <dt-bindings/thermal/thermal.h>
+#include "sdxprairie-thermal-integrated.dtsi"
+
+&cpufreq_hw {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,cpu-isolation {
+ compatible = "qcom,cpu-isolate";
+ cpu0_isolate: cpu0-isolate {
+ qcom,cpu = <&CPU0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1_isolate: cpu1-isolate {
+ qcom,cpu = <&CPU1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2_isolate: cpu2-isolate {
+ qcom,cpu = <&CPU2>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3_isolate: cpu3-isolate {
+ qcom,cpu = <&CPU3>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4_isolate: cpu4-isolate {
+ qcom,cpu = <&CPU4>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5_isolate: cpu5-isolate {
+ qcom,cpu = <&CPU5>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6_isolate: cpu6-isolate {
+ qcom,cpu = <&CPU6>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7_isolate: cpu7-isolate {
+ qcom,cpu = <&CPU7>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ lmh_dcvs0: qcom,limits-dcvs@18358800 {
+ compatible = "qcom,msm-hw-limits";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,affinity = <0>;
+ reg = <0x18358800 0x1000>,
+ <0x18323000 0x1000>;
+ qcom,no-cooling-device-register;
+ #thermal-sensor-cells = <0>;
+ };
+
+ lmh_dcvs1: qcom,limits-dcvs@18350800 {
+ compatible = "qcom,msm-hw-limits";
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,affinity = <1>;
+ reg = <0x18350800 0x1000>,
+ <0x18325800 0x1000>;
+ qcom,no-cooling-device-register;
+ #thermal-sensor-cells = <0>;
+ };
+
+ lmh_dcvs2: qcom,limits-dcvs@18327800 {
+ compatible = "qcom,msm-hw-limits";
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,affinity = <1>;
+ reg = <0x18350800 0x1000>,
+ <0x18327800 0x1000>;
+ qcom,no-cooling-device-register;
+ #thermal-sensor-cells = <0>;
+ };
+};
+
+&soc {
+ lmh_cpu_vdd0: qcom,lmh-cpu-vdd@18358800 {
+ compatible = "qcom,lmh-cpu-vdd";
+ reg = <0x18358800 0x1000>;
+ #cooling-cells = <2>;
+ };
+
+ lmh_cpu_vdd1: qcom,lmh-cpu-vdd@18350800 {
+ compatible = "qcom,lmh-cpu-vdd";
+ reg = <0x18350800 0x1000>;
+ #cooling-cells = <2>;
+ };
+
+ lmh_isense_cdsp {
+ compatible = "qcom,msm-limits-cdsp";
+ };
+};
+
+&thermal_zones {
+ aoss0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 0>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 1>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 3>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 4>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-4-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 5>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-5-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 6>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 7>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 8>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 9>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 10>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 11>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 12>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 13>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 14>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ min-temp-0-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 16>;
+ thermal-governor = "low_limits_floor";
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ min_temp_0_lowf: active-config0 {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ lpi_cx_vdd_cdev {
+ trip = <&min_temp_0_lowf>;
+ cooling-device = <&lpi_cx_cdev 0 0>;
+ };
+ };
+
+ };
+
+ min-temp-0-lowc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 16>;
+ thermal-governor = "low_limits_cap";
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ min_temp_0_lowc: active-config0 {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ lmh_cpu0_cdev {
+ trip = <&min_temp_0_lowc>;
+ cooling-device = <&lmh_cpu_vdd0 1 1>;
+ };
+
+ lmh_cpu6_cdev {
+ trip = <&min_temp_0_lowc>;
+ cooling-device = <&lmh_cpu_vdd1 1 1>;
+ };
+ };
+ };
+
+ aoss-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 0>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cwlan-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 1>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ video-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 2>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ ddr-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 3>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ q6-hvx-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 4>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cmpss-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 5>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ npu-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 6>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 7>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-vec-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 8>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-scl-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 9>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-core-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 10>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-core-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens1 11>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-config {
+ temperature = <115000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpuss-max-step {
+ polling-delay-passive = <10>;
+ polling-delay = <100>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ gpu_trip0: gpu-trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ gpu_cdev {
+ trip = <&gpu_trip0>;
+ cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu-0-max-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ silver-trip {
+ temperature = <120000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-max-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ gold-trip {
+ temperature = <120000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-0-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 1>;
+ wake-capable-sensor;
+ trips {
+ cpu00_config: cpu00-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu00_cdev {
+ trip = <&cpu00_config>;
+ cooling-device = <&cpu0_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 2>;
+ wake-capable-sensor;
+ trips {
+ cpu01_config: cpu01-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu01_cdev {
+ trip = <&cpu01_config>;
+ cooling-device = <&cpu1_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-2-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 3>;
+ wake-capable-sensor;
+ trips {
+ cpu02_config: cpu02-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu02_cdev {
+ trip = <&cpu02_config>;
+ cooling-device = <&cpu2_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-3-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 4>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu03_config: cpu03-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu03_cdev {
+ trip = <&cpu03_config>;
+ cooling-device = <&cpu3_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-4-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 5>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu04_config: cpu04-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu04_cdev {
+ trip = <&cpu04_config>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-5-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 6>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu05_config: cpu05-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu05_cdev {
+ trip = <&cpu05_config>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 9>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu10_config: cpu10-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu10_cdev {
+ trip = <&cpu10_config>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 10>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu11_config: cpu11-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu11_cdev {
+ trip = <&cpu11_config>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-2-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 11>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu12_config: cpu12-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu12_cdev {
+ trip = <&cpu12_config>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-3-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 12>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu13_config: cpu13-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu13_cdev {
+ trip = <&cpu13_config>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ q6-hvx-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 4>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ q6_hvx_trip1: q6-hvx-trip1 {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev1 {
+ trip = <&q6_hvx_trip1>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&q6_hvx_trip1>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&q6_hvx_trip1>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&q6_hvx_trip1>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&q6_hvx_trip1>;
+ cooling-device = <&msm_npu THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+
+ min-temp-1-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 16>;
+ thermal-governor = "low_limits_floor";
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ min_temp_1_lowf: active-config0 {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ lpi_cx_vdd_cdev {
+ trip = <&min_temp_1_lowf>;
+ cooling-device = <&lpi_cx_cdev 0 0>;
+ };
+ };
+ };
+
+ min-temp-1-lowc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 16>;
+ thermal-governor = "low_limits_cap";
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ min_temp_1_lowc: active-config0 {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ lmh_cpu0_cdev {
+ trip = <&min_temp_1_lowc>;
+ cooling-device = <&lmh_cpu_vdd0 1 1>;
+ };
+
+ lmh_cpu6_cdev {
+ trip = <&min_temp_1_lowc>;
+ cooling-device = <&lmh_cpu_vdd1 1 1>;
+ };
+ };
+ };
+
+ npu-step {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 6>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ npu_trip0: npu-trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ npu_cdev {
+ trip = <&npu_trip0>;
+ cooling-device =
+ <&msm_npu THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ mdm-vec-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 8>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ modem_vec_trip0: modem-vec-trip0 {
+ temperature = <95000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_vec_trip1: modem-vec-trip1 {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_vec_trip2: modem-vec-trip2 {
+ temperature = <115000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ modem_tj1_cdev {
+ trip = <&modem_vec_trip0>;
+ cooling-device = <&modem_tj 1 1>;
+ };
+
+ modem_tj2_cdev {
+ trip = <&modem_vec_trip1>;
+ cooling-device = <&modem_tj 2 2>;
+ };
+
+ modem_tj3_cdev {
+ trip = <&modem_vec_trip2>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+ };
+ };
+
+ mdm-scl-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 9>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ modem_scl_trip0: modem-scl-trip0 {
+ temperature = <95000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_scl_trip1: modem-scl-trip1 {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_scl_trip2: modem-scl-trip2 {
+ temperature = <115000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ modem_tj1_cdev {
+ trip = <&modem_scl_trip0>;
+ cooling-device = <&modem_tj 1 1>;
+ };
+
+ modem_tj2_cdev {
+ trip = <&modem_scl_trip1>;
+ cooling-device = <&modem_tj 2 2>;
+ };
+
+ modem_tj3_cdev {
+ trip = <&modem_scl_trip2>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+ };
+ };
+
+ mdm-core-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 10>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ modem_core_0_trip0: modem-core-0-trip0 {
+ temperature = <95000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_core_0_trip1: modem-core-0-trip1 {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_core_0_trip2: modem-core-0-trip2 {
+ temperature = <115000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ modem_tj1_cdev {
+ trip = <&modem_core_0_trip0>;
+ cooling-device = <&modem_tj 1 1>;
+ };
+
+ modem_tj2_cdev {
+ trip = <&modem_core_0_trip1>;
+ cooling-device = <&modem_tj 2 2>;
+ };
+
+ modem_tj3_cdev {
+ trip = <&modem_core_0_trip2>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+ };
+ };
+
+ mdm-core-1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 11>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ modem_core_1_trip0: modem-core-1-trip0 {
+ temperature = <95000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_core_1_trip1: modem-core-1-trip1 {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+
+ modem_core_1_trip2: modem-core-1-trip2 {
+ temperature = <115000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ modem_tj1_cdev {
+ trip = <&modem_core_1_trip0>;
+ cooling-device = <&modem_tj 1 1>;
+ };
+
+ modem_tj2_cdev {
+ trip = <&modem_core_1_trip1>;
+ cooling-device = <&modem_tj 2 2>;
+ };
+
+ modem_tj3_cdev {
+ trip = <&modem_core_1_trip2>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+ };
+ };
+
+ /delete-node/ modem-mmw-pa1-usr;
+ /delete-node/ modem-mmw-pa2-usr;
+ /delete-node/ modem-mmw-pa3-usr;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-usb.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-usb.dtsi
new file mode 100755
index 0000000..b86ef83
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-usb.dtsi
@@ -0,0 +1,326 @@
+#include <dt-bindings/clock/qcom,gcc-lito.h>
+#include <dt-bindings/phy/qcom,lito-qmp-usb3.h>
+
+&soc {
+ /* Primary USB port related controller */
+ usb0: ssusb@a600000 {
+ compatible = "qcom,dwc-usb3-msm";
+ reg = <0x0a600000 0x100000>;
+ reg-names = "core_base";
+
+ iommus = <&apps_smmu 0xE0 0x0>;
+ qcom,iommu-dma = "atomic";
+ qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
+ <&intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 15 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+ "ss_phy_irq", "dm_hs_phy_irq";
+ qcom,use-pdc-interrupts;
+
+ USB3_GDSC-supply = <&usb30_prim_gdsc>;
+ qcom,gdsc-collapse-in-host-suspend;
+ dpdm-supply = <&usb2_phy0>;
+ clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
+ clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+ "utmi_clk", "sleep_clk", "xo";
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+ reset-names = "core_reset";
+
+ qcom,core-clk-rate = <133333333>;
+ qcom,core-clk-rate-hs = <66666667>;
+ qcom,num-gsi-evt-buffs = <0x3>;
+ qcom,gsi-reg-offset =
+ <0x0fc /* GSI_GENERAL_CFG */
+ 0x110 /* GSI_DBL_ADDR_L */
+ 0x120 /* GSI_DBL_ADDR_H */
+ 0x130 /* GSI_RING_BASE_ADDR_L */
+ 0x144 /* GSI_RING_BASE_ADDR_H */
+ 0x1a4>; /* GSI_IF_STS */
+ qcom,gsi-disable-io-coherency;
+ qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
+ qcom,pm-qos-latency = <61>; /* CPU0-WFI-LVL latency +1 */
+
+ qcom,msm-bus,name = "usb0";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ /* suspend vote */
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>,
+
+ /* nominal vote */
+ <MSM_BUS_MASTER_USB3
+ MSM_BUS_SLAVE_EBI_CH0 1000000 2500000>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+ /* svs vote */
+ <MSM_BUS_MASTER_USB3
+ MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+ /* min vote */
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 1 1>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 1 1>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 1 1>;
+
+ dwc3@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0x0a600000 0xcd00>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;
+ linux,sysdev_is_parent;
+ snps,disable-clk-gating;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3-u1u2-disable;
+ usb-core-id = <0>;
+ tx-fifo-resize;
+ maximum-speed = "super-speed";
+ dr_mode = "drd";
+ };
+ };
+
+ /* Primary USB port related High Speed PHY */
+ usb2_phy0: hsphy@88e3000 {
+ compatible = "qcom,usb-hsphy-snps-femto";
+ reg = <0x88e3000 0x110>,
+ <0x088e2000 0x4>;
+ reg-names = "hsusb_phy_base",
+ "eud_enable_reg";
+
+ vdd-supply = <&pm8150_l5>;
+ vdda18-supply = <&pm8150_l12>;
+ vdda33-supply = <&pm8150_l2>;
+ qcom,vdd-voltage-level = <0 880000 880000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref_clk_src";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ reset-names = "phy_reset";
+ qcom,param-override-seq = <0x63 0x6c>,
+ <0x85 0x70>,
+ <0x17 0x74>;
+ };
+
+ /* Primary USB port related QMP USB DP Combo PHY */
+ usb_qmp_dp_phy: ssphy@88e8000 {
+ compatible = "qcom,usb-ssphy-qmp-dp-combo";
+ reg = <0x88e8000 0x3000>;
+ reg-names = "qmp_phy_base";
+
+ core-supply = <&pm8150_l9>;
+ qcom,vdd-voltage-level = <0 880000 880000>;
+ qcom,vdd-max-load-uA = <47000>;
+ qcom,vbus-valid-override;
+ qcom,qmp-phy-init-seq =
+ /* <reg_offset, value, delay> */
+ <USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
+ USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
+ USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
+ USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
+ USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
+ USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
+ USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
+ USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
+ USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0
+ USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
+ USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0
+ USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
+ USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
+ USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
+ USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
+ USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
+ USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
+ USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
+ USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
+ USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
+ USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
+ USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
+ USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
+ USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
+ USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0
+ USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
+ USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
+ USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
+ USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0
+ USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
+ USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
+ USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0
+ USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0
+ USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0
+ USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x05 0
+ USB3_DP_QSERDES_TXA_LANE_MODE_1 0x55 0
+ USB3_DP_QSERDES_TXA_LANE_MODE_2 0x02 0
+ USB3_DP_QSERDES_TXA_LANE_MODE_4 0x2A 0
+ USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F 0
+ USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
+ USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x20 0
+ USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05 0
+ USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
+ USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
+ USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
+ USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
+ USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
+ USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x04 0
+ USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
+ USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x05 0
+ USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x05 0
+ USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
+ USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x08 0
+ USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
+ USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
+ USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
+ USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
+ USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
+ USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
+ USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
+ USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBF 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0xBF 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x3F 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F 0
+ USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x94 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x5B 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x1B 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13 0
+ USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9 0
+ USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
+ USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x00 0
+ USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
+ USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
+ USB3_DP_QSERDES_RXA_GM_CAL 0x00 0
+ USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
+ USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0
+ USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0
+ USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0
+ USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x05 0
+ USB3_DP_QSERDES_TXB_LANE_MODE_1 0x55 0
+ USB3_DP_QSERDES_TXB_LANE_MODE_2 0x02 0
+ USB3_DP_QSERDES_TXB_LANE_MODE_4 0x2A 0
+ USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0
+ USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
+ USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x02 0
+ USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05 0
+ USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
+ USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
+ USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
+ USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
+ USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
+ USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x04 0
+ USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
+ USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x05 0
+ USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x05 0
+ USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
+ USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x08 0
+ USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
+ USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
+ USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
+ USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
+ USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
+ USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0
+ USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
+ USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBF 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xBF 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F 0
+ USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0x94 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x5B 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x1B 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13 0
+ USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9 0
+ USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
+ USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x00 0
+ USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
+ USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
+ USB3_DP_QSERDES_RXB_GM_CAL 0x00 0
+ USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
+ USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
+ USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
+ USB3_DP_PCS_RX_SIGDET_LVL 0xAA 0
+ USB3_DP_PCS_CDR_RESET_TIME 0x0F 0
+ USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
+ USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
+ USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
+ USB3_DP_PCS_EQ_CONFIG1 0x4B 0
+ USB3_DP_PCS_EQ_CONFIG5 0x10 0
+ USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
+ USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
+ 0xffffffff 0xffffffff 0x00>;
+
+ qcom,qmp-phy-reg-offset =
+ <USB3_DP_PCS_PCS_STATUS1
+ USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
+ USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
+ USB3_DP_PCS_POWER_DOWN_CONTROL
+ USB3_DP_PCS_SW_RESET
+ USB3_DP_PCS_START_CONTROL
+ 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
+ 0x2a18 /* USB3_DP_DP_PHY_PD_CTL */
+ USB3_DP_COM_POWER_DOWN_CTRL
+ USB3_DP_COM_SW_RESET
+ USB3_DP_COM_RESET_OVRD_CTRL
+ USB3_DP_COM_PHY_MODE_CTRL
+ USB3_DP_COM_TYPEC_CTRL
+ USB3_DP_COM_SWI_CTRL
+ USB3_DP_PCS_CLAMP_ENABLE
+ USB3_DP_PCS_PCS_STATUS2
+ USB3_DP_PCS_INSIG_SW_CTRL3
+ USB3_DP_PCS_INSIG_MX_CTRL3>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
+ "com_aux_clk";
+
+ resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_PHY_PRIM_BCR>;
+ reset-names = "global_phy_reset", "phy_reset";
+
+ status = "ok";
+ };
+
+ usb_audio_qmi_dev {
+ compatible = "qcom,usb-audio-qmi-dev";
+ iommus = <&apps_smmu 0x140f 0x0>;
+ qcom,iommu-dma = "disabled";
+ qcom,usb-audio-stream-id = <0xf>;
+ qcom,usb-audio-intr-num = <2>;
+ };
+
+ usb_nop_phy: usb_nop_phy {
+ compatible = "usb-nop-xceiv";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-v2-atp-lcd-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lito-v2-atp-lcd-overlay.dts
new file mode 100755
index 0000000..54567e9
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-v2-atp-lcd-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lito-atp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito v2 LCD ATP";
+ compatible = "qcom,lito-atp", "qcom,lito", "qcom,atp";
+ qcom,msm-id = <440 0x20000>;
+ qcom,board-id = <33 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-v2-atp-lcd.dts b/arch/arm64/boot/dts/vendor/qcom/lito-v2-atp-lcd.dts
new file mode 100755
index 0000000..10eabb7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-v2-atp-lcd.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+#include "lito-v2.dtsi"
+#include "lito-atp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito v2 LCD ATP";
+ compatible = "qcom,lito-atp", "qcom,lito", "qcom,atp";
+ qcom,board-id = <33 1>;
+};
+
+&ufsphy_mem {
+ /delete-property/ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-v2-atp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lito-v2-atp-overlay.dts
new file mode 100755
index 0000000..28a3845
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-v2-atp-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lito-atp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito v2 ATP";
+ compatible = "qcom,lito-atp", "qcom,lito", "qcom,atp";
+ qcom,msm-id = <400 0x20000>, <440 0x20000>;
+ qcom,board-id = <33 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-v2-atp.dts b/arch/arm64/boot/dts/vendor/qcom/lito-v2-atp.dts
new file mode 100755
index 0000000..56fdad3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-v2-atp.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+#include "lito-v2.dtsi"
+#include "lito-atp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito v2 ATP";
+ compatible = "qcom,lito-atp", "qcom,lito", "qcom,atp";
+ qcom,board-id = <33 0>;
+};
+
+&ufsphy_mem {
+ /delete-property/ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-v2-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-v2-audio.dtsi
new file mode 100755
index 0000000..ee0dbd5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-v2-audio.dtsi
@@ -0,0 +1,11 @@
+
+&lpi_tlmm {
+ qcom,lpi-slew-base-tbl = <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x0355C000>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-v2-cdp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lito-v2-cdp-overlay.dts
new file mode 100755
index 0000000..33c9f88
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-v2-cdp-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lito-cdp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito v2 CDP";
+ compatible = "qcom,lito-cdp", "qcom,lito", "qcom,cdp";
+ qcom,msm-id = <400 0x20000>, <440 0x20000>;
+ qcom,board-id = <1 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-v2-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/lito-v2-cdp.dts
new file mode 100755
index 0000000..09c92fd
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-v2-cdp.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+#include "lito-v2.dtsi"
+#include "lito-cdp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito v2 CDP";
+ compatible = "qcom,lito-cdp", "qcom,lito", "qcom,cdp";
+ qcom,board-id = <1 0>;
+};
+
+&ufsphy_mem {
+ /delete-property/ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-v2-mtp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lito-v2-mtp-overlay.dts
new file mode 100755
index 0000000..d60d066
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-v2-mtp-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "lito-mtp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito v2 MTP";
+ compatible = "qcom,lito-mtp", "qcom,lito", "qcom,mtp";
+ qcom,msm-id = <400 0x20000>, <440 0x20000>;
+ qcom,board-id = <8 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-v2-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/lito-v2-mtp.dts
new file mode 100755
index 0000000..888adca
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-v2-mtp.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+#include "lito-v2.dtsi"
+#include "lito-mtp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito v2 MTP";
+ compatible = "qcom,lito-mtp", "qcom,lito", "qcom,mtp";
+ qcom,board-id = <8 0>;
+};
+
+&ufsphy_mem {
+ /delete-property/ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-v2-qrd-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/lito-v2-qrd-overlay.dts
new file mode 100755
index 0000000..a9cbb2b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-v2-qrd-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include "lito-qrd.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito v2 QRD";
+ compatible = "qcom,lito-qrd", "qcom,lito", "qcom,qrd";
+ qcom,msm-id = <400 0x20000>, <440 0x20000>;
+ qcom,board-id = <11 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-v2-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/lito-v2-qrd.dts
new file mode 100755
index 0000000..281ad0f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-v2-qrd.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+#include "lito-v2.dtsi"
+#include "lito-qrd.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito v2 QRD";
+ compatible = "qcom,lito-qrd", "qcom,lito", "qcom,qrd";
+ qcom,board-id = <11 0>;
+};
+
+&ufsphy_mem {
+ /delete-property/ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-v2.dts b/arch/arm64/boot/dts/vendor/qcom/lito-v2.dts
new file mode 100755
index 0000000..a3da016
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-v2.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "lito-v2.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito v2 SoC";
+ compatible = "qcom,lito";
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-v2.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-v2.dtsi
new file mode 100755
index 0000000..b6045c7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-v2.dtsi
@@ -0,0 +1,630 @@
+#include "lito.dtsi"
+#include "camera/lito-v2-camera.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito v2";
+ compatible = "qcom,lito";
+ qcom,msm-id = <400 0x20000>, <440 0x20000>;
+};
+
+&lito_snd {
+ qcom,lito-is-v2-enabled = <1>;
+};
+
+&camcc {
+ compatible = "qcom,lito-camcc-v2", "syscon";
+};
+
+&npucc {
+ compatible = "qcom,lito-npucc-v2", "syscon";
+};
+
+&pm8008_regulators {
+ vdd_l7-supply = <&BOB>;
+};
+
+&msm_gpu {
+ /delete-property/qcom,chipid;
+ qcom,chipid = <0x06020001>;
+
+ /delete-node/qcom,gpu-pwrlevel-bins;
+ qcom,gpu-pwrlevel-bins {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible="qcom,gpu-pwrlevel-bins";
+
+ qcom,gpu-pwrlevels-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <0>;
+ qcom,ca-target-pwrlevel = <4>;
+ qcom,initial-pwrlevel = <5>;
+ qcom,throttle-pwrlevel = <0>;
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <750000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <12>;
+ qcom,acd-level = <0xA02C5FFD>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <670000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <12>;
+ qcom,acd-level = <0xA02C5FFD>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <625000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <12>;
+ qcom,acd-level = <0x802D5FFD>;
+ };
+
+ /* SVS L1 */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <500000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <10>;
+ qcom,acd-level = <0xA02D5FFD>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ qcom,acd-level = <0x802E5FFD>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <275000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ qcom,acd-level = <0x802F5FFD>;
+ };
+
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <132>;
+
+ qcom,initial-pwrlevel = <3>;
+ qcom,ca-target-pwrlevel = <2>;
+
+ /* NOM */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <625000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <12>;
+ qcom,acd-level = <0x802D5FFD>;
+ };
+
+ /* SVS L1 */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <500000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <10>;
+ qcom,acd-level = <0xA02D5FFD>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ qcom,acd-level = <0x802E5FFD>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <275000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ qcom,acd-level = <0x802F5FFD>;
+ };
+
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <115>;
+ qcom,initial-pwrlevel = <2>;
+ qcom,ca-target-pwrlevel = <1>;
+
+ /* SVS L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <540000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <12>;
+ qcom,acd-level = <0x802D5FFD>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ qcom,acd-level = <0x802E5FFD>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <275000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ qcom,acd-level = <0x802F5FFD>;
+ };
+
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <158>;
+ qcom,ca-target-pwrlevel = <4>;
+ qcom,initial-pwrlevel = <5>;
+ qcom,throttle-pwrlevel = <0>;
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <750000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <12>;
+ qcom,acd-level = <0xA02C5FFD>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <670000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <12>;
+ qcom,acd-level = <0xA02C5FFD>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <625000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <12>;
+ qcom,acd-level = <0x802D5FFD>;
+ };
+
+ /* SVS L1 */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <500000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <10>;
+ qcom,acd-level = <0xA02D5FFD>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ qcom,acd-level = <0x802E5FFD>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <275000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ qcom,acd-level = <0x802F5FFD>;
+ };
+
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <165>;
+
+ qcom,initial-pwrlevel = <3>;
+ qcom,ca-target-pwrlevel = <2>;
+
+ /* NOM */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <625000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <12>;
+ qcom,acd-level = <0x802D5FFD>;
+ };
+
+ /* SVS L1 */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <500000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <10>;
+ qcom,acd-level = <0xA02D5FFD>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ qcom,acd-level = <0x802E5FFD>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <275000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ qcom,acd-level = <0x802F5FFD>;
+ };
+
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+ };
+};
+
+&cpu0_cpu_l3_latmon {
+ qcom,core-dev-table =
+ < 614400 300000000 >,
+ < 864000 556800000 >,
+ < 1075200 787200000 >,
+ < 1363200 940800000 >,
+ < 1804800 1516800000 >;
+};
+
+&cpu0_cpu_llcc_latmon {
+ qcom,core-dev-table =
+ < 1075200 MHZ_TO_MBPS(300, 16) >,
+ < 1363200 MHZ_TO_MBPS(466, 16) >,
+ < 1804800 MHZ_TO_MBPS(600, 16) >;
+};
+
+&cpu0_llcc_ddr_latmon {
+ qcom,core-dev-table =
+ < 614400 MHZ_TO_MBPS( 300, 4) >,
+ < 864000 MHZ_TO_MBPS( 451, 4) >,
+ < 1075200 MHZ_TO_MBPS( 547, 4) >,
+ < 1363200 MHZ_TO_MBPS( 768, 4) >,
+ < 1804800 MHZ_TO_MBPS(1017, 4) >;
+};
+
+&cpu0_computemon {
+ qcom,core-dev-table =
+ < 614400 MHZ_TO_MBPS( 300, 4) >,
+ < 1075200 MHZ_TO_MBPS( 451, 4) >,
+ < 1363200 MHZ_TO_MBPS( 547, 4) >,
+ < 1804800 MHZ_TO_MBPS( 768, 4) >;
+};
+
+&cpu6_cpu_l3_latmon {
+ qcom,core-dev-table =
+ < 940800 556800000 >,
+ < 1152000 787200000 >,
+ < 1728000 1209600000 >,
+ < 1900800 1382400000 >,
+ < 2342400 1516800000 >;
+};
+
+&cpu7_cpu_l3_latmon {
+ qcom,core-dev-table =
+ < 1094400 556800000 >,
+ < 1401600 787200000 >,
+ < 1996800 1209600000 >,
+ < 2188800 1324800000 >,
+ < 2707200 1516800000 >;
+};
+
+&cpu6_cpu_llcc_latmon {
+ qcom,core-dev-table =
+ < 652800 MHZ_TO_MBPS( 300, 16) >,
+ < 940800 MHZ_TO_MBPS( 466, 16) >,
+ < 1152000 MHZ_TO_MBPS( 600, 16) >,
+ < 1728000 MHZ_TO_MBPS( 806, 16) >,
+ < 2342400 MHZ_TO_MBPS( 933, 16) >,
+ < 3000000 MHZ_TO_MBPS(1066, 16) >;
+};
+
+&cpu6_llcc_ddr_latmon {
+ qcom,core-dev-table =
+ < 652800 MHZ_TO_MBPS( 451, 4) >,
+ < 940800 MHZ_TO_MBPS( 547, 4) >,
+ < 1152000 MHZ_TO_MBPS(1017, 4) >,
+ < 1728000 MHZ_TO_MBPS(1555, 4) >,
+ < 2342400 MHZ_TO_MBPS(1804, 4) >,
+ < 3000000 MHZ_TO_MBPS(2092, 4) >;
+};
+
+&cpu6_computemon {
+ qcom,core-dev-table =
+ < 652800 MHZ_TO_MBPS( 300, 4) >,
+ < 1152000 MHZ_TO_MBPS( 547, 4) >,
+ < 1478400 MHZ_TO_MBPS( 768, 4) >,
+ < 1728000 MHZ_TO_MBPS(1017, 4) >,
+ < 2342400 MHZ_TO_MBPS(1804, 4) >,
+ < 3000000 MHZ_TO_MBPS(2092, 4) >;
+};
+
+&cpu7_computemon {
+ qcom,core-dev-table =
+ < 806400 MHZ_TO_MBPS( 300, 4) >,
+ < 1401600 MHZ_TO_MBPS( 547, 4) >,
+ < 1766400 MHZ_TO_MBPS( 768, 4) >,
+ < 1996800 MHZ_TO_MBPS(1017, 4) >,
+ < 2707200 MHZ_TO_MBPS(1804, 4) >,
+ < 3000000 MHZ_TO_MBPS(2092, 4) >;
+};
+
+/* NPU overrides */
+&msm_npu {
+ qcom,npu-pwrlevels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,npu-pwrlevels";
+ initial-pwrlevel = <5>;
+ qcom,npu-pwrlevel@0 {
+ reg = <0>;
+ vreg = <1>;
+ clk-freq = <19200000
+ 100000000
+ 230000000
+ 230000000
+ 150000000
+ 40000000
+ 300000000
+ 100000000
+ 19200000
+ 50000000
+ 50000000
+ 100000000
+ 100000000
+ 100000000
+ 19200000
+ 100000000
+ 19200000
+ 50000000
+ 230000000
+ 50000000
+ 19200000
+ 230000000
+ 19200000
+ 300000000>;
+ };
+
+ qcom,npu-pwrlevel@1 {
+ reg = <1>;
+ vreg = <2>;
+ clk-freq = <19200000
+ 200000000
+ 422000000
+ 422000000
+ 207000000
+ 40000000
+ 403000000
+ 200000000
+ 19200000
+ 50000000
+ 50000000
+ 200000000
+ 200000000
+ 200000000
+ 19200000
+ 200000000
+ 19200000
+ 50000000
+ 422000000
+ 50000000
+ 19200000
+ 422000000
+ 19200000
+ 400000000>;
+ };
+
+ qcom,npu-pwrlevel@2 {
+ reg = <2>;
+ vreg = <3>;
+ clk-freq = <19200000
+ 333000000
+ 557000000
+ 557000000
+ 300000000
+ 75000000
+ 533000000
+ 214000000
+ 19200000
+ 50000000
+ 100000000
+ 214000000
+ 214000000
+ 214000000
+ 19200000
+ 214000000
+ 19200000
+ 50000000
+ 557000000
+ 50000000
+ 19200000
+ 557000000
+ 19200000
+ 500000000>;
+ };
+
+ qcom,npu-pwrlevel@3 {
+ reg = <3>;
+ vreg = <4>;
+ clk-freq = <19200000
+ 400000000
+ 729000000
+ 729000000
+ 403000000
+ 75000000
+ 700000000
+ 285714286
+ 19200000
+ 100000000
+ 200000000
+ 285714286
+ 285714286
+ 285714286
+ 19200000
+ 285714286
+ 19200000
+ 100000000
+ 729000000
+ 100000000
+ 19200000
+ 729000000
+ 19200000
+ 660000000>;
+ };
+
+ qcom,npu-pwrlevel@4 {
+ reg = <4>;
+ vreg = <6>;
+ clk-freq = <19200000
+ 500000000
+ 844000000
+ 844000000
+ 533000000
+ 75000000
+ 806000000
+ 285714286
+ 19200000
+ 100000000
+ 200000000
+ 285714286
+ 285714286
+ 285714286
+ 19200000
+ 285714286
+ 19200000
+ 100000000
+ 844000000
+ 100000000
+ 19200000
+ 844000000
+ 19200000
+ 800000000>;
+ };
+
+ qcom,npu-pwrlevel@5 {
+ reg = <5>;
+ vreg = <7>;
+ clk-freq = <19200000
+ 500000000
+ 1000000000
+ 1000000000
+ 533000000
+ 75000000
+ 806000000
+ 285714286
+ 19200000
+ 100000000
+ 200000000
+ 285714286
+ 285714286
+ 285714286
+ 19200000
+ 285714286
+ 19200000
+ 100000000
+ 1000000000
+ 100000000
+ 19200000
+ 1000000000
+ 19200000
+ 800000000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito-vidc.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito-vidc.dtsi
new file mode 100755
index 0000000..40007b8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito-vidc.dtsi
@@ -0,0 +1,233 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/clock/qcom,videocc-lito.h>
+
+&soc {
+ msm_vidc0: qcom,vidc0 {
+ compatible = "qcom,msm-vidc", "qcom,lito-vidc";
+ status = "ok";
+ sku-index = <0>;
+ reg = <0xaa00000 0x200000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ /* Supply */
+ iris-ctl-supply = <&mvsc_gdsc>;
+ vcodec-supply = <&mvs0_gdsc>;
+ cvp-supply = <&mvs1_gdsc>;
+
+ /* Clocks */
+ clock-names = "video_cc_mvsc_ctl_axi", "video_cc_mvs0_ctl_axi",
+ "video_cc_mvs1_ctl_axi", "core_clk", "vcodec_clk",
+ "cvp_clk", "iface_clk";
+ clocks = <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
+ <&videocc VIDEO_CC_MVS0_AXI_CLK>,
+ <&videocc VIDEO_CC_MVS1_AXI_CLK>,
+ <&videocc VIDEO_CC_MVSC_CORE_CLK>,
+ <&videocc VIDEO_CC_MVS0_CORE_CLK>,
+ <&videocc VIDEO_CC_MVS1_CORE_CLK>,
+ <&videocc VIDEO_CC_VENUS_AHB_CLK>;
+
+ qcom,proxy-clock-names = "video_cc_mvsc_ctl_axi",
+ "video_cc_mvs0_ctl_axi", "video_cc_mvs1_ctl_axi",
+ "core_clk", "vcodec_clk", "cvp_clk", "iface_clk";
+
+ qcom,clock-configs = <0x0 0x0 0x0 0x1 0x1 0x1 0x0>;
+ qcom,allowed-clock-rates = <240000000 338000000 365000000>;
+
+ /* Buses */
+ bus_cnoc {
+ compatible = "qcom,msm-vidc,bus";
+ label = "cnoc";
+ qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <1000 1000>;
+ };
+
+ venus_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "venus-ddr";
+ qcom,bus-range-kbps = <1000 6533000>;
+ };
+
+ arm9_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-arm9-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <1000 1000>;
+ };
+
+ /* MMUs */
+ non_secure_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_ns";
+ iommus = <&apps_smmu 0x1380 0x60>,
+ <&apps_smmu 0x1360 0x0>;
+ qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
+ qcom,iommu-faults = "non-fatal";
+ buffer-types = <0xfff>;
+ virtual-addr-pool = <0x25800000 0xba800000>;
+ };
+
+ secure_non_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_non_pixel";
+ iommus = <&apps_smmu 0x1304 0xe0>;
+ qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
+ buffer-types = <0x480>;
+ virtual-addr-pool = <0x1000000 0x24800000>;
+ qcom,secure-context-bank;
+ };
+
+ secure_bitstream_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_bitstream";
+ iommus = <&apps_smmu 0x1361 0x4>;
+ qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
+ buffer-types = <0x241>;
+ virtual-addr-pool = <0x500000 0xdfb00000>;
+ qcom,secure-context-bank;
+ };
+
+ secure_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_pixel";
+ iommus = <&apps_smmu 0x1303 0xe0>;
+ qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
+ buffer-types = <0x106>;
+ virtual-addr-pool = <0x500000 0xdfb00000>;
+ qcom,secure-context-bank;
+ };
+
+ /* Memory Heaps */
+ qcom,msm-vidc,mem_cdsp {
+ compatible = "qcom,msm-vidc,mem-cdsp";
+ memory-region = <&cdsp_mem>;
+ };
+ };
+
+ msm_vidc1: qcom,vidc1 {
+ compatible = "qcom,msm-vidc", "qcom,lito-vidc";
+ status = "ok";
+ sku-index = <1>;
+ reg = <0xaa00000 0x200000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ /* Supply */
+ iris-ctl-supply = <&mvsc_gdsc>;
+ vcodec-supply = <&mvs0_gdsc>;
+ cvp-supply = <&mvs1_gdsc>;
+
+ /* Clocks */
+ clock-names = "video_cc_mvsc_ctl_axi", "video_cc_mvs0_ctl_axi",
+ "video_cc_mvs1_ctl_axi", "core_clk", "vcodec_clk",
+ "cvp_clk", "iface_clk";
+ clocks = <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
+ <&videocc VIDEO_CC_MVS0_AXI_CLK>,
+ <&videocc VIDEO_CC_MVS1_AXI_CLK>,
+ <&videocc VIDEO_CC_MVSC_CORE_CLK>,
+ <&videocc VIDEO_CC_MVS0_CORE_CLK>,
+ <&videocc VIDEO_CC_MVS1_CORE_CLK>,
+ <&videocc VIDEO_CC_VENUS_AHB_CLK>;
+
+ qcom,proxy-clock-names = "video_cc_mvsc_ctl_axi",
+ "video_cc_mvs0_ctl_axi", "video_cc_mvs1_ctl_axi",
+ "core_clk", "vcodec_clk", "cvp_clk", "iface_clk";
+
+ qcom,clock-configs = <0x0 0x0 0x0 0x1 0x1 0x1 0x0>;
+ qcom,allowed-clock-rates = <200000000>;
+
+ /* Buses */
+ bus_cnoc {
+ compatible = "qcom,msm-vidc,bus";
+ label = "cnoc";
+ qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <1000 1000>;
+ };
+
+ venus_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "venus-ddr";
+ qcom,bus-range-kbps = <1000 6533000>;
+ };
+
+ arm9_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-arm9-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <1000 1000>;
+ };
+
+ /* MMUs */
+ non_secure_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_ns";
+ iommus = <&apps_smmu 0x1380 0x60>,
+ <&apps_smmu 0x1360 0x0>;
+ qcom,iommu-dma-addr-pool = <0x25800000 0xba800000>;
+ qcom,iommu-faults = "non-fatal";
+ buffer-types = <0xfff>;
+ virtual-addr-pool = <0x25800000 0xba800000>;
+ };
+
+ secure_non_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_non_pixel";
+ iommus = <&apps_smmu 0x1304 0xe0>;
+ qcom,iommu-dma-addr-pool = <0x01000000 0x24800000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
+ buffer-types = <0x480>;
+ virtual-addr-pool = <0x1000000 0x24800000>;
+ qcom,secure-context-bank;
+ };
+
+ secure_bitstream_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_bitstream";
+ iommus = <&apps_smmu 0x1361 0x4>;
+ qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
+ buffer-types = <0x241>;
+ virtual-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,secure-context-bank;
+ };
+
+ secure_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_pixel";
+ iommus = <&apps_smmu 0x1303 0xe0>;
+ qcom,iommu-dma-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
+ buffer-types = <0x106>;
+ virtual-addr-pool = <0x00500000 0xdfb00000>;
+ qcom,secure-context-bank;
+ };
+
+ /* Memory Heaps */
+ qcom,msm-vidc,mem_cdsp {
+ compatible = "qcom,msm-vidc,mem-cdsp";
+ memory-region = <&cdsp_mem>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito.dts b/arch/arm64/boot/dts/vendor/qcom/lito.dts
new file mode 100755
index 0000000..24ed52b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "lito.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito SoC";
+ compatible = "qcom,lito";
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/lito.dtsi b/arch/arm64/boot/dts/vendor/qcom/lito.dtsi
new file mode 100755
index 0000000..452e680
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/lito.dtsi
@@ -0,0 +1,3952 @@
+#include <dt-bindings/clock/qcom,aop-qmp.h>
+#include <dt-bindings/clock/qcom,camcc-lito.h>
+#include <dt-bindings/clock/qcom,dispcc-lito.h>
+#include <dt-bindings/clock/qcom,gcc-lito.h>
+#include <dt-bindings/clock/qcom,gpucc-lito.h>
+#include <dt-bindings/clock/qcom,npucc-lito.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,videocc-lito.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/soc/qcom,dcc_v2.h>
+#include <dt-bindings/soc/qcom,ipcc.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/spmi/spmi.h>
+
+#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
+#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
+
+/ {
+ model = "Qualcomm Technologies, Inc. Lito";
+ compatible = "qcom,lito";
+ qcom,msm-id = <400 0x10000>, <440 0x10000>;
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+ mem-offline {
+ compatible = "qcom,mem-offline";
+ offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
+ <0x1 0xc0000000 0x0 0x80000000>,
+ <0x2 0xc0000000 0x1 0x40000000>;
+ granule = <512>;
+ mboxes = <&qmp_aop 0>;
+ };
+
+ aliases {
+ serial0 = &qupv3_se2_2uart; /*RUMI*/
+ ufshc1 = &ufshc_mem; /* Embedded UFS slot */
+ swr0 = &swr0;
+ swr1 = &swr1;
+ swr2 = &swr2;
+ sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
+ sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ qcom,freq-domain = <&cpufreq_hw 0 6>;
+ next-level-cache = <&L2_0>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ #cooling-cells = <2>;
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+
+ L3_0: l3-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <3>;
+ };
+ };
+
+ L1_I_0: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_0: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ qcom,freq-domain = <&cpufreq_hw 0 6>;
+ next-level-cache = <&L2_100>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ L2_100: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_100: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_100: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ qcom,freq-domain = <&cpufreq_hw 0 6>;
+ next-level-cache = <&L2_200>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ L2_200: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_200: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_200: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ qcom,freq-domain = <&cpufreq_hw 0 6>;
+ next-level-cache = <&L2_300>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ L2_300: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_300: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_300: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ qcom,freq-domain = <&cpufreq_hw 0 6>;
+ next-level-cache = <&L2_400>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ L2_400: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_400: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_400: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ qcom,freq-domain = <&cpufreq_hw 0 6>;
+ next-level-cache = <&L2_500>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ L2_500: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_500: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_500: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1740>;
+ dynamic-power-coefficient = <341>;
+ qcom,freq-domain = <&cpufreq_hw 1 2>;
+ next-level-cache = <&L2_600>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+ #cooling-cells = <2>;
+ L2_600: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_600: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_600: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1740>;
+ dynamic-power-coefficient = <375>;
+ qcom,freq-domain = <&cpufreq_hw 2 2>;
+ next-level-cache = <&L2_700>;
+ qcom,lmh-dcvs = <&lmh_dcvs2>;
+ #cooling-cells = <2>;
+ L2_700: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ next-level-cache = <&L3_0>;
+ };
+
+ L1_I_700: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_700: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+
+ core4 {
+ cpu = <&CPU4>;
+ };
+
+ core5 {
+ cpu = <&CPU5>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU6>;
+ };
+ };
+
+ cluster2 {
+ core0 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+ };
+
+ firmware: firmware {
+ android {
+ compatible = "android,firmware";
+ vbmeta {
+ compatible = "android,vbmeta";
+ parts = "vbmeta,boot,system,vendor,dtbo";
+ };
+
+ fstab {
+ compatible = "android,fstab";
+ vendor {
+ compatible = "android,vendor";
+ dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,discard";
+ fsmgr_flags = "wait,slotselect,avb";
+ status = "ok";
+ };
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: hyp_region@80000000 {
+ no-map;
+ reg = <0x0 0x80000000 0x0 0x600000>;
+ };
+
+ xbl_aop_mem: xbl_aop_region@80700000 {
+ no-map;
+ reg = <0x0 0x80700000 0x0 0x160000>;
+ };
+
+ cmd_db: reserved-memory@80860000 {
+ reg = <0x0 0x80860000 0x0 0x20000>;
+ compatible = "qcom,cmd-db";
+ no-map;
+ };
+
+ reserved_xbl_uefi_log: res_xbl_uefi_log_region@80880000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x80880000 0x0 0x14000>;
+ };
+
+ sec_apps_mem: sec_apps_region@808ff000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x808ff000 0x0 0x1000>;
+ };
+
+ smem_mem: smem_region@80900000 {
+ no-map;
+ reg = <0x0 0x80900000 0x0 0x200000>;
+ };
+
+ removed_mem: removed_region@80b00000 {
+ no-map;
+ reg = <0x0 0x80b00000 0x0 0x1300000>;
+ };
+
+ qtee_apps_mem: qtee_apps_region@81e00000 {
+ no-map;
+ reg = <0x0 0x81e00000 0x0 0x2600000>;
+ };
+
+ pil_camera_mem: pil_camera_region@86000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86000000 0x0 0x500000>;
+ };
+
+ pil_npu_mem: pil_npu_region@86500000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86500000 0x0 0x500000>;
+ };
+
+ pil_video_mem: pil_video_region@86a00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86a00000 0x0 0x500000>;
+ };
+
+ pil_cdsp_mem: pil_cdsp_region@87400000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x87400000 0x0 0x1e00000>;
+ };
+
+ pil_adsp_mem: pil_adsp_region@89200000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x89200000 0x0 0x2800000>;
+ };
+
+ pil_wlan_fw_mem: pil_wlan_fw_region@8ba00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8ba00000 0x0 0x200000>;
+ };
+
+ pil_ipa_fw_mem: pil_ipa_fw_region@8bc00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8bc00000 0x0 0x10000>;
+ };
+
+ pil_ipa_gsi_mem: pil_ipa_gsi_region@8bc10000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8bc10000 0x0 0x5400>;
+ };
+
+ pil_gpu_mem: pil_gpu_region@8bc15400 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8bc15400 0x0 0x2000>;
+ };
+
+ reserved_pil: reserved_pil_mem_region@8bc17400 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8bc17400 0x0 0x3e8c00>;
+ };
+
+ modem_wlan_mem: modem_wlan_region@8c000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8c000000 0x0 0xf800000>;
+ };
+
+ qseecom_mem: qseecom_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1400000>;
+ };
+
+ qseecom_ta_mem: qseecom_ta_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ cdsp_sec_mem: cdsp_sec_regions@9f400000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x9f400000 0x0 0xc00000>;
+ };
+
+ adsp_mem: adsp_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0xC00000>;
+ };
+
+ sdsp_mem: sdsp_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x400000>;
+ };
+
+ cdsp_mem: cdsp_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x400000>;
+ };
+
+ secure_display_memory: secure_display_region { /* Secure UI */
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0xA000000>;
+ };
+
+ cont_splash_memory: cont_splash_region {
+ reg = <0x0 0xA0000000 0x0 0x02300000>;
+ label = "cont_splash_region";
+ };
+
+ dfps_data_memory: dfps_data_region@a2300000 {
+ reg = <0x0 0xa2300000 0x0 0x0100000>;
+ label = "dfps_data_region";
+ };
+
+ disp_rdump_memory: disp_rdump_region@0xa0000000 {
+ reg = <0x0 0xA0000000 0x0 0x02300000>;
+ label = "disp_rdump_region";
+ };
+
+ dump_mem: mem_dump_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ size = <0 0x2800000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+
+ };
+
+ chosen {
+ bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 earlycon=msm_geni_serial,0x888000 kpti=off";
+ };
+
+ soc: soc { };
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ slim_aud: slim@3ac0000 {
+ cell-index = <1>;
+ compatible = "qcom,slim-ngd";
+ reg = <0x3ac0000 0x2c000>,
+ <0x3a84000 0x2c000>;
+ reg-names = "slimbus_physical", "slimbus_bam_physical";
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "slimbus_irq", "slimbus_bam_irq";
+ qcom,apps-ch-pipes = <0x700000>;
+ qcom,ea-pc = <0x330>;
+ iommus = <&apps_smmu 0x1426 0x0>,
+ <&apps_smmu 0x142f 0x0>,
+ <&apps_smmu 0x1430 0x1>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+ qcom,iommu-dma = "atomic";
+ status = "ok";
+
+ /* Slimbus Slave DT for WCN3990 */
+ btfmslim_codec: wcn3990 {
+ compatible = "qcom,btfmslim_slave";
+ elemental-addr = [00 01 20 02 17 02];
+ qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
+ qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
+ };
+ };
+
+ bluetooth: bt_wcn3990 {
+ compatible = "qca,wcn3990";
+ qca,bt-sw-ctrl-gpio = <&tlmm 73 0>; /* SW_CTRL */
+ qca,bt-vdd-io-supply = <&pm8150_s4>;
+ qca,bt-vdd-core-supply = <&pm8150a_l2>;
+ qca,bt-vdd-pa-supply = <&pm8150a_l10>;
+ qca,bt-vdd-xtal-supply = <&pm8150_l14>;
+
+ qca,bt-vdd-io-voltage-level = <1800000 1800000>; /* IO */
+ qca,bt-vdd-core-voltage-level = <1304000 1304000>; /* RFA */
+ qca,bt-vdd-pa-voltage-level = <3000000 3312000>; /*chain0 */
+ qca,bt-vdd-xtal-voltage-level = <1800000 1800000>; /* XO */
+
+ qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */
+ };
+
+ thermal_zones: thermal-zones {
+ };
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ reg = <0x17a00000 0x10000>, /* GICD */
+ <0x17a60000 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,lito-pdc";
+ reg = <0xb220000 0x30000>, <0x17c000f0 0x60>;
+ qcom,pdc-ranges = <0 480 42>, <42 612 28>, <70 63 1>,
+ <71 640 15>, <86 522 52>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ qcom,memshare {
+ compatible = "qcom,memshare";
+
+ qcom,client_1 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x0>;
+ qcom,client-id = <0>;
+ qcom,allocate-boot-time;
+ label = "modem";
+ };
+
+ qcom,client_2 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x0>;
+ qcom,client-id = <2>;
+ label = "modem";
+ };
+
+ mem_client_3_size: qcom,client_3 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x500000>;
+ qcom,client-id = <1>;
+ qcom,allocate-on-request;
+ label = "modem";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <19200000>;
+ };
+
+ timer@17c20000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x17c20000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@17c21000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c21000 0x1000>,
+ <0x17c22000 0x1000>;
+ };
+
+ frame@17c23000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c23000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c25000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c25000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c27000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c27000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c29000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c29000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c2b000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x17c2d000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ qcom,msm-imem@146ab000 {
+ compatible = "qcom,msm-imem";
+ reg = <0x146ab000 0x1000>;
+ ranges = <0x0 0x146ab000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mem_dump_table@10 {
+ compatible = "qcom,msm-imem-mem_dump_table";
+ reg = <0x10 0x8>;
+ };
+
+ restart_reason@65c {
+ compatible = "qcom,msm-imem-restart_reason";
+ reg = <0x65c 0x4>;
+ };
+
+ dload_type@1c {
+ compatible = "qcom,msm-imem-dload-type";
+ reg = <0x1c 0x4>;
+ };
+
+ boot_stats@6b0 {
+ compatible = "qcom,msm-imem-boot_stats";
+ reg = <0x6b0 0x20>;
+ };
+
+ kaslr_offset@6d0 {
+ compatible = "qcom,msm-imem-kaslr_offset";
+ reg = <0x6d0 0xc>;
+ };
+
+ pil@94c {
+ compatible = "qcom,msm-imem-pil";
+ reg = <0x94c 0xc8>;
+ };
+
+ diag_dload@c8 {
+ compatible = "qcom,msm-imem-diag-dload";
+ reg = <0xc8 0xc8>;
+ };
+ };
+
+ dcc: dcc_v2@1022000 {
+ compatible = "qcom,dcc-v2";
+ reg = <0x1022000 0x1000>,
+ <0x103b000 0x5000>;
+ reg-names = "dcc-base", "dcc-ram-base";
+
+ dcc-ram-offset = <0xb000>;
+
+ qcom,curr-link-list = <6>;
+ qcom,data-sink = "sram";
+ qcom,link-list = <DCC_READ 0x18000024 1 0>,
+ <DCC_READ 0x18000040 1 0>,
+ <DCC_READ 0x18010024 1 0>,
+ <DCC_READ 0x18010040 1 0>,
+ <DCC_READ 0x18020024 1 0>,
+ <DCC_READ 0x18020040 1 0>,
+ <DCC_READ 0x18030024 1 0>,
+ <DCC_READ 0x18030040 1 0>,
+ <DCC_READ 0x18040024 1 0>,
+ <DCC_READ 0x18040040 1 0>,
+ <DCC_READ 0x18050024 1 0>,
+ <DCC_READ 0x18050040 1 0>,
+ <DCC_READ 0x18060024 1 0>,
+ <DCC_READ 0x18060040 1 0>,
+ <DCC_READ 0x18070024 1 0>,
+ <DCC_READ 0x18070040 1 0>,
+ <DCC_READ 0x18080024 1 0>,
+ <DCC_READ 0x18080040 1 0>,
+ <DCC_READ 0x18080044 1 0>,
+ <DCC_READ 0x18080048 1 0>,
+ <DCC_READ 0x1808004c 1 0>,
+ <DCC_READ 0x18080054 1 0>,
+ <DCC_READ 0x1808006c 1 0>,
+ <DCC_READ 0x18080070 1 0>,
+ <DCC_READ 0x18080074 1 0>,
+ <DCC_READ 0x18080078 1 0>,
+ <DCC_READ 0x1808007c 1 0>,
+ <DCC_READ 0x180800f4 1 0>,
+ <DCC_READ 0x180800f8 1 0>,
+ <DCC_READ 0x18080104 1 0>,
+ <DCC_READ 0x18080118 1 0>,
+ <DCC_READ 0x1808011c 1 0>,
+ <DCC_READ 0x18080128 1 0>,
+ <DCC_READ 0x1808012c 1 0>,
+ <DCC_READ 0x18080130 1 0>,
+ <DCC_READ 0x18080134 1 0>,
+ <DCC_READ 0x18080138 1 0>,
+ <DCC_READ 0x18080158 1 0>,
+ <DCC_READ 0x1808015c 1 0>,
+ <DCC_READ 0x18080168 1 0>,
+ <DCC_READ 0x18080170 1 0>,
+ <DCC_READ 0x18080174 1 0>,
+ <DCC_READ 0x18080188 1 0>,
+ <DCC_READ 0x1808018c 1 0>,
+ <DCC_READ 0x18080198 1 0>,
+ <DCC_READ 0x180801ac 1 0>,
+ <DCC_READ 0x180801b0 1 0>,
+ <DCC_READ 0x180801b4 1 0>,
+ <DCC_READ 0x180801b8 1 0>,
+ <DCC_READ 0x180801bc 1 0>,
+ <DCC_READ 0x180801f0 1 0>,
+ <DCC_READ 0x18280000 1 0>,
+ <DCC_READ 0x18282000 1 0>,
+ <DCC_READ 0x18284000 1 0>,
+ <DCC_READ 0x18286000 1 0>,
+ <DCC_READ 0x1800005c 1 0>,
+ <DCC_READ 0x1801005c 1 0>,
+ <DCC_READ 0x1802005c 1 0>,
+ <DCC_READ 0x1803005c 1 0>,
+ <DCC_READ 0x1804005c 1 0>,
+ <DCC_READ 0x1805005c 1 0>,
+ <DCC_READ 0x1806005c 1 0>,
+ <DCC_READ 0x1807005c 1 0>,
+ <DCC_READ 0x18101908 1 0>,
+ <DCC_READ 0x18101c18 1 0>,
+ <DCC_READ 0x18390810 1 0>,
+ <DCC_READ 0x18390c50 1 0>,
+ <DCC_READ 0x18390814 1 0>,
+ <DCC_READ 0x18390c54 1 0>,
+ <DCC_READ 0x18390818 1 0>,
+ <DCC_READ 0x18390c58 1 0>,
+ <DCC_READ 0x18393a84 2 0>,
+ <DCC_READ 0x18100908 1 0>,
+ <DCC_READ 0x18100c18 1 0>,
+ <DCC_READ 0x183a0810 1 0>,
+ <DCC_READ 0x183a0c50 1 0>,
+ <DCC_READ 0x183a0814 1 0>,
+ <DCC_READ 0x183a0c54 1 0>,
+ <DCC_READ 0x183a0818 1 0>,
+ <DCC_READ 0x183a0c58 1 0>,
+ <DCC_READ 0x183a3a84 2 0>,
+ <DCC_READ 0x18393500 1 0>,
+ <DCC_READ 0x18393580 1 0>,
+ <DCC_READ 0x183a3500 1 0>,
+ <DCC_READ 0x183a3580 1 0>,
+ <DCC_READ 0x18280000 4 0>,
+ <DCC_READ 0x18284000 4 0>,
+ <DCC_READ 0x18286000 4 0>,
+ <DCC_READ 0x18282000 4 0>,
+ <DCC_READ 0x18282028 1 0>,
+ <DCC_READ 0x18282038 1 0>,
+ <DCC_READ 0x18282080 5 0>,
+ <DCC_READ 0x18286000 4 0>,
+ <DCC_READ 0x18286028 1 0>,
+ <DCC_READ 0x18286038 1 0>,
+ <DCC_READ 0x18286080 5 0>,
+ <DCC_READ 0x0c201244 1 0>,
+ <DCC_READ 0x0c202244 1 0>,
+ <DCC_READ 0x18300000 1 0>,
+ <DCC_READ 0x1829208c 1 0>,
+ <DCC_READ 0x18292098 1 0>,
+ <DCC_READ 0x18292098 1 0>,
+ <DCC_READ 0x1829608c 1 0>,
+ <DCC_READ 0x18296098 1 0>,
+ <DCC_READ 0x1832102c 1 0>,
+ <DCC_READ 0x18321044 1 0>,
+ <DCC_READ 0x18321700 1 0>,
+ <DCC_READ 0x18321710 1 0>,
+ <DCC_READ 0x1832176c 1 0>,
+ <DCC_READ 0x18321818 1 0>,
+ <DCC_READ 0x18321920 1 0>,
+ <DCC_READ 0x18322c18 1 0>,
+ <DCC_READ 0x1832302c 1 0>,
+ <DCC_READ 0x18323044 1 0>,
+ <DCC_READ 0x18323700 1 0>,
+ <DCC_READ 0x18323710 1 0>,
+ <DCC_READ 0x1832376c 1 0>,
+ <DCC_READ 0x18323818 1 0>,
+ <DCC_READ 0x18323920 1 0>,
+ <DCC_READ 0x18324c18 1 0>,
+ <DCC_READ 0x1832582c 1 0>,
+ <DCC_READ 0x18325844 1 0>,
+ <DCC_READ 0x18325f00 1 0>,
+ <DCC_READ 0x18325f10 1 0>,
+ <DCC_READ 0x18325f6c 1 0>,
+ <DCC_READ 0x18326018 1 0>,
+ <DCC_READ 0x18326120 1 0>,
+ <DCC_READ 0x18327418 1 0>,
+ <DCC_READ 0x1832782c 1 0>,
+ <DCC_READ 0x18327844 1 0>,
+ <DCC_READ 0x18327f00 1 0>,
+ <DCC_READ 0x18327f10 1 0>,
+ <DCC_READ 0x18327f6c 1 0>,
+ <DCC_READ 0x18328018 1 0>,
+ <DCC_READ 0x18328120 1 0>,
+ <DCC_READ 0x18329418 1 0>,
+ <DCC_READ 0x9680000 1 0>,
+ <DCC_READ 0x9680004 1 0>,
+ <DCC_LOOP 8 0 0>,
+ <DCC_READ 0x9681000 1 0>,
+ <DCC_LOOP 1 0 0>,
+ <DCC_READ 0x9681004 13 0>,
+ <DCC_READ 0x968103c 1 0>,
+ <DCC_READ 0x9698100 1 0>,
+ <DCC_READ 0x9698104 1 0>,
+ <DCC_READ 0x9698108 1 0>,
+ <DCC_READ 0x9698110 1 0>,
+ <DCC_READ 0x9698120 1 0>,
+ <DCC_READ 0x9698124 1 0>,
+ <DCC_READ 0x9698128 1 0>,
+ <DCC_READ 0x969812c 1 0>,
+ <DCC_READ 0x9698130 1 0>,
+ <DCC_READ 0x9698134 1 0>,
+ <DCC_READ 0x9698138 1 0>,
+ <DCC_READ 0x969813c 1 0>,
+ <DCC_READ 0x16e0000 1 0>,
+ <DCC_READ 0x16e0004 1 0>,
+ <DCC_READ 0x16e0288 1 0>,
+ <DCC_READ 0x16e0290 1 0>,
+ <DCC_READ 0x16e0300 1 0>,
+ <DCC_READ 0x16e0408 1 0>,
+ <DCC_READ 0x16e0410 1 0>,
+ <DCC_READ 0x16e0420 1 0>,
+ <DCC_READ 0x16e0424 1 0>,
+ <DCC_READ 0x16e0428 1 0>,
+ <DCC_READ 0x16e042c 1 0>,
+ <DCC_READ 0x16e0430 1 0>,
+ <DCC_READ 0x16e0434 1 0>,
+ <DCC_READ 0x16e0438 1 0>,
+ <DCC_READ 0x16e043c 1 0>,
+ <DCC_READ 0x16e0688 1 0>,
+ <DCC_READ 0x16e0690 1 0>,
+ <DCC_READ 0x16e0700 1 0>,
+ <DCC_READ 0x16e0888 1 0>,
+ <DCC_READ 0x16e0890 1 0>,
+ <DCC_READ 0x16e0900 1 0>,
+ <DCC_READ 0x16e0904 1 0>,
+ <DCC_READ 0x16e0a40 1 0>,
+ <DCC_READ 0x16e0a48 1 0>,
+ <DCC_READ 0x16e0a88 1 0>,
+ <DCC_READ 0x16e0a90 1 0>,
+ <DCC_READ 0x16e0b00 1 0>,
+ <DCC_READ 0x1700204 1 0>,
+ <DCC_READ 0x1700240 1 0>,
+ <DCC_READ 0x1700248 1 0>,
+ <DCC_READ 0x1700288 1 0>,
+ <DCC_READ 0x1700290 1 0>,
+ <DCC_READ 0x1700300 1 0>,
+ <DCC_READ 0x1700304 1 0>,
+ <DCC_READ 0x1700308 1 0>,
+ <DCC_READ 0x170030c 1 0>,
+ <DCC_READ 0x1700310 1 0>,
+ <DCC_READ 0x1700400 1 0>,
+ <DCC_READ 0x1700404 1 0>,
+ <DCC_READ 0x1700488 1 0>,
+ <DCC_READ 0x1700490 1 0>,
+ <DCC_READ 0x1700500 1 0>,
+ <DCC_READ 0x1700504 1 0>,
+ <DCC_READ 0x1700508 1 0>,
+ <DCC_READ 0x170050c 1 0>,
+ <DCC_READ 0x1700c00 1 0>,
+ <DCC_READ 0x1700c04 1 0>,
+ <DCC_READ 0x1700c08 1 0>,
+ <DCC_READ 0x1700c10 1 0>,
+ <DCC_READ 0x1700c20 1 0>,
+ <DCC_READ 0x1700c24 1 0>,
+ <DCC_READ 0x1700c28 1 0>,
+ <DCC_READ 0x1700c2c 1 0>,
+ <DCC_READ 0x1700c30 1 0>,
+ <DCC_READ 0x1700c34 1 0>,
+ <DCC_READ 0x1700c38 1 0>,
+ <DCC_READ 0x1700c3c 1 0>,
+ <DCC_READ 0x1620000 1 0>,
+ <DCC_READ 0x1620004 1 0>,
+ <DCC_READ 0x1620008 1 0>,
+ <DCC_READ 0x1620010 1 0>,
+ <DCC_READ 0x1620020 1 0>,
+ <DCC_READ 0x1620024 1 0>,
+ <DCC_READ 0x1620028 1 0>,
+ <DCC_READ 0x162002c 1 0>,
+ <DCC_READ 0x1620030 1 0>,
+ <DCC_READ 0x1620034 1 0>,
+ <DCC_READ 0x1620038 1 0>,
+ <DCC_READ 0x162003c 1 0>,
+ <DCC_READ 0x1620100 1 0>,
+ <DCC_READ 0x1620104 1 0>,
+ <DCC_READ 0x1620108 1 0>,
+ <DCC_READ 0x1620110 1 0>,
+ <DCC_READ 0x1620200 1 0>,
+ <DCC_READ 0x1620204 1 0>,
+ <DCC_READ 0x1620240 1 0>,
+ <DCC_READ 0x1620248 1 0>,
+ <DCC_READ 0x1620288 1 0>,
+ <DCC_READ 0x162028c 1 0>,
+ <DCC_READ 0x1620290 1 0>,
+ <DCC_READ 0x1620294 1 0>,
+ <DCC_READ 0x16202a8 1 0>,
+ <DCC_READ 0x16202ac 1 0>,
+ <DCC_READ 0x16202b0 1 0>,
+ <DCC_READ 0x16202b4 1 0>,
+ <DCC_READ 0x1620300 1 0>,
+ <DCC_READ 0x1620400 1 0>,
+ <DCC_READ 0x1620404 1 0>,
+ <DCC_READ 0x1620488 1 0>,
+ <DCC_READ 0x1620490 1 0>,
+ <DCC_READ 0x1620500 1 0>,
+ <DCC_READ 0x1620504 1 0>,
+ <DCC_READ 0x1620508 1 0>,
+ <DCC_READ 0x162050c 1 0>,
+ <DCC_READ 0x1620510 1 0>,
+ <DCC_READ 0x1620600 1 0>,
+ <DCC_READ 0x1620604 1 0>,
+ <DCC_READ 0x1620688 1 0>,
+ <DCC_READ 0x1620690 1 0>,
+ <DCC_READ 0x1620700 1 0>,
+ <DCC_READ 0x1620704 1 0>,
+ <DCC_READ 0x1620708 1 0>,
+ <DCC_READ 0x162070c 1 0>,
+ <DCC_READ 0x1620710 1 0>,
+ <DCC_READ 0x1620800 1 0>,
+ <DCC_READ 0x1620804 1 0>,
+ <DCC_READ 0x1620900 1 0>,
+ <DCC_READ 0x1620a00 1 0>,
+ <DCC_READ 0x1620a04 1 0>,
+ <DCC_READ 0x1620b00 1 0>,
+ <DCC_READ 0x1620b04 1 0>,
+ <DCC_READ 0x1620e00 1 0>,
+ <DCC_READ 0x1620e04 1 0>,
+ <DCC_READ 0x1620e88 1 0>,
+ <DCC_READ 0x1620e90 1 0>,
+ <DCC_READ 0x1620f00 1 0>,
+ <DCC_READ 0x1639000 1 0>,
+ <DCC_READ 0x1639004 1 0>,
+ <DCC_READ 0x1639088 1 0>,
+ <DCC_READ 0x1639090 1 0>,
+ <DCC_READ 0x1639100 1 0>,
+ <DCC_READ 0x3c41800 1 0>,
+ <DCC_READ 0x3c41804 1 0>,
+ <DCC_READ 0x3c41880 1 0>,
+ <DCC_READ 0x3c41888 1 0>,
+ <DCC_READ 0x3c41890 1 0>,
+ <DCC_READ 0x3c41900 1 0>,
+ <DCC_READ 0x3c41a00 1 0>,
+ <DCC_READ 0x3c41a04 1 0>,
+ <DCC_READ 0x3c41a40 1 0>,
+ <DCC_READ 0x3c41a48 1 0>,
+ <DCC_READ 0x3c41c00 1 0>,
+ <DCC_READ 0x3c41c04 1 0>,
+ <DCC_READ 0x3c41d00 1 0>,
+ <DCC_READ 0x3c42680 1 0>,
+ <DCC_READ 0x3c42684 1 0>,
+ <DCC_READ 0x3c42688 1 0>,
+ <DCC_READ 0x3c42690 1 0>,
+ <DCC_READ 0x3c42698 1 0>,
+ <DCC_READ 0x3c426a0 1 0>,
+ <DCC_READ 0x3c426a4 1 0>,
+ <DCC_READ 0x3c426a8 1 0>,
+ <DCC_READ 0x3c426ac 1 0>,
+ <DCC_READ 0x3c426b0 1 0>,
+ <DCC_READ 0x3c426b4 1 0>,
+ <DCC_READ 0x3c426b8 1 0>,
+ <DCC_READ 0x3c426bc 1 0>,
+ <DCC_READ 0x9681010 1 0>,
+ <DCC_READ 0x9681014 1 0>,
+ <DCC_READ 0x9681018 1 0>,
+ <DCC_READ 0x968101c 1 0>,
+ <DCC_READ 0x9681020 1 0>,
+ <DCC_READ 0x9681024 1 0>,
+ <DCC_READ 0x9681028 1 0>,
+ <DCC_READ 0x968102c 1 0>,
+ <DCC_READ 0x9681030 1 0>,
+ <DCC_READ 0x9681034 1 0>,
+ <DCC_READ 0x968103c 1 0>,
+ <DCC_READ 0x9692000 1 0>,
+ <DCC_READ 0x9692004 1 0>,
+ <DCC_READ 0x9692008 1 0>,
+ <DCC_READ 0x9692040 1 0>,
+ <DCC_READ 0x9692048 1 0>,
+ <DCC_READ 0x9695000 1 0>,
+ <DCC_READ 0x9695004 1 0>,
+ <DCC_READ 0x9695080 1 0>,
+ <DCC_READ 0x9695084 1 0>,
+ <DCC_READ 0x9695088 1 0>,
+ <DCC_READ 0x969508c 1 0>,
+ <DCC_READ 0x9695090 1 0>,
+ <DCC_READ 0x9695094 1 0>,
+ <DCC_READ 0x96950a0 1 0>,
+ <DCC_READ 0x96950a8 1 0>,
+ <DCC_READ 0x96950b0 1 0>,
+ <DCC_READ 0x9695100 1 0>,
+ <DCC_READ 0x9695104 1 0>,
+ <DCC_READ 0x9695108 1 0>,
+ <DCC_READ 0x969510c 1 0>,
+ <DCC_READ 0x9695110 1 0>,
+ <DCC_READ 0x9695114 1 0>,
+ <DCC_READ 0x9695118 1 0>,
+ <DCC_READ 0x969511c 1 0>,
+ <DCC_READ 0x9696000 1 0>,
+ <DCC_READ 0x9696004 1 0>,
+ <DCC_READ 0x9696080 1 0>,
+ <DCC_READ 0x9696088 1 0>,
+ <DCC_READ 0x9696090 1 0>,
+ <DCC_READ 0x9696100 1 0>,
+ <DCC_READ 0x9696104 1 0>,
+ <DCC_READ 0x9696108 1 0>,
+ <DCC_READ 0x969610c 1 0>,
+ <DCC_READ 0x9696114 1 0>,
+ <DCC_READ 0x9696118 1 0>,
+ <DCC_READ 0x969611c 1 0>,
+ <DCC_READ 0x9698000 1 0>,
+ <DCC_READ 0x9698004 1 0>,
+ <DCC_READ 0x9698008 1 0>,
+ <DCC_READ 0x9698010 1 0>,
+ <DCC_READ 0x9698100 1 0>,
+ <DCC_READ 0x9698104 1 0>,
+ <DCC_READ 0x9698108 1 0>,
+ <DCC_READ 0x9698110 1 0>,
+ <DCC_READ 0x9698118 1 0>,
+ <DCC_READ 0x9698120 1 0>,
+ <DCC_READ 0x9698124 1 0>,
+ <DCC_READ 0x9698128 1 0>,
+ <DCC_READ 0x969812c 1 0>,
+ <DCC_READ 0x9698130 1 0>,
+ <DCC_READ 0x9698134 1 0>,
+ <DCC_READ 0x9698138 1 0>,
+ <DCC_READ 0x969813c 1 0>,
+ <DCC_READ 0x9698200 1 0>,
+ <DCC_READ 0x9698204 1 0>,
+ <DCC_READ 0x9698240 1 0>,
+ <DCC_READ 0x9698244 1 0>,
+ <DCC_READ 0x9698248 1 0>,
+ <DCC_READ 0x969824c 1 0>,
+ <DCC_READ 0x9220480 1 0>,
+ <DCC_READ 0x9232100 1 0>,
+ <DCC_READ 0x92360b0 1 0>,
+ <DCC_READ 0x9236044 4 0>,
+ <DCC_READ 0x923e030 1 0>,
+ <DCC_READ 0x9241000 1 0>,
+ <DCC_READ 0x9248048 4 0>,
+ <DCC_READ 0x9248058 4 0>,
+ <DCC_READ 0x9260400 1 0>,
+ <DCC_READ 0x9260410 1 0>,
+ <DCC_READ 0x9260414 1 0>,
+ <DCC_READ 0x9260418 1 0>,
+ <DCC_READ 0x9260420 1 0>,
+ <DCC_READ 0x9260424 1 0>,
+ <DCC_READ 0x9260430 1 0>,
+ <DCC_READ 0x9260440 1 0>,
+ <DCC_READ 0x9260448 1 0>,
+ <DCC_READ 0x92604a0 1 0>,
+ <DCC_READ 0x92604b8 1 0>,
+ <DCC_READ 0x9265804 1 0>,
+ <DCC_READ 0x9266418 1 0>,
+ <DCC_READ 0x92e0400 1 0>,
+ <DCC_READ 0x92e0410 1 0>,
+ <DCC_READ 0x92e0414 1 0>,
+ <DCC_READ 0x92e0418 1 0>,
+ <DCC_READ 0x92e0420 1 0>,
+ <DCC_READ 0x92e0424 1 0>,
+ <DCC_READ 0x92e0430 1 0>,
+ <DCC_READ 0x92e0440 1 0>,
+ <DCC_READ 0x92e0448 1 0>,
+ <DCC_READ 0x92e04a0 1 0>,
+ <DCC_READ 0x92e04b8 1 0>,
+ <DCC_READ 0x92e5804 1 0>,
+ <DCC_READ 0x92e6418 1 0>,
+ <DCC_READ 0x9600000 1 0>,
+ <DCC_READ 0x9600004 1 0>,
+ <DCC_READ 0x9601000 1 0>,
+ <DCC_READ 0x9601004 1 0>,
+ <DCC_READ 0x9602000 1 0>,
+ <DCC_READ 0x9602004 1 0>,
+ <DCC_READ 0x9603000 1 0>,
+ <DCC_READ 0x9603004 1 0>,
+ <DCC_READ 0x9604000 1 0>,
+ <DCC_READ 0x9604004 1 0>,
+ <DCC_READ 0x9605000 1 0>,
+ <DCC_READ 0x9605004 1 0>,
+ <DCC_READ 0x9606000 1 0>,
+ <DCC_READ 0x9606004 1 0>,
+ <DCC_READ 0x9607000 1 0>,
+ <DCC_READ 0x9607004 1 0>,
+ <DCC_READ 0x9608000 1 0>,
+ <DCC_READ 0x9608004 1 0>,
+ <DCC_READ 0x9609000 1 0>,
+ <DCC_READ 0x9609004 1 0>,
+ <DCC_READ 0x960a000 1 0>,
+ <DCC_READ 0x960a004 1 0>,
+ <DCC_READ 0x960b000 1 0>,
+ <DCC_READ 0x960b004 1 0>,
+ <DCC_READ 0x960c000 1 0>,
+ <DCC_READ 0x960c004 1 0>,
+ <DCC_READ 0x960d000 1 0>,
+ <DCC_READ 0x960d004 1 0>,
+ <DCC_READ 0x960e000 1 0>,
+ <DCC_READ 0x960e004 1 0>,
+ <DCC_READ 0x960f000 1 0>,
+ <DCC_READ 0x960f004 1 0>,
+ <DCC_READ 0x9610000 1 0>,
+ <DCC_READ 0x9610004 1 0>,
+ <DCC_READ 0x9611000 1 0>,
+ <DCC_READ 0x9611004 1 0>,
+ <DCC_READ 0x9612000 1 0>,
+ <DCC_READ 0x9612004 1 0>,
+ <DCC_READ 0x9613000 1 0>,
+ <DCC_READ 0x9613004 1 0>,
+ <DCC_READ 0x9614000 1 0>,
+ <DCC_READ 0x9614004 1 0>,
+ <DCC_READ 0x9615000 1 0>,
+ <DCC_READ 0x9615004 1 0>,
+ <DCC_READ 0x9616000 1 0>,
+ <DCC_READ 0x9616004 1 0>,
+ <DCC_READ 0x9617000 1 0>,
+ <DCC_READ 0x9617004 1 0>,
+ <DCC_READ 0x9618000 1 0>,
+ <DCC_READ 0x9618004 1 0>,
+ <DCC_READ 0x9619000 1 0>,
+ <DCC_READ 0x9619004 1 0>,
+ <DCC_READ 0x961a000 1 0>,
+ <DCC_READ 0x961a004 1 0>,
+ <DCC_READ 0x961b000 1 0>,
+ <DCC_READ 0x961b004 1 0>,
+ <DCC_READ 0x961c000 1 0>,
+ <DCC_READ 0x961c004 1 0>,
+ <DCC_READ 0x961d000 1 0>,
+ <DCC_READ 0x961d004 1 0>,
+ <DCC_READ 0x961e000 1 0>,
+ <DCC_READ 0x961e004 1 0>,
+ <DCC_READ 0x961f000 1 0>,
+ <DCC_READ 0x961f004 1 0>,
+ <DCC_READ 0x9050008 1 0>,
+ <DCC_READ 0x9050068 1 0>,
+ <DCC_READ 0x9050078 1 0>,
+ <DCC_READ 0x90b0280 1 0>,
+ <DCC_READ 0x90b0288 1 0>,
+ <DCC_READ 0x90b028c 1 0>,
+ <DCC_READ 0x90b0290 1 0>,
+ <DCC_READ 0x90b0294 1 0>,
+ <DCC_READ 0x90b0298 1 0>,
+ <DCC_READ 0x90b029c 1 0>,
+ <DCC_READ 0x90b02a0 1 0>,
+ <DCC_READ 0x92a0480 1 0>,
+ <DCC_READ 0x92b2100 1 0>,
+ <DCC_READ 0x92b6044 1 0>,
+ <DCC_READ 0x92b6048 1 0>,
+ <DCC_READ 0x92b604c 1 0>,
+ <DCC_READ 0x92b6050 1 0>,
+ <DCC_READ 0x92b60b0 1 0>,
+ <DCC_READ 0x92be030 1 0>,
+ <DCC_READ 0x92c1000 1 0>,
+ <DCC_READ 0x92c8048 4 0>,
+ <DCC_READ 0x92c8058 1 0>,
+ <DCC_READ 0x92c805c 1 0>,
+ <DCC_READ 0x92c8060 1 0>,
+ <DCC_READ 0x92c8064 1 0>;
+ };
+
+ restart@c264000 {
+ compatible = "qcom,pshold";
+ reg = <0xc264000 0x4>,
+ <0x1fd3000 0x4>;
+ reg-names = "pshold-base", "tcsr-boot-misc-detect";
+ };
+
+ qcom_seecom: qseecom@82200000 {
+ compatible = "qcom,qseecom";
+ reg = <0x82200000 0x2200000>;
+ reg-names = "secapp-region";
+ memory-region = <&qseecom_mem>;
+ qcom,hlos-num-ce-hw-instances = <1>;
+ qcom,hlos-ce-hw-instance = <0>;
+ qcom,qsee-ce-hw-instance = <0>;
+ qcom,disk-encrypt-pipe-pair = <2>;
+ qcom,support-fde;
+ qcom,no-clock-support;
+ qcom,fde-key-size;
+ qcom,commonlib64-loaded-by-uefi;
+ qcom,qsee-reentrancy-support = <2>;
+ };
+
+ qcom_smcinvoke: smcinvoke@82200000 {
+ compatible = "qcom,smcinvoke";
+ reg = <0x82200000 0x2200000>;
+ reg-names = "secapp-region";
+ };
+
+ qcom_rng: qrng@793000 {
+ compatible = "qcom,msm-rng";
+ reg = <0x793000 0x1000>;
+ qcom,msm-rng-iface-clk;
+ qcom,no-qrng-config;
+ qcom,msm-bus,name = "msm-rng-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_PRNG 0 0>, /* No vote */
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_PRNG 0 300000>; /* 75 MHz */
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "iface_clk";
+ };
+
+ qcom_tzlog: tz-log@146ab720 {
+ compatible = "qcom,tz-log";
+ reg = <0x146ab720 0x3000>;
+ qcom,hyplog-enabled;
+ hyplog-address-offset = <0x410>;
+ hyplog-size-offset = <0x414>;
+ };
+
+ qcom_cedev: qcedev@1de0000 {
+ compatible = "qcom,qcedev";
+ reg = <0x1de0000 0x20000>,
+ <0x1dc4000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <3>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,ce-hw-shared;
+ qcom,bam-ee = <0>;
+ qcom,msm-bus,name = "qcedev-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CRYPTO_CORE_0
+ MSM_BUS_SLAVE_FIRST 0 0>,
+ <MSM_BUS_MASTER_CRYPTO_CORE_0
+ MSM_BUS_SLAVE_FIRST 393600 393600>;
+ qcom,smmu-s1-enable;
+ qcom,no-clock-support;
+ iommus = <&apps_smmu 0x0506 0x0011>,
+ <&apps_smmu 0x0516 0x0011>;
+ qcom,iommu-dma = "atomic";
+
+ qcom_cedev_ns_cb {
+ compatible = "qcom,qcedev,context-bank";
+ label = "ns_context";
+ iommus = <&apps_smmu 0x512 0>,
+ <&apps_smmu 0x518 0x1>,
+ <&apps_smmu 0x51F 0>;
+ };
+
+ qcom_cedev_s_cb {
+ compatible = "qcom,qcedev,context-bank";
+ label = "secure_context";
+ iommus = <&apps_smmu 0x513 0>,
+ <&apps_smmu 0x51C 0x1>,
+ <&apps_smmu 0x51E 0>;
+ qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
+ qcom,secure-context-bank;
+ };
+ };
+
+ qcom_crypto: qcrypto@1de0000 {
+ compatible = "qcom,qcrypto";
+ reg = <0x1de0000 0x20000>,
+ <0x1dc4000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <2>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,bam-ee = <0>;
+ qcom,ce-hw-shared;
+ qcom,clk-mgmt-sus-res;
+ qcom,msm-bus,name = "qcrypto-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CRYPTO_CORE_0 MSM_BUS_SLAVE_FIRST 0 0>,
+ <MSM_BUS_MASTER_CRYPTO_CORE_0
+ MSM_BUS_SLAVE_FIRST 393600 393600>;
+ qcom,use-sw-aes-cbc-ecb-ctr-algo;
+ qcom,use-sw-aes-xts-algo;
+ qcom,use-sw-aes-ccm-algo;
+ qcom,use-sw-ahash-algo;
+ qcom,use-sw-aead-algo;
+ qcom,use-sw-hmac-algo;
+ qcom,smmu-s1-enable;
+ qcom,no-clock-support;
+ iommus = <&apps_smmu 0x0504 0x0011>,
+ <&apps_smmu 0x0514 0x0011>;
+ qcom,iommu-dma = "atomic";
+ };
+
+ qcom,mpm2-sleep-counter@0xc221000 {
+ compatible = "qcom,mpm2-sleep-counter";
+ reg = <0xc221000 0x1000>;
+ clock-frequency = <32768>;
+ };
+
+ qcom,msm-rtb {
+ compatible = "qcom,msm-rtb";
+ qcom,rtb-size = <0x100000>;
+ };
+
+ wdog: qcom,wdt@17c10000 {
+ compatible = "qcom,msm-watchdog";
+ reg = <0x17c10000 0x1000>;
+ reg-names = "wdt-base";
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bark-time = <11000>;
+ qcom,pet-time = <9360>;
+ qcom,ipi-ping;
+ qcom,wakeup-enable;
+ };
+
+ jtag_mm0: jtagmm@7040000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7040000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU0>;
+ };
+
+ jtag_mm1: jtagmm@7140000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7140000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU1>;
+ };
+
+ jtag_mm2: jtagmm@7240000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7240000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU2>;
+ };
+
+ jtag_mm3: jtagmm@7340000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7340000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU3>;
+ };
+
+ jtag_mm4: jtagmm@7440000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7440000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU4>;
+ };
+
+ jtag_mm5: jtagmm@7540000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7540000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU5>;
+ };
+
+ jtag_mm6: jtagmm@7640000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7640000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU6>;
+ };
+
+ jtag_mm7: jtagmm@7740000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7740000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&aopcc QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU7>;
+ };
+
+ keepalive_opp_table: keepalive-opp-table {
+ compatible = "operating-points-v2";
+ opp-1 {
+ opp-hz = /bits/ 64 < 1 >;
+ };
+ };
+
+ snoc_cnoc_keepalive: qcom,snoc_cnoc_keepalive {
+ compatible = "qcom,devbw";
+ governor = "powersave";
+ qcom,src-dst-ports = <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_IMEM_CFG>;
+ qcom,active-only;
+ status = "ok";
+ operating-points-v2 = <&keepalive_opp_table>;
+ };
+
+ bus_proxy_client: qcom,bus_proxy_client {
+ compatible = "qcom,bus-proxy-client";
+ qcom,msm-bus,name = "bus-proxy-client";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>, <23 512 0 0>,
+ <22 512 0 5000000>, <23 512 0 5000000>;
+ qcom,msm-bus,active-only;
+ status = "ok";
+ };
+
+ qcom,sps {
+ compatible = "qcom,msm-sps-4k";
+ qcom,pipe-attr-ee;
+ };
+
+ tsens0: tsens@c222000 {
+ compatible = "qcom,tsens26xx";
+ reg = <0xc222000 0x8>,
+ <0xc263000 0x1ff>;
+ reg-names = "tsens_srot_physical",
+ "tsens_tm_physical";
+
+ interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 20 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tsens-upper-lower",
+ "tsens-critical", "tsens-0C";
+ 0C-sensor-num = <16>;
+ tsens-reinit-wa;
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: tsens@c223000 {
+ compatible = "qcom,tsens26xx";
+ reg = <0xc223000 0x8>,
+ <0xc265000 0x1ff>;
+ reg-names = "tsens_srot_physical",
+ "tsens_tm_physical";
+
+ interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tsens-upper-lower",
+ "tsens-critical", "tsens-0C";
+ 0C-sensor-num = <16>;
+ tsens-reinit-wa;
+ #thermal-sensor-cells = <1>;
+ };
+
+ qcom,ghd {
+ compatible = "qcom,gladiator-hang-detect-v3";
+ qcom,threshold-arr = <0x17e0041c>;
+ qcom,config-reg = <0x17e00434>;
+ };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+ clock-output-names = "xo_board";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-output-names = "chip_sleep_clk";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ aopcc: qcom,aopclk {
+ compatible = "qcom,aop-qmp-clk";
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "qdss_clk";
+ qcom,clk-stop-bimc-log;
+ #clock-cells = <1>;
+ };
+
+ gcc: qcom,gcc@100000 {
+ compatible = "qcom,gcc-lito", "syscon";
+ reg = <0x100000 0x1f0000>;
+ reg-names = "cc_base";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ camcc: qcom,camcc@ad00000 {
+ compatible = "qcom,lito-camcc", "syscon";
+ reg = <0xad00000 0x10000>;
+ reg-names = "cc_base";
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ clock-names = "cfg_ahb_clk";
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ videocc: qcom,videocc@ab00000 {
+ compatible = "qcom,lito-videocc", "syscon";
+ reg = <0x0ab00000 0x10000>;
+ reg-names = "cc_base";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ clock-names = "cfg_ahb_clk";
+ clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+ nvmem-cells = <&iris_efuse>;
+ nvmem-cell-names = "iris-bin";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ dispcc: qcom,dispcc@af00000 {
+ compatible = "qcom,lito-dispcc", "syscon";
+ reg = <0xaf00000 0x20000>;
+ reg-names = "cc_base";
+ clock-names = "cfg_ahb_clk";
+ clocks = <&gcc GCC_DISP_AHB_CLK>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gpucc: qcom,gpucc@3d90000 {
+ compatible = "qcom,lito-gpucc", "syscon";
+ reg = <0x3d90000 0x9000>;
+ reg-names = "cc_base";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ npucc: qcom,npucc@9980000 {
+ compatible = "qcom,lito-npucc", "syscon";
+ reg = <0x9980000 0x10000>,
+ <0x9800000 0x10000>,
+ <0x9810000 0x10000>;
+ reg-names = "cc", "qdsp6ss", "qdsp6ss_pll";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ nvmem-cells = <&npu_efuse>;
+ nvmem-cell-names = "npu-bin";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cpucc: syscon@182a0018 {
+ compatible = "syscon";
+ reg = <0x182a0000 0x4>;
+ };
+
+ mccc: syscon@90b0000 {
+ compatible = "syscon";
+ reg = <0x90b0000 0x1000>;
+ };
+
+ debugcc: qcom,cc-debug {
+ compatible = "qcom,lito-debugcc";
+ qcom,gcc = <&gcc>;
+ qcom,videocc = <&videocc>;
+ qcom,dispcc = <&dispcc>;
+ qcom,camcc = <&camcc>;
+ qcom,gpucc = <&gpucc>;
+ qcom,npucc = <&npucc>;
+ qcom,cpucc = <&cpucc>;
+ qcom,mccc = <&mccc>;
+ clock-names = "xo_clk_src";
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ #clock-cells = <1>;
+ };
+
+ cpufreq_hw: qcom,cpufreq-hw {
+ compatible = "qcom,cpufreq-hw";
+ reg = <0x18323000 0x1000>, <0x18325800 0x1000>,
+ <0x18327800 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1",
+ "freq-domain2";
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+ qcom,no-accumulative-counter;
+ #freq-domain-cells = <2>;
+ };
+
+ qcom,cpufreq-hw-debug@18320000 {
+ compatible = "qcom,cpufreq-hw-debug-trace";
+ reg = <0x18320000 0x800>;
+ reg-names = "domain-top";
+ qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>,
+ <&cpufreq_hw 2>;
+ };
+
+ qcom,devfreq-l3 {
+ compatible = "qcom,devfreq-fw";
+ reg = <0x18321000 0x4>, <0x18321110 0x500>, <0x18321920 0x4>,
+ <0x18321700 0x4>;
+ reg-names = "en-base", "ftbl-base", "perf-base", "pstate-base";
+
+ qcom,ftbl-row-size = <32>;
+ qcom,support-panic-notifier;
+
+ cpu0_l3: qcom,cpu0-cpu-l3-lat {
+ compatible = "qcom,devfreq-fw-voter";
+ };
+
+ cpu6_l3: qcom,cpu6-cpu-l3-lat {
+ compatible = "qcom,devfreq-fw-voter";
+ };
+
+ cpu7_l3: qcom,cpu7-cpu-l3-lat {
+ compatible = "qcom,devfreq-fw-voter";
+ };
+
+ cdsp_l3: qcom,cdsp-cdsp-l3-lat {
+ compatible = "qcom,devfreq-fw-voter";
+ };
+ };
+
+ spmi_bus: qcom,spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0xc440000 0x1100>,
+ <0xc600000 0x2000000>,
+ <0xe600000 0x100000>,
+ <0xe700000 0xa0000>,
+ <0xc40a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
+ ufshc_mem: ufshc@1d84000 {
+ compatible = "qcom,ufshc";
+ reg = <0x1d84000 0x3000>, <0x1d90000 0x8000>;
+ reg-names = "ufs_mem", "ufs_ice";
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufsphy_mem>;
+ phy-names = "ufsphy";
+
+ lanes-per-direction = <2>;
+ dev-ref-clk-freq = <0>; /* 19.2 MHz */
+ spm-level = <3>;
+
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "core_clk_ice",
+ "core_clk_ice_hw_ctl",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+ clocks =
+ <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+ <&gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ freq-table-hz =
+ <50000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <37500000 150000000>,
+ <75000000 300000000>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ qcom,msm-bus,name = "ufshc_mem";
+ qcom,msm-bus,num-cases = <22>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /*
+ * During HS G3 UFS runs at nominal voltage corner, vote
+ * higher bandwidth to push other buses in the data path
+ * to run at nominal to achieve max throughput.
+ * 4GBps pushes BIMC to run at nominal.
+ * 200MBps pushes CNOC to run at nominal.
+ * Vote for half of this bandwidth for HS G3 1-lane.
+ * For max bandwidth, vote high enough to push the buses
+ * to run in turbo voltage corner.
+ */
+ <123 512 0 0>, <1 757 0 0>, /* No vote */
+ <123 512 922 0>, <1 757 1000 0>, /* PWM G1 */
+ <123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */
+ <123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */
+ <123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */
+ <123 512 1844 0>, <1 757 1000 0>, /* PWM G1 L2 */
+ <123 512 3688 0>, <1 757 1000 0>, /* PWM G2 L2 */
+ <123 512 7376 0>, <1 757 1000 0>, /* PWM G3 L2 */
+ <123 512 14752 0>, <1 757 1000 0>, /* PWM G4 L2 */
+ <123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */
+ <123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */
+ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */
+ <123 512 255591 0>, <1 757 1000 0>, /* HS G1 RA L2 */
+ <123 512 511181 0>, <1 757 1000 0>, /* HS G2 RA L2 */
+ <123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */
+ <123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */
+ <123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */
+ <123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */
+ <123 512 298189 0>, <1 757 1000 0>, /* HS G1 RB L2 */
+ <123 512 596378 0>, <1 757 1000 0>, /* HS G2 RB L2 */
+ /* As UFS working in HS G3 RB L2 mode, aggregated
+ * bandwidth (AB) should take care of providing
+ * optimum throughput requested. However, as tested,
+ * in order to scale up CNOC clock, instantaneous
+ * bindwidth (IB) needs to be given a proper value too.
+ */
+ <123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */
+ <123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
+
+ qcom,bus-vector-names = "MIN",
+ "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
+ "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
+ "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
+ "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",
+ "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
+ "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",
+ "MAX";
+
+ /* PM QoS */
+ qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
+ qcom,pm-qos-cpu-group-latency-us = <67 67>;
+ qcom,pm-qos-default-cpu = <0>;
+
+ pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
+ pinctrl-0 = <&ufs_dev_reset_assert>;
+ pinctrl-1 = <&ufs_dev_reset_deassert>;
+
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "core_reset";
+ non-removable;
+
+ status = "disabled";
+ };
+
+ sdhc_1: sdhci@7c4000 {
+ compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe";
+ reg = <0x7c4000 0x1000>, <0x7c5000 0x1000>, <0x7c8000 0x8000>;
+ reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";
+
+ interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <8>;
+ qcom,large-address-bus;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
+ 192000000 384000000>;
+ qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+
+ qcom,devfreq,freq-table = <50000000 200000000>;
+
+ qcom,scaling-lower-bus-speed-mode = "DDR52";
+
+ qcom,msm-bus,name = "sdhc1";
+ qcom,msm-bus,num-cases = <9>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <150 10073 0 0>,
+ <135 512 0 0>,
+ <1 825 0 0>,
+ /* 400 KB/s*/
+ <150 10073 1000 7600>,
+ <135 512 1000 90000>,
+ <1 825 2000 6600>,
+ /* 20 MB/s */
+ <150 10073 25000 76000>,
+ <135 512 25000 900000>,
+ <1 825 20000 66000>,
+ /* 25 MB/s */
+ <150 10073 50000 76000>,
+ <135 512 50000 900000>,
+ <1 825 30000 66000>,
+ /* 50 MB/s */
+ <150 10073 50000 76000>,
+ <135 512 80000 900000>,
+ <1 825 40000 66000>,
+ /* 100 MB/s */
+ <150 10073 50000 76000>,
+ <135 512 100000 900000>,
+ <1 825 50000 66000>,
+ /* 200 MB/s */
+ <150 10073 50000 76000>,
+ <150 512 150000 900000>,
+ <1 825 80000 76000>,
+ /* 400 MB/s */
+ <150 10073 261438 2300000>,
+ <135 512 261438 4700000>,
+ <1 825 300000 300000>,
+ /* Max. bandwidth */
+ <150 10073 1338562 4096000>,
+ <135 512 1338562 4096000>,
+ <1 825 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100750000 200000000 400000000 4294967295>;
+
+ /* PM QoS */
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <67 67>;
+ qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
+ qcom,pm-qos-cmdq-latency-us = <67 67>, <67 67>;
+ qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface_clk", "core_clk", "ice_core_clk";
+
+ qcom,ice-clk-rates = <300000000 100000000>;
+
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x2c010800 0x80040868>;
+
+ qcom,nonremovable;
+ status = "disabled";
+ };
+
+ sdhc_2: sdhci@8804000 {
+ compatible = "qcom,sdhci-msm-v5";
+ reg = <0x8804000 0x1000>;
+ reg-names = "hc_mem";
+
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <4>;
+ qcom,large-address-bus;
+
+ qcom,clk-rates = <400000 20000000 25000000
+ 50000000 100000000 202000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
+ "SDR104";
+
+ qcom,devfreq,freq-table = <50000000 202000000>;
+
+ qcom,msm-bus,name = "sdhc2";
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <81 10073 0 0>,
+ <135 512 0 0>,
+ <1 825 0 0>,
+ /* 400 KB/s*/
+ <81 10073 1000 7600>,
+ <135 512 1000 90000>,
+ <1 825 2000 6600>,
+ /* 20 MB/s */
+ <81 10073 25000 76000>,
+ <135 512 25000 900000>,
+ <1 825 20000 66000>,
+ /* 25 MB/s */
+ <81 10073 50000 76000>,
+ <135 512 50000 900000>,
+ <1 825 30000 66000>,
+ /* 50 MB/s */
+ <81 10073 50000 76000>,
+ <135 512 80000 900000>,
+ <1 825 40000 66000>,
+ /* 100 MB/s */
+ <81 10073 50000 76000>,
+ <135 512 100000 900000>,
+ <1 825 50000 66000>,
+ /* 200 MB/s */
+ <81 10073 261438 2300000>,
+ <135 512 261438 4700000>,
+ <1 825 300000 300000>,
+ /* Max. bandwidth */
+ <81 10073 1338562 4096000>,
+ <135 512 1338562 4096000>,
+ <1 825 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100750000 200000000 400000000 4294967295>;
+
+ /* PM QoS */
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <67 67>;
+ qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
+ qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>;
+ clock-names = "iface_clk", "core_clk";
+
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2c010800 0x80040868>;
+
+ status = "disabled";
+ };
+
+ apps_rsc: rsc@18200000 {
+ label = "apps_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x18200000 0x10000>,
+ <0x18210000 0x10000>,
+ <0x18220000 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 3>,
+ <WAKE_TCS 3>,
+ <CONTROL_TCS 1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ system_pm {
+ compatible = "qcom,system-pm";
+ };
+
+ rpmhcc: qcom,rpmhclk {
+ compatible = "qcom,lito-rpmh-clk";
+ #clock-cells = <1>;
+ };
+
+ msm_bus_apps_rsc {
+ compatible = "qcom,msm-bus-rsc";
+ qcom,msm-bus-id = <MSM_BUS_RSC_APPS>;
+ };
+
+ ufsphy_mem: ufsphy_mem@1d87000 {
+ reg = <0x1d87000 0xe00>, <0x1d90000 0x8000>;
+ reg-names = "phy_mem", "ufs_ice";
+ #phy-cells = <0>;
+
+ lanes-per-direction = <2>;
+ qcom,rpmh-resource-name = "qphy.lvl";
+
+ clock-names = "ref_clk_src",
+ "ref_clk",
+ "ref_aux_clk";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_1X_CLKREF_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ };
+ };
+
+ disp_rsc: rsc@af20000 {
+ label = "disp_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0xaf20000 0x10000>;
+ reg-names = "drv-0";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0x1c00>;
+ qcom,drv-id = <0>;
+ qcom,tcs-config = <ACTIVE_TCS 0>,
+ <SLEEP_TCS 1>,
+ <WAKE_TCS 1>,
+ <CONTROL_TCS 0>;
+
+ msm_bus_disp_rsc {
+ compatible = "qcom,msm-bus-rsc";
+ qcom,msm-bus-id = <MSM_BUS_RSC_DISP>;
+ };
+
+ sde_rsc_rpmh {
+ compatible = "qcom,sde-rsc-rpmh";
+ cell-index = <0>;
+ };
+
+ };
+
+ qcom,rmtfs_sharedmem@0 {
+ compatible = "qcom,sharedmem-uio";
+ reg = <0x0 0x280000>;
+ reg-names = "rmtfs";
+ qcom,client-id = <0x00000001>;
+ };
+
+ ipcc_mproc: qcom,ipcc@408000 {
+ compatible = "qcom,ipcc";
+ reg = <0x408000 0x1000>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #mbox-cells = <2>;
+ };
+
+ llcc: cache-controller@9200000 {
+ compatible = "qcom,llcc-v1";
+ reg = <0x9200000 0xd0000> , <0x9600000 0x50000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ cap-based-alloc-and-pwr-collapse;
+
+ LLCC_1: llcc_1_dcache {
+ qcom,dump-size = <0x1141c0>;
+ };
+
+ LLCC_2: llcc_2_dcache {
+ qcom,dump-size = <0x1141c0>;
+ };
+ };
+
+ cpu_pmu: cpu-pmu {
+ compatible = "arm,armv8-pmuv3";
+ qcom,irq-is-percpu;
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ qcom_msmhdcp: qcom,msm_hdcp {
+ compatible = "qcom,msm-hdcp";
+ };
+
+ mem_dump {
+ compatible = "qcom,mem-dump";
+ memory-region = <&dump_mem>;
+
+ c0_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x0>;
+ };
+
+ c100_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x1>;
+ };
+
+ c200_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x2>;
+ };
+
+ c300_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x3>;
+ };
+
+ c400_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x4>;
+ };
+
+ c500_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x5>;
+ };
+
+ c600_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x6>;
+ };
+
+ c700_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x7>;
+ };
+
+ c0_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x130>;
+ };
+
+ c100_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x131>;
+ };
+
+ c200_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x132>;
+ };
+
+ c300_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x133>;
+ };
+
+ c400_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x134>;
+ };
+
+ c500_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x135>;
+ };
+
+ c600_scandump {
+ qcom,dump-size = <0x25900>;
+ qcom,dump-id = <0x136>;
+ };
+
+ c700_scandump {
+ qcom,dump-size = <0x25900>;
+ qcom,dump-id = <0x137>;
+ };
+
+ l1_i_cache0 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x60>;
+ };
+
+ l1_icache100 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x61>;
+ };
+
+ l1_icache200 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x62>;
+ };
+
+ l1_icache300 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x63>;
+ };
+
+ l1_icache400 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x64>;
+ };
+
+ l1_icache500 {
+ qcom,dump-size = <0x10800>;
+ qcom,dump-id = <0x65>;
+ };
+
+ l1_icache600 {
+ qcom,dump-size = <0x21000>;
+ qcom,dump-id = <0x66>;
+ };
+
+ l1_icache700 {
+ qcom,dump-size = <0x21000>;
+ qcom,dump-id = <0x67>;
+ };
+
+ l1_dcache0 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x80>;
+ };
+
+ l1_dcache100 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x81>;
+ };
+
+ l1_dcache200 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x82>;
+ };
+
+ l1_dcache300 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x83>;
+ };
+
+ l1_dcache400 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x84>;
+ };
+
+ l1_dcache500 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x85>;
+ };
+
+ l1_dcache600 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x86>;
+ };
+
+ l1_dcache700 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x87>;
+ };
+
+ l1_itlb600 {
+ qcom,dump-size = <0x300>;
+ qcom,dump-id = <0x26>;
+ };
+
+ l1_itlb700 {
+ qcom,dump-size = <0x300>;
+ qcom,dump-id = <0x27>;
+ };
+
+ l1_dtlb600 {
+ qcom,dump-size = <0x480>;
+ qcom,dump-id = <0x46>;
+ };
+
+ l1_dtlb700 {
+ qcom,dump-size = <0x480>;
+ qcom,dump-id = <0x47>;
+ };
+
+ l2_cache600 {
+ qcom,dump-size = <0x48000>;
+ qcom,dump-id = <0xc6>;
+ };
+
+ l2_cache700 {
+ qcom,dump-size = <0x48000>;
+ qcom,dump-id = <0xc7>;
+ };
+
+ l2_tlb0 {
+ qcom,dump-size = <0x5a00>;
+ qcom,dump-id = <0x120>;
+ };
+
+ l2_tlb100 {
+ qcom,dump-size = <0x5a00>;
+ qcom,dump-id = <0x121>;
+ };
+
+ l2_tlb200 {
+ qcom,dump-size = <0x5a00>;
+ qcom,dump-id = <0x122>;
+ };
+
+ l2_tlb300 {
+ qcom,dump-size = <0x5a00>;
+ qcom,dump-id = <0x123>;
+ };
+
+ l2_tlb400 {
+ qcom,dump-size = <0x5a00>;
+ qcom,dump-id = <0x124>;
+ };
+
+ l2_tlb500 {
+ qcom,dump-size = <0x5a00>;
+ qcom,dump-id = <0x125>;
+ };
+
+ l2_tlb600 {
+ qcom,dump-size = <0x7800>;
+ qcom,dump-id = <0x126>;
+ };
+
+ l2_tlb700 {
+ qcom,dump-size = <0x7800>;
+ qcom,dump-id = <0x127>;
+ };
+
+ llcc1_d_cache {
+ qcom,dump-size = <0x1141c0>;
+ qcom,dump-id = <0x140>;
+ };
+
+ llcc2_d_cache {
+ qcom,dump-size = <0x1141c0>;
+ qcom,dump-id = <0x141>;
+ };
+
+ rpmh {
+ qcom,dump-size = <0x2000000>;
+ qcom,dump-id = <0xec>;
+ };
+
+ rpm_sw {
+ qcom,dump-size = <0x28000>;
+ qcom,dump-id = <0xea>;
+ };
+
+ pmic {
+ qcom,dump-size = <0x80000>;
+ qcom,dump-id = <0xe4>;
+ };
+
+ fcm {
+ qcom,dump-size = <0x8400>;
+ qcom,dump-id = <0xee>;
+ };
+
+ etf_swao {
+ qcom,dump-size = <0x10000>;
+ qcom,dump-id = <0xf1>;
+ };
+
+ etr_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x100>;
+ };
+
+ etfswao_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x102>;
+ };
+
+ misc_data {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xe8>;
+ };
+
+ ipa {
+ qcom,dump-size = <0x11000>;
+ qcom,dump-id = <0x150>;
+ };
+
+ etf_slpi {
+ qcom,dump-size = <0x4000>;
+ qcom,dump-id = <0xf3>;
+ };
+
+ etfslpi_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x103>;
+ };
+
+ etf_lpass {
+ qcom,dump-size = <0x4000>;
+ qcom,dump-id = <0xf4>;
+ };
+
+ etflpass_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x104>;
+ };
+
+ clk_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x163>;
+ };
+
+ osm_reg {
+ qcom,dump-size = <0x400>;
+ qcom,dump-id = <0x163>;
+ };
+
+ pcu_reg {
+ qcom,dump-size = <0x400>;
+ qcom,dump-id = <0x164>;
+ };
+
+ fsm_data {
+ qcom,dump-size = <0x400>;
+ qcom,dump-id = <0x165>;
+ };
+ };
+
+ qcom,chd_silver {
+ compatible = "qcom,core-hang-detect";
+ label = "silver";
+ qcom,threshold-arr = <0x18000058 0x18010058
+ 0x18020058 0x18030058
+ 0x18040058 0x18050058>;
+ qcom,config-arr = <0x18000060 0x18010060
+ 0x18020060 0x18030060
+ 0x18040060 0x18050060>;
+ };
+
+ qcom,chd_gold {
+ compatible = "qcom,core-hang-detect";
+ label = "gold";
+ qcom,threshold-arr = <0x18060058 0x18070058>;
+ qcom,config-arr = <0x18060060 0x18070060>;
+ };
+
+ kryo-erp {
+ compatible = "arm,arm64-kryo-cpu-erp";
+ interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "l1-l2-faultirq",
+ "l3-scu-faultirq";
+ };
+
+ tcsr_mutex_block: syscon@1f40000 {
+ compatible = "syscon";
+ reg = <0x1f40000 0x20000>;
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_block 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ smem: qcom,smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ qcom,glink {
+ compatible = "qcom,glink";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ glink_modem: modem {
+ qcom,remote-pid = <1>;
+ transport = "smem";
+ mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "modem_smem";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_MPSS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ label = "modem";
+ qcom,glink-label = "mpss";
+
+ qcom,modem_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,low-latency;
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,modem_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_adsp>,
+ <&glink_cdsp>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,modem_ds {
+ qcom,glink-channels = "DS";
+ qcom,intents = <0x4000 0x2>;
+ };
+ };
+
+ glink_adsp: adsp {
+ qcom,remote-pid = <2>;
+ transport = "smem";
+ mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "adsp_smem";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ label = "adsp";
+ qcom,glink-label = "lpass";
+
+ qcom,adsp_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,low-latency;
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,apr_tal_rpmsg {
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,intents = <0x200 20>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,adsp_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_cdsp>;
+ };
+ };
+
+ glink_cdsp: cdsp {
+ qcom,remote-pid = <5>;
+ transport = "smem";
+ mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "dsps_smem";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ label = "cdsp";
+ qcom,glink-label = "cdsp";
+
+ qcom,cdsp_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,msm_cdsprm_rpmsg {
+ compatible = "qcom,msm-cdsprm-rpmsg";
+ qcom,glink-channels = "cdsprmglink-apps-dsp";
+ qcom,intents = <0x20 12>;
+
+ qcom,cdsp-cdsp-l3-gov {
+ compatible = "qcom,cdsp-l3";
+ qcom,target-dev = <&cdsp_l3>;
+ };
+
+ msm_cdsp_rm: qcom,msm_cdsp_rm {
+ compatible = "qcom,msm-cdsp-rm";
+ qcom,qos-latency-us = <44>;
+ qcom,qos-maxhold-ms = <20>;
+ qcom,compute-cx-limit-en;
+ qcom,compute-priority-mode = <2>;
+ #cooling-cells = <2>;
+ };
+
+ msm_hvx_rm: qcom,msm_hvx_rm {
+ compatible = "qcom,msm-hvx-rm";
+ #cooling-cells = <2>;
+ };
+ };
+
+ qcom,cdsp_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_adsp>,
+ <&glink_npu>;
+ };
+ };
+
+ glink_npu: npu {
+ qcom,remote-pid = <10>;
+ transport = "smem";
+ mboxes = <&msm_npu IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "npu_smem";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_NPU
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ label = "npu";
+ qcom,glink-label = "npu";
+
+ qcom,npu_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,npu_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_adsp>,
+ <&glink_cdsp>;
+ };
+ };
+ };
+
+ qcom,glinkpkt {
+ compatible = "qcom,glinkpkt";
+
+ qcom,glinkpkt-at-mdm0 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DS";
+ qcom,glinkpkt-dev-name = "at_mdm0";
+ };
+
+ qcom,glinkpkt-apr-apps2 {
+ qcom,glinkpkt-edge = "adsp";
+ qcom,glinkpkt-ch-name = "apr_apps2";
+ qcom,glinkpkt-dev-name = "apr_apps2";
+ };
+
+ qcom,glinkpkt-data40-cntl {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA40_CNTL";
+ qcom,glinkpkt-dev-name = "smdcntl8";
+ };
+
+ qcom,glinkpkt-data1 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA1";
+ qcom,glinkpkt-dev-name = "smd7";
+ };
+
+ qcom,glinkpkt-data4 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA4";
+ qcom,glinkpkt-dev-name = "smd8";
+ };
+
+ qcom,glinkpkt-data11 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA11";
+ qcom,glinkpkt-dev-name = "smd11";
+ };
+ };
+
+ qmp_aop: qcom,qmp-aop@c300000 {
+ compatible = "qcom,qmp-mbox";
+ reg = <0xc300000 0x1000>;
+ reg-names = "msgram";
+ mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+ mbox-names = "aop_qmp";
+ interrupt-parent = <&ipcc_mproc>;
+ interrupts = <IPCC_CLIENT_AOP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+
+ label = "aop";
+ qcom,early-boot;
+ priority = <0>;
+ mbox-desc-offset = <0x0>;
+ #mbox-cells = <1>;
+ };
+
+ aop-msg-client {
+ compatible = "qcom,debugfs-qmp-client";
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "aop";
+ };
+
+ pil_modem: qcom,mss@4080000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x4080000 0x100>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+ vdd_mss-supply = <&VDD_MSS_LEVEL>;
+ qcom,vdd_mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+ qcom,proxy-reg-names = "vdd_cx", "vdd_mss";
+
+ qcom,firmware-name = "modem";
+ memory-region = <&modem_wlan_mem>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,sysmon-id = <0>;
+ qcom,ssctl-instance-id = <0x12>;
+ qcom,pas-id = <4>;
+ qcom,smem-id = <421>;
+ qcom,minidump-id = <3>;
+ qcom,aux-minidump-ids = <4>;
+ qcom,signal-aop;
+ qcom,complete-ramdump;
+
+ qcom,msm-bus,name = "pil-modem";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <129 512 0 0>,
+ <129 512 0 8171520>;
+
+ /* Inputs from mss */
+ interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
+ <&mpss_smp2p_in 0 IRQ_TYPE_NONE>,
+ <&mpss_smp2p_in 1 IRQ_TYPE_NONE>,
+ <&mpss_smp2p_in 2 IRQ_TYPE_NONE>,
+ <&mpss_smp2p_in 3 IRQ_TYPE_NONE>,
+ <&mpss_smp2p_in 7 IRQ_TYPE_NONE>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,err-ready",
+ "qcom,proxy-unvote",
+ "qcom,stop-ack",
+ "qcom,shutdown-ack";
+
+ /* Outputs to mss */
+ qcom,smem-states = <&mpss_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "mss-pil";
+ };
+
+ qcom,lpass@3000000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x3000000 0x00100>;
+
+ vdd_lpi_cx-supply = <&L18A_LEVEL>;
+ qcom,vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ vdd_lpi_mx-supply = <&L4A_LEVEL>;
+ qcom,vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+
+ qcom,pas-id = <1>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <423>;
+ qcom,minidump-id = <5>;
+ qcom,sysmon-id = <1>;
+ qcom,ssctl-instance-id = <0x14>;
+ qcom,firmware-name = "adsp";
+ memory-region = <&pil_adsp_mem>;
+ qcom,signal-aop;
+ qcom,complete-ramdump;
+ qcom,minidump-as-elf32;
+
+ /* Inputs from lpass */
+ interrupts-extended = <&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
+ <&adsp_smp2p_in 0 0>,
+ <&adsp_smp2p_in 1 0>,
+ <&adsp_smp2p_in 2 0>,
+ <&adsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,err-ready",
+ "qcom,proxy-unvote",
+ "qcom,stop-ack";
+
+ /* Outputs to lpass */
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "adsp-pil";
+ };
+
+ qcom,turing@8300000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x8300000 0x100000>;
+
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,proxy-reg-names = "vdd_cx";
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+
+ qcom,pas-id = <18>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <601>;
+ qcom,minidump-id = <7>;
+ qcom,sysmon-id = <7>;
+ qcom,ssctl-instance-id = <0x17>;
+ qcom,firmware-name = "cdsp";
+ memory-region = <&pil_cdsp_mem>;
+ qcom,complete-ramdump;
+ qcom,signal-aop;
+ qcom,minidump-as-elf32;
+
+ qcom,msm-bus,name = "pil-cdsp";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <154 821 0 0>,
+ <154 821 0 1>;
+
+ /* Inputs from turing */
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
+ <&cdsp_smp2p_in 0 0>,
+ <&cdsp_smp2p_in 2 0>,
+ <&cdsp_smp2p_in 1 0>,
+ <&cdsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack";
+
+ /* Outputs to turing */
+ qcom,smem-states = <&cdsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ mboxes = <&qmp_aop 0>;
+ mbox-names = "cdsp-pil";
+ };
+
+ qcom,smp2p_sleepstate {
+ compatible = "qcom,smp2p-sleepstate";
+ qcom,smem-states = <&sleepstate_smp2p_out 0>;
+ interrupt-parent = <&sleepstate_smp2p_in>;
+ interrupts = <0 0>;
+ interrupt-names = "smp2p-sleepstate-in";
+ };
+
+ qcom,msm-cdsp-loader {
+ compatible = "qcom,cdsp-loader";
+ qcom,proc-img-to-load = "cdsp";
+ };
+
+ qcom,msm-adsprpc-mem {
+ compatible = "qcom,msm-adsprpc-mem-region";
+ status = "ok";
+ memory-region = <&adsp_mem>;
+ restrict-access;
+ };
+
+ msm_fastrpc: qcom,msm_fastrpc {
+ compatible = "qcom,msm-fastrpc-compute";
+ status = "ok";
+ qcom,adsp-remoteheap-vmid = <22 37>;
+ qcom,fastrpc-adsp-audio-pdr;
+ qcom,fastrpc-adsp-sensors-pdr;
+ qcom,rpc-latency-us = <235>;
+ qcom,qos-cores = <0 1 2 3 4 5>;
+
+ qcom,msm_fastrpc_compute_cb1 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1801 0x0440>,
+ <&apps_smmu 0x1821 0x0400>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb2 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1802 0x0440>,
+ <&apps_smmu 0x1822 0x0400>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb3 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1803 0x0440>,
+ <&apps_smmu 0x1823 0x0400>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb4 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1804 0x0440>,
+ <&apps_smmu 0x1824 0x0400>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb5 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1805 0x0440>,
+ <&apps_smmu 0x1825 0x0400>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb6 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1806 0x0460>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb7 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1807 0x0440>,
+ <&apps_smmu 0x1827 0x0400>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb8 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&apps_smmu 0x1808 0x0440>,
+ <&apps_smmu 0x1828 0x0400>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb9 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ qcom,secure-context-bank;
+ iommus = <&apps_smmu 0x1809 0x0460>;
+ qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb10 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x1403 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb11 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x1404 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb12 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x1405 0x0>;
+ shared-cb = <5>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ dma-coherent;
+ };
+ };
+
+ qcom,venus@aae0000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0xaae0000 0x4000>;
+
+ vdd-supply = <&mvsc_gdsc>;
+ qcom,proxy-reg-names = "vdd";
+
+ clocks = <&videocc VIDEO_CC_XO_CLK>,
+ <&videocc VIDEO_CC_MVSC_CORE_CLK>;
+ clock-names = "xo", "core";
+ qcom,proxy-clock-names = "xo", "core";
+
+ qcom,core-freq = <240000000>;
+ qcom,ahb-freq = <240000000>;
+
+ qcom,pas-id = <9>;
+ qcom,msm-bus,name = "pil-venus";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <63 512 0 0>,
+ <63 512 0 304000>;
+ qcom,proxy-timeout-ms = <100>;
+ qcom,firmware-name = "venus";
+ memory-region = <&pil_video_mem>;
+ };
+
+ gpi_dma0: qcom,gpi-dma@800000 {
+ #dma-cells = <5>;
+ compatible = "qcom,gpi-dma";
+ reg = <0x800000 0x60000>;
+ reg-names = "gpi-top";
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,max-num-gpii = <10>;
+ qcom,gpii-mask = <0x1f>;
+ qcom,ev-factor = <2>;
+ qcom,gpi-ee-offset = <0x10000>;
+ iommus = <&apps_smmu 0x4f6 0x0>;
+ qcom,smmu-cfg = <0x1>;
+ qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+ status = "ok";
+ };
+
+ gpi_dma1: qcom,gpi-dma@900000 {
+ #dma-cells = <5>;
+ compatible = "qcom,gpi-dma";
+ reg = <0x900000 0x60000>;
+ reg-names = "gpi-top";
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,max-num-gpii = <10>;
+ qcom,gpii-mask = <0x3f>;
+ qcom,ev-factor = <2>;
+ qcom,gpi-ee-offset = <0x10000>;
+ iommus = <&apps_smmu 0x36 0x0>;
+ qcom,smmu-cfg = <0x1>;
+ qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+ status = "ok";
+ };
+
+ eud: qcom,msm-eud@88e0000 {
+ compatible = "qcom,msm-eud";
+ interrupt-names = "eud_irq";
+ interrupt-parent = <&pdc>;
+ interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x088e0000 0x2000>,
+ <0x088e2000 0x1000>;
+ reg-names = "eud_base", "eud_mode_mgr2";
+ qcom,secure-eud-en;
+ qcom,eud-clock-vote-req;
+ clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_BCR>;
+ clock-names = "eud_ahb2phy_clk";
+ status = "ok";
+ };
+
+ llcc_pmu: llcc-pmu@90cc000 {
+ compatible = "qcom,llcc-pmu-ver1";
+ reg = <0x090cc000 0x300>;
+ reg-names = "lagg-base";
+ };
+
+ llcc_bw_opp_table: llcc-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
+ BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
+ BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
+ BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
+ BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
+ BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
+ BW_OPP_ENTRY(1066, 16); /* 16265 MB/s */
+ };
+
+ suspendable_llcc_bw_opp_table: suspendable-llcc-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 0, 16); /* 0 MB/s */
+ BW_OPP_ENTRY( 150, 16); /* 2288 MB/s */
+ BW_OPP_ENTRY( 300, 16); /* 4577 MB/s */
+ BW_OPP_ENTRY( 466, 16); /* 7110 MB/s */
+ BW_OPP_ENTRY( 600, 16); /* 9155 MB/s */
+ BW_OPP_ENTRY( 806, 16); /* 12298 MB/s */
+ BW_OPP_ENTRY( 933, 16); /* 14236 MB/s */
+ BW_OPP_ENTRY(1066, 16); /* 16265 MB/s */
+ };
+
+ cpu_cpu_llcc_bw: qcom,cpu-cpu-llcc-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;
+ qcom,active-only;
+ operating-points-v2 = <&llcc_bw_opp_table>;
+ };
+
+ cpu_cpu_llcc_bwmon: qcom,cpu-cpu-llcc-bwmon@90b6400 {
+ compatible = "qcom,bimc-bwmon4";
+ reg = <0x90B6300 0x300>, <0x090B6200 0x200>;
+ reg-names = "base", "global_base";
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&cpu_cpu_llcc_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ ddr_bw_opp_table: ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 200, 4); /* 762 MB/s */
+ BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */
+ BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */
+ BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */
+ BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */
+ BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */
+ BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */
+ BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */
+ BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */
+ BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */
+ BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */
+ };
+
+ cpu_llcc_ddr_bw: qcom,cpu-llcc-ddr-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu_llcc_ddr_bwmon: qcom,cpu-llcc-ddr-bwmon@90cd000 {
+ compatible = "qcom,bimc-bwmon5";
+ reg = <0x90cd000 0x1000>;
+ reg-names = "base";
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&cpu_llcc_ddr_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 0, 4); /* 0 MB/s */
+ BW_OPP_ENTRY( 200, 4); /* 762 MB/s */
+ BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */
+ BW_OPP_ENTRY( 451, 4); /* 1720 MB/s */
+ BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */
+ BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */
+ BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */
+ BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */
+ BW_OPP_ENTRY(1353, 4); /* 5161 MB/s */
+ BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */
+ BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */
+ BW_OPP_ENTRY(2092, 4); /* 7980 MB/s */
+ };
+
+ npu_npu_llcc_bw: qcom,npu-npu-llcc-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_LLCC>;
+ operating-points-v2 = <&suspendable_llcc_bw_opp_table>;
+ };
+
+ npu_npu_llcc_bwmon: qcom,npu-npu-llcc-bwmon@9960300 {
+ compatible = "qcom,bimc-bwmon4";
+ reg = <0x00060400 0x300>, <0x00060300 0x200>;
+ reg-names = "base", "global_base";
+ clocks = <&gcc GCC_NPU_BWMON_CFG_AHB_CLK>,
+ <&gcc GCC_NPU_BWMON_AXI_CLK>,
+ <&gcc GCC_NPU_BWMON2_AXI_CLK>;
+ clock-names = "npu_bwmon_ahb", "npu_bwmon_axi",
+ "npu_bwmon2_axi";
+ qcom,bwmon_clks = "npu_bwmon_ahb", "npu_bwmon_axi",
+ "npu_bwmon2_axi";
+ qcom,msm_bus = <154 512>;
+ qcom,msm_bus_name = "npu_bwmon_cdsp";
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&npu_npu_llcc_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ npu_llcc_ddr_bw: qcom,npu-llcc-ddr-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports = <MSM_BUS_SLAVE_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
+ };
+
+ npu_llcc_ddr_bwmon: qcom,npu-llcc-ddr-bwmon@90CE000 {
+ compatible = "qcom,bimc-bwmon5";
+ reg = <0x90CE000 0x1000>;
+ reg-names = "base";
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&npu_llcc_ddr_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ npudsp_npu_ddr_bw: qcom,npudsp-npu-ddr-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports = <MSM_BUS_MASTER_NPU MSM_BUS_SLAVE_EBI_CH0>;
+ operating-points-v2 = <&suspendable_ddr_bw_opp_table>;
+ };
+
+ npudsp_npu_ddr_bwmon: qcom,npudsp-npu-ddr-bwmon@70200 {
+ compatible = "qcom,bimc-bwmon4";
+ reg = <0x00070300 0x300>, <0x00070200 0x200>;
+ reg-names = "base", "global_base";
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_NPU_BWMON_CFG_AHB_CLK>,
+ <&gcc GCC_NPU_BWMON_AXI_CLK>,
+ <&gcc GCC_NPU_BWMON2_AXI_CLK>;
+ clock-names = "npu_bwmon_ahb", "npu_bwmon_axi",
+ "npu_bwmon2_axi";
+ qcom,bwmon_clks = "npu_bwmon_ahb", "npu_bwmon_axi",
+ "npu_bwmon2_axi";
+ qcom,msm_bus = <154 512>;
+ qcom,msm_bus_name = "npu_bwmon_cdsp";
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&npudsp_npu_ddr_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ cpu0_cpu_llcc_lat: qcom,cpu0-cpu-llcc-lat {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;
+ qcom,active-only;
+ operating-points-v2 = <&llcc_bw_opp_table>;
+ };
+
+ cpu0_llcc_ddr_lat: qcom,cpu0-llcc-ddr-lat {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
+
+ cpu0_cpu_l3_latmon: qcom,cpu0-cpu-l3-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
+ qcom,target-dev = <&cpu0_l3>;
+ qcom,cachemiss-ev = <0x17>;
+ qcom,core-dev-table =
+ < 672000 300000000 >,
+ < 940800 556800000 >,
+ < 1228800 806400000 >,
+ < 1459200 940800000 >,
+ < 1728000 1420000000 >;
+ };
+
+ cpu0_cpu_llcc_latmon: qcom,cpu0-cpu-llcc-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
+ qcom,target-dev = <&cpu0_cpu_llcc_lat>;
+ qcom,cachemiss-ev = <0x2A>;
+ qcom,core-dev-table =
+ < 1228800 MHZ_TO_MBPS(300, 16) >,
+ < 1459200 MHZ_TO_MBPS(466, 16) >,
+ < 1728000 MHZ_TO_MBPS(600, 16) >;
+ };
+
+ cpu0_llcc_ddr_latmon: qcom,cpu0-llcc-ddr-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
+ qcom,target-dev = <&cpu0_llcc_ddr_lat>;
+ qcom,cachemiss-ev = <0x1000>;
+ qcom,core-dev-table =
+ < 672000 MHZ_TO_MBPS( 300, 4) >,
+ < 940800 MHZ_TO_MBPS( 451, 4) >,
+ < 1228800 MHZ_TO_MBPS( 547, 4) >,
+ < 1459200 MHZ_TO_MBPS( 768, 4) >,
+ < 1728000 MHZ_TO_MBPS(1017, 4) >;
+ };
+
+ cpu0_computemon: qcom,cpu0-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
+ qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 672000 MHZ_TO_MBPS( 300, 4) >,
+ < 1228800 MHZ_TO_MBPS( 451, 4) >,
+ < 1459200 MHZ_TO_MBPS( 547, 4) >,
+ < 1728000 MHZ_TO_MBPS( 768, 4) >;
+ };
+ };
+
+ cpu6_cpu_llcc_lat: qcom,cpu6-cpu-llcc-lat {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_LLCC>;
+ qcom,active-only;
+ operating-points-v2 = <&llcc_bw_opp_table>;
+ };
+
+ cpu6_llcc_ddr_lat: qcom,cpu6-llcc-ddr-lat {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu6_cpu_ddr_latfloor: qcom,cpu6-cpu-ddr-latfloor {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu7_cpu_ddr_latfloor: qcom,cpu7-cpu-ddr-latfloor {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU6 &CPU7>;
+
+ cpu6_cpu_l3_latmon: qcom,cpu6-cpu-l3-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU6>;
+ qcom,target-dev = <&cpu6_l3>;
+ qcom,cachemiss-ev = <0x17>;
+ qcom,core-dev-table =
+ < 940800 556800000 >,
+ < 1228800 806400000 >,
+ < 1708800 1190400000 >,
+ < 1900800 1382400000 >,
+ < 2323200 1420000000 >;
+ };
+
+ cpu7_cpu_l3_latmon: qcom,cpu7-cpu-l3-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU7>;
+ qcom,target-dev = <&cpu7_l3>;
+ qcom,cachemiss-ev = <0x17>;
+ qcom,core-dev-table =
+ < 940800 556800000 >,
+ < 1228800 806400000 >,
+ < 1708800 1190400000 >,
+ < 1900800 1382400000 >,
+ < 2323200 1420000000 >;
+ };
+
+ cpu6_cpu_llcc_latmon: qcom,cpu6-cpu-llcc-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU6 &CPU7>;
+ qcom,target-dev = <&cpu6_cpu_llcc_lat>;
+ qcom,cachemiss-ev = <0x2A>;
+ qcom,core-dev-table =
+ < 672000 MHZ_TO_MBPS( 300, 16) >,
+ < 940800 MHZ_TO_MBPS( 466, 16) >,
+ < 1228000 MHZ_TO_MBPS( 600, 16) >,
+ < 1708800 MHZ_TO_MBPS( 806, 16) >,
+ < 2350000 MHZ_TO_MBPS( 933, 16) >,
+ < 3000000 MHZ_TO_MBPS(1066, 16) >;
+ };
+
+ cpu6_llcc_ddr_latmon: qcom,cpu6-llcc-ddr-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU6 &CPU7>;
+ qcom,target-dev = <&cpu6_llcc_ddr_lat>;
+ qcom,cachemiss-ev = <0x1000>;
+ qcom,core-dev-table =
+ < 672000 MHZ_TO_MBPS( 451, 4) >,
+ < 940800 MHZ_TO_MBPS( 547, 4) >,
+ < 1228000 MHZ_TO_MBPS(1017, 4) >,
+ < 1708800 MHZ_TO_MBPS(1555, 4) >,
+ < 2350000 MHZ_TO_MBPS(1804, 4) >,
+ < 3000000 MHZ_TO_MBPS(2092, 4) >;
+ };
+
+ cpu6_computemon: qcom,cpu6-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU6>;
+ qcom,target-dev = <&cpu6_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 672000 MHZ_TO_MBPS( 300, 4) >,
+ < 1228800 MHZ_TO_MBPS( 547, 4) >,
+ < 1516800 MHZ_TO_MBPS( 768, 4) >,
+ < 1708800 MHZ_TO_MBPS(1017, 4) >,
+ < 2350000 MHZ_TO_MBPS(1804, 4) >,
+ < 3000000 MHZ_TO_MBPS(2092, 4) >;
+ };
+
+ cpu7_computemon: qcom,cpu7-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU7>;
+ qcom,target-dev = <&cpu7_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 672000 MHZ_TO_MBPS( 300, 4) >,
+ < 1228800 MHZ_TO_MBPS( 547, 4) >,
+ < 1516800 MHZ_TO_MBPS( 768, 4) >,
+ < 1708800 MHZ_TO_MBPS(1017, 4) >,
+ < 2350000 MHZ_TO_MBPS(1804, 4) >,
+ < 3000000 MHZ_TO_MBPS(2092, 4) >;
+ };
+ };
+
+ qcom,msm_gsi {
+ compatible = "qcom,msm_gsi";
+ };
+
+ qcom,rmnet-ipa {
+ compatible = "qcom,rmnet-ipa3";
+ qcom,rmnet-ipa-ssr;
+ qcom,ipa-platform-type-msm;
+ qcom,ipa-advertise-sg-support;
+ qcom,ipa-napi-enable;
+ };
+
+ qcom,ipa_fws {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <0xf>;
+ qcom,firmware-name = "ipa_fws";
+ qcom,pil-force-shutdown;
+ memory-region = <&pil_ipa_fw_mem>;
+ };
+
+ ipa_hw: qcom,ipa@1e00000 {
+ compatible = "qcom,ipa";
+ reg = <0x1e00000 0x84000>,
+ <0x1e04000 0x23000>;
+ reg-names = "ipa-base", "gsi-base";
+ interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ipa-irq", "gsi-irq";
+ qcom,ipa-hw-ver = <18>; /* IPA core version = IPAv4.7 */
+ qcom,ipa-hw-mode = <0>;
+ qcom,platform-type = <1>; /* MSM platform */
+ qcom,ee = <0>;
+ qcom,use-ipa-tethering-bridge;
+ qcom,modem-cfg-emb-pipe-flt;
+ qcom,ipa-wdi2;
+ qcom,ipa-wdi2_over_gsi;
+ qcom,use-ipa-pm;
+ qcom,arm-smmu;
+ qcom,smmu-fast-map;
+ qcom,bandwidth-vote-for-ipa;
+ qcom,ipa-endp-delay-wa;
+ qcom,use-64-bit-dma-mask;
+ qcom,msm-bus,name = "ipa";
+ qcom,wan-use-skb-page;
+ qcom,msm-bus,num-cases = <5>;
+ qcom,msm-bus,num-paths = <5>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 0 0>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 0>,
+
+ /* SVS2 */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 150000 500000>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 150000 700000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 75000 700000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 76800>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 100>,
+
+ /* SVS */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 625000 1200000>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 625000 1100000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 312500 1500000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 150000>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 150>,
+
+ /* NOMINAL */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 1250000 2400000>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 1250000 1800000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 625000 3100000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 400000>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 450>,
+
+ /* TURBO */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_LLCC 2000000 3500000>,
+ <MSM_BUS_MASTER_LLCC MSM_BUS_SLAVE_EBI_CH0 2000000 2000000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 1000000 4100000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 400000>,
+ <MSM_BUS_MASTER_IPA_CORE MSM_BUS_SLAVE_IPA_CORE 0 550>;
+
+
+ qcom,bus-vector-names =
+ "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
+ qcom,throughput-threshold = <310 600 1000>;
+ qcom,scaling-exceptions = <>;
+
+ /* smp2p information */
+ qcom,smp2p_map_ipa_1_out {
+ compatible = "qcom,smp2p-map-ipa-1-out";
+ qcom,smem-states = <&smp2p_ipa_1_out 0>;
+ qcom,smem-state-names = "ipa-smp2p-out";
+ };
+
+ qcom,smp2p_map_ipa_1_in {
+ compatible = "qcom,smp2p-map-ipa-1-in";
+ interrupts-extended = <&smp2p_ipa_1_in 0 0>;
+ interrupt-names = "ipa-smp2p-in";
+ };
+ };
+
+ ipa_smmu_ap: ipa_smmu_ap {
+ compatible = "qcom,ipa-smmu-ap-cb";
+ iommus = <&apps_smmu 0x0520 0x0>;
+ qcom,iommu-dma-addr-pool = <0x20000000 0x40000000>;
+ /* modem tables in IMEM */
+ qcom,additional-mapping = <0x146a9000 0x146a9000 0x2000>;
+ qcom,iommu-dma = "fastmap";
+ qcom,ipa-q6-smem-size = <26624>;
+ };
+
+ ipa_smmu_wlan: ipa_smmu_wlan {
+ compatible = "qcom,ipa-smmu-wlan-cb";
+ iommus = <&apps_smmu 0x0521 0x0>;
+ /* ipa-uc ram */
+ qcom,additional-mapping = <0x1ea0000 0x1ea0000 0x80000>;
+ qcom,iommu-dma = "fastmap";
+ };
+
+ ipa_smmu_uc: ipa_smmu_uc {
+ compatible = "qcom,ipa-smmu-uc-cb";
+ iommus = <&apps_smmu 0x0522 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0x20000000>;
+ qcom,iommu-dma = "fastmap";
+ };
+
+ icnss: qcom,icnss@18800000 {
+ compatible = "qcom,icnss";
+ reg = <0x18800000 0x800000>,
+ <0xb0000000 0x10000>;
+ reg-names = "membase", "smmu_iova_ipa";
+ iommus = <&apps_smmu 0xC0 0x1>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
+ <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
+ <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
+ <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
+ <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH /* CE10 */ >,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH /* CE11 */ >;
+ qcom,wlan-msa-fixed-region = <&pil_wlan_fw_mem>;
+ qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
+ qcom,iommu-dma = "fastmap";
+ qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
+ vdd-cx-mx-supply = <&L1A>;
+ vdd-1.8-xo-supply = <&L14A>;
+ vdd-1.3-rfa-supply = <&L2C>;
+ vdd-3.3-ch1-supply = <&L11C>;
+ vdd-3.3-ch0-supply = <&L10C>;
+ qcom,vdd-cx-mx-config = <0 0>;
+ qcom,vdd-3.3-ch1-config = <3000000 3312000>;
+ qcom,vdd-3.3-ch0-config = <3000000 3312000>;
+ qcom,smp2p_map_wlan_1_in {
+ interrupts-extended = <&smp2p_wlan_1_in 0 0>,
+ <&smp2p_wlan_1_in 1 0>;
+ interrupt-names = "qcom,smp2p-force-fatal-error",
+ "qcom,smp2p-early-crash-ind";
+ };
+ };
+
+ qcom,npu@9800000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x9800000 0x800000>;
+ status = "ok";
+ qcom,pas-id = <23>;
+ qcom,firmware-name = "npu";
+ memory-region = <&pil_npu_mem>;
+
+ /* Outputs to npu */
+ qcom,smem-states = <&npu_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+ };
+
+ qfprom: qfprom@780000 {
+ compatible = "qcom,qfprom";
+ reg = <0x00780000 0x7000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ read-only;
+ ranges;
+
+ gpu_speed_bin: gpu_speed_bin@1ea {
+ reg = <0x1ea 0x2>;
+ bits = <5 8>;
+ };
+
+ gpu_gaming_bin: gpu_gaming_bin@212 {
+ reg = <0x212 0x1>;
+ bits = <0 1>;
+ };
+
+ gpu_lm_efuse: gpu_lm_efuse@45c8 {
+ reg = <0x45c8 0x4>;
+ };
+
+ adsp_variant: adsp_variant@210 {
+ reg = <0x213 0x1>;
+ bits = <1 2>;
+ };
+
+ iris_efuse: iris@6008 {
+ reg = <0x6008 0x4>;
+ };
+
+ npu_efuse: npu@6010 {
+ reg = <0x6010 0x4>;
+ };
+
+ feat_conf10: feat_conf10@602c {
+ reg = <0x602c 0x4>;
+ };
+
+ stm_debug_fuse: stm@20f0 {
+ reg = <0x20f0 0x4>;
+ };
+ };
+
+ qcom,demux {
+ compatible = "qcom,demux";
+ };
+};
+
+#include "lito-pinctrl.dtsi"
+#include "lito-pm.dtsi"
+#include "lito-gdsc.dtsi"
+#include "msm-arm-smmu-lito.dtsi"
+#include "lito-regulators.dtsi"
+#include "lito-smp2p.dtsi"
+#include "lito-usb.dtsi"
+#include "lito-ion.dtsi"
+#include "lito-vidc.dtsi"
+#include "lito-bus.dtsi"
+#include "lito-gpu.dtsi"
+#include "lito-thermal.dtsi"
+#include "lito-npu.dtsi"
+#include "msm-rdbg.dtsi"
+#include "ipcc-test-lito.dtsi"
+
+&ufs_phy_gdsc {
+ status = "ok";
+};
+
+&usb30_prim_gdsc {
+ status = "ok";
+ qcom,retain-regs;
+};
+
+&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
+ status = "ok";
+};
+
+&bps_gdsc {
+ clock-names = "ahb_clk";
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&ipe_0_gdsc {
+ clock-names = "ahb_clk";
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&ipe_1_gdsc {
+ clock-names = "ahb_clk";
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&ife_0_gdsc {
+ clock-names = "ahb_clk";
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+ status = "ok";
+};
+
+&ife_1_gdsc {
+ clock-names = "ahb_clk";
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+ status = "ok";
+};
+
+&titan_top_gdsc {
+ clock-names = "ahb_clk";
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>;
+ status = "ok";
+};
+
+&mdss_core_gdsc {
+ clock-names = "ahb_clk";
+ clocks = <&gcc GCC_DISP_AHB_CLK>;
+ status = "ok";
+};
+
+&gpu_cx_gdsc {
+ parent-supply = <&VDD_CX_LEVEL>;
+ vdd_parent-supply = <&VDD_CX_LEVEL>;
+ status = "ok";
+};
+
+&gpu_gx_gdsc {
+ parent-supply = <&VDD_GFX_LEVEL>;
+ vdd_parent-supply = <&VDD_GFX_LEVEL>;
+ status = "ok";
+};
+
+&npu_core_gdsc {
+ status = "ok";
+ qcom,retain-regs;
+};
+
+&mvsc_gdsc {
+ clock-names = "ahb_clk";
+ clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+ status = "ok";
+};
+
+&mvs0_gdsc {
+ clock-names = "ahb_clk";
+ clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&mvs1_gdsc {
+ clock-names = "ahb_clk";
+ clocks = <&gcc GCC_VIDEO_AHB_CLK>;
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+#include "lito-qupv3.dtsi"
+#include "lito-coresight.dtsi"
+#include "camera/lito-camera.dtsi"
+#include "lito-audio.dtsi"
+
+&qupv3_se9_i2c {
+ status = "ok";
+ #include "pm8008.dtsi"
+};
+
+&qupv3_se2_2uart {
+ status = "ok";
+};
+
+&qupv3_se5_4uart {
+ status = "ok";
+};
+
+&pm8008_8 {
+ /* PM8008 IRQ STAT */
+ interrupt-parent = <&tlmm>;
+ interrupts = <45 IRQ_TYPE_EDGE_RISING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm8008_active &pm8008_interrupt>;
+};
+
+&pm8008_regulators {
+ vdd_l1_l2-supply = <&S8C>;
+ vdd_l3_l4-supply = <&BOB>;
+ vdd_l5-supply = <&BOB>;
+ vdd_l6-supply = <&S5A>;
+ vdd_l7-supply = <&S5A>;
+};
+
+&L1P {
+ regulator-max-microvolt = <1056000>;
+ /* Reduced the headroom by 16mV for AHC */
+ qcom,min-dropout-voltage = <209000>;
+};
+
+&L2P {
+ regulator-max-microvolt = <1104000>;
+ /* Reduced the headroom by 16mV for AHC */
+ qcom,min-dropout-voltage = <209000>;
+};
+
+&L3P {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ qcom,min-dropout-voltage = <136000>;
+};
+
+&L4P {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2904000>;
+ qcom,min-dropout-voltage = <160000>;
+};
+
+&L5P {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ qcom,min-dropout-voltage = <300000>;
+};
+
+&L6P {
+ regulator-max-microvolt = <1800000>;
+ qcom,min-dropout-voltage = <184000>;
+};
+
+&L7P {
+ regulator-max-microvolt = <1800000>;
+ qcom,min-dropout-voltage = <200000>;
+};
+#include "lito-sde.dtsi"
+#include "lito-sde-pll.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/litomagnus-cdp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/litomagnus-cdp-overlay.dts
new file mode 100755
index 0000000..9924e3b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/litomagnus-cdp-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "litomagnus-cdp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Litomagnus CDP";
+ compatible = "qcom,lito-cdp", "qcom,lito", "qcom,cdp";
+ qcom,msm-id = <400 0x20000>, <440 0x20000>;
+ qcom,board-id = <1 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/litomagnus-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/litomagnus-cdp.dts
new file mode 100755
index 0000000..0ec6b8a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/litomagnus-cdp.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+#include "litomagnus.dtsi"
+#include "litomagnus-cdp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Litomagnus CDP";
+ compatible = "qcom,lito-cdp", "qcom,lito", "qcom,cdp";
+ qcom,board-id = <1 1>;
+};
+
+&ufsphy_mem {
+ /delete-property/ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/litomagnus-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/litomagnus-cdp.dtsi
new file mode 100755
index 0000000..4282166
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/litomagnus-cdp.dtsi
@@ -0,0 +1,77 @@
+#include "lito-cdp.dtsi"
+
+&soc {
+
+};
+
+&usb_qmp_dp_phy {
+ /delete-property/vdd-supply;
+ vdd-supply = <&L11A>;
+};
+
+&sde_dp {
+ vdda-0p9-supply = <&L11A>;
+};
+
+&swr0 {
+ wsa883x_0221: wsa883x@02170221 {
+ compatible = "qcom,wsa883x";
+ reg = <0x02 0x02170221>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+ qcom,bolero-handle = <&bolero>;
+ cdc-vdd-1p8-supply = <&S4A>;
+
+ qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-1p8-current = <20000>;
+ qcom,cdc-vdd-1p8-lpm-supported = <1>;
+ qcom,cdc-static-supplies = "cdc-vdd-1p8";
+ };
+
+ wsa883x_0222: wsa883x@02170222 {
+ compatible = "qcom,wsa883x";
+ reg = <0x02 0x02170222>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero>;
+
+ cdc-vdd-1p8-supply = <&S4A>;
+ qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-1p8-current = <20000>;
+ qcom,cdc-vdd-1p8-lpm-supported = <1>;
+ qcom,cdc-static-supplies = "cdc-vdd-1p8";
+ };
+};
+
+&wsa881x_0211 {
+ status = "disabled";
+};
+
+&wsa881x_0212 {
+ status = "disabled";
+};
+
+&wsa881x_0213 {
+ status = "disabled";
+};
+
+&wsa881x_0214 {
+ status = "disabled";
+};
+
+&lito_snd {
+ qcom,model = "lito-orchidmtp-snd-card";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa883x_0221>, <&wsa883x_0222>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight";
+};
+
+&pm8150_rtc {
+ status = "disabled";
+};
+
+&pmk8350_adc_tm {
+ status = "disabled";
+};
+
+&pmk8350_vadc {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/litomagnus-mtp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/litomagnus-mtp-overlay.dts
new file mode 100755
index 0000000..4bce619
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/litomagnus-mtp-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "litomagnus-mtp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Litomagnus MTP";
+ compatible = "qcom,lito-mtp", "qcom,lito", "qcom,mtp";
+ qcom,msm-id = <400 0x20000>, <440 0x20000>;
+ qcom,board-id = <8 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/litomagnus-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/litomagnus-mtp.dts
new file mode 100755
index 0000000..0cc277c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/litomagnus-mtp.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+#include "litomagnus.dtsi"
+#include "litomagnus-mtp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Litomagnus MTP";
+ compatible = "qcom,lito-mtp", "qcom,lito", "qcom,mtp";
+ qcom,board-id = <8 1>;
+};
+
+&ufsphy_mem {
+ /delete-property/ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/litomagnus-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/litomagnus-mtp.dtsi
new file mode 100755
index 0000000..f0b383d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/litomagnus-mtp.dtsi
@@ -0,0 +1,133 @@
+#include "lito-mtp.dtsi"
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&soc {
+
+};
+
+&usb_qmp_dp_phy {
+ /delete-property/vdd-supply;
+ vdd-supply = <&L11A>;
+};
+
+&sde_dp {
+ vdda-0p9-supply = <&L11A>;
+};
+
+&swr0 {
+ wsa883x_0221: wsa883x@02170221 {
+ compatible = "qcom,wsa883x";
+ reg = <0x02 0x02170221>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+ qcom,bolero-handle = <&bolero>;
+
+ cdc-vdd-1p8-supply = <&S4A>;
+ qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-1p8-current = <20000>;
+ qcom,cdc-vdd-1p8-lpm-supported = <1>;
+ qcom,cdc-static-supplies = "cdc-vdd-1p8";
+ };
+
+ wsa883x_0222: wsa883x@02170222 {
+ compatible = "qcom,wsa883x";
+ reg = <0x02 0x02170222>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero>;
+
+ cdc-vdd-1p8-supply = <&S4A>;
+ qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-1p8-current = <20000>;
+ qcom,cdc-vdd-1p8-lpm-supported = <1>;
+ qcom,cdc-static-supplies = "cdc-vdd-1p8";
+ };
+};
+
+&wsa881x_0211 {
+ status = "disabled";
+};
+
+&wsa881x_0212 {
+ status = "disabled";
+};
+
+&wsa881x_0213 {
+ status = "disabled";
+};
+
+&wsa881x_0214 {
+ status = "disabled";
+};
+
+&lito_snd {
+ qcom,model = "lito-orchidmtp-snd-card";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa883x_0221>, <&wsa883x_0222>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight";
+};
+
+&pm8150_rtc {
+ status = "disabled";
+};
+
+&pmk8350_adc_tm {
+ status = "disabled";
+};
+
+&pmk8350_vadc {
+ status = "disabled";
+};
+
+&pm7250b_qg {
+ qcom,use-cp-iin-sns;
+};
+
+&pm7250b_vadc {
+ smb1390_therm@e {
+ qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_SMB1398_TEMP>;
+ };
+};
+
+&pm7250b_gpios {
+ smb_stat {
+ smb_stat_default: smb_stat_default {
+ pins = "gpio6";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+ power-source = <0>;
+ };
+ };
+};
+
+&qupv3_se9_i2c {
+ qcom,clk-freq-out = <100000>;
+ status = "ok";
+ #include "smb1398.dtsi"
+};
+
+&smb1396 {
+ interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&spmi_bus>;
+ interrupt-names = "smb1396";
+ pinctrl-names = "default";
+ qcom,enable-toggle-stat;
+ pinctrl-0 = <&smb_stat_default>;
+ status = "ok";
+};
+
+&smb1396_div2_cp_master {
+ io-channels = <&pm7250b_vadc ADC_AMUX_THM2>;
+ qcom,parallel-input-mode = <1>; /* USBIN */
+ qcom,parallel-output-mode = <2>; /* VBAT */
+ qcom,min-ilim-ua = <1000000>;
+ status = "ok";
+};
+
+&smb1396_slave {
+ status = "ok";
+};
+
+&smb1396_div2_cp_slave {
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/litomagnus.dts b/arch/arm64/boot/dts/vendor/qcom/litomagnus.dts
new file mode 100755
index 0000000..1b02677
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/litomagnus.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "litomagnus.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Litomagnus SoC";
+ compatible = "qcom,lito";
+ qcom,board-id = <0 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/litomagnus.dtsi b/arch/arm64/boot/dts/vendor/qcom/litomagnus.dtsi
new file mode 100755
index 0000000..a2798f5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/litomagnus.dtsi
@@ -0,0 +1,12 @@
+#include "lito-v2.dtsi"
+#include "pmk8350.dtsi"
+#include "magnus.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Litomagnus";
+ compatible = "qcom,lito";
+};
+
+&llcc {
+ compatible = "qcom,llcc-v2";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/magnus.dtsi b/arch/arm64/boot/dts/vendor/qcom/magnus.dtsi
new file mode 100755
index 0000000..5c0f3f1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/magnus.dtsi
@@ -0,0 +1,12 @@
+&pm8008_regulators {
+ vdd_l6-supply = <&BOB>;
+};
+
+&rpmhcc {
+ compatible = "qcom,litomagnus-rpmh-clk";
+ #clock-cells = <1>;
+};
+
+&apps_rsc {
+ /delete-node/ rpmh-regulator-ldoa7;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-660.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-660.dtsi
new file mode 100755
index 0000000..7bdd448
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-660.dtsi
@@ -0,0 +1,205 @@
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+ anoc2_smmu: arm,smmu-anoc2@16c0000 {
+ compatible = "qcom,smmu-v2";
+ reg = <0x16c0000 0x40000>;
+ #iommu-cells = <1>;
+ qcom,skip-init;
+ qcom,use-3-lvl-tables;
+ qcom,regulator-names = "vdd";
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_rpmcc AGGR2_NOC_SMMU_CLK>;
+ clock-names = "smmu_aggr2_noc_clk";
+ #clock-cells = <1>;
+ };
+
+ lpass_q6_smmu: arm,smmu-lpass_q6@5100000 {
+ compatible = "qcom,smmu-v2";
+ reg = <0x5100000 0x40000>;
+ #iommu-cells = <1>;
+ qcom,skip-init;
+ qcom,use-3-lvl-tables;
+ qcom,regulator-names = "vdd";
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
+ vdd-supply = <&gdsc_hlos1_vote_lpass_adsp>;
+ clocks = <&clock_gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
+ clock-names = "lpass_q6_smmu_clk";
+ #clock-cells = <1>;
+ };
+
+ mmss_bimc_smmu: arm,smmu-mmss@cd00000 {
+ compatible = "qcom,smmu-v2";
+ reg = <0xcd00000 0x40000>;
+ #iommu-cells = <1>;
+ qcom,skip-init;
+ qcom,use-3-lvl-tables;
+ qcom,regulator-names = "vdd";
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
+ vdd-supply = <&gdsc_bimc_smmu>;
+ clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
+ clock-names = "mmss_mnoc_ahb_clk",
+ "mmssnoc_axi_clk",
+ "mmss_bimc_smmu_ahb_clk",
+ "mmss_bimc_smmu_axi_clk";
+ #clock-cells = <1>;
+ qcom,bus-master-id = <MSM_BUS_MNOC_BIMC_MAS>;
+ };
+
+ kgsl_smmu: arm,smmu-kgsl@5040000 {
+ compatible = "qcom,smmu-v2";
+ reg = <0x5040000 0x10000>;
+ #iommu-cells = <1>;
+ qcom,dynamic;
+ qcom,use-3-lvl-tables;
+ qcom,disable-atos;
+ qcom,regulator-names = "vdd";
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,deferred-regulator-disable-delay = <80>;
+ vdd-supply = <&gdsc_gpu_cx>;
+ clocks = <&clock_gcc GCC_GPU_CFG_AHB_CLK>,
+ <&clock_gcc GCC_BIMC_GFX_CLK>,
+ <&clock_gcc GCC_GPU_BIMC_GFX_CLK>;
+ clock-names = "gcc_gpu_cfg_ahb_clk",
+ "gcc_bimc_gfx_clk",
+ "gcc_gpu_bimc_gfx_clk";
+ #clock-cells = <1>;
+ };
+
+ turing_q6_smmu: arm,smmu-turing_q6@5180000 {
+ compatible = "qcom,smmu-v2";
+ reg = <0x5180000 0x40000>;
+ #iommu-cells = <1>;
+ qcom,register-save;
+ qcom,skip-init;
+ qcom,regulator-names = "vdd";
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
+ vdd-supply = <&gdsc_hlos1_vote_turing_adsp>;
+ clocks = <&clock_gcc HLOS1_VOTE_TURING_ADSP_SMMU_CLK>;
+ clock-names = "turing_q6_smmu_clk";
+ #clock-cells = <1>;
+ };
+
+ iommu_test_device {
+ compatible = "iommu-debug-test";
+ /*
+ * 42 shouldn't be used by anyone on the mmss_smmu. We just
+ * need _something_ here to get this node recognized by the
+ * SMMU driver. Our test uses ATOS, which doesn't use SIDs
+ * anyways, so using a dummy value is ok.
+ */
+ iommus = <&mmss_bimc_smmu 42>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-8917.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-8917.dtsi
new file mode 100755
index 0000000..adea3a4
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-8917.dtsi
@@ -0,0 +1,81 @@
+&soc {
+ gfx_iommu: qcom,iommu@1f00000 {
+ status = "ok";
+ compatible = "qcom,qsmmu-v500";
+ reg = <0x1f00000 0x10000>,
+ <0x1ee2000 0x20>;
+ reg-names = "base", "tcu-base";
+ #iommu-cells = <1>;
+ qcom,tz-device-id = "GPU";
+ qcom,skip-init;
+ qcom,enable-static-cb;
+ qcom,dynamic;
+ qcom,use-3-lvl-tables;
+ qcom,regulator-names = "vdd";
+ #global-interrupts = <0>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_GFX_TCU_CLK>;
+ clock-names = "iface_clk", "core_clk";
+ };
+
+ apps_iommu: qcom,iommu@1e00000 {
+ status = "okay";
+ compatible = "qcom,qsmmu-v500";
+ reg = <0x1e00000 0x40000>,
+ <0x1ee2000 0x20>;
+ reg-names = "base", "tcu-base";
+ #iommu-cells = <2>;
+ qcom,tz-device-id = "APPS";
+ qcom,skip-init;
+ qcom,disable-atos;
+ ranges;
+ qcom,enable-static-cb;
+ qcom,use-3-lvl-tables;
+ qcom,regulator-names = "vdd";
+ #global-interrupts = <0>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_APSS_TCU_CLK>;
+ clock-names = "iface_clk", "core_clk";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-8937.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-8937.dtsi
new file mode 100755
index 0000000..0ca2104
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-8937.dtsi
@@ -0,0 +1,89 @@
+&soc {
+ kgsl_smmu: arm,smmu-kgsl@1c40000 {
+ status = "ok";
+ compatible = "qcom,smmu-v2";
+ qcom,tz-device-id = "GPU";
+ reg = <0x1c40000 0x10000>;
+ #iommu-cells = <1>;
+ #global-interrupts = <0>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,dynamic;
+ qcom,use-3-lvl-tables;
+ qcom,enable-smmu-halt;
+ qcom,skip-init;
+ vdd-supply = <&gdsc_oxili_cx>;
+ qcom,regulator-names = "vdd";
+ clocks = <&gcc GCC_OXILI_AHB_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>;
+ clock-names = "gpu_ahb_clk", "gcc_bimc_gfx_clk";
+ };
+
+ /* A test device to test the SMMU operation */
+ kgsl_iommu_test_device0 {
+ status = "disabled";
+ compatible = "iommu-debug-test";
+ /* The SID should be valid one to get the proper
+ *SMR,S2CR indices.
+ */
+ iommus = <&kgsl_smmu 0x0>;
+ };
+
+ apps_iommu: qcom,iommu@1e00000 {
+ status = "okay";
+ compatible = "qcom,qsmmu-v500";
+ reg = <0x1e00000 0x40000>,
+ <0x1ee2000 0x20>;
+ reg-names = "base", "tcu-base";
+ #iommu-cells = <2>;
+ qcom,tz-device-id = "APPS";
+ qcom,skip-init;
+ qcom,enable-static-cb;
+ qcom,use-3-lvl-tables;
+ qcom,disable-atos;
+ qcom,regulator-names = "vdd";
+ #global-interrupts = <0>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges;
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_APSS_TCU_CLK>;
+ clock-names = "iface_clk", "core_clk";
+ };
+};
+
+#include "msm-arm-smmu-impl-defs-8937.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-bengal.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-bengal.dtsi
new file mode 100755
index 0000000..4e352f8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-bengal.dtsi
@@ -0,0 +1,241 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ kgsl_smmu: kgsl-smmu@0x59a0000 {
+ status = "okay";
+ compatible = "qcom,qsmmu-v500";
+ reg = <0x59a0000 0x10000>,
+ <0x59c2000 0x20>;
+ reg-names = "base", "tcu-base";
+ #iommu-cells = <2>;
+ qcom,dynamic;
+ qcom,skip-init;
+ qcom,testbus-version = <1>;
+ qcom,no-dynamic-asid;
+ qcom,use-3-lvl-tables;
+ #global-interrupts = <1>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&gpu_cx_gdsc>;
+
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gcc_gpu_memnoc_gfx",
+ "gcc_gpu_snoc_dvm_gfx",
+ "gpu_cc_ahb",
+ "gpu_cc_hlos1_vote_gpu_smmu_clk";
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,actlr =
+ /* All CBs of GFX: +15 deep PF */
+ <0x0 0x3ff 0x30B>;
+
+ gfx_0_tbu: gfx_0_tbu@0x59c5000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x59c5000 0x1000>,
+ <0x59c2200 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x0 0x400>;
+ };
+ };
+
+ apps_smmu: apps-smmu@0xc600000 {
+ status = "okay";
+ compatible = "qcom,qsmmu-v500";
+ reg = <0xc600000 0x80000>,
+ <0xc782000 0x20>;
+ reg-names = "base", "tcu-base";
+ #iommu-cells = <2>;
+ qcom,skip-init;
+ qcom,use-3-lvl-tables;
+ #global-interrupts = <1>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 1000>;
+
+ qcom,actlr =
+ /* For rt TBU +3 deep PF */
+ <0x400 0x3ff 0x103>,
+ /* For nrt TBU +3 deep PF */
+ <0x800 0x3ff 0x103>;
+
+ anoc_1_tbu: anoc_1_tbu@0xc785000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0xc785000 0x1000>,
+ <0xc782200 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x0 0x400>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IMEM_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 1000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IMEM_CFG 0 1000>;
+
+ };
+
+ mm_rt_tbu: mm_rt_tbu@0xc789000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0xc789000 0x1000>,
+ <0xc782208 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x400 0x400>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 0>,
+ <MSM_BUS_MASTER_MDP_PORT0 MSM_BUS_SLAVE_SNOC_BIMC_RT 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 1000>,
+ <MSM_BUS_MASTER_MDP_PORT0 MSM_BUS_SLAVE_SNOC_BIMC_RT 0 1000>;
+ };
+
+ mm_nrt_tbu: mm_nrt_tbu@0xc78d000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0xc78d000 0x1000>,
+ <0xc782210 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x800 0x400>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_SF MSM_BUS_SLAVE_SNOC_BIMC_NRT 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 1000>,
+ <MSM_BUS_MASTER_CAMNOC_SF MSM_BUS_SLAVE_SNOC_BIMC_NRT 0 1000>;
+
+ };
+
+ cdsp_tbu: cdsp_tbu@0xc791000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0xc791000 0x1000>,
+ <0xc782218 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0xc00 0x400>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&hlos1_vote_turing_mmu_tbu0_gdsc>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 1000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0 0 1000>;
+ };
+ };
+
+ kgsl_iommu_test_device {
+ compatible = "iommu-debug-test";
+ qcom,iommu-dma = "disabled";
+ iommus = <&kgsl_smmu 0x7 0x0>;
+ };
+
+ apps_iommu_test_device {
+ compatible = "iommu-debug-test";
+ qcom,iommu-dma = "disabled";
+ iommus = <&apps_smmu 0x1e0 0>;
+ };
+
+ apps_iommu_coherent_test_device {
+ compatible = "iommu-debug-test";
+ qcom,iommu-dma = "disabled";
+ iommus = <&apps_smmu 0x1e1 0>;
+ dma-coherent;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-impl-defs-660.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-impl-defs-660.dtsi
new file mode 100755
index 0000000..532632b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-impl-defs-660.dtsi
@@ -0,0 +1,397 @@
+&kgsl_smmu {
+ attach-impl-defs = <0x6000 0x2378>,
+ <0x6060 0x1055>,
+ <0x678c 0x8>,
+ <0x6794 0x28>,
+ <0x6800 0x6>,
+ <0x6900 0x3ff>,
+ <0x6924 0x204>,
+ <0x6928 0x11000>,
+ <0x6930 0x800>,
+ <0x6960 0xffffffff>,
+ <0x6b64 0x1a5551>,
+ <0x6b68 0x9a82a382>;
+};
+
+&lpass_q6_smmu {
+ attach-impl-defs = <0x6000 0x2378>,
+ <0x6060 0x1055>,
+ <0x6070 0xe0>,
+ <0x6074 0xe0>,
+ <0x6078 0xe0>,
+ <0x607c 0xe0>,
+ <0x60f0 0xc0>,
+ <0x60f4 0xc8>,
+ <0x60f8 0xd0>,
+ <0x60fc 0xd8>,
+ <0x6170 0x0>,
+ <0x6174 0x30>,
+ <0x6178 0x60>,
+ <0x617c 0x90>,
+ <0x6270 0x0>,
+ <0x6274 0x2>,
+ <0x6278 0x4>,
+ <0x627c 0x6>,
+ <0x62f0 0x8>,
+ <0x62f4 0xe>,
+ <0x62f8 0x14>,
+ <0x62fc 0x1a>,
+ <0x6370 0x20>,
+ <0x6374 0x40>,
+ <0x6378 0x60>,
+ <0x637c 0x80>,
+ <0x6784 0x0>,
+ <0x678c 0x10>,
+ <0x67a0 0x0>,
+ <0x67a4 0x0>,
+ <0x67a8 0x20>,
+ <0x67b0 0x0>,
+ <0x67b4 0x8>,
+ <0x67b8 0xc8>,
+ <0x67d0 0x4>,
+ <0x67dc 0x8>,
+ <0x67e0 0x8>,
+ <0x6800 0x6>,
+ <0x6900 0x3ff>,
+ <0x6924 0x202>,
+ <0x6928 0x10a00>,
+ <0x6930 0x500>,
+ <0x6960 0xffffffff>,
+ <0x6b64 0x121151>,
+ <0x6b68 0xea800080>,
+ <0x6c00 0x0>,
+ <0x6c04 0x0>,
+ <0x6c08 0x0>,
+ <0x6c0c 0x0>,
+ <0x6c10 0x1>,
+ <0x6c14 0x1>,
+ <0x6c18 0x1>,
+ <0x6c1c 0x1>,
+ <0x6c20 0x2>,
+ <0x6c24 0x2>,
+ <0x6c28 0x2>,
+ <0x6c2c 0x2>,
+ <0x6c30 0x3>,
+ <0x6c34 0x3>,
+ <0x6c38 0x3>,
+ <0x6c3c 0x3>;
+};
+
+&turing_q6_smmu {
+ attach-impl-defs = <0x6000 0x2378>,
+ <0x6060 0x1055>,
+ <0x6070 0xe0>,
+ <0x6074 0xe0>,
+ <0x6078 0xe0>,
+ <0x607c 0xe0>,
+ <0x60f0 0xc0>,
+ <0x60f4 0xc8>,
+ <0x60f8 0xd0>,
+ <0x60fc 0xd8>,
+ <0x6170 0x0>,
+ <0x6174 0x30>,
+ <0x6178 0x60>,
+ <0x617c 0x90>,
+ <0x6270 0x0>,
+ <0x6274 0x2>,
+ <0x6278 0x4>,
+ <0x627c 0x6>,
+ <0x62f0 0x8>,
+ <0x62f4 0xe>,
+ <0x62f8 0x14>,
+ <0x62fc 0x1a>,
+ <0x6370 0x20>,
+ <0x6374 0x40>,
+ <0x6378 0x60>,
+ <0x637c 0x80>,
+ <0x6784 0x0>,
+ <0x678c 0x10>,
+ <0x67a0 0x0>,
+ <0x67a4 0x0>,
+ <0x67a8 0x20>,
+ <0x67b0 0x0>,
+ <0x67b4 0x8>,
+ <0x67b8 0xc8>,
+ <0x67d0 0x4>,
+ <0x67dc 0x8>,
+ <0x67e0 0x8>,
+ <0x6800 0x6>,
+ <0x6900 0x3ff>,
+ <0x6924 0x202>,
+ <0x6928 0x10a00>,
+ <0x6930 0x500>,
+ <0x6960 0xffffffff>,
+ <0x6b64 0x121151>,
+ <0x6b68 0xea800080>,
+ <0x6c00 0x0>,
+ <0x6c04 0x0>,
+ <0x6c08 0x0>,
+ <0x6c0c 0x0>,
+ <0x6c10 0x1>,
+ <0x6c14 0x1>,
+ <0x6c18 0x1>,
+ <0x6c1c 0x1>,
+ <0x6c20 0x2>,
+ <0x6c24 0x2>,
+ <0x6c28 0x2>,
+ <0x6c2c 0x2>,
+ <0x6c30 0x3>,
+ <0x6c34 0x3>,
+ <0x6c38 0x3>,
+ <0x6c3c 0x3>;
+};
+
+&mmss_bimc_smmu {
+ attach-impl-defs = <0x6000 0x2378>,
+ <0x6060 0x1055>,
+ <0x678c 0x28>,
+ <0x6794 0xe0>,
+ <0x6800 0x6>,
+ <0x6900 0x3ff>,
+ <0x6924 0x204>,
+ <0x6928 0x11002>,
+ <0x6930 0x800>,
+ <0x6960 0xffffffff>,
+ <0x6964 0xffffffff>,
+ <0x6968 0xffffffff>,
+ <0x696c 0xffffffff>,
+ <0x6b48 0x330330>,
+ <0x6b4c 0x81>,
+ <0x6b50 0x3333>,
+ <0x6b54 0x3333>,
+ <0x6b64 0x1a5555>,
+ <0x6b68 0xbaaa892a>,
+ <0x6b70 0x10100202>,
+ <0x6b74 0x10100202>,
+ <0x6b78 0x10100000>,
+ <0x6b80 0x20042004>,
+ <0x6b84 0x20042004>;
+};
+
+&anoc2_smmu {
+ attach-impl-defs = <0x6000 0x2378>,
+ <0x6060 0x1055>,
+ <0x6070 0xf>,
+ <0x6074 0x23>,
+ <0x6078 0x37>,
+ <0x607c 0x39>,
+ <0x6080 0x3f>,
+ <0x6084 0x6f>,
+ <0x6088 0x74>,
+ <0x608c 0x92>,
+ <0x6090 0xb0>,
+ <0x6094 0xf0>,
+ <0x6098 0xf0>,
+ <0x609c 0xf0>,
+ <0x60f0 0x0>,
+ <0x60f4 0x1>,
+ <0x60f8 0x3>,
+ <0x60fc 0x4>,
+ <0x6100 0x6>,
+ <0x6104 0x8>,
+ <0x6108 0x9>,
+ <0x610c 0xb>,
+ <0x6110 0xd>,
+ <0x6114 0xf>,
+ <0x6118 0xf>,
+ <0x611c 0xf>,
+ <0x6170 0x0>,
+ <0x6174 0x0>,
+ <0x6178 0x0>,
+ <0x617c 0x0>,
+ <0x6180 0x0>,
+ <0x6184 0x0>,
+ <0x6188 0x0>,
+ <0x618c 0x0>,
+ <0x6190 0x0>,
+ <0x6194 0x0>,
+ <0x6198 0x0>,
+ <0x619c 0x0>,
+ <0x6270 0x0>,
+ <0x6274 0x1>,
+ <0x6278 0x2>,
+ <0x627c 0x4>,
+ <0x6280 0x4>,
+ <0x6284 0x6>,
+ <0x6288 0x6>,
+ <0x628c 0xa>,
+ <0x6290 0xc>,
+ <0x6294 0xc>,
+ <0x6298 0xc>,
+ <0x629c 0xc>,
+ <0x62f0 0xc>,
+ <0x62f4 0x12>,
+ <0x62f8 0x18>,
+ <0x62fc 0x1a>,
+ <0x6300 0x1d>,
+ <0x6304 0x23>,
+ <0x6308 0x24>,
+ <0x630c 0x28>,
+ <0x6310 0x2c>,
+ <0x6314 0x30>,
+ <0x6318 0x30>,
+ <0x631c 0x30>,
+ <0x6370 0x30>,
+ <0x6374 0x35>,
+ <0x6378 0x3a>,
+ <0x637c 0x3e>,
+ <0x6380 0x46>,
+ <0x6384 0x50>,
+ <0x6388 0x55>,
+ <0x638c 0x5d>,
+ <0x6390 0x67>,
+ <0x6394 0x80>,
+ <0x6398 0x80>,
+ <0x639c 0x80>,
+ <0x678c 0x12>,
+ <0x6794 0x32>,
+ <0x67a0 0x0>,
+ <0x67a4 0xe1>,
+ <0x67a8 0xf0>,
+ <0x67b0 0x0>,
+ <0x67b4 0xc>,
+ <0x67b8 0x9c>,
+ <0x67d0 0x0>,
+ <0x67dc 0x4>,
+ <0x67e0 0x8>,
+ <0x6800 0x6>,
+ <0x6900 0x3ff>,
+ <0x6b48 0x330330>,
+ <0x6b4c 0x81>,
+ <0x6b50 0x1313>,
+ <0x6b64 0x121155>,
+ <0x6b68 0xcaa84920>,
+ <0x6b70 0xc0c0000>,
+ <0x6b74 0x8080000>,
+ <0x6b78 0x8080000>,
+ <0x6b80 0x20002000>,
+ <0x6b84 0x20002000>,
+ <0x6c00 0x5>,
+ <0x6c04 0x0>,
+ <0x6c08 0x5>,
+ <0x6c0c 0x0>,
+ <0x6c10 0x5>,
+ <0x6c14 0x0>,
+ <0x6c18 0x5>,
+ <0x6c1c 0x0>,
+ <0x6c20 0x5>,
+ <0x6c24 0x0>,
+ <0x6c28 0x0>,
+ <0x6c2c 0x0>,
+ <0x6c30 0x0>,
+ <0x6c34 0x0>,
+ <0x6c38 0x0>,
+ <0x6c3c 0x0>,
+ <0x6c40 0x0>,
+ <0x6c44 0x0>,
+ <0x6c48 0x0>,
+ <0x6c4c 0x0>,
+ <0x6c50 0x0>,
+ <0x6c54 0x0>,
+ <0x6c58 0x0>,
+ <0x6c5c 0x0>,
+ <0x6c60 0x0>,
+ <0x6c64 0x0>,
+ <0x6c68 0x0>,
+ <0x6c6c 0x0>,
+ <0x6c70 0x0>,
+ <0x6c74 0x0>,
+ <0x6c78 0x0>,
+ <0x6c7c 0x0>,
+ <0x6c80 0x0>,
+ <0x6c84 0x0>,
+ <0x6c88 0x0>,
+ <0x6c8c 0x0>,
+ <0x6c90 0x0>,
+ <0x6c94 0x0>,
+ <0x6c98 0x0>,
+ <0x6c9c 0x0>,
+ <0x6ca0 0x0>,
+ <0x6ca4 0x0>,
+ <0x6ca8 0x0>,
+ <0x6cac 0x0>,
+ <0x6cb0 0x0>,
+ <0x6cb4 0x0>,
+ <0x6cb8 0x0>,
+ <0x6cbc 0x0>,
+ <0x6cc0 0x0>,
+ <0x6cc4 0x0>,
+ <0x6cc8 0x0>,
+ <0x6ccc 0x0>,
+ <0x6cd0 0x0>,
+ <0x6cd4 0x0>,
+ <0x6cd8 0x0>,
+ <0x6cdc 0x0>,
+ <0x6ce0 0x0>,
+ <0x6ce4 0x0>,
+ <0x6ce8 0x0>,
+ <0x6cec 0x0>,
+ <0x6cf0 0x0>,
+ <0x6cf4 0x0>,
+ <0x6cf8 0x0>,
+ <0x6cfc 0x0>,
+ <0x6d00 0x3>,
+ <0x6d04 0x4>,
+ <0x6d08 0x4>,
+ <0x6d0c 0x0>,
+ <0x6d10 0x8>,
+ <0x6d14 0x8>,
+ <0x6d18 0x3>,
+ <0x6d1c 0x2>,
+ <0x6d20 0x4>,
+ <0x6d24 0x0>,
+ <0x6d28 0x4>,
+ <0x6d2c 0x0>,
+ <0x6d30 0x7>,
+ <0x6d34 0x0>,
+ <0x6d38 0x6>,
+ <0x6d3c 0x0>,
+ <0x6d40 0x0>,
+ <0x6d44 0x1>,
+ <0x6d48 0x4>,
+ <0x6d4c 0x0>,
+ <0x6d50 0x4>,
+ <0x6d54 0x0>,
+ <0x6d58 0x4>,
+ <0x6d5c 0x0>,
+ <0x6d60 0x0>,
+ <0x6d64 0x0>,
+ <0x6d68 0x0>,
+ <0x6d6c 0x0>,
+ <0x6d70 0x0>,
+ <0x6d74 0x0>,
+ <0x6d78 0x0>,
+ <0x6d7c 0x0>,
+ <0x6d80 0x0>,
+ <0x6d84 0x0>,
+ <0x6d88 0x0>,
+ <0x6d8c 0x0>,
+ <0x6d90 0x0>,
+ <0x6d94 0x0>,
+ <0x6d98 0x0>,
+ <0x6d9c 0x0>,
+ <0x6da0 0x0>,
+ <0x6da4 0x0>,
+ <0x6da8 0x0>,
+ <0x6dac 0x0>,
+ <0x6db0 0x0>,
+ <0x6db4 0x0>,
+ <0x6db8 0x0>,
+ <0x6dbc 0x0>,
+ <0x6dc0 0x0>,
+ <0x6dc4 0x0>,
+ <0x6dc8 0x0>,
+ <0x6dcc 0x0>,
+ <0x6dd0 0x0>,
+ <0x6dd4 0x0>,
+ <0x6dd8 0x0>,
+ <0x6ddc 0x0>,
+ <0x6de0 0x0>,
+ <0x6de4 0x0>,
+ <0x6de8 0x0>,
+ <0x6dec 0x0>,
+ <0x6df0 0x0>,
+ <0x6df4 0x0>,
+ <0x6df8 0x0>,
+ <0x6dfc 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-impl-defs-8937.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-impl-defs-8937.dtsi
new file mode 100755
index 0000000..6ee2f98e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-impl-defs-8937.dtsi
@@ -0,0 +1,12 @@
+&kgsl_smmu {
+ attach-impl-defs = <0x6000 0x270>,
+ <0x6060 0x1055>,
+ <0x6800 0x6>,
+ <0x6900 0x3ff>,
+ <0x6924 0x204>,
+ <0x6928 0x10800>,
+ <0x6930 0x400>,
+ <0x6960 0xffffffff>,
+ <0x6b64 0xa0000>,
+ <0x6b68 0xaaab92a>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-kona.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-kona.dtsi
new file mode 100755
index 0000000..5ce2401
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-kona.dtsi
@@ -0,0 +1,439 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+ kgsl_smmu: kgsl-smmu@3da0000 {
+ compatible = "qcom,qsmmu-v500";
+ reg = <0x3DA0000 0x10000>,
+ <0x3DC2000 0x20>;
+ reg-names = "base", "tcu-base";
+ #iommu-cells = <2>;
+ qcom,skip-init;
+ qcom,use-3-lvl-tables;
+ qcom,no-dynamic-asid;
+ #global-interrupts = <2>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&gpu_cx_gdsc>;
+
+ clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&clock_gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&clock_gpucc GPU_CC_AHB_CLK>;
+ clock-names = "gcc_gpu_memnoc_gfx",
+ "gcc_gpu_snoc_dvm_gfx",
+ "gpu_cc_ahb";
+
+ interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
+
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GPU_TCU>,
+ <MSM_BUS_SLAVE_EBI_CH0>,
+ <0 0>,
+ <MSM_BUS_MASTER_GPU_TCU>,
+ <MSM_BUS_SLAVE_EBI_CH0>,
+ <0 1000>;
+
+ qcom,actlr =
+ /* All CBs of GFX: +15 deep PF */
+ <0x2 0x400 0x32B>,
+ <0x4 0x400 0x32B>,
+ <0x5 0x400 0x32B>,
+ <0x7 0x400 0x32B>,
+ <0x0 0x401 0x32B>;
+
+ gfx_0_tbu: gfx_0_tbu@3dc5000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x3DC5000 0x1000>,
+ <0x3DC2200 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x0 0x400>;
+ };
+
+ gfx_1_tbu: gfx_1_tbu@3dc9000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x3DC9000 0x1000>,
+ <0x3DC2208 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x400 0x400>;
+ };
+ };
+
+ apps_smmu: apps-smmu@15000000 {
+ compatible = "qcom,qsmmu-v500";
+ reg = <0x15000000 0x100000>,
+ <0x15182000 0x20>;
+ reg-names = "base", "tcu-base";
+ #iommu-cells = <2>;
+ qcom,skip-init;
+ qcom,use-3-lvl-tables;
+ #global-interrupts = <2>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 0>,
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 1000>;
+
+ qcom,actlr =
+ /* For HF-0 TBU +3 deep PF */
+ <0x800 0x3ff 0x103>,
+ /* For HF-1 TBU +3 deep PF */
+ <0xC00 0x3ff 0x103>,
+ /* For SF-0 TBU +3 deep PF */
+ <0x2000 0x3ff 0x103>,
+ /* For SF-1 TBU +3 deep PF */
+ <0x2400 0x3ff 0x103>,
+ /* For NPU +3 deep PF */
+ <0x1081 0x400 0x103>,
+ <0x1082 0x400 0x103>,
+ <0x1085 0x400 0x103>,
+ <0x10a1 0x400 0x103>,
+ <0x10a2 0x400 0x103>,
+ <0x10a5 0x400 0x103>;
+
+ anoc_1_tbu: anoc_1_tbu@15185000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15185000 0x1000>,
+ <0x15182200 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x0 0x400>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 0>,
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 1000>;
+ };
+
+ anoc_2_tbu: anoc_2_tbu@15189000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15189000 0x1000>,
+ <0x15182208 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x400 0x400>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 0>,
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 1000>;
+ };
+
+ mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518d000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x1518D000 0x1000>,
+ <0x15182210 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x800 0x400>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
+ qcom,msm-bus,name = "mnoc_hf_0_tbu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_MDP_PORT0>,
+ <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,
+ <0 0>,
+ <MSM_BUS_MASTER_MDP_PORT0>,
+ <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,
+ <0 1000>;
+ };
+
+ mnoc_hf_1_tbu: mnoc_hf_1_tbu@15191000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15191000 0x1000>,
+ <0x15182218 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0xc00 0x400>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
+ qcom,msm-bus,name = "mnoc_hf_1_tbu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_MDP_PORT0>,
+ <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,
+ <0 0>,
+ <MSM_BUS_MASTER_MDP_PORT0>,
+ <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,
+ <0 1000>;
+ };
+
+ compute_dsp_1_tbu: compute_dsp_1_tbu@15195000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15195000 0x1000>,
+ <0x15182220 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x1000 0x400>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_NPU>,
+ <MSM_BUS_SLAVE_CDSP_MEM_NOC>,
+ <0 0>,
+ <MSM_BUS_MASTER_NPU>,
+ <MSM_BUS_SLAVE_CDSP_MEM_NOC>,
+ <0 1000>;
+ };
+
+ compute_dsp_0_tbu: compute_dsp_0_tbu@15199000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15199000 0x1000>,
+ <0x15182228 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x1400 0x400>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_NPU>,
+ <MSM_BUS_SLAVE_CDSP_MEM_NOC>,
+ <0 0>,
+ <MSM_BUS_MASTER_NPU>,
+ <MSM_BUS_SLAVE_CDSP_MEM_NOC>,
+ <0 1000>;
+
+ };
+
+ adsp_tbu: adsp_tbu@1519d000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x1519D000 0x1000>,
+ <0x15182230 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x1800 0x400>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 0>,
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 1000>;
+ };
+
+ anoc_1_pcie_tbu: anoc_1_pcie_tbu@151a1000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x151A1000 0x1000>,
+ <0x15182238 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x1c00 0x400>;
+ clock-names = "gcc_aggre_noc_pcie_tbu_clk";
+ clocks = <&clock_gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 0>,
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 1000>;
+
+ };
+
+ mnoc_sf_0_tbu: mnoc_sf_0_tbu@151a5000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x151A5000 0x1000>,
+ <0x15182240 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x2000 0x400>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>;
+ qcom,msm-bus,name = "mnoc_sf_0_tbu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_SF>,
+ <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>,
+ <0 0>,
+ <MSM_BUS_MASTER_CAMNOC_SF>,
+ <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>,
+ <0 1000>;
+ };
+
+ mnoc_sf_1_tbu: mnoc_sf_1_tbu@151a9000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x151A9000 0x1000>,
+ <0x15182248 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x2400 0x400>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc>;
+ qcom,msm-bus,name = "mnoc_sf_1_tbu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_SF>,
+ <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>,
+ <0 0>,
+ <MSM_BUS_MASTER_CAMNOC_SF>,
+ <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>,
+ <0 1000>;
+ };
+ };
+
+ kgsl_iommu_test_device {
+ compatible = "iommu-debug-test";
+ iommus = <&kgsl_smmu 0x7 0>;
+ qcom,iommu-dma = "disabled";
+ };
+
+ kgsl_iommu_coherent_test_device {
+ status = "disabled";
+ compatible = "iommu-debug-test";
+ iommus = <&kgsl_smmu 0x9 0>;
+ qcom,iommu-dma = "disabled";
+ dma-coherent;
+ };
+
+ apps_iommu_test_device {
+ compatible = "iommu-debug-test";
+ iommus = <&apps_smmu 0x21 0>;
+ qcom,iommu-dma = "disabled";
+ };
+
+ apps_iommu_coherent_test_device {
+ compatible = "iommu-debug-test";
+ iommus = <&apps_smmu 0x23 0>;
+ qcom,iommu-dma = "disabled";
+ dma-coherent;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-lagoon.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-lagoon.dtsi
new file mode 100755
index 0000000..be474f7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-lagoon.dtsi
@@ -0,0 +1,319 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+ kgsl_smmu: arm,smmu-kgsl@3d40000 {
+ status = "ok";
+ compatible = "qcom,smmu-v2";
+ reg = <0x3d40000 0x10000>;
+ #iommu-cells = <1>;
+ qcom,use-3-lvl-tables;
+ qcom,no-dynamic-asid;
+ #global-interrupts = <2>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&gpu_cx_gdsc>;
+ clock-names = "gcc_gpu_memnoc_gfx_clk";
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ attach-impl-defs =
+ <0x6000 0x2378>,
+ <0x6060 0x1055>,
+ <0x678c 0x8>,
+ <0x6794 0x28>,
+ <0x6800 0x6>,
+ <0x6900 0x3ff>,
+ <0x6924 0x204>,
+ <0x6928 0x11000>,
+ <0x6930 0x800>,
+ <0x6960 0xffffffff>,
+ <0x6b64 0x1a5551>,
+ <0x6b68 0x9a82a382>;
+ };
+
+ apps_smmu: apps-smmu@15000000 {
+ compatible = "qcom,qsmmu-v500";
+ reg = <0x15000000 0x100000>,
+ <0x15182000 0x20>;
+ reg-names = "base", "tcu-base";
+ #iommu-cells = <2>;
+ qcom,skip-init;
+ qcom,use-3-lvl-tables;
+ #global-interrupts = <1>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
+
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 0>,
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 1000>;
+
+ qcom,actlr =
+ /* For HF-0 TBU +3 deep PF */
+ <0x800 0x3ff 0x103>,
+ /* For SF-0 TBU +3 deep PF */
+ <0xC00 0x3ff 0x103>,
+ /* For NPU +3 deep PF */
+ <0x1440 0x2f 0x103>,
+ <0x1480 0xf 0x103>;
+
+ anoc_1_tbu: anoc_1_tbu@15185000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15185000 0x1000>,
+ <0x15182200 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x0 0x400>;
+ interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 0>,
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 1000>;
+ };
+
+ anoc_2_tbu: anoc_2_tbu@15189000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15189000 0x1000>,
+ <0x15182208 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x400 0x400>;
+ interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 0>,
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 1000>;
+ };
+
+ mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518d000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x1518d000 0x1000>,
+ <0x15182210 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x800 0x400>;
+ interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
+ qcom,msm-bus,name = "mnoc_hf_0_tbu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_MDP_PORT0>,
+ <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,
+ <0 0>,
+ <MSM_BUS_MASTER_MDP_PORT0>,
+ <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,
+ <0 1000>;
+ };
+
+ mnoc_sf_0_tbu: mnoc_sf_0_tbu@15191000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15191000 0x1000>,
+ <0x15182218 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0xc00 0x400>;
+ interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc>;
+ qcom,msm-bus,name = "mnoc_sf_0_tbu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_SF>,
+ <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>,
+ <0 0>,
+ <MSM_BUS_MASTER_CAMNOC_SF>,
+ <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>,
+ <0 1000>;
+ };
+
+ adsp_tbu: adsp_tbu@15195000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15195000 0x1000>,
+ <0x15182220 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x1000 0x400>;
+ interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 0>,
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 1000>;
+ };
+
+ compute_dsp_0_tbu: compute_dsp_0_tbu@15199000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15199000 0x1000>,
+ <0x15182228 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x1400 0x400>;
+ interrupts = <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_NPU>,
+ <MSM_BUS_SLAVE_CDSP_GEM_NOC>,
+ <0 0>,
+ <MSM_BUS_MASTER_NPU>,
+ <MSM_BUS_SLAVE_CDSP_GEM_NOC>,
+ <0 1000>;
+ };
+
+ pcie_tbu: pcie_tbu@1519d000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x1519d000 0x1000>,
+ <0x15182230 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x1800 0x400>;
+ interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 0>,
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 1000>;
+ };
+ };
+
+ kgsl_iommu_test_device {
+ compatible = "iommu-debug-test";
+ qcom,iommu-dma = "disabled";
+ iommus = <&kgsl_smmu 0x7>;
+ };
+
+ apps_iommu_test_device {
+ compatible = "iommu-debug-test";
+ qcom,iommu-dma = "disabled";
+ iommus = <&apps_smmu 0x1 0>;
+ };
+
+ apps_iommu_coherent_test_device {
+ compatible = "iommu-debug-test";
+ qcom,iommu-dma = "disabled";
+ iommus = <&apps_smmu 0x3 0>;
+ dma-coherent;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-lito.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-lito.dtsi
new file mode 100755
index 0000000..7b0cc7d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-lito.dtsi
@@ -0,0 +1,384 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+ kgsl_smmu: kgsl-smmu@3da0000 {
+ compatible = "qcom,qsmmu-v500";
+ reg = <0x3da0000 0x10000>,
+ <0x3dc2000 0x20>;
+ reg-names = "base", "tcu-base";
+ #iommu-cells = <2>;
+ qcom,skip-init;
+ qcom,use-3-lvl-tables;
+ qcom,no-dynamic-asid;
+ #global-interrupts = <1>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&gpu_cx_gdsc>;
+
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gcc_gpu_memnoc_gfx",
+ "gcc_gpu_snoc_dvm_gfx",
+ "gpu_cc_ahb",
+ "gpu_cc_hlos1_vote_gpu_smmu_clk";
+
+ interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>;
+
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GPU_TCU>,
+ <MSM_BUS_SLAVE_EBI_CH0>,
+ <0 0>,
+ <MSM_BUS_MASTER_GPU_TCU>,
+ <MSM_BUS_SLAVE_EBI_CH0>,
+ <0 1000>;
+
+ qcom,actlr =
+ /* All CBs of GFX: +15 deep PF */
+ <0x0 0x3ff 0x32B>,
+ <0x400 0x3ff 0x32B>;
+
+ gfx_0_tbu: gfx_0_tbu@3dc5000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x3dc5000 0x1000>,
+ <0x3dc2200 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x0 0x400>;
+ interrupts = <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ gfx_1_tbu: gfx_1_tbu@3dc9000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x3dc9000 0x1000>,
+ <0x3dc2208 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x400 0x400>;
+ interrupts = <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ apps_smmu: apps-smmu@15000000 {
+ compatible = "qcom,qsmmu-v500";
+ reg = <0x15000000 0x100000>,
+ <0x15182000 0x20>;
+ reg-names = "base", "tcu-base";
+ #iommu-cells = <2>;
+ qcom,skip-init;
+ qcom,use-3-lvl-tables;
+ #global-interrupts = <1>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 0>,
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 1000>;
+
+ qcom,actlr =
+ /* For HF-0 TBU +3 deep PF */
+ <0x800 0x3ff 0x103>,
+ /* For HF-1 TBU +3 deep PF */
+ <0xd00 0x5e0 0x103>,
+ <0xc80 0x5e0 0x103>,
+ <0xc20 0x5e0 0x103>,
+ <0xd20 0x5e0 0x103>,
+ <0xca0 0x5e0 0x103>,
+ <0xd40 0x5e0 0x103>,
+ <0xcc0 0x5e0 0x103>,
+ <0xf40 0x402 0x103>,
+ <0xf42 0x402 0x103>,
+ /* For SF-0 TBU +3 deep PF */
+ <0x1000 0x3ff 0x103>,
+ /* For NPU +3 deep PF */
+ <0x1861 0x400 0x103>,
+ <0x1862 0x400 0x103>,
+ <0x1863 0x404 0x103>,
+ <0x1864 0x400 0x103>,
+ <0x1865 0x400 0x103>,
+ <0x1868 0x400 0x103>;
+
+ anoc_1_tbu: anoc_1_tbu@15185000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15185000 0x1000>,
+ <0x15182200 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x0 0x400>;
+ interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 0>,
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 1000>;
+ };
+
+ anoc_2_tbu: anoc_2_tbu@15189000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15189000 0x1000>,
+ <0x15182208 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x400 0x400>;
+ interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 0>,
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 1000>;
+ };
+
+ mnoc_hf_0_tbu: mnoc_hf_0_tbu@1518d000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x1518D000 0x1000>,
+ <0x15182210 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x800 0x400>;
+ interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc>;
+ qcom,msm-bus,name = "mnoc_hf_0_tbu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_MDP_PORT0>,
+ <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,
+ <0 0>,
+ <MSM_BUS_MASTER_MDP_PORT0>,
+ <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,
+ <0 1000>;
+ };
+
+ mnoc_hf_1_tbu: mnoc_hf_1_tbu@15191000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15191000 0x1000>,
+ <0x15182218 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0xc00 0x400>;
+ interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc>;
+ qcom,msm-bus,name = "mnoc_hf_1_tbu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_MDP_PORT0>,
+ <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,
+ <0 0>,
+ <MSM_BUS_MASTER_MDP_PORT0>,
+ <MSM_BUS_SLAVE_MNOC_HF_MEM_NOC>,
+ <0 1000>;
+ };
+
+ mnoc_sf_0_tbu: mnoc_sf_0_tbu@15195000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15195000 0x1000>,
+ <0x15182220 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x1000 0x400>;
+ interrupts = <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc>;
+ qcom,msm-bus,name = "mnoc_sf_0_tbu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CAMNOC_SF>,
+ <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>,
+ <0 0>,
+ <MSM_BUS_MASTER_CAMNOC_SF>,
+ <MSM_BUS_SLAVE_MNOC_SF_MEM_NOC>,
+ <0 1000>;
+ };
+
+ adsp_tbu: adsp_tbu@15199000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x15199000 0x1000>,
+ <0x15182228 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x1400 0x400>;
+ interrupts = <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 0>,
+ <MSM_BUS_MASTER_GEM_NOC_SNOC>,
+ <MSM_BUS_SLAVE_IMEM_CFG>,
+ <0 1000>;
+ };
+
+ compute_dsp_0_tbu: compute_dsp_0_tbu@1519d000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x1519D000 0x1000>,
+ <0x15182230 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x1800 0x400>;
+ interrupts = <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_NPU>,
+ <MSM_BUS_SLAVE_CDSP_GEM_NOC>,
+ <0 0>,
+ <MSM_BUS_MASTER_NPU>,
+ <MSM_BUS_SLAVE_CDSP_GEM_NOC>,
+ <0 1000>;
+ };
+
+ compute_dsp_1_tbu: compute_dsp_1_tbu@151a1000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x151A1000 0x1000>,
+ <0x15182238 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x1c00 0x400>;
+ interrupts = <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_NPU>,
+ <MSM_BUS_SLAVE_CDSP_GEM_NOC>,
+ <0 0>,
+ <MSM_BUS_MASTER_NPU>,
+ <MSM_BUS_SLAVE_CDSP_GEM_NOC>,
+ <0 1000>;
+ };
+ };
+
+ kgsl_iommu_test_device {
+ compatible = "iommu-debug-test";
+ qcom,iommu-dma = "disabled";
+ iommus = <&kgsl_smmu 0x7 0x400>;
+ };
+
+ apps_iommu_test_device {
+ compatible = "iommu-debug-test";
+ qcom,iommu-dma = "disabled";
+ iommus = <&apps_smmu 0x1 0>;
+ };
+
+ apps_iommu_coherent_test_device {
+ compatible = "iommu-debug-test";
+ qcom,iommu-dma = "disabled";
+ iommus = <&apps_smmu 0x3 0>;
+ dma-coherent;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-scuba.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-scuba.dtsi
new file mode 100755
index 0000000..1d4df9e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-arm-smmu-scuba.dtsi
@@ -0,0 +1,221 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ kgsl_smmu: kgsl-smmu@0x59a0000 {
+ status = "okay";
+ compatible = "qcom,qsmmu-v500";
+ reg = <0x59a0000 0x10000>,
+ <0x59c2000 0x20>;
+ reg-names = "base", "tcu-base";
+ #iommu-cells = <2>;
+ qcom,skip-init;
+ qcom,no-dynamic-asid;
+ qcom,use-3-lvl-tables;
+ #global-interrupts = <1>;
+ qcom,regulator-names = "vdd";
+ vdd-supply = <&gpu_cx_gdsc>;
+ clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+ clock-names = "gcc_gpu_memnoc_gfx",
+ "gcc_gpu_snoc_dvm_gfx",
+ "gpu_cc_ahb",
+ "gpu_cc_hlos1_vote_gpu_smmu_clk";
+ #size-cells = <1>;
+ ranges;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ qcom,actlr =
+ /* ALL CBs of GFX: +15 deep PF */
+ <0x0 0x3ff 0x30B>;
+
+ gfx_0_tbu: gfx_0_tbu@0x59c5000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0x59c5000 0x1000>,
+ <0x59c2200 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x0 0x400>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ apps_smmu: apps-smmu@0xc600000 {
+ status = "okay";
+ compatible = "qcom,qsmmu-v500";
+ reg = <0xc600000 0x80000>,
+ <0xc782000 0x20>;
+ reg-names = "base", "tcu-base";
+ #iommu-cells = <2>;
+ qcom,skip-init;
+ qcom,use-3-lvl-tables;
+ #global-interrupts = <1>;
+ #size-cells = <1>;
+ #address-cells = <1>;
+ ranges;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 1000>;
+
+ qcom,actlr =
+ /* For rt TBU +3 deep PF */
+ <0x400 0x3ff 0x103>,
+ /* For nrt TBU +3 deep PF */
+ <0x800 0x3ff 0x103>;
+
+ anoc_1_tbu: anoc_1_tbu@0xc785000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0xc785000 0x1000>,
+ <0xc782200 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x0 0x400>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IMEM_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 1000>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IMEM_CFG 0 1000>;
+
+ };
+
+ mm_rt_tbu: mm_rt_tbu@0xc789000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0xc789000 0x1000>,
+ <0xc782208 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x400 0x400>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 0>,
+ <MSM_BUS_MASTER_MDP_PORT0 MSM_BUS_SLAVE_SNOC_BIMC_RT 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 1000>,
+ <MSM_BUS_MASTER_MDP_PORT0 MSM_BUS_SLAVE_SNOC_BIMC_RT 0 1000>;
+
+ };
+
+ mm_nrt_tbu: mm_nrt_tbu@0xc78d000 {
+ compatible = "qcom,qsmmuv500-tbu";
+ reg = <0xc78d000 0x1000>,
+ <0xc782210 0x8>;
+ reg-names = "base", "status-reg";
+ qcom,stream-id-range = <0x800 0x400>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,msm-bus,name = "apps_smmu";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 0>,
+ <MSM_BUS_MASTER_CAMNOC_SF MSM_BUS_SLAVE_SNOC_BIMC_NRT 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_TCU 0 1000>,
+ <MSM_BUS_MASTER_CAMNOC_SF MSM_BUS_SLAVE_SNOC_BIMC_NRT 0 1000>;
+
+ };
+
+ };
+
+ kgsl_iommu_test_device {
+ compatible = "iommu-debug-test";
+ qcom,iommu-dma = "disabled";
+ iommus = <&kgsl_smmu 0x7 0x0>;
+ };
+
+ apps_iommu_test_device {
+ compatible = "iommu-debug-test";
+ qcom,iommu-dma = "disabled";
+ iommus = <&apps_smmu 0x1E0 0x0>;
+ };
+
+ apps_iommu_coherent_test_device {
+ compatible = "iommu-debug-test";
+ qcom,iommu-dma = "disabled";
+ iommus = <&apps_smmu 0x1E1 0x0>;
+ dma-coherent;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-audio-lpass.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-audio-lpass.dtsi
new file mode 100755
index 0000000..a9496d8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-audio-lpass.dtsi
@@ -0,0 +1,789 @@
+&soc {
+ pcm0: qcom,msm-pcm {
+ compatible = "qcom,msm-pcm-dsp";
+ qcom,msm-pcm-dsp-id = <0>;
+ };
+
+ routing: qcom,msm-pcm-routing {
+ compatible = "qcom,msm-pcm-routing";
+ };
+
+ compr: qcom,msm-compr-dsp {
+ compatible = "qcom,msm-compr-dsp";
+ };
+
+ pcm1: qcom,msm-pcm-low-latency {
+ compatible = "qcom,msm-pcm-dsp";
+ qcom,msm-pcm-dsp-id = <1>;
+ qcom,msm-pcm-low-latency;
+ qcom,latency-level = "regular";
+ };
+
+ pcm2: qcom,msm-ultra-low-latency {
+ compatible = "qcom,msm-pcm-dsp";
+ qcom,msm-pcm-dsp-id = <2>;
+ qcom,msm-pcm-low-latency;
+ qcom,latency-level = "ultra";
+ };
+
+ pcm_noirq: qcom,msm-pcm-dsp-noirq {
+ compatible = "qcom,msm-pcm-dsp-noirq";
+ qcom,msm-pcm-low-latency;
+ qcom,latency-level = "ultra";
+ };
+
+ trans_loopback: qcom,msm-transcode-loopback {
+ compatible = "qcom,msm-transcode-loopback";
+ };
+
+ compress: qcom,msm-compress-dsp {
+ compatible = "qcom,msm-compress-dsp";
+ };
+
+ voip: qcom,msm-voip-dsp {
+ compatible = "qcom,msm-voip-dsp";
+ };
+
+ voice: qcom,msm-pcm-voice {
+ compatible = "qcom,msm-pcm-voice";
+ qcom,destroy-cvd;
+ };
+
+ stub_codec: qcom,msm-stub-codec {
+ compatible = "qcom,msm-stub-codec";
+ };
+
+ qcom,msm-dai-fe {
+ compatible = "qcom,msm-dai-fe";
+ };
+
+ afe: qcom,msm-pcm-afe {
+ compatible = "qcom,msm-pcm-afe";
+ };
+
+ dai_hdmi: qcom,msm-dai-q6-hdmi {
+ compatible = "qcom,msm-dai-q6-hdmi";
+ qcom,msm-dai-q6-dev-id = <8>;
+ };
+
+ dai_dp: qcom,msm-dai-q6-dp {
+ compatible = "qcom,msm-dai-q6-hdmi";
+ qcom,msm-dai-q6-dev-id = <0>;
+ };
+
+ dai_dp1: qcom,msm-dai-q6-dp1 {
+ compatible = "qcom,msm-dai-q6-hdmi";
+ qcom,msm-dai-q6-dev-id = <1>;
+ };
+
+ loopback: qcom,msm-pcm-loopback {
+ compatible = "qcom,msm-pcm-loopback";
+ };
+
+ loopback1: qcom,msm-pcm-loopback-low-latency {
+ compatible = "qcom,msm-pcm-loopback";
+ qcom,msm-pcm-loopback-low-latency;
+ };
+
+ pcm_dtmf: qcom,msm-pcm-dtmf {
+ compatible = "qcom,msm-pcm-dtmf";
+ };
+
+ msm_dai_mi2s: qcom,msm-dai-mi2s {
+ compatible = "qcom,msm-dai-mi2s";
+ dai_mi2s0: qcom,msm-dai-q6-mi2s-prim {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <0>;
+ qcom,msm-mi2s-rx-lines = <3>;
+ qcom,msm-mi2s-tx-lines = <0>;
+ };
+
+ dai_mi2s1: qcom,msm-dai-q6-mi2s-sec {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <1>;
+ qcom,msm-mi2s-rx-lines = <1>;
+ qcom,msm-mi2s-tx-lines = <0>;
+ };
+
+ dai_mi2s2: qcom,msm-dai-q6-mi2s-tert {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <2>;
+ qcom,msm-mi2s-rx-lines = <0>;
+ qcom,msm-mi2s-tx-lines = <3>;
+ };
+
+ dai_mi2s3: qcom,msm-dai-q6-mi2s-quat {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <3>;
+ qcom,msm-mi2s-rx-lines = <1>;
+ qcom,msm-mi2s-tx-lines = <2>;
+ };
+
+ dai_mi2s4: qcom,msm-dai-q6-mi2s-quin {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <4>;
+ qcom,msm-mi2s-rx-lines = <1>;
+ qcom,msm-mi2s-tx-lines = <2>;
+ };
+
+ dai_mi2s5: qcom,msm-dai-q6-mi2s-senary {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <5>;
+ qcom,msm-mi2s-rx-lines = <0>;
+ qcom,msm-mi2s-tx-lines = <3>;
+ };
+ };
+
+ msm_dai_cdc_dma: qcom,msm-dai-cdc-dma {
+ compatible = "qcom,msm-dai-cdc-dma";
+ wsa_cdc_dma_0_rx: qcom,msm-dai-wsa-cdc-dma-0-rx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45056>;
+ };
+
+ wsa_cdc_dma_0_tx: qcom,msm-dai-wsa-cdc-dma-0-tx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45057>;
+ };
+
+ wsa_cdc_dma_1_rx: qcom,msm-dai-wsa-cdc-dma-1-rx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45058>;
+ };
+
+ wsa_cdc_dma_1_tx: qcom,msm-dai-wsa-cdc-dma-1-tx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45059>;
+ };
+
+ wsa_cdc_dma_2_tx: qcom,msm-dai-wsa-cdc-dma-2-tx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45061>;
+ };
+
+ va_cdc_dma_0_tx: qcom,msm-dai-va-cdc-dma-0-tx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45089>;
+ };
+
+ va_cdc_dma_1_tx: qcom,msm-dai-va-cdc-dma-1-tx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45091>;
+ };
+
+ va_cdc_dma_2_tx: qcom,msm-dai-va-cdc-dma-2-tx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45093>;
+ };
+
+ rx_cdc_dma_0_rx: qcom,msm-dai-rx-cdc-dma-0-rx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45104>;
+ };
+
+ rx_cdc_dma_1_rx: qcom,msm-dai-rx-cdc-dma-1-rx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45106>;
+ };
+
+ rx_cdc_dma_2_rx: qcom,msm-dai-rx-cdc-dma-2-rx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45108>;
+ };
+
+ rx_cdc_dma_3_rx: qcom,msm-dai-rx-cdc-dma-3-rx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45110>;
+ };
+
+ rx_cdc_dma_4_rx: qcom,msm-dai-rx-cdc-dma-4-rx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45112>;
+ };
+
+ rx_cdc_dma_5_rx: qcom,msm-dai-rx-cdc-dma-5-rx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45114>;
+ };
+
+ rx_cdc_dma_6_rx: qcom,msm-dai-rx-cdc-dma-6-rx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45116>;
+ };
+
+ rx_cdc_dma_7_rx: qcom,msm-dai-rx-cdc-dma-7-rx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45118>;
+ };
+
+ tx_cdc_dma_0_tx: qcom,msm-dai-tx-cdc-dma-0-tx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45105>;
+ };
+
+ tx_cdc_dma_1_tx: qcom,msm-dai-tx-cdc-dma-1-tx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45107>;
+ };
+
+ tx_cdc_dma_2_tx: qcom,msm-dai-tx-cdc-dma-2-tx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45109>;
+ };
+
+ tx_cdc_dma_3_tx: qcom,msm-dai-tx-cdc-dma-3-tx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45111>;
+ };
+
+ tx_cdc_dma_4_tx: qcom,msm-dai-tx-cdc-dma-4-tx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45113>;
+ };
+
+ tx_cdc_dma_5_tx: qcom,msm-dai-tx-cdc-dma-5-tx {
+ compatible = "qcom,msm-dai-cdc-dma-dev";
+ qcom,msm-dai-cdc-dma-dev-id = <45115>;
+ };
+ };
+
+ lsm: qcom,msm-lsm-client {
+ compatible = "qcom,msm-lsm-client";
+ };
+
+ qcom,msm-dai-q6 {
+ compatible = "qcom,msm-dai-q6";
+ sb_0_rx: qcom,msm-dai-q6-sb-0-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16384>;
+ };
+
+ sb_0_tx: qcom,msm-dai-q6-sb-0-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16385>;
+ };
+
+ sb_1_rx: qcom,msm-dai-q6-sb-1-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16386>;
+ };
+
+ sb_1_tx: qcom,msm-dai-q6-sb-1-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16387>;
+ };
+
+ sb_2_rx: qcom,msm-dai-q6-sb-2-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16388>;
+ };
+
+ sb_2_tx: qcom,msm-dai-q6-sb-2-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16389>;
+ };
+
+ sb_3_rx: qcom,msm-dai-q6-sb-3-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16390>;
+ };
+
+ sb_3_tx: qcom,msm-dai-q6-sb-3-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16391>;
+ };
+
+ sb_4_rx: qcom,msm-dai-q6-sb-4-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16392>;
+ };
+
+ sb_4_tx: qcom,msm-dai-q6-sb-4-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16393>;
+ };
+
+ sb_5_tx: qcom,msm-dai-q6-sb-5-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16395>;
+ };
+
+ sb_5_rx: qcom,msm-dai-q6-sb-5-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16394>;
+ };
+
+ sb_6_rx: qcom,msm-dai-q6-sb-6-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16396>;
+ };
+
+ sb_7_rx: qcom,msm-dai-q6-sb-7-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16398>;
+ qcom,msm-dai-q6-slim-dev-id = <0>;
+ };
+
+ sb_7_tx: qcom,msm-dai-q6-sb-7-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16399>;
+ qcom,msm-dai-q6-slim-dev-id = <0>;
+ };
+
+ sb_8_rx: qcom,msm-dai-q6-sb-8-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16400>;
+ };
+
+ sb_8_tx: qcom,msm-dai-q6-sb-8-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16401>;
+ qcom,msm-dai-q6-slim-dev-id = <0>;
+ };
+
+ bt_sco_rx: qcom,msm-dai-q6-bt-sco-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12288>;
+ };
+
+ bt_sco_tx: qcom,msm-dai-q6-bt-sco-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12289>;
+ };
+
+ int_fm_rx: qcom,msm-dai-q6-int-fm-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12292>;
+ };
+
+ int_fm_tx: qcom,msm-dai-q6-int-fm-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12293>;
+ };
+
+ afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <224>;
+ };
+
+ afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <225>;
+ };
+
+ afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <241>;
+ };
+
+ afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <240>;
+ };
+
+ incall_record_rx: qcom,msm-dai-q6-incall-record-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <32771>;
+ };
+
+ incall_record_tx: qcom,msm-dai-q6-incall-record-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <32772>;
+ };
+
+ incall_music_rx: qcom,msm-dai-q6-incall-music-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <32773>;
+ };
+
+ incall_music_2_rx: qcom,msm-dai-q6-incall-music-2-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <32770>;
+ };
+
+ proxy_rx: qcom,msm-dai-q6-proxy-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <8194>;
+ };
+
+ proxy_tx: qcom,msm-dai-q6-proxy-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <8195>;
+ };
+
+ usb_audio_rx: qcom,msm-dai-q6-usb-audio-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <28672>;
+ };
+
+ usb_audio_tx: qcom,msm-dai-q6-usb-audio-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <28673>;
+ };
+ };
+
+ hostless: qcom,msm-pcm-hostless {
+ compatible = "qcom,msm-pcm-hostless";
+ };
+
+ audio_apr: qcom,msm-audio-apr {
+ compatible = "qcom,msm-audio-apr";
+ qcom,subsys-name = "apr_adsp";
+
+ msm_audio_ion: qcom,msm-audio-ion {
+ compatible = "qcom,msm-audio-ion";
+ qcom,smmu-version = <2>;
+ qcom,smmu-enabled;
+ iommus = <&apps_smmu 0x1801 0x0>;
+ qcom,iommu-dma-addr-pool = <0x10000000 0x10000000>;
+ };
+ };
+
+ dai_pri_auxpcm: qcom,msm-pri-auxpcm {
+ compatible = "qcom,msm-auxpcm-dev";
+ qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
+ qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
+ qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-data = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
+ qcom,msm-auxpcm-interface = "primary";
+ qcom,msm-cpudai-afe-clk-ver = <2>;
+ };
+
+ dai_sec_auxpcm: qcom,msm-sec-auxpcm {
+ compatible = "qcom,msm-auxpcm-dev";
+ qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
+ qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
+ qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-data = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
+ qcom,msm-auxpcm-interface = "secondary";
+ qcom,msm-cpudai-afe-clk-ver = <2>;
+ };
+
+ dai_tert_auxpcm: qcom,msm-tert-auxpcm {
+ compatible = "qcom,msm-auxpcm-dev";
+ qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
+ qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
+ qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-data = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
+ qcom,msm-auxpcm-interface = "tertiary";
+ qcom,msm-cpudai-afe-clk-ver = <2>;
+ };
+
+ dai_quat_auxpcm: qcom,msm-quat-auxpcm {
+ compatible = "qcom,msm-auxpcm-dev";
+ qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
+ qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
+ qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-data = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
+ qcom,msm-auxpcm-interface = "quaternary";
+ qcom,msm-cpudai-afe-clk-ver = <2>;
+ };
+
+ dai_quin_auxpcm: qcom,msm-quin-auxpcm {
+ compatible = "qcom,msm-auxpcm-dev";
+ qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
+ qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
+ qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-data = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
+ qcom,msm-auxpcm-interface = "quinary";
+ qcom,msm-cpudai-afe-clk-ver = <2>;
+ };
+
+ dai_sen_auxpcm: qcom,msm-sen-auxpcm {
+ compatible = "qcom,msm-auxpcm-dev";
+ qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
+ qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
+ qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-data = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
+ qcom,msm-auxpcm-interface = "senary";
+ qcom,msm-cpudai-afe-clk-ver = <2>;
+ };
+
+ hdmi_dba: qcom,msm-hdmi-dba-codec-rx {
+ compatible = "qcom,msm-hdmi-dba-codec-rx";
+ qcom,dba-bridge-chip = "adv7533";
+ };
+
+ adsp_loader: qcom,msm-adsp-loader {
+ status = "ok";
+ compatible = "qcom,adsp-loader";
+ qcom,adsp-state = <0>;
+ };
+
+ tdm_pri_rx: qcom,msm-dai-tdm-pri-rx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37120>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36864>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36864>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ tdm_pri_tx: qcom,msm-dai-tdm-pri-tx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37121>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36865>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36865>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ tdm_sec_rx: qcom,msm-dai-tdm-sec-rx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37136>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36880>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36880>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ tdm_sec_tx: qcom,msm-dai-tdm-sec-tx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37137>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36881>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36881>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ tdm_tert_rx: qcom,msm-dai-tdm-tert-rx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37152>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36896>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36896>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ tdm_tert_tx: qcom,msm-dai-tdm-tert-tx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37153>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36897 >;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36897 >;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ tdm_quat_rx: qcom,msm-dai-tdm-quat-rx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37168>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36912>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36912>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ tdm_quat_tx: qcom,msm-dai-tdm-quat-tx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37169>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36913 >;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36913 >;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ tdm_quin_rx: qcom,msm-dai-tdm-quin-rx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37184>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36928>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_quin_tdm_rx_0: qcom,msm-dai-q6-tdm-quin-rx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36928>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ tdm_quin_tx: qcom,msm-dai-tdm-quin-tx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37185>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36929>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_quin_tdm_tx_0: qcom,msm-dai-q6-tdm-quin-tx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36929>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ tdm_sen_rx: qcom,msm-dai-tdm-sen-rx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37200>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36944>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_sen_tdm_rx_0: qcom,msm-dai-q6-tdm-sen-rx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36944>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ tdm_sen_tx: qcom,msm-dai-tdm-sen-tx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37201>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36945>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_sen_tdm_tx_0: qcom,msm-dai-q6-tdm-sen-tx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36945>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ dai_pri_spdif_rx: qcom,msm-dai-q6-spdif-pri-rx {
+ compatible = "qcom,msm-dai-q6-spdif";
+ qcom,msm-dai-q6-dev-id = <20480>;
+ };
+
+ dai_pri_spdif_tx: qcom,msm-dai-q6-spdif-pri-tx {
+ compatible = "qcom,msm-dai-q6-spdif";
+ qcom,msm-dai-q6-dev-id = <20481>;
+ };
+
+ dai_sec_spdif_rx: qcom,msm-dai-q6-spdif-sec-rx {
+ compatible = "qcom,msm-dai-q6-spdif";
+ qcom,msm-dai-q6-dev-id = <20482>;
+ };
+
+ dai_sec_spdif_tx: qcom,msm-dai-q6-spdif-sec-tx {
+ compatible = "qcom,msm-dai-q6-spdif";
+ qcom,msm-dai-q6-dev-id = <20483>;
+ };
+
+ afe_loopback_tx: qcom,msm-dai-q6-afe-loopback-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <24577>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-audio.dtsi
new file mode 100755
index 0000000..8b9166d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-audio.dtsi
@@ -0,0 +1,847 @@
+&spi_7 {
+ status = "okay";
+};
+
+&pm660_gpios {
+ pmi_clk {
+ pmi_clk_default: pmi_clk_default {
+ status = "ok";
+ pins = "gpio3";
+ function = "func1";
+ output-enable;
+ output-low;
+ qcom,drive-strength = <2>;
+ };
+ };
+};
+
+&soc {
+ pcm0: qcom,msm-pcm {
+ compatible = "qcom,msm-pcm-dsp";
+ qcom,msm-pcm-dsp-id = <0>;
+ };
+
+ routing: qcom,msm-pcm-routing {
+ compatible = "qcom,msm-pcm-routing";
+ };
+
+ compr: qcom,msm-compr-dsp {
+ compatible = "qcom,msm-compr-dsp";
+ };
+
+ pcm2: qcom,msm-ultra-low-latency {
+ compatible = "qcom,msm-pcm-dsp";
+ qcom,msm-pcm-dsp-id = <2>;
+ qcom,msm-pcm-low-latency;
+ qcom,latency-level = "ultra";
+ };
+
+ pcm1: qcom,msm-pcm-low-latency {
+ compatible = "qcom,msm-pcm-dsp";
+ qcom,msm-pcm-dsp-id = <1>;
+ qcom,msm-pcm-low-latency;
+ qcom,latency-level = "regular";
+ };
+
+ pcm2: qcom,msm-ultra-low-latency {
+ compatible = "qcom,msm-pcm-dsp";
+ qcom,msm-pcm-dsp-id = <2>;
+ qcom,msm-pcm-low-latency;
+ qcom,latency-level = "ultra";
+ };
+
+ pcm_noirq: qcom,msm-pcm-dsp-noirq {
+ compatible = "qcom,msm-pcm-dsp-noirq";
+ qcom,msm-pcm-low-latency;
+ qcom,latency-level = "ultra";
+ };
+
+ cpe: qcom,msm-cpe-lsm {
+ compatible = "qcom,msm-cpe-lsm";
+ };
+
+ cpe3: qcom,msm-cpe-lsm@3 {
+ compatible = "qcom,msm-cpe-lsm";
+ qcom,msm-cpe-lsm-id = <3>;
+ };
+
+ wdsp_mgr: qcom,wcd-dsp-mgr {
+ compatible = "qcom,wcd-dsp-mgr";
+ qcom,wdsp-components = <&wcd934x_cdc 0>,
+ <&wcd_spi_0 1>,
+ <&glink_spi_xprt_wdsp 2>;
+ qcom,img-filename = "cpe_9340";
+ };
+
+ wdsp_glink: qcom,wcd-dsp-glink {
+ compatible = "qcom,wcd-dsp-glink";
+ qcom,wdsp-channels = "g_glink_ctrl",
+ "g_glink_persistent_data_nild",
+ "g_glink_persistent_data_ild",
+ "g_glink_audio_data";
+ };
+
+ compress: qcom,msm-compress-dsp {
+ compatible = "qcom,msm-compress-dsp";
+ };
+
+ voip: qcom,msm-voip-dsp {
+ compatible = "qcom,msm-voip-dsp";
+ };
+
+ voice: qcom,msm-pcm-voice {
+ compatible = "qcom,msm-pcm-voice";
+ qcom,destroy-cvd;
+ };
+
+ stub_codec: qcom,msm-stub-codec {
+ compatible = "qcom,msm-stub-codec";
+ };
+
+ qcom,msm-dai-fe {
+ compatible = "qcom,msm-dai-fe";
+ };
+
+ afe: qcom,msm-pcm-afe {
+ compatible = "qcom,msm-pcm-afe";
+ };
+
+ dai_dp: qcom,msm-dai-q6-dp {
+ compatible = "qcom,msm-dai-q6-hdmi";
+ qcom,msm-dai-q6-dev-id = <0>;
+ };
+
+ loopback: qcom,msm-pcm-loopback {
+ compatible = "qcom,msm-pcm-loopback";
+ };
+
+ qcom,msm-dai-mi2s {
+ compatible = "qcom,msm-dai-mi2s";
+ dai_mi2s0: qcom,msm-dai-q6-mi2s-prim {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <0>;
+ qcom,msm-mi2s-rx-lines = <3>;
+ qcom,msm-mi2s-tx-lines = <0>;
+ };
+
+ dai_mi2s1: qcom,msm-dai-q6-mi2s-sec {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <1>;
+ qcom,msm-mi2s-rx-lines = <1>;
+ qcom,msm-mi2s-tx-lines = <0>;
+ };
+
+ dai_mi2s3: qcom,msm-dai-q6-mi2s-quat {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <3>;
+ qcom,msm-mi2s-rx-lines = <1>;
+ qcom,msm-mi2s-tx-lines = <2>;
+ };
+
+ dai_mi2s2: qcom,msm-dai-q6-mi2s-tert {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <2>;
+ qcom,msm-mi2s-rx-lines = <0>;
+ qcom,msm-mi2s-tx-lines = <3>;
+ };
+
+ dai_mi2s4: qcom,msm-dai-q6-mi2s-quin {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <4>;
+ qcom,msm-mi2s-rx-lines = <1>;
+ qcom,msm-mi2s-tx-lines = <2>;
+ };
+
+ dai_mi2s6: qcom,msm-dai-q6-mi2s-senary {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <6>;
+ qcom,msm-mi2s-rx-lines = <0>;
+ qcom,msm-mi2s-tx-lines = <3>;
+ };
+
+ dai_int_mi2s0: qcom,msm-dai-q6-int-mi2s0 {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <7>;
+ qcom,msm-mi2s-rx-lines = <3>;
+ qcom,msm-mi2s-tx-lines = <0>;
+ };
+
+ dai_int_mi2s1: qcom,msm-dai-q6-int-mi2s1 {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <8>;
+ qcom,msm-mi2s-rx-lines = <3>;
+ qcom,msm-mi2s-tx-lines = <0>;
+ };
+
+ dai_int_mi2s2: qcom,msm-dai-q6-int-mi2s2 {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <9>;
+ qcom,msm-mi2s-rx-lines = <0>;
+ qcom,msm-mi2s-tx-lines = <3>;
+ };
+
+ dai_int_mi2s3: qcom,msm-dai-q6-int-mi2s3 {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <10>;
+ qcom,msm-mi2s-rx-lines = <0>;
+ qcom,msm-mi2s-tx-lines = <3>;
+ };
+
+ dai_int_mi2s4: qcom,msm-dai-q6-int-mi2s4 {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <11>;
+ qcom,msm-mi2s-rx-lines = <3>;
+ qcom,msm-mi2s-tx-lines = <0>;
+ };
+
+ dai_int_mi2s5: qcom,msm-dai-q6-int-mi2s5 {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <12>;
+ qcom,msm-mi2s-rx-lines = <0>;
+ qcom,msm-mi2s-tx-lines = <3>;
+ };
+
+ dai_int_mi2s6: qcom,msm-dai-q6-int-mi2s6 {
+ compatible = "qcom,msm-dai-q6-mi2s";
+ qcom,msm-dai-q6-mi2s-dev-id = <13>;
+ qcom,msm-mi2s-rx-lines = <0>;
+ qcom,msm-mi2s-tx-lines = <3>;
+ };
+ };
+
+ lsm: qcom,msm-lsm-client {
+ compatible = "qcom,msm-lsm-client";
+ };
+
+ qcom,msm-dai-q6 {
+ compatible = "qcom,msm-dai-q6";
+ sb_0_rx: qcom,msm-dai-q6-sb-0-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16384>;
+ };
+
+ sb_0_tx: qcom,msm-dai-q6-sb-0-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16385>;
+ };
+
+ sb_1_rx: qcom,msm-dai-q6-sb-1-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16386>;
+ };
+
+ sb_1_tx: qcom,msm-dai-q6-sb-1-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16387>;
+ };
+
+ sb_2_rx: qcom,msm-dai-q6-sb-2-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16388>;
+ };
+
+ sb_2_tx: qcom,msm-dai-q6-sb-2-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16389>;
+ };
+
+
+ sb_3_rx: qcom,msm-dai-q6-sb-3-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16390>;
+ };
+
+ sb_3_tx: qcom,msm-dai-q6-sb-3-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16391>;
+ };
+
+ sb_4_rx: qcom,msm-dai-q6-sb-4-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16392>;
+ };
+
+ sb_4_tx: qcom,msm-dai-q6-sb-4-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16393>;
+ };
+
+ sb_5_tx: qcom,msm-dai-q6-sb-5-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16395>;
+ };
+
+ sb_5_rx: qcom,msm-dai-q6-sb-5-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16394>;
+ };
+
+ sb_6_rx: qcom,msm-dai-q6-sb-6-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16396>;
+ };
+
+ sb_7_tx: qcom,msm-dai-q6-sb-7-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16399>;
+ qcom,msm-dai-q6-slim-dev-id = <1>;
+ };
+
+ sb_7_rx: qcom,msm-dai-q6-sb-7-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16398>;
+ qcom,msm-dai-q6-slim-dev-id = <1>;
+ };
+
+ sb_8_tx: qcom,msm-dai-q6-sb-8-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16401>;
+ qcom,msm-dai-q6-slim-dev-id = <1>;
+ };
+
+ sb_8_rx: qcom,msm-dai-q6-sb-8-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <16400>;
+ qcom,msm-dai-q6-slim-dev-id = <1>;
+ };
+
+ bt_sco_rx: qcom,msm-dai-q6-bt-sco-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12288>;
+ };
+
+ bt_sco_tx: qcom,msm-dai-q6-bt-sco-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12289>;
+ };
+
+ int_fm_rx: qcom,msm-dai-q6-int-fm-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12292>;
+ };
+
+ int_fm_tx: qcom,msm-dai-q6-int-fm-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <12293>;
+ };
+
+ afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <224>;
+ };
+
+ afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <225>;
+ };
+
+ afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <241>;
+ };
+
+ afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <240>;
+ };
+
+ incall_record_rx: qcom,msm-dai-q6-incall-record-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <32771>;
+ };
+
+ incall_record_tx: qcom,msm-dai-q6-incall-record-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <32772>;
+ };
+
+ incall_music_rx: qcom,msm-dai-q6-incall-music-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <32773>;
+ };
+
+ incall_music_2_rx: qcom,msm-dai-q6-incall-music-2-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <32770>;
+ };
+
+ proxy_rx: qcom,msm-dai-q6-proxy-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <8194>;
+ };
+
+ proxy_tx: qcom,msm-dai-q6-proxy-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <8195>;
+ };
+
+ usb_audio_rx: qcom,msm-dai-q6-usb-audio-rx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <28672>;
+ };
+
+ usb_audio_tx: qcom,msm-dai-q6-usb-audio-tx {
+ compatible = "qcom,msm-dai-q6-dev";
+ qcom,msm-dai-q6-dev-id = <28673>;
+ };
+ };
+
+ hostless: qcom,msm-pcm-hostless {
+ compatible = "qcom,msm-pcm-hostless";
+ };
+
+ dai_pri_auxpcm: qcom,msm-pri-auxpcm {
+ compatible = "qcom,msm-auxpcm-dev";
+ qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
+ qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
+ qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-data = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
+ qcom,msm-auxpcm-interface = "primary";
+ qcom,msm-cpudai-afe-clk-ver = <2>;
+ };
+
+ dai_sec_auxpcm: qcom,msm-sec-auxpcm {
+ compatible = "qcom,msm-auxpcm-dev";
+ qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
+ qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
+ qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-data = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
+ qcom,msm-auxpcm-interface = "secondary";
+ qcom,msm-cpudai-afe-clk-ver = <2>;
+ };
+
+ dai_tert_auxpcm: qcom,msm-tert-auxpcm {
+ compatible = "qcom,msm-auxpcm-dev";
+ qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
+ qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
+ qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-data = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
+ qcom,msm-auxpcm-interface = "tertiary";
+ qcom,msm-cpudai-afe-clk-ver = <2>;
+ };
+
+ dai_quat_auxpcm: qcom,msm-quat-auxpcm {
+ compatible = "qcom,msm-auxpcm-dev";
+ qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
+ qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
+ qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-data = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
+ qcom,msm-auxpcm-interface = "quaternary";
+ qcom,msm-cpudai-afe-clk-ver = <2>;
+ };
+ dai_quin_auxpcm: qcom,msm-quin-auxpcm {
+ compatible = "qcom,msm-auxpcm-dev";
+ qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
+ qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
+ qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
+ qcom,msm-cpudai-auxpcm-data = <0>, <0>;
+ qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
+ qcom,msm-auxpcm-interface = "quinary";
+ qcom,msm-cpudai-afe-clk-ver = <2>;
+ };
+
+ qcom,msm-adsp-loader {
+ compatible = "qcom,adsp-loader";
+ qcom,adsp-state = <0>;
+ };
+
+ qcom,msm-dai-tdm-pri-rx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37120>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36864>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36864>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ qcom,msm-dai-tdm-pri-tx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37121>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36865>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36865>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ qcom,msm-dai-tdm-sec-rx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37136>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36880>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36880>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ qcom,msm-dai-tdm-sec-tx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37137>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36881>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36881>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ qcom,msm-dai-tdm-tert-rx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37152>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36896>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36896>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ qcom,msm-dai-tdm-tert-tx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37153>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36897 >;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36897 >;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ qcom,msm-dai-tdm-quat-rx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37168>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36912>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36912>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ qcom,msm-dai-tdm-quat-tx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37169>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36913 >;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36913 >;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ tdm_quin_rx: qcom,msm-dai-tdm-quin-rx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37184>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36928>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_quin_tdm_rx_0: qcom,msm-dai-q6-tdm-quin-rx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36928>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ tdm_quin_tx: qcom,msm-dai-tdm-quin-tx {
+ compatible = "qcom,msm-dai-tdm";
+ qcom,msm-cpudai-tdm-group-id = <37185>;
+ qcom,msm-cpudai-tdm-group-num-ports = <1>;
+ qcom,msm-cpudai-tdm-group-port-id = <36929>;
+ qcom,msm-cpudai-tdm-clk-rate = <1536000>;
+ qcom,msm-cpudai-tdm-clk-internal = <1>;
+ qcom,msm-cpudai-tdm-sync-mode = <1>;
+ qcom,msm-cpudai-tdm-sync-src = <1>;
+ qcom,msm-cpudai-tdm-data-out = <0>;
+ qcom,msm-cpudai-tdm-invert-sync = <1>;
+ qcom,msm-cpudai-tdm-data-delay = <1>;
+ dai_quin_tdm_tx_0: qcom,msm-dai-q6-tdm-quin-tx-0 {
+ compatible = "qcom,msm-dai-q6-tdm";
+ qcom,msm-cpudai-tdm-dev-id = <36929>;
+ qcom,msm-cpudai-tdm-data-align = <0>;
+ };
+ };
+
+ qcom,avtimer@150f700c {
+ compatible = "qcom,avtimer";
+ reg = <0x150f700c 0x4>,
+ <0x150f7010 0x4>;
+ reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
+ qcom,clk-div = <27>;
+ };
+
+ audio_apr: qcom,msm-audio-apr {
+ compatible = "qcom,msm-audio-apr";
+ qcom,subsys-name = "apr_adsp";
+ msm_audio_ion: qcom,msm-audio-ion {
+ compatible = "qcom,msm-audio-ion";
+ qcom,smmu-version = <2>;
+ qcom,smmu-enabled;
+ iommus = <&lpass_q6_smmu 1>;
+ };
+ };
+
+ tasha_snd: sound-9335 {
+ status = "disabled";
+ compatible = "qcom,sdm660-asoc-snd-tasha";
+ qcom,model = "sdm660-tasha-snd-card";
+ qcom,mi2s-audio-intf;
+ qcom,auxpcm-audio-intf;
+ qcom,ext-disp-audio-rx;
+ qcom,wcn-btfm;
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
+ qcom,audio-routing =
+ "AIF4 VI", "MCLK",
+ "RX_BIAS", "MCLK",
+ "MADINPUT", "MCLK",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Headset Mic",
+ "AMIC3", "MIC BIAS2",
+ "MIC BIAS2", "ANCRight Headset Mic",
+ "AMIC4", "MIC BIAS2",
+ "MIC BIAS2", "ANCLeft Headset Mic",
+ "AMIC5", "MIC BIAS3",
+ "MIC BIAS3", "Handset Mic",
+ "AMIC6", "MIC BIAS4",
+ "MIC BIAS4", "Analog Mic6",
+ "DMIC0", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic0",
+ "DMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic1",
+ "DMIC2", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic2",
+ "DMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic3",
+ "DMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "SpkrLeft IN", "SPK1 OUT",
+ "SpkrRight IN", "SPK2 OUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ qcom,us-euro-gpios = <&us_euro_gpio>;
+ qcom,hph-en0-gpio = <&tasha_hph_en0>;
+ qcom,hph-en1-gpio = <&tasha_hph_en1>;
+ qcom,msm-mclk-freq = <9600000>;
+ asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
+ <&loopback>, <&compress>, <&hostless>,
+ <&afe>, <&lsm>, <&routing>, <&cpe>, <&compr>,
+ <&pcm_noirq>, <&cpe3>;
+ asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
+ "msm-pcm-dsp.2", "msm-voip-dsp",
+ "msm-pcm-voice", "msm-pcm-loopback",
+ "msm-compress-dsp", "msm-pcm-hostless",
+ "msm-pcm-afe", "msm-lsm-client",
+ "msm-pcm-routing", "msm-cpe-lsm",
+ "msm-compr-dsp", "msm-pcm-dsp-noirq",
+ "msm-cpe-lsm.3";
+ asoc-cpu = <&dai_dp>,
+ <&dai_mi2s0>, <&dai_mi2s1>, <&dai_mi2s2>,
+ <&dai_mi2s3>, <&dai_mi2s4>,
+ <&dai_pri_auxpcm>, <&dai_sec_auxpcm>,
+ <&dai_tert_auxpcm>, <&dai_quat_auxpcm>,
+ <&dai_quin_auxpcm>,
+ <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>,
+ <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>,
+ <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>,
+ <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>,
+ <&afe_proxy_tx>, <&incall_record_rx>,
+ <&incall_record_tx>, <&incall_music_rx>,
+ <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>,
+ <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, <&sb_8_rx>,
+ <&usb_audio_rx>, <&usb_audio_tx>,
+ <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>,
+ <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>,
+ <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>,
+ <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>,
+ <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>,
+ <&proxy_rx>, <&proxy_tx>;
+
+ asoc-cpu-names = "msm-dai-q6-dp.0", "msm-dai-q6-mi2s.0",
+ "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2",
+ "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.4",
+ "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2",
+ "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4",
+ "msm-dai-q6-auxpcm.5",
+ "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385",
+ "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387",
+ "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389",
+ "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391",
+ "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393",
+ "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224",
+ "msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
+ "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
+ "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
+ "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394",
+ "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398",
+ "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401",
+ "msm-dai-q6-dev.16400", "msm-dai-q6-dev.28672",
+ "msm-dai-q6-dev.28673", "msm-dai-q6-tdm.36864",
+ "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36880",
+ "msm-dai-q6-tdm.36881", "msm-dai-q6-tdm.36896",
+ "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36912",
+ "msm-dai-q6-tdm.36913", "msm-dai-q6-tdm.36928",
+ "msm-dai-q6-tdm.36929",
+ "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195";
+ asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>;
+ asoc-codec-names = "msm-stub-codec.1",
+ "msm-ext-disp-audio-codec-rx";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa881x_211>, <&wsa881x_212>,
+ <&wsa881x_213>, <&wsa881x_214>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+ "SpkrLeft", "SpkrRight";
+ };
+
+ us_euro_gpio: msm_cdc_pinctrl@75 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wcd_gnd_mic_swap_active>;
+ pinctrl-1 = <&wcd_gnd_mic_swap_idle>;
+ };
+
+ wcd9xxx_intc: wcd9xxx-irq {
+ compatible = "qcom,wcd9xxx-irq";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <0 177 0>;
+ interrupt-names = "wcd_irq";
+ };
+
+ clock_audio: audio_ext_clk {
+ status = "disabled";
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <13>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmi_clk_default>;
+ qcom,audio-ref-clk-gpio = <&pm660_gpios 3 0>;
+ clock-names = "osr_clk";
+ clocks = <&clock_rpmcc RPM_SMD_DIV_CLK1>;
+ qcom,node_has_rpm_clock;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_native: audio_ext_clk_native {
+ status = "disabled";
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <3>;
+ qcom,use-pinctrl = <1>;
+ clock-names = "osr_clk";
+ #clock-cells = <1>;
+ qcom,codec-mclk-clk-freq = <11289600>;
+ qcom,mclk-clk-reg = <0x15020018 0x0>;
+ pinctrl-names = "sleep", "active";
+ pinctrl-0 = <&lpi_mclk0_sleep>;
+ pinctrl-1 = <&lpi_mclk0_active>;
+ };
+
+ clock_audio_lnbb: audio_ext_clk_lnbb {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <1>;
+ clock-names = "osr_clk";
+ clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK2>;
+ qcom,node_has_rpm_clock;
+ #clock-cells = <1>;
+ };
+
+ wcd_rst_gpio: msm_cdc_pinctrl@64 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&lpi_cdc_reset_active>;
+ pinctrl-1 = <&lpi_cdc_reset_sleep>;
+ qcom,lpi-gpios;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-gdsc-660.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-gdsc-660.dtsi
new file mode 100755
index 0000000..a61f037
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-gdsc-660.dtsi
@@ -0,0 +1,146 @@
+&soc {
+ /* GCC GDSCs */
+ gdsc_usb30: qcom,gdsc@10f004 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_usb30";
+ reg = <0x10f004 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_ufs: qcom,gdsc@175004 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_ufs";
+ reg = <0x175004 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_hlos1_vote_lpass_adsp: qcom,gdsc@17d034 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_hlos1_vote_lpass_adsp";
+ reg = <0x17d034 0x4>;
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ gdsc_hlos1_vote_turing_adsp: qcom,gdsc@17d04c {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_hlos1_vote_turing_adsp";
+ reg = <0x17d04c 0x4>;
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ gdsc_hlos2_vote_turing_adsp: qcom,gdsc@17e04c {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_hlos2_vote_turing_adsp";
+ reg = <0x17e04c 0x4>;
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ /* MMSS GDSCs */
+ bimc_smmu_hw_ctrl: syscon@c8ce024 {
+ compatible = "syscon";
+ reg = <0xc8ce024 0x4>;
+ };
+
+ gdsc_bimc_smmu: qcom,gdsc@c8ce020 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_bimc_smmu";
+ reg = <0xc8ce020 0x4>;
+ hw-ctrl-addr = <&bimc_smmu_hw_ctrl>;
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ gdsc_venus: qcom,gdsc@c8c1024 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_venus";
+ reg = <0xc8c1024 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_venus_core0: qcom,gdsc@c8c1040 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_venus_core0";
+ reg = <0xc8c1040 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_camss_top: qcom,gdsc@c8c34a0 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_camss_top";
+ reg = <0xc8c34a0 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_vfe0: qcom,gdsc@c8c3664 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_vfe0";
+ reg = <0xc8c3664 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_vfe1: qcom,gdsc@c8c3674 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_vfe1";
+ reg = <0xc8c3674 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_cpp: qcom,gdsc@c8c36d4 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_cpp";
+ reg = <0xc8c36d4 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_mdss: qcom,gdsc@c8c2304 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_mdss";
+ reg = <0xc8c2304 0x4>;
+ status = "disabled";
+ };
+
+ /* GPU GDSCs */
+ gpu_cx_hw_ctrl: syscon@5066008 {
+ compatible = "syscon";
+ reg = <0x5066008 0x4>;
+ };
+
+ gdsc_gpu_cx: qcom,gdsc@5066004 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_gpu_cx";
+ reg = <0x5066004 0x4>;
+ hw-ctrl-addr = <&gpu_cx_hw_ctrl>;
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <2000>;
+ status = "disabled";
+ };
+
+ /* GPU GX GDSCs */
+ gpu_gx_domain_addr: syscon@5065130 {
+ compatible = "syscon";
+ reg = <0x5065130 0x4>;
+ };
+
+ gpu_gx_sw_reset: syscon@5066090 {
+ compatible = "syscon";
+ reg = <0x5066090 0x4>;
+ };
+
+ gdsc_gpu_gx: qcom,gdsc@5066094 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_gpu_gx";
+ reg = <0x5066094 0x4>;
+ domain-addr = <&gpu_gx_domain_addr>;
+ sw-reset = <&gpu_gx_sw_reset>;
+ qcom,retain-periph;
+ qcom,reset-aon-logic;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-gdsc-8916.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-gdsc-8916.dtsi
new file mode 100755
index 0000000..89a35d7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-gdsc-8916.dtsi
@@ -0,0 +1,78 @@
+&soc {
+ gdsc_venus: qcom,gdsc@184c018 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_venus";
+ reg = <0x184c018 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_mdss: qcom,gdsc@184d078 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_mdss";
+ reg = <0x184d078 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_jpeg: qcom,gdsc@185701c {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_jpeg";
+ reg = <0x185701c 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_vfe: qcom,gdsc@1858034 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_vfe";
+ reg = <0x1858034 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_vfe1: qcom,gdsc@185806c {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_vfe1";
+ reg = <0x185806c 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_cpp: qcom,gdsc@1858078 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_cpp";
+ reg = <0x1858078 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_oxili_gx: qcom,gdsc@185901c {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_oxili_gx";
+ reg = <0x185901c 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_venus_core0: qcom,gdsc@184c028 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_venus_core0";
+ reg = <0x184c028 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_venus_core1: qcom,gdsc@184c030 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_venus_core1";
+ reg = <0x184c030 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_oxili_cx: qcom,gdsc@185904c {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_oxili_cx";
+ reg = <0x185904c 0x4>;
+ status = "disabled";
+ };
+
+ gdsc_usb30: qcom,gdsc@183f078 {
+ compatible = "qcom,gdsc";
+ regulator-name = "gdsc_usb30";
+ reg = <0x183f078 0x4>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-pm660a.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-pm660a.dtsi
new file mode 100755
index 0000000..ace6e91
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-pm660a.dtsi
@@ -0,0 +1,17 @@
+/* Disable WLED */
+&pm660l_wled {
+ status = "disabled";
+};
+
+/* disable LCDB */
+&pm660l_lcdb {
+ status = "disabled";
+};
+
+&pm660a_oledb {
+ status = "okay";
+};
+
+&pm660a_labibb {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-qvr-external.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-qvr-external.dtsi
new file mode 100755
index 0000000..e5056b6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-qvr-external.dtsi
@@ -0,0 +1,9 @@
+&soc {
+
+ qcom,smp2p_interrupt_qvrexternal_5_out {
+ compatible = "qcom,smp2p-interrupt-qvrexternal-5-out";
+ qcom,smem-states = <&smp2p_qvrexternal5_out 0>;
+ qcom,smem-state-names = "qvrexternal-smp2p-out";
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-rdbg-scuba.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-rdbg-scuba.dtsi
new file mode 100755
index 0000000..758dda2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-rdbg-scuba.dtsi
@@ -0,0 +1,15 @@
+&soc {
+ /* smp2p information */
+ qcom,smp2p_interrupt_rdbg_2_out {
+ compatible = "qcom,smp2p-interrupt-rdbg-2-out";
+ qcom,smem-states = <&smp2p_rdbg2_out 0>;
+ qcom,smem-state-names = "rdbg-smp2p-out";
+ };
+
+ qcom,smp2p_interrupt_rdbg_2_in {
+ compatible = "qcom,smp2p-interrupt-rdbg-2-in";
+ interrupts-extended = <&smp2p_rdbg2_in 0 0>;
+ interrupt-names = "rdbg-smp2p-in";
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm-rdbg.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm-rdbg.dtsi
new file mode 100755
index 0000000..bb2adf8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm-rdbg.dtsi
@@ -0,0 +1,26 @@
+&soc {
+ /* smp2p information */
+ qcom,smp2p_interrupt_rdbg_2_out {
+ compatible = "qcom,smp2p-interrupt-rdbg-2-out";
+ qcom,smem-states = <&smp2p_rdbg2_out 0>;
+ qcom,smem-state-names = "rdbg-smp2p-out";
+ };
+
+ qcom,smp2p_interrupt_rdbg_2_in {
+ compatible = "qcom,smp2p-interrupt-rdbg-2-in";
+ interrupts-extended = <&smp2p_rdbg2_in 0 0>;
+ interrupt-names = "rdbg-smp2p-in";
+ };
+
+ qcom,smp2p_interrupt_rdbg_5_out {
+ compatible = "qcom,smp2p-interrupt-rdbg-5-out";
+ qcom,smem-states = <&smp2p_rdbg5_out 0>;
+ qcom,smem-state-names = "rdbg-smp2p-out";
+ };
+
+ qcom,smp2p_interrupt_rdbg_5_in {
+ compatible = "qcom,smp2p-interrupt-rdbg-5-in";
+ interrupts-extended = <&smp2p_rdbg5_in 0 0>;
+ interrupt-names = "rdbg-smp2p-in";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-bus.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-bus.dtsi
new file mode 100755
index 0000000..2ce4843
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-bus.dtsi
@@ -0,0 +1,932 @@
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ /* Version = 11 */
+ ad_hoc_bus: ad-hoc-bus@580000 {
+ compatible = "qcom,msm-bus-device";
+ reg = <0x580000 0x16080>,
+ <0x580000 0x16080>,
+ <0x400000 0x5a000>,
+ <0x500000 0x13080>;
+ reg-names = "snoc-base", "snoc-mm-base",
+ "bimc-base", "pcnoc-base";
+
+ /* Buses */
+ fab_bimc: fab-bimc {
+ cell-id = <MSM_BUS_FAB_BIMC>;
+ label = "fab-bimc";
+ qcom,fab-dev;
+ qcom,base-name = "bimc-base";
+ qcom,bus-type = <2>;
+ qcom,util-fact = <154>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc BIMC_MSMBUS_CLK>,
+ <&rpmcc BIMC_MSMBUS_A_CLK>;
+ };
+
+ fab_pcnoc: fab-pcnoc {
+ cell-id = <MSM_BUS_FAB_PERIPH_NOC>;
+ label = "fab-pcnoc";
+ qcom,fab-dev;
+ qcom,base-name = "pcnoc-base";
+ qcom,base-offset = <0x7000>;
+ qcom,qos-off = <0x1000>;
+ qcom,bus-type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc PNOC_MSMBUS_CLK>,
+ <&rpmcc PNOC_MSMBUS_A_CLK>;
+ };
+
+ fab_snoc: fab-snoc {
+ cell-id = <MSM_BUS_FAB_SYS_NOC>;
+ label = "fab-snoc";
+ qcom,fab-dev;
+ qcom,base-name = "snoc-base";
+ qcom,base-offset = <0x7000>;
+ qcom,qos-off = <0x1000>;
+ qcom,bus-type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc SNOC_MSMBUS_CLK>,
+ <&rpmcc SNOC_MSMBUS_A_CLK>;
+ };
+
+ fab_snoc_mm: fab-snoc-mm {
+ cell-id = <MSM_BUS_FAB_MMSS_NOC>;
+ label = "fab-snoc-mm";
+ qcom,fab-dev;
+ qcom,base-name = "snoc-mm-base";
+ qcom,base-offset = <0x7000>;
+ qcom,qos-off = <0x1000>;
+ qcom,bus-type = <1>;
+ qcom,util-fact = <154>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc SYSMMNOC_MSMBUS_CLK>,
+ <&rpmcc SYSMMNOC_MSMBUS_A_CLK>;
+ };
+
+ /* BIMC Masters */
+ mas_apps_proc: mas-apps-proc {
+ cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
+ label = "mas-apps-proc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,prio-lvl = <0>;
+ qcom,prio-rd = <0>;
+ qcom,prio-wr = <0>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_APPSS_PROC>;
+ };
+
+ mas_oxili: mas-oxili {
+ cell-id = <MSM_BUS_MASTER_GRAPHICS_3D>;
+ label = "mas-oxili";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,prio-lvl = <0>;
+ qcom,prio-rd = <0>;
+ qcom,prio-wr = <0>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_GFX3D>;
+ };
+
+ mas_snoc_bimc_0: mas-snoc-bimc-0 {
+ cell-id = <MSM_BUS_SNOC_BIMC_0_MAS>;
+ label = "mas-snoc-bimc-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <3>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_0>;
+ };
+
+ mas_snoc_bimc_2: mas-snoc-bimc-2 {
+ cell-id = <MSM_BUS_SNOC_BIMC_2_MAS>;
+ label = "mas-snoc-bimc-2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <4>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_2>;
+ };
+
+ mas_snoc_bimc_1: mas-snoc-bimc-1 {
+ cell-id = <MSM_BUS_SNOC_BIMC_1_MAS>;
+ label = "mas-snoc-bimc-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <5>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_ebi>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_1>;
+ };
+
+ mas_tcu_0: mas-tcu-0 {
+ cell-id = <MSM_BUS_MASTER_TCU_0>;
+ label = "mas-tcu-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <6>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,prio-lvl = <2>;
+ qcom,prio-rd = <2>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_TCU_0>;
+ };
+
+ /* PCNOC Masters */
+ mas_spdm: mas-spdm {
+ cell-id = <MSM_BUS_MASTER_SPDM>;
+ label = "mas-spdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&pcnoc_m_0>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SPDM>;
+ };
+
+ mas_blsp_1: mas-blsp-1 {
+ cell-id = <MSM_BUS_MASTER_BLSP_1>;
+ label = "mas-blsp-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&pcnoc_m_1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BLSP_1>;
+ };
+
+ mas_blsp_2: mas-blsp-2 {
+ cell-id = <MSM_BUS_MASTER_BLSP_2>;
+ label = "mas-blsp-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&pcnoc_m_1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BLSP_2>;
+ };
+
+ mas_usb_hs1: mas-usb-hs1 {
+ cell-id = <MSM_BUS_MASTER_USB_HS>;
+ label = "mas-usb-hs1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <12>;
+ qcom,qos-mode = "fixed";
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,connections = <&pcnoc_int_0>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_USB_HS1>;
+ };
+
+ mas_xi_usb_hs1: mas-xi-usb-hs1 {
+ cell-id = <MSM_BUS_MASTER_XM_USB_HS1>;
+ label = "mas-xi-usb-hs1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <11>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&pcnoc_int_0>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_XI_USB_HS1>;
+ };
+
+ mas_crypto: mas-crypto {
+ cell-id = <MSM_BUS_MASTER_CRYPTO_CORE0>;
+ label = "mas-crypto";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&pcnoc_int_0>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO>;
+ };
+
+ mas_sdcc_1: mas-sdcc-1 {
+ cell-id = <MSM_BUS_MASTER_SDCC_1>;
+ label = "mas-sdcc-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <7>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&pcnoc_int_0>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SDCC_1>;
+ };
+
+ mas_sdcc_2: mas-sdcc-2 {
+ cell-id = <MSM_BUS_MASTER_SDCC_2>;
+ label = "mas-sdcc-2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <8>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&pcnoc_int_0>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SDCC_2>;
+ };
+
+ mas_snoc_pcnoc: mas-snoc-pcnoc {
+ cell-id = <MSM_BUS_SNOC_PNOC_MAS>;
+ label = "mas-snoc-pcnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <9>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&pcnoc_s_7
+ &pcnoc_int_2 &pcnoc_int_3>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_PCNOC>;
+ };
+
+ /* SNOC Masters */
+ mas_qdss_bam: mas-qdss-bam {
+ cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
+ label = "mas-qdss-bam";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <11>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&qdss_int>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAM>;
+ };
+
+ mas_bimc_snoc: mas-bimc-snoc {
+ cell-id = <MSM_BUS_BIMC_SNOC_MAS>;
+ label = "mas-bimc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&snoc_int_0
+ &snoc_int_1 &snoc_int_2>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BIMC_SNOC>;
+ };
+
+ mas_jpeg: mas-jpeg {
+ cell-id = <MSM_BUS_MASTER_JPEG>;
+ label = "mas-jpeg";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <6>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_snoc_bimc_2>;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,mas-rpm-id = <ICBID_MASTER_JPEG>;
+ };
+
+ mas_mdp: mas-mdp {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT0>;
+ label = "mas-mdp";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <7>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_snoc_bimc_0>;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,mas-rpm-id = <ICBID_MASTER_MDP>;
+ };
+
+ mas_pcnoc_snoc: mas-pcnoc-snoc {
+ cell-id = <MSM_BUS_PNOC_SNOC_MAS>;
+ label = "mas-pcnoc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <5>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&snoc_int_0
+ &snoc_int_1 &slv_snoc_bimc_1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PNOC_SNOC>;
+ qcom,blacklist = <&slv_snoc_pcnoc>;
+ };
+
+ mas_venus: mas-venus {
+ cell-id = <MSM_BUS_MASTER_VIDEO_P0>;
+ label = "mas-venus";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <8>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_snoc_bimc_2>;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VIDEO>;
+ };
+
+ mas_vfe0: mas-vfe0 {
+ cell-id = <MSM_BUS_MASTER_VFE>;
+ label = "mas-vfe0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <9>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_snoc_bimc_0>;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VFE>;
+ };
+
+ mas_vfe1: mas-vfe1 {
+ cell-id = <MSM_BUS_MASTER_VFE1>;
+ label = "mas-vfe1";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <13>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_snoc_bimc_0>;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VFE1>;
+ };
+
+ mas_cpp: mas-cpp {
+ cell-id = <MSM_BUS_MASTER_CPP>;
+ label = "mas-cpp";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <12>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_snoc_bimc_2>;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CPP>;
+ };
+
+ mas_qdss_etr: mas-qdss-etr {
+ cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
+ label = "mas-qdss-etr";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <10>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&qdss_int>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>;
+ };
+
+ /* Internal nodes */
+ pcnoc_m_0: pcnoc-m-0 {
+ cell-id = <MSM_BUS_PNOC_M_0>;
+ label = "pcnoc-m-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <5>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&pcnoc_int_0>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_0>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_0>;
+ };
+
+ pcnoc_m_1: pcnoc-m-1 {
+ cell-id = <MSM_BUS_PNOC_M_1>;
+ label = "pcnoc-m-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&pcnoc_int_0>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_1>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_1>;
+ };
+
+ pcnoc_int_0: pcnoc-int-0 {
+ cell-id = <MSM_BUS_PNOC_INT_0>;
+ label = "pcnoc-int-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_pcnoc_snoc
+ &pcnoc_s_7 &pcnoc_int_3 &pcnoc_int_2>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_0>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_0>;
+ };
+
+ pcnoc_int_1: pcnoc-int-1 {
+ cell-id = <MSM_BUS_PNOC_INT_1>;
+ label = "pcnoc-int-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_pcnoc_snoc
+ &pcnoc_s_7 &pcnoc_int_3 &pcnoc_int_2>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_1>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_1>;
+ };
+
+ pcnoc_int_2: pcnoc-int-2 {
+ cell-id = <MSM_BUS_PNOC_INT_2>;
+ label = "pcnoc-int-2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&pcnoc_s_2
+ &pcnoc_s_3 &pcnoc_s_6 &pcnoc_s_8>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_2>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_2>;
+ };
+
+ pcnoc_int_3: pcnoc-int-3 {
+ cell-id = <MSM_BUS_PNOC_INT_3>;
+ label = "pcnoc-int-3";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = < &pcnoc_s_1 &pcnoc_s_0 &pcnoc_s_4
+ &slv_gpu_cfg &slv_tcu >;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_3>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_3>;
+ };
+
+ pcnoc_s_0: pcnoc-s-0 {
+ cell-id = <MSM_BUS_PNOC_SLV_0>;
+ label = "pcnoc-s-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_spdm &slv_pdm &slv_prng
+ &slv_sdcc_2>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_0>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_0>;
+ };
+
+ pcnoc_s_1: pcnoc-s-1 {
+ cell-id = <MSM_BUS_PNOC_SLV_1>;
+ label = "pcnoc-s-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_tcsr>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_1>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_1>;
+ };
+
+ pcnoc_s_2: pcnoc-s-2 {
+ cell-id = <MSM_BUS_PNOC_SLV_2>;
+ label = "pcnoc-s-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_snoc_cfg>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_2>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_2>;
+ };
+
+ pcnoc_s_3: pcnoc-s-3 {
+ cell-id = <MSM_BUS_PNOC_SLV_3>;
+ label = "pcnoc-s-3";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_message_ram>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_3>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_3>;
+ };
+
+ pcnoc_s_4: pcnoc-s-4 {
+ cell-id = <MSM_BUS_PNOC_SLV_4>;
+ label = "pcnoc-s-4";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_camera_ss_cfg
+ &slv_disp_ss_cfg &slv_venus_cfg>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_4>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_4>;
+ };
+
+ pcnoc_s_6: pcnoc-s-6 {
+ cell-id = <MSM_BUS_PNOC_SLV_6>;
+ label = "pcnoc-s-6";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_tlmm &slv_blsp_1 &slv_blsp_2>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_6>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_6>;
+ };
+
+ pcnoc_s_7: pcnoc-s-7 {
+ cell-id = <MSM_BUS_PNOC_SLV_7>;
+ label = "pcnoc-s-7";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = < &slv_sdcc_1 &slv_pmic_arb>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_7>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_7>;
+ };
+
+ pcnoc_s_8: pcnoc-s-8 {
+ cell-id = <MSM_BUS_PNOC_SLV_8>;
+ label = "pcnoc-s-8";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_usb_hs &slv_crypto_0_cfg>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_8>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_8>;
+ };
+
+ qdss_int: qdss-int {
+ cell-id = <MSM_BUS_SNOC_QDSS_INT>;
+ label = "qdss-int";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&snoc_int_1 &slv_snoc_bimc_1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_INT>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_INT>;
+ };
+
+ snoc_int_0: snoc-int-0 {
+ cell-id = <MSM_BUS_SNOC_INT_0>;
+ label = "snoc-int-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_lpass
+ &slv_wcss &slv_kpss_ahb>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_0>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_0>;
+ };
+
+ snoc_int_1: snoc-int-1 {
+ cell-id = <MSM_BUS_SNOC_INT_1>;
+ label = "snoc-int-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qdss_stm
+ &slv_imem &slv_snoc_pcnoc>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_1>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_1>;
+ };
+
+ snoc_int_2: snoc-int-2 {
+ cell-id = <MSM_BUS_SNOC_INT_2>;
+ label = "snoc-int-2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_cats_0 &slv_cats_1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_2>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_2>;
+ };
+
+ /* Slaves */
+ slv_ebi:slv-ebi {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ label = "slv-ebi";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_EBI1>;
+ };
+
+ slv_bimc_snoc:slv-bimc-snoc {
+ cell-id = <MSM_BUS_BIMC_SNOC_SLV>;
+ label = "slv-bimc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,connections = <&mas_bimc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_SNOC>;
+ };
+
+ slv_sdcc_2:slv-sdcc-2 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_2>;
+ label = "slv-sdcc-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_2>;
+ };
+
+ slv_spdm:slv-spdm {
+ cell-id = <MSM_BUS_SLAVE_SPDM_WRAPPER>;
+ label = "slv-spdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SPDM_WRAPPER>;
+ };
+
+ slv_pdm:slv-pdm {
+ cell-id = <MSM_BUS_SLAVE_PDM>;
+ label = "slv-pdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PDM>;
+ };
+
+ slv_prng:slv-prng {
+ cell-id = <MSM_BUS_SLAVE_PRNG>;
+ label = "slv-prng";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>;
+ };
+
+ slv_tcsr:slv-tcsr {
+ cell-id = <MSM_BUS_SLAVE_TCSR>;
+ label = "slv-tcsr";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>;
+ };
+
+ slv_snoc_cfg:slv-snoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
+ label = "slv-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CFG>;
+ };
+
+ slv_message_ram:slv-message-ram {
+ cell-id = <MSM_BUS_SLAVE_MESSAGE_RAM>;
+ label = "slv-message-ram";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MESSAGE_RAM>;
+ };
+
+ slv_camera_ss_cfg:slv-camera-ss-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_CFG>;
+ label = "slv-camera-ss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_CFG>;
+ };
+
+ slv_disp_ss_cfg:slv-disp-ss-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_CFG>;
+ label = "slv-disp-ss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_CFG>;
+ };
+
+ slv_venus_cfg:slv-venus-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_CFG>;
+ label = "slv-venus-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_CFG>;
+ };
+
+ slv_gpu_cfg:slv-gpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_GRAPHICS_3D_CFG>;
+ label = "slv-gpu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GFX3D_CFG>;
+ };
+
+ slv_tlmm:slv-tlmm {
+ cell-id = <MSM_BUS_SLAVE_TLMM>;
+ label = "slv-tlmm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TLMM>;
+ };
+
+ slv_blsp_1:slv-blsp-1 {
+ cell-id = <MSM_BUS_SLAVE_BLSP_1>;
+ label = "slv-blsp-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_1>;
+ };
+
+ slv_blsp_2:slv-blsp-2 {
+ cell-id = <MSM_BUS_SLAVE_BLSP_2>;
+ label = "slv-blsp-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_2>;
+ };
+
+ slv_pmic_arb:slv-pmic-arb {
+ cell-id = <MSM_BUS_SLAVE_PMIC_ARB>;
+ label = "slv-pmic-arb";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PMIC_ARB>;
+ };
+
+ slv_sdcc_1:slv-sdcc-1 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_1>;
+ label = "slv-sdcc-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_1>;
+ };
+
+ slv_crypto_0_cfg:slv-crypto-0-cfg {
+ cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>;
+ label = "slv-crypto-0-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CRYPTO_0_CFG>;
+ };
+
+ slv_usb_hs:slv-usb-hs {
+ cell-id = <MSM_BUS_SLAVE_USB_HS>;
+ label = "slv-usb-hs";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_USB_HS>;
+ };
+
+ slv_tcu:slv-tcu {
+ cell-id = <MSM_BUS_SLAVE_TCU>;
+ label = "slv-tcu";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TCU>;
+ };
+
+ slv_pcnoc_snoc:slv-pcnoc-snoc {
+ cell-id = <MSM_BUS_PNOC_SNOC_SLV>;
+ label = "slv-pcnoc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,connections = <&mas_pcnoc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_SNOC>;
+ };
+
+ slv_kpss_ahb:slv-kpss-ahb {
+ cell-id = <MSM_BUS_SLAVE_APPSS>;
+ label = "slv-kpss-ahb";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_APPSS>;
+ };
+
+ slv_wcss:slv-wcss {
+ cell-id = <MSM_BUS_SLAVE_WCSS>;
+ label = "slv-wcss";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_WCSS>;
+ };
+
+ slv_snoc_bimc_0:slv-snoc-bimc-0 {
+ cell-id = <MSM_BUS_SNOC_BIMC_0_SLV>;
+ label = "slv-snoc-bimc-0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,connections = <&mas_snoc_bimc_0>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_0>;
+ };
+
+ slv_snoc_bimc_1:slv-snoc-bimc-1 {
+ cell-id = <MSM_BUS_SNOC_BIMC_1_SLV>;
+ label = "slv-snoc-bimc-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,connections = <&mas_snoc_bimc_1>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_1>;
+ };
+
+ slv_snoc_bimc_2:slv-snoc-bimc-2 {
+ cell-id = <MSM_BUS_SNOC_BIMC_2_SLV>;
+ label = "slv-snoc-bimc-2";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,connections = <&mas_snoc_bimc_2>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_2>;
+ };
+
+ slv_imem:slv-imem {
+ cell-id = <MSM_BUS_SLAVE_OCIMEM>;
+ label = "slv-imem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IMEM>;
+ };
+
+ slv_snoc_pcnoc:slv-snoc-pcnoc {
+ cell-id = <MSM_BUS_SNOC_PNOC_SLV>;
+ label = "slv-snoc-pcnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,connections = <&mas_snoc_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_PCNOC>;
+ };
+
+ slv_qdss_stm:slv-qdss-stm {
+ cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
+ label = "slv-qdss-stm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>;
+ };
+
+ slv_cats_0:slv-cats-0 {
+ cell-id = <MSM_BUS_SLAVE_CATS_128>;
+ label = "slv-cats-0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CATS_0>;
+ };
+
+ slv_cats_1:slv-cats-1 {
+ cell-id = <MSM_BUS_SLAVE_OCMEM_64>;
+ label = "slv-cats-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CATS_1>;
+ };
+
+ slv_lpass:slv-lpass {
+ cell-id = <MSM_BUS_SLAVE_LPASS>;
+ label = "slv-lpass";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_LPASS>;
+ };
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-camera-pinctrl.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-camera-pinctrl.dtsi
new file mode 100755
index 0000000..3f7bc45
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-camera-pinctrl.dtsi
@@ -0,0 +1,292 @@
+cci {
+ cci0_active: cci0_active {
+ /* cci0 active state */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio29", "gpio30";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio29", "gpio30";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable; /* No PULL */
+ };
+ };
+
+ cci0_suspend: cci0_suspend {
+ /* cci0 suspended state */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio29", "gpio30";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio29", "gpio30";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable; /* No PULL */
+ };
+ };
+
+ cci1_active: cci1_active {
+ /* cci1 active state */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio31", "gpio32";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio31", "gpio32";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable; /* No PULL */
+ };
+ };
+
+ cci1_suspend: cci1_suspend {
+ /* cci1 suspended state */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio31", "gpio32";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio31", "gpio32";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable; /* No PULL */
+ };
+ };
+};
+
+/*sensors */
+cam_sensor_mclk0_default: cam_sensor_mclk0_default {
+ /* MCLK0 */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio26";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio26";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_mclk0_sleep: cam_sensor_mclk0_sleep {
+ /* MCLK0 */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio26";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio26";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_rear_default: cam_sensor_rear_default {
+ /* RESET, STANDBY */
+ mux {
+ pins = "gpio36", "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio36","gpio35";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_rear_sleep: cam_sensor_rear_sleep {
+ /* RESET, STANDBY */
+ mux {
+ pins = "gpio36","gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio36","gpio35";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_rear_vdig: cam_sensor_rear_vdig {
+ /* VDIG */
+ mux {
+ pins = "gpio62";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio62";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_rear_vdig_sleep: cam_sensor_rear_vdig_sleep {
+ /* VDIG */
+ mux {
+ pins = "gpio62";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio62";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_rear_vdig_qm215: cam_sensor_rear_vdig_qm215 {
+ /* VDIG */
+ mux {
+ pins = "gpio25";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio25";
+ output-high;
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_rear_vdig_sleep_qm215: cam_sensor_rear_vdig_sleep_qm215 {
+ /* VDIG */
+ mux {
+ pins = "gpio25";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio25";
+ output-low;
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_mclk1_default: cam_sensor_mclk1_default {
+ /* MCLK1 */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio27";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio27";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_mclk1_sleep: cam_sensor_mclk1_sleep {
+ /* MCLK1 */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio27";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio27";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_front_default: cam_sensor_front_default {
+ /* RESET, STANDBY */
+ mux {
+ pins = "gpio38","gpio50";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio38","gpio50";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_front_sleep: cam_sensor_front_sleep {
+ /* RESET, STANDBY */
+ mux {
+ pins = "gpio38","gpio50";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio38","gpio50";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_mclk2_default: cam_sensor_mclk2_default {
+ /* MCLK2 */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio28";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio28";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_mclk2_sleep: cam_sensor_mclk2_sleep {
+ /* MCLK2 */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio28";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio28";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_front1_default: cam_sensor_front1_default {
+ /* RESET, STANDBY */
+ mux {
+ pins = "gpio40", "gpio39";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio40", "gpio39";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+};
+
+cam_sensor_front1_sleep: cam_sensor_front1_sleep {
+ /* RESET, STANDBY */
+ mux {
+ pins = "gpio40", "gpio39";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio40", "gpio39";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-camera.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-camera.dtsi
new file mode 100755
index 0000000..4bd8513
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-camera.dtsi
@@ -0,0 +1,508 @@
+&soc {
+ qcom,msm-cam@1b00000 {
+ compatible = "qcom,msm-cam";
+ reg = <0x1b00000 0x40000>;
+ reg-names = "msm-cam";
+ status = "ok";
+ bus-vectors = "suspend", "svs", "nominal", "turbo";
+ qcom,bus-votes = <0 160000000 320000000 320000000>;
+ };
+
+ qcom,csiphy@1b34000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy";
+ reg = <0x1b34000 0x1000>,
+ <0x1b00030 0x4>;
+ reg-names = "csiphy", "csiphy_clk_mux";
+ interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csiphy";
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc CSI0PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
+ <&gcc CAMSS_TOP_AHB_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI0PHY_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",
+ "csiphy_timer_src_clk", "csiphy_timer_clk",
+ "camss_ahb_src", "csi_phy_clk",
+ "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 200000000 0 0 0 0>;
+ };
+
+ qcom,csiphy@1b35000 {
+ status = "ok";
+ cell-index = <1>;
+ compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy";
+ reg = <0x1b35000 0x1000>,
+ <0x1b00038 0x4>;
+ reg-names = "csiphy", "csiphy_clk_mux";
+ interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csiphy";
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc CSI1PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
+ <&gcc CAMSS_TOP_AHB_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI1PHY_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",
+ "csiphy_timer_src_clk", "csiphy_timer_clk",
+ "camss_ahb_src", "csi_phy_clk",
+ "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 200000000 0 0 0 0>;
+ };
+
+ qcom,csid@1b30000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,csid-v3.4.3", "qcom,csid";
+ reg = <0x1b30000 0x400>;
+ reg-names = "csid";
+ interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid";
+ qcom,csi-vdd-voltage = <1200000>;
+ qcom,mipi-csi-vdd-supply = <&pm8937_l2>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
+ <&gcc CSI0_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI0RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk",
+ "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",
+ "csi_clk", "csi_pix_clk",
+ "csi_rdi_clk", "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0>;
+ };
+
+ qcom,csid@1b30400 {
+ status = "ok";
+ cell-index = <1>;
+ compatible = "qcom,csid-v3.4.3", "qcom,csid";
+ reg = <0x1b30400 0x400>;
+ reg-names = "csid";
+ interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid";
+ qcom,csi-vdd-voltage = <1200000>;
+ qcom,mipi-csi-vdd-supply = <&pm8937_l2>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
+ <&gcc CSI1_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI1RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk",
+ "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",
+ "csi_clk", "csi_pix_clk",
+ "csi_rdi_clk", "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0>;
+ };
+
+ qcom,csid@1b30800 {
+ status = "ok";
+ cell-index = <2>;
+ compatible = "qcom,csid-v3.4.3", "qcom,csid";
+ reg = <0x1b30800 0x400>;
+ reg-names = "csid";
+ interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid";
+ qcom,csi-vdd-voltage = <1200000>;
+ qcom,mipi-csi-vdd-supply = <&pm8937_l2>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI2_AHB_CLK>,
+ <&gcc CSI2_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI2_CLK>,
+ <&gcc GCC_CAMSS_CSI2PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI2RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk",
+ "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",
+ "csi_clk", "csi_pix_clk",
+ "csi_rdi_clk", "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0>;
+ };
+
+ qcom,ispif@1b31000 {
+ cell-index = <0>;
+ compatible = "qcom,ispif-v3.0", "qcom,ispif";
+ reg = <0x1b31000 0x500>,
+ <0x1b00020 0x10>;
+ reg-names = "ispif", "csi_clk_mux";
+ interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ispif";
+ qcom,num-isps = <0x2>;
+ vfe0-vdd-supply = <&gdsc_vfe>;
+ vfe1-vdd-supply = <&gdsc_vfe1>;
+ qcom,vdd-names = "vfe0-vdd", "vfe1-vdd";
+ clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc CAMSS_TOP_AHB_CLK_SRC>,
+ <&gcc CSI0_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI0_CLK>,
+ <&gcc GCC_CAMSS_CSI0RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI0PIX_CLK>,
+ <&gcc CSI1_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI1_CLK>,
+ <&gcc GCC_CAMSS_CSI1RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI1PIX_CLK>,
+ <&gcc CSI2_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI2_CLK>,
+ <&gcc GCC_CAMSS_CSI2RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI2PIX_CLK>,
+ <&gcc VFE0_CLK_SRC>,
+ <&gcc GCC_CAMSS_VFE0_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
+ <&gcc VFE1_CLK_SRC>,
+ <&gcc GCC_CAMSS_VFE1_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE1_CLK>;
+ clock-names = "ispif_ahb_clk",
+ "camss_ahb_clk", "camss_top_ahb_clk",
+ "camss_ahb_src",
+ "csi0_src_clk", "csi0_clk",
+ "csi0_rdi_clk", "csi0_pix_clk",
+ "csi1_src_clk", "csi1_clk",
+ "csi1_rdi_clk", "csi1_pix_clk",
+ "csi2_src_clk", "csi2_clk",
+ "csi2_rdi_clk", "csi2_pix_clk",
+ "vfe0_clk_src", "camss_vfe_vfe0_clk",
+ "camss_csi_vfe0_clk", "vfe1_clk_src",
+ "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";
+ qcom,clock-rates = <61540000 0 0 0
+ 200000000 0 0 0
+ 200000000 0 0 0
+ 200000000 0 0 0
+ 0 0 0
+ 0 0 0>;
+ qcom,clock-cntl-support;
+ qcom,clock-control = "SET_RATE","NO_SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "NO_SET_RATE", "SET_RATE",
+ "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
+ "SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE",
+ "NO_SET_RATE";
+ };
+
+ vfe0: qcom,vfe0@1b10000 {
+ cell-index = <0>;
+ compatible = "qcom,vfe40";
+ reg = <0x1b10000 0x1000>,
+ <0x1b40000 0x200>;
+ reg-names = "vfe", "vfe_vbif";
+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vfe";
+ vdd-supply = <&gdsc_vfe>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc VFE0_CLK_SRC>,
+ <&gcc GCC_CAMSS_VFE0_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
+ <&gcc GCC_CAMSS_VFE_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE_AXI_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk", "camss_ahb_clk",
+ "vfe_clk_src", "camss_vfe_vfe_clk",
+ "camss_csi_vfe_clk", "iface_clk",
+ "bus_clk", "iface_ahb_clk";
+ qcom,clock-rates = <0 0 266670000 0 0 0 0 0>;
+ qos-entries = <8>;
+ qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8
+ 0x2dc 0x2e0>;
+ qos-settings = <0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55>;
+ vbif-entries = <1>;
+ vbif-regs = <0x124>;
+ vbif-settings = <0x3>;
+ ds-entries = <17>;
+ ds-regs = <0x988 0x98c 0x990 0x994 0x998
+ 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0
+ 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>;
+ ds-settings = <0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0x00000110>;
+ max-clk-nominal = <400000000>;
+ max-clk-turbo = <432000000>;
+ };
+
+ vfe1: qcom,vfe1@1b14000 {
+ cell-index = <1>;
+ compatible = "qcom,vfe40";
+ reg = <0x1b14000 0x1000>,
+ <0x1ba0000 0x200>;
+ reg-names = "vfe", "vfe_vbif";
+ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vfe";
+ vdd-supply = <&gdsc_vfe1>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc VFE1_CLK_SRC>,
+ <&gcc GCC_CAMSS_VFE1_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE1_CLK>,
+ <&gcc GCC_CAMSS_VFE1_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE1_AXI_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk" , "camss_ahb_clk",
+ "vfe_clk_src", "camss_vfe_vfe_clk",
+ "camss_csi_vfe_clk", "iface_clk",
+ "bus_clk", "iface_ahb_clk";
+ qcom,clock-rates = <0 0 266670000 0 0 0 0 0>;
+ qos-entries = <8>;
+ qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8
+ 0x2dc 0x2e0>;
+ qos-settings = <0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55>;
+ vbif-entries = <1>;
+ vbif-regs = <0x124>;
+ vbif-settings = <0x3>;
+ ds-entries = <17>;
+ ds-regs = <0x988 0x98c 0x990 0x994 0x998
+ 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0
+ 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>;
+ ds-settings = <0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0x00000110>;
+ max-clk-nominal = <400000000>;
+ max-clk-turbo = <432000000>;
+ };
+
+ qcom,vfe {
+ compatible = "qcom,vfe";
+ num_child = <2>;
+ };
+
+ qcom,cam_smmu {
+ status = "ok";
+ compatible = "qcom,msm-cam-smmu";
+ msm_cam_smmu_cb1: msm_cam_smmu_cb1 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_iommu 0x400 0x00>,
+ <&apps_iommu 0x2400 0x00>;
+ label = "vfe";
+ qcom,scratch-buf-support;
+ };
+
+ msm_cam_smmu_cb3: msm_cam_smmu_cb3 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_iommu 0x1c00 0x00>;
+ label = "cpp";
+ };
+
+ msm_cam_smmu_cb4: msm_cam_smmu_cb4 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_iommu 0x1800 0x00>;
+ label = "jpeg_enc0";
+ };
+ };
+
+ qcom,jpeg@1b1c000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,jpeg";
+ reg = <0x1b1c000 0x400>,
+ <0x1b60000 0xc30>;
+ reg-names = "jpeg_hw", "jpeg_vbif";
+ interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "jpeg";
+ vdd-supply = <&gdsc_jpeg>;
+ qcom,vdd-names = "vdd";
+ clock-names = "core_clk", "iface_clk", "bus_clk0",
+ "camss_top_ahb_clk", "camss_ahb_clk";
+ clocks = <&gcc GCC_CAMSS_JPEG0_CLK>,
+ <&gcc GCC_CAMSS_JPEG_AHB_CLK>,
+ <&gcc GCC_CAMSS_JPEG_AXI_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ qcom,clock-rates = <266670000 0 0 0 0>;
+ qcom,qos-reg-settings = <0x28 0x0000555e>,
+ <0xc8 0x00005555>;
+ qcom,msm-bus,name = "msm_camera_jpeg0";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <62 512 0 0>,
+ <62 512 800000 800000>;
+ qcom,vbif-reg-settings = <0xc0 0x10101000>,
+ <0xb0 0x10100010>;
+ };
+
+ qcom,cpp@1b04000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,cpp";
+ reg = <0x1b04000 0x100>,
+ <0x1b80000 0x200>,
+ <0x1b18000 0x018>,
+ <0x1858078 0x4>;
+ reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp";
+ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpp";
+ vdd-supply = <&gdsc_cpp>;
+ qcom,vdd-names = "vdd";
+ clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc CPP_CLK_SRC>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_CPP_AHB_CLK>,
+ <&gcc GCC_CAMSS_CPP_AXI_CLK>,
+ <&gcc GCC_CAMSS_CPP_CLK>,
+ <&gcc GCC_CAMSS_MICRO_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "ispif_ahb_clk", "cpp_core_clk",
+ "camss_top_ahb_clk", "camss_vfe_cpp_ahb_clk",
+ "camss_vfe_cpp_axi_clk", "camss_vfe_cpp_clk",
+ "micro_iface_clk", "camss_ahb_clk";
+ qcom,clock-rates = <61540000 180000000 0 0 0 180000000 0 0>;
+ qcom,min-clock-rate = <133000000>;
+ resets = <&gcc GCC_CAMSS_MICRO_BCR>;
+ reset-names = "micro_iface_reset";
+ qcom,bus-master = <1>;
+ qcom,msm-bus,name = "msm_camera_cpp";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <106 512 0 0>,
+ <106 512 0 0>;
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,micro-reset;
+ qcom,cpp-fw-payload-info {
+ qcom,stripe-base = <156>;
+ qcom,plane-base = <141>;
+ qcom,stripe-size = <27>;
+ qcom,plane-size = <5>;
+ qcom,fe-ptr-off = <5>;
+ qcom,we-ptr-off = <11>;
+ };
+ };
+
+ cci: qcom,cci@1b0c000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,cci";
+ reg = <0x1b0c000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "cci";
+ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cci";
+ clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc CCI_CLK_SRC>,
+ <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>;
+ clock-names = "ispif_ahb_clk", "cci_src_clk",
+ "cci_ahb_clk", "camss_cci_clk",
+ "camss_ahb_clk", "camss_top_ahb_clk";
+ qcom,clock-rates = <61540000 19200000 0 0 0 0>,
+ <61540000 37500000 0 0 0 0>;
+ pinctrl-names = "cci_default", "cci_suspend";
+ pinctrl-0 = <&cci0_active &cci1_active>;
+ pinctrl-1 = <&cci0_suspend &cci1_suspend>;
+ gpios = <&tlmm 29 0>,
+ <&tlmm 30 0>,
+ <&tlmm 31 0>,
+ <&tlmm 32 0>;
+ qcom,gpio-tbl-num = <0 1 2 3>;
+ qcom,gpio-tbl-flags = <1 1 1 1>;
+ qcom,gpio-tbl-label = "CCI_I2C_DATA0",
+ "CCI_I2C_CLK0",
+ "CCI_I2C_DATA1",
+ "CCI_I2C_CLK1";
+ i2c_freq_100Khz: qcom,i2c_standard_mode {
+ status = "disabled";
+ };
+
+ i2c_freq_400Khz: qcom,i2c_fast_mode {
+ status = "disabled";
+ };
+
+ i2c_freq_custom: qcom,i2c_custom_mode {
+ status = "disabled";
+ };
+
+ i2c_freq_1Mhz: qcom,i2c_fast_plus_mode {
+ status = "disabled";
+ };
+ };
+};
+
+&i2c_freq_100Khz {
+ qcom,hw-thigh = <78>;
+ qcom,hw-tlow = <114>;
+ qcom,hw-tsu-sto = <28>;
+ qcom,hw-tsu-sta = <28>;
+ qcom,hw-thd-dat = <10>;
+ qcom,hw-thd-sta = <77>;
+ qcom,hw-tbuf = <118>;
+ qcom,hw-scl-stretch-en = <0>;
+ qcom,hw-trdhld = <6>;
+ qcom,hw-tsp = <1>;
+};
+
+&i2c_freq_400Khz {
+ qcom,hw-thigh = <20>;
+ qcom,hw-tlow = <28>;
+ qcom,hw-tsu-sto = <21>;
+ qcom,hw-tsu-sta = <21>;
+ qcom,hw-thd-dat = <13>;
+ qcom,hw-thd-sta = <18>;
+ qcom,hw-tbuf = <32>;
+ qcom,hw-scl-stretch-en = <0>;
+ qcom,hw-trdhld = <6>;
+ qcom,hw-tsp = <3>;
+ status = "ok";
+};
+
+&i2c_freq_custom {
+ qcom,hw-thigh = <15>;
+ qcom,hw-tlow = <28>;
+ qcom,hw-tsu-sto = <21>;
+ qcom,hw-tsu-sta = <21>;
+ qcom,hw-thd-dat = <13>;
+ qcom,hw-thd-sta = <18>;
+ qcom,hw-tbuf = <25>;
+ qcom,hw-scl-stretch-en = <1>;
+ qcom,hw-trdhld = <6>;
+ qcom,hw-tsp = <3>;
+ status = "ok";
+};
+
+&i2c_freq_1Mhz {
+ qcom,hw-thigh = <16>;
+ qcom,hw-tlow = <22>;
+ qcom,hw-tsu-sto = <17>;
+ qcom,hw-tsu-sta = <18>;
+ qcom,hw-thd-dat = <16>;
+ qcom,hw-thd-sta = <15>;
+ qcom,hw-tbuf = <19>;
+ qcom,hw-scl-stretch-en = <1>;
+ qcom,hw-trdhld = <3>;
+ qcom,hw-tsp = <3>;
+ qcom,cci-clk-src = <37500000>;
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-coresight.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-coresight.dtsi
new file mode 100755
index 0000000..d40e3b5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-coresight.dtsi
@@ -0,0 +1,31 @@
+#include "msm8937-coresight.dtsi"
+
+&funnel_apss {
+ ports {
+ /delete-node/ port@1;
+ /delete-node/ port@2;
+ /delete-node/ port@3;
+ /delete-node/ port@4;
+ };
+};
+
+&funnel_mm {
+ ports {
+ /delete-node/ port@4;
+ };
+};
+
+&soc {
+ /delete-node/ etm@619c000;
+ /delete-node/ etm@619d000;
+ /delete-node/ etm@619e000;
+ /delete-node/ etm@619f000;
+ /delete-node/ cti@6198000;
+ /delete-node/ cti@6199000;
+ /delete-node/ cti@619a000;
+ /delete-node/ cti@619b000;
+};
+
+&dbgui {
+ qcom,dbgui-size = <32>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-cpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-cpu.dtsi
new file mode 100755
index 0000000..71cb09d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-cpu.dtsi
@@ -0,0 +1,132 @@
+/ {
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu-map {
+
+ cluster0 {
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+ };
+
+ CPU0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_0>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L2_1: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ };
+
+ L1_I_100: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_100: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_0>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L1_I_101: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_101: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU2: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x102>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_0>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L1_I_102: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_102: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU3: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x103>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_0>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L1_I_103: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_103: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ };
+
+ energy_costs: energy-costs {
+
+ CPU_COST_0: core-cost0 {
+ busy-cost-data = <
+ 656 159
+ 682 172
+ 748 207
+ 827 244
+ 853 256
+ 893 283
+ 958 327
+ 1024 343
+ >;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-gpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-gpu.dtsi
new file mode 100755
index 0000000..aa7d410
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-gpu.dtsi
@@ -0,0 +1,183 @@
+&soc {
+ msm_bus: qcom,kgsl-busmon {
+ label = "kgsl-busmon";
+ compatible = "qcom,kgsl-busmon";
+ };
+
+ gpu_bw_tbl: gpu-bw-tbl {
+ compatible = "operating-points-v2";
+ opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */
+
+ opp-100 { opp-hz = /bits/ 64 < 769 >; }; /* 1. 100 MHz */
+
+ opp-211 { opp-hz = /bits/ 64 < 1611 >; }; /* 2. 211 MHz */
+
+ opp-297 { opp-hz = /bits/ 64 < 2270 >; }; /* 3. 297 MHz */
+
+ opp-384 { opp-hz = /bits/ 64 < 2929 >; }; /* 4. 384 MHz */
+
+ opp-557 { opp-hz = /bits/ 64 < 4248 >; }; /* 5. 557 MHz */
+
+ opp-595 { opp-hz = /bits/ 64 < 4541 >; }; /* 6. 595 MHz */
+
+ opp-672 { opp-hz = /bits/ 64 < 5126 >; }; /* 7. 672 MHz */
+
+ opp-739 { opp-hz = /bits/ 64 < 5639 >; }; /* 8. 739 MHz */
+ };
+
+ /* Bus governor */
+ gpubw: qcom,gpubw {
+ compatible = "qcom,devbw";
+ governor = "bw_vbif";
+ qcom,src-dst-ports = <26 512>;
+ operating-points-v2 = <&gpu_bw_tbl>;
+ qcom,active-only;
+ };
+
+ msm_gpu: qcom,kgsl-3d0@1c00000 {
+ label = "kgsl-3d0";
+ compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
+ reg = <0x1c00000 0x10000
+ 0x1c10000 0x10000
+ 0x00a0000 0x06fff>;
+ reg-names = "kgsl_3d0_reg_memory" , "kgsl_3d0_shader_memory",
+ "qfprom_memory";
+ interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+ qcom,id = <0>;
+
+ qcom,chipid = <0x03000620>;
+
+ qcom,initial-pwrlevel = <3>;
+
+ qcom,idle-timeout = <80>; //msecs
+ qcom,strtstp-sleepwake;
+ qcom,gpu-bimc-interface-clk-freq = <400000000>; //In Hz
+
+ clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
+ <&gcc GCC_OXILI_AHB_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>,
+ <&gcc GCC_BIMC_GPU_CLK>,
+ <&gcc GCC_GTCU_AHB_CLK>,
+ <&gcc GCC_GFX_TCU_CLK>,
+ <&gcc GCC_GFX_TBU_CLK>,
+ <&rpmcc RPM_SMD_BIMC_GPU_CLK>;
+
+ clock-names = "core_clk", "iface_clk", "mem_iface_clk",
+ "alt_mem_iface_clk", "gtcu_iface_clk",
+ "gtcu_clk", "gtbu_clk", "bimc_gpu_clk";
+
+ /* Bus Scale Settings */
+ qcom,gpubw-dev = <&gpubw>;
+ qcom,bus-control;
+ qcom,bus-width = <16>;
+ qcom,msm-bus,name = "grp3d";
+ qcom,msm-bus,num-cases = <9>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <26 512 0 0>, /* off */
+ <26 512 0 806400>, /* 1. 100.80 MHz */
+ <26 512 0 1689600>, /* 2. 211.20 MHz */
+ <26 512 0 2380800>, /* 3. 297.60 MHz */
+ <26 512 0 3072000>, /* 4. 384.00 MHz */
+ <26 512 0 4454400>, /* 5. 556.80 MHz */
+ <26 512 0 4761600>, /* 6. 595.20 MHz */
+ <26 512 0 5376000>, /* 7. 672.00 MHz */
+ <26 512 0 5913600>; /* 8. 739.20 MHz */
+
+ /* GDSC regulator names */
+ regulator-names = "vdd";
+ /* GDSC oxili regulators */
+ vdd-supply = <&gdsc_oxili_gx>;
+
+ /* CPU latency parameter */
+ qcom,pm-qos-active-latency = <651>;
+
+ /* Enable gpu cooling device */
+ #cooling-cells = <2>;
+
+ /* Power levels */
+ qcom,gpu-pwrlevels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "qcom,gpu-pwrlevels";
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <598000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <7>;
+ };
+
+ /* NOM+ */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <523200000>;
+ qcom,bus-freq = <6>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <484800000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <6>;
+ };
+
+ /* SVS+ */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <270000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <1>;
+ qcom,bus-max = <3>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+};
+
+ kgsl_msm_iommu: qcom,kgsl-iommu@1f00000 {
+ compatible = "qcom,kgsl-smmu-v2";
+ reg = <0x1f00000 0x10000>;
+ /*
+ * The gpu can only program a single context bank
+ * at this fixed offset.
+ */
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_GFX_TCU_CLK>,
+ <&gcc GCC_GTCU_AHB_CLK>,
+ <&gcc GCC_GFX_TBU_CLK>;
+ clock-names = "scfg_clk", "gtcu_clk", "gtcu_iface_clk",
+ "gtbu_clk";
+ qcom,retention;
+ gfx3d_user: gfx3d_user {
+ compatible = "qcom,smmu-kgsl-cb";
+ iommus = <&gfx_iommu 0>;
+ qcom,iommu-dma = "disabled";
+ qcom,gpu-offset = <0xa000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-ion.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-ion.dtsi
new file mode 100755
index 0000000..5ad5c15
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-ion.dtsi
@@ -0,0 +1,24 @@
+&soc {
+ qcom,ion {
+ compatible = "qcom,msm-ion";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ion-heap@25 {
+ reg = <25>;
+ qcom,ion-heap-type = "SYSTEM";
+ };
+
+ qcom,ion-heap@27 { /* QSEECOM HEAP */
+ reg = <27>;
+ memory-region = <&qseecom_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@19 { /* QSEECOM TA HEAP */
+ reg = <19>;
+ memory-region = <&qseecom_ta_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-mdss-pll.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-mdss-pll.dtsi
new file mode 100755
index 0000000..1519024
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-mdss-pll.dtsi
@@ -0,0 +1,7 @@
+#include "msm8937-mdss-pll.dtsi"
+
+&mdss_dsi0_pll {
+ vddio-supply = <&pm8937_l6>;
+};
+
+/delete-node/ &mdss_dsi1_pll;
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-mdss.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-mdss.dtsi
new file mode 100755
index 0000000..0f2e80e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-mdss.dtsi
@@ -0,0 +1,83 @@
+#include "msm8937-mdss.dtsi"
+&mdss_dsi {
+ vdda-supply = <&pm8937_l2>;
+ vddio-supply = <&pm8937_l6>;
+
+ ranges = <0x1a94000 0x1a94000 0x300
+ 0x1a94400 0x1a94400 0x280
+ 0x1a94b80 0x1a94b80 0x30
+ 0x193e000 0x193e000 0x30>;
+
+ clocks = <&gcc_mdss MDSS_MDP_VOTE_CLK>,
+ <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll PCLK_SRC_0_CLK>;
+ clock-names = "mdp_core_clk", "iface_clk", "bus_clk",
+ "ext_byte0_clk", "ext_pixel0_clk";
+
+ /delete-property/ qcom,mdss-fb-map-sec;
+
+};
+
+&mdss_dsi0 {
+ vdd-supply = <&pm8937_l17>;
+ vddio-supply = <&pm8937_l6>;
+};
+
+/delete-node/ &mdss_dsi1;
+
+&mdss_mdp {
+ qcom,max-bandwidth-low-kbps = <1800000>;
+ qcom,max-bandwidth-high-kbps = <1800000>;
+ qcom,max-bandwidth-per-pipe-kbps = <1000000>;
+
+ qcom,mdss-intf-off = <0x00000000 0x0006B800>;
+ qcom,mdss-pingpong-off = <0x00071000>;
+ qcom,mdss-mixer-intf-off = <0x00045000>;
+ qcom,mdss-mixer-wb-off = <0x00046000>;
+ qcom,mdss-wfd-mode = "dedicated";
+ qcom,mdss-per-pipe-panic-luts = <0x000f>,
+ <0x0>,
+ <0xfffc>,
+ <0x0>;
+
+ /delete-property/ qcom,mdss-highest-bank-bit;
+ /delete-property/ qcom,vbif-settings;
+
+ qcom,regs-dump-mdp = <0x01000 0x01454>,
+ <0x02000 0x02064>,
+ <0x02200 0x02264>,
+ <0x02400 0x02464>,
+ <0x05000 0x05150>,
+ <0x05200 0x05230>,
+ <0x15000 0x15150>,
+ <0x17000 0x17150>,
+ <0x25000 0x25150>,
+ <0x35000 0x35150>,
+ <0x45000 0x452bc>,
+ <0x46000 0x462bc>,
+ <0x55000 0x5522c>,
+ <0x65000 0x652c0>,
+ <0x66000 0x662c0>,
+ <0x6b800 0x6ba68>,
+ <0x71000 0x710d4>;
+
+ qcom,regs-dump-names-mdp = "MDP",
+ "CTL_0", "CTL_1", "CTL_2",
+ "VIG0_SSPP", "VIG0",
+ "RGB0_SSPP", "RGB1_SSPP",
+ "DMA0_SSPP",
+ "CURSOR0_SSPP",
+ "LAYER_0", "LAYER_1",
+ "DSPP_0",
+ "WB_0", "WB_2",
+ "INTF_1",
+ "PP_0";
+};
+
+&mdss_rotator {
+ /delete-property/ qcom,mdss-has-ubwc;
+};
+
+/delete-node/ &mdss_fb2;
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-pinctrl.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-pinctrl.dtsi
new file mode 100755
index 0000000..0a590db
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-pinctrl.dtsi
@@ -0,0 +1,1852 @@
+&soc {
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,msm8917-pinctrl";
+ reg = <0x1000000 0x300000>;
+ reg-names = "pinctrl_regs";
+ interrupts-extended = <&wakegic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ wakeup-parent = <&wakegpio>;
+ #interrupt-cells = <2>;
+ irqdomain-map = <38 0 &wakegpio 3 0>,
+ <1 0 &wakegpio 4 0>,
+ <5 0 &wakegpio 5 0>,
+ <9 0 &wakegpio 6 0>,
+ <37 0 &wakegpio 8 0>,
+ <36 0 &wakegpio 9 0>,
+ <13 0 &wakegpio 10 0>,
+ <35 0 &wakegpio 11 0>,
+ <17 0 &wakegpio 12 0>,
+ <21 0 &wakegpio 13 0>,
+ <54 0 &wakegpio 14 0>,
+ <34 0 &wakegpio 15 0>,
+ <31 0 &wakegpio 16 0>,
+ <58 0 &wakegpio 17 0>,
+ <28 0 &wakegpio 18 0>,
+ <42 0 &wakegpio 19 0>,
+ <25 0 &wakegpio 20 0>,
+ <12 0 &wakegpio 21 0>,
+ <43 0 &wakegpio 22 0>,
+ <44 0 &wakegpio 23 0>,
+ <45 0 &wakegpio 24 0>,
+ <46 0 &wakegpio 25 0>,
+ <48 0 &wakegpio 26 0>,
+ <65 0 &wakegpio 27 0>,
+ <93 0 &wakegpio 28 0>,
+ <97 0 &wakegpio 29 0>,
+ <63 0 &wakegpio 30 0>,
+ <70 0 &wakegpio 31 0>,
+ <71 0 &wakegpio 32 0>,
+ <72 0 &wakegpio 33 0>,
+ <81 0 &wakegpio 34 0>,
+ <126 0 &wakegpio 35 0>,
+ <90 0 &wakegpio 36 0>,
+ <128 0 &wakegpio 37 0>,
+ <91 0 &wakegpio 38 0>,
+ <41 0 &wakegpio 39 0>,
+ <127 0 &wakegpio 40 0>,
+ <86 0 &wakegpio 41 0>,
+ <67 0 &wakegpio 50 0>,
+ <73 0 &wakegpio 51 0>,
+ <74 0 &wakegpio 52 0>,
+ <62 0 &wakegpio 53 0>,
+ <124 0 &wakegpio 54 0>,
+ <61 0 &wakegpio 55 0>,
+ <130 0 &wakegpio 56 0>,
+ <59 0 &wakegpio 57 0>,
+ <50 0 &wakegpio 59 0>;
+ irqdomain-map-pass-thru = <0 0xff>;
+ irqdomain-map-mask = <0xff 0>;
+
+#include "msm8917-camera-pinctrl.dtsi"
+ /* add pingrp for touchscreen */
+ pmx_ts_int_active {
+ ts_int_active: ts_int_active {
+ mux {
+ pins = "gpio65";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio65";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_int_suspend {
+ ts_int_suspend: ts_int_suspend {
+ mux {
+ pins = "gpio65";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio65";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_reset_active {
+ ts_reset_active: ts_reset_active {
+ mux {
+ pins = "gpio64";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio64";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_reset_suspend {
+ ts_reset_suspend: ts_reset_suspend {
+ mux {
+ pins = "gpio64";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio64";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_release {
+ ts_release: ts_release {
+ mux {
+ pins = "gpio65", "gpio64";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio65", "gpio64";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx-uartconsole {
+ uart_console_active: uart_console_active {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ uart_console_sleep: uart_console_sleep {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ };
+
+ blsp1_uart1 {
+ blsp1_uart1_active: blsp1_uart1_active {
+ mux {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ function = "blsp_uart1";
+ };
+
+ config {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp1_uart1_sleep: blsp1_uart1_sleep {
+ mux {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ wcnss_pmux_5wire {
+ /* Active configuration of bus pins */
+ wcnss_default: wcnss_default {
+ wcss_wlan2 {
+ pins = "gpio76";
+ function = "wcss_wlan2";
+ };
+
+ wcss_wlan1 {
+ pins = "gpio77";
+ function = "wcss_wlan1";
+ };
+
+ wcss_wlan0 {
+ pins = "gpio78";
+ function = "wcss_wlan0";
+ };
+
+ wcss_wlan {
+ pins = "gpio79", "gpio80";
+ function = "wcss_wlan";
+ };
+
+ config {
+ pins = "gpio76", "gpio77",
+ "gpio78", "gpio79",
+ "gpio80";
+ drive-strength = <6>; /* 6 MA */
+ bias-pull-up; /* PULL UP */
+ };
+ };
+
+ wcnss_sleep: wcnss_sleep {
+ wcss_wlan2 {
+ pins = "gpio76";
+ function = "wcss_wlan2";
+ };
+
+ wcss_wlan1 {
+ pins = "gpio77";
+ function = "wcss_wlan1";
+ };
+
+ wcss_wlan0 {
+ pins = "gpio78";
+ function = "wcss_wlan0";
+ };
+
+ wcss_wlan {
+ pins = "gpio79", "gpio80";
+ function = "wcss_wlan";
+ };
+
+ config {
+ pins = "gpio76", "gpio77",
+ "gpio78", "gpio79",
+ "gpio80";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-down; /* PULL Down */
+ };
+ };
+ };
+
+ wcnss_pmux_gpio: wcnss_pmux_gpio {
+ wcnss_gpio_default: wcnss_gpio_default {
+ /* Active configuration of bus pins */
+ mux {
+ /* Uses general purpose pins */
+ pins = "gpio76", "gpio77",
+ "gpio78", "gpio79",
+ "gpio80";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio76", "gpio77",
+ "gpio78", "gpio79",
+ "gpio80";
+ drive-strength = <6>; /* 6 MA */
+ bias-pull-up; /* PULL UP */
+ };
+ };
+ };
+
+ cdc_mclk2_pin {
+ cdc_mclk2_sleep: cdc_mclk2_sleep {
+ mux {
+ pins = "gpio66";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio66";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+
+ cdc_mclk2_active: cdc_mclk2_active {
+ mux {
+ pins = "gpio66";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio66";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ pmx_mdss: pmx_mdss {
+ mdss_dsi_active: mdss_dsi_active {
+ mux {
+ pins = "gpio60", "gpio98";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio60", "gpio98";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable = <0>; /* no pull */
+ output-high;
+ };
+ };
+
+ mdss_dsi_suspend: mdss_dsi_suspend {
+ mux {
+ pins = "gpio60", "gpio98";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio60", "gpio98";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* pull down */
+ };
+ };
+ };
+
+ pmx_mdss_te {
+ mdss_te_active: mdss_te_active {
+ mux {
+ pins = "gpio24";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio24";
+ drive-strength = <2>; /* 8 mA */
+ bias-pull-down; /* pull down*/
+ };
+ };
+
+ mdss_te_suspend: mdss_te_suspend {
+ mux {
+ pins = "gpio24";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio24";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* pull down */
+ };
+ };
+ };
+
+ pmx_qdsd_clk {
+ qdsd_clk_sdcard: clk_sdcard {
+ config {
+ pins = "qdsd_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ qdsd_clk_trace: clk_trace {
+ config {
+ pins = "qdsd_clk";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_clk_swdtrc: clk_swdtrc {
+ config {
+ pins = "qdsd_clk";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_clk_spmi: clk_spmi {
+ config {
+ pins = "qdsd_clk";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ pmx_qdsd_cmd {
+ qdsd_cmd_sdcard: cmd_sdcard {
+ config {
+ pins = "qdsd_cmd";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_cmd_trace: cmd_trace {
+ config {
+ pins = "qdsd_cmd";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_cmd_swduart: cmd_uart {
+ config {
+ pins = "qdsd_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_cmd_swdtrc: cmd_swdtrc {
+ config {
+ pins = "qdsd_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_cmd_jtag: cmd_jtag {
+ config {
+ pins = "qdsd_cmd";
+ bias-disable; /* NO pull */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_cmd_spmi: cmd_spmi {
+ config {
+ pins = "qdsd_cmd";
+ bias-pull-down; /* pull down */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+ };
+
+ pmx_qdsd_data0 {
+ qdsd_data0_sdcard: data0_sdcard {
+ config {
+ pins = "qdsd_data0";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data0_trace: data0_trace {
+ config {
+ pins = "qdsd_data0";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data0_swduart: data0_uart {
+ config {
+ pins = "qdsd_data0";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data0_swdtrc: data0_swdtrc {
+ config {
+ pins = "qdsd_data0";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data0_jtag: data0_jtag {
+ config {
+ pins = "qdsd_data0";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data0_spmi: data0_spmi {
+ config {
+ pins = "qdsd_data0";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ pmx_qdsd_data1 {
+ qdsd_data1_sdcard: data1_sdcard {
+ config {
+ pins = "qdsd_data1";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data1_trace: data1_trace {
+ config {
+ pins = "qdsd_data1";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data1_swduart: data1_uart {
+ config {
+ pins = "qdsd_data1";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data1_swdtrc: data1_swdtrc {
+ config {
+ pins = "qdsd_data1";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data1_jtag: data1_jtag {
+ config {
+ pins = "qdsd_data1";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ pmx_qdsd_data2 {
+ qdsd_data2_sdcard: data2_sdcard {
+ config {
+ pins = "qdsd_data2";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data2_trace: data2_trace {
+ config {
+ pins = "qdsd_data2";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data2_swduart: data2_uart {
+ config {
+ pins = "qdsd_data2";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data2_swdtrc: data2_swdtrc {
+ config {
+ pins = "qdsd_data2";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data2_jtag: data2_jtag {
+ config {
+ pins = "qdsd_data2";
+ bias-pull-up; /* pull up */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+ };
+
+ pmx_qdsd_data3 {
+ qdsd_data3_sdcard: data3_sdcard {
+ config {
+ pins = "qdsd_data3";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data3_trace: data3_trace {
+ config {
+ pins = "qdsd_data3";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data3_swduart: data3_uart {
+ config {
+ pins = "qdsd_data3";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data3_swdtrc: data3_swdtrc {
+ config {
+ pins = "qdsd_data3";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data3_jtag: data3_jtag {
+ config {
+ pins = "qdsd_data3";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data3_spmi: data3_spmi {
+ config {
+ pins = "qdsd_data3";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+ };
+
+ pmx_sdc1_rclk {
+ sdc1_rclk_on: sdc1_rclk_on {
+ config {
+ pins = "sdc1_rclk";
+ bias-pull-down; /* pull down */
+ };
+ };
+
+ sdc1_rclk_off: sdc1_rclk_off {
+ config {
+ pins = "sdc1_rclk";
+ bias-pull-down; /* pull down */
+ };
+ };
+ };
+
+ pmx_sdc1_clk {
+ sdc1_clk_on: sdc1_clk_on {
+ config {
+ pins = "sdc1_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc1_clk_off: sdc1_clk_off {
+ config {
+ pins = "sdc1_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ pmx_sdc1_cmd {
+ sdc1_cmd_on: sdc1_cmd_on {
+ config {
+ pins = "sdc1_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc1_cmd_off: sdc1_cmd_off {
+ config {
+ pins = "sdc1_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ pmx_sdc1_data {
+ sdc1_data_on: sdc1_data_on {
+ config {
+ pins = "sdc1_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc1_data_off: sdc1_data_off {
+ config {
+ pins = "sdc1_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ sdhc2_cd_pin {
+ sdc2_cd_on: cd_on {
+ mux {
+ pins = "gpio67";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio67";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_cd_off: cd_off {
+ mux {
+ pins = "gpio67";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio67";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ pmx_sdc2_clk {
+ sdc2_clk_on: sdc2_clk_on {
+ config {
+ pins = "sdc2_clk";
+ drive-strength = <16>; /* 16 MA */
+ bias-disable; /* NO pull */
+ };
+ };
+
+ sdc2_clk_off: sdc2_clk_off {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ pmx_sdc2_cmd {
+ sdc2_cmd_on: sdc2_cmd_on {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_cmd_off: sdc2_cmd_off {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ pmx_sdc2_data {
+ sdc2_data_on: sdc2_data_on {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_data_off: sdc2_data_off {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ sdc2_wlan_gpio {
+ sdc2_wlan_gpio_active: sdc2_wlan_gpio_active {
+ config {
+ pins = "gpio99";
+ output-high;
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_wlan_gpio_sleep: sdc2_wlan_gpio_sleep {
+ config {
+ pins = "gpio99";
+ output-low;
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ wcd9xxx_intr {
+ wcd_intr_default: wcd_intr_default {
+ mux {
+ pins = "gpio73";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio73";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* pull down */
+ input-enable;
+ };
+ };
+ };
+
+ pri_mi2s_mclk_b_lines {
+ pri_mi2s_mclk_b_default: pri_mi2s_mclk_default {
+ mux {
+ pins = "gpio69";
+ function = "pri_mi2s_mclk_b";
+ };
+
+ config {
+ pins = "gpio69";
+ drive-strength = <8>;
+ bias-disable;
+ input-enable;
+ };
+ };
+ };
+
+ sec_mi2s_mclk_a_lines {
+ sec_mi2s_mclk_a_active: sec_mi2s_mclk_a_active {
+ mux {
+ pins = "gpio25";
+ function = "sec_mi2s_mclk_a";
+ };
+
+ config {
+ pins = "gpio25";
+ drive-strength = <8>; /* 8 MA */
+ output-high;
+ bias-disable;
+ };
+ };
+
+ sec_mi2s_mclk_a_sleep: sec_mi2s_mclk_a_sleep {
+ mux {
+ pins = "gpio25";
+ function = "sec_mi2s_mclk_a";
+ };
+
+ config {
+ pins = "gpio25";
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ bias-pull-down;
+ };
+ };
+ };
+
+ cdc_reset_ctrl {
+ cdc_reset_sleep: cdc_reset_sleep {
+ mux {
+ pins = "gpio68";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio68";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_reset_active:cdc_reset_active {
+ mux {
+ pins = "gpio68";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio68";
+ drive-strength = <16>;
+ bias-pull-down;
+ output-high;
+ };
+ };
+ };
+
+ cdc-pdm-2-lines {
+ cdc_pdm_lines_2_act: pdm_lines_2_on {
+ mux {
+ pins = "gpio70", "gpio71", "gpio72";
+ function = "cdc_pdm0";
+ };
+
+ config {
+ pins = "gpio70", "gpio71", "gpio72";
+ drive-strength = <8>;
+ };
+ };
+
+ cdc_pdm_lines_2_sus: pdm_lines_2_off {
+ mux {
+ pins = "gpio70", "gpio71", "gpio72";
+ function = "cdc_pdm0";
+ };
+
+ config {
+ pins = "gpio70", "gpio71", "gpio72";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ cdc-pdm-lines {
+ cdc_pdm_lines_act: pdm_lines_on {
+ mux {
+ pins = "gpio69", "gpio73", "gpio74";
+ function = "cdc_pdm0";
+ };
+
+ config {
+ pins = "gpio69", "gpio73", "gpio74";
+ drive-strength = <8>;
+ };
+ };
+
+ cdc_pdm_lines_sus: pdm_lines_off {
+ mux {
+ pins = "gpio69", "gpio73", "gpio74";
+ function = "cdc_pdm0";
+ };
+
+ config {
+ pins = "gpio69", "gpio73", "gpio74";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ cross-conn-det {
+ cross_conn_det_act: lines_on {
+ mux {
+ pins = "gpio63";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio63";
+ drive-strength = <8>;
+ output-low;
+ bias-pull-down;
+ };
+ };
+
+ cross_conn_det_sus: lines_off {
+ mux {
+ pins = "gpio63";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio63";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ /* WSA VI sense */
+ wsa-vi {
+ wsa_vi_on: wsa_vi_on {
+ mux {
+ pins = "gpio94", "gpio95";
+ function = "wsa_io";
+ };
+
+ config {
+ pins = "gpio94", "gpio95";
+ drive-strength = <8>; /* 8 MA */
+ bias-disable; /* NO pull */
+ };
+ };
+
+ wsa_vi_off: wsa_vi_off {
+ mux {
+ pins = "gpio94", "gpio95";
+ function = "wsa_io";
+ };
+
+ config {
+ pins = "gpio94", "gpio95";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-down;
+ };
+ };
+ };
+
+ /* WSA Reset */
+ wsa_reset {
+ wsa_reset_on: wsa_reset_on {
+ mux {
+ pins = "gpio96";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio96";
+ drive-strength = <2>; /* 2 MA */
+ output-high;
+ };
+ };
+
+ wsa_reset_off: wsa_reset_off {
+ mux {
+ pins = "gpio96";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio96";
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+ };
+
+ /* WSA CLK */
+ wsa_clk {
+ wsa_clk_on: wsa_clk_on {
+ mux {
+ pins = "gpio25";
+ function = "pri_mi2s_mclk_a";
+ };
+
+ config {
+ pins = "gpio25";
+ drive-strength = <8>; /* 8 MA */
+ output-high;
+ };
+ };
+
+ wsa_clk_off: wsa_clk_off {
+ mux {
+ pins = "gpio25";
+ function = "pri_mi2s_mclk_a";
+ };
+
+ config {
+ pins = "gpio25";
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pri-tlmm-lines {
+ pri_tlmm_lines_act: pri_tlmm_lines_act {
+ mux {
+ pins = "gpio85", "gpio88";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio85", "gpio88";
+ drive-strength = <8>;
+ };
+ };
+
+ pri_tlmm_lines_sus: pri_tlmm_lines_sus {
+ mux {
+ pins = "gpio85", "gpio88";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio85", "gpio88";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pri-tlmm-ws-lines {
+ pri_tlmm_ws_act: pri_tlmm_ws_act {
+ mux {
+ pins = "gpio87";
+ function = "pri_mi2s_ws";
+ };
+
+ config {
+ pins = "gpio87";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ pri_tlmm_ws_sus: pri_tlmm_ws_sus {
+ mux {
+ pins = "gpio87";
+ function = "pri_mi2s_ws";
+ };
+
+ config {
+ pins = "gpio87";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+ };
+ };
+
+ spi3 {
+ spi3_default: spi3_default {
+ /* active state */
+ mux {
+ /* MOSI, MISO, CLK */
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "blsp_spi3";
+ };
+
+ config {
+ pins = "gpio8", "gpio9", "gpio11";
+ drive-strength = <12>; /* 12 MA */
+ bias-disable = <0>; /* No PULL */
+ };
+ };
+
+ spi3_sleep: spi3_sleep {
+ /* suspended state */
+ mux {
+ /* MOSI, MISO, CLK */
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8", "gpio9", "gpio11";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-down; /* PULL Down */
+ };
+ };
+
+ spi3_cs0_active: cs0_active {
+ /* CS */
+ mux {
+ pins = "gpio10";
+ function = "blsp_spi3";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+ };
+
+ spi3_cs0_sleep: cs0_sleep {
+ /* CS */
+ mux {
+ pins = "gpio10";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+ };
+ };
+
+ spi6 {
+ spi6_default: spi6_default {
+ /* active state */
+ mux {
+ /* MOSI, MISO, CLK */
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "blsp_spi6";
+ };
+
+ config {
+ pins = "gpio20", "gpio21", "gpio23";
+ drive-strength = <16>; /* 16 MA */
+ bias-disable = <0>; /* No PULL */
+ };
+ };
+
+ spi6_sleep: spi6_sleep {
+ /* suspended state */
+ mux {
+ /* MOSI, MISO, CLK */
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio20", "gpio21", "gpio23";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-down; /* PULL Down */
+ };
+ };
+
+ spi6_cs0_active: cs0_active {
+ /* CS */
+ mux {
+ pins = "gpio47";
+ function = "blsp6_spi";
+ };
+
+ config {
+ pins = "gpio47";
+ drive-strength = <16>;
+ bias-disable = <0>;
+ };
+ };
+
+ spi6_cs0_sleep: cs0_sleep {
+ /* CS */
+ mux {
+ pins = "gpio47";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio47";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+ };
+
+ spi6_cs1_active: cs1_active {
+ /* CS */
+ mux {
+ pins = "gpio22";
+ function = "blsp_spi6";
+ };
+
+ config {
+ pins = "gpio22";
+ drive-strength = <16>;
+ bias-disable = <0>;
+ };
+ };
+
+ spi6_cs1_sleep: cs1_sleep {
+ /* CS */
+ mux {
+ pins = "gpio22";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio22";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+ };
+ };
+
+ fpc_reset_int {
+ fpc_reset_low: reset_low {
+ mux {
+ pins = "gpio124";
+ function = "fpc_reset_gpio_low";
+ };
+
+ config {
+ pins = "gpio124";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ fpc_reset_high: reset_high {
+ mux {
+ pins = "gpio124";
+ function = "fpc_reset_gpio_high";
+ };
+
+ config {
+ pins = "gpio124";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ fpc_int_low: int_low {
+ mux {
+ pins = "gpio48";
+ };
+
+ config {
+ pins = "gpio48";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+ };
+ };
+
+
+ i2c_2 {
+ i2c_2_active: i2c_2_active {
+ /* active state */
+ mux {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+ };
+
+ config {
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_2_sleep: i2c_2_sleep {
+ /* suspended state */
+ mux {
+ pins = "gpio6", "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ i2c_3 {
+ i2c_3_active: i2c_3_active {
+ /* active state */
+ mux {
+ pins = "gpio10", "gpio11";
+ function = "blsp_i2c3";
+ };
+
+ config {
+ pins = "gpio10", "gpio11";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_3_sleep: i2c_3_sleep {
+ /* suspended state */
+ mux {
+ pins = "gpio10", "gpio11";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio10", "gpio11";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ /* IO Expander SX150xq */
+ i2c_4 {
+ i2c_4_active: i2c_4_active {
+ /* active state */
+ mux {
+ pins = "gpio14", "gpio15";
+ function = "blsp_i2c4";
+ };
+
+ config {
+ pins = "gpio14", "gpio15";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_4_sleep: i2c_4_sleep {
+ /* suspended state */
+ mux {
+ pins = "gpio14", "gpio15";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio14", "gpio15";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ i2c_5 {
+ i2c_5_active: i2c_5_active {
+ /* active state */
+ mux {
+ pins = "gpio18", "gpio19";
+ function = "blsp_i2c5";
+ };
+
+ config {
+ pins = "gpio18", "gpio19";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_5_sleep: i2c_5_sleep {
+ /* suspended state */
+ mux {
+ pins = "gpio18", "gpio19";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio18", "gpio19";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ i2c_6 {
+ i2c_6_active: i2c_6_active {
+ /* active state */
+ mux {
+ pins = "gpio22", "gpio23";
+ function = "blsp_i2c6";
+ };
+
+ config {
+ pins = "gpio22", "gpio23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_6_sleep: i2c_6_sleep {
+ /* suspended state */
+ mux {
+ pins = "gpio22", "gpio23";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio22", "gpio23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ nfc {
+ nfc_int_active: nfc_int_active {
+ /* active state */
+ mux {
+ /* GPIO 17 NFC Read Interrupt */
+ pins = "gpio17";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_int_suspend: nfc_int_suspend {
+ /* sleep state */
+ mux {
+ /* GPIO 17 NFC Read Interrupt */
+ pins = "gpio17";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_disable_active: nfc_disable_active {
+ /* active state */
+ mux {
+ /* 16: NFC ENABLE 130: FW DNLD */
+ pins = "gpio16", "gpio130";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio16", "gpio130";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_disable_suspend: nfc_disable_suspend {
+ /* sleep state */
+ mux {
+ /* 16: NFC ENABLE 130: FW DNLD */
+ pins = "gpio16", "gpio130";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio16", "gpio130";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable;
+ };
+ };
+ };
+
+ tlmm_gpio_key {
+ gpio_key_active: gpio_key_active {
+ mux {
+ pins = "gpio91", "gpio127", "gpio128";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ gpio_key_suspend: gpio_key_suspend {
+ mux {
+ pins = "gpio91", "gpio127", "gpio128";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ tlmm_pmi_flash_led {
+ rear_flash_led_enable: rear_flash_led_enable {
+ mux {
+ pins = "gpio33";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio33";
+ drive-strength = <16>;
+ output-high;
+ };
+ };
+
+ rear_flash_led_disable: rear_flash_led_disable {
+ mux {
+ pins = "gpio33";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio33";
+ drive-strength = <2>;
+ output-low;
+ };
+ };
+
+ front_flash_led_enable: front_flash_led_enable {
+ mux {
+ pins = "gpio50";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio50";
+ drive-strength = <16>;
+ output-high;
+ };
+ };
+
+ front_flash_led_disable: front_flash_led_disable {
+ mux {
+ pins = "gpio50";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio50";
+ drive-strength = <2>;
+ output-low;
+ };
+ };
+ };
+
+ usbc_int_default: usbc_int_default {
+ mux {
+ pins = "gpio97", "gpio131";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio97", "gpio131";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ pri_mi2s_sck {
+ pri_mi2s_sck_sleep: pri_mi2s_sck_sleep {
+ mux {
+ pins = "gpio85";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio85";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_mi2s_sck_active: pri_mi2s_sck_active {
+ mux {
+ pins = "gpio85";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio85";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ pri_mi2s_sd0 {
+ pri_mi2s_sd0_sleep: pri_mi2s_sd0_sleep {
+ mux {
+ pins = "gpio88";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio88";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_mi2s_sd0_active: pri_mi2s_sd0_active {
+ mux {
+ pins = "gpio88";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio88";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ pri_mi2s_sd1 {
+ pri_mi2s_sd1_sleep: pri_mi2s_sd1_sleep {
+ mux {
+ pins = "gpio86";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio86";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ pri_mi2s_sd1_active: pri_mi2s_sd1_active {
+ mux {
+ pins = "gpio86";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio86";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ sec_mi2s_ws {
+ sec_mi2s_ws_sleep: sec_mi2s_ws_sleep {
+ mux {
+ pins = "gpio95";
+ function = "sec_mi2s";
+ };
+
+ config {
+ pins = "gpio95";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+
+ sec_mi2s_ws_active: sec_mi2s_ws_active {
+ mux {
+ pins = "gpio95";
+ function = "sec_mi2s";
+ };
+
+ config {
+ pins = "gpio95";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ sec_mi2s_sck {
+ sec_mi2s_sck_sleep: sec_mi2s_sck_sleep {
+ mux {
+ pins = "gpio94";
+ function = "sec_mi2s";
+ };
+
+ config {
+ pins = "gpio94";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+
+ sec_mi2s_sck_active: sec_mi2s_sck_active {
+ mux {
+ pins = "gpio94";
+ function = "sec_mi2s";
+ };
+
+ config {
+ pins = "gpio94";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ sec_mi2s_sd0 {
+ sec_mi2s_sd0_sleep: sec_mi2s_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "sec_mi2s";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_mi2s_sd0_active: sec_mi2s_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "sec_mi2s";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ sec_mi2s_sd1 {
+ sec_mi2s_sd1_sleep: sec_mi2s_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "sec_mi2s";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ sec_mi2s_sd1_active: sec_mi2s_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "sec_mi2s";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ usb_mode_select: usb_mode_select {
+ mux {
+ pins = "gpio130";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio130";
+ drive-strength = <2>;
+ bias-disable;
+ input-enable;
+ };
+ };
+
+ usb2533_hub_reset: usb2533_hub_reset {
+ mux {
+ pins = "gpio100";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio100";
+ drive-strength = <2>;
+ output-low;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-pm.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-pm.dtsi
new file mode 100755
index 0000000..3097871
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-pm.dtsi
@@ -0,0 +1,120 @@
+#include <dt-bindings/msm/pm.h>
+
+&soc {
+ qcom,spm@b012000 {
+ compatible = "qcom,spm-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb012000 0x1000>;
+ qcom,name = "perf-l2";
+ qcom,saw2-ver-reg = <0xfd0>;
+ qcom,saw2-cfg = <0x14>;
+ qcom,saw2-spm-dly= <0x3C11840A>;
+ qcom,saw2-spm-ctl = <0xe>;
+ qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,vctl-timeout-us = <500>;
+ qcom,vctl-port = <0x0>;
+ };
+
+ qcom,lpm-levels {
+ compatible = "qcom,lpm-levels";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,pm-cluster@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "perf";
+ qcom,psci-mode-shift = <4>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cluster-level@0 {
+ reg = <0>;
+ label = "perf-l2-wfi";
+ qcom,psci-mode = <1>;
+ qcom,entry-latency-us = <125>;
+ qcom,exit-latency-us = <180>;
+ qcom,min-residency-us = <305>;
+ };
+
+ qcom,pm-cluster-level@1 {
+ reg = <1>;
+ label = "perf-l2-gdhs";
+ qcom,psci-mode = <4>;
+ qcom,entry-latency-us = <240>;
+ qcom,exit-latency-us = <280>;
+ qcom,min-residency-us = <806>;
+ qcom,min-child-idx = <1>;
+ qcom,reset-level = <LPM_RESET_LVL_GDHS>;
+ };
+
+ qcom,pm-cluster-level@2 {
+ reg = <2>;
+ label = "perf-l2-retention";
+ qcom,psci-mode = <2>;
+ qcom,entry-latency-us = <700>;
+ qcom,exit-latency-us = <650>;
+ qcom,min-residency-us = <1972>;
+ qcom,min-child-idx = <1>;
+ qcom,reset-level = <LPM_RESET_LVL_RET>;
+ };
+
+ qcom,pm-cluster-level@3 {
+ reg = <3>;
+ label = "perf-l2-pc";
+ qcom,psci-mode = <5>;
+ qcom,entry-latency-us = <800>;
+ qcom,exit-latency-us = <11200>;
+ qcom,min-residency-us = <6501>;
+ qcom,min-child-idx = <1>;
+ qcom,is-reset;
+ qcom,notify-rpm;
+ qcom,reset-level = <LPM_RESET_LVL_PC>;
+ };
+
+ qcom,pm-cpu {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+ qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ qcom,pm-cpu-level@0 {
+ reg = <0>;
+ label = "wfi";
+ qcom,psci-cpu-mode = <1>;
+ qcom,entry-latency-us = <13>;
+ qcom,exit-latency-us = <12>;
+ qcom,min-residency-us = <25>;
+ };
+
+ qcom,pm-cpu-level@1 {
+ reg = <1>;
+ label = "pc";
+ qcom,psci-cpu-mode = <3>;
+ qcom,entry-latency-us = <125>;
+ qcom,exit-latency-us = <180>;
+ qcom,min-residency-us = <595>;
+ qcom,use-broadcast-timer;
+ qcom,is-reset;
+ qcom,reset-level = <LPM_RESET_LVL_PC>;
+ };
+ };
+ };
+ };
+
+ qcom,rpm-stats@29dba0 {
+ compatible = "qcom,rpm-stats";
+ reg = <0x200000 0x1000>, <0x290014 0x4>;
+ reg-names = "phys_addr_base", "offset_addr";
+ };
+
+ qcom,rpm-master-stats@60150 {
+ compatible = "qcom,rpm-master-stats";
+ reg = <0x60150 0x5000>;
+ qcom,masters = "APSS", "MPSS", "PRONTO", "TZ", "LPASS";
+ qcom,master-stats-version = <2>;
+ qcom,master-offset = <4096>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-regulator.dtsi
new file mode 100755
index 0000000..c125a62
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-regulator.dtsi
@@ -0,0 +1,277 @@
+#include "msm8937-regulator.dtsi"
+
+&soc {
+ /* delete the CPR and MEM ACC nodes of msm8937 */
+ /delete-node/ regulator@b018000;
+ /delete-node/ regulator@01946004;
+
+ mem_acc_vreg_corner: regulator@01946004 {
+ compatible = "qcom,mem-acc-regulator";
+ reg = <0xa4000 0x1000>;
+ reg-names = "efuse_addr";
+ regulator-name = "mem_acc_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <3>;
+
+ qcom,acc-reg-addr-list =
+ <0x01942138 0x01942130 0x01942120 0x01942124>;
+
+ qcom,acc-init-reg-config = <1 0xff>, <2 0x5555>;
+
+ qcom,num-acc-corners = <3>;
+ qcom,boot-acc-corner = <2>;
+ qcom,corner1-reg-config =
+ /* SVS+ => SVS+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => TURBO/NOM+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x0>,
+ < 4 0x0>;
+
+ qcom,corner2-reg-config =
+ /* NOM => SVS+ */
+ < 3 0x30c30c3>, < 4 0x30c3>,
+ /* NOM => NOM */
+ <(-1) (-1)>, <(-1) (-1)>,
+ /* NOM => TURBO/NOM+ */
+ < 3 0x0>, < 4 0x0>;
+
+ qcom,corner3-reg-config =
+ /* TURBO/NOM+ => SVS+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>,
+ < 4 0x30c3>,
+ /* TURBO/NOM+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* TURBO/NOM+ => TURBO/NOM+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>;
+
+ qcom,override-acc-fuse-sel = <71 17 3 0>;
+ qcom,override-fuse-version-map = <1>,
+ <2>,
+ <3>,
+ <4>;
+ qcom,override-corner1-addr-val-map =
+ /* 1st fuse version tuple matched */
+ /* SVS+ => SVS+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => TURBO/NOM+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x1>,
+ < 4 0x0>,
+
+ /* 2nd fuse version tuple matched */
+ /* SVS+ => SVS+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => TURBO/NOM+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x3>,
+ < 4 0x0>,
+
+ /* 3rd fuse version tuple matched */
+ /* SVS+ => SVS+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => NOM */
+ < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => TURBO/NOM+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x0>,
+ < 4 0x0>,
+
+ /* 4th fuse version tuple matched */
+ /* SVS+ => SVS+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => NOM */
+ < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => TURBO/NOM+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x1>,
+ < 4 0x0>;
+
+ qcom,override-corner2-addr-val-map =
+ /* 1st fuse version tuple matched */
+ /* NOM => SVS+ */
+ < 3 0x30c30c3>, < 4 0x30c3>,
+ /* NOM => NOM */
+ <(-1) (-1)>, <(-1) (-1)>,
+ /* NOM => TURBO/NOM+ */
+ < 3 0x1>, < 4 0x0>,
+
+ /* 2nd fuse version tuple matched */
+ /* NOM => SVS+ */
+ < 3 0x30c30c3>, < 4 0x30c3>,
+ /* NOM => NOM */
+ <(-1) (-1)>, <(-1) (-1)>,
+ /* NOM => TURBO/NOM+ */
+ < 3 0x3>, < 4 0x0>,
+
+ /* 3rd fuse version tuple matched */
+ /* NOM => SVS+ */
+ < 3 0x30c30c3>, < 4 0x30c3>,
+ /* NOM => NOM */
+ <(-1) (-1)>, <(-1) (-1)>,
+ /* NOM => TURBO/NOM+ */
+ < 3 0x0>, < 4 0x0>,
+
+ /* 4th fuse version tuple matched */
+ /* NOM => SVS+ */
+ < 3 0x30c30c3>, < 4 0x30c3>,
+ /* NOM => NOM */
+ <(-1) (-1)>, <(-1) (-1)>,
+ /* NOM => TURBO/NOM+ */
+ < 3 0x1>, < 4 0x0>;
+
+ qcom,override-corner3-addr-val-map =
+ /* 1st fuse version tuple matched */
+ /* TURBO/NOM+ => SVS+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>,
+ < 4 0x30c3>,
+ /* TURBO/NOM+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* TURBO/NOM+ => TURBO/NOM+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+
+ /* 2nd fuse version tuple matched */
+ /* TURBO/NOM+ => SVS+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>,
+ < 4 0x30c3>,
+ /* TURBO/NOM+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* TURBO/NOM+ => TURBO/NOM+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+
+ /* 3rd fuse version tuple matched */
+ /* TURBO/NOM+ => SVS+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>,
+ < 4 0x30c3>,
+ /* TURBO/NOM+ => NOM */
+ < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* TURBO/NOM+ => TURBO/NOM+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+
+ /* 4th fuse version tuple matched */
+ /* TURBO/NOM+ => SVS+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>,
+ < 4 0x30c3>,
+ /* TURBO/NOM+ => NOM */
+ < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* TURBO/NOM+ => TURBO/NOM+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>;
+ };
+
+ apc_vreg_corner: regulator@b018000 {
+ compatible = "qcom,cpr-regulator";
+ reg = <0xb018000 0x1000>, <0xb011064 0x4>, <0xa4000 0x1000>;
+ reg-names = "rbcpr", "rbcpr_clk", "efuse_addr";
+ interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+ regulator-name = "apc_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <5>;
+
+ qcom,cpr-fuse-corners = <3>;
+ qcom,cpr-voltage-ceiling = <1155000 1225000 1350000>;
+ qcom,cpr-voltage-floor = <1050000 1050000 1090000>;
+ vdd-apc-supply = <&pm8937_s5>;
+
+ mem-acc-supply = <&mem_acc_vreg_corner>;
+
+ qcom,cpr-ref-clk = <19200>;
+ qcom,cpr-timer-delay = <5000>;
+ qcom,cpr-timer-cons-up = <0>;
+ qcom,cpr-timer-cons-down = <2>;
+ qcom,cpr-irq-line = <0>;
+ qcom,cpr-step-quotient = <16>;
+ qcom,cpr-up-threshold = <2>;
+ qcom,cpr-down-threshold = <4>;
+ qcom,cpr-idle-clocks = <15>;
+ qcom,cpr-gcnt-time = <1>;
+ qcom,vdd-apc-step-up-limit = <1>;
+ qcom,vdd-apc-step-down-limit = <1>;
+ qcom,cpr-apc-volt-step = <5000>;
+
+ qcom,cpr-fuse-row = <67 0>;
+ qcom,cpr-fuse-target-quot = <42 24 6>;
+ qcom,cpr-fuse-ro-sel = <60 57 54>;
+ qcom,cpr-init-voltage-ref = <1155000 1225000 1350000>;
+ qcom,cpr-fuse-init-voltage =
+ <67 36 6 0>,
+ <67 18 6 0>,
+ <67 0 6 0>;
+ qcom,cpr-fuse-quot-offset =
+ <71 26 6 0>,
+ <71 20 6 0>,
+ <70 54 7 0>;
+ qcom,cpr-fuse-quot-offset-scale = <5 5 5>;
+ qcom,cpr-init-voltage-step = <10000>;
+ qcom,cpr-corner-map = <1 2 3 3 3>;
+ qcom,cpr-corner-frequency-map =
+ <1 960000000>,
+ <2 1094400000>,
+ <3 1248000000>,
+ <4 1401000000>,
+ <5 1497600000>;
+ qcom,speed-bin-fuse-sel = <37 34 3 0>;
+ qcom,cpr-speed-bin-max-corners =
+ <0 (-1) 1 2 4>,
+ <1 (-1) 1 2 5>;
+ qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>;
+ qcom,cpr-voltage-scaling-factor-max = <0 2000 2000>;
+ qcom,cpr-scaled-init-voltage-as-ceiling;
+ qcom,cpr-fuse-revision = <69 39 3 0>;
+ qcom,pvs-version-fuse-sel = <37 40 3 0>; /* foundry */
+ qcom,cpr-fuse-version-map =
+ < 1 0 3 (-1) (-1) (-1)>,
+ < 1 5 3 (-1) (-1) (-1)>,
+ <(-1) 0 1 (-1) (-1) (-1)>,
+ <(-1) 0 2 (-1) (-1) (-1)>,
+ <(-1) 5 1 (-1) (-1) (-1)>,
+ <(-1) 5 2 (-1) (-1) (-1)>,
+ <(-1) (-1) (-1) (-1) (-1) (-1)>;
+ qcom,cpr-quotient-adjustment =
+ <50 40 50>,
+ <0 0 40>,
+ <50 40 100>,
+ <50 40 50>,
+ <0 0 100>,
+ <0 0 50>,
+ <0 0 0>;
+ qcom,cpr-init-voltage-adjustment =
+ <30000 5000 10000>,
+ <0 0 0>,
+ <30000 5000 35000>,
+ <30000 5000 10000>,
+ <0 0 20000>,
+ <0 0 0>,
+ <0 0 0>;
+ qcom,cpr-enable;
+ };
+
+ eldo2_pm8937: eldo2 {
+ compatible = "regulator-fixed";
+ regulator-name = "eldo2_pm8937";
+ startup-delay-us = <0>;
+ enable-active-high;
+ gpio = <&pm8937_gpios 7 0>;
+ regulator-always-on;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-thermal.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-thermal.dtsi
new file mode 100755
index 0000000..7135a3d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-thermal.dtsi
@@ -0,0 +1,364 @@
+#include <dt-bindings/thermal/thermal.h>
+
+&apsscc {
+ qcom,cpu-isolation {
+ compatible = "qcom,cpu-isolate";
+ cpu0_isolate: cpu0-isolate {
+ qcom,cpu = <&CPU0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1_isolate: cpu1-isolate {
+ qcom,cpu = <&CPU1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2_isolate: cpu2-isolate {
+ qcom,cpu = <&CPU2>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3_isolate: cpu3-isolate {
+ qcom,cpu = <&CPU3>;
+ #cooling-cells = <2>;
+ };
+ };
+};
+
+&soc {
+ qmi-tmd-devices {
+ compatible = "qcom,qmi-cooling-devices";
+
+ modem {
+ qcom,instance-id = <0x0>;
+
+ modem_pa: modem_pa {
+ qcom,qmi-dev-name = "pa";
+ #cooling-cells = <2>;
+ };
+
+ modem_proc: modem_proc {
+ qcom,qmi-dev-name = "modem";
+ #cooling-cells = <2>;
+ };
+
+ modem_current: modem_current {
+ qcom,qmi-dev-name = "modem_current";
+ #cooling-cells = <2>;
+ };
+
+ modem_vdd: modem_vdd {
+ qcom,qmi-dev-name = "cpuv_restriction_cold";
+ #cooling-cells = <2>;
+ };
+ };
+ };
+};
+
+&thermal_zones {
+ aoss0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 0>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-core-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 1>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ q6-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 2>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 3>;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 4>;
+ thermal-governor = "user_space";
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ apc1-cpu0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 5>;
+ thermal-governor = "user_space";
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ apc1-cpu1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 6>;
+ thermal-governor = "user_space";
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ apc1-cpu2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 7>;
+ thermal-governor = "user_space";
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ apc1-cpu3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 8>;
+ thermal-governor = "user_space";
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpu0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 9>;
+ thermal-governor = "user_space";
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ penta-cpu-max-step {
+ polling-delay-passive = <50>;
+ polling-delay = <100>;
+ thermal-governor = "step_wise";
+ trips {
+ cpu_trip:cpu-trip {
+ temperature = <85000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_cdev {
+ trip = <&cpu_trip>;
+ cooling-device =
+ <&CPU0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ gpu0-step {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 9>;
+ thermal-governor = "step_wise";
+ trips {
+ gpu_step_trip: gpu-step-trip {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ gpu_cdev0 {
+ trip = <&gpu_step_trip>;
+ cooling-device =
+ <&msm_gpu THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ apc1-cpu0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 5>;
+ thermal-governor = "step_wise";
+ trips {
+ apc1_cpu0_trip: apc1-cpu0-trip {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_cdev {
+ trip = <&apc1_cpu0_trip>;
+ cooling-device =
+ <&cpu0_isolate 1 1>;
+ };
+ };
+ };
+
+ apc1-cpu1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 6>;
+ thermal-governor = "step_wise";
+ trips {
+ apc1_cpu1_trip: apc1-cpu1--trip {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu1_cdev {
+ trip = <&apc1_cpu1_trip>;
+ cooling-device =
+ <&cpu1_isolate 1 1>;
+ };
+ };
+ };
+
+ apc1-cpu2-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 7>;
+ thermal-governor = "step_wise";
+ trips {
+ apc1_cpu2_trip: apc1-cpu2-trip {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu2_cdev {
+ trip = <&apc1_cpu2_trip>;
+ cooling-device =
+ <&cpu2_isolate 1 1>;
+ };
+ };
+ };
+
+ apc1-cpu3-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 8>;
+ thermal-governor = "step_wise";
+ trips {
+ apc1_cpu3_trip: apc1-cpu3-trip {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu3_cdev {
+ trip = <&apc1_cpu3_trip>;
+ cooling-device =
+ <&cpu3_isolate 1 1>;
+ };
+ };
+ };
+
+ aoss0-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 0>;
+ tracks-low;
+ trips {
+ aoss_lowf: aoss-lowf {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_cdev {
+ trip = <&aoss_lowf>;
+ cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2)
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ cx_vdd_cdev {
+ trip = <&aoss_lowf>;
+ cooling-device = <&pm8937_cx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&aoss_lowf>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917-vidc.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917-vidc.dtsi
new file mode 100755
index 0000000..982a9f6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917-vidc.dtsi
@@ -0,0 +1,170 @@
+&soc {
+ qcom,vidc@1d00000 {
+ compatible = "qcom,msm-vidc";
+ reg = <0x01d00000 0xff000>;
+ interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,hfi-version = "3xx";
+ venus-supply = <&gdsc_venus>;
+ venus-core0-supply = <&gdsc_venus_core0>;
+ clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
+ <&gcc GCC_VENUS0_CORE0_VCODEC0_CLK>,
+ <&gcc GCC_VENUS0_AHB_CLK>,
+ <&gcc GCC_VENUS0_AXI_CLK>;
+ clock-names = "core_clk", "core0_clk", "iface_clk", "bus_clk";
+ qcom,clock-configs = <0x1 0x0 0x0 0x0>;
+ qcom,sw-power-collapse;
+ qcom,slave-side-cp;
+ qcom,dcvs-tbl =
+ <108000 108000 244800 0x00000004>, /* Encoder */
+ <108000 108000 244800 0x0c000000>; /* Decoder */
+ qcom,dcvs-limit =
+ <8160 30>, /* Encoder */
+ <8160 30>; /* Decoder */
+ qcom,hfi = "venus";
+ qcom,reg-presets = <0xe0020 0x05555556>,
+ <0xe0024 0x05555556>,
+ <0x80124 0x00000003>;
+ qcom,qdss-presets = <0x826000 0x1000>,
+ <0x827000 0x1000>,
+ <0x822000 0x1000>,
+ <0x803000 0x1000>,
+ <0x9180000 0x1000>,
+ <0x9181000 0x1000>;
+ qcom,max-hw-load = <352800>; /* 1080p@30 + 720p@30 */
+ qcom,pm-qos-latency-us = <651>;
+ qcom,firmware-name = "venus";
+ qcom,allowed-clock-rates = <360000000 329140000
+ 308570000 270000000 200000000>;
+ qcom,clock-freq-tbl {
+ qcom,profile-enc {
+ qcom,codec-mask = <0x55555555>;
+ qcom,cycles-per-mb = <2470>;
+ qcom,low-power-mode-factor = <32768>;
+ };
+
+ qcom,profile-dec {
+ qcom,codec-mask = <0xf3ffffff>;
+ qcom,cycles-per-mb = <788>;
+ };
+
+ qcom,profile-hevcdec {
+ qcom,codec-mask = <0x0c000000>;
+ qcom,cycles-per-mb = <1015>;
+ };
+ };
+ /* MMUs */
+ non_secure_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_ns";
+ iommus = <&apps_iommu 0x800 0x00>,
+ <&apps_iommu 0x807 0x00>,
+ <&apps_iommu 0x808 0x27>,
+ <&apps_iommu 0x811 0x20>;
+ qcom,iommu-dma-addr-pool = <0x5dc00000 0x7f000000
+ 0xdcc00000 0x1000000>;
+ qcom,iommu-faults = "non-fatal";
+ buffer-types = <0xfff>;
+ virtual-addr-pool = <0x5dc00000 0x7f000000
+ 0xdcc00000 0x1000000>;
+ };
+
+ secure_bitstream_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_bitstream";
+ iommus = <&apps_iommu 0x900 0x00>,
+ <&apps_iommu 0x90a 0x04>,
+ <&apps_iommu 0x909 0x22>;
+ qcom,iommu-dma-addr-pool = <0x4b000000 0x12c00000>;
+ qcom,iommu-faults = "non-fatal";
+ buffer-types = <0x241>;
+ virtual-addr-pool = <0x4b000000 0x12c00000>;
+ qcom,secure-context-bank;
+ qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
+ };
+
+ secure_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_pixel";
+ iommus = <&apps_iommu 0x90c 0x20>;
+ qcom,iommu-dma-addr-pool = <0x25800000 0x25800000>;
+ qcom,iommu-faults = "non-fatal";
+ buffer-types = <0x106>;
+ virtual-addr-pool = <0x25800000 0x25800000>;
+ qcom,secure-context-bank;
+ qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
+ };
+
+ secure_non_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_non_pixel";
+ iommus = <&apps_iommu 0x940 0x00>,
+ <&apps_iommu 0x907 0x08>,
+ <&apps_iommu 0x908 0x20>,
+ <&apps_iommu 0x90d 0x20>;
+ qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>;
+ qcom,iommu-faults = "non-fatal";
+ buffer-types = <0x480>;
+ virtual-addr-pool = <0x1000000 0x24800000>;
+ qcom,secure-context-bank;
+ qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
+ };
+
+ venus_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "venus-ddr";
+ qcom,bus-range-kbps = <1000 917000>;
+ };
+
+ arm9_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-arm9-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <1 1>;
+ };
+ };
+
+ venus-ddr-gov {
+ compatible = "qcom,msm-vidc,governor,table";
+ name = "venus-ddr-gov";
+ status = "ok";
+ qcom,bus-freq-table {
+ qcom,profile-enc {
+ qcom,codec-mask = <0x55555555>;
+ qcom,load-busfreq-tbl =
+ <244800 841000>, /* 1080p30E */
+ <216000 740000>, /* 720p60E */
+ <194400 680000>, /* FWVGA120E */
+ <144000 496000>, /* VGA120E */
+ <108000 370000>, /* 720p30E */
+ <97200 340000>, /* FWVGA60E */
+ <48600 170000>, /* FWVGA30E */
+ <72000 248000>, /* VGA60E */
+ <36000 124000>, /* VGA30E */
+ <18000 70000>, /* QVGA60E */
+ <9000 35000>, /* QVGA30E */
+ <0 0>;
+ };
+
+ qcom,profile-dec {
+ qcom,codec-mask = <0xffffffff>;
+ qcom,load-busfreq-tbl =
+ <244800 605000>, /* 1080p30D */
+ <216000 540000>, /* 720p60D */
+ <194400 484000>, /* FWVGA120D */
+ <144000 360000>, /* VGA120D */
+ <108000 270000>, /* 720p30D */
+ <97200 242000>, /* FWVGA60D */
+ <48600 121000>, /* FWVGA30D */
+ <72000 180000>, /* VGA60D */
+ <36000 90000>, /* VGA30D */
+ <18000 45000>, /* HVGA30D */
+ <0 0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8917.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8917.dtsi
new file mode 100755
index 0000000..037033b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8917.dtsi
@@ -0,0 +1,2223 @@
+#include "skeleton64.dtsi"
+#include <dt-bindings/clock/qcom,gcc-sdm429w.h>
+#include <dt-bindings/clock/mdss-28nm-pll-clk-legacy.h>
+#include <dt-bindings/clock/qcom,cpu-sdm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
+#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8917";
+ compatible = "qcom,msm8917";
+ qcom,msm-id = <303 0x0>, <308 0x0>, <309 0x0>;
+ interrupt-parent = <&wakegic>;
+
+ chosen {
+ bootargs = "sched_enable_hmp=1";
+ };
+
+ aliases {
+ sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
+ sdhc2 = &sdhc_2; /* SDC2 for SD card */
+ spi3 = &spi_3;
+ spi6 = &spi_6;
+ i2c2 = &i2c_2;
+ i2c5 = &i2c_5;
+ i2c3 = &i2c_3;
+ i2c4 = &i2c_4;
+ };
+
+ firmware: firmware {
+ android {
+ compatible = "android,firmware";
+ vbmeta {
+ compatible = "android,vbmeta";
+ parts = "vbmeta,boot,system,vendor,dtbo,recovery";
+ };
+
+ fstab {
+ compatible = "android,fstab";
+ vendor {
+ compatible = "android,vendor";
+ dev = "/dev/block/platform/soc/7824900.sdhci/by-name/vendor";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,discard";
+ fsmgr_flags = "wait,avb";
+ status = "ok";
+ };
+ };
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ other_ext_mem: other_ext_region@0 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x85b00000 0x0 0xd00000>;
+ };
+
+ modem_mem: modem_region@0 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86800000 0x0 0x5500000>;
+ };
+
+ adsp_fw_mem: adsp_fw_region@0 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8bd00000 0x0 0x1100000>;
+ };
+
+ wcnss_fw_mem: wcnss_fw_region@0 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8ce00000 0x0 0x700000>;
+ };
+
+ venus_mem: venus_region@0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ alloc-ranges = <0x0 0x80000000 0x0 0x10000000>;
+ alignment = <0 0x400000>;
+ size = <0 0x0800000>;
+ };
+
+ qseecom_mem: qseecom_region@0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x1000000>;
+ };
+
+ qseecom_ta_mem: qseecom_ta_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x00000000 0 0xffffffff>;
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x400000>;
+ };
+
+ adsp_mem: adsp_region@0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x400000>;
+ };
+
+ cont_splash_mem: splash_region@83000000 {
+ reg = <0x0 0x90000000 0x0 0x1400000>;
+ };
+
+ dump_mem: mem_dump_region {
+ compatible = "shared-dma-pool";
+ reusable;
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ alignment = <0x0 0x400000>;
+ size = <0 0xd5000>;
+ };
+ };
+
+ clocks {
+ xo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ clock-output-names = "xo_board";
+ };
+ };
+
+ soc: soc { };
+
+ vendor: vendor {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+ };
+};
+
+#include "msm8917-pinctrl.dtsi"
+#include "msm8917-camera.dtsi"
+#include "msm8917-cpu.dtsi"
+#include "msm8917-pm.dtsi"
+#include "msm8917-ion.dtsi"
+#include "msm8917-coresight.dtsi"
+#include "msm8917-bus.dtsi"
+#include "msm8917-mdss.dtsi"
+#include "msm8917-mdss-pll.dtsi"
+#include "msm-arm-smmu-8917.dtsi"
+#include "msm8917-gpu.dtsi"
+#include "msm8917-vidc.dtsi"
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ intc: interrupt-controller@b000000 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <3>;
+ reg = <0x0b000000 0x1000>,
+ <0x0b002000 0x1000>;
+ };
+
+ dcc: dcc@b3000 {
+ compatible = "qcom,dcc";
+ reg = <0xb3000 0x1000>,
+ <0xb4000 0x2000>;
+ reg-names = "dcc-base", "dcc-ram-base";
+
+ clocks = <&gcc GCC_DCC_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,save-reg;
+ };
+
+ wakegic: wake-gic {
+ compatible = "qcom,mpm-gic-msm8937", "qcom,mpm-gic";
+ interrupts-extended = <&wakegic GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
+ reg = <0x601d0 0x1000>,
+ <0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */
+ reg-names = "vmpm", "ipc";
+ qcom,num-mpm-irqs = <64>;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <3>;
+ };
+
+ wakegpio: wake-gpio {
+ compatible = "qcom,mpm-gpio";
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <2>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 2 0xff08>,
+ <1 3 0xff08>,
+ <1 4 0xff08>,
+ <1 1 0xff08>;
+ clock-frequency = <19200000>;
+ };
+
+ qcom,sps {
+ compatible = "qcom,msm-sps-4k";
+ qcom,pipe-attr-ee;
+ };
+
+ thermal_zones: thermal-zones {};
+
+ mem_dump {
+ compatible = "qcom,mem-dump";
+ memory-region = <&dump_mem>;
+
+ rpm_sw_dump {
+ qcom,dump-size = <0x28000>;
+ qcom,dump-id = <0xea>;
+ };
+
+ pmic_dump {
+ qcom,dump-size = <0x10000>;
+ qcom,dump-id = <0xe4>;
+ };
+
+ vsense_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xe9>;
+ };
+
+ tmc_etf_dump {
+ qcom,dump-size = <0x10000>;
+ qcom,dump-id = <0xf0>;
+ };
+
+ tmc_etr_reg_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x100>;
+ };
+
+ tmc_etf_reg_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x101>;
+ };
+
+ misc_data_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xe8>;
+ };
+
+ c0_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x130>;
+ };
+
+ c100_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x131>;
+ };
+
+ c200_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x132>;
+ };
+
+ c300_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x133>;
+ };
+
+ c0_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x0>;
+ };
+
+ c1_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x1>;
+ };
+
+ c2_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x2>;
+ };
+
+ c3_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x3>;
+ };
+
+ l1_icache100 {
+ qcom,dump-size = <0x8800>;
+ qcom,dump-id = <0x60>;
+ };
+
+ l1_icache101 {
+ qcom,dump-size = <0x8800>;
+ qcom,dump-id = <0x61>;
+ };
+
+ l1_icache102 {
+ qcom,dump-size = <0x8800>;
+ qcom,dump-id = <0x62>;
+ };
+
+ l1_icache103 {
+ qcom,dump-size = <0x8800>;
+ qcom,dump-id = <0x63>;
+ };
+
+ l1_dcache100 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x80>;
+ };
+
+ l1_dcache101 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x81>;
+ };
+
+ l1_dcache102 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x82>;
+ };
+
+ l1_dcache103 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x83>;
+ };
+
+ };
+
+ tsens0: tsens@4a8000 {
+ compatible = "qcom,msm8937-tsens";
+ reg = <0x4a8000 0x1000>,
+ <0x4a9000 0x1000>,
+ <0xa4000 0x1000>;
+ reg-names = "tsens_srot_physical",
+ "tsens_tm_physical", "tsens_eeprom_physical";
+ interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tsens-upper-lower";
+ #thermal-sensor-cells = <1>;
+ };
+
+ timer@b120000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xb120000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@b121000 {
+ frame-number = <0>;
+ interrupts = <0 8 0x4>,
+ <0 7 0x4>;
+ reg = <0xb121000 0x1000>,
+ <0xb122000 0x1000>;
+ };
+
+ frame@b123000 {
+ frame-number = <1>;
+ interrupts = <0 9 0x4>;
+ reg = <0xb123000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b124000 {
+ frame-number = <2>;
+ interrupts = <0 10 0x4>;
+ reg = <0xb124000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b125000 {
+ frame-number = <3>;
+ interrupts = <0 11 0x4>;
+ reg = <0xb125000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b126000 {
+ frame-number = <4>;
+ interrupts = <0 12 0x4>;
+ reg = <0xb126000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b127000 {
+ frame-number = <5>;
+ interrupts = <0 13 0x4>;
+ reg = <0xb127000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b128000 {
+ frame-number = <6>;
+ interrupts = <0 14 0x4>;
+ reg = <0xb128000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ qcom,rmtfs_sharedmem@00000000 {
+ compatible = "qcom,sharedmem-uio";
+ reg = <0x00000000 0x00180000>;
+ reg-names = "rmtfs";
+ qcom,client-id = <0x00000001>;
+ };
+
+ restart@4ab000 {
+ compatible = "qcom,pshold";
+ reg = <0x4ab000 0x4>,
+ <0x193d100 0x4>;
+ reg-names = "pshold-base", "tcsr-boot-misc-detect";
+ };
+
+ qcom,mpm2-sleep-counter@4a3000 {
+ compatible = "qcom,mpm2-sleep-counter";
+ reg = <0x4a3000 0x1000>;
+ clock-frequency = <32768>;
+ };
+
+ cpu-pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <1 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ slim_msm: slim@c140000 {
+ cell-index = <1>;
+ compatible = "qcom,slim-ngd";
+ reg = <0xc140000 0x2c000>,
+ <0xc104000 0x2a000>;
+ reg-names = "slimbus_physical", "slimbus_bam_physical";
+ interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>,
+ <0 180 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "slimbus_irq", "slimbus_bam_irq";
+ qcom,apps-ch-pipes = <0x600000>;
+ qcom,ea-pc = <0x230>;
+ status = "disabled";
+ };
+
+
+ blsp1_uart2: serial@78b0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78b0000 0x200>;
+ interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ blsp1_uart1: uart@78af000 { /* BLSP1 UART1 */
+ compatible = "qcom,msm-hsuart-v14";
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ reg = <0x78af000 0x200>,
+ <0x7884000 0x1f000>;
+ reg-names = "core_mem", "bam_mem";
+ interrupt-parent = <&blsp1_uart1>;
+ interrupts = <0 1 2>;
+ interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
+ interrupt-map = <0 &intc 0 107 0
+ 1 &intc 0 238 0
+ 2 &tlmm 1 0>;
+ interrupt-map-mask = <0xffffffff>;
+
+ qcom,inject-rx-on-wakeup;
+ qcom,rx-char-to-inject = <0xFD>;
+
+ qcom,bam-tx-ep-pipe-index = <0>;
+ qcom,bam-rx-ep-pipe-index = <1>;
+ qcom,master-id = <86>;
+ clock-names = "core_clk", "iface_clk";
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ pinctrl-names = "sleep", "default";
+ pinctrl-0 = <&blsp1_uart1_sleep>;
+ pinctrl-1 = <&blsp1_uart1_active>;
+
+ qcom,msm-bus,name = "blsp1_uart1";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <86 512 0 0>,
+ <86 512 500 800>;
+ status = "disabled";
+ };
+
+ dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */
+ #dma-cells = <4>;
+ compatible = "qcom,sps-dma";
+ reg = <0x7884000 0x1f000>;
+ interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,summing-threshold = <10>;
+ };
+
+ dma_blsp2: qcom,sps-dma@7ac4000 { /* BLSP2 */
+ #dma-cells = <4>;
+ compatible = "qcom,sps-dma";
+ reg = <0x7ac4000 0x1f000>;
+ interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,summing-threshold = <10>;
+ };
+
+
+ /* IO Expander SX150xq */
+ /* BLSP1 QUP4 */
+ i2c_4: i2c@78b8000 {
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "qup_phys_addr";
+ reg = <0x78b8000 0x600>;
+ interrupt-names = "qup_irq";
+ interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
+ pinctrl-names = "i2c_active", "i2c_sleep";
+ pinctrl-0 = <&i2c_4_active>;
+ pinctrl-1 = <&i2c_4_sleep>;
+ qcom,noise-rjct-scl = <0>;
+ qcom,noise-rjct-sda = <0>;
+ qcom,master-id = <86>;
+ dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
+ <&dma_blsp1 11 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ rpm_bus: qcom,rpm-smd {
+ compatible = "qcom,rpm-smd";
+ rpm-channel-name = "rpm_requests";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ rpm-channel-type = <15>; /* SMD_APPS_RPM */
+ };
+
+ rpmcc: qcom,rpmcc {
+ compatible = "qcom,rpmcc-qm215";
+ #clock-cells = <1>;
+ };
+
+ gcc: qcom,gcc@1800000 {
+ compatible = "qcom,gcc-msm8917", "syscon";
+ reg = <0x1800000 0x80000>,
+ <0x00a6018 0x00004>;
+ reg-names = "cc_base", "gpu-bin";
+ qcom,gcc_oxili_gfx3d_clk-opp-handle = <&msm_gpu>;
+ vdd_cx-supply = <&pm8937_s2_level>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "bi_tcxo";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cpu_debug: syscon@0b01101c {
+ compatible = "syscon";
+ reg = <0x0b01101c 0x4>;
+ };
+
+ debugcc: qcom,cc-debug {
+ compatible = "qcom,qm215-debugcc";
+ reg = <0x1874000 0x4>,
+ <0xb01101c 0x8>;
+ reg-names = "cc_base", "meas";
+ qcom,gcc = <&gcc>;
+ qcom,cpu = <&cpu_debug>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo_clk_src";
+ #clock-cells = <1>;
+ };
+
+ gcc_mdss: qcom,gcc-mdss@1800000 {
+ compatible = "qcom,gcc-mdss-qm215";
+ reg = <0x1800000 0x80000>;
+ clocks = <&mdss_dsi0_pll PCLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>;
+ clock-names = "pclk0_src", "byte0_src";
+ #clock-cells = <1>;
+ };
+
+ apsscc: qcom,clock-cpu@b011050 {
+ compatible = "qcom,cpu-clock-qm215";
+ reg = <0xb011050 0x8>,
+ <0xb016000 0x34>,
+ <0x00a412c 0x8>,
+ <0xb011200 0x100>;
+ reg-names = "apcs-c1-rcg-base",
+ "apcs_pll1", "efuse", "spm_c1_base";
+ cpu-vdd-supply = <&apc_vreg_corner>;
+ vdd_dig_ao-supply = <&pm8916_s1_level_ao>;
+ vdd_hf_pll-supply = <&pm8916_l7_ao>;
+ clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
+ <&gcc GPLL0_AO_OUT_MAIN>;
+ clock-names = "xo_ao", "gpll0_ao" ;
+ qcom,speed0-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1094400000 2>,
+ < 1248000000 3>,
+ < 1401000000 4>;
+
+ qcom,speed1-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1094400000 2>,
+ < 1248000000 3>,
+ < 1401000000 4>,
+ < 1497600000 5>;
+
+ qcom,speed2-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1094400000 2>,
+ < 1209600000 3>;
+
+ qcom,speed3-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1094400000 2>,
+ < 1248000000 3>,
+ < 1305600000 4>;
+
+ #clock-cells = <1>;
+ };
+
+ msm_cpufreq: qcom,msm-cpufreq {
+ compatible = "qcom,msm-cpufreq";
+ clock-names = "cpu0_clk";
+ clocks = <&apsscc APCS_MUX_C1_CLK>;
+
+ qcom,governor-per-policy;
+
+ qcom,cpufreq-table =
+ < 960000 >,
+ < 1094400 >,
+ < 1209600 >,
+ < 1248000 >,
+ < 1305600 >,
+ < 1401000 >,
+ < 1497600 >;
+ };
+
+ i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "qup_phys_addr";
+ reg = <0x78b6000 0x600>;
+ interrupt-names = "qup_irq";
+ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ pinctrl-names = "i2c_active", "i2c_sleep";
+ pinctrl-0 = <&i2c_2_active>;
+ pinctrl-1 = <&i2c_2_sleep>;
+ qcom,noise-rjct-scl = <0>;
+ qcom,noise-rjct-sda = <0>;
+ qcom,master-id = <86>;
+ dmas = <&dma_blsp1 6 64 0x20000020 0x20>,
+ <&dma_blsp1 7 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "qup_phys_addr";
+ reg = <0x78b7000 0x600>;
+ interrupt-names = "qup_irq";
+ interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+
+ pinctrl-names = "i2c_active", "i2c_sleep";
+ pinctrl-0 = <&i2c_3_active>;
+ pinctrl-1 = <&i2c_3_sleep>;
+ qcom,noise-rjct-scl = <0>;
+ qcom,noise-rjct-sda = <0>;
+ qcom,master-id = <86>;
+ dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
+ <&dma_blsp1 9 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c_5: i2c@7af5000 { /* BLSP2 QUP1 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "qup_phys_addr";
+ reg = <0x7af5000 0x600>;
+ interrupt-names = "qup_irq";
+ interrupts = <0 299 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
+
+ pinctrl-names = "i2c_active", "i2c_sleep";
+ pinctrl-0 = <&i2c_5_active>;
+ pinctrl-1 = <&i2c_5_sleep>;
+ qcom,noise-rjct-scl = <0>;
+ qcom,noise-rjct-sda = <0>;
+ qcom,master-id = <84>;
+ dmas = <&dma_blsp2 4 64 0x20000020 0x20>,
+ <&dma_blsp2 5 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi_3: spi@78b7000 { /* BLSP1 QUP3 */
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "spi_physical", "spi_bam_physical";
+ reg = <0x78b7000 0x600>,
+ <0x7884000 0x1f000>;
+ interrupt-names = "spi_irq", "spi_bam_irq";
+ interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>,
+ <0 238 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ pinctrl-names = "spi_default", "spi_sleep";
+ pinctrl-0 = <&spi3_default &spi3_cs0_active>;
+ pinctrl-1 = <&spi3_sleep &spi3_cs0_sleep>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
+ clock-names = "iface_clk", "core_clk";
+ qcom,infinite-mode = <0>;
+ qcom,use-bam;
+ qcom,use-pinctrl;
+ qcom,ver-reg-exists;
+ qcom,bam-consumer-pipe-index = <8>;
+ qcom,bam-producer-pipe-index = <9>;
+ qcom,master-id = <86>;
+ status = "disabled";
+ };
+
+ usb_otg: usb@78db000 {
+ compatible = "qcom,hsusb-otg";
+ reg = <0x78db000 0x400>, <0x6c000 0x200>;
+ reg-names = "core", "phy_csr";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupts = <0 134 IRQ_TYPE_LEVEL_HIGH>,
+ <0 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "core_irq", "async_irq";
+
+ hsusb_vdd_dig-supply = <&pm8937_l2>;
+ HSUSB_1p8-supply = <&pm8937_l7>;
+ HSUSB_3p3-supply = <&pm8937_l13>;
+ qcom,vdd-voltage-level = <0 1200000 1200000>;
+ vbus_otg-supply = <&smbcharger_charger_otg>;
+
+ qcom,hsusb-otg-phy-type = <3>; /* SNPS Femto PHY */
+ qcom,hsusb-otg-mode = <3>; /* OTG mode */
+ qcom,hsusb-otg-otg-control = <2>; /* PMIC */
+ qcom,dp-manual-pullup;
+ qcom,phy-dvdd-always-on;
+ qcom,boost-sysclk-with-streaming;
+ qcom,axi-prefetch-enable;
+ qcom,enable-sdp-typec-current-limit;
+ qcom,hsusb-otg-delay-lpm;
+
+ qcom,msm-bus,name = "usb2";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <87 512 0 0>,
+ <87 512 80000 0>,
+ <87 512 6000 6000>;
+ clocks = <&gcc GCC_USB_HS_AHB_CLK>,
+ <&gcc GCC_USB_HS_SYSTEM_CLK>,
+ <&gcc GCC_USB2A_PHY_SLEEP_CLK>,
+ <&rpmcc BIMC_USB_A_CLK>,
+ <&rpmcc SNOC_USB_A_CLK>,
+ <&rpmcc PNOC_USB_A_CLK>,
+ <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+ <&rpmcc CXO_SMD_OTG_CLK>;
+ clock-names = "iface_clk", "core_clk", "sleep_clk",
+ "bimc_clk", "snoc_clk", "pcnoc_clk",
+ "phy_csr_clk", "xo";
+ qcom,bus-clk-rate = <595200000 200000000 100000000>;
+ qcom,max-nominal-sysclk-rate = <133330000>;
+
+ resets = <&gcc GCC_USB_HS_BCR>,
+ <&gcc GCC_QUSB2_PHY_BCR>,
+ <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
+ reset-names = "core_reset", "phy_reset", "phy_por_reset";
+
+ qcom,usbbam@78c4000 {
+ compatible = "qcom,usb-bam-msm";
+ reg = <0x78c4000 0x17000>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 135 IRQ_TYPE_LEVEL_HIGH>;
+
+ qcom,bam-type = <1>;
+ qcom,usb-bam-num-pipes = <4>;
+ qcom,usb-bam-fifo-baseaddr = <0x08605000>;
+ qcom,ignore-core-reset-ack;
+ qcom,disable-clk-gating;
+ qcom,usb-bam-max-mbps-highspeed = <400>;
+ qcom,reset-bam-on-disconnect;
+
+ qcom,pipe0 {
+ label = "hsusb-qdss-in-0";
+ qcom,usb-bam-mem-type = <2>;
+ qcom,dir = <1>;
+ qcom,pipe-num = <0>;
+ qcom,peer-bam = <0>;
+ qcom,peer-bam-physical-address = <0x6044000>;
+ qcom,src-bam-pipe-index = <0>;
+ qcom,dst-bam-pipe-index = <0>;
+ qcom,data-fifo-offset = <0x0>;
+ qcom,data-fifo-size = <0xe00>;
+ qcom,descriptor-fifo-offset = <0xe00>;
+ qcom,descriptor-fifo-size = <0x200>;
+ };
+ };
+ };
+
+ ddr_bw_opp_table: ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 100, 8); /* 769 MB/s */
+ BW_OPP_ENTRY( 211, 8); /* 1611 MB/s */
+ BW_OPP_ENTRY( 297, 8); /* 2270 MB/s */
+ BW_OPP_ENTRY( 384, 8); /* 2929 MB/s */
+ BW_OPP_ENTRY( 556, 8); /* 4248 MB/s */
+ BW_OPP_ENTRY( 595, 8); /* 4541 MB/s */
+ BW_OPP_ENTRY( 672, 8); /* 5126 MB/s */
+ BW_OPP_ENTRY( 740, 8); /* 5645 MB/s */
+ };
+
+ cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@408000 {
+ compatible = "qcom,bimc-bwmon2";
+ reg = <0x408000 0x300>, <0x401000 0x200>;
+ reg-names = "base", "global_base";
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,target-dev = <&cpu_cpu_ddr_bw>;
+ };
+
+ cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ cpu0_computemon: qcom,cpu0-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 998400 MHZ_TO_MBPS(230, 8) >,
+ < 1094400 MHZ_TO_MBPS(557, 8) >,
+ < 1497600 MHZ_TO_MBPS(557, 8) >;
+ };
+ };
+
+ qcom,wdt@b017000 {
+ compatible = "qcom,msm-watchdog";
+ reg = <0xb017000 0x1000>;
+ reg-names = "wdt-base";
+ interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 4 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bark-time = <11000>;
+ qcom,pet-time = <10000>;
+ qcom,ipi-ping;
+ qcom,wakeup-enable;
+ };
+
+ qcom,memshare {
+ compatible = "qcom,memshare";
+
+ qcom,client_1 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x200000>;
+ qcom,client-id = <0>;
+ qcom,allocate-boot-time;
+ label = "modem";
+ };
+
+ qcom,client_2 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x300000>;
+ qcom,client-id = <2>;
+ label = "modem";
+ };
+
+ mem_client_3_size: qcom,client_3 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x0>;
+ qcom,client-id = <1>;
+ label = "modem";
+ };
+ };
+
+ spmi_bus: qcom,spmi@200f000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x200f000 0x1000>,
+ <0x2400000 0x800000>,
+ <0x2c00000 0x800000>,
+ <0x3800000 0x200000>,
+ <0x200a000 0x2100>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
+ qcom,msm-rtb {
+ compatible = "qcom,msm-rtb";
+ qcom,rtb-size = <0x100000>; /* 1M EBI1 buffer */
+ };
+
+ qcom,msm-imem@8600000 {
+ compatible = "qcom,msm-imem";
+ reg = <0x08600000 0x1000>; /* Address and size of IMEM */
+ ranges = <0x0 0x08600000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mem_dump_table@10 {
+ compatible = "qcom,msm-imem-mem_dump_table";
+ reg = <0x10 0x8>;
+ };
+
+ dload_type@1c {
+ compatible = "qcom,msm-imem-dload-type";
+ reg = <0x1c 0x4>;
+ };
+
+ restart_reason@65c {
+ compatible = "qcom,msm-imem-restart_reason";
+ reg = <0x65c 0x4>;
+ };
+
+ boot_stats@6b0 {
+ compatible = "qcom,msm-imem-boot_stats";
+ reg = <0x6b0 0x20>;
+ };
+
+ kaslr_offset@6d0 {
+ compatible = "qcom,msm-imem-kaslr_offset";
+ reg = <0x6d0 0xc>;
+ };
+
+ pil@94c {
+ compatible = "qcom,msm-imem-pil";
+ reg = <0x94c 0xc8>;
+ };
+
+ diag_dload@c8 {
+ compatible = "qcom,msm-imem-diag-dload";
+ reg = <0xc8 0xc8>;
+ };
+ };
+
+ jtag_mm0: jtagmm@61bc000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x61bc000 0x1000>,
+ <0x61b0000 0x1000>;
+ reg-names = "etm-base", "debug-base";
+
+ qcom,coresight-jtagmm-cpu = <&CPU0>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+ };
+
+ jtag_mm1: jtagmm@61bd000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x61bd000 0x1000>,
+ <0x61b2000 0x1000>;
+ reg-names = "etm-base", "debug-base";
+
+ qcom,coresight-jtagmm-cpu = <&CPU1>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+ };
+
+ jtag_mm2: jtagmm@61be000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x61be000 0x1000>,
+ <0x61b4000 0x1000>;
+ reg-names = "etm-base", "debug-base";
+
+ qcom,coresight-jtagmm-cpu = <&CPU2>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+ };
+
+ jtag_mm3: jtagmm@61bf000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x61bf000 0x1000>,
+ <0x61b6000 0x1000>;
+ reg-names = "etm-base", "debug-base";
+
+ qcom,coresight-jtagmm-cpu = <&CPU3>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+ };
+
+ qcom,ipc-spinlock@1905000 {
+ compatible = "qcom,ipc-spinlock-sfpb";
+ reg = <0x1905000 0x8000>;
+ qcom,num-locks = <8>;
+ };
+
+ apcs: syscon@0b011008 {
+ compatible = "syscon";
+ reg = <0x0b011008 0x04>;
+ };
+
+ tcsr_mutex_block: syscon@01905000 {
+ compatible = "syscon";
+ reg = <0x01905000 0x20000>;
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_block 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ rpm_msg_ram: memory@60000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x60000 0x8000>;
+ };
+
+ smem_mem: smem_region@86300000 {
+ no-map;
+ reg = <0x86300000 0x100000>;
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ smp2p-modem {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 0 14>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 0 10>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sleepstate_smp2p_out: sleepstate-out {
+ qcom,entry-name = "sleepstate";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ sleepstate_smp2p_in: qcom,sleepstate-in {
+ qcom,entry-name = "sleepstate_see";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p_sleepstate {
+ compatible = "qcom,smp2p-sleepstate";
+ qcom,smem-states = <&sleepstate_smp2p_out 0>;
+ interrupt-parent = <&sleepstate_smp2p_in>;
+ interrupts = <0 0>;
+ interrupt-names = "smp2p-sleepstate-in";
+ };
+
+ smp2p-wcnss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <451>, <431>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 0 18>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <4>;
+
+ wcnss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wcnss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smd {
+ compatible = "qcom,smd";
+
+ modem {
+ interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 0 12>;
+ qcom,smd-edge = <0>;
+ qcom,remote-pid = <1>;
+ label = "mpss";
+
+ qcom,smd-channels = "IPCRTR";
+ qcom,modem_qrtr {
+ qcom,net-id = <1>;
+ qcom,low-latency;
+ };
+
+ qcom,diag {
+ qcom,smd-channels = "DIAG";
+ };
+
+ qcom,diag_cntl {
+ qcom,smd-channels = "DIAG_CNTL";
+ };
+
+ qcom,diag_cmd {
+ qcom,smd-channels = "DIAG_CMD";
+ };
+
+ qcom,diag_dci {
+ qcom,smd-channels = "DIAG_2";
+ };
+
+ qcom.diag_dci_cmd {
+ qcom,smd-channels = "DIAG_2_CMD";
+ };
+ };
+
+ adsp {
+ interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 0 8>;
+ qcom,smd-edge = <1>;
+ qcom,remote-pid = <2>;
+ mbox-names = "adsp_smem";
+ label = "adsp";
+
+ qcom,smd-channels = "IPCRTR";
+ qcom,adsp_qrtr {
+ qcom,net-id = <1>;
+ qcom,low-latency;
+ };
+
+ qcom,diag {
+ qcom,smd-channels = "DIAG";
+ };
+
+ qcom,diag_cntl {
+ qcom,smd-channels = "DIAG_CNTL";
+ };
+
+ qcom,apr_tal_rpmsg {
+ qcom,smd-channels = "apr_audio_svc";
+ };
+ };
+
+ wcnss {
+ interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 0 17>;
+ qcom,smd-edge = <6>;
+ qcom,remote-pid = <4>;
+ label = "wcnss";
+
+ qcom,smd-channels = "IPCRTR";
+ qcom,wcnss_qrtr {
+ qcom,net-id = <1>;
+ qcom,low-latency;
+ };
+
+ qcom,diag {
+ qcom,smd-channels = "APPS_RIVA_DATA";
+ };
+
+ qcom,diag_cntl {
+ qcom,smd-channels = "APPS_RIVA_CTRL";
+ };
+ };
+
+ rpm {
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 0 0>;
+ qcom,smd-edge = <15>;
+ label = "rpm";
+
+ rpm_requests: rpm_requests@0 {
+ compatible = "qcom,rpm-smd";
+ qcom,smd-channels = "rpm_requests";
+ };
+ };
+
+ };
+
+ qcom,smsm {
+ compatible = "qcom,smsm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ipc-1 = <&apcs 0 13>;
+ qcom,ipc-2 = <&apcs 0 9>;
+ qcom,ipc-3 = <&apcs 0 19>;
+
+ apps_smsm: apps@0 {
+ reg = <0>;
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smsm: modem@1 {
+ reg = <1>;
+ interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ adsp_smsm: adsp@2 {
+ reg = <2>;
+ interrupts = <0 290 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ wcnss_smsm: wcnss@3 {
+ reg = <3>;
+ interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smdpkt {
+ compatible = "qcom,smdpkt";
+
+ qcom,smdpkt-data5-cntl {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA5_CNTL";
+ qcom,smdpkt-dev-name = "smdcntl0";
+ };
+
+ qcom,smdpkt-data22 {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA22";
+ qcom,smdpkt-dev-name = "smd22";
+ };
+
+ qcom,smdpkt-data40-cntl {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA40_CNTL";
+ qcom,smdpkt-dev-name = "smdcntl8";
+ };
+
+ qcom,smdpkt-data2 {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA2";
+ qcom,smdpkt-dev-name = "at_mdm0";
+ };
+
+ qcom,smdpkt-apr-apps2 {
+ qcom,smdpkt-edge = "adsp";
+ qcom,smdpkt-ch-name = "apr_apps2";
+ qcom,smdpkt-dev-name = "apr_apps2";
+ };
+
+ qcom,smdpkt-apps-riva-bt-acl {
+ qcom,smdpkt-edge = "wcnss";
+ qcom,smdpkt-ch-name = "APPS_RIVA_BT_ACL";
+ qcom,smdpkt-dev-name = "smd2";
+ qcom,smdpkt-fragmented-read;
+ };
+
+ qcom,smdpkt-apps-riva-bt-cmd {
+ qcom,smdpkt-edge = "wcnss";
+ qcom,smdpkt-ch-name = "APPS_RIVA_BT_CMD";
+ qcom,smdpkt-dev-name = "smd3";
+ qcom,smdpkt-fragmented-read;
+ };
+
+ qcom,smdpkt-mbalbridge {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "MBALBRIDGE";
+ qcom,smdpkt-dev-name = "smd4";
+ };
+
+ qcom,smdpkt-apps-riva-ant-cmd {
+ qcom,smdpkt-edge = "wcnss";
+ qcom,smdpkt-ch-name = "APPS_RIVA_ANT_CMD";
+ qcom,smdpkt-dev-name = "smd5";
+ };
+
+ qcom,smdpkt-apps-riva-ant-data {
+ qcom,smdpkt-edge = "wcnss";
+ qcom,smdpkt-ch-name = "APPS_RIVA_ANT_DATA";
+ qcom,smdpkt-dev-name = "smd6";
+ };
+
+ qcom,smdpkt-data1 {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA1";
+ qcom,smdpkt-dev-name = "smd7";
+ };
+
+ qcom,smdpkt-data4 {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA4";
+ qcom,smdpkt-dev-name = "smd8";
+ };
+
+ qcom,smdpkt-data11 {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA11";
+ qcom,smdpkt-dev-name = "smd11";
+ };
+
+ qcom,smdpkt-data21 {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA21";
+ qcom,smdpkt-dev-name = "smd21";
+ };
+ };
+
+ qcom_tzlog: tz-log@8600720 {
+ compatible = "qcom,tz-log";
+ reg = <0x08600720 0x2000>;
+ };
+
+ bam_dmux: qcom,bam_dmux@4044000 {
+ compatible = "qcom,bam_dmux";
+ reg = <0x4044000 0x19000>;
+ qcom,rx-ring-size = <32>;
+ qcom,max-rx-mtu = <4096>;
+ qcom,fast-shutdown;
+ qcom,no-cpu-affinity;
+
+ qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
+ qcom,smem-state-names = "pwrctrl", "pwrctrlack";
+
+ interrupts-extended =
+ <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smsm 1 IRQ_TYPE_EDGE_BOTH>,
+ <&modem_smsm 11 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "dmux", "ctrl", "ack";
+ };
+
+ sdcc1_ice: sdcc1ice@7803000 {
+ compatible = "qcom,ice";
+ reg = <0x7803000 0x8000>;
+ interrupt-names = "sdcc_ice_nonsec_level_irq",
+ "sdcc_ice_sec_level_irq";
+ interrupts = <0 312 IRQ_TYPE_LEVEL_HIGH>,
+ <0 313 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,enable-ice-clk;
+ clock-names = "ice_core_clk_src", "ice_core_clk",
+ "bus_clk", "iface_clk";
+ clocks = <&gcc SDCC1_ICE_CORE_CLK_SRC>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>;
+ qcom,op-freq-hz = <200000000>, <0>, <0>, <0>;
+ qcom,msm-bus,name = "sdcc_ice_noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <78 512 0 0>, /* No vote */
+ <78 512 1000 0>; /* Max. bandwidth */
+ qcom,bus-vector-names = "MIN", "MAX";
+ qcom,instance-type = "sdcc";
+ };
+
+ sdhc_1: sdhci@7824900 {
+ compatible = "qcom,sdhci-msm", "qcom,sdhci-msm-cqe";
+ reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>,
+ <0x7803000 0x8000>;
+ reg-names = "hc_mem", "core_mem", "cqhci_mem", "cqhci_ice";
+
+ interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <8>;
+ qcom,large-address-bus;
+
+ qcom,devfreq,freq-table = <50000000 200000000>;
+
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <13 651>;
+
+ qcom,pm-qos-cpu-groups = <0x0f>;
+ qcom,pm-qos-cmdq-latency-us = <13 651>;
+
+ qcom,pm-qos-legacy-latency-us = <13 651>;
+
+ qcom,msm-bus,name = "sdhc1";
+ qcom,msm-bus,num-cases = <9>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
+ <78 512 1046 3200>, /* 400 KB/s*/
+ <78 512 52286 160000>, /* 20 MB/s */
+ <78 512 65360 200000>, /* 25 MB/s */
+ <78 512 130718 400000>, /* 50 MB/s */
+ <78 512 130718 400000>, /* 100 MB/s */
+ <78 512 261438 800000>, /* 200 MB/s */
+ <78 512 261438 800000>, /* 400 MB/s */
+ <78 512 1338562 4096000>; /* Max. bandwidth */
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000
+ 50000000 100000000 200000000 400000000 4294967295>;
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface_clk", "core_clk", "ice_core_clk";
+ qcom,ice-clk-rates = <200000000 100000000>;
+
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x00076400 0x0 0x0 0x0 0x00040868>;
+
+ qcom,scaling-lower-bus-speed-mode = "DDR52";
+ status = "disabled";
+ };
+
+ sdhc_2: sdhci@7864900 {
+ compatible = "qcom,sdhci-msm";
+ reg = <0x7864900 0x500>, <0x7864000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+
+ interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <4>;
+ qcom,large-address-bus;
+
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <13 651>;
+
+ qcom,pm-qos-cpu-groups = <0x0f>;
+ qcom,pm-qos-legacy-latency-us = <13 651>;
+
+ qcom,msm-bus,name = "sdhc2";
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
+ <81 512 1046 3200>, /* 400 KB/s*/
+ <81 512 52286 160000>, /* 20 MB/s */
+ <81 512 65360 200000>, /* 25 MB/s */
+ <81 512 130718 400000>, /* 50 MB/s */
+ <81 512 261438 800000>, /* 100 MB/s */
+ <81 512 261438 800000>, /* 200 MB/s */
+ <81 512 1338562 4096000>; /* Max. bandwidth */
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100000000 200000000 4294967295>;
+
+ qcom,devfreq,freq-table = <50000000 200000000>;
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>;
+ clock-names = "iface_clk", "core_clk";
+
+ status = "disabled";
+ };
+
+ qcom_seecom: qseecom@85b00000 {
+ compatible = "qcom,qseecom";
+ reg = <0x85b00000 0x800000>;
+ reg-names = "secapp-region";
+ qcom,hlos-num-ce-hw-instances = <1>;
+ qcom,hlos-ce-hw-instance = <0>;
+ qcom,qsee-ce-hw-instance = <0>;
+ qcom,disk-encrypt-pipe-pair = <2>;
+ qcom,support-fde;
+ qcom,msm-bus,name = "qseecom-noc";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,support-bus-scaling;
+ qcom,msm-bus,vectors-KBps =
+ <55 512 0 0>,
+ <55 512 0 0>,
+ <55 512 120000 1200000>,
+ <55 512 393600 3936000>;
+ clocks = <&gcc CRYPTO_CLK_SRC>,
+ <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>;
+ clock-names = "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ qcom,ce-opp-freq = <100000000>;
+ };
+
+ qcom,iris-fm {
+ compatible = "qcom,iris_fm";
+ };
+
+ qcom,mss@4080000 {
+ compatible = "qcom,pil-q6v55-mss";
+ reg = <0x04080000 0x100>,
+ <0x0194f000 0x010>,
+ <0x01950000 0x008>,
+ <0x01951000 0x008>,
+ <0x04020000 0x040>,
+ <0x01871000 0x004>;
+ reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc",
+ "rmb_base", "restart_reg";
+
+ interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>;
+ vdd_mss-supply = <&pm8937_s1>;
+ vdd_cx-supply = <&pm8937_s2_level>;
+ vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ vdd_mx-supply = <&pm8937_l3_level_ao>;
+ vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ vdd_pll-supply = <&pm8937_l7>;
+ qcom,vdd_pll = <1800000>;
+ vdd_mss-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+
+ clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>,
+ <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
+ <&gcc GCC_BOOT_ROM_AHB_CLK>;
+ clock-names = "xo", "iface_clk", "bus_clk", "mem_clk";
+ qcom,proxy-clock-names = "xo";
+ qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk";
+
+ qcom,firmware-name = "modem";
+ qcom,pil-self-auth;
+ qcom,sequential-fw-load;
+ qcom,override-acc-1 = <0x80800000>;
+ qcom,sysmon-id = <0>;
+ qcom,ssctl-instance-id = <0x12>;
+ qcom,qdsp6v56-1-8-inrush-current;
+ qcom,reset-clk;
+ qcom,iommu-vmid = <0xF>; /* VMID_MSS_MSA */
+ /* Inputs from mss */
+ /* TBD */
+ interrupts-extended = <&modem_smp2p_in 0 0>,
+ <&modem_smp2p_in 1 0>,
+ <&modem_smp2p_in 2 0>,
+ <&modem_smp2p_in 3 0>,
+ <&modem_smp2p_in 7 0>;
+
+ interrupt-names = "qcom,err-fatal",
+ "qcom,err-ready",
+ "qcom,proxy-unvote",
+ "qcom,stop-ack",
+ "qcom,shutdown-ack";
+
+ /* Output to mss */
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ memory-region = <&modem_mem>;
+ };
+
+ qcom,lpass@c200000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0xc200000 0x00100>;
+ interrupts = <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>;
+
+ vdd_cx-supply = <&pm8937_s2_level>;
+ qcom,proxy-reg-names = "vdd_cx";
+ qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
+
+ clocks = <&rpmcc CXO_SMD_PIL_PRONTO_CLK>,
+ <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>,
+ <&gcc CRYPTO_CLK_SRC>;
+ clock-names = "xo", "scm_core_clk", "scm_iface_clk",
+ "scm_bus_clk", "scm_core_clk_src";
+ qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",
+ "scm_bus_clk", "scm_core_clk_src";
+ qcom,scm_core_clk_src-freq = <80000000>;
+
+ qcom,mas-crypto = <&mas_crypto>;
+ qcom,pas-id = <1>;
+ qcom,complete-ramdump;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <423>;
+ qcom,sysmon-id = <1>;
+ qcom,ssctl-instance-id = <0x14>;
+ qcom,firmware-name = "adsp";
+
+ /* Inputs from lpass */
+ /* TBD */
+ interrupts-extended = <&adsp_smp2p_in 0 0>,
+ <&adsp_smp2p_in 2 0>,
+ <&adsp_smp2p_in 1 0>,
+ <&adsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack";
+
+ /* Output to lpass */
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ memory-region = <&adsp_fw_mem>;
+ };
+
+ qcom,pronto@a21b000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x0a21b000 0x3000>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>;
+
+ vdd_pronto_pll-supply = <&pm8937_l7>;
+ proxy-reg-names = "vdd_pronto_pll";
+ vdd_pronto_pll-uV-uA = <1800000 18000>;
+ clocks = <&rpmcc CXO_SMD_PIL_PRONTO_CLK>,
+ <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>,
+ <&gcc CRYPTO_CLK_SRC>;
+
+ clock-names = "xo", "scm_core_clk", "scm_iface_clk",
+ "scm_bus_clk", "scm_core_clk_src";
+ qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",
+ "scm_bus_clk", "scm_core_clk_src";
+ qcom,scm_core_clk_src = <80000000>;
+
+ qcom,mas-crypto = <&mas_crypto>;
+ qcom,pas-id = <6>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <422>;
+ qcom,sysmon-id = <6>;
+ qcom,ssctl-instance-id = <0x13>;
+ qcom,firmware-name = "wcnss";
+
+ /* Inputs from wcnss */
+ /* TBD */
+ interrupts-extended = <&wcnss_smp2p_in 0 0>,
+ <&wcnss_smp2p_in 1 0>,
+ <&wcnss_smp2p_in 2 0>,
+ <&wcnss_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,err-fatal",
+ "qcom,err-ready",
+ "qcom,proxy-unvote",
+ "qcom,stop-ack";
+
+ /* Output to wcnss */
+ qcom,smem-states = <&wcnss_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ memory-region = <&wcnss_fw_mem>;
+ };
+
+ qcom,venus@1de0000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x1de0000 0x4000>;
+
+ vdd-supply = <&gdsc_venus>;
+ qcom,proxy-reg-names = "vdd";
+
+ clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
+ <&gcc GCC_VENUS0_AHB_CLK>,
+ <&gcc GCC_VENUS0_AXI_CLK>,
+ <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>,
+ <&gcc CRYPTO_CLK_SRC>;
+
+ clock-names = "core_clk", "iface_clk", "bus_clk",
+ "scm_core_clk", "scm_iface_clk",
+ "scm_bus_clk", "scm_core_clk_src";
+
+ qcom,proxy-clock-names = "core_clk", "iface_clk",
+ "bus_clk", "scm_core_clk",
+ "scm_iface_clk", "scm_bus_clk",
+ "scm_core_clk_src";
+ qcom,scm_core_clk_src-freq = <80000000>;
+
+ qcom,msm-bus,name = "pil-venus";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <63 512 0 0>,
+ <63 512 0 304000>;
+
+ qcom,mas-crypto = <&mas_crypto>;
+ qcom,pas-id = <9>;
+ qcom,proxy-timeout-ms = <100>;
+ qcom,firmware-name = "venus";
+ memory-region = <&venus_mem>;
+ };
+
+ qcom_rng: qrng@e3000 {
+ compatible = "qcom,msm-rng";
+ reg = <0xe3000 0x1000>;
+ qcom,msm-rng-iface-clk;
+ qcom,no-qrng-config;
+ qcom,msm-bus,name = "msm-rng-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 618 0 0>, /* No vote */
+ <1 618 0 800>; /* 100 MB/s */
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "iface_clk";
+ };
+
+ qcom_crypto: qcrypto@720000 {
+ compatible = "qcom,qcrypto";
+ reg = <0x720000 0x20000>,
+ <0x704000 0x20000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <2>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,ce-hw-shared;
+ qcom,clk-mgmt-sus-res;
+ qcom,msm-bus,name = "qcrypto-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <55 512 0 0>,
+ <55 512 393600 393600>;
+ clocks = <&gcc CRYPTO_CLK_SRC>,
+ <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>;
+ clock-names = "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ qcom,use-sw-aes-cbc-ecb-ctr-algo;
+ qcom,use-sw-aes-xts-algo;
+ qcom,use-sw-aes-ccm-algo;
+ qcom,use-sw-ahash-algo;
+ qcom,use-sw-hmac-algo;
+ qcom,use-sw-aead-algo;
+ qcom,ce-opp-freq = <100000000>;
+ };
+
+ qcom_cedev: qcedev@720000 {
+ compatible = "qcom,qcedev";
+ reg = <0x720000 0x20000>,
+ <0x704000 0x20000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <1>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,ce-hw-shared;
+ qcom,msm-bus,name = "qcedev-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <55 512 0 0>,
+ <55 512 393600 393600>;
+ clocks = <&gcc CRYPTO_CLK_SRC>,
+ <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>;
+ clock-names = "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ qcom,ce-opp-freq = <100000000>;
+ };
+
+ qcom,adsprpc-mem {
+ compatible = "qcom,msm-adsprpc-mem-region";
+ memory-region = <&adsp_mem>;
+ };
+
+ qcom,msm_fastrpc {
+ compatible = "qcom,msm-fastrpc-legacy-compute";
+ qcom,msm_fastrpc_compute_cb {
+ compatible = "qcom,msm-fastrpc-legacy-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_iommu 0x2008 0x7>;
+ sids = <0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>;
+ };
+ };
+
+ spi_6: spi@7af6000 { /* BLSP2 QUP2 */
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "spi_physical", "spi_bam_physical";
+ reg = <0x7af6000 0x600>,
+ <0x7ac4000 0x1d000>;
+ interrupt-names = "spi_irq", "spi_bam_irq";
+ interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>,
+ <0 239 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ pinctrl-names = "spi_default", "spi_sleep";
+ pinctrl-0 = <&spi6_default &spi6_cs0_active>;
+ pinctrl-1 = <&spi6_sleep &spi6_cs0_sleep>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>;
+ clock-names = "iface_clk", "core_clk";
+ qcom,infinite-mode = <0>;
+ qcom,use-bam;
+ qcom,use-pinctrl;
+ qcom,ver-reg-exists;
+ qcom,bam-consumer-pipe-index = <6>;
+ qcom,bam-producer-pipe-index = <7>;
+ qcom,master-id = <84>;
+ status = "disabled";
+ };
+
+ qcom,wcnss-wlan@a000000 {
+ compatible = "qcom,wcnss_wlan";
+ reg = <0xa000000 0x280000>,
+ <0xb011008 0x4>,
+ <0xa21b000 0x3000>,
+ <0x3204000 0x100>,
+ <0x3200800 0x200>,
+ <0xa100400 0x200>,
+ <0xa205050 0x200>,
+ <0xa219000 0x20>,
+ <0xa080488 0x8>,
+ <0xa080fb0 0x8>,
+ <0xa08040c 0x8>,
+ <0xa0120a8 0x8>,
+ <0xa012448 0x8>,
+ <0xa080c00 0x1>;
+
+ reg-names = "wcnss_mmio", "wcnss_fiq",
+ "pronto_phy_base", "riva_phy_base",
+ "riva_ccu_base", "pronto_a2xb_base",
+ "pronto_ccpu_base", "pronto_saw2_base",
+ "wlan_tx_phy_aborts","wlan_brdg_err_source",
+ "wlan_tx_status", "alarms_txctl",
+ "alarms_tactl", "pronto_mcu_base";
+
+ interrupts = <0 145 IRQ_TYPE_EDGE_RISING>,
+ <0 146 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
+
+ qcom,pronto-vddmx-supply = <&pm8937_l3_level_ao>;
+ qcom,pronto-vddcx-supply = <&pm8937_s2_level>;
+ qcom,pronto-vddpx-supply = <&pm8937_l5>;
+ qcom,iris-vddxo-supply = <&pm8937_l7>;
+ qcom,iris-vddrfa-supply = <&pm8937_l19>;
+ qcom,iris-vddpa-supply = <&pm8937_l9>;
+ qcom,iris-vdddig-supply = <&pm8937_l5>;
+
+ qcom,iris-vddxo-voltage-level = <1800000 0 1800000>;
+ qcom,iris-vddrfa-voltage-level = <1300000 0 1300000>;
+ qcom,iris-vddpa-voltage-level = <3300000 0 3300000>;
+ qcom,iris-vdddig-voltage-level = <1800000 0 1800000>;
+
+ qcom,vddmx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_TURBO
+ RPM_SMD_REGULATOR_LEVEL_NONE
+ RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,vddcx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_NOM
+ RPM_SMD_REGULATOR_LEVEL_NONE
+ RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,vddpx-voltage-level = <1800000 0 1800000>;
+
+ qcom,iris-vddxo-current = <10000>;
+ qcom,iris-vddrfa-current = <100000>;
+ qcom,iris-vddpa-current = <515000>;
+ qcom,iris-vdddig-current = <10000>;
+
+ qcom,pronto-vddmx-current = <0>;
+ qcom,pronto-vddcx-current = <0>;
+ qcom,pronto-vddpx-current = <0>;
+
+ pinctrl-names = "wcnss_default", "wcnss_sleep",
+ "wcnss_gpio_default";
+ pinctrl-0 = <&wcnss_default>;
+ pinctrl-1 = <&wcnss_sleep>;
+ pinctrl-2 = <&wcnss_gpio_default>;
+
+ gpios = <&tlmm 76 0>, <&tlmm 77 0>, <&tlmm 78 0>,
+ <&tlmm 79 0>, <&tlmm 80 0>;
+
+ clocks = <&rpmcc CXO_SMD_WLAN_CLK>,
+ <&rpmcc RPM_SMD_RF_CLK2>;
+
+ clock-names = "xo", "rf_clk";
+
+ qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>, <&apps_smsm 12>;
+ qcom,smem-state-names = "tx-enable", "tx-rings-empty", "wake-state";
+
+ qcom,has-autodetect-xo;
+ qcom,is-pronto-v3;
+ qcom,has-pronto-hw;
+ qcom,has-vsys-adc-channel;
+ qcom,wcnss-adc_tm = <&pm8937_adc_tm>;
+ };
+
+ ssc_sensors: qcom,msm-ssc-sensors {
+ compatible = "qcom,msm-ssc-sensors";
+ };
+};
+
+#include "pm8937-rpm-regulator.dtsi"
+#include "msm8917-regulator.dtsi"
+#include "pm8937.dtsi"
+#include "msm-gdsc-8916.dtsi"
+#include "msm8917-thermal.dtsi"
+
+&gdsc_venus {
+ clock-names = "bus_clk", "core_clk";
+ clocks = <&gcc GCC_VENUS0_AXI_CLK>,
+ <&gcc GCC_VENUS0_VCODEC0_CLK>;
+ status = "okay";
+};
+
+&gdsc_venus_core0 {
+ qcom,support-hw-trigger;
+ clock-names ="core0_clk";
+ clocks = <&gcc GCC_VENUS0_CORE0_VCODEC0_CLK>;
+ status = "okay";
+};
+
+&gdsc_mdss {
+ clock-names = "core_clk", "bus_clk";
+ clocks = <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>;
+ status = "okay";
+};
+
+&gdsc_jpeg {
+ clock-names = "core_clk", "bus_clk";
+ clocks = <&gcc GCC_CAMSS_JPEG0_CLK>,
+ <&gcc GCC_CAMSS_JPEG_AXI_CLK>;
+ status = "okay";
+};
+
+&gdsc_vfe {
+ clock-names = "core_clk", "bus_clk", "micro_clk",
+ "csi_clk";
+ clocks = <&gcc GCC_CAMSS_VFE0_CLK>,
+ <&gcc GCC_CAMSS_VFE_AXI_CLK>,
+ <&gcc GCC_CAMSS_MICRO_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>;
+ status = "okay";
+};
+
+&gdsc_vfe1 {
+ clock-names = "core_clk", "bus_clk", "micro_clk",
+ "csi_clk";
+ clocks = <&gcc GCC_CAMSS_VFE1_CLK>,
+ <&gcc GCC_CAMSS_VFE1_AXI_CLK>,
+ <&gcc GCC_CAMSS_MICRO_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE1_CLK>;
+ status = "okay";
+};
+
+&gdsc_cpp {
+ clock-names = "core_clk", "bus_clk";
+ clocks = <&gcc GCC_CAMSS_CPP_CLK>,
+ <&gcc GCC_CAMSS_CPP_AXI_CLK>;
+ status = "okay";
+};
+
+&gdsc_oxili_gx {
+ clock-names = "core_root_clk", "gfx_clk";
+ clocks =<&gcc GFX3D_CLK_SRC>,
+ <&gcc GCC_OXILI_GFX3D_CLK>;
+ qcom,enable-root-clk;
+ qcom,clk-dis-wait-val = <0x5>;
+ status = "okay";
+};
+
+/* GPU overrides */
+&msm_gpu {
+
+ qcom,gpu-speed-bin-vectors =
+ <0x6018 0x80000000 31>,
+ <0x0164 0x00000400 9>;
+ /delete-node/qcom,gpu-pwrlevels;
+
+ qcom,gpu-pwrlevel-bins {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible="qcom,gpu-pwrlevel-bins";
+
+ qcom,gpu-pwrlevels-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <0>;
+ qcom,initial-pwrlevel = <3>;
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <598000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <7>;
+ };
+
+ /* NOM+ */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <523200000>;
+ qcom,bus-freq = <6>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <484800000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <6>;
+ };
+
+ /* SVS+ */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <270000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <1>;
+ qcom,bus-max = <3>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <1>;
+ qcom,initial-pwrlevel = <3>;
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <650000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <8>;
+ };
+
+ /* NOM+ */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <523200000>;
+ qcom,bus-freq = <6>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <484800000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <6>;
+ };
+
+ /* SVS+ */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <270000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <1>;
+ qcom,bus-max = <3>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <2>;
+ qcom,initial-pwrlevel = <1>;
+
+ /* NOM */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ };
+
+ /* SVS+ */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <270000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <1>;
+ qcom,bus-max = <3>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-audio.dtsi
new file mode 100755
index 0000000..fbf539a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-audio.dtsi
@@ -0,0 +1,470 @@
+#include <dt-bindings/clock/qcom,audio-ext-clk.h>
+#include "msm-audio-lpass.dtsi"
+#include "msm8953-wsa881x.dtsi"
+
+&msm_audio_ion {
+ iommus = <&apps_iommu 0x2001 0x0>;
+ qcom,smmu-sid-mask = /bits/ 64 <0xf>;
+};
+
+&soc {
+ audio_apr: qcom,msm-audio-apr {
+ compatible = "qcom,msm-audio-apr";
+ q6core: q6core {
+ compatible = "qcom,q6core-audio";
+ };
+ };
+
+ qcom,avtimer@c0a300c {
+ compatible = "qcom,avtimer";
+ reg = <0x0c0a300c 0x4>,
+ <0x0c0a3010 0x4>;
+ reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
+ qcom,clk-div = <27>;
+ };
+
+ int_codec: sound {
+ status = "okay";
+ compatible = "qcom,msm8952-audio-codec";
+ qcom,model = "msm8952-snd-card-mtp";
+ reg = <0xc051000 0x4>,
+ <0xc051004 0x4>,
+ <0xc055000 0x4>,
+ <0xc052000 0x4>;
+ reg-names = "csr_gp_io_mux_mic_ctl",
+ "csr_gp_io_mux_spkr_ctl",
+ "csr_gp_io_lpaif_pri_pcm_pri_mode_muxsel",
+ "csr_gp_io_mux_quin_ctl";
+
+ qcom,msm-ext-pa = "primary";
+ qcom,msm-mclk-freq = <9600000>;
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+ qcom,msm-hs-micbias-type = "external";
+ qcom,msm-micbias1-ext-cap;
+
+ qcom,audio-routing =
+ "RX_BIAS", "MCLK",
+ "SPK_RX_BIAS", "MCLK",
+ "INT_LDO_H", "MCLK",
+ "RX_I2S_CLK", "MCLK",
+ "TX_I2S_CLK", "MCLK",
+ "MIC BIAS External", "Handset Mic",
+ "MIC BIAS External2", "Headset Mic",
+ "MIC BIAS External", "Secondary Mic",
+ "AMIC1", "MIC BIAS External",
+ "AMIC2", "MIC BIAS External2",
+ "AMIC3", "MIC BIAS External",
+ "ADC1_IN", "ADC1_OUT",
+ "ADC2_IN", "ADC2_OUT",
+ "ADC3_IN", "ADC3_OUT",
+ "PDM_IN_RX1", "PDM_OUT_RX1",
+ "PDM_IN_RX2", "PDM_OUT_RX2",
+ "PDM_IN_RX3", "PDM_OUT_RX3",
+ "WSA_SPK OUT", "VDD_WSA_SWITCH",
+ "SpkrMono WSA_IN", "WSA_SPK OUT";
+
+ qcom,cdc-us-euro-gpios = <&tlmm 63 0>;
+ qcom,cdc-us-eu-gpios = <&cdc_us_euro_sw>;
+ qcom,pri-mi2s-gpios = <&cdc_pri_mi2s_gpios>;
+ qcom,quin-mi2s-gpios = <&cdc_quin_mi2s_gpios>;
+
+ asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
+ <&loopback>, <&compress>, <&hostless>,
+ <&afe>, <&lsm>, <&routing>, <&pcm_noirq>;
+ asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
+ "msm-pcm-dsp.2", "msm-voip-dsp",
+ "msm-pcm-voice", "msm-pcm-loopback",
+ "msm-compress-dsp", "msm-pcm-hostless",
+ "msm-pcm-afe", "msm-lsm-client",
+ "msm-pcm-routing", "msm-pcm-dsp-noirq";
+ asoc-cpu = <&dai_pri_auxpcm>,
+ <&dai_mi2s0>, <&dai_mi2s1>,
+ <&dai_mi2s2>, <&dai_mi2s3>,
+ <&dai_mi2s4>, <&dai_mi2s5>,
+ <&bt_sco_rx>, <&bt_sco_tx>,
+ <&int_fm_rx>, <&int_fm_tx>,
+ <&afe_pcm_rx>, <&afe_pcm_tx>,
+ <&afe_proxy_rx>, <&afe_proxy_tx>,
+ <&incall_record_rx>, <&incall_record_tx>,
+ <&incall_music_rx>, <&incall_music_2_rx>,
+ <&proxy_rx>, <&proxy_tx>;
+
+ asoc-cpu-names = "msm-dai-q6-auxpcm.1",
+ "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",
+ "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",
+ "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.6",
+ "msm-dai-q6-dev.12288", "msm-dai-q6-dev.12289",
+ "msm-dai-q6-dev.12292", "msm-dai-q6-dev.12293",
+ "msm-dai-q6-dev.224", "msm-dai-q6-dev.225",
+ "msm-dai-q6-dev.241", "msm-dai-q6-dev.240",
+ "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772",
+ "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770",
+ "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195";
+
+ asoc-codec = <&stub_codec>, <&msm_digital_codec>,
+ <&pmic_analog_codec>;
+ asoc-codec-names = "msm-stub-codec.1", "msm-dig-codec",
+ "analog-codec";
+ asoc-wsa-codec-names = "wsa881x-i2c-codec.2-000f";
+ asoc-wsa-codec-prefixes = "SpkrMono";
+ msm-vdd-wsa-switch-supply = <&pm8937_l5>;
+ qcom,msm-vdd-wsa-switch-voltage = <1800000>;
+ qcom,msm-vdd-wsa-switch-current = <10000>;
+ };
+
+ cdc_us_euro_sw: msm_cdc_pinctrl_us_euro_sw {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cross_conn_det_act>;
+ pinctrl-1 = <&cross_conn_det_sus>;
+ };
+
+ cdc_pri_mi2s_gpios: msm_cdc_pinctrl_pri {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_pdm_lines_act &cdc_pdm_lines_2_act>;
+ pinctrl-1 = <&cdc_pdm_lines_sus &cdc_pdm_lines_2_sus>;
+ };
+
+ cdc_quin_mi2s_gpios: msm_cdc_pinctrl_quin {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&pri_tlmm_lines_act &pri_tlmm_ws_act>;
+ pinctrl-1 = <&pri_tlmm_lines_sus &pri_tlmm_ws_sus>;
+ };
+
+
+ i2c@78b6000 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ wsa881x_i2c_f: wsa881x-i2c-codec@f {
+ status = "okay";
+ compatible = "qcom,wsa881x-i2c-codec";
+ reg = <0x0f>;
+ clock-names = "wsa_mclk";
+ clocks = <&wsa881x_analog_clk 0>;
+ qcom,wsa-analog-vi-gpio = <&wsa881x_analog_vi_gpio>;
+ qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>;
+ qcom,wsa-analog-reset-gpio =
+ <&wsa881x_analog_reset_gpio>;
+ };
+
+ wsa881x_i2c_45: wsa881x-i2c-codec@45 {
+ status = "okay";
+ compatible = "qcom,wsa881x-i2c-codec";
+ reg = <0x45>;
+ };
+ };
+
+ wsa881x_analog_vi_gpio: wsa881x_analog_vi_pctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wsa_vi_on>;
+ pinctrl-1 = <&wsa_vi_off>;
+ };
+
+ wsa881x_analog_clk_gpio: wsa881x_analog_clk_pctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wsa_clk_on>;
+ pinctrl-1 = <&wsa_clk_off>;
+ };
+
+ wsa881x_analog_reset_gpio: wsa881x_analog_reset_pctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wsa_reset_on>;
+ pinctrl-1 = <&wsa_reset_off>;
+ };
+
+ wsa881x_analog_clk: wsa_ana_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
+ qcom,codec-lpass-ext-clk-freq = <9600000>;
+ qcom,codec-lpass-clk-id = <0x300>;
+ #clock-cells = <1>;
+ };
+
+ ext_codec: sound-9335 {
+ status = "disabled";
+ compatible = "qcom,msm8952-audio-slim-codec";
+ qcom,model = "msm8952-tasha-snd-card";
+
+ reg = <0xc051000 0x4>,
+ <0xc051004 0x4>,
+ <0xc055000 0x4>,
+ <0xc052000 0x4>;
+ reg-names = "csr_gp_io_mux_mic_ctl",
+ "csr_gp_io_mux_spkr_ctl",
+ "csr_gp_io_lpaif_pri_pcm_pri_mode_muxsel",
+ "csr_gp_io_mux_quin_ctl";
+
+ qcom,audio-routing =
+ "AIF4 VI", "MCLK",
+ "AIF4 VI", "MICBIAS_REGULATOR",
+ "RX_BIAS", "MCLK",
+ "MADINPUT", "MCLK",
+ "AIF4 MAD", "MICBIAS_REGULATOR",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Headset Mic",
+ "AMIC3", "MIC BIAS2",
+ "MIC BIAS2", "ANCRight Headset Mic",
+ "AMIC4", "MIC BIAS2",
+ "MIC BIAS2", "ANCLeft Headset Mic",
+ "AMIC5", "MIC BIAS3",
+ "MIC BIAS3", "Handset Mic",
+ "AMIC6", "MIC BIAS4",
+ "MIC BIAS4", "Analog Mic6",
+ "DMIC0", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic0",
+ "DMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic1",
+ "DMIC2", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic2",
+ "DMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic3",
+ "DMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "MIC BIAS1", "MICBIAS_REGULATOR",
+ "MIC BIAS2", "MICBIAS_REGULATOR",
+ "MIC BIAS3", "MICBIAS_REGULATOR",
+ "MIC BIAS4", "MICBIAS_REGULATOR",
+ "SpkrLeft IN", "SPK1 OUT",
+ "SpkrRight IN", "SPK2 OUT";
+
+ qcom,tasha-mclk-clk-freq = <9600000>;
+ qcom,cdc-us-euro-gpios = <&tlmm 63 0>;
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+ qcom,cdc-us-eu-gpios = <&cdc_us_euro_sw>;
+ qcom,quin-mi2s-gpios = <&cdc_quin_mi2s_gpios>;
+
+ asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
+ <&loopback>, <&compress>, <&hostless>,
+ <&afe>, <&lsm>, <&routing>, <&cpe>,
+ <&pcm_noirq>;
+ asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
+ "msm-pcm-dsp.2", "msm-voip-dsp",
+ "msm-pcm-voice", "msm-pcm-loopback",
+ "msm-compress-dsp", "msm-pcm-hostless",
+ "msm-pcm-afe", "msm-lsm-client",
+ "msm-pcm-routing", "msm-cpe-lsm",
+ "msm-pcm-dsp-noirq";
+
+ asoc-cpu = <&dai_pri_auxpcm>,
+ <&dai_mi2s2>, <&dai_mi2s3>, <&dai_mi2s5>,
+ <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>,
+ <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>,
+ <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>,
+ <&afe_pcm_rx>, <&afe_pcm_tx>,
+ <&afe_proxy_rx>, <&afe_proxy_tx>,
+ <&incall_record_rx>, <&incall_record_tx>,
+ <&incall_music_rx>, <&incall_music_2_rx>,
+ <&sb_5_rx>, <&bt_sco_rx>, <&bt_sco_tx>,
+ <&int_fm_rx>, <&int_fm_tx>, <&sb_6_rx>,
+ <&proxy_rx>, <&proxy_tx>;
+
+ asoc-cpu-names = "msm-dai-q6-auxpcm.1",
+ "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",
+ "msm-dai-q6-mi2s.5", "msm-dai-q6-dev.16384",
+ "msm-dai-q6-dev.16385", "msm-dai-q6-dev.16386",
+ "msm-dai-q6-dev.16387", "msm-dai-q6-dev.16388",
+ "msm-dai-q6-dev.16389", "msm-dai-q6-dev.16390",
+ "msm-dai-q6-dev.16391", "msm-dai-q6-dev.16392",
+ "msm-dai-q6-dev.16393", "msm-dai-q6-dev.16395",
+ "msm-dai-q6-dev.224", "msm-dai-q6-dev.225",
+ "msm-dai-q6-dev.241", "msm-dai-q6-dev.240",
+ "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772",
+ "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770",
+ "msm-dai-q6-dev.16394", "msm-dai-q6-dev.12288",
+ "msm-dai-q6-dev.12289", "msm-dai-q6-dev.12292",
+ "msm-dai-q6-dev.12293", "msm-dai-q6-dev.16396",
+ "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195";
+
+ asoc-codec = <&stub_codec>, <&hdmi_dba>;
+ asoc-codec-names = "msm-stub-codec.1", "msm-hdmi-dba-codec-rx";
+
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa881x_211>, <&wsa881x_212>,
+ <&wsa881x_213>, <&wsa881x_214>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+ "SpkrLeft", "SpkrRight";
+ };
+
+ cpe: qcom,msm-cpe-lsm {
+ compatible = "qcom,msm-cpe-lsm";
+ };
+
+ wcd9xxx_intc: wcd9xxx-irq {
+ status = "disabled";
+ compatible = "qcom,wcd9xxx-irq";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&tlmm>;
+ qcom,gpio-connect = <&tlmm 73 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&wcd_intr_default>;
+ };
+
+ clock_audio: audio_ext_clk {
+ status = "disabled";
+ compatible = "qcom,audio-ref-clk";
+ qcom,use-pinctrl = <1>;
+ qcom,codec-ext-clk-src = <14>;
+ clock-names = "osr_clk";
+ qcom,node_has_rpm_clock;
+ #clock-cells = <1>;
+ qcom,audio-ref-clk-gpio = <&pm8937_gpios 1 0>;
+ clocks = <&rpmcc RPM_SMD_DIV_CLK2>;
+ pinctrl-0 = <&cdc_mclk2_sleep>;
+ pinctrl-1 = <&cdc_mclk2_active>;
+ };
+
+ wcd_rst_gpio: msm_cdc_pinctrl {
+ status = "disabled";
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_reset_active>;
+ pinctrl-1 = <&cdc_reset_sleep>;
+ };
+};
+
+&slim_msm {
+ status = "disabled";
+
+ dai_slim: msm_dai_slim {
+ status = "disabled";
+ compatible = "qcom,msm-dai-slim";
+ elemental-addr = [ff ff ff fe 17 02];
+ };
+
+ wcd9335: tasha_codec {
+ status = "disabled";
+ compatible = "qcom,tasha-slim-pgd";
+ elemental-addr = [00 01 A0 01 17 02];
+
+ qcom,cdc-slim-ifd = "tasha-slim-ifd";
+ qcom,cdc-slim-ifd-elemental-addr = [00 00 A0 01 17 02];
+
+ interrupt-parent = <&wcd9xxx_intc>;
+ interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+ 17 18 19 20 21 22 23 24 25 26 27 28 29 30>;
+
+ qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
+
+ clock-names = "wcd_clk", "wcd_native_clk";
+ clocks = < &clock_audio 0>,
+ <&clock_audio_native 0>;
+
+ qcom,cdc-static-supplies =
+ "cdc-vdd-buck",
+ "cdc-buck-sido",
+ "cdc-vdd-tx-h",
+ "cdc-vdd-rx-h",
+ "cdc-vdd-px";
+ qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias";
+ qcom,cdc-micbias1-mv = <1800>;
+ qcom,cdc-micbias2-mv = <1800>;
+ qcom,cdc-micbias3-mv = <1800>;
+ qcom,cdc-micbias4-mv = <1800>;
+
+ qcom,cdc-dmic-sample-rate = <2400000>;
+ qcom,cdc-mclk-clk-rate = <9600000>;
+
+ cdc-vdd-buck-supply = <&eldo2_pm8937>;
+ qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-buck-current = <650000>;
+
+ cdc-buck-sido-supply = <&eldo2_pm8937>;
+ qcom,cdc-buck-sido-voltage = <1800000 1800000>;
+ qcom,cdc-buck-sido-current = <250000>;
+
+ cdc-vdd-tx-h-supply = <&pm8937_l5>;
+ qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-tx-h-current = <25000>;
+
+ cdc-vdd-rx-h-supply = <&pm8937_l5>;
+ qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-rx-h-current = <25000>;
+
+ cdc-vdd-px-supply = <&pm8937_l5>;
+ qcom,cdc-vdd-px-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-px-current = <10000>;
+
+ cdc-vdd-mic-bias-supply = <&pm8937_l13>;
+ qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>;
+ qcom,cdc-vdd-mic-bias-current = <15000>;
+ };
+};
+
+&pm8937_1 {
+ pmic_analog_codec: analog-codec@f000 {
+ status = "okay";
+ compatible = "qcom,pmic-analog-codec";
+ reg = <0xf000 0x200>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-parent = <&spmi_bus>;
+ interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x1 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x2 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x3 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x4 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x5 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x6 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x7 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x0 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x1 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x2 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x3 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x4 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x5 IRQ_TYPE_NONE>;
+ interrupt-names = "spk_cnp_int",
+ "spk_clip_int",
+ "spk_ocp_int",
+ "ins_rem_det1",
+ "but_rel_det",
+ "but_press_det",
+ "ins_rem_det",
+ "mbhc_int",
+ "ear_ocp_int",
+ "hphr_ocp_int",
+ "hphl_ocp_det",
+ "ear_cnp_int",
+ "hphr_cnp_int",
+ "hphl_cnp_int";
+
+ cdc-vdda-cp-supply = <&pm8937_s4>;
+ qcom,cdc-vdda-cp-voltage = <2050000 2050000>;
+ qcom,cdc-vdda-cp-current = <210000>;
+
+ cdc-vdd-io-supply = <&pm8937_l5>;
+ qcom,cdc-vdd-io-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-io-current = <5000>;
+
+ cdc-vdd-pa-supply = <&pm8937_s4>;
+ qcom,cdc-vdd-pa-voltage = <1900000 2050000>;
+ qcom,cdc-vdd-pa-current = <260000>;
+
+ cdc-vdd-mic-bias-supply = <&pm8937_l13>;
+ qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>;
+ qcom,cdc-vdd-mic-bias-current = <5000>;
+
+ qcom,cdc-mclk-clk-rate = <9600000>;
+
+ qcom,cdc-static-supplies = "cdc-vdd-io",
+ "cdc-vdd-pa",
+ "cdc-vdda-cp";
+
+ qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias";
+
+ msm_digital_codec: msm-dig-codec {
+ compatible = "qcom,msm-digital-codec";
+ reg = <0xc0f0000 0x0>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-bus.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-bus.dtsi
new file mode 100755
index 0000000..d423704
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-bus.dtsi
@@ -0,0 +1,932 @@
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ /*Version = 11 */
+ ad_hoc_bus: ad-hoc-bus@580000 {
+ compatible = "qcom,msm-bus-device";
+ reg = <0x580000 0x16080>,
+ <0x580000 0x16080>,
+ <0x400000 0x5A000>,
+ <0x500000 0x13080>;
+ reg-names = "snoc-base", "snoc-mm-base",
+ "bimc-base", "pcnoc-base";
+
+ /*Buses*/
+ fab_bimc: fab-bimc {
+ cell-id = <MSM_BUS_FAB_BIMC>;
+ label = "fab-bimc";
+ qcom,fab-dev;
+ qcom,base-name = "bimc-base";
+ qcom,bus-type = <2>;
+ qcom,util-fact = <154>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc BIMC_MSMBUS_CLK>,
+ <&rpmcc BIMC_MSMBUS_A_CLK>;
+ };
+
+ fab_pcnoc: fab-pcnoc {
+ cell-id = <MSM_BUS_FAB_PERIPH_NOC>;
+ label = "fab-pcnoc";
+ qcom,fab-dev;
+ qcom,base-name = "pcnoc-base";
+ qcom,base-offset = <0x7000>;
+ qcom,qos-off = <0x1000>;
+ qcom,bus-type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc PNOC_MSMBUS_CLK>,
+ <&rpmcc PNOC_MSMBUS_A_CLK>;
+ };
+
+ fab_snoc: fab-snoc {
+ cell-id = <MSM_BUS_FAB_SYS_NOC>;
+ label = "fab-snoc";
+ qcom,fab-dev;
+ qcom,base-name = "snoc-base";
+ qcom,base-offset = <0x7000>;
+ qcom,qos-off = <0x1000>;
+ qcom,bus-type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc SNOC_MSMBUS_CLK>,
+ <&rpmcc SNOC_MSMBUS_A_CLK>;
+ };
+
+ fab_snoc_mm: fab-snoc-mm {
+ cell-id = <MSM_BUS_FAB_MMSS_NOC>;
+ label = "fab-snoc-mm";
+ qcom,fab-dev;
+ qcom,base-name = "snoc-mm-base";
+ qcom,base-offset = <0x7000>;
+ qcom,qos-off = <0x1000>;
+ qcom,bus-type = <1>;
+ qcom,util-fact = <154>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc SYSMMNOC_MSMBUS_CLK>,
+ <&rpmcc SYSMMNOC_MSMBUS_A_CLK>;
+ };
+
+ /*BIMC Masters*/
+ mas_apps_proc: mas-apps-proc {
+ cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
+ label = "mas-apps-proc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,prio-lvl = <0>;
+ qcom,prio-rd = <0>;
+ qcom,prio-wr = <0>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_APPSS_PROC>;
+ };
+
+ mas_oxili: mas-oxili {
+ cell-id = <MSM_BUS_MASTER_GRAPHICS_3D>;
+ label = "mas-oxili";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,prio-lvl = <0>;
+ qcom,prio-rd = <0>;
+ qcom,prio-wr = <0>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_GFX3D>;
+ };
+
+ mas_snoc_bimc_0: mas-snoc-bimc-0 {
+ cell-id = <MSM_BUS_SNOC_BIMC_0_MAS>;
+ label = "mas-snoc-bimc-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <3>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_0>;
+ };
+
+ mas_snoc_bimc_2: mas-snoc-bimc-2 {
+ cell-id = <MSM_BUS_SNOC_BIMC_2_MAS>;
+ label = "mas-snoc-bimc-2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <4>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_2>;
+ };
+
+ mas_snoc_bimc_1: mas-snoc-bimc-1 {
+ cell-id = <MSM_BUS_SNOC_BIMC_1_MAS>;
+ label = "mas-snoc-bimc-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <5>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_ebi>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_1>;
+ };
+
+ mas_tcu_0: mas-tcu-0 {
+ cell-id = <MSM_BUS_MASTER_TCU_0>;
+ label = "mas-tcu-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <6>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,prio-lvl = <2>;
+ qcom,prio-rd = <2>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_TCU_0>;
+ };
+
+ /*PCNOC Masters*/
+ mas_spdm: mas-spdm {
+ cell-id = <MSM_BUS_MASTER_SPDM>;
+ label = "mas-spdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&pcnoc_m_0>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SPDM>;
+ };
+
+ mas_blsp_1: mas-blsp-1 {
+ cell-id = <MSM_BUS_MASTER_BLSP_1>;
+ label = "mas-blsp-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&pcnoc_m_1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BLSP_1>;
+ };
+
+ mas_blsp_2: mas-blsp-2 {
+ cell-id = <MSM_BUS_MASTER_BLSP_2>;
+ label = "mas-blsp-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&pcnoc_m_1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BLSP_2>;
+ };
+
+ mas_usb_hs1: mas-usb-hs1 {
+ cell-id = <MSM_BUS_MASTER_USB_HS>;
+ label = "mas-usb-hs1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <12>;
+ qcom,qos-mode = "fixed";
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,connections = <&pcnoc_int_0>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_USB_HS1>;
+ };
+
+ mas_xi_usb_hs1: mas-xi-usb-hs1 {
+ cell-id = <MSM_BUS_MASTER_XM_USB_HS1>;
+ label = "mas-xi-usb-hs1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <11>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&pcnoc_int_0>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_XI_USB_HS1>;
+ };
+
+ mas_crypto: mas-crypto {
+ cell-id = <MSM_BUS_MASTER_CRYPTO_CORE0>;
+ label = "mas-crypto";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&pcnoc_int_0>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO>;
+ };
+
+ mas_sdcc_1: mas-sdcc-1 {
+ cell-id = <MSM_BUS_MASTER_SDCC_1>;
+ label = "mas-sdcc-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <7>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&pcnoc_int_0>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SDCC_1>;
+ };
+
+ mas_sdcc_2: mas-sdcc-2 {
+ cell-id = <MSM_BUS_MASTER_SDCC_2>;
+ label = "mas-sdcc-2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <8>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&pcnoc_int_0>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SDCC_2>;
+ };
+
+ mas_snoc_pcnoc: mas-snoc-pcnoc {
+ cell-id = <MSM_BUS_SNOC_PNOC_MAS>;
+ label = "mas-snoc-pcnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <9>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&pcnoc_s_7
+ &pcnoc_int_2 &pcnoc_int_3>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_PCNOC>;
+ };
+
+ /*SNOC Masters*/
+ mas_qdss_bam: mas-qdss-bam {
+ cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
+ label = "mas-qdss-bam";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <11>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&qdss_int>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAM>;
+ };
+
+ mas_bimc_snoc: mas-bimc-snoc {
+ cell-id = <MSM_BUS_BIMC_SNOC_MAS>;
+ label = "mas-bimc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&snoc_int_0
+ &snoc_int_1 &snoc_int_2>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BIMC_SNOC>;
+ };
+
+ mas_jpeg: mas-jpeg {
+ cell-id = <MSM_BUS_MASTER_JPEG>;
+ label = "mas-jpeg";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <6>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_snoc_bimc_2>;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,mas-rpm-id = <ICBID_MASTER_JPEG>;
+ };
+
+ mas_mdp: mas-mdp {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT0>;
+ label = "mas-mdp";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <7>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_snoc_bimc_0>;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,mas-rpm-id = <ICBID_MASTER_MDP>;
+ };
+
+ mas_pcnoc_snoc: mas-pcnoc-snoc {
+ cell-id = <MSM_BUS_PNOC_SNOC_MAS>;
+ label = "mas-pcnoc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <5>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&snoc_int_0
+ &snoc_int_1 &slv_snoc_bimc_1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PNOC_SNOC>;
+ qcom,blacklist = <&slv_snoc_pcnoc>;
+ };
+
+ mas_venus: mas-venus {
+ cell-id = <MSM_BUS_MASTER_VIDEO_P0>;
+ label = "mas-venus";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <8>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_snoc_bimc_2>;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VIDEO>;
+ };
+
+ mas_vfe0: mas-vfe0 {
+ cell-id = <MSM_BUS_MASTER_VFE>;
+ label = "mas-vfe0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <9>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_snoc_bimc_0>;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VFE>;
+ };
+
+ mas_vfe1: mas-vfe1 {
+ cell-id = <MSM_BUS_MASTER_VFE1>;
+ label = "mas-vfe1";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <13>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_snoc_bimc_0>;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VFE1>;
+ };
+
+ mas_cpp: mas-cpp {
+ cell-id = <MSM_BUS_MASTER_CPP>;
+ label = "mas-cpp";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <12>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_snoc_bimc_2>;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CPP>;
+ };
+
+ mas_qdss_etr: mas-qdss-etr {
+ cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
+ label = "mas-qdss-etr";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <10>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&qdss_int>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>;
+ };
+
+ /*Internal nodes*/
+ pcnoc_m_0: pcnoc-m-0 {
+ cell-id = <MSM_BUS_PNOC_M_0>;
+ label = "pcnoc-m-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <5>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&pcnoc_int_0>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_0>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_0>;
+ };
+
+ pcnoc_m_1: pcnoc-m-1 {
+ cell-id = <MSM_BUS_PNOC_M_1>;
+ label = "pcnoc-m-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&pcnoc_int_0>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_M_1>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_M_1>;
+ };
+
+ pcnoc_int_0: pcnoc-int-0 {
+ cell-id = <MSM_BUS_PNOC_INT_0>;
+ label = "pcnoc-int-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_pcnoc_snoc
+ &pcnoc_s_7 &pcnoc_int_3 &pcnoc_int_2>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_0>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_0>;
+ };
+
+ pcnoc_int_1: pcnoc-int-1 {
+ cell-id = <MSM_BUS_PNOC_INT_1>;
+ label = "pcnoc-int-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_pcnoc_snoc
+ &pcnoc_s_7 &pcnoc_int_3 &pcnoc_int_2>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_1>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_1>;
+ };
+
+ pcnoc_int_2: pcnoc-int-2 {
+ cell-id = <MSM_BUS_PNOC_INT_2>;
+ label = "pcnoc-int-2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&pcnoc_s_2
+ &pcnoc_s_3 &pcnoc_s_6 &pcnoc_s_8>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_2>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_2>;
+ };
+
+ pcnoc_int_3: pcnoc-int-3 {
+ cell-id = <MSM_BUS_PNOC_INT_3>;
+ label = "pcnoc-int-3";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = < &pcnoc_s_1 &pcnoc_s_0 &pcnoc_s_4
+ &slv_gpu_cfg &slv_tcu >;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_INT_3>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_INT_3>;
+ };
+
+ pcnoc_s_0: pcnoc-s-0 {
+ cell-id = <MSM_BUS_PNOC_SLV_0>;
+ label = "pcnoc-s-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_spdm &slv_pdm &slv_prng
+ &slv_sdcc_2>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_0>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_0>;
+ };
+
+ pcnoc_s_1: pcnoc-s-1 {
+ cell-id = <MSM_BUS_PNOC_SLV_1>;
+ label = "pcnoc-s-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_tcsr>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_1>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_1>;
+ };
+
+ pcnoc_s_2: pcnoc-s-2 {
+ cell-id = <MSM_BUS_PNOC_SLV_2>;
+ label = "pcnoc-s-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_snoc_cfg>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_2>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_2>;
+ };
+
+ pcnoc_s_3: pcnoc-s-3 {
+ cell-id = <MSM_BUS_PNOC_SLV_3>;
+ label = "pcnoc-s-3";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_message_ram>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_3>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_3>;
+ };
+
+ pcnoc_s_4: pcnoc-s-4 {
+ cell-id = <MSM_BUS_PNOC_SLV_4>;
+ label = "pcnoc-s-4";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_camera_ss_cfg
+ &slv_disp_ss_cfg &slv_venus_cfg>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_4>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_4>;
+ };
+
+ pcnoc_s_6: pcnoc-s-6 {
+ cell-id = <MSM_BUS_PNOC_SLV_6>;
+ label = "pcnoc-s-6";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_tlmm &slv_blsp_1 &slv_blsp_2>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_6>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_6>;
+ };
+
+ pcnoc_s_7: pcnoc-s-7 {
+ cell-id = <MSM_BUS_PNOC_SLV_7>;
+ label = "pcnoc-s-7";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = < &slv_sdcc_1 &slv_pmic_arb>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_7>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_7>;
+ };
+
+ pcnoc_s_8: pcnoc-s-8 {
+ cell-id = <MSM_BUS_PNOC_SLV_8>;
+ label = "pcnoc-s-8";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_usb_hs &slv_crypto_0_cfg>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PCNOC_S_8>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_S_8>;
+ };
+
+ qdss_int: qdss-int {
+ cell-id = <MSM_BUS_SNOC_QDSS_INT>;
+ label = "qdss-int";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&snoc_int_1 &slv_snoc_bimc_1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_INT>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_INT>;
+ };
+
+ snoc_int_0: snoc-int-0 {
+ cell-id = <MSM_BUS_SNOC_INT_0>;
+ label = "snoc-int-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_lpass
+ &slv_wcss &slv_kpss_ahb>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_0>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_0>;
+ };
+
+ snoc_int_1: snoc-int-1 {
+ cell-id = <MSM_BUS_SNOC_INT_1>;
+ label = "snoc-int-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qdss_stm
+ &slv_imem &slv_snoc_pcnoc>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_1>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_1>;
+ };
+
+ snoc_int_2: snoc-int-2 {
+ cell-id = <MSM_BUS_SNOC_INT_2>;
+ label = "snoc-int-2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_cats_0 &slv_cats_1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_INT_2>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_INT_2>;
+ };
+ /*Slaves*/
+
+ slv_ebi:slv-ebi {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ label = "slv-ebi";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_EBI1>;
+ };
+
+ slv_bimc_snoc:slv-bimc-snoc {
+ cell-id = <MSM_BUS_BIMC_SNOC_SLV>;
+ label = "slv-bimc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,connections = <&mas_bimc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_SNOC>;
+ };
+
+ slv_sdcc_2:slv-sdcc-2 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_2>;
+ label = "slv-sdcc-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_2>;
+ };
+
+ slv_spdm:slv-spdm {
+ cell-id = <MSM_BUS_SLAVE_SPDM_WRAPPER>;
+ label = "slv-spdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SPDM_WRAPPER>;
+ };
+
+ slv_pdm:slv-pdm {
+ cell-id = <MSM_BUS_SLAVE_PDM>;
+ label = "slv-pdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PDM>;
+ };
+
+ slv_prng:slv-prng {
+ cell-id = <MSM_BUS_SLAVE_PRNG>;
+ label = "slv-prng";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>;
+ };
+
+ slv_tcsr:slv-tcsr {
+ cell-id = <MSM_BUS_SLAVE_TCSR>;
+ label = "slv-tcsr";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>;
+ };
+
+ slv_snoc_cfg:slv-snoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
+ label = "slv-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CFG>;
+ };
+
+ slv_message_ram:slv-message-ram {
+ cell-id = <MSM_BUS_SLAVE_MESSAGE_RAM>;
+ label = "slv-message-ram";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MESSAGE_RAM>;
+ };
+
+ slv_camera_ss_cfg:slv-camera-ss-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_CFG>;
+ label = "slv-camera-ss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_CFG>;
+ };
+
+ slv_disp_ss_cfg:slv-disp-ss-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_CFG>;
+ label = "slv-disp-ss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_CFG>;
+ };
+
+ slv_venus_cfg:slv-venus-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_CFG>;
+ label = "slv-venus-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_CFG>;
+ };
+
+ slv_gpu_cfg:slv-gpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_GRAPHICS_3D_CFG>;
+ label = "slv-gpu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GFX3D_CFG>;
+ };
+
+ slv_tlmm:slv-tlmm {
+ cell-id = <MSM_BUS_SLAVE_TLMM>;
+ label = "slv-tlmm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TLMM>;
+ };
+
+ slv_blsp_1:slv-blsp-1 {
+ cell-id = <MSM_BUS_SLAVE_BLSP_1>;
+ label = "slv-blsp-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_1>;
+ };
+
+ slv_blsp_2:slv-blsp-2 {
+ cell-id = <MSM_BUS_SLAVE_BLSP_2>;
+ label = "slv-blsp-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_2>;
+ };
+
+ slv_pmic_arb:slv-pmic-arb {
+ cell-id = <MSM_BUS_SLAVE_PMIC_ARB>;
+ label = "slv-pmic-arb";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PMIC_ARB>;
+ };
+
+ slv_sdcc_1:slv-sdcc-1 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_1>;
+ label = "slv-sdcc-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_1>;
+ };
+
+ slv_crypto_0_cfg:slv-crypto-0-cfg {
+ cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>;
+ label = "slv-crypto-0-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CRYPTO_0_CFG>;
+ };
+
+ slv_usb_hs:slv-usb-hs {
+ cell-id = <MSM_BUS_SLAVE_USB_HS>;
+ label = "slv-usb-hs";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_USB_HS>;
+ };
+
+ slv_tcu:slv-tcu {
+ cell-id = <MSM_BUS_SLAVE_TCU>;
+ label = "slv-tcu";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TCU>;
+ };
+
+ slv_pcnoc_snoc:slv-pcnoc-snoc {
+ cell-id = <MSM_BUS_PNOC_SNOC_SLV>;
+ label = "slv-pcnoc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_pcnoc>;
+ qcom,connections = <&mas_pcnoc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCNOC_SNOC>;
+ };
+
+ slv_kpss_ahb:slv-kpss-ahb {
+ cell-id = <MSM_BUS_SLAVE_APPSS>;
+ label = "slv-kpss-ahb";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_APPSS>;
+ };
+
+ slv_wcss:slv-wcss {
+ cell-id = <MSM_BUS_SLAVE_WCSS>;
+ label = "slv-wcss";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_WCSS>;
+ };
+
+ slv_snoc_bimc_0:slv-snoc-bimc-0 {
+ cell-id = <MSM_BUS_SNOC_BIMC_0_SLV>;
+ label = "slv-snoc-bimc-0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,connections = <&mas_snoc_bimc_0>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_0>;
+ };
+
+ slv_snoc_bimc_1:slv-snoc-bimc-1 {
+ cell-id = <MSM_BUS_SNOC_BIMC_1_SLV>;
+ label = "slv-snoc-bimc-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,connections = <&mas_snoc_bimc_1>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_1>;
+ };
+
+ slv_snoc_bimc_2:slv-snoc-bimc-2 {
+ cell-id = <MSM_BUS_SNOC_BIMC_2_SLV>;
+ label = "slv-snoc-bimc-2";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,connections = <&mas_snoc_bimc_2>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_2>;
+ };
+
+ slv_imem:slv-imem {
+ cell-id = <MSM_BUS_SLAVE_OCIMEM>;
+ label = "slv-imem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IMEM>;
+ };
+
+ slv_snoc_pcnoc:slv-snoc-pcnoc {
+ cell-id = <MSM_BUS_SNOC_PNOC_SLV>;
+ label = "slv-snoc-pcnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,connections = <&mas_snoc_pcnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_PCNOC>;
+ };
+
+ slv_qdss_stm:slv-qdss-stm {
+ cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
+ label = "slv-qdss-stm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>;
+ };
+
+ slv_cats_0:slv-cats-0 {
+ cell-id = <MSM_BUS_SLAVE_CATS_128>;
+ label = "slv-cats-0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc_mm>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CATS_0>;
+ };
+
+ slv_cats_1:slv-cats-1 {
+ cell-id = <MSM_BUS_SLAVE_OCMEM_64>;
+ label = "slv-cats-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CATS_1>;
+ };
+
+ slv_lpass:slv-lpass {
+ cell-id = <MSM_BUS_SLAVE_LPASS>;
+ label = "slv-lpass";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_LPASS>;
+ };
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-camera.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-camera.dtsi
new file mode 100755
index 0000000..98ed0d5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-camera.dtsi
@@ -0,0 +1,519 @@
+&soc {
+ qcom,msm-cam@1b00000 {
+ compatible = "qcom,msm-cam";
+ reg = <0x1b00000 0x40000>;
+ reg-names = "msm-cam";
+ status = "ok";
+ bus-vectors = "suspend", "svs", "nominal", "turbo";
+ qcom,bus-votes = <0 160000000 320000000 320000000>;
+ };
+
+ qcom,csiphy@1b34000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy";
+ reg = <0x1b34000 0x1000>,
+ <0x1b00030 0x4>;
+ reg-names = "csiphy", "csiphy_clk_mux";
+ interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csiphy";
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc CSI0PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
+ <&gcc CAMSS_TOP_AHB_CLK_SRC>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",
+ "csiphy_timer_src_clk", "csiphy_timer_clk",
+ "camss_ahb_src", "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 200000000 0 0 0>;
+ };
+
+ qcom,csiphy@1b35000 {
+ status = "ok";
+ cell-index = <1>;
+ compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy";
+ reg = <0x1b35000 0x1000>,
+ <0x1b00038 0x4>;
+ reg-names = "csiphy", "csiphy_clk_mux";
+ interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csiphy";
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc CSI1PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
+ <&gcc CAMSS_TOP_AHB_CLK_SRC>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",
+ "csiphy_timer_src_clk", "csiphy_timer_clk",
+ "camss_ahb_src", "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 200000000 0 0 0>;
+ };
+
+ qcom,csid@1b30000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,csid-v3.4.2", "qcom,csid";
+ reg = <0x1b30000 0x400>;
+ reg-names = "csid";
+ interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid";
+ qcom,csi-vdd-voltage = <1200000>;
+ qcom,mipi-csi-vdd-supply = <&pm8937_l2>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
+ <&gcc CSI0_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI0PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI0RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk",
+ "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",
+ "csi0_phy_clk",
+ "csi_clk", "csi_pix_clk",
+ "csi_rdi_clk", "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0 0>;
+ };
+
+ qcom,csid@1b30400 {
+ status = "ok";
+ cell-index = <1>;
+ compatible = "qcom,csid-v3.4.2", "qcom,csid";
+ reg = <0x1b30400 0x400>;
+ reg-names = "csid";
+ interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid";
+ qcom,csi-vdd-voltage = <1200000>;
+ qcom,mipi-csi-vdd-supply = <&pm8937_l2>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
+ <&gcc CSI1_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI1PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI1RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk",
+ "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",
+ "csi1_phy_clk",
+ "csi_clk", "csi_pix_clk",
+ "csi_rdi_clk", "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0 0>;
+ };
+
+ qcom,csid@1b30800 {
+ status = "ok";
+ cell-index = <2>;
+ compatible = "qcom,csid-v3.4.2", "qcom,csid";
+ reg = <0x1b30800 0x400>;
+ reg-names = "csid";
+ interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid";
+ qcom,csi-vdd-voltage = <1200000>;
+ qcom,mipi-csi-vdd-supply = <&pm8937_l2>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI2_AHB_CLK>,
+ <&gcc CSI2_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI2PHY_CLK>,
+ <&gcc GCC_CAMSS_CSI2_CLK>,
+ <&gcc GCC_CAMSS_CSI2PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI2RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk",
+ "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",
+ "csi2_phy_clk",
+ "csi_clk", "csi_pix_clk",
+ "csi_rdi_clk", "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0 0>;
+ };
+
+ qcom,ispif@1b31000 {
+ cell-index = <0>;
+ compatible = "qcom,ispif-v3.0", "qcom,ispif";
+ reg = <0x1b31000 0x500>,
+ <0x1b00020 0x10>;
+ reg-names = "ispif", "csi_clk_mux";
+ interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ispif";
+ qcom,num-isps = <0x2>;
+ vfe0-vdd-supply = <&gdsc_vfe>;
+ vfe1-vdd-supply = <&gdsc_vfe1>;
+ qcom,vdd-names = "vfe0-vdd", "vfe1-vdd";
+ clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc CAMSS_TOP_AHB_CLK_SRC>,
+ <&gcc CSI0_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI0_CLK>,
+ <&gcc GCC_CAMSS_CSI0RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI0PIX_CLK>,
+ <&gcc CSI1_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI1_CLK>,
+ <&gcc GCC_CAMSS_CSI1RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI1PIX_CLK>,
+ <&gcc CSI2_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI2_CLK>,
+ <&gcc GCC_CAMSS_CSI2RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI2PIX_CLK>,
+ <&gcc VFE0_CLK_SRC>,
+ <&gcc GCC_CAMSS_VFE0_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
+ <&gcc VFE1_CLK_SRC>,
+ <&gcc GCC_CAMSS_VFE1_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE1_CLK>;
+ clock-names = "ispif_ahb_clk",
+ "camss_ahb_clk", "camss_top_ahb_clk",
+ "camss_ahb_src",
+ "csi0_src_clk", "csi0_clk",
+ "csi0_rdi_clk", "csi0_pix_clk",
+ "csi1_src_clk", "csi1_clk",
+ "csi1_rdi_clk", "csi1_pix_clk",
+ "csi2_src_clk", "csi2_clk",
+ "csi2_rdi_clk", "csi2_pix_clk",
+ "vfe0_clk_src", "camss_vfe_vfe0_clk",
+ "camss_csi_vfe0_clk", "vfe1_clk_src",
+ "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";
+ qcom,clock-rates = <61540000 0 0 0
+ 200000000 0 0 0
+ 200000000 0 0 0
+ 200000000 0 0 0
+ 0 0 0
+ 0 0 0>;
+ qcom,clock-cntl-support;
+ qcom,clock-control = "SET_RATE","NO_SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "NO_SET_RATE", "SET_RATE",
+ "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
+ "SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE",
+ "NO_SET_RATE";
+ };
+
+ vfe0: qcom,vfe0@1b10000 {
+ cell-index = <0>;
+ compatible = "qcom,vfe40";
+ reg = <0x1b10000 0x1000>,
+ <0x1b40000 0x200>;
+ reg-names = "vfe", "vfe_vbif";
+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vfe";
+ vdd-supply = <&gdsc_vfe>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc VFE0_CLK_SRC>,
+ <&gcc GCC_CAMSS_VFE0_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
+ <&gcc GCC_CAMSS_VFE_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE_AXI_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk", "camss_ahb_clk",
+ "vfe_clk_src", "camss_vfe_vfe_clk",
+ "camss_csi_vfe_clk", "iface_clk",
+ "bus_clk", "iface_ahb_clk";
+ qcom,clock-rates = <0 0 266670000 0 0 0 0 0>;
+ qos-entries = <8>;
+ qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8
+ 0x2dc 0x2e0>;
+ qos-settings = <0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55>;
+ vbif-entries = <1>;
+ vbif-regs = <0x124>;
+ vbif-settings = <0x3>;
+ ds-entries = <17>;
+ ds-regs = <0x988 0x98c 0x990 0x994 0x998
+ 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0
+ 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>;
+ ds-settings = <0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0x00000110>;
+ max-clk-nominal = <400000000>;
+ max-clk-turbo = <432000000>;
+ };
+
+ vfe1: qcom,vfe1@1b14000 {
+ cell-index = <1>;
+ compatible = "qcom,vfe40";
+ reg = <0x1b14000 0x1000>,
+ <0x1ba0000 0x200>;
+ reg-names = "vfe", "vfe_vbif";
+ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vfe";
+ vdd-supply = <&gdsc_vfe1>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc VFE1_CLK_SRC>,
+ <&gcc GCC_CAMSS_VFE1_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE1_CLK>,
+ <&gcc GCC_CAMSS_VFE1_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE1_AXI_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk" , "camss_ahb_clk",
+ "vfe_clk_src", "camss_vfe_vfe_clk",
+ "camss_csi_vfe_clk", "iface_clk",
+ "bus_clk", "iface_ahb_clk";
+ qcom,clock-rates = <0 0 266670000 0 0 0 0 0>;
+ qos-entries = <8>;
+ qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8
+ 0x2dc 0x2e0>;
+ qos-settings = <0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55>;
+ vbif-entries = <1>;
+ vbif-regs = <0x124>;
+ vbif-settings = <0x3>;
+ ds-entries = <17>;
+ ds-regs = <0x988 0x98c 0x990 0x994 0x998
+ 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0
+ 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>;
+ ds-settings = <0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0x00000110>;
+ max-clk-nominal = <400000000>;
+ max-clk-turbo = <432000000>;
+ };
+
+ qcom,vfe {
+ compatible = "qcom,vfe";
+ num_child = <2>;
+ };
+
+ qcom,cam_smmu {
+ status = "ok";
+ compatible = "qcom,msm-cam-smmu";
+ msm_cam_smmu_cb1: msm_cam_smmu_cb1 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_iommu 0x400 0x00>,
+ <&apps_iommu 0x2400 0x00>;
+ iommu-cells = <2>;
+ qcom,iommu-dma-addr-pool = <0x10000000 0x70000000>;
+ label = "vfe";
+ qcom,scratch-buf-support;
+ };
+
+ msm_cam_smmu_cb3: msm_cam_smmu_cb3 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_iommu 0x1c00 0x00>;
+ iommu-cells = <2>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0x78000000>;
+ label = "cpp";
+ };
+
+ msm_cam_smmu_cb4: msm_cam_smmu_cb4 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_iommu 0x1800 0x00>;
+ iommu-cells = <2>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0x78000000>;
+ label = "jpeg_enc0";
+ };
+ };
+
+ qcom,jpeg@1b1c000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,jpeg";
+ reg = <0x1b1c000 0x400>,
+ <0x1b60000 0xc30>;
+ reg-names = "jpeg_hw", "jpeg_vbif";
+ interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "jpeg";
+ vdd-supply = <&gdsc_jpeg>;
+ qcom,vdd-names = "vdd";
+ clock-names = "core_clk", "iface_clk", "bus_clk0",
+ "camss_top_ahb_clk", "camss_ahb_clk";
+ clocks = <&gcc GCC_CAMSS_JPEG0_CLK>,
+ <&gcc GCC_CAMSS_JPEG_AHB_CLK>,
+ <&gcc GCC_CAMSS_JPEG_AXI_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ qcom,clock-rates = <266670000 0 0 0 0>;
+ qcom,qos-reg-settings = <0x28 0x0000555e>,
+ <0xc8 0x00005555>;
+ qcom,vbif-reg-settings = <0xc0 0x10101000>,
+ <0xb0 0x10100010>;
+ qcom,msm-bus,name = "msm_camera_jpeg0";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <62 512 0 0>,
+ <62 512 800000 800000>;
+ };
+
+ qcom,cpp@1b04000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,cpp";
+ reg = <0x1b04000 0x100>,
+ <0x1b80000 0x200>,
+ <0x1b18000 0x018>,
+ <0x1858078 0x4>;
+ reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp";
+ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpp";
+ vdd-supply = <&gdsc_cpp>;
+ qcom,vdd-names = "vdd";
+ clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc CPP_CLK_SRC>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_CPP_AHB_CLK>,
+ <&gcc GCC_CAMSS_CPP_AXI_CLK>,
+ <&gcc GCC_CAMSS_CPP_CLK>,
+ <&gcc GCC_CAMSS_MICRO_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "ispif_ahb_clk", "cpp_core_clk",
+ "camss_top_ahb_clk", "camss_vfe_cpp_ahb_clk",
+ "camss_vfe_cpp_axi_clk", "camss_vfe_cpp_clk",
+ "micro_iface_clk", "camss_ahb_clk";
+ qcom,clock-rates = <61540000 180000000 0 0 0 180000000 0 0>;
+ qcom,min-clock-rate = <133000000>;
+ resets = <&gcc GCC_CAMSS_MICRO_BCR>;
+ reset-names = "micro_iface_reset";
+ qcom,bus-master = <1>;
+ qcom,msm-bus,name = "msm_camera_cpp";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <106 512 0 0>,
+ <106 512 0 0>;
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,micro-reset;
+ qcom,src-clock-rates = <133333333 160000000 200000000
+ 266666667 308570000 320000000 360000000>;
+ qcom,cpp-fw-payload-info {
+ qcom,stripe-base = <156>;
+ qcom,plane-base = <141>;
+ qcom,stripe-size = <27>;
+ qcom,plane-size = <5>;
+ qcom,fe-ptr-off = <5>;
+ qcom,we-ptr-off = <11>;
+ };
+ };
+
+ cci: qcom,cci@1b0c000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,cci";
+ reg = <0x1b0c000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "cci";
+ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cci";
+ clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc CCI_CLK_SRC>,
+ <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>;
+ clock-names = "ispif_ahb_clk", "cci_src_clk",
+ "cci_ahb_clk", "camss_cci_clk",
+ "camss_ahb_clk", "camss_top_ahb_clk";
+ qcom,clock-rates = <61540000 19200000 0 0 0 0>,
+ <61540000 37500000 0 0 0 0>;
+ pinctrl-names = "cci_default", "cci_suspend";
+ pinctrl-0 = <&cci0_active &cci1_active>;
+ pinctrl-1 = <&cci0_suspend &cci1_suspend>;
+ gpios = <&tlmm 29 0>,
+ <&tlmm 30 0>,
+ <&tlmm 31 0>,
+ <&tlmm 32 0>;
+ qcom,gpio-tbl-num = <0 1 2 3>;
+ qcom,gpio-tbl-flags = <1 1 1 1>;
+ qcom,gpio-tbl-label = "CCI_I2C_DATA0",
+ "CCI_I2C_CLK0",
+ "CCI_I2C_DATA1",
+ "CCI_I2C_CLK1";
+ i2c_freq_100Khz: qcom,i2c_standard_mode {
+ status = "disabled";
+ };
+
+ i2c_freq_400Khz: qcom,i2c_fast_mode {
+ status = "disabled";
+ };
+
+ i2c_freq_custom: qcom,i2c_custom_mode {
+ status = "disabled";
+ };
+
+ i2c_freq_1Mhz: qcom,i2c_fast_plus_mode {
+ status = "disabled";
+ };
+
+ };
+};
+
+&i2c_freq_100Khz {
+ qcom,hw-thigh = <78>;
+ qcom,hw-tlow = <114>;
+ qcom,hw-tsu-sto = <28>;
+ qcom,hw-tsu-sta = <28>;
+ qcom,hw-thd-dat = <10>;
+ qcom,hw-thd-sta = <77>;
+ qcom,hw-tbuf = <118>;
+ qcom,hw-scl-stretch-en = <0>;
+ qcom,hw-trdhld = <6>;
+ qcom,hw-tsp = <1>;
+};
+
+&i2c_freq_400Khz {
+ qcom,hw-thigh = <20>;
+ qcom,hw-tlow = <28>;
+ qcom,hw-tsu-sto = <21>;
+ qcom,hw-tsu-sta = <21>;
+ qcom,hw-thd-dat = <13>;
+ qcom,hw-thd-sta = <18>;
+ qcom,hw-tbuf = <32>;
+ qcom,hw-scl-stretch-en = <0>;
+ qcom,hw-trdhld = <6>;
+ qcom,hw-tsp = <3>;
+ status = "ok";
+};
+
+&i2c_freq_custom {
+ qcom,hw-thigh = <15>;
+ qcom,hw-tlow = <28>;
+ qcom,hw-tsu-sto = <21>;
+ qcom,hw-tsu-sta = <21>;
+ qcom,hw-thd-dat = <13>;
+ qcom,hw-thd-sta = <18>;
+ qcom,hw-tbuf = <25>;
+ qcom,hw-scl-stretch-en = <1>;
+ qcom,hw-trdhld = <6>;
+ qcom,hw-tsp = <3>;
+ status = "ok";
+};
+
+&i2c_freq_1Mhz {
+ qcom,hw-thigh = <16>;
+ qcom,hw-tlow = <22>;
+ qcom,hw-tsu-sto = <17>;
+ qcom,hw-tsu-sta = <18>;
+ qcom,hw-thd-dat = <16>;
+ qcom,hw-thd-sta = <15>;
+ qcom,hw-tbuf = <19>;
+ qcom,hw-scl-stretch-en = <1>;
+ qcom,hw-trdhld = <3>;
+ qcom,hw-tsp = <3>;
+ qcom,cci-clk-src = <37500000>;
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-coresight.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-coresight.dtsi
new file mode 100755
index 0000000..6847709
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-coresight.dtsi
@@ -0,0 +1,1203 @@
+&soc {
+ tmc_etr: tmc@6028000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+
+ reg = <0x6028000 0x1000>,
+ <0x6044000 0x15000>;
+ reg-names = "tmc-base", "bam-base";
+
+ interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "byte-cntr-irq";
+
+ arm,buffer-size = <0x400000>;
+ qcom,force-reg-dump;
+ arm,scatter-gather;
+
+ coresight-name = "coresight-tmc-etr";
+ coresight-csr = <&csr>;
+ coresight-ctis = <&cti0 &cti8>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tmc_etr_in_replicator: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator_out_tmc_etr>;
+ };
+ };
+ };
+
+ tmc_etf: tmc@6027000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+
+ reg = <0x6027000 0x1000>;
+ reg-names = "tmc-base";
+
+ coresight-name = "coresight-tmc-etf";
+ coresight-csr = <&csr>;
+
+ arm,default-sink;
+ qcom,force-reg-dump;
+
+ coresight-ctis = <&cti0 &cti8>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ tmc_etf_out_replicator:endpoint {
+ remote-endpoint =
+ <&replicator_in_tmc_etf>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tmc_etf_in_funnel_in0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_in0_out_tmc_etf>;
+ };
+ };
+ };
+ };
+
+ replicator: replicator@6026000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+
+ reg = <0x6026000 0x1000>;
+ reg-names = "replicator-base";
+
+ coresight-name = "coresight-replicator";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ replicator_out_tmc_etr: endpoint {
+ remote-endpoint =
+ <&tmc_etr_in_replicator>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ replicator_in_tmc_etf: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tmc_etf_out_replicator>;
+ };
+ };
+ };
+ };
+
+ funnel_in0: funnel@6021000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6021000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-in0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ funnel_in0_out_tmc_etf: endpoint {
+ remote-endpoint =
+ <&tmc_etf_in_funnel_in0>;
+ };
+ };
+
+ port@1 {
+ reg = <7>;
+ funnel_in0_in_stm: endpoint {
+ slave-mode;
+ remote-endpoint = <&stm_out_funnel_in0>;
+ };
+ };
+
+ port@2 {
+ reg = <6>;
+ funnel_in0_in_tpda: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_out_funnel_in0>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_in0_in_funnel_center: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_center_out_funnel_in0>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ funnel_in0_in_funnel_right: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_right_out_funnel_in0>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ funnel_in0_in_funnel_mm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_mm_out_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel_center: funnel@6100000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6100000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-center";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ funnel_center_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_funnel_center>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_center_in_rpm_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&rpm_etm0_out_funnel_center>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_center_in_dbgui: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&dbgui_out_funnel_center>;
+ };
+ };
+ };
+ };
+
+ funnel_right: funnel@6120000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6120000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-right";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ funnel_right_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_funnel_right>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_right_in_modem_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&modem_etm0_out_funnel_right>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_right_in_funnel_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_apss_out_funnel_right>;
+ };
+ };
+ };
+ };
+
+ funnel_mm: funnel@6130000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6130000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-mm";
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ funnel_mm_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_funnel_mm>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_mm_in_wcn_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&wcn_etm0_out_funnel_mm>;
+ };
+ };
+
+ port@2 {
+ reg = <4>;
+ funnel_mm_in_funnel_cam: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_cam_out_funnel_mm>;
+ };
+ };
+
+ port@3 {
+ reg = <5>;
+ funnel_mm_in_audio_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&audio_etm0_out_funnel_mm>;
+ };
+ };
+
+ port@4 {
+ reg = <6>;
+ funnel_mm_in_gfx: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&gfx_out_funnel_mm>;
+ };
+ };
+ };
+ };
+
+ funnel_cam: funnel@6132000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6132000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-cam";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ funnel_cam_out_funnel_mm: endpoint {
+ remote-endpoint = <&funnel_mm_in_funnel_cam>;
+ };
+ };
+ };
+
+ funnel_apss: funnel@61a1000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x61a1000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-apss";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ funnel_apss_out_funnel_right: endpoint {
+ remote-endpoint =
+ <&funnel_right_in_funnel_apss>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_apss0_in_etm4: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm4_out_funnel_apss0>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_apss0_in_etm5: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm5_out_funnel_apss0>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ funnel_apss0_in_etm6: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm6_out_funnel_apss0>;
+ };
+ };
+
+ port@4 {
+ reg = <3>;
+ funnel_apss0_in_etm7: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm7_out_funnel_apss0>;
+ };
+ };
+
+ port@5 {
+ reg = <4>;
+ funnel_apss0_in_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm0_out_funnel_apss0>;
+ };
+ };
+
+ port@6 {
+ reg = <5>;
+ funnel_apss0_in_etm1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm1_out_funnel_apss0>;
+ };
+ };
+
+ port@7 {
+ reg = <6>;
+ funnel_apss0_in_etm2: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm2_out_funnel_apss0>;
+ };
+ };
+
+ port@8 {
+ reg = <7>;
+ funnel_apss0_in_etm3: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm3_out_funnel_apss0>;
+ };
+ };
+ };
+ };
+
+ etm4: etm@619c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x619c000 0x1000>;
+ cpu = <&CPU4>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm4";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm4_out_funnel_apss0: endpoint {
+ remote-endpoint = <&funnel_apss0_in_etm4>;
+ };
+ };
+ };
+
+ etm5: etm@619d000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x619d000 0x1000>;
+ cpu = <&CPU5>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm5";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm5_out_funnel_apss0: endpoint {
+ remote-endpoint = <&funnel_apss0_in_etm5>;
+ };
+ };
+ };
+
+ etm6: etm@619e000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x619e000 0x1000>;
+ cpu = <&CPU6>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm6";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm6_out_funnel_apss0: endpoint {
+ remote-endpoint = <&funnel_apss0_in_etm6>;
+ };
+ };
+ };
+
+ etm7: etm@619f000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x619f000 0x1000>;
+ cpu = <&CPU7>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm7";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm7_out_funnel_apss0: endpoint {
+ remote-endpoint = <&funnel_apss0_in_etm7>;
+ };
+ };
+ };
+
+ etm0: etm@61bc000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x61bc000 0x1000>;
+ cpu = <&CPU0>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm0_out_funnel_apss0: endpoint {
+ remote-endpoint = <&funnel_apss0_in_etm0>;
+ };
+ };
+ };
+
+ etm1: etm@61bd000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x61bd000 0x1000>;
+ cpu = <&CPU1>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm1";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm1_out_funnel_apss0: endpoint {
+ remote-endpoint = <&funnel_apss0_in_etm1>;
+ };
+ };
+ };
+
+ etm2: etm@61be000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x61be000 0x1000>;
+ cpu = <&CPU2>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm2";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm2_out_funnel_apss0: endpoint {
+ remote-endpoint = <&funnel_apss0_in_etm2>;
+ };
+ };
+ };
+
+ etm3: etm@61bf000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x61bf000 0x1000>;
+
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm3";
+ cpu = <&CPU3>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ etm3_out_funnel_apss0: endpoint {
+ remote-endpoint = <&funnel_apss0_in_etm3>;
+ };
+ };
+ };
+
+ stm: stm@6002000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb962>;
+
+ reg = <0x6002000 0x1000>,
+ <0x9280000 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ coresight-name = "coresight-stm";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ stm_out_funnel_in0: endpoint {
+ remote-endpoint = <&funnel_in0_in_stm>;
+ };
+ };
+ };
+
+ cti0: cti@6010000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6010000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1: cti@6011000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6011000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti1";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2: cti@6012000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6012000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti2";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti3: cti@6013000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6013000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti3";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti4: cti@6014000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6014000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti4";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti5: cti@6015000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6015000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti5";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti6: cti@6016000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6016000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti6";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti7: cti@6017000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6017000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti7";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti8: cti@6018000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6018000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti8";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti9: cti@6019000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6019000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti9";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti10: cti@601a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x601a000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti10";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti11: cti@601b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x601b000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti11";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti12: cti@601c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x601c000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti12";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti13: cti@601d000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x601d000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti13";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti14: cti@601e000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x601e000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti14";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti15: cti@601f000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x601f000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti15";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu0: cti@61b8000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x61b8000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti-cpu0";
+ cpu = <&CPU0>;
+ qcom,cti-save;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu1: cti@61b9000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x61b9000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti-cpu1";
+ cpu = <&CPU1>;
+ qcom,cti-save;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu2: cti@61ba000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x61ba000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti-cpu2";
+ cpu = <&CPU2>;
+ qcom,cti-save;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu3: cti@61bb000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x61bb000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti-cpu3";
+ cpu = <&CPU3>;
+ qcom,cti-save;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu4: cti@6198000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6198000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti-cpu4";
+ cpu = <&CPU4>;
+ qcom,cti-save;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu5: cti@6199000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6199000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti-cpu5";
+ cpu = <&CPU5>;
+ qcom,cti-save;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu6: cti@619a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x619a000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti-cpu6";
+ cpu = <&CPU6>;
+ qcom,cti-save;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_cpu7: cti@619b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x619b000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti-cpu7";
+ cpu = <&CPU7>;
+ qcom,cti-save;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_modem_cpu0: cti@6124000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6124000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti-modem-cpu0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ /* Venus CTI */
+ cti_video_cpu0: cti@6035000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6035000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti-video-cpu0";
+
+ status = "disabled";
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ /* Pronto CTI */
+ cti_wcn_cpu0: cti@6039000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x6039000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti-wcn-cpu0";
+
+ status = "disabled";
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ /* LPASS CTI */
+ cti_audio_cpu0: cti@613c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x613c000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti-audio-cpu0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_rpm_cpu0: cti@610c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x610c000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti-rpm-cpu0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ /* Pronto ETM */
+ wcn_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+ coresight-name = "coresight-wcn-etm0";
+ qcom,inst-id = <3>;
+
+ port {
+ wcn_etm0_out_funnel_mm: endpoint {
+ remote-endpoint = <&funnel_mm_in_wcn_etm0>;
+ };
+ };
+ };
+
+ rpm_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+ coresight-name = "coresight-rpm-etm0";
+ qcom,inst-id = <4>;
+
+ port {
+ rpm_etm0_out_funnel_center: endpoint {
+ remote-endpoint = <&funnel_center_in_rpm_etm0>;
+ };
+ };
+ };
+
+ /* LPASS ETM */
+ audio_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+ coresight-name = "coresight-audio-etm0";
+ qcom,inst-id = <5>;
+
+ port {
+ audio_etm0_out_funnel_mm: endpoint {
+ remote-endpoint = <&funnel_mm_in_audio_etm0>;
+ };
+ };
+ };
+
+ /* MSS_SCL */
+ modem_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+ coresight-name = "coresight-modem-etm0";
+ qcom,inst-id = <2>;
+
+ port {
+ modem_etm0_out_funnel_right: endpoint {
+ remote-endpoint = <&funnel_right_in_modem_etm0>;
+ };
+ };
+ };
+
+
+ csr: csr@6001000 {
+ compatible = "qcom,coresight-csr";
+ reg = <0x6001000 0x1000>;
+ reg-names = "csr-base";
+ coresight-name = "coresight-csr";
+
+ qcom,usb-bam-support;
+ qcom,hwctrl-set-support;
+ qcom,set-byte-cntr-support;
+
+ qcom,blk-size = <1>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ dbgui: dbgui@6108000 {
+ compatible = "qcom,coresight-dbgui";
+ reg = <0x6108000 0x1000>;
+ reg-names = "dbgui-base";
+ coresight-name = "coresight-dbgui";
+
+ qcom,dbgui-addr-offset = <0x30>;
+ qcom,dbgui-data-offset = <0x130>;
+ qcom,dbgui-size = <64>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ dbgui_out_funnel_center: endpoint {
+ remote-endpoint = <&funnel_center_in_dbgui>;
+ };
+ };
+ };
+
+ tpda: tpda@6003000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+
+ reg = <0x6003000 0x1000>;
+ reg-names = "tpda-base";
+ coresight-name = "coresight-tpda";
+
+ qcom,tpda-atid = <64>;
+ qcom,cmb-elem-size = <0 32>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ tpda_out_funnel_in0: endpoint {
+ remote-endpoint = <&funnel_in0_in_tpda>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_in_tpdm_dcc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dcc_out_tpda>;
+ };
+ };
+ };
+ };
+
+ tpdm_dcc: tpdm@6110000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+
+ reg = <0x6110000 0x1000>;
+ reg-names = "tpdm-base";
+ coresight-name = "coresight-tpdm-dcc";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ tpdm_dcc_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_dcc>;
+ };
+ };
+ };
+
+ hwevent: hwevent@6101000 {
+ compatible = "qcom,coresight-hwevent";
+
+ reg = <0x6101000 0x148>,
+ <0x6101fb0 0x4>,
+ <0x6121000 0x148>,
+ <0x6121fb0 0x4>,
+ <0x6131000 0x148>,
+ <0x6131fb0 0x4>,
+ <0x78c5010 0x4>,
+ <0x7885010 0x4>;
+
+ reg-names = "center-wrapper-mux", "center-wrapper-lockaccess",
+ "right-wrapper-mux", "right-wrapper-lockaccess",
+ "mm-wrapper-mux", "mm-wrapper-lockaccess",
+ "usbbam-mux", "blsp-mux";
+
+ coresight-name = "coresight-hwevent";
+ coresight-csr = <&csr>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>,
+ <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-cpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-cpu.dtsi
new file mode 100755
index 0000000..a39b6e9
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-cpu.dtsi
@@ -0,0 +1,225 @@
+/ {
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+ };
+
+ CPU0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1126>;
+ sched-energy-costs = <&CPU_COST_0>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L2_1: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ };
+
+ L1_I_100: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_100: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x101>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1126>;
+ sched-energy-costs = <&CPU_COST_0>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L1_I_101: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_101: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU2: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x102>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1126>;
+ sched-energy-costs = <&CPU_COST_0>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L1_I_102: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_102: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU3: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x103>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1126>;
+ sched-energy-costs = <&CPU_COST_0>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L1_I_103: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_103: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU4: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_1>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ };
+
+ L1_I_0: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_0: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU5: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_1>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ L1_I_1: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_1: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU6: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x2>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_1>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ L1_I_2: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_2: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU7: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x3>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_1>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ L1_I_3: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_3: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+ };
+
+ energy_costs: energy-costs {
+
+ CPU_COST_0: core-cost0 {
+ busy-cost-data = <
+ 512 623
+ 731 917
+ 805 1106
+ 914 1432
+ 1024 1740
+ >;
+ };
+
+ CPU_COST_1: core-cost1 {
+ busy-cost-data = <
+ 333 70
+ 532 114
+ 599 141
+ 665 178
+ 732 213
+ >;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-gpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-gpu.dtsi
new file mode 100755
index 0000000..6183246
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-gpu.dtsi
@@ -0,0 +1,247 @@
+&soc {
+ msm_bus: qcom,kgsl-busmon {
+ label = "kgsl-busmon";
+ compatible = "qcom,kgsl-busmon";
+ };
+
+ gpu_bw_tbl: gpu-bw-tbl {
+ compatible = "operating-points-v2";
+ opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */
+
+ opp-100 { opp-hz = /bits/ 64 < 769 >; }; /* 1. 100 MHz */
+
+ opp-211 { opp-hz = /bits/ 64 < 1611 >; }; /* 2. 211 MHz */
+
+ opp-278 { opp-hz = /bits/ 64 < 2124 >; }; /* 3. 278 MHz */
+
+ opp-384 { opp-hz = /bits/ 64 < 2929 >; }; /* 4. 384 MHz */
+
+ opp-537 { opp-hz = /bits/ 64 < 4101 >; }; /* 5. 537 MHz */
+
+ opp-557 { opp-hz = /bits/ 64 < 4248 >; }; /* 6. 557 MHz */
+
+ opp-700 { opp-hz = /bits/ 64 < 5346 >; }; /* 7. 700 MHz */
+
+ opp-748 { opp-hz = /bits/ 64 < 5712 >; }; /* 8. 748 MHz */
+
+ opp-806 { opp-hz = /bits/ 64 < 6152 >; }; /* 9. 806 MHz */
+
+ opp-922 { opp-hz = /bits/ 64 < 7031 >; }; /* 10. 922 MHz */
+ };
+
+ gpubw: qcom,gpubw {
+ compatible = "qcom,devbw";
+ governor = "bw_vbif";
+ qcom,src-dst-ports = <26 512>;
+ operating-points-v2 = <&gpu_bw_tbl>;
+ /*
+ * active-only flag is used while registering the bus
+ * governor.It helps release the bus vote when the CPU
+ * subsystem is inactiv3
+ */
+ qcom,active-only;
+ };
+
+ msm_gpu: qcom,kgsl-3d0@1c00000 {
+ label = "kgsl-3d0";
+ compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
+ status = "ok";
+ reg = <0x1c00000 0x40000
+ 0xa0000 0x6fff>;
+ reg-names = "kgsl_3d0_reg_memory", "qfprom_memory";
+ interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+ qcom,id = <0>;
+ qcom,chipid = <0x05000500>;
+
+ qcom,initial-pwrlevel = <2>;
+
+ qcom,idle-timeout = <80>; //msecs
+ qcom,strtstp-sleepwake;
+
+ qcom,highest-bank-bit = <14>;
+
+ qcom,snapshot-size = <1048576>; //bytes
+
+ clocks = <&gcc GCC_OXILI_GFX3D_CLK>,
+ <&gcc GCC_OXILI_AHB_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>,
+ <&gcc GCC_BIMC_GPU_CLK>,
+ <&gcc GCC_OXILI_TIMER_CLK>,
+ <&gcc GCC_OXILI_AON_CLK>;
+
+ clock-names = "core_clk", "iface_clk",
+ "mem_iface_clk", "alt_mem_iface_clk",
+ "rbbmtimer_clk", "alwayson_clk";
+
+
+ /* Bus Scale Settings */
+ qcom,gpubw-dev = <&gpubw>;
+ qcom,bus-control;
+ qcom,bus-width = <16>;
+ qcom,msm-bus,name = "grp3d";
+ qcom,msm-bus,num-cases = <11>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <26 512 0 0>, /* off */
+ <26 512 0 806400>, /* 1. 100.80 MHz */
+ <26 512 0 1689600>, /* 2. 211.20 MHz */
+ <26 512 0 2227200>, /* 3. 278.40 MHz */
+ <26 512 0 3072000>, /* 4. 384.00 MHz */
+ <26 512 0 4300800>, /* 5. 537.60 MHz */
+ <26 512 0 4454400>, /* 6. 556.80 MHz */
+ <26 512 0 5299200>, /* 7. 662.40 MHz */
+ <26 512 0 5990400>, /* 8. 748.80 MHz */
+ <26 512 0 6451200>, /* 9. 806.40 MHz */
+ <26 512 0 7372800>; /* 10. 921.60 MHz */
+
+ /* GDSC regulator names */
+ regulator-names = "vddcx", "vdd";
+ /* GDSC oxili regulators */
+ vddcx-supply = <&gdsc_oxili_cx>;
+ vdd-supply = <&gdsc_oxili_gx>;
+
+ /* CPU latency parameter */
+ qcom,pm-qos-active-latency = <360>;
+ qcom,pm-qos-wakeup-latency = <360>;
+
+ /* Quirks */
+ qcom,gpu-quirk-two-pass-use-wfi;
+ qcom,gpu-quirk-dp2clockgating-disable;
+ qcom,gpu-quirk-lmloadkill-disable;
+
+ /* Enable context aware freq. scaling */
+ qcom,enable-ca-jump;
+
+ /* Context aware jump busy penalty in us */
+ qcom,ca-busy-penalty = <12000>;
+
+ /* Context aware jump target power level */
+ qcom,ca-target-pwrlevel = <1>;
+
+ /* Enable gpu cooling device */
+ #cooling-cells = <2>;
+
+ /* GPU Mempools */
+ qcom,gpu-mempools {
+ #address-cells= <1>;
+ #size-cells = <0>;
+ compatible = "qcom,gpu-mempools";
+
+ qcom,mempool-max-pages = <32768>;
+
+ /* 4K Page Pool configuration */
+ qcom,gpu-mempool@0 {
+ reg = <0>;
+ qcom,mempool-page-size = <4096>;
+ };
+ /* 64K Page Pool configuration */
+ qcom,gpu-mempool@1 {
+ reg = <1>;
+ qcom,mempool-page-size = <65536>;
+ };
+ };
+
+ qcom,gpu-coresights {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,gpu-coresight";
+
+ /* Trace bus */
+ qcom,gpu-coresight@0 {
+ reg = <0>;
+ coresight-name = "coresight-gfx";
+ coresight-atid = <67>;
+ port {
+ gfx_out_funnel_mm: endpoint {
+ remote-endpoint =
+ <&funnel_mm_in_gfx>;
+ };
+ };
+ };
+ };
+
+ /* Power levels */
+ qcom,gpu-pwrlevels {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "qcom,gpu-pwrlevels";
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <450000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <9>;
+ };
+
+ /* NOM+ */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <6>;
+ qcom,bus-max = <9>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <375000000>;
+ qcom,bus-freq = <6>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ };
+
+ /* SVS+ */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <300000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <7>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <216000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <1>;
+ qcom,bus-max = <4>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+ };
+
+ kgsl_msm_iommu: qcom,kgsl-iommu@1c40000 {
+ compatible = "qcom,kgsl-smmu-v2";
+
+ reg = <0x1c40000 0x10000>;
+
+ clocks = <&gcc GCC_OXILI_AHB_CLK>,
+ <&gcc GCC_BIMC_GFX_CLK>;
+
+ clock-names = "gpu_ahb_clk", "gcc_bimc_gfx_clk";
+
+ qcom,secure_align_mask = <0xfff>;
+ qcom,retention;
+ gfx3d_user: gfx3d_user {
+ compatible = "qcom,smmu-kgsl-cb";
+ label = "gfx3d_user";
+ iommus = <&kgsl_smmu 0>;
+ qcom,iommu-dma = "disabled";
+ qcom,gpu-offset = <0x48000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429-cdp.dts
new file mode 100755
index 0000000..2a85d99
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429-cdp.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "msm8937-interposer-sdm429.dtsi"
+#include "sdm429-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8937 Interposer SDM429 CDP";
+ compatible = "qcom,msm8937-cdp", "qcom,msm8937", "qcom,cdp";
+ qcom,board-id = <1 3>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429-mtp.dts
new file mode 100755
index 0000000..ae35852
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429-mtp.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "msm8937-interposer-sdm429.dtsi"
+#include "sdm429-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8937 Interposer SDM429 MTP";
+ compatible = "qcom,msm8937-mtp", "qcom,msm8937", "qcom,mtp";
+ qcom,board-id = <8 2>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429.dts b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429.dts
new file mode 100755
index 0000000..dd794d2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "msm8937-interposer-sdm429.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8953 + PMI632 SOC";
+ compatible = "qcom,msm8953";
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+ qcom.pmic-name = "PMI632";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429.dtsi
new file mode 100755
index 0000000..c05f013
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm429.dtsi
@@ -0,0 +1,68 @@
+#include "msm8937-interposer-sdm439.dtsi"
+#include "sdm429-cpu.dtsi"
+
+&apsscc {
+ qcom,cpu-isolation {
+ /delete-node/ cpu4-isolate;
+ /delete-node/ cpu5-isolate;
+ /delete-node/ cpu6-isolate;
+ /delete-node/ cpu7-isolate;
+ };
+};
+
+&soc {
+ /delete-node/ etm@619c000;
+ /delete-node/ etm@619d000;
+ /delete-node/ etm@619e000;
+ /delete-node/ etm@619f000;
+ /delete-node/ cti@6198000;
+ /delete-node/ cti@6199000;
+ /delete-node/ cti@619a000;
+ /delete-node/ cti@619b000;
+ /delete-node/ jtagmm@619c000;
+ /delete-node/ jtagmm@619d000;
+ /delete-node/ jtagmm@619e000;
+ /delete-node/ jtagmm@619f000;
+ /delete-node/ qcom,cpu4-cpugrp;
+
+ qcom,spm@b1d2000 {
+ qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ };
+
+ qcom,lpm-levels {
+ qcom,pm-cluster@0 {
+ /delete-node/qcom,pm-cluster@1;
+ };
+ };
+};
+
+&funnel_apss {
+ ports {
+ /delete-node/ port@1;
+ /delete-node/ port@2;
+ /delete-node/ port@3;
+ /delete-node/ port@4;
+ };
+};
+
+&thermal_zones {
+ hexa-cpu-max-step {
+ cooling-maps {
+ /delete-node/ cpu4_cdev;
+ /delete-node/ cpu5_cdev;
+ /delete-node/ cpu6_cdev;
+ /delete-node/ cpu7_cdev;
+ };
+ };
+
+ /delete-node/ cpuss0-step;
+
+ quiet-therm-step {
+ cooling-maps {
+ /delete-node/ skin_cpu4;
+ /delete-node/ skin_cpu5;
+ /delete-node/ skin_cpu6;
+ /delete-node/ skin_cpu7;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439-cdp.dts
new file mode 100755
index 0000000..01353a3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439-cdp.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "msm8937-interposer-sdm439.dtsi"
+#include "sdm439-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8937 Interposer SDM439 CDP";
+ compatible = "qcom,msm8937-cdp", "qcom,msm8937", "qcom,cdp";
+ qcom,board-id = <1 2>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439-mtp.dts
new file mode 100755
index 0000000..b734cbd
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439-mtp.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "msm8937-interposer-sdm439.dtsi"
+#include "sdm439-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8937 Interposer SDM439 MTP";
+ compatible = "qcom,msm8937-mtp", "qcom,msm8937", "qcom,mtp";
+ qcom,board-id = <8 1>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439-qrd.dts
new file mode 100755
index 0000000..66e2757
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439-qrd.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "msm8937-interposer-sdm439.dtsi"
+#include "sdm439-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8937 Interposer SDM439 QRD";
+ compatible = "qcom,msm8937-qrd", "qcom,msm8937", "qcom,qrd";
+ qcom,board-id = <0xb 2>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439.dts b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439.dts
new file mode 100755
index 0000000..57d2674e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "msm8937-interposer-sdm439.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8953 + PMI632 SOC";
+ compatible = "qcom,msm8953";
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+ qcom.pmic-name = "PMI632";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439.dtsi
new file mode 100755
index 0000000..4c9e512
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-interposer-sdm439.dtsi
@@ -0,0 +1,172 @@
+#include "msm8937.dtsi"
+#include "sdm439-pm8953.dtsi"
+#include "sdm439-audio.dtsi"
+#include "sdm439-pmi632.dtsi"
+
+&pm8953_s5 {
+ regulator-min-microvolt = <1155000>;
+ regulator-max-microvolt = <1350000>;
+};
+
+&pm8953_s5_limit {
+ regulator-min-microvolt = <1155000>;
+ regulator-max-microvolt = <1350000>;
+};
+
+&soc {
+ qcom,csiphy@1b34000 {
+ compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy";
+ };
+
+ qcom,csiphy@1b35000 {
+ compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy";
+ };
+
+ qcom,csid@1b30000 {
+ qcom,mipi-csi-vdd-supply = <&pm8953_l2>;
+ };
+
+ qcom,csid@1b30400 {
+ qcom,mipi-csi-vdd-supply = <&pm8953_l2>;
+ };
+
+ qcom,csid@1b30800 {
+ qcom,mipi-csi-vdd-supply = <&pm8953_l2>;
+ };
+
+ mem_acc_vreg_corner: regulator@01946004 {
+ compatible = "qcom,mem-acc-regulator";
+ regulator-name = "mem_acc_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <3>;
+
+ qcom,acc-reg-addr-list =
+ <0x01942138 0x01942130 0x01942120
+ 0x01942124 0x01946000 0x01946004>;
+
+ qcom,acc-init-reg-config = <1 0xff>, <2 0x5555>, <6 0x55>;
+
+ qcom,num-acc-corners = <3>;
+ qcom,boot-acc-corner = <2>;
+ qcom,corner1-reg-config =
+ /* SVS+ => SVS+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ /* SVS+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>,
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ /* SVS+ => TURBO/NOM+ */
+ < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>,
+ < 3 0x0>, < 4 0x0>, < 5 0x0>;
+
+ qcom,corner2-reg-config =
+ /* NOM => SVS+ */
+ < 3 0x30c30c3>, < 4 0x30c3>, < 5 0x6060606>,
+ /* NOM => NOM */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ /* NOM => TURBO/NOM+ */
+ < 3 0x0>, < 4 0x0>, < 5 0x0>;
+
+ qcom,corner3-reg-config =
+ /* TURBO/NOM+ => SVS+ */
+ < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>,
+ < 3 0x30c30c3>, < 4 0x30c3>, < 5 0x6060606>,
+ /* TURBO/NOM+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>,
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ /* TURBO/NOM+ => TURBO/NOM+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>;
+ };
+
+ apc_vreg_corner: regulator@b018000 {
+ compatible = "qcom,cpr-regulator";
+ reg = <0xb018000 0x1000>, <0xb011064 0x4>, <0xa4000 0x1000>;
+ reg-names = "rbcpr", "rbcpr_clk", "efuse_addr";
+ interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+ regulator-name = "apc_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <7>;
+
+ qcom,cpr-fuse-corners = <3>;
+ qcom,cpr-voltage-ceiling = <1155000 1225000 1350000>;
+ qcom,cpr-voltage-floor = <1050000 1050000 1090000>;
+ vdd-apc-supply = <&pm8953_s5>;
+
+ mem-acc-supply = <&mem_acc_vreg_corner>;
+
+ qcom,cpr-ref-clk = <19200>;
+ qcom,cpr-timer-delay = <5000>;
+ qcom,cpr-timer-cons-up = <0>;
+ qcom,cpr-timer-cons-down = <2>;
+ qcom,cpr-irq-line = <0>;
+ qcom,cpr-step-quotient = <10>;
+ qcom,cpr-up-threshold = <2>;
+ qcom,cpr-down-threshold = <4>;
+ qcom,cpr-idle-clocks = <15>;
+ qcom,cpr-gcnt-time = <1>;
+ qcom,vdd-apc-step-up-limit = <1>;
+ qcom,vdd-apc-step-down-limit = <1>;
+ qcom,cpr-apc-volt-step = <5000>;
+
+ qcom,cpr-fuse-row = <67 0>;
+ qcom,cpr-fuse-target-quot = <42 24 6>;
+ qcom,cpr-fuse-ro-sel = <60 57 54>;
+ qcom,cpr-init-voltage-ref = <1155000 1225000 1350000>;
+ qcom,cpr-fuse-init-voltage =
+ <67 36 6 0>,
+ <67 18 6 0>,
+ <67 0 6 0>;
+ qcom,cpr-fuse-quot-offset =
+ <71 26 6 0>,
+ <71 20 6 0>,
+ <70 54 7 0>;
+ qcom,cpr-fuse-quot-offset-scale = <5 5 5>;
+ qcom,cpr-init-voltage-step = <10000>;
+ qcom,cpr-corner-map = <1 2 3 3 3 3 3>;
+ qcom,cpr-corner-frequency-map =
+ <1 960000000>,
+ <2 1094400000>,
+ <3 1209600000>,
+ <4 1248000000>,
+ <5 1344000000>,
+ <6 1401000000>,
+ <7 1497600000>;
+ qcom,speed-bin-fuse-sel = <37 34 3 0>;
+ qcom,cpr-speed-bin-max-corners =
+ <0 0 1 2 6>,
+ <1 0 1 2 7>,
+ <2 0 1 2 3>;
+ qcom,cpr-fuse-revision = <69 39 3 0>;
+ qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>;
+ qcom,cpr-voltage-scaling-factor-max = <0 2000 2000>;
+ qcom,cpr-scaled-init-voltage-as-ceiling;
+ qcom,cpr-fuse-version-map =
+ <0 (-1) 1 (-1) (-1) (-1)>,
+ <(-1) (-1) 2 (-1) (-1) (-1)>,
+ <(-1) (-1) 3 (-1) (-1) (-1)>,
+ <(-1) (-1) (-1) (-1) (-1) (-1)>;
+ qcom,cpr-quotient-adjustment =
+ <(-20) (-40) (-20)>,
+ <0 (-40) (20)>,
+ <0 0 (20)>,
+ <0 0 0>;
+ qcom,cpr-init-voltage-adjustment =
+ <0 0 0>,
+ <(10000) (15000) (20000)>,
+ <0 0 0>,
+ <0 0 0>;
+ qcom,cpr-enable;
+ };
+
+ qcom,clock-cpu@b111050 {
+ vdd-c0-supply = <&apc_vreg_corner>;
+ cpu-vdd-supply = <&apc_vreg_corner>;
+ vdd-cci-supply = <&apc_vreg_corner>;
+ };
+};
+
+&mdss_dsi {
+ vdda-supply = <&pm8953_l2>;
+ vddio-supply = <&pm8953_l6>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-ion.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-ion.dtsi
new file mode 100755
index 0000000..86feded
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-ion.dtsi
@@ -0,0 +1,30 @@
+&soc {
+ qcom,ion {
+ compatible = "qcom,msm-ion";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ion-heap@25 {
+ reg = <25>;
+ qcom,ion-heap-type = "SYSTEM";
+ };
+
+ qcom,ion-heap@8 { /* CP_MM HEAP */
+ reg = <8>;
+ memory-region = <&secure_mem>;
+ qcom,ion-heap-type = "SECURE_DMA";
+ };
+
+ qcom,ion-heap@27 { /* QSEECOM HEAP */
+ reg = <27>;
+ memory-region = <&qseecom_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@19 { /* QSEECOM TA HEAP */
+ reg = <19>;
+ memory-region = <&qseecom_ta_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-mdss-panels.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-mdss-panels.dtsi
new file mode 100755
index 0000000..46dced5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-mdss-panels.dtsi
@@ -0,0 +1,84 @@
+#include "dsi-panel-sim-video.dtsi"
+#include "dsi-panel-sim-cmd.dtsi"
+#include "dsi-panel-truly-1080p-video.dtsi"
+#include "dsi-panel-truly-1080p-cmd.dtsi"
+#include "dsi-panel-truly-720p-video.dtsi"
+#include "dsi-panel-truly-720p-cmd.dtsi"
+#include "dsi-panel-r69006-1080p-cmd.dtsi"
+#include "dsi-panel-r69006-1080p-video.dtsi"
+#include "dsi-panel-hx8394f-720p-video.dtsi"
+#include "dsi-adv7533-1080p.dtsi"
+#include "dsi-adv7533-720p.dtsi"
+#include "dsi-panel-hx8399c-fhd-plus-video.dtsi"
+#include "dsi-panel-hx8399c-hd-plus-video.dtsi"
+#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
+#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
+#include "dsi-panel-icn9706-720-1440p-video.dtsi"
+#include "dsi-panel-edo-rm67162-qvga-cmd.dtsi"
+
+&soc {
+ dsi_panel_pwr_supply: dsi_panel_pwr_supply {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdd";
+ qcom,supply-min-voltage = <2850000>;
+ qcom,supply-max-voltage = <2850000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@2 {
+ reg = <2>;
+ qcom,supply-name = "lab";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@3 {
+ reg = <3>;
+ qcom,supply-name = "ibb";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-post-on-sleep = <10>;
+ };
+ };
+
+ dsi_pm660_panel_pwr_supply: dsi_pm660_panel_pwr_supply {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdd";
+ qcom,supply-min-voltage = <2800000>;
+ qcom,supply-max-voltage = <2800000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-mdss-pll.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-mdss-pll.dtsi
new file mode 100755
index 0000000..56d7c1e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-mdss-pll.dtsi
@@ -0,0 +1,91 @@
+&soc {
+ mdss_dsi0_pll: qcom,mdss_dsi_pll@1a94a00 {
+ compatible = "qcom,mdss_dsi_pll_28lpm";
+ label = "MDSS DSI 0 PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+
+ reg = <0x001a94a00 0xd4>,
+ <0x0184d074 0x8>;
+ reg-names = "pll_base", "gdsc_base";
+
+ gdsc-supply = <&gdsc_mdss>;
+ vddio-supply = <&pm8937_l6>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ qcom,ssc-frequency-hz = <30000>;
+ qcom,ssc-ppm = <5000>;
+
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+
+ qcom,platform-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+ };
+ };
+
+ mdss_dsi1_pll: qcom,mdss_dsi_pll@1a96a00 {
+ compatible = "qcom,mdss_dsi_pll_28lpm";
+ label = "MDSS DSI 1 PLL";
+ cell-index = <1>;
+ #clock-cells = <1>;
+
+ reg = <0x001a96a00 0xd4>,
+ <0x0184d074 0x8>;
+ reg-names = "pll_base", "gdsc_base";
+
+ gdsc-supply = <&gdsc_mdss>;
+ vddio-supply = <&pm8937_l6>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ qcom,ssc-frequency-hz = <30000>;
+ qcom,ssc-ppm = <5000>;
+
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+
+ qcom,platform-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-mdss.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-mdss.dtsi
new file mode 100755
index 0000000..59b8a28
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-mdss.dtsi
@@ -0,0 +1,406 @@
+&soc {
+ mdss_mdp: qcom,mdss_mdp@1a00000 {
+ compatible = "qcom,mdss_mdp";
+ reg = <0x01a00000 0x90000>,
+ <0x01ab0000 0x1040>;
+ reg-names = "mdp_phys", "vbif_phys";
+ interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
+ vdd-supply = <&gdsc_mdss>;
+
+ /* Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_mdp";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>,
+ <22 512 0 6400000>,
+ <22 512 0 6400000>;
+
+ /* Fudge factors */
+ qcom,mdss-ab-factor = <1 1>; /* 1 time */
+ qcom,mdss-ib-factor = <1 1>; /* 1 time */
+ qcom,mdss-clk-factor = <105 100>; /* 1.05 times */
+
+ qcom,max-mixer-width = <2048>;
+ qcom,max-pipe-width = <2048>;
+
+ /* VBIF QoS remapper settings*/
+ qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>;
+ qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>;
+
+ qcom,mdss-has-panic-ctrl;
+ qcom,mdss-per-pipe-panic-luts = <0x000f>,
+ <0xffff>,
+ <0xfffc>,
+ <0xff00>;
+
+ qcom,mdss-mdp-reg-offset = <0x00001000>;
+ qcom,max-bandwidth-low-kbps = <3100000>;
+ qcom,max-bandwidth-high-kbps = <3100000>;
+ qcom,max-bandwidth-per-pipe-kbps = <2300000>;
+
+ /* Bandwidth limit settings */
+ qcom,max-bw-settings = <1 3100000>, /* Default */
+ <2 1700000>; /* Camera */
+
+ qcom,max-clk-rate = <320000000>;
+ qcom,mdss-default-ot-rd-limit = <32>;
+ qcom,mdss-default-ot-wr-limit = <16>;
+
+ qcom,mdss-pipe-vig-off = <0x00005000>;
+ qcom,mdss-pipe-rgb-off = <0x00015000 0x00017000>;
+ qcom,mdss-pipe-dma-off = <0x00025000>;
+ qcom,mdss-pipe-cursor-off = <0x00035000>;
+
+ qcom,mdss-pipe-vig-xin-id = <0>;
+ qcom,mdss-pipe-rgb-xin-id = <1 5>;
+ qcom,mdss-pipe-dma-xin-id = <2>;
+ qcom,mdss-pipe-cursor-xin-id = <7>;
+
+ /* Offsets relative to "mdp_phys + mdp-reg-offset" address */
+ qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2AC 0 0>;
+ qcom,mdss-pipe-rgb-clk-ctrl-offsets = <0x2AC 4 8>,
+ <0x2B4 4 8>;
+ qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2AC 8 12>;
+ qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3A8 16 15>;
+
+
+ qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400>;
+ qcom,mdss-mixer-intf-off = <0x00045000 0x00046000>;
+ qcom,mdss-dspp-off = <0x00055000>;
+ qcom,mdss-wb-off = <0x00065000 0x00066000>;
+ qcom,mdss-intf-off = <0x00000000 0x0006B800 0x0006C000>;
+ qcom,mdss-pingpong-off = <0x00071000 0x00071800>;
+ qcom,mdss-slave-pingpong-off = <0x00073000>;
+ qcom,mdss-cdm-off = <0x0007a200>;
+ qcom,mdss-wfd-mode = "intf";
+ qcom,mdss-highest-bank-bit = <0x1>;
+ qcom,mdss-has-decimation;
+ qcom,mdss-has-non-scalar-rgb;
+ qcom,mdss-has-rotator-downscale;
+ qcom,mdss-rot-downscale-min = <2>;
+ qcom,mdss-rot-downscale-max = <16>;
+ qcom,mdss-idle-power-collapse-enabled;
+ qcom,mdss-rot-block-size = <64>;
+
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&gcc MDP_CLK_SRC>,
+ <&gcc_mdss MDSS_MDP_VOTE_CLK>,
+ <&gcc GCC_MDSS_VSYNC_CLK>;
+ clock-names = "iface_clk", "bus_clk", "core_clk_src",
+ "core_clk", "vsync_clk";
+
+ qcom,mdp-settings = <0x0506c 0x00000000>,
+ <0x1506c 0x00000000>,
+ <0x1706c 0x00000000>,
+ <0x2506c 0x00000000>;
+
+ qcom,vbif-settings = <0x0d0 0x00000010>;
+
+ qcom,regs-dump-mdp = <0x01000 0x01454>,
+ <0x02000 0x02064>,
+ <0x02200 0x02264>,
+ <0x02400 0x02464>,
+ <0x05000 0x05150>,
+ <0x05200 0x05230>,
+ <0x15000 0x15150>,
+ <0x17000 0x17150>,
+ <0x25000 0x25150>,
+ <0x35000 0x35150>,
+ <0x45000 0x452bc>,
+ <0x46000 0x462bc>,
+ <0x55000 0x5522c>,
+ <0x65000 0x652c0>,
+ <0x66000 0x662c0>,
+ <0x6b800 0x6ba68>,
+ <0x6c000 0x6c268>,
+ <0x71000 0x710d4>,
+ <0x71800 0x718d4>;
+
+ qcom,regs-dump-names-mdp = "MDP",
+ "CTL_0", "CTL_1", "CTL_2",
+ "VIG0_SSPP", "VIG0",
+ "RGB0_SSPP", "RGB1_SSPP",
+ "DMA0_SSPP",
+ "CURSOR0_SSPP",
+ "LAYER_0", "LAYER_1",
+ "DSPP_0",
+ "WB_0", "WB_2",
+ "INTF_1", "INTF_2",
+ "PP_0", "PP_1";
+
+ /* buffer parameters to calculate prefill bandwidth */
+ qcom,mdss-prefill-outstanding-buffer-bytes = <0>;
+ qcom,mdss-prefill-y-buffer-bytes = <0>;
+ qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>;
+ qcom,mdss-prefill-scaler-buffer-lines-caf = <4>;
+ qcom,mdss-prefill-post-scaler-buffer-pixels = <2048>;
+ qcom,mdss-prefill-pingpong-buffer-pixels = <4096>;
+
+ qcom,mdss-pp-offsets {
+ qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>;
+ qcom,mdss-sspp-vig-pcc-off = <0x1780>;
+ qcom,mdss-sspp-rgb-pcc-off = <0x380>;
+ qcom,mdss-sspp-dma-pcc-off = <0x380>;
+ qcom,mdss-lm-pgc-off = <0x3C0>;
+ qcom,mdss-dspp-pcc-off = <0x1700>;
+ qcom,mdss-dspp-pgc-off = <0x17C0>;
+ };
+
+ qcom,mdss-reg-bus {
+ /* Reg Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 160000>,
+ <1 590 0 320000>;
+ };
+
+ qcom,mdss-hw-rt-bus {
+ /* Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_hw_rt";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>,
+ <22 512 0 1000>;
+ };
+
+ smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb {
+ compatible = "qcom,smmu_mdp_unsec";
+ iommus = <&apps_iommu 0x2800 0>; /* For NS ctx bank */
+ qcom,iommu-dma-addr-pool = <0x08000000 0xF8000000>;
+ qcom,iommu-earlymap; /* for cont-splash */
+
+ };
+
+ smmu_mdp_sec: qcom,smmu_mdp_sec_cb {
+ compatible = "qcom,smmu_mdp_sec";
+ iommus = <&apps_iommu 0x2801 0>; /* For SEC Ctx Bank */
+ qcom,iommu-dma-addr-pool = <0x08000000 0xF8000000>;
+ qcom,secure-context-bank;
+ qcom,iommu-vmid = <0x11>; /*VMID_CP_SEC_DISPLAY*/
+ };
+
+ mdss_fb0: qcom,mdss_fb_primary {
+ cell-index = <0>;
+ compatible = "qcom,mdss-fb";
+ qcom,cont-splash-memory {
+ linux,contiguous-region = <&cont_splash_mem>;
+ };
+ };
+
+ mdss_fb1: qcom,mdss_fb_wfd {
+ cell-index = <1>;
+ compatible = "qcom,mdss-fb";
+ };
+
+ mdss_fb2: qcom,mdss_fb_secondary {
+ cell-index = <2>;
+ compatible = "qcom,mdss-fb";
+ };
+ };
+
+ mdss_dsi: qcom,mdss_dsi@0 {
+ compatible = "qcom,mdss-dsi";
+ hw-config = "single_dsi";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ gdsc-supply = <&gdsc_mdss>;
+ vdda-supply = <&pm8937_l2>;
+ vddio-supply = <&pm8937_l6>;
+
+ /* Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_dsi";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>,
+ <22 512 0 1000>;
+
+ ranges = <0x1a94000 0x1a94000 0x300
+ 0x1a94400 0x1a94400 0x280
+ 0x1a94b80 0x1a94b80 0x30
+ 0x193e000 0x193e000 0x30
+ 0x1a96000 0x1a96000 0x300
+ 0x1a96400 0x1a96400 0x280
+ 0x1a96b80 0x1a96b80 0x30
+ 0x193e000 0x193e000 0x30>;
+
+ clocks = <&gcc_mdss MDSS_MDP_VOTE_CLK>,
+ <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
+ <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>,
+ <&mdss_dsi0_pll PCLK_SRC_0_CLK>,
+ <&mdss_dsi1_pll PCLK_SRC_1_CLK>;
+
+ clock-names = "mdp_core_clk", "iface_clk", "bus_clk",
+ "ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk",
+ "ext_pixel1_clk";
+
+ qcom,mmss-ulp-clamp-ctrl-offset = <0x20>;
+ qcom,mmss-phyreset-ctrl-offset = <0x24>;
+
+ qcom,mdss-fb-map-prim = <&mdss_fb0>;
+ qcom,mdss-fb-map-sec = <&mdss_fb2>;
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda";
+ qcom,supply-min-voltage = <1200000>;
+ qcom,supply-max-voltage = <1200000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+ };
+
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+ };
+
+ mdss_dsi0: qcom,mdss_dsi_ctrl0@1a94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ label = "MDSS DSI CTRL->0";
+ cell-index = <0>;
+ reg = <0x1a94000 0x300>,
+ <0x1a94400 0x280>,
+ <0x1a94b80 0x30>,
+ <0x193e000 0x30>;
+ reg-names = "dsi_ctrl", "dsi_phy",
+ "dsi_phy_regulator", "mmss_misc_phys";
+
+ qcom,timing-db-mode;
+ qcom,mdss-mdp = <&mdss_mdp>;
+ vdd-supply = <&pm8937_l17>;
+ vddio-supply = <&pm8937_l6>;
+
+ clocks = <&gcc_mdss GCC_MDSS_BYTE0_CLK>,
+ <&gcc_mdss GCC_MDSS_PCLK0_CLK>,
+ <&gcc GCC_MDSS_ESC0_CLK>,
+ <&gcc_mdss BYTE0_CLK_SRC>,
+ <&gcc_mdss PCLK0_CLK_SRC>;
+ clock-names = "byte_clk", "pixel_clk", "core_clk",
+ "byte_clk_rcg", "pixel_clk_rcg";
+
+ qcom,platform-strength-ctrl = [ff 06];
+ qcom,platform-bist-ctrl = [00 00 b1 ff 00 00];
+ qcom,platform-regulator-settings = [03 08 07 00
+ 20 07 01];
+ qcom,platform-lane-config = [01 c0 00 00 00 00 00 01 97
+ 01 c0 00 00 05 00 00 01 97
+ 01 c0 00 00 0a 00 00 01 97
+ 01 c0 00 00 0f 00 00 01 97
+ 00 40 00 00 00 00 00 01 ff];
+ };
+
+ mdss_dsi1: qcom,mdss_dsi_ctrl1@1a96000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ label = "MDSS DSI CTRL->1";
+ cell-index = <1>;
+ reg = <0x1a96000 0x300>,
+ <0x1a96400 0x280>,
+ <0x1a94b80 0x30>,
+ <0x193e000 0x30>;
+ reg-names = "dsi_ctrl", "dsi_phy",
+ "dsi_phy_regulator", "mmss_misc_phys";
+
+ qcom,mdss-mdp = <&mdss_mdp>;
+ vdd-supply = <&pm8937_l17>;
+ vddio-supply = <&pm8937_l6>;
+
+ clocks = <&gcc_mdss GCC_MDSS_BYTE1_CLK>,
+ <&gcc_mdss GCC_MDSS_PCLK1_CLK>,
+ <&gcc GCC_MDSS_ESC1_CLK>,
+ <&gcc_mdss BYTE1_CLK_SRC>,
+ <&gcc_mdss PCLK1_CLK_SRC>;
+ clock-names = "byte_clk", "pixel_clk", "core_clk",
+ "byte_clk_rcg", "pixel_clk_rcg";
+
+ qcom,platform-strength-ctrl = [ff 06];
+ qcom,platform-bist-ctrl = [00 00 b1 ff 00 00];
+ qcom,platform-regulator-settings = [03 08 07 00
+ 20 07 01];
+ qcom,platform-lane-config = [01 c0 00 00 00 00 00 01 97
+ 01 c0 00 00 05 00 00 01 97
+ 01 c0 00 00 0a 00 00 01 97
+ 01 c0 00 00 0f 00 00 01 97
+ 00 40 00 00 00 00 00 01 ff];
+
+ };
+
+ };
+
+ qcom,mdss_wb_panel {
+ compatible = "qcom,mdss_wb";
+ qcom,mdss_pan_res = <640 640>;
+ qcom,mdss_pan_bpp = <24>;
+ qcom,mdss-fb-map = <&mdss_fb1>;
+ };
+
+ mdss_rotator: qcom,mdss_rotator {
+ compatible = "qcom,mdss_rotator";
+ qcom,mdss-wb-count = <1>;
+ qcom,mdss-has-downscale;
+ qcom,mdss-has-ubwc;
+ /* Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_rotator";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>,
+ <22 512 0 6400000>,
+ <22 512 0 6400000>;
+
+ rot-vdd-supply = <&gdsc_mdss>;
+ qcom,supply-names = "rot-vdd";
+ qcom,mdss-has-reg-bus;
+ clocks = <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc_mdss MDSS_ROTATOR_VOTE_CLK>;
+ clock-names = "iface_clk", "rot_core_clk";
+
+ qcom,mdss-rot-reg-bus {
+ /* Reg Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_rot_reg";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-pinctrl.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-pinctrl.dtsi
new file mode 100755
index 0000000..4e7db8e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-pinctrl.dtsi
@@ -0,0 +1,2026 @@
+&soc {
+ tlmm: pinctrl@1000000 {
+ compatible = "qcom,msm8937-pinctrl";
+ reg = <0x1000000 0x300000>;
+ reg-names = "pinctrl_regs";
+ interrupts-extended = <&wakegic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ wakeup-parent = <&wakegpio>;
+ #interrupt-cells = <2>;
+ irqdomain-map = <38 0 &wakegpio 3 0>,
+ <1 0 &wakegpio 4 0>,
+ <5 0 &wakegpio 5 0>,
+ <9 0 &wakegpio 6 0>,
+ <37 0 &wakegpio 8 0>,
+ <36 0 &wakegpio 9 0>,
+ <13 0 &wakegpio 10 0>,
+ <35 0 &wakegpio 11 0>,
+ <17 0 &wakegpio 12 0>,
+ <21 0 &wakegpio 13 0>,
+ <54 0 &wakegpio 14 0>,
+ <34 0 &wakegpio 15 0>,
+ <31 0 &wakegpio 16 0>,
+ <58 0 &wakegpio 17 0>,
+ <28 0 &wakegpio 18 0>,
+ <42 0 &wakegpio 19 0>,
+ <25 0 &wakegpio 20 0>,
+ <12 0 &wakegpio 21 0>,
+ <43 0 &wakegpio 22 0>,
+ <44 0 &wakegpio 23 0>,
+ <45 0 &wakegpio 24 0>,
+ <46 0 &wakegpio 25 0>,
+ <48 0 &wakegpio 26 0>,
+ <65 0 &wakegpio 27 0>,
+ <93 0 &wakegpio 28 0>,
+ <97 0 &wakegpio 29 0>,
+ <63 0 &wakegpio 30 0>,
+ <70 0 &wakegpio 31 0>,
+ <71 0 &wakegpio 32 0>,
+ <72 0 &wakegpio 33 0>,
+ <81 0 &wakegpio 34 0>,
+ <126 0 &wakegpio 35 0>,
+ <90 0 &wakegpio 36 0>,
+ <128 0 &wakegpio 37 0>,
+ <91 0 &wakegpio 38 0>,
+ <41 0 &wakegpio 39 0>,
+ <127 0 &wakegpio 40 0>,
+ <86 0 &wakegpio 41 0>,
+ <67 0 &wakegpio 50 0>,
+ <73 0 &wakegpio 51 0>,
+ <74 0 &wakegpio 52 0>,
+ <62 0 &wakegpio 53 0>,
+ <124 0 &wakegpio 54 0>,
+ <61 0 &wakegpio 55 0>,
+ <130 0 &wakegpio 56 0>,
+ <59 0 &wakegpio 57 0>,
+ <50 0 &wakegpio 59 0>;
+ irqdomain-map-pass-thru = <0 0xff>;
+ irqdomain-map-mask = <0xff 0>;
+
+ pmx-uartconsole {
+ uart_console_active: uart_console_active {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ uart_console_sleep: uart_console_sleep {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ };
+
+ i2c_2 {
+ i2c_2_active: i2c_2_active {
+ /* active state */
+ mux {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+ };
+
+ config {
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_2_sleep: i2c_2_sleep {
+ /* suspended state */
+ mux {
+ pins = "gpio6", "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ i2c_3 {
+ i2c_3_active: i2c_3_active {
+ /* active state */
+ mux {
+ pins = "gpio10", "gpio11";
+ function = "blsp_i2c3";
+ };
+
+ config {
+ pins = "gpio10", "gpio11";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_3_sleep: i2c_3_sleep {
+ /* suspended state */
+ mux {
+ pins = "gpio10", "gpio11";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio10", "gpio11";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ i2c_4 {
+ i2c_4_active: i2c_4_active {
+ /* active state */
+ mux {
+ pins = "gpio14", "gpio15";
+ function = "blsp_i2c4";
+ };
+
+ config {
+ pins = "gpio14", "gpio15";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_4_sleep: i2c_4_sleep {
+ /* suspended state */
+ mux {
+ pins = "gpio14", "gpio15";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio14", "gpio15";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ i2c_5 {
+ i2c_5_active: i2c_5_active {
+ /* active state */
+ mux {
+ pins = "gpio18", "gpio19";
+ function = "blsp_i2c5";
+ };
+
+ config {
+ pins = "gpio18", "gpio19";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_5_sleep: i2c_5_sleep {
+ /* suspended state */
+ mux {
+ pins = "gpio18", "gpio19";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio18", "gpio19";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ nfc {
+ nfc_int_active: nfc_int_active {
+ /* active state */
+ mux {
+ /* GPIO 17 NFC Read Interrupt */
+ pins = "gpio17";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_int_suspend: nfc_int_suspend {
+ /* sleep state */
+ mux {
+ /* GPIO 17 NFC Read Interrupt */
+ pins = "gpio17";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_disable_active: nfc_disable_active {
+ /* active state */
+ mux {
+ /* 16: NFC ENABLE 130: FW DNLD */
+ /* 93: ESE Enable */
+ pins = "gpio16", "gpio130", "gpio93";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio16", "gpio130", "gpio93";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_disable_suspend: nfc_disable_suspend {
+ /* sleep state */
+ mux {
+ /* 16: NFC ENABLE 130: FW DNLD */
+ /* 93: ESE Enable */
+ pins = "gpio16", "gpio130", "gpio93";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio16", "gpio130", "gpio93";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable;
+ };
+ };
+ };
+
+ tlmm_pmi_flash_led {
+ rear_flash_led_enable: rear_flash_led_enable {
+ mux {
+ pins = "gpio33";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio33";
+ drive-strength = <16>;
+ output-high;
+ };
+ };
+
+ rear_flash_led_disable: rear_flash_led_disable {
+ mux {
+ pins = "gpio33";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio33";
+ drive-strength = <2>;
+ output-low;
+ };
+ };
+
+ front_flash_led_enable: front_flash_led_enable {
+ mux {
+ pins = "gpio50";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio50";
+ drive-strength = <16>;
+ output-high;
+ };
+ };
+
+ front_flash_led_disable: front_flash_led_disable {
+ mux {
+ pins = "gpio50";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio50";
+ drive-strength = <2>;
+ output-low;
+ };
+ };
+ };
+
+ spi3 {
+ spi3_default: spi3_default {
+ /* active state */
+ mux {
+ /* MOSI, MISO, CLK */
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "blsp_spi3";
+ };
+
+ config {
+ pins = "gpio8", "gpio9", "gpio11";
+ drive-strength = <12>; /* 12 MA */
+ bias-disable = <0>; /* No PULL */
+ };
+ };
+
+ spi3_sleep: spi3_sleep {
+ /* suspended state */
+ mux {
+ /* MOSI, MISO, CLK */
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8", "gpio9", "gpio11";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-down; /* PULL Down */
+ };
+ };
+
+ spi3_cs0_active: cs0_active {
+ /* CS */
+ mux {
+ pins = "gpio10";
+ function = "blsp_spi3";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+ };
+
+ spi3_cs0_sleep: cs0_sleep {
+ /* CS */
+ mux {
+ pins = "gpio10";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+ };
+ };
+
+ spi6 {
+ spi6_default: spi6_default {
+ /* active state */
+ mux {
+ /* MOSI, MISO, CLK */
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "blsp_spi6";
+ };
+
+ config {
+ pins = "gpio20", "gpio21", "gpio23";
+ drive-strength = <12>; /* 12 MA */
+ bias-disable = <0>; /* No PULL */
+ };
+ };
+
+ spi6_sleep: spi6_sleep {
+ /* suspended state */
+ mux {
+ /* MOSI, MISO, CLK */
+ pins = "gpio20", "gpio21", "gpio23";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio20", "gpio21", "gpio23";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-down; /* PULL Down */
+ };
+ };
+
+ spi6_cs0_active: cs0_active {
+ /* CS */
+ mux {
+ pins = "gpio22";
+ function = "blsp_spi6";
+ };
+
+ config {
+ pins = "gpio22";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+ };
+
+ spi6_cs0_sleep: cs0_sleep {
+ /* CS */
+ mux {
+ pins = "gpio22";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio22";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+ };
+ };
+
+ blsp2_uart2_active: blsp2_uart2_active {
+ mux {
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ function = "blsp_uart6";
+ };
+
+ config {
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp2_uart2_sleep: blsp2_uart2_sleep {
+ mux {
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ spi7 {
+ spi7_default: spi7_default {
+ mux {
+ pins = "gpio85", "gpio86", "gpio88";
+ function = "blsp_spi7";
+ };
+
+ config {
+ pins = "gpio85", "gpio86", "gpio88";
+ drive-strength = <16>;
+ bias-disable = <0>;
+ };
+ };
+
+ spi7_sleep: spi7_sleep {
+ mux {
+ pins = "gpio85", "gpio86", "gpio88";
+ function = "blsp_spi7";
+ };
+
+ config {
+ pins = "gpio85", "gpio86", "gpio88";
+ drive-strength = <16>;
+ bias-disable = <0>;
+ };
+ };
+
+ spi7_cs0_active: cs0_active {
+ mux {
+ pins = "gpio87";
+ function = "blsp_spi7_cs0";
+ };
+
+ config {
+ pins = "gpio87";
+ drive-strength = <2>;
+ bias-disable = <0>;
+ };
+ };
+ };
+
+ fpc_reset_int {
+ fpc_reset_low: reset_low {
+ mux {
+ pins = "gpio124";
+ function = "fpc_reset_gpio_low";
+ };
+
+ config {
+ pins = "gpio124";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ fpc_reset_high: reset_high {
+ mux {
+ pins = "gpio124";
+ function = "fpc_reset_gpio_high";
+ };
+
+ config {
+ pins = "gpio124";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ fpc_int_low: int_low {
+ mux {
+ pins = "gpio48";
+ };
+
+ config {
+ pins = "gpio48";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+ };
+ };
+
+ wcnss_pmux_5wire {
+ /* Active configuration of bus pins */
+ wcnss_default: wcnss_default {
+ wcss_wlan2 {
+ pins = "gpio76";
+ function = "wcss_wlan2";
+ };
+
+ wcss_wlan1 {
+ pins = "gpio77";
+ function = "wcss_wlan1";
+ };
+
+ wcss_wlan0 {
+ pins = "gpio78";
+ function = "wcss_wlan0";
+ };
+
+ wcss_wlan {
+ pins = "gpio79", "gpio80";
+ function = "wcss_wlan";
+ };
+
+ config {
+ pins = "gpio76", "gpio77",
+ "gpio78", "gpio79",
+ "gpio80";
+ drive-strength = <6>; /* 6 MA */
+ bias-pull-up; /* PULL UP */
+ };
+ };
+
+ wcnss_sleep: wcnss_sleep {
+ wcss_wlan2 {
+ pins = "gpio76";
+ function = "wcss_wlan2";
+ };
+
+ wcss_wlan1 {
+ pins = "gpio77";
+ function = "wcss_wlan1";
+ };
+
+ wcss_wlan0 {
+ pins = "gpio78";
+ function = "wcss_wlan0";
+ };
+
+ wcss_wlan {
+ pins = "gpio79", "gpio80";
+ function = "wcss_wlan";
+ };
+
+ config {
+ pins = "gpio76", "gpio77",
+ "gpio78", "gpio79",
+ "gpio80";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-down; /* PULL Down */
+ };
+ };
+ };
+
+ wcnss_pmux_gpio: wcnss_pmux_gpio {
+ wcnss_gpio_default: wcnss_gpio_default {
+ /* Active configuration of bus pins */
+ mux {
+ /* Uses general purpose pins */
+ pins = "gpio76", "gpio77",
+ "gpio78", "gpio79",
+ "gpio80";
+ function = "gpio";
+
+ };
+
+ config {
+ pins = "gpio76", "gpio77",
+ "gpio78", "gpio79",
+ "gpio80";
+ drive-strength = <6>; /* 6 MA */
+ bias-pull-up; /* PULL UP */
+ };
+ };
+ };
+
+ pmx_quat_mi2s {
+ label = "quat_mi2s";
+ quat_mi2s_active: quat_mi2s_active {
+ mux {
+ pins = "gpio94", "gpio95";
+ function = "sec_mi2s";
+ };
+
+ configs {
+ pins = "gpio94", "gpio95";
+ drive-strength = <8>; /* 8 MA */
+ bias-disable; /* No PULL */
+ };
+ };
+
+ quat_mi2s_sleep: quat_mi2s_sleep {
+ mux {
+ pins = "gpio94", "gpio95";
+ function = "sec_mi2s";
+ };
+
+ configs {
+ pins = "gpio94", "gpio95";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+ };
+
+ pmx_quat_mi2s_din {
+ label = "quat_mi2s_din";
+ quat_mi2s_din_active: quat_mi2s_din_active {
+ mux {
+ pins = "gpio12", "gpio13";
+ function = "sec_mi2s";
+ };
+
+ configs {
+ pins = "gpio12", "gpio13";
+ drive-strength = <8>; /* 8 MA */
+ bias-disable; /* No PULL */
+ output-high;
+ };
+ };
+
+ quat_mi2s_din_sleep: quat_mi2s_din_sleep {
+ mux {
+ pins = "gpio12", "gpio13";
+ function = "sec_mi2s";
+ };
+
+ configs {
+ pins = "gpio12", "gpio13";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+ };
+
+ cdc_mclk2_pin {
+ cdc_mclk2_sleep: cdc_mclk2_sleep {
+ mux {
+ pins = "gpio66";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio66";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ };
+ };
+
+ cdc_mclk2_active: cdc_mclk2_active {
+ mux {
+ pins = "gpio66";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio66";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ };
+ };
+ };
+
+ blsp2_uart1_active: blsp2_uart1_active {
+ mux {
+ pins = "gpio16", "gpio17", "gpio18", "gpio19";
+ function = "blsp_uart5";
+ };
+
+ config {
+ pins = "gpio16", "gpio17", "gpio18", "gpio19";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp2_uart1_sleep: blsp2_uart1_sleep {
+ mux {
+ pins = "gpio16", "gpio17", "gpio18", "gpio19";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio16", "gpio17", "gpio18", "gpio19";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ pmx_adv7533_int: pmx_adv7533_int {
+ adv7533_int_active: adv7533_int_active {
+ mux {
+ pins = "gpio126";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio126";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ adv7533_int_suspend: adv7533_int_suspend {
+ mux {
+ pins = "gpio126";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio126";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ };
+
+ pmx_mdss: pmx_mdss {
+ mdss_dsi_active: mdss_dsi_active {
+ mux {
+ pins = "gpio60", "gpio98", "gpio99";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio60", "gpio98", "gpio99";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable = <0>; /* no pull */
+ output-high;
+ };
+ };
+
+ mdss_dsi_suspend: mdss_dsi_suspend {
+ mux {
+ pins = "gpio60", "gpio98", "gpio99";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio60", "gpio98", "gpio99";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* pull down */
+ input-enable;
+ };
+ };
+ };
+
+ pmx_mdss_te {
+ mdss_te_active: mdss_te_active {
+ mux {
+ pins = "gpio24";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio24";
+ drive-strength = <2>; /* 8 mA */
+ bias-pull-down; /* pull down*/
+ };
+ };
+
+ mdss_te_suspend: mdss_te_suspend {
+ mux {
+ pins = "gpio24";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio24";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* pull down */
+ };
+ };
+ };
+
+ usbc_int_default: usbc_int_default {
+ mux {
+ pins = "gpio97", "gpio131";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio97", "gpio131";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ tlmm_gpio_key {
+ gpio_key_active: gpio_key_active {
+ mux {
+ pins = "gpio91", "gpio127", "gpio128";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio91", "gpio127", "gpio128";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ gpio_key_suspend: gpio_key_suspend {
+ mux {
+ pins = "gpio91", "gpio127", "gpio128";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio91", "gpio127", "gpio128";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ /* add pingrp for touchscreen */
+ pmx_ts_int_active {
+ ts_int_active: ts_int_active {
+ mux {
+ pins = "gpio65";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio65";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_int_suspend {
+ ts_int_suspend: ts_int_suspend {
+ mux {
+ pins = "gpio65";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio65";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_reset_active {
+ ts_reset_active: ts_reset_active {
+ mux {
+ pins = "gpio64";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio64";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_reset_suspend {
+ ts_reset_suspend: ts_reset_suspend {
+ mux {
+ pins = "gpio64";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio64";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_release {
+ ts_release: ts_release {
+ mux {
+ pins = "gpio65", "gpio64";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio65", "gpio64";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_qdsd_clk {
+ qdsd_clk_sdcard: clk_sdcard {
+ config {
+ pins = "qdsd_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ qdsd_clk_trace: clk_trace {
+ config {
+ pins = "qdsd_clk";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_clk_swdtrc: clk_swdtrc {
+ config {
+ pins = "qdsd_clk";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_clk_spmi: clk_spmi {
+ config {
+ pins = "qdsd_clk";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ pmx_qdsd_cmd {
+ qdsd_cmd_sdcard: cmd_sdcard {
+ config {
+ pins = "qdsd_cmd";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_cmd_trace: cmd_trace {
+ config {
+ pins = "qdsd_cmd";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_cmd_swduart: cmd_uart {
+ config {
+ pins = "qdsd_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_cmd_swdtrc: cmd_swdtrc {
+ config {
+ pins = "qdsd_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_cmd_jtag: cmd_jtag {
+ config {
+ pins = "qdsd_cmd";
+ bias-disable; /* NO pull */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_cmd_spmi: cmd_spmi {
+ config {
+ pins = "qdsd_cmd";
+ bias-pull-down; /* pull down */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+ };
+
+ pmx_qdsd_data0 {
+ qdsd_data0_sdcard: data0_sdcard {
+ config {
+ pins = "qdsd_data0";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data0_trace: data0_trace {
+ config {
+ pins = "qdsd_data0";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data0_swduart: data0_uart {
+ config {
+ pins = "qdsd_data0";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data0_swdtrc: data0_swdtrc {
+ config {
+ pins = "qdsd_data0";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data0_jtag: data0_jtag {
+ config {
+ pins = "qdsd_data0";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data0_spmi: data0_spmi {
+ config {
+ pins = "qdsd_data0";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ pmx_qdsd_data1 {
+ qdsd_data1_sdcard: data1_sdcard {
+ config {
+ pins = "qdsd_data1";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data1_trace: data1_trace {
+ config {
+ pins = "qdsd_data1";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data1_swduart: data1_uart {
+ config {
+ pins = "qdsd_data1";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data1_swdtrc: data1_swdtrc {
+ config {
+ pins = "qdsd_data1";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data1_jtag: data1_jtag {
+ config {
+ pins = "qdsd_data1";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ pmx_qdsd_data2 {
+ qdsd_data2_sdcard: data2_sdcard {
+ config {
+ pins = "qdsd_data2";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data2_trace: data2_trace {
+ config {
+ pins = "qdsd_data2";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data2_swduart: data2_uart {
+ config {
+ pins = "qdsd_data2";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data2_swdtrc: data2_swdtrc {
+ config {
+ pins = "qdsd_data2";
+ bias-pull-down; /* pull down */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data2_jtag: data2_jtag {
+ config {
+ pins = "qdsd_data2";
+ bias-pull-up; /* pull up */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+ };
+
+ pmx_qdsd_data3 {
+ qdsd_data3_sdcard: data3_sdcard {
+ config {
+ pins = "qdsd_data3";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data3_trace: data3_trace {
+ config {
+ pins = "qdsd_data3";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+
+ qdsd_data3_swduart: data3_uart {
+ config {
+ pins = "qdsd_data3";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data3_swdtrc: data3_swdtrc {
+ config {
+ pins = "qdsd_data3";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data3_jtag: data3_jtag {
+ config {
+ pins = "qdsd_data3";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ qdsd_data3_spmi: data3_spmi {
+ config {
+ pins = "qdsd_data3";
+ bias-pull-down; /* pull down */
+ drive-strength = <8>; /* 8 MA */
+ };
+ };
+ };
+
+ pmx_sdc1_rclk {
+ sdc1_rclk_on: sdc1_rclk_on {
+ config {
+ pins = "sdc1_rclk";
+ bias-pull-down; /* pull down */
+ };
+ };
+
+ sdc1_rclk_off: sdc1_rclk_off {
+ config {
+ pins = "sdc1_rclk";
+ bias-pull-down; /* pull down */
+ };
+ };
+ };
+
+ wcd9xxx_intr {
+ wcd_intr_default: wcd_intr_default {
+ mux {
+ pins = "gpio73";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio73";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* pull down */
+ input-enable;
+ };
+ };
+ };
+
+ cdc_reset_ctrl {
+ cdc_reset_sleep: cdc_reset_sleep {
+ mux {
+ pins = "gpio68";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio68";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_reset_active:cdc_reset_active {
+ mux {
+ pins = "gpio68";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio68";
+ drive-strength = <16>;
+ bias-pull-down;
+ output-high;
+ };
+ };
+ };
+
+ cdc-pdm-2-lines {
+ cdc_pdm_lines_2_act: pdm_lines_2_on {
+ mux {
+ pins = "gpio70", "gpio71", "gpio72";
+ function = "cdc_pdm0";
+ };
+
+ config {
+ pins = "gpio70", "gpio71", "gpio72";
+ drive-strength = <8>;
+ };
+ };
+
+ cdc_pdm_lines_2_sus: pdm_lines_2_off {
+ mux {
+ pins = "gpio70", "gpio71", "gpio72";
+ function = "cdc_pdm0";
+ };
+
+ config {
+ pins = "gpio70", "gpio71", "gpio72";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ cdc-pdm-lines {
+ cdc_pdm_lines_act: pdm_lines_on {
+ mux {
+ pins = "gpio69", "gpio73", "gpio74";
+ function = "cdc_pdm0";
+ };
+
+ config {
+ pins = "gpio69", "gpio73", "gpio74";
+ drive-strength = <8>;
+ };
+ };
+
+ cdc_pdm_lines_sus: pdm_lines_off {
+ mux {
+ pins = "gpio69", "gpio73", "gpio74";
+ function = "cdc_pdm0";
+ };
+
+ config {
+ pins = "gpio69", "gpio73", "gpio74";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ cross-conn-det {
+ cross_conn_det_act: lines_on {
+ mux {
+ pins = "gpio63";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio63";
+ drive-strength = <8>;
+ output-low;
+ bias-pull-down;
+ };
+ };
+
+ cross_conn_det_sus: lines_off {
+ mux {
+ pins = "gpio63";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio63";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ /* WSA VI sense */
+ wsa-vi {
+ wsa_vi_on: wsa_vi_on {
+ mux {
+ pins = "gpio94", "gpio95";
+ function = "wsa_io";
+ };
+
+ config {
+ pins = "gpio94", "gpio95";
+ drive-strength = <8>; /* 8 MA */
+ bias-disable; /* NO pull */
+ };
+ };
+
+ wsa_vi_off: wsa_vi_off {
+ mux {
+ pins = "gpio94", "gpio95";
+ function = "wsa_io";
+ };
+
+ config {
+ pins = "gpio94", "gpio95";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-down;
+ };
+ };
+ };
+
+ /* WSA Reset */
+ wsa_reset {
+ wsa_reset_on: wsa_reset_on {
+ mux {
+ pins = "gpio96";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio96";
+ drive-strength = <2>; /* 2 MA */
+ output-high;
+ };
+ };
+
+ wsa_reset_off: wsa_reset_off {
+ mux {
+ pins = "gpio96";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio96";
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+ };
+
+ /* WSA CLK */
+ wsa_clk {
+ wsa_clk_on: wsa_clk_on {
+ mux {
+ pins = "gpio25";
+ function = "pri_mi2s_mclk_a";
+ };
+
+ config {
+ pins = "gpio25";
+ drive-strength = <8>; /* 8 MA */
+ output-high;
+ };
+ };
+
+ wsa_clk_off: wsa_clk_off {
+ mux {
+ pins = "gpio25";
+ function = "pri_mi2s_mclk_a";
+ };
+
+ config {
+ pins = "gpio25";
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pri-tlmm-lines {
+ pri_tlmm_lines_act: pri_tlmm_lines_act {
+ mux {
+ pins = "gpio85", "gpio88";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio85", "gpio88";
+ drive-strength = <8>;
+ };
+ };
+
+ pri_tlmm_lines_sus: pri_tlmm_lines_sus {
+ mux {
+ pins = "gpio85", "gpio88";
+ function = "pri_mi2s";
+ };
+
+ config {
+ pins = "gpio85", "gpio88";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pri-tlmm-ws-lines {
+ pri_tlmm_ws_act: pri_tlmm_ws_act {
+ mux {
+ pins = "gpio87";
+ function = "pri_mi2s_ws";
+ };
+
+ config {
+ pins = "gpio87";
+ drive-strength = <8>;
+ };
+ };
+
+ pri_tlmm_ws_sus: pri_tlmm_ws_sus {
+ mux {
+ pins = "gpio87";
+ function = "pri_mi2s_ws";
+ };
+
+ config {
+ pins = "gpio87";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_sdc1_clk {
+ sdc1_clk_on: sdc1_clk_on {
+ config {
+ pins = "sdc1_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc1_clk_off: sdc1_clk_off {
+ config {
+ pins = "sdc1_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ pmx_sdc1_cmd {
+ sdc1_cmd_on: sdc1_cmd_on {
+ config {
+ pins = "sdc1_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc1_cmd_off: sdc1_cmd_off {
+ config {
+ pins = "sdc1_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ pmx_sdc1_data {
+ sdc1_data_on: sdc1_data_on {
+ config {
+ pins = "sdc1_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc1_data_off: sdc1_data_off {
+ config {
+ pins = "sdc1_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ sdhc2_cd_pin {
+ sdc2_cd_on: cd_on {
+ mux {
+ pins = "gpio67";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio67";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_cd_off: cd_off {
+ mux {
+ pins = "gpio67";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio67";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ pmx_sdc2_clk {
+ sdc2_clk_on: sdc2_clk_on {
+ config {
+ pins = "sdc2_clk";
+ drive-strength = <16>; /* 16 MA */
+ bias-disable; /* NO pull */
+ };
+ };
+
+ sdc2_clk_off: sdc2_clk_off {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ pmx_sdc2_cmd {
+ sdc2_cmd_on: sdc2_cmd_on {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_cmd_off: sdc2_cmd_off {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ pmx_sdc2_data {
+ sdc2_data_on: sdc2_data_on {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_data_off: sdc2_data_off {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+
+ cci {
+ cci0_active: cci0_active {
+ /* cci0 active state */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio29", "gpio30";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio29", "gpio30";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable; /* No PULL */
+ };
+ };
+
+ cci0_suspend: cci0_suspend {
+ /* cci0 suspended state */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio29", "gpio30";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio29", "gpio30";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable; /* No PULL */
+ };
+ };
+
+ cci1_active: cci1_active {
+ /* cci1 active state */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio31", "gpio32";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio31", "gpio32";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable; /* No PULL */
+ };
+ };
+
+ cci1_suspend: cci1_suspend {
+ /* cci1 suspended state */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio31", "gpio32";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio31", "gpio32";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable; /* No PULL */
+ };
+ };
+ };
+
+ cdc-dmic-lines {
+ cdc_dmic0_clk_act: dmic0_clk_on {
+ mux {
+ pins = "gpio89";
+ function = "dmic0_clk";
+ };
+
+ config {
+ pins = "gpio89";
+ drive-strength = <8>;
+ bias-pull-none;
+ };
+ };
+
+ cdc_dmic0_clk_sus: dmic0_clk_off {
+ mux {
+ pins = "gpio89";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio89";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ cdc_dmic0_data_act: dmic0_data_on {
+ mux {
+ pins = "gpio90";
+ function = "dmic0_data";
+ };
+
+ config {
+ pins = "gpio90";
+ drive-strength = <8>;
+ bias-pull-none;
+ };
+ };
+
+ cdc_dmic0_data_sus: dmic0_data_off {
+ mux {
+ pins = "gpio90";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio90";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+ /*sensors */
+ cam_sensor_mclk0_default: cam_sensor_mclk0_default {
+ /* MCLK0 */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio26";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio26";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk0_sleep: cam_sensor_mclk0_sleep {
+ /* MCLK0 */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio26";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio26";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear_reset: cam_sensor_rear_reset {
+ /* RESET */
+ mux {
+ pins = "gpio36";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio36";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear_reset_sleep: cam_sensor_rear_reset_sleep {
+ /* RESET */
+ mux {
+ pins = "gpio36";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio36";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear_standby: cam_sensor_rear_standby {
+ /* STANDBY */
+ mux {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio35";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear_standby_sleep: cam_sensor_rear_standby_sleep {
+ /* STANDBY */
+ mux {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio35";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear_vdig: cam_sensor_rear_vdig {
+ /* VDIG */
+ mux {
+ pins = "gpio62";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio62";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear_vdig_sleep: cam_sensor_rear_vdig_sleep {
+ /* VDIG */
+ mux {
+ pins = "gpio62";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio62";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear_vana: cam_sensor_rear_vana {
+ /* VANA */
+ mux {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio35";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear_vana_sleep: cam_sensor_rear_vana_sleep {
+ /* VANA */
+ mux {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio35";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk1_default: cam_sensor_mclk1_default {
+ /* MCLK1 */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio27";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio27";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk1_sleep: cam_sensor_mclk1_sleep {
+ /* MCLK1 */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio27";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio27";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_front_default: cam_sensor_front_default {
+ /* RESET, STANDBY */
+ mux {
+ pins = "gpio38","gpio50";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio38","gpio50";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_front_sleep: cam_sensor_front_sleep {
+ /* RESET, STANDBY */
+ mux {
+ pins = "gpio38","gpio50";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio38","gpio50";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk2_default: cam_sensor_mclk2_default {
+ /* MCLK2 */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio28";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio28";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk2_sleep: cam_sensor_mclk2_sleep {
+ /* MCLK2 */
+ mux {
+ /* CLK, DATA */
+ pins = "gpio28";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio28";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_front1_default: cam_sensor_front1_default {
+ /* RESET, STANDBY */
+ mux {
+ pins = "gpio40", "gpio39";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio40", "gpio39";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_front1_sleep: cam_sensor_front1_sleep {
+ /* RESET, STANDBY */
+ mux {
+ pins = "gpio40", "gpio39";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio40", "gpio39";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-pm.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-pm.dtsi
new file mode 100755
index 0000000..0f2d91f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-pm.dtsi
@@ -0,0 +1,242 @@
+#include <dt-bindings/msm/pm.h>
+
+&soc {
+ qcom,spm@b1d2000 {
+ compatible = "qcom,spm-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xb1d2000 0x1000>;
+ qcom,name = "system-cci";
+ qcom,saw2-ver-reg = <0xfd0>;
+ qcom,saw2-cfg = <0x14>;
+ qcom,saw2-spm-dly= <0x3C102800>;
+ qcom,saw2-spm-ctl = <0xe>;
+ qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3
+ &CPU4 &CPU5 &CPU6 &CPU7>;
+ qcom,vctl-timeout-us = <500>;
+ qcom,vctl-port = <0x0>;
+ qcom,phase-port = <0x1>;
+ qcom,pfm-port = <0x2>;
+ };
+
+ qcom,lpm-levels {
+ compatible = "qcom,lpm-levels";
+ qcom,use-psci;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,pm-cluster@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "system";
+ qcom,psci-mode-shift = <8>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cluster-level@0 {
+ reg = <0>;
+ label = "system-active";
+ qcom,psci-mode = <0>;
+ qcom,entry-latency-us = <565>;
+ qcom,exit-latency-us = <415>;
+ qcom,min-residency-us = <980>;
+ };
+
+ qcom,pm-cluster-level@1 {
+ reg = <1>;
+ label = "system-wfi";
+ qcom,psci-mode = <1>;
+ qcom,entry-latency-us = <575>;
+ qcom,exit-latency-us = <475>;
+ qcom,min-residency-us = <3288>;
+ qcom,min-child-idx = <1>;
+ };
+
+ qcom,pm-cluster-level@2 {
+ reg = <2>;
+ label = "system-ret";
+ qcom,psci-mode = <2>;
+ qcom,entry-latency-us = <350>;
+ qcom,exit-latency-us = <900>;
+ qcom,min-residency-us = <6272>;
+ qcom,min-child-idx = <1>;
+ qcom,reset-level = <LPM_RESET_LVL_RET>;
+ };
+
+ qcom,pm-cluster-level@3 {
+ reg = <3>;
+ label = "system-pc";
+ qcom,psci-mode = <3>;
+ qcom,entry-latency-us = <644>;
+ qcom,exit-latency-us = <10782>;
+ qcom,min-residency-us = <7500>;
+ qcom,min-child-idx = <2>;
+ qcom,notify-rpm;
+ qcom,is-reset;
+ qcom,reset-level = <LPM_RESET_LVL_PC>;
+ };
+
+ qcom,pm-cluster@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "perf";
+ qcom,psci-mode-shift = <4>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cluster-level@0 {
+ reg = <0>;
+ label = "perf-l2-wfi";
+ qcom,psci-mode = <1>;
+ qcom,entry-latency-us = <116>;
+ qcom,exit-latency-us = <210>;
+ qcom,min-residency-us = <326>;
+ };
+
+ qcom,pm-cluster-level@1 {
+ reg = <1>;
+ label = "perf-l2-gdhs";
+ qcom,psci-mode = <4>;
+ qcom,entry-latency-us = <360>;
+ qcom,exit-latency-us = <267>;
+ qcom,min-residency-us = <967>;
+ qcom,min-child-idx = <1>;
+ qcom,reset-level = <LPM_RESET_LVL_GDHS>;
+ };
+
+ qcom,pm-cluster-level@2 {
+ reg = <2>;
+ label = "perf-l2-pc";
+ qcom,psci-mode = <5>;
+ qcom,entry-latency-us = <574>;
+ qcom,exit-latency-us = <305>;
+ qcom,min-residency-us = <3118>;
+ qcom,min-child-idx = <1>;
+ qcom,is-reset;
+ qcom,reset-level = <LPM_RESET_LVL_PC>;
+ };
+
+ qcom,pm-cpu {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+ qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ qcom,pm-cpu-level@0 {
+ reg = <0>;
+ qcom,psci-cpu-mode = <0>;
+ label = "wfi";
+ qcom,entry-latency-us = <66>;
+ qcom,exit-latency-us = <1>;
+ qcom,min-residency-us = <67>;
+ };
+
+ qcom,pm-cpu-level@1 {
+ reg = <1>;
+ qcom,psci-cpu-mode = <3>;
+ label = "pc";
+ qcom,entry-latency-us = <136>;
+ qcom,exit-latency-us = <190>;
+ qcom,min-residency-us = <901>;
+ qcom,use-broadcast-timer;
+ qcom,is-reset;
+ qcom,reset-level =
+ <LPM_RESET_LVL_PC>;
+ };
+ };
+ };
+
+ qcom,pm-cluster@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "pwr";
+ qcom,psci-mode-shift = <4>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cluster-level@0 {
+ reg = <0>;
+ label = "pwr-l2-wfi";
+ qcom,psci-mode = <1>;
+ qcom,entry-latency-us = <179>;
+ qcom,exit-latency-us = <221>;
+ qcom,min-residency-us = <400>;
+ };
+
+ qcom,pm-cluster-level@1 {
+ reg = <1>;
+ label = "pwr-l2-gdhs";
+ qcom,psci-mode = <4>;
+ qcom,entry-latency-us = <380>;
+ qcom,exit-latency-us = <337>;
+ qcom,min-residency-us = <981>;
+ qcom,min-child-idx = <1>;
+ qcom,reset-level =
+ <LPM_RESET_LVL_GDHS>;
+ };
+
+ qcom,pm-cluster-level@2 {
+ reg = <2>;
+ label = "pwr-l2-pc";
+ qcom,psci-mode = <5>;
+ qcom,entry-latency-us = <565>;
+ qcom,exit-latency-us = <415>;
+ qcom,min-residency-us = <3561>;
+ qcom,min-child-idx = <1>;
+ qcom,is-reset;
+ qcom,reset-level =
+ <LPM_RESET_LVL_PC>;
+ };
+
+ qcom,pm-cpu {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+ qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>;
+
+ qcom,pm-cpu-level@0 {
+ reg = <0>;
+ qcom,psci-cpu-mode = <0>;
+ label = "wfi";
+ qcom,entry-latency-us = <56>;
+ qcom,exit-latency-us = <1>;
+ qcom,min-residency-us = <57>;
+ };
+
+ qcom,pm-cpu-level@1 {
+ reg = <1>;
+ qcom,psci-cpu-mode = <3>;
+ label = "pc";
+ qcom,entry-latency-us = <179>;
+ qcom,exit-latency-us = <221>;
+ qcom,min-residency-us = <401>;
+ qcom,use-broadcast-timer;
+ qcom,is-reset;
+ qcom,reset-level =
+ <LPM_RESET_LVL_PC>;
+ };
+ };
+ };
+ };
+ };
+
+ qcom,rpm-stats@200000 {
+ compatible = "qcom,rpm-stats";
+ reg = <0x200000 0x1000>,
+ <0x290014 0x4>,
+ <0x29001c 0x4>;
+ reg-names = "phys_addr_base", "offset_addr",
+ "heap_phys_addrbase";
+ qcom,sleep-stats-version = <2>;
+ };
+
+ qcom,rpm-master-stats@60150 {
+ compatible = "qcom,rpm-master-stats";
+ reg = <0x60150 0x5000>;
+ qcom,masters = "APSS", "MPSS", "PRONTO", "TZ", "LPASS";
+ qcom,master-stats-version = <2>;
+ qcom,master-offset = <4096>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-regulator.dtsi
new file mode 100755
index 0000000..c4ab6a5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-regulator.dtsi
@@ -0,0 +1,444 @@
+&rpm_bus {
+ rpm-regulator-smpa1 {
+ status = "okay";
+ pm8937_s1: regulator-s1 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1225000>;
+ qcom,init-voltage = <1000000>;
+ status = "okay";
+ };
+ };
+
+ /* VDD_CX supply */
+ rpm-regulator-smpa2 {
+ status = "okay";
+ pm8937_s2_level: regulator-s2-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_s2_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ pm8937_s2_floor_level: regulator-s2-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_s2_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+
+ pm8937_s2_level_ao: regulator-s2-level-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_s2_level_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ pm8937_cx_cdev: regulator-cx-cdev {
+ compatible = "qcom,regulator-cooling-device";
+ regulator-cdev-supply = <&pm8937_s2_floor_level>;
+ regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NOM_PLUS
+ RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ rpm-regulator-smpa3 {
+ status = "okay";
+ pm8937_s3: regulator-s3 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,init-voltage = <1300000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpa4 {
+ status = "okay";
+ pm8937_s4: regulator-s4 {
+ regulator-min-microvolt = <2050000>;
+ regulator-max-microvolt = <2050000>;
+ qcom,init-voltage = <2050000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa2 {
+ status = "okay";
+ pm8937_l2: regulator-l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ qcom,init-voltage = <1200000>;
+ status = "okay";
+ };
+ };
+
+ /* VDD_MX supply */
+ rpm-regulator-ldoa3 {
+ status = "okay";
+ pm8937_l3_level_ao: regulator-l3-level-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l3_level_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ qcom,always-send-voltage;
+ };
+
+ pm8937_l3_level_so: regulator-l3-level-so {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l3_level_so";
+ qcom,set = <2>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,init-voltage-level =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ qcom,use-voltage-level;
+ };
+ };
+
+ rpm-regulator-ldoa5 {
+ status = "okay";
+ pm8937_l5: regulator-l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa6 {
+ status = "okay";
+ pm8937_l6: regulator-l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa7 {
+ status = "okay";
+ pm8937_l7: regulator-l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+
+ pm8937_l7_ao: regulator-l7-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l7_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ };
+ };
+
+ rpm-regulator-ldoa8 {
+ status = "okay";
+ pm8937_l8: regulator-l8 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2900000>;
+ qcom,init-voltage = <2900000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa9 {
+ status = "okay";
+ pm8937_l9: regulator-l9 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <3000000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa10 {
+ status = "okay";
+ pm8937_l10: regulator-l10 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <3000000>;
+ qcom,init-voltage = <2800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa11 {
+ status = "okay";
+ pm8937_l11: regulator-l11 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ qcom,init-voltage = <2950000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa12 {
+ status = "okay";
+ pm8937_l12: regulator-l12 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <2950000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa13 {
+ status = "okay";
+ pm8937_l13: regulator-l13 {
+ regulator-min-microvolt = <3075000>;
+ regulator-max-microvolt = <3075000>;
+ qcom,init-voltage = <3075000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa14 {
+ status = "okay";
+ pm8937_l14: regulator-l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa15 {
+ status = "okay";
+ pm8937_l15: regulator-l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa16 {
+ status = "okay";
+ pm8937_l16: regulator-l16 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa17 {
+ status = "okay";
+ pm8937_l17: regulator-l17 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2900000>;
+ qcom,init-voltage = <2800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa19 {
+ status = "okay";
+ pm8937_l19: regulator-l19 {
+ regulator-min-microvolt = <1225000>;
+ regulator-max-microvolt = <1350000>;
+ qcom,init-voltage = <1225000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa22 {
+ status = "okay";
+ pm8937_l22: regulator-l22 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ qcom,init-voltage = <2800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa23 {
+ status = "okay";
+ pm8937_l23: regulator-l23 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ qcom,init-voltage = <1200000>;
+ status = "okay";
+ };
+ };
+};
+
+/* SPM controlled regulators */
+&spmi_bus {
+ qcom,pm8937@1 {
+ /* PM8937 S5 + S6 = VDD_APC supply */
+ pm8937_s5: spm-regulator@2000 {
+ compatible = "qcom,spm-regulator";
+ reg = <0x2000 0x100>;
+ regulator-name = "pm8937_s5";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1350000>;
+ };
+ };
+};
+
+&soc {
+ mem_acc_vreg_corner: regulator@01946004 {
+ compatible = "qcom,mem-acc-regulator";
+ regulator-name = "mem_acc_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <3>;
+
+ qcom,acc-reg-addr-list =
+ <0x01942138 0x01942130 0x01942120
+ 0x01942124 0x01946000 0x01946004>;
+
+ qcom,acc-init-reg-config = <1 0xff>, <2 0x5555>, <6 0x55>;
+
+ qcom,num-acc-corners = <3>;
+ qcom,boot-acc-corner = <2>;
+ qcom,corner1-reg-config =
+ /* SVS+ => SVS+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ /* SVS+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>,
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ /* SVS+ => TURBO/NOM+ */
+ < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>,
+ < 3 0x0>, < 4 0x0>, < 5 0x0>;
+
+ qcom,corner2-reg-config =
+ /* NOM => SVS+ */
+ < 3 0x30c30c3>, < 4 0x30c3>, < 5 0x6060606>,
+ /* NOM => NOM */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ /* NOM => TURBO/NOM+ */
+ < 3 0x0>, < 4 0x0>, < 5 0x0>;
+
+ qcom,corner3-reg-config =
+ /* TURBO/NOM+ => SVS+ */
+ < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>,
+ < 3 0x30c30c3>, < 4 0x30c3>, < 5 0x6060606>,
+ /* TURBO/NOM+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, < 5 0x2020202>,
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ /* TURBO/NOM+ => TURBO/NOM+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>;
+ };
+
+ apc_vreg_corner: regulator@b018000 {
+ compatible = "qcom,cpr-regulator";
+ reg = <0xb018000 0x1000>, <0xb011064 0x4>, <0xa4000 0x1000>;
+ reg-names = "rbcpr", "rbcpr_clk", "efuse_addr";
+ interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+ regulator-name = "apc_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <7>;
+
+ qcom,cpr-fuse-corners = <3>;
+ qcom,cpr-voltage-ceiling = <1155000 1225000 1350000>;
+ qcom,cpr-voltage-floor = <1050000 1050000 1090000>;
+ vdd-apc-supply = <&pm8937_s5>;
+
+ mem-acc-supply = <&mem_acc_vreg_corner>;
+
+ qcom,cpr-ref-clk = <19200>;
+ qcom,cpr-timer-delay = <5000>;
+ qcom,cpr-timer-cons-up = <0>;
+ qcom,cpr-timer-cons-down = <2>;
+ qcom,cpr-irq-line = <0>;
+ qcom,cpr-step-quotient = <10>;
+ qcom,cpr-up-threshold = <2>;
+ qcom,cpr-down-threshold = <4>;
+ qcom,cpr-idle-clocks = <15>;
+ qcom,cpr-gcnt-time = <1>;
+ qcom,vdd-apc-step-up-limit = <1>;
+ qcom,vdd-apc-step-down-limit = <1>;
+ qcom,cpr-apc-volt-step = <5000>;
+
+ qcom,cpr-fuse-row = <67 0>;
+ qcom,cpr-fuse-target-quot = <42 24 6>;
+ qcom,cpr-fuse-ro-sel = <60 57 54>;
+ qcom,cpr-init-voltage-ref = <1155000 1225000 1350000>;
+ qcom,cpr-fuse-init-voltage =
+ <67 36 6 0>,
+ <67 18 6 0>,
+ <67 0 6 0>;
+ qcom,cpr-fuse-quot-offset =
+ <71 26 6 0>,
+ <71 20 6 0>,
+ <70 54 7 0>;
+ qcom,cpr-fuse-quot-offset-scale = <5 5 5>;
+ qcom,cpr-init-voltage-step = <10000>;
+ qcom,cpr-corner-map = <1 2 3 3 3 3 3>;
+ qcom,cpr-corner-frequency-map =
+ <1 960000000>,
+ <2 1094400000>,
+ <3 1209600000>,
+ <4 1248000000>,
+ <5 1344000000>,
+ <6 1401000000>,
+ <7 1497600000>;
+ qcom,speed-bin-fuse-sel = <37 34 3 0>;
+ qcom,cpr-speed-bin-max-corners =
+ <0 0 1 2 6>,
+ <1 0 1 2 7>,
+ <2 0 1 2 3>;
+ qcom,cpr-fuse-revision = <69 39 3 0>;
+ qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>;
+ qcom,cpr-voltage-scaling-factor-max = <0 2000 2000>;
+ qcom,cpr-scaled-init-voltage-as-ceiling;
+ qcom,cpr-fuse-version-map =
+ <0 (-1) 1 (-1) (-1) (-1)>,
+ <(-1) (-1) 2 (-1) (-1) (-1)>,
+ <(-1) (-1) 3 (-1) (-1) (-1)>,
+ <(-1) (-1) (-1) (-1) (-1) (-1)>;
+ qcom,cpr-quotient-adjustment =
+ <(-20) (-40) (-20)>,
+ <0 (-40) (20)>,
+ <0 0 (20)>,
+ <0 0 0>;
+ qcom,cpr-init-voltage-adjustment =
+ <0 0 0>,
+ <(10000) (15000) (20000)>,
+ <0 0 0>,
+ <0 0 0>;
+ qcom,cpr-enable;
+ };
+
+ eldo2_pm8937: eldo2 {
+ compatible = "regulator-fixed";
+ regulator-name = "eldo2_pm8937";
+ startup-delay-us = <0>;
+ enable-active-high;
+ gpio = <&pm8937_gpios 7 0>;
+ regulator-always-on;
+ };
+
+ adv_vreg: adv_vreg {
+ compatible = "regulator-fixed";
+ regulator-name = "adv_vreg";
+ startup-delay-us = <400>;
+ enable-active-high;
+ gpio = <&pm8937_gpios 8 0>;
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-thermal.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-thermal.dtsi
new file mode 100755
index 0000000..d7a05a5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-thermal.dtsi
@@ -0,0 +1,804 @@
+#include <dt-bindings/thermal/thermal.h>
+
+&apsscc {
+ qcom,cpu-isolation {
+ compatible = "qcom,cpu-isolate";
+ cpu0_isolate: cpu0-isolate {
+ qcom,cpu = <&CPU0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1_isolate: cpu1-isolate {
+ qcom,cpu = <&CPU1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2_isolate: cpu2-isolate {
+ qcom,cpu = <&CPU2>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3_isolate: cpu3-isolate {
+ qcom,cpu = <&CPU3>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4_isolate: cpu4-isolate {
+ qcom,cpu = <&CPU4>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5_isolate: cpu5-isolate {
+ qcom,cpu = <&CPU5>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6_isolate: cpu6-isolate {
+ qcom,cpu = <&CPU6>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7_isolate: cpu7-isolate {
+ qcom,cpu = <&CPU7>;
+ #cooling-cells = <2>;
+ };
+ };
+};
+
+&soc {
+ qmi-tmd-devices {
+ compatible = "qcom,qmi-cooling-devices";
+
+ modem {
+ qcom,instance-id = <0x0>;
+
+ modem_pa: modem_pa {
+ qcom,qmi-dev-name = "pa";
+ #cooling-cells = <2>;
+ };
+
+ modem_proc: modem_proc {
+ qcom,qmi-dev-name = "modem";
+ #cooling-cells = <2>;
+ };
+
+ modem_current: modem_current {
+ qcom,qmi-dev-name = "modem_current";
+ #cooling-cells = <2>;
+ };
+
+ modem_vdd: modem_vdd {
+ qcom,qmi-dev-name = "cpuv_restriction_cold";
+ #cooling-cells = <2>;
+ };
+ };
+ };
+};
+
+&thermal_zones {
+ aoss0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 0>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-core-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 1>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ lpass-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 3>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 4>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ apc1-cpu0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 5>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ apc1-cpu1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 6>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ apc1-cpu2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 7>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ apc1-cpu3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 8>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 9>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpu-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 10>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpu-step {
+ polling-delay-passive = <250>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 10>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ gpu_step_trip: gpu-step-trip {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ gpu_cdev0 {
+ trip = <&gpu_step_trip>;
+ cooling-device =
+ <&msm_gpu THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ hexa-cpu-max-step {
+ polling-delay-passive = <50>;
+ polling-delay = <100>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu_trip:cpu-trip {
+ temperature = <85000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_cdev {
+ trip = <&cpu_trip>;
+ cooling-device =
+ <&CPU0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+
+ cpu4_cdev {
+ trip = <&cpu_trip>;
+ cooling-device =
+ <&CPU4 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ apc1-cpu0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 5>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ apc1_cpu0_trip: apc1-cpu0-trip {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_cdev {
+ trip = <&apc1_cpu0_trip>;
+ cooling-device =
+ <&cpu0_isolate 1 1>;
+ };
+ };
+ };
+
+ apc1-cpu1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 6>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ apc1_cpu1_trip: apc1-cpu1-trip {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu1_cdev {
+ trip = <&apc1_cpu1_trip>;
+ cooling-device =
+ <&cpu1_isolate 1 1>;
+ };
+ };
+ };
+
+ apc1-cpu2-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 7>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ apc1_cpu2_trip: apc1-cpu2-trip {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu2_cdev {
+ trip = <&apc1_cpu2_trip>;
+ cooling-device =
+ <&cpu2_isolate 1 1>;
+ };
+ };
+ };
+
+ apc1-cpu3-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 8>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ apc1_cpu3_trip: apc1-cpu3-trip {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu3_cdev {
+ trip = <&apc1_cpu3_trip>;
+ cooling-device =
+ <&cpu3_isolate 1 1>;
+ };
+ };
+ };
+
+ cpuss0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 9>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpuss0_step_trip: cpuss0-step-trip {
+ temperature = <105000>;
+ hysteresis = <15000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu4_cdev {
+ trip = <&cpuss0_step_trip>;
+ cooling-device =
+ <&cpu4_isolate 1 1>;
+ };
+
+ cpu5_cdev {
+ trip = <&cpuss0_step_trip>;
+ cooling-device =
+ <&cpu5_isolate 1 1>;
+ };
+
+ cpu6_cdev {
+ trip = <&cpuss0_step_trip>;
+ cooling-device =
+ <&cpu6_isolate 1 1>;
+ };
+
+ cpu7_cdev {
+ trip = <&cpuss0_step_trip>;
+ cooling-device =
+ <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ aoss0-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 0>;
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ aoss0_trip: aoss-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_vdd_cdev {
+ trip = <&aoss0_trip>;
+ cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2)
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ cx_vdd_cdev {
+ trip = <&aoss0_trip>;
+ cooling-device = <&pm8937_cx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&aoss0_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+ };
+ };
+
+ mdm-core-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 1>;
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ mdm_core_trip: mdm-core-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_vdd_cdev {
+ trip = <&mdm_core_trip>;
+ cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2)
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ cx_vdd_cdev {
+ trip = <&mdm_core_trip>;
+ cooling-device = <&pm8937_cx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&mdm_core_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+ };
+ };
+
+ lpass-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 2>;
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ qdsp_trip: qdsp-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_vdd_cdev {
+ trip = <&qdsp_trip>;
+ cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2)
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ cx_vdd_cdev {
+ trip = <&qdsp_trip>;
+ cooling-device = <&pm8937_cx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&qdsp_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+ };
+ };
+
+ camera-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 3>;
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ camera_trip: camera-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_vdd_cdev {
+ trip = <&camera_trip>;
+ cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2)
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ cx_vdd_cdev {
+ trip = <&camera_trip>;
+ cooling-device = <&pm8937_cx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&camera_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+ };
+ };
+
+ cpuss1-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 4>;
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ cpuss1_trip: cpuss1-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_vdd_cdev {
+ trip = <&cpuss1_trip>;
+ cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2)
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ cx_vdd_cdev {
+ trip = <&cpuss1_trip>;
+ cooling-device = <&pm8937_cx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&cpuss1_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+ };
+ };
+
+ apc1-cpu0-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 5>;
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ cpu0_trip: apc1-cpu0-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_vdd_cdev {
+ trip = <&cpu0_trip>;
+ cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2)
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ cx_vdd_cdev {
+ trip = <&cpu0_trip>;
+ cooling-device = <&pm8937_cx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&cpu0_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+ };
+ };
+
+ apc1-cpu1-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 6>;
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ cpu1_trip: apc1-cpu1-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_vdd_cdev {
+ trip = <&cpu1_trip>;
+ cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2)
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ cx_vdd_cdev {
+ trip = <&cpu1_trip>;
+ cooling-device = <&pm8937_cx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&cpu1_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+ };
+ };
+
+ apc1-cpu2-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 7>;
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ cpu2_trip: apc1-cpu2-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_vdd_cdev {
+ trip = <&cpu2_trip>;
+ cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2)
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ cx_vdd_cdev {
+ trip = <&cpu2_trip>;
+ cooling-device = <&pm8937_cx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&cpu2_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+ };
+ };
+
+ apc1-cpu3-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 8>;
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ cpu3_trip: apc1-cpu3-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_vdd_cdev {
+ trip = <&cpu3_trip>;
+ cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2)
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ cx_vdd_cdev {
+ trip = <&cpu3_trip>;
+ cooling-device = <&pm8937_cx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&cpu3_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+ };
+ };
+
+ cpuss0-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 9>;
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ cpuss0_lowf_trip: cpuss0-lowf-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_vdd_cdev {
+ trip = <&cpuss0_lowf_trip>;
+ cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2)
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ cx_vdd_cdev {
+ trip = <&cpuss0_lowf_trip>;
+ cooling-device = <&pm8937_cx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&cpuss0_lowf_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+ };
+ };
+
+ gpu-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 10>;
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ gpu_lowf_trip: gpu-lowf-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_vdd_cdev {
+ trip = <&gpu_lowf_trip>;
+ cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-2)
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ cx_vdd_cdev {
+ trip = <&gpu_lowf_trip>;
+ cooling-device = <&pm8937_cx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&gpu_lowf_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937-vidc.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937-vidc.dtsi
new file mode 100755
index 0000000..fe387d3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937-vidc.dtsi
@@ -0,0 +1,171 @@
+&soc {
+ qcom,vidc@1d00000 {
+ compatible = "qcom,msm-vidc";
+ reg = <0x01d00000 0xff000>;
+ interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,hfi-version = "3xx";
+ venus-supply = <&gdsc_venus>;
+ venus-core0-supply = <&gdsc_venus_core0>;
+ clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
+ <&gcc GCC_VENUS0_CORE0_VCODEC0_CLK>,
+ <&gcc GCC_VENUS0_AHB_CLK>,
+ <&gcc GCC_VENUS0_AXI_CLK>;
+ clock-names = "core_clk", "core0_clk", "iface_clk", "bus_clk";
+ qcom,clock-configs = <0x1 0x0 0x0 0x0>;
+ qcom,sw-power-collapse;
+ qcom,slave-side-cp;
+ qcom,dcvs-tbl =
+ <108000 108000 244800 0x00000004>, /* Encoder */
+ <108000 108000 244800 0x0f00000c>; /* Decoder */
+ qcom,dcvs-limit =
+ <8160 30>, /* Encoder */
+ <8160 30>; /* Decoder */
+ qcom,hfi = "venus";
+ qcom,reg-presets = <0xe0020 0x05555556>,
+ <0xe0024 0x05555556>,
+ <0x80124 0x00000003>;
+ qcom,qdss-presets = <0x826000 0x1000>,
+ <0x827000 0x1000>,
+ <0x822000 0x1000>,
+ <0x803000 0x1000>,
+ <0x9180000 0x1000>,
+ <0x9181000 0x1000>;
+ qcom,max-hw-load = <352800>; /* 1080p@30 + 720p@30 */
+ qcom,firmware-name = "venus";
+ qcom,allowed-clock-rates = <360000000 320000000
+ 308570000 240000000 166150000>;
+ qcom,clock-freq-tbl {
+ qcom,profile-enc {
+ qcom,codec-mask = <0x55555555>;
+ qcom,cycles-per-mb = <2316>;
+ qcom,low-power-mode-factor = <32768>;
+ };
+
+ qcom,profile-dec {
+ qcom,codec-mask = <0xf3ffffff>;
+ qcom,cycles-per-mb = <788>;
+ };
+
+ qcom,profile-hevcdec {
+ qcom,codec-mask = <0x0c000000>;
+ qcom,cycles-per-mb = <1015>;
+ };
+ };
+
+ /* MMUs */
+ non_secure_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_ns";
+ iommus = <&apps_iommu 0x800 0x00>,
+ <&apps_iommu 0x807 0x00>,
+ <&apps_iommu 0x808 0x27>,
+ <&apps_iommu 0x811 0x20>;
+ qcom,iommu-dma-addr-pool = <0x5dc00000 0x7f000000
+ 0xdcc00000 0x1000000>;
+ qcom,iommu-faults = "non-fatal";
+ buffer-types = <0xfff>;
+ virtual-addr-pool = <0x5dc00000 0x7f000000
+ 0xdcc00000 0x1000000>;
+ };
+
+ secure_bitstream_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_bitstream";
+ iommus = <&apps_iommu 0x900 0x00>,
+ <&apps_iommu 0x90a 0x04>,
+ <&apps_iommu 0x909 0x22>;
+ qcom,iommu-dma-addr-pool = <0x4b000000 0x12c00000>;
+ qcom,iommu-faults = "non-fatal";
+ buffer-types = <0x241>;
+ virtual-addr-pool = <0x4b000000 0x12c00000>;
+ qcom,secure-context-bank;
+ qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
+ };
+
+ secure_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_pixel";
+ iommus = <&apps_iommu 0x90c 0x20>;
+ qcom,iommu-dma-addr-pool = <0x25800000 0x25800000>;
+ qcom,iommu-faults = "non-fatal";
+ buffer-types = <0x106>;
+ virtual-addr-pool = <0x25800000 0x25800000>;
+ qcom,secure-context-bank;
+ qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
+ };
+
+ secure_non_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_non_pixel";
+ iommus = <&apps_iommu 0x940 0x00>,
+ <&apps_iommu 0x907 0x08>,
+ <&apps_iommu 0x908 0x20>,
+ <&apps_iommu 0x90d 0x20>;
+ qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>;
+ qcom,iommu-faults = "non-fatal";
+ buffer-types = <0x480>;
+ virtual-addr-pool = <0x1000000 0x24800000>;
+ qcom,secure-context-bank;
+ qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
+ };
+
+ /* Buses */
+ venus_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "venus-ddr";
+ qcom,bus-range-kbps = <1000 917000>;
+ };
+
+ arm9_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-arm9-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <1 1>;
+ };
+ };
+
+ venus-ddr-gov {
+ compatible = "qcom,msm-vidc,governor,table";
+ name = "venus-ddr-gov";
+ status = "ok";
+ qcom,bus-freq-table {
+ qcom,profile-enc {
+ qcom,codec-mask = <0x55555555>;
+ qcom,load-busfreq-tbl =
+ <244800 841000>, /* 1080p30E */
+ <216000 740000>, /* 720p60E */
+ <194400 680000>, /* FWVGA120E */
+ <144000 496000>, /* VGA120E */
+ <108000 370000>, /* 720p30E */
+ <97200 340000>, /* FWVGA60E */
+ <48600 170000>, /* FWVGA30E */
+ <72000 248000>, /* VGA60E */
+ <36000 124000>, /* VGA30E */
+ <18000 70000>, /* QVGA60E */
+ <9000 35000>, /* QVGA30E */
+ <0 0>;
+ };
+
+ qcom,profile-dec {
+ qcom,codec-mask = <0xffffffff>;
+ qcom,load-busfreq-tbl =
+ <244800 605000>, /* 1080p30D */
+ <216000 540000>, /* 720p60D */
+ <194400 484000>, /* FWVGA120D */
+ <144000 360000>, /* VGA120D */
+ <108000 270000>, /* 720p30D */
+ <97200 242000>, /* FWVGA60D */
+ <48600 121000>, /* FWVGA30D */
+ <72000 180000>, /* VGA60D */
+ <36000 90000>, /* VGA30D */
+ <18000 45000>, /* HVGA30D */
+ <0 0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8937.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8937.dtsi
new file mode 100755
index 0000000..dfacaa5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8937.dtsi
@@ -0,0 +1,2296 @@
+#include "skeleton64.dtsi"
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-sdm429w.h>
+#include <dt-bindings/clock/qcom,cpu-sdm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/mdss-28nm-pll-clk-legacy.h>
+
+#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
+#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
+
+/ {
+ model = "Qualcomm Technologies, Inc. MSM8937";
+ compatible = "qcom,msm8937";
+ qcom,msm-id = <294 0x0>;
+ interrupt-parent = <&wakegic>;
+
+ chosen {
+ bootargs = "sched_enable_hmp=1 kpti=0";
+ };
+
+ firmware: firmware {
+ android {
+ compatible = "android,firmware";
+ vbmeta {
+ compatible = "android,vbmeta";
+ parts = "vbmeta,boot,system,vendor,dtbo";
+ };
+
+ fstab {
+ compatible = "android,fstab";
+ vendor {
+ compatible = "android,vendor";
+ dev = "/dev/block/platform/soc/7824900.sdhci/by-name/vendor";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,discard";
+ fsmgr_flags = "wait,slotselect,avb";
+ status = "ok";
+ };
+ };
+ };
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ other_ext_mem: other_ext_region@0 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x85b00000 0x0 0xd00000>;
+ };
+
+ modem_mem: modem_region@0 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86800000 0x0 0x5000000>;
+ };
+
+ adsp_fw_mem: adsp_fw_region@0 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8b800000 0x0 0x1100000>;
+ };
+
+ wcnss_fw_mem: wcnss_fw_region@0 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8c900000 0x0 0x700000>;
+ };
+
+
+ venus_mem: venus_region@0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ alloc-ranges = <0x0 0x80000000 0x0 0x10000000>;
+ alignment = <0 0x400000>;
+ size = <0 0x0800000>;
+ };
+
+ secure_mem: secure_region@0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x7000000>;
+ };
+
+ qseecom_mem: qseecom_region@0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x1000000>;
+ };
+
+ qseecom_ta_mem: qseecom_ta_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x00000000 0 0xffffffff>;
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x1000000>;
+ };
+
+ adsp_mem: adsp_region@0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x400000>;
+ };
+
+ cont_splash_mem: splash_region@83000000 {
+ reg = <0x0 0x90000000 0x0 0x1400000>;
+ };
+
+ dump_mem: mem_dump_region {
+ compatible = "shared-dma-pool";
+ reusable;
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ alignment = <0x0 0x400000>;
+ size = <0x19d000>;
+ };
+ };
+
+ aliases {
+ i2c2 = &i2c_2;
+ i2c5 = &i2c_5;
+ spi3 = &spi_3;
+ spi6 = &spi_6;
+ i2c3 = &i2c_3;
+ i2c4 = &i2c_4;
+ sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
+ sdhc2 = &sdhc_2; /* SDC2 for SD card */
+ };
+
+ clocks {
+ xo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ clock-output-names = "xo_board";
+ };
+ };
+
+ soc: soc { };
+
+ vendor: vendor {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+ };
+
+
+};
+
+#include "msm8937-pinctrl.dtsi"
+#include "msm8937-cpu.dtsi"
+#include "msm8937-ion.dtsi"
+#include "msm-arm-smmu-8937.dtsi"
+#include "msm8937-bus.dtsi"
+#include "msm8937-vidc.dtsi"
+#include "msm8937-pm.dtsi"
+#include "msm8937-gpu.dtsi"
+#include "msm8937-mdss.dtsi"
+#include "msm8937-mdss-pll.dtsi"
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ intc: interrupt-controller@b000000 {
+ compatible = "qcom,msm-qgic2";
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <3>;
+ reg = <0x0b000000 0x1000>,
+ <0x0b002000 0x1000>;
+ };
+
+ dcc: dcc@b3000 {
+ compatible = "qcom,dcc";
+ reg = <0xb3000 0x1000>,
+ <0xb4000 0x2000>;
+ reg-names = "dcc-base", "dcc-ram-base";
+
+ clocks = <&gcc GCC_DCC_CLK>;
+ clock-names = "apb_pclk";
+ qcom,save-reg;
+ };
+
+ wakegic: wake-gic {
+ compatible = "qcom,mpm-gic-msm8937", "qcom,mpm-gic";
+ interrupts-extended = <&wakegic GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
+ reg = <0x601d0 0x1000>,
+ <0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */
+ reg-names = "vmpm", "ipc";
+ qcom,num-mpm-irqs = <64>;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <3>;
+ };
+
+ wakegpio: wake-gpio {
+ compatible = "qcom,mpm-gpio";
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <2>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 2 0xff08>,
+ <1 3 0xff08>,
+ <1 4 0xff08>,
+ <1 1 0xff08>;
+ clock-frequency = <19200000>;
+ };
+
+ timer@b120000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xb120000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@b121000 {
+ frame-number = <0>;
+ interrupts = <0 8 0x4>,
+ <0 7 0x4>;
+ reg = <0xb121000 0x1000>,
+ <0xb122000 0x1000>;
+ };
+
+ frame@b123000 {
+ frame-number = <1>;
+ interrupts = <0 9 0x4>;
+ reg = <0xb123000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b124000 {
+ frame-number = <2>;
+ interrupts = <0 10 0x4>;
+ reg = <0xb124000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b125000 {
+ frame-number = <3>;
+ interrupts = <0 11 0x4>;
+ reg = <0xb125000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b126000 {
+ frame-number = <4>;
+ interrupts = <0 12 0x4>;
+ reg = <0xb126000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b127000 {
+ frame-number = <5>;
+ interrupts = <0 13 0x4>;
+ reg = <0xb127000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@b128000 {
+ frame-number = <6>;
+ interrupts = <0 14 0x4>;
+ reg = <0xb128000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ qcom,rmtfs_sharedmem@00000000 {
+ compatible = "qcom,sharedmem-uio";
+ reg = <0x00000000 0x00180000>;
+ reg-names = "rmtfs";
+ qcom,client-id = <0x00000001>;
+ };
+
+ restart@4ab000 {
+ compatible = "qcom,pshold";
+ reg = <0x4ab000 0x4>,
+ <0x193d100 0x4>;
+ reg-names = "pshold-base", "tcsr-boot-misc-detect";
+ };
+
+ qcom,mpm2-sleep-counter@4a3000 {
+ compatible = "qcom,mpm2-sleep-counter";
+ reg = <0x4a3000 0x1000>;
+ clock-frequency = <32768>;
+ };
+
+ cpu-pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <1 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ qcom,sps {
+ compatible = "qcom,msm-sps-4k";
+ qcom,pipe-attr-ee;
+ };
+
+ thermal_zones: thermal-zones {};
+
+ mem_dump {
+ compatible = "qcom,mem-dump";
+ memory-region = <&dump_mem>;
+
+ rpm_sw_dump {
+ qcom,dump-size = <0x28000>;
+ qcom,dump-id = <0xea>;
+ };
+
+ pmic_dump {
+ qcom,dump-size = <0x10000>;
+ qcom,dump-id = <0xe4>;
+ };
+
+ vsense_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xe9>;
+ };
+
+ tmc_etf_dump {
+ qcom,dump-size = <0x10000>;
+ qcom,dump-id = <0xf0>;
+ };
+
+ tmc_etr_reg_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x100>;
+ };
+
+ tmc_etf_reg_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x101>;
+ };
+
+ misc_data_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xe8>;
+ };
+
+ c_scandump {
+ qcom,dump-size = <0x40000>;
+ qcom,dump-id = <0xeb>;
+ };
+
+ c0_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x130>;
+ };
+
+ c100_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x131>;
+ };
+
+ c200_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x132>;
+ };
+
+ c300_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x133>;
+ };
+
+ c400_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x134>;
+ };
+
+ c500_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x135>;
+ };
+
+ c600_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x136>;
+ };
+
+ c700_scandump {
+ qcom,dump-size = <0x10100>;
+ qcom,dump-id = <0x137>;
+ };
+
+ c0_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x0>;
+ };
+
+ c1_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x1>;
+ };
+
+ c2_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x2>;
+ };
+
+ c3_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x3>;
+ };
+
+ c100_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x4>;
+ };
+
+ c101_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x5>;
+ };
+
+ c102_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x6>;
+ };
+
+ c103_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x7>;
+ };
+
+ l1_icache0 {
+ qcom,dump-size = <0x8800>;
+ qcom,dump-id = <0x60>;
+ };
+
+ l1_icache1 {
+ qcom,dump-size = <0x8800>;
+ qcom,dump-id = <0x61>;
+ };
+
+ l1_icache2 {
+ qcom,dump-size = <0x8800>;
+ qcom,dump-id = <0x62>;
+ };
+
+ l1_icache3 {
+ qcom,dump-size = <0x8800>;
+ qcom,dump-id = <0x63>;
+ };
+
+ l1_icache100 {
+ qcom,dump-size = <0x8800>;
+ qcom,dump-id = <0x64>;
+ };
+
+ l1_icache101 {
+ qcom,dump-size = <0x8800>;
+ qcom,dump-id = <0x65>;
+ };
+
+ l1_icache102 {
+ qcom,dump-size = <0x8800>;
+ qcom,dump-id = <0x66>;
+ };
+
+ l1_icache103 {
+ qcom,dump-size = <0x8800>;
+ qcom,dump-id = <0x67>;
+ };
+
+ l1_dcache0 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x80>;
+ };
+
+ l1_dcache1 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x81>;
+ };
+
+ l1_dcache2 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x82>;
+ };
+
+ l1_dcache3 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x83>;
+ };
+
+ l1_dcache100 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x84>;
+ };
+
+ l1_dcache101 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x85>;
+ };
+
+ l1_dcache102 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x86>;
+ };
+
+ l1_dcache103 {
+ qcom,dump-size = <0x9000>;
+ qcom,dump-id = <0x87>;
+ };
+
+ };
+
+ tsens0: tsens@4a8000 {
+ compatible = "qcom,msm8937-tsens";
+ reg = <0x4a8000 0x1000>,
+ <0x4a9000 0x1000>,
+ <0xa4000 0x1000>;
+ reg-names = "tsens_srot_physical",
+ "tsens_tm_physical", "tsens_eeprom_physical";
+ interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tsens-upper-lower";
+ #thermal-sensor-cells = <1>;
+ };
+
+ slim_msm: slim@c140000 {
+ cell-index = <1>;
+ compatible = "qcom,slim-ngd";
+ reg = <0xc140000 0x2c000>,
+ <0xc104000 0x2a000>;
+ reg-names = "slimbus_physical", "slimbus_bam_physical";
+ interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>,
+ <0 180 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "slimbus_irq", "slimbus_bam_irq";
+ qcom,apps-ch-pipes = <0x600000>;
+ qcom,ea-pc = <0x230>;
+ status = "disabled";
+ };
+
+ blsp1_uart2: serial@78b0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0x78b0000 0x200>;
+ interrupts = <0 108 0>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */
+ #dma-cells = <4>;
+ compatible = "qcom,sps-dma";
+ reg = <0x7884000 0x1f000>;
+ interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,summing-threshold = <10>;
+ };
+
+ dma_blsp2: qcom,sps-dma@7ac4000 { /* BLSP2 */
+ #dma-cells = <4>;
+ compatible = "qcom,sps-dma";
+ reg = <0x7ac4000 0x1f000>;
+ interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,summing-threshold = <10>;
+ };
+
+ rpmcc: qcom,rpmcc {
+ compatible = "qcom,rpmcc-sdm439";
+ #clock-cells = <1>;
+ };
+
+ gcc: qcom,gcc@1800000 {
+ compatible = "qcom,gcc-sdm439", "syscon";
+ reg = <0x1800000 0x80000>;
+ reg-names = "cc_base";
+ qcom,gcc_oxili_gfx3d_clk-opp-handle = <&msm_gpu>;
+ vdd_cx-supply = <&pm8937_s2_level>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "bi_tcxo";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cpu_debug: syscon@0b11101c {
+ compatible = "syscon";
+ reg = <0xb11101c 0x4>;
+ };
+
+ debugcc: qcom,cc-debug {
+ compatible = "qcom,sdm439-debugcc";
+ qcom,gcc = <&gcc>;
+ qcom,cpu = <&cpu_debug>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo_clk_src";
+ #clock-cells = <1>;
+ };
+
+ gcc_mdss: qcom,gcc-mdss@1800000 {
+ compatible = "qcom,gcc-mdss-msm8937";
+ reg = <0x1800000 0x80000>;
+ clocks = <&mdss_dsi0_pll PCLK_SRC_0_CLK>,
+ <&mdss_dsi0_pll BYTECLK_SRC_0_CLK>,
+ <&mdss_dsi1_pll PCLK_SRC_1_CLK>,
+ <&mdss_dsi1_pll BYTECLK_SRC_1_CLK>;
+ clock-names = "pclk0_src", "byte0_src", "pclk1_src",
+ "byte1_src";
+ #clock-cells = <1>;
+ };
+
+ apsscc: qcom,clock-cpu@b111050 {
+ compatible = "qcom,cpu-clock-sdm439";
+ reg = <0xb011050 0x8>,
+ <0xb016000 0x34>,
+ <0xb011200 0x100>,
+ <0xb1d1050 0x8>,
+ <0xb111050 0x8>,
+ <0xb116000 0x34>,
+ <0xb111200 0x100>,
+ <0x00a412c 0x8>;
+ reg-names = "apcs-c1-rcg-base", "apcs_pll1", "spm_c1_base",
+ "apcs-cci-rcg-base", "apcs-c0-rcg-base",
+ "apcs_pll0", "spm_c0_base", "efuse";
+ clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
+ <&gcc GPLL0_AO_OUT_MAIN>;
+ clock-names = "xo_ao", "gpll0_ao" ;
+ qcom,speed0-bin-v0-c0 =
+ < 0 0>,
+ < 768000000 1>,
+ < 902400000 2>,
+ < 998400000 4>,
+ < 1094400000 6>;
+
+ qcom,speed0-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1094400000 2>,
+ < 1248000000 4>,
+ < 1344000000 5>,
+ < 1401000000 6>;
+
+ qcom,speed0-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+
+ qcom,speed1-bin-v0-c0 =
+ < 0 0>,
+ < 768000000 1>,
+ < 902400000 2>,
+ < 998400000 4>,
+ < 1094400000 6>,
+ < 1209600000 7>;
+
+ qcom,speed1-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1094400000 2>,
+ < 1248000000 4>,
+ < 1344000000 5>,
+ < 1401000000 6>,
+ < 1497600000 7>;
+
+ qcom,speed1-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+
+ qcom,speed2-bin-v0-c0 =
+ < 0 0>,
+ < 768000000 1>,
+ < 902400000 2>,
+ < 998400000 3>;
+
+ qcom,speed2-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1094400000 2>,
+ < 1209600000 3>;
+
+ qcom,speed2-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+ #clock-cells = <1>;
+ };
+
+ i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "qup_phys_addr";
+ reg = <0x78b6000 0x600>;
+ interrupt-names = "qup_irq";
+ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+
+ pinctrl-names = "i2c_active", "i2c_sleep";
+ pinctrl-0 = <&i2c_2_active>;
+ pinctrl-1 = <&i2c_2_sleep>;
+ qcom,noise-rjct-scl = <0>;
+ qcom,noise-rjct-sda = <0>;
+ qcom,master-id = <86>;
+ dmas = <&dma_blsp1 6 64 0x20000020 0x20>,
+ <&dma_blsp1 7 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "qup_phys_addr";
+ reg = <0x78b7000 0x600>;
+ interrupt-names = "qup_irq";
+ interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+
+ pinctrl-names = "i2c_active", "i2c_sleep";
+ pinctrl-0 = <&i2c_3_active>;
+ pinctrl-1 = <&i2c_3_sleep>;
+ qcom,noise-rjct-scl = <0>;
+ qcom,noise-rjct-sda = <0>;
+ qcom,master-id = <86>;
+ dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
+ <&dma_blsp1 9 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c_4: i2c@78b8000 { /* BLSP1 QUP4 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "qup_phys_addr";
+ reg = <0x78b8000 0x600>;
+ interrupt-names = "qup_irq";
+ interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
+
+ pinctrl-names = "i2c_active", "i2c_sleep";
+ pinctrl-0 = <&i2c_4_active>;
+ pinctrl-1 = <&i2c_4_sleep>;
+ qcom,noise-rjct-scl = <0>;
+ qcom,noise-rjct-sda = <0>;
+ qcom,master-id = <86>;
+ dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
+ <&dma_blsp1 11 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c_5: i2c@7af5000 { /* BLSP2 QUP1 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "qup_phys_addr";
+ reg = <0x7af5000 0x600>;
+ interrupt-names = "qup_irq";
+ interrupts = <0 299 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
+
+ pinctrl-names = "i2c_active", "i2c_sleep";
+ pinctrl-0 = <&i2c_5_active>;
+ pinctrl-1 = <&i2c_5_sleep>;
+ qcom,noise-rjct-scl = <0>;
+ qcom,noise-rjct-sda = <0>;
+ qcom,master-id = <84>;
+ dmas = <&dma_blsp2 4 64 0x20000020 0x20>,
+ <&dma_blsp2 5 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi_3: spi@78b7000 { /* BLSP1 QUP3 */
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "spi_physical", "spi_bam_physical";
+ reg = <0x78b7000 0x600>,
+ <0x7884000 0x1f000>;
+ interrupt-names = "spi_irq", "spi_bam_irq";
+ interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>,
+ <0 238 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <19200000>;
+ pinctrl-names = "spi_default", "spi_sleep";
+ pinctrl-0 = <&spi3_default &spi3_cs0_active>;
+ pinctrl-1 = <&spi3_sleep &spi3_cs0_sleep>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
+ clock-names = "iface_clk", "core_clk";
+ qcom,infinite-mode = <0>;
+ qcom,use-bam;
+ qcom,use-pinctrl;
+ qcom,ver-reg-exists;
+ qcom,bam-consumer-pipe-index = <8>;
+ qcom,bam-producer-pipe-index = <9>;
+ qcom,master-id = <86>;
+ status = "disabled";
+ };
+
+ spi_6: spi@7af6000 { /* BLSP2 QUP1 */
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "spi_physical", "spi_bam_physical";
+ reg = <0x7af6000 0x600>,
+ <0x7ac4000 0x1f000>;
+ interrupt-names = "spi_irq", "spi_bam_irq";
+ interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>,
+ <0 239 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <19200000>;
+ pinctrl-names = "spi_default", "spi_sleep";
+ pinctrl-0 = <&spi6_default &spi6_cs0_active>;
+ pinctrl-1 = <&spi6_sleep &spi6_cs0_sleep>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>,
+ <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>;
+ clock-names = "iface_clk", "core_clk";
+ qcom,infinite-mode = <0>;
+ qcom,use-bam;
+ qcom,use-pinctrl;
+ qcom,ver-reg-exists;
+ qcom,bam-consumer-pipe-index = <6>;
+ qcom,bam-producer-pipe-index = <7>;
+ qcom,master-id = <84>;
+ status = "disabled";
+ };
+
+ blsp2_uart2: uart@7af0000 { /* BLSP2 UART2 */
+ compatible = "qcom,msm-hsuart-v14";
+ reg = <0x7af0000 0x200>,
+ <0x7ac4000 0x1f000>;
+ reg-names = "core_mem", "bam_mem";
+ interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
+ #address-cells = <0>;
+ interrupt-parent = <&blsp2_uart2>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 307 0
+ 1 &intc 0 239 0
+ 2 &tlmm 21 0>;
+
+ qcom,inject-rx-on-wakeup;
+ qcom,rx-char-to-inject = <0xfd>;
+
+ qcom,bam-tx-ep-pipe-index = <2>;
+ qcom,bam-rx-ep-pipe-index = <3>;
+ qcom,master-id = <84>;
+ clock-names = "core_clk", "iface_clk";
+ clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ pinctrl-names = "sleep", "default";
+ pinctrl-0 = <&blsp2_uart2_sleep>;
+ pinctrl-1 = <&blsp2_uart2_active>;
+ qcom,msm-bus,name = "blsp2_uart2";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <84 512 0 0>,
+ <84 512 500 800>;
+ status = "disabled";
+ };
+
+ msm_cpufreq: qcom,msm-cpufreq {
+ compatible = "qcom,msm-cpufreq";
+ clocks = <&apsscc APCS_MUX_CCI_CLK>,
+ <&apsscc APCS_MUX_C1_CLK>,
+ <&apsscc APCS_MUX_C0_CLK>;
+ clock-names = "l2_clk", "cpu0_clk", "cpu4_clk";
+
+ qcom,governor-per-policy;
+
+ qcom,cpufreq-table-0 =
+ < 960000 >,
+ < 1094400 >,
+ < 1209600 >,
+ < 1248000 >,
+ < 1344000 >,
+ < 1401000 >,
+ < 1497600 >;
+
+ qcom,cpufreq-table-4 =
+ < 768000 >,
+ < 902400 >,
+ < 998400 >,
+ < 1094400 >,
+ < 1209600 >;
+ };
+
+ cci_cache: qcom,cci {
+ compatible = "devfreq-simple-dev";
+ clock-names = "devfreq_clk";
+ clocks = <&apsscc APCS_MUX_CCI_CLK>;
+ governor = "performance";
+ freq-tbl-khz =
+ < 400000 >,
+ < 533333 >;
+ };
+
+ ddr_bw_opp_table: ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 100, 8); /* 769 MB/s */
+ BW_OPP_ENTRY( 211, 8); /* 1611 MB/s */
+ BW_OPP_ENTRY( 278, 8); /* 2124 MB/s */
+ BW_OPP_ENTRY( 384, 8); /* 2929 MB/s */
+ BW_OPP_ENTRY( 537, 8); /* 4101 MB/s */
+ BW_OPP_ENTRY( 556, 8); /* 4248 MB/s */
+ BW_OPP_ENTRY( 662, 8); /* 5053 MB/s */
+ BW_OPP_ENTRY( 748, 8); /* 5712 MB/s */
+ BW_OPP_ENTRY( 806, 8); /* 6152 MB/s */
+ BW_OPP_ENTRY( 921, 8); /* 7031 MB/s */
+ };
+
+ cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@408000 {
+ compatible = "qcom,bimc-bwmon2";
+ reg = <0x408000 0x300>, <0x401000 0x200>;
+ reg-names = "base", "global_base";
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,target-dev = <&cpu_cpu_ddr_bw>;
+ };
+
+ cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ cpu0_computemon: qcom,cpu0-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 1094400 MHZ_TO_MBPS(384, 8) >,
+ < 1497600 MHZ_TO_MBPS(557, 8) >;
+ };
+ };
+
+ cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+
+ cpu4_computemon: qcom,cpu4-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+ qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 998400 MHZ_TO_MBPS(384, 8) >,
+ < 1209600 MHZ_TO_MBPS(557, 8) >;
+ };
+ };
+
+ blsp2_uart1: uart@7aef000 {
+ compatible = "qcom,msm-hsuart-v14";
+ reg = <0x7aef000 0x200>,
+ <0x7ac4000 0x1f000>;
+ reg-names = "core_mem", "bam_mem";
+ interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
+ #address-cells = <0>;
+ interrupt-parent = <&blsp2_uart1>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 306 0
+ 1 &intc 0 239 0
+ 2 &tlmm 17 0>;
+
+ qcom,inject-rx-on-wakeup;
+ qcom,rx-char-to-inject = <0xfd>;
+
+ qcom,bam-tx-ep-pipe-index = <0>;
+ qcom,bam-rx-ep-pipe-index = <1>;
+ qcom,master-id = <84>;
+ clock-names = "core_clk", "iface_clk";
+ clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ pinctrl-names = "sleep", "default";
+ pinctrl-0 = <&blsp2_uart1_sleep>;
+ pinctrl-1 = <&blsp2_uart1_active>;
+ qcom,msm-bus,name = "blsp2_uart1";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <84 512 0 0>,
+ <84 512 500 800>;
+ status = "disabled";
+ };
+
+ qcom,ipc-spinlock@1905000 {
+ compatible = "qcom,ipc-spinlock-sfpb";
+ reg = <0x1905000 0x8000>;
+ qcom,num-locks = <8>;
+ };
+
+ qcom,iris-fm {
+ compatible = "qcom,iris_fm";
+ };
+
+ rpm_bus: qcom,rpm-smd {
+ compatible = "qcom,rpm-smd";
+ rpm-channel-name = "rpm_requests";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ rpm-channel-type = <15>; /* SMD_APPS_RPM */
+ };
+
+ usb_otg: usb@78db000 {
+ compatible = "qcom,hsusb-otg";
+ reg = <0x78db000 0x400>, <0x6c000 0x200>;
+ reg-names = "core", "phy_csr";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupts = <0 134 IRQ_TYPE_LEVEL_HIGH>,
+ <0 140 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "core_irq", "async_irq";
+
+ hsusb_vdd_dig-supply = <&pm8937_l2>;
+ HSUSB_1p8-supply = <&pm8937_l7>;
+ HSUSB_3p3-supply = <&pm8937_l13>;
+ qcom,vdd-voltage-level = <0 1200000 1200000>;
+
+ qcom,hsusb-otg-phy-type = <3>; /* SNPS Femto PHY */
+ qcom,hsusb-otg-mode = <3>; /* OTG mode */
+ qcom,hsusb-otg-otg-control = <2>; /* PMIC */
+ qcom,dp-manual-pullup;
+ qcom,phy-dvdd-always-on;
+ qcom,boost-sysclk-with-streaming;
+ qcom,axi-prefetch-enable;
+ qcom,hsusb-otg-delay-lpm;
+
+ qcom,msm-bus,name = "usb2";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <87 512 0 0>,
+ <87 512 80000 0>,
+ <87 512 6000 6000>;
+ clocks = <&gcc GCC_USB_HS_AHB_CLK>,
+ <&gcc GCC_USB_HS_SYSTEM_CLK>,
+ <&gcc GCC_USB2A_PHY_SLEEP_CLK>,
+ <&rpmcc BIMC_USB_A_CLK>,
+ <&rpmcc SNOC_USB_A_CLK>,
+ <&rpmcc PNOC_USB_A_CLK>,
+ <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+ <&rpmcc CXO_SMD_OTG_CLK>;
+ clock-names = "iface_clk", "core_clk", "sleep_clk",
+ "bimc_clk", "snoc_clk", "pcnoc_clk",
+ "phy_csr_clk", "xo";
+ qcom,bus-clk-rate = <748800000 200000000 100000000>;
+ qcom,max-nominal-sysclk-rate = <133330000>;
+
+ resets = <&gcc GCC_USB_HS_BCR>,
+ <&gcc GCC_QUSB2_PHY_BCR>,
+ <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
+ reset-names = "core_reset", "phy_reset", "phy_por_reset";
+
+ qcom,usbbam@78c4000 {
+ compatible = "qcom,usb-bam-msm";
+ reg = <0x78c4000 0x17000>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 135 IRQ_TYPE_LEVEL_HIGH>;
+
+ qcom,bam-type = <1>;
+ qcom,usb-bam-num-pipes = <4>;
+ qcom,usb-bam-fifo-baseaddr = <0x08605000>;
+ qcom,ignore-core-reset-ack;
+ qcom,disable-clk-gating;
+ qcom,usb-bam-max-mbps-highspeed = <400>;
+ qcom,reset-bam-on-disconnect;
+
+ qcom,pipe0 {
+ label = "hsusb-qdss-in-0";
+ qcom,usb-bam-mem-type = <2>;
+ qcom,dir = <1>;
+ qcom,pipe-num = <0>;
+ qcom,peer-bam = <0>;
+ qcom,peer-bam-physical-address = <0x6044000>;
+ qcom,src-bam-pipe-index = <0>;
+ qcom,dst-bam-pipe-index = <0>;
+ qcom,data-fifo-offset = <0x0>;
+ qcom,data-fifo-size = <0xe00>;
+ qcom,descriptor-fifo-offset = <0xe00>;
+ qcom,descriptor-fifo-size = <0x200>;
+ };
+ };
+ };
+
+ qcom,wdt@b017000 {
+ compatible = "qcom,msm-watchdog";
+ reg = <0xb017000 0x1000>;
+ reg-names = "wdt-base";
+ interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
+ <0 4 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bark-time = <11000>;
+ qcom,pet-time = <9360>;
+ qcom,ipi-ping;
+ qcom,wakeup-enable;
+ status = "okay";
+ };
+
+ spmi_bus: qcom,spmi@200f000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x200f000 0x1000>,
+ <0x2400000 0x800000>,
+ <0x2c00000 0x800000>,
+ <0x3800000 0x200000>,
+ <0x200a000 0x2100>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
+ qcom,chd {
+ compatible = "qcom,core-hang-detect";
+ qcom,threshold-arr = <0xb088094 0xb098094 0xb0a8094
+ 0xb0b8094 0xb188094 0xb198094 0xb1a8094 0xb1a8094>;
+ qcom,config-arr = <0xb08809c 0xb09809c 0xb0a809c
+ 0xb0b809c 0xb18809c 0xb19809c 0xb1a809c 0xb1b809c>;
+ };
+
+ qcom,msm-rtb {
+ compatible = "qcom,msm-rtb";
+ qcom,rtb-size = <0x100000>; /* 1M EBI1 buffer */
+ };
+
+ qcom,msm-imem@8600000 {
+ compatible = "qcom,msm-imem";
+ reg = <0x08600000 0x1000>; /* Address and size of IMEM */
+ ranges = <0x0 0x08600000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mem_dump_table@10 {
+ compatible = "qcom,msm-imem-mem_dump_table";
+ reg = <0x10 0x8>;
+ };
+
+ dload_type@1c {
+ compatible = "qcom,msm-imem-dload-type";
+ reg = <0x1c 0x4>;
+ };
+
+ restart_reason@65c {
+ compatible = "qcom,msm-imem-restart_reason";
+ reg = <0x65c 0x4>;
+ };
+
+ boot_stats@6b0 {
+ compatible = "qcom,msm-imem-boot_stats";
+ reg = <0x6b0 0x20>;
+ };
+
+ kaslr_offset@6d0 {
+ compatible = "qcom,msm-imem-kaslr_offset";
+ reg = <0x6d0 0xc>;
+ };
+
+ pil@94c {
+ compatible = "qcom,msm-imem-pil";
+ reg = <0x94c 0xc8>;
+ };
+
+ diag_dload@c8 {
+ compatible = "qcom,msm-imem-diag-dload";
+ reg = <0xc8 0xc8>;
+ };
+ };
+
+ qcom,memshare {
+ compatible = "qcom,memshare";
+
+ qcom,client_1 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x200000>;
+ qcom,client-id = <0>;
+ qcom,allocate-boot-time;
+ label = "modem";
+ };
+
+ qcom,client_2 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x300000>;
+ qcom,client-id = <2>;
+ label = "modem";
+ };
+
+ qcom,client_3 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x500000>;
+ qcom,client-id = <1>;
+ qcom,allocate-boot-time;
+ label = "modem";
+ };
+ };
+
+ jtag_mm0: jtagmm@61bc000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x61bc000 0x1000>;
+ reg-names = "etm-base";
+
+ qcom,coresight-jtagmm-cpu = <&CPU0>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+ };
+
+ jtag_mm1: jtagmm@61bd000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x61bd000 0x1000>;
+ reg-names = "etm-base";
+
+ qcom,coresight-jtagmm-cpu = <&CPU1>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+ };
+
+ jtag_mm2: jtagmm@61be000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x61be000 0x1000>;
+ reg-names = "etm-base";
+
+ qcom,coresight-jtagmm-cpu = <&CPU2>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+ };
+
+ jtag_mm3: jtagmm@61bf000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x61bf000 0x1000>;
+ reg-names = "etm-base";
+
+ qcom,coresight-jtagmm-cpu = <&CPU3>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+ };
+
+ jtag_mm4: jtagmm@619c000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x619c000 0x1000>;
+ reg-names = "etm-base";
+
+ qcom,coresight-jtagmm-cpu = <&CPU4>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+ };
+
+ jtag_mm5: jtagmm@619d000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x619d000 0x1000>;
+ reg-names = "etm-base";
+
+ qcom,coresight-jtagmm-cpu = <&CPU5>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+ };
+
+ jtag_mm6: jtagmm@619e000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x619e000 0x1000>;
+ reg-names = "etm-base";
+
+ qcom,coresight-jtagmm-cpu = <&CPU6>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+ };
+
+ jtag_mm7: jtagmm@619f000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x619f000 0x1000>;
+ reg-names = "etm-base";
+
+ qcom,coresight-jtagmm-cpu = <&CPU7>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+ };
+
+ apcs: syscon@0b011008 {
+ compatible = "syscon";
+ reg = <0x0b011008 0x04>;
+ };
+
+ tcsr_mutex_block: syscon@01905000 {
+ compatible = "syscon";
+ reg = <0x01905000 0x20000>;
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_block 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ rpm_msg_ram: memory@60000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x60000 0x8000>;
+ };
+
+ smem_mem: smem_region@86300000 {
+ no-map;
+ reg = <0x86300000 0x100000>;
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ smp2p-modem {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 0 14>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 0 10>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sleepstate_smp2p_out: sleepstate-out {
+ qcom,entry-name = "sleepstate";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ sleepstate_smp2p_in: qcom,sleepstate-in {
+ qcom,entry-name = "sleepstate_see";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p_sleepstate {
+ compatible = "qcom,smp2p-sleepstate";
+ qcom,smem-states = <&sleepstate_smp2p_out 0>;
+ interrupt-parent = <&sleepstate_smp2p_in>;
+ interrupts = <0 0>;
+ interrupt-names = "smp2p-sleepstate-in";
+ };
+
+ smp2p-wcnss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <451>, <431>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 0 18>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <4>;
+
+ wcnss_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ wcnss_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smd {
+ compatible = "qcom,smd";
+
+ modem {
+ interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 0 12>;
+ qcom,smd-edge = <0>;
+ qcom,remote-pid = <1>;
+ label = "mpss";
+
+ qcom,smd-channels = "IPCRTR";
+ qcom,modem_qrtr {
+ qcom,net-id = <1>;
+ qcom,low-latency;
+ };
+
+ qcom,diag {
+ qcom,smd-channels = "DIAG";
+ };
+
+ qcom,diag_cntl {
+ qcom,smd-channels = "DIAG_CNTL";
+ };
+
+ qcom,diag_cmd {
+ qcom,smd-channels = "DIAG_CMD";
+ };
+
+ qcom,diag_dci {
+ qcom,smd-channels = "DIAG_2";
+ };
+
+ qcom.diag_dci_cmd {
+ qcom,smd-channels = "DIAG_2_CMD";
+ };
+ };
+
+ adsp {
+ interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 0 8>;
+ qcom,smd-edge = <1>;
+ qcom,remote-pid = <2>;
+ mbox-names = "adsp_smem";
+ label = "adsp";
+
+ qcom,smd-channels = "IPCRTR";
+ qcom,adsp_qrtr {
+ qcom,net-id = <1>;
+ qcom,low-latency;
+ };
+
+ qcom,diag {
+ qcom,smd-channels = "DIAG";
+ };
+
+ qcom,diag_cntl {
+ qcom,smd-channels = "DIAG_CNTL";
+ };
+
+ qcom,apr_tal_rpmsg {
+ qcom,smd-channels = "apr_audio_svc";
+ };
+ };
+
+ wcnss {
+ interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&apcs 0 17>;
+ qcom,smd-edge = <6>;
+ qcom,remote-pid = <4>;
+ label = "wcnss";
+
+ qcom,smd-channels = "IPCRTR";
+ qcom,wcnss_qrtr {
+ qcom,net-id = <1>;
+ qcom,low-latency;
+ };
+
+ qcom,diag {
+ qcom,smd-channels = "APPS_RIVA_DATA";
+ };
+
+ qcom,diag_cntl {
+ qcom,smd-channels = "APPS_RIVA_CTRL";
+ };
+ };
+
+ rpm {
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,ipc = <&apcs 0 0>;
+ qcom,smd-edge = <15>;
+ label = "rpm";
+
+ rpm_requests: rpm_requests@0 {
+ compatible = "qcom,rpm-smd";
+ qcom,smd-channels = "rpm_requests";
+ };
+
+ };
+ };
+
+ qcom,smsm {
+ compatible = "qcom,smsm";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ipc-1 = <&apcs 0 13>;
+ qcom,ipc-2 = <&apcs 0 9>;
+ qcom,ipc-3 = <&apcs 0 19>;
+
+ apps_smsm: apps@0 {
+ reg = <0>;
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smsm: modem@1 {
+ reg = <1>;
+ interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ adsp_smsm: adsp@2 {
+ reg = <2>;
+ interrupts = <0 290 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ wcnss_smsm: wcnss@3 {
+ reg = <3>;
+ interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smdpkt {
+ compatible = "qcom,smdpkt";
+
+ qcom,smdpkt-data5-cntl {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA5_CNTL";
+ qcom,smdpkt-dev-name = "smdcntl0";
+ };
+
+ qcom,smdpkt-data22 {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA22";
+ qcom,smdpkt-dev-name = "smd22";
+ };
+
+ qcom,smdpkt-data40-cntl {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA40_CNTL";
+ qcom,smdpkt-dev-name = "smdcntl8";
+ };
+
+ qcom,smdpkt-data2 {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA2";
+ qcom,smdpkt-dev-name = "at_mdm0";
+ };
+
+ qcom,smdpkt-apr-apps2 {
+ qcom,smdpkt-edge = "adsp";
+ qcom,smdpkt-ch-name = "apr_apps2";
+ qcom,smdpkt-dev-name = "apr_apps2";
+ };
+
+ qcom,smdpkt-apps-riva-bt-acl {
+ qcom,smdpkt-edge = "wcnss";
+ qcom,smdpkt-ch-name = "APPS_RIVA_BT_ACL";
+ qcom,smdpkt-dev-name = "smd2";
+ qcom,smdpkt-fragmented-read;
+ };
+
+ qcom,smdpkt-apps-riva-bt-cmd {
+ qcom,smdpkt-edge = "wcnss";
+ qcom,smdpkt-ch-name = "APPS_RIVA_BT_CMD";
+ qcom,smdpkt-dev-name = "smd3";
+ qcom,smdpkt-fragmented-read;
+ };
+
+ qcom,smdpkt-mbalbridge {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "MBALBRIDGE";
+ qcom,smdpkt-dev-name = "smd4";
+ };
+
+ qcom,smdpkt-apps-riva-ant-cmd {
+ qcom,smdpkt-edge = "wcnss";
+ qcom,smdpkt-ch-name = "APPS_RIVA_ANT_CMD";
+ qcom,smdpkt-dev-name = "smd5";
+ };
+
+ qcom,smdpkt-apps-riva-ant-data {
+ qcom,smdpkt-edge = "wcnss";
+ qcom,smdpkt-ch-name = "APPS_RIVA_ANT_DATA";
+ qcom,smdpkt-dev-name = "smd6";
+ };
+
+ qcom,smdpkt-data1 {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA1";
+ qcom,smdpkt-dev-name = "smd7";
+ };
+
+ qcom,smdpkt-data4 {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA4";
+ qcom,smdpkt-dev-name = "smd8";
+ };
+
+ qcom,smdpkt-data11 {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA11";
+ qcom,smdpkt-dev-name = "smd11";
+ };
+
+ qcom,smdpkt-data21 {
+ qcom,smdpkt-edge = "modem";
+ qcom,smdpkt-ch-name = "DATA21";
+ qcom,smdpkt-dev-name = "smd21";
+ };
+ };
+
+ qcom_tzlog: tz-log@08600720 {
+ compatible = "qcom,tz-log";
+ reg = <0x08600720 0x2000>;
+ };
+
+ qcom,adsprpc-mem {
+ compatible = "qcom,msm-adsprpc-mem-region";
+ memory-region = <&adsp_mem>;
+ };
+
+ qcom,msm_fastrpc {
+ compatible = "qcom,msm-fastrpc-legacy-compute";
+ qcom,msm_fastrpc_compute_cb {
+ compatible = "qcom,msm-fastrpc-legacy-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_iommu 0x2008 0x7>;
+ sids = <0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf>;
+ };
+ };
+
+ sdcc1_ice: sdcc1ice@7803000 {
+ compatible = "qcom,ice";
+ reg = <0x7803000 0x8000>;
+ interrupt-names = "sdcc_ice_nonsec_level_irq",
+ "sdcc_ice_sec_level_irq";
+ interrupts = <0 312 IRQ_TYPE_LEVEL_HIGH>,
+ <0 313 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,enable-ice-clk;
+ clock-names = "ice_core_clk_src", "ice_core_clk",
+ "bus_clk", "iface_clk";
+ clocks = <&gcc SDCC1_ICE_CORE_CLK_SRC>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_AHB_CLK>;
+ qcom,op-freq-hz = <200000000>, <0>, <0>, <0>;
+ qcom,msm-bus,name = "sdcc_ice_noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <78 512 0 0>, /* No vote */
+ <78 512 1000 0>; /* Max. bandwidth */
+ qcom,bus-vector-names = "MIN", "MAX";
+ qcom,instance-type = "sdcc";
+ };
+
+ sdhc_1: sdhci@7824900 {
+ compatible = "qcom,sdhci-msm", "qcom,sdhci-msm-cqe";
+ reg = <0x7824900 0x500>, <0x7824000 0x800>, <0x7824e00 0x200>,
+ <0x7803000 0x8000>;
+ reg-names = "hc_mem", "core_mem", "cqhci_mem", "cqhci_ice";
+
+ interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 138 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <8>;
+ qcom,large-address-bus;
+
+ qcom,devfreq,freq-table = <50000000 200000000>;
+
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <2 200>;
+
+ qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
+ qcom,pm-qos-cmdq-latency-us = <2 200>, <2 200>;
+
+ qcom,pm-qos-legacy-latency-us = <2 200>, <2 200>;
+
+ qcom,msm-bus,name = "sdhc1";
+ qcom,msm-bus,num-cases = <9>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
+ <78 512 1046 3200>, /* 400 KB/s*/
+ <78 512 52286 160000>, /* 20 MB/s */
+ <78 512 65360 200000>, /* 25 MB/s */
+ <78 512 130718 400000>, /* 50 MB/s */
+ <78 512 130718 400000>, /* 100 MB/s */
+ <78 512 261438 800000>, /* 200 MB/s */
+ <78 512 261438 800000>, /* 400 MB/s */
+ <78 512 1338562 4096000>; /* Max. bandwidth */
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000
+ 50000000 100000000 200000000 400000000 4294967295>;
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface_clk", "core_clk", "ice_core_clk";
+ qcom,ice-clk-rates = <200000000 100000000>;
+
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x00076400 0x0 0x0 0x0 0x00040868>;
+
+ qcom,scaling-lower-bus-speed-mode = "DDR52";
+ status = "disabled";
+ };
+
+ sdhc_2: sdhci@7864900 {
+ compatible = "qcom,sdhci-msm";
+ reg = <0x7864900 0x500>, <0x7864000 0x800>;
+ reg-names = "hc_mem", "core_mem";
+
+ interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <4>;
+ qcom,large-address-bus;
+
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <2 200>;
+
+ qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
+ qcom,pm-qos-legacy-latency-us = <2 200>, <2 200>;
+
+ qcom,msm-bus,name = "sdhc2";
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
+ <81 512 1046 3200>, /* 400 KB/s*/
+ <81 512 52286 160000>, /* 20 MB/s */
+ <81 512 65360 200000>, /* 25 MB/s */
+ <81 512 130718 400000>, /* 50 MB/s */
+ <81 512 261438 800000>, /* 100 MB/s */
+ <81 512 261438 800000>, /* 200 MB/s */
+ <81 512 1338562 4096000>; /* Max. bandwidth */
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100000000 200000000 4294967295>;
+
+ qcom,devfreq,freq-table = <50000000 200000000>;
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>;
+ clock-names = "iface_clk", "core_clk";
+
+ status = "disabled";
+ };
+
+ qcom_seecom: qseecom@85b00000 {
+ compatible = "qcom,qseecom";
+ reg = <0x85b00000 0x800000>;
+ reg-names = "secapp-region";
+ qcom,hlos-num-ce-hw-instances = <1>;
+ qcom,hlos-ce-hw-instance = <0>;
+ qcom,qsee-ce-hw-instance = <0>;
+ qcom,disk-encrypt-pipe-pair = <2>;
+ qcom,support-fde;
+ qcom,commonlib64-loaded-by-uefi;
+ qcom,msm-bus,name = "qseecom-noc";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,support-bus-scaling;
+ qcom,msm-bus,vectors-KBps =
+ <55 512 0 0>,
+ <55 512 0 0>,
+ <55 512 120000 1200000>,
+ <55 512 393600 3936000>;
+ clocks = <&gcc CRYPTO_CLK_SRC>,
+ <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>;
+ clock-names = "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ qcom,ce-opp-freq = <100000000>;
+ };
+
+ qcom_rng: qrng@e3000 {
+ compatible = "qcom,msm-rng";
+ reg = <0xe3000 0x1000>;
+ qcom,msm-rng-iface-clk;
+ qcom,no-qrng-config;
+ qcom,msm-bus,name = "msm-rng-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 618 0 0>, /* No vote */
+ <1 618 0 800>; /* 100 MB/s */
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "iface_clk";
+ };
+
+ qcom_crypto: qcrypto@720000 {
+ compatible = "qcom,qcrypto";
+ reg = <0x720000 0x20000>,
+ <0x704000 0x20000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <2>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,ce-hw-shared;
+ qcom,clk-mgmt-sus-res;
+ qcom,msm-bus,name = "qcrypto-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <55 512 0 0>,
+ <55 512 393600 393600>;
+ clocks = <&gcc CRYPTO_CLK_SRC>,
+ <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>;
+ clock-names = "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ qcom,use-sw-aes-cbc-ecb-ctr-algo;
+ qcom,use-sw-aes-xts-algo;
+ qcom,use-sw-aes-ccm-algo;
+ qcom,use-sw-ahash-algo;
+ qcom,use-sw-hmac-algo;
+ qcom,use-sw-aead-algo;
+ qcom,ce-opp-freq = <100000000>;
+ };
+
+ qcom_cedev: qcedev@720000 {
+ compatible = "qcom,qcedev";
+ reg = <0x720000 0x20000>,
+ <0x704000 0x20000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <0 207 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <1>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,ce-hw-shared;
+ qcom,msm-bus,name = "qcedev-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <55 512 0 0>,
+ <55 512 393600 393600>;
+ clocks = <&gcc CRYPTO_CLK_SRC>,
+ <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>;
+ clock-names = "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ qcom,ce-opp-freq = <100000000>;
+ };
+
+ pil_mss: qcom,mss@4080000 {
+ compatible = "qcom,pil-q6v55-mss";
+ reg = <0x04080000 0x100>,
+ <0x0194f000 0x010>,
+ <0x01950000 0x008>,
+ <0x01951000 0x008>,
+ <0x04020000 0x040>,
+ <0x01871000 0x004>;
+ reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc",
+ "rmb_base", "restart_reg";
+
+ interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>;
+ vdd_mss-supply = <&pm8937_s1>;
+ vdd_cx-supply = <&pm8937_s2_level>;
+ vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ vdd_mx-supply = <&pm8937_l3_level_ao>;
+ vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ vdd_pll-supply = <&pm8937_l7>;
+ qcom,vdd_pll = <1800000>;
+ vdd_mss-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+
+ clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>,
+ <&gcc GCC_MSS_CFG_AHB_CLK>,
+ <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
+ <&gcc GCC_BOOT_ROM_AHB_CLK>;
+ clock-names = "xo", "iface_clk", "bus_clk", "mem_clk";
+ qcom,proxy-clock-names = "xo";
+ qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk";
+
+ qcom,pas-id = <5>;
+ qcom,pil-mss-memsetup;
+ qcom,firmware-name = "modem";
+ qcom,pil-self-auth;
+ qcom,sequential-fw-load;
+ qcom,override-acc-1 = <0x80800000>;
+ qcom,sysmon-id = <0>;
+ qcom,ssctl-instance-id = <0x12>;
+ qcom,qdsp6v56-1-8-inrush-current;
+ qcom,reset-clk;
+
+ /* Inputs from mss */
+ interrupts-extended = <&modem_smp2p_in 0 0>,
+ <&modem_smp2p_in 1 0>,
+ <&modem_smp2p_in 2 0>,
+ <&modem_smp2p_in 3 0>,
+ <&modem_smp2p_in 7 0>;
+
+ interrupt-names = "qcom,err-fatal",
+ "qcom,err-ready",
+ "qcom,proxy-unvote",
+ "qcom,stop-ack",
+ "qcom,shutdown-ack";
+
+ /* Outputs to mss */
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ memory-region = <&modem_mem>;
+ };
+
+ qcom,lpass@c200000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0xc200000 0x00100>;
+ interrupts = <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>;
+
+ vdd_cx-supply = <&pm8937_s2_level>;
+ qcom,proxy-reg-names = "vdd_cx";
+ qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
+
+ clocks = <&rpmcc CXO_SMD_PIL_PRONTO_CLK>,
+ <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>,
+ <&gcc CRYPTO_CLK_SRC>;
+ clock-names = "xo", "scm_core_clk", "scm_iface_clk",
+ "scm_bus_clk", "scm_core_clk_src";
+ qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",
+ "scm_bus_clk", "scm_core_clk_src";
+ qcom,scm_core_clk_src-freq = <80000000>;
+
+ qcom,mas-crypto = <&mas_crypto>;
+ qcom,pas-id = <1>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <423>;
+ qcom,sysmon-id = <1>;
+ qcom,ssctl-instance-id = <0x14>;
+ qcom,firmware-name = "adsp";
+
+ /* Inputs from lpass */
+ interrupts-extended = <&adsp_smp2p_in 0 0>,
+ <&adsp_smp2p_in 1 0>,
+ <&adsp_smp2p_in 2 0>,
+ <&adsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,err-fatal",
+ "qcom,err-ready",
+ "qcom,proxy-unvote",
+ "qcom,stop-ack";
+
+ /* Outputs to lpass */
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ memory-region = <&adsp_fw_mem>;
+ };
+
+ qcom,pronto@a21b000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x0a21b000 0x3000>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>;
+
+ vdd_pronto_pll-supply = <&pm8937_l7>;
+ proxy-reg-names = "vdd_pronto_pll";
+ vdd_pronto_pll-uV-uA = <1800000 18000>;
+ clocks = <&rpmcc CXO_SMD_PIL_PRONTO_CLK>,
+ <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>,
+ <&gcc CRYPTO_CLK_SRC>;
+
+ clock-names = "xo", "scm_core_clk", "scm_iface_clk",
+ "scm_bus_clk", "scm_core_clk_src";
+ qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",
+ "scm_bus_clk", "scm_core_clk_src";
+ qcom,scm_core_clk_src = <80000000>;
+
+ qcom,mas-crypto = <&mas_crypto>;
+ qcom,pas-id = <6>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <422>;
+ qcom,sysmon-id = <6>;
+ qcom,ssctl-instance-id = <0x13>;
+ qcom,firmware-name = "wcnss";
+
+ /* Inputs from wcnss */
+ interrupts-extended = <&wcnss_smp2p_in 0 0>,
+ <&wcnss_smp2p_in 1 0>,
+ <&wcnss_smp2p_in 2 0>,
+ <&wcnss_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,err-fatal",
+ "qcom,err-ready",
+ "qcom,proxy-unvote",
+ "qcom,stop-ack";
+
+ /* Outputs to wcnss */
+ qcom,smem-states = <&wcnss_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ memory-region = <&wcnss_fw_mem>;
+ };
+
+ qcom,venus@1de0000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x1de0000 0x4000>;
+
+ vdd-supply = <&gdsc_venus>;
+ qcom,proxy-reg-names = "vdd";
+
+ clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
+ <&gcc GCC_VENUS0_AHB_CLK>,
+ <&gcc GCC_VENUS0_AXI_CLK>,
+ <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>,
+ <&gcc CRYPTO_CLK_SRC>;
+
+ clock-names = "core_clk", "iface_clk", "bus_clk",
+ "scm_core_clk", "scm_iface_clk",
+ "scm_bus_clk", "scm_core_clk_src";
+
+ qcom,proxy-clock-names = "core_clk", "iface_clk",
+ "bus_clk", "scm_core_clk",
+ "scm_iface_clk", "scm_bus_clk",
+ "scm_core_clk_src";
+ qcom,scm_core_clk_src-freq = <80000000>;
+
+ qcom,msm-bus,name = "pil-venus";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <63 512 0 0>,
+ <63 512 0 304000>;
+
+ qcom,mas-crypto = <&mas_crypto>;
+ qcom,pas-id = <9>;
+ qcom,proxy-timeout-ms = <100>;
+ qcom,firmware-name = "venus";
+ memory-region = <&venus_mem>;
+ };
+
+ qcom,wcnss-wlan@0a000000 {
+ compatible = "qcom,wcnss_wlan";
+ reg = <0x0a000000 0x280000>,
+ <0xb011008 0x04>,
+ <0x0a21b000 0x3000>,
+ <0x03204000 0x00000100>,
+ <0x03200800 0x00000200>,
+ <0x0a100400 0x00000200>,
+ <0x0a205050 0x00000200>,
+ <0x0a219000 0x00000020>,
+ <0x0a080488 0x00000008>,
+ <0x0a080fb0 0x00000008>,
+ <0x0a08040c 0x00000008>,
+ <0x0a0120a8 0x00000008>,
+ <0x0a012448 0x00000008>,
+ <0x0a080c00 0x00000001>;
+
+ reg-names = "wcnss_mmio", "wcnss_fiq",
+ "pronto_phy_base", "riva_phy_base",
+ "riva_ccu_base", "pronto_a2xb_base",
+ "pronto_ccpu_base", "pronto_saw2_base",
+ "wlan_tx_phy_aborts","wlan_brdg_err_source",
+ "wlan_tx_status", "alarms_txctl",
+ "alarms_tactl", "pronto_mcu_base";
+
+ interrupts = <0 145 IRQ_TYPE_EDGE_RISING>,
+ <0 146 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
+
+ qcom,pronto-vddmx-supply = <&pm8937_l3_level_ao>;
+ qcom,pronto-vddcx-supply = <&pm8937_s2_level>;
+ qcom,pronto-vddpx-supply = <&pm8937_l5>;
+ qcom,iris-vddxo-supply = <&pm8937_l7>;
+ qcom,iris-vddrfa-supply = <&pm8937_l19>;
+ qcom,iris-vddpa-supply = <&pm8937_l9>;
+ qcom,iris-vdddig-supply = <&pm8937_l5>;
+
+ qcom,iris-vddxo-voltage-level = <1800000 0 1800000>;
+ qcom,iris-vddrfa-voltage-level = <1300000 0 1300000>;
+ qcom,iris-vddpa-voltage-level = <3300000 0 3300000>;
+ qcom,iris-vdddig-voltage-level = <1800000 0 1800000>;
+
+ qcom,vddmx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_TURBO
+ RPM_SMD_REGULATOR_LEVEL_NONE
+ RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,vddcx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_NOM
+ RPM_SMD_REGULATOR_LEVEL_NONE
+ RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,vddpx-voltage-level = <1800000 0 1800000>;
+
+ qcom,iris-vddxo-current = <10000>;
+ qcom,iris-vddrfa-current = <100000>;
+ qcom,iris-vddpa-current = <515000>;
+ qcom,iris-vdddig-current = <10000>;
+
+ qcom,pronto-vddmx-current = <0>;
+ qcom,pronto-vddcx-current = <0>;
+ qcom,pronto-vddpx-current = <0>;
+
+ pinctrl-names = "wcnss_default", "wcnss_sleep",
+ "wcnss_gpio_default";
+ pinctrl-0 = <&wcnss_default>;
+ pinctrl-1 = <&wcnss_sleep>;
+ pinctrl-2 = <&wcnss_gpio_default>;
+
+ gpios = <&tlmm 76 0>, <&tlmm 77 0>, <&tlmm 78 0>,
+ <&tlmm 79 0>, <&tlmm 80 0>;
+
+ clocks = <&rpmcc CXO_SMD_WLAN_CLK>,
+ <&rpmcc RPM_SMD_RF_CLK2>,
+ <&rpmcc SNOC_WCNSS_A_CLK>;
+
+ clock-names = "xo", "rf_clk", "snoc_wcnss";
+
+ qcom,snoc-wcnss-clock-freq = <200000000>;
+
+ qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>, <&apps_smsm 12>;
+ qcom,smem-state-names = "tx-enable", "tx-rings-empty", "wake-state";
+
+ qcom,has-autodetect-xo;
+ qcom,is-pronto-v3;
+ qcom,has-pronto-hw;
+ qcom,has-vsys-adc-channel;
+ qcom,wcnss-adc_tm = <&pm8937_adc_tm>;
+ };
+
+ bam_dmux: qcom,bam_dmux@4044000 {
+ compatible = "qcom,bam_dmux";
+ reg = <0x4044000 0x19000>;
+ qcom,rx-ring-size = <32>;
+ qcom,max-rx-mtu = <4096>;
+ qcom,fast-shutdown;
+ qcom,no-cpu-affinity;
+
+ qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>;
+ qcom,smem-state-names = "pwrctrl", "pwrctrlack";
+
+ interrupts-extended =
+ <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smsm 1 IRQ_TYPE_EDGE_BOTH>,
+ <&modem_smsm 11 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "dmux", "ctrl", "ack";
+ };
+
+ ssc_sensors: qcom,msm-ssc-sensors {
+ compatible = "qcom,msm-ssc-sensors";
+ status = "ok";
+ };
+
+};
+
+#include "pm8937-rpm-regulator.dtsi"
+#include "msm8937-regulator.dtsi"
+#include "pm8937.dtsi"
+#include "msm8937-audio.dtsi"
+#include "msm8937-camera.dtsi"
+#include "msm-gdsc-8916.dtsi"
+#include "msm8937-coresight.dtsi"
+#include "msm8937-thermal.dtsi"
+
+&gdsc_venus {
+ clock-names = "bus_clk", "core_clk";
+ clocks = <&gcc GCC_VENUS0_AXI_CLK>,
+ <&gcc GCC_VENUS0_VCODEC0_CLK>;
+ status = "okay";
+};
+
+&gdsc_venus_core0 {
+ qcom,support-hw-trigger;
+ clock-names ="core0_clk";
+ clocks = <&gcc GCC_VENUS0_CORE0_VCODEC0_CLK>;
+ status = "okay";
+};
+
+&gdsc_mdss {
+ clock-names = "core_clk", "bus_clk";
+ clocks = <&gcc GCC_MDSS_MDP_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>;
+ qcom,disallow-clear;
+ status = "okay";
+};
+
+&gdsc_jpeg {
+ clock-names = "core_clk", "bus_clk";
+ clocks = <&gcc GCC_CAMSS_JPEG0_CLK>,
+ <&gcc GCC_CAMSS_JPEG_AXI_CLK>;
+ status = "okay";
+};
+
+&gdsc_vfe {
+ clock-names = "core_clk", "bus_clk", "micro_clk",
+ "csi_clk";
+ clocks = <&gcc GCC_CAMSS_VFE0_CLK>,
+ <&gcc GCC_CAMSS_VFE_AXI_CLK>,
+ <&gcc GCC_CAMSS_MICRO_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>;
+ status = "okay";
+};
+
+&gdsc_vfe1 {
+ clock-names = "core_clk", "bus_clk", "micro_clk",
+ "csi_clk";
+ clocks = <&gcc GCC_CAMSS_VFE1_CLK>,
+ <&gcc GCC_CAMSS_VFE1_AXI_CLK>,
+ <&gcc GCC_CAMSS_MICRO_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE1_CLK>;
+ status = "okay";
+};
+
+&gdsc_cpp {
+ clock-names = "core_clk", "bus_clk";
+ clocks = <&gcc GCC_CAMSS_CPP_CLK>,
+ <&gcc GCC_CAMSS_CPP_AXI_CLK>;
+ status = "okay";
+};
+
+&gdsc_oxili_gx {
+ clock-names = "core_root_clk";
+ clocks =<&gcc GFX3D_CLK_SRC>;
+ qcom,enable-root-clk;
+ qcom,clk-dis-wait-val = <0x5>;
+ status = "okay";
+};
+
+&gdsc_oxili_cx {
+ reg = <0x1859044 0x4>;
+ clock-names = "core_clk";
+ clocks = <&gcc GCC_OXILI_GFX3D_CLK>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/msm8953-wsa881x.dtsi b/arch/arm64/boot/dts/vendor/qcom/msm8953-wsa881x.dtsi
new file mode 100755
index 0000000..009521a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/msm8953-wsa881x.dtsi
@@ -0,0 +1,34 @@
+&slim_msm {
+ tasha_codec {
+ swr_master {
+ compatible = "qcom,swr-wcd";
+ qcom,swr-num-dev = <2>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ wsa881x_211: wsa881x@20170211 {
+ compatible = "qcom,wsa881x";
+ reg = <0x00 0x20170211>;
+ qcom,spkr-sd-n-gpio = <&tlmm 96 0>;
+ };
+
+ wsa881x_212: wsa881x@20170212 {
+ compatible = "qcom,wsa881x";
+ reg = <0x00 0x20170212>;
+ qcom,spkr-sd-n-gpio = <&tlmm 96 0>;
+ };
+
+ wsa881x_213: wsa881x@21170213 {
+ compatible = "qcom,wsa881x";
+ reg = <0x00 0x21170213>;
+ qcom,spkr-sd-n-gpio = <&tlmm 96 0>;
+ };
+
+ wsa881x_214: wsa881x@21170214 {
+ compatible = "qcom,wsa881x";
+ reg = <0x00 0x21170214>;
+ qcom,spkr-sd-n-gpio = <&tlmm 96 0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/orchid-cdp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/orchid-cdp-overlay.dts
new file mode 100755
index 0000000..583452f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/orchid-cdp-overlay.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "orchid-cdp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Orchid CDP";
+ compatible = "qcom,orchid-cdp", "qcom,orchid", "qcom,cdp";
+ qcom,msm-id = <476 0x10000>;
+ qcom,board-id = <1 1>;
+};
+
+/*
+ * overriding adsp-fw-names with empty string
+ * to allow default adsp img load
+ */
+&adsp_loader {
+ adsp-fw-names="";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/orchid-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/orchid-cdp.dts
new file mode 100755
index 0000000..ac9f7a3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/orchid-cdp.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+#include "orchid.dtsi"
+#include "orchid-cdp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Orchid CDP";
+ compatible = "qcom,orchid-cdp", "qcom,orchid", "qcom,cdp";
+ qcom,board-id = <1 1>;
+};
+
+&ufsphy_mem {
+ /delete-property/ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/orchid-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/orchid-cdp.dtsi
new file mode 100755
index 0000000..2d5623c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/orchid-cdp.dtsi
@@ -0,0 +1,89 @@
+#include "lito-cdp.dtsi"
+
+&soc {
+
+};
+
+&usb_qmp_dp_phy {
+ /delete-property/vdd-supply;
+ vdd-supply = <&L11A>;
+};
+
+&sde_dp {
+ vdda-0p9-supply = <&L11A>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_fhd_plus_cmd>;
+};
+
+&sde_dsi1 {
+ status = "disabled";
+};
+
+&mdss_mdp {
+ connectors = <&sde_wb &sde_dsi &sde_dp &sde_rscc>;
+};
+
+&swr0 {
+ wsa883x_0221: wsa883x@02170221 {
+ compatible = "qcom,wsa883x";
+ reg = <0x02 0x02170221>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+ qcom,bolero-handle = <&bolero>;
+
+ cdc-vdd-1p8-supply = <&S4A>;
+ qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-1p8-current = <20000>;
+ qcom,cdc-vdd-1p8-lpm-supported = <1>;
+ qcom,cdc-static-supplies = "cdc-vdd-1p8";
+ };
+
+ wsa883x_0222: wsa883x@02170222 {
+ compatible = "qcom,wsa883x";
+ reg = <0x02 0x02170222>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero>;
+
+ cdc-vdd-1p8-supply = <&S4A>;
+ qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-1p8-current = <20000>;
+ qcom,cdc-vdd-1p8-lpm-supported = <1>;
+ qcom,cdc-static-supplies = "cdc-vdd-1p8";
+ };
+};
+
+&wsa881x_0211 {
+ status = "disabled";
+};
+
+&wsa881x_0212 {
+ status = "disabled";
+};
+
+&wsa881x_0213 {
+ status = "disabled";
+};
+
+&wsa881x_0214 {
+ status = "disabled";
+};
+
+&lito_snd {
+ qcom,model = "lito-orchidmtp-snd-card";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa883x_0221>, <&wsa883x_0222>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight";
+};
+
+&pm8150_rtc {
+ status = "disabled";
+};
+
+&pmk8350_adc_tm {
+ status = "disabled";
+};
+
+&pmk8350_vadc {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/orchid-mtp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/orchid-mtp-overlay.dts
new file mode 100755
index 0000000..ed8a112
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/orchid-mtp-overlay.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "orchid-mtp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Orchid MTP";
+ compatible = "qcom,orchid-mtp", "qcom,orchid", "qcom,mtp";
+ qcom,msm-id = <476 0x10000>;
+ qcom,board-id = <8 0>;
+};
+
+/*
+ * overriding adsp-fw-names with empty string
+ * to allow default adsp img load
+ */
+&adsp_loader {
+ adsp-fw-names="";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/orchid-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/orchid-mtp.dts
new file mode 100755
index 0000000..89a3a48
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/orchid-mtp.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+#include "orchid.dtsi"
+#include "orchid-mtp.dtsi"
+#include "lito-v2-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Orchid MTP";
+ compatible = "qcom,orchid-mtp", "qcom,orchid", "qcom,mtp";
+ qcom,board-id = <8 0>;
+};
+
+&ufsphy_mem {
+ /delete-property/ vdda-phy-always-on;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/orchid-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/orchid-mtp.dtsi
new file mode 100755
index 0000000..0e0172a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/orchid-mtp.dtsi
@@ -0,0 +1,146 @@
+#include "lito-mtp.dtsi"
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&soc {
+
+};
+
+&usb_qmp_dp_phy {
+ /delete-property/vdd-supply;
+ vdd-supply = <&L11A>;
+};
+
+&sde_dp {
+ vdda-0p9-supply = <&L11A>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_sw43404_amoled_fhd_plus_cmd>;
+};
+
+&sde_dsi1 {
+ status = "disabled";
+};
+
+&mdss_mdp {
+ connectors = <&sde_wb &sde_dsi &sde_dp &sde_rscc>;
+};
+
+&swr0 {
+ wsa883x_0221: wsa883x@02170221 {
+ compatible = "qcom,wsa883x";
+ reg = <0x02 0x02170221>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+ qcom,bolero-handle = <&bolero>;
+ cdc-vdd-1p8-supply = <&S4A>;
+
+ qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-1p8-current = <20000>;
+ qcom,cdc-vdd-1p8-lpm-supported = <1>;
+ qcom,cdc-static-supplies = "cdc-vdd-1p8";
+ };
+
+ wsa883x_0222: wsa883x@02170222 {
+ compatible = "qcom,wsa883x";
+ reg = <0x02 0x02170222>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ qcom,bolero-handle = <&bolero>;
+
+ cdc-vdd-1p8-supply = <&S4A>;
+ qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-1p8-current = <20000>;
+ qcom,cdc-vdd-1p8-lpm-supported = <1>;
+ qcom,cdc-static-supplies = "cdc-vdd-1p8";
+ };
+};
+
+&wsa881x_0211 {
+ status = "disabled";
+};
+
+&wsa881x_0212 {
+ status = "disabled";
+};
+
+&wsa881x_0213 {
+ status = "disabled";
+};
+
+&wsa881x_0214 {
+ status = "disabled";
+};
+
+&lito_snd {
+ qcom,model = "lito-orchidmtp-snd-card";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa883x_0221>, <&wsa883x_0222>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight";
+};
+
+
+&pm8150_rtc {
+ status = "disabled";
+};
+
+&pmk8350_adc_tm {
+ status = "disabled";
+};
+
+&pmk8350_vadc {
+ status = "disabled";
+};
+
+&pm7250b_qg {
+ qcom,use-cp-iin-sns;
+};
+
+&pm7250b_vadc {
+ smb1390_therm@e {
+ qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM5_SMB1398_TEMP>;
+ };
+};
+
+&pm7250b_gpios {
+ smb_stat {
+ smb_stat_default: smb_stat_default {
+ pins = "gpio6";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+ power-source = <0>;
+ };
+ };
+};
+
+&qupv3_se9_i2c {
+ qcom,clk-freq-out = <100000>;
+ status = "ok";
+ #include "smb1398.dtsi"
+};
+
+&smb1396 {
+ interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&spmi_bus>;
+ interrupt-names = "smb1396";
+ pinctrl-names = "default";
+ qcom,enable-toggle-stat;
+ pinctrl-0 = <&smb_stat_default>;
+ status = "ok";
+};
+
+&smb1396_div2_cp_master {
+ io-channels = <&pm7250b_vadc ADC_AMUX_THM2>;
+ qcom,parallel-input-mode = <1>; /* USBIN */
+ qcom,parallel-output-mode = <2>; /* VBAT */
+ qcom,min-ilim-ua = <1000000>;
+ status = "ok";
+};
+
+&smb1396_slave {
+ status = "ok";
+};
+
+&smb1396_div2_cp_slave {
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/orchid.dts b/arch/arm64/boot/dts/vendor/qcom/orchid.dts
new file mode 100755
index 0000000..1fcf2cc
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/orchid.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "orchid.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Orchid SoC";
+ compatible = "qcom,orchid";
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/orchid.dtsi b/arch/arm64/boot/dts/vendor/qcom/orchid.dtsi
new file mode 100755
index 0000000..5dfead6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/orchid.dtsi
@@ -0,0 +1,46 @@
+#include "lito-v2.dtsi"
+#include "pmk8350.dtsi"
+#include "magnus.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Orchid";
+ compatible = "qcom,orchid";
+ qcom,msm-id = <476 0x10000>;
+};
+
+&sde_dp {
+ /delete-property/ qcom,mst-enable;
+ qcom,no-mst-encoder;
+};
+
+&mdss_dsi1 {
+ status = "disabled";
+};
+
+&mdss_dsi_phy1 {
+ status = "disabled";
+};
+
+&mdss_dsi1_pll {
+ status = "disabled";
+};
+
+&mdss_mdp {
+ qcom,sde-intf-off = <0x6b000 0x6b800>;
+ qcom,sde-intf-type = "dp", "dsi";
+ qcom,sde-sspp-type = "vig", "dma", "dma", "dma";
+ qcom,sde-sspp-off = <0x5000 0x25000 0x27000 0x29000>;
+ qcom,sde-sspp-xin-id = <0 1 5 9>;
+ qcom,sde-sspp-excl-rect = <1 1 1 1>;
+ qcom,sde-sspp-smart-dma-priority = <4 1 2 3>;
+ qcom,sde-max-per-pipe-bw-kbps = <4700000 4700000 4700000
+ 4700000>;
+ qcom,sde-max-per-pipe-bw-high-kbps = <4700000 4700000 4700000
+ 4700000>;
+ qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>, <0x2b4 8>,
+ <0x2c4 8>;
+};
+
+&llcc {
+ compatible = "qcom,llcc-v2";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm2250-rpm-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm2250-rpm-regulator.dtsi
new file mode 100755
index 0000000..ed8a655
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm2250-rpm-regulator.dtsi
@@ -0,0 +1,439 @@
+&rpm_bus {
+ rpm-regulator-smpa1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_s1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_s2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_s3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa4 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <4>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s4 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_s4";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa4 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <4>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l4 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l4";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa5 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <5>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l5 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l5";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa6 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <6>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l6 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l6";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa7 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <7>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l7 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l7";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa8 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <8>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l8 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l8";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa9 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <9>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l9 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l9";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa10 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <10>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l10 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l10";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa11 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <11>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l11 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l11";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa12 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <12>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l12 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l12";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa13 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <13>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l13 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l13";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa14 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <14>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l14 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l14";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa15 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <15>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l15 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l15";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa16 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <16>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l16 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l16";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa17 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <17>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l17 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l17";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa18 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <18>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l18 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l18";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa19 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <19>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l19 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l19";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa20 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <20>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l20 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l20";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa21 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <21>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l21 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l21";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa22 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <22>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l22 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l22";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm2250.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm2250.dtsi
new file mode 100755
index 0000000..27310ed
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm2250.dtsi
@@ -0,0 +1,492 @@
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/qcom,qpnp-power-on.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ qcom,pm2250@0 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm2250_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "kpdpwr", "resin";
+ qcom,pon-dbc-delay = <15625>;
+ qcom,kpdpwr-sw-debounce;
+ qcom,system-reset;
+ qcom,store-hard-reset-reason;
+
+ qcom,pon_1 {
+ qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
+ qcom,pull-up = <1>;
+ linux,code = <KEY_POWER>;
+ };
+
+ qcom,pon_2 {
+ qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
+ qcom,pull-up = <1>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+
+ pm2250_tz: qcom,temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pm2250_vadc ADC_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ qcom,temperature-threshold-set = <1>;
+ };
+
+ pm2250_vadc: vadc@3100 {
+ compatible = "qcom,spmi-adc5-lite";
+ reg = <0x3100 0x100>;
+ reg-names = "adc5-usr-base";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set";
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+
+ /* Channel nodes */
+ ref_gnd {
+ reg = <ADC_REF_GND>;
+ label = "ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref_1p25 {
+ reg = <ADC_1P25VREF>;
+ label = "vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ die_temp {
+ reg = <ADC_DIE_TEMP>;
+ label = "die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vph_pwr {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vbat_sns {
+ reg = <ADC_VBAT_SNS>;
+ label = "vbat_sns";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ usb_in_v_div_16 {
+ reg = <ADC_USB_IN_V_16>;
+ label = "usb_in_v_div_16";
+ qcom,pre-scaling = <1 16>;
+ };
+
+ chg_temp {
+ reg = <ADC_CHG_TEMP>;
+ label = "chg_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bat_therm {
+ reg = <ADC_BAT_THERM_PU2>;
+ label = "bat_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bat_therm_30k {
+ reg = <ADC_BAT_THERM_PU1>;
+ label = "bat_therm_30k";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bat_therm_400k {
+ reg = <ADC_BAT_THERM_PU3>;
+ label = "bat_therm_400k";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bat_id {
+ reg = <ADC_BAT_ID_PU2>;
+ label = "bat_id";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ die_temp_s3 {
+ reg = <ADC_SBUx>;
+ label = "die_temp_s3";
+ qcom,pre-scaling = <1 3>;
+ qcom,scale-fn-type = <ADC_SCALE_HW_CALIB_PM2250_S3_DIE_TEMP>;
+ };
+ };
+
+
+ pm2250_gpios: pinctrl@c000 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0xa00>;
+ interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>,
+ <0x0 0xc1 0 IRQ_TYPE_NONE>,
+ <0x0 0xc2 0 IRQ_TYPE_NONE>,
+ <0x0 0xc3 0 IRQ_TYPE_NONE>,
+ <0x0 0xc4 0 IRQ_TYPE_NONE>,
+ <0x0 0xc5 0 IRQ_TYPE_NONE>,
+ <0x0 0xc6 0 IRQ_TYPE_NONE>,
+ <0x0 0xc7 0 IRQ_TYPE_NONE>,
+ <0x0 0xc8 0 IRQ_TYPE_NONE>,
+ <0x0 0xc9 0 IRQ_TYPE_NONE>;
+
+ interrupt-names = "pm2250_gpio1", "pm2250_gpio2",
+ "pm2250_gpio3", "pm2250_gpio4",
+ "pm2250_gpio5", "pm2250_gpio6",
+ "pm2250_gpio7", "pm2250_gpio8",
+ "pm2250_gpio9", "pm2250_gpio10";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pm2250_rtc: qcom,pm2250_rtc {
+ compatible = "qcom,pm8941-rtc";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ };
+
+ pm2250_cdc: qcom,pm2250-cdc {
+ compatible = "qcom,pm2250-spmi";
+ };
+
+ pm2250_qg: qpnp,qg {
+ compatible = "qcom,qpnp-qg-lite";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qcom,vbatt-cutoff-mv = <3400>;
+ qcom,vbatt-low-mv = <3500>;
+ qcom,vbatt-low-cold-mv = <3800>;
+ qcom,vbatt-empty-mv = <3200>;
+ qcom,vbatt-empty-cold-mv = <3000>;
+ qcom,s3-entry-fifo-length = <2>;
+
+ qcom,pmic-revid = <&pm2250_revid>;
+ io-channels = <&pm2250_vadc ADC_BAT_THERM_PU2>,
+ <&pm2250_vadc ADC_BAT_ID_PU2>;
+ io-channel-names = "batt-therm", "batt-id";
+
+ qcom,qgauge@4800 {
+ status = "okay";
+ reg = <0x4800 0x100>;
+ interrupts =
+ <0x0 0x48 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x48 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x48 0x5 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "qg-vbat-empty",
+ "qg-fifo-done",
+ "qg-good-ocv";
+ };
+
+ qcom,qg-sdam@b600 {
+ status = "okay";
+ reg = <0xb600 0x100>;
+ };
+ };
+
+ pm2250_charger: qcom,qpnp-smblite {
+ compatible = "qcom,qpnp-smblite";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #cooling-cells = <2>;
+
+ qcom,pmic-revid = <&pm2250_revid>;
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts =
+ <0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x10 0x4 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "chgr-error",
+ "chg-state-change",
+ "buck-oc",
+ "vph-ov";
+ };
+
+ qcom,dcdc@1100 {
+ reg = <0x1100 0x100>;
+ interrupts =
+ <0x0 0x11 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x11 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x11 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x11 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x11 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "otg-fail",
+ "otg-fault",
+ "skip-mode",
+ "input-current-limiting",
+ "switcher-power-ok";
+ };
+
+ qcom,batif@1200 {
+ reg = <0x1200 0x100>;
+ interrupts =
+ <0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 0x4 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "bat-temp",
+ "bat-therm-or-id-missing",
+ "bat-low",
+ "bat-ov",
+ "bsm-active";
+ };
+
+ qcom,usb@1300 {
+ reg = <0x1300 0x100>;
+ interrupts =
+ <0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 0x4 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "usbin-plugin",
+ "usbin-collapse",
+ "usbin-uv",
+ "usbin-ov",
+ "usbin-gtvt",
+ "usbin-icl-change";
+ };
+
+ qcom,typec@1500 {
+ reg = <0x1500 0x100>;
+ interrupts =
+ <0x0 0x15 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x15 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x15 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x15 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x15 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x15 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x15 0x7 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "typec-or-rid-detect-change",
+ "typec-vpd-detect",
+ "typec-cc-state-change",
+ "typec-vbus-change",
+ "typec-attach-detach",
+ "typec-legacy-cable-detect",
+ "typec-try-snk-src-detect";
+ };
+
+ qcom,misc@1600 {
+ reg = <0x1600 0x100>;
+ interrupts =
+ <0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x16 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x16 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x16 0x4 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x16 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x16 0x6 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "wdog-snarl",
+ "wdog-bark",
+ "aicl-fail",
+ "aicl-done",
+ "imp-trigger",
+ "all-chnl-cond-done",
+ "temp-change";
+ };
+
+ qcom,schgm-flashlite@a600 {
+ reg = <0xa600 0x100>;
+ interrupts =
+ <0x0 0xa6 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0xa6 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0xa6 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0xa6 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "flash-state-change",
+ "ilim1-s1",
+ "ilim2-s2",
+ "vreg-ok";
+ };
+ };
+ };
+
+ pm2250_1: qcom,pm2250@1 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm2250_vib: qcom,vibrator@5600 {
+ compatible = "qcom,qpnp-vibrator-ldo";
+ reg = <0x5600 0x100>;
+ qcom,vib-ldo-volt-uv = <3000000>;
+ qcom,disable-overdrive;
+ };
+
+ pm2250_pwm1: qcom,pwms@bc00 {
+ compatible = "qcom,pwm-lpg";
+ reg = <0xbc00 0x100>;
+ reg-names = "lpg-base";
+ qcom,num-lpg-channels = <1>;
+ #pwm-cells = <2>;
+ };
+
+ pm2250_pwm2: qcom,pwms@bd00 {
+ compatible = "qcom,pwm-lpg";
+ reg = <0xbd00 0x100>;
+ reg-names = "lpg-base";
+ qcom,num-lpg-channels = <1>;
+ #pwm-cells = <2>;
+ };
+
+ pm2250_pwm3: qcom,pwms@be00 {
+ compatible = "qcom,pwm-lpg";
+ reg = <0xbe00 0x100>;
+ reg-names = "lpg-base";
+ qcom,num-lpg-channels = <1>;
+ #pwm-cells = <2>;
+ };
+
+ pm2250_rg_leds: qcom,rg_leds {
+ compatible = "pwm-leds";
+
+ red {
+ label = "red";
+ pwms = <&pm2250_pwm1 0 1000000>;
+ max-brightness = <255>;
+ linux,default-trigger = "timer";
+ };
+
+ green {
+ label = "green";
+ pwms = <&pm2250_pwm2 0 1000000>;
+ max-brightness = <255>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ pm2250_flash: qcom,flash_led@d300 {
+ compatible = "qcom,pm2250-flash-led";
+ reg = <0xd300>;
+ interrupts = <0x1 0xd3 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x1 0xd3 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x1 0xd3 0x4 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "led-fault-irq",
+ "all-ramp-down-done-irq",
+ "all-ramp-up-done-irq";
+
+ pm2250_flash0: qcom,flash_0 {
+ label = "flash";
+ qcom,led-name = "led:flash_0";
+ qcom,max-current-ma = <1000>;
+ qcom,default-led-trigger = "flash0_trigger";
+ qcom,id = <0>;
+ qcom,duration-ms = <1280>;
+ qcom,ires-ua = <12500>;
+ };
+
+ pm2250_torch0: qcom,torch_0 {
+ label = "torch";
+ qcom,led-name = "led:torch_0";
+ qcom,max-current-ma = <200>;
+ qcom,default-led-trigger = "torch0_trigger";
+ qcom,id = <0>;
+ qcom,ires-ua = <12500>;
+ };
+
+ pm2250_switch0: qcom,led_switch_0 {
+ label = "switch";
+ qcom,led-name = "led:switch_0";
+ qcom,led-mask = <1>;
+ qcom,default-led-trigger = "switch0_trigger";
+ };
+ };
+
+ bcl_soc: bcl-soc {
+ compatible = "qcom,msm-bcl-soc";
+ #thermal-sensor-cells = <0>;
+ };
+ };
+};
+
+&thermal_zones {
+ pm2250-tz {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm2250_tz>;
+ wake-capable-sensor;
+
+ trips {
+ pm2250_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm2250_trip1: trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+
+ soc {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&bcl_soc>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ pm2250_low_soc: low-soc {
+ temperature = <10>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm6125-rpm-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm6125-rpm-regulator.dtsi
new file mode 100755
index 0000000..b699d86
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm6125-rpm-regulator.dtsi
@@ -0,0 +1,509 @@
+&rpm_bus {
+ /* VDD_APC supply */
+ rpm-regulator-smpa1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "rwmx";
+ qcom,resource-id = <0>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_s1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ /* VDD_CX */
+ rpm-regulator-smpa3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "rwcx";
+ qcom,resource-id = <0>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_s3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ /* VDD_MX */
+ rpm-regulator-smpa5 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "rwmx";
+ qcom,resource-id = <0>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s5 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_s5";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa6 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <6>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s6 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_s6";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa7 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <7>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s7 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_s7";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa8 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <8>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s8 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_s8";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa4 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <4>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l4 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l4";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa5 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <5>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l5 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l5";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa6 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <6>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l6 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l6";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa7 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <7>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l7 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l7";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ /* VDD_WCSS_CX */
+ rpm-regulator-ldoa8 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <8>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l8 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l8";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa9 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <9>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l9 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l9";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa10 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <10>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l10 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l10";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa11 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <11>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l11 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l11";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa12 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <12>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l12 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l12";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa13 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <13>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l13 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l13";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa14 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <14>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l14 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l14";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa15 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <15>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l15 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l15";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa16 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <16>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l16 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l16";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa17 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <17>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l17 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l17";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa18 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <18>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l18 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l18";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa19 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <19>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l19 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l19";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa20 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <20>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l20 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l20";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa21 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <21>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l21 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l21";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa22 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <22>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l22 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l22";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa23 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <23>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l23 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l23";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa24 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <24>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic5-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l24 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm6125_l24";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm6125.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm6125.dtsi
new file mode 100755
index 0000000..a79905c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm6125.dtsi
@@ -0,0 +1,196 @@
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/qcom,qpnp-power-on.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+ qcom,pm6125@0 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x0 0x0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm6125_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "kpdpwr", "resin";
+ qcom,pon-dbc-delay = <15625>;
+ qcom,kpdpwr-sw-debounce;
+ qcom,system-reset;
+ qcom,store-hard-reset-reason;
+
+ qcom,pon_1 {
+ qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
+ qcom,pull-up = <1>;
+ linux,code = <KEY_POWER>;
+ };
+
+ qcom,pon_2 {
+ qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
+ qcom,pull-up = <1>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+
+ pm6125_vadc: vadc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-vdd-reference = <1875>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+
+ /* Channel nodes */
+ ref_gnd {
+ reg = <ADC_REF_GND>;
+ label = "ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref_1p25 {
+ reg = <ADC_1P25VREF>;
+ label = "vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ die_temp {
+ reg = <ADC_DIE_TEMP>;
+ label = "die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vph_pwr {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vcoin {
+ reg = <ADC_VCOIN>;
+ label = "vcoin";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ xo_therm {
+ reg = <ADC_XO_THERM_PU2>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pm6125_adc_tm: adc_tm@3500 {
+ compatible = "qcom,adc-tm5";
+ reg = <0x3500 0x100>;
+ interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "thr-int-en";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ pm6125_tz: qcom,temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ qcom,temperature-threshold-set = <1>;
+ };
+
+ pm6125_clkdiv: clock-controller@5b00 {
+ compatible = "qcom,spmi-clkdiv";
+ reg = <0x5b00 0x100>;
+ #clock-cells = <1>;
+ qcom,num-clkdivs = <1>;
+ clock-output-names = "pm6125_div_clk1";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+ assigned-clocks = <&pm6125_clkdiv 1>;
+ assigned-clock-rates = <9600000>;
+ };
+
+ pm6125_gpios: pinctrl@c000 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0x900>;
+ interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>,
+ <0x0 0xc1 0 IRQ_TYPE_NONE>,
+ <0x0 0xc2 0 IRQ_TYPE_NONE>,
+ <0x0 0xc3 0 IRQ_TYPE_NONE>,
+ <0x0 0xc4 0 IRQ_TYPE_NONE>,
+ <0x0 0xc5 0 IRQ_TYPE_NONE>,
+ <0x0 0xc6 0 IRQ_TYPE_NONE>,
+ <0x0 0xc7 0 IRQ_TYPE_NONE>,
+ <0x0 0xc8 0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm6125_gpio1", "pm6125_gpio2",
+ "pm6125_gpio3", "pm6125_gpio4",
+ "pm6125_gpio5", "pm6125_gpio6",
+ "pm6125_gpio7", "pm6125_gpio8",
+ "pm6125_gpio9";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pm6125_rtc: qcom,pm6125_rtc {
+ compatible = "qcom,pm8941-rtc";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ };
+ };
+
+ qcom,pm6125@1 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x1 0x0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm6125_pwm: qcom,pwms@b300 {
+ status = "disabled";
+ compatible = "qcom,pwm-lpg";
+ reg = <0xb300 0x100>;
+ reg-names = "lpg-base";
+ qcom,num-lpg-channels = <1>;
+ #pwm-cells = <2>;
+ };
+ };
+};
+
+&thermal_zones {
+ pm6125-tz {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm6125_tz>;
+ wake-capable-sensor;
+
+ trips {
+ pm6125_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm6125_trip1: trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm6150l.dtsi
new file mode 100755
index 0000000..4ab08e1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm6150l.dtsi
@@ -0,0 +1,552 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ qcom,pm6150l@4 {
+ compatible = "qcom,spmi-pmic";
+ reg = <4 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm6150l_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ };
+
+ pm6150l_tz: qcom,temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ qcom,temperature-threshold-set = <1>;
+ };
+
+ pm6150l_bcl: bcl@3d00 {
+ compatible = "qcom,bcl-v5";
+ reg = <0x3d00 0x100>;
+ interrupts = <0x4 0x3d 0x0 IRQ_TYPE_NONE>,
+ <0x4 0x3d 0x1 IRQ_TYPE_NONE>,
+ <0x4 0x3d 0x2 IRQ_TYPE_NONE>;
+ interrupt-names = "bcl-lvl0",
+ "bcl-lvl1",
+ "bcl-lvl2";
+ #thermal-sensor-cells = <1>;
+ };
+
+ pm6150l_vadc: vadc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-vdd-reference = <1875>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+
+ /* Channel node */
+ ref_gnd {
+ reg = <ADC_REF_GND>;
+ label = "ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref_1p25 {
+ reg = <ADC_1P25VREF>;
+ label = "vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ die_temp {
+ reg = <ADC_DIE_TEMP>;
+ label = "die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vph_pwr {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+ };
+
+ pm6150l_adc_tm: adc_tm@3500 {
+ compatible = "qcom,adc-tm5";
+ reg = <0x3500 0x100>;
+ interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "thr-int-en";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ pm6150l_clkdiv: clock-controller@5b00 {
+ compatible = "qcom,spmi-clkdiv";
+ reg = <0x5b00 0x100>;
+ #clock-cells = <1>;
+ qcom,num-clkdivs = <1>;
+ clock-output-names = "pm6150l_div_clk1";
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ status = "disabled";
+ };
+
+ pm6150l_gpios: pinctrl@c000 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0xc00>;
+ interrupts = <0x4 0xc0 0 IRQ_TYPE_NONE>,
+ <0x4 0xc1 0 IRQ_TYPE_NONE>,
+ <0x4 0xc2 0 IRQ_TYPE_NONE>,
+ <0x4 0xc3 0 IRQ_TYPE_NONE>,
+ <0x4 0xc4 0 IRQ_TYPE_NONE>,
+ <0x4 0xc5 0 IRQ_TYPE_NONE>,
+ <0x4 0xc6 0 IRQ_TYPE_NONE>,
+ <0x4 0xc7 0 IRQ_TYPE_NONE>,
+ <0x4 0xc8 0 IRQ_TYPE_NONE>,
+ <0x4 0xc9 0 IRQ_TYPE_NONE>,
+ <0x4 0xca 0 IRQ_TYPE_NONE>,
+ <0x4 0xcb 0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm6150l_gpio1", "pm6150l_gpio2",
+ "pm6150l_gpio3", "pm6150l_gpio4",
+ "pm6150l_gpio5", "pm6150l_gpio6",
+ "pm6150l_gpio7", "pm6150l_gpio8",
+ "pm6150l_gpio9", "pm6150l_gpio10",
+ "pm6150l_gpio11", "pm6150l_gpio12";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ qcom,pm6150l@5 {
+ compatible ="qcom,spmi-pmic";
+ reg = <5 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm6150l_pwm_1: qcom,pwms@bc00 {
+ status = "disabled";
+ compatible = "qcom,pwm-lpg";
+ reg = <0xbc00 0x100>;
+ reg-names = "lpg-base";
+ qcom,num-lpg-channels = <1>;
+ #pwm-cells = <2>;
+ };
+
+ pm6150l_lcdb: qcom,lcdb@ec00 {
+ compatible = "qcom,qpnp-lcdb-regulator";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xec00 0x100>;
+ interrupts = <0x5 0xec 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "sc-irq";
+ qcom,pmic-revid = <&pm6150l_revid>;
+ qcom,voltage-step-ramp;
+ status = "disabled";
+
+ lcdb_ldo_vreg: ldo {
+ label = "ldo";
+ regulator-name = "lcdb_ldo";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6000000>;
+ };
+
+ lcdb_ncp_vreg: ncp {
+ label = "ncp";
+ regulator-name = "lcdb_ncp";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6000000>;
+ };
+
+ lcdb_bst_vreg: bst {
+ label = "bst";
+ regulator-name = "lcdb_bst";
+ regulator-min-microvolt = <4700000>;
+ regulator-max-microvolt = <6275000>;
+ };
+ };
+
+ flash_led: qcom,leds@d300 {
+ compatible = "qcom,qpnp-flash-led-v2";
+ status = "okay";
+ reg = <0xd300 0x100>;
+ label = "flash";
+ interrupts = <0x5 0xd3 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x5 0xd3 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x5 0xd3 0x4 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "led-fault-irq",
+ "all-ramp-down-done-irq",
+ "all-ramp-up-done-irq";
+ qcom,hdrm-auto-mode;
+ qcom,short-circuit-det;
+ qcom,open-circuit-det;
+ qcom,vph-droop-det;
+ qcom,thermal-derate-en;
+ qcom,thermal-derate-current = <200 500 1000>;
+ qcom,isc-delay = <192>;
+ qcom,pmic-revid = <&pm6150l_revid>;
+
+ pm6150l_flash0: qcom,flash_0 {
+ label = "flash";
+ qcom,led-name = "led:flash_0";
+ qcom,max-current = <1500>;
+ qcom,default-led-trigger = "flash0_trigger";
+ qcom,id = <0>;
+ qcom,current-ma = <1000>;
+ qcom,duration-ms = <1280>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pm6150l_flash1: qcom,flash_1 {
+ label = "flash";
+ qcom,led-name = "led:flash_1";
+ qcom,max-current = <1500>;
+ qcom,default-led-trigger = "flash1_trigger";
+ qcom,id = <1>;
+ qcom,current-ma = <1000>;
+ qcom,duration-ms = <1280>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pm6150l_flash2: qcom,flash_2 {
+ label = "flash";
+ qcom,led-name = "led:flash_2";
+ qcom,max-current = <750>;
+ qcom,default-led-trigger = "flash2_trigger";
+ qcom,id = <2>;
+ qcom,current-ma = <500>;
+ qcom,duration-ms = <1280>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ status = "disabled";
+ };
+
+ pm6150l_torch0: qcom,torch_0 {
+ label = "torch";
+ qcom,led-name = "led:torch_0";
+ qcom,max-current = <500>;
+ qcom,default-led-trigger = "torch0_trigger";
+ qcom,id = <0>;
+ qcom,current-ma = <180>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pm6150l_torch1: qcom,torch_1 {
+ label = "torch";
+ qcom,led-name = "led:torch_1";
+ qcom,max-current = <500>;
+ qcom,default-led-trigger = "torch1_trigger";
+ qcom,id = <1>;
+ qcom,current-ma = <180>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pm6150l_torch2: qcom,torch_2 {
+ label = "torch";
+ qcom,led-name = "led:torch_2";
+ qcom,max-current = <500>;
+ qcom,default-led-trigger = "torch2_trigger";
+ qcom,id = <2>;
+ qcom,current-ma = <300>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ status = "disabled";
+ };
+
+ pm6150l_switch0: qcom,led_switch_0 {
+ label = "switch";
+ qcom,led-name = "led:switch_0";
+ qcom,led-mask = <1>;
+ qcom,default-led-trigger = "switch0_trigger";
+ };
+
+ pm6150l_switch1: qcom,led_switch_1 {
+ label = "switch";
+ qcom,led-name = "led:switch_1";
+ qcom,led-mask = <2>;
+ qcom,default-led-trigger = "switch1_trigger";
+ };
+
+ pm6150l_switch2: qcom,led_switch_2 {
+ label = "switch";
+ qcom,led-name = "led:switch_2";
+ qcom,led-mask = <3>;
+ qcom,default-led-trigger = "switch2_trigger";
+ };
+ };
+
+ pm6150l_wled: qcom,wled@d800 {
+ compatible = "qcom,pm6150l-spmi-wled";
+ reg = <0xd800 0x100>, <0xd900 0x100>;
+ reg-names = "wled-ctrl-base", "wled-sink-base";
+ label = "backlight";
+ interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x5 0xd8 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x5 0xd8 0x5 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "ovp-irq", "pre-flash-irq",
+ "flash-irq";
+ qcom,pmic-revid = <&pm6150l_revid>;
+ qcom,auto-calibration;
+ status = "disabled";
+
+ wled_flash: qcom,wled-flash {
+ label = "flash";
+ qcom,default-led-trigger = "wled_flash";
+ };
+
+ wled_torch: qcom,wled-torch {
+ label = "torch";
+ qcom,default-led-trigger = "wled_torch";
+ qcom,wled-torch-timer = <1200>;
+ };
+
+ wled_switch: qcom,wled-switch {
+ label = "switch";
+ qcom,default-led-trigger = "wled_switch";
+ };
+ };
+
+ pm6150l_lpg: qcom,pwms@b100 {
+ compatible = "qcom,pwm-lpg";
+ reg = <0xb100 0x300>, <0xb000 0x100>;
+ reg-names = "lpg-base", "lut-base";
+ #pwm-cells = <2>;
+ qcom,num-lpg-channels = <3>;
+ qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100
+ 90 80 70 60 50 40 30 20 10 0>;
+ lpg1 {
+ qcom,lpg-chan-id = <1>;
+ qcom,ramp-step-ms = <100>;
+ qcom,ramp-pause-hi-count = <2>;
+ qcom,ramp-pause-lo-count = <2>;
+ qcom,ramp-low-index = <0>;
+ qcom,ramp-high-index = <20>;
+ qcom,ramp-from-low-to-high;
+ qcom,ramp-pattern-repeat;
+ };
+
+ lpg2 {
+ qcom,lpg-chan-id = <2>;
+ qcom,ramp-step-ms = <100>;
+ qcom,ramp-pause-hi-count = <2>;
+ qcom,ramp-pause-lo-count = <2>;
+ qcom,ramp-low-index = <0>;
+ qcom,ramp-high-index = <20>;
+ qcom,ramp-from-low-to-high;
+ qcom,ramp-pattern-repeat;
+ };
+
+ lpg3 {
+ qcom,lpg-chan-id = <3>;
+ qcom,ramp-step-ms = <100>;
+ qcom,ramp-pause-hi-count = <2>;
+ qcom,ramp-pause-lo-count = <2>;
+ qcom,ramp-low-index = <0>;
+ qcom,ramp-high-index = <20>;
+ qcom,ramp-from-low-to-high;
+ qcom,ramp-pattern-repeat;
+ };
+ };
+
+ pm6150l_rgb_led: qcom,leds@d000 {
+ compatible = "qcom,tri-led";
+ reg = <0xd000 0x100>;
+ red {
+ label = "red";
+ pwms = <&pm6150l_lpg 0 1000000>;
+ led-sources = <0>;
+ linux,default-trigger = "timer";
+ };
+
+ green {
+ label = "green";
+ pwms = <&pm6150l_lpg 1 1000000>;
+ led-sources = <1>;
+ linux,default-trigger = "timer";
+ };
+
+ blue {
+ label = "blue";
+ pwms = <&pm6150l_lpg 2 1000000>;
+ led-sources = <2>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ pm6150a_amoled: qcom,amoled {
+ compatible = "qcom,qpnp-amoled-regulator";
+ status = "disabled";
+
+ oledb_vreg: oledb@e000 {
+ reg = <0xe000 0x100>;
+ reg-names = "oledb_base";
+ regulator-name = "oledb";
+ regulator-min-microvolt = <4925000>;
+ regulator-max-microvolt = <8100000>;
+ qcom,swire-control;
+ };
+
+ ab_vreg: ab@de00 {
+ reg = <0xde00 0x100>;
+ reg-names = "ab_base";
+ regulator-name = "ab";
+ regulator-min-microvolt = <4600000>;
+ regulator-max-microvolt = <6100000>;
+ qcom,swire-control;
+ };
+
+ ibb_vreg: ibb@dc00 {
+ reg = <0xdc00 0x100>;
+ reg-names = "ibb_base";
+ regulator-name = "ibb";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <5400000>;
+ qcom,swire-control;
+ };
+ };
+ };
+};
+
+&thermal_zones {
+ pm6150l_temp_alarm: pm6150l-tz {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm6150l_tz>;
+ wake-capable-sensor;
+
+ trips {
+ pm6150l_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm6150l_trip1: trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm6150l-vph-lvl0 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&pm6150l_bcl 2>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ vph_lvl0: vph-lvl0 {
+ temperature = <3000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm6150l-vph-lvl1 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&pm6150l_bcl 3>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ vph_lvl1:vph-lvl1 {
+ temperature = <2750>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm6150l-vph-lvl2 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&pm6150l_bcl 4>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ vph_lvl2:vph-lvl2 {
+ temperature = <2500>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm6150l-bcl-lvl0 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm6150l_bcl 5>;
+ wake-capable-sensor;
+
+ trips {
+ l_bcl_lvl0: l-bcl-lvl0 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm6150l-bcl-lvl1 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm6150l_bcl 6>;
+ wake-capable-sensor;
+
+ trips {
+ l_bcl_lvl1: l-bcl-lvl1 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm6150l-bcl-lvl2 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm6150l_bcl 7>;
+ wake-capable-sensor;
+
+ trips {
+ l_bcl_lvl2: l-bcl-lvl2 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm6350.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm6350.dtsi
new file mode 100755
index 0000000..d74f35b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm6350.dtsi
@@ -0,0 +1,132 @@
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/qcom,qpnp-power-on.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ qcom,pm6350@0 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm6350_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "kpdpwr", "resin";
+ qcom,pon-dbc-delay = <15625>;
+ qcom,kpdpwr-sw-debounce;
+ qcom,system-reset;
+ qcom,store-hard-reset-reason;
+
+ qcom,pon_1 {
+ qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
+ qcom,pull-up;
+ linux,code = <KEY_POWER>;
+ };
+
+ qcom,pon_2 {
+ qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
+ qcom,pull-up;
+ linux,code = <KEY_VOLUMEDOWN>;
+ };
+ };
+
+ pm6350_tz: qcom,temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ qcom,temperature-threshold-set = <1>;
+ };
+
+ pm6350_clkdiv: clock-controller@5b00 {
+ compatible = "qcom,spmi-clkdiv";
+ reg = <0x5b00 0x100>;
+ #clock-cells = <1>;
+ qcom,num-clkdivs = <1>;
+ clock-output-names = "pm6350_div_clk1";
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ status = "disabled";
+ };
+
+ pm6350_gpios: pinctrl@c000 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0x900>;
+ interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>,
+ <0x0 0xc1 0 IRQ_TYPE_NONE>,
+ <0x0 0xc2 0 IRQ_TYPE_NONE>,
+ <0x0 0xc3 0 IRQ_TYPE_NONE>,
+ <0x0 0xc4 0 IRQ_TYPE_NONE>,
+ <0x0 0xc5 0 IRQ_TYPE_NONE>,
+ <0x0 0xc6 0 IRQ_TYPE_NONE>,
+ <0x0 0xc7 0 IRQ_TYPE_NONE>,
+ <0x0 0xc8 0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm6350_gpio1", "pm6350_gpio2",
+ "pm6350_gpio3", "pm6350_gpio4",
+ "pm6350_gpio5", "pm6350_gpio6",
+ "pm6350_gpio7", "pm6350_gpio8",
+ "pm6350_gpio9";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ qcom,pm6350@1 {
+ compatible ="qcom,spmi-pmic";
+ reg = <1 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm6350_pwm: qcom,pwms@6000 {
+ status = "disabled";
+ compatible = "qcom,pwm-lpg";
+ reg = <0x6000 0x100>;
+ reg-names = "lpg-base";
+ qcom,num-lpg-channels = <1>;
+ #pwm-cells = <2>;
+ };
+ };
+};
+
+&thermal_zones {
+ pm6350_tz {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm6350_tz>;
+ wake-capable-sensor;
+
+ trips {
+ pm6350_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm6350_trip1: trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm6350_trip2: trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm660-rpm-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm660-rpm-regulator.dtsi
new file mode 100755
index 0000000..a026072
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm660-rpm-regulator.dtsi
@@ -0,0 +1,403 @@
+&rpm_bus {
+ rpm-regulator-smpa1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_s1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_s2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_s3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa4 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <4>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s4 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_s4";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa5 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <5>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s5 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_s5";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa6 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <6>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s6 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_s6";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa5 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <5>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l5 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l5";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa6 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <6>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l6 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l6";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa7 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <7>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l7 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l7";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa8 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <8>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l8 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l8";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa9 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <9>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l9 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l9";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa10 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <10>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l10 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l10";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa11 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <11>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l11 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l11";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa12 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <12>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l12 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l12";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa13 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <13>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l13 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l13";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa14 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <14>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l14 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l14";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa15 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <15>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l15 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l15";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa16 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <16>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l16 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l16";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa17 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <17>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l17 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l17";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa18 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <18>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l18 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l18";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa19 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <19>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ qcom,hpm-min-load = <10000>;
+ status = "disabled";
+
+ regulator-l19 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l19";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm660.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm660.dtsi
new file mode 100755
index 0000000..a36f102
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm660.dtsi
@@ -0,0 +1,557 @@
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&spmi_bus {
+ qcom,pm660@0 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm660_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ qcom,fab-id-valid;
+ qcom,tp-rev-valid;
+ };
+
+ pm660_misc: qcom,misc@900 {
+ compatible = "qcom,qpnp-misc";
+ reg = <0x900 0x100>;
+ };
+
+ pm660_pon: qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>,
+ <0x0 0x8 0x1 IRQ_TYPE_NONE>,
+ <0x0 0x8 0x4 IRQ_TYPE_NONE>,
+ <0x0 0x8 0x5 IRQ_TYPE_NONE>;
+ interrupt-names = "kpdpwr", "resin",
+ "resin-bark", "kpdpwr-resin-bark";
+ qcom,pon-dbc-delay = <15625>;
+ qcom,kpdpwr-sw-debounce;
+ qcom,system-reset;
+ qcom,store-hard-reset-reason;
+
+ qcom,pon_1 {
+ qcom,pon-type = <0>;
+ qcom,pull-up = <1>;
+ linux,code = <116>;
+ };
+
+ qcom,pon_2 {
+ qcom,pon-type = <1>;
+ qcom,pull-up = <1>;
+ linux,code = <114>;
+ };
+ };
+
+ pm660_tz: qcom,temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+ #thermal-sensor-cells = <0>;
+ qcom,temperature-threshold-set = <1>;
+ };
+
+ pm660_gpios: pinctrl@c000 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0xd00>;
+ interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>,
+ <0x0 0xc1 0 IRQ_TYPE_NONE>,
+ <0x0 0xc2 0 IRQ_TYPE_NONE>,
+ <0x0 0xc3 0 IRQ_TYPE_NONE>,
+ <0x0 0xc4 0 IRQ_TYPE_NONE>,
+ <0x0 0xc5 0 IRQ_TYPE_NONE>,
+ <0x0 0xc6 0 IRQ_TYPE_NONE>,
+ <0x0 0xc7 0 IRQ_TYPE_NONE>,
+ <0x0 0xc8 0 IRQ_TYPE_NONE>,
+ <0x0 0xc9 0 IRQ_TYPE_NONE>,
+ <0x0 0xca 0 IRQ_TYPE_NONE>,
+ <0x0 0xcb 0 IRQ_TYPE_NONE>,
+ <0x0 0xcc 0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm660_gpio1", "pm660_gpio2",
+ "pm660_gpio3", "pm660_gpio4",
+ "pm660_gpio5", "pm660_gpio6",
+ "pm660_gpio7", "pm660_gpio8",
+ "pm660_gpio9", "pm660_gpio10",
+ "pm660_gpio11", "pm660_gpio12",
+ "pm660_gpio13";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pm660_rtc: qcom,pm660_rtc {
+ compatible = "qcom,pm8941-rtc";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ };
+
+ pm660_pbs: qcom,pbs@7400 {
+ compatible = "qcom,qpnp-pbs";
+ reg = <0x7400 0x100>;
+ status = "disabled";
+ };
+
+ pm660_vadc: vadc@3100 {
+ compatible = "qcom,spmi-adc-rev2";
+ reg = <0x3100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set";
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+
+ /* Channel nodes */
+ die_temp {
+ reg = <ADC_DIE_TEMP>;
+ label = "die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_gnd {
+ reg = <ADC_REF_GND>;
+ label = "ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref_1p25 {
+ reg = <ADC_1P25VREF>;
+ label = "vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+
+ vph_pwr {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vcoin {
+ reg = <ADC_VCOIN>;
+ label = "vcoin";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ xo_therm {
+ reg = <ADC_XO_THERM_PU2>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ msm_therm{
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "msm_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ quiet_therm{
+ reg = <ADC_AMUX_THM5_PU2>;
+ label = "quiet_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ emmc_therm{
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "emmc_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm0{
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "pa_therm0";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ drax_temp{
+ reg = <ANA_IN>;
+ label = "drax_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pm660_charger: qcom,qpnp-smb2 {
+ compatible = "qcom,qpnp-smb2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qcom,pmic-revid = <&pm660_revid>;
+
+ io-channels = <&pm660_rradc 8>,
+ <&pm660_rradc 10>,
+ <&pm660_rradc 3>,
+ <&pm660_rradc 4>;
+ io-channel-names = "charger_temp",
+ "charger_temp_max",
+ "usbin_i",
+ "usbin_v";
+
+ qcom,wipower-max-uw = <5000000>;
+ dpdm-supply = <&qusb_phy0>;
+
+ qcom,thermal-mitigation
+ = <3000000 2500000 2000000 1500000
+ 1000000 500000>;
+
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts =
+ <0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x10 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x10 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x10 0x4 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "chg-error",
+ "chg-state-change",
+ "step-chg-state-change",
+ "step-chg-soc-update-fail",
+ "step-chg-soc-update-request";
+ };
+
+ qcom,otg@1100 {
+ reg = <0x1100 0x100>;
+ interrupts = <0x0 0x11 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x11 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x11 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x11 0x3 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "otg-fail",
+ "otg-overcurrent",
+ "otg-oc-dis-sw-sts",
+ "testmode-change-detect";
+ };
+
+ qcom,bat-if@1200 {
+ reg = <0x1200 0x100>;
+ interrupts =
+ <0x0 0x12 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 0x5 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "bat-temp",
+ "bat-ocp",
+ "bat-ov",
+ "bat-low",
+ "bat-therm-or-id-missing",
+ "bat-terminal-missing";
+ };
+
+ qcom,usb-chgpth@1300 {
+ reg = <0x1300 0x100>;
+ interrupts =
+ <0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x13 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x13 0x7 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "usbin-collapse",
+ "usbin-lt-3p6v",
+ "usbin-uv",
+ "usbin-ov",
+ "usbin-plugin",
+ "usbin-src-change",
+ "usbin-icl-change",
+ "type-c-change";
+ };
+
+ qcom,dc-chgpth@1400 {
+ reg = <0x1400 0x100>;
+ interrupts =
+ <0x0 0x14 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x14 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x14 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x14 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x14 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x14 0x5 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x14 0x6 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "dcin-collapse",
+ "dcin-lt-3p6v",
+ "dcin-uv",
+ "dcin-ov",
+ "dcin-plugin",
+ "div2-en-dg",
+ "dcin-icl-change";
+ };
+
+ qcom,chgr-misc@1600 {
+ reg = <0x1600 0x100>;
+ interrupts =
+ <0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x16 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x16 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x16 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x16 0x5 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x16 0x6 IRQ_TYPE_EDGE_FALLING>,
+ <0x0 0x16 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "wdog-snarl",
+ "wdog-bark",
+ "aicl-fail",
+ "aicl-done",
+ "high-duty-cycle",
+ "input-current-limiting",
+ "temperature-change",
+ "switcher-power-ok";
+ };
+ };
+
+ pm660_pdphy: qcom,usb-pdphy@1700 {
+ compatible = "qcom,qpnp-pdphy";
+ reg = <0x1700 0x100>;
+ vdd-pdphy-supply = <&pm660l_l7>;
+ vbus-supply = <&smb2_vbus>;
+ vconn-supply = <&smb2_vconn>;
+ interrupts = <0x0 0x17 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x17 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x17 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x17 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x17 0x4 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x17 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x17 0x6 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "sig-tx",
+ "sig-rx",
+ "msg-tx",
+ "msg-rx",
+ "msg-tx-failed",
+ "msg-tx-discarded",
+ "msg-rx-discarded";
+
+ qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */
+ <9000 3000>; /* 9V @ 3A */
+ qcom,no-usb3-dp-concurrency;
+ qcom,pd-20-source-only;
+ };
+
+ pm660_adc_tm: vadc@3400 {
+ compatible = "qcom,adc-tm-rev2";
+ reg = <0x3400 0x100>;
+ interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "thr-int-en";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ qcom,pmic-revid = <&pm660_revid>;
+ };
+
+ pm660_rradc: rradc@4500 {
+ compatible = "qcom,rradc";
+ reg = <0x4500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ qcom,pmic-revid = <&pm660_revid>;
+ };
+
+ pm660_fg: qpnp,fg {
+ compatible = "qcom,fg-gen3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,pmic-revid = <&pm660_revid>;
+ io-channels = <&pm660_rradc 0>,
+ <&pm660_rradc 7>;
+ io-channel-names = "rradc_batt_id",
+ "rradc_die_temp";
+ qcom,rradc-base = <0x4500>;
+ qcom,fg-esr-timer-awake = <96 96>;
+ qcom,fg-esr-timer-asleep = <256 256>;
+ qcom,fg-esr-timer-charging = <0 96>;
+ qcom,cycle-counter-en;
+ status = "okay";
+
+ qcom,fg-batt-soc@4000 {
+ status = "okay";
+ reg = <0x4000 0x100>;
+ interrupts = <0x0 0x40 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x40 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x40 0x2
+ IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x40 0x3
+ IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x40 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x40 0x5
+ IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x40 0x6 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x40 0x7 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "soc-update",
+ "soc-ready",
+ "bsoc-delta",
+ "msoc-delta",
+ "msoc-low",
+ "msoc-empty",
+ "msoc-high",
+ "msoc-full";
+ };
+
+ qcom,fg-batt-info@4100 {
+ status = "okay";
+ reg = <0x4100 0x100>;
+ interrupts = <0x0 0x41 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x41 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x41 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x41 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x41 0x6 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "vbatt-pred-delta",
+ "vbatt-low",
+ "esr-delta",
+ "batt-missing",
+ "batt-temp-delta";
+ };
+
+ qcom,fg-memif@4400 {
+ status = "okay";
+ reg = <0x4400 0x100>;
+ interrupts = <0x0 0x44 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x44 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x44 0x2 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "ima-rdy",
+ "mem-xcp",
+ "dma-grant";
+ };
+ };
+
+ bcl_sensor:bcl@4200 {
+ compatible = "qcom,msm-bcl-lmh";
+ reg = <0x4200 0xff>,
+ <0x4300 0xff>;
+ reg-names = "fg_user_adc",
+ "fg_lmh";
+ interrupts = <0x0 0x42 0x0 IRQ_TYPE_NONE>,
+ <0x0 0x42 0x1 IRQ_TYPE_NONE>,
+ <0x0 0x42 0x2 IRQ_TYPE_NONE>,
+ <0x0 0x42 0x3 IRQ_TYPE_NONE>,
+ <0x0 0x42 0x4 IRQ_TYPE_NONE>;
+ interrupt-names = "bcl-high-ibat",
+ "bcl-very-high-ibat",
+ "bcl-low-vbat",
+ "bcl-very-low-vbat",
+ "bcl-crit-low-vbat";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ qcom,pm660@1 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm660_haptics: qcom,haptic@c000 {
+ compatible = "qcom,pm660-haptics";
+ reg = <0xc000 0x100>;
+ interrupts = <0x1 0xc0 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x1 0xc0 0x1 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "hap-sc-irq", "hap-play-irq";
+ qcom,actuator-type = "lra";
+ qcom,vmax-mv = <3200>;
+ qcom,play-rate-us = <6667>;
+ qcom,lra-resonance-sig-shape = "sine";
+ qcom,lra-auto-resonance-mode = "qwd";
+ qcom,lra-allow-variable-play-rate;
+
+ wf_0 {
+ /* CLICK */
+ qcom,effect-id = <0>;
+ qcom,wf-vmax-mv = <3600>;
+ qcom,wf-pattern = [3e 3e 3e];
+ qcom,wf-play-rate-us = <6667>;
+ qcom,wf-brake-pattern = [01 00 00 00];
+ qcom,lra-auto-resonance-disable;
+ };
+ wf_1 {
+ /* DOUBLE CLICK */
+ qcom,effect-id = <1>;
+ qcom,wf-vmax-mv = <3600>;
+ qcom,wf-pattern = [7e 7e 02 02 02 02 02 02];
+ qcom,wf-play-rate-us = <7143>;
+ qcom,wf-repeat-count = <2>;
+ qcom,wf-s-repeat-count = <1>;
+ qcom,lra-auto-resonance-disable;
+ };
+ wf_2 {
+ /* TICK */
+ qcom,effect-id = <2>;
+ qcom,wf-vmax-mv = <3600>;
+ qcom,wf-pattern = [7e 7e];
+ qcom,wf-play-rate-us = <4000>;
+ qcom,lra-auto-resonance-disable;
+ };
+ wf_3 {
+ /* THUD */
+ qcom,effect-id = <3>;
+ qcom,wf-vmax-mv = <3600>;
+ qcom,wf-pattern = [7e 7e 7e];
+ qcom,wf-play-rate-us = <6667>;
+ qcom,lra-auto-resonance-disable;
+ };
+ wf_4 {
+ /* POP */
+ qcom,effect-id = <4>;
+ qcom,wf-vmax-mv = <3600>;
+ qcom,wf-pattern = [7e 7e];
+ qcom,wf-play-rate-us = <5000>;
+ qcom,lra-auto-resonance-disable;
+ };
+ wf_5 {
+ /* HEAVY CLICK */
+ qcom,effect-id = <5>;
+ qcom,wf-vmax-mv = <3600>;
+ qcom,wf-pattern = [7e 7e 7e];
+ qcom,wf-play-rate-us = <6667>;
+ qcom,wf-brake-pattern = [03 00 00 00];
+ qcom,lra-auto-resonance-disable;
+ };
+ };
+ };
+};
+
+&thermal_zones {
+ pm660_temp_alarm: pm660-tz {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm660_tz>;
+ wake-capable-sensor;
+
+ trips {
+ pm660_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ pm660_trip1: trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ pm660_trip2: trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm660l-rpm-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm660l-rpm-regulator.dtsi
new file mode 100755
index 0000000..fcb1d95
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm660l-rpm-regulator.dtsi
@@ -0,0 +1,237 @@
+&rpm_bus {
+ rpm-regulator-smpb1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpb";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <1>;
+ status = "disabled";
+
+ regulator-s1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_s1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpb2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpb";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <1>;
+ status = "disabled";
+
+ regulator-s2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_s2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpb3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "rwcx";
+ qcom,resource-id = <0>;
+ qcom,regulator-type = <1>;
+ status = "disabled";
+
+ regulator-s3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_s3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpb5 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "rwmx";
+ qcom,resource-id = <0>;
+ qcom,regulator-type = <1>;
+ status = "disabled";
+
+ regulator-s5 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_s5";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldob1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldob";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_l1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldob2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldob";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_l2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldob3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldob";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_l3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldob4 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldob";
+ qcom,resource-id = <4>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l4 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_l4";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldob5 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldob";
+ qcom,resource-id = <5>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l5 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_l5";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldob6 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldob";
+ qcom,resource-id = <6>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l6 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_l6";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldob7 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldob";
+ qcom,resource-id = <7>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l7 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_l7";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldob8 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldob";
+ qcom,resource-id = <8>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l8 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_l8";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldob9 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "rwlc";
+ qcom,resource-id = <0>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l9 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_l9";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldob10 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "rwlm";
+ qcom,resource-id = <0>;
+ qcom,regulator-type = <0>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l10 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_l10";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-bobb {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "bobb";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <4>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-bob {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_bob";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm660l.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm660l.dtsi
new file mode 100755
index 0000000..e5fa849
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm660l.dtsi
@@ -0,0 +1,379 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/msm/power-on.h>
+
+&spmi_bus {
+ qcom,pm660l@2 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x2 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm660l_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ pm660l_pbs: qcom,pbs@7300 {
+ compatible = "qcom,qpnp-pbs";
+ reg = <0x7300 0x100>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ qcom,secondary-pon-reset;
+ qcom,hard-reset-poweroff-type =
+ <PON_POWER_OFF_SHUTDOWN>;
+ };
+
+ pm660l_tz: qcom,temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+ #thermal-sensor-cells = <0>;
+ qcom,temperature-threshold-set = <1>;
+ };
+
+ pm660l_gpios: pinctrl@c000 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0xc00>;
+ interrupts = <0x2 0xc0 0 IRQ_TYPE_NONE>,
+ <0x2 0xc1 0 IRQ_TYPE_NONE>,
+ <0x2 0xc2 0 IRQ_TYPE_NONE>,
+ <0x2 0xc3 0 IRQ_TYPE_NONE>,
+ <0x2 0xc4 0 IRQ_TYPE_NONE>,
+ <0x2 0xc5 0 IRQ_TYPE_NONE>,
+ <0x2 0xc6 0 IRQ_TYPE_NONE>,
+ <0x2 0xc7 0 IRQ_TYPE_NONE>,
+ <0x2 0xc8 0 IRQ_TYPE_NONE>,
+ <0x2 0xc9 0 IRQ_TYPE_NONE>,
+ <0x2 0xca 0 IRQ_TYPE_NONE>,
+ <0x2 0xcb 0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm660l_gpio1", "pm660l_gpio2",
+ "pm660l_gpio3", "pm660l_gpio4",
+ "pm660l_gpio5", "pm660l_gpio6",
+ "pm660l_gpio7", "pm660l_gpio8",
+ "pm660l_gpio9", "pm660l_gpio10",
+ "pm660l_gpio11", "pm660l_gpio12";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ pm660l_3: qcom,pm660l@3 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm660l_lpg: qcom,pwms@b100 {
+ compatible = "qcom,pwm-lpg";
+ reg = <0xb100 0x300>, <0xb000 0x100>;
+ reg-names = "lpg-base", "lut-base";
+ #pwm-cells = <2>;
+ qcom,num-lpg-channels = <3>;
+ qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100
+ 90 80 70 60 50 40 30 20 10 0>;
+
+ lpg1 {
+ qcom,lpg-chan-id = <1>;
+ qcom,ramp-step-ms = <100>;
+ qcom,ramp-pause-hi-count = <2>;
+ qcom,ramp-pause-lo-count = <2>;
+ qcom,ramp-low-index = <0>;
+ qcom,ramp-high-index = <20>;
+ qcom,ramp-from-low-to-high;
+ qcom,ramp-pattern-repeat;
+ };
+ lpg2 {
+ qcom,lpg-chan-id = <2>;
+ qcom,ramp-step-ms = <100>;
+ qcom,ramp-pause-hi-count = <2>;
+ qcom,ramp-pause-lo-count = <2>;
+ qcom,ramp-low-index = <0>;
+ qcom,ramp-high-index = <20>;
+ qcom,ramp-from-low-to-high;
+ qcom,ramp-pattern-repeat;
+ };
+
+ lpg3 {
+ qcom,lpg-chan-id = <3>;
+ qcom,ramp-step-ms = <100>;
+ qcom,ramp-pause-hi-count = <2>;
+ qcom,ramp-pause-lo-count = <2>;
+ qcom,ramp-low-index = <0>;
+ qcom,ramp-high-index = <20>;
+ qcom,ramp-from-low-to-high;
+ qcom,ramp-pattern-repeat;
+ };
+ };
+
+ pm660l_pwm: qcom,pwms@b400 {
+ compatible = "qcom,pwm-lpg";
+ reg = <0xb400 0x100>;
+ reg-names = "lpg-base";
+ #pwm-cells = <2>;
+ qcom,num-lpg-channels = <1>;
+ };
+
+ pm660l_rgb_led: qcom,leds@d000 {
+ compatible = "qcom,tri-led";
+ reg = <0xd000 0x100>;
+ red {
+ label = "red";
+ pwms = <&pm660l_lpg 2 1000000>;
+ led-sources = <0>;
+ linux,default-trigger = "timer";
+ };
+ green {
+ label = "green";
+ pwms = <&pm660l_lpg 1 1000000>;
+ led-sources = <1>;
+ linux,default-trigger = "timer";
+ };
+ blue {
+ label = "blue";
+ pwms = <&pm660l_lpg 0 1000000>;
+ led-sources = <2>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ pm660l_wled: qcom,leds@d800 {
+ compatible = "qcom,pm660l-spmi-wled";
+ reg = <0xd800 0x100>,
+ <0xd900 0x100>;
+ reg-names = "wled-ctrl-base",
+ "wled-sink-base";
+ interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ovp-irq";
+ label = "backlight";
+ qcom,pmic-revid = <&pm660l_revid>;
+ qcom,auto-calibration;
+ qcom,sync-dly = <800>;
+ status = "ok";
+ };
+
+ flash_led: qcom,leds@d300 {
+ compatible = "qcom,qpnp-flash-led-v2";
+ reg = <0xd300 0x100>;
+ label = "flash";
+ interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x3 0xd3 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x3 0xd3 0x4 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "led-fault-irq",
+ "all-ramp-down-done-irq",
+ "all-ramp-up-done-irq";
+ qcom,hdrm-auto-mode;
+ qcom,short-circuit-det;
+ qcom,open-circuit-det;
+ qcom,vph-droop-det;
+ qcom,thermal-derate-en;
+ qcom,thermal-derate-current = <200 500 1000>;
+ qcom,isc-delay = <192>;
+ qcom,pmic-revid = <&pm660l_revid>;
+
+ pm660l_flash0: qcom,flash_0 {
+ label = "flash";
+ qcom,led-name = "led:flash_0";
+ qcom,max-current = <1500>;
+ qcom,default-led-trigger = "flash0_trigger";
+ qcom,id = <0>;
+ qcom,current-ma = <1000>;
+ qcom,duration-ms = <1280>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pm660l_flash1: qcom,flash_1 {
+ label = "flash";
+ qcom,led-name = "led:flash_1";
+ qcom,max-current = <1500>;
+ qcom,default-led-trigger = "flash1_trigger";
+ qcom,id = <1>;
+ qcom,current-ma = <1000>;
+ qcom,duration-ms = <1280>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pm660l_flash2: qcom,flash_2 {
+ label = "flash";
+ qcom,led-name = "led:flash_2";
+ qcom,max-current = <750>;
+ qcom,default-led-trigger = "flash2_trigger";
+ qcom,id = <2>;
+ qcom,current-ma = <500>;
+ qcom,duration-ms = <1280>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pm660l_torch0: qcom,torch_0 {
+ label = "torch";
+ qcom,led-name = "led:torch_0";
+ qcom,max-current = <500>;
+ qcom,default-led-trigger = "torch0_trigger";
+ qcom,id = <0>;
+ qcom,current-ma = <300>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pm660l_torch1: qcom,torch_1 {
+ label = "torch";
+ qcom,led-name = "led:torch_1";
+ qcom,max-current = <500>;
+ qcom,default-led-trigger = "torch1_trigger";
+ qcom,id = <1>;
+ qcom,current-ma = <300>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pm660l_torch2: qcom,torch_2 {
+ label = "torch";
+ qcom,led-name = "led:torch_2";
+ qcom,max-current = <500>;
+ qcom,default-led-trigger = "torch2_trigger";
+ qcom,id = <2>;
+ qcom,current-ma = <300>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pm660l_switch0: qcom,led_switch_0 {
+ label = "switch";
+ qcom,led-name = "led:switch_0";
+ qcom,led-mask = <3>;
+ qcom,default-led-trigger = "switch0_trigger";
+ };
+
+ pm660l_switch1: qcom,led_switch_1 {
+ label = "switch";
+ qcom,led-name = "led:switch_1";
+ qcom,led-mask = <4>;
+ qcom,default-led-trigger = "switch1_trigger";
+ };
+ };
+
+ pm660l_lcdb: qpnp-lcdb@ec00 {
+ compatible = "qcom,qpnp-lcdb-regulator";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xec00 0x100>;
+ interrupts = <0x3 0xec 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "sc-irq";
+
+ qcom,pmic-revid = <&pm660l_revid>;
+
+ lcdb_ldo_vreg: ldo {
+ label = "ldo";
+ regulator-name = "lcdb_ldo";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6000000>;
+ };
+
+ lcdb_ncp_vreg: ncp {
+ label = "ncp";
+ regulator-name = "lcdb_ncp";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6000000>;
+ };
+ };
+
+ pm660a_oledb: qpnp-oledb@e000 {
+ compatible = "qcom,qpnp-oledb-regulator";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,pmic-revid = <&pm660l_revid>;
+ reg = <0xe000 0x100>;
+ qcom,pbs-client = <&pm660l_pbs>;
+
+ label = "oledb";
+ regulator-name = "regulator-oledb";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <8100000>;
+
+ qcom,swire-control;
+ qcom,ext-pin-control;
+ status = "disabled";
+ };
+
+ pm660a_labibb: qpnp-labibb-regulator {
+ compatible = "qcom,qpnp-labibb-regulator";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,pmic-revid = <&pm660l_revid>;
+ qcom,swire-control;
+ status = "disabled";
+
+ ibb_regulator: qcom,ibb@dc00 {
+ reg = <0xdc00 0x100>;
+ reg-names = "ibb_reg";
+ regulator-name = "ibb_reg";
+
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6300000>;
+
+ qcom,qpnp-ibb-min-voltage = <1400000>;
+ qcom,qpnp-ibb-step-size = <100000>;
+ qcom,qpnp-ibb-slew-rate = <2000000>;
+ qcom,qpnp-ibb-init-voltage = <4000000>;
+ qcom,qpnp-ibb-init-amoled-voltage = <4000000>;
+ };
+
+ lab_regulator: qcom,lab@de00 {
+ reg = <0xde00 0x100>;
+ reg-names = "lab";
+ regulator-name = "lab_reg";
+
+ regulator-min-microvolt = <4600000>;
+ regulator-max-microvolt = <6100000>;
+
+ qcom,qpnp-lab-min-voltage = <4600000>;
+ qcom,qpnp-lab-step-size = <100000>;
+ qcom,qpnp-lab-slew-rate = <5000>;
+ qcom,qpnp-lab-init-voltage = <4600000>;
+ qcom,qpnp-lab-init-amoled-voltage = <4600000>;
+
+ qcom,notify-lab-vreg-ok-sts;
+ };
+ };
+ };
+};
+
+&thermal_zones {
+ pm660l_temp_alarm: pm660l-tz {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm660l_tz>;
+ wake-capable-sensor;
+
+ trips {
+ pm660l_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ pm660l_trip1: trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm7250b.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm7250b.dtsi
new file mode 100755
index 0000000..c8e90a4
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm7250b.dtsi
@@ -0,0 +1,641 @@
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ qcom,pm7250b@2 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x2 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm7250b_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ pm7250b_pon: qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ };
+
+ pm7250b_charger: qcom,qpnp-smb5 {
+ compatible = "qcom,qpnp-smb5";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #cooling-cells = <2>;
+
+ qcom,thermal-mitigation = <5400000 4500000 4000000
+ 3500000 3000000 2500000 2000000 1500000
+ 1000000 500000>;
+ qcom,pmic-revid = <&pm7250b_revid>;
+ qcom,hvdcp2-max-icl-ua = <2000000>;
+ qcom,hvdcp2-12v-max-icl-ua = <1500000>;
+
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts =
+ <0x2 0x10 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x4 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "chgr-error",
+ "chg-state-change",
+ "step-chg-state-change",
+ "step-chg-soc-update-fail",
+ "step-chg-soc-update-req",
+ "fg-fvcal-qualified",
+ "vph-alarm",
+ "vph-drop-prechg";
+ };
+
+ qcom,dcdc@1100 {
+ reg = <0x1100 0x100>;
+ interrupts =
+ <0x2 0x11 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x11 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x11 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x11 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x11 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x11 0x5 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x11 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x11 0x7 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "otg-fail",
+ "otg-oc-disable-sw",
+ "otg-oc-hiccup",
+ "bsm-active",
+ "high-duty-cycle",
+ "input-current-limiting",
+ "concurrent-mode-disable",
+ "switcher-power-ok";
+ };
+
+ qcom,batif@1200 {
+ reg = <0x1200 0x100>;
+ interrupts =
+ <0x2 0x12 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x5 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x6 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x7 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "bat-temp",
+ "bat-ov",
+ "bat-low",
+ "bat-therm-or-id-missing",
+ "bat-terminal-missing",
+ "buck-oc",
+ "vph-ov";
+ };
+
+ qcom,usb@1300 {
+ reg = <0x1300 0x100>;
+ interrupts =
+ <0x2 0x13 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x5 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x13 0x7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "usbin-collapse",
+ "usbin-vashdn",
+ "usbin-uv",
+ "usbin-ov",
+ "usbin-plugin",
+ "usbin-revi-change",
+ "usbin-src-change",
+ "usbin-icl-change";
+ };
+
+ qcom,dc@1400 {
+ reg = <0x1400 0x100>;
+ interrupts =
+ <0x2 0x14 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x14 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x14 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x14 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x14 0x5 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x14 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x14 0x7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "dcin-vashdn",
+ "dcin-uv",
+ "dcin-ov",
+ "dcin-plugin",
+ "dcin-revi",
+ "dcin-pon",
+ "dcin-en";
+ };
+
+ qcom,typec@1500 {
+ reg = <0x1500 0x100>;
+ interrupts =
+ <0x2 0x15 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x4 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "typec-or-rid-detect-change",
+ "typec-vpd-detect",
+ "typec-cc-state-change",
+ "typec-vconn-oc",
+ "typec-vbus-change",
+ "typec-attach-detach",
+ "typec-legacy-cable-detect",
+ "typec-try-snk-src-detect";
+ };
+
+ qcom,misc@1600 {
+ reg = <0x1600 0x100>;
+ interrupts =
+ <0x2 0x16 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x16 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x16 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x16 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x16 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x16 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x16 0x7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog-snarl",
+ "wdog-bark",
+ "aicl-fail",
+ "aicl-done",
+ "smb-en",
+ "imp-trigger",
+ "temp-change",
+ "temp-change-smb";
+ };
+
+ qcom,chg-sdam@b000 {
+ reg = <0xb000 0x100>;
+ };
+ };
+
+ pm7250b_pdphy: qcom,usb-pdphy@1700 {
+ compatible = "qcom,qpnp-pdphy";
+ reg = <0x1700 0x100>;
+ interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x17 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x17 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x17 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x17 0x4 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x17 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x17 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x17 0x7 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "sig-tx",
+ "sig-rx",
+ "msg-tx",
+ "msg-rx",
+ "msg-tx-failed",
+ "msg-tx-discarded",
+ "msg-rx-discarded",
+ "fr-swap";
+
+ qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */
+ <9000 3000>, /* 9V @ 3A */
+ <12000 2250>; /* 12V @ 2.25A */
+ };
+
+ pm7250b_tz: qcom,temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pm7250b_vadc ADC_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ qcom,temperature-threshold-set = <1>;
+ };
+
+ pm7250b_qg: qpnp,qg {
+ compatible = "qcom,qpnp-qg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qcom,vbatt-cutoff-mv = <3200>;
+ qcom,vbatt-low-mv = <3300>;
+ qcom,vbatt-low-cold-mv = <3700>;
+ qcom,vbatt-empty-mv = <3000>;
+ qcom,vbatt-empty-cold-mv = <3000>;
+ qcom,s3-entry-fifo-length = <2>;
+
+ qcom,pmic-revid = <&pm7250b_revid>;
+
+ qcom,qgauge@4800 {
+ status = "okay";
+ reg = <0x4800 0x100>;
+ interrupts =
+ <0x2 0x48 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x48 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x48 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x48 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x48 0x4 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "qg-batt-missing",
+ "qg-vbat-low",
+ "qg-vbat-empty",
+ "qg-fifo-done",
+ "qg-good-ocv";
+ };
+
+ qcom,qg-sdam@b100 {
+ status = "okay";
+ reg = <0xb100 0x100>;
+ };
+ };
+
+ pm7250b_clkdiv: clock-controller@5b00 {
+ compatible = "qcom,spmi-clkdiv";
+ reg = <0x5b00 0x100>;
+ #clock-cells = <1>;
+ qcom,num-clkdivs = <1>;
+ clock-output-names = "pm7250b_div_clk1";
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ assigned-clocks = <&pm7250b_clkdiv 1>;
+ assigned-clock-rates = <19200000>;
+ };
+
+ pm7250b_gpios: pinctrl@c000 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0xc00>;
+ interrupts = <0x2 0xc0 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc1 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc2 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc3 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc4 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc5 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc6 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc7 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc8 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc9 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xca 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xcb 0x0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm7250b_gpio1", "pm7250b_gpio2",
+ "pm7250b_gpio3", "pm7250b_gpio4",
+ "pm7250b_gpio5", "pm7250b_gpio6",
+ "pm7250b_gpio7", "pm7250b_gpio8",
+ "pm7250b_gpio9", "pm7250b_gpio10",
+ "pm7250b_gpio11", "pm7250b_gpio12";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pm7250b_vadc: vadc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100 0x100>;
+ reg-names = "adc5-usr-base";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-vdd-reference = <1875>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+
+ /* Channel node */
+ ref_gnd@0 {
+ reg = <ADC_REF_GND>;
+ label = "ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref_1p25@1 {
+ reg = <ADC_1P25VREF>;
+ label = "vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ die_temp@2 {
+ reg = <ADC_DIE_TEMP>;
+ label = "die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vph_pwr@83 {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vbat_sns@84 {
+ reg = <ADC_VBAT_SNS>;
+ label = "vbat_sns";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ usb_in_i_uv@7 {
+ reg = <ADC_USB_IN_I>;
+ label = "usb_in_i_uv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ usb_in_v_div_16@8 {
+ reg = <ADC_USB_IN_V_16>;
+ label = "usb_in_v_div_16";
+ qcom,pre-scaling = <1 16>;
+ };
+
+ chg_temp@9 {
+ reg = <ADC_CHG_TEMP>;
+ label = "chg_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bat_therm@4a {
+ reg = <ADC_BAT_THERM_PU2>;
+ label = "bat_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bat_therm_30k@2a {
+ reg = <ADC_BAT_THERM_PU1>;
+ label = "bat_therm_30k";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bat_therm_400k@6a {
+ reg = <ADC_BAT_THERM_PU3>;
+ label = "bat_therm_400k";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bat_id@4b {
+ reg = <ADC_BAT_ID_PU2>;
+ label = "bat_id";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ smb1390_therm@e {
+ reg = <ADC_AMUX_THM2>;
+ label = "smb1390_therm";
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ chg_sbux@99 {
+ reg = <ADC_SBUx>;
+ label = "chg_sbux";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ mid_chg_div6@1e {
+ reg = <ADC_MID_CHG_DIV6>;
+ label = "chg_mid";
+ qcom,pre-scaling = <1 6>;
+ };
+
+ v_i_int_ext@b0 {
+ reg = <ADC_INT_EXT_ISENSE_VBAT_VDATA>;
+ label = "v_i_int_vbat_vdata";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ v_i_parallel@b0 {
+ reg = <ADC_PARALLEL_ISENSE_VBAT_VDATA>;
+ label = "v_i_parallel_vbat_vdata";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pm7250b_adc_tm: adc_tm@3500 {
+ compatible = "qcom,adc-tm5";
+ reg = <0x3500 0x100>;
+ interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "thr-int-en";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ pm7250b_bcl: bcl@1d00 {
+ compatible = "qcom,bcl-v5";
+ reg = <0x1d00 0x100>;
+ interrupts = <0x2 0x1d 0x0 IRQ_TYPE_NONE>,
+ <0x2 0x1d 0x1 IRQ_TYPE_NONE>,
+ <0x2 0x1d 0x2 IRQ_TYPE_NONE>;
+ interrupt-names = "bcl-lvl0",
+ "bcl-lvl1",
+ "bcl-lvl2";
+ #thermal-sensor-cells = <1>;
+ };
+
+ bcl_soc:bcl-soc {
+ compatible = "qcom,msm-bcl-soc";
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ qcom,pm7250b@3 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm7250b_vib: qcom,vibrator@5300 {
+ compatible = "qcom,qpnp-vibrator-ldo";
+ reg = <0x5300 0x100>;
+ qcom,vib-ldo-volt-uv = <3000000>;
+ qcom,disable-overdrive;
+ };
+ };
+};
+
+&thermal_zones {
+ pm7250b_temp_alarm: pm7250b-tz {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm7250b_tz>;
+ wake-capable-sensor;
+
+ trips {
+ pm7250b_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm7250b_trip1: trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm7250b-ibat-lvl0 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm7250b_bcl 0>;
+ wake-capable-sensor;
+
+ trips {
+ ibat_lvl0:ibat-lvl0 {
+ temperature = <5500>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm7250b-ibat-lvl1 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm7250b_bcl 1>;
+ wake-capable-sensor;
+
+ trips {
+ ibat_lvl1:ibat-lvl1 {
+ temperature = <6000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm7250b-vbat-lvl0 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&pm7250b_bcl 2>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ vbat_lvl0: vbat-lvl0 {
+ temperature = <3000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm7250b-vbat-lvl1 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&pm7250b_bcl 3>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ vbat_lvl1:vbat-lvl1 {
+ temperature = <2800>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm7250b-vbat-lvl2 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&pm7250b_bcl 4>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ vbat_lvl2:vbat-lvl2 {
+ temperature = <2600>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm7250b-bcl-lvl0 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm7250b_bcl 5>;
+ wake-capable-sensor;
+
+ trips {
+ b_bcl_lvl0: b-bcl-lvl0 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm7250b-bcl-lvl1 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm7250b_bcl 6>;
+ wake-capable-sensor;
+
+ trips {
+ b_bcl_lvl1: b-bcl-lvl1 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm7250b-bcl-lvl2 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm7250b_bcl 7>;
+ wake-capable-sensor;
+
+ trips {
+ b_bcl_lvl2: b-bcl-lvl2 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+
+ soc {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&bcl_soc>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ soc_trip:soc-trip {
+ temperature = <10>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm8008.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm8008.dtsi
new file mode 100755
index 0000000..f4fc4e8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm8008.dtsi
@@ -0,0 +1,127 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+
+pm8008_8: qcom,pm8008@8 {
+ compatible = "qcom,i2c-pmic";
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ interrupt-names = "pm8008";
+ qcom,periph-map = <0x09 0x24 0xc0 0xc1>;
+
+ pm8008_chip: qcom,pm8008-chip@900 {
+ compatible = "qcom,pm8008-chip";
+ reg = <0x900>;
+ interrupts = <0x09 4 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ocp";
+
+ PM8008_EN: qcom,pm8008-chip-en {
+ regulator-name = "pm8008-chip-en";
+ };
+ };
+
+ qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100>;
+ };
+
+ pm8008_gpios: pinctrl@c000 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0x200>;
+ interrupts = <0xc0 0 IRQ_TYPE_EDGE_RISING>,
+ <0xc1 0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "pm8008_gpio1", "pm8008_gpio2";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ pm8008_gpio1_active: pm8008_gpio1_active {
+ pins = "gpio1";
+ function = "func1";
+ power-source = <1>;
+ output-enable;
+ input-disable;
+ bias-disable;
+ };
+ };
+};
+
+pm8008_9: qcom,pm8008@9 {
+ compatible = "qcom,i2c-pmic";
+ reg = <0x9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm8008_gpio1_active>;
+
+ pm8008_regulators: qcom,pm8008-regulator {
+ compatible = "qcom,pm8008-regulator";
+ pm8008_en-supply = <&PM8008_EN>;
+ qcom,enable-ocp-broadcast;
+
+ L1P: qcom,pm8008-l1@4000 {
+ reg = <0x4000>;
+ regulator-name = "pm8008_l1";
+ regulator-min-microvolt = <528000>;
+ regulator-max-microvolt = <1504000>;
+ qcom,min-dropout-voltage = <225000>;
+ qcom,hpm-min-load = <0>;
+ };
+
+ L2P: qcom,pm8008-l2@4100 {
+ reg = <0x4100>;
+ regulator-name = "pm8008_l2";
+ regulator-min-microvolt = <528000>;
+ regulator-max-microvolt = <1504000>;
+ qcom,min-dropout-voltage = <225000>;
+ qcom,hpm-min-load = <0>;
+ };
+
+ L3P: qcom,pm8008-l3@4200 {
+ reg = <0x4200>;
+ regulator-name = "pm8008_l3";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3400000>;
+ qcom,min-dropout-voltage = <200000>;
+ qcom,hpm-min-load = <0>;
+ };
+
+ L4P: qcom,pm8008-l4@4300 {
+ reg = <0x4300>;
+ regulator-name = "pm8008_l4";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3400000>;
+ qcom,min-dropout-voltage = <200000>;
+ qcom,hpm-min-load = <0>;
+ };
+
+ L5P: qcom,pm8008-l5@4400 {
+ reg = <0x4400>;
+ regulator-name = "pm8008_l5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3400000>;
+ qcom,min-dropout-voltage = <300000>;
+ qcom,hpm-min-load = <0>;
+ };
+
+ L6P: qcom,pm8008-l6@4400 {
+ reg = <0x4500>;
+ regulator-name = "pm8008_l6";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3400000>;
+ qcom,min-dropout-voltage = <300000>;
+ qcom,hpm-min-load = <0>;
+ };
+
+ L7P: qcom,pm8008-l7@4400 {
+ reg = <0x4600>;
+ regulator-name = "pm8008_l7";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <3400000>;
+ qcom,min-dropout-voltage = <300000>;
+ qcom,hpm-min-load = <0>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm8009.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm8009.dtsi
new file mode 100755
index 0000000..dd1cea2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm8009.dtsi
@@ -0,0 +1,46 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ qcom,pm8009@a {
+ compatible ="qcom,spmi-pmic";
+ reg = <0xa SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ };
+
+ pm8009_gpios: pinctrl@c000 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0x400>;
+ interrupts = <0xa 0xc0 0 IRQ_TYPE_NONE>,
+ <0xa 0xc1 0 IRQ_TYPE_NONE>,
+ <0xa 0xc2 0 IRQ_TYPE_NONE>,
+ <0xa 0xc3 0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm8009_gpio1", "pm8009_gpio2",
+ "pm8009_gpio3", "pm8009_gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ qcom,pm8009@b {
+ compatible = "qcom,spmi-pmic";
+ reg = <0xb SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm8150.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm8150.dtsi
new file mode 100755
index 0000000..3bbba49
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm8150.dtsi
@@ -0,0 +1,172 @@
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/input/qcom,qpnp-power-on.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ qcom,pm8150@0 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x0 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "kpdpwr", "resin";
+ qcom,pon-dbc-delay = <15625>;
+ qcom,kpdpwr-sw-debounce;
+ qcom,system-reset;
+ qcom,store-hard-reset-reason;
+
+ qcom,pon_1 {
+ qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
+ linux,code = <KEY_POWER>;
+ qcom,pull-up;
+ };
+
+ qcom,pon_2 {
+ qcom,pon-type = <PON_POWER_ON_TYPE_RESIN>;
+ linux,code = <KEY_VOLUMEDOWN>;
+ qcom,pull-up;
+ };
+ };
+
+ pm8150_tz: qcom,temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pm8150_vadc ADC_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ qcom,temperature-threshold-set = <1>;
+ };
+
+ pm8150_clkdiv: clock-controller@5b00 {
+ compatible = "qcom,spmi-clkdiv";
+ reg = <0x5b00 0x200>;
+ #clock-cells = <1>;
+ qcom,num-clkdivs = <2>;
+ clock-output-names = "pm8150_div_clk1",
+ "pm8150_div_clk2";
+ clocks = <&clock_rpmh RPMH_CXO_CLK>;
+ clock-names = "xo";
+ };
+
+ pm8150_sdam_2: sdam@b100 {
+ compatible = "qcom,spmi-sdam";
+ reg = <0xb100 0x100>;
+ };
+
+ pm8150_gpios: pinctrl@c000 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0xa00>;
+ interrupts = <0x0 0xc0 0x0 IRQ_TYPE_NONE>,
+ <0x0 0xc2 0x0 IRQ_TYPE_NONE>,
+ <0x0 0xc5 0x0 IRQ_TYPE_NONE>,
+ <0x0 0xc6 0x0 IRQ_TYPE_NONE>,
+ <0x0 0xc8 0x0 IRQ_TYPE_NONE>,
+ <0x0 0xc9 0x0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm8150_gpio1", "pm8150_gpio3",
+ "pm8150_gpio6", "pm8150_gpio7",
+ "pm8150_gpio9", "pm8150_gpio10";
+ gpio-controller;
+ #gpio-cells = <2>;
+ qcom,gpios-disallowed = <2 4 5 8>;
+ };
+
+ pm8150_rtc: qcom,pm8150_rtc {
+ compatible = "qcom,pm8941-rtc";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ };
+
+ pm8150_vadc: vadc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-vdd-reference = <1875>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+
+ /* Channel node */
+ ref_gnd@0 {
+ reg = <ADC_REF_GND>;
+ label = "ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref_1p25@1 {
+ reg = <ADC_1P25VREF>;
+ label = "vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ die_temp@2 {
+ reg = <ADC_DIE_TEMP>;
+ label = "die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pm8150_adc_tm: adc_tm@3500 {
+ compatible = "qcom,adc-tm5";
+ reg = <0x3500 0x100>;
+ interrupts = <0x0 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "thr-int-en";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ io-channels = <&pm8150_vadc ADC_AMUX_THM1_PU2>,
+ <&pm8150_vadc ADC_AMUX_THM2_PU2>;
+ };
+ };
+
+ qcom,pm8150@1 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x1 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
+};
+
+&thermal_zones {
+ pm8150_temp_alarm: pm8150_tz {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150_tz>;
+ wake-capable-sensor;
+
+ trips {
+ pm8150_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm8150_trip1: trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm8150b.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm8150b.dtsi
new file mode 100755
index 0000000..9d46333
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm8150b.dtsi
@@ -0,0 +1,731 @@
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ qcom,pm8150b@2 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x2 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm8150b_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ };
+
+ pm8150b_tz: qcom,temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pm8150b_vadc ADC_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ qcom,temperature-threshold-set = <1>;
+ };
+
+ pm8150b_clkdiv: clock-controller@6000 {
+ compatible = "qcom,spmi-clkdiv";
+ reg = <0x6000 0x100>;
+ #clock-cells = <1>;
+ qcom,num-clkdivs = <1>;
+ clock-output-names = "pm8150b_div_clk1";
+ clocks = <&clock_rpmh RPMH_CXO_CLK>;
+ clock-names = "xo";
+ };
+
+ pm8150b_pbs1: qcom,pbs@7200 {
+ compatible = "qcom,qpnp-pbs";
+ reg = <0x7200 0x100>;
+ };
+
+ pm8150b_qnovo: qcom,sdam-qnovo@b000 {
+ compatible = "qcom,qpnp-qnovo5";
+ reg = <0xb000 0x100>;
+ interrupts = <0x2 0xb0 1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ptrain-done";
+ };
+
+ pm8150b_gpios: pinctrl@c000 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0xc00>;
+ interrupts = <0x2 0xc0 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc1 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc4 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc5 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc6 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc7 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc8 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xc9 0x0 IRQ_TYPE_NONE>,
+ <0x2 0xcb 0x0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm8150b_gpio1", "pm8150b_gpio2",
+ "pm8150b_gpio5", "pm8150b_gpio6",
+ "pm8150b_gpio7", "pm8150b_gpio8",
+ "pm8150b_gpio9", "pm8150b_gpio10",
+ "pm8150b_gpio12";
+ gpio-controller;
+ #gpio-cells = <2>;
+ qcom,gpios-disallowed = <3 4 11>;
+ };
+
+ pm8150b_charger: qcom,qpnp-smb5 {
+ compatible = "qcom,qpnp-smb5";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #cooling-cells = <2>;
+
+ qcom,pmic-revid = <&pm8150b_revid>;
+
+ qcom,thermal-mitigation
+ = <3000000 1500000 1000000 500000>;
+
+ qcom,chg-term-src = <1>;
+ qcom,charger-temp-max = <800>;
+ qcom,smb-temp-max = <800>;
+ status = "disabled";
+
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts =
+ <0x2 0x10 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x4 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x6 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x10 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "chgr-error",
+ "chg-state-change",
+ "step-chg-state-change",
+ "step-chg-soc-update-fail",
+ "step-chg-soc-update-req",
+ "vph-alarm",
+ "vph-drop-prechg";
+ };
+
+ qcom,dcdc@1100 {
+ reg = <0x1100 0x100>;
+ interrupts =
+ <0x2 0x11 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x11 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x11 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x11 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x11 0x5 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x11 0x6 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x11 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "otg-fail",
+ "otg-oc-disable-sw",
+ "otg-oc-hiccup",
+ "high-duty-cycle",
+ "input-current-limiting",
+ "concurrent-mode-disable",
+ "switcher-power-ok";
+ };
+
+ qcom,batif@1200 {
+ reg = <0x1200 0x100>;
+ interrupts =
+ <0x2 0x12 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x5 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x6 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "bat-temp",
+ "bat-ov",
+ "bat-low",
+ "bat-therm-or-id-missing",
+ "bat-terminal-missing",
+ "buck-oc",
+ "vph-ov";
+ };
+
+ qcom,usb@1300 {
+ reg = <0x1300 0x100>;
+ interrupts =
+ <0x2 0x13 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x5 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x13 0x7 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "usbin-collapse",
+ "usbin-vashdn",
+ "usbin-uv",
+ "usbin-ov",
+ "usbin-plugin",
+ "usbin-revi-change",
+ "usbin-src-change",
+ "usbin-icl-change";
+ };
+
+ qcom,dc@1400 {
+ reg = <0x1400 0x100>;
+ interrupts =
+ <0x2 0x14 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x14 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x14 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x14 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x14 0x5 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x14 0x6 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x14 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "dcin-vashdn",
+ "dcin-uv",
+ "dcin-ov",
+ "dcin-plugin",
+ "dcin-revi",
+ "dcin-pon",
+ "dcin-en";
+ };
+
+ qcom,typec@1500 {
+ reg = <0x1500 0x100>;
+ interrupts =
+ <0x2 0x15 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x15 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x15 0x4 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x6 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x15 0x7 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "typec-or-rid-detect-change",
+ "typec-vpd-detect",
+ "typec-cc-state-change",
+ "typec-vconn-oc",
+ "typec-vbus-change",
+ "typec-attach-detach",
+ "typec-legacy-cable-detect",
+ "typec-try-snk-src-detect";
+ };
+
+ qcom,misc@1600 {
+ reg = <0x1600 0x100>;
+ interrupts =
+ <0x2 0x16 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x16 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x16 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x16 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x16 0x6 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x16 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "wdog-snarl",
+ "wdog-bark",
+ "aicl-fail",
+ "aicl-done",
+ "smb-en",
+ "temp-change",
+ "temp-change-smb";
+ };
+ };
+
+ pm8150b_pdphy: qcom,usb-pdphy@1700 {
+ compatible = "qcom,qpnp-pdphy";
+ reg = <0x1700 0x100>;
+ interrupts = <0x2 0x17 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x17 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x17 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x17 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x17 0x4 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x17 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x17 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x17 0x7 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "sig-tx",
+ "sig-rx",
+ "msg-tx",
+ "msg-rx",
+ "msg-tx-failed",
+ "msg-tx-discarded",
+ "msg-rx-discarded",
+ "fr-swap";
+
+ qcom,default-sink-caps = <5000 3000>, /* 5V @ 3A */
+ <9000 3000>, /* 9V @ 3A */
+ <12000 2250>; /* 12V @ 2.25A */
+ };
+
+ pm8150b_bcl: bcl@1d00 {
+ compatible = "qcom,bcl-v5";
+ reg = <0x1d00 0x100>;
+ interrupts = <0x2 0x1d 0x0 IRQ_TYPE_NONE>,
+ <0x2 0x1d 0x1 IRQ_TYPE_NONE>,
+ <0x2 0x1d 0x2 IRQ_TYPE_NONE>;
+ interrupt-names = "bcl-lvl0",
+ "bcl-lvl1",
+ "bcl-lvl2";
+ #thermal-sensor-cells = <1>;
+ };
+
+ bcl_soc:bcl-soc {
+ compatible = "qcom,msm-bcl-soc";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8150b_fg: qpnp,fg {
+ compatible = "qcom,fg-gen4";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ qcom,pmic-revid = <&pm8150b_revid>;
+ qcom,pmic-pbs = <&pm8150b_pbs1>;
+ status = "disabled";
+
+ qcom,fg-batt-soc@4000 {
+ status = "okay";
+ reg = <0x4000 0x100>;
+ interrupts = <0x2 0x40 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x40 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x40 0x2
+ IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x40 0x3
+ IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x40 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x40 0x5
+ IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x40 0x6 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x40 0x7 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "soc-update",
+ "soc-ready",
+ "bsoc-delta",
+ "msoc-delta",
+ "msoc-low",
+ "msoc-empty",
+ "msoc-high",
+ "msoc-full";
+ };
+
+ qcom,fg-batt-info@4100 {
+ status = "okay";
+ reg = <0x4100 0x100>;
+ interrupts = <0x2 0x41 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x41 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x41 0x3
+ IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "vbatt-low",
+ "vbatt-pred-delta",
+ "esr-delta";
+ };
+
+ qcom,fg-rradc@4200 {
+ status = "okay";
+ reg = <0x4200 0x100>;
+ interrupts = <0x2 0x42 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x42 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x42 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x42 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x42 0x4 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "batt-missing",
+ "batt-id",
+ "batt-temp-delta",
+ "batt-temp-hot",
+ "batt-temp-cold";
+ };
+
+ qcom,fg-memif@4300 {
+ status = "okay";
+ reg = <0x4300 0x100>;
+ interrupts = <0x2 0x43 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x43 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x43 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x43 0x3
+ IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x43 0x4
+ IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "ima-rdy",
+ "ima-xcp",
+ "dma-xcp",
+ "dma-grant",
+ "mem-attn";
+ };
+ };
+
+ pm8150b_vadc: vadc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100 0x100>, <0x3700 0x100>;
+ reg-names = "adc5-usr-base", "adc5-cal-base";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-vdd-reference = <1875>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+
+ /* Channel node */
+ ref_gnd@0 {
+ reg = <ADC_REF_GND>;
+ label = "ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref_1p25@1 {
+ reg = <ADC_1P25VREF>;
+ label = "vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ die_temp@2 {
+ reg = <ADC_DIE_TEMP>;
+ label = "die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ chg_temp@9 {
+ reg = <ADC_CHG_TEMP>;
+ label = "chg_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bat_id@4b {
+ reg = <ADC_BAT_ID_PU2>;
+ label = "bat_id";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ smb1390_therm@e {
+ reg = <ADC_AMUX_THM2>;
+ label = "smb1390_therm";
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ smb1355_therm@4e {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "smb1355_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pm8150b_adc_tm: adc_tm@3500 {
+ compatible = "qcom,adc-tm5";
+ reg = <0x3500 0x100>;
+ interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "thr-int-en";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ qcom,pmic-revid = <&pm8150b_revid>;
+ };
+ };
+
+ qcom,pm8150b@3 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x3 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm8150b_pwm: qcom,pwms@b100 {
+ compatible = "qcom,pwm-lpg";
+ reg = <0xb100 0x200>;
+ reg-names = "lpg-base";
+ #pwm-cells = <2>;
+ qcom,num-lpg-channels = <2>;
+ };
+
+ pm8150b_hr_led: qcom,leds@d000 {
+ compatible = "qcom,tri-led";
+ reg = <0xd000 0x100>;
+ nvmem-names = "pbs_sdam";
+ nvmem = <&pm8150_sdam_2>;
+ hr_led1 {
+ label = "hr_led1";
+ pwms = <&pm8150b_pwm 0 1000000>;
+ led-sources = <0>;
+ };
+
+ hr_led2 {
+ label = "hr_led2";
+ pwms = <&pm8150b_pwm 1 1000000>;
+ led-sources = <1>;
+ };
+ };
+
+ pm8150b_haptics: qcom,haptics@c000 {
+ compatible = "qcom,haptics";
+ reg = <0xc000 0x100>;
+ interrupts = <0x3 0xc0 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x3 0xc0 0x1 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "hap-sc-irq", "hap-play-irq";
+ qcom,actuator-type = "lra";
+ qcom,vmax-mv = <3600>;
+ qcom,play-rate-us = <6667>;
+ qcom,lra-resonance-sig-shape = "sine";
+ qcom,lra-auto-resonance-mode = "qwd";
+ qcom,lra-allow-variable-play-rate;
+
+ wf_0 {
+ /* CLICK */
+ qcom,effect-id = <0>;
+ qcom,wf-vmax-mv = <3600>;
+ qcom,wf-pattern = [3e 3e 3e 3e 3e 3e 3e 3e];
+ qcom,wf-play-rate-us = <6667>;
+ qcom,wf-brake-pattern = [00 00 00 00];
+ qcom,wf-repeat-count = <1>;
+ qcom,wf-s-repeat-count = <1>;
+ qcom,lra-auto-resonance-disable;
+ };
+
+ wf_1 {
+ /* DOUBLE CLICK */
+ qcom,effect-id = <1>;
+ qcom,wf-vmax-mv = <3600>;
+ qcom,wf-pattern = [3e 3e 3e 3e 3e 3e 3e 3e];
+ qcom,wf-play-rate-us = <6667>;
+ qcom,wf-brake-pattern = [00 00 00 00];
+ qcom,wf-repeat-count = <1>;
+ qcom,wf-s-repeat-count = <1>;
+ qcom,lra-auto-resonance-disable;
+ };
+
+ wf_2 {
+ /* TICK */
+ qcom,effect-id = <2>;
+ qcom,wf-vmax-mv = <3600>;
+ qcom,wf-pattern = [3e 3e 3e 3e 3e 3e 3e 3e];
+ qcom,wf-play-rate-us = <6667>;
+ qcom,wf-brake-pattern = [00 00 00 00];
+ qcom,wf-repeat-count = <1>;
+ qcom,wf-s-repeat-count = <1>;
+ qcom,lra-auto-resonance-disable;
+ };
+
+ wf_3 {
+ /* THUD */
+ qcom,effect-id = <3>;
+ qcom,wf-vmax-mv = <3600>;
+ qcom,wf-pattern = [3e 3e 3e 3e 3e 3e 3e 3e];
+ qcom,wf-play-rate-us = <6667>;
+ qcom,wf-brake-pattern = [00 00 00 00];
+ qcom,wf-repeat-count = <1>;
+ qcom,wf-s-repeat-count = <1>;
+ qcom,lra-auto-resonance-disable;
+ };
+
+ wf_4 {
+ /* POP */
+ qcom,effect-id = <4>;
+ qcom,wf-vmax-mv = <3600>;
+ qcom,wf-pattern = [3e 3e 3e 3e 3e 3e 3e 3e];
+ qcom,wf-play-rate-us = <6667>;
+ qcom,wf-brake-pattern = [00 00 00 00];
+ qcom,wf-repeat-count = <1>;
+ qcom,wf-s-repeat-count = <1>;
+ qcom,lra-auto-resonance-disable;
+ };
+
+ wf_5 {
+ /* HEAVY CLICK */
+ qcom,effect-id = <5>;
+ qcom,wf-vmax-mv = <3600>;
+ qcom,wf-pattern = [3e 3e 3e 3e 3e 3e 3e 3e];
+ qcom,wf-play-rate-us = <6667>;
+ qcom,wf-brake-pattern = [00 00 00 00];
+ qcom,wf-repeat-count = <1>;
+ qcom,wf-s-repeat-count = <1>;
+ qcom,lra-auto-resonance-disable;
+ };
+ };
+ };
+};
+
+&thermal_zones {
+ pm8150b_temp_alarm: pm8150b_tz {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150b_tz>;
+ wake-capable-sensor;
+
+ trips {
+ pm8150b_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm8150b_trip1: trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150b-ibat-lvl0 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150b_bcl 0>;
+ wake-capable-sensor;
+
+ trips {
+ ibat_lvl0:ibat-lvl0 {
+ temperature = <4500>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150b-ibat-lvl1 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150b_bcl 1>;
+ wake-capable-sensor;
+
+ trips {
+ ibat_lvl1:ibat-lvl1 {
+ temperature = <5000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150b-vbat-lvl0 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&pm8150b_bcl 2>;
+ tracks-low;
+ wake-capable-sensor;
+
+ trips {
+ vbat_lvl0: vbat-lvl0 {
+ temperature = <3000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150b-vbat-lvl1 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&pm8150b_bcl 3>;
+ tracks-low;
+ wake-capable-sensor;
+
+ trips {
+ vbat_lvl1:vbat-lvl1 {
+ temperature = <2800>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150b-vbat-lvl2 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&pm8150b_bcl 4>;
+ tracks-low;
+ wake-capable-sensor;
+
+ trips {
+ vbat_lvl2:vbat-lvl2 {
+ temperature = <2600>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150b-bcl-lvl0 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150b_bcl 5>;
+ wake-capable-sensor;
+
+ trips {
+ b_bcl_lvl0: b-bcl-lvl0 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150b-bcl-lvl1 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150b_bcl 6>;
+ wake-capable-sensor;
+
+ trips {
+ b_bcl_lvl1: b-bcl-lvl1 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150b-bcl-lvl2 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150b_bcl 7>;
+ wake-capable-sensor;
+
+ trips {
+ b_bcl_lvl2: b-bcl-lvl2 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+
+ soc {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&bcl_soc>;
+ tracks-low;
+ wake-capable-sensor;
+
+ trips {
+ soc_trip:soc-trip {
+ temperature = <10>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm8150l.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm8150l.dtsi
new file mode 100755
index 0000000..d89288b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm8150l.dtsi
@@ -0,0 +1,558 @@
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ qcom,pm8150l@4 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x4 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm8150l_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ };
+
+ pm8150l_tz: qcom,temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ io-channels = <&pm8150l_vadc ADC_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ qcom,temperature-threshold-set = <1>;
+ };
+
+ pm8150l_clkdiv: clock-controller@5b00 {
+ compatible = "qcom,spmi-clkdiv";
+ reg = <0x5b00 0x100>;
+ #clock-cells = <1>;
+ qcom,num-clkdivs = <1>;
+ clock-output-names = "pm8150l_div_clk1";
+ clocks = <&clock_rpmh RPMH_CXO_CLK>;
+ clock-names = "xo";
+ };
+
+ pm8150l_gpios: pinctrl@c000 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0xc00>;
+ interrupts = <0x4 0xc0 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc2 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc3 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc4 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc5 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc6 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc7 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xc9 0x0 IRQ_TYPE_NONE>,
+ <0x4 0xca 0x0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm8150l_gpio1", "pm8150l_gpio3",
+ "pm8150l_gpio4", "pm8150l_gpio5",
+ "pm8150l_gpio6", "pm8150l_gpio7",
+ "pm8150l_gpio8", "pm8150l_gpio10",
+ "pm8150l_gpio11";
+ gpio-controller;
+ #gpio-cells = <2>;
+ qcom,gpios-disallowed = <2 9 12>;
+ };
+
+ pm8150l_vadc: vadc@3100 {
+ compatible = "qcom,spmi-adc5";
+ reg = <0x3100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-vdd-reference = <1875>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+
+ /* Channel node */
+ ref_gnd@0 {
+ reg = <ADC_REF_GND>;
+ label = "ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref_1p25@1 {
+ reg = <ADC_1P25VREF>;
+ label = "vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ die_temp@2 {
+ reg = <ADC_DIE_TEMP>;
+ label = "die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pm8150l_bcl: bcl@3d00 {
+ compatible = "qcom,bcl-v5";
+ reg = <0x3d00 0x100>;
+ interrupts = <0x4 0x3d 0x0 IRQ_TYPE_NONE>,
+ <0x4 0x3d 0x1 IRQ_TYPE_NONE>,
+ <0x4 0x3d 0x2 IRQ_TYPE_NONE>;
+ interrupt-names = "bcl-lvl0",
+ "bcl-lvl1",
+ "bcl-lvl2";
+ #thermal-sensor-cells = <1>;
+ };
+
+ pm8150l_adc_tm: adc_tm@3500 {
+ compatible = "qcom,adc-tm5";
+ reg = <0x3500 0x100>;
+ interrupts = <0x4 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "thr-int-en";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ io-channels = <&pm8150l_vadc ADC_AMUX_THM1_PU2>,
+ <&pm8150l_vadc ADC_AMUX_THM2_PU2>,
+ <&pm8150l_vadc ADC_AMUX_THM3_PU2>;
+ };
+ };
+
+ qcom,pm8150l@5 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x5 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm8150l_lcdb: qcom,lcdb@ec00 {
+ compatible = "qcom,qpnp-lcdb-regulator";
+ reg = <0xec00 0x100>;
+ interrupts = <0x5 0xec 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "sc-irq";
+ qcom,pmic-revid = <&pm8150l_revid>;
+ qcom,voltage-step-ramp;
+ status = "disabled";
+
+ lcdb_ldo_vreg: ldo {
+ label = "ldo";
+ regulator-name = "lcdb_ldo";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6000000>;
+ };
+
+ lcdb_ncp_vreg: ncp {
+ label = "ncp";
+ regulator-name = "lcdb_ncp";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6000000>;
+ };
+
+ lcdb_bst_vreg: bst {
+ label = "bst";
+ regulator-name = "lcdb_bst";
+ regulator-min-microvolt = <4700000>;
+ regulator-max-microvolt = <6275000>;
+ };
+ };
+
+ flash_led: qcom,leds@d300 {
+ compatible = "qcom,qpnp-flash-led-v2";
+ status = "okay";
+ reg = <0xd300 0x100>;
+ label = "flash";
+ interrupts = <0x5 0xd3 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x5 0xd3 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x5 0xd3 0x4 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "led-fault-irq",
+ "all-ramp-down-done-irq",
+ "all-ramp-up-done-irq";
+ qcom,hdrm-auto-mode;
+ qcom,short-circuit-det;
+ qcom,open-circuit-det;
+ qcom,vph-droop-det;
+ qcom,thermal-derate-en;
+ qcom,thermal-derate-current = <200 500 1000>;
+ qcom,isc-delay = <192>;
+ qcom,pmic-revid = <&pm8150l_revid>;
+
+ pm8150l_flash0: qcom,flash_0 {
+ label = "flash";
+ qcom,led-name = "led:flash_0";
+ qcom,max-current = <1500>;
+ qcom,default-led-trigger = "flash0_trigger";
+ qcom,id = <0>;
+ qcom,current-ma = <1000>;
+ qcom,duration-ms = <1280>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pm8150l_flash1: qcom,flash_1 {
+ label = "flash";
+ qcom,led-name = "led:flash_1";
+ qcom,max-current = <1500>;
+ qcom,default-led-trigger = "flash1_trigger";
+ qcom,id = <1>;
+ qcom,current-ma = <1000>;
+ qcom,duration-ms = <1280>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pm8150l_flash2: qcom,flash_2 {
+ label = "flash";
+ qcom,led-name = "led:flash_2";
+ qcom,max-current = <750>;
+ qcom,default-led-trigger = "flash2_trigger";
+ qcom,id = <2>;
+ qcom,current-ma = <500>;
+ qcom,duration-ms = <1280>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ status = "disabled";
+ };
+
+ pm8150l_torch0: qcom,torch_0 {
+ label = "torch";
+ qcom,led-name = "led:torch_0";
+ qcom,max-current = <500>;
+ qcom,default-led-trigger = "torch0_trigger";
+ qcom,id = <0>;
+ qcom,current-ma = <300>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pm8150l_torch1: qcom,torch_1 {
+ label = "torch";
+ qcom,led-name = "led:torch_1";
+ qcom,max-current = <500>;
+ qcom,default-led-trigger = "torch1_trigger";
+ qcom,id = <1>;
+ qcom,current-ma = <300>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pm8150l_torch2: qcom,torch_2 {
+ label = "torch";
+ qcom,led-name = "led:torch_2";
+ qcom,max-current = <500>;
+ qcom,default-led-trigger = "torch2_trigger";
+ qcom,id = <2>;
+ qcom,current-ma = <300>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <325>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ status = "disabled";
+ };
+
+ pm8150l_switch0: qcom,led_switch_0 {
+ label = "switch";
+ qcom,led-name = "led:switch_0";
+ qcom,led-mask = <1>; /* Channel 1 */
+ qcom,default-led-trigger = "switch0_trigger";
+ };
+
+ pm8150l_switch1: qcom,led_switch_1 {
+ label = "switch";
+ qcom,led-name = "led:switch_1";
+ qcom,led-mask = <2>; /* Channel 2 */
+ qcom,default-led-trigger = "switch1_trigger";
+ };
+
+ pm8150l_switch2: qcom,led_switch_2 {
+ label = "switch";
+ qcom,led-name = "led:switch_2";
+ qcom,led-mask = <3>; /* Channels 1 and 2 */
+ qcom,default-led-trigger = "switch2_trigger";
+ };
+
+ pm8150l_switch3: qcom,led_switch_3 {
+ label = "switch";
+ qcom,led-name = "led:switch_3";
+ qcom,led-mask = <4>; /* Channel 3 */
+ qcom,default-led-trigger = "switch3_trigger";
+ };
+ };
+
+ pm8150l_wled: qcom,wled@d800 {
+ compatible = "qcom,pm8150l-spmi-wled";
+ reg = <0xd800 0x100>, <0xd900 0x100>;
+ reg-names = "wled-ctrl-base", "wled-sink-base";
+ label = "backlight";
+ interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x5 0xd8 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x5 0xd8 0x5 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "ovp-irq", "pre-flash-irq",
+ "flash-irq";
+ qcom,pmic-revid = <&pm8150l_revid>;
+ qcom,auto-calibration;
+ status = "disabled";
+
+ wled_flash: qcom,wled-flash {
+ label = "flash";
+ qcom,default-led-trigger = "wled_flash";
+ };
+
+ wled_torch: qcom,wled-torch {
+ label = "torch";
+ qcom,default-led-trigger = "wled_torch";
+ qcom,wled-torch-timer = <1200>;
+ };
+
+ wled_switch: qcom,wled-switch {
+ label = "switch";
+ qcom,default-led-trigger = "wled_switch";
+ };
+ };
+
+ pm8150l_lpg: qcom,pwms@b100 {
+ compatible = "qcom,pwm-lpg";
+ reg = <0xb100 0x300>, <0xb000 0x100>;
+ reg-names = "lpg-base", "lut-base";
+ #pwm-cells = <2>;
+ qcom,num-lpg-channels = <3>;
+ qcom,lut-patterns = <0 10 20 30 40 50 60 70 80 90 100
+ 90 80 70 60 50 40 30 20 10 0>;
+ lpg1 {
+ qcom,lpg-chan-id = <1>;
+ qcom,ramp-step-ms = <100>;
+ qcom,ramp-pause-hi-count = <2>;
+ qcom,ramp-pause-lo-count = <2>;
+ qcom,ramp-low-index = <0>;
+ qcom,ramp-high-index = <20>;
+ qcom,ramp-from-low-to-high;
+ qcom,ramp-pattern-repeat;
+ };
+
+ lpg2 {
+ qcom,lpg-chan-id = <2>;
+ qcom,ramp-step-ms = <100>;
+ qcom,ramp-pause-hi-count = <2>;
+ qcom,ramp-pause-lo-count = <2>;
+ qcom,ramp-low-index = <0>;
+ qcom,ramp-high-index = <20>;
+ qcom,ramp-from-low-to-high;
+ qcom,ramp-pattern-repeat;
+ };
+
+ lpg3 {
+ qcom,lpg-chan-id = <3>;
+ qcom,ramp-step-ms = <100>;
+ qcom,ramp-pause-hi-count = <2>;
+ qcom,ramp-pause-lo-count = <2>;
+ qcom,ramp-low-index = <0>;
+ qcom,ramp-high-index = <20>;
+ qcom,ramp-from-low-to-high;
+ qcom,ramp-pattern-repeat;
+ };
+ };
+
+ pm8150l_pwm: qcom,pwms@bc00 {
+ compatible = "qcom,pwm-lpg";
+ reg = <0xbc00 0x200>;
+ reg-names = "lpg-base";
+ #pwm-cells = <2>;
+ qcom,num-lpg-channels = <2>;
+ };
+
+ pm8150l_rgb_led: qcom,leds@d000 {
+ compatible = "qcom,tri-led";
+ reg = <0xd000 0x100>;
+ red {
+ label = "red";
+ pwms = <&pm8150l_lpg 0 1000000>;
+ led-sources = <0>;
+ linux,default-trigger = "timer";
+ };
+
+ green {
+ label = "green";
+ pwms = <&pm8150l_lpg 1 1000000>;
+ led-sources = <1>;
+ linux,default-trigger = "timer";
+ };
+
+ blue {
+ label = "blue";
+ pwms = <&pm8150l_lpg 2 1000000>;
+ led-sources = <2>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ pm8150a_amoled: qcom,amoled {
+ compatible = "qcom,qpnp-amoled-regulator";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ oledb_vreg: oledb@e000 {
+ reg = <0xe000 0x100>;
+ reg-names = "oledb_base";
+ regulator-name = "oledb";
+ regulator-min-microvolt = <4925000>;
+ regulator-max-microvolt = <8100000>;
+ qcom,swire-control;
+ };
+
+ ab_vreg: ab@de00 {
+ reg = <0xde00 0x100>;
+ reg-names = "ab_base";
+ regulator-name = "ab";
+ regulator-min-microvolt = <4600000>;
+ regulator-max-microvolt = <6100000>;
+ qcom,swire-control;
+ };
+
+ ibb_vreg: ibb@dc00 {
+ reg = <0xdc00 0x100>;
+ reg-names = "ibb_base";
+ regulator-name = "ibb";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <5400000>;
+ qcom,swire-control;
+ };
+ };
+ };
+};
+
+&thermal_zones {
+ pm8150l_temp_alarm: pm8150l_tz {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150l_tz>;
+ wake-capable-sensor;
+
+ trips {
+ trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150l-vph-lvl0 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&pm8150l_bcl 2>;
+ tracks-low;
+ wake-capable-sensor;
+
+ trips {
+ vph_lvl0: vph-lvl0 {
+ temperature = <3000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150l-vph-lvl1 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&pm8150l_bcl 3>;
+ tracks-low;
+ wake-capable-sensor;
+
+ trips {
+ vph_lvl1:vph-lvl1 {
+ temperature = <2750>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150l-vph-lvl2 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&pm8150l_bcl 4>;
+ tracks-low;
+ wake-capable-sensor;
+
+ trips {
+ vph_lvl2:vph-lvl2 {
+ temperature = <2500>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150l-bcl-lvl0 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150l_bcl 5>;
+ wake-capable-sensor;
+
+ trips {
+ l_bcl_lvl0: l-bcl-lvl0 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150l-bcl-lvl1 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150l_bcl 6>;
+ wake-capable-sensor;
+
+ trips {
+ l_bcl_lvl1: l-bcl-lvl1 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8150l-bcl-lvl2 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8150l_bcl 7>;
+ wake-capable-sensor;
+
+ trips {
+ l_bcl_lvl2: l-bcl-lvl2 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm8916-rpm-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm8916-rpm-regulator.dtsi
new file mode 100755
index 0000000..b9a31fc
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm8916-rpm-regulator.dtsi
@@ -0,0 +1,371 @@
+&rpm_bus {
+ rpm-regulator-smpa1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_s1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_s2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_s3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa4 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <4>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s4 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_s4";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa4 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <4>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l4 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l4";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa5 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <5>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l5 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l5";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa6 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <6>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l6 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l6";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa7 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <7>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l7 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l7";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa8 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <8>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l8 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l8";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa9 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <9>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l9 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l9";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa10 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <10>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l10 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l10";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa11 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <11>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l11 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l11";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa12 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <12>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l12 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l12";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa13 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <13>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <5000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l13 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l13";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa14 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <14>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <5000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l14 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l14";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa15 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <15>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <5000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l15 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l15";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa16 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <16>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <5000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l16 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l16";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa17 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <17>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l17 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l17";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa18 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <18>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l18 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l18";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm8916.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm8916.dtsi
new file mode 100755
index 0000000..f5059b4
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm8916.dtsi
@@ -0,0 +1,386 @@
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+
+ pm8916_0: pm8916@0 {
+ compatible = "qcom,pm8916", "qcom,spmi-pmic";
+ reg = <0 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm8916_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ pm8916_pon: qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>,
+ <0x0 0x8 0x1 IRQ_TYPE_NONE>;
+ interrupt-names = "kpdpwr", "resin";
+ qcom,pon-dbc-delay = <15625>;
+ qcom,system-reset;
+ qcom,clear-warm-reset;
+ qcom,store-hard-reset-reason;
+
+ qcom,pon_1 {
+ qcom,pon-type = <0>;
+ qcom,support-reset = <1>;
+ qcom,pull-up = <1>;
+ qcom,s1-timer = <10256>;
+ qcom,s2-timer = <2000>;
+ qcom,s2-type = <1>;
+ linux,code = <116>;
+ };
+
+ qcom,pon_2 {
+ qcom,pon-type = <1>;
+ qcom,pull-up = <1>;
+ linux,code = <114>;
+ };
+ };
+
+ pm8916_gpios: pinctrl@c000 {
+ compatible = "qcom,pm8916-gpio";
+ reg = <0xc000 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
+ <0 0xc1 0 IRQ_TYPE_NONE>,
+ <0 0xc2 0 IRQ_TYPE_NONE>,
+ <0 0xc3 0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm8916_gpio1", "pm8916_gpio2",
+ "pm8916_gpio3", "pm8916_gpio4";
+ };
+
+ pm8916_mpps: mpps@a000 {
+ compatible = "qcom,pm8916-mpp";
+ reg = <0xa000 0x400>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
+ <0 0xa1 0 IRQ_TYPE_NONE>,
+ <0 0xa2 0 IRQ_TYPE_NONE>,
+ <0 0xa3 0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm8916_mpp1", "pm8916_mpp2",
+ "pm8916_mpp3", "pm8916_mpp4";
+ };
+
+ pm8916_rtc: qcom,pm8916_rtc {
+ compatible = "qcom,pm8916-rtc";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ };
+
+ pm8916_vadc: vadc@3100 {
+ compatible = "qcom,spmi-vadc";
+ reg = <0x3100 0x100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+
+ die_temp {
+ reg = <VADC_DIE_TEMP>;
+ label = "die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_625mv {
+ reg = <VADC_REF_625MV>;
+ label = "ref_625mv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_1250v {
+ reg = <VADC_REF_1250MV>;
+ label = "ref_1250v";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_buf_625mv {
+ reg = <VADC_SPARE1>;
+ label = "ref_buf_625mv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_vdd {
+ reg = <VADC_VDD_VADC>;
+ label = "ref_vdd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_gnd {
+ reg = <VADC_GND_REF>;
+ label = "ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pm8916_tz: temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pm8916_vadc VADC_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8916_adc_tm_iio: adc_tm_iio {
+ compatible = "qcom,adc-tm5-iio";
+ reg = <0x3500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ pm8916_adc_tm: vadc@3400 {
+ compatible = "qcom,qpnp-adc-tm";
+ reg = <0x3400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x34 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x34 0x4 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set",
+ "high-thr-en-set",
+ "low-thr-en-set";
+ qcom,adc-vdd-reference = <1800>;
+ #thermal-sensor-cells = <1>;
+ qcom,pmic-revid = <&pm8916_revid>;
+ io-channels = <&pm8916_vadc VADC_REF_625MV>,
+ <&pm8916_vadc VADC_REF_1250MV>,
+ <&pm8916_vadc VADC_VDD_VADC>,
+ <&pm8916_vadc VADC_GND_REF>;
+ io-channel-names = "ref_625mv", "ref_1250v", "ref_vdd",
+ "ref_gnd";
+ };
+
+ pm8916_chg: qcom,charger {
+ compatible = "qcom,qpnp-linear-charger";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #cooling-cells = <2>;
+
+ qcom,v-cutoff-mv = <3400>;
+ qcom,vddmax-mv = <4200>;
+ qcom,vddsafe-mv = <4200>;
+ qcom,vinmin-mv = <4308>;
+ qcom,ibatsafe-ma = <1440>;
+ qcom,thermal-mitigation = <1440 720 630 0>;
+ qcom,cool-bat-decidegc = <100>;
+ qcom,warm-bat-decidegc = <450>;
+ qcom,cool-bat-mv = <4100>;
+ qcom,warm-bat-mv = <4100>;
+ qcom,ibatmax-warm-ma = <360>;
+ qcom,ibatmax-cool-ma = <360>;
+ qcom,batt-hot-percentage = <25>;
+ qcom,batt-cold-percentage = <80>;
+ qcom,tchg-mins = <232>;
+ qcom,resume-soc = <99>;
+ io-channels = <&pm8916_vadc VADC_VBAT_SNS>,
+ <&pm8916_vadc VADC_LR_MUX1_BAT_THERM>;
+ io-channel-names = "vbat_sns", "batt_therm";
+ qcom,chg-adc_tm = <&pm8916_adc_tm>;
+
+ status = "disabled";
+
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts =
+ <0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x10 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x10 0x5 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x10 0x0 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "chg-done",
+ "chg-failed",
+ "fast-chg-on",
+ "vbat-det-lo";
+ };
+
+ qcom,bat-if@1200 {
+ reg = <0x1200 0x100>;
+ interrupts = <0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "bat-temp-ok",
+ "batt-pres";
+ };
+
+ qcom,usb-chgpth@1300 {
+ reg = <0x1300 0x100>;
+ interrupts =
+ <0 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0 0x13 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "usb-over-temp",
+ "chg-gone",
+ "usbin-valid";
+ };
+
+ qcom,chg-misc@1600 {
+ reg = <0x1600 0x100>;
+ };
+ };
+
+ pm8916_bms: qcom,vmbms {
+ compatible = "qcom,qpnp-vm-bms";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+
+ qcom,v-cutoff-uv = <3400000>;
+ qcom,max-voltage-uv = <4200000>;
+ qcom,r-conn-mohm = <0>;
+ qcom,shutdown-soc-valid-limit = <100>;
+ qcom,low-soc-calculate-soc-threshold = <15>;
+ qcom,low-voltage-calculate-soc-ms = <1000>;
+ qcom,low-soc-calculate-soc-ms = <5000>;
+ qcom,calculate-soc-ms = <20000>;
+ qcom,volatge-soc-timeout-ms = <60000>;
+ qcom,low-voltage-threshold = <3450000>;
+ qcom,s3-ocv-tolerence-uv = <1200>;
+ qcom,s2-fifo-length = <5>;
+ qcom,low-soc-fifo-length = <2>;
+ io-channels = <&pm8916_vadc VADC_REF_625MV>,
+ <&pm8916_vadc VADC_REF_1250MV>,
+ <&pm8916_vadc VADC_VBAT_SNS>,
+ <&pm8916_vadc VADC_LR_MUX1_BAT_THERM>,
+ <&pm8916_vadc VADC_DIE_TEMP>,
+ <&pm8916_vadc VADC_LR_MUX2_BAT_ID>;
+ io-channel-names = "ref_625mv", "ref_1250v",
+ "vbat_sns", "batt_therm",
+ "die_temp", "batt_id";
+ qcom,bms-adc_tm = <&pm8916_adc_tm>;
+ qcom,pmic-revid = <&pm8916_revid>;
+
+ qcom,force-s3-on-suspend;
+ qcom,force-s2-in-charging;
+ qcom,report-charger-eoc;
+
+ qcom,batt-pres-status@1208 {
+ reg = <0x1208 0x1>;
+ };
+
+ qcom,qpnp-chg-pres@1008 {
+ reg = <0x1008 0x1>;
+ };
+
+ qcom,vm-bms@4000 {
+ reg = <0x4000 0x100>;
+ interrupts = <0x0 0x40 0x0 IRQ_TYPE_NONE>,
+ <0x0 0x40 0x1 IRQ_TYPE_NONE>,
+ <0x0 0x40 0x2 IRQ_TYPE_NONE>,
+ <0x0 0x40 0x3 IRQ_TYPE_NONE>,
+ <0x0 0x40 0x4 IRQ_TYPE_NONE>,
+ <0x0 0x40 0x5 IRQ_TYPE_NONE>;
+
+ interrupt-names = "leave_cv",
+ "enter_cv",
+ "good_ocv",
+ "ocv_thr",
+ "fifo_update_done",
+ "fsm_state_change";
+ };
+ };
+
+ pm8916_leds: qcom,leds@a100 {
+ compatible = "qcom,leds-qpnp";
+ reg = <0xa100 0x100>;
+ label = "mpp";
+ };
+ };
+
+ pm8916_1: pm8916@1 {
+ compatible = "qcom,pm8916", "qcom,spmi-pmic";
+ reg = <1 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pm8916_pwm: qcom,pwms@bc00 {
+ compatible = "qcom,pwm-lpg";
+ reg = <0xbc00 0x100>;
+ reg-names = "lpg-base";
+ #pwm-cells = <2>;
+ qcom,num-lpg-channels = <1>;
+ };
+
+ pm8916_vib: qcom,vibrator@c000 {
+ compatible = "qcom,qpnp-vibrator";
+ reg = <0xc000 0x100>;
+ label = "vibrator";
+ status = "disabled";
+ };
+
+ pm8916_tombak_dig: msm8x16_wcd_codec@f000 {
+ compatible = "qcom,msm8x16_wcd_codec";
+ reg = <0xf000 0x100>;
+ interrupt-parent = <&spmi_bus>;
+ interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x1 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x2 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x3 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x4 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x5 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x6 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x7 IRQ_TYPE_NONE>;
+ interrupt-names = "spk_cnp_int",
+ "spk_clip_int",
+ "spk_ocp_int",
+ "ins_rem_det1",
+ "but_rel_det",
+ "but_press_det",
+ "ins_rem_det",
+ "mbhc_int";
+
+ cdc-vdda-cp-supply = <&pm8916_s4>;
+ qcom,cdc-vdda-cp-voltage = <1800000 2200000>;
+ qcom,cdc-vdda-cp-current = <770000>;
+
+ cdc-vdda-h-supply = <&pm8916_l5>;
+ qcom,cdc-vdda-h-voltage = <1800000 1800000>;
+ qcom,cdc-vdda-h-current = <20000>;
+
+ cdc-vdd-px-supply = <&pm8916_s4>;
+ qcom,cdc-vdd-px-voltage = <1800000 2200000>;
+ qcom,cdc-vdd-px-current = <770000>;
+
+ cdc-vdd-pa-supply = <&pm8916_l5>;
+ qcom,cdc-vdd-pa-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-pa-current = <5000>;
+
+ cdc-vdd-mic-bias-supply = <&pm8916_l13>;
+ qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>;
+ qcom,cdc-vdd-mic-bias-current = <25000>;
+
+ qcom,cdc-mclk-clk-rate = <9600000>;
+
+ qcom,cdc-static-supplies = "cdc-vdda-h",
+ "cdc-vdd-px",
+ "cdc-vdd-pa",
+ "cdc-vdda-cp";
+
+ qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias";
+ qcom,subsys-name = "modem";
+ };
+
+ pm8916_tombak_analog: msm8x16_wcd_codec@f100 {
+ compatible = "qcom,msm8x16_wcd_codec";
+ reg = <0xf100 0x100>;
+ interrupt-parent = <&spmi_bus>;
+ interrupts = <0x1 0xf1 0x0 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x1 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x2 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x3 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x4 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x5 IRQ_TYPE_NONE>;
+ interrupt-names = "ear_ocp_int",
+ "hphr_ocp_int",
+ "hphl_ocp_det",
+ "ear_cnp_int",
+ "hphr_cnp_int",
+ "hphl_cnp_int";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm8937-rpm-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm8937-rpm-regulator.dtsi
new file mode 100755
index 0000000..8ecb8d0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm8937-rpm-regulator.dtsi
@@ -0,0 +1,371 @@
+&rpm_bus {
+ rpm-regulator-smpa1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_s1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_s2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_s3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa4 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <4>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s4 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_s4";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa5 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <5>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l5 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l5";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa6 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <6>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l6 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l6";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa7 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <7>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l7 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l7";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa8 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <8>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l8 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l8";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa9 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <9>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l9 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l9";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa10 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <10>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l10 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l10";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa11 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <11>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l11 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l11";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa12 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <12>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l12 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l12";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa13 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <13>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <5000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l13 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l13";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa14 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <14>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <5000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l14 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l14";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa15 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <15>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <5000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l15 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l15";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa16 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <16>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <5000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l16 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l16";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa17 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <17>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l17 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l17";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa19 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <19>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l19 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l19";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa22 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <22>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l22 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l22";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa23 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <23>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l23 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8937_l23";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm8937.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm8937.dtsi
new file mode 100755
index 0000000..701ad1c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm8937.dtsi
@@ -0,0 +1,429 @@
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+
+ qcom,pm8937@0 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pm8937_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>,
+ <0x0 0x8 0x1 IRQ_TYPE_NONE>,
+ <0x0 0x8 0x4 IRQ_TYPE_NONE>,
+ <0x0 0x8 0x5 IRQ_TYPE_NONE>;
+ interrupt-names = "kpdpwr", "resin",
+ "resin-bark", "kpdpwr-resin-bark";
+ qcom,pon-dbc-delay = <15625>;
+ qcom,system-reset;
+ qcom,store-hard-reset-reason;
+
+ qcom,pon_1 {
+ qcom,pon-type = <0>;
+ qcom,pull-up = <1>;
+ linux,code = <116>;
+ };
+
+ qcom,pon_2 {
+ qcom,pon-type = <1>;
+ qcom,pull-up = <1>;
+ linux,code = <114>;
+ };
+ };
+
+ pm8937_tz: qcom,temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pm8937_vadc VADC_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+
+ pm8937_rtc: qcom,pm8937_rtc {
+ compatible = "qcom,pm8941-rtc";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ };
+
+ pm8937_mpps: mpps {
+ compatible = "qcom,spmi-mpp";
+ reg = <0xa000 0x400>;
+ interrupts = <0x0 0xa0 0 IRQ_TYPE_NONE>,
+ <0x0 0xa1 0 IRQ_TYPE_NONE>,
+ <0x0 0xa2 0 IRQ_TYPE_NONE>,
+ <0x0 0xa3 0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm8937_mpp1", "pm8937_mpp2",
+ "pm8937_mpp3", "pm8937_mpp4";
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ case_therm {
+ cas_therm_default: cas_therm_default {
+ pins = "mpp4";
+ function = "analog";
+ input-enable;
+ qcom,amux-route = <3>;
+ };
+ };
+
+ pa_therm1 {
+ pa_therm1_default: pa_therm1_default {
+ pins = "mpp2";
+ function = "analog";
+ input-enable;
+ qcom,amux-route = <1>;
+ };
+ };
+ };
+
+ pm8937_gpios: gpios {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0x800>;
+ interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>,
+ <0x0 0xc1 0 IRQ_TYPE_NONE>,
+ <0x0 0xc4 0 IRQ_TYPE_NONE>,
+ <0x0 0xc6 0 IRQ_TYPE_NONE>,
+ <0x0 0xc7 0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm8937_gpio1", "pm8937_gpio2",
+ "pm8937_gpio5", "pmi8937_gpio7",
+ "pm8937_gpio8";
+ gpio-controller;
+ #gpio-cells = <2>;
+ qcom,gpios-disallowed = <3 4 6>;
+ };
+
+ pm8937_vadc: vadc@3100 {
+ compatible = "qcom,spmi-vadc";
+ reg = <0x3100 0x100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pa_therm1_default &cas_therm_default>;
+
+ /* Channel nodes */
+ vcoin {
+ reg = <VADC_VCOIN>;
+ label = "vcoin";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vph_pwr {
+ reg = <VADC_VSYS>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ die_temp {
+ reg = <VADC_DIE_TEMP>;
+ label = "die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_625mv {
+ reg = <VADC_REF_625MV>;
+ label = "ref_625mv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_1250v {
+ reg = <VADC_REF_1250MV>;
+ label = "ref_1250v";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_buf_625mv {
+ reg = <VADC_SPARE1>;
+ label = "ref_buf_625mv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_vdd {
+ reg = <VADC_VDD_VADC>;
+ label = "ref_vdd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_gnd {
+ reg = <VADC_GND_REF>;
+ label = "ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm0 {
+ reg = <VADC_LR_MUX7_HW_ID>;
+ label = "pa_therm0";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1 {
+ reg = <VADC_P_MUX2_1_1>;
+ label = "pa_therm1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm {
+ reg = <VADC_LR_MUX3_XO_THERM>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm_buf {
+ reg = <VADC_LR_MUX3_BUF_XO_THERM>;
+ label = "xo_therm_buf";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ case_therm {
+ reg = <VADC_P_MUX4_1_1>;
+ label = "case_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pm8937_adc_tm_iio: adc_tm_iio {
+ compatible = "qcom,adc-tm5-iio";
+ reg = <0x3500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ io-channels = <&pm8937_vadc VADC_P_MUX2_1_1>,
+ <&pm8937_vadc VADC_LR_MUX3_XO_THERM>,
+ <&pm8937_vadc
+ VADC_LR_MUX3_BUF_XO_THERM>,
+ <&pm8937_vadc VADC_P_MUX4_1_1>;
+
+ pa_therm1 {
+ reg = <VADC_P_MUX2_1_1>;
+ label = "pa_therm1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm {
+ reg = <VADC_LR_MUX3_XO_THERM>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm_buf {
+ reg = <VADC_LR_MUX3_BUF_XO_THERM>;
+ label = "xo_therm_buf";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ case_therm {
+ reg = <VADC_P_MUX4_1_1>;
+ label = "case_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pm8937_adc_tm: vadc@3400 {
+ compatible = "qcom,qpnp-adc-tm";
+ reg = <0x3400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x34 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x34 0x4 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set",
+ "high-thr-en-set",
+ "low-thr-en-set";
+ #thermal-sensor-cells = <1>;
+ qcom,adc-vdd-reference = <1800>;
+ io-channels = <&pm8937_vadc VADC_REF_625MV>,
+ <&pm8937_vadc VADC_REF_1250MV>,
+ <&pm8937_vadc VADC_VDD_VADC>,
+ <&pm8937_vadc VADC_GND_REF>;
+ io-channel-names = "ref_625mv", "ref_1250v", "ref_vdd",
+ "ref_gnd";
+
+ pa_therm0 {
+ label = "pa_therm0";
+ reg = <VADC_LR_MUX7_HW_ID>;
+ io-channels = <&pm8937_vadc VADC_LR_MUX7_HW_ID>;
+ io-channel-names = "pa_therm0";
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,ratiometric;
+ qcom,scale-fn-type = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,fast-avg-setup = <0>;
+ qcom,btm-channel-number = <0x48>;
+ qcom,thermal-node;
+ };
+
+ vph_pwr {
+ label = "vph_pwr";
+ reg = <VADC_VSYS>;
+ io-channels = <&pm8937_vadc VADC_VSYS>;
+ io-channel-names = "vph_pwr";
+ qcom,decimation = <0>;
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,scale-fn-type = <0>;
+ qcom,hw-settle-time = <0>;
+ qcom,fast-avg-setup = <0>;
+ qcom,btm-channel-number = <0x68>;
+ };
+ };
+ };
+
+ pm8937_1: qcom,pm8937@1 {
+ compatible = "qcom,spmi-pmic";
+ reg = <1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pm8937_pwm: pwm@bc00 {
+ status = "disabled";
+ compatible = "qcom,qpnp-pwm";
+ reg = <0xbc00 0x100>;
+ reg-names = "qpnp-lpg-channel-base";
+ qcom,channel-id = <0>;
+ qcom,supported-sizes = <6>, <9>;
+ #pwm-cells = <2>;
+ };
+ };
+};
+
+&thermal_zones {
+ pa-therm1-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8937_adc_tm_iio VADC_P_MUX2_1_1>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8937_adc_tm_iio VADC_LR_MUX3_XO_THERM>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-buf-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8937_adc_tm_iio
+ VADC_LR_MUX3_BUF_XO_THERM>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ case-therm-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8937_adc_tm_iio VADC_P_MUX4_1_1>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa-therm0-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8937_adc_tm VADC_LR_MUX7_HW_ID>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8937_tz {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8937_tz>;
+ wake-capable-sensor;
+
+ trips {
+ pm8937_trip0: pm8937-trip0 {
+ temperature = <105000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm8937_trip1: pm8937-trip1 {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm8937_trip2: pm8937-trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm8953-rpm-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm8953-rpm-regulator.dtsi
new file mode 100755
index 0000000..3c10ed7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm8953-rpm-regulator.dtsi
@@ -0,0 +1,386 @@
+&rpm_bus {
+ rpm-regulator-smpa1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_s1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_s2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_s3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa4 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <4>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s4 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_s4";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-smpa7 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "smpa";
+ qcom,resource-id = <7>;
+ qcom,regulator-type = <1>;
+ qcom,hpm-min-load = <100000>;
+ status = "disabled";
+
+ regulator-s7 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_s7";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa1 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <1>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l1";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa2 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <2>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l2";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa3 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l3";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa5 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <5>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l5 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l5";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa6 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <6>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l6 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l6";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa7 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <7>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l7 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l7";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa8 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <8>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l8 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l8";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa9 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <9>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l9 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l9";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa10 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <10>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l10 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l10";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa11 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <11>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l11 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l11";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa12 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <12>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l12 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l12";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa13 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <13>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <5000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l13 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l13";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa16 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <16>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <5000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l16 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l16";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa17 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <17>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l17 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l17";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa19 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <19>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l19 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l19";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa22 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <22>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l22 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l22";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ rpm-regulator-ldoa23 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <23>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ qcom,regulator-hw-type = "pmic4-ldo";
+ status = "disabled";
+
+ regulator-l23 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l23";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+
+ /* Regulator to notify APC corner to RPM */
+ rpm-regulator-clk0 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "clk0";
+ qcom,resource-id = <3>;
+ qcom,regulator-type = <1>;
+ status = "disabled";
+
+ regulator-clk0 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "rpm_apc";
+ qcom,set = <3>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pm8953.dtsi b/arch/arm64/boot/dts/vendor/qcom/pm8953.dtsi
new file mode 100755
index 0000000..ba8b071
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pm8953.dtsi
@@ -0,0 +1,379 @@
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+
+ qcom,pm8953@0 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pm8953_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>,
+ <0x0 0x8 0x1 IRQ_TYPE_NONE>,
+ <0x0 0x8 0x4 IRQ_TYPE_NONE>,
+ <0x0 0x8 0x5 IRQ_TYPE_NONE>;
+ interrupt-names = "kpdpwr", "resin",
+ "resin-bark", "kpdpwr-resin-bark";
+ qcom,pon-dbc-delay = <15625>;
+ qcom,system-reset;
+ qcom,store-hard-reset-reason;
+
+ qcom,pon_1 {
+ qcom,pon-type = <0>;
+ qcom,pull-up = <1>;
+ linux,code = <116>;
+ };
+
+ qcom,pon_2 {
+ qcom,pon-type = <1>;
+ qcom,pull-up = <1>;
+ linux,code = <114>;
+ };
+ };
+
+ pm8953_tz: qcom,temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
+ io-channels = <&pm8953_vadc VADC_DIE_TEMP>;
+ io-channel-names = "thermal";
+ #thermal-sensor-cells = <0>;
+ };
+
+ pm8953_mpps: mpps {
+ compatible = "qcom,spmi-mpp";
+ reg = <0xa000 0x400>;
+
+ interrupts = <0x0 0xa0 0 IRQ_TYPE_NONE>,
+ <0x0 0xa1 0 IRQ_TYPE_NONE>,
+ <0x0 0xa2 0 IRQ_TYPE_NONE>,
+ <0x0 0xa3 0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm8953_mpp1", "pm8953_mpp2",
+ "pm8953_mpp3", "pm8953_mpp4";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ case_therm {
+ cas_therm_default: cas_therm_default {
+ pins = "mpp4";
+ function = "analog";
+ input-enable;
+ qcom,amux-route = <3>;
+ };
+ };
+
+ pa_therm1 {
+ pa_therm1_default: pa_therm1_default {
+ pins = "mpp2";
+ function = "analog";
+ input-enable;
+ qcom,amux-route = <1>;
+ };
+ };
+ };
+
+ pm8953_gpios: gpios {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0x800>;
+
+ interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>,
+ <0x0 0xc1 0 IRQ_TYPE_NONE>,
+ <0x0 0xc3 0 IRQ_TYPE_NONE>,
+ <0x0 0xc4 0 IRQ_TYPE_NONE>,
+ <0x0 0xc6 0 IRQ_TYPE_NONE>,
+ <0x0 0xc7 0 IRQ_TYPE_NONE>;
+ interrupt-names = "pm8953_gpio1", "pm8953_gpio2",
+ "pm8953_gpio4", "pm8953_gpio5",
+ "pm8953_gpio7", "pm8953_gpio8";
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ qcom,gpios-disallowed = <3 6>;
+ };
+
+ pm8953_vadc: vadc@3100 {
+ compatible = "qcom,spmi-vadc";
+ reg = <0x3100 0x100>;
+ interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pa_therm1_default &cas_therm_default>;
+
+ /* Channel nodes */
+ vcoin {
+ reg = <VADC_VCOIN>;
+ label = "vcoin";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vph_pwr {
+ reg = <VADC_VSYS>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ die_temp {
+ reg = <VADC_DIE_TEMP>;
+ label = "die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_625mv {
+ reg = <VADC_REF_625MV>;
+ label = "ref_625mv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_1250v {
+ reg = <VADC_REF_1250MV>;
+ label = "ref_1250v";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_buf_625mv {
+ reg = <VADC_SPARE1>;
+ label = "ref_buf_625mv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_vdd {
+ reg = <VADC_VDD_VADC>;
+ label = "ref_vdd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ ref_gnd {
+ reg = <VADC_GND_REF>;
+ label = "ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm0 {
+ reg = <VADC_LR_MUX7_HW_ID>;
+ label = "pa_therm0";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm1 {
+ reg = <VADC_P_MUX2_1_1>;
+ label = "pa_therm1";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm {
+ reg = <VADC_LR_MUX3_XO_THERM>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm_buf {
+ reg = <VADC_LR_MUX3_BUF_XO_THERM>;
+ label = "xo_therm_buf";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ case_therm {
+ reg = <VADC_P_MUX4_1_1>;
+ label = "case_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pm8953_adc_tm_iio: adc_tm_iio {
+ compatible = "qcom,adc-tm5-iio";
+ reg = <0x3500 0x100>;
+ #thermal-sensor-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ io-channels = <&pm8953_vadc VADC_LR_MUX3_BUF_XO_THERM>;
+
+ xo_therm_buf {
+ reg = <VADC_LR_MUX3_BUF_XO_THERM>;
+ label = "xo_therm_buf";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pm8953_adc_tm: vadc@3400 {
+ compatible = "qcom,qpnp-adc-tm";
+ reg = <0x3400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x34 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0x34 0x4 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set",
+ "high-thr-en-set",
+ "low-thr-en-set";
+ #thermal-sensor-cells = <1>;
+ qcom,adc-vdd-reference = <1800>;
+ io-channels = <&pm8953_vadc VADC_REF_625MV>,
+ <&pm8953_vadc VADC_REF_1250MV>,
+ <&pm8953_vadc VADC_VDD_VADC>,
+ <&pm8953_vadc VADC_GND_REF>;
+ io-channel-names = "ref_625mv", "ref_1250v", "ref_vdd",
+ "ref_gnd";
+
+ pa_therm0 {
+ label = "pa_therm0";
+ reg = <VADC_LR_MUX7_HW_ID>;
+ io-channels = <&pm8953_vadc VADC_LR_MUX7_HW_ID>;
+ io-channel-names = "pa_therm0";
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,decimation = <0>;
+ qcom,ratiometric;
+ qcom,scale-fn-type = <2>;
+ qcom,hw-settle-time = <2>;
+ qcom,btm-channel-number = <0x48>;
+ qcom,fast-avg-setup = <0>;
+ qcom,thermal-node;
+ };
+
+ xo_therm {
+ label = "xo_therm";
+ reg = <VADC_LR_MUX3_XO_THERM>;
+ io-channels = <&pm8953_vadc
+ VADC_LR_MUX3_XO_THERM>;
+ io-channel-names = "xo_therm";
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,decimation = <0>;
+ qcom,ratiometric;
+ qcom,scale-fn-type = <4>;
+ qcom,hw-settle-time = <2>;
+ qcom,btm-channel-number = <0x68>;
+ qcom,fast-avg-setup = <0>;
+ qcom,thermal-node;
+ };
+ };
+
+ pm8953_rtc: qcom,pm8953_rtc {
+ compatible = "qcom,pm8916-rtc";
+ interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
+ };
+
+ pm8953_typec: qcom,pm8953_typec@bf00 {
+ compatible = "qcom,qpnp-typec";
+ reg = <0xbf00 0x100>;
+ interrupts = <0x0 0xbf 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0xbf 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0xbf 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0xbf 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0xbf 0x4 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0xbf 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x0 0xbf 0x7 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "vrd-change",
+ "ufp-detect",
+ "ufp-detach",
+ "dfp-detect",
+ "dfp-detach",
+ "vbus-err",
+ "vconn-oc";
+ };
+ };
+
+ pm8953_1: qcom,pm8953@1 {
+ compatible = "qcom,spmi-pmic";
+ reg = <1 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pm8953_pwm: qcom,pwms@bc00 {
+ status = "disabled";
+ compatible = "qcom,pwm-lpg";
+ reg = <0xbc00 0x100>;
+ reg-names = "lpg-base";
+ #pwm-cells = <2>;
+ qcom,num-lpg-channels = <1>;
+ };
+ };
+};
+
+&thermal_zones {
+ xo-therm-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8953_adc_tm VADC_LR_MUX3_XO_THERM>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-buf-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8953_adc_tm_iio
+ VADC_LR_MUX3_BUF_XO_THERM>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pm8953_temp_alarm: pm8953_tz {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8953_tz>;
+ wake-capable-sensor;
+
+ trips {
+ pm8953_trip0: pm8953-trip0 {
+ temperature = <105000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm8953_trip1: pm8953-trip1 {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm8953_trip2: pm8953-trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pmi632.dtsi b/arch/arm64/boot/dts/vendor/qcom/pmi632.dtsi
new file mode 100755
index 0000000..92636bd
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pmi632.dtsi
@@ -0,0 +1,776 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&spmi_bus {
+ qcom,pmi632@2 {
+ compatible = "qcom,spmi-pmic";
+ reg = <0x2 0x0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pmi632_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ pmi632_pon: qcom,power-on@800 {
+ compatible = "qcom,qpnp-power-on";
+ reg = <0x800 0x100>;
+ };
+
+ pmi632_vadc: vadc@3100 {
+ compatible = "qcom,spmi-adc5-lite";
+ reg = <0x3100 0x100>, <0x3700 0x100>;
+ reg-names = "adc5-usr-base", "adc5-cal-base";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x2 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set";
+ qcom,adc-vdd-reference = <1875>;
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+ qcom,pmic-revid = <&pmi632_revid>;
+
+ /* Channel nodes */
+ ref_gnd {
+ reg = <ADC_REF_GND>;
+ label = "ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref_1p25 {
+ reg = <ADC_1P25VREF>;
+ label = "vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ die_temp {
+ reg = <ADC_DIE_TEMP>;
+ label = "die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vph_pwr {
+ reg = <ADC_VPH_PWR>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vbat_sns {
+ reg = <ADC_VBAT_SNS>;
+ label = "vbat_sns";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ usb_in_i_uv {
+ reg = <ADC_USB_IN_I>;
+ label = "usb_in_i_uv";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ usb_in_v_div_16 {
+ reg = <ADC_USB_IN_V_16>;
+ label = "usb_in_v_div_16";
+ qcom,pre-scaling = <1 16>;
+ };
+
+ chg_temp {
+ reg = <ADC_CHG_TEMP>;
+ label = "chg_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bat_therm {
+ reg = <ADC_BAT_THERM_PU2>;
+ label = "bat_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bat_therm_30k {
+ reg = <ADC_BAT_THERM_PU1>;
+ label = "bat_therm_30k";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bat_therm_400k {
+ reg = <ADC_BAT_THERM_PU3>;
+ label = "bat_therm_400k";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ bat_id {
+ reg = <ADC_BAT_ID_PU2>;
+ label = "bat_id";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ i_parallel {
+ reg = <ADC_PARALLEL_ISENSE>;
+ label = "i_parallel";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ v_i_int_ext {
+ reg = <ADC_INT_EXT_ISENSE_VBAT_VDATA>;
+ label = "v_i_int_vbat_vdata";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ v_i_parallel {
+ reg = <ADC_PARALLEL_ISENSE_VBAT_VDATA>;
+ label = "v_i_parallel_vbat_vdata";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ };
+
+ pmi632_adc_tm: adc_tm@3500 {
+ compatible = "qcom,adc-tm5";
+ reg = <0x3500 0x100>;
+ interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "thr-int-en";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ pmi632_tz: qcom,temp-alarm@2400 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0x2400 0x100>;
+ interrupts = <0x2 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ qcom,temperature-threshold-set = <1>;
+ };
+
+ pmi632_gpios: pinctrl@c000 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xc000 0x800>;
+ interrupts = <0x2 0xc0 0 IRQ_TYPE_NONE>,
+ <0x2 0xc1 0 IRQ_TYPE_NONE>,
+ <0x2 0xc2 0 IRQ_TYPE_NONE>,
+ <0x2 0xc3 0 IRQ_TYPE_NONE>,
+ <0x2 0xc4 0 IRQ_TYPE_NONE>,
+ <0x2 0xc5 0 IRQ_TYPE_NONE>,
+ <0x2 0xc6 0 IRQ_TYPE_NONE>,
+ <0x2 0xc7 0 IRQ_TYPE_NONE>;
+ interrupt-names = "pmi632_gpio1", "pmi632_gpio2",
+ "pmi632_gpio3", "pmi632_gpio4",
+ "pmi632_gpio5", "pmi632_gpio6",
+ "pmi632_gpio7", "pmi632_gpio8";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pmi632_charger: qcom,qpnp-smb5 {
+ compatible = "qcom,qpnp-smb5";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #cooling-cells = <2>;
+
+ qcom,pmic-revid = <&pmi632_revid>;
+ io-channels = <&pmi632_vadc ADC_USB_IN_V_16>,
+ <&pmi632_vadc ADC_USB_IN_I>,
+ <&pmi632_vadc ADC_CHG_TEMP>,
+ <&pmi632_vadc ADC_DIE_TEMP>;
+ io-channel-names = "usb_in_voltage",
+ "usb_in_current",
+ "chg_temp",
+ "die_temp";
+
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts =
+ <0x2 0x10 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x4 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x10 0x7 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "chgr-error",
+ "chg-state-change",
+ "step-chg-state-change",
+ "step-chg-soc-update-fail",
+ "step-chg-soc-update-req",
+ "fg-fvcal-qualified",
+ "vph-alarm",
+ "vph-drop-prechg";
+ };
+
+ qcom,dcdc@1100 {
+ reg = <0x1100 0x100>;
+ interrupts =
+ <0x2 0x11 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x11 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x11 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x11 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x11 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x11 0x5 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x11 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x11 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "otg-fail",
+ "otg-oc-disable-sw",
+ "otg-oc-hiccup",
+ "bsm-active",
+ "high-duty-cycle",
+ "input-current-limiting",
+ "concurrent-mode-disable",
+ "switcher-power-ok";
+ };
+
+ qcom,batif@1200 {
+ reg = <0x1200 0x100>;
+ interrupts =
+ <0x2 0x12 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x12 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x5 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x6 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x12 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "bat-temp",
+ "all-chnl-conv-done",
+ "bat-ov",
+ "bat-low",
+ "bat-therm-or-id-missing",
+ "bat-terminal-missing",
+ "buck-oc",
+ "vph-ov";
+ };
+
+ qcom,usb@1300 {
+ reg = <0x1300 0x100>;
+ interrupts =
+ <0x2 0x13 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x13 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x5 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x13 0x7 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "usbin-collapse",
+ "usbin-vashdn",
+ "usbin-uv",
+ "usbin-ov",
+ "usbin-plugin",
+ "usbin-revi-change",
+ "usbin-src-change",
+ "usbin-icl-change";
+ };
+
+ qcom,typec@1500 {
+ reg = <0x1500 0x100>;
+ interrupts =
+ <0x2 0x15 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x15 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x15 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x15 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x15 0x7 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "typec-or-rid-detect-change",
+ "typec-vpd-detect",
+ "typec-cc-state-change",
+ "typec-vconn-oc",
+ "typec-vbus-change",
+ "typec-attach-detach",
+ "typec-legacy-cable-detect",
+ "typec-try-snk-src-detect";
+ };
+
+ qcom,misc@1600 {
+ reg = <0x1600 0x100>;
+ interrupts =
+ <0x2 0x16 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x16 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x16 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x16 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x16 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x16 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x16 0x7 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "wdog-snarl",
+ "wdog-bark",
+ "aicl-fail",
+ "aicl-done",
+ "smb-en",
+ "imp-trigger",
+ "temp-change",
+ "temp-change-smb";
+ };
+
+ qcom,schgm-flash@a600 {
+ reg = <0xa600 0x100>;
+ interrupts =
+ <0x2 0xa6 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0xa6 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0xa6 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0xa6 0x7 IRQ_TYPE_EDGE_BOTH>;
+
+ interrupt-names = "flash-state-change",
+ "ilim1-s1",
+ "ilim2-s2",
+ "vreg-ok";
+ };
+ smb5_vbus: qcom,smb5-vbus {
+ regulator-name = "smb5-vbus";
+ };
+ };
+
+ pmi632_qg: qpnp,qg {
+ compatible = "qcom,qpnp-qg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qcom,pmic-revid = <&pmi632_revid>;
+ io-channels = <&pmi632_vadc ADC_BAT_THERM_PU2>,
+ <&pmi632_vadc ADC_BAT_ID_PU2>;
+ io-channel-names = "batt-therm",
+ "batt-id";
+
+ qcom,qgauge@4800 {
+ status = "okay";
+ reg = <0x4800 0x100>;
+ interrupts =
+ <0x2 0x48 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x48 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x2 0x48 0x2 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x48 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x2 0x48 0x4 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "qg-batt-missing",
+ "qg-vbat-low",
+ "qg-vbat-empty",
+ "qg-fifo-done",
+ "qg-good-ocv";
+ };
+
+ qcom,qg-sdam@b100 {
+ status = "okay";
+ reg = <0xb100 0x100>;
+ };
+ };
+
+ pmi632_pbs_client3: qcom,pbs@7400 {
+ compatible = "qcom,qpnp-pbs";
+ reg = <0x7400 0x100>;
+ };
+
+ pmi632_sdam7: qcom,sdam@b600 {
+ compatible = "qcom,spmi-sdam";
+ reg = <0xb600 0x100>;
+ };
+
+ bcl_sensor: bcl@3d00 {
+ compatible = "qcom,bcl-v5";
+ reg = <0x3d00 0x100>;
+ interrupts = <0x2 0x3d 0x0 IRQ_TYPE_NONE>,
+ <0x2 0x3d 0x1 IRQ_TYPE_NONE>,
+ <0x2 0x3d 0x2 IRQ_TYPE_NONE>;
+ interrupt-names = "bcl-lvl0",
+ "bcl-lvl1",
+ "bcl-lvl2";
+ qcom,ibat-use-qg-adc-5a;
+ #thermal-sensor-cells = <1>;
+ };
+
+ bcl_soc: bcl-soc {
+ compatible = "qcom,msm-bcl-soc";
+ #thermal-sensor-cells = <0>;
+ };
+ };
+
+ pmi632_3: qcom,pmi632@3 {
+ compatible ="qcom,spmi-pmic";
+ reg = <0x3 0x0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pmi632_vib: qcom,vibrator@5700 {
+ compatible = "qcom,qpnp-vibrator-ldo";
+ reg = <0x5700 0x100>;
+ qcom,vib-ldo-volt-uv = <3000000>;
+ qcom,disable-overdrive;
+ };
+
+ pmi632_pwm: qcom,pwms@b300 {
+ compatible = "qcom,pwm-lpg";
+ reg = <0xb300 0x500>;
+ reg-names = "lpg-base";
+ #pwm-cells = <2>;
+ qcom,num-lpg-channels = <5>;
+ nvmem-names = "ppg_sdam";
+ nvmem = <&pmi632_sdam7>;
+ qcom,pbs-client = <&pmi632_pbs_client3>;
+ qcom,lut-sdam-base = <0x80>;
+ qcom,lut-patterns = <0 0 0 14 28 42 56 70 84 100
+ 100 84 70 56 42 28 14 0 0 0>;
+ lpg@1 {
+ qcom,lpg-chan-id = <1>;
+ qcom,ramp-step-ms = <200>;
+ qcom,ramp-low-index = <0>;
+ qcom,ramp-high-index = <19>;
+ qcom,ramp-pattern-repeat;
+ qcom,lpg-sdam-base = <0x48>;
+ };
+
+ lpg@2 {
+ qcom,lpg-chan-id = <2>;
+ qcom,ramp-step-ms = <200>;
+ qcom,ramp-low-index = <0>;
+ qcom,ramp-high-index = <19>;
+ qcom,ramp-pattern-repeat;
+ qcom,lpg-sdam-base = <0x56>;
+ };
+
+ lpg@3 {
+ qcom,lpg-chan-id = <3>;
+ qcom,ramp-step-ms = <200>;
+ qcom,ramp-low-index = <0>;
+ qcom,ramp-high-index = <19>;
+ qcom,ramp-pattern-repeat;
+ qcom,lpg-sdam-base = <0x64>;
+ };
+ };
+
+ pmi632_rgb: qcom,leds@d000 {
+ compatible = "qcom,tri-led";
+ reg = <0xd000 0x100>;
+ red {
+ label = "red";
+ pwms = <&pmi632_pwm 0 1000000>;
+ led-sources = <0>;
+ linux,default-trigger = "timer";
+ };
+
+ green {
+ label = "green";
+ pwms = <&pmi632_pwm 1 1000000>;
+ led-sources = <1>;
+ linux,default-trigger = "timer";
+ };
+
+ blue {
+ label = "blue";
+ pwms = <&pmi632_pwm 2 1000000>;
+ led-sources = <2>;
+ linux,default-trigger = "timer";
+ };
+ };
+
+ pmi632_lcdb: qpnp-lcdb@ec00 {
+ compatible = "qcom,qpnp-lcdb-regulator";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xec00 0x100>;
+ interrupts = <0x3 0xec 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "sc-irq";
+
+ qcom,pmic-revid = <&pmi632_revid>;
+ qcom,voltage-step-ramp;
+
+ lcdb_ldo_vreg: ldo {
+ label = "ldo";
+ regulator-name = "lcdb_ldo";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6000000>;
+ };
+
+ lcdb_ncp_vreg: ncp {
+ label = "ncp";
+ regulator-name = "lcdb_ncp";
+ regulator-min-microvolt = <4000000>;
+ regulator-max-microvolt = <6000000>;
+ };
+
+ lcdb_bst_vreg: bst {
+ label = "bst";
+ regulator-name = "lcdb_bst";
+ regulator-min-microvolt = <4700000>;
+ regulator-max-microvolt = <6275000>;
+ };
+ };
+
+ flash_led: qcom,leds@d300 {
+ compatible = "qcom,qpnp-flash-led-v2";
+ status = "okay";
+ reg = <0xd300 0x100>;
+ label = "flash";
+ interrupts = <0x3 0xd3 0x0 IRQ_TYPE_EDGE_RISING>,
+ <0x3 0xd3 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x3 0xd3 0x4 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "led-fault-irq",
+ "all-ramp-down-done-irq",
+ "all-ramp-up-done-irq";
+ qcom,short-circuit-det;
+ qcom,open-circuit-det;
+ qcom,vph-droop-det;
+ qcom,thermal-derate-en;
+ qcom,thermal-derate-current = <200 500 1000>;
+ qcom,isc-delay = <192>;
+ qcom,pmic-revid = <&pmi632_revid>;
+
+ pmi632_flash0: qcom,flash_0 {
+ label = "flash";
+ qcom,led-name = "led:flash_0";
+ qcom,max-current = <1500>;
+ qcom,default-led-trigger = "flash0_trigger";
+ qcom,id = <0>;
+ qcom,current-ma = <1000>;
+ qcom,duration-ms = <1280>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <400>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pmi632_flash1: qcom,flash_1 {
+ label = "flash";
+ qcom,led-name = "led:flash_1";
+ qcom,max-current = <1500>;
+ qcom,default-led-trigger = "flash1_trigger";
+ qcom,id = <1>;
+ qcom,current-ma = <1000>;
+ qcom,duration-ms = <1280>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <400>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pmi632_torch0: qcom,torch_0 {
+ label = "torch";
+ qcom,led-name = "led:torch_0";
+ qcom,max-current = <500>;
+ qcom,default-led-trigger = "torch0_trigger";
+ qcom,id = <0>;
+ qcom,current-ma = <300>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <400>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pmi632_torch1: qcom,torch_1 {
+ label = "torch";
+ qcom,led-name = "led:torch_1";
+ qcom,max-current = <500>;
+ qcom,default-led-trigger = "torch1_trigger";
+ qcom,id = <1>;
+ qcom,current-ma = <300>;
+ qcom,ires-ua = <12500>;
+ qcom,hdrm-voltage-mv = <400>;
+ qcom,hdrm-vol-hi-lo-win-mv = <100>;
+ };
+
+ pmi632_switch0: qcom,led_switch_0 {
+ label = "switch";
+ qcom,led-name = "led:switch_0";
+ qcom,led-mask = <3>;
+ qcom,default-led-trigger = "switch0_trigger";
+ };
+
+ pmi632_switch1: qcom,led_switch_1 {
+ label = "switch";
+ qcom,led-name = "led:switch_1";
+ qcom,led-mask = <2>;
+ qcom,default-led-trigger = "switch1_trigger";
+ };
+
+ };
+
+ };
+};
+
+&thermal_zones {
+ pmi632-tz {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pmi632_tz>;
+ wake-capable-sensor;
+
+ trips {
+ pmi632_trip0: trip0 {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pmi632_trip1: trip1 {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmi632-ibat-lvl0 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&bcl_sensor 0>;
+ wake-capable-sensor;
+
+ trips {
+ pmi632_ibat_lvl0: ibat-lvl0 {
+ temperature = <4000>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmi632-ibat-lvl1 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&bcl_sensor 1>;
+ wake-capable-sensor;
+
+ trips {
+ pmi632_ibat_lvl1: ibat-lvl1 {
+ temperature = <4200>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmi632-vbat-lvl0 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&bcl_sensor 2>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ pmi632_vbat_lvl0: vbat-lvl0 {
+ temperature = <3000>;
+ hysteresis = <100>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmi632-vbat-lvl1 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&bcl_sensor 3>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ pmi632_vbat_lvl1: vbat-lvl1 {
+ temperature = <2800>;
+ hysteresis = <100>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmi632-vbat-lvl2 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&bcl_sensor 4>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ pmi632_vbat_lvl2: vbat-lvl1 {
+ temperature = <2600>;
+ hysteresis = <100>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmi632-bcl-lvl0 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&bcl_sensor 5>;
+ wake-capable-sensor;
+
+ trips {
+ bcl_lvl0: bcl-lvl0 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmi632-bcl-lvl1 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&bcl_sensor 6>;
+ wake-capable-sensor;
+
+ trips {
+ bcl_lvl1: bcl-lvl1 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+
+ pmi632-bcl-lvl2 {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&bcl_sensor 7>;
+ wake-capable-sensor;
+
+ trips {
+ bcl_lvl2: bcl-lvl2 {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+ };
+
+ soc {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&bcl_soc>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ pmi632_low_soc: low-soc {
+ temperature = <10>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/vendor/qcom/pmk8350.dtsi
new file mode 100755
index 0000000..34e012c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pmk8350.dtsi
@@ -0,0 +1,106 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+#define PMK8350_SID 6
+
+#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
+
+&spmi_bus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ qcom,pmk8350@6 {
+ compatible = "qcom,spmi-pmic";
+ reg = <6 SPMI_USID>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ pmk8350_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ pmk8350_vadc: vadc@3100 {
+ compatible = "qcom,spmi-adc7";
+ reg = <0x3100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0x6 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "eoc-int-en-set";
+ #io-channel-cells = <1>;
+ io-channel-ranges;
+
+ /* Channel nodes */
+ ref_gnd {
+ reg = <PMK8350_ADC7_REF_GND>;
+ label = "ref_gnd";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ vref_1p25 {
+ reg = <PMK8350_ADC7_1P25VREF>;
+ label = "vref_1p25";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ die_temp {
+ reg = <PMK8350_ADC7_DIE_TEMP>;
+ label = "die_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm {
+ reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+ };
+
+ pmk8350_adc_tm: adc_tm@3400 {
+ compatible = "qcom,adc-tm7";
+ reg = <0x3400>;
+ interrupts = <0x6 0x34 0x0 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "thr-int-en";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ pmk8350_rtc: rtc@6100 {
+ compatible = "qcom,pmk8350-rtc";
+ reg = <0x6100>, <0x6200>;
+ reg-names = "rtc", "alarm";
+ interrupts = <0x6 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
+ };
+
+ pmk8350_gpios: pinctrl@b000 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0xb000 0x400>;
+ interrupts = <0x6 0xb0 0x0 IRQ_TYPE_NONE>,
+ <0x6 0xb1 0x0 IRQ_TYPE_NONE>,
+ <0x6 0xb2 0x0 IRQ_TYPE_NONE>,
+ <0x6 0xb3 0x0 IRQ_TYPE_NONE>;
+ interrupt-names = "pmk8350_gpio1", "pmk8350_gpio2",
+ "pmk8350_gpio3", "pmk8350_gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pmk8350_clkdiv: clock-controller@5e00 {
+ compatible = "qcom,spmi-clkdiv";
+ status = "ok";
+ reg = <0x5e00 0x100>;
+ #clock-cells = <1>;
+ qcom,num-clkdivs = <1>;
+ clock-output-names = "pmk8350_div_clk1";
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+ assigned-clocks = <&pmk8350_clkdiv 1>;
+ assigned-clock-rates = <19200000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pmr735b.dtsi b/arch/arm64/boot/dts/vendor/qcom/pmr735b.dtsi
new file mode 100755
index 0000000..2d085ab
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pmr735b.dtsi
@@ -0,0 +1,42 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/spmi/spmi.h>
+
+&spmi_bus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ qcom,pmr735b@a {
+ compatible = "qcom,spmi-pmic";
+ reg = <10 SPMI_USID>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pmr735b_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ pmr735b_tz: qcom,temp-alarm@a00 {
+ compatible = "qcom,spmi-temp-alarm";
+ reg = <0xa00 0x100>;
+ interrupts = <0xa 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
+ #thermal-sensor-cells = <0>;
+ qcom,temperature-threshold-set = <1>;
+ };
+
+ pmr735b_gpios: pinctrl@8800 {
+ compatible = "qcom,spmi-gpio";
+ reg = <0x8800 0x400>;
+ interrupts = <0xa 0x88 0x0 IRQ_TYPE_NONE>,
+ <0xa 0x89 0x0 IRQ_TYPE_NONE>,
+ <0xa 0x8a 0x0 IRQ_TYPE_NONE>,
+ <0xa 0x8b 0x0 IRQ_TYPE_NONE>;
+ interrupt-names = "pmr735b_gpio1", "pmr735b_gpio2",
+ "pmr735b_gpio3", "pmr735b_gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pxlw/pxlw-iris6-cfg-dsi-panel-hx83112a-auo-1080p-video.dtsi b/arch/arm64/boot/dts/vendor/qcom/pxlw/pxlw-iris6-cfg-dsi-panel-hx83112a-auo-1080p-video.dtsi
new file mode 100644
index 0000000..b3702f5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pxlw/pxlw-iris6-cfg-dsi-panel-hx83112a-auo-1080p-video.dtsi
@@ -0,0 +1,2130 @@
+// build : 06-30-2021 15:30
+// workbook: v1.18
+// panel : dsi-panel-hx83112a-auo-1080p-video
+// cfg : t2m_v1
+&soc {
+pxlw {
+mdss_iris_cfg_hx83112a_auo_fhd_60fps_video: pxlw,mdss_iris_cfg_hx83112a_auo_fhd_60fps_video {
+pxlw,platform = <1>;
+pxlw,panel-type = "PANEL_OLED";
+/*low power control: dynamic power gating, ulps low power, analog bypass */
+pxlw,low-power = [00 00 01];
+/*light up path, pq update path, single-ipopt path, 0-dsi, 1-i2c */
+pxlw,path-sel = [00 00 00];
+pxlw,chip-ver = <0x6936>;
+pxlw,iris-chip-enable;
+pxlw,iris-soft-disable;
+pxlw,iris-default-mode-pt;
+pxlw,pkt-payload-size = <228>;
+pxlw,last-per-pkt = <1>;
+pxlw,min-color-temp = <2500>;
+pxlw,max-color-temp = <10000>;
+pxlw,vivid-color-temp = <6500>;
+pxlw,P3-color-temp = <7500>;
+pxlw,sRGB-color-temp = <7500>;
+pxlw,hdr-color-temp = <7500>;
+//pxlw,virtual-channel-enable;
+pxlw,virtual-channel-id = [00 02 03];
+pxlw,dsi-embedded-enable = [00 02];
+pxlw,non-embedded-mode-transfer-length = <0x0 0x400>;
+pxlw,dpp-only-enable = <0>;
+pxlw,qsync-mode = <0>;
+pxlw,esd-ctrl = <0>;
+pxlw,iris-lightup-sequence-pre = [
+/*mipi rx*/
+01 f1 00
+];
+pxlw,iris-lightup-sequence-pre0 = [
+/*sys*/
+00 a0 00
+00 00 00
+00 07 00
+];
+pxlw,iris-lightup-sequence-pre1 = [
+/*sys*/
+00 a0 00
+00 00 00
+00 07 00
+];
+
+pxlw,iris-lightup-sequence = [
+/* rx ctrl */
+01 f0 01
+/* tx */
+02 01 01
+02 00 00
+/* mipi dma */
+01 e0 01
+01 e3 01
+/* dtg */
+05 00 01
+05 f0 01
+/* dma */
+11 e1 00
+/* lut table */
+80 00 01
+80 01 01
+80 f1 01
+84 00 01
+84 10 01
+84 20 01
+84 30 01
+85 00 01
+85 01 01
+85 02 01
+85 03 01
+85 04 01
+85 05 01
+86 00 01
+86 11 01
+86 20 01
+86 30 01
+86 40 01
+86 50 01
+86 60 01
+86 70 01
+/* dbc */
+0f f0 01
+0f 00 01
+0f fc 01
+/* blc_pwm */
+06 f0 01
+06 00 01
+/* scaler1d */
+0b f0 01
+/* dport */
+04 f0 01
+04 80 01
+/* pwil */
+03 f0 01
+03 d0 01
+03 80 01
+03 fc 01
+03 51 01
+/*3d-lut, 17*/
+81 00 01
+81 01 01
+81 02 01
+81 03 01
+81 04 01
+81 05 01
+/*gamma,65-bin*/
+83 00 01
+/*dpp dither*/
+89 00 01
+/*dpp*/
+0e 00 01
+0e 10 01
+0e 20 01
+0e 30 01
+0e 51 01
+0e 52 01
+0e 53 01
+0e 50 01
+0e 70 01
+0e 60 01
+0e 61 01
+0e 62 01
+0e 63 01
+0e 54 01
+0e 21 01
+0e 22 01
+0e 40 01
+0e 31 01
+0e 23 01
+0e 32 01
+0e 33 01
+0e a0 01
+0e 72 01
+0e 80 01
+/*hdr_v2*/
+09 00 01
+09 10 01
+09 20 01
+09 30 01
+09 40 01
+09 50 01
+09 60 01
+09 70 01
+09 90 01
+09 a0 01
+09 b0 01
+09 c0 01
+0a 00 01
+0a 10 01
+09 d0 01
+09 80 01
+/* dma */
+11 f0 00
+];
+
+pxlw,iris-pq-default-val = [
+/* pwil */
+03 fc
+/* dport */
+04 f0
+/* dbc PQ */
+0f 00
+0f 10
+0f fc
+/* dbc lut */
+80 00
+80 01
+80 f1
+/* blc_pwm */
+06 00
+/* scaler1d */
+84 00
+84 10
+84 20
+84 30
+/* hdr col */
+86 00
+86 11
+86 20
+86 30
+86 40
+86 50
+86 60
+86 70
+/*dpp*/
+0e 00
+0e 01
+0e 20
+0e 30
+0e 51
+0e 52
+0e 50
+0e 70
+0e 60
+0e 61
+0e 62
+0e 63
+0e 54
+0e 40
+0e 71
+81 00
+83 00
+83 10
+83 20
+/* hdr */
+09 00
+09 10
+09 20
+09 30
+09 40
+09 50
+09 60
+09 70
+09 90
+09 a0
+09 b0
+09 c0
+09 d0
+0a 00
+0a 10
+];
+
+pxlw,iris-cmd-list =
+<
+
+// mipi_rx: dphy
+0x29 0x01 0x00 0x01 0x01F1 0x013 0xFFFFFFF4
+0xF1100808 0x0D020200 0xF1100818 0x00000006 0xF1100A00 0x0000C960
+0xF1100A08 0x000002F7 0xF1100A14 0x000002F7 0xF1100A1C 0x000002F7
+0xF1100A24 0x000002F7 0xF1100A2C 0x000002F7 0xF1100800 0x00001200
+
+// mipi_rx: ctrl
+0x29 0x01 0x00 0x01 0x00F0 0x013 0xFFFFFFF4
+0xF110001C 0x00000000 0xF1100080 0x00000100 0xF1100104 0x00000000
+0xF1100144 0x0048021C 0xF1100148 0x0000021C 0xF1100238 0x00770000
+0xF1100300 0x04370000 0xF1100304 0x09230000 0xF1101804 0x00000924
+
+// mipi: man bypass ctrl
+0x29 0x01 0x00 0x01 0x00D0 0x003 0xFFFFFFF4
+0xF140001C 0xC988BC71
+
+// mipi: abyp 0
+0x29 0x00 0x00 0x01 0x00E0 0x021 0x0000000C 0xF1091800
+0x0D020200 0x00000006 0x0000C960 0x0000022F 0x00000000 0x00000100
+0x00000000 0x0048021C 0x0000021C 0x00770000 0x04370000 0x09230000
+0x00000924 0x00004960 0x00410304 0x00000570 0xC200C039 0x08200438
+0x0048021C 0x0000021C 0x04370000 0x09230000 0x00210011 0xC988BC71
+0x3D030007 0x250A2409 0x25092109 0x0000C018 0x00000000 0x0000080C
+0x00003E39
+
+// mipi: abyp 1
+0x29 0x01 0x00 0x01 0x00E0 0x008 0x0000000C 0xF1091C7C
+0x000002F7 0x000002F7 0x000002F7 0x000002F7 0x000002F7 0x00001200
+
+// mipi: man bypass ctrl dma
+0x29 0x01 0x00 0x01 0x00E2 0x003 0x0000000C 0xF109185C
+0xC988BC71
+
+// mipi: misc
+0x29 0x01 0x00 0x01 0x00E3 0x007 0xFFFFFFF4
+0xF1090600 0x00000001 0xF1090794 0x00000000 0xF10914C0 0x00000040
+
+// mipi: bitmask pb req
+0x29 0x01 0x00 0x01 0x00E4 0x003 0xFFFFFFF4
+0xF1100050 0x00000000
+
+// mipi: abyp sys dpg
+0x29 0x01 0x00 0x01 0x00E5 0x003 0x0000000C 0xF1091878
+0x00003E39
+
+// sys: a0: init 0
+0x29 0x01 0x64 0x00 0x00A0 0x013 0xFFFFFFF4
+0xF0000028 0x00000000 0xF0010040 0x00000008 0xF0000000 0x00000000
+0xF0000004 0x000A80B2 0xF0000008 0x0000F018 0xF000002C 0x00008420
+0xF0010040 0x0000000A 0xF0000028 0x000004D8 0xF0010040 0x00000008
+
+// sys: misc
+0x29 0x01 0x00 0x00 0x0000 0x013 0xFFFFFFF4
+0xF000003C 0x00000003 0xF0000040 0x0000004F 0xF0000050 0x000001FD
+0xF000005C 0x0000080C 0xF0000058 0x00000008 0xF0000080 0x0000004E
+0xF00000E0 0x10000001 0xF00000E4 0x0000C400 0xF0010004 0x0090A01A
+
+// sys: abyp: enter
+0x29 0x01 0x00 0x00 0x0004 0x005 0xFFFFFFF4
+0xF00000EC 0x00000002 0xF00000EC 0x00000000
+
+// sys: abyp: exit
+0x29 0x01 0x00 0x00 0x0105 0x005 0xFFFFFFF4
+0xF00000EC 0x00000001 0xF00000EC 0x00000000
+
+// sys: mpg off
+0x29 0x01 0x00 0x00 0x0006 0x003 0xFFFFFFF4
+0xF000003C 0x00000003
+
+// sys: dma ctrl
+0x29 0x01 0x00 0x00 0x0007 0x003 0xFFFFFFF4
+0xF000007C 0x00000100
+
+// sys: dpg event off
+0x29 0x01 0x00 0x00 0x0010 0x003 0xFFFFFFF4
+0xF0000038 0x00003E3F
+
+// sys: dpg event on
+0x29 0x01 0x00 0x00 0x0011 0x003 0xFFFFFFF4
+0xF0000038 0x00003F39
+
+// sys: dma0 one time trig
+0x29 0x01 0x00 0x00 0x0020 0x005 0xFFFFFFF4
+0xF000005C 0x0000082C 0xF000005C 0x0000080C
+
+// sys: bitmask dpg ctrl
+0x29 0x01 0x00 0x00 0x00F0 0x003 0xFFFFFFF4
+0xF0000038 0x00003E39
+
+// sys: bitmask mpg ctrl
+0x29 0x01 0x00 0x00 0x00F1 0x003 0xFFFFFFF4
+0xF000003C 0x00000007
+
+// sys: bitmask abp ctrl
+0x29 0x01 0x00 0x00 0x00F2 0x003 0xFFFFFFF4
+0xF0010004 0x0090A01A
+
+// sys: bitmask ulps ctrl
+0x29 0x01 0x00 0x00 0x00F3 0x003 0xFFFFFFF4
+0xF0000080 0x0000004E
+
+// sys: bitmask alt_ctrl0
+0x29 0x01 0x00 0x00 0x00F4 0x003 0xFFFFFFF4
+0xF00000E0 0x10200001
+
+// sys: bitmask pmu ctrl
+0x29 0x01 0x00 0x00 0x00F5 0x003 0xFFFFFFF4
+0xF0000040 0x0000004F
+
+// sys: bitmask dma trig gen ctrl
+0x29 0x01 0x00 0x00 0x00F6 0x003 0xFFFFFFF4
+0xF000005C 0x0000080C
+
+// sys: bitmask alt_ctrl1
+0x29 0x01 0x00 0x00 0x00F7 0x003 0xFFFFFFF4
+0xF00000E4 0x0000C400
+
+// dtg: ctrl
+0x29 0x01 0x00 0x05 0x0000 0x016 0x00000000 0xF10C0000
+0x00000008 0x00000008 0x00000438 0x0000001C 0x00000005 0x00000005
+0x00000924 0x0000001B 0x01010143 0x00001296 0x00000000 0x00000000
+0x00000008 0x000041CE 0x00002BE8 0x00298039 0x00000001 0x00000001
+0x00000001 0x00001F40
+
+// dtg: update
+0x29 0x01 0x00 0x05 0x00F0 0x003 0xFFFFFFF4
+0xF10D0000 0x00000001
+
+// mipi_tx: ctrl
+0x29 0x01 0x00 0x02 0x0000 0x019 0xFFFFFFF4
+0xF1400000 0xC200C039 0xF1400004 0x08200438 0xF1400008 0x0048021C
+0xF140000C 0x0000021C 0xF1400010 0x04370000 0xF1400014 0x09230000
+0xF1400018 0x00210011 0xF140001C 0xC988BC71 0xF1400040 0x3D030007
+0xF1400044 0x250A2409 0xF1400048 0x25092109 0xF140004C 0x0000C018
+
+// mipi_tx: dphy
+0x29 0x01 0x00 0x02 0x0001 0x007 0xFFFFFFF4
+0xF1440200 0x00004960 0xF1440004 0x00410304 0xF1440210 0x00000570
+
+// dport: init
+0x29 0x01 0x00 0x04 0x00F0 0x009 0x0000000C 0xF1090688
+0x00004007 0x49240438 0x21008801 0x46000800 0x06001805 0x082C0100
+0x00000000
+
+// dport: update
+0x29 0x01 0x00 0x04 0x0080 0x003 0x0000000C 0xF10906A0
+0x00000001
+
+// pwil: ctrl
+0x29 0x01 0x00 0x03 0x00F0 0x022 0x0000000C 0xF1090604
+0x02801104 0x00080008 0x00000040 0x09240438 0xE4100010 0x00000888
+0x00000000 0x09240438 0x09240438 0xE4100020 0x00000888 0x00000000
+0x07800438 0x07800438 0x00000000 0x021C021C 0x00900240 0x00000001
+0x0000001D 0x0951094E 0x7FFE094E 0x10E47E4C 0x7BBD0E56 0x00000000
+0x00000000 0x00000000 0x00000000 0x09BA3C00 0xFFFFFFFF 0x00000040
+0x09230000 0x04370000
+
+// pwil: update
+0x29 0x01 0x00 0x03 0x0080 0x003 0x0000000C 0xF1090684
+0x00000100
+
+// pwil: capen 0
+0x29 0x01 0x00 0x03 0x0050 0x003 0xFFFFFFF4
+0xF1140044 0x00000000
+
+// pwil: capen 1
+0x29 0x01 0x00 0x03 0x0051 0x003 0x0000000C 0xF10914C4
+0x00000001
+
+// pwil: capen 0 (dma)
+0x29 0x01 0x00 0x03 0x0052 0x003 0x0000000C 0xF10914C4
+0x00000000
+
+// pwil: bitmask: data path
+0x29 0x01 0x00 0x03 0x00FC 0x003 0x0000000C 0xF1090608
+0x00080008
+
+// pwil: bitmask: data path1
+0x29 0x01 0x00 0x03 0x00FD 0x003 0x0000000C 0xF109060C
+0x00000040
+
+// pwil: sw_clean_path
+0x29 0x01 0x00 0x03 0x00D0 0x004 0x0000000C 0xF1091C94
+0x02801904 0x02801104
+
+// dpp: init
+0x29 0x01 0x00 0x0E 0x00F0 0x042 0x0000000C 0xF10914C8
+0x00210043 0x00004055 0x00000240 0x00000010 0x00000000 0x00000000
+0x00000000 0x45104510 0x45104510 0x40004000 0x40004000 0x00040C00
+0x00400020 0xB29500A0 0x80808080 0x00000002 0x00000028 0x40004000
+0x00004000 0x00800040 0x0708021C 0x3FFFFFFF 0x00000000 0x00780050
+0x00780050 0x00008000 0x00400003 0x0760C00B 0x21F5B0DF 0x000FFEFB
+0x17F3FC7F 0x2FF9FDFF 0x000FFF7F 0x0154AC55 0x00000006 0x60402000
+0xDFBF9F80 0x000000FF 0x18040080 0x300A0200 0x00000011 0x08000000
+0x00000000 0x08000000 0x00000800 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x17F3FC7F 0x2FF9FDFF 0x000FFF7F 0x08000000
+0x00000000 0x08000000 0x00000800 0x00000000 0x08000000 0x00000000
+0x08000000 0x00000800 0x00000000 0x00000800
+
+// dpp: gamma LUT
+0x29 0x01 0x00 0x0E 0x00FE 0x002 0x0000000C 0xF10915C8
+
+
+// dpp: dither LUT
+0x29 0x01 0x00 0x0E 0x00F8 0x002 0x0000000C 0xF109187C
+
+
+// dpp: CLT_EN
+0x29 0x01 0x00 0x0E 0x0000 0x003 0x0000000C 0xF10914C8
+0x00210043
+
+// dpp: bitmask: path ctrl
+0x29 0x01 0x00 0x0E 0x0010 0x003 0x0000000C 0xF10914CC
+0x00004055
+
+// dpp: bitmask: gamma mode
+0x29 0x01 0x00 0x0E 0x0020 0x003 0x0000000C 0xF10914D0
+0x00000240
+
+// dpp: csc2 ctrl
+0x29 0x01 0x00 0x0E 0x0030 0x006 0x0000000C 0xF10914D4
+0x00000010 0x00000000 0x00000000 0x00000000
+
+// dpp: lut interp
+0x29 0x01 0x00 0x0E 0x0051 0x004 0x0000000C 0xF10914E4
+0x45104510 0x45104510
+
+// dpp: lut gain
+0x29 0x01 0x00 0x0E 0x0052 0x003 0x0000000C 0xF10914EC
+0x40004000
+
+// dpp: lut gain2
+0x29 0x01 0x00 0x0E 0x0053 0x004 0x0000000C 0xF10914F0
+0x40004000 0x00040C00
+
+// dpp: lut ctrl
+0x29 0x01 0x00 0x0E 0x0050 0x003 0x0000000C 0xF10914F8
+0x00400020
+
+// dpp: s curve 0
+0x29 0x01 0x00 0x0E 0x0070 0x005 0x0000000C 0xF10914FC
+0xB29500A0 0x80808080 0x00000002
+
+// dpp: FD
+0x29 0x01 0x00 0x0E 0x0060 0x003 0x0000000C 0xF1091508
+0x00000028
+
+// dpp: DIMM
+0x29 0x01 0x00 0x0E 0x0061 0x004 0x0000000C 0xF109150C
+0x40004000 0x00004000
+
+// dpp: FD shape
+0x29 0x01 0x00 0x0E 0x0062 0x005 0x0000000C 0xF1091514
+0x00800040 0x0708021C 0x3FFFFFFF
+
+// dpp: demo win
+0x29 0x01 0x00 0x0E 0x0063 0x005 0x0000000C 0xF1091520
+0x00000000 0x00780050 0x00780050
+
+// dpp: FADE
+0x29 0x01 0x00 0x0E 0x0054 0x003 0x0000000C 0xF109152C
+0x00008000
+
+// dpp: APL ctrl
+0x29 0x01 0x00 0x0E 0x0021 0x003 0x0000000C 0xF1091530
+0x00400003
+
+// dpp: APL ctrl 2
+0x29 0x01 0x00 0x0E 0x0022 0x00F 0x0000000C 0xF1091534
+0x0760C00B 0x21F5B0DF 0x000FFEFB 0x17F3FC7F 0x2FF9FDFF 0x000FFF7F
+0x0154AC55 0x00000006 0x60402000 0xDFBF9F80 0x000000FF 0x18040080
+0x300A0200
+
+// dpp: csc cm
+0x29 0x01 0x00 0x0E 0x0040 0x00B 0x0000000C 0xF1091568
+0x00000011 0x08000000 0x00000000 0x08000000 0x00000800 0x00000000
+0x00000000 0x00000000 0x00000000
+
+// dpp: csc2 crstk cctrl
+0x29 0x01 0x00 0x0E 0x0031 0x003 0x0000000C 0xF109158C
+0x00000000
+
+// dpp: csc2 apl
+0x29 0x01 0x00 0x0E 0x0023 0x005 0x0000000C 0xF1091590
+0x17F3FC7F 0x2FF9FDFF 0x000FFF7F
+
+// dpp: csc2 crstk coef
+0x29 0x01 0x00 0x0E 0x0032 0x00C 0x0000000C 0xF109159C
+0x08000000 0x00000000 0x08000000 0x00000800 0x00000000 0x08000000
+0x00000000 0x08000000 0x00000800 0x00000000
+
+// dpp: csc2 coef
+0x29 0x01 0x00 0x0E 0x0033 0x007 0x0000000C 0xF10917E8
+0x08000000 0x00000000 0x08000000 0x00000800 0x00000000
+
+// dpp: gc
+0x29 0x01 0x00 0x0E 0x00A0 0x003 0x0000000C 0xF10915C4
+0x00000800
+
+// dpp: s curve 0
+0x29 0x01 0x00 0x0E 0x0071 0x024 0x0000000C 0xF1091760
+0x00800800 0x00800800 0x00800800 0x00800800 0x00800800 0x00800800
+0x00800800 0x00800800 0x00800800 0x00800800 0x00800800 0x00800800
+0x00800800 0x00800800 0x00800800 0x00800800 0x00000800 0x00800800
+0x00800800 0x00800800 0x00800800 0x00800800 0x00800800 0x00800800
+0x00800800 0x00800800 0x00800800 0x00800800 0x00800800 0x00800800
+0x00800800 0x00800800 0x00800800 0x00000800
+
+// dpp: s curve 1
+0x29 0x01 0x00 0x0E 0x0072 0x024 0x0000000C 0xF1091760
+0x00FFF800 0x00FFFFFF 0x00FFFFFF 0x00FFFFFF 0x00FFFFFF 0x00FFFFFF
+0x00FFFFFF 0x00FFFFFF 0x00FFFFFF 0x00F11FD2 0x00DC5E63 0x00CAFD34
+0x00BC5C35 0x00AFBB5C 0x00A4CAA1 0x009B39FD 0x0000096D 0x008EC92B
+0x0087A8B1 0x00813845 0x007E37FF 0x007B17C9 0x0078979C 0x0076A778
+0x0075375E 0x0074674C 0x00742743 0x00747743 0x0075574C 0x0076D75F
+0x0079177D 0x007C17A7 0x008007DE 0x00000800
+
+// dpp: s curve 2
+0x29 0x01 0x00 0x0E 0x0073 0x024 0x0000000C 0xF1091760
+0x003E0800 0x0050B490 0x005BA568 0x006375FB 0x0069C66C 0x006F46CD
+0x0074271D 0x00784765 0x007C27A4 0x007FB7DE 0x00822810 0x00840831
+0x0085784C 0x00868860 0x00876870 0x0088187C 0x00000885 0x0088A888
+0x0088E88D 0x00890890 0x00890890 0x0088E88F 0x0088A88C 0x00885888
+0x0087F882 0x0087687B 0x0086D872 0x0085285F 0x0083C846 0x0082B833
+0x0081E824 0x00812818 0x0080080B 0x00000800
+
+// dpp: update
+0x29 0x01 0x00 0x0E 0x0080 0x003 0x0000000C 0xF10917FC
+0x00000001
+
+// dbc: init 0
+0x29 0x00 0x00 0x0F 0x00F0 0x003 0x0000000C 0xF1090798
+0x00000800
+
+// dbc: init 1
+0x29 0x01 0x00 0x0F 0x00F0 0x00D 0x0000000C 0xF109089C
+0x00000000 0x000003CB 0x000001C0 0x000003CB 0x000001C0 0x0000003F
+0x00000002 0x00000FFF 0x00000000 0x00000000 0x40850423
+
+// dbc: COREX0K0
+0x29 0x01 0x00 0x0F 0x00FE 0x002 0x0000000C 0xF109079C
+
+
+// dbc: off
+0x29 0x01 0x00 0x0F 0x0000 0x003 0x0000000C 0xF10908C4
+0x40850423
+
+// dbc: on
+0x29 0x01 0x00 0x0F 0x0001 0x003 0x0000000C 0xF10908C4
+0x40840423
+
+// dbc: level 0
+0x29 0x01 0x00 0x0F 0x0010 0x004 0x0000000C 0xF10908B0
+0x00000000 0x00000000
+
+// dbc: level 1
+0x29 0x01 0x00 0x0F 0x0011 0x004 0x0000000C 0xF10908B0
+0x00000027 0x00000002
+
+// dbc: level 2
+0x29 0x01 0x00 0x0F 0x0012 0x004 0x0000000C 0xF10908B0
+0x00000022 0x00000002
+
+// dbc: level 3
+0x29 0x01 0x00 0x0F 0x0013 0x004 0x0000000C 0xF10908B0
+0x0000001B 0x00000002
+
+// dbc: compenk table 0
+0x29 0x01 0x00 0x0F 0x0020 0x003 0x0000000C 0xF10908BC
+0x00000000
+
+// dbc: compenk table 1
+0x29 0x01 0x00 0x0F 0x0021 0x003 0x0000000C 0xF10908BC
+0x00000001
+
+// dbc: income table 0
+0x29 0x01 0x00 0x0F 0x0030 0x003 0x0000000C 0xF10908C0
+0x00000000
+
+// dbc: income table 1
+0x29 0x01 0x00 0x0F 0x0031 0x003 0x0000000C 0xF10908C0
+0x00000001
+
+// dbc: bitmask: bl_user
+0x29 0x01 0x00 0x0F 0x00FD 0x003 0x0000000C 0xF10908B8
+0x00000FFF
+
+// dbc: bitmask: led0d_gain
+0x29 0x01 0x00 0x0F 0x00FC 0x003 0x0000000C 0xF10908B0
+0x00000000
+
+// blc_pwm: init
+0x29 0x01 0x00 0x06 0x00F0 0x003 0xFFFFFFF4
+0xF1040014 0x0001100A
+
+// blc_pwm: disable
+0x29 0x01 0x00 0x06 0x0000 0x003 0xFFFFFFF4
+0xF1040000 0x00000481
+
+// blc_pwm: enable
+0x29 0x01 0x00 0x06 0x0001 0x003 0xFFFFFFF4
+0xF1040000 0x00000484
+
+// blc_pwm: bitmask: PWM_GEN_FREQ_SET
+0x29 0x01 0x00 0x06 0x00FD 0x003 0xFFFFFFF4
+0xF1040010 0x00000001
+
+// dsc_dec: sw_rst_en
+0x29 0x01 0x00 0x07 0x00D0 0x004 0x0000000C 0xF1091C9C
+0x00490358 0x00480358
+
+// dsc_dec: init
+0x29 0x01 0x00 0x07 0x00F0 0x01C 0x0000000C 0xF10906A4
+0x00480358 0x01E001E0 0x00000800 0x89000011 0x24098030 0x48003804
+0x1C021C02 0x2A040002 0xFD062000 0x0C000700 0x6A015B01 0xF0100018
+0x00200C03 0x330B0B06 0x382A1C0E 0x69625446 0x7B797770 0x02017E7D
+0x40090001 0xFC19BE09 0xF819FA19 0x781A381A 0xF62AB61A 0x742B342B
+0xF463743B 0x00000001
+
+// dsc_enc: init
+0x29 0x01 0x00 0x08 0x00F0 0x024 0x0000000C 0xF109070C
+0x00000003 0x00000002 0x00B40168 0x0002021C 0x00B4010E 0x000097E0
+0x00009900 0x00004BF0 0xC0122010 0x00B4021C 0x00000000 0x89000011
+0x24098030 0x48003804 0x1C021C02 0x0E020002 0xFD062000 0x0C000700
+0x6A015B01 0xF0100018 0x00200C03 0x330B0B06 0x382A1C0E 0x69625446
+0x7B797770 0x02017E7D 0x40090001 0xFC19BE09 0xF819FA19 0x781A381A
+0xF62AB61A 0x742B342B 0xF463743B 0x00000004
+
+// scaler_pp: init
+0x29 0x01 0x00 0x0B 0x00F0 0x014 0x0000000C 0xF1090928
+0x00026620 0x00000441 0x00080000 0x00080000 0x00006410 0x09240924
+0x00020003 0x00020003 0x00000000 0x0000001E 0x04380438 0x00080000
+0x00080000 0x00020003 0x00020003 0x00006410 0x00000000 0x00000800
+
+// dma: init
+0x29 0x01 0x00 0x11 0x00F0 0x09A 0x0000000C 0xF1090000
+0x10010600 0xF1100050 0x801B0604 0xF1140000 0x80030670 0xF1140108
+0x8002067C 0xF1141004 0x80010684 0xF1150000 0x80060688 0xF1380000
+0x800106A0 0xF1390000 0x001906A4 0xF1180000 0x00010708 0xF119FF00
+0x000A070C 0xF13C0000 0x00010734 0xF13C0054 0x00160738 0xF13C0064
+0x00010790 0xF13C0114 0x00010794 0xF1100050 0x84010798 0xF1300000
+0x8440079C 0xF1300088 0x840B089C 0xF13001E4 0xC41808C8 0xF1318000
+0x04120928 0xF1240000 0xC5620970 0xF11D1104 0x856D0EF8 0xF11C0000
+0x840214AC 0xF11D1000 0x840114B4 0xF11C0348 0x840214B8 0xF11D10FC
+0x040114C0 0xF1140008 0x800114C4 0xF1140044 0x884014C8 0xF1480000
+0x888D15C8 0xF1480200 0x880117FC 0xF1480434 0x88011800 0xF1100808
+0x88011804 0xF1100818 0x88011808 0xF1100A00 0x8801180C 0xF1100010
+0x88011810 0xF110001C 0x88011814 0xF1100080 0x88011818 0xF1100104
+0x8802181C 0xF1100144 0x88011824 0xF1100238 0x88021828 0xF1100300
+0x88011830 0xF1101804 0x88011834 0xF1440200 0x88011838 0xF1440004
+0x8801183C 0xF1440210 0x88081840 0xF1400000 0x88041860 0xF1400040
+0x8C011870 0xF10914B4 0x08011874 0xF000005C 0x88011878 0xF0000038
+0x8900187C 0xF1607C00 0x88011C7C 0xF1100A08 0x88011C80 0xF1100A14
+0x88011C84 0xF1100A1C 0x88011C88 0xF1100A24 0x88011C8C 0xF1100A2C
+0x88011C90 0xF1100800 0x90011C94 0xF1140000 0x90011C98 0xF1140000
+0x10011C9C 0xF1180000 0x10011CA0 0xF1180000 0xAC1B0604 0xF1140000
+0xAC030670 0xF1140108 0xAC02067C 0xF1141004 0xAC010684 0xF1150000
+0xA04014C8 0xF1480000 0xA08D15C8 0xF1480200 0xA00117FC 0xF1480434
+0xA56D0EF8 0xF11C0000 0xA40214AC 0xF11D1000 0xA40114B4 0xF11C0348
+0xA40214B8 0xF11D10FC 0xA8010798 0xF1300000 0xA840079C 0xF1300088
+0xA80B089C 0xF13001E4 0xB0060688 0xF1380000 0xB00106A0 0xF1390000
+0xAC0114C4 0xF1140044
+
+// dma: init ctrl
+0x29 0x01 0x00 0x11 0x00E1 0x013 0xFFFFFFF4
+0xF1080000 0x0000000D 0xF1080004 0x00000000 0xF1080008 0x004C0000
+0xF1080014 0xFFFFFFFF 0xF1080104 0x00000004 0xF1080108 0x00000002
+0xF108010C 0x00000002 0xF1080110 0x00000001 0xF1080114 0x00000001
+
+// dma: trigger HDR
+0x29 0x01 0x00 0x11 0x00E2 0x005 0xFFFFFFF4
+0xF1080004 0x00000000 0xF1080004 0x00000A00
+
+// dma: trigger DPP
+0x29 0x01 0x00 0x11 0x00E3 0x005 0xFFFFFFF4
+0xF1080004 0x00000000 0xF1080004 0x00000100
+
+// dma: trigger PQ
+0x29 0x01 0x00 0x11 0x00E4 0x005 0xFFFFFFF4
+0xF1080004 0x00000000 0xF1080004 0x00000800
+
+// dma: trigger DBC
+0x29 0x01 0x00 0x11 0x00E5 0x005 0xFFFFFFF4
+0xF1080004 0x00000000 0xF1080004 0x00000C00
+
+// dma: PD08 power protection
+0x29 0x01 0x00 0x11 0x00E6 0x003 0xFFFFFFF4
+0xF1080104 0x00000004
+
+// dma: trigger DPORT
+0x29 0x01 0x00 0x11 0x00E7 0x005 0xFFFFFFF4
+0xF1080004 0x00000000 0xF1080004 0x00001000
+
+// dma: PD11 power protection
+0x29 0x01 0x00 0x11 0x00E8 0x003 0xFFFFFFF4
+0xF1080110 0x00000001
+
+// hdr: top_ctrl
+0x29 0x01 0x00 0x09 0x0000 0x00E 0x0000000C 0xF1090EF8
+0x00107AB5 0x00065905 0x00000D3F 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl
+0x29 0x01 0x00 0x09 0x0010 0x038 0x0000000C 0xF1090F28
+0x00003001 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x0287D1F4 0x0467D17C 0x0197D12C
+0x00960000 0x0C800961 0x000013CA 0x00020014 0x000003FF 0x000003FF
+0x02320F7D 0x023C0000 0x00FFF000 0x00002002 0x0000040C 0x0200007F
+0x00040810 0x00FDF309 0x0000009E 0x00033D91 0x0000A8B0 0x00100000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl
+0x29 0x01 0x00 0x09 0x0020 0x007 0x0000000C 0xF1091000
+0x05001FFF 0x1F100700 0x00080001 0x00011133 0x07AA0800
+
+// hdr: tl_ctrl
+0x29 0x01 0x00 0x09 0x0030 0x04A 0x0000000C 0xF1091014
+0x1E77C1FA 0x1CC755DE 0x1B06E9C3 0x195679A7 0x17B60D8C 0x1605A572
+0x14653D57 0x12D4D53E 0x11447124 0x0FC4110C 0x0E43B0F4 0x0CE354DD
+0x0B82FCC6 0x0A32A8B1 0x0902589D 0x07D20C89 0x06C1C477 0x05B18066
+0x04C14456 0x03E10C47 0x0320D83A 0x0260A82E 0x01D08023 0x01405C1A
+0x00D03C12 0x0070240B 0x00301406 0x00100402 0x00000000 0x00000000
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000400
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x5A2DB058
+
+// hdr: tm_ctrl
+0x29 0x01 0x00 0x09 0x0040 0x035 0x0000000C 0xF1091134
+0x01290000 0x040D0309 0x06670568 0x07EC07EC 0x07EC07EC 0x07EC07EC
+0x07EC07EC 0x000007EC 0x01290000 0x040D0309 0x06670568 0x07EC07EC
+0x07EC07EC 0x07EC07EC 0x07EC07EC 0x000007EC 0x012C03E8 0x00640064
+0x00280032 0x00280028 0x00280028 0x00280028 0x00280028 0x0A0A0A02
+0x10100002 0x10101010 0x00001010 0x0FFF0FFF 0x005F0005 0x07EC1A02
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x04000100 0x00000202 0x00000883
+0x00000080 0x0000021C 0x0100021C
+
+// hdr: tm_sw_cfg
+0x29 0x01 0x00 0x09 0x0050 0x013 0x0000000C 0xF1091200
+0x01290000 0x040D0309 0x06670568 0x07EC07EC 0x07EC07EC 0x07EC07EC
+0x07EC07EC 0x000007EC 0x01290000 0x040D0309 0x06670568 0x07EC07EC
+0x07EC07EC 0x07EC07EC 0x07EC07EC 0x000007EC 0x00000000
+
+// hdr: ratio_ctrl
+0x29 0x01 0x00 0x09 0x0060 0x005 0x0000000C 0xF1091244
+0x00001000 0x00001000 0x00000100
+
+// hdr: col_ctrl
+0x29 0x01 0x00 0x09 0x0070 0x00A 0x0000000C 0xF1091250
+0x0000194D 0x00140678 0x00140763 0x00000CCC 0x00000CCC 0x00808080
+0x00080000 0x00080000
+
+// hdr: csc_ctrl
+0x29 0x01 0x00 0x09 0x0090 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E3C
+0x00000D9B 0x00002DC6 0x0000049F 0x0000F8AB 0x0000E755 0x00002000
+0x00002000 0x0000E2EF 0x0000FD11 0x00000000 0x00000000 0x00000000
+0x0001A649 0x00016E2A 0x0000B8CF 0x0000D9BE 0x0002DC55 0x000049EC
+0x000013CB 0x00007A0E 0x0003CD58 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x00000000 0x000064C9
+0x00004000 0x0000F403 0x0000E20A 0x00004000 0x000076C2 0x00000000
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl
+0x29 0x01 0x00 0x09 0x00A0 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl
+0x29 0x01 0x00 0x09 0x00B0 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000400 0x00140118 0x00000190 0x00200080
+0x0000012C 0x00008000 0x000003E8
+
+// hdr: de_ctrl
+0x29 0x01 0x00 0x09 0x00C0 0x020 0x0000000C 0xF10913D8
+0x000C0000 0x00645040 0x00008080 0x0000012A 0x0000018D 0x00000309
+0x00000667 0x000007EC 0x00204080 0x00000010 0x0000001A 0x00000062
+0x0000012A 0x0000018D 0x00000246 0x00050118 0x00801201 0x01690C0C
+0x001021C0 0x00000000 0x0FFF2800 0x00004002 0x0AF40FFF 0x1079512A
+0x1003E81E 0x08012C50 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+// hdr: ai_ctrl
+0x29 0x01 0x00 0x0A 0x0000 0x016 0x0000000C 0xF1091450
+0x001C4002 0x0000000F 0x00011000 0x0005007D 0x04040404 0x00040404
+0x000115B8 0x000115C8 0x000115D8 0x000115E8 0x000115F8 0x000115F8
+0x000115F8 0x00000380 0x00040040 0x00000100 0x000003FF 0x00000000
+0x00000000 0x88000007
+
+// hdr: demo_ctrl
+0x29 0x01 0x00 0x09 0x00D0 0x005 0x0000000C 0xF10914A0
+0x00000000 0x00000000 0x00000000
+
+// hdr: ai_ctrl 2
+0x29 0x01 0x00 0x0A 0x0010 0x004 0x0000000C 0xF10914AC
+0x0000007D 0x000000FA
+
+// hdr: update
+0x29 0x01 0x00 0x09 0x0080 0x004 0x0000000C 0xF10914B8
+0x00000000 0x00000004
+
+// hdr: tm_trig
+0x29 0x01 0x00 0x09 0x00FB 0x003 0x0000000C 0xF10914B4
+0x00000000
+
+// hdr: ctrl
+0x29 0x01 0x00 0x09 0x00FD 0x003 0x0000000C 0xF1090F00
+0x00000D3F
+
+// hdr: path_ctrl
+0x29 0x01 0x00 0x09 0x00FC 0x003 0x0000000C 0xF1090EFC
+0x00065905
+
+// hdr: top_ctrl l2
+0x29 0x01 0x00 0x09 0x0002 0x00E 0x0000000C 0xF1090EF8
+0x0010B00B 0x00021358 0x000014F0 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl l2
+0x29 0x01 0x00 0x09 0x0012 0x038 0x0000000C 0xF1090F28
+0x00003001 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x0287D1F4 0x0467D17C 0x0197D12C
+0x00960000 0x0C8008C9 0x00000BD7 0x00020014 0x00000002 0x000003FF
+0x02640AD2 0x020A0000 0x00AF4000 0x00002EBE 0x0000040C 0x000A0057
+0x0005E293 0x00AEC4CB 0x0000006B 0x0004C8F8 0x00006AD2 0x00400000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl l2
+0x29 0x01 0x00 0x09 0x0022 0x007 0x0000000C 0xF1091000
+0x05014FFF 0x28140802 0x00080190 0x00042233 0x07AA0FA0
+
+// hdr: tl_ctrl l2
+0x29 0x01 0x00 0x09 0x0032 0x04A 0x0000000C 0xF1091014
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x18C6C1D5 0x12451969 0x0C639104 0x077240AA 0x03A13060 0x0120742A
+0x00000C09 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000400
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x2E175A2D
+
+// hdr: tm_ctrl l2
+0x29 0x01 0x00 0x09 0x0042 0x035 0x0000000C 0xF1091134
+0x07F50000 0x09A30916 0x0A7009F2 0x0B230AD2 0x0BBE0B67 0x0C7B0C06
+0x0D660CF3 0x00000FFF 0x05720000 0x06990638 0x072506CF 0x07A00768
+0x080A07CE 0x088B083B 0x092C08DD 0x00000AF4 0x0014000A 0x00C80032
+0x03E800C8 0x02580320 0x00C800C8 0x00140064 0x00140014 0x02010101
+0x06040303 0x02020202 0x00000202 0x0AF40FFF 0x00FA0001 0x08201A03
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x001400AF 0x00000004 0x00000D66
+0x00000080 0x00002710 0x00AF021C
+
+// hdr: ratio_ctrl l2
+0x29 0x01 0x00 0x09 0x0062 0x005 0x0000000C 0xF1091244
+0x00001000 0x000035FC 0x00001285
+
+// hdr: col_ctrl l2
+0x29 0x01 0x00 0x09 0x0072 0x00A 0x0000000C 0xF1091250
+0x0000197D 0x0014060F 0x001406EF 0x00000CCC 0x00000CCC 0x00808080
+0x00080000 0x00080000
+
+// hdr: csc_ctrl l2
+0x29 0x01 0x00 0x09 0x0092 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E38
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00000000 0x00000000 0x00000000
+0x00028C3E 0x00009416 0x0000ACEF 0x00010D01 0x0002B645 0x00003CB9
+0x00000000 0x00001CBF 0x00043E72 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x0000008D 0x0000071B
+0x00004000 0x0000FF73 0x0000F8E5 0x00004000 0x000023D7 0x0000EB7B
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl l2
+0x29 0x01 0x00 0x09 0x00A2 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl l2
+0x29 0x01 0x00 0x09 0x00B2 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000040 0x00100100 0x00000190 0x00200080
+0x0000012C 0x00008000 0x000003E8
+
+// hdr: de_ctrl l2
+0x29 0x01 0x00 0x09 0x00C2 0x020 0x0000000C 0xF10913D8
+0x00040000 0x00645040 0x00008080 0x00000266 0x00000303 0x000004CB
+0x00000752 0x00000821 0x00408080 0x00000020 0x0000002F 0x000000DB
+0x00000266 0x00000303 0x000003F7 0x00050168 0x00801201 0x016B0C0C
+0x001021C0 0x000000FF 0x0AF42800 0x00004002 0x0AF40AF4 0x10D3C266
+0x1003E81E 0x08012C50 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+// hdr: tm_sw_cfg l2
+0x29 0x01 0x00 0x09 0x0052 0x013 0x0000000C 0xF1091200
+0x07F50000 0x09A30916 0x0A7009F2 0x0B230AD2 0x0BBE0B67 0x0C7B0C06
+0x0D660CF3 0x00000FFF 0x05720000 0x06990638 0x072506CF 0x07A00768
+0x080A07CE 0x088B083B 0x092C08DD 0x00000AF4 0x00000000
+
+// hdr: top_ctrl l3
+0x29 0x01 0x00 0x09 0x0003 0x00E 0x0000000C 0xF1090EF8
+0x0010B00B 0x00021350 0x000014F0 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl l3
+0x29 0x01 0x00 0x09 0x0013 0x038 0x0000000C 0xF1090F28
+0x00003001 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x0287D1F4 0x0467D17C 0x0197D12C
+0x00960000 0x0C8008C9 0x00000BD7 0x00020014 0x00000002 0x000003FF
+0x02640AD2 0x020A0000 0x00AF4000 0x00002EBE 0x0000040C 0x000A0057
+0x0005E293 0x00AEC4CB 0x0000006B 0x0004C8F8 0x00006AD2 0x00400000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl l3
+0x29 0x01 0x00 0x09 0x0023 0x007 0x0000000C 0xF1091000
+0x05014FFF 0x28140802 0x00080190 0x00042233 0x07AA0FA0
+
+// hdr: tl_ctrl l3
+0x29 0x01 0x00 0x09 0x0033 0x04A 0x0000000C 0xF1091014
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x18C6C1D5 0x12451969 0x0C639104 0x077240AA 0x03A13060 0x0120742A
+0x00000C09 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000400
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x2E175A2D
+
+// hdr: tm_ctrl l3
+0x29 0x01 0x00 0x09 0x0043 0x035 0x0000000C 0xF1091134
+0x02660000 0x06B404CB 0x0820078F 0x09F20943 0x0B670AD2 0x0FFF0C06
+0x0FFF0FFF 0x00000FFF 0x01A40000 0x04970348 0x0590052C 0x06CF0657
+0x07CE0768 0x0AF4083B 0x0AF40AF4 0x00000AF4 0x0014000A 0x00C80032
+0x03E800C8 0x02580320 0x00C800C8 0x00140064 0x00140014 0x02010101
+0x06040303 0x02020202 0x00000202 0x0AF40FFF 0x00FA0001 0x08201A03
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x001400AF 0x00000006 0x00000D66
+0x00000080 0x00002710 0x00AF021C
+
+// hdr: ratio_ctrl l3
+0x29 0x01 0x00 0x09 0x0063 0x005 0x0000000C 0xF1091244
+0x00001000 0x000035FC 0x00001285
+
+// hdr: col_ctrl l3
+0x29 0x01 0x00 0x09 0x0073 0x00A 0x0000000C 0xF1091250
+0x0000197D 0x0014060F 0x001406EF 0x00000CCC 0x00000CCC 0x00808080
+0x00080000 0x00080000
+
+// hdr: csc_ctrl l3
+0x29 0x01 0x00 0x09 0x0093 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E38
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00000000 0x00000000 0x00000000
+0x00028C3E 0x00009416 0x0000ACEF 0x00010D01 0x0002B645 0x00003CB9
+0x00000000 0x00001CBF 0x00043E72 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x0000008D 0x0000071B
+0x00004000 0x0000FF73 0x0000F8E5 0x00004000 0x000023D7 0x0000EB7B
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl l3
+0x29 0x01 0x00 0x09 0x00A3 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl l3
+0x29 0x01 0x00 0x09 0x00B3 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000040 0x00100100 0x00000190 0x00200080
+0x0000012C 0x00008000 0x000003E8
+
+// hdr: de_ctrl l3
+0x29 0x01 0x00 0x09 0x00C3 0x020 0x0000000C 0xF10913D8
+0x00040000 0x00645040 0x00008080 0x00000266 0x00000303 0x000004CB
+0x00000752 0x00000821 0x00408080 0x00000020 0x0000002F 0x000000DB
+0x00000266 0x00000303 0x000003F7 0x00050168 0x00801201 0x016B0C0C
+0x001021C0 0x000000FF 0x0AF42800 0x00004002 0x0AF40AF4 0x11B9A12A
+0x100D3065 0x08012C50 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+// hdr: top_ctrl l5
+0x29 0x01 0x00 0x09 0x0005 0x00E 0x0000000C 0xF1090EF8
+0x00107AB5 0x00064194 0x00000D7F 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl l5
+0x29 0x01 0x00 0x09 0x0015 0x038 0x0000000C 0xF1090F28
+0x00003011 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x0287D1F4 0x0647D17C 0x0407D12C
+0x0096000A 0x032007EC 0x00000F7D 0x00020032 0x00000002 0x000001F4
+0x025A07EC 0x02140ED3 0x00FFF000 0x00002002 0x0000040C 0x000A007F
+0x00040810 0x00FBF40D 0x0000009E 0x00033D91 0x00007E65 0x00080000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl l5
+0x29 0x01 0x00 0x09 0x0025 0x007 0x0000000C 0xF1091000
+0x050140C8 0x28140802 0x00080190 0x00042233 0x07AA0FA0
+
+// hdr: tl_ctrl l5
+0x29 0x01 0x00 0x09 0x0035 0x04A 0x0000000C 0xF1091014
+0x1E77C1FA 0x1CC755DE 0x1B06E9C3 0x195679A7 0x17B60D8C 0x1605A572
+0x14653D57 0x12D4D53E 0x11447124 0x0FC4110C 0x0E43B0F4 0x0CE354DD
+0x0B82FCC6 0x0A32A8B1 0x0902589D 0x07D20C89 0x06C1C477 0x05B18066
+0x04C14456 0x03E10C47 0x0320D83A 0x0260A82E 0x01D08023 0x01405C1A
+0x00D03C12 0x0070240B 0x00301406 0x00100402 0x00000000 0x00000000
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000400
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x5A2DB058
+
+// hdr: tm_ctrl l5
+0x29 0x01 0x00 0x09 0x0045 0x035 0x0000000C 0xF1091134
+0x01290000 0x0246018D 0x03980309 0x04CC040D 0x06670568 0x07EC0738
+0x07EC07EC 0x000007EC 0x01290000 0x0246018D 0x03980309 0x04CC040D
+0x06670568 0x07EC0738 0x07EC07EC 0x000007EC 0x032003E8 0x0032012C
+0x00280028 0x00280028 0x00280028 0x00280028 0x00280028 0x040A0A02
+0x10101000 0x10101010 0x00001010 0x0FFF0FFF 0x0080000C 0x07EC1A02
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00140100 0x00000002 0x00000883
+0x00000080 0x0000021C 0x0100021C
+
+// hdr: ratio_ctrl l5
+0x29 0x01 0x00 0x09 0x0065 0x005 0x0000000C 0xF1091244
+0x00001000 0x00001000 0x00000100
+
+// hdr: col_ctrl l5
+0x29 0x01 0x00 0x09 0x0075 0x00A 0x0000000C 0xF1091250
+0x0000194D 0x00140678 0x00140763 0x00000CCC 0x00000CCC 0x00808080
+0x00080000 0x00080000
+
+// hdr: csc_ctrl l5
+0x29 0x01 0x00 0x09 0x0095 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E3C
+0x00000D9B 0x00002DC6 0x0000049F 0x0000F8AB 0x0000E755 0x00002000
+0x00002000 0x0000E2EF 0x0000FD11 0x00000000 0x00000000 0x00000000
+0x0001A649 0x00016E2A 0x0000B8CF 0x0000D9BE 0x0002DC55 0x000049EC
+0x000013CB 0x00007A0E 0x0003CD58 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x00000000 0x000064C9
+0x00004000 0x0000F403 0x0000E20A 0x00004000 0x000076C2 0x00000000
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl l5
+0x29 0x01 0x00 0x09 0x00A5 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl l5
+0x29 0x01 0x00 0x09 0x00B5 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000040 0x0012C10E 0x000003E8 0x00200080
+0x0000012C 0x00008000 0x00000000
+
+// hdr: de_ctrl l5
+0x29 0x01 0x00 0x09 0x00C5 0x020 0x0000000C 0xF10913D8
+0x00040000 0x00805040 0x00008080 0x0000012A 0x000001D6 0x00000309
+0x000007EC 0x00000FFF 0x00204080 0x00000010 0x00000062 0x000000DF
+0x0000012A 0x0000018D 0x00000246 0x00064168 0x00801201 0x02E70C0C
+0x001021C0 0x000000FF 0x0FFF4000 0x00004002 0x0FFF0FFF 0x20F7E12A
+0x100FFC1E 0x08011850 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+// hdr: top_ctrl l6
+0x29 0x01 0x00 0x09 0x0006 0x00E 0x0000000C 0xF1090EF8
+0x00107AB5 0x00064194 0x00000D7F 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl l6
+0x29 0x01 0x00 0x09 0x0016 0x038 0x0000000C 0xF1090F28
+0x00003011 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x0287D1F4 0x0647D17C 0x0407D12C
+0x0096000A 0x032007EC 0x00000F7D 0x00020032 0x00000002 0x000001F4
+0x025A07EC 0x02140ED3 0x00FFF000 0x00002002 0x0000040C 0x000A007F
+0x00040810 0x00FBF40D 0x0000009E 0x00033D91 0x00007E65 0x00080000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl l6
+0x29 0x01 0x00 0x09 0x0026 0x007 0x0000000C 0xF1091000
+0x050140C8 0x28140802 0x00080190 0x00042233 0x07AA0FA0
+
+// hdr: tl_ctrl l6
+0x29 0x01 0x00 0x09 0x0036 0x04A 0x0000000C 0xF1091014
+0x1E77C1FA 0x1CC755DE 0x1B06E9C3 0x195679A7 0x17B60D8C 0x1605A572
+0x14653D57 0x12D4D53E 0x11447124 0x0FC4110C 0x0E43B0F4 0x0CE354DD
+0x0B82FCC6 0x0A32A8B1 0x0902589D 0x07D20C89 0x06C1C477 0x05B18066
+0x04C14456 0x03E10C47 0x0320D83A 0x0260A82E 0x01D08023 0x01405C1A
+0x00D03C12 0x0070240B 0x00301406 0x00100402 0x00000000 0x00000000
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000400
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x5A2DB058
+
+// hdr: tm_ctrl l6
+0x29 0x01 0x00 0x09 0x0046 0x035 0x0000000C 0xF1091134
+0x01290000 0x0246018D 0x03980309 0x04CC040D 0x06670568 0x07EC0738
+0x07EC07EC 0x000007EC 0x01290000 0x0246018D 0x03980309 0x04CC040D
+0x06670568 0x07EC0738 0x07EC07EC 0x000007EC 0x032003E8 0x0032012C
+0x00280028 0x00280028 0x00280028 0x00280028 0x00280028 0x040A0A02
+0x10101000 0x10101010 0x00001010 0x0FFF0FFF 0x0080000C 0x07EC1A02
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00140100 0x00000002 0x00000883
+0x00000080 0x0000021C 0x0100021C
+
+// hdr: ratio_ctrl l6
+0x29 0x01 0x00 0x09 0x0066 0x005 0x0000000C 0xF1091244
+0x00001000 0x00001000 0x00000100
+
+// hdr: col_ctrl l6
+0x29 0x01 0x00 0x09 0x0076 0x00A 0x0000000C 0xF1091250
+0x0000194D 0x00140678 0x00140763 0x00000CCC 0x00000CCC 0x00808080
+0x00080000 0x00080000
+
+// hdr: csc_ctrl l6
+0x29 0x01 0x00 0x09 0x0096 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E3C
+0x00000D9B 0x00002DC6 0x0000049F 0x0000F8AB 0x0000E755 0x00002000
+0x00002000 0x0000E2EF 0x0000FD11 0x00000000 0x00000000 0x00000000
+0x0001A649 0x00016E2A 0x0000B8CF 0x0000D9BE 0x0002DC55 0x000049EC
+0x000013CB 0x00007A0E 0x0003CD58 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x00000000 0x000064C9
+0x00004000 0x0000F403 0x0000E20A 0x00004000 0x000076C2 0x00000000
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl l6
+0x29 0x01 0x00 0x09 0x00A6 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl l6
+0x29 0x01 0x00 0x09 0x00B6 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000040 0x0012C10E 0x000003E8 0x00200080
+0x0000012C 0x00008000 0x00000000
+
+// hdr: de_ctrl l6
+0x29 0x01 0x00 0x09 0x00C6 0x020 0x0000000C 0xF10913D8
+0x00040000 0x00805040 0x00008080 0x0000012A 0x000001D6 0x00000309
+0x000007EC 0x00000FFF 0x00204080 0x00000010 0x00000062 0x000000DF
+0x0000012A 0x0000018D 0x00000246 0x00064168 0x00801201 0x02E70C0C
+0x001021C0 0x000000FF 0x0FFF4000 0x00004002 0x0FFF0FFF 0x20F7E12A
+0x100FFC1E 0x08011850 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+// hdr: top_ctrl l10
+0x29 0x01 0x00 0x09 0x000A 0x00E 0x0000000C 0xF1090EF8
+0x00107AB5 0x00064194 0x00000D7F 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl l10
+0x29 0x01 0x00 0x09 0x001A 0x038 0x0000000C 0xF1090F28
+0x00003011 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x014C0100 0x0647095E 0x03CC0190
+0x50501E32 0x01E007EC 0x01E00F7D 0x00020032 0x00000032 0x00000190
+0x025A07EC 0x023C0ED3 0x00FFF000 0x00002002 0x0000040C 0x000A007F
+0x00040810 0x00FBF40D 0x0000009E 0x00033D91 0x00007E65 0x00080000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl l10
+0x29 0x01 0x00 0x09 0x002A 0x007 0x0000000C 0xF1091000
+0x050140C8 0x28140802 0x00080190 0x00042233 0x07AA0FA0
+
+// hdr: tl_ctrl l10
+0x29 0x01 0x00 0x09 0x003A 0x04A 0x0000000C 0xF1091014
+0x1E77C1FA 0x1CC755DE 0x1B06E9C3 0x195679A7 0x17B60D8C 0x1605A572
+0x14653D57 0x12D4D53E 0x11447124 0x0FC4110C 0x0E43B0F4 0x0CE354DD
+0x0B82FCC6 0x0A32A8B1 0x0902589D 0x07D20C89 0x06C1C477 0x05B18066
+0x04C14456 0x03E10C47 0x0320D83A 0x0260A82E 0x01D08023 0x01405C1A
+0x00D03C12 0x0070240B 0x00301406 0x00100402 0x00000000 0x00000000
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000400
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x5A2DB058
+
+// hdr: tm_ctrl l10
+0x29 0x01 0x00 0x09 0x004A 0x035 0x0000000C 0xF1091134
+0x01290000 0x0246018D 0x03980309 0x04CC040D 0x06670568 0x07EC0738
+0x07EC07EC 0x000007EC 0x01290000 0x0246018D 0x03980309 0x04CC040D
+0x06670568 0x07EC0738 0x07EC07EC 0x000007EC 0x032003E8 0x0032012C
+0x00280028 0x00280028 0x00280028 0x00280028 0x00280028 0x040A0A02
+0x10101000 0x10101010 0x00001010 0x0FFF0FFF 0x0080000C 0x07EC1A02
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00140100 0x00000002 0x00000883
+0x00000080 0x0000021C 0x0100021C
+
+// hdr: ratio_ctrl l10
+0x29 0x01 0x00 0x09 0x006A 0x005 0x0000000C 0xF1091244
+0x00001000 0x00001000 0x00000100
+
+// hdr: col_ctrl l10
+0x29 0x01 0x00 0x09 0x007A 0x00A 0x0000000C 0xF1091250
+0x0000194D 0x00140678 0x00140763 0x00000CCC 0x00000CCC 0x0080803C
+0x00080000 0x00080000
+
+// hdr: csc_ctrl l10
+0x29 0x01 0x00 0x09 0x009A 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E3C
+0x00000D9B 0x00002DC6 0x0000049F 0x0000F8AB 0x0000E755 0x00002000
+0x00002000 0x0000E2EF 0x0000FD11 0x00000000 0x00000000 0x00000000
+0x0001A649 0x00016E2A 0x0000B8CF 0x0000D9BE 0x0002DC55 0x000049EC
+0x000013CB 0x00007A0E 0x0003CD58 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x00000000 0x000064C9
+0x00004000 0x0000F403 0x0000E20A 0x00004000 0x000076C2 0x00000000
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl l10
+0x29 0x01 0x00 0x09 0x00AA 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl l10
+0x29 0x01 0x00 0x09 0x00BA 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000040 0x0010E118 0x00000190 0x00200080
+0x0000012C 0x00008000 0x00000000
+
+// hdr: de_ctrl l10
+0x29 0x01 0x00 0x09 0x00CA 0x020 0x0000000C 0xF10913D8
+0x00040000 0x00804020 0x00008080 0x0000012A 0x000001D6 0x00000309
+0x000007EC 0x00000FFF 0x00204080 0x00000010 0x00000062 0x000000DF
+0x0000012A 0x0000018D 0x00000246 0x000500F0 0x00801201 0x01BB0C0C
+0x001021C0 0x000000FF 0x0FFF4000 0x00004002 0x0FFF0FFF 0x10F7E12A
+0x100FFC1E 0x08011850 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+// hdr: top_ctrl l11
+0x29 0x01 0x00 0x09 0x000B 0x00E 0x0000000C 0xF1090EF8
+0x00107AB5 0x00064114 0x00000D7F 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl l11
+0x29 0x01 0x00 0x09 0x001B 0x038 0x0000000C 0xF1090F28
+0x00003011 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x0287D1F4 0x0647D17C 0x0407D12C
+0x0096000A 0x032007EC 0x00000F7D 0x00020032 0x00000032 0x000001F4
+0x025A07EC 0x02140ED3 0x00FFF000 0x00002002 0x0000040C 0x000A007F
+0x00040810 0x00FBF40D 0x0000009E 0x00033D91 0x00007E65 0x00080000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl l11
+0x29 0x01 0x00 0x09 0x002B 0x007 0x0000000C 0xF1091000
+0x050140C8 0x28140802 0x00080190 0x00042233 0x07AA0FA0
+
+// hdr: tl_ctrl l11
+0x29 0x01 0x00 0x09 0x003B 0x04A 0x0000000C 0xF1091014
+0x1E77C1FA 0x1CC755DE 0x1B06E9C3 0x195679A7 0x17B60D8C 0x1605A572
+0x14653D57 0x12D4D53E 0x11447124 0x0FC4110C 0x0E43B0F4 0x0CE354DD
+0x0B82FCC6 0x0A32A8B1 0x0902589D 0x07D20C89 0x06C1C477 0x05B18066
+0x04C14456 0x03E10C47 0x0320D83A 0x0260A82E 0x01D08023 0x01405C1A
+0x00D03C12 0x0070240B 0x00301406 0x00100402 0x00000000 0x00000000
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000400
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x5A2DB058
+
+// hdr: tm_ctrl l11
+0x29 0x01 0x00 0x09 0x004B 0x035 0x0000000C 0xF1091134
+0x00000000 0x02460129 0x062C04CC 0x09A2083E 0x0D5A0BFB 0x0FDF0E8C
+0x0FFF0FFF 0x00000FFF 0x00000000 0x02460129 0x062C04CC 0x09A2083E
+0x0D5A0BFB 0x0FDF0E8C 0x0FFF0FFF 0x00000FFF 0x032003E8 0x0032012C
+0x00280028 0x00280028 0x00280028 0x00280028 0x00280028 0x040A0A02
+0x10101000 0x10101010 0x00001010 0x0FFF0FFF 0x0080000C 0x07EC1A02
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00C80100 0x0000007A 0x00000883
+0x00000080 0x0000021C 0x0100021C
+
+// hdr: ratio_ctrl l11
+0x29 0x01 0x00 0x09 0x006B 0x005 0x0000000C 0xF1091244
+0x00001000 0x00001000 0x00000100
+
+// hdr: col_ctrl l11
+0x29 0x01 0x00 0x09 0x007B 0x00A 0x0000000C 0xF1091250
+0x0000194D 0x00140678 0x00140763 0x00000CCC 0x00000CCC 0x00808080
+0x00080000 0x00080000
+
+// hdr: csc_ctrl l11
+0x29 0x01 0x00 0x09 0x009B 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E3C
+0x00000D9B 0x00002DC6 0x0000049F 0x0000F8AB 0x0000E755 0x00002000
+0x00002000 0x0000E2EF 0x0000FD11 0x00000000 0x00000000 0x00000000
+0x0001A649 0x00016E2A 0x0000B8CF 0x0000D9BE 0x0002DC55 0x000049EC
+0x000013CB 0x00007A0E 0x0003CD58 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x00000000 0x000064C9
+0x00004000 0x0000F403 0x0000E20A 0x00004000 0x000076C2 0x00000000
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl l11
+0x29 0x01 0x00 0x09 0x00AB 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl l11
+0x29 0x01 0x00 0x09 0x00BB 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000040 0x0012C136 0x000003E8 0x00200080
+0x0000012C 0x00008000 0x00000000
+
+// hdr: de_ctrl l11
+0x29 0x01 0x00 0x09 0x00CB 0x020 0x0000000C 0xF10913D8
+0x00040000 0x00805040 0x00008080 0x0000012A 0x000001D6 0x00000309
+0x000007EC 0x00000FFF 0x00204080 0x00000010 0x00000062 0x000000DF
+0x0000012A 0x0000018D 0x00000246 0x00064168 0x00801201 0x02E70C0C
+0x001021C0 0x000000FF 0x0FFF4000 0x00004002 0x0FFF0FFF 0x20F7E12A
+0x100FFC1E 0x08011850 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+// hdr: top_ctrl l12
+0x29 0x01 0x00 0x09 0x000C 0x00E 0x0000000C 0xF1090EF8
+0x00107AB5 0x00064184 0x00000D3F 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl l12
+0x29 0x01 0x00 0x09 0x001C 0x038 0x0000000C 0xF1090F28
+0x00003001 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x028320C8 0x0467D17C 0x0197D12C
+0x00963232 0x0C800961 0x000013CA 0x00020014 0x00000002 0x000003FF
+0x02140F7D 0x020A0000 0x00FFF000 0x00002002 0x0000040C 0x000A007F
+0x00040810 0x00FDF309 0x0000009E 0x00033D91 0x0000A8B0 0x00100000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl l12
+0x29 0x01 0x00 0x09 0x002C 0x007 0x0000000C 0xF1091000
+0x05014FFF 0x28140802 0x00080190 0x00042233 0x07AA0FA0
+
+// hdr: tl_ctrl l12
+0x29 0x01 0x00 0x09 0x003C 0x04A 0x0000000C 0xF1091014
+0x1E77C1FA 0x1CC755DE 0x1B06E9C3 0x195679A7 0x17B60D8C 0x1605A572
+0x14653D57 0x12D4D53E 0x11447124 0x0FC4110C 0x0E43B0F4 0x0CE354DD
+0x0B82FCC6 0x0A32A8B1 0x0902589D 0x07D20C89 0x06C1C477 0x05B18066
+0x04C14456 0x03E10C47 0x0320D83A 0x0260A82E 0x01D08023 0x01405C1A
+0x00D03C12 0x0070240B 0x00301406 0x00100402 0x00000000 0x00000000
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000400
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x5A2DB058
+
+// hdr: tm_ctrl l12
+0x29 0x01 0x00 0x09 0x004C 0x035 0x0000000C 0xF1091134
+0x01290000 0x0246018D 0x03980309 0x04CC040D 0x06670568 0x07EC0738
+0x07EC07EC 0x000007EC 0x01290000 0x0246018D 0x03980309 0x04CC040D
+0x06670568 0x07EC0738 0x07EC07EC 0x000007EC 0x032003E8 0x0032012C
+0x00280028 0x00280028 0x00280028 0x00280028 0x00280028 0x040A0A02
+0x10101000 0x10101010 0x00001010 0x0FFF0FFF 0x0080000C 0x07EC1A02
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00140100 0x00000002 0x00000883
+0x00000080 0x0000021C 0x0100021C
+
+// hdr: ratio_ctrl l12
+0x29 0x01 0x00 0x09 0x006C 0x005 0x0000000C 0xF1091244
+0x00001000 0x00001000 0x00000100
+
+// hdr: col_ctrl l12
+0x29 0x01 0x00 0x09 0x007C 0x00A 0x0000000C 0xF1091250
+0x0000194D 0x00140678 0x00140763 0x00000CCC 0x00000CCC 0x00808080
+0x00080000 0x00080000
+
+// hdr: csc_ctrl l12
+0x29 0x01 0x00 0x09 0x009C 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E3C
+0x00000D9B 0x00002DC6 0x0000049F 0x0000F8AB 0x0000E755 0x00002000
+0x00002000 0x0000E2EF 0x0000FD11 0x00000000 0x00000000 0x00000000
+0x0001A649 0x00016E2A 0x0000B8CF 0x0000D9BE 0x0002DC55 0x000049EC
+0x000013CB 0x00007A0E 0x0003CD58 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x00000000 0x000064C9
+0x00004000 0x0000F403 0x0000E20A 0x00004000 0x000076C2 0x00000000
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl l12
+0x29 0x01 0x00 0x09 0x00AC 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl l12
+0x29 0x01 0x00 0x09 0x00BC 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000040 0x00140118 0x00000190 0x00200080
+0x0000012C 0x00008000 0x000003E8
+
+// hdr: de_ctrl l12
+0x29 0x01 0x00 0x09 0x00CC 0x020 0x0000000C 0xF10913D8
+0x00040000 0x00645040 0x00008080 0x0000012A 0x0000018D 0x00000309
+0x00000667 0x000007EC 0x00408080 0x00000020 0x0000001A 0x00000062
+0x0000012A 0x0000018D 0x00000246 0x00050168 0x00801201 0x016B0C0C
+0x001021C0 0x000000FF 0x0FFF2800 0x00004002 0x0FFF0FFF 0x1079512A
+0x1003E81E 0x08012C50 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+// hdr: top_ctrl l7
+0x29 0x01 0x00 0x09 0x0007 0x00E 0x0000000C 0xF1090EF8
+0x00107AB5 0x00064194 0x00000D7F 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl l7
+0x29 0x01 0x00 0x09 0x0017 0x038 0x0000000C 0xF1090F28
+0x00003011 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x0287D1F4 0x0647D17C 0x0407D12C
+0x0096000A 0x032007EC 0x00000F7D 0x00020032 0x00000002 0x000001F4
+0x025A07EC 0x02140ED3 0x00FFF000 0x00002002 0x0000040C 0x000A007F
+0x00040810 0x00FBF40D 0x0000009E 0x00033D91 0x00007E65 0x00080000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl l7
+0x29 0x01 0x00 0x09 0x0027 0x007 0x0000000C 0xF1091000
+0x050140C8 0x28140802 0x00080190 0x00042233 0x07AA0FA0
+
+// hdr: tl_ctrl l7
+0x29 0x01 0x00 0x09 0x0037 0x04A 0x0000000C 0xF1091014
+0x1E77C1FA 0x1CC755DE 0x1B06E9C3 0x195679A7 0x17B60D8C 0x1605A572
+0x14653D57 0x12D4D53E 0x11447124 0x0FC4110C 0x0E43B0F4 0x0CE354DD
+0x0B82FCC6 0x0A32A8B1 0x0902589D 0x07D20C89 0x06C1C477 0x05B18066
+0x04C14456 0x03E10C47 0x0320D83A 0x0260A82E 0x01D08023 0x01405C1A
+0x00D03C12 0x0070240B 0x00301406 0x00100402 0x00000000 0x00000000
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000400
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x5A2DB058
+
+// hdr: tm_ctrl l7
+0x29 0x01 0x00 0x09 0x0047 0x035 0x0000000C 0xF1091134
+0x01290000 0x0246018D 0x03980309 0x04CC040D 0x06670568 0x07EC0738
+0x07EC07EC 0x000007EC 0x01290000 0x0246018D 0x03980309 0x04CC040D
+0x06670568 0x07EC0738 0x07EC07EC 0x000007EC 0x032003E8 0x0032012C
+0x00280028 0x00280028 0x00280028 0x00280028 0x00280028 0x040A0A02
+0x10101000 0x10101010 0x00001010 0x0FFF0FFF 0x0080000C 0x07EC1A02
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00140100 0x00000002 0x00000883
+0x00000080 0x0000021C 0x0100021C
+
+// hdr: ratio_ctrl l7
+0x29 0x01 0x00 0x09 0x0067 0x005 0x0000000C 0xF1091244
+0x00001000 0x00001000 0x00000100
+
+// hdr: col_ctrl l7
+0x29 0x01 0x00 0x09 0x0077 0x00A 0x0000000C 0xF1091250
+0x0000194D 0x00140678 0x00140763 0x00000CCC 0x00000CCC 0x00808080
+0x00080000 0x00080000
+
+// hdr: csc_ctrl l7
+0x29 0x01 0x00 0x09 0x0097 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E3C
+0x00000D9B 0x00002DC6 0x0000049F 0x0000F8AB 0x0000E755 0x00002000
+0x00002000 0x0000E2EF 0x0000FD11 0x00000000 0x00000000 0x00000000
+0x0001A649 0x00016E2A 0x0000B8CF 0x0000D9BE 0x0002DC55 0x000049EC
+0x000013CB 0x00007A0E 0x0003CD58 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x00000000 0x000064C9
+0x00004000 0x0000F403 0x0000E20A 0x00004000 0x000076C2 0x00000000
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl l7
+0x29 0x01 0x00 0x09 0x00A7 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl l7
+0x29 0x01 0x00 0x09 0x00B7 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000040 0x0012C10E 0x000003E8 0x00200080
+0x0000012C 0x00008000 0x00000000
+
+// hdr: de_ctrl l7
+0x29 0x01 0x00 0x09 0x00C7 0x020 0x0000000C 0xF10913D8
+0x00040000 0x00805040 0x00008080 0x0000012A 0x000001D6 0x00000309
+0x000007EC 0x00000FFF 0x00204080 0x00000010 0x00000062 0x000000DF
+0x0000012A 0x0000018D 0x00000246 0x00064168 0x00801201 0x02E70C0C
+0x001021C0 0x000000FF 0x0FFF4000 0x00004002 0x0FFF0FFF 0x20F7E12A
+0x100FFC1E 0x08011850 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+// hdr: top_ctrl l13
+0x29 0x01 0x00 0x09 0x000D 0x00E 0x0000000C 0xF1090EF8
+0x00107AB5 0x000753D4 0x00000D3F 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl l13
+0x29 0x01 0x00 0x09 0x001D 0x038 0x0000000C 0xF1090F28
+0x00003001 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x028320C8 0x0467D17C 0x0197D12C
+0x00963232 0x0C800961 0x000013CA 0x00020014 0x00000002 0x000003FF
+0x02140F7D 0x020A0000 0x00FFF000 0x00002002 0x0000040C 0x000A007F
+0x00040810 0x00FDF309 0x0000009E 0x00033D91 0x0000A8B0 0x00100000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl l13
+0x29 0x01 0x00 0x09 0x002D 0x007 0x0000000C 0xF1091000
+0x05014FFF 0x28140802 0x00080190 0x00042233 0x07AA0FA0
+
+// hdr: tl_ctrl l13
+0x29 0x01 0x00 0x09 0x003D 0x04A 0x0000000C 0xF1091014
+0x1E77C1FA 0x1CC755DE 0x1B06E9C3 0x195679A7 0x17B60D8C 0x1605A572
+0x14653D57 0x12D4D53E 0x11447124 0x0FC4110C 0x0E43B0F4 0x0CE354DD
+0x0B82FCC6 0x0A32A8B1 0x0902589D 0x07D20C89 0x06C1C477 0x05B18066
+0x04C14456 0x03E10C47 0x0320D83A 0x0260A82E 0x01D08023 0x01405C1A
+0x00D03C12 0x0070240B 0x00301406 0x00100402 0x00000000 0x00000000
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000400
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x5A2DB058
+
+// hdr: tm_ctrl l13
+0x29 0x01 0x00 0x09 0x004D 0x035 0x0000000C 0xF1091134
+0x01290000 0x0246018D 0x03980309 0x04CC040D 0x06670568 0x07EC0738
+0x07EC07EC 0x000007EC 0x01290000 0x0246018D 0x03980309 0x04CC040D
+0x06670568 0x07EC0738 0x07EC07EC 0x000007EC 0x032003E8 0x0032012C
+0x00280028 0x00280028 0x00280028 0x00280028 0x00280028 0x040A0A02
+0x10101000 0x10101010 0x00001010 0x0FFF0FFF 0x0080000C 0x07EC1A02
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00140100 0x00000002 0x00000883
+0x00000080 0x0000021C 0x0100021C
+
+// hdr: ratio_ctrl l13
+0x29 0x01 0x00 0x09 0x006D 0x005 0x0000000C 0xF1091244
+0x00001000 0x00001000 0x00000100
+
+// hdr: col_ctrl l13
+0x29 0x01 0x00 0x09 0x007D 0x00A 0x0000000C 0xF1091250
+0x0000194D 0x00140678 0x00140763 0x00000CCC 0x00000CCC 0x00808080
+0x00080000 0x00080000
+
+// hdr: csc_ctrl l13
+0x29 0x01 0x00 0x09 0x009D 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E3C
+0x00000D9B 0x00002DC6 0x0000049F 0x0000F8AB 0x0000E755 0x00002000
+0x00002000 0x0000E2EF 0x0000FD11 0x00000000 0x00000000 0x00000000
+0x0001A649 0x00016E2A 0x0000B8CF 0x0000D9BE 0x0002DC55 0x000049EC
+0x000013CB 0x00007A0E 0x0003CD58 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x00000000 0x000064C9
+0x00004000 0x0000F403 0x0000E20A 0x00004000 0x000076C2 0x00000000
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl l13
+0x29 0x01 0x00 0x09 0x00AD 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl l13
+0x29 0x01 0x00 0x09 0x00BD 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000040 0x00140118 0x00000190 0x00200080
+0x0000012C 0x00008000 0x000003E8
+
+// hdr: de_ctrl l13
+0x29 0x01 0x00 0x09 0x00CD 0x020 0x0000000C 0xF10913D8
+0x00040000 0x00645040 0x00008080 0x0000012A 0x0000018D 0x00000309
+0x00000667 0x000007EC 0x00408080 0x00000020 0x0000001A 0x00000062
+0x0000012A 0x0000018D 0x00000246 0x00050168 0x00801201 0x016B0C0C
+0x001021C0 0x000000FF 0x0FFF2800 0x00004002 0x0FFF0FFF 0x1079512A
+0x1003E81E 0x08012C50 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+// hdr: top_ctrl l4
+0x29 0x01 0x00 0x09 0x0004 0x00E 0x0000000C 0xF1090EF8
+0x0010B00B 0x00021350 0x000014F0 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl l4
+0x29 0x01 0x00 0x09 0x0014 0x038 0x0000000C 0xF1090F28
+0x00003001 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x0287D1F4 0x0467D17C 0x0197D12C
+0x00960000 0x0C8008C9 0x00000BD7 0x00020014 0x00000002 0x000003FF
+0x02640AD2 0x020A0000 0x00AF4000 0x00002EBE 0x0000040C 0x000A0057
+0x0005E293 0x00AEC4CB 0x0000006B 0x0004C8F8 0x00006AD2 0x00400000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl l4
+0x29 0x01 0x00 0x09 0x0024 0x007 0x0000000C 0xF1091000
+0x05014FFF 0x28140802 0x00080190 0x00042233 0x07AA0FA0
+
+// hdr: tl_ctrl l4
+0x29 0x01 0x00 0x09 0x0034 0x04A 0x0000000C 0xF1091014
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x18C6C1D5 0x12451969 0x0C639104 0x077240AA 0x03A13060 0x0120742A
+0x00000C09 0x00000800 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000400
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x2E175A2D
+
+// hdr: tm_ctrl l4
+0x29 0x01 0x00 0x09 0x0044 0x035 0x0000000C 0xF1091134
+0x04CB0000 0x08E407F5 0x09F2097F 0x0AD20A70 0x0B860B23 0x0C060BD7
+0x0CBB0C58 0x00000FFF 0x04CB0000 0x08E407F5 0x09F2097F 0x0AD20A70
+0x0B860B23 0x0C060BD7 0x0CBB0C58 0x00000FFF 0x02580578 0x01900258
+0x01900190 0x01900190 0x01900190 0x01900190 0x00140190 0x04080802
+0x04040404 0x02040404 0x00000202 0x0FFF0FFF 0x00FA0001 0x08201A03
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00140100 0x00000004 0x00000D66
+0x00000080 0x00002710 0x01002710
+
+// hdr: ratio_ctrl l4
+0x29 0x01 0x00 0x09 0x0064 0x005 0x0000000C 0xF1091244
+0x00001000 0x00001000 0x00000100
+
+// hdr: col_ctrl l4
+0x29 0x01 0x00 0x09 0x0074 0x00A 0x0000000C 0xF1091250
+0x0000197D 0x0014060F 0x001406EF 0x00000CCC 0x00000CCC 0x00808080
+0x00080000 0x00080000
+
+// hdr: csc_ctrl l4
+0x29 0x01 0x00 0x09 0x0094 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E38
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00000000 0x00000000 0x00000000
+0x00028C3E 0x00009416 0x0000ACEF 0x00010D01 0x0002B645 0x00003CB9
+0x00000000 0x00001CBF 0x00043E72 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x0000008D 0x0000071B
+0x00004000 0x0000FF73 0x0000F8E5 0x00004000 0x000023D7 0x0000EB7B
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl l4
+0x29 0x01 0x00 0x09 0x00A4 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl l4
+0x29 0x01 0x00 0x09 0x00B4 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000040 0x00100100 0x00000190 0x00200080
+0x0000012C 0x00008000 0x00000000
+
+// hdr: de_ctrl l4
+0x29 0x01 0x00 0x09 0x00C4 0x020 0x0000000C 0xF10913D8
+0x00040000 0x00645040 0x00008080 0x00000266 0x00000303 0x000004CB
+0x00000752 0x00000821 0x00408080 0x00000020 0x0000002F 0x000000DB
+0x00000266 0x00000303 0x000003F7 0x00050168 0x00801201 0x016B0C0C
+0x001021C0 0x000000FF 0x0FFF2800 0x00004002 0x0FFF0FFF 0x1082E058
+0x1003E81E 0x08012C50 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+// hdr: tm_sw_cfg l4
+0x29 0x01 0x00 0x09 0x0054 0x013 0x0000000C 0xF1091200
+0x04CB0000 0x08E407F5 0x09F2097F 0x0AD20A70 0x0B860B23 0x0C060BD7
+0x0CBB0C58 0x00000FFF 0x04CB0000 0x08E407F5 0x09F2097F 0x0AD20A70
+0x0B860B23 0x0C060BD7 0x0CBB0C58 0x00000FFF 0x00000000
+
+// hdr: top_ctrl l8
+0x29 0x01 0x00 0x09 0x0008 0x00E 0x0000000C 0xF1090EF8
+0x00107AB5 0x00064194 0x00000D7F 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl l8
+0x29 0x01 0x00 0x09 0x0018 0x038 0x0000000C 0xF1090F28
+0x00003011 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x0287D1F4 0x0647D17C 0x0407D12C
+0x0096000A 0x032007EC 0x00000F7D 0x00020032 0x00000002 0x000001F4
+0x025A07EC 0x02140ED3 0x00FFF000 0x00002002 0x0000040C 0x000A007F
+0x00040810 0x00FBF40D 0x0000009E 0x00033D91 0x00007E65 0x00080000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl l8
+0x29 0x01 0x00 0x09 0x0028 0x007 0x0000000C 0xF1091000
+0x050140C8 0x28140802 0x00080190 0x00042233 0x07AA0FA0
+
+// hdr: tl_ctrl l8
+0x29 0x01 0x00 0x09 0x0038 0x04A 0x0000000C 0xF1091014
+0x1E77C1FA 0x1CC755DE 0x1B06E9C3 0x195679A7 0x17B60D8C 0x1605A572
+0x14653D57 0x12D4D53E 0x11447124 0x0FC4110C 0x0E43B0F4 0x0CE354DD
+0x0B82FCC6 0x0A32A8B1 0x0902589D 0x07D20C89 0x06C1C477 0x05B18066
+0x04C14456 0x03E10C47 0x0320D83A 0x0260A82E 0x01D08023 0x01405C1A
+0x00D03C12 0x0070240B 0x00301406 0x00100402 0x00000000 0x00000000
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000400
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x5A2DB058
+
+// hdr: tm_ctrl l8
+0x29 0x01 0x00 0x09 0x0048 0x035 0x0000000C 0xF1091134
+0x01290000 0x0246018D 0x03980309 0x04CC040D 0x06670568 0x07EC0738
+0x07EC07EC 0x000007EC 0x01290000 0x0246018D 0x03980309 0x04CC040D
+0x06670568 0x07EC0738 0x07EC07EC 0x000007EC 0x032003E8 0x0032012C
+0x00280028 0x00280028 0x00280028 0x00280028 0x00280028 0x040A0A02
+0x10101000 0x10101010 0x00001010 0x0FFF0FFF 0x0080000C 0x07EC1A02
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00140100 0x00000002 0x00000883
+0x00000080 0x0000021C 0x0100021C
+
+// hdr: ratio_ctrl l8
+0x29 0x01 0x00 0x09 0x0068 0x005 0x0000000C 0xF1091244
+0x00001000 0x00001000 0x00000100
+
+// hdr: col_ctrl l8
+0x29 0x01 0x00 0x09 0x0078 0x00A 0x0000000C 0xF1091250
+0x0000194D 0x00140678 0x00140763 0x00000CCC 0x00000CCC 0x00808080
+0x00080000 0x00080000
+
+// hdr: csc_ctrl l8
+0x29 0x01 0x00 0x09 0x0098 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E3C
+0x00000D9B 0x00002DC6 0x0000049F 0x0000F8AB 0x0000E755 0x00002000
+0x00002000 0x0000E2EF 0x0000FD11 0x00000000 0x00000000 0x00000000
+0x0001A649 0x00016E2A 0x0000B8CF 0x0000D9BE 0x0002DC55 0x000049EC
+0x000013CB 0x00007A0E 0x0003CD58 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x00000000 0x000064C9
+0x00004000 0x0000F403 0x0000E20A 0x00004000 0x000076C2 0x00000000
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl l8
+0x29 0x01 0x00 0x09 0x00A8 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl l8
+0x29 0x01 0x00 0x09 0x00B8 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000040 0x0012C10E 0x000003E8 0x00200080
+0x0000012C 0x00008000 0x00000000
+
+// hdr: de_ctrl l8
+0x29 0x01 0x00 0x09 0x00C8 0x020 0x0000000C 0xF10913D8
+0x00040000 0x00805040 0x00008080 0x0000012A 0x000001D6 0x00000309
+0x000007EC 0x00000FFF 0x00204080 0x00000010 0x00000062 0x000000DF
+0x0000012A 0x0000018D 0x00000246 0x00064168 0x00801201 0x02E70C0C
+0x001021C0 0x000000FF 0x0FFF4000 0x00004002 0x0FFF0FFF 0x20F7E12A
+0x100FFC1E 0x08011850 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+// hdr: top_ctrl l9
+0x29 0x01 0x00 0x09 0x0009 0x00E 0x0000000C 0xF1090EF8
+0x00107AB5 0x00064194 0x00000D7F 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl l9
+0x29 0x01 0x00 0x09 0x0019 0x038 0x0000000C 0xF1090F28
+0x00003011 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x0287D1F4 0x0647D17C 0x0407D12C
+0x0096000A 0x032007EC 0x00000F7D 0x00020032 0x00000002 0x000001F4
+0x025A07EC 0x02140ED3 0x00FFF000 0x00002002 0x0000040C 0x000A007F
+0x00040810 0x00FBF40D 0x0000009E 0x00033D91 0x00007E65 0x00080000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl l9
+0x29 0x01 0x00 0x09 0x0029 0x007 0x0000000C 0xF1091000
+0x050140C8 0x28140802 0x00080190 0x00042233 0x07AA0FA0
+
+// hdr: tl_ctrl l9
+0x29 0x01 0x00 0x09 0x0039 0x04A 0x0000000C 0xF1091014
+0x1E77C1FA 0x1CC755DE 0x1B06E9C3 0x195679A7 0x17B60D8C 0x1605A572
+0x14653D57 0x12D4D53E 0x11447124 0x0FC4110C 0x0E43B0F4 0x0CE354DD
+0x0B82FCC6 0x0A32A8B1 0x0902589D 0x07D20C89 0x06C1C477 0x05B18066
+0x04C14456 0x03E10C47 0x0320D83A 0x0260A82E 0x01D08023 0x01405C1A
+0x00D03C12 0x0070240B 0x00301406 0x00100402 0x00000000 0x00000000
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000400
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x5A2DB058
+
+// hdr: tm_ctrl l9
+0x29 0x01 0x00 0x09 0x0049 0x035 0x0000000C 0xF1091134
+0x01290000 0x0246018D 0x03980309 0x04CC040D 0x06670568 0x07EC0738
+0x07EC07EC 0x000007EC 0x01290000 0x0246018D 0x03980309 0x04CC040D
+0x06670568 0x07EC0738 0x07EC07EC 0x000007EC 0x032003E8 0x0032012C
+0x00280028 0x00280028 0x00280028 0x00280028 0x00280028 0x040A0A02
+0x10101000 0x10101010 0x00001010 0x0FFF0FFF 0x0080000C 0x07EC1A02
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00140100 0x00000002 0x00000883
+0x00000080 0x0000021C 0x0100021C
+
+// hdr: ratio_ctrl l9
+0x29 0x01 0x00 0x09 0x0069 0x005 0x0000000C 0xF1091244
+0x00001000 0x00001000 0x00000100
+
+// hdr: col_ctrl l9
+0x29 0x01 0x00 0x09 0x0079 0x00A 0x0000000C 0xF1091250
+0x0000194D 0x00140678 0x00140763 0x00000CCC 0x00000CCC 0x00808080
+0x00080000 0x00080000
+
+// hdr: csc_ctrl l9
+0x29 0x01 0x00 0x09 0x0099 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E3C
+0x00000D9B 0x00002DC6 0x0000049F 0x0000F8AB 0x0000E755 0x00002000
+0x00002000 0x0000E2EF 0x0000FD11 0x00000000 0x00000000 0x00000000
+0x0001A649 0x00016E2A 0x0000B8CF 0x0000D9BE 0x0002DC55 0x000049EC
+0x000013CB 0x00007A0E 0x0003CD58 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x00000000 0x000064C9
+0x00004000 0x0000F403 0x0000E20A 0x00004000 0x000076C2 0x00000000
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl l9
+0x29 0x01 0x00 0x09 0x00A9 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl l9
+0x29 0x01 0x00 0x09 0x00B9 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000040 0x0012C10E 0x000003E8 0x00200080
+0x0000012C 0x00008000 0x00000000
+
+// hdr: de_ctrl l9
+0x29 0x01 0x00 0x09 0x00C9 0x020 0x0000000C 0xF10913D8
+0x00040000 0x00805040 0x00008080 0x0000012A 0x000001D6 0x00000309
+0x000007EC 0x00000FFF 0x00204080 0x00000010 0x00000062 0x000000DF
+0x0000012A 0x0000018D 0x00000246 0x00064168 0x00801201 0x02E70C0C
+0x001021C0 0x000000FF 0x0FFF4000 0x00004002 0x0FFF0FFF 0x20F7E12A
+0x100FFC1E 0x08011850 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+// hdr: top_ctrl l14
+0x29 0x01 0x00 0x09 0x000E 0x00E 0x0000000C 0xF1090EF8
+0x00107AB5 0x000751D4 0x00000D7F 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl l14
+0x29 0x01 0x00 0x09 0x001E 0x038 0x0000000C 0xF1090F28
+0x00003011 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x014C0100 0x0647097C 0x040C0200
+0x50501E32 0x014007EC 0x05A00F7D 0x00020032 0x00000032 0x00000190
+0x025A07EC 0x02140ED3 0x00FFF000 0x00002002 0x0000040C 0x000A007F
+0x00040810 0x00FBF40D 0x0000009E 0x00033D91 0x00007E65 0x00080000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl l14
+0x29 0x01 0x00 0x09 0x002E 0x007 0x0000000C 0xF1091000
+0x050140C8 0x28140802 0x00080190 0x00042233 0x07AA0FA0
+
+// hdr: tl_ctrl l14
+0x29 0x01 0x00 0x09 0x003E 0x04A 0x0000000C 0xF1091014
+0x1E77C1FA 0x1CC755DE 0x1B06E9C3 0x195679A7 0x17B60D8C 0x1605A572
+0x14653D57 0x12D4D53E 0x11447124 0x0FC4110C 0x0E43B0F4 0x0CE354DD
+0x0B82FCC6 0x0A32A8B1 0x0902589D 0x07D20C89 0x06C1C477 0x05B18066
+0x04C14456 0x03E10C47 0x0320D83A 0x0260A82E 0x01D08023 0x01405C1A
+0x00D03C12 0x0070240B 0x00301406 0x00100402 0x00000000 0x00000000
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000500
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x5A2DB058
+
+// hdr: tm_ctrl l14
+0x29 0x01 0x00 0x09 0x004E 0x035 0x0000000C 0xF1091134
+0x01290000 0x0246018D 0x03980309 0x04CC040D 0x06670568 0x07EC0738
+0x07EC07EC 0x000007EC 0x01290000 0x0246018D 0x03980309 0x04CC040D
+0x06670568 0x07EC0738 0x07EC07EC 0x000007EC 0x032003E8 0x0032012C
+0x00280028 0x00280028 0x00280028 0x00280028 0x00280028 0x040A0A02
+0x10101000 0x10101010 0x00001010 0x0FFF0FFF 0x0080000C 0x07EC1A02
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00140100 0x00000002 0x00000883
+0x00000080 0x0000021C 0x0100021C
+
+// hdr: ratio_ctrl l14
+0x29 0x01 0x00 0x09 0x006E 0x005 0x0000000C 0xF1091244
+0x00001000 0x00001000 0x00000100
+
+// hdr: col_ctrl l14
+0x29 0x01 0x00 0x09 0x007E 0x00A 0x0000000C 0xF1091250
+0x0000194D 0x00140678 0x00140763 0x00000CCC 0x00000CCC 0x00808080
+0x00080000 0x00080000
+
+// hdr: csc_ctrl l14
+0x29 0x01 0x00 0x09 0x009E 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E3C
+0x00000D9B 0x00002DC6 0x0000049F 0x0000F8AB 0x0000E755 0x00002000
+0x00002000 0x0000E2EF 0x0000FD11 0x00000000 0x00000000 0x00000000
+0x0001A649 0x00016E2A 0x0000B8CF 0x0000D9BE 0x0002DC55 0x000049EC
+0x000013CB 0x00007A0E 0x0003CD58 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x00000000 0x000064C9
+0x00004000 0x0000F403 0x0000E20A 0x00004000 0x000076C2 0x00000000
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl l14
+0x29 0x01 0x00 0x09 0x00AE 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl l14
+0x29 0x01 0x00 0x09 0x00BE 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000040 0x001180E6 0x000003E8 0x00200080
+0x0000012C 0x00008000 0x00000000
+
+// hdr: de_ctrl l14
+0x29 0x01 0x00 0x09 0x00CE 0x020 0x0000000C 0xF10913D8
+0x00040000 0x00464646 0x00004646 0x0000012A 0x000001D6 0x00000309
+0x000007EC 0x00000FFF 0x00204080 0x00000010 0x00000062 0x000000DF
+0x0000012A 0x0000018D 0x00000246 0x000500F0 0x00801201 0x01BB0C0C
+0x001021C0 0x000000FF 0x0FFF4000 0x00004002 0x0FFF0FFF 0x10F7E12A
+0x100FFC1E 0x08011850 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+// hdr: top_ctrl l15
+0x29 0x01 0x00 0x09 0x000F 0x00E 0x0000000C 0xF1090EF8
+0x00107AB5 0x000653D4 0x00000D3F 0x09240438 0x00000800 0x00000000
+0x00000000 0x00000020 0x00200020 0x00000020 0x00000020 0x00000020
+
+// hdr: lce_ctrl l15
+0x29 0x01 0x00 0x09 0x001F 0x038 0x0000000C 0xF1090F28
+0x00003001 0x04370000 0x09230000 0x001D40D8 0x00000100 0x001B00D8
+0x00360288 0x003A81D4 0x0075057C 0x028320C8 0x0467D17C 0x0197D12C
+0x00963232 0x0C800961 0x000013CA 0x00020014 0x00000002 0x000003FF
+0x02140F7D 0x020A0000 0x00FFF000 0x00002002 0x0000040C 0x000A007F
+0x00040810 0x00FDF309 0x0000009E 0x00033D91 0x0000A8B0 0x00100000
+0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD 0x0982ACBE
+0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403 0x000012F6
+0x000008C0 0x1D87B200 0x1986B9C3 0x1555B182 0x1134A53F 0x0D33A0FD
+0x0982ACBE 0x0641D086 0x03A11C55 0x01A08C2E 0x00703012 0x00000403
+
+// hdr: gra_ctrl l15
+0x29 0x01 0x00 0x09 0x002F 0x007 0x0000000C 0xF1091000
+0x05014FFF 0x28140802 0x00080190 0x00042233 0x07AA0FA0
+
+// hdr: tl_ctrl l15
+0x29 0x01 0x00 0x09 0x003F 0x04A 0x0000000C 0xF1091014
+0x1E77C1FA 0x1CC755DE 0x1B06E9C3 0x195679A7 0x17B60D8C 0x1605A572
+0x14653D57 0x12D4D53E 0x11447124 0x0FC4110C 0x0E43B0F4 0x0CE354DD
+0x0B82FCC6 0x0A32A8B1 0x0902589D 0x07D20C89 0x06C1C477 0x05B18066
+0x04C14456 0x03E10C47 0x0320D83A 0x0260A82E 0x01D08023 0x01405C1A
+0x00D03C12 0x0070240B 0x00301406 0x00100402 0x00000000 0x00000000
+0x1C3755E7 0x18C679B0 0x1575A57B 0x1244D546 0x0F441114 0x0C6354E4
+0x09D2A8B8 0x07720C90 0x0561806C 0x03A10C4C 0x0230A832 0x01205C1D
+0x0060240D 0x00000403 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000400
+0x00000400 0x0003EFBF 0x0003EFBE 0x0003DF7D 0x0000003C 0x00038EFF
+0x00028BF2 0x0001E926 0x00000017 0x00000000 0x00000000 0x5A2DB058
+
+// hdr: tm_ctrl l15
+0x29 0x01 0x00 0x09 0x004F 0x035 0x0000000C 0xF1091134
+0x01290000 0x0246018D 0x03980309 0x04CC040D 0x06670568 0x07EC0738
+0x07EC07EC 0x000007EC 0x01290000 0x0246018D 0x03980309 0x04CC040D
+0x06670568 0x07EC0738 0x07EC07EC 0x000007EC 0x032003E8 0x0032012C
+0x00280028 0x00280028 0x00280028 0x00280028 0x00280028 0x040A0A02
+0x10101000 0x10101010 0x00001010 0x0FFF0FFF 0x0080000C 0x07EC1A02
+0x00000000 0x000001A8 0x00001001 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
+0x00000000 0x00000000 0x00000000 0x00140100 0x00000002 0x00000883
+0x00000080 0x0000021C 0x0100021C
+
+// hdr: ratio_ctrl l15
+0x29 0x01 0x00 0x09 0x006F 0x005 0x0000000C 0xF1091244
+0x00001000 0x00001000 0x00000100
+
+// hdr: col_ctrl l15
+0x29 0x01 0x00 0x09 0x007F 0x00A 0x0000000C 0xF1091250
+0x0000194D 0x00140678 0x00140763 0x00000CCC 0x00000CCC 0x00808080
+0x00080000 0x00080000
+
+// hdr: csc_ctrl l15
+0x29 0x01 0x00 0x09 0x009F 0x04D 0x0000000C 0xF1091270
+0x00000E38 0x00001278 0x00000C18 0x00001058 0x00000E38 0x00000E3C
+0x00000D9B 0x00002DC6 0x0000049F 0x0000F8AB 0x0000E755 0x00002000
+0x00002000 0x0000E2EF 0x0000FD11 0x00000000 0x00000000 0x00000000
+0x0001A649 0x00016E2A 0x0000B8CF 0x0000D9BE 0x0002DC55 0x000049EC
+0x000013CB 0x00007A0E 0x0003CD58 0x00000000 0x00000000 0x00000000
+0x00000D9B 0x00002DC6 0x0000049F 0x000FF8AB 0x000FE755 0x00002000
+0x00002000 0x000FE2EF 0x000FFD11 0x00000000 0x00002000 0x00002000
+0x0000A09F 0x0000544C 0x00000B14 0x000011B0 0x0000EB68 0x000002E5
+0x00000433 0x0000168A 0x0000E543 0x00000000 0x00000000 0x00000000
+0x00004000 0x00000000 0x00000000 0x00000000 0x00004000 0x00000000
+0x00000000 0x00000000 0x00004000 0x00004000 0x00000000 0x000064C9
+0x00004000 0x0000F403 0x0000E20A 0x00004000 0x000076C2 0x00000000
+0x00000000 0x00000000 0x00000000
+
+// hdr: lut_ctrl l15
+0x29 0x01 0x00 0x09 0x00AF 0x008 0x0000000C 0xF109139C
+0x000000A8 0x000000A8 0x00000090 0x00000090 0x000000A8 0x00000090
+
+// hdr: scurve_ctrl l15
+0x29 0x01 0x00 0x09 0x00BF 0x00B 0x0000000C 0xF10913B4
+0x00000000 0x00000000 0x00000040 0x00100100 0x00000190 0x00200080
+0x0000012C 0x00008000 0x000003E8
+
+// hdr: de_ctrl l15
+0x29 0x01 0x00 0x09 0x00CF 0x020 0x0000000C 0xF10913D8
+0x00040000 0x00645040 0x00008080 0x0000012A 0x0000018D 0x00000309
+0x00000667 0x000007EC 0x00408080 0x00000020 0x0000001A 0x00000062
+0x0000012A 0x0000018D 0x00000246 0x00050168 0x00801201 0x016B0C0C
+0x001021C0 0x000000FF 0x0FFF2800 0x00004002 0x0FFF0FFF 0x1079512A
+0x1003E81E 0x08012C50 0x01A80100 0x00080200 0x0066640A 0x0033320A
+
+>;
+};
+};
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/pxlw/pxlw-iris6.dtsi b/arch/arm64/boot/dts/vendor/qcom/pxlw/pxlw-iris6.dtsi
new file mode 100644
index 0000000..66abe61
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/pxlw/pxlw-iris6.dtsi
@@ -0,0 +1,131 @@
+/* Copyright (c) 2020, Pixelworks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "pxlw-iris6-cfg-dsi-panel-hx83112a-auo-1080p-video.dtsi"
+
+&qupv3_se10_i2c {
+ //qcom,clk-freq-out = <1000000>;
+ status = "ok";
+ pixelworks@26 { //i2c: 22, i3c: 26
+ status = "ok";
+ compatible = "pixelworks,iris";
+ reg = <0x26>;
+ };
+};
+
+&tlmm {
+ pxlw_iris_gpio: pxlw_iris_gpio {
+ iris_wakeup_active: iris_wakeup_active {
+ mux {
+ pins = "gpio49";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio49";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ iris_wakeup_suspend: iris_wakeup_suspend {
+ mux {
+ pins = "gpio49";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio49";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ iris_abyp_ready_active: iris_abyp_ready_active {
+ mux {
+ pins = "gpio8";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ iris_abyp_ready_suspend: iris_abyp_ready_suspend {
+ mux {
+ pins = "gpio8";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ iris_vdd18_active: iris_vdd18_active {
+ mux {
+ pins = "gpio10";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ iris_vdd18_suspend: iris_vdd18_suspend {
+ mux {
+ pins = "gpio10";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+};
+
+&soc {
+ pxlw,iris {
+ compatible = "pxlw,iris";
+ index = <0>;
+
+ pinctrl-names = "iris_active", "iris_suspend";
+ pinctrl-0 = <&iris_wakeup_active &iris_abyp_ready_active>;
+ pinctrl-1 = <&iris_wakeup_suspend &iris_abyp_ready_suspend>;
+
+ qcom,iris-reset-gpio = <&tlmm 28 0>;
+ qcom,iris-wakeup-gpio = <&tlmm 49 0>;
+ qcom,iris-abyp-ready-gpio = <&tlmm 8 0>;
+ qcom,iris-vdd-gpio = <&tlmm 10 0>;
+
+ clocks = <&pmk8350_clkdiv 1>;
+ clock-names = "iris_clk";
+ };
+};
+
+&dsi_hx83112a_auo_1080_video {
+ qcom,mdss-dsi-display-timings {
+ timing@0{
+ pxlw,iris-lightup-config = <&mdss_iris_cfg_hx83112a_auo_fhd_60fps_video>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qcm2150-qrd-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/qcm2150-qrd-overlay.dts
new file mode 100755
index 0000000..67fbe50
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qcm2150-qrd-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+#include "qcm2150-qrd.dtsi"
+
+/ {
+ model = "QRD";
+ qcom,board-id = <0x01000b 4>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qcm2150-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/qcm2150-qrd.dts
new file mode 100755
index 0000000..5dbd00e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qcm2150-qrd.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "qcm2150.dtsi"
+#include "qcm2150-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCM2150 QRD";
+ compatible = "qcom,qcm2150-qrd", "qcom,qcm2150", "qcom,qrd";
+ qcom,board-id = <0x01000b 4>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qcm2150-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/qcm2150-qrd.dtsi
new file mode 100755
index 0000000..ae36bce
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qcm2150-qrd.dtsi
@@ -0,0 +1,5 @@
+#include "qm215-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCM2150 QRD";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qcm2150.dts b/arch/arm64/boot/dts/vendor/qcom/qcm2150.dts
new file mode 100755
index 0000000..3285ef4
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qcm2150.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "qcm2150.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCM2150";
+ compatible = "qcom,qcm2150";
+ qcom,pmic-name = "PM8916";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qcm2150.dtsi b/arch/arm64/boot/dts/vendor/qcom/qcm2150.dtsi
new file mode 100755
index 0000000..07091d40
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qcm2150.dtsi
@@ -0,0 +1,11 @@
+#include "qm215.dtsi"
+#include "qm215-pm8916.dtsi"
+/* TBD */
+/* #include "qm215-audio.dtsi" */
+
+/ {
+ model = "Qualcomm Technologies, Inc. QCM2150";
+ compatible = "qcom,qcm2150";
+ qcom,msm-id = <436 0x0>;
+ qcom,msm-name = "QCM2150";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-alium-3600mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-alium-3600mah.dtsi
new file mode 100755
index 0000000..051f641
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-alium-3600mah.dtsi
@@ -0,0 +1,1035 @@
+qcom,alium_860_89032_0000_3600mAh {
+ /* Alium_860_89032_0000_3600mAh_averaged_MasterSlave_Jun15th2018 */
+ qcom,max-voltage-uv = <4350000>;
+ qcom,fg-cc-cv-threshold-uv = <4340000>;
+ qcom,fastchg-current-ma = <5400>;
+ qcom,batt-id-kohm = <107>;
+ qcom,battery-beta = <4250>;
+ qcom,battery-therm-kohm = <100>;
+ qcom,battery-type = "Alium_860_89032_0000_3600mAh_Jun15th2018";
+ qcom,qg-batt-profile-ver = <100>;
+
+ qcom,jeita-fcc-ranges = <0 50 2500000
+ 51 400 5400000
+ 401 450 2500000>;
+ qcom,jeita-fv-ranges = <0 50 4250000
+ 51 400 4350000
+ 401 450 4250000>;
+ qcom,step-chg-ranges = <3600000 3800000 5400000
+ 3800001 4300000 3600000
+ 4300001 4350000 2500000>;
+ qcom,ocv-based-step-chg;
+
+ /* COOL = 5 DegC, WARM = 40 DegC */
+ qcom,jeita-soft-thresholds = <0x5314 0x25e3>;
+ /* COLD = 0 DegC, HOT = 45 DegC */
+ qcom,jeita-hard-thresholds = <0x58cd 0x20b8>;
+ /* COOL hys = 8 DegC, WARM hys = 37 DegC */
+ qcom,jeita-soft-hys-thresholds = <0x4f5e 0x2943>;
+ qcom,jeita-soft-fcc-ua = <2500000 2500000>;
+ qcom,jeita-soft-fv-uv = <4250000 4250000>;
+
+ qcom,fcc1-temp-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-data = <3426 3519 3581 3613 3630>;
+ };
+
+ qcom,fcc2-temp-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-data = <3546 3576 3586 3588 3583 3583>;
+ };
+
+ qcom,pc-temp-v1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <43078 43267 43365 43394 43399>,
+ <42839 43052 43147 43186 43196>,
+ <42609 42823 42920 42964 42981>,
+ <42392 42591 42693 42738 42759>,
+ <42186 42370 42469 42513 42535>,
+ <41983 42159 42248 42289 42310>,
+ <41776 41953 42032 42066 42085>,
+ <41565 41745 41820 41847 41863>,
+ <41376 41534 41607 41630 41645>,
+ <41226 41338 41393 41412 41426>,
+ <41086 41189 41206 41205 41212>,
+ <40873 41057 41063 41032 41014>,
+ <40523 40858 40918 40878 40833>,
+ <40155 40509 40680 40678 40639>,
+ <39917 40145 40325 40390 40407>,
+ <39757 39925 40039 40116 40180>,
+ <39638 39781 39894 39960 40010>,
+ <39541 39669 39779 39850 39877>,
+ <39455 39579 39646 39699 39715>,
+ <39364 39489 39487 39469 39489>,
+ <39266 39366 39306 39235 39257>,
+ <39165 39210 39096 39058 39072>,
+ <39060 39042 38900 38912 38919>,
+ <38955 38854 38767 38784 38785>,
+ <38859 38675 38671 38668 38668>,
+ <38773 38551 38581 38562 38562>,
+ <38692 38462 38490 38466 38462>,
+ <38619 38394 38403 38377 38369>,
+ <38552 38343 38327 38296 38283>,
+ <38491 38301 38257 38222 38203>,
+ <38439 38261 38195 38156 38132>,
+ <38392 38224 38142 38097 38067>,
+ <38348 38190 38095 38043 38010>,
+ <38306 38161 38052 37989 37952>,
+ <38265 38135 38015 37938 37895>,
+ <38223 38102 37976 37886 37836>,
+ <38181 38066 37935 37830 37771>,
+ <38128 38020 37890 37771 37701>,
+ <38054 37950 37823 37699 37623>,
+ <37964 37850 37727 37613 37538>,
+ <37862 37740 37617 37512 37439>,
+ <37739 37617 37494 37390 37318>,
+ <37601 37487 37361 37256 37185>,
+ <37448 37354 37221 37119 37052>,
+ <37327 37238 37120 37019 36955>,
+ <37241 37161 37057 36960 36898>,
+ <37209 37134 37035 36943 36881>,
+ <37182 37113 37018 36927 36865>,
+ <37146 37086 36991 36896 36829>,
+ <37036 36976 36855 36724 36634>,
+ <36712 36636 36510 36372 36278>,
+ <36253 36181 36056 35916 35819>,
+ <35673 35600 35476 35330 35231>,
+ <34889 34811 34685 34533 34429>,
+ <33644 33573 33450 33289 33175>,
+ <30000 30000 30000 30000 30000>;
+ };
+
+ qcom,pc-temp-v2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <43405 43390 43380 43360 43310 43280>,
+ <43003 43066 43092 43094 43055 43033>,
+ <42659 42770 42823 42839 42808 42792>,
+ <42388 42505 42573 42597 42570 42556>,
+ <42183 42269 42342 42369 42341 42328>,
+ <41972 42046 42121 42146 42116 42104>,
+ <41647 41828 41907 41928 41893 41879>,
+ <41314 41618 41700 41715 41674 41657>,
+ <41242 41409 41488 41499 41455 41438>,
+ <41295 41194 41265 41273 41232 41219>,
+ <41338 41020 41073 41079 41031 41013>,
+ <41030 40918 40949 40949 40883 40839>,
+ <40301 40831 40837 40833 40747 40674>,
+ <39816 40619 40617 40621 40542 40474>,
+ <39553 40056 40158 40222 40214 40226>,
+ <39352 39574 39750 39893 39934 39999>,
+ <39187 39400 39544 39757 39792 39836>,
+ <39047 39287 39391 39659 39684 39694>,
+ <38903 39154 39240 39507 39524 39512>,
+ <38748 38998 39093 39269 39281 39271>,
+ <38600 38840 38951 39039 39045 39043>,
+ <38473 38688 38809 38867 38872 38870>,
+ <38360 38541 38673 38723 38728 38725>,
+ <38269 38408 38551 38598 38603 38600>,
+ <38195 38289 38441 38488 38492 38488>,
+ <38132 38186 38339 38387 38390 38385>,
+ <38076 38102 38245 38293 38296 38290>,
+ <38026 38033 38158 38206 38208 38200>,
+ <37976 37977 38077 38128 38127 38118>,
+ <37929 37931 38001 38058 38053 38043>,
+ <37882 37891 37932 37991 37985 37974>,
+ <37835 37852 37869 37926 37922 37912>,
+ <37786 37815 37814 37863 37863 37853>,
+ <37734 37776 37764 37798 37793 37778>,
+ <37680 37735 37722 37732 37704 37675>,
+ <37621 37692 37680 37666 37610 37565>,
+ <37558 37641 37633 37602 37526 37469>,
+ <37492 37582 37583 37538 37448 37384>,
+ <37421 37513 37524 37470 37374 37308>,
+ <37348 37429 37450 37396 37302 37235>,
+ <37274 37332 37362 37312 37222 37156>,
+ <37201 37229 37261 37208 37121 37056>,
+ <37130 37124 37145 37082 36997 36933>,
+ <37054 37029 37028 36964 36881 36820>,
+ <36966 36949 36952 36902 36830 36771>,
+ <36849 36873 36903 36875 36801 36743>,
+ <36768 36823 36880 36854 36784 36726>,
+ <36666 36763 36850 36823 36756 36699>,
+ <36509 36668 36775 36740 36671 36604>,
+ <36284 36467 36557 36486 36422 36338>,
+ <35954 36107 36161 36071 36005 35919>,
+ <35477 35597 35626 35539 35482 35397>,
+ <34808 34917 34941 34844 34796 34717>,
+ <33818 33942 34003 33928 33918 33830>,
+ <32458 32548 32795 32808 32663 32496>,
+ <28619 28270 28017 28020 27984 27930>;
+ };
+
+ qcom,pc-temp-z1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <14545 13238 12041 11680 11593>,
+ <14523 13183 12045 11678 11602>,
+ <14531 13174 12043 11685 11612>,
+ <14535 13182 12039 11687 11616>,
+ <14547 13186 12035 11688 11618>,
+ <14571 13181 12033 11688 11620>,
+ <14591 13164 12034 11689 11623>,
+ <14582 13150 12035 11692 11626>,
+ <14551 13149 12037 11694 11629>,
+ <14518 13154 12041 11697 11631>,
+ <14486 13152 12045 11701 11634>,
+ <14452 13134 12047 11704 11639>,
+ <14403 13116 12047 11707 11643>,
+ <14352 13102 12043 11707 11644>,
+ <14318 13096 12036 11705 11644>,
+ <14291 13097 12033 11703 11644>,
+ <14262 13097 12036 11707 11647>,
+ <14226 13100 12042 11714 11653>,
+ <14194 13111 12052 11721 11659>,
+ <14181 13129 12065 11726 11663>,
+ <14179 13150 12076 11731 11667>,
+ <14186 13172 12085 11736 11672>,
+ <14195 13188 12093 11741 11676>,
+ <14207 13195 12101 11745 11681>,
+ <14215 13201 12109 11751 11686>,
+ <14220 13210 12116 11756 11690>,
+ <14223 13222 12123 11760 11695>,
+ <14228 13229 12130 11764 11699>,
+ <14239 13234 12137 11768 11703>,
+ <14255 13242 12143 11772 11707>,
+ <14279 13250 12149 11776 11711>,
+ <14302 13257 12154 11780 11716>,
+ <14310 13265 12160 11784 11720>,
+ <14314 13278 12166 11789 11725>,
+ <14320 13297 12174 11794 11729>,
+ <14343 13315 12181 11799 11733>,
+ <14395 13333 12189 11802 11736>,
+ <14443 13346 12197 11804 11738>,
+ <14481 13351 12202 11807 11740>,
+ <14512 13353 12205 11809 11741>,
+ <14514 13357 12209 11811 11742>,
+ <14472 13369 12217 11813 11744>,
+ <14451 13384 12223 11815 11745>,
+ <14446 13399 12224 11816 11746>,
+ <14433 13385 12228 11817 11746>,
+ <14447 13396 12231 11819 11746>,
+ <14441 13396 12232 11819 11745>,
+ <14440 13403 12233 11819 11746>,
+ <14431 13399 12239 11820 11747>,
+ <14460 13394 12241 11824 11750>,
+ <14470 13423 12251 11830 11755>,
+ <14506 13430 12275 11839 11760>,
+ <14485 13470 12295 11850 11770>,
+ <14544 13512 12338 11868 11782>,
+ <14544 13512 12338 11868 11782>,
+ <14544 13512 12338 11868 11782>;
+ };
+
+ qcom,pc-temp-z2-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <11192 9778 10257 10603 10910>,
+ <10253 10813 10276 10490 10558>,
+ <9726 10534 10287 10428 10436>,
+ <9734 10061 10282 10413 10412>,
+ <9760 9938 10269 10392 10406>,
+ <9775 9923 10261 10380 10404>,
+ <9777 9909 10257 10375 10408>,
+ <9772 9898 10258 10370 10412>,
+ <9765 9890 10262 10368 10412>,
+ <9755 9884 10265 10372 10421>,
+ <9746 9880 10259 10375 10444>,
+ <9750 9878 10227 10382 10452>,
+ <9766 9881 10199 10414 10451>,
+ <9772 9895 10216 10429 10452>,
+ <9752 9907 10260 10399 10450>,
+ <9717 9910 10282 10371 10439>,
+ <9701 9914 10279 10383 10449>,
+ <9697 9923 10269 10418 10506>,
+ <9693 9949 10295 10465 10551>,
+ <9686 9981 10388 10545 10559>,
+ <9673 10014 10446 10602 10559>,
+ <9662 10050 10419 10553 10531>,
+ <9655 10080 10371 10429 10478>,
+ <9649 10101 10339 10379 10444>,
+ <9631 10116 10316 10398 10420>,
+ <9588 10124 10303 10422 10405>,
+ <9554 10131 10300 10409 10406>,
+ <9540 10135 10301 10384 10415>,
+ <9483 10134 10309 10376 10426>,
+ <9426 10131 10329 10376 10445>,
+ <9408 10130 10351 10380 10472>,
+ <9395 10131 10373 10399 10506>,
+ <9386 10133 10396 10437 10548>,
+ <9378 10137 10420 10474 10594>,
+ <9372 10146 10446 10506 10651>,
+ <9368 10154 10463 10533 10695>,
+ <9374 10162 10468 10556 10712>,
+ <9380 10167 10471 10580 10722>,
+ <9389 10171 10479 10593 10733>,
+ <9398 10176 10491 10596 10745>,
+ <9397 10178 10497 10597 10753>,
+ <9384 10169 10490 10609 10755>,
+ <9380 10140 10483 10625 10759>,
+ <9386 9964 10481 10631 10781>,
+ <9324 9926 10454 10642 10811>,
+ <9305 9932 10438 10669 10808>,
+ <9287 9948 10463 10697 10858>,
+ <9289 9933 10557 10698 10889>,
+ <9274 9965 10622 10758 10917>,
+ <9278 9923 10533 10711 10837>,
+ <9316 9884 10462 10634 10693>,
+ <9326 9807 10425 10609 10671>,
+ <9285 9724 10395 10535 10591>,
+ <9245 9615 10285 10458 10500>,
+ <9245 9615 10285 10458 10500>,
+ <9245 9615 10285 10458 10500>;
+ };
+
+ qcom,pc-temp-z3-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <19525 19431 19373 19383 19355>,
+ <19784 19494 19408 19370 19350>,
+ <19920 19574 19438 19372 19351>,
+ <19937 19651 19450 19380 19356>,
+ <19918 19673 19455 19382 19359>,
+ <19895 19676 19456 19383 19362>,
+ <19884 19677 19454 19381 19362>,
+ <19879 19677 19451 19376 19359>,
+ <19877 19680 19448 19372 19355>,
+ <19874 19682 19446 19372 19353>,
+ <19872 19668 19440 19372 19352>,
+ <19877 19628 19423 19367 19352>,
+ <19894 19610 19400 19355 19349>,
+ <19909 19638 19406 19350 19345>,
+ <19892 19671 19439 19363 19347>,
+ <19843 19665 19457 19379 19351>,
+ <19796 19628 19436 19373 19348>,
+ <19760 19594 19408 19356 19338>,
+ <19726 19567 19407 19352 19335>,
+ <19697 19550 19425 19366 19342>,
+ <19672 19554 19438 19379 19351>,
+ <19654 19573 19439 19379 19357>,
+ <19644 19591 19439 19374 19361>,
+ <19636 19603 19437 19373 19362>,
+ <19628 19612 19434 19380 19360>,
+ <19619 19613 19433 19386 19358>,
+ <19607 19611 19439 19383 19356>,
+ <19596 19607 19445 19378 19354>,
+ <19583 19601 19446 19374 19352>,
+ <19567 19594 19444 19369 19350>,
+ <19549 19588 19442 19365 19348>,
+ <19530 19583 19439 19362 19345>,
+ <19514 19578 19434 19360 19342>,
+ <19499 19571 19431 19359 19338>,
+ <19486 19563 19429 19358 19334>,
+ <19479 19557 19426 19358 19332>,
+ <19483 19551 19422 19358 19332>,
+ <19491 19546 19418 19357 19334>,
+ <19513 19542 19415 19356 19334>,
+ <19535 19539 19414 19351 19331>,
+ <19526 19535 19412 19347 19329>,
+ <19496 19530 19410 19347 19330>,
+ <19483 19519 19408 19347 19330>,
+ <19481 19451 19404 19347 19331>,
+ <19372 19379 19382 19344 19327>,
+ <19345 19348 19360 19337 19320>,
+ <19337 19340 19358 19328 19312>,
+ <19339 19335 19342 19326 19312>,
+ <19316 19318 19331 19324 19309>,
+ <19320 19317 19352 19335 19324>,
+ <19371 19345 19355 19339 19331>,
+ <19418 19350 19357 19342 19332>,
+ <19442 19348 19353 19346 19335>,
+ <19464 19360 19359 19349 19340>,
+ <19464 19360 19359 19349 19340>,
+ <19464 19360 19359 19349 19340>;
+ };
+
+ qcom,pc-temp-z4-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <16385 15501 14962 14712 14715>,
+ <16621 15491 14959 14790 14777>,
+ <16602 15456 14922 14802 14786>,
+ <16518 15370 14881 14784 14773>,
+ <16384 15265 14843 14759 14750>,
+ <16241 15178 14812 14736 14726>,
+ <16119 15106 14786 14721 14710>,
+ <16009 15051 14764 14710 14700>,
+ <15894 15008 14752 14704 14694>,
+ <15746 14969 14746 14701 14689>,
+ <15604 14928 14744 14698 14685>,
+ <15557 14895 14744 14693 14681>,
+ <15579 14889 14745 14687 14673>,
+ <15600 14901 14749 14689 14670>,
+ <15554 14908 14754 14704 14683>,
+ <15436 14889 14752 14715 14696>,
+ <15339 14846 14732 14699 14686>,
+ <15282 14813 14713 14669 14663>,
+ <15245 14793 14712 14671 14662>,
+ <15230 14781 14722 14728 14708>,
+ <15221 14780 14742 14778 14758>,
+ <15217 14783 14794 14782 14763>,
+ <15221 14793 14846 14777 14751>,
+ <15227 14842 14846 14766 14737>,
+ <15232 14904 14815 14739 14722>,
+ <15237 14918 14783 14717 14709>,
+ <15244 14915 14759 14707 14700>,
+ <15250 14910 14740 14702 14693>,
+ <15262 14895 14729 14697 14687>,
+ <15275 14872 14722 14693 14682>,
+ <15283 14853 14717 14690 14677>,
+ <15290 14837 14715 14686 14673>,
+ <15294 14821 14714 14682 14670>,
+ <15292 14806 14713 14682 14669>,
+ <15285 14792 14713 14684 14672>,
+ <15265 14778 14712 14686 14677>,
+ <15218 14764 14710 14689 14683>,
+ <15171 14753 14707 14691 14689>,
+ <15100 14750 14704 14691 14691>,
+ <15036 14748 14701 14691 14688>,
+ <15028 14745 14698 14690 14685>,
+ <15035 14740 14695 14688 14684>,
+ <15033 14741 14690 14685 14683>,
+ <15011 14800 14682 14681 14680>,
+ <15037 14827 14679 14667 14668>,
+ <15046 14838 14675 14645 14644>,
+ <15051 14840 14669 14641 14637>,
+ <15043 14842 14681 14633 14624>,
+ <15056 14851 14689 14629 14622>,
+ <15040 14847 14670 14638 14636>,
+ <15003 14839 14678 14645 14640>,
+ <14990 14846 14681 14646 14645>,
+ <14996 14862 14691 14647 14646>,
+ <15017 14877 14695 14650 14646>,
+ <15017 14877 14695 14650 14646>,
+ <15017 14877 14695 14650 14646>;
+ };
+
+ qcom,pc-temp-z5-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <11068 11690 13464 19085 17868>,
+ <12016 12370 14843 18209 18510>,
+ <12567 13373 16287 18434 19041>,
+ <12767 14431 17166 19331 19871>,
+ <12906 14953 17644 19970 20772>,
+ <13043 15275 18035 20553 21985>,
+ <13254 15589 18448 20812 22838>,
+ <13520 16021 18878 20763 23075>,
+ <13787 16665 19253 20832 23069>,
+ <14074 17170 19532 21287 23403>,
+ <14425 17078 19373 21540 24108>,
+ <14893 16220 17894 20839 24888>,
+ <15428 16083 16100 18925 24832>,
+ <15715 18342 16976 18223 24189>,
+ <15770 20589 20553 20659 24472>,
+ <15797 20502 22513 23616 25498>,
+ <15834 19565 21295 23828 25788>,
+ <15830 19061 19385 22969 25708>,
+ <15750 18918 21990 23440 25684>,
+ <15580 18870 30436 27428 25707>,
+ <15309 20532 34653 30469 25746>,
+ <15057 25755 30884 27232 24220>,
+ <14852 31080 25218 20500 20766>,
+ <14649 35866 22212 18547 19399>,
+ <14406 39481 20440 20518 19854>,
+ <14102 39590 19963 22400 20596>,
+ <13801 37343 21441 23200 21434>,
+ <13549 34779 23939 23840 22513>,
+ <13290 32437 26091 24203 23750>,
+ <13021 30286 28345 24605 25226>,
+ <12746 29196 30150 25017 26620>,
+ <12479 28629 31211 25585 27804>,
+ <12282 28181 32038 26640 28805>,
+ <12126 27688 32872 28101 29029>,
+ <11990 27267 33745 30291 28636>,
+ <11896 27207 34089 31579 28289>,
+ <11945 27442 32771 31455 28513>,
+ <12049 27808 30864 31087 28942>,
+ <12350 28315 30537 30322 28828>,
+ <12671 28953 30633 27821 27284>,
+ <12642 29117 30687 26060 26101>,
+ <12299 27717 30577 26308 26287>,
+ <12208 24781 30313 26635 26505>,
+ <12309 16408 28848 26643 26112>,
+ <11428 13096 22891 26468 25271>,
+ <11198 12322 18301 26248 25109>,
+ <11112 12144 18213 22490 22887>,
+ <11116 12041 15832 22757 25790>,
+ <10935 11705 14733 23506 25696>,
+ <10976 11757 17791 27597 30144>,
+ <11440 12275 17295 25361 28944>,
+ <11648 12197 17311 24873 26253>,
+ <11657 11966 16067 25059 25290>,
+ <11600 11884 16052 23410 24581>,
+ <11600 11884 16052 23410 24581>,
+ <11600 11884 16052 23410 24581>;
+ };
+
+ qcom,pc-temp-z6-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <16538 15406 14813 14639 14611>,
+ <16749 15432 14830 14667 14637>,
+ <16795 15447 14830 14674 14643>,
+ <16769 15440 14820 14671 14641>,
+ <16699 15411 14805 14663 14634>,
+ <16612 15372 14791 14653 14625>,
+ <16540 15333 14779 14645 14619>,
+ <16482 15307 14768 14638 14613>,
+ <16423 15289 14762 14634 14608>,
+ <16352 15271 14759 14633 14606>,
+ <16282 15242 14755 14632 14604>,
+ <16243 15204 14746 14628 14603>,
+ <16229 15190 14734 14620 14598>,
+ <16213 15202 14738 14617 14595>,
+ <16158 15216 14756 14631 14602>,
+ <16064 15204 14764 14643 14610>,
+ <15984 15167 14745 14634 14604>,
+ <15930 15138 14722 14613 14590>,
+ <15887 15120 14722 14612 14588>,
+ <15858 15110 14737 14646 14613>,
+ <15836 15113 14757 14675 14640>,
+ <15826 15129 14785 14678 14644>,
+ <15826 15150 14807 14675 14644>,
+ <15831 15182 14806 14671 14642>,
+ <15836 15213 14793 14664 14635>,
+ <15841 15221 14782 14658 14628>,
+ <15846 15221 14776 14653 14623>,
+ <15850 15220 14772 14648 14620>,
+ <15854 15214 14769 14645 14617>,
+ <15856 15204 14766 14641 14614>,
+ <15856 15196 14763 14638 14611>,
+ <15856 15188 14761 14635 14608>,
+ <15855 15180 14760 14632 14605>,
+ <15853 15174 14759 14632 14604>,
+ <15851 15168 14759 14633 14604>,
+ <15851 15164 14758 14634 14604>,
+ <15853 15160 14756 14636 14607>,
+ <15855 15157 14754 14637 14611>,
+ <15855 15157 14752 14637 14612>,
+ <15854 15158 14751 14634 14610>,
+ <15851 15158 14750 14632 14608>,
+ <15842 15157 14749 14631 14608>,
+ <15832 15156 14747 14631 14607>,
+ <15821 15148 14743 14630 14607>,
+ <15777 15126 14731 14621 14600>,
+ <15764 15120 14719 14609 14585>,
+ <15763 15114 14716 14602 14578>,
+ <15759 15116 14713 14598 14572>,
+ <15757 15111 14711 14595 14570>,
+ <15765 15116 14716 14605 14584>,
+ <15777 15136 14723 14612 14591>,
+ <15805 15152 14732 14616 14594>,
+ <15840 15173 14739 14621 14598>,
+ <15893 15213 14754 14628 14605>,
+ <15893 15213 14754 14628 14605>,
+ <15893 15213 14754 14628 14605>;
+ };
+
+ qcom,pc-temp-y1-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <7598 6764 6071 5440 5223 5179>,
+ <7604 6767 6083 5439 5222 5181>,
+ <7616 6772 6090 5438 5222 5182>,
+ <7629 6778 6094 5436 5222 5184>,
+ <7640 6782 6096 5435 5223 5185>,
+ <7645 6784 6096 5434 5223 5187>,
+ <7644 6784 6092 5434 5224 5187>,
+ <7642 6784 6086 5434 5226 5188>,
+ <7635 6781 6085 5435 5228 5189>,
+ <7612 6774 6088 5436 5229 5190>,
+ <7594 6768 6090 5437 5231 5192>,
+ <7603 6766 6086 5437 5232 5193>,
+ <7624 6767 6080 5437 5234 5195>,
+ <7644 6772 6081 5438 5236 5197>,
+ <7668 6789 6096 5445 5241 5202>,
+ <7683 6807 6107 5453 5244 5204>,
+ <7674 6820 6111 5455 5244 5205>,
+ <7655 6831 6115 5458 5245 5205>,
+ <7640 6832 6116 5460 5246 5206>,
+ <7626 6817 6114 5461 5248 5209>,
+ <7619 6805 6114 5464 5251 5212>,
+ <7638 6807 6125 5468 5255 5216>,
+ <7673 6815 6139 5472 5259 5219>,
+ <7681 6821 6141 5477 5262 5223>,
+ <7680 6824 6136 5481 5265 5226>,
+ <7684 6828 6135 5485 5267 5230>,
+ <7689 6840 6144 5489 5270 5234>,
+ <7692 6860 6155 5494 5274 5237>,
+ <7690 6871 6158 5499 5277 5240>,
+ <7672 6876 6162 5505 5280 5242>,
+ <7648 6878 6167 5510 5283 5245>,
+ <7641 6875 6171 5515 5287 5248>,
+ <7643 6871 6175 5520 5290 5252>,
+ <7645 6871 6176 5523 5293 5255>,
+ <7649 6869 6177 5526 5296 5257>,
+ <7656 6867 6179 5529 5298 5259>,
+ <7671 6879 6183 5531 5300 5260>,
+ <7690 6895 6188 5533 5301 5261>,
+ <7693 6895 6193 5534 5301 5262>,
+ <7679 6883 6197 5535 5302 5262>,
+ <7669 6879 6202 5537 5303 5263>,
+ <7670 6885 6209 5541 5305 5265>,
+ <7670 6891 6220 5544 5306 5266>,
+ <7670 6898 6217 5546 5307 5267>,
+ <7674 6904 6224 5551 5310 5269>,
+ <7684 6923 6224 5553 5310 5270>,
+ <7689 6920 6233 5556 5310 5270>,
+ <7718 6926 6243 5556 5310 5270>,
+ <7735 6923 6251 5558 5311 5270>,
+ <7724 6942 6247 5561 5314 5272>,
+ <7721 6975 6265 5570 5317 5275>,
+ <7736 7003 6293 5585 5324 5280>,
+ <7777 7007 6312 5604 5331 5286>,
+ <7862 7038 6346 5623 5340 5292>,
+ <7862 7038 6346 5623 5340 5292>,
+ <7862 7038 6346 5623 5340 5292>;
+ };
+
+ qcom,pc-temp-y2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <9686 10401 10680 11050 11104 11401>,
+ <9784 10367 10651 11029 11106 11345>,
+ <9844 10346 10618 11003 11105 11260>,
+ <9875 10335 10585 10974 11102 11170>,
+ <9887 10331 10557 10941 11096 11098>,
+ <9890 10330 10539 10906 11089 11068>,
+ <9836 10343 10530 10861 11080 11075>,
+ <9739 10365 10523 10815 11067 11086>,
+ <9714 10360 10518 10793 11048 11085>,
+ <9726 10302 10514 10780 11017 11066>,
+ <9749 10260 10512 10771 10981 11044>,
+ <9880 10338 10522 10756 10934 11003>,
+ <10116 10474 10547 10736 10885 10947>,
+ <10170 10505 10586 10738 10874 10940>,
+ <9944 10486 10664 10781 10896 10992>,
+ <9729 10473 10720 10835 10928 11033>,
+ <9701 10495 10746 10897 10988 11035>,
+ <9694 10532 10766 10960 11059 11032>,
+ <9688 10541 10781 10991 11079 11043>,
+ <9682 10540 10795 11004 11080 11097>,
+ <9677 10537 10806 11018 11082 11163>,
+ <9674 10483 10815 11049 11128 11225>,
+ <9672 10313 10824 11092 11200 11283>,
+ <9670 10193 10827 11124 11234 11325>,
+ <9667 10079 10832 11151 11254 11356>,
+ <9664 10012 10836 11169 11271 11377>,
+ <9663 9998 10834 11180 11289 11395>,
+ <9662 9984 10826 11184 11309 11414>,
+ <9661 9965 10822 11175 11317 11445>,
+ <9660 9940 10820 11150 11329 11500>,
+ <9659 9913 10815 11136 11341 11537>,
+ <9659 9889 10729 11139 11328 11522>,
+ <9658 9867 10574 11151 11311 11482>,
+ <9657 9842 10507 11164 11315 11466>,
+ <9656 9813 10490 11161 11321 11473>,
+ <9656 9786 10478 11140 11317 11478>,
+ <9655 9762 10470 11112 11316 11484>,
+ <9655 9732 10507 11097 11321 11496>,
+ <9654 9708 10556 11103 11323 11495>,
+ <9654 9694 10525 11104 11318 11473>,
+ <9654 9684 10426 11103 11314 11461>,
+ <9654 9675 10396 11106 11316 11468>,
+ <9654 9668 10406 11101 11314 11471>,
+ <9653 9662 10267 11078 11283 11464>,
+ <9653 9659 10199 11060 11283 11440>,
+ <9653 9659 10180 11025 11296 11394>,
+ <9653 9658 10256 11021 11274 11345>,
+ <9653 9657 10321 11043 11240 11336>,
+ <9653 9656 10323 11048 11247 11344>,
+ <9652 9656 10295 10982 11294 11322>,
+ <9652 9654 10240 10956 11255 11261>,
+ <9652 9653 10172 10913 11134 11175>,
+ <9652 9652 10118 10825 11023 11061>,
+ <9650 9652 10099 10780 10831 10826>,
+ <9650 9652 10099 10780 10831 10826>,
+ <9650 9652 10099 10780 10831 10826>;
+ };
+
+ qcom,pc-temp-y3-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <13434 13398 13345 13285 13280 13272>,
+ <13675 13407 13338 13284 13280 13274>,
+ <13823 13420 13334 13283 13280 13275>,
+ <13901 13433 13334 13283 13280 13277>,
+ <13931 13444 13336 13283 13280 13278>,
+ <13936 13449 13340 13285 13280 13278>,
+ <13804 13449 13347 13288 13280 13278>,
+ <13564 13448 13355 13293 13281 13278>,
+ <13499 13451 13358 13295 13281 13278>,
+ <13498 13470 13359 13296 13281 13277>,
+ <13499 13484 13360 13296 13281 13277>,
+ <13523 13470 13373 13303 13284 13279>,
+ <13572 13441 13392 13313 13289 13282>,
+ <13584 13425 13393 13314 13290 13283>,
+ <13548 13416 13371 13310 13288 13282>,
+ <13516 13410 13351 13307 13286 13282>,
+ <13520 13407 13346 13309 13288 13282>,
+ <13536 13405 13343 13313 13292 13283>,
+ <13543 13402 13339 13313 13292 13283>,
+ <13545 13397 13334 13305 13287 13280>,
+ <13546 13391 13329 13296 13283 13277>,
+ <13548 13381 13324 13288 13281 13276>,
+ <13552 13365 13319 13283 13280 13275>,
+ <13557 13351 13318 13282 13279 13275>,
+ <13568 13340 13317 13283 13278 13275>,
+ <13586 13335 13317 13284 13278 13274>,
+ <13605 13336 13317 13283 13278 13274>,
+ <13625 13339 13317 13283 13277 13274>,
+ <13647 13343 13317 13285 13277 13274>,
+ <13675 13347 13317 13289 13277 13273>,
+ <13709 13352 13317 13292 13277 13273>,
+ <13746 13357 13312 13293 13278 13273>,
+ <13786 13364 13305 13292 13278 13274>,
+ <13834 13372 13302 13292 13279 13274>,
+ <13889 13385 13303 13290 13278 13274>,
+ <13952 13400 13304 13288 13278 13273>,
+ <14017 13416 13307 13286 13278 13273>,
+ <14082 13434 13314 13284 13277 13273>,
+ <14146 13456 13320 13283 13277 13273>,
+ <14209 13488 13324 13283 13277 13273>,
+ <14273 13532 13327 13283 13277 13273>,
+ <14339 13585 13333 13283 13278 13274>,
+ <14405 13648 13342 13283 13278 13274>,
+ <14482 13731 13345 13284 13278 13274>,
+ <14570 13843 13353 13283 13278 13274>,
+ <14605 13890 13360 13291 13279 13276>,
+ <14655 13886 13365 13292 13281 13277>,
+ <14684 13912 13378 13296 13283 13280>,
+ <14733 14009 13393 13298 13282 13280>,
+ <14859 14104 13394 13294 13281 13277>,
+ <14999 14246 13402 13296 13280 13277>,
+ <15153 14472 13423 13301 13283 13281>,
+ <15376 14712 13458 13305 13286 13284>,
+ <16172 14971 13514 13315 13290 13286>,
+ <16172 14971 13514 13315 13290 13286>,
+ <16172 14971 13514 13315 13290 13286>;
+ };
+
+ qcom,pc-temp-y4-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <17845 16850 16626 16493 16453 16452>,
+ <17707 16859 16623 16499 16453 16450>,
+ <17643 16875 16623 16504 16455 16449>,
+ <17641 16896 16626 16507 16456 16448>,
+ <17685 16923 16631 16509 16458 16448>,
+ <17761 16953 16638 16510 16459 16448>,
+ <17959 16995 16646 16508 16461 16449>,
+ <18315 17038 16657 16506 16462 16452>,
+ <18708 17060 16668 16506 16465 16454>,
+ <19236 17069 16679 16513 16469 16457>,
+ <19572 17084 16696 16524 16475 16461>,
+ <19006 17415 16799 16542 16489 16473>,
+ <17760 17958 16951 16564 16509 16488>,
+ <17274 17986 16977 16573 16513 16492>,
+ <17223 17320 16899 16575 16509 16491>,
+ <17197 16817 16810 16579 16507 16490>,
+ <17184 16821 16750 16620 16529 16506>,
+ <17165 16866 16699 16681 16570 16536>,
+ <17135 16877 16663 16682 16576 16541>,
+ <17076 16837 16634 16593 16532 16509>,
+ <17012 16792 16611 16517 16486 16475>,
+ <16969 16768 16596 16504 16468 16461>,
+ <16936 16750 16584 16498 16457 16451>,
+ <16927 16747 16578 16495 16456 16450>,
+ <16931 16735 16574 16491 16456 16450>,
+ <16939 16719 16571 16489 16457 16451>,
+ <16945 16707 16570 16491 16459 16453>,
+ <16955 16695 16570 16493 16462 16456>,
+ <16966 16694 16569 16494 16465 16460>,
+ <16978 16706 16564 16496 16471 16465>,
+ <16990 16724 16560 16498 16478 16472>,
+ <17002 16743 16564 16500 16488 16483>,
+ <17014 16767 16573 16502 16499 16496>,
+ <17027 16792 16580 16500 16501 16498>,
+ <17040 16818 16585 16489 16484 16481>,
+ <17052 16845 16589 16478 16463 16460>,
+ <17064 16879 16594 16475 16452 16451>,
+ <17077 16927 16600 16473 16446 16447>,
+ <17095 16964 16604 16474 16446 16448>,
+ <17121 16978 16617 16477 16450 16453>,
+ <17160 16988 16637 16480 16455 16458>,
+ <17211 16994 16652 16483 16456 16459>,
+ <17278 17008 16664 16484 16454 16456>,
+ <17363 17031 16681 16481 16445 16443>,
+ <17450 17090 16711 16491 16449 16446>,
+ <17435 17135 16736 16501 16471 16474>,
+ <17438 17159 16742 16516 16496 16504>,
+ <17389 17194 16787 16546 16537 16546>,
+ <17360 17262 16870 16574 16540 16536>,
+ <17381 17283 16862 16542 16494 16484>,
+ <17398 17284 16856 16542 16480 16473>,
+ <17425 17312 16891 16573 16496 16487>,
+ <17507 17393 16998 16635 16528 16517>,
+ <18186 17570 17197 16862 16705 16664>,
+ <18186 17570 17197 16862 16705 16664>,
+ <18186 17570 17197 16862 16705 16664>;
+ };
+
+ qcom,pc-temp-y5-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <8712 13450 15024 13637 17779 13876>,
+ <8712 13482 14393 13094 17299 16002>,
+ <9887 13538 13920 12763 16795 17370>,
+ <12171 13602 13593 12592 16319 18144>,
+ <13352 13655 13402 12528 15924 18488>,
+ <13712 13682 13338 12519 15663 18564>,
+ <12526 13686 13491 13011 15524 18119>,
+ <10345 13688 13732 13797 15423 17285>,
+ <9855 13494 13762 13896 15233 16665>,
+ <10836 12338 13637 13520 14742 16018>,
+ <12278 11512 13460 13263 14463 15589>,
+ <14305 12246 13117 13605 14692 15613>,
+ <16658 13838 12700 14184 15051 15805>,
+ <17024 14948 12908 14300 15117 15807>,
+ <14139 15828 14686 14149 14970 15538>,
+ <11513 16242 16074 14033 14913 15280>,
+ <11523 16069 16259 14411 15080 15197>,
+ <11996 15810 16323 15261 15416 15147>,
+ <12172 15770 16274 15815 15959 15251>,
+ <12062 15859 16079 16180 16933 16031>,
+ <11868 15956 15846 16328 17499 16947>,
+ <11620 15469 15368 15383 17703 17632>,
+ <11312 13975 14705 13688 17924 18203>,
+ <11115 12872 14496 13266 17959 18431>,
+ <11014 12058 14552 13626 17682 18509>,
+ <10964 11631 14629 13920 17362 18511>,
+ <10973 11596 14709 13944 17173 18320>,
+ <10988 11605 14796 13932 17044 17852>,
+ <10995 11588 14900 14573 17019 17407>,
+ <11030 11538 15113 16622 17008 17007>,
+ <11086 11527 15270 18010 17024 16810>,
+ <11136 11527 14539 18405 17391 17083>,
+ <11177 11500 13186 18651 18220 17910>,
+ <11216 11497 12702 18616 19096 18783>,
+ <11256 11585 12708 17851 20108 19561>,
+ <11296 11690 12725 16773 20954 20137>,
+ <11333 11737 12833 15892 21243 20622>,
+ <11364 11658 13487 15086 21079 21066>,
+ <11372 11570 14099 14616 20668 21138>,
+ <11354 11602 14046 14527 20112 20711>,
+ <11333 11673 13559 14611 19900 20367>,
+ <11347 11689 13647 14598 20136 20790>,
+ <11447 11633 14091 14488 20830 22215>,
+ <11628 11564 13261 14690 21851 23634>,
+ <11886 11464 12890 13840 19650 20132>,
+ <12228 11536 12810 15945 17300 17267>,
+ <12464 11547 13361 15880 17100 16566>,
+ <12844 11910 14094 16530 16574 16161>,
+ <12886 12441 14613 16353 15911 15963>,
+ <12844 12583 14513 15967 17037 16654>,
+ <12567 12345 14561 17027 17428 17457>,
+ <12151 12056 14328 17704 18241 18950>,
+ <11887 11870 14282 17302 18299 19121>,
+ <11109 11677 14642 17219 17830 18283>,
+ <11109 11677 14642 17219 17830 18283>,
+ <11109 11677 14642 17219 17830 18283>;
+ };
+
+ qcom,pc-temp-y6-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <6900 5639 5266 5065 5021 5010>,
+ <6907 5646 5261 5064 5021 5011>,
+ <6911 5654 5258 5063 5021 5012>,
+ <6911 5662 5258 5064 5021 5013>,
+ <6908 5670 5260 5065 5022 5013>,
+ <6903 5678 5262 5066 5023 5014>,
+ <6855 5686 5268 5068 5023 5015>,
+ <6776 5694 5276 5071 5025 5015>,
+ <6772 5702 5281 5074 5026 5016>,
+ <6911 5708 5283 5076 5027 5017>,
+ <7024 5719 5288 5079 5029 5018>,
+ <6900 5804 5324 5090 5036 5023>,
+ <6611 5932 5379 5103 5045 5030>,
+ <6465 5932 5387 5106 5047 5032>,
+ <6414 5744 5349 5105 5045 5031>,
+ <6390 5602 5310 5104 5043 5031>,
+ <6395 5604 5291 5117 5051 5036>,
+ <6409 5621 5276 5138 5065 5045>,
+ <6413 5625 5263 5138 5067 5047>,
+ <6412 5613 5251 5107 5051 5035>,
+ <6410 5600 5242 5078 5035 5023>,
+ <6413 5590 5235 5069 5028 5018>,
+ <6426 5582 5230 5064 5025 5015>,
+ <6444 5577 5229 5063 5024 5015>,
+ <6469 5575 5230 5063 5024 5015>,
+ <6500 5574 5231 5064 5024 5016>,
+ <6530 5579 5232 5065 5025 5016>,
+ <6560 5589 5235 5066 5026 5017>,
+ <6592 5602 5237 5068 5027 5018>,
+ <6630 5619 5238 5072 5029 5020>,
+ <6673 5639 5239 5076 5031 5022>,
+ <6719 5661 5240 5078 5035 5026>,
+ <6770 5688 5241 5079 5039 5030>,
+ <6823 5717 5243 5078 5040 5031>,
+ <6880 5750 5247 5074 5035 5026>,
+ <6940 5787 5251 5070 5029 5020>,
+ <7001 5830 5256 5068 5026 5018>,
+ <7062 5880 5264 5067 5024 5016>,
+ <7124 5938 5274 5066 5024 5017>,
+ <7187 6002 5285 5067 5025 5018>,
+ <7249 6076 5296 5069 5027 5020>,
+ <7312 6161 5311 5070 5028 5021>,
+ <7379 6261 5328 5071 5027 5020>,
+ <7458 6383 5344 5072 5025 5017>,
+ <7552 6532 5369 5074 5027 5018>,
+ <7589 6585 5388 5083 5033 5027>,
+ <7631 6596 5395 5089 5042 5037>,
+ <7646 6631 5423 5100 5055 5051>,
+ <7684 6743 5466 5110 5056 5048>,
+ <7789 6847 5472 5099 5042 5031>,
+ <7903 6977 5491 5102 5038 5029>,
+ <8038 7181 5547 5117 5046 5036>,
+ <8244 7391 5646 5141 5058 5047>,
+ <9160 7653 5795 5217 5112 5092>,
+ <9160 7653 5795 5217 5112 5092>,
+ <9160 7653 5795 5217 5112 5092>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-ascent-3450mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-ascent-3450mah.dtsi
new file mode 100755
index 0000000..ee06816
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-ascent-3450mah.dtsi
@@ -0,0 +1,1031 @@
+qcom,ascent_3450mah {
+ /* Ascent_wConn_3450mAh_Fresh_averaged_MasterSlave_Feb7th2018 */
+ qcom,max-voltage-uv = <4350000>;
+ qcom,fg-cc-cv-threshold-mv = <4340>;
+ qcom,fastchg-current-ma = <3450>;
+ qcom,batt-id-kohm = <60>;
+ qcom,battery-beta = <3435>;
+ qcom,battery-therm-kohm = <68>;
+ qcom,battery-type =
+ "Ascent_wConn_3450mAh_Fresh_averaged_MasterSlave_Feb7th2018";
+ qcom,qg-batt-profile-ver = <100>;
+
+ qcom,jeita-fcc-ranges = <0 100 1725000
+ 101 400 3450000
+ 401 450 2760000>;
+ qcom,jeita-fv-ranges = <0 100 4250000
+ 101 400 4350000
+ 401 450 4250000>;
+ qcom,step-chg-ranges = <3600000 4200000 3450000
+ 4201000 4300000 2760000
+ 4301000 4350000 2070000>;
+
+ /* COOL = 5 DegC, WARM = 40 DegC */
+ qcom,jeita-soft-thresholds = <0x44bd 0x1fc4>;
+ /* COLD = 0 DegC, HOT = 45 DegC */
+ qcom,jeita-hard-thresholds = <0x4aa5 0x1bfb>;
+
+ qcom,fcc1-temp-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-data = <3377 3428 3481 3496 3500>;
+ };
+
+ qcom,fcc2-temp-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-data = <3480 3482 3476 3492 3478 3466>;
+ };
+
+ qcom,pc-temp-v1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <43212 43315 43370 43380 43383>,
+ <42963 43071 43141 43149 43152>,
+ <42723 42832 42902 42916 42922>,
+ <42488 42597 42662 42683 42693>,
+ <42262 42367 42430 42454 42465>,
+ <42043 42143 42202 42225 42238>,
+ <41832 41924 41976 41999 42013>,
+ <41624 41709 41754 41775 41791>,
+ <41419 41497 41536 41556 41571>,
+ <41220 41288 41322 41341 41355>,
+ <41039 41091 41113 41132 41143>,
+ <40866 40911 40916 40928 40936>,
+ <40676 40732 40729 40729 40734>,
+ <40449 40526 40541 40538 40541>,
+ <40230 40302 40340 40351 40355>,
+ <40061 40115 40146 40170 40176>,
+ <39918 39974 39984 40002 40007>,
+ <39787 39846 39843 39845 39846>,
+ <39672 39712 39697 39690 39689>,
+ <39560 39579 39548 39536 39538>,
+ <39426 39419 39388 39376 39384>,
+ <39271 39170 39192 39187 39198>,
+ <39112 38928 38961 38960 38967>,
+ <38934 38809 38788 38776 38775>,
+ <38764 38736 38674 38650 38646>,
+ <38660 38665 38581 38546 38539>,
+ <38589 38587 38491 38448 38439>,
+ <38533 38513 38408 38359 38347>,
+ <38487 38444 38334 38278 38263>,
+ <38448 38381 38265 38204 38187>,
+ <38407 38323 38204 38138 38118>,
+ <38364 38269 38149 38078 38055>,
+ <38322 38219 38099 38026 37999>,
+ <38284 38175 38053 37975 37942>,
+ <38249 38137 38014 37930 37889>,
+ <38211 38098 37974 37884 37834>,
+ <38174 38061 37930 37831 37767>,
+ <38129 38020 37882 37771 37691>,
+ <38055 37954 37816 37698 37610>,
+ <37946 37848 37718 37605 37524>,
+ <37825 37726 37602 37497 37426>,
+ <37689 37595 37474 37372 37301>,
+ <37541 37451 37332 37231 37156>,
+ <37372 37290 37178 37080 36999>,
+ <37271 37162 37061 36964 36886>,
+ <37191 37093 36992 36897 36819>,
+ <37157 37064 36970 36870 36798>,
+ <37128 37039 36949 36844 36770>,
+ <37084 37007 36903 36788 36714>,
+ <36927 36851 36683 36562 36488>,
+ <36555 36481 36290 36180 36108>,
+ <36071 35999 35771 35687 35620>,
+ <35450 35376 35098 35050 34994>,
+ <34604 34523 34174 34184 34150>,
+ <33275 33138 32725 32851 32862>,
+ <30000 30000 30000 30000 30000>;
+ };
+
+ qcom,pc-temp-v2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <43425 43415 43385 43360 43315 43295>,
+ <43070 43109 43097 43094 43052 43033>,
+ <42748 42821 42826 42838 42799 42781>,
+ <42462 42555 42571 42594 42557 42541>,
+ <42208 42308 42333 42361 42326 42312>,
+ <41968 42072 42101 42133 42099 42086>,
+ <41736 41844 41872 41904 41872 41860>,
+ <41516 41625 41649 41680 41649 41637>,
+ <41303 41405 41431 41460 41430 41419>,
+ <41100 41186 41217 41243 41215 41204>,
+ <40896 40979 41012 41034 41005 40994>,
+ <40694 40796 40826 40840 40802 40789>,
+ <40482 40616 40642 40648 40604 40590>,
+ <40220 40407 40432 40445 40411 40399>,
+ <39903 40175 40199 40233 40222 40214>,
+ <39636 39954 39996 40043 40042 40036>,
+ <39443 39759 39844 39886 39877 39868>,
+ <39272 39570 39700 39736 39717 39706>,
+ <39091 39370 39511 39573 39556 39547>,
+ <38908 39162 39283 39399 39396 39391>,
+ <38742 38973 39072 39208 39217 39217>,
+ <38591 38806 38886 38975 38988 38994>,
+ <38460 38655 38721 38760 38766 38771>,
+ <38358 38519 38585 38613 38613 38614>,
+ <38274 38396 38468 38496 38494 38494>,
+ <38201 38287 38362 38390 38388 38387>,
+ <38138 38189 38265 38294 38291 38288>,
+ <38080 38106 38177 38206 38202 38198>,
+ <38027 38039 38096 38126 38120 38114>,
+ <37980 37983 38021 38051 38044 38037>,
+ <37934 37935 37954 37984 37976 37967>,
+ <37889 37895 37891 37921 37915 37905>,
+ <37843 37856 37838 37862 37856 37846>,
+ <37795 37815 37799 37803 37790 37781>,
+ <37746 37774 37768 37746 37720 37707>,
+ <37692 37727 37728 37685 37643 37621>,
+ <37633 37677 37677 37620 37554 37517>,
+ <37568 37618 37617 37550 37465 37411>,
+ <37491 37546 37548 37475 37387 37327>,
+ <37404 37459 37466 37395 37313 37256>,
+ <37310 37360 37369 37301 37226 37174>,
+ <37206 37243 37246 37187 37117 37069>,
+ <37103 37111 37106 37050 36988 36945>,
+ <37005 36964 36946 36900 36839 36796>,
+ <36909 36860 36837 36818 36761 36712>,
+ <36808 36782 36769 36775 36718 36673>,
+ <36746 36740 36732 36741 36690 36651>,
+ <36670 36688 36684 36692 36649 36612>,
+ <36553 36594 36591 36575 36542 36528>,
+ <36329 36380 36368 36272 36271 36278>,
+ <35961 35991 35957 35796 35833 35867>,
+ <35436 35452 35401 35193 35271 35340>,
+ <34709 34745 34680 34409 34550 34676>,
+ <33672 33759 33677 33330 33585 33791>,
+ <31857 32191 32244 31867 32001 32517>,
+ <28160 28896 29014 27510 28586 29617>;
+ };
+
+ qcom,pc-temp-z1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <13703 12983 12375 12138 12079>,
+ <13647 12967 12370 12145 12092>,
+ <13621 12953 12363 12143 12093>,
+ <13606 12942 12357 12142 12093>,
+ <13594 12927 12349 12140 12093>,
+ <13585 12916 12342 12137 12093>,
+ <13577 12905 12339 12136 12092>,
+ <13569 12898 12337 12135 12092>,
+ <13560 12896 12337 12135 12091>,
+ <13551 12895 12339 12135 12091>,
+ <13540 12896 12342 12136 12091>,
+ <13527 12899 12342 12136 12091>,
+ <13512 12901 12342 12137 12093>,
+ <13488 12896 12342 12139 12095>,
+ <13469 12887 12343 12141 12097>,
+ <13469 12883 12347 12144 12098>,
+ <13473 12891 12352 12147 12101>,
+ <13478 12904 12360 12151 12103>,
+ <13489 12912 12369 12155 12106>,
+ <13502 12919 12378 12160 12109>,
+ <13514 12927 12387 12165 12113>,
+ <13525 12937 12396 12171 12117>,
+ <13538 12948 12404 12177 12122>,
+ <13555 12957 12412 12184 12127>,
+ <13572 12965 12422 12189 12131>,
+ <13578 12971 12431 12195 12135>,
+ <13580 12978 12440 12200 12139>,
+ <13582 12985 12448 12206 12143>,
+ <13594 12992 12456 12212 12147>,
+ <13613 13004 12464 12218 12151>,
+ <13625 13010 12472 12224 12156>,
+ <13631 13010 12479 12230 12160>,
+ <13632 13010 12486 12237 12165>,
+ <13627 13015 12494 12244 12171>,
+ <13618 13033 12505 12253 12177>,
+ <13619 13047 12517 12262 12183>,
+ <13629 13056 12529 12271 12190>,
+ <13640 13065 12541 12280 12196>,
+ <13647 13068 12553 12290 12203>,
+ <13654 13070 12565 12301 12210>,
+ <13663 13071 12577 12311 12217>,
+ <13678 13085 12588 12322 12224>,
+ <13694 13098 12598 12332 12232>,
+ <13718 13107 12607 12344 12239>,
+ <13717 13110 12621 12356 12248>,
+ <13717 13111 12638 12367 12256>,
+ <13693 13110 12640 12374 12262>,
+ <13712 13131 12642 12382 12269>,
+ <13714 13118 12659 12395 12280>,
+ <13717 13140 12677 12408 12291>,
+ <13717 13160 12678 12422 12303>,
+ <13740 13166 12691 12436 12316>,
+ <13739 13183 12711 12456 12332>,
+ <13754 13201 12735 12479 12355>,
+ <13754 13201 12735 12479 12355>,
+ <13754 13201 12735 12479 12355>;
+ };
+
+ qcom,pc-temp-z2-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <9983 10351 10639 10481 10418>,
+ <10020 10341 10669 10329 10279>,
+ <10051 10333 10528 10319 10282>,
+ <10083 10331 10397 10312 10281>,
+ <10100 10329 10358 10299 10263>,
+ <10094 10325 10328 10285 10234>,
+ <10081 10303 10324 10279 10227>,
+ <10069 10281 10328 10277 10237>,
+ <10058 10278 10330 10276 10251>,
+ <10050 10280 10326 10276 10266>,
+ <10044 10285 10321 10281 10280>,
+ <10039 10298 10323 10288 10285>,
+ <10038 10310 10324 10308 10284>,
+ <10045 10309 10318 10321 10285>,
+ <10054 10304 10304 10319 10295>,
+ <10056 10302 10291 10314 10309>,
+ <10056 10312 10297 10316 10321>,
+ <10058 10329 10320 10326 10335>,
+ <10070 10353 10339 10334 10341>,
+ <10090 10386 10349 10339 10346>,
+ <10111 10400 10358 10343 10354>,
+ <10138 10396 10373 10334 10340>,
+ <10157 10388 10395 10289 10270>,
+ <10169 10381 10400 10243 10212>,
+ <10178 10372 10354 10197 10174>,
+ <10183 10364 10306 10161 10144>,
+ <10190 10352 10304 10160 10141>,
+ <10194 10341 10307 10170 10149>,
+ <10185 10335 10310 10181 10158>,
+ <10169 10332 10311 10196 10169>,
+ <10165 10332 10314 10216 10183>,
+ <10168 10343 10327 10238 10202>,
+ <10171 10357 10356 10267 10226>,
+ <10175 10368 10381 10298 10253>,
+ <10180 10376 10405 10333 10288>,
+ <10183 10384 10422 10367 10326>,
+ <10186 10393 10431 10393 10358>,
+ <10189 10403 10438 10416 10387>,
+ <10187 10410 10442 10437 10405>,
+ <10181 10419 10455 10461 10418>,
+ <10175 10423 10465 10476 10426>,
+ <10164 10407 10466 10476 10430>,
+ <10152 10385 10468 10474 10428>,
+ <10142 10373 10453 10473 10402>,
+ <10064 10371 10455 10479 10389>,
+ <10173 10285 10486 10517 10402>,
+ <10003 10290 10490 10530 10416>,
+ <10151 10295 10531 10566 10477>,
+ <10255 10515 10588 10612 10540>,
+ <10077 10376 10556 10524 10421>,
+ <9948 10240 10480 10454 10314>,
+ <9854 10122 10384 10398 10256>,
+ <9640 9998 10319 10342 10182>,
+ <9440 9830 10255 10261 10065>,
+ <9440 9830 10255 10261 10065>,
+ <9440 9830 10255 10261 10065>;
+ };
+
+ qcom,pc-temp-z3-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <19441 19367 19362 19326 19316>,
+ <19560 19428 19358 19334 19329>,
+ <19615 19467 19373 19341 19335>,
+ <19645 19480 19383 19346 19340>,
+ <19658 19487 19385 19351 19344>,
+ <19657 19488 19387 19354 19347>,
+ <19657 19486 19386 19355 19348>,
+ <19655 19483 19384 19354 19347>,
+ <19651 19481 19382 19352 19346>,
+ <19647 19479 19380 19350 19345>,
+ <19645 19477 19378 19347 19344>,
+ <19642 19470 19377 19345 19342>,
+ <19642 19464 19374 19345 19342>,
+ <19642 19464 19372 19344 19341>,
+ <19643 19467 19372 19343 19338>,
+ <19639 19467 19372 19342 19336>,
+ <19626 19460 19371 19340 19334>,
+ <19615 19450 19369 19338 19332>,
+ <19604 19448 19368 19337 19330>,
+ <19596 19446 19368 19337 19328>,
+ <19597 19447 19369 19337 19326>,
+ <19605 19452 19372 19340 19328>,
+ <19612 19460 19378 19350 19341>,
+ <19619 19462 19386 19357 19350>,
+ <19626 19464 19394 19361 19353>,
+ <19627 19466 19401 19364 19355>,
+ <19626 19472 19400 19364 19355>,
+ <19624 19480 19398 19362 19352>,
+ <19620 19480 19395 19359 19349>,
+ <19615 19476 19391 19356 19346>,
+ <19611 19473 19388 19353 19343>,
+ <19609 19469 19384 19350 19340>,
+ <19606 19466 19381 19347 19336>,
+ <19604 19463 19379 19343 19332>,
+ <19601 19461 19377 19338 19327>,
+ <19597 19458 19375 19335 19324>,
+ <19592 19454 19373 19334 19325>,
+ <19587 19451 19370 19334 19329>,
+ <19584 19448 19368 19334 19330>,
+ <19582 19446 19366 19334 19328>,
+ <19579 19443 19364 19334 19326>,
+ <19575 19441 19362 19334 19326>,
+ <19571 19438 19360 19334 19327>,
+ <19565 19434 19359 19336 19329>,
+ <19361 19423 19353 19335 19328>,
+ <19262 19382 19344 19323 19324>,
+ <19263 19371 19336 19321 19317>,
+ <19261 19361 19332 19317 19313>,
+ <19261 19273 19326 19317 19309>,
+ <19262 19274 19335 19327 19319>,
+ <19263 19303 19337 19330 19324>,
+ <19263 19274 19357 19333 19327>,
+ <19266 19275 19361 19337 19335>,
+ <19272 19280 19368 19349 19345>,
+ <19272 19280 19368 19349 19345>,
+ <19272 19280 19368 19349 19345>;
+ };
+
+ qcom,pc-temp-z4-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <15627 15107 14765 14761 14758>,
+ <15711 15099 14864 14812 14796>,
+ <15693 15080 14843 14798 14788>,
+ <15530 15036 14821 14778 14775>,
+ <15355 14952 14794 14760 14761>,
+ <15246 14887 14764 14740 14745>,
+ <15155 14845 14741 14726 14731>,
+ <15085 14812 14721 14713 14719>,
+ <15031 14784 14710 14705 14711>,
+ <14985 14760 14705 14700 14707>,
+ <14938 14745 14702 14697 14705>,
+ <14895 14735 14696 14693 14702>,
+ <14876 14729 14689 14688 14699>,
+ <14872 14730 14686 14684 14697>,
+ <14869 14735 14686 14681 14694>,
+ <14856 14737 14686 14680 14692>,
+ <14830 14720 14682 14677 14689>,
+ <14808 14702 14673 14672 14684>,
+ <14790 14701 14669 14669 14681>,
+ <14778 14706 14676 14670 14679>,
+ <14782 14717 14687 14675 14677>,
+ <14805 14815 14716 14690 14685>,
+ <14835 14927 14778 14733 14726>,
+ <14898 14927 14803 14755 14750>,
+ <14965 14883 14774 14738 14735>,
+ <14974 14842 14741 14715 14712>,
+ <14963 14813 14728 14705 14703>,
+ <14950 14789 14721 14700 14699>,
+ <14932 14778 14717 14696 14696>,
+ <14910 14771 14715 14693 14692>,
+ <14892 14767 14713 14691 14688>,
+ <14878 14766 14712 14688 14683>,
+ <14867 14765 14712 14684 14677>,
+ <14856 14764 14710 14681 14673>,
+ <14847 14763 14709 14676 14668>,
+ <14838 14761 14706 14673 14666>,
+ <14826 14756 14703 14673 14669>,
+ <14816 14748 14700 14674 14680>,
+ <14809 14744 14697 14674 14683>,
+ <14804 14742 14695 14673 14677>,
+ <14797 14739 14693 14671 14673>,
+ <14787 14730 14687 14667 14673>,
+ <14774 14718 14678 14663 14675>,
+ <14753 14708 14673 14662 14682>,
+ <14897 14683 14660 14653 14674>,
+ <14965 14689 14638 14630 14635>,
+ <14964 14694 14635 14621 14624>,
+ <14958 14699 14630 14614 14617>,
+ <14951 14794 14633 14616 14620>,
+ <14945 14795 14637 14644 14655>,
+ <14957 14769 14642 14654 14664>,
+ <14968 14805 14636 14660 14668>,
+ <14977 14809 14655 14668 14668>,
+ <14993 14817 14684 14674 14665>,
+ <14993 14817 14684 14674 14665>,
+ <14993 14817 14684 14674 14665>;
+ };
+
+ qcom,pc-temp-z5-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <11983 12740 15393 15537 15330>,
+ <13357 14824 16249 17310 17529>,
+ <14286 16482 17811 18377 18523>,
+ <14945 17642 19175 19223 19510>,
+ <15486 18555 20024 20275 20513>,
+ <15957 19327 20723 21346 21540>,
+ <16368 19918 21568 22345 22519>,
+ <16781 20541 22514 23454 23469>,
+ <17187 21683 23120 24074 24236>,
+ <17674 23224 23449 23971 24698>,
+ <18442 24060 23713 23757 25052>,
+ <19483 24549 23914 23816 25554>,
+ <20437 24925 24207 24637 26312>,
+ <21361 25257 24451 25542 26851>,
+ <22105 25909 24697 26092 27021>,
+ <22478 26475 25087 26614 27131>,
+ <22735 27141 26348 27394 27470>,
+ <23076 28081 28954 28566 28331>,
+ <23809 29715 30229 29356 28825>,
+ <24938 32251 30431 29724 28646>,
+ <27176 33544 30446 29885 28135>,
+ <31932 33025 28578 28445 26783>,
+ <35226 31860 23567 23249 22747>,
+ <36819 29994 21621 20580 20432>,
+ <37874 26035 23092 21806 21763>,
+ <37147 24128 25214 23841 23948>,
+ <34993 26078 27156 25488 25430>,
+ <32825 29127 29386 27105 26647>,
+ <30980 31187 31134 28441 27481>,
+ <29376 32887 32400 29515 28206>,
+ <28873 34208 33430 30375 28775>,
+ <28786 35400 34311 31101 29161>,
+ <28801 36250 35051 31824 29873>,
+ <28836 36325 35497 32045 30283>,
+ <28862 36122 35938 31861 30590>,
+ <28907 35854 36221 31646 31106>,
+ <28980 35186 35497 31570 32686>,
+ <29132 34291 33694 31549 35494>,
+ <29670 33796 32315 31543 36261>,
+ <30652 33516 31332 31469 34185>,
+ <30992 33114 30388 31412 32325>,
+ <29938 32130 29262 32046 32870>,
+ <29033 30867 28327 33225 34089>,
+ <28928 29512 27958 34867 35083>,
+ <16971 28826 27177 35407 35456>,
+ <11113 18542 25875 28236 38118>,
+ <11084 16735 22486 31621 32274>,
+ <11037 15601 21798 36765 39261>,
+ <11035 11499 20071 40032 37713>,
+ <11055 11574 22201 35765 26327>,
+ <11017 12415 21829 29484 22484>,
+ <10951 11419 39496 26044 20817>,
+ <10890 11348 40899 24307 20580>,
+ <10822 11392 37952 25288 21070>,
+ <10822 11392 37952 25288 21070>,
+ <10822 11392 37952 25288 21070>;
+ };
+
+ qcom,pc-temp-z6-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <15711 15103 14773 14710 14694>,
+ <15778 15117 14813 14736 14718>,
+ <15776 15120 14809 14733 14717>,
+ <15702 15106 14804 14728 14716>,
+ <15620 15065 14793 14722 14713>,
+ <15561 15031 14779 14715 14707>,
+ <15508 15007 14768 14709 14701>,
+ <15467 14987 14758 14703 14696>,
+ <15435 14971 14751 14698 14692>,
+ <15407 14959 14748 14695 14689>,
+ <15379 14949 14746 14692 14687>,
+ <15353 14940 14743 14689 14685>,
+ <15339 14935 14739 14687 14684>,
+ <15332 14935 14736 14685 14682>,
+ <15326 14938 14737 14684 14680>,
+ <15316 14939 14738 14683 14678>,
+ <15302 14930 14736 14681 14676>,
+ <15293 14921 14733 14679 14673>,
+ <15289 14921 14732 14677 14671>,
+ <15286 14926 14736 14678 14670>,
+ <15291 14936 14744 14682 14669>,
+ <15312 14986 14761 14691 14674>,
+ <15338 15040 14795 14718 14702>,
+ <15373 15042 14808 14732 14717>,
+ <15408 15027 14802 14727 14713>,
+ <15415 15016 14795 14720 14706>,
+ <15414 15011 14791 14717 14702>,
+ <15412 15007 14788 14714 14699>,
+ <15408 15006 14786 14712 14697>,
+ <15402 15004 14785 14710 14694>,
+ <15399 15004 14784 14708 14691>,
+ <15398 15005 14784 14706 14688>,
+ <15397 15006 14784 14704 14684>,
+ <15397 15009 14784 14701 14680>,
+ <15398 15012 14784 14699 14677>,
+ <15400 15015 14785 14696 14674>,
+ <15402 15016 14785 14697 14677>,
+ <15405 15017 14786 14699 14684>,
+ <15410 15020 14787 14700 14687>,
+ <15416 15026 14789 14702 14685>,
+ <15423 15031 14791 14703 14683>,
+ <15430 15034 14791 14703 14684>,
+ <15437 15037 14791 14704 14687>,
+ <15444 15040 14792 14706 14693>,
+ <15425 15039 14789 14704 14690>,
+ <15419 15030 14781 14691 14673>,
+ <15424 15030 14778 14688 14665>,
+ <15425 15032 14777 14685 14661>,
+ <15431 15036 14780 14688 14662>,
+ <15438 15047 14792 14708 14685>,
+ <15458 15060 14801 14718 14695>,
+ <15477 15072 14815 14726 14702>,
+ <15501 15088 14835 14737 14710>,
+ <15534 15114 14862 14753 14720>,
+ <15534 15114 14862 14753 14720>,
+ <15534 15114 14862 14753 14720>;
+ };
+
+ qcom,pc-temp-y1-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <6963 6363 6007 5630 5512 5470>,
+ <6945 6361 6003 5629 5510 5471>,
+ <6934 6357 5999 5628 5508 5471>,
+ <6929 6354 5995 5627 5506 5471>,
+ <6928 6353 5992 5626 5505 5470>,
+ <6928 6357 5988 5625 5503 5470>,
+ <6934 6366 5985 5624 5502 5469>,
+ <6942 6374 5981 5624 5501 5467>,
+ <6939 6374 5982 5623 5500 5467>,
+ <6920 6366 5984 5624 5499 5467>,
+ <6910 6360 5985 5624 5498 5466>,
+ <6919 6357 5980 5623 5498 5466>,
+ <6931 6356 5973 5622 5498 5465>,
+ <6935 6362 5973 5622 5499 5465>,
+ <6938 6380 5978 5625 5500 5466>,
+ <6939 6390 5981 5628 5501 5467>,
+ <6942 6389 5985 5631 5501 5468>,
+ <6946 6387 5990 5634 5502 5469>,
+ <6943 6388 5989 5637 5503 5470>,
+ <6932 6391 5988 5639 5506 5471>,
+ <6929 6394 5987 5643 5508 5472>,
+ <6957 6397 5989 5647 5510 5473>,
+ <6985 6400 5994 5653 5513 5475>,
+ <6976 6405 6001 5658 5515 5478>,
+ <6942 6414 6012 5663 5518 5480>,
+ <6928 6418 6018 5668 5522 5483>,
+ <6934 6419 6019 5674 5525 5486>,
+ <6942 6418 6020 5681 5529 5488>,
+ <6951 6418 6021 5687 5533 5491>,
+ <6972 6418 6023 5692 5537 5493>,
+ <6978 6418 6025 5698 5541 5497>,
+ <6971 6422 6028 5705 5545 5500>,
+ <6961 6425 6032 5712 5550 5504>,
+ <6947 6422 6038 5720 5554 5507>,
+ <6929 6416 6048 5727 5559 5509>,
+ <6925 6416 6055 5734 5563 5512>,
+ <6932 6428 6059 5741 5569 5516>,
+ <6939 6438 6062 5748 5575 5522>,
+ <6939 6433 6063 5757 5580 5526>,
+ <6942 6422 6064 5767 5585 5529>,
+ <6944 6417 6067 5775 5591 5533>,
+ <6946 6416 6077 5783 5596 5537>,
+ <6941 6418 6083 5787 5603 5541>,
+ <6923 6429 6090 5790 5610 5546>,
+ <6953 6428 6086 5808 5622 5555>,
+ <6932 6433 6091 5813 5631 5561>,
+ <6928 6433 6099 5818 5635 5565>,
+ <6933 6442 6113 5834 5640 5567>,
+ <6932 6430 6105 5835 5645 5571>,
+ <6936 6436 6106 5848 5654 5578>,
+ <6965 6440 6099 5858 5666 5585>,
+ <6990 6464 6110 5873 5684 5600>,
+ <7027 6445 6123 5887 5704 5613>,
+ <7064 6471 6136 5914 5726 5633>,
+ <7064 6471 6136 5914 5726 5633>,
+ <7064 6471 6136 5914 5726 5633>;
+ };
+
+ qcom,pc-temp-y2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <9643 10780 11037 11216 11097 11009>,
+ <9653 10747 10993 11177 11076 11016>,
+ <9867 10710 10945 11129 11053 11018>,
+ <10082 10673 10898 11080 11031 11018>,
+ <10246 10642 10860 11037 11010 11015>,
+ <10308 10624 10837 11007 10992 11010>,
+ <10281 10616 10826 10987 10977 10981>,
+ <10241 10610 10820 10968 10962 10937>,
+ <10275 10600 10816 10953 10942 10920>,
+ <10440 10586 10802 10939 10913 10908>,
+ <10531 10580 10792 10927 10894 10901>,
+ <10522 10610 10786 10915 10881 10897>,
+ <10502 10665 10780 10900 10869 10890>,
+ <10430 10721 10797 10878 10869 10877>,
+ <10226 10789 10873 10846 10876 10849>,
+ <10115 10817 10940 10834 10878 10831>,
+ <9949 10805 10988 10876 10871 10840>,
+ <9749 10791 11021 10939 10863 10860>,
+ <9704 10791 11014 10991 10869 10866>,
+ <9683 10795 10979 11041 10898 10870>,
+ <9677 10801 10965 11063 10936 10877>,
+ <9676 10808 10997 11078 11004 10940>,
+ <9676 10820 11042 11093 11066 11026>,
+ <9674 10836 11062 11099 11074 11055>,
+ <9670 10861 11077 11105 11063 11066>,
+ <9667 10915 11082 11111 11064 11068>,
+ <9665 11341 11085 11126 11092 11072>,
+ <9663 11748 11091 11149 11125 11083>,
+ <9661 11516 11099 11179 11148 11096>,
+ <9659 10816 11110 11217 11174 11118>,
+ <9658 10376 11118 11236 11190 11131>,
+ <9657 10155 11117 11245 11208 11140>,
+ <9656 10000 11109 11252 11224 11152>,
+ <9655 9892 11094 11259 11233 11175>,
+ <9654 9812 11060 11260 11250 11208>,
+ <9654 9762 11020 11250 11255 11218>,
+ <9653 9725 10915 11227 11244 11186>,
+ <9653 9701 10784 11207 11227 11146>,
+ <9653 9688 10695 11192 11211 11135>,
+ <9652 9678 10615 11172 11194 11131>,
+ <9652 9671 10480 11143 11192 11126>,
+ <9652 9665 10201 11106 11216 11112>,
+ <9651 9661 10108 11076 11220 11105>,
+ <9651 9658 10159 11042 11183 11120>,
+ <9651 9656 9965 10929 11157 11073>,
+ <9651 9654 9856 10889 11090 11023>,
+ <9651 9653 9796 10823 11057 10968>,
+ <9650 9653 9741 10794 11051 10955>,
+ <9650 9652 9696 10740 11029 10918>,
+ <9650 9652 9680 10652 10968 10907>,
+ <9650 9651 9670 10540 10916 10868>,
+ <9649 9651 9663 10397 10801 10776>,
+ <9648 9650 9657 10262 10712 10696>,
+ <9648 9650 9654 10448 10584 10596>,
+ <9648 9650 9654 10448 10584 10596>,
+ <9648 9650 9654 10448 10584 10596>;
+ };
+
+ qcom,pc-temp-y3-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <13491 13351 13296 13276 13275 13272>,
+ <13481 13348 13297 13278 13275 13272>,
+ <13476 13346 13298 13280 13275 13273>,
+ <13476 13347 13300 13282 13276 13274>,
+ <13480 13349 13302 13283 13276 13274>,
+ <13486 13352 13303 13283 13276 13275>,
+ <13513 13358 13303 13283 13276 13275>,
+ <13546 13363 13304 13283 13276 13275>,
+ <13543 13365 13306 13283 13277 13275>,
+ <13505 13365 13310 13284 13278 13275>,
+ <13476 13366 13315 13285 13278 13276>,
+ <13465 13371 13319 13285 13278 13276>,
+ <13456 13377 13322 13285 13278 13276>,
+ <13446 13376 13322 13286 13278 13276>,
+ <13434 13369 13321 13288 13279 13277>,
+ <13428 13363 13320 13290 13279 13277>,
+ <13428 13359 13318 13291 13280 13278>,
+ <13428 13354 13316 13292 13282 13278>,
+ <13414 13349 13313 13292 13283 13279>,
+ <13377 13343 13308 13291 13283 13281>,
+ <13356 13338 13304 13290 13284 13281>,
+ <13351 13336 13301 13286 13280 13278>,
+ <13349 13333 13299 13283 13276 13274>,
+ <13354 13323 13298 13282 13275 13273>,
+ <13374 13301 13297 13281 13275 13273>,
+ <13397 13289 13297 13281 13275 13273>,
+ <13424 13273 13297 13280 13275 13273>,
+ <13457 13259 13297 13280 13275 13273>,
+ <13494 13259 13296 13280 13275 13273>,
+ <13537 13259 13296 13280 13275 13273>,
+ <13586 13260 13295 13280 13274 13272>,
+ <13644 13261 13291 13280 13274 13272>,
+ <13708 13262 13288 13279 13274 13272>,
+ <13777 13264 13289 13279 13274 13272>,
+ <13853 13268 13293 13279 13273 13272>,
+ <13939 13274 13295 13279 13273 13272>,
+ <14040 13285 13294 13279 13274 13272>,
+ <14153 13299 13292 13280 13274 13273>,
+ <14276 13317 13292 13279 13274 13273>,
+ <14412 13340 13293 13279 13274 13273>,
+ <14564 13372 13291 13279 13274 13273>,
+ <14738 13423 13271 13280 13275 13273>,
+ <14925 13493 13262 13280 13275 13273>,
+ <15128 13598 13261 13280 13274 13273>,
+ <15354 13729 13263 13279 13275 13274>,
+ <15547 13885 13266 13284 13276 13275>,
+ <15700 13996 13270 13284 13277 13277>,
+ <15883 14139 13280 13288 13279 13277>,
+ <16098 14305 13309 13290 13280 13277>,
+ <16340 14489 13343 13292 13280 13276>,
+ <16656 14726 13389 13294 13281 13277>,
+ <17634 15025 13481 13299 13283 13278>,
+ <19636 15401 13635 13309 13286 13283>,
+ <22946 16005 13899 13335 13293 13287>,
+ <22946 16005 13899 13335 13293 13287>,
+ <22946 16005 13899 13335 13293 13287>;
+ };
+
+ qcom,pc-temp-y4-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <16973 16623 16526 16458 16452 16456>,
+ <16999 16632 16525 16457 16452 16456>,
+ <17030 16641 16525 16457 16452 16456>,
+ <17060 16652 16526 16457 16452 16456>,
+ <17082 16663 16528 16457 16452 16456>,
+ <17089 16674 16531 16457 16452 16456>,
+ <17077 16687 16535 16459 16452 16456>,
+ <17059 16701 16539 16462 16453 16456>,
+ <17098 16711 16545 16465 16453 16456>,
+ <17276 16720 16552 16468 16454 16457>,
+ <17396 16735 16563 16473 16455 16457>,
+ <17426 16824 16584 16480 16458 16458>,
+ <17443 16930 16612 16490 16461 16460>,
+ <17384 16951 16638 16498 16465 16462>,
+ <17155 16958 16663 16504 16470 16465>,
+ <17028 16959 16695 16515 16476 16469>,
+ <17014 16934 16758 16539 16486 16475>,
+ <17005 16887 16816 16571 16502 16486>,
+ <16980 16831 16800 16609 16530 16506>,
+ <16933 16754 16713 16656 16576 16541>,
+ <16886 16692 16635 16664 16593 16558>,
+ <16837 16644 16572 16570 16535 16521>,
+ <16797 16610 16522 16475 16468 16470>,
+ <16783 16607 16507 16460 16455 16458>,
+ <16776 16623 16498 16454 16451 16455>,
+ <16770 16632 16494 16453 16449 16454>,
+ <16765 16645 16493 16454 16449 16453>,
+ <16761 16659 16493 16455 16448 16453>,
+ <16761 16662 16492 16457 16449 16453>,
+ <16761 16663 16493 16461 16452 16454>,
+ <16762 16667 16493 16466 16456 16455>,
+ <16764 16677 16492 16474 16464 16461>,
+ <16767 16687 16492 16479 16471 16470>,
+ <16770 16690 16494 16478 16474 16476>,
+ <16775 16693 16500 16474 16474 16483>,
+ <16778 16693 16505 16467 16471 16482>,
+ <16782 16689 16508 16455 16458 16467>,
+ <16784 16685 16510 16448 16447 16453>,
+ <16783 16685 16511 16449 16450 16455>,
+ <16781 16683 16512 16452 16456 16465>,
+ <16779 16681 16517 16455 16459 16471>,
+ <16770 16670 16558 16460 16458 16470>,
+ <16768 16654 16579 16464 16456 16468>,
+ <16776 16634 16584 16465 16448 16452>,
+ <16801 16629 16593 16474 16448 16444>,
+ <16819 16647 16617 16493 16467 16470>,
+ <16856 16669 16641 16507 16488 16496>,
+ <16905 16699 16672 16536 16520 16521>,
+ <16944 16754 16675 16565 16529 16536>,
+ <16949 16780 16683 16555 16503 16488>,
+ <16941 16767 16681 16554 16495 16479>,
+ <17078 16794 16695 16582 16508 16485>,
+ <17565 16874 16751 16646 16545 16510>,
+ <19162 17124 16888 16859 16671 16581>,
+ <19162 17124 16888 16859 16671 16581>,
+ <19162 17124 16888 16859 16671 16581>;
+ };
+
+ qcom,pc-temp-y5-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <11501 16034 14767 13793 19407 15565>,
+ <11603 15822 15156 15683 19413 16938>,
+ <11875 15497 15333 17017 19416 18058>,
+ <12285 15152 15352 17855 19416 18894>,
+ <12803 14881 15266 18259 19413 19416>,
+ <13403 14778 15128 18284 19405 19590>,
+ <14551 14807 14793 17405 18933 19301>,
+ <15710 14848 14419 16236 18269 18809>,
+ <15425 14688 14471 15943 18195 18561>,
+ <13533 13983 14951 15873 18327 18385>,
+ <12513 13556 15219 15744 18394 18198>,
+ <13803 13493 14892 15050 17832 17726>,
+ <15473 13460 14418 14306 16921 17099>,
+ <15394 13744 14254 14381 16318 16821>,
+ <14258 14851 14181 14869 15815 16673>,
+ <13562 15643 14199 15070 15556 16471>,
+ <13428 15965 14556 14786 15450 15954>,
+ <13274 16199 15160 14490 15387 15465>,
+ <12936 16398 15863 14755 15446 15449>,
+ <12423 16588 16824 15793 15777 15650>,
+ <11952 16732 17460 16919 16267 15980>,
+ <11476 16879 17821 18292 17600 16933>,
+ <11117 16964 18087 19430 19112 18163>,
+ <11033 16245 18242 19821 19838 19000>,
+ <11009 14141 18325 19945 20331 19696>,
+ <11024 12876 18331 19914 20756 20093>,
+ <11056 11798 18517 19842 21457 20297>,
+ <11084 10948 18759 19785 21999 20418>,
+ <11132 10879 18828 19716 21658 20286>,
+ <11232 10862 18868 19575 20509 19563>,
+ <11269 10868 18768 19409 19604 18813>,
+ <11345 11005 17096 19184 18920 18072>,
+ <11421 11165 15478 19049 18499 17524>,
+ <11456 11261 16038 19331 18661 17776>,
+ <11520 11350 17571 20041 19331 19034>,
+ <11543 11387 18037 20606 20274 20444>,
+ <11613 11553 17270 21412 23017 22060>,
+ <11678 11697 16300 21789 25208 23225>,
+ <11640 11640 15861 20914 24442 22731>,
+ <11545 11511 15530 19618 22425 21047>,
+ <11506 11463 14798 19274 21559 20283>,
+ <11457 11412 12697 19217 21506 20308>,
+ <11415 11500 11853 18717 21719 20486>,
+ <11368 11742 11779 17923 22443 22679>,
+ <11364 11818 11639 16687 21754 22971>,
+ <11379 11581 11310 17555 18408 18279>,
+ <11464 11576 11214 16686 17313 17483>,
+ <11729 11969 11315 17033 16467 15409>,
+ <12142 11899 11677 16717 15881 14424>,
+ <11979 11895 11966 17491 17177 15372>,
+ <11649 12007 11983 17478 18213 16253>,
+ <11017 11938 11964 17190 17836 15973>,
+ <10265 11845 11923 16780 17343 17751>,
+ <9626 11312 12185 16916 17400 17911>,
+ <9626 11312 12185 16916 17400 17911>,
+ <9626 11312 12185 16916 17400 17911>;
+ };
+
+ qcom,pc-temp-y6-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <6106 5405 5178 5064 5046 5042>,
+ <6097 5401 5177 5064 5046 5042>,
+ <6092 5400 5176 5065 5046 5042>,
+ <6089 5400 5176 5066 5047 5043>,
+ <6088 5401 5176 5067 5047 5044>,
+ <6088 5403 5176 5067 5047 5044>,
+ <6090 5407 5176 5068 5047 5044>,
+ <6094 5413 5177 5068 5047 5044>,
+ <6102 5416 5178 5069 5047 5044>,
+ <6117 5418 5182 5071 5048 5044>,
+ <6129 5422 5187 5073 5049 5045>,
+ <6135 5450 5195 5075 5050 5045>,
+ <6139 5483 5204 5078 5051 5046>,
+ <6123 5488 5211 5081 5052 5047>,
+ <6059 5490 5218 5085 5054 5048>,
+ <6027 5490 5226 5089 5056 5050>,
+ <6030 5484 5243 5097 5060 5052>,
+ <6034 5472 5259 5107 5066 5055>,
+ <6032 5457 5253 5118 5075 5062>,
+ <6027 5435 5225 5131 5088 5073>,
+ <6025 5421 5201 5133 5093 5078>,
+ <6031 5414 5182 5104 5074 5065>,
+ <6042 5409 5169 5075 5052 5048>,
+ <6061 5410 5167 5071 5048 5044>,
+ <6095 5412 5166 5069 5047 5043>,
+ <6132 5415 5166 5069 5046 5042>,
+ <6169 5421 5168 5070 5047 5042>,
+ <6210 5431 5171 5071 5047 5042>,
+ <6254 5444 5175 5073 5048 5043>,
+ <6302 5464 5178 5075 5049 5043>,
+ <6354 5486 5181 5078 5050 5044>,
+ <6411 5511 5183 5081 5052 5046>,
+ <6471 5539 5185 5083 5055 5048>,
+ <6535 5569 5192 5084 5056 5050>,
+ <6602 5603 5205 5084 5056 5053>,
+ <6677 5640 5216 5084 5056 5053>,
+ <6759 5681 5225 5083 5053 5049>,
+ <6849 5727 5234 5083 5051 5046>,
+ <6948 5778 5244 5084 5052 5047>,
+ <7058 5835 5257 5087 5055 5050>,
+ <7178 5899 5273 5091 5057 5052>,
+ <7313 5971 5295 5095 5058 5052>,
+ <7461 6060 5322 5099 5058 5052>,
+ <7625 6170 5355 5104 5056 5049>,
+ <7801 6295 5404 5112 5059 5048>,
+ <7952 6438 5465 5127 5066 5057>,
+ <8083 6542 5513 5135 5074 5067>,
+ <8233 6666 5574 5150 5086 5075>,
+ <8404 6813 5646 5166 5090 5080>,
+ <8597 6972 5725 5172 5084 5066>,
+ <8831 7159 5819 5184 5085 5065>,
+ <9655 7408 5955 5214 5093 5070>,
+ <11356 7725 6149 5262 5110 5083>,
+ <14260 8288 6430 5374 5157 5109>,
+ <14260 8288 6430 5374 5157 5109>,
+ <14260 8288 6430 5374 5157 5109>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-atl436186020H_3780mAh.dtsi b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-atl436186020H_3780mAh.dtsi
new file mode 100755
index 0000000..e9a3598
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-atl436186020H_3780mAh.dtsi
@@ -0,0 +1,1046 @@
+qcom,ATL436186_020H_3780mAh {
+ /* ATL436186_020H_3780mAh_Averaged_MasterSlave_Feb25th2020 */
+ qcom,max-voltage-uv = <4400000>;
+ qcom,fg-cc-cv-threshold-uv = <4400000>;
+ qcom,fastchg-current-ma = <10000>;
+ qcom,batt-id-kohm = <39>;
+ qcom,battery-beta = <4250>;
+ qcom,battery-therm-kohm = <100>;
+ qcom,battery-type =
+ "ATL436186_020H_3780mAh_Averaged_MasterSlave_Feb25th2020";
+ qcom,qg-batt-profile-ver = <100>;
+
+ qcom,jeita-fcc-ranges = <0 100 1890000
+ 101 200 3780000
+ 201 420 10000000
+ 421 434 8000000
+ 435 450 7000000
+ 451 550 1890000>;
+
+ qcom,jeita-fv-ranges = <0 100 4400000
+ 101 200 4400000
+ 201 420 4400000
+ 421 434 4400000
+ 435 450 4400000
+ 451 550 4050000>;
+
+ qcom,step-chg-ranges = <3500000 4000000 10000000
+ 4000001 4200000 8000000
+ 4200001 4400000 6000000>;
+ qcom,ocv-based-step-chg;
+
+ /* Rise-Hys = 1 DeciDegC, Fall-Hys=10 deciDegC */
+ qcom,qcom,step-jeita-hysteresis = <1 10>;
+ /* COOL = 10 degc, WARM = 45 degC */
+ qcom,jeita-soft-thresholds = <0x4ccc 0x20b8>;
+ /* COLD = 0 degC, HOT = 55 degC*/
+ qcom,jeita-hard-thresholds = <0x58cd 0x181d>;
+ /* COOL hys = 13 degC, WARM hys = 42 degC */
+ qcom,jeita-soft-hys-thresholds = <0x48d4 0x23c0>;
+ qcom,jeita-soft-fcc-ua = <1890000 1890000>;
+ qcom,jeita-soft-fv-uv = <4400000 4050000>;
+
+ qcom,fcc1-temp-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-data = <3697 3755 3812 3835 3845>;
+ };
+
+ qcom,fcc2-temp-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-data = <3792 3795 3802 3819 3809 3801>;
+ };
+
+ qcom,pc-temp-v1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <43837 43914 43961 43974 43979>,
+ <43618 43702 43752 43762 43768>,
+ <43394 43485 43537 43549 43556>,
+ <43166 43264 43318 43332 43342>,
+ <42938 43039 43095 43113 43125>,
+ <42710 42810 42869 42890 42903>,
+ <42481 42578 42639 42662 42677>,
+ <42256 42346 42406 42431 42450>,
+ <42034 42119 42176 42201 42223>,
+ <41817 41896 41949 41975 41997>,
+ <41609 41677 41725 41751 41771>,
+ <41407 41462 41506 41531 41550>,
+ <41207 41252 41291 41313 41332>,
+ <41011 41053 41083 41103 41121>,
+ <40819 40863 40881 40898 40917>,
+ <40625 40675 40686 40700 40720>,
+ <40431 40487 40499 40510 40529>,
+ <40258 40304 40321 40329 40345>,
+ <40119 40139 40148 40153 40167>,
+ <39977 39988 39986 39986 39997>,
+ <39774 39809 39817 39819 39828>,
+ <39506 39562 39607 39622 39634>,
+ <39289 39314 39366 39391 39406>,
+ <39151 39148 39169 39185 39199>,
+ <39041 39021 39021 39027 39039>,
+ <38943 38908 38896 38893 38903>,
+ <38856 38802 38783 38774 38781>,
+ <38774 38706 38682 38669 38673>,
+ <38695 38620 38590 38572 38573>,
+ <38621 38542 38505 38481 38478>,
+ <38554 38471 38429 38398 38392>,
+ <38493 38405 38359 38322 38312>,
+ <38438 38346 38296 38252 38238>,
+ <38387 38291 38238 38189 38170>,
+ <38341 38243 38188 38137 38109>,
+ <38300 38198 38138 38084 38049>,
+ <38266 38162 38090 38022 37975>,
+ <38227 38123 38040 37953 37891>,
+ <38155 38058 37972 37872 37800>,
+ <38045 37951 37874 37776 37702>,
+ <37922 37829 37759 37666 37594>,
+ <37785 37699 37633 37539 37465>,
+ <37631 37552 37490 37396 37318>,
+ <37448 37375 37320 37231 37158>,
+ <37301 37226 37175 37102 37032>,
+ <37200 37139 37097 37033 36972>,
+ <37176 37110 37072 37016 36954>,
+ <37175 37095 37054 37001 36939>,
+ <37137 37069 37036 36980 36914>,
+ <37063 36993 36930 36851 36764>,
+ <36758 36680 36593 36504 36417>,
+ <36291 36221 36130 36040 35954>,
+ <35695 35625 35535 35440 35357>,
+ <34884 34815 34721 34626 34546>,
+ <33616 33554 33462 33363 33302>,
+ <30000 30000 30000 30000 30000>;
+ };
+
+ qcom,pc-temp-v2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <44010 43990 43980 43955 43910 43895>,
+ <43674 43710 43723 43710 43669 43653>,
+ <43367 43445 43475 43472 43433 43418>,
+ <43093 43196 43238 43240 43203 43189>,
+ <42851 42966 43012 43017 42980 42968>,
+ <42613 42737 42786 42792 42757 42746>,
+ <42365 42504 42555 42562 42527 42517>,
+ <42121 42270 42323 42330 42297 42288>,
+ <41898 42038 42094 42100 42070 42062>,
+ <41692 41806 41864 41873 41844 41837>,
+ <41486 41578 41638 41648 41621 41615>,
+ <41265 41355 41418 41427 41403 41397>,
+ <41047 41138 41202 41209 41188 41182>,
+ <40862 40936 40996 41001 40980 40975>,
+ <40707 40746 40796 40798 40776 40772>,
+ <40521 40559 40598 40601 40580 40577>,
+ <40232 40377 40403 40410 40392 40389>,
+ <39909 40189 40207 40224 40211 40207>,
+ <39657 39968 40007 40045 40036 40032>,
+ <39447 39713 39804 39870 39866 39866>,
+ <39247 39471 39594 39674 39679 39682>,
+ <39047 39253 39364 39429 39442 39449>,
+ <38856 39052 39141 39188 39206 39213>,
+ <38674 38878 38961 39005 39025 39033>,
+ <38496 38724 38807 38848 38871 38882>,
+ <38358 38586 38671 38714 38738 38751>,
+ <38264 38460 38551 38597 38623 38636>,
+ <38190 38345 38443 38492 38520 38532>,
+ <38129 38232 38342 38395 38426 38435>,
+ <38078 38123 38247 38304 38337 38344>,
+ <38030 38040 38160 38220 38255 38261>,
+ <37982 37980 38078 38142 38179 38186>,
+ <37935 37931 38002 38068 38106 38114>,
+ <37884 37893 37933 38000 38035 38038>,
+ <37832 37863 37868 37935 37964 37959>,
+ <37777 37829 37812 37862 37879 37865>,
+ <37715 37789 37766 37778 37771 37744>,
+ <37646 37742 37719 37690 37659 37617>,
+ <37568 37678 37654 37600 37560 37514>,
+ <37480 37592 37571 37507 37468 37423>,
+ <37378 37484 37472 37409 37367 37324>,
+ <37250 37342 37350 37301 37256 37212>,
+ <37117 37183 37208 37173 37128 37083>,
+ <36996 37011 37048 37022 36979 36931>,
+ <36898 36881 36926 36922 36889 36842>,
+ <36814 36811 36868 36890 36863 36817>,
+ <36773 36779 36838 36869 36848 36802>,
+ <36727 36738 36803 36842 36825 36779>,
+ <36660 36680 36748 36790 36781 36737>,
+ <36517 36561 36624 36620 36609 36535>,
+ <36231 36271 36298 36228 36203 36133>,
+ <35764 35780 35781 35692 35681 35615>,
+ <35118 35133 35110 35007 35009 34946>,
+ <34216 34250 34193 34048 34114 34057>,
+ <32787 32833 32800 32877 32759 32761>,
+ <29558 29605 29729 29539 29540 29544>;
+ };
+
+ qcom,pc-temp-z1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <10270 9660 9205 8982 8932>,
+ <10729 10185 9985 9894 9870>,
+ <10961 10522 10161 10008 9971>,
+ <11078 10616 10231 10065 10021>,
+ <11137 10656 10248 10073 10030>,
+ <11151 10675 10258 10073 10030>,
+ <11155 10683 10258 10073 10029>,
+ <11157 10687 10253 10071 10028>,
+ <11160 10685 10249 10068 10027>,
+ <11164 10677 10247 10067 10027>,
+ <11163 10670 10245 10066 10026>,
+ <11158 10666 10244 10066 10026>,
+ <11155 10663 10242 10066 10026>,
+ <11156 10660 10241 10066 10026>,
+ <11157 10657 10242 10066 10026>,
+ <11156 10656 10243 10066 10026>,
+ <11151 10657 10244 10066 10027>,
+ <11148 10661 10245 10067 10028>,
+ <11149 10661 10246 10069 10029>,
+ <11150 10662 10249 10070 10030>,
+ <11154 10662 10251 10071 10030>,
+ <11163 10665 10253 10073 10031>,
+ <11167 10668 10256 10075 10032>,
+ <11169 10672 10259 10077 10033>,
+ <11173 10677 10263 10079 10035>,
+ <11179 10682 10268 10081 10037>,
+ <11187 10688 10272 10083 10039>,
+ <11191 10694 10276 10084 10040>,
+ <11188 10695 10280 10086 10041>,
+ <11182 10696 10284 10089 10042>,
+ <11180 10697 10287 10091 10044>,
+ <11182 10699 10290 10093 10046>,
+ <11186 10703 10294 10095 10047>,
+ <11195 10707 10298 10098 10048>,
+ <11210 10711 10302 10101 10050>,
+ <11214 10715 10307 10104 10052>,
+ <11209 10725 10311 10107 10054>,
+ <11204 10735 10316 10109 10057>,
+ <11209 10736 10321 10112 10059>,
+ <11224 10733 10326 10114 10060>,
+ <11232 10731 10331 10116 10062>,
+ <11233 10740 10335 10119 10063>,
+ <11234 10751 10340 10121 10065>,
+ <11236 10753 10345 10123 10065>,
+ <11250 10761 10351 10125 10066>,
+ <11246 10766 10354 10126 10067>,
+ <11246 10761 10358 10127 10067>,
+ <11257 10768 10360 10127 10067>,
+ <11246 10764 10362 10128 10068>,
+ <11264 10770 10369 10131 10069>,
+ <11271 10785 10373 10132 10072>,
+ <11301 10793 10379 10137 10073>,
+ <11283 10797 10389 10144 10076>,
+ <11343 10815 10399 10147 10080>,
+ <11343 10815 10399 10147 10080>,
+ <11343 10815 10399 10147 10080>;
+ };
+
+ qcom,pc-temp-z2-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <9998 10274 10794 10844 10945>,
+ <10167 10355 10550 10730 10846>,
+ <10239 10399 10603 10678 10871>,
+ <10266 10395 10627 10658 10860>,
+ <10276 10383 10590 10661 10840>,
+ <10258 10382 10530 10681 10820>,
+ <10229 10393 10504 10694 10818>,
+ <10222 10402 10503 10691 10838>,
+ <10225 10403 10506 10686 10861>,
+ <10230 10402 10495 10698 10866>,
+ <10468 10399 10479 10712 10863>,
+ <10817 10392 10478 10717 10858>,
+ <10830 10389 10490 10720 10866>,
+ <10488 10389 10497 10723 10887>,
+ <10237 10383 10489 10733 10919>,
+ <10238 10380 10479 10753 10955>,
+ <10250 10394 10485 10763 10976>,
+ <10293 10409 10508 10767 10990>,
+ <10590 10407 10522 10769 10998>,
+ <10856 10392 10525 10764 10996>,
+ <10737 10386 10523 10757 10989>,
+ <10407 10410 10531 10746 10961>,
+ <10271 10437 10570 10711 10841>,
+ <10271 10447 10592 10670 10746>,
+ <10273 10453 10576 10628 10731>,
+ <10283 10454 10553 10595 10727>,
+ <10306 10441 10542 10604 10733>,
+ <10322 10425 10536 10639 10758>,
+ <10324 10424 10535 10657 10785>,
+ <10323 10434 10540 10663 10803>,
+ <10323 10447 10549 10671 10824>,
+ <10329 10467 10557 10698 10870>,
+ <10336 10487 10569 10749 10948>,
+ <10345 10497 10586 10795 11004>,
+ <10355 10502 10622 10833 11059>,
+ <10358 10503 10654 10871 11110>,
+ <10355 10506 10670 10914 11142>,
+ <10351 10511 10681 10958 11183>,
+ <10348 10514 10696 10979 11193>,
+ <10344 10522 10730 10992 11177>,
+ <10338 10526 10756 11000 11154>,
+ <10307 10496 10725 10996 11137>,
+ <10278 10462 10682 10987 11119>,
+ <10264 10453 10689 10977 11087>,
+ <10246 10428 10699 10978 11047>,
+ <10229 10374 10720 11010 11096>,
+ <10188 10355 10691 11025 11117>,
+ <10121 10306 10709 11029 11193>,
+ <10243 10335 10714 11081 11268>,
+ <10479 10337 10724 10961 10999>,
+ <10405 10348 10693 10847 10883>,
+ <10327 10360 10632 10748 10808>,
+ <9992 10290 10623 10696 10740>,
+ <10016 10209 10570 10627 10634>,
+ <10016 10209 10570 10627 10634>,
+ <10016 10209 10570 10627 10634>;
+ };
+
+ qcom,pc-temp-z3-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <19393 19347 19322 19314 19304>,
+ <19481 19407 19348 19323 19310>,
+ <19528 19444 19374 19334 19318>,
+ <19557 19459 19384 19340 19321>,
+ <19571 19467 19381 19338 19320>,
+ <19574 19469 19375 19332 19319>,
+ <19576 19464 19371 19330 19317>,
+ <19574 19458 19367 19329 19315>,
+ <19563 19453 19365 19329 19313>,
+ <19554 19448 19361 19327 19312>,
+ <19555 19445 19358 19323 19311>,
+ <19558 19444 19356 19321 19310>,
+ <19555 19442 19354 19320 19310>,
+ <19544 19439 19353 19319 19309>,
+ <19533 19433 19353 19318 19306>,
+ <19526 19431 19353 19318 19302>,
+ <19521 19432 19352 19317 19300>,
+ <19520 19434 19351 19315 19300>,
+ <19527 19434 19350 19314 19299>,
+ <19535 19434 19349 19312 19299>,
+ <19537 19434 19349 19311 19299>,
+ <19543 19435 19353 19313 19303>,
+ <19546 19436 19361 19324 19317>,
+ <19536 19440 19369 19333 19326>,
+ <19524 19451 19377 19336 19325>,
+ <19524 19456 19381 19338 19323>,
+ <19532 19456 19380 19338 19321>,
+ <19538 19454 19377 19335 19319>,
+ <19538 19451 19374 19332 19317>,
+ <19537 19445 19369 19330 19315>,
+ <19535 19440 19365 19327 19312>,
+ <19531 19436 19361 19324 19309>,
+ <19527 19434 19358 19321 19306>,
+ <19524 19432 19356 19318 19303>,
+ <19521 19430 19355 19315 19301>,
+ <19519 19429 19354 19313 19300>,
+ <19515 19426 19353 19312 19300>,
+ <19511 19424 19352 19312 19301>,
+ <19506 19420 19350 19312 19301>,
+ <19499 19415 19347 19313 19303>,
+ <19494 19410 19343 19314 19304>,
+ <19492 19407 19342 19315 19306>,
+ <19489 19404 19341 19316 19307>,
+ <19483 19400 19338 19319 19308>,
+ <19461 19390 19335 19317 19308>,
+ <19456 19383 19327 19309 19299>,
+ <19436 19385 19328 19304 19295>,
+ <19263 19371 19326 19300 19292>,
+ <19262 19374 19319 19296 19290>,
+ <19261 19369 19326 19308 19301>,
+ <19261 19365 19335 19313 19303>,
+ <19261 19355 19338 19313 19303>,
+ <19264 19362 19329 19315 19304>,
+ <19263 19368 19332 19316 19306>,
+ <19263 19368 19332 19316 19306>,
+ <19263 19368 19332 19316 19306>;
+ };
+
+ qcom,pc-temp-z4-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <15411 15118 14858 14791 14756>,
+ <15540 15131 14945 14798 14741>,
+ <15522 15130 14892 14768 14727>,
+ <15372 15081 14836 14731 14698>,
+ <15215 14972 14795 14714 14687>,
+ <15110 14894 14763 14705 14683>,
+ <15022 14847 14748 14697 14679>,
+ <14959 14816 14739 14690 14675>,
+ <14908 14802 14731 14684 14670>,
+ <14869 14794 14723 14679 14665>,
+ <14839 14788 14717 14674 14661>,
+ <14817 14781 14710 14669 14656>,
+ <14812 14775 14704 14663 14651>,
+ <14820 14769 14698 14658 14647>,
+ <14832 14763 14693 14652 14643>,
+ <14850 14762 14688 14647 14640>,
+ <14880 14770 14686 14643 14636>,
+ <14889 14779 14685 14640 14631>,
+ <14846 14773 14684 14639 14628>,
+ <14800 14754 14688 14641 14629>,
+ <14825 14750 14695 14648 14632>,
+ <14928 14825 14724 14663 14641>,
+ <14993 14913 14779 14695 14664>,
+ <15001 14914 14799 14712 14678>,
+ <14998 14879 14781 14707 14677>,
+ <14983 14850 14758 14697 14673>,
+ <14949 14834 14746 14689 14669>,
+ <14924 14823 14738 14683 14664>,
+ <14914 14821 14734 14678 14660>,
+ <14908 14820 14732 14673 14656>,
+ <14907 14819 14731 14670 14652>,
+ <14908 14821 14731 14669 14650>,
+ <14909 14823 14731 14668 14648>,
+ <14909 14826 14732 14668 14647>,
+ <14909 14829 14734 14669 14646>,
+ <14909 14831 14738 14670 14646>,
+ <14902 14827 14742 14676 14650>,
+ <14892 14820 14745 14686 14661>,
+ <14881 14812 14746 14689 14665>,
+ <14868 14804 14742 14686 14662>,
+ <14851 14792 14736 14681 14659>,
+ <14827 14773 14724 14676 14657>,
+ <14801 14751 14709 14671 14655>,
+ <14776 14733 14701 14668 14655>,
+ <14722 14697 14683 14659 14649>,
+ <14692 14666 14659 14644 14634>,
+ <14706 14660 14649 14639 14629>,
+ <14871 14659 14641 14630 14620>,
+ <14866 14650 14633 14626 14617>,
+ <14863 14655 14638 14628 14623>,
+ <14867 14664 14635 14630 14625>,
+ <14872 14672 14633 14629 14625>,
+ <14872 14667 14638 14627 14624>,
+ <14877 14663 14636 14625 14622>,
+ <14877 14663 14636 14625 14622>,
+ <14877 14663 14636 14625 14622>;
+ };
+
+ qcom,pc-temp-z5-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <12262 12657 13731 16808 17854>,
+ <13952 14497 15898 18081 19486>,
+ <15214 16021 17443 19818 21650>,
+ <16162 17186 18570 21296 23275>,
+ <17097 18170 19329 21536 24003>,
+ <18157 19258 19745 21509 24358>,
+ <19290 20662 19830 21628 24381>,
+ <20511 21771 20008 22343 23971>,
+ <21891 22042 20173 22938 23666>,
+ <23153 22138 20134 22808 23885>,
+ <24239 22299 20112 22359 24494>,
+ <25122 22870 20235 22259 25170>,
+ <25283 23518 20612 22732 26113>,
+ <24901 23610 21090 23419 26820>,
+ <24579 23449 21852 24318 26214>,
+ <24560 23299 22739 25492 24698>,
+ <24597 23117 23372 26450 24419>,
+ <24657 22978 23855 27282 26292>,
+ <24758 24230 24222 27692 27840>,
+ <24963 27807 24600 27046 27691>,
+ <27120 29427 24875 25350 27235>,
+ <33501 27662 23857 23361 26672>,
+ <36732 25045 20915 20755 24954>,
+ <32079 23961 19681 19621 23155>,
+ <25894 23427 20225 19990 22122>,
+ <25017 23670 21187 20786 21421>,
+ <26081 25610 22464 21686 21497>,
+ <27398 27942 24124 22802 22457>,
+ <28893 29059 25372 23931 23556>,
+ <30402 29771 26311 25076 24526>,
+ <31214 30415 27177 26252 25453>,
+ <31859 31149 28012 27490 26246>,
+ <32223 31779 28804 28771 27082>,
+ <32238 32053 29691 29417 27978>,
+ <32222 32216 30909 29665 29280>,
+ <32171 32224 31681 29773 30219>,
+ <31897 31917 31314 28697 28966>,
+ <31589 31417 30242 26131 25565>,
+ <31432 30966 29114 25294 24387>,
+ <31306 30513 27668 25736 25464>,
+ <31237 30105 26683 26472 27140>,
+ <31178 29635 26578 27651 29292>,
+ <31252 29276 26516 29015 31174>,
+ <31626 29252 25441 29682 30555>,
+ <31440 30295 26157 28469 30177>,
+ <32621 30638 26358 26578 24593>,
+ <28667 32814 29500 26931 25216>,
+ <11283 24894 31532 29489 30335>,
+ <11256 26655 27253 28994 33457>,
+ <11252 24276 28331 30163 34171>,
+ <11253 21078 30650 32037 33143>,
+ <11197 17749 31712 30278 31282>,
+ <11126 18743 23249 30719 30746>,
+ <11019 19676 23476 30978 30980>,
+ <11019 19676 23476 30978 30980>,
+ <11019 19676 23476 30978 30980>;
+ };
+
+ qcom,pc-temp-z6-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <14990 14531 14250 14172 14140>,
+ <15156 14653 14425 14331 14298>,
+ <15177 14719 14443 14341 14309>,
+ <15121 14708 14447 14344 14312>,
+ <15058 14667 14434 14340 14311>,
+ <15003 14634 14414 14332 14308>,
+ <14950 14608 14404 14326 14304>,
+ <14907 14588 14397 14323 14301>,
+ <14868 14577 14391 14319 14297>,
+ <14840 14569 14386 14316 14295>,
+ <14826 14563 14381 14312 14292>,
+ <14817 14558 14377 14308 14290>,
+ <14813 14553 14373 14305 14287>,
+ <14809 14548 14370 14302 14285>,
+ <14806 14542 14367 14299 14282>,
+ <14809 14540 14365 14297 14278>,
+ <14818 14544 14364 14294 14275>,
+ <14821 14549 14363 14292 14273>,
+ <14809 14546 14362 14291 14272>,
+ <14796 14539 14364 14292 14272>,
+ <14808 14538 14368 14294 14274>,
+ <14856 14573 14383 14302 14280>,
+ <14885 14613 14414 14324 14298>,
+ <14885 14616 14425 14335 14309>,
+ <14882 14609 14421 14334 14309>,
+ <14877 14602 14416 14332 14306>,
+ <14871 14596 14412 14329 14304>,
+ <14866 14592 14407 14325 14301>,
+ <14864 14589 14404 14321 14298>,
+ <14862 14587 14401 14318 14295>,
+ <14861 14586 14399 14316 14292>,
+ <14863 14587 14397 14314 14289>,
+ <14864 14589 14396 14312 14287>,
+ <14865 14591 14396 14311 14285>,
+ <14867 14593 14398 14310 14284>,
+ <14867 14594 14400 14310 14283>,
+ <14867 14594 14402 14312 14285>,
+ <14866 14593 14405 14317 14291>,
+ <14865 14591 14405 14318 14293>,
+ <14863 14588 14403 14318 14292>,
+ <14861 14584 14400 14317 14292>,
+ <14859 14579 14395 14315 14292>,
+ <14858 14574 14389 14314 14292>,
+ <14856 14569 14386 14314 14293>,
+ <14840 14557 14379 14311 14291>,
+ <14835 14546 14366 14300 14280>,
+ <14833 14546 14362 14295 14275>,
+ <14822 14541 14359 14289 14270>,
+ <14825 14541 14353 14285 14267>,
+ <14833 14546 14359 14292 14276>,
+ <14843 14554 14364 14297 14279>,
+ <14856 14555 14367 14297 14280>,
+ <14867 14566 14367 14299 14281>,
+ <14891 14579 14371 14300 14282>,
+ <14891 14579 14371 14300 14282>,
+ <14891 14579 14371 14300 14282>;
+ };
+
+ qcom,pc-temp-y1-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <5613 5139 4854 4609 4486 4453>,
+ <5582 5142 4858 4605 4484 4452>,
+ <5561 5141 4859 4600 4482 4452>,
+ <5548 5138 4858 4596 4480 4451>,
+ <5541 5134 4856 4592 4478 4450>,
+ <5539 5133 4853 4590 4477 4450>,
+ <5549 5131 4848 4587 4476 4450>,
+ <5563 5129 4842 4585 4475 4450>,
+ <5562 5129 4838 4583 4474 4449>,
+ <5545 5126 4835 4580 4474 4447>,
+ <5535 5124 4832 4578 4473 4446>,
+ <5536 5124 4827 4577 4472 4447>,
+ <5537 5122 4823 4575 4470 4447>,
+ <5539 5121 4821 4574 4470 4447>,
+ <5550 5118 4820 4572 4470 4447>,
+ <5558 5117 4820 4571 4470 4447>,
+ <5560 5127 4820 4572 4470 4447>,
+ <5560 5138 4822 4572 4470 4447>,
+ <5556 5137 4822 4573 4470 4447>,
+ <5550 5127 4821 4574 4471 4448>,
+ <5547 5124 4821 4576 4472 4448>,
+ <5548 5124 4824 4576 4472 4448>,
+ <5549 5126 4826 4577 4472 4449>,
+ <5552 5130 4827 4579 4473 4449>,
+ <5561 5136 4829 4581 4473 4450>,
+ <5570 5140 4831 4583 4474 4451>,
+ <5579 5139 4834 4585 4476 4451>,
+ <5585 5137 4837 4588 4477 4452>,
+ <5579 5139 4841 4591 4478 4452>,
+ <5566 5146 4848 4594 4479 4453>,
+ <5563 5150 4851 4597 4480 4453>,
+ <5559 5154 4853 4600 4482 4454>,
+ <5551 5159 4854 4604 4484 4455>,
+ <5550 5161 4854 4607 4486 4456>,
+ <5556 5162 4855 4611 4488 4458>,
+ <5561 5162 4856 4615 4489 4458>,
+ <5559 5157 4859 4619 4490 4459>,
+ <5555 5152 4862 4623 4491 4460>,
+ <5560 5155 4871 4624 4492 4461>,
+ <5575 5164 4883 4625 4493 4462>,
+ <5582 5167 4888 4627 4495 4463>,
+ <5567 5164 4886 4631 4496 4463>,
+ <5558 5165 4888 4634 4497 4464>,
+ <5581 5178 4892 4640 4499 4465>,
+ <5588 5163 4895 4644 4500 4466>,
+ <5579 5172 4907 4646 4501 4466>,
+ <5597 5165 4900 4650 4502 4466>,
+ <5597 5165 4903 4654 4502 4468>,
+ <5638 5175 4904 4656 4503 4467>,
+ <5637 5176 4909 4658 4503 4468>,
+ <5722 5182 4909 4660 4503 4468>,
+ <5802 5199 4918 4665 4506 4469>,
+ <5999 5220 4916 4671 4508 4470>,
+ <6440 5346 4923 4681 4510 4473>,
+ <6440 5346 4923 4681 4510 4473>,
+ <6440 5346 4923 4681 4510 4473>;
+ };
+
+ qcom,pc-temp-y2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <10579 10898 11101 11195 11534 11808>,
+ <10587 10890 11091 11188 11513 11753>,
+ <10595 10879 11070 11175 11481 11696>,
+ <10604 10868 11044 11157 11444 11639>,
+ <10612 10857 11017 11136 11403 11584>,
+ <10621 10848 10996 11113 11363 11533>,
+ <10630 10840 10976 11081 11311 11480>,
+ <10639 10830 10955 11051 11264 11433>,
+ <10650 10820 10936 11044 11251 11410>,
+ <10673 10808 10914 11046 11247 11392>,
+ <10698 10802 10904 11044 11242 11376>,
+ <10744 10811 10908 11020 11234 11359>,
+ <10793 10832 10916 10994 11227 11343>,
+ <10791 10866 10931 11000 11228 11330>,
+ <10754 10934 10967 11040 11240 11314>,
+ <10733 10997 11008 11088 11247 11303>,
+ <10770 11068 11064 11140 11246 11302>,
+ <10824 11133 11128 11204 11248 11309>,
+ <10829 11137 11183 11298 11292 11337>,
+ <10812 11095 11236 11421 11410 11407>,
+ <10788 11055 11257 11462 11470 11467>,
+ <10757 11032 11230 11408 11472 11558>,
+ <10716 11010 11191 11350 11476 11666>,
+ <10655 10989 11177 11340 11522 11710>,
+ <10520 10968 11170 11336 11595 11730>,
+ <10362 10946 11169 11335 11630 11752>,
+ <10105 10916 11177 11364 11639 11784>,
+ <9860 10890 11186 11400 11646 11820>,
+ <9786 10887 11191 11417 11670 11856>,
+ <9751 10889 11190 11437 11713 11899>,
+ <9729 10890 11180 11443 11749 11939>,
+ <9712 10843 11139 11445 11777 11976>,
+ <9699 10771 11103 11445 11803 12006>,
+ <9691 10761 11101 11445 11829 12028>,
+ <9685 10796 11105 11451 11852 12052>,
+ <9680 10818 11107 11445 11855 12059>,
+ <9676 10793 11098 11416 11825 12028>,
+ <9673 10743 11080 11393 11794 11998>,
+ <9671 10658 11045 11390 11782 12004>,
+ <9669 10468 10976 11389 11776 12021>,
+ <9667 10230 10887 11379 11772 12015>,
+ <9666 9913 10756 11355 11767 11932>,
+ <9664 9749 10615 11333 11749 11876>,
+ <9663 9708 10495 11285 11708 11873>,
+ <9662 9691 10413 11193 11663 11846>,
+ <9660 9683 10344 11207 11610 11670>,
+ <9659 9678 10297 11200 11562 11627>,
+ <9658 9673 10226 11178 11454 11533>,
+ <9657 9669 10160 11156 11417 11523>,
+ <9654 9666 10110 11116 11448 11504>,
+ <9651 9663 10039 11055 11432 11472>,
+ <9650 9659 9904 10988 11333 11399>,
+ <9648 9654 9774 10991 11236 11296>,
+ <9648 9651 9700 11020 11107 11175>,
+ <9648 9651 9700 11020 11107 11175>,
+ <9648 9651 9700 11020 11107 11175>;
+ };
+
+ qcom,pc-temp-y3-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <13401 13334 13305 13279 13270 13266>,
+ <13404 13336 13305 13280 13270 13266>,
+ <13407 13339 13306 13281 13271 13267>,
+ <13409 13341 13307 13281 13271 13268>,
+ <13412 13343 13308 13282 13272 13269>,
+ <13414 13345 13309 13282 13272 13270>,
+ <13415 13347 13310 13283 13273 13270>,
+ <13416 13349 13312 13283 13273 13270>,
+ <13421 13351 13312 13284 13274 13270>,
+ <13434 13352 13313 13284 13274 13271>,
+ <13442 13353 13314 13285 13275 13271>,
+ <13422 13356 13315 13285 13275 13272>,
+ <13394 13359 13316 13285 13275 13272>,
+ <13389 13356 13316 13286 13275 13273>,
+ <13391 13345 13316 13288 13276 13273>,
+ <13393 13339 13316 13289 13276 13273>,
+ <13388 13342 13313 13290 13277 13274>,
+ <13379 13346 13310 13291 13279 13275>,
+ <13373 13345 13309 13291 13279 13275>,
+ <13369 13337 13308 13290 13280 13276>,
+ <13364 13329 13308 13289 13280 13277>,
+ <13360 13325 13305 13286 13277 13274>,
+ <13356 13322 13300 13282 13274 13270>,
+ <13351 13319 13298 13280 13272 13269>,
+ <13343 13318 13297 13279 13270 13268>,
+ <13338 13316 13296 13278 13270 13268>,
+ <13339 13315 13296 13278 13270 13268>,
+ <13342 13314 13295 13278 13270 13268>,
+ <13347 13312 13295 13278 13270 13268>,
+ <13356 13310 13295 13278 13271 13268>,
+ <13365 13309 13294 13278 13271 13268>,
+ <13373 13306 13293 13278 13271 13268>,
+ <13381 13304 13293 13278 13270 13269>,
+ <13391 13305 13293 13278 13270 13269>,
+ <13406 13311 13292 13278 13271 13269>,
+ <13425 13316 13293 13278 13271 13268>,
+ <13451 13318 13293 13277 13270 13268>,
+ <13484 13321 13294 13277 13269 13267>,
+ <13520 13323 13295 13276 13269 13267>,
+ <13561 13327 13295 13274 13269 13267>,
+ <13608 13332 13296 13275 13269 13268>,
+ <13660 13343 13298 13276 13269 13268>,
+ <13722 13357 13299 13277 13270 13268>,
+ <13798 13368 13301 13277 13270 13268>,
+ <13898 13385 13305 13278 13269 13267>,
+ <13981 13408 13307 13278 13270 13270>,
+ <14066 13433 13309 13279 13272 13271>,
+ <14173 13468 13312 13281 13273 13271>,
+ <14311 13522 13319 13285 13275 13271>,
+ <14673 13589 13329 13285 13273 13270>,
+ <15387 13676 13335 13285 13273 13270>,
+ <16730 13847 13348 13287 13274 13271>,
+ <19422 14291 13383 13291 13275 13271>,
+ <24674 15433 13481 13297 13276 13273>,
+ <24674 15433 13481 13297 13276 13273>,
+ <24674 15433 13481 13297 13276 13273>;
+ };
+
+ qcom,pc-temp-y4-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <16694 16620 16544 16472 16435 16430>,
+ <16722 16640 16554 16470 16434 16428>,
+ <16772 16662 16560 16467 16433 16426>,
+ <16827 16684 16563 16465 16431 16424>,
+ <16872 16700 16565 16463 16430 16422>,
+ <16890 16706 16565 16462 16429 16422>,
+ <16887 16703 16562 16462 16429 16422>,
+ <16884 16698 16557 16461 16429 16422>,
+ <16883 16695 16555 16462 16430 16423>,
+ <16885 16692 16555 16463 16431 16424>,
+ <16889 16691 16555 16465 16432 16424>,
+ <16942 16691 16558 16469 16434 16426>,
+ <17027 16693 16566 16474 16438 16427>,
+ <17070 16714 16578 16479 16441 16429>,
+ <17099 16795 16599 16484 16446 16433>,
+ <17108 16843 16624 16491 16451 16436>,
+ <17016 16843 16657 16503 16456 16441>,
+ <16874 16835 16685 16519 16463 16446>,
+ <16813 16813 16685 16543 16477 16457>,
+ <16782 16754 16670 16575 16501 16474>,
+ <16750 16699 16650 16585 16510 16481>,
+ <16705 16656 16605 16546 16490 16467>,
+ <16657 16619 16553 16498 16463 16447>,
+ <16613 16593 16528 16477 16449 16437>,
+ <16568 16574 16513 16462 16439 16430>,
+ <16550 16558 16506 16458 16436 16428>,
+ <16559 16545 16503 16459 16436 16429>,
+ <16570 16532 16502 16460 16438 16430>,
+ <16576 16512 16501 16463 16440 16431>,
+ <16581 16488 16500 16468 16444 16435>,
+ <16587 16478 16500 16474 16449 16439>,
+ <16596 16484 16498 16479 16456 16444>,
+ <16606 16495 16495 16485 16463 16450>,
+ <16615 16506 16490 16490 16469 16454>,
+ <16625 16517 16481 16494 16473 16457>,
+ <16632 16529 16479 16494 16473 16457>,
+ <16639 16549 16486 16481 16460 16447>,
+ <16644 16569 16497 16466 16445 16436>,
+ <16647 16580 16503 16453 16440 16434>,
+ <16650 16587 16507 16443 16437 16433>,
+ <16650 16588 16511 16442 16435 16433>,
+ <16636 16578 16517 16445 16432 16432>,
+ <16620 16568 16522 16450 16430 16431>,
+ <16614 16563 16525 16453 16428 16427>,
+ <16615 16562 16523 16451 16422 16420>,
+ <16613 16564 16518 16456 16427 16422>,
+ <16627 16574 16527 16464 16431 16427>,
+ <16649 16594 16545 16476 16440 16441>,
+ <16680 16626 16576 16495 16462 16472>,
+ <16773 16666 16611 16492 16462 16446>,
+ <16928 16677 16605 16482 16430 16426>,
+ <17295 16696 16613 16495 16436 16431>,
+ <18563 16866 16657 16525 16454 16445>,
+ <24332 17928 16752 16586 16506 16498>,
+ <24332 17928 16752 16586 16506 16498>,
+ <24332 17928 16752 16586 16506 16498>;
+ };
+
+ qcom,pc-temp-y5-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <17385 18969 19820 18348 20163 15959>,
+ <17747 18838 19450 18890 20657 19132>,
+ <18103 18812 19205 19190 21127 22137>,
+ <18411 18852 19060 19305 21522 24662>,
+ <18626 18918 18991 19291 21795 26391>,
+ <18705 18971 18974 19205 21896 27007>,
+ <18629 19094 19073 18964 21813 26331>,
+ <18510 19255 19222 18609 21627 25304>,
+ <18766 19163 19149 18291 21388 24842>,
+ <20163 18555 18614 17964 21017 24218>,
+ <21032 18009 18042 17605 20541 23551>,
+ <19032 17765 17592 16853 19821 22949>,
+ <16117 17560 17120 16095 18943 22277>,
+ <16345 17065 16488 16048 18051 21384>,
+ <19627 15838 15525 16241 17057 20196>,
+ <21566 15288 15054 16327 16646 19365>,
+ <21325 17934 15379 15963 16689 18762>,
+ <20982 21635 16106 15532 16771 18242>,
+ <21191 22355 17495 15688 16847 18058>,
+ <22316 22435 20149 16465 16869 17992>,
+ <23224 22550 21963 17525 17119 18301>,
+ <23686 22921 22848 19857 19274 19217>,
+ <23988 23459 23408 22065 21698 20457>,
+ <23290 23862 23498 22361 21910 21812>,
+ <19618 24215 23492 22200 21660 23372>,
+ <16438 24526 23534 22071 21408 23966>,
+ <14775 24905 23990 22050 21155 23476>,
+ <13666 25190 24552 22075 21047 22545>,
+ <13635 24764 24798 22051 21119 21378>,
+ <13849 22890 24942 21876 21068 19896>,
+ <13996 20838 25126 21761 20694 19265>,
+ <14033 18639 25610 21706 19522 19158>,
+ <14060 16889 26149 21672 18549 19111>,
+ <14124 17260 26121 21984 18968 19337>,
+ <14308 19696 25472 22832 20290 20169>,
+ <14508 21521 24816 23852 21110 20787>,
+ <14746 22141 24379 25326 21478 20975>,
+ <14986 22550 23907 26231 21632 21128>,
+ <15179 22752 23025 24735 21694 21438>,
+ <15372 22757 21838 22015 22081 22256>,
+ <15402 22360 21056 21454 22681 23441>,
+ <14907 20259 20513 22055 23749 25248>,
+ <14397 17852 19989 21633 24797 27697>,
+ <14093 15614 19667 21203 26044 30188>,
+ <13935 14761 20276 22289 27496 29447>,
+ <13951 14682 20221 21232 22757 27736>,
+ <13926 14690 18886 19253 22810 27775>,
+ <14234 14424 17632 18735 22875 24541>,
+ <14603 14818 17328 19657 22999 21351>,
+ <13616 15527 17751 21342 20705 20460>,
+ <12552 15663 18495 22607 27375 29585>,
+ <11145 14831 17455 22804 28646 29386>,
+ <9957 13010 16230 23779 29324 28727>,
+ <9195 10486 14924 24477 27339 28153>,
+ <9195 10486 14924 24477 27339 28153>,
+ <9195 10486 14924 24477 27339 28153>;
+ };
+
+ qcom,pc-temp-y6-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <5494 5203 5060 4960 4929 4921>,
+ <5509 5209 5061 4960 4929 4921>,
+ <5520 5213 5060 4959 4928 4921>,
+ <5526 5215 5059 4959 4928 4921>,
+ <5530 5216 5058 4958 4928 4921>,
+ <5531 5216 5057 4958 4928 4921>,
+ <5527 5214 5055 4958 4928 4921>,
+ <5521 5210 5053 4958 4929 4922>,
+ <5521 5207 5051 4958 4929 4922>,
+ <5525 5205 5050 4959 4930 4923>,
+ <5530 5204 5049 4959 4931 4923>,
+ <5532 5203 5050 4960 4931 4924>,
+ <5535 5204 5052 4962 4932 4925>,
+ <5541 5208 5055 4963 4934 4926>,
+ <5556 5221 5060 4966 4935 4927>,
+ <5563 5231 5066 4969 4937 4928>,
+ <5536 5233 5073 4973 4939 4930>,
+ <5494 5234 5079 4978 4942 4932>,
+ <5478 5229 5079 4985 4947 4935>,
+ <5470 5207 5074 4993 4954 4941>,
+ <5463 5187 5068 4996 4956 4943>,
+ <5453 5173 5053 4982 4948 4937>,
+ <5444 5162 5036 4966 4938 4928>,
+ <5437 5156 5028 4959 4933 4925>,
+ <5431 5152 5023 4954 4929 4922>,
+ <5429 5150 5021 4953 4928 4922>,
+ <5436 5149 5021 4953 4928 4922>,
+ <5449 5148 5022 4954 4928 4922>,
+ <5463 5146 5023 4955 4929 4923>,
+ <5480 5145 5024 4957 4931 4923>,
+ <5500 5145 5025 4959 4933 4925>,
+ <5522 5150 5026 4961 4934 4927>,
+ <5546 5159 5026 4963 4936 4929>,
+ <5573 5171 5027 4965 4938 4930>,
+ <5604 5188 5027 4967 4940 4931>,
+ <5637 5207 5028 4967 4940 4931>,
+ <5673 5229 5032 4964 4936 4927>,
+ <5711 5253 5039 4959 4931 4924>,
+ <5753 5277 5046 4956 4930 4923>,
+ <5798 5302 5053 4953 4929 4924>,
+ <5845 5328 5061 4953 4929 4924>,
+ <5892 5353 5072 4955 4928 4924>,
+ <5947 5381 5086 4959 4928 4924>,
+ <6021 5417 5102 4961 4927 4922>,
+ <6115 5463 5120 4962 4926 4920>,
+ <6200 5508 5125 4964 4928 4922>,
+ <6283 5549 5138 4968 4931 4925>,
+ <6392 5602 5160 4974 4934 4929>,
+ <6541 5672 5190 4983 4941 4939>,
+ <6922 5760 5227 4983 4941 4930>,
+ <7615 5860 5251 4980 4931 4924>,
+ <8825 6039 5300 4988 4934 4926>,
+ <11227 6535 5388 5002 4940 4931>,
+ <16611 7839 5546 5027 4956 4948>,
+ <16611 7839 5546 5027 4956 4948>,
+ <16611 7839 5546 5027 4956 4948>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-atl466271_3300mAh.dtsi b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-atl466271_3300mAh.dtsi
new file mode 100755
index 0000000..456c17bc
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-atl466271_3300mAh.dtsi
@@ -0,0 +1,1041 @@
+qcom,ATL466271_3300mAh {
+ /* ATL466271_3300mAh_averaged_MasterSlave_Jun12th2019 */
+ qcom,max-voltage-uv = <4400000>;
+ qcom,fg-cc-cv-threshold-uv = <4390000>;
+ qcom,fastchg-current-ma = <8000>;
+ qcom,batt-id-kohm = <24>;
+ qcom,battery-beta = <4250>;
+ qcom,battery-therm-kohm = <100>;
+ qcom,battery-type =
+ "ATL466271_3300mAh_averaged_MasterSlave_Jun12th2019";
+ qcom,qg-batt-profile-ver = <100>;
+
+ qcom,jeita-fcc-ranges = <0 100 1600000
+ 101 200 3200000
+ 201 450 8000000
+ 451 550 1600000>;
+
+ qcom,jeita-fv-ranges = <0 100 4400000
+ 101 200 4400000
+ 201 450 4400000
+ 451 550 4050000>;
+
+ qcom,step-chg-ranges = <3500000 4000000 8000000
+ 4000001 4200000 6000000
+ 4200001 4400000 4000000>;
+ qcom,ocv-based-step-chg;
+
+ /* COOL = 10 degc, WARM = 45 degC */
+ qcom,jeita-soft-thresholds = <0x4ccc 0x20b8>;
+ /* COLD = 0 degC, HOT = 55 degC*/
+ qcom,jeita-hard-thresholds = <0x58cd 0x181d>;
+ /* COOL hys = 13 degC, WARM hys = 42 degC */
+ qcom,jeita-soft-hys-thresholds = <0x48d4 0x23c0>;
+ qcom,jeita-soft-fcc-ua = <1600000 1600000>;
+ qcom,jeita-soft-fv-uv = <4400000 4050000>;
+
+ qcom,fcc1-temp-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-data = <3191 3260 3320 3354 3366>;
+ };
+
+ qcom,fcc2-temp-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-data = <3307 3309 3324 3332 3330 3326>;
+ };
+
+ qcom,pc-temp-v1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <43710 43825 43909 43937 43942>,
+ <43473 43605 43706 43721 43723>,
+ <43237 43380 43489 43509 43510>,
+ <43003 43150 43267 43294 43299>,
+ <42775 42918 43038 43070 43079>,
+ <42550 42687 42804 42837 42850>,
+ <42328 42457 42573 42606 42620>,
+ <42109 42230 42341 42375 42390>,
+ <41894 42008 42113 42145 42161>,
+ <41684 41789 41886 41917 41933>,
+ <41476 41574 41663 41690 41705>,
+ <41278 41360 41446 41467 41481>,
+ <41103 41159 41232 41247 41261>,
+ <40943 40987 41027 41035 41047>,
+ <40756 40823 40831 40833 40840>,
+ <40499 40625 40638 40639 40642>,
+ <40235 40371 40434 40442 40448>,
+ <40047 40136 40224 40241 40259>,
+ <39905 39978 40039 40053 40076>,
+ <39770 39845 39893 39894 39909>,
+ <39637 39668 39742 39742 39748>,
+ <39498 39402 39527 39546 39554>,
+ <39319 39159 39260 39286 39299>,
+ <39057 39018 39056 39062 39070>,
+ <38841 38914 38916 38909 38913>,
+ <38748 38814 38798 38783 38786>,
+ <38688 38714 38686 38668 38667>,
+ <38628 38621 38584 38566 38559>,
+ <38566 38536 38491 38471 38460>,
+ <38504 38459 38406 38380 38367>,
+ <38445 38391 38330 38297 38282>,
+ <38388 38330 38261 38223 38205>,
+ <38337 38276 38199 38156 38134>,
+ <38292 38228 38143 38095 38068>,
+ <38251 38187 38095 38043 38009>,
+ <38214 38146 38049 37992 37951>,
+ <38182 38111 38004 37933 37881>,
+ <38143 38071 37958 37869 37800>,
+ <38074 38006 37895 37793 37711>,
+ <37974 37903 37802 37697 37614>,
+ <37864 37788 37692 37587 37506>,
+ <37736 37663 37571 37457 37376>,
+ <37592 37522 37433 37310 37228>,
+ <37427 37351 37270 37152 37071>,
+ <37293 37218 37135 37037 36964>,
+ <37218 37148 37061 36976 36918>,
+ <37197 37127 37043 36958 36899>,
+ <37176 37114 37027 36945 36884>,
+ <37152 37086 37005 36915 36845>,
+ <37053 36954 36879 36723 36623>,
+ <36674 36578 36526 36347 36242>,
+ <36195 36086 36041 35859 35751>,
+ <35574 35449 35427 35229 35116>,
+ <34729 34574 34574 34362 34242>,
+ <33401 33172 33225 32989 32851>,
+ <30000 30000 30000 30000 30000>;
+ };
+
+ qcom,pc-temp-v2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <43975 43950 43930 43905 43855 43835>,
+ <43614 43647 43667 43663 43617 43596>,
+ <43279 43361 43410 43424 43383 43362>,
+ <42972 43092 43162 43188 43150 43130>,
+ <42688 42841 42921 42956 42921 42903>,
+ <42432 42596 42682 42724 42691 42675>,
+ <42220 42350 42446 42490 42458 42443>,
+ <42020 42110 42212 42257 42225 42210>,
+ <41772 41881 41982 42027 41995 41980>,
+ <41458 41662 41755 41799 41766 41751>,
+ <41235 41448 41531 41574 41541 41526>,
+ <41153 41235 41310 41352 41318 41305>,
+ <41088 41026 41094 41134 41100 41087>,
+ <40904 40832 40899 40930 40893 40877>,
+ <40447 40653 40720 40736 40694 40672>,
+ <40034 40458 40525 40537 40495 40472>,
+ <39788 40221 40292 40319 40288 40277>,
+ <39585 39967 40050 40106 40087 40088>,
+ <39406 39734 39841 39926 39912 39913>,
+ <39248 39515 39652 39767 39754 39750>,
+ <39074 39305 39456 39583 39572 39566>,
+ <38832 39100 39232 39336 39328 39323>,
+ <38584 38908 39017 39089 39082 39080>,
+ <38426 38747 38845 38906 38903 38901>,
+ <38310 38609 38699 38752 38755 38754>,
+ <38226 38477 38570 38621 38627 38625>,
+ <38164 38335 38453 38506 38513 38511>,
+ <38113 38204 38348 38403 38410 38407>,
+ <38062 38112 38253 38308 38314 38311>,
+ <38014 38043 38166 38221 38224 38220>,
+ <37968 37988 38082 38140 38142 38137>,
+ <37925 37942 37996 38064 38067 38062>,
+ <37882 37901 37921 37993 37995 37989>,
+ <37836 37861 37870 37925 37926 37914>,
+ <37789 37823 37831 37859 37858 37837>,
+ <37739 37781 37790 37789 37775 37745>,
+ <37688 37735 37747 37715 37668 37625>,
+ <37631 37682 37698 37637 37559 37505>,
+ <37562 37619 37632 37559 37469 37410>,
+ <37480 37542 37547 37477 37386 37325>,
+ <37385 37449 37447 37382 37290 37228>,
+ <37268 37321 37322 37269 37178 37113>,
+ <37144 37177 37181 37135 37045 36979>,
+ <37027 37026 37025 36987 36895 36830>,
+ <36932 36918 36939 36908 36841 36784>,
+ <36855 36857 36899 36885 36818 36762>,
+ <36812 36827 36875 36867 36801 36749>,
+ <36761 36786 36846 36843 36779 36722>,
+ <36679 36721 36775 36779 36692 36597>,
+ <36475 36551 36546 36552 36390 36264>,
+ <36066 36173 36127 36133 35937 35797>,
+ <35499 35647 35579 35596 35370 35211>,
+ <34766 34968 34863 34909 34633 34453>,
+ <33784 34024 33935 33996 33658 33408>,
+ <32412 32711 32567 32650 31840 31311>,
+ <28215 28831 27522 28579 27814 27518>;
+ };
+
+ qcom,pc-temp-z1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <11770 11167 10508 10200 10123>,
+ <11802 11193 10579 10273 10190>,
+ <11806 11200 10581 10275 10191>,
+ <11805 11183 10570 10275 10191>,
+ <11792 11170 10557 10270 10189>,
+ <11777 11154 10545 10264 10185>,
+ <11765 11131 10537 10259 10182>,
+ <11755 11116 10530 10255 10180>,
+ <11743 11111 10524 10251 10178>,
+ <11735 11108 10520 10250 10177>,
+ <11730 11108 10517 10249 10175>,
+ <11726 11108 10514 10248 10174>,
+ <11721 11108 10512 10248 10173>,
+ <11717 11105 10511 10247 10173>,
+ <11714 11099 10510 10247 10172>,
+ <11704 11097 10508 10245 10172>,
+ <11693 11095 10507 10245 10172>,
+ <11693 11095 10506 10245 10172>,
+ <11704 11097 10506 10246 10174>,
+ <11714 11101 10509 10248 10175>,
+ <11726 11106 10513 10252 10177>,
+ <11741 11114 10517 10254 10179>,
+ <11744 11122 10522 10256 10181>,
+ <11737 11128 10527 10258 10183>,
+ <11732 11133 10532 10260 10185>,
+ <11733 11134 10537 10264 10187>,
+ <11737 11132 10542 10267 10190>,
+ <11740 11131 10548 10272 10194>,
+ <11743 11133 10553 10276 10197>,
+ <11747 11137 10558 10280 10200>,
+ <11750 11142 10564 10285 10203>,
+ <11754 11154 10571 10288 10206>,
+ <11758 11165 10579 10292 10209>,
+ <11769 11165 10584 10296 10213>,
+ <11781 11161 10589 10301 10217>,
+ <11789 11159 10594 10306 10221>,
+ <11796 11169 10600 10312 10225>,
+ <11803 11182 10606 10317 10229>,
+ <11809 11185 10612 10322 10233>,
+ <11816 11186 10619 10326 10236>,
+ <11819 11188 10625 10330 10239>,
+ <11821 11199 10630 10335 10243>,
+ <11823 11208 10636 10340 10246>,
+ <11826 11206 10642 10342 10248>,
+ <11820 11215 10648 10344 10249>,
+ <11820 11220 10655 10347 10250>,
+ <11830 11225 10660 10348 10252>,
+ <11816 11232 10658 10350 10253>,
+ <11831 11224 10662 10354 10257>,
+ <11856 11221 10671 10358 10261>,
+ <11833 11233 10673 10362 10265>,
+ <11848 11251 10678 10368 10270>,
+ <11885 11257 10688 10374 10275>,
+ <11898 11288 10702 10382 10282>,
+ <11898 11288 10702 10382 10282>,
+ <11898 11288 10702 10382 10282>;
+ };
+
+ qcom,pc-temp-z2-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <9894 9757 10034 10106 10345>,
+ <9913 9932 10014 10164 10226>,
+ <9939 10003 10052 10124 10214>,
+ <9961 9993 10069 10079 10205>,
+ <9956 9975 10063 10081 10205>,
+ <9932 9968 10050 10100 10208>,
+ <9909 9964 10028 10116 10214>,
+ <9894 9962 9988 10127 10224>,
+ <9882 9965 9971 10137 10239>,
+ <9879 9971 9979 10146 10256>,
+ <9887 9975 9990 10155 10278>,
+ <9899 9978 9996 10160 10293>,
+ <9908 9983 10003 10160 10302>,
+ <9915 10111 10010 10159 10307>,
+ <9923 10305 10017 10164 10303>,
+ <9937 10319 10021 10171 10296>,
+ <9949 10152 10020 10170 10294>,
+ <9950 10028 10015 10163 10294>,
+ <9944 10019 10013 10158 10295>,
+ <9940 10013 10022 10178 10307>,
+ <9940 10015 10039 10212 10331>,
+ <9943 10049 10081 10217 10334>,
+ <9948 10079 10155 10205 10297>,
+ <9962 10074 10180 10185 10246>,
+ <9973 10059 10141 10123 10180>,
+ <9974 10052 10094 10050 10113>,
+ <9972 10052 10070 10041 10102>,
+ <9972 10053 10053 10046 10113>,
+ <9973 10046 10049 10054 10127>,
+ <9975 10033 10060 10064 10141>,
+ <9976 10029 10075 10077 10158>,
+ <9978 10038 10091 10098 10180>,
+ <9980 10052 10108 10129 10208>,
+ <9983 10064 10127 10163 10243>,
+ <9988 10077 10148 10206 10293>,
+ <9992 10087 10168 10244 10345>,
+ <9997 10095 10183 10263 10380>,
+ <10003 10102 10195 10276 10409>,
+ <10012 10114 10208 10287 10417>,
+ <10023 10130 10226 10298 10403>,
+ <10024 10137 10237 10306 10390>,
+ <10014 10120 10220 10308 10389>,
+ <10008 10106 10192 10307 10384>,
+ <10006 10106 10186 10298 10361>,
+ <10058 10124 10199 10299 10329>,
+ <10061 10124 10204 10309 10360>,
+ <10054 10113 10214 10301 10359>,
+ <10052 10093 10207 10352 10392>,
+ <10039 10104 10227 10397 10452>,
+ <9972 10155 10228 10268 10254>,
+ <10081 10129 10171 10193 10218>,
+ <10034 10095 10128 10161 10175>,
+ <9993 10043 10103 10128 10146>,
+ <9836 9993 10057 10083 10063>,
+ <9836 9993 10057 10083 10063>,
+ <9836 9993 10057 10083 10063>;
+ };
+
+ qcom,pc-temp-z3-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <19500 19444 19370 19351 19313>,
+ <19626 19520 19402 19353 19340>,
+ <19677 19560 19426 19362 19348>,
+ <19706 19570 19435 19369 19353>,
+ <19708 19575 19432 19369 19353>,
+ <19704 19574 19427 19367 19351>,
+ <19701 19566 19421 19364 19348>,
+ <19699 19557 19414 19360 19345>,
+ <19697 19549 19409 19355 19341>,
+ <19692 19541 19406 19353 19340>,
+ <19680 19535 19404 19352 19339>,
+ <19665 19529 19401 19351 19338>,
+ <19649 19525 19397 19351 19337>,
+ <19632 19526 19395 19351 19336>,
+ <19625 19529 19394 19350 19335>,
+ <19632 19529 19394 19349 19331>,
+ <19639 19523 19394 19348 19329>,
+ <19638 19517 19394 19347 19327>,
+ <19628 19510 19394 19345 19325>,
+ <19621 19502 19390 19341 19323>,
+ <19618 19501 19385 19335 19320>,
+ <19616 19515 19389 19337 19322>,
+ <19618 19527 19402 19355 19339>,
+ <19632 19520 19415 19369 19354>,
+ <19643 19503 19428 19376 19357>,
+ <19638 19499 19437 19380 19359>,
+ <19626 19519 19437 19380 19359>,
+ <19619 19539 19434 19373 19356>,
+ <19618 19539 19430 19368 19353>,
+ <19618 19535 19425 19366 19350>,
+ <19619 19530 19418 19364 19347>,
+ <19621 19524 19413 19362 19343>,
+ <19622 19517 19409 19358 19340>,
+ <19621 19512 19405 19354 19336>,
+ <19618 19508 19401 19349 19331>,
+ <19615 19505 19398 19346 19328>,
+ <19611 19503 19397 19346 19330>,
+ <19607 19500 19396 19347 19336>,
+ <19603 19497 19395 19348 19339>,
+ <19597 19494 19393 19350 19339>,
+ <19593 19490 19390 19351 19339>,
+ <19592 19487 19386 19352 19339>,
+ <19588 19483 19383 19353 19339>,
+ <19579 19481 19385 19354 19341>,
+ <19543 19466 19382 19350 19341>,
+ <19529 19450 19368 19337 19321>,
+ <19525 19448 19365 19331 19318>,
+ <19523 19438 19363 19324 19312>,
+ <19489 19434 19359 19320 19312>,
+ <19401 19438 19363 19342 19330>,
+ <19514 19442 19376 19345 19331>,
+ <19508 19444 19378 19345 19332>,
+ <19506 19447 19381 19346 19334>,
+ <19479 19451 19379 19353 19342>,
+ <19479 19451 19379 19353 19342>,
+ <19479 19451 19379 19353 19342>;
+ };
+
+ qcom,pc-temp-z4-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <15847 15406 14998 14784 14808>,
+ <15949 15355 15044 14878 14825>,
+ <15794 15280 14959 14838 14798>,
+ <15524 15160 14880 14782 14745>,
+ <15335 15024 14821 14755 14725>,
+ <15199 14932 14776 14735 14717>,
+ <15092 14862 14760 14724 14712>,
+ <15007 14818 14752 14719 14708>,
+ <14938 14795 14745 14715 14704>,
+ <14892 14781 14736 14710 14700>,
+ <14861 14774 14728 14704 14696>,
+ <14839 14771 14722 14699 14691>,
+ <14823 14768 14716 14693 14687>,
+ <14809 14746 14714 14688 14682>,
+ <14805 14717 14714 14683 14677>,
+ <14837 14717 14714 14679 14672>,
+ <14877 14763 14713 14676 14669>,
+ <14877 14798 14707 14672 14666>,
+ <14845 14782 14700 14669 14663>,
+ <14819 14748 14691 14667 14660>,
+ <14809 14748 14684 14665 14657>,
+ <14802 14849 14717 14676 14662>,
+ <14817 14940 14810 14736 14713>,
+ <14926 14941 14844 14773 14752>,
+ <15018 14932 14810 14755 14738>,
+ <15011 14916 14769 14725 14711>,
+ <14979 14870 14751 14712 14699>,
+ <14949 14826 14739 14706 14693>,
+ <14922 14811 14733 14701 14688>,
+ <14898 14803 14730 14696 14684>,
+ <14881 14800 14728 14693 14681>,
+ <14867 14800 14728 14691 14678>,
+ <14859 14800 14727 14689 14675>,
+ <14855 14800 14728 14689 14674>,
+ <14853 14801 14730 14689 14673>,
+ <14850 14801 14732 14690 14672>,
+ <14845 14800 14733 14694 14676>,
+ <14843 14799 14734 14701 14687>,
+ <14846 14800 14735 14703 14692>,
+ <14851 14805 14736 14701 14691>,
+ <14852 14807 14737 14699 14691>,
+ <14843 14799 14733 14696 14691>,
+ <14831 14786 14724 14692 14690>,
+ <14819 14776 14719 14690 14690>,
+ <14767 14740 14703 14678 14676>,
+ <14740 14710 14680 14653 14645>,
+ <14731 14703 14668 14647 14637>,
+ <14725 14696 14656 14637 14627>,
+ <14741 14692 14651 14632 14622>,
+ <14832 14699 14662 14641 14641>,
+ <14739 14707 14661 14645 14646>,
+ <14748 14705 14661 14648 14648>,
+ <14752 14704 14661 14650 14649>,
+ <14789 14699 14665 14647 14645>,
+ <14789 14699 14665 14647 14645>,
+ <14789 14699 14665 14647 14645>;
+ };
+
+ qcom,pc-temp-z5-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <11792 12279 13535 15414 14204>,
+ <13001 13808 15235 16383 17416>,
+ <13841 15100 16456 17237 19077>,
+ <14514 16104 17533 18315 20517>,
+ <15113 17028 18754 19244 21245>,
+ <15689 18181 19650 20146 21743>,
+ <16375 19593 19683 20412 21915>,
+ <17353 20752 19475 20064 21544>,
+ <18570 21607 19385 19726 21069>,
+ <19714 22312 19837 19833 21119>,
+ <20922 22624 20368 20227 21592>,
+ <21654 22649 20366 20704 22135>,
+ <21494 22792 20190 21409 22819>,
+ <21073 24392 20127 22129 23478>,
+ <21017 26764 20584 22757 23767>,
+ <22555 26941 21094 23386 23725>,
+ <24349 24455 21214 23801 23655>,
+ <24216 22548 21439 24313 23878>,
+ <22900 22853 21828 24599 24211>,
+ <22166 23930 23250 24474 24553>,
+ <23067 25813 24579 24129 24960>,
+ <25218 31144 24161 23371 24839>,
+ <27733 35337 22682 21648 23111>,
+ <31628 31478 21716 20674 21705>,
+ <34089 22242 21182 20941 21493>,
+ <31865 19114 20879 21395 21408>,
+ <26536 20884 21549 21643 21618>,
+ <23985 23280 23503 21875 22646>,
+ <23503 25063 24966 22255 23786>,
+ <23364 26728 25863 23569 24665>,
+ <23874 27767 26627 25316 25537>,
+ <25339 28404 27366 26549 26565>,
+ <26580 28812 28051 27647 27783>,
+ <27299 28952 28637 28369 28438>,
+ <27859 29013 29244 28922 28605>,
+ <28127 28980 29596 29269 28749>,
+ <28121 28632 29354 28928 29008>,
+ <28035 28071 28613 27970 29397>,
+ <28032 27480 27672 27629 29838>,
+ <28024 26731 26146 27677 30769>,
+ <27889 25936 24626 27779 31609>,
+ <27436 24934 23369 28434 31801>,
+ <26929 24388 22499 29368 31887>,
+ <26421 24450 22608 28936 31937>,
+ <27988 25663 22852 26365 31185>,
+ <27430 25453 21972 22626 21099>,
+ <26554 25602 22352 22600 22211>,
+ <26806 23914 24361 22775 24450>,
+ <23478 23641 24736 23227 28936>,
+ <18946 23905 22228 28971 29716>,
+ <23561 21707 23990 27451 26335>,
+ <20333 21474 23601 25150 24619>,
+ <18967 20996 23606 23367 22997>,
+ <16796 21104 21653 24495 23716>,
+ <16796 21104 21653 24495 23716>,
+ <16796 21104 21653 24495 23716>;
+ };
+
+ qcom,pc-temp-z6-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <15776 15081 14574 14403 14378>,
+ <15822 15066 14611 14457 14412>,
+ <15728 15042 14587 14444 14404>,
+ <15561 14985 14560 14425 14386>,
+ <15434 14901 14531 14412 14376>,
+ <15332 14840 14504 14402 14371>,
+ <15250 14790 14491 14394 14367>,
+ <15184 14755 14482 14389 14362>,
+ <15130 14736 14475 14384 14359>,
+ <15088 14723 14469 14380 14356>,
+ <15057 14715 14464 14377 14353>,
+ <15033 14710 14459 14374 14350>,
+ <15014 14704 14454 14371 14348>,
+ <14997 14693 14451 14368 14345>,
+ <14991 14680 14450 14366 14342>,
+ <15002 14679 14449 14363 14338>,
+ <15017 14691 14448 14361 14335>,
+ <15016 14701 14446 14359 14333>,
+ <14999 14693 14443 14357 14331>,
+ <14987 14676 14438 14354 14328>,
+ <14985 14676 14433 14350 14326>,
+ <14985 14729 14451 14357 14329>,
+ <14996 14777 14500 14394 14362>,
+ <15054 14775 14519 14417 14387>,
+ <15101 14767 14512 14412 14383>,
+ <15097 14759 14503 14404 14374>,
+ <15080 14752 14497 14398 14368>,
+ <15067 14746 14492 14393 14365>,
+ <15057 14742 14488 14389 14362>,
+ <15050 14739 14484 14386 14358>,
+ <15047 14737 14482 14384 14356>,
+ <15045 14735 14480 14382 14353>,
+ <15045 14734 14478 14379 14350>,
+ <15046 14734 14478 14378 14347>,
+ <15047 14735 14478 14376 14345>,
+ <15049 14736 14479 14375 14343>,
+ <15050 14738 14480 14377 14345>,
+ <15052 14740 14481 14381 14354>,
+ <15055 14743 14482 14384 14358>,
+ <15061 14747 14484 14384 14358>,
+ <15065 14749 14485 14385 14359>,
+ <15066 14747 14482 14385 14359>,
+ <15067 14746 14478 14385 14360>,
+ <15067 14745 14478 14385 14361>,
+ <15047 14732 14473 14378 14356>,
+ <15035 14716 14457 14362 14333>,
+ <15030 14712 14451 14356 14327>,
+ <15027 14706 14445 14348 14320>,
+ <15020 14704 14442 14344 14318>,
+ <15023 14714 14450 14360 14336>,
+ <15046 14724 14459 14366 14341>,
+ <15055 14730 14462 14368 14344>,
+ <15068 14739 14467 14371 14347>,
+ <15088 14751 14472 14376 14351>,
+ <15088 14751 14472 14376 14351>,
+ <15088 14751 14472 14376 14351>;
+ };
+
+ qcom,pc-temp-y1-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <5821 5347 5037 4674 4481 4427>,
+ <5843 5351 5036 4672 4484 4429>,
+ <5865 5355 5035 4670 4485 4430>,
+ <5883 5361 5033 4667 4485 4430>,
+ <5897 5365 5031 4664 4484 4431>,
+ <5903 5367 5030 4660 4482 4431>,
+ <5900 5367 5025 4656 4477 4430>,
+ <5895 5365 5019 4650 4473 4429>,
+ <5896 5364 5014 4646 4472 4427>,
+ <5901 5359 5010 4643 4472 4425>,
+ <5903 5356 5008 4640 4472 4423>,
+ <5904 5358 5011 4637 4470 4422>,
+ <5908 5361 5015 4634 4468 4422>,
+ <5911 5361 5013 4632 4467 4421>,
+ <5920 5359 5004 4630 4465 4419>,
+ <5925 5358 5000 4629 4464 4419>,
+ <5922 5365 5003 4629 4464 4419>,
+ <5917 5374 5007 4629 4464 4419>,
+ <5917 5376 5008 4629 4464 4419>,
+ <5916 5373 5005 4630 4465 4419>,
+ <5914 5372 5003 4631 4465 4419>,
+ <5914 5377 5004 4633 4467 4420>,
+ <5916 5382 5005 4635 4469 4422>,
+ <5917 5383 5005 4638 4469 4422>,
+ <5917 5382 5006 4640 4469 4422>,
+ <5917 5382 5008 4643 4470 4423>,
+ <5915 5390 5013 4646 4472 4423>,
+ <5911 5400 5019 4650 4474 4424>,
+ <5907 5401 5024 4654 4476 4426>,
+ <5900 5398 5029 4659 4479 4428>,
+ <5896 5395 5032 4664 4481 4430>,
+ <5906 5395 5032 4669 4484 4431>,
+ <5922 5398 5032 4675 4487 4432>,
+ <5932 5401 5035 4679 4490 4434>,
+ <5943 5403 5043 4682 4493 4437>,
+ <5946 5405 5047 4686 4496 4440>,
+ <5933 5401 5047 4691 4499 4442>,
+ <5912 5395 5048 4695 4501 4444>,
+ <5901 5393 5053 4701 4504 4445>,
+ <5892 5393 5061 4707 4506 4446>,
+ <5887 5393 5065 4710 4509 4448>,
+ <5896 5394 5064 4713 4511 4451>,
+ <5900 5398 5066 4715 4513 4451>,
+ <5883 5418 5079 4717 4515 4451>,
+ <5915 5410 5075 4725 4518 4454>,
+ <5906 5399 5089 4726 4521 4456>,
+ <5899 5402 5088 4727 4519 4457>,
+ <5893 5400 5081 4734 4522 4457>,
+ <5894 5416 5082 4737 4521 4457>,
+ <5893 5422 5089 4735 4523 4458>,
+ <5951 5403 5099 4738 4525 4460>,
+ <5978 5411 5100 4752 4529 4462>,
+ <5943 5406 5107 4748 4534 4464>,
+ <5955 5420 5108 4757 4536 4469>,
+ <5955 5420 5108 4757 4536 4469>,
+ <5955 5420 5108 4757 4536 4469>;
+ };
+
+ qcom,pc-temp-y2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <10091 10247 10509 10767 10785 10927>,
+ <10085 10259 10500 10740 10807 10958>,
+ <10082 10274 10489 10711 10818 10974>,
+ <10082 10288 10479 10684 10821 10978>,
+ <10084 10301 10470 10661 10818 10974>,
+ <10088 10309 10463 10643 10813 10967>,
+ <10129 10314 10458 10630 10787 10948>,
+ <10196 10318 10454 10619 10754 10920>,
+ <10242 10317 10452 10606 10748 10891>,
+ <10309 10310 10448 10589 10749 10854>,
+ <10343 10306 10446 10578 10750 10833>,
+ <10348 10349 10451 10581 10744 10834>,
+ <10361 10433 10462 10588 10735 10837>,
+ <10354 10516 10482 10588 10734 10833>,
+ <10267 10617 10525 10585 10733 10822>,
+ <10196 10671 10577 10591 10733 10816>,
+ <9993 10677 10646 10622 10733 10824>,
+ <9724 10679 10709 10670 10734 10837>,
+ <9677 10682 10732 10741 10732 10847>,
+ <9671 10689 10745 10841 10729 10857>,
+ <9668 10692 10750 10877 10736 10873>,
+ <9666 10695 10747 10828 10833 10914>,
+ <9664 10701 10743 10775 10940 10965>,
+ <9663 10698 10754 10784 10956 10999>,
+ <9661 10676 10777 10824 10960 11030>,
+ <9660 10640 10792 10857 10965 11054>,
+ <9659 10551 10798 10880 10972 11078>,
+ <9658 10416 10805 10900 10980 11102>,
+ <9657 10287 10820 10916 10994 11121>,
+ <9656 10134 10847 10930 11021 11137>,
+ <9656 10010 10858 10948 11048 11156>,
+ <9655 9913 10844 10989 11077 11185>,
+ <9655 9833 10824 11022 11105 11210>,
+ <9654 9791 10807 11021 11137 11220>,
+ <9654 9761 10786 11011 11170 11226>,
+ <9654 9737 10768 11005 11177 11228>,
+ <9654 9716 10753 11011 11139 11200>,
+ <9654 9699 10737 11017 11102 11170>,
+ <9653 9689 10712 11012 11096 11161>,
+ <9653 9681 10675 10996 11093 11144>,
+ <9653 9675 10616 10980 11081 11118>,
+ <9653 9671 10491 10961 11032 11066>,
+ <9653 9667 10377 10936 11009 11056>,
+ <9653 9664 10284 10902 11002 11096>,
+ <9653 9661 10205 10867 11000 10997>,
+ <9652 9659 10189 10820 10935 10941>,
+ <9652 9659 10170 10842 10880 10907>,
+ <9652 9658 10266 10786 10907 10898>,
+ <9652 9657 10342 10819 10926 10908>,
+ <9652 9656 10250 10823 10875 10851>,
+ <9652 9655 10037 10750 10829 10802>,
+ <9652 9654 9972 10651 10750 10766>,
+ <9651 9653 9891 10735 10690 10675>,
+ <9650 9653 10171 10679 10569 10544>,
+ <9650 9653 10171 10679 10569 10544>,
+ <9650 9653 10171 10679 10569 10544>;
+ };
+
+ qcom,pc-temp-y3-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <14020 13485 13348 13290 13276 13269>,
+ <13912 13484 13350 13290 13276 13270>,
+ <13847 13482 13351 13290 13277 13271>,
+ <13814 13481 13352 13290 13277 13272>,
+ <13802 13479 13353 13290 13278 13274>,
+ <13800 13477 13353 13290 13278 13274>,
+ <13846 13474 13353 13290 13278 13275>,
+ <13915 13471 13353 13289 13279 13275>,
+ <13881 13472 13353 13290 13279 13275>,
+ <13646 13477 13352 13291 13279 13275>,
+ <13499 13480 13351 13292 13280 13275>,
+ <13535 13470 13351 13294 13280 13276>,
+ <13592 13454 13351 13296 13280 13277>,
+ <13605 13449 13352 13297 13281 13277>,
+ <13589 13442 13356 13297 13282 13277>,
+ <13574 13436 13358 13298 13282 13277>,
+ <13544 13434 13352 13298 13282 13277>,
+ <13507 13429 13343 13300 13283 13277>,
+ <13503 13421 13341 13301 13284 13278>,
+ <13510 13403 13340 13302 13285 13280>,
+ <13517 13385 13338 13303 13286 13281>,
+ <13521 13372 13331 13298 13282 13278>,
+ <13523 13361 13323 13291 13278 13275>,
+ <13523 13352 13319 13288 13277 13274>,
+ <13533 13345 13316 13286 13277 13273>,
+ <13553 13338 13314 13285 13276 13272>,
+ <13593 13320 13311 13285 13277 13273>,
+ <13646 13299 13309 13285 13277 13273>,
+ <13696 13288 13308 13285 13276 13273>,
+ <13750 13271 13307 13286 13276 13273>,
+ <13806 13266 13305 13286 13275 13273>,
+ <13866 13268 13303 13285 13275 13273>,
+ <13929 13271 13301 13285 13275 13272>,
+ <13994 13274 13301 13285 13275 13272>,
+ <14060 13278 13303 13284 13276 13272>,
+ <14134 13284 13305 13284 13277 13272>,
+ <14220 13295 13307 13283 13276 13273>,
+ <14312 13311 13309 13282 13275 13273>,
+ <14405 13332 13311 13282 13275 13273>,
+ <14501 13362 13312 13282 13276 13274>,
+ <14596 13393 13313 13282 13276 13274>,
+ <14687 13416 13313 13282 13277 13274>,
+ <14781 13443 13314 13283 13277 13274>,
+ <14884 13488 13317 13284 13276 13273>,
+ <14998 13565 13322 13285 13276 13274>,
+ <14988 13596 13326 13288 13278 13276>,
+ <15059 13649 13330 13289 13279 13277>,
+ <15152 13712 13339 13294 13283 13279>,
+ <15247 13784 13351 13296 13282 13277>,
+ <15340 13847 13352 13295 13280 13276>,
+ <15443 13922 13355 13295 13281 13277>,
+ <15627 14060 13367 13298 13284 13279>,
+ <15865 14258 13384 13304 13286 13283>,
+ <16661 14530 13427 13312 13291 13287>,
+ <16661 14530 13427 13312 13291 13287>,
+ <16661 14530 13427 13312 13291 13287>;
+ };
+
+ qcom,pc-temp-y4-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <18008 16999 16718 16500 16460 16456>,
+ <18072 17065 16719 16497 16459 16454>,
+ <18111 17109 16717 16493 16457 16452>,
+ <18131 17135 16714 16489 16455 16451>,
+ <18138 17148 16709 16486 16453 16449>,
+ <18139 17152 16703 16485 16453 16448>,
+ <18029 17137 16693 16486 16452 16448>,
+ <17863 17112 16683 16486 16452 16447>,
+ <17896 17097 16681 16488 16452 16448>,
+ <18235 17083 16680 16490 16454 16449>,
+ <18508 17077 16680 16492 16455 16450>,
+ <18619 17111 16683 16496 16457 16451>,
+ <18700 17180 16689 16501 16461 16452>,
+ <18607 17260 16712 16509 16466 16453>,
+ <18107 17384 16786 16522 16473 16457>,
+ <17766 17446 16846 16538 16481 16462>,
+ <17718 17379 16883 16554 16487 16468>,
+ <17687 17259 16908 16574 16496 16475>,
+ <17629 17174 16905 16613 16516 16490>,
+ <17534 17108 16880 16675 16554 16516>,
+ <17407 17042 16841 16697 16568 16526>,
+ <17159 16963 16746 16628 16535 16505>,
+ <16891 16889 16644 16542 16492 16476>,
+ <16806 16845 16607 16507 16473 16463>,
+ <16770 16818 16587 16484 16461 16454>,
+ <16755 16786 16580 16478 16457 16452>,
+ <16753 16727 16578 16479 16457 16452>,
+ <16753 16673 16578 16480 16457 16452>,
+ <16756 16669 16579 16483 16459 16453>,
+ <16763 16685 16581 16490 16462 16455>,
+ <16771 16697 16581 16497 16467 16458>,
+ <16783 16705 16558 16506 16473 16464>,
+ <16797 16717 16535 16512 16481 16470>,
+ <16813 16732 16538 16515 16488 16475>,
+ <16831 16753 16552 16517 16495 16479>,
+ <16846 16769 16568 16515 16495 16479>,
+ <16858 16781 16587 16493 16474 16465>,
+ <16869 16791 16601 16473 16454 16451>,
+ <16877 16794 16600 16470 16450 16451>,
+ <16883 16792 16599 16468 16449 16452>,
+ <16885 16788 16599 16469 16448 16452>,
+ <16876 16770 16608 16474 16449 16451>,
+ <16865 16757 16618 16479 16448 16448>,
+ <16860 16757 16628 16481 16442 16435>,
+ <16879 16761 16645 16484 16444 16435>,
+ <16891 16789 16652 16498 16455 16453>,
+ <16943 16827 16682 16511 16475 16497>,
+ <17014 16881 16733 16537 16536 16562>,
+ <17081 16976 16802 16590 16557 16530>,
+ <17089 17020 16800 16563 16478 16467>,
+ <17047 16991 16801 16554 16477 16469>,
+ <17042 17006 16834 16584 16500 16488>,
+ <17105 17082 16903 16649 16553 16544>,
+ <17555 17233 17100 16828 16767 16718>,
+ <17555 17233 17100 16828 16767 16718>,
+ <17555 17233 17100 16828 16767 16718>;
+ };
+
+ qcom,pc-temp-y5-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <11727 11942 13506 16264 17485 13743>,
+ <11187 12181 13834 16304 17713 15443>,
+ <10948 12440 14154 16154 17943 16969>,
+ <10946 12689 14439 15889 18142 18238>,
+ <11119 12897 14661 15580 18277 19164>,
+ <11403 13035 14792 15300 18315 19661>,
+ <12465 13100 14855 14911 18249 19739>,
+ <13822 13150 14864 14518 18113 19553>,
+ <13670 13301 14746 14395 17867 19106>,
+ <11695 13714 14420 14341 17361 18217>,
+ <10462 13958 14096 14326 16853 17639>,
+ <11501 13114 13863 14506 16406 17596>,
+ <13219 11865 13624 14722 15945 17611>,
+ <13884 11823 13278 14498 15435 17295>,
+ <13848 12774 12797 13693 14834 16535>,
+ <13691 13748 12589 13309 14470 15845>,
+ <13167 14554 12751 13334 14271 15143>,
+ <12586 15195 13107 13390 14142 14574>,
+ <13020 15258 13900 13564 14152 14504>,
+ <14413 15027 15523 14068 14254 14631>,
+ <15535 14881 16342 14723 14446 14876>,
+ <15575 14923 16444 15913 15152 15787>,
+ <15061 15014 16478 16911 16165 16899>,
+ <14339 15197 16434 16931 17201 17475>,
+ <12334 15627 16343 16746 18331 17902>,
+ <11314 15978 16268 16667 18791 18109>,
+ <11399 15505 16100 16581 18776 18180>,
+ <11512 14520 15934 16533 18615 18169>,
+ <11525 13737 16028 16730 18175 18053>,
+ <11550 12045 16380 17082 17340 17858>,
+ <11588 11352 16565 17187 16713 17565>,
+ <11718 11445 16382 17060 16198 16814>,
+ <11865 11550 16160 16944 15883 16183>,
+ <11908 11637 16198 17254 16375 16323>,
+ <11980 11737 16327 17954 17689 16949>,
+ <12075 11818 16423 18152 18505 17767>,
+ <12422 11915 16495 17982 18987 19240>,
+ <12794 12071 16540 17734 19303 20755>,
+ <12843 12334 16444 17425 19669 21829>,
+ <12812 12824 16116 17020 20264 22723>,
+ <12740 13086 15663 16654 20463 22879>,
+ <12356 12741 14862 16171 20541 22449>,
+ <11882 12264 14369 16034 20626 22711>,
+ <11570 11949 14152 16151 21020 24835>,
+ <11487 11951 14006 15816 18734 20674>,
+ <11662 11903 13943 16003 17805 20181>,
+ <11655 12101 13682 15426 17094 17583>,
+ <11840 12432 13801 16015 16324 15006>,
+ <12476 12948 14155 15430 14898 14594>,
+ <12752 13151 14323 16256 17791 17272>,
+ <12081 13073 14285 16869 17629 17625>,
+ <11734 12858 14199 16707 19166 17889>,
+ <11770 12567 13945 17145 18317 18429>,
+ <11976 12244 15223 16959 17784 17367>,
+ <11976 12244 15223 16959 17784 17367>,
+ <11976 12244 15223 16959 17784 17367>;
+ };
+
+ qcom,pc-temp-y6-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <6551 5600 5220 4990 4943 4930>,
+ <6534 5605 5216 4988 4942 4931>,
+ <6511 5605 5211 4986 4942 4931>,
+ <6488 5601 5205 4984 4942 4931>,
+ <6470 5594 5199 4983 4942 4932>,
+ <6461 5584 5193 4982 4942 4932>,
+ <6460 5570 5186 4981 4942 4932>,
+ <6461 5554 5179 4980 4942 4932>,
+ <6450 5545 5174 4981 4942 4932>,
+ <6403 5538 5169 4981 4942 4933>,
+ <6375 5535 5166 4982 4943 4933>,
+ <6433 5536 5165 4984 4943 4933>,
+ <6517 5539 5164 4987 4945 4934>,
+ <6504 5548 5169 4989 4946 4935>,
+ <6362 5577 5191 4993 4949 4936>,
+ <6258 5593 5206 4998 4951 4938>,
+ <6231 5576 5210 5003 4954 4939>,
+ <6212 5543 5212 5009 4956 4942>,
+ <6209 5514 5211 5021 4962 4946>,
+ <6205 5486 5203 5040 4974 4955>,
+ <6199 5459 5190 5046 4978 4958>,
+ <6156 5431 5159 5023 4966 4950>,
+ <6101 5407 5125 4994 4951 4939>,
+ <6096 5397 5113 4982 4945 4934>,
+ <6119 5393 5107 4974 4941 4931>,
+ <6146 5387 5105 4972 4940 4930>,
+ <6186 5373 5105 4973 4940 4930>,
+ <6237 5359 5106 4974 4940 4931>,
+ <6285 5359 5108 4975 4940 4931>,
+ <6335 5374 5112 4978 4941 4932>,
+ <6386 5394 5113 4981 4942 4933>,
+ <6438 5418 5109 4984 4944 4934>,
+ <6491 5448 5106 4986 4946 4936>,
+ <6546 5478 5109 4988 4949 4938>,
+ <6603 5512 5120 4989 4952 4939>,
+ <6665 5547 5133 4989 4952 4939>,
+ <6732 5583 5145 4983 4946 4936>,
+ <6803 5621 5158 4978 4940 4932>,
+ <6876 5662 5167 4978 4940 4932>,
+ <6950 5708 5176 4978 4940 4933>,
+ <7022 5754 5186 4979 4940 4933>,
+ <7089 5799 5201 4982 4942 4934>,
+ <7157 5850 5219 4985 4942 4933>,
+ <7235 5915 5240 4987 4939 4929>,
+ <7330 6003 5272 4991 4941 4930>,
+ <7326 6045 5279 4998 4946 4937>,
+ <7395 6104 5304 5003 4952 4950>,
+ <7483 6173 5341 5014 4973 4970>,
+ <7577 6261 5385 5032 4978 4960>,
+ <7656 6331 5397 5024 4954 4941>,
+ <7727 6392 5417 5023 4955 4943>,
+ <7873 6517 5468 5035 4965 4950>,
+ <8078 6702 5539 5060 4982 4970>,
+ <8853 6954 5681 5120 5047 5023>,
+ <8853 6954 5681 5120 5047 5023>,
+ <8853 6954 5681 5120 5047 5023>;
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-fp4-veken-4360mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-fp4-veken-4360mah.dtsi
new file mode 100644
index 0000000..97cf3df
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-fp4-veken-4360mah.dtsi
@@ -0,0 +1,1068 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+qcom,fp4_veken_4500mAh {
+ /* 4251176_TCL_T1Pro_Veken_4500mAH_PM6150_averaged_MasterSlave_Nov29th2019 */
+ qcom,default-battery-type;
+ qcom,max-voltage-uv = <4400000>;
+ qcom,fg-cc-cv-threshold-uv = <4390000>;
+ qcom,fastchg-current-ma = <4296>;//change to 1.1c
+ qcom,batt-id-kohm = <82>;
+ qcom,battery-beta = <3435>;
+ qcom,battery-therm-kohm = <10>;
+ qcom,battery-type = "fp4-veken_v4";
+ qcom,qg-batt-profile-ver = <100>;
+
+/*zxzadd if change below value need change the value temperature define in driver
+smblib_get_prop_batt_health
+#define JEITA_HARD_COLD_TEMP (0)
+#define JEITA_SOFT_COLD_TEMP (100)
+#define JEITA_SOFT_HOT_TEMP (450)
+#define JEITA_HARD_HOT_TEMP (600)
+*/
+ qcom,jeita-fcc-ranges = <(-300) 49 0
+ 50 120 780000
+ 121 450 4296000
+ 451 550 1950000
+ 551 600 0>;
+
+ qcom,jeita-fv-ranges = <50 450 4400000
+ 451 550 4100000>;
+
+ qcom,step-chg-ranges = <2800000 4250000 4296000
+ 4250001 4400000 1950000>;
+
+ qcom,ocv-based-step-chg;
+
+/*zxz add comment below value need check */
+/*zxz add should notice that below jeitavalue is not work, them is not set in driver, defined 'qcom,sw-jeita-enable' in dtsi ,but smblib_notifier_call
+function add "if ((!chg->sw_jeita_enabled)" so not do "jeita_update_work" .
+jeita value is set in amss_smxx50/BOOT.XF.3.3/boot_images/QcomPkg/SocPkg/BitraPkg/Settings/Charger/QcomChargerConfig_VbattTh_fp4.cfg
+
+*/
+ /* COOL = 10 DegC, WARM = 45 DegC */
+ qcom,jeita-soft-thresholds = <0x2aee 0xfb3>;
+ /* COLD = 0 DegC, HOT = 60 DegC */
+ qcom,jeita-hard-thresholds = <0x3733 0xa2c>;
+ /* COOL hys = 13 DegC, WARM hys = 42 DegC */
+ qcom,jeita-soft-hys-thresholds = <0x279a 0x1124>;
+
+ qcom,jeita-soft-fcc-ua = <1950000 1950000>;
+ qcom,jeita-soft-fv-uv = <4100000 4100000>;
+
+
+ qcom,fcc1-temp-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-data = <3744 3836 3916 3949 3959>;
+ };
+
+ qcom,fcc2-temp-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-data = <3902 3909 3924 3913 3922 3921>;
+ };
+
+ qcom,pc-temp-v1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <43547 43741 43838 43878 43889>,
+ <43295 43490 43613 43655 43670>,
+ <43050 43248 43383 43427 43440>,
+ <42810 43012 43144 43197 43212>,
+ <42578 42778 42901 42964 42985>,
+ <42352 42543 42663 42729 42756>,
+ <42130 42311 42432 42497 42523>,
+ <41913 42086 42202 42264 42288>,
+ <41701 41865 41972 42034 42057>,
+ <41493 41648 41743 41805 41828>,
+ <41290 41432 41520 41578 41602>,
+ <41096 41222 41303 41358 41381>,
+ <40916 41031 41091 41141 41163>,
+ <40725 40857 40889 40934 40953>,
+ <40489 40671 40692 40734 40749>,
+ <40233 40440 40494 40537 40551>,
+ <40030 40197 40287 40336 40358>,
+ <39878 40011 40093 40139 40172>,
+ <39745 39867 39932 39965 39996>,
+ <39614 39729 39790 39817 39837>,
+ <39490 39582 39629 39654 39668>,
+ <39364 39431 39427 39435 39456>,
+ <39234 39250 39214 39196 39226>,
+ <39101 38993 39010 39008 39036>,
+ <38958 38765 38808 38853 38879>,
+ <38791 38651 38665 38724 38742>,
+ <38642 38577 38578 38619 38625>,
+ <38546 38512 38508 38527 38523>,
+ <38474 38452 38432 38437 38428>,
+ <38417 38398 38359 38346 38339>,
+ <38373 38346 38291 38264 38259>,
+ <38337 38296 38226 38192 38185>,
+ <38301 38250 38168 38128 38118>,
+ <38267 38206 38116 38071 38056>,
+ <38236 38165 38070 38021 38002>,
+ <38206 38128 38028 37973 37946>,
+ <38177 38098 37994 37925 37886>,
+ <38138 38061 37957 37876 37822>,
+ <38076 37999 37899 37810 37747>,
+ <37995 37907 37812 37724 37659>,
+ <37898 37807 37713 37626 37559>,
+ <37773 37693 37605 37517 37449>,
+ <37632 37561 37479 37391 37321>,
+ <37474 37401 37318 37231 37161>,
+ <37333 37253 37171 37090 37024>,
+ <37240 37160 37074 36995 36937>,
+ <37217 37136 37052 36970 36914>,
+ <37195 37117 37035 36956 36897>,
+ <37169 37102 37019 36938 36879>,
+ <37122 37068 36985 36895 36827>,
+ <36943 36874 36782 36669 36577>,
+ <36509 36445 36359 36241 36147>,
+ <35943 35888 35803 35679 35583>,
+ <35182 35126 35038 34914 34818>,
+ <33980 33929 33854 33733 33636>,
+ <30000 30000 30000 30000 30000>;
+ };
+
+ qcom,pc-temp-v2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <43895 43880 43865 43810 43800 43780>,
+ <43511 43554 43585 43527 43531 43518>,
+ <43163 43251 43318 43260 43272 43264>,
+ <42853 42975 43063 43007 43025 43020>,
+ <42574 42725 42822 42771 42790 42786>,
+ <42328 42484 42585 42539 42558 42555>,
+ <42128 42243 42348 42306 42325 42322>,
+ <41947 42007 42113 42075 42093 42091>,
+ <41721 41776 41885 41847 41865 41864>,
+ <41415 41548 41660 41623 41639 41640>,
+ <41171 41332 41442 41401 41416 41418>,
+ <41071 41140 41229 41184 41196 41200>,
+ <41004 40961 41022 40969 40980 40984>,
+ <40846 40769 40819 40763 40774 40778>,
+ <40354 40568 40619 40562 40576 40576>,
+ <39851 40346 40417 40366 40383 40381>,
+ <39605 40059 40208 40166 40187 40193>,
+ <39428 39735 39994 39968 39994 40012>,
+ <39255 39498 39777 39793 39818 39838>,
+ <39085 39340 39552 39647 39666 39679>,
+ <38919 39196 39337 39492 39504 39509>,
+ <38743 39029 39141 39274 39288 39291>,
+ <38565 38856 38960 39017 39044 39049>,
+ <38430 38702 38801 38817 38850 38857>,
+ <38335 38570 38661 38668 38698 38706>,
+ <38258 38445 38535 38543 38568 38577>,
+ <38188 38310 38421 38434 38455 38463>,
+ <38126 38172 38318 38338 38355 38362>,
+ <38069 38076 38224 38248 38264 38268>,
+ <38014 38014 38139 38161 38180 38180>,
+ <37963 37966 38059 38082 38104 38101>,
+ <37914 37923 37979 38011 38035 38030>,
+ <37867 37886 37904 37948 37972 37966>,
+ <37818 37850 37846 37888 37907 37898>,
+ <37767 37816 37805 37834 37841 37826>,
+ <37713 37780 37768 37779 37770 37747>,
+ <37655 37733 37729 37718 37683 37648>,
+ <37593 37673 37689 37651 37581 37532>,
+ <37525 37607 37640 37580 37490 37430>,
+ <37450 37537 37574 37507 37413 37349>,
+ <37370 37459 37494 37428 37336 37269>,
+ <37287 37365 37393 37333 37241 37174>,
+ <37199 37249 37267 37217 37130 37065>,
+ <37116 37120 37124 37079 36995 36930>,
+ <37037 36983 36991 36952 36881 36817>,
+ <36946 36880 36911 36895 36832 36773>,
+ <36895 36845 36888 36881 36820 36764>,
+ <36841 36810 36867 36864 36804 36748>,
+ <36776 36769 36837 36843 36783 36724>,
+ <36688 36698 36776 36790 36718 36649>,
+ <36506 36521 36579 36592 36485 36381>,
+ <36138 36111 36133 36140 36015 35908>,
+ <35550 35513 35515 35555 35413 35297>,
+ <34710 34679 34667 34771 34602 34476>,
+ <33331 33366 33473 33598 33431 33279>,
+ <30369 29555 29368 29464 29626 29624>;
+ };
+
+ qcom,pc-temp-z1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <13072 12198 11375 11047 10895>,
+ <13153 12271 11457 11098 10965>,
+ <13199 12267 11500 11129 11004>,
+ <13200 12251 11497 11134 11014>,
+ <13156 12242 11488 11131 11016>,
+ <13116 12236 11479 11129 11017>,
+ <13112 12229 11469 11127 11017>,
+ <13110 12216 11460 11126 11017>,
+ <13107 12194 11456 11124 11017>,
+ <13083 12184 11453 11122 11016>,
+ <13053 12183 11452 11121 11014>,
+ <13041 12183 11452 11120 11014>,
+ <13034 12174 11452 11120 11014>,
+ <13027 12141 11449 11120 11013>,
+ <13009 12115 11445 11118 11012>,
+ <12977 12105 11442 11116 11011>,
+ <12946 12097 11439 11116 11012>,
+ <12910 12096 11438 11117 11013>,
+ <12882 12096 11439 11117 11015>,
+ <12884 12098 11443 11117 11016>,
+ <12902 12108 11447 11117 11018>,
+ <12915 12124 11451 11118 11018>,
+ <12914 12130 11455 11119 11018>,
+ <12911 12123 11460 11121 11018>,
+ <12915 12117 11465 11124 11021>,
+ <12932 12120 11471 11128 11025>,
+ <12949 12129 11478 11132 11027>,
+ <12952 12137 11485 11136 11028>,
+ <12947 12148 11491 11140 11031>,
+ <12944 12158 11496 11145 11034>,
+ <12943 12161 11501 11149 11037>,
+ <12942 12162 11506 11152 11040>,
+ <12943 12162 11511 11154 11044>,
+ <12948 12165 11516 11158 11047>,
+ <12954 12168 11522 11163 11049>,
+ <12964 12175 11529 11167 11052>,
+ <12980 12192 11537 11171 11055>,
+ <12996 12207 11546 11175 11059>,
+ <13016 12215 11552 11179 11061>,
+ <13036 12224 11557 11183 11063>,
+ <13040 12228 11562 11186 11065>,
+ <13028 12234 11571 11188 11068>,
+ <13030 12240 11578 11191 11070>,
+ <13040 12251 11581 11194 11072>,
+ <13065 12253 11590 11198 11072>,
+ <13039 12240 11598 11200 11073>,
+ <13034 12238 11600 11199 11075>,
+ <13039 12234 11597 11200 11074>,
+ <13022 12240 11604 11201 11075>,
+ <13058 12240 11608 11205 11078>,
+ <13080 12259 11613 11210 11080>,
+ <13051 12280 11628 11214 11085>,
+ <13103 12296 11638 11224 11094>,
+ <13106 12313 11652 11236 11106>,
+ <13106 12313 11652 11236 11106>,
+ <13106 12313 11652 11236 11106>;
+ };
+
+ qcom,pc-temp-z2-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <10097 10392 10291 10239 10066>,
+ <10060 10195 10789 10867 10703>,
+ <10032 10156 10993 11172 11141>,
+ <10016 10132 10785 11184 11217>,
+ <10005 10110 10405 11047 11107>,
+ <9999 10087 10313 10871 10946>,
+ <9998 10069 10406 10607 10682>,
+ <9997 10060 10481 10354 10369>,
+ <9996 10054 10423 10377 10346>,
+ <9987 10052 10311 10646 10685>,
+ <9977 10057 10284 10806 10939>,
+ <9976 10067 10293 10793 10930>,
+ <9980 10098 10309 10772 10906>,
+ <9983 10181 10389 10773 10897>,
+ <9971 10231 10533 10794 10913>,
+ <9946 10213 10578 10818 10920>,
+ <9939 10184 10557 10839 10908>,
+ <9973 10182 10524 10851 10895>,
+ <10016 10199 10468 10782 10832>,
+ <10032 10216 10392 10474 10500>,
+ <10040 10226 10383 10302 10279>,
+ <10048 10234 10437 10453 10430>,
+ <10058 10236 10485 10672 10674>,
+ <10069 10225 10467 10674 10711>,
+ <10080 10214 10402 10441 10525>,
+ <10091 10217 10374 10283 10380>,
+ <10102 10230 10387 10315 10504>,
+ <10111 10243 10409 10379 10737>,
+ <10121 10254 10431 10436 10773>,
+ <10129 10265 10457 10501 10600>,
+ <10137 10271 10467 10535 10412>,
+ <10145 10275 10453 10486 10284>,
+ <10154 10279 10433 10407 10182>,
+ <10164 10282 10422 10390 10164>,
+ <10175 10286 10413 10398 10184>,
+ <10185 10290 10409 10410 10215>,
+ <10196 10294 10416 10440 10266>,
+ <10207 10300 10431 10489 10333>,
+ <10222 10314 10452 10528 10383>,
+ <10238 10334 10491 10567 10426>,
+ <10255 10346 10517 10587 10451>,
+ <10274 10350 10525 10584 10446>,
+ <10302 10358 10531 10579 10433>,
+ <10357 10391 10537 10562 10430>,
+ <10714 10601 10605 10535 10428>,
+ <10699 10659 10640 10492 10378>,
+ <10620 10695 10622 10489 10401>,
+ <10531 10734 10628 10493 10409>,
+ <10481 10965 10616 10471 10415>,
+ <10489 11224 10672 10555 10543>,
+ <10478 10796 10786 10624 10393>,
+ <10367 10862 10768 10373 10166>,
+ <10160 10888 10917 10329 10109>,
+ <10013 10741 10891 10265 10072>,
+ <10013 10741 10891 10265 10072>,
+ <10013 10741 10891 10265 10072>;
+ };
+
+ qcom,pc-temp-z3-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <19692 19717 19379 19339 19348>,
+ <19848 19666 19446 19392 19357>,
+ <19960 19698 19494 19422 19393>,
+ <19998 19730 19519 19447 19415>,
+ <20015 19742 19538 19470 19432>,
+ <20022 19744 19550 19481 19441>,
+ <20017 19744 19559 19465 19434>,
+ <20003 19741 19562 19442 19420>,
+ <19995 19731 19548 19438 19417>,
+ <19994 19724 19522 19448 19427>,
+ <19992 19716 19505 19453 19433>,
+ <19983 19707 19490 19445 19428>,
+ <19959 19700 19480 19435 19417>,
+ <19942 19680 19486 19429 19410>,
+ <19963 19668 19500 19425 19405>,
+ <20005 19662 19504 19421 19399>,
+ <20017 19651 19497 19417 19393>,
+ <19975 19642 19487 19414 19384>,
+ <19925 19630 19473 19404 19374>,
+ <19909 19621 19454 19381 19359>,
+ <19902 19623 19449 19367 19349>,
+ <19898 19630 19464 19380 19357>,
+ <19897 19638 19481 19401 19371>,
+ <19896 19653 19479 19401 19372>,
+ <19896 19665 19470 19374 19346>,
+ <19903 19662 19460 19354 19327>,
+ <19909 19651 19447 19352 19348>,
+ <19907 19641 19437 19351 19389>,
+ <19897 19633 19439 19358 19401>,
+ <19885 19626 19448 19394 19403>,
+ <19871 19625 19458 19418 19403>,
+ <19856 19626 19471 19417 19398>,
+ <19844 19626 19482 19415 19387>,
+ <19832 19628 19483 19411 19378>,
+ <19821 19630 19480 19403 19370>,
+ <19810 19629 19476 19394 19364>,
+ <19798 19622 19469 19387 19361>,
+ <19789 19615 19460 19381 19359>,
+ <19783 19612 19455 19377 19357>,
+ <19777 19609 19452 19374 19355>,
+ <19768 19605 19448 19372 19354>,
+ <19754 19597 19444 19371 19356>,
+ <19735 19586 19440 19371 19359>,
+ <19702 19570 19433 19369 19360>,
+ <19564 19516 19417 19360 19358>,
+ <19491 19495 19412 19356 19349>,
+ <19391 19477 19402 19352 19336>,
+ <19331 19456 19401 19343 19335>,
+ <19326 19385 19393 19343 19329>,
+ <19323 19329 19371 19335 19323>,
+ <19322 19453 19372 19332 19344>,
+ <19330 19427 19363 19359 19359>,
+ <19335 19329 19330 19360 19365>,
+ <19340 19314 19322 19355 19361>,
+ <19340 19314 19322 19355 19361>,
+ <19340 19314 19322 19355 19361>;
+ };
+
+ qcom,pc-temp-z4-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <16552 15336 15215 14970 14883>,
+ <16332 15663 15174 14974 14907>,
+ <16126 15572 15126 14943 14882>,
+ <15932 15376 15066 14904 14855>,
+ <15743 15232 14998 14849 14817>,
+ <15582 15136 14936 14813 14787>,
+ <15463 15059 14871 14803 14776>,
+ <15366 15000 14828 14795 14766>,
+ <15284 14953 14814 14782 14756>,
+ <15213 14917 14804 14749 14727>,
+ <15152 14889 14797 14727 14705>,
+ <15102 14865 14793 14722 14702>,
+ <15059 14838 14787 14717 14699>,
+ <15021 14802 14765 14710 14695>,
+ <14985 14784 14728 14699 14688>,
+ <14952 14802 14714 14689 14682>,
+ <14929 14829 14711 14683 14679>,
+ <14913 14831 14709 14677 14677>,
+ <14899 14804 14705 14676 14675>,
+ <14878 14776 14701 14685 14680>,
+ <14849 14764 14705 14698 14690>,
+ <14830 14755 14724 14724 14713>,
+ <14823 14759 14755 14766 14756>,
+ <14819 14837 14803 14809 14796>,
+ <14822 14915 14873 14858 14842>,
+ <14858 14918 14899 14883 14868>,
+ <14892 14908 14892 14876 14839>,
+ <14895 14896 14879 14859 14779>,
+ <14894 14881 14861 14831 14744>,
+ <14893 14864 14833 14778 14724>,
+ <14884 14847 14805 14737 14712>,
+ <14868 14828 14775 14720 14705>,
+ <14855 14810 14750 14709 14701>,
+ <14843 14794 14739 14706 14698>,
+ <14831 14780 14732 14705 14696>,
+ <14820 14769 14730 14704 14694>,
+ <14810 14761 14729 14707 14697>,
+ <14801 14757 14729 14713 14704>,
+ <14790 14758 14732 14720 14711>,
+ <14783 14761 14745 14733 14723>,
+ <14782 14761 14752 14741 14729>,
+ <14783 14754 14742 14732 14719>,
+ <14782 14748 14732 14723 14708>,
+ <14776 14744 14731 14725 14710>,
+ <14774 14720 14716 14718 14700>,
+ <14833 14712 14697 14700 14689>,
+ <14938 14718 14694 14694 14689>,
+ <14997 14732 14677 14681 14671>,
+ <14996 14799 14669 14658 14652>,
+ <14990 14855 14687 14659 14647>,
+ <14987 14723 14709 14696 14665>,
+ <15004 14767 14735 14680 14660>,
+ <15009 14883 14772 14679 14655>,
+ <15018 14903 14783 14687 14661>,
+ <15018 14903 14783 14687 14661>,
+ <15018 14903 14783 14687 14661>;
+ };
+
+ qcom,pc-temp-z5-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <11886 14413 12567 13102 14178>,
+ <12614 13780 13644 14479 14279>,
+ <13204 14265 14624 15634 16088>,
+ <13607 14843 15494 16974 17343>,
+ <13900 15368 16345 18793 18701>,
+ <14135 15882 17208 19693 19560>,
+ <14338 16345 18357 18973 19423>,
+ <14529 16749 19093 17953 19227>,
+ <14759 17188 19044 18480 19855>,
+ <15214 17541 18856 21544 23476>,
+ <15659 18062 18677 23352 26139>,
+ <15766 18631 18349 23071 25691>,
+ <15786 19177 18101 22663 24784>,
+ <15818 20344 19895 22874 24720>,
+ <17557 20981 23876 24323 26144>,
+ <21016 20322 25137 25835 27203>,
+ <22203 19430 24533 27136 26780>,
+ <21184 19541 23684 28285 25703>,
+ <20069 20118 23016 27744 24271>,
+ <20255 21038 22919 23542 21923>,
+ <21764 23532 24295 21313 20779>,
+ <23804 28090 32731 26724 23517>,
+ <26533 32520 41002 34677 27989>,
+ <30194 37714 39409 34519 28103>,
+ <34261 41364 32041 24669 20795>,
+ <39901 39609 26133 17194 15196>,
+ <43976 33334 22016 15796 15983>,
+ <43531 28780 19356 15011 17918>,
+ <40937 26400 19188 15359 19582>,
+ <38199 24888 19413 18225 21177>,
+ <35616 24801 19831 21410 22344>,
+ <33158 25294 22413 23899 22861>,
+ <31585 26003 26202 26110 23226>,
+ <30517 27885 29171 27448 23749>,
+ <29680 30346 32046 28444 24523>,
+ <28861 31082 33178 28875 25138>,
+ <28088 31087 32459 28333 25470>,
+ <27851 31026 31138 27139 25695>,
+ <29032 31420 29725 25716 25308>,
+ <30503 32217 27880 23446 22685>,
+ <30384 32267 26244 21667 20847>,
+ <28748 30519 25091 20970 20928>,
+ <27814 28564 24014 20404 21047>,
+ <26873 26828 22620 19641 20984>,
+ <22035 27109 23042 18982 20817>,
+ <18173 25404 24156 18997 19077>,
+ <13919 21365 21787 18653 17041>,
+ <12110 19251 22544 18066 18007>,
+ <12039 15544 21621 20382 19528>,
+ <12053 12864 17589 19192 19704>,
+ <12124 19269 16872 15338 18983>,
+ <12051 15940 14845 16984 19612>,
+ <11973 12316 12947 16550 20090>,
+ <11867 11920 12520 15346 17888>,
+ <11867 11920 12520 15346 17888>,
+ <11867 11920 12520 15346 17888>;
+ };
+
+ qcom,pc-temp-z6-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <16270 15305 14815 14617 14564>,
+ <16211 15410 14843 14659 14600>,
+ <16142 15378 14853 14670 14613>,
+ <16062 15296 14844 14670 14615>,
+ <15962 15229 14819 14661 14609>,
+ <15866 15178 14796 14649 14600>,
+ <15791 15134 14775 14635 14591>,
+ <15725 15097 14755 14621 14580>,
+ <15672 15065 14736 14610 14571>,
+ <15630 15040 14719 14602 14565>,
+ <15592 15022 14706 14595 14560>,
+ <15549 15006 14697 14588 14554>,
+ <15498 14982 14689 14581 14548>,
+ <15463 14950 14681 14574 14542>,
+ <15451 14934 14674 14566 14535>,
+ <15445 14935 14667 14559 14529>,
+ <15432 14937 14661 14554 14523>,
+ <15399 14934 14655 14550 14518>,
+ <15364 14915 14647 14544 14513>,
+ <15345 14900 14636 14536 14507>,
+ <15331 14900 14633 14531 14503>,
+ <15324 14901 14649 14549 14517>,
+ <15324 14905 14673 14581 14545>,
+ <15323 14948 14695 14596 14559>,
+ <15326 14989 14719 14603 14566>,
+ <15347 14990 14728 14606 14569>,
+ <15367 14982 14720 14602 14567>,
+ <15367 14974 14710 14595 14563>,
+ <15364 14965 14703 14589 14558>,
+ <15359 14956 14697 14585 14552>,
+ <15349 14948 14692 14581 14546>,
+ <15337 14942 14687 14575 14540>,
+ <15327 14937 14683 14569 14533>,
+ <15318 14933 14680 14564 14528>,
+ <15311 14930 14676 14560 14522>,
+ <15303 14927 14674 14556 14519>,
+ <15297 14923 14670 14555 14519>,
+ <15294 14920 14667 14554 14520>,
+ <15295 14923 14668 14554 14521>,
+ <15296 14927 14673 14558 14525>,
+ <15297 14929 14675 14561 14528>,
+ <15299 14926 14671 14557 14525>,
+ <15299 14923 14665 14554 14522>,
+ <15291 14917 14663 14554 14523>,
+ <15236 14888 14650 14547 14518>,
+ <15224 14877 14641 14537 14508>,
+ <15217 14870 14635 14532 14503>,
+ <15212 14866 14627 14522 14493>,
+ <15211 14860 14620 14512 14482>,
+ <15213 14859 14618 14508 14476>,
+ <15220 14871 14630 14524 14497>,
+ <15239 14883 14640 14533 14505>,
+ <15255 14891 14642 14536 14508>,
+ <15282 14904 14647 14540 14512>,
+ <15282 14904 14647 14540 14512>,
+ <15282 14904 14647 14540 14512>;
+ };
+
+ qcom,pc-temp-y1-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <6642 6057 5647 5184 4959 4892>,
+ <6654 6057 5637 5180 4959 4891>,
+ <6664 6056 5627 5174 4959 4889>,
+ <6673 6053 5616 5168 4957 4887>,
+ <6680 6051 5608 5163 4956 4886>,
+ <6684 6050 5601 5160 4954 4885>,
+ <6676 6050 5596 5159 4952 4884>,
+ <6661 6049 5592 5158 4950 4884>,
+ <6656 6048 5586 5156 4948 4883>,
+ <6652 6041 5577 5153 4945 4882>,
+ <6650 6034 5571 5149 4944 4881>,
+ <6665 6024 5568 5147 4944 4880>,
+ <6695 6013 5566 5146 4944 4879>,
+ <6702 6012 5562 5145 4944 4879>,
+ <6688 6029 5556 5145 4941 4879>,
+ <6676 6044 5552 5144 4939 4879>,
+ <6680 6046 5556 5145 4941 4879>,
+ <6691 6047 5564 5145 4943 4880>,
+ <6695 6049 5567 5146 4944 4879>,
+ <6694 6051 5565 5148 4943 4878>,
+ <6693 6052 5563 5150 4943 4877>,
+ <6689 6051 5561 5152 4943 4878>,
+ <6679 6046 5559 5154 4945 4880>,
+ <6668 6043 5560 5156 4946 4882>,
+ <6652 6048 5569 5161 4948 4883>,
+ <6639 6052 5577 5166 4951 4883>,
+ <6636 6048 5577 5170 4953 4885>,
+ <6639 6037 5577 5174 4955 4888>,
+ <6638 6033 5578 5178 4957 4890>,
+ <6630 6035 5585 5182 4960 4891>,
+ <6621 6038 5590 5187 4962 4893>,
+ <6617 6035 5589 5192 4965 4895>,
+ <6615 6029 5584 5198 4968 4898>,
+ <6613 6028 5584 5203 4971 4900>,
+ <6614 6033 5587 5208 4976 4901>,
+ <6614 6039 5590 5212 4980 4903>,
+ <6608 6038 5590 5214 4981 4904>,
+ <6593 6037 5590 5217 4981 4907>,
+ <6584 6035 5593 5219 4982 4908>,
+ <6593 6027 5607 5222 4983 4909>,
+ <6607 6017 5620 5225 4984 4910>,
+ <6610 6012 5623 5229 4985 4911>,
+ <6608 6005 5621 5233 4986 4911>,
+ <6596 5999 5621 5239 4988 4912>,
+ <6565 5999 5625 5248 4992 4914>,
+ <6605 6021 5632 5253 4996 4917>,
+ <6605 6033 5628 5252 4996 4919>,
+ <6619 6044 5644 5251 4996 4919>,
+ <6619 6049 5641 5257 4996 4918>,
+ <6595 6023 5643 5254 4997 4918>,
+ <6619 6016 5641 5266 4996 4919>,
+ <6652 6020 5649 5267 5001 4922>,
+ <6670 6044 5660 5281 5007 4926>,
+ <6745 6053 5663 5299 5015 4934>,
+ <6745 6053 5663 5299 5015 4934>,
+ <6745 6053 5663 5299 5015 4934>;
+ };
+
+ qcom,pc-temp-y2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <10132 10426 10863 11220 10914 10948>,
+ <10065 10415 10836 11188 10918 10957>,
+ <10035 10412 10808 11137 10916 10958>,
+ <10034 10413 10780 11080 10911 10955>,
+ <10053 10419 10757 11030 10902 10947>,
+ <10083 10426 10741 11001 10891 10937>,
+ <10138 10440 10729 10987 10869 10906>,
+ <10219 10457 10721 10974 10844 10855>,
+ <10285 10457 10720 10975 10848 10816>,
+ <10348 10433 10722 10979 10912 10779>,
+ <10387 10414 10724 10982 10959 10760>,
+ <10390 10514 10725 10975 10935 10781>,
+ <10385 10707 10727 10961 10890 10820>,
+ <10406 10756 10740 10959 10880 10825>,
+ <10547 10713 10812 10971 10902 10795>,
+ <10666 10677 10876 10992 10933 10771>,
+ <10427 10687 10896 11040 10964 10825>,
+ <9874 10718 10908 11117 11004 10946>,
+ <9680 10749 10918 11170 11064 11029>,
+ <9676 10783 10928 11210 11186 11092>,
+ <9674 10819 10939 11233 11271 11126>,
+ <9671 10862 10959 11210 11231 11118>,
+ <9669 10907 10989 11155 11142 11096>,
+ <9667 10922 11017 11138 11102 11081>,
+ <9666 10917 11043 11163 11086 11059>,
+ <9665 10913 11068 11196 11079 11046>,
+ <9664 10935 11094 11221 11102 11064>,
+ <9663 10989 11118 11244 11165 11104>,
+ <9662 11009 11125 11266 11220 11135>,
+ <9661 10985 11125 11287 11265 11165>,
+ <9661 10949 11125 11305 11309 11192>,
+ <9660 10916 11131 11319 11360 11215>,
+ <9659 10877 11144 11334 11413 11243>,
+ <9659 10835 11147 11340 11440 11268>,
+ <9658 10799 11125 11333 11430 11304>,
+ <9658 10749 11096 11321 11400 11333>,
+ <9658 10529 11074 11310 11335 11305>,
+ <9658 9982 11053 11291 11225 11212>,
+ <9657 9704 11028 11275 11179 11170>,
+ <9657 9689 10997 11264 11187 11152>,
+ <9657 9680 10960 11251 11202 11128>,
+ <9656 9673 10915 11228 11195 11112>,
+ <9656 9667 10863 11194 11166 11101>,
+ <9656 9664 10807 11176 11137 11085>,
+ <9656 9662 10737 11153 11087 11025>,
+ <9656 9660 10662 11060 11044 10878>,
+ <9656 9660 10652 11077 11021 10822>,
+ <9655 9659 10623 11069 10993 10835>,
+ <9655 9658 10591 11075 11004 10850>,
+ <9655 9657 10575 11052 11010 10876>,
+ <9654 9656 10516 11046 10971 10829>,
+ <9654 9656 10433 10998 10904 10745>,
+ <9652 9654 10343 10919 10826 10684>,
+ <9650 9653 10081 10860 10774 10611>,
+ <9650 9653 10081 10860 10774 10611>,
+ <9650 9653 10081 10860 10774 10611>;
+ };
+
+ qcom,pc-temp-y3-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <14023 13482 13356 13296 13281 13280>,
+ <13929 13489 13359 13294 13282 13279>,
+ <13869 13495 13362 13293 13283 13278>,
+ <13836 13499 13365 13293 13284 13278>,
+ <13822 13502 13368 13294 13285 13278>,
+ <13819 13503 13370 13295 13286 13278>,
+ <13845 13501 13370 13297 13288 13279>,
+ <13891 13498 13370 13300 13289 13280>,
+ <13877 13499 13370 13302 13290 13281>,
+ <13690 13515 13372 13306 13291 13285>,
+ <13543 13527 13373 13308 13291 13288>,
+ <13558 13505 13372 13308 13291 13289>,
+ <13595 13463 13371 13307 13292 13290>,
+ <13604 13451 13370 13308 13292 13290>,
+ <13589 13457 13370 13312 13297 13290>,
+ <13567 13461 13370 13316 13301 13290>,
+ <13541 13456 13370 13314 13299 13291>,
+ <13512 13442 13371 13310 13295 13294>,
+ <13504 13433 13370 13309 13294 13295>,
+ <13510 13428 13364 13313 13296 13295>,
+ <13516 13423 13357 13317 13297 13295>,
+ <13508 13415 13352 13314 13295 13291>,
+ <13486 13404 13348 13306 13289 13282>,
+ <13477 13396 13344 13300 13285 13280>,
+ <13483 13390 13341 13297 13283 13280>,
+ <13494 13383 13338 13294 13282 13280>,
+ <13510 13370 13336 13296 13282 13280>,
+ <13535 13351 13334 13298 13282 13281>,
+ <13561 13343 13334 13299 13282 13281>,
+ <13588 13343 13333 13298 13282 13279>,
+ <13618 13345 13333 13297 13283 13278>,
+ <13654 13350 13331 13297 13283 13278>,
+ <13698 13359 13329 13299 13284 13279>,
+ <13742 13368 13328 13299 13285 13279>,
+ <13782 13373 13330 13300 13285 13280>,
+ <13823 13379 13333 13300 13285 13280>,
+ <13866 13387 13335 13300 13284 13280>,
+ <13913 13396 13338 13299 13282 13278>,
+ <13963 13407 13340 13298 13281 13278>,
+ <14018 13421 13343 13297 13281 13278>,
+ <14074 13439 13344 13297 13282 13279>,
+ <14124 13462 13343 13298 13282 13281>,
+ <14168 13493 13341 13298 13283 13282>,
+ <14222 13537 13342 13298 13283 13280>,
+ <14289 13600 13346 13299 13282 13277>,
+ <14361 13667 13347 13305 13287 13283>,
+ <14301 13653 13348 13305 13288 13288>,
+ <14362 13714 13355 13305 13293 13290>,
+ <14443 13786 13364 13314 13299 13293>,
+ <14546 13863 13373 13320 13300 13293>,
+ <14653 13942 13376 13314 13295 13289>,
+ <14795 14061 13379 13310 13293 13290>,
+ <15283 14266 13392 13321 13296 13292>,
+ <16203 14597 13423 13330 13303 13297>,
+ <16203 14597 13423 13330 13303 13297>,
+ <16203 14597 13423 13330 13303 13297>;
+ };
+
+ qcom,pc-temp-y4-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <17119 16831 16642 16502 16479 16471>,
+ <17330 16854 16642 16507 16475 16469>,
+ <17459 16885 16642 16511 16472 16468>,
+ <17527 16918 16644 16514 16471 16468>,
+ <17552 16946 16645 16517 16470 16468>,
+ <17556 16961 16647 16519 16470 16468>,
+ <17488 16967 16648 16521 16472 16470>,
+ <17367 16970 16650 16522 16474 16472>,
+ <17374 16967 16654 16523 16477 16472>,
+ <17656 16939 16664 16528 16481 16472>,
+ <17900 16918 16677 16534 16486 16472>,
+ <17945 17011 16689 16542 16493 16474>,
+ <17972 17189 16704 16555 16502 16479>,
+ <17930 17238 16734 16568 16508 16485>,
+ <17476 17225 16806 16581 16511 16494>,
+ <17080 17202 16856 16597 16515 16503>,
+ <17109 17093 16853 16618 16526 16509>,
+ <17208 16899 16840 16643 16546 16515>,
+ <17237 16836 16816 16665 16567 16525>,
+ <17166 16834 16739 16688 16597 16550>,
+ <17072 16833 16663 16702 16616 16568>,
+ <17000 16817 16623 16659 16590 16551>,
+ <16935 16779 16594 16558 16531 16513>,
+ <16912 16749 16581 16514 16499 16490>,
+ <16910 16729 16574 16504 16483 16476>,
+ <16910 16709 16571 16499 16476 16469>,
+ <16910 16682 16572 16500 16477 16470>,
+ <16910 16651 16574 16503 16483 16473>,
+ <16910 16640 16575 16507 16489 16478>,
+ <16910 16647 16575 16515 16498 16487>,
+ <16910 16655 16575 16524 16508 16499>,
+ <16910 16657 16569 16533 16521 16511>,
+ <16911 16660 16557 16543 16535 16523>,
+ <16912 16664 16554 16548 16539 16526>,
+ <16915 16674 16562 16550 16538 16526>,
+ <16920 16691 16575 16551 16536 16524>,
+ <16921 16721 16589 16546 16523 16513>,
+ <16922 16774 16604 16529 16495 16487>,
+ <16923 16806 16615 16520 16484 16477>,
+ <16918 16817 16621 16519 16485 16477>,
+ <16911 16823 16626 16518 16487 16478>,
+ <16912 16822 16628 16519 16488 16478>,
+ <16925 16812 16630 16522 16488 16477>,
+ <16941 16796 16626 16520 16481 16470>,
+ <16963 16780 16623 16512 16473 16462>,
+ <16992 16792 16624 16514 16474 16468>,
+ <16947 16792 16621 16516 16485 16476>,
+ <16963 16819 16646 16538 16500 16504>,
+ <16997 16855 16681 16553 16531 16542>,
+ <17029 16912 16722 16576 16549 16552>,
+ <17023 16950 16725 16566 16513 16494>,
+ <16985 16907 16695 16532 16478 16470>,
+ <17127 16908 16710 16545 16485 16475>,
+ <17490 17021 16766 16585 16513 16501>,
+ <17490 17021 16766 16585 16513 16501>,
+ <17490 17021 16766 16585 16513 16501>;
+ };
+
+ qcom,pc-temp-y5-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <13104 13557 14464 15143 15577 17102>,
+ <12233 13749 15227 14550 15999 16788>,
+ <11833 13980 15679 14104 16264 16235>,
+ <11818 14204 15894 13783 16406 15603>,
+ <12104 14376 15943 13567 16458 15054>,
+ <12606 14448 15898 13435 16453 14751>,
+ <14595 14417 15653 13542 16328 14590>,
+ <17508 14363 15251 13812 16071 14428>,
+ <17741 14452 14986 13890 15800 14548>,
+ <14246 15163 14714 13970 15481 15525>,
+ <11482 15710 14435 13953 15120 16242>,
+ <13113 14820 14079 13620 14612 16070>,
+ <16467 13096 13711 13166 14094 15640>,
+ <17424 12971 13638 13021 14033 15162>,
+ <17063 16007 13728 12995 14425 14483>,
+ <16478 18548 13904 12983 14728 14058>,
+ <15219 18005 15442 13008 14278 14197>,
+ <13271 16708 18172 13097 13407 14482>,
+ <12680 16365 19120 13444 13207 14557>,
+ <13211 17048 19330 15697 13602 14524>,
+ <13719 17720 19418 17833 14250 14495>,
+ <13394 17822 19293 18297 15591 14839>,
+ <12429 17824 18989 18552 17433 15707>,
+ <11874 17984 18743 18506 17916 16461>,
+ <11659 18797 18273 17186 17566 17210>,
+ <11542 19522 17834 15930 17063 17671>,
+ <11536 18300 17643 16273 16491 17496>,
+ <11537 14909 17549 17289 15836 16934>,
+ <11541 13340 17670 17642 15534 16266>,
+ <11587 13221 18509 17156 15480 15215>,
+ <11654 13304 19218 16659 15547 14449>,
+ <11743 13646 18846 16861 15782 14504>,
+ <11939 14398 17944 17646 16225 14802>,
+ <12101 15044 17612 18347 16752 15219>,
+ <12205 15661 17697 19103 17578 16080>,
+ <12286 16124 17832 19670 18185 16862>,
+ <12339 15642 17942 19515 17994 17088>,
+ <12399 13887 18038 18810 17339 17221>,
+ <12429 12972 17998 18077 16793 17245>,
+ <12426 12944 17779 17343 16358 16951>,
+ <12400 12953 17429 16698 16013 16629>,
+ <12266 12954 16652 16273 15814 16830>,
+ <11903 12956 15620 15856 15720 17336>,
+ <11836 12880 15525 15809 15955 16802>,
+ <11909 12658 15453 16135 16259 15475>,
+ <11982 12360 15095 16764 16225 15485>,
+ <12118 12374 15004 16453 15435 16617>,
+ <12271 12513 14970 15027 15750 15941>,
+ <12298 12850 14972 16105 16518 15735>,
+ <12566 12942 15092 16635 16379 15435>,
+ <12659 12751 15042 15809 16193 15842>,
+ <12332 12661 15278 16057 17343 18102>,
+ <11224 12640 15399 18598 18544 18606>,
+ <10511 11954 15095 20229 21495 21660>,
+ <10511 11954 15095 20229 21495 21660>,
+ <10511 11954 15095 20229 21495 21660>;
+ };
+
+ qcom,pc-temp-y6-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <6436 5587 5232 5046 5000 4991>,
+ <6425 5591 5233 5045 5000 4990>,
+ <6412 5593 5233 5044 5000 4989>,
+ <6398 5594 5232 5045 5001 4989>,
+ <6387 5595 5231 5045 5002 4989>,
+ <6379 5595 5229 5046 5003 4990>,
+ <6376 5591 5227 5048 5004 4991>,
+ <6373 5583 5224 5050 5005 4992>,
+ <6363 5578 5223 5052 5007 4993>,
+ <6325 5574 5224 5055 5009 4996>,
+ <6296 5572 5225 5058 5011 4998>,
+ <6316 5580 5226 5060 5013 4999>,
+ <6358 5596 5228 5063 5015 5001>,
+ <6358 5601 5233 5067 5018 5003>,
+ <6240 5601 5251 5074 5021 5006>,
+ <6130 5600 5264 5081 5025 5008>,
+ <6112 5571 5263 5086 5028 5011>,
+ <6104 5511 5261 5090 5031 5014>,
+ <6096 5490 5254 5096 5035 5018>,
+ <6087 5488 5228 5105 5045 5025>,
+ <6078 5486 5201 5111 5051 5030>,
+ <6065 5478 5186 5097 5042 5022>,
+ <6050 5464 5175 5062 5020 5005>,
+ <6045 5457 5169 5046 5008 4996>,
+ <6058 5455 5166 5041 5003 4992>,
+ <6079 5452 5165 5039 5000 4990>,
+ <6100 5446 5165 5040 5000 4990>,
+ <6126 5436 5166 5043 5002 4991>,
+ <6152 5433 5168 5046 5004 4993>,
+ <6177 5447 5171 5048 5007 4995>,
+ <6203 5470 5173 5051 5010 4997>,
+ <6233 5492 5172 5054 5015 5001>,
+ <6268 5517 5171 5058 5020 5005>,
+ <6303 5544 5171 5061 5021 5007>,
+ <6337 5573 5178 5064 5021 5007>,
+ <6373 5603 5188 5065 5020 5007>,
+ <6409 5633 5198 5063 5016 5004>,
+ <6446 5664 5209 5058 5007 4996>,
+ <6485 5698 5220 5056 5004 4992>,
+ <6524 5738 5231 5056 5004 4993>,
+ <6563 5782 5242 5056 5006 4994>,
+ <6602 5828 5252 5057 5007 4995>,
+ <6642 5876 5264 5060 5007 4996>,
+ <6691 5933 5279 5060 5005 4993>,
+ <6753 6001 5301 5061 5003 4988>,
+ <6824 6078 5313 5067 5008 4995>,
+ <6781 6070 5310 5068 5012 5001>,
+ <6834 6130 5338 5074 5019 5011>,
+ <6906 6204 5370 5086 5032 5024>,
+ <6997 6285 5407 5097 5038 5027>,
+ <7082 6365 5429 5091 5025 5007>,
+ <7196 6462 5449 5079 5013 5001>,
+ <7700 6639 5520 5094 5019 5005>,
+ <8617 6974 5615 5116 5033 5019>,
+ <8617 6974 5615 5116 5033 5019>,
+ <8617 6974 5615 5116 5033 5019>;
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-mlp356477-2800mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-mlp356477-2800mah.dtsi
new file mode 100755
index 0000000..c64ba57
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-mlp356477-2800mah.dtsi
@@ -0,0 +1,1028 @@
+qcom,mlp356477_2800mah {
+ /* mlp356477_2800mah_averaged_MasterSlave_Mar13th2018 */
+ qcom,max-voltage-uv = <4400000>;
+ qcom,fg-cc-cv-threshold-mv = <4390>;
+ qcom,fastchg-current-ma = <4200>;
+ qcom,batt-id-kohm = <82>;
+ qcom,battery-beta = <4250>;
+ qcom,battery-therm-kohm = <100>;
+ qcom,battery-type =
+ "mlp356477_2800mah_averaged_MasterSlave_Mar13th2018";
+ qcom,qg-batt-profile-ver = <100>;
+
+ qcom,jeita-fcc-ranges = <0 150 560000
+ 151 450 4200000
+ 451 550 2380000>;
+ qcom,jeita-fv-ranges = <0 150 4150000
+ 151 450 4400000
+ 451 550 4150000>;
+
+ /* COOL = 15 DegC, WARM = 45 DegC */
+ qcom,jeita-soft-thresholds = <0x4621 0x20b8>;
+ /* COLD = 0 DegC, HOT = 55 DegC */
+ qcom,jeita-hard-thresholds = <0x58cd 0x181d>;
+
+ qcom,fcc1-temp-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-data = <2715 2788 2861 2898 2908>;
+ };
+
+ qcom,fcc2-temp-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-data = <2864 2846 2860 2868 2865 2865>;
+ };
+
+ qcom,pc-temp-v1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <43494 43682 43812 43865 43879>,
+ <43243 43420 43582 43645 43659>,
+ <42984 43174 43350 43418 43434>,
+ <42737 42940 43115 43191 43208>,
+ <42506 42710 42878 42958 42978>,
+ <42287 42479 42641 42722 42746>,
+ <42087 42250 42407 42489 42514>,
+ <41903 42027 42175 42255 42281>,
+ <41709 41807 41948 42023 42050>,
+ <41489 41592 41723 41794 41822>,
+ <41265 41381 41502 41568 41596>,
+ <41069 41176 41286 41348 41374>,
+ <40898 40982 41074 41131 41155>,
+ <40720 40799 40871 40921 40942>,
+ <40501 40613 40673 40716 40735>,
+ <40269 40405 40482 40518 40534>,
+ <40088 40193 40295 40329 40343>,
+ <39955 40022 40116 40148 40162>,
+ <39834 39894 39952 39975 39988>,
+ <39708 39765 39807 39818 39827>,
+ <39583 39577 39645 39659 39667>,
+ <39447 39345 39420 39461 39475>,
+ <39277 39148 39173 39221 39239>,
+ <39089 38991 38991 39014 39028>,
+ <38930 38860 38851 38860 38868>,
+ <38794 38758 38733 38728 38732>,
+ <38683 38676 38628 38611 38612>,
+ <38607 38602 38535 38507 38505>,
+ <38548 38529 38451 38414 38409>,
+ <38501 38462 38373 38327 38317>,
+ <38466 38407 38305 38251 38234>,
+ <38437 38360 38245 38182 38160>,
+ <38405 38317 38193 38121 38092>,
+ <38366 38277 38147 38067 38030>,
+ <38329 38240 38109 38022 37980>,
+ <38300 38203 38069 37977 37929>,
+ <38273 38170 38027 37921 37863>,
+ <38236 38130 37980 37857 37784>,
+ <38162 38057 37912 37781 37700>,
+ <38062 37946 37816 37690 37609>,
+ <37947 37830 37704 37585 37507>,
+ <37801 37713 37578 37463 37382>,
+ <37644 37575 37436 37322 37239>,
+ <37473 37394 37270 37162 37082>,
+ <37320 37251 37129 37032 36959>,
+ <37220 37161 37058 36960 36899>,
+ <37185 37129 37033 36942 36880>,
+ <37156 37103 37014 36927 36865>,
+ <37120 37070 36988 36902 36835>,
+ <37014 36957 36885 36755 36652>,
+ <36682 36593 36544 36398 36287>,
+ <36204 36109 36077 35921 35807>,
+ <35597 35486 35476 35307 35181>,
+ <34771 34630 34656 34460 34321>,
+ <33460 33262 33379 33128 32955>,
+ <30000 30000 30000 30000 30000>;
+ };
+
+ qcom,pc-temp-v2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <43865 43850 43830 43805 43740 43725>,
+ <43432 43429 43514 43528 43481 43467>,
+ <43037 43064 43219 43264 43228 43216>,
+ <42685 42767 42948 43012 42983 42973>,
+ <42369 42526 42700 42773 42744 42738>,
+ <42075 42296 42458 42537 42509 42505>,
+ <41776 42059 42213 42303 42277 42272>,
+ <41517 41822 41972 42071 42047 42041>,
+ <41353 41571 41739 41843 41820 41814>,
+ <41239 41298 41515 41619 41595 41589>,
+ <41095 41069 41297 41398 41374 41368>,
+ <40895 40928 41088 41181 41158 41151>,
+ <40650 40808 40884 40967 40946 40938>,
+ <40329 40611 40677 40763 40742 40734>,
+ <39941 40284 40461 40566 40541 40534>,
+ <39654 39989 40259 40373 40348 40342>,
+ <39456 39811 40087 40180 40164 40158>,
+ <39278 39662 39920 39993 39985 39980>,
+ <39086 39459 39722 39821 39814 39808>,
+ <38900 39184 39492 39664 39651 39646>,
+ <38740 38924 39264 39483 39469 39466>,
+ <38598 38721 39048 39237 39230 39230>,
+ <38480 38546 38846 38982 38986 38989>,
+ <38386 38403 38678 38799 38809 38813>,
+ <38308 38282 38535 38654 38669 38674>,
+ <38240 38189 38406 38530 38547 38552>,
+ <38182 38125 38286 38419 38438 38442>,
+ <38127 38075 38179 38320 38341 38343>,
+ <38076 38030 38090 38229 38250 38250>,
+ <38028 37992 38012 38144 38166 38164>,
+ <37978 37955 37949 38066 38089 38086>,
+ <37927 37916 37900 37993 38019 38016>,
+ <37875 37875 37857 37925 37953 37949>,
+ <37820 37832 37817 37860 37884 37875>,
+ <37763 37788 37781 37801 37812 37795>,
+ <37699 37738 37740 37738 37728 37702>,
+ <37630 37680 37688 37671 37625 37587>,
+ <37555 37613 37625 37600 37519 37469>,
+ <37475 37537 37552 37525 37430 37374>,
+ <37392 37448 37465 37446 37352 37292>,
+ <37308 37349 37363 37353 37263 37200>,
+ <37222 37237 37238 37238 37151 37088>,
+ <37133 37114 37101 37106 37022 36960>,
+ <37035 36989 36957 36952 36870 36813>,
+ <36935 36875 36859 36862 36807 36758>,
+ <36817 36792 36792 36828 36785 36734>,
+ <36752 36754 36762 36812 36769 36719>,
+ <36667 36707 36710 36780 36736 36687>,
+ <36541 36633 36613 36721 36656 36581>,
+ <36342 36472 36411 36517 36379 36276>,
+ <36024 36149 36031 36113 35946 35829>,
+ <35575 35650 35485 35584 35386 35258>,
+ <34953 34964 34771 34884 34643 34500>,
+ <34073 34007 33739 33902 33598 33440>,
+ <32647 32474 32144 32393 32025 31829>,
+ <30018 28051 26513 28737 27554 26991>;
+ };
+
+ qcom,pc-temp-z1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <14442 13243 12339 11979 11839>,
+ <14411 13218 12328 11916 11773>,
+ <14392 13199 12294 11893 11756>,
+ <14384 13180 12273 11879 11745>,
+ <14381 13174 12263 11870 11738>,
+ <14377 13179 12257 11863 11735>,
+ <14369 13182 12253 11858 11731>,
+ <14358 13175 12250 11851 11726>,
+ <14349 13158 12248 11847 11722>,
+ <14339 13146 12242 11845 11720>,
+ <14332 13143 12237 11845 11719>,
+ <14327 13144 12237 11844 11718>,
+ <14321 13142 12238 11840 11716>,
+ <14313 13135 12234 11837 11715>,
+ <14306 13128 12222 11835 11714>,
+ <14299 13120 12215 11834 11714>,
+ <14293 13113 12211 11833 11713>,
+ <14293 13111 12203 11830 11714>,
+ <14297 13119 12202 11828 11715>,
+ <14304 13129 12210 11831 11716>,
+ <14312 13133 12215 11837 11718>,
+ <14318 13130 12221 11841 11721>,
+ <14319 13125 12230 11843 11726>,
+ <14320 13135 12234 11846 11730>,
+ <14324 13151 12236 11852 11734>,
+ <14340 13158 12238 11860 11737>,
+ <14358 13165 12247 11865 11741>,
+ <14373 13167 12258 11870 11747>,
+ <14389 13165 12260 11873 11752>,
+ <14394 13167 12258 11877 11757>,
+ <14373 13169 12256 11880 11760>,
+ <14334 13168 12253 11886 11764>,
+ <14321 13167 12247 11892 11768>,
+ <14348 13170 12248 11897 11772>,
+ <14378 13177 12260 11901 11778>,
+ <14371 13182 12271 11905 11783>,
+ <14343 13188 12277 11910 11788>,
+ <14331 13194 12283 11917 11792>,
+ <14346 13205 12290 11924 11797>,
+ <14369 13219 12300 11931 11803>,
+ <14389 13228 12307 11937 11809>,
+ <14412 13237 12311 11941 11815>,
+ <14410 13245 12315 11945 11820>,
+ <14367 13259 12315 11949 11823>,
+ <14429 13239 12311 11954 11824>,
+ <14440 13243 12333 11959 11830>,
+ <14452 13241 12320 11961 11828>,
+ <14443 13243 12329 11964 11831>,
+ <14484 13241 12332 11968 11836>,
+ <14448 13263 12343 11977 11845>,
+ <14473 13293 12346 11988 11856>,
+ <14501 13300 12357 12000 11864>,
+ <14521 13333 12374 12015 11879>,
+ <14603 13373 12420 12034 11897>,
+ <14603 13373 12420 12034 11897>,
+ <14603 13373 12420 12034 11897>;
+ };
+
+ qcom,pc-temp-z2-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <9070 11213 10264 10349 10299>,
+ <9403 10211 10276 10386 10313>,
+ <9826 10116 10342 10430 10322>,
+ <9983 10114 10362 10447 10350>,
+ <9978 10115 10368 10437 10342>,
+ <9967 10120 10372 10407 10282>,
+ <9846 10126 10371 10393 10237>,
+ <9534 10132 10368 10388 10217>,
+ <9372 10137 10365 10382 10206>,
+ <9574 10141 10365 10378 10208>,
+ <9873 10143 10365 10386 10216>,
+ <9940 10145 10357 10384 10231>,
+ <9908 10147 10346 10370 10273>,
+ <9890 10148 10344 10357 10310>,
+ <9864 10149 10352 10353 10325>,
+ <9749 10147 10354 10353 10336>,
+ <9714 10144 10347 10355 10342>,
+ <10069 10146 10343 10360 10343>,
+ <10530 10156 10344 10366 10344>,
+ <10637 10166 10343 10378 10353>,
+ <10631 10154 10344 10396 10363>,
+ <10605 10119 10374 10405 10360>,
+ <10392 10103 10415 10412 10326>,
+ <10061 10118 10414 10414 10294>,
+ <9958 10135 10371 10402 10266>,
+ <9962 10132 10339 10387 10241>,
+ <9968 10117 10335 10377 10241>,
+ <9971 10107 10337 10360 10253>,
+ <9975 10109 10342 10353 10270>,
+ <9977 10112 10351 10373 10299>,
+ <9855 10116 10359 10397 10330>,
+ <9628 10123 10362 10398 10343>,
+ <9563 10131 10365 10389 10349>,
+ <9597 10143 10370 10392 10366>,
+ <9647 10159 10379 10443 10415>,
+ <9714 10166 10389 10499 10464>,
+ <9809 10169 10397 10520 10486>,
+ <9844 10172 10405 10533 10511>,
+ <9756 10186 10432 10548 10531>,
+ <9631 10212 10505 10586 10563>,
+ <9541 10225 10551 10621 10587>,
+ <9445 10161 10538 10637 10540>,
+ <9378 10144 10527 10646 10468>,
+ <9335 10322 10539 10611 10495>,
+ <9269 13378 10554 10627 10491>,
+ <9218 14361 10475 10629 10534>,
+ <9220 14794 10469 10642 10588>,
+ <9212 15070 10496 10651 10586>,
+ <9188 13785 10469 10739 10647>,
+ <9170 13219 10622 10694 10458>,
+ <9151 12652 10655 10557 10325>,
+ <9135 12236 10610 10495 10272>,
+ <9116 11644 10496 10432 10195>,
+ <9081 11027 10456 10300 10139>,
+ <9081 11027 10456 10300 10139>,
+ <9081 11027 10456 10300 10139>;
+ };
+
+ qcom,pc-temp-z3-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <19308 19258 19367 19369 19345>,
+ <19567 19611 19463 19395 19370>,
+ <19850 19705 19512 19411 19381>,
+ <19967 19740 19520 19416 19385>,
+ <19987 19749 19515 19414 19384>,
+ <19996 19735 19507 19405 19379>,
+ <19860 19713 19499 19400 19373>,
+ <19484 19698 19492 19395 19369>,
+ <19288 19687 19483 19391 19365>,
+ <19508 19679 19473 19388 19362>,
+ <19829 19673 19467 19382 19358>,
+ <19858 19667 19463 19378 19357>,
+ <19678 19660 19461 19372 19355>,
+ <19567 19648 19461 19369 19353>,
+ <19627 19641 19463 19369 19353>,
+ <19647 19646 19465 19368 19355>,
+ <19577 19654 19458 19367 19355>,
+ <19415 19653 19447 19366 19345>,
+ <19268 19631 19443 19365 19337>,
+ <19258 19613 19443 19365 19337>,
+ <19258 19623 19446 19366 19337>,
+ <19260 19652 19459 19374 19342>,
+ <19450 19665 19480 19393 19364>,
+ <19797 19666 19494 19403 19379>,
+ <19919 19667 19506 19402 19379>,
+ <19924 19671 19511 19400 19378>,
+ <19927 19681 19507 19400 19374>,
+ <19922 19686 19499 19400 19366>,
+ <19906 19684 19492 19399 19360>,
+ <19891 19680 19487 19397 19359>,
+ <19798 19673 19482 19393 19359>,
+ <19639 19661 19476 19390 19359>,
+ <19579 19650 19470 19386 19357>,
+ <19566 19644 19465 19382 19355>,
+ <19553 19639 19460 19380 19352>,
+ <19468 19636 19457 19378 19348>,
+ <19316 19630 19455 19375 19346>,
+ <19261 19624 19453 19373 19344>,
+ <19262 19618 19450 19371 19343>,
+ <19263 19609 19443 19369 19345>,
+ <19264 19576 19437 19368 19347>,
+ <19267 19367 19435 19368 19350>,
+ <19269 19261 19432 19367 19353>,
+ <19270 19260 19421 19365 19353>,
+ <19274 19257 19413 19361 19354>,
+ <19278 19257 19368 19354 19332>,
+ <19278 19257 19367 19346 19332>,
+ <19279 19257 19362 19331 19323>,
+ <19282 19257 19368 19326 19327>,
+ <19284 19257 19354 19338 19350>,
+ <19287 19257 19361 19346 19348>,
+ <19290 19257 19368 19356 19347>,
+ <19295 19257 19370 19353 19356>,
+ <19308 19258 19392 19382 19373>,
+ <19308 19258 19392 19382 19373>,
+ <19308 19258 19392 19382 19373>;
+ };
+
+ qcom,pc-temp-z4-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <16598 15992 15337 14972 14879>,
+ <16815 16035 15386 15059 14940>,
+ <16561 15923 15277 14982 14899>,
+ <16283 15657 15173 14901 14842>,
+ <15982 15436 15082 14879 14824>,
+ <15774 15304 15020 14868 14816>,
+ <15800 15207 14988 14856 14809>,
+ <15941 15154 14966 14843 14802>,
+ <16005 15119 14946 14830 14794>,
+ <15750 15094 14928 14818 14785>,
+ <15383 15076 14912 14807 14775>,
+ <15316 15063 14897 14797 14766>,
+ <15433 15048 14884 14788 14757>,
+ <15501 15033 14874 14778 14748>,
+ <15463 15025 14866 14769 14737>,
+ <15509 15037 14860 14760 14725>,
+ <15596 15057 14852 14751 14718>,
+ <15677 15056 14841 14742 14715>,
+ <15729 15002 14835 14738 14712>,
+ <15708 14951 14832 14736 14709>,
+ <15684 15017 14833 14735 14707>,
+ <15650 15207 14923 14756 14718>,
+ <15508 15302 15068 14837 14777>,
+ <15298 15313 15091 14879 14814>,
+ <15235 15319 15040 14870 14809>,
+ <15282 15294 14989 14855 14800>,
+ <15330 15200 14962 14841 14793>,
+ <15320 15131 14943 14826 14787>,
+ <15270 15105 14932 14814 14780>,
+ <15232 15088 14926 14805 14771>,
+ <15276 15076 14923 14798 14761>,
+ <15373 15065 14921 14794 14754>,
+ <15397 15057 14920 14791 14747>,
+ <15385 15051 14919 14789 14742>,
+ <15376 15043 14916 14787 14738>,
+ <15430 15036 14914 14786 14736>,
+ <15544 15016 14915 14794 14745>,
+ <15577 14998 14918 14811 14767>,
+ <15550 14991 14917 14816 14774>,
+ <15520 14987 14909 14811 14768>,
+ <15502 14998 14896 14803 14760>,
+ <15491 15139 14873 14788 14752>,
+ <15475 15211 14850 14774 14747>,
+ <15445 15195 14842 14774 14750>,
+ <15345 15130 14813 14764 14741>,
+ <15318 15079 14802 14736 14721>,
+ <15308 15066 14777 14720 14700>,
+ <15301 15057 14757 14705 14684>,
+ <15285 15045 14739 14698 14668>,
+ <15274 15053 14775 14717 14688>,
+ <15294 15076 14782 14719 14696>,
+ <15311 15080 14778 14712 14701>,
+ <15326 15091 14779 14719 14701>,
+ <15354 15108 14768 14706 14703>,
+ <15354 15108 14768 14706 14703>,
+ <15354 15108 14768 14706 14703>;
+ };
+
+ qcom,pc-temp-z5-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <10764 10957 12110 13794 13670>,
+ <11745 12925 13686 14768 14977>,
+ <12716 14010 14746 16056 16445>,
+ <13404 14718 15521 16744 17361>,
+ <13905 15321 16180 16789 17415>,
+ <14200 15933 16545 16568 17166>,
+ <13611 16455 16653 16420 16940>,
+ <11869 16730 16710 16364 16838>,
+ <10978 16895 16699 16401 16763>,
+ <12521 17062 16594 16402 16659>,
+ <14783 17315 16549 16292 16587>,
+ <15011 17507 16656 16178 16634>,
+ <13819 17490 16845 16003 16770>,
+ <13134 17527 17100 15977 16943>,
+ <13823 17638 17538 16159 17435>,
+ <14192 17626 17786 16425 18421>,
+ <13660 17482 17557 16723 18632>,
+ <12194 17384 17254 17131 17493>,
+ <10877 17447 17366 17305 16542>,
+ <10795 17704 18253 17609 16717>,
+ <10808 18910 18937 18108 17070>,
+ <10857 21136 18167 17900 17037>,
+ <13850 21892 16713 16569 16529>,
+ <19285 19957 16394 15708 16174>,
+ <21102 17736 16736 15560 16006>,
+ <20977 17560 17186 15557 15832>,
+ <20752 18050 17734 15845 15773>,
+ <20272 18693 18431 16567 15708>,
+ <19413 19705 19132 17289 15707>,
+ <18772 20743 19927 17959 16182>,
+ <17386 21034 20581 18611 16967>,
+ <15327 21059 21018 19179 17620>,
+ <14631 21034 21355 19699 18403>,
+ <14512 21133 21507 20256 19056>,
+ <14338 21373 21604 21000 19675>,
+ <13329 21460 21643 21494 20064>,
+ <11563 21322 21601 20994 19488>,
+ <10927 21163 21493 19730 18023>,
+ <10937 21134 21270 19156 17559>,
+ <10948 21040 20651 18991 17865>,
+ <10942 20318 20135 18929 18319>,
+ <10912 14582 19994 18903 18925>,
+ <10885 11608 19761 18788 19444>,
+ <10861 11587 18126 17802 18686>,
+ <10871 11314 17978 17266 18426>,
+ <10857 11130 15054 17271 15914>,
+ <10841 11088 15214 17078 16658>,
+ <10831 11067 15184 16484 17071>,
+ <10841 11046 15966 16365 19357>,
+ <10877 11142 14378 15551 19427>,
+ <10922 11156 14140 15626 17699>,
+ <10887 11109 14272 16679 16814>,
+ <10848 11069 14202 15606 17668>,
+ <10790 10995 15166 19180 19716>,
+ <10790 10995 15166 19180 19716>,
+ <10790 10995 15166 19180 19716>;
+ };
+
+ qcom,pc-temp-z6-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <17029 15901 15123 14807 14723>,
+ <17156 16022 15165 14844 14750>,
+ <17081 15990 15131 14815 14734>,
+ <16977 15851 15090 14780 14711>,
+ <16818 15720 15039 14766 14700>,
+ <16645 15630 15000 14756 14693>,
+ <16486 15560 14978 14746 14686>,
+ <16331 15519 14962 14737 14680>,
+ <16255 15490 14945 14728 14674>,
+ <16244 15468 14929 14720 14668>,
+ <16238 15452 14916 14712 14662>,
+ <16217 15438 14905 14704 14656>,
+ <16172 15422 14897 14697 14651>,
+ <16139 15401 14891 14691 14646>,
+ <16146 15390 14887 14686 14642>,
+ <16166 15395 14883 14681 14638>,
+ <16163 15403 14876 14677 14633>,
+ <16120 15402 14866 14672 14627>,
+ <16076 15372 14862 14670 14622>,
+ <16063 15345 14862 14670 14621>,
+ <16057 15380 14865 14671 14621>,
+ <16055 15480 14915 14684 14629>,
+ <16092 15533 14991 14732 14668>,
+ <16168 15543 15006 14757 14692>,
+ <16218 15549 14992 14753 14691>,
+ <16251 15541 14976 14746 14687>,
+ <16270 15511 14964 14741 14683>,
+ <16266 15488 14954 14735 14676>,
+ <16246 15479 14948 14730 14671>,
+ <16227 15473 14944 14726 14666>,
+ <16204 15467 14942 14722 14662>,
+ <16176 15459 14941 14719 14659>,
+ <16164 15454 14939 14716 14657>,
+ <16159 15453 14938 14715 14654>,
+ <16154 15453 14937 14714 14651>,
+ <16145 15453 14936 14714 14649>,
+ <16133 15450 14939 14717 14652>,
+ <16130 15447 14943 14725 14662>,
+ <16133 15449 14943 14727 14665>,
+ <16139 15454 14940 14725 14664>,
+ <16147 15454 14936 14723 14663>,
+ <16161 15429 14929 14718 14662>,
+ <16171 15417 14922 14712 14662>,
+ <16178 15424 14918 14713 14664>,
+ <16162 15408 14909 14708 14663>,
+ <16165 15399 14883 14694 14643>,
+ <16168 15398 14875 14684 14633>,
+ <16172 15401 14867 14670 14622>,
+ <16179 15405 14866 14665 14618>,
+ <16193 15425 14881 14682 14641>,
+ <16228 15451 14892 14690 14645>,
+ <16262 15468 14902 14695 14650>,
+ <16300 15497 14912 14700 14657>,
+ <16361 15535 14930 14716 14672>,
+ <16361 15535 14930 14716 14672>,
+ <16361 15535 14930 14716 14672>;
+ };
+
+ qcom,pc-temp-y1-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <7929 6704 6050 5566 5322 5235>,
+ <8028 6701 6050 5560 5320 5234>,
+ <8101 6693 6051 5554 5318 5233>,
+ <8151 6684 6051 5548 5316 5231>,
+ <8179 6676 6052 5543 5313 5230>,
+ <8186 6673 6053 5540 5311 5228>,
+ <8157 6667 6054 5539 5308 5225>,
+ <8120 6659 6054 5538 5305 5222>,
+ <8110 6663 6055 5536 5302 5222>,
+ <8104 6693 6056 5529 5299 5222>,
+ <8099 6717 6055 5525 5298 5222>,
+ <8120 6716 6050 5525 5297 5220>,
+ <8146 6707 6044 5526 5296 5217>,
+ <8147 6706 6044 5528 5295 5216>,
+ <8147 6707 6049 5533 5293 5217>,
+ <8146 6709 6052 5536 5291 5217>,
+ <8135 6705 6053 5534 5290 5219>,
+ <8119 6699 6055 5532 5288 5221>,
+ <8100 6700 6057 5532 5289 5221>,
+ <8079 6708 6062 5531 5290 5220>,
+ <8070 6715 6065 5531 5292 5219>,
+ <8070 6712 6067 5532 5294 5220>,
+ <8076 6706 6071 5532 5296 5222>,
+ <8117 6703 6071 5532 5297 5223>,
+ <8170 6702 6070 5532 5298 5225>,
+ <8167 6702 6069 5532 5299 5227>,
+ <8118 6700 6068 5535 5301 5229>,
+ <8084 6699 6065 5539 5305 5232>,
+ <8087 6697 6062 5540 5309 5236>,
+ <8100 6691 6059 5541 5311 5240>,
+ <8092 6688 6059 5542 5314 5243>,
+ <8059 6691 6063 5546 5317 5244>,
+ <8043 6695 6069 5550 5320 5245>,
+ <8027 6693 6072 5553 5324 5247>,
+ <8011 6677 6077 5556 5329 5251>,
+ <8021 6667 6080 5558 5333 5255>,
+ <8050 6679 6081 5563 5336 5258>,
+ <8082 6697 6082 5568 5339 5261>,
+ <8123 6698 6085 5570 5342 5263>,
+ <8148 6684 6094 5571 5348 5265>,
+ <8101 6675 6101 5572 5352 5268>,
+ <8041 6691 6098 5581 5353 5271>,
+ <8104 6707 6096 5586 5356 5275>,
+ <8088 6704 6102 5586 5363 5282>,
+ <8048 6708 6104 5593 5368 5284>,
+ <8055 6725 6098 5595 5370 5288>,
+ <8059 6724 6114 5601 5370 5288>,
+ <8092 6743 6089 5598 5376 5290>,
+ <8157 6750 6086 5605 5374 5291>,
+ <8197 6722 6104 5609 5381 5293>,
+ <8269 6738 6105 5608 5384 5292>,
+ <8288 6759 6112 5624 5392 5304>,
+ <8380 6766 6128 5643 5400 5313>,
+ <8422 6779 6149 5656 5417 5324>,
+ <8422 6779 6149 5656 5417 5324>,
+ <8422 6779 6149 5656 5417 5324>;
+ };
+
+ qcom,pc-temp-y2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <9654 9643 10639 11070 11121 11086>,
+ <9654 9643 10662 11056 11097 11058>,
+ <9655 9643 10675 11037 11063 11029>,
+ <9655 9871 10680 11014 11027 11001>,
+ <9656 10190 10680 10988 10997 10976>,
+ <9656 10325 10677 10959 10981 10958>,
+ <9657 10308 10664 10918 10973 10946>,
+ <9657 10282 10644 10881 10967 10935>,
+ <9657 10301 10632 10875 10959 10916>,
+ <9658 10440 10623 10874 10933 10882>,
+ <9658 10534 10619 10874 10919 10864>,
+ <9658 10489 10626 10869 10936 10874>,
+ <9659 10417 10643 10861 10961 10888>,
+ <9658 10413 10676 10856 10952 10885>,
+ <9657 10487 10748 10851 10897 10860>,
+ <9657 10553 10801 10851 10866 10840>,
+ <9657 10580 10826 10885 10876 10837>,
+ <9657 10597 10843 10946 10896 10845>,
+ <9657 10521 10842 11018 10943 10884>,
+ <9656 10042 10822 11115 11060 10984>,
+ <9656 9696 10809 11159 11120 11034>,
+ <9656 9682 10815 11129 11098 11013>,
+ <9656 9676 10826 11091 11071 10987>,
+ <9656 9675 10835 11085 11079 11009>,
+ <9656 9676 10846 11088 11121 11106>,
+ <9655 9676 10848 11093 11154 11162>,
+ <9655 9675 10684 11108 11176 11166>,
+ <9655 9671 10460 11130 11199 11168>,
+ <9655 9668 10652 11152 11224 11182>,
+ <9654 9665 11565 11178 11263 11214>,
+ <9654 9662 12069 11192 11286 11238>,
+ <9654 9660 11796 11199 11310 11257>,
+ <9654 9659 11319 11203 11338 11277>,
+ <9654 9657 10963 11202 11344 11307>,
+ <9654 9656 10643 11198 11320 11345>,
+ <9654 9655 10423 11189 11299 11359>,
+ <9653 9654 10140 11148 11294 11325>,
+ <9653 9653 9828 11108 11301 11280>,
+ <9653 9653 9733 11099 11301 11271>,
+ <9653 9653 9707 11096 11290 11278>,
+ <9653 9652 9692 11071 11287 11277>,
+ <9653 9652 9681 10975 11329 11250>,
+ <9653 9652 9674 10939 11356 11231>,
+ <9653 9652 9668 10913 11303 11229>,
+ <9653 9652 9664 10802 11253 11135>,
+ <9653 9652 9663 10839 11180 11044>,
+ <9653 9652 9661 10832 11146 11009>,
+ <9652 9652 9660 10811 11105 10962>,
+ <9652 9651 9659 10794 11061 10965>,
+ <9651 9651 9658 10764 11053 10938>,
+ <9650 9651 9658 10711 10981 10871>,
+ <9650 9651 9656 10651 10927 10829>,
+ <9649 9651 9654 10594 10851 10747>,
+ <9648 9651 9654 10531 10798 10659>,
+ <9648 9651 9654 10531 10798 10659>,
+ <9648 9651 9654 10531 10798 10659>;
+ };
+
+ qcom,pc-temp-y3-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <14501 13677 13390 13309 13301 13279>,
+ <14412 13657 13393 13309 13294 13279>,
+ <14328 13634 13397 13311 13289 13279>,
+ <14249 13612 13400 13312 13285 13279>,
+ <14179 13596 13403 13314 13283 13279>,
+ <14117 13590 13406 13315 13282 13279>,
+ <14063 13594 13408 13315 13283 13280>,
+ <14017 13600 13410 13316 13286 13281>,
+ <13976 13594 13412 13317 13287 13282>,
+ <13939 13548 13416 13319 13287 13282>,
+ <13929 13515 13419 13321 13287 13282>,
+ <13957 13513 13421 13322 13289 13282>,
+ <13986 13512 13423 13323 13291 13282>,
+ <13945 13509 13422 13325 13291 13283>,
+ <13843 13504 13414 13328 13291 13284>,
+ <13803 13497 13407 13329 13291 13286>,
+ <13797 13488 13401 13328 13292 13287>,
+ <13793 13478 13395 13325 13294 13288>,
+ <13788 13470 13387 13324 13297 13290>,
+ <13783 13465 13376 13323 13301 13294>,
+ <13783 13458 13367 13322 13303 13296>,
+ <13788 13428 13360 13315 13297 13290>,
+ <13796 13384 13354 13306 13287 13281>,
+ <13814 13362 13349 13303 13283 13278>,
+ <13843 13349 13346 13300 13281 13277>,
+ <13874 13344 13341 13299 13280 13277>,
+ <13910 13351 13308 13299 13280 13277>,
+ <13952 13369 13266 13299 13282 13277>,
+ <13999 13391 13259 13298 13282 13277>,
+ <14052 13422 13259 13299 13283 13277>,
+ <14110 13460 13258 13299 13283 13277>,
+ <14174 13503 13258 13298 13283 13277>,
+ <14243 13554 13259 13298 13283 13277>,
+ <14318 13615 13263 13298 13283 13277>,
+ <14398 13690 13285 13299 13283 13278>,
+ <14481 13777 13302 13299 13283 13278>,
+ <14568 13879 13294 13296 13281 13277>,
+ <14658 13996 13281 13292 13279 13276>,
+ <14750 14118 13282 13292 13278 13276>,
+ <14850 14247 13299 13292 13277 13277>,
+ <14963 14377 13319 13293 13277 13277>,
+ <15082 14502 13343 13295 13277 13278>,
+ <15198 14624 13368 13298 13277 13278>,
+ <15302 14737 13402 13303 13278 13276>,
+ <15264 14824 13470 13304 13280 13278>,
+ <15439 14801 13476 13307 13284 13280>,
+ <15557 14824 13517 13316 13291 13286>,
+ <15783 14890 13560 13319 13292 13287>,
+ <16058 14961 13607 13332 13295 13287>,
+ <16423 15021 13665 13332 13292 13286>,
+ <16935 15095 13703 13333 13294 13286>,
+ <17701 15215 13779 13341 13296 13289>,
+ <18847 15382 13934 13350 13299 13292>,
+ <20636 15571 14143 13370 13308 13299>,
+ <20636 15571 14143 13370 13308 13299>,
+ <20636 15571 14143 13370 13308 13299>;
+ };
+
+ qcom,pc-temp-y4-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <17448 17305 16798 16610 16483 16470>,
+ <17520 17330 16862 16610 16486 16469>,
+ <17601 17378 16934 16609 16489 16468>,
+ <17679 17433 17001 16608 16491 16467>,
+ <17744 17479 17051 16607 16493 16467>,
+ <17783 17501 17070 16605 16493 16466>,
+ <17798 17503 17059 16603 16493 16466>,
+ <17813 17504 17041 16601 16492 16466>,
+ <17918 17511 17030 16599 16493 16466>,
+ <18180 17550 17023 16599 16497 16470>,
+ <18279 17608 17020 16599 16500 16473>,
+ <18148 17742 17034 16602 16502 16478>,
+ <17945 17902 17062 16609 16506 16483>,
+ <17736 17876 17086 16619 16512 16487>,
+ <17506 17547 17110 16638 16523 16492>,
+ <17399 17320 17134 16659 16535 16498>,
+ <17363 17344 17161 16679 16546 16506>,
+ <17328 17386 17183 16703 16560 16518>,
+ <17266 17370 17170 16748 16586 16537>,
+ <17193 17216 17080 16821 16630 16569>,
+ <17141 17060 16974 16852 16651 16585>,
+ <17100 16974 16865 16754 16602 16552>,
+ <17077 16908 16761 16616 16529 16502>,
+ <17070 16873 16703 16567 16502 16483>,
+ <17066 16851 16662 16543 16489 16473>,
+ <17066 16841 16647 16535 16485 16469>,
+ <17066 16841 16681 16535 16485 16470>,
+ <17067 16842 16727 16535 16487 16471>,
+ <17070 16843 16732 16537 16489 16474>,
+ <17074 16844 16721 16543 16497 16482>,
+ <17079 16845 16716 16549 16507 16491>,
+ <17088 16852 16721 16554 16521 16504>,
+ <17095 16866 16730 16558 16535 16515>,
+ <17099 16879 16732 16556 16540 16518>,
+ <17103 16893 16714 16549 16540 16515>,
+ <17111 16906 16704 16540 16534 16509>,
+ <17124 16920 16735 16528 16505 16492>,
+ <17134 16932 16784 16517 16477 16475>,
+ <17142 16941 16805 16517 16476 16471>,
+ <17149 16947 16815 16522 16479 16469>,
+ <17157 16950 16818 16530 16481 16469>,
+ <17167 16948 16818 16544 16482 16469>,
+ <17187 16945 16817 16555 16481 16467>,
+ <17208 16947 16815 16561 16471 16454>,
+ <17140 16965 16826 16575 16477 16456>,
+ <17176 16961 16849 16584 16493 16477>,
+ <17202 16977 16893 16606 16503 16495>,
+ <17281 17046 16954 16635 16528 16531>,
+ <17390 17107 17025 16679 16557 16532>,
+ <17524 17131 17054 16682 16515 16493>,
+ <17690 17101 17038 16673 16527 16498>,
+ <17978 17060 17051 16712 16548 16514>,
+ <18577 17063 17124 16764 16588 16554>,
+ <20156 17135 17255 16879 16727 16719>,
+ <20156 17135 17255 16879 16727 16719>,
+ <20156 17135 17255 16879 16727 16719>;
+ };
+
+ qcom,pc-temp-y5-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <10030 8712 14223 14774 19943 16308>,
+ <10448 8888 14349 15148 18667 15835>,
+ <10794 10562 14526 15365 17009 15457>,
+ <11054 12204 14713 15466 15353 15176>,
+ <11214 13579 14867 15489 14086 14997>,
+ <11260 14452 14948 15472 13593 14920>,
+ <11143 14948 14973 15335 13800 15003>,
+ <11001 15270 14986 15151 14123 15144>,
+ <11151 15028 14986 15098 14118 15087>,
+ <11850 13370 14973 15056 13826 14716>,
+ <12871 12246 14930 14978 13664 14315>,
+ <15188 13353 14287 14743 13788 13961>,
+ <17100 15163 13386 14398 13870 13634>,
+ <15786 15495 13334 14078 13643 13482>,
+ <12439 15197 13853 13740 13191 13549>,
+ <11406 14993 14346 13497 12887 13638>,
+ <11547 15443 14672 13207 12793 13546>,
+ <11662 16191 15006 12923 12796 13423>,
+ <11574 16138 15417 13004 13001 13548>,
+ <11364 14708 15994 13654 13569 14033>,
+ <11181 13284 16419 14434 14193 14440>,
+ <10986 12599 16670 15491 14905 14826>,
+ <10835 12068 16832 16433 15541 15160>,
+ <10734 11544 16827 16644 15650 15196>,
+ <10666 10962 16682 16591 15306 15346>,
+ <10655 10655 16390 16622 15048 15474>,
+ <10654 10648 14341 16597 15293 15494>,
+ <10654 10645 11728 16540 15744 15472>,
+ <10689 10665 11156 16578 15865 15229>,
+ <10734 10802 11032 16695 15749 14663>,
+ <10745 10946 10959 16756 15607 14352>,
+ <10765 11017 10901 16831 15502 14290>,
+ <10797 11076 10865 16959 15400 14311>,
+ <10882 11177 11054 17363 15705 14665>,
+ <10953 11367 12196 18097 16573 15740>,
+ <10940 11520 13011 18310 16919 16424>,
+ <10897 11584 12496 17269 16620 16376>,
+ <10863 11627 11602 15914 16091 16215>,
+ <10835 11630 11486 15213 15448 16327>,
+ <10820 11595 11681 14700 14692 16543>,
+ <10867 11570 11787 14330 14365 16550>,
+ <10955 11579 11797 14105 14243 16259>,
+ <11030 11596 11778 14219 14209 16346>,
+ <11029 11509 11647 14611 15058 16893>,
+ <11044 11331 11779 14198 14882 16382>,
+ <11143 11388 11508 14156 14882 14589>,
+ <11321 11488 11654 14603 16012 16142>,
+ <11356 11493 11662 14001 15040 14960>,
+ <11206 11613 11939 14918 15399 14828>,
+ <10932 11747 12726 15439 17093 17327>,
+ <10539 11665 12655 15981 17753 17255>,
+ <10263 11585 12280 16288 17881 17960>,
+ <9994 11459 12118 16141 17436 18200>,
+ <9668 11818 11932 16090 17352 17825>,
+ <9668 11818 11932 16090 17352 17825>,
+ <9668 11818 11932 16090 17352 17825>;
+ };
+
+ qcom,pc-temp-y6-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <7467 6132 5538 5158 5055 5027>,
+ <7418 6176 5550 5158 5053 5026>,
+ <7371 6205 5557 5158 5050 5025>,
+ <7326 6223 5561 5157 5048 5025>,
+ <7283 6232 5562 5156 5046 5025>,
+ <7242 6234 5562 5154 5046 5025>,
+ <7194 6227 5555 5152 5046 5025>,
+ <7159 6211 5540 5150 5047 5026>,
+ <7167 6191 5531 5149 5047 5027>,
+ <7202 6161 5522 5149 5048 5028>,
+ <7216 6144 5519 5149 5049 5029>,
+ <7195 6170 5520 5150 5051 5030>,
+ <7155 6214 5522 5151 5053 5031>,
+ <7075 6207 5523 5154 5055 5033>,
+ <6953 6119 5523 5160 5058 5035>,
+ <6899 6058 5522 5167 5061 5038>,
+ <6884 6060 5524 5172 5065 5041>,
+ <6872 6065 5527 5177 5070 5045>,
+ <6853 6054 5521 5188 5079 5052>,
+ <6834 5986 5487 5208 5095 5064>,
+ <6828 5923 5449 5216 5102 5070>,
+ <6826 5892 5413 5184 5083 5056>,
+ <6825 5871 5381 5138 5056 5035>,
+ <6839 5868 5365 5122 5045 5028>,
+ <6867 5872 5355 5114 5040 5024>,
+ <6893 5878 5349 5111 5038 5023>,
+ <6923 5895 5343 5112 5039 5023>,
+ <6956 5926 5339 5113 5040 5024>,
+ <6991 5960 5339 5115 5042 5026>,
+ <7030 5999 5342 5118 5045 5028>,
+ <7074 6044 5346 5121 5048 5031>,
+ <7122 6096 5354 5124 5053 5034>,
+ <7175 6156 5367 5126 5057 5038>,
+ <7232 6222 5383 5127 5059 5039>,
+ <7293 6297 5405 5127 5060 5039>,
+ <7357 6380 5430 5127 5058 5038>,
+ <7425 6470 5458 5124 5049 5032>,
+ <7495 6568 5491 5120 5041 5027>,
+ <7567 6667 5530 5121 5040 5027>,
+ <7643 6768 5579 5127 5041 5027>,
+ <7727 6867 5632 5133 5042 5028>,
+ <7816 6963 5689 5144 5044 5028>,
+ <7908 7053 5751 5155 5044 5028>,
+ <7994 7135 5817 5167 5043 5024>,
+ <7959 7206 5905 5181 5046 5026>,
+ <8096 7192 5921 5188 5056 5034>,
+ <8195 7214 5976 5205 5063 5044>,
+ <8412 7280 6034 5219 5072 5055>,
+ <8678 7350 6096 5248 5083 5055>,
+ <9031 7405 6155 5252 5069 5043>,
+ <9521 7454 6196 5257 5074 5046>,
+ <10251 7535 6282 5285 5084 5053>,
+ <11352 7666 6442 5320 5100 5069>,
+ <13075 7846 6646 5385 5148 5123>,
+ <13075 7846 6646 5385 5148 5123>,
+ <13075 7846 6646 5385 5148 5123>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-n10-byd-4360mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-n10-byd-4360mah.dtsi
new file mode 100644
index 0000000..18427af
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-n10-byd-4360mah.dtsi
@@ -0,0 +1,1049 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+qcom,ottawa_byd_4500mAh {
+ /* 4363603_TCL_T1_Pro_4500mAH_PM6150_averaged_MasterSlave_Mar2th2020 */
+ qcom,max-voltage-uv = <4400000>;
+ qcom,fg-cc-cv-threshold-uv = <4390000>;
+ qcom,fastchg-current-ma = <3500>;
+ qcom,batt-id-kohm = <18>;
+ qcom,battery-beta = <3435>;
+ qcom,battery-therm-kohm = <10>;
+ qcom,battery-type = "ottawa-byd-v3";
+ qcom,qg-batt-profile-ver = <100>;
+
+ qcom,jeita-fcc-ranges = <0 130 1200000
+ 131 430 3500000
+ 431 550 2000000
+ 551 600 0>;
+ qcom,jeita-fv-ranges = <0 130 4400000
+ 131 430 4400000
+ 431 600 4100000>;
+ qcom,step-chg-ranges = <2800000 4250000 3500000
+ 4250001 4400000 2800000>;
+ qcom,ocv-based-step-chg;
+
+ /* COOL = 10 DegC, WARM = 45 DegC */
+ qcom,jeita-soft-thresholds = <0x2aee 0xfb3>;
+ /* COLD = 0 DegC, HOT = 55 DegC */
+ qcom,jeita-hard-thresholds = <0x3733 0xbc2>;
+ /* COOL hys = 13 DegC, WARM hys = 42 DegC */
+ qcom,jeita-soft-hys-thresholds = <0x279a 0x1124>;
+
+ qcom,jeita-soft-fcc-ua = <2000000 2000000>;
+ qcom,jeita-soft-fv-uv = <4100000 4100000>;
+
+ qcom,fcc1-temp-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-data = <4291 4368 4478 4521 4535>;
+ };
+
+ qcom,fcc2-temp-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-data = <4465 4464 4470 4466 4474 4471>;
+ };
+
+ qcom,pc-temp-v1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <43544 43714 43823 43852 43861>,
+ <43278 43458 43594 43642 43655>,
+ <43027 43209 43362 43421 43436>,
+ <42788 42966 43125 43194 43213>,
+ <42558 42728 42887 42959 42982>,
+ <42335 42492 42648 42721 42747>,
+ <42118 42263 42411 42485 42510>,
+ <41906 42043 42175 42248 42272>,
+ <41701 41830 41946 42014 42038>,
+ <41505 41622 41720 41782 41807>,
+ <41319 41418 41500 41552 41579>,
+ <41130 41220 41288 41326 41353>,
+ <40928 41029 41082 41104 41130>,
+ <40703 40844 40881 40895 40914>,
+ <40432 40634 40677 40697 40704>,
+ <40136 40352 40463 40503 40501>,
+ <39918 40062 40226 40303 40306>,
+ <39785 39886 40006 40105 40119>,
+ <39681 39782 39851 39929 39943>,
+ <39573 39678 39733 39781 39789>,
+ <39465 39538 39587 39621 39626>,
+ <39351 39371 39347 39382 39397>,
+ <39218 39179 39084 39096 39114>,
+ <39072 38929 38900 38898 38912>,
+ <38926 38711 38755 38774 38792>,
+ <38780 38604 38643 38673 38691>,
+ <38649 38535 38559 38577 38578>,
+ <38552 38477 38489 38489 38467>,
+ <38471 38425 38421 38404 38371>,
+ <38409 38380 38356 38319 38290>,
+ <38366 38339 38296 38242 38218>,
+ <38332 38301 38239 38175 38154>,
+ <38302 38265 38186 38115 38097>,
+ <38275 38232 38137 38059 38038>,
+ <38251 38200 38092 38007 37979>,
+ <38224 38167 38049 37957 37920>,
+ <38197 38134 38009 37909 37863>,
+ <38161 38094 37968 37862 37806>,
+ <38100 38030 37907 37795 37732>,
+ <38018 37941 37820 37700 37630>,
+ <37918 37840 37719 37593 37516>,
+ <37789 37718 37607 37486 37406>,
+ <37652 37578 37477 37364 37284>,
+ <37504 37413 37310 37199 37119>,
+ <37379 37265 37170 37066 36995>,
+ <37279 37171 37075 36987 36926>,
+ <37241 37145 37046 36957 36896>,
+ <37212 37127 37030 36939 36877>,
+ <37181 37102 37014 36919 36855>,
+ <37130 37062 36969 36867 36797>,
+ <36938 36861 36753 36622 36527>,
+ <36510 36428 36317 36188 36091>,
+ <35940 35859 35745 35616 35519>,
+ <35174 35083 34971 34838 34738>,
+ <33961 33854 33748 33625 33515>,
+ <30000 30000 30000 30000 30000>;
+ };
+
+ qcom,pc-temp-v2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <43895 43830 43835 43780 43755 43730>,
+ <43465 43467 43536 43498 43494 43477>,
+ <43080 43133 43252 43228 43238 43229>,
+ <42748 42832 42984 42970 42990 42986>,
+ <42459 42557 42733 42725 42748 42749>,
+ <42198 42307 42487 42484 42508 42512>,
+ <41957 42093 42240 42246 42270 42275>,
+ <41736 41892 41999 42010 42033 42038>,
+ <41531 41648 41772 41779 41800 41805>,
+ <41333 41328 41558 41552 41570 41572>,
+ <41177 41110 41350 41331 41343 41345>,
+ <41089 41059 41154 41122 41124 41125>,
+ <41016 41029 40960 40917 40908 40910>,
+ <40821 40903 40740 40702 40699 40701>,
+ <40220 40372 40482 40470 40491 40495>,
+ <39670 39872 40229 40247 40292 40297>,
+ <39456 39686 40013 40047 40103 40106>,
+ <39313 39563 39814 39864 39924 39924>,
+ <39146 39404 39619 39704 39753 39752>,
+ <38945 39191 39428 39575 39600 39597>,
+ <38758 38969 39236 39431 39431 39429>,
+ <38606 38753 39033 39207 39202 39203>,
+ <38476 38544 38831 38931 38944 38948>,
+ <38377 38391 38661 38726 38748 38751>,
+ <38302 38282 38520 38579 38600 38602>,
+ <38237 38198 38392 38456 38475 38476>,
+ <38174 38135 38266 38348 38364 38362>,
+ <38115 38085 38147 38252 38264 38261>,
+ <38059 38037 38055 38164 38175 38170>,
+ <38007 37993 37984 38080 38095 38089>,
+ <37955 37950 37929 38004 38023 38017>,
+ <37902 37909 37889 37935 37959 37951>,
+ <37849 37868 37858 37872 37903 37891>,
+ <37793 37825 37826 37816 37839 37826>,
+ <37737 37781 37794 37770 37768 37755>,
+ <37678 37734 37759 37725 37692 37676>,
+ <37614 37683 37721 37672 37610 37580>,
+ <37545 37628 37678 37614 37525 37471>,
+ <37472 37565 37623 37546 37442 37375>,
+ <37393 37489 37544 37469 37364 37297>,
+ <37312 37399 37446 37381 37282 37220>,
+ <37236 37288 37329 37278 37186 37125>,
+ <37164 37160 37190 37157 37074 37011>,
+ <37095 37039 37038 37027 36948 36887>,
+ <37027 36933 36904 36912 36845 36791>,
+ <36950 36864 36836 36856 36801 36749>,
+ <36904 36834 36813 36836 36790 36737>,
+ <36847 36798 36788 36817 36772 36720>,
+ <36771 36750 36747 36789 36742 36688>,
+ <36657 36651 36667 36718 36655 36586>,
+ <36429 36417 36439 36458 36338 36238>,
+ <36030 35978 35970 35987 35840 35737>,
+ <35442 35346 35332 35368 35192 35073>,
+ <34582 34448 34451 34531 34306 34168>,
+ <33177 33014 33092 33262 33030 32907>,
+ <28802 27992 27897 27933 28022 27983>;
+ };
+
+ qcom,pc-temp-z1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <12902 12262 11778 11474 11333>,
+ <12923 12298 11785 11476 11335>,
+ <12915 12291 11783 11470 11331>,
+ <12899 12278 11772 11461 11325>,
+ <12880 12267 11758 11447 11315>,
+ <12864 12248 11747 11433 11306>,
+ <12853 12225 11736 11421 11298>,
+ <12841 12207 11724 11409 11291>,
+ <12834 12192 11711 11400 11285>,
+ <12833 12184 11698 11393 11282>,
+ <12834 12180 11692 11389 11280>,
+ <12831 12177 11692 11390 11278>,
+ <12802 12165 11691 11391 11277>,
+ <12754 12139 11686 11391 11275>,
+ <12709 12124 11673 11382 11274>,
+ <12669 12124 11666 11374 11273>,
+ <12654 12126 11665 11373 11273>,
+ <12666 12126 11666 11374 11274>,
+ <12688 12132 11667 11376 11275>,
+ <12702 12140 11674 11379 11276>,
+ <12710 12147 11680 11381 11277>,
+ <12718 12156 11685 11383 11278>,
+ <12733 12159 11690 11385 11278>,
+ <12751 12157 11694 11387 11280>,
+ <12756 12156 11699 11390 11281>,
+ <12750 12163 11703 11392 11283>,
+ <12744 12177 11708 11396 11286>,
+ <12748 12183 11712 11401 11290>,
+ <12761 12182 11719 11406 11294>,
+ <12769 12179 11726 11411 11297>,
+ <12768 12181 11732 11417 11301>,
+ <12767 12191 11737 11422 11306>,
+ <12772 12197 11740 11428 11310>,
+ <12787 12199 11744 11434 11316>,
+ <12804 12201 11748 11440 11321>,
+ <12814 12206 11752 11447 11327>,
+ <12825 12216 11759 11454 11332>,
+ <12833 12226 11767 11461 11337>,
+ <12838 12233 11774 11467 11343>,
+ <12842 12240 11780 11473 11348>,
+ <12850 12248 11785 11479 11353>,
+ <12872 12257 11792 11488 11359>,
+ <12900 12267 11801 11498 11364>,
+ <12933 12277 11819 11502 11368>,
+ <12953 12303 11826 11507 11373>,
+ <12941 12312 11825 11512 11375>,
+ <12936 12307 11822 11515 11374>,
+ <12943 12311 11835 11516 11375>,
+ <12917 12310 11834 11520 11379>,
+ <12922 12311 11829 11529 11386>,
+ <12945 12325 11850 11536 11395>,
+ <12969 12340 11861 11543 11403>,
+ <13024 12377 11867 11559 11414>,
+ <13078 12420 11901 11579 11428>,
+ <13078 12420 11901 11579 11428>,
+ <13078 12420 11901 11579 11428>;
+ };
+
+ qcom,pc-temp-z2-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <10785 10208 10547 10180 10170>,
+ <10201 10493 10627 10322 10160>,
+ <10245 10526 10660 10413 10269>,
+ <10269 10518 10640 10439 10308>,
+ <10270 10499 10567 10409 10274>,
+ <10272 10458 10499 10370 10233>,
+ <10281 10416 10453 10332 10216>,
+ <10288 10387 10416 10282 10201>,
+ <10292 10363 10390 10245 10179>,
+ <10288 10347 10372 10229 10131>,
+ <10276 10335 10367 10226 10080>,
+ <10284 10328 10374 10240 10045>,
+ <10342 10427 10379 10258 10014>,
+ <10375 10815 10378 10253 10002>,
+ <10324 11057 10390 10177 10018>,
+ <10243 10853 10401 10105 10042>,
+ <10213 10517 10400 10098 10059>,
+ <10205 10430 10392 10101 10075>,
+ <10197 10431 10387 10108 10090>,
+ <10195 10435 10394 10130 10103>,
+ <10203 10471 10421 10169 10120>,
+ <10215 10535 10554 10321 10202>,
+ <10239 10556 10695 10556 10340>,
+ <10277 10543 10669 10588 10365>,
+ <10307 10529 10527 10361 10270>,
+ <10327 10538 10454 10182 10194>,
+ <10344 10567 10457 10188 10428>,
+ <10359 10584 10463 10226 10977>,
+ <10374 10587 10481 10296 11141>,
+ <10386 10587 10525 10494 10874>,
+ <10391 10588 10566 10641 10543>,
+ <10395 10594 10605 10595 10307>,
+ <10396 10600 10640 10476 10106>,
+ <10398 10605 10643 10378 10052>,
+ <10400 10610 10626 10288 10049>,
+ <10405 10617 10616 10239 10049>,
+ <10415 10624 10620 10244 10073>,
+ <10427 10634 10632 10261 10133>,
+ <10446 10654 10658 10296 10192>,
+ <10465 10683 10723 10396 10257>,
+ <10471 10697 10761 10465 10298>,
+ <10472 10697 10750 10427 10304>,
+ <10417 10696 10740 10381 10309>,
+ <10193 10696 10747 10494 10367>,
+ <11963 10818 10738 10486 10352>,
+ <11905 10826 10747 10403 10281>,
+ <12046 10807 10722 10400 10260>,
+ <12088 10820 10692 10416 10278>,
+ <11990 10816 10639 10419 10297>,
+ <12129 10877 10680 10504 10406>,
+ <11455 10917 10705 10450 10302>,
+ <10891 10899 10678 10275 10092>,
+ <10730 10690 10632 10206 10033>,
+ <9900 10598 10515 10168 9987>,
+ <9900 10598 10515 10168 9987>,
+ <9900 10598 10515 10168 9987>;
+ };
+
+ qcom,pc-temp-z3-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <19513 19368 19338 19329 19340>,
+ <19592 19467 19389 19364 19358>,
+ <19657 19508 19423 19389 19379>,
+ <19687 19531 19435 19404 19392>,
+ <19690 19540 19441 19413 19401>,
+ <19685 19543 19444 19419 19406>,
+ <19678 19545 19447 19422 19411>,
+ <19668 19543 19448 19424 19414>,
+ <19657 19538 19448 19424 19415>,
+ <19644 19533 19446 19419 19410>,
+ <19630 19528 19443 19414 19403>,
+ <19626 19523 19439 19411 19398>,
+ <19626 19521 19434 19409 19396>,
+ <19627 19520 19426 19404 19393>,
+ <19627 19519 19415 19393 19389>,
+ <19628 19513 19411 19384 19385>,
+ <19626 19500 19414 19380 19381>,
+ <19612 19487 19416 19378 19377>,
+ <19588 19470 19410 19374 19373>,
+ <19574 19459 19397 19367 19365>,
+ <19565 19461 19392 19363 19360>,
+ <19561 19467 19401 19368 19361>,
+ <19566 19471 19412 19379 19365>,
+ <19578 19473 19410 19379 19365>,
+ <19586 19474 19398 19360 19348>,
+ <19588 19474 19390 19344 19331>,
+ <19589 19473 19388 19345 19356>,
+ <19589 19472 19386 19348 19416>,
+ <19588 19472 19387 19356 19436>,
+ <19586 19472 19392 19383 19430>,
+ <19582 19471 19397 19404 19420>,
+ <19576 19470 19405 19404 19409>,
+ <19571 19470 19414 19401 19397>,
+ <19566 19469 19415 19397 19387>,
+ <19561 19469 19414 19390 19378>,
+ <19554 19467 19412 19381 19371>,
+ <19547 19464 19406 19372 19362>,
+ <19541 19460 19399 19364 19355>,
+ <19538 19457 19395 19362 19352>,
+ <19535 19453 19393 19362 19351>,
+ <19532 19449 19391 19362 19350>,
+ <19527 19446 19386 19360 19353>,
+ <19500 19442 19382 19358 19358>,
+ <19402 19437 19381 19364 19365>,
+ <19285 19420 19372 19362 19363>,
+ <19259 19411 19365 19346 19348>,
+ <19259 19405 19365 19343 19344>,
+ <19258 19392 19359 19336 19333>,
+ <19258 19386 19348 19330 19329>,
+ <19258 19362 19343 19326 19315>,
+ <19259 19382 19345 19344 19339>,
+ <19259 19370 19364 19364 19361>,
+ <19261 19345 19369 19365 19360>,
+ <19265 19341 19349 19357 19357>,
+ <19265 19341 19349 19357 19357>,
+ <19265 19341 19349 19357 19357>;
+ };
+
+ qcom,pc-temp-z4-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <15857 15325 15050 14901 14870>,
+ <15989 15423 15055 14949 14909>,
+ <15829 15360 15048 14926 14896>,
+ <15639 15210 15015 14897 14877>,
+ <15485 15092 14947 14863 14852>,
+ <15352 15010 14889 14828 14823>,
+ <15249 14943 14849 14799 14798>,
+ <15167 14891 14815 14774 14774>,
+ <15104 14848 14785 14754 14756>,
+ <15055 14817 14759 14739 14744>,
+ <15012 14796 14744 14728 14736>,
+ <14958 14777 14737 14722 14730>,
+ <14889 14743 14732 14718 14725>,
+ <14841 14691 14724 14714 14720>,
+ <14833 14666 14714 14708 14715>,
+ <14838 14699 14709 14705 14710>,
+ <14832 14751 14710 14703 14706>,
+ <14812 14757 14711 14701 14703>,
+ <14789 14727 14704 14696 14698>,
+ <14772 14703 14685 14683 14688>,
+ <14754 14705 14677 14673 14680>,
+ <14742 14713 14722 14708 14711>,
+ <14741 14732 14793 14792 14797>,
+ <14743 14811 14833 14835 14841>,
+ <14748 14884 14861 14850 14849>,
+ <14774 14885 14871 14857 14853>,
+ <14802 14869 14861 14849 14820>,
+ <14809 14852 14842 14828 14740>,
+ <14813 14835 14825 14801 14707>,
+ <14815 14816 14807 14759 14703>,
+ <14809 14800 14788 14725 14700>,
+ <14797 14785 14768 14712 14696>,
+ <14785 14772 14750 14703 14692>,
+ <14774 14760 14740 14700 14688>,
+ <14763 14750 14734 14699 14685>,
+ <14752 14741 14730 14698 14683>,
+ <14742 14731 14727 14697 14683>,
+ <14733 14726 14725 14696 14682>,
+ <14725 14727 14726 14698 14685>,
+ <14719 14727 14730 14710 14703>,
+ <14718 14727 14733 14719 14717>,
+ <14719 14722 14726 14714 14710>,
+ <14740 14715 14717 14707 14700>,
+ <14829 14708 14714 14705 14705>,
+ <14884 14683 14695 14693 14694>,
+ <14893 14672 14675 14678 14673>,
+ <14889 14666 14668 14673 14670>,
+ <14880 14664 14657 14661 14662>,
+ <14873 14659 14649 14644 14640>,
+ <14867 14680 14644 14633 14635>,
+ <14870 14667 14662 14655 14666>,
+ <14893 14697 14659 14657 14670>,
+ <14904 14732 14657 14662 14679>,
+ <14919 14744 14681 14673 14685>,
+ <14919 14744 14681 14673 14685>,
+ <14919 14744 14681 14673 14685>;
+ };
+
+ qcom,pc-temp-z5-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <12719 12607 13139 13972 14503>,
+ <13511 14576 15152 15894 15713>,
+ <14310 15773 16609 17425 17678>,
+ <14907 16652 17361 18530 19028>,
+ <15225 17538 17813 19343 19864>,
+ <15510 18475 18335 20137 20647>,
+ <15924 19419 19053 21112 21893>,
+ <16420 20326 19934 22160 23585>,
+ <16837 21205 20999 23131 24607>,
+ <17133 22209 22293 24033 24905>,
+ <17443 23342 23446 24938 25139>,
+ <18018 24772 24367 26040 25576>,
+ <19153 27408 24990 27170 26366>,
+ <20590 32133 24981 27303 27318>,
+ <22325 34811 24886 25792 28431>,
+ <24361 33005 25334 24499 29586>,
+ <25238 29603 26351 24570 30758>,
+ <24126 27959 27203 25139 32157>,
+ <22591 27229 27852 25820 33360>,
+ <22278 26912 29675 27505 34315>,
+ <23001 32282 32788 30117 35107>,
+ <24474 43306 40752 34280 35601>,
+ <29828 47301 48491 38950 35514>,
+ <39947 47289 46086 38714 33923>,
+ <46812 46996 34270 28326 25155>,
+ <50265 44986 26304 19201 17432>,
+ <52306 40162 23688 17777 21801>,
+ <52186 36899 22203 17134 32820>,
+ <50928 35287 22150 17486 36845>,
+ <49414 34278 22675 21492 36574>,
+ <47382 34242 23516 26105 35828>,
+ <44704 34722 26089 29040 34271>,
+ <42579 35455 30065 31418 31806>,
+ <40980 37045 33668 32702 31104>,
+ <39583 39294 37441 33529 31717>,
+ <38169 41010 39152 33908 32221>,
+ <36756 42548 38854 33371 32000>,
+ <36201 43392 38185 32186 31362>,
+ <37741 43161 37368 31636 30644>,
+ <39748 42428 36180 31493 29707>,
+ <39929 41357 34561 31276 28726>,
+ <38616 38915 31101 28219 27657>,
+ <35116 36981 28673 24900 26942>,
+ <25434 35927 28872 28193 30650>,
+ <14423 38239 29033 28519 31130>,
+ <11781 35678 29040 22616 23835>,
+ <11695 32125 29349 21734 21488>,
+ <11625 26422 27917 20974 19411>,
+ <11607 26031 24954 22608 22482>,
+ <11604 20276 24866 24339 20631>,
+ <11694 23343 21915 27100 25005>,
+ <11661 18332 23795 25747 22814>,
+ <11563 14961 24455 23181 19574>,
+ <11452 14193 17490 18431 16639>,
+ <11452 14193 17490 18431 16639>,
+ <11452 14193 17490 18431 16639>;
+ };
+
+ qcom,pc-temp-z6-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <16003 15264 14843 14667 14630>,
+ <16023 15320 14860 14703 14658>,
+ <15926 15288 14865 14704 14661>,
+ <15806 15208 14854 14700 14660>,
+ <15701 15140 14820 14687 14653>,
+ <15605 15087 14788 14673 14643>,
+ <15527 15041 14766 14661 14634>,
+ <15463 15002 14747 14649 14625>,
+ <15408 14969 14730 14638 14617>,
+ <15363 14943 14715 14628 14608>,
+ <15324 14923 14704 14619 14600>,
+ <15280 14905 14699 14615 14594>,
+ <15226 14881 14694 14612 14590>,
+ <15183 14851 14684 14608 14586>,
+ <15163 14837 14670 14597 14581>,
+ <15150 14844 14664 14589 14576>,
+ <15137 14853 14665 14586 14572>,
+ <15120 14852 14666 14584 14568>,
+ <15105 14833 14661 14580 14563>,
+ <15097 14819 14648 14570 14555>,
+ <15091 14821 14643 14564 14548>,
+ <15088 14830 14669 14584 14563>,
+ <15092 14846 14707 14627 14603>,
+ <15103 14883 14721 14641 14619>,
+ <15117 14915 14729 14639 14615>,
+ <15134 14916 14731 14636 14609>,
+ <15148 14912 14727 14632 14608>,
+ <15153 14906 14720 14626 14607>,
+ <15157 14900 14715 14622 14606>,
+ <15159 14894 14711 14619 14601>,
+ <15156 14888 14707 14616 14595>,
+ <15151 14884 14705 14612 14588>,
+ <15147 14880 14703 14608 14581>,
+ <15144 14877 14701 14604 14574>,
+ <15140 14874 14700 14601 14569>,
+ <15137 14872 14698 14598 14565>,
+ <15134 14870 14696 14593 14561>,
+ <15132 14869 14693 14589 14557>,
+ <15135 14871 14693 14589 14557>,
+ <15141 14875 14698 14595 14564>,
+ <15147 14878 14700 14599 14570>,
+ <15156 14880 14698 14597 14569>,
+ <15161 14882 14695 14595 14568>,
+ <15165 14884 14696 14599 14574>,
+ <15153 14877 14689 14594 14570>,
+ <15148 14872 14680 14580 14554>,
+ <15146 14866 14677 14577 14550>,
+ <15145 14858 14669 14568 14541>,
+ <15144 14855 14661 14558 14530>,
+ <15147 14855 14660 14552 14521>,
+ <15160 14870 14673 14573 14548>,
+ <15181 14885 14687 14589 14565>,
+ <15201 14895 14694 14595 14572>,
+ <15231 14914 14702 14600 14577>,
+ <15231 14914 14702 14600 14577>,
+ <15231 14914 14702 14600 14577>;
+ };
+
+ qcom,pc-temp-y1-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <6236 5929 5536 5314 5108 5032>,
+ <6280 5927 5555 5311 5111 5032>,
+ <6318 5924 5569 5309 5112 5031>,
+ <6347 5921 5578 5306 5112 5029>,
+ <6367 5917 5583 5303 5110 5028>,
+ <6374 5913 5584 5300 5109 5026>,
+ <6365 5907 5577 5296 5106 5024>,
+ <6349 5902 5568 5290 5102 5021>,
+ <6345 5901 5566 5287 5099 5019>,
+ <6349 5907 5568 5284 5096 5018>,
+ <6353 5912 5569 5283 5093 5016>,
+ <6354 5916 5568 5282 5091 5015>,
+ <6354 5920 5566 5282 5090 5013>,
+ <6356 5923 5565 5282 5088 5013>,
+ <6370 5926 5566 5281 5084 5012>,
+ <6384 5929 5567 5280 5081 5012>,
+ <6387 5933 5573 5281 5083 5012>,
+ <6384 5937 5582 5285 5087 5013>,
+ <6382 5937 5586 5287 5088 5013>,
+ <6384 5937 5588 5289 5087 5014>,
+ <6386 5936 5590 5290 5086 5014>,
+ <6386 5936 5588 5291 5087 5015>,
+ <6388 5938 5585 5292 5090 5015>,
+ <6391 5940 5585 5294 5093 5016>,
+ <6379 5939 5589 5301 5095 5017>,
+ <6364 5937 5592 5307 5097 5019>,
+ <6363 5935 5589 5309 5101 5022>,
+ <6367 5933 5585 5310 5105 5024>,
+ <6367 5931 5584 5312 5109 5027>,
+ <6354 5931 5591 5315 5113 5031>,
+ <6340 5930 5597 5319 5118 5034>,
+ <6340 5928 5597 5323 5123 5038>,
+ <6344 5926 5595 5328 5127 5041>,
+ <6347 5925 5594 5333 5132 5044>,
+ <6340 5923 5597 5336 5135 5046>,
+ <6332 5922 5600 5339 5138 5048>,
+ <6328 5924 5602 5342 5142 5051>,
+ <6326 5926 5603 5348 5145 5055>,
+ <6326 5926 5603 5353 5148 5057>,
+ <6332 5921 5600 5355 5151 5059>,
+ <6339 5918 5598 5358 5154 5060>,
+ <6338 5920 5602 5361 5156 5061>,
+ <6335 5925 5607 5370 5159 5063>,
+ <6333 5929 5605 5380 5166 5068>,
+ <6331 5931 5602 5390 5176 5075>,
+ <6385 5952 5610 5396 5187 5076>,
+ <6399 5953 5634 5393 5183 5075>,
+ <6402 5952 5647 5384 5178 5074>,
+ <6400 5972 5628 5392 5173 5075>,
+ <6399 5966 5796 5395 5174 5076>,
+ <6411 5963 5638 5386 5179 5078>,
+ <6437 5983 5649 5399 5186 5084>,
+ <6436 6001 5661 5425 5201 5091>,
+ <6507 6048 5677 5436 5211 5101>,
+ <6507 6048 5677 5436 5211 5101>,
+ <6507 6048 5677 5436 5211 5101>;
+ };
+
+ qcom,pc-temp-y2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <9643 10134 10800 11406 10953 10902>,
+ <9643 10204 10871 11350 10938 10864>,
+ <9644 10263 10919 11296 10918 10827>,
+ <9714 10308 10950 11244 10895 10792>,
+ <9794 10338 10966 11195 10870 10760>,
+ <9880 10351 10971 11151 10844 10733>,
+ <9999 10342 10961 11109 10813 10710>,
+ <10107 10328 10936 11070 10783 10690>,
+ <10079 10429 10891 11042 10765 10676>,
+ <9834 11025 10778 11023 10750 10665>,
+ <9674 11472 10702 11003 10741 10657>,
+ <9675 11201 10869 10971 10740 10649>,
+ <9676 10677 11172 10939 10739 10642>,
+ <9676 10554 11249 10942 10744 10643>,
+ <9673 10734 11227 11025 10770 10660>,
+ <9670 10942 11208 11126 10806 10674>,
+ <9670 11098 11269 11199 10855 10670>,
+ <9670 11227 11390 11275 10922 10662>,
+ <9669 11168 11436 11376 11004 10683>,
+ <9669 10441 11442 11534 11129 10856>,
+ <9668 9800 11440 11638 11210 10993>,
+ <9668 9723 11431 11566 11152 10979>,
+ <9668 9697 11418 11412 11039 10948>,
+ <9667 9692 11414 11365 11009 10937>,
+ <9667 9693 11414 11390 11038 10928>,
+ <9666 9693 11412 11428 11075 10920>,
+ <9665 9690 11388 11467 11112 10931>,
+ <9665 9684 11341 11511 11156 10969>,
+ <9665 9679 11320 11553 11184 11011>,
+ <9664 9676 11322 11600 11220 11074>,
+ <9664 9674 11322 11629 11267 11127>,
+ <9663 9671 11308 11628 11338 11147>,
+ <9663 9669 11281 11622 11420 11160>,
+ <9663 9667 11246 11612 11442 11184>,
+ <9662 9666 11192 11589 11405 11236>,
+ <9662 9665 11127 11556 11353 11275>,
+ <9662 9664 11067 11521 11318 11243>,
+ <9661 9663 11000 11480 11288 11140>,
+ <9661 9662 10849 11442 11252 11069>,
+ <9661 9661 10313 11409 11198 11044>,
+ <9661 9661 9811 11376 11160 11042>,
+ <9660 9660 9719 11335 11166 11053>,
+ <9660 9660 9695 11285 11176 11026>,
+ <9660 9659 9685 11207 11083 10909>,
+ <9659 9659 9678 11089 10968 10777>,
+ <9659 9658 9675 11063 10922 10745>,
+ <9659 9658 9676 11067 10982 10759>,
+ <9659 9658 9673 11070 11030 10808>,
+ <9658 9658 9669 11105 11087 10847>,
+ <9657 9657 9668 11099 11089 10872>,
+ <9657 9657 9666 10998 11006 10726>,
+ <9657 9656 9663 10876 10870 10649>,
+ <9656 9656 9660 10786 10813 10557>,
+ <9653 9655 9658 10748 10728 10499>,
+ <9653 9655 9658 10748 10728 10499>,
+ <9653 9655 9658 10748 10728 10499>;
+ };
+
+ qcom,pc-temp-y3-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <13980 13540 13353 13294 13283 13280>,
+ <13931 13519 13354 13295 13284 13281>,
+ <13863 13507 13355 13296 13284 13282>,
+ <13793 13501 13356 13298 13285 13283>,
+ <13735 13500 13358 13299 13286 13284>,
+ <13702 13501 13359 13300 13286 13284>,
+ <13692 13512 13361 13301 13286 13285>,
+ <13685 13530 13363 13301 13287 13286>,
+ <13657 13520 13366 13302 13287 13286>,
+ <13564 13435 13373 13303 13288 13286>,
+ <13500 13373 13377 13304 13288 13287>,
+ <13511 13379 13372 13306 13289 13288>,
+ <13533 13390 13361 13308 13292 13290>,
+ <13534 13393 13354 13309 13293 13292>,
+ <13504 13393 13345 13309 13294 13292>,
+ <13481 13392 13339 13309 13295 13293>,
+ <13487 13387 13338 13306 13297 13293>,
+ <13500 13376 13338 13302 13298 13293>,
+ <13504 13371 13337 13301 13298 13293>,
+ <13501 13372 13331 13302 13296 13293>,
+ <13498 13373 13325 13302 13293 13293>,
+ <13498 13366 13320 13300 13288 13289>,
+ <13500 13349 13316 13293 13284 13283>,
+ <13503 13336 13312 13290 13282 13280>,
+ <13518 13326 13309 13288 13282 13280>,
+ <13537 13321 13306 13288 13281 13280>,
+ <13554 13328 13304 13287 13280 13279>,
+ <13573 13347 13302 13287 13279 13279>,
+ <13593 13366 13300 13287 13279 13279>,
+ <13618 13384 13299 13286 13278 13279>,
+ <13644 13404 13298 13286 13278 13280>,
+ <13669 13426 13299 13285 13279 13279>,
+ <13696 13452 13303 13285 13281 13279>,
+ <13725 13481 13306 13285 13281 13279>,
+ <13754 13511 13308 13286 13281 13280>,
+ <13784 13543 13310 13287 13281 13282>,
+ <13813 13579 13312 13287 13281 13281>,
+ <13843 13619 13315 13288 13281 13280>,
+ <13873 13661 13321 13289 13281 13280>,
+ <13903 13704 13335 13290 13281 13282>,
+ <13935 13747 13349 13290 13282 13283>,
+ <13973 13787 13353 13292 13284 13284>,
+ <14018 13826 13353 13294 13285 13283>,
+ <14068 13868 13369 13294 13283 13282>,
+ <14128 13917 13402 13295 13283 13283>,
+ <14165 13959 13429 13301 13290 13289>,
+ <14183 13975 13428 13301 13294 13291>,
+ <14229 14009 13452 13306 13296 13293>,
+ <14297 14063 13484 13313 13297 13294>,
+ <14380 14117 13522 13318 13297 13293>,
+ <14459 14161 13563 13314 13293 13289>,
+ <14559 14232 13619 13316 13293 13291>,
+ <14713 14351 13751 13324 13300 13296>,
+ <15199 14492 13933 13336 13310 13308>,
+ <15199 14492 13933 13336 13310 13308>,
+ <15199 14492 13933 13336 13310 13308>;
+ };
+
+ qcom,pc-temp-y4-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <17114 16865 16657 16527 16479 16481>,
+ <17132 16907 16695 16526 16477 16479>,
+ <17148 16953 16730 16525 16475 16477>,
+ <17159 16995 16759 16524 16473 16475>,
+ <17164 17027 16779 16523 16472 16473>,
+ <17162 17040 16786 16522 16471 16472>,
+ <17131 17032 16780 16521 16471 16471>,
+ <17089 17019 16767 16519 16471 16470>,
+ <17119 17030 16759 16519 16472 16469>,
+ <17358 17122 16752 16522 16475 16470>,
+ <17552 17241 16748 16525 16478 16471>,
+ <17596 17381 16790 16528 16480 16472>,
+ <17622 17526 16867 16530 16482 16474>,
+ <17572 17508 16890 16535 16486 16477>,
+ <17185 17131 16876 16546 16493 16481>,
+ <16867 16836 16859 16561 16502 16486>,
+ <16838 16844 16840 16582 16510 16491>,
+ <16827 16878 16812 16610 16520 16500>,
+ <16804 16883 16790 16637 16537 16514>,
+ <16752 16836 16768 16667 16576 16546>,
+ <16702 16769 16741 16684 16603 16568>,
+ <16674 16697 16692 16641 16573 16548>,
+ <16655 16623 16630 16545 16510 16502>,
+ <16650 16600 16594 16503 16480 16478>,
+ <16649 16603 16576 16490 16468 16467>,
+ <16649 16607 16560 16485 16463 16461>,
+ <16652 16605 16534 16486 16465 16462>,
+ <16658 16599 16503 16490 16470 16465>,
+ <16663 16598 16491 16493 16476 16470>,
+ <16666 16603 16490 16496 16486 16477>,
+ <16670 16610 16492 16498 16496 16486>,
+ <16674 16617 16499 16498 16506 16499>,
+ <16680 16625 16513 16497 16515 16514>,
+ <16684 16634 16529 16497 16517 16519>,
+ <16689 16647 16548 16501 16512 16518>,
+ <16692 16661 16568 16505 16504 16516>,
+ <16694 16668 16589 16506 16493 16505>,
+ <16695 16672 16609 16507 16479 16482>,
+ <16696 16673 16624 16508 16475 16474>,
+ <16694 16674 16634 16512 16481 16482>,
+ <16691 16675 16642 16518 16488 16492>,
+ <16695 16667 16647 16527 16490 16495>,
+ <16708 16651 16650 16536 16488 16490>,
+ <16730 16641 16640 16541 16478 16470>,
+ <16763 16639 16633 16548 16474 16462>,
+ <16768 16647 16637 16553 16493 16499>,
+ <16765 16658 16641 16552 16513 16530>,
+ <16779 16680 16660 16574 16547 16564>,
+ <16808 16720 16694 16609 16581 16597>,
+ <16826 16751 16730 16645 16596 16590>,
+ <16823 16757 16738 16608 16514 16499>,
+ <16805 16746 16716 16596 16501 16490>,
+ <16802 16746 16725 16617 16512 16490>,
+ <16939 16771 16752 16659 16544 16510>,
+ <16939 16771 16752 16659 16544 16510>,
+ <16939 16771 16752 16659 16544 16510>;
+ };
+
+ qcom,pc-temp-y5-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <15182 15052 15375 19227 22572 18105>,
+ <13708 14689 15789 19466 22024 19966>,
+ <13231 14679 16271 19522 21392 21158>,
+ <13493 14958 16748 19457 20757 21840>,
+ <14238 15466 17151 19332 20195 22171>,
+ <15210 16141 17405 19208 19786 22311>,
+ <17107 17754 17505 18952 19233 21984>,
+ <19219 19705 17579 18511 18458 21297>,
+ <18966 19421 17924 18128 17757 20763>,
+ <15486 15128 19378 17717 16850 19517>,
+ <13162 11987 20429 17263 16324 18632>,
+ <15858 14116 18321 16618 16516 18868>,
+ <20727 18065 14482 15952 16886 19289>,
+ <21402 19154 13796 15812 16935 19289>,
+ <17261 19108 16132 15909 16586 18510>,
+ <14014 19097 18519 15985 16186 17533>,
+ <14973 20026 19516 15501 15844 16590>,
+ <17090 21707 20261 14577 15525 15709>,
+ <17685 22179 21083 14599 15435 15420>,
+ <17039 21960 22121 17006 15446 15318>,
+ <16088 21569 23018 19703 15494 15287>,
+ <14906 20432 23553 21321 17083 16683>,
+ <13636 18012 23948 22584 20030 19522>,
+ <13294 15823 24288 22855 20936 20573>,
+ <13302 13765 24643 22502 20899 20735>,
+ <13308 12565 24903 22199 20716 20786>,
+ <13257 12691 24858 22273 19688 19741>,
+ <13135 13142 24377 22452 17752 17656>,
+ <13133 13452 23427 22514 16990 16867>,
+ <13420 13603 20603 22450 16863 16673>,
+ <13699 13753 18473 22401 16809 16566>,
+ <13859 14010 18625 22531 17576 16626>,
+ <14074 14358 19205 22736 19560 16896>,
+ <14313 14626 19421 22727 20866 17544>,
+ <14583 14783 19271 22517 21589 20104>,
+ <14782 14934 19116 22195 21954 22320>,
+ <14807 15226 19202 21743 21910 22288>,
+ <14788 15883 19483 21060 21673 21780>,
+ <14741 16344 19562 20256 21266 21465>,
+ <14534 16390 18925 19164 20251 21318>,
+ <14231 16305 17898 18180 19453 21247>,
+ <13988 15927 16637 17772 20455 22411>,
+ <13807 15300 15479 17543 21839 23962>,
+ <13645 14658 15053 17161 19689 21462>,
+ <13611 14122 14826 16887 16934 17943>,
+ <13939 14195 15017 17301 17268 16287>,
+ <14219 14158 14908 16951 17388 15514>,
+ <14305 14044 14960 16882 16646 15123>,
+ <14370 14303 14700 17310 16404 15040>,
+ <15046 15056 15342 17576 16355 15025>,
+ <15049 15260 15749 17696 17401 16121>,
+ <14487 14687 15126 18044 17467 16407>,
+ <14220 14363 15053 18960 18786 16829>,
+ <13035 14274 15098 20621 22470 25019>,
+ <13035 14274 15098 20621 22470 25019>,
+ <13035 14274 15098 20621 22470 25019>;
+ };
+
+ qcom,pc-temp-y6-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <6292 5726 5316 5085 5021 5009>,
+ <6257 5722 5318 5084 5021 5009>,
+ <6223 5717 5319 5083 5020 5009>,
+ <6191 5710 5319 5082 5020 5010>,
+ <6162 5705 5318 5080 5020 5010>,
+ <6136 5701 5317 5079 5020 5010>,
+ <6110 5699 5312 5078 5020 5010>,
+ <6088 5697 5304 5077 5020 5010>,
+ <6074 5691 5300 5076 5020 5010>,
+ <6062 5667 5298 5077 5021 5010>,
+ <6056 5651 5297 5077 5022 5011>,
+ <6068 5684 5302 5078 5023 5012>,
+ <6089 5743 5311 5080 5025 5014>,
+ <6077 5745 5312 5081 5027 5016>,
+ <5954 5648 5303 5084 5029 5017>,
+ <5857 5572 5292 5088 5032 5019>,
+ <5857 5576 5287 5092 5036 5021>,
+ <5862 5587 5282 5099 5040 5023>,
+ <5862 5589 5275 5106 5045 5027>,
+ <5849 5572 5266 5114 5054 5036>,
+ <5836 5551 5255 5119 5059 5042>,
+ <5834 5535 5238 5105 5048 5034>,
+ <5834 5521 5219 5073 5026 5015>,
+ <5835 5517 5209 5060 5016 5006>,
+ <5846 5522 5206 5057 5012 5003>,
+ <5863 5532 5203 5055 5011 5001>,
+ <5879 5547 5198 5056 5011 5002>,
+ <5896 5568 5192 5059 5012 5002>,
+ <5915 5590 5191 5061 5014 5004>,
+ <5935 5612 5196 5063 5017 5006>,
+ <5956 5637 5204 5064 5020 5009>,
+ <5978 5664 5214 5066 5025 5013>,
+ <6000 5694 5230 5067 5029 5017>,
+ <6023 5726 5246 5069 5030 5020>,
+ <6047 5759 5266 5072 5029 5020>,
+ <6071 5793 5287 5076 5027 5021>,
+ <6096 5828 5311 5079 5024 5018>,
+ <6120 5864 5338 5082 5021 5011>,
+ <6145 5901 5365 5086 5020 5009>,
+ <6168 5939 5393 5091 5023 5012>,
+ <6194 5975 5421 5097 5026 5017>,
+ <6227 6007 5451 5104 5028 5018>,
+ <6269 6038 5483 5114 5029 5016>,
+ <6318 6071 5521 5124 5026 5011>,
+ <6380 6116 5568 5138 5027 5010>,
+ <6424 6154 5602 5150 5039 5026>,
+ <6442 6171 5600 5147 5047 5036>,
+ <6483 6206 5637 5160 5057 5047>,
+ <6548 6263 5682 5179 5068 5057>,
+ <6619 6316 5734 5192 5072 5055>,
+ <6689 6358 5779 5180 5046 5026>,
+ <6778 6417 5836 5192 5044 5026>,
+ <6911 6520 5963 5229 5055 5031>,
+ <7378 6654 6136 5274 5074 5047>,
+ <7378 6654 6136 5274 5074 5047>,
+ <7378 6654 6136 5274 5074 5047>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-n10-veken-4360mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-n10-veken-4360mah.dtsi
new file mode 100644
index 0000000..44f2bfd
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qg-batterydata-n10-veken-4360mah.dtsi
@@ -0,0 +1,1050 @@
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+qcom,ottawa_veken_4500mAh {
+ /* 4251176_TCL_T1Pro_Veken_4500mAH_PM6150_averaged_MasterSlave_Nov29th2019 */
+ qcom,default-battery-type;
+ qcom,max-voltage-uv = <4400000>;
+ qcom,fg-cc-cv-threshold-uv = <4390000>;
+ qcom,fastchg-current-ma = <2000>;
+ qcom,batt-id-kohm = <82>;
+ qcom,battery-beta = <3435>;
+ qcom,battery-therm-kohm = <10>;
+ qcom,battery-type = "n10-veken_v4";
+ qcom,qg-batt-profile-ver = <100>;
+
+ qcom,jeita-fcc-ranges = <0 130 1500000
+ 131 430 2000000
+ 431 550 1500000
+ 551 600 0>;
+ qcom,jeita-fv-ranges = <0 130 4400000
+ 131 430 4400000
+ 431 600 4100000>;
+ qcom,step-chg-ranges = <2800000 4250000 2000000
+ 4250001 4400000 1800000>;
+ qcom,ocv-based-step-chg;
+
+ /* COOL = 10 DegC, WARM = 45 DegC */
+ qcom,jeita-soft-thresholds = <0x2aee 0xfb3>;
+ /* COLD = 0 DegC, HOT = 55 DegC */
+ qcom,jeita-hard-thresholds = <0x3733 0xbc2>;
+ /* COOL hys = 13 DegC, WARM hys = 42 DegC */
+ qcom,jeita-soft-hys-thresholds = <0x279a 0x1124>;
+
+ qcom,jeita-soft-fcc-ua = <2000000 2000000>;
+ qcom,jeita-soft-fv-uv = <4100000 4100000>;
+
+ qcom,fcc1-temp-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-data = <4278 4386 4491 4535 4546>;
+ };
+
+ qcom,fcc2-temp-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-data = <4480 4483 4504 4485 4502 4505>;
+ };
+
+ qcom,pc-temp-v1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <43393 43624 43782 43841 43853>,
+ <43115 43319 43523 43569 43573>,
+ <42856 43056 43264 43311 43316>,
+ <42614 42817 43011 43062 43070>,
+ <42386 42585 42761 42820 42829>,
+ <42167 42356 42515 42583 42593>,
+ <41955 42131 42280 42349 42360>,
+ <41749 41914 42052 42119 42128>,
+ <41553 41702 41827 41891 41899>,
+ <41373 41500 41603 41666 41673>,
+ <41195 41318 41389 41443 41450>,
+ <40987 41139 41199 41223 41231>,
+ <40741 40927 41016 41004 41014>,
+ <40489 40666 40798 40795 40805>,
+ <40246 40409 40538 40592 40605>,
+ <40011 40184 40302 40398 40412>,
+ <39831 39979 40118 40213 40226>,
+ <39708 39823 39958 40037 40048>,
+ <39605 39713 39812 39869 39877>,
+ <39498 39610 39681 39719 39723>,
+ <39390 39489 39540 39563 39566>,
+ <39285 39359 39367 39370 39377>,
+ <39179 39217 39173 39148 39156>,
+ <39074 39045 38970 38950 38958>,
+ <38973 38866 38749 38777 38788>,
+ <38877 38706 38591 38633 38644>,
+ <38784 38553 38508 38529 38536>,
+ <38693 38444 38446 38446 38449>,
+ <38604 38377 38385 38367 38367>,
+ <38525 38327 38325 38290 38284>,
+ <38458 38291 38270 38220 38208>,
+ <38397 38266 38218 38156 38139>,
+ <38345 38244 38170 38099 38076>,
+ <38301 38221 38129 38047 38018>,
+ <38262 38199 38094 38003 37968>,
+ <38228 38173 38059 37960 37919>,
+ <38196 38146 38027 37916 37868>,
+ <38159 38110 37991 37873 37815>,
+ <38109 38058 37939 37813 37748>,
+ <38046 37982 37856 37731 37659>,
+ <37960 37889 37758 37633 37558>,
+ <37836 37768 37649 37528 37450>,
+ <37707 37627 37519 37404 37327>,
+ <37572 37459 37353 37243 37169>,
+ <37410 37302 37200 37094 37028>,
+ <37287 37195 37094 37002 36941>,
+ <37245 37163 37068 36971 36911>,
+ <37209 37140 37045 36950 36893>,
+ <37177 37123 37031 36935 36873>,
+ <37136 37092 36999 36900 36833>,
+ <37004 36954 36834 36711 36613>,
+ <36611 36535 36417 36291 36190>,
+ <36050 35982 35856 35726 35629>,
+ <35301 35225 35096 34958 34860>,
+ <34109 34044 33919 33769 33670>,
+ <30000 30000 30000 30000 30000>;
+ };
+
+ qcom,pc-temp-v2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <43865 43830 43815 43745 43725 43715>,
+ <43366 43406 43452 43415 43417 43411>,
+ <42943 43029 43124 43112 43130 43127>,
+ <42618 42705 42837 42840 42867 42866>,
+ <42366 42422 42588 42599 42626 42627>,
+ <42130 42178 42350 42366 42392 42393>,
+ <41874 41982 42111 42132 42157 42160>,
+ <41630 41806 41877 41902 41926 41928>,
+ <41447 41586 41646 41676 41699 41700>,
+ <41308 41299 41412 41453 41474 41475>,
+ <41178 41101 41201 41237 41254 41254>,
+ <41052 41043 41039 41040 41040 41037>,
+ <40911 41005 40886 40849 40831 40825>,
+ <40649 40846 40677 40631 40624 40620>,
+ <40090 40280 40391 40375 40416 40420>,
+ <39611 39788 40125 40143 40219 40229>,
+ <39405 39621 39924 39970 40042 40047>,
+ <39257 39507 39745 39822 39876 39873>,
+ <39089 39358 39561 39678 39714 39708>,
+ <38903 39169 39380 39545 39563 39557>,
+ <38730 38979 39195 39393 39396 39391>,
+ <38579 38798 38995 39176 39180 39182>,
+ <38447 38626 38796 38926 38950 38959>,
+ <38349 38468 38626 38730 38761 38772>,
+ <38275 38314 38476 38572 38600 38605>,
+ <38211 38198 38340 38439 38463 38465>,
+ <38151 38133 38202 38329 38352 38352>,
+ <38094 38086 38080 38233 38256 38255>,
+ <38039 38042 38011 38144 38169 38167>,
+ <37988 38000 37969 38061 38090 38087>,
+ <37937 37960 37932 37987 38020 38016>,
+ <37884 37921 37895 37918 37956 37952>,
+ <37830 37883 37860 37858 37897 37893>,
+ <37772 37843 37826 37808 37834 37828>,
+ <37713 37799 37795 37770 37770 37760>,
+ <37652 37752 37759 37731 37701 37683>,
+ <37590 37700 37715 37684 37624 37586>,
+ <37529 37643 37663 37631 37542 37483>,
+ <37465 37579 37600 37568 37464 37396>,
+ <37401 37507 37525 37495 37390 37321>,
+ <37337 37425 37440 37411 37309 37243>,
+ <37277 37320 37342 37312 37218 37157>,
+ <37216 37202 37227 37194 37113 37057>,
+ <37149 37098 37086 37056 36981 36919>,
+ <37070 37011 36954 36924 36859 36807>,
+ <36967 36941 36866 36853 36802 36754>,
+ <36910 36903 36839 36838 36793 36745>,
+ <36839 36867 36816 36823 36778 36733>,
+ <36749 36817 36781 36799 36756 36709>,
+ <36615 36726 36712 36749 36697 36641>,
+ <36387 36528 36527 36566 36455 36372>,
+ <36028 36131 36110 36123 35975 35888>,
+ <35480 35537 35492 35520 35347 35250>,
+ <34654 34677 34618 34705 34497 34385>,
+ <33273 33360 33302 33477 33279 33164>,
+ <29440 28853 28714 28637 28563 28582>;
+ };
+
+ qcom,pc-temp-z1-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <13744 12803 12055 11640 11489>,
+ <13744 12821 12047 11640 11468>,
+ <13761 12814 12043 11637 11471>,
+ <13769 12790 12038 11633 11472>,
+ <13743 12773 12030 11626 11468>,
+ <13704 12768 12021 11618 11462>,
+ <13692 12765 12012 11611 11458>,
+ <13699 12760 12003 11603 11455>,
+ <13708 12749 11998 11599 11453>,
+ <13711 12737 11995 11597 11452>,
+ <13698 12730 11994 11596 11451>,
+ <13661 12723 11996 11597 11451>,
+ <13593 12707 12000 11600 11451>,
+ <13544 12665 11996 11601 11451>,
+ <13526 12633 11975 11596 11451>,
+ <13509 12629 11962 11590 11451>,
+ <13492 12628 11964 11590 11451>,
+ <13466 12630 11967 11592 11452>,
+ <13443 12642 11971 11594 11453>,
+ <13433 12658 11982 11597 11454>,
+ <13427 12674 11991 11599 11455>,
+ <13422 12692 11996 11601 11455>,
+ <13415 12703 12000 11602 11456>,
+ <13410 12708 12003 11603 11457>,
+ <13409 12713 12005 11604 11458>,
+ <13413 12720 12007 11606 11461>,
+ <13420 12737 12011 11609 11463>,
+ <13433 12745 12018 11614 11467>,
+ <13453 12739 12022 11618 11470>,
+ <13463 12729 12026 11623 11474>,
+ <13462 12729 12030 11627 11478>,
+ <13459 12740 12033 11632 11482>,
+ <13466 12752 12036 11636 11485>,
+ <13497 12759 12044 11641 11488>,
+ <13523 12766 12061 11645 11493>,
+ <13522 12775 12071 11650 11497>,
+ <13515 12785 12071 11653 11500>,
+ <13519 12798 12070 11657 11503>,
+ <13538 12818 12071 11661 11505>,
+ <13565 12846 12080 11668 11509>,
+ <13597 12859 12090 11675 11512>,
+ <13638 12857 12099 11680 11516>,
+ <13641 12860 12108 11684 11520>,
+ <13602 12883 12120 11687 11523>,
+ <13660 12912 12123 11694 11527>,
+ <13638 12883 12138 11698 11529>,
+ <13667 12891 12129 11698 11529>,
+ <13644 12899 12125 11699 11531>,
+ <13611 12903 12136 11702 11532>,
+ <13615 12895 12140 11710 11538>,
+ <13631 12919 12162 11720 11545>,
+ <13658 12930 12160 11731 11555>,
+ <13663 12939 12176 11741 11567>,
+ <13671 12970 12219 11763 11583>,
+ <13671 12970 12219 11763 11583>,
+ <13671 12970 12219 11763 11583>;
+ };
+
+ qcom,pc-temp-z2-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <9963 11124 10631 10272 10157>,
+ <10076 10365 10667 10358 10255>,
+ <10162 10264 11033 10412 10354>,
+ <10193 10242 11098 10443 10408>,
+ <10200 10229 10708 10419 10392>,
+ <10206 10214 10376 10389 10357>,
+ <10209 10201 10438 10484 10330>,
+ <10206 10191 10596 10747 10307>,
+ <10201 10182 10615 10838 10296>,
+ <10197 10175 10426 11039 10292>,
+ <10193 10173 10275 11347 10288>,
+ <10185 10171 10376 11221 10287>,
+ <10158 10163 10582 10638 10292>,
+ <10125 10147 10632 10391 10291>,
+ <10099 10138 10510 10992 10250>,
+ <10077 10142 10402 11670 10197>,
+ <10068 10157 10394 11470 10196>,
+ <10066 10176 10390 10685 10225>,
+ <10064 10209 10397 10352 10254>,
+ <10065 10247 10428 10363 10271>,
+ <10071 10282 10467 10384 10293>,
+ <10079 10318 10515 10450 10376>,
+ <10086 10349 10559 10578 10561>,
+ <10094 10380 10565 10620 10638>,
+ <10102 10402 10548 10551 10540>,
+ <10112 10402 10534 10481 10418>,
+ <10125 10398 10522 10465 10389>,
+ <10138 10396 10508 10455 10376>,
+ <10153 10409 10511 10456 10379>,
+ <10170 10432 10527 10485 10419>,
+ <10190 10444 10540 10511 10456>,
+ <10212 10453 10544 10503 10449>,
+ <10234 10460 10548 10484 10416>,
+ <10255 10468 10557 10478 10382>,
+ <10276 10477 10572 10481 10336>,
+ <10296 10489 10586 10486 10304>,
+ <10315 10503 10594 10503 10323>,
+ <10340 10520 10602 10535 10380>,
+ <10375 10541 10616 10566 10438>,
+ <10416 10566 10640 10608 10516>,
+ <10456 10588 10659 10635 10571>,
+ <10498 10603 10672 10639 10580>,
+ <10397 10622 10679 10641 10584>,
+ <9842 10648 10679 10638 10576>,
+ <10019 10872 10733 10646 10533>,
+ <10644 10958 10788 10562 10485>,
+ <10246 11003 10795 10571 10468>,
+ <10415 11128 10778 10567 10484>,
+ <11495 11535 10858 10596 10493>,
+ <12809 11438 10902 10673 10573>,
+ <12857 11091 10914 10644 10472>,
+ <10270 11041 10831 10523 10314>,
+ <10331 11022 10759 10460 10267>,
+ <10140 10655 10778 10420 10209>,
+ <10140 10655 10778 10420 10209>,
+ <10140 10655 10778 10420 10209>;
+ };
+
+ qcom,pc-temp-z3-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <19640 19597 19383 19354 19377>,
+ <19743 19655 19445 19401 19373>,
+ <19781 19682 19476 19427 19397>,
+ <19786 19702 19493 19439 19414>,
+ <19748 19708 19509 19443 19424>,
+ <19703 19701 19520 19447 19430>,
+ <19688 19690 19527 19453 19431>,
+ <19681 19682 19532 19465 19430>,
+ <19678 19674 19530 19468 19427>,
+ <19681 19667 19515 19468 19421>,
+ <19688 19658 19502 19467 19412>,
+ <19701 19649 19499 19455 19407>,
+ <19729 19644 19499 19429 19404>,
+ <19755 19641 19497 19418 19400>,
+ <19762 19637 19490 19429 19393>,
+ <19765 19628 19480 19441 19385>,
+ <19764 19613 19471 19433 19380>,
+ <19748 19595 19461 19408 19377>,
+ <19722 19568 19455 19392 19374>,
+ <19703 19547 19450 19385 19369>,
+ <19686 19544 19448 19381 19365>,
+ <19678 19545 19452 19386 19368>,
+ <19681 19548 19459 19400 19378>,
+ <19693 19561 19462 19404 19383>,
+ <19703 19575 19460 19396 19375>,
+ <19711 19578 19458 19386 19364>,
+ <19718 19578 19454 19380 19360>,
+ <19722 19578 19449 19377 19358>,
+ <19724 19576 19449 19376 19358>,
+ <19723 19574 19451 19387 19372>,
+ <19717 19571 19454 19398 19388>,
+ <19708 19566 19459 19404 19393>,
+ <19699 19560 19464 19409 19395>,
+ <19689 19556 19464 19409 19393>,
+ <19678 19551 19461 19405 19385>,
+ <19666 19547 19457 19398 19375>,
+ <19651 19544 19453 19393 19369>,
+ <19636 19540 19449 19387 19364>,
+ <19617 19535 19445 19385 19363>,
+ <19599 19531 19443 19384 19363>,
+ <19593 19525 19440 19383 19364>,
+ <19591 19518 19435 19380 19365>,
+ <19537 19511 19430 19377 19366>,
+ <19280 19505 19427 19378 19367>,
+ <19263 19471 19414 19376 19364>,
+ <19261 19451 19404 19360 19352>,
+ <19261 19440 19398 19359 19348>,
+ <19261 19409 19398 19358 19339>,
+ <19259 19302 19375 19349 19337>,
+ <19257 19260 19374 19342 19328>,
+ <19257 19267 19373 19348 19349>,
+ <19261 19340 19388 19357 19368>,
+ <19261 19290 19393 19364 19361>,
+ <19261 19285 19367 19360 19358>,
+ <19261 19285 19367 19360 19358>,
+ <19261 19285 19367 19360 19358>;
+ };
+
+ qcom,pc-temp-z4-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <16885 15792 15257 14963 14893>,
+ <17121 15968 15275 15033 14947>,
+ <16859 15843 15179 14975 14911>,
+ <16580 15569 15088 14917 14871>,
+ <16327 15356 15005 14876 14837>,
+ <16104 15231 14935 14837 14806>,
+ <15926 15132 14869 14794 14781>,
+ <15774 15054 14809 14749 14759>,
+ <15644 14991 14783 14722 14743>,
+ <15532 14938 14772 14693 14733>,
+ <15432 14891 14764 14667 14725>,
+ <15342 14851 14741 14672 14718>,
+ <15257 14821 14710 14698 14711>,
+ <15189 14797 14703 14709 14706>,
+ <15143 14782 14717 14678 14702>,
+ <15108 14777 14727 14644 14700>,
+ <15072 14774 14721 14649 14695>,
+ <15030 14770 14711 14672 14688>,
+ <14991 14759 14701 14682 14682>,
+ <14964 14746 14689 14679 14676>,
+ <14946 14734 14683 14676 14671>,
+ <14926 14723 14694 14687 14681>,
+ <14898 14719 14719 14724 14719>,
+ <14861 14734 14756 14760 14756>,
+ <14831 14759 14822 14800 14793>,
+ <14807 14787 14855 14826 14818>,
+ <14788 14828 14845 14823 14816>,
+ <14780 14848 14825 14811 14803>,
+ <14775 14843 14807 14794 14786>,
+ <14773 14831 14788 14769 14757>,
+ <14772 14818 14770 14744 14727>,
+ <14771 14800 14755 14726 14709>,
+ <14769 14782 14742 14710 14694>,
+ <14764 14767 14735 14704 14691>,
+ <14758 14753 14730 14702 14691>,
+ <14753 14741 14727 14701 14692>,
+ <14748 14730 14724 14701 14693>,
+ <14745 14722 14721 14703 14695>,
+ <14742 14718 14721 14706 14698>,
+ <14740 14714 14723 14713 14707>,
+ <14736 14713 14725 14717 14714>,
+ <14725 14711 14716 14711 14707>,
+ <14773 14710 14705 14701 14697>,
+ <15026 14703 14700 14699 14698>,
+ <14954 14685 14684 14686 14689>,
+ <14937 14677 14667 14674 14674>,
+ <14930 14677 14661 14666 14670>,
+ <14924 14701 14651 14653 14662>,
+ <14918 14812 14660 14643 14641>,
+ <14913 14851 14655 14640 14636>,
+ <14913 14845 14664 14655 14649>,
+ <14934 14788 14665 14666 14653>,
+ <14956 14856 14663 14663 14662>,
+ <14972 14873 14696 14671 14669>,
+ <14972 14873 14696 14671 14669>,
+ <14972 14873 14696 14671 14669>;
+ };
+
+ qcom,pc-temp-z5-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <12188 12867 12846 13605 14521>,
+ <12728 13913 13920 15248 14950>,
+ <13269 14609 14682 16708 16769>,
+ <13643 15119 15472 17770 18403>,
+ <13844 15554 16628 18504 19620>,
+ <14018 15926 17971 19165 20631>,
+ <14216 16289 19500 20735 21454>,
+ <14448 16756 21032 23823 22260>,
+ <14671 17326 21646 25486 22772>,
+ <14847 17987 21691 28590 22877>,
+ <15029 18774 21847 32652 22937>,
+ <15355 19764 23733 31722 23232>,
+ <16018 21118 27035 26434 24127>,
+ <16645 23294 28384 24319 24647>,
+ <17006 24872 28918 32325 24114>,
+ <17329 24957 28925 41212 23401>,
+ <17475 24411 27627 38690 23573>,
+ <17228 23700 25743 29078 24700>,
+ <16843 22451 25892 25145 25730>,
+ <16713 21493 28947 25539 26268>,
+ <16684 22252 33007 26312 26883>,
+ <16677 25437 39283 30188 29297>,
+ <17286 30109 45835 38578 34491>,
+ <19164 41217 46475 41118 36407>,
+ <21415 52548 42035 33266 29970>,
+ <24280 54738 37409 24407 21966>,
+ <27650 53178 32621 21235 19178>,
+ <31527 51217 27950 19264 17548>,
+ <36083 48995 27160 18872 17201>,
+ <38880 46212 27394 20197 19081>,
+ <39999 43945 27952 22345 21926>,
+ <40687 41643 30562 25328 25018>,
+ <40762 40045 34754 29345 28676>,
+ <40056 39423 38012 32056 29850>,
+ <38871 39222 41069 34107 29859>,
+ <36720 39556 42479 35178 29754>,
+ <33287 40604 42412 34738 29518>,
+ <30798 41511 42229 33620 29103>,
+ <28649 41745 41780 32637 28701>,
+ <26806 41827 40275 31767 28155>,
+ <27048 41563 38394 30706 27667>,
+ <29742 38580 35903 28670 27140>,
+ <27377 36527 33978 26985 26703>,
+ <12208 37238 33276 27710 27540>,
+ <11897 36443 33534 28761 27769>,
+ <11918 32799 33483 24510 23701>,
+ <11875 27905 30201 24492 22265>,
+ <11855 20759 31274 26299 20689>,
+ <11843 12718 21861 24882 24239>,
+ <11827 11804 22251 23732 23230>,
+ <11869 12201 22033 22105 27815>,
+ <11916 16556 23149 19874 26577>,
+ <11769 12200 22674 20403 20943>,
+ <11606 11883 16988 18240 18167>,
+ <11606 11883 16988 18240 18167>,
+ <11606 11883 16988 18240 18167>;
+ };
+
+ qcom,pc-temp-z6-lut {
+ qcom,lut-col-legend = <0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200>,
+ <9000 8800 8600 8400 8200>,
+ <8000 7800 7600 7400 7200>,
+ <7000 6800 6600 6400 6200>,
+ <6000 5800 5600 5400 5200>,
+ <5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200>,
+ <3000 2800 2600 2400 2200>,
+ <2000 1800 1600 1400 1200>,
+ <1000 900 800 700 600>,
+ <500 400 300 200 100>,
+ <0>;
+ qcom,lut-data = <16721 15696 14993 14731 14679>,
+ <16826 15758 15021 14776 14701>,
+ <16688 15710 14994 14766 14697>,
+ <16529 15576 14964 14754 14692>,
+ <16364 15461 14928 14737 14683>,
+ <16213 15385 14897 14720 14671>,
+ <16101 15323 14870 14705 14661>,
+ <16012 15272 14845 14692 14651>,
+ <15936 15231 14826 14680 14642>,
+ <15873 15195 14812 14668 14634>,
+ <15817 15162 14799 14658 14625>,
+ <15763 15133 14787 14652 14619>,
+ <15712 15104 14775 14649 14614>,
+ <15668 15074 14768 14645 14609>,
+ <15633 15051 14763 14638 14604>,
+ <15603 15040 14759 14631 14598>,
+ <15572 15032 14752 14626 14593>,
+ <15538 15022 14744 14621 14589>,
+ <15504 15007 14738 14617 14584>,
+ <15480 14995 14732 14613 14579>,
+ <15462 14994 14730 14610 14575>,
+ <15447 14993 14737 14617 14580>,
+ <15432 14994 14753 14641 14603>,
+ <15419 15008 14773 14658 14621>,
+ <15413 15029 14801 14671 14632>,
+ <15412 15046 14815 14678 14638>,
+ <15411 15065 14810 14675 14637>,
+ <15413 15073 14800 14669 14630>,
+ <15416 15072 14793 14663 14624>,
+ <15417 15068 14788 14658 14620>,
+ <15417 15063 14784 14654 14616>,
+ <15416 15054 14781 14650 14612>,
+ <15414 15045 14778 14647 14608>,
+ <15410 15038 14776 14644 14604>,
+ <15406 15033 14775 14641 14600>,
+ <15403 15030 14773 14638 14596>,
+ <15401 15029 14771 14636 14594>,
+ <15400 15028 14769 14635 14592>,
+ <15400 15029 14769 14635 14592>,
+ <15400 15031 14772 14638 14596>,
+ <15401 15034 14774 14640 14600>,
+ <15408 15035 14770 14636 14598>,
+ <15409 15037 14766 14632 14595>,
+ <15402 15039 14766 14632 14596>,
+ <15377 15027 14758 14627 14591>,
+ <15372 15017 14749 14615 14579>,
+ <15369 15013 14744 14611 14575>,
+ <15368 15009 14740 14605 14567>,
+ <15368 15005 14734 14596 14557>,
+ <15370 15006 14734 14593 14551>,
+ <15380 15015 14743 14604 14568>,
+ <15399 15035 14756 14617 14583>,
+ <15419 15050 14764 14622 14587>,
+ <15443 15070 14773 14628 14592>,
+ <15443 15070 14773 14628 14592>,
+ <15443 15070 14773 14628 14592>;
+ };
+
+ qcom,pc-temp-y1-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <6931 6268 5885 5443 5214 5111>,
+ <6893 6266 5873 5450 5215 5113>,
+ <6865 6265 5862 5453 5215 5115>,
+ <6847 6264 5852 5453 5215 5115>,
+ <6837 6264 5846 5452 5214 5116>,
+ <6834 6264 5843 5451 5212 5115>,
+ <6843 6267 5849 5449 5210 5114>,
+ <6857 6274 5858 5445 5207 5113>,
+ <6860 6283 5858 5445 5205 5111>,
+ <6858 6302 5848 5447 5204 5110>,
+ <6856 6314 5841 5448 5203 5108>,
+ <6860 6300 5845 5445 5202 5108>,
+ <6866 6278 5852 5441 5202 5107>,
+ <6863 6274 5855 5440 5201 5107>,
+ <6850 6280 5863 5442 5198 5108>,
+ <6842 6286 5869 5445 5196 5109>,
+ <6853 6288 5867 5451 5199 5108>,
+ <6872 6287 5863 5460 5203 5107>,
+ <6878 6289 5861 5461 5204 5107>,
+ <6888 6307 5860 5453 5203 5109>,
+ <6897 6322 5859 5448 5203 5110>,
+ <6889 6313 5859 5450 5203 5111>,
+ <6867 6295 5858 5453 5205 5112>,
+ <6857 6291 5860 5456 5207 5113>,
+ <6848 6297 5866 5459 5211 5115>,
+ <6842 6302 5869 5462 5214 5117>,
+ <6855 6300 5868 5467 5216 5119>,
+ <6880 6298 5867 5472 5218 5120>,
+ <6896 6302 5866 5478 5221 5123>,
+ <6908 6316 5864 5486 5224 5125>,
+ <6915 6324 5863 5492 5228 5128>,
+ <6898 6310 5866 5492 5232 5131>,
+ <6859 6286 5870 5491 5236 5135>,
+ <6840 6283 5872 5491 5239 5138>,
+ <6830 6304 5873 5495 5242 5139>,
+ <6824 6320 5873 5499 5245 5141>,
+ <6831 6313 5876 5502 5247 5143>,
+ <6844 6302 5883 5505 5250 5146>,
+ <6847 6299 5885 5506 5252 5148>,
+ <6848 6296 5884 5510 5256 5149>,
+ <6851 6292 5884 5514 5259 5151>,
+ <6861 6284 5885 5518 5263 5154>,
+ <6873 6278 5888 5524 5267 5158>,
+ <6857 6301 5892 5533 5273 5161>,
+ <6841 6315 5890 5550 5287 5167>,
+ <6893 6327 5904 5569 5290 5172>,
+ <6916 6348 5919 5560 5291 5173>,
+ <6967 6338 5911 5556 5290 5171>,
+ <6953 6346 5926 5558 5290 5170>,
+ <6942 6384 5912 5558 5290 5169>,
+ <6931 6395 5916 5560 5289 5171>,
+ <6989 6394 5921 5567 5297 5175>,
+ <6964 6381 5944 5576 5310 5185>,
+ <7050 6424 5972 5589 5327 5197>,
+ <7050 6424 5972 5589 5327 5197>,
+ <7050 6424 5972 5589 5327 5197>;
+ };
+
+ qcom,pc-temp-y2-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <10233 10673 10754 11269 11221 11072>,
+ <10011 10382 10711 11241 11199 11053>,
+ <9914 10199 10686 11212 11158 11022>,
+ <9912 10099 10674 11184 11110 10988>,
+ <9973 10057 10670 11157 11068 10957>,
+ <10068 10049 10672 11132 11043 10940>,
+ <10284 10110 10694 11109 11029 10932>,
+ <10545 10235 10727 11087 11016 10926>,
+ <10517 10344 10714 11060 11001 10912>,
+ <10038 10475 10618 11027 10973 10878>,
+ <9702 10544 10558 10996 10955 10854>,
+ <9822 10503 10689 10963 10958 10852>,
+ <10040 10439 10892 10936 10965 10855>,
+ <10066 10450 10934 10939 10973 10860>,
+ <9850 10607 10936 10997 10982 10867>,
+ <9680 10791 10939 11064 10995 10877>,
+ <9675 10960 10990 11111 11021 10900>,
+ <9674 11110 11077 11156 11063 10937>,
+ <9673 11137 11137 11217 11119 10988>,
+ <9673 11103 11186 11312 11208 11064>,
+ <9672 11044 11222 11366 11265 11129>,
+ <9671 10887 11248 11358 11271 11175>,
+ <9670 10614 11266 11343 11267 11209>,
+ <9669 10362 11269 11343 11266 11212>,
+ <9668 9968 11266 11369 11276 11192>,
+ <9668 9724 11259 11396 11292 11182>,
+ <9667 9707 11155 11410 11317 11192>,
+ <9666 9699 11029 11423 11350 11210>,
+ <9666 9692 11014 11440 11389 11236>,
+ <9665 9686 10945 11469 11442 11290>,
+ <9664 9681 10870 11489 11473 11336>,
+ <9664 9677 10693 11487 11482 11361>,
+ <9663 9673 10508 11481 11488 11379>,
+ <9663 9670 10576 11475 11484 11384>,
+ <9662 9668 10842 11460 11461 11386>,
+ <9662 9666 10937 11441 11433 11380>,
+ <9661 9664 10471 11418 11404 11331>,
+ <9661 9663 9842 11380 11374 11260>,
+ <9661 9662 9711 11340 11357 11224>,
+ <9661 9662 9690 11295 11342 11202>,
+ <9661 9661 9679 11241 11336 11189>,
+ <9661 9661 9673 11176 11339 11213>,
+ <9660 9660 9669 11100 11335 11239>,
+ <9660 9660 9666 10997 11299 11191>,
+ <9659 9659 9663 10894 11193 11057>,
+ <9659 9659 9663 10866 11131 10986>,
+ <9659 9659 9662 10862 11122 10982>,
+ <9658 9658 9661 10848 11125 10998>,
+ <9658 9658 9660 10833 11120 11027>,
+ <9658 9658 9659 10835 11185 11062>,
+ <9658 9657 9659 10790 11142 11008>,
+ <9657 9657 9658 10696 11041 10901>,
+ <9656 9656 9657 10596 10953 10839>,
+ <9654 9656 9656 10530 10895 10701>,
+ <9654 9656 9656 10530 10895 10701>,
+ <9654 9656 9656 10530 10895 10701>;
+ };
+
+ qcom,pc-temp-y3-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <13832 13669 13388 13308 13287 13280>,
+ <13809 13623 13394 13308 13286 13281>,
+ <13779 13595 13399 13309 13286 13282>,
+ <13749 13580 13402 13310 13286 13283>,
+ <13726 13574 13404 13311 13286 13284>,
+ <13716 13573 13405 13312 13287 13285>,
+ <13720 13589 13403 13313 13287 13285>,
+ <13726 13614 13400 13314 13288 13286>,
+ <13706 13598 13406 13315 13288 13286>,
+ <13585 13471 13436 13315 13289 13287>,
+ <13497 13384 13455 13316 13290 13287>,
+ <13499 13395 13415 13319 13293 13288>,
+ <13508 13417 13355 13323 13296 13288>,
+ <13506 13423 13349 13323 13297 13288>,
+ <13490 13421 13371 13318 13298 13289>,
+ <13477 13418 13384 13315 13298 13289>,
+ <13472 13412 13381 13315 13299 13291>,
+ <13470 13402 13373 13315 13301 13294>,
+ <13471 13391 13366 13316 13301 13295>,
+ <13475 13375 13360 13316 13299 13295>,
+ <13476 13364 13354 13317 13297 13295>,
+ <13467 13363 13347 13314 13294 13293>,
+ <13453 13363 13340 13308 13291 13287>,
+ <13451 13356 13334 13304 13289 13284>,
+ <13465 13318 13329 13302 13287 13282>,
+ <13482 13289 13321 13300 13285 13281>,
+ <13497 13295 13304 13300 13285 13280>,
+ <13514 13309 13285 13300 13284 13280>,
+ <13534 13322 13277 13300 13284 13280>,
+ <13562 13335 13266 13299 13284 13280>,
+ <13592 13351 13259 13298 13285 13280>,
+ <13622 13374 13268 13297 13285 13280>,
+ <13654 13405 13284 13297 13285 13280>,
+ <13686 13436 13297 13297 13286 13281>,
+ <13718 13467 13316 13298 13285 13281>,
+ <13752 13499 13331 13299 13285 13281>,
+ <13791 13534 13339 13299 13285 13280>,
+ <13833 13570 13348 13300 13284 13279>,
+ <13870 13607 13359 13301 13285 13279>,
+ <13901 13646 13371 13303 13285 13281>,
+ <13933 13683 13386 13305 13286 13283>,
+ <13972 13712 13414 13307 13287 13284>,
+ <14016 13740 13452 13309 13288 13285>,
+ <14064 13772 13493 13309 13288 13283>,
+ <14120 13816 13545 13310 13287 13283>,
+ <14130 13837 13547 13314 13289 13287>,
+ <14144 13848 13583 13316 13294 13291>,
+ <14199 13892 13629 13321 13297 13293>,
+ <14259 13940 13676 13326 13300 13295>,
+ <14324 13985 13720 13334 13302 13295>,
+ <14392 14027 13762 13335 13297 13290>,
+ <14482 14078 13810 13333 13295 13291>,
+ <14614 14172 13906 13341 13301 13294>,
+ <15087 14292 14005 13352 13310 13302>,
+ <15087 14292 14005 13352 13310 13302>,
+ <15087 14292 14005 13352 13310 13302>;
+ };
+
+ qcom,pc-temp-y4-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <17102 16753 16727 16538 16480 16472>,
+ <17117 16868 16746 16539 16478 16469>,
+ <17126 16961 16776 16540 16477 16466>,
+ <17130 17029 16808 16541 16475 16463>,
+ <17131 17071 16834 16541 16475 16461>,
+ <17130 17085 16844 16541 16475 16460>,
+ <17048 17059 16843 16540 16475 16461>,
+ <16915 17016 16840 16538 16476 16461>,
+ <16958 17038 16824 16539 16477 16463>,
+ <17380 17229 16761 16544 16480 16465>,
+ <17676 17413 16722 16549 16482 16467>,
+ <17651 17513 16873 16555 16482 16470>,
+ <17582 17586 17101 16561 16483 16474>,
+ <17456 17529 17113 16565 16484 16478>,
+ <17130 17108 16957 16570 16490 16484>,
+ <16908 16807 16848 16578 16498 16489>,
+ <16894 16826 16835 16600 16508 16494>,
+ <16886 16865 16826 16637 16521 16499>,
+ <16865 16870 16815 16663 16542 16510>,
+ <16803 16841 16801 16685 16575 16534>,
+ <16754 16798 16780 16696 16593 16548>,
+ <16745 16733 16734 16655 16570 16537>,
+ <16739 16661 16674 16576 16528 16516>,
+ <16735 16647 16633 16534 16500 16495>,
+ <16731 16665 16602 16511 16476 16472>,
+ <16729 16678 16583 16499 16466 16461>,
+ <16729 16676 16574 16497 16467 16462>,
+ <16729 16670 16569 16496 16470 16465>,
+ <16728 16667 16576 16495 16474 16470>,
+ <16726 16668 16610 16495 16481 16478>,
+ <16724 16669 16633 16494 16490 16487>,
+ <16726 16667 16620 16491 16499 16499>,
+ <16731 16665 16596 16487 16508 16510>,
+ <16735 16666 16586 16486 16509 16512>,
+ <16740 16675 16571 16492 16506 16510>,
+ <16744 16685 16569 16498 16502 16508>,
+ <16749 16694 16600 16502 16489 16491>,
+ <16756 16702 16640 16505 16474 16470>,
+ <16765 16706 16660 16509 16472 16468>,
+ <16781 16707 16673 16514 16474 16472>,
+ <16800 16707 16679 16520 16478 16478>,
+ <16819 16695 16678 16530 16485 16486>,
+ <16839 16677 16676 16542 16489 16491>,
+ <16866 16671 16667 16552 16478 16469>,
+ <16882 16673 16658 16555 16474 16458>,
+ <16844 16678 16645 16546 16475 16465>,
+ <16821 16686 16655 16550 16488 16490>,
+ <16840 16708 16674 16568 16514 16523>,
+ <16850 16741 16703 16595 16550 16559>,
+ <16857 16775 16748 16628 16574 16575>,
+ <16857 16783 16762 16626 16528 16509>,
+ <16852 16760 16732 16600 16496 16479>,
+ <16858 16754 16719 16614 16508 16482>,
+ <17046 16785 16734 16648 16541 16507>,
+ <17046 16785 16734 16648 16541 16507>,
+ <17046 16785 16734 16648 16541 16507>;
+ };
+
+ qcom,pc-temp-y5-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <16585 15340 15228 18086 17042 15403>,
+ <14231 14792 15712 18394 17213 16907>,
+ <13450 14543 16330 18589 17122 18026>,
+ <13874 14539 16944 18695 16886 18789>,
+ <15138 14730 17415 18740 16624 19225>,
+ <16877 15066 17602 18749 16454 19362>,
+ <20253 17518 17520 18683 16262 19084>,
+ <24042 21150 17396 18511 15994 18540>,
+ <23786 20975 17877 18221 15795 18054>,
+ <17955 15612 20332 17559 15573 17465>,
+ <13913 11906 21830 16855 15460 16918>,
+ <17108 14418 18696 16252 15984 16501>,
+ <22546 18653 14049 15720 16791 16119>,
+ <22928 19469 14273 15458 16831 15687>,
+ <17443 18543 19465 15314 16235 15155>,
+ <13436 17824 22722 15214 15756 14892>,
+ <13881 18682 22058 15126 15529 15094>,
+ <14845 20435 21061 15075 15338 15400>,
+ <15261 21356 21118 15388 15268 15429>,
+ <15479 21744 22336 17438 15156 15256>,
+ <15565 22239 23298 19792 15192 15183>,
+ <14621 23891 23595 21746 17233 16842>,
+ <12948 26097 23793 23449 20174 19267>,
+ <12526 25489 23919 23886 20726 19781>,
+ <12569 17760 24060 23666 20641 19809>,
+ <12603 11878 24109 23505 20488 19731>,
+ <12607 11881 20340 23800 19821 18965>,
+ <12607 12112 14697 24183 18924 17816>,
+ <12640 12203 12933 24282 18783 17307>,
+ <12873 12278 12121 24249 18956 17027>,
+ <13100 12403 11764 24211 19223 16923>,
+ <13176 12760 12353 24195 19821 17065>,
+ <13205 13307 13546 24358 20687 17407>,
+ <13177 13595 14786 24492 21401 18143>,
+ <13111 13781 16792 24470 22049 19814>,
+ <13051 13910 17745 24264 22415 20725>,
+ <13040 14035 16629 23537 22340 20403>,
+ <13058 14214 14997 22336 22171 19912>,
+ <13022 14354 14543 21352 22120 19981>,
+ <12881 14679 14380 20562 21662 20605>,
+ <12779 14953 14323 19774 21208 21065>,
+ <12888 14713 14467 18881 20700 21383>,
+ <13163 14150 14622 17956 20379 21509>,
+ <13417 13801 14294 16871 20340 20439>,
+ <13695 13672 14011 16474 18724 19208>,
+ <13932 13816 13944 17383 18238 18386>,
+ <14147 13640 14045 17507 18689 17847>,
+ <14245 13928 14206 17290 17961 17057>,
+ <14723 14083 14142 17034 17555 16495>,
+ <15109 14404 14139 17207 17669 16303>,
+ <15076 14871 14389 17538 18479 17101>,
+ <14872 14468 14240 17565 18901 18981>,
+ <14276 14375 14262 17885 19804 19028>,
+ <13001 14369 14220 18328 23134 23661>,
+ <13001 14369 14220 18328 23134 23661>,
+ <13001 14369 14220 18328 23134 23661>;
+ };
+
+ qcom,pc-temp-y6-lut {
+ qcom,lut-col-legend = <(-10) 0 10 25 40 50>;
+ qcom,lut-row-legend = <10000 9800 9600 9400 9200 9000>,
+ <8800 8600 8400 8200 8000 7800>,
+ <7600 7400 7200 7000 6800 6600>,
+ <6400 6200 6000 5800 5600 5400>,
+ <5200 5000 4800 4600 4400 4200>,
+ <4000 3800 3600 3400 3200 3000>,
+ <2800 2600 2400 2200 2000 1800>,
+ <1600 1400 1200 1000 900 800>,
+ <700 600 500 400 300 200>,
+ <100 0>;
+ qcom,lut-data = <6441 5891 5409 5108 5033 5015>,
+ <6405 5878 5413 5109 5032 5015>,
+ <6368 5864 5416 5110 5031 5014>,
+ <6332 5850 5417 5110 5031 5014>,
+ <6297 5839 5418 5110 5031 5015>,
+ <6262 5831 5418 5111 5031 5015>,
+ <6221 5827 5414 5111 5031 5015>,
+ <6184 5823 5406 5110 5032 5016>,
+ <6174 5813 5401 5111 5033 5016>,
+ <6173 5787 5396 5111 5034 5017>,
+ <6174 5771 5393 5113 5035 5018>,
+ <6176 5796 5407 5116 5037 5019>,
+ <6175 5837 5427 5120 5039 5021>,
+ <6150 5828 5426 5121 5041 5022>,
+ <6039 5717 5399 5119 5043 5024>,
+ <5961 5637 5377 5118 5045 5026>,
+ <5961 5640 5371 5125 5048 5029>,
+ <5961 5648 5367 5137 5054 5032>,
+ <5960 5648 5361 5145 5059 5036>,
+ <5952 5637 5353 5151 5067 5044>,
+ <5944 5624 5343 5154 5071 5047>,
+ <5940 5611 5326 5141 5063 5042>,
+ <5936 5599 5306 5115 5048 5032>,
+ <5937 5588 5294 5101 5038 5023>,
+ <5950 5577 5286 5093 5030 5015>,
+ <5966 5571 5279 5089 5026 5011>,
+ <5980 5581 5271 5090 5027 5012>,
+ <5995 5604 5265 5091 5027 5012>,
+ <6013 5627 5266 5091 5028 5013>,
+ <6035 5649 5278 5092 5031 5016>,
+ <6060 5674 5294 5092 5034 5019>,
+ <6086 5702 5310 5093 5038 5023>,
+ <6113 5732 5330 5093 5041 5027>,
+ <6140 5765 5353 5095 5041 5027>,
+ <6166 5802 5381 5099 5041 5027>,
+ <6193 5840 5412 5105 5040 5027>,
+ <6225 5876 5447 5109 5037 5022>,
+ <6260 5913 5485 5114 5033 5015>,
+ <6294 5948 5526 5120 5033 5015>,
+ <6325 5983 5569 5127 5034 5018>,
+ <6357 6014 5616 5136 5037 5021>,
+ <6393 6037 5666 5149 5040 5025>,
+ <6433 6058 5716 5164 5043 5027>,
+ <6477 6085 5764 5180 5041 5019>,
+ <6531 6124 5819 5199 5040 5017>,
+ <6550 6148 5826 5201 5044 5023>,
+ <6564 6165 5861 5205 5051 5033>,
+ <6616 6205 5906 5220 5061 5044>,
+ <6671 6254 5956 5241 5073 5055>,
+ <6728 6304 6011 5262 5080 5060>,
+ <6791 6343 6053 5268 5064 5038>,
+ <6869 6382 6092 5273 5055 5031>,
+ <6987 6461 6172 5318 5065 5035>,
+ <7491 6577 6267 5371 5084 5050>,
+ <7491 6577 6267 5371 5084 5050>,
+ <7491 6577 6267 5371 5084 5050>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/qm215-audio.dtsi
new file mode 100755
index 0000000..ce76e90
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qm215-audio.dtsi
@@ -0,0 +1,194 @@
+#include "msm-audio-lpass.dtsi"
+
+&msm_audio_ion {
+ iommus = <&apps_iommu 0x2001 0x0>;
+ qcom,smmu-sid-mask = /bits/ 64 <0xf>;
+};
+
+
+&soc {
+ qcom,avtimer@c0a300c {
+ compatible = "qcom,avtimer";
+ reg = <0x0c0a300c 0x4>,
+ <0x0c0a3010 0x4>;
+ reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
+ qcom,clk-div = <27>;
+ };
+
+ audio_apr: qcom,msm-audio-apr {
+ compatible = "qcom,msm-audio-apr";
+ q6core: q6core {
+ compatible = "qcom,q6core-audio";
+ };
+ };
+
+ int_codec: sound {
+ status = "okay";
+ compatible = "qcom,msm8952-audio-codec";
+ qcom,model = "msm8952-snd-card-mtp";
+ reg = <0xc051000 0x4>,
+ <0xc051004 0x4>,
+ <0xc055000 0x4>,
+ <0xc052000 0x4>;
+ reg-names = "csr_gp_io_mux_mic_ctl",
+ "csr_gp_io_mux_spkr_ctl",
+ "csr_gp_io_lpaif_pri_pcm_pri_mode_muxsel",
+ "csr_gp_io_mux_quin_ctl";
+
+ qcom,msm-ext-pa = "primary";
+ qcom,msm-mclk-freq = <9600000>;
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ qcom,msm-hs-micbias-type = "external";
+ qcom,msm-micbias1-ext-cap;
+
+ qcom,audio-routing =
+ "RX_BIAS", "MCLK",
+ "SPK_RX_BIAS", "MCLK",
+ "INT_LDO_H", "MCLK",
+ "RX_I2S_CLK", "MCLK",
+ "TX_I2S_CLK", "MCLK",
+ "MIC BIAS External", "Handset Mic",
+ "MIC BIAS External2", "Headset Mic",
+ "MIC BIAS External", "Secondary Mic",
+ "AMIC1", "MIC BIAS External",
+ "AMIC2", "MIC BIAS External2",
+ "AMIC3", "MIC BIAS External",
+ "ADC1_IN", "ADC1_OUT",
+ "ADC2_IN", "ADC2_OUT",
+ "ADC3_IN", "ADC3_OUT",
+ "PDM_IN_RX1", "PDM_OUT_RX1",
+ "PDM_IN_RX2", "PDM_OUT_RX2",
+ "PDM_IN_RX3", "PDM_OUT_RX3";
+
+ qcom,pri-mi2s-gpios = <&cdc_pri_mi2s_gpios>;
+ qcom,quin-mi2s-gpios = <&cdc_quin_mi2s_gpios>;
+
+ asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
+ <&loopback>, <&compress>, <&hostless>,
+ <&afe>, <&lsm>, <&routing>, <&pcm_noirq>;
+ asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
+ "msm-pcm-dsp.2", "msm-voip-dsp",
+ "msm-pcm-voice", "msm-pcm-loopback",
+ "msm-compress-dsp", "msm-pcm-hostless",
+ "msm-pcm-afe", "msm-lsm-client",
+ "msm-pcm-routing", "msm-pcm-dsp-noirq";
+ asoc-cpu = <&dai_pri_auxpcm>,
+ <&dai_mi2s0>, <&dai_mi2s1>,
+ <&dai_mi2s2>, <&dai_mi2s3>,
+ <&dai_mi2s4>, <&dai_mi2s5>,
+ <&bt_sco_rx>, <&bt_sco_tx>,
+ <&int_fm_rx>, <&int_fm_tx>,
+ <&afe_pcm_rx>, <&afe_pcm_tx>,
+ <&afe_proxy_rx>, <&afe_proxy_tx>,
+ <&incall_record_rx>, <&incall_record_tx>,
+ <&incall_music_rx>, <&incall_music_2_rx>,
+ <&proxy_rx>, <&proxy_tx>;
+
+ asoc-cpu-names = "msm-dai-q6-auxpcm.1",
+ "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",
+ "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",
+ "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.6",
+ "msm-dai-q6-dev.12288", "msm-dai-q6-dev.12289",
+ "msm-dai-q6-dev.12292", "msm-dai-q6-dev.12293",
+ "msm-dai-q6-dev.224", "msm-dai-q6-dev.225",
+ "msm-dai-q6-dev.241", "msm-dai-q6-dev.240",
+ "msm-dai-q6-dev.32771", "msm-dai-q6-dev.32772",
+ "msm-dai-q6-dev.32773", "msm-dai-q6-dev.32770",
+ "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195";
+
+ asoc-codec = <&stub_codec>, <&msm_digital_codec>,
+ <&pmic_analog_codec>;
+ asoc-codec-names = "msm-stub-codec.1", "msm-dig-codec",
+ "analog-codec";
+ };
+
+ cdc_us_euro_sw: msm_cdc_pinctrl_us_euro_sw {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cross_conn_det_act>;
+ pinctrl-1 = <&cross_conn_det_sus>;
+ };
+
+ cdc_pri_mi2s_gpios: msm_cdc_pinctrl_pri {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_pdm_lines_act &cdc_pdm_lines_2_act>;
+ pinctrl-1 = <&cdc_pdm_lines_sus &cdc_pdm_lines_2_sus>;
+ };
+
+ cdc_quin_mi2s_gpios: msm_cdc_pinctrl_quin {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&pri_tlmm_lines_act &pri_tlmm_ws_act>;
+ pinctrl-1 = <&pri_tlmm_lines_sus &pri_tlmm_ws_sus>;
+ };
+};
+
+&pm8916_1 {
+ pmic_analog_codec: analog-codec@f000 {
+ status = "okay";
+ compatible = "qcom,pmic-analog-codec";
+ reg = <0xf000 0x200>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-parent = <&spmi_bus>;
+ interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x1 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x2 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x3 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x4 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x5 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x6 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x7 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x0 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x1 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x2 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x3 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x4 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x5 IRQ_TYPE_NONE>;
+ interrupt-names = "spk_cnp_int",
+ "spk_clip_int",
+ "spk_ocp_int",
+ "ins_rem_det1",
+ "but_rel_det",
+ "but_press_det",
+ "ins_rem_det",
+ "mbhc_int",
+ "ear_ocp_int",
+ "hphr_ocp_int",
+ "hphl_ocp_det",
+ "ear_cnp_int",
+ "hphr_cnp_int",
+ "hphl_cnp_int";
+
+ cdc-vdd-pa-cp-supply = <&pm8916_s4>;
+ qcom,cdc-vdd-pa-cp-voltage = <2050000 2050000>;
+ qcom,cdc-vdd-pa-cp-current = <550000>;
+
+ cdc-vdd-io-supply = <&pm8916_l5>;
+ qcom,cdc-vdd-io-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-io-current = <5000>;
+
+ cdc-vdda-h-supply = <&pm8916_l5>;
+ qcom,cdc-vdda-h-voltage = <1800000 1800000>;
+ qcom,cdc-vdda-h-current = <10000>;
+
+ cdc-vdd-mic-bias-supply = <&pm8916_l13>;
+ qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>;
+ qcom,cdc-vdd-mic-bias-current = <5000>;
+
+ qcom,cdc-mclk-clk-rate = <9600000>;
+
+ qcom,cdc-static-supplies = "cdc-vdd-io",
+ "cdc-vdd-pa-cp",
+ "cdc-vdda-h";
+
+ qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias";
+
+ msm_digital_codec: msm-dig-codec {
+ compatible = "qcom,msm-digital-codec";
+ reg = <0xc0f0000 0x0>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-camera-sensor-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/qm215-camera-sensor-qrd.dtsi
new file mode 100755
index 0000000..7b068f7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qm215-camera-sensor-qrd.dtsi
@@ -0,0 +1,191 @@
+&cci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ actuator0: qcom,actuator@0 {
+ cell-index = <0>;
+ reg = <0x0>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <0>;
+ cam_vaf-supply = <&pm8916_l10>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2850000>;
+ qcom,cam-vreg-max-voltage = <2850000>;
+ qcom,cam-vreg-op-mode = <80000>;
+ };
+
+ eeprom0: qcom,eeprom@0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ qcom,cci-master = <0>;
+ reg = <0x0>;
+ cam_vana-supply = <&pm8916_l16>;
+ cam_vio-supply = <&pm8916_l6>;
+ cam_vaf-supply = <&pm8916_l10>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vaf";
+ qcom,cam-vreg-min-voltage = <0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <0 80000 100000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_default
+ &cam_sensor_rear_vdig_qm215
+ &cam_sensor_rear_default>;
+ pinctrl-1 = <&cam_sensor_mclk0_sleep
+ &cam_sensor_rear_vdig_sleep_qm215
+ &cam_sensor_rear_sleep>;
+ gpios = <&tlmm 25 0>,
+ <&tlmm 26 0>,
+ <&tlmm 36 0>;
+ qcom,gpio-reset = <2>;
+ qcom,gpio-vdig = <0>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <0 1 0>;
+ qcom,gpio-req-tbl-label = "CAM_VDIG",
+ "CAMIF_MCLK0",
+ "CAM_RESET0";
+ status = "ok";
+ clocks = <&gcc MCLK0_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <19200000 0>;
+ };
+
+ eeprom2: qcom,eeprom@2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ reg = <0x02>;
+ cam_vana-supply = <&pm8916_l16>;
+ cam_vio-supply = <&pm8916_l6>;
+ cam_vaf-supply = <&pm8916_l10>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vaf";
+ qcom,cam-vreg-min-voltage = <0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <0 80000 100000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_default
+ &cam_sensor_rear_vdig_qm215
+ &cam_sensor_front1_default>;
+ pinctrl-1 = <&cam_sensor_mclk2_sleep
+ &cam_sensor_rear_vdig_sleep_qm215
+ &cam_sensor_front1_sleep>;
+ gpios = <&tlmm 25 0>,
+ <&tlmm 28 0>,
+ <&tlmm 40 0>;
+ qcom,gpio-reset = <2>;
+ qcom,gpio-standby = <0>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0 >;
+ qcom,gpio-req-tbl-label = "CAM_VDIG",
+ "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_STANDBY2";
+ qcom,cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc MCLK2_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <19200000 0>;
+ };
+
+ flash0: qcom,camera-flash {
+ cell-index = <0>;
+ compatible = "qcom,qm215-gpio-flash";
+ qcom,flash-type = <2>;
+ gpios = <&tlmm 34 0>,
+ <&tlmm 33 0>;
+ qcom,gpio-req-tbl-num = <0 1>;
+ qcom,gpio-req-tbl-flags = <1 0>;
+ qcom,gpio-flash-en = <0>;
+ qcom,gpio-flash-now = <1>;
+ qcom,gpio-req-tbl-label = "CAM_FLASH",
+ "CAM_TORCH";
+ status = "ok";
+ };
+
+ qcom,camera@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera";
+ reg = <0x0>;
+ qcom,csiphy-sd-index = <0>;
+ qcom,csid-sd-index = <0>;
+ qcom,mount-angle = <90>;
+ qcom,led-flash-src = <&flash0>;
+ qcom,actuator-src = <&actuator0>;
+ qcom,eeprom-src = <&eeprom0>;
+ cam_vana-supply = <&pm8916_l16>;
+ cam_vio-supply = <&pm8916_l6>;
+ cam_vaf-supply = <&pm8916_l10>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vaf";
+ qcom,cam-vreg-min-voltage = <0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <0 80000 100000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_default
+ &cam_sensor_rear_vdig_qm215
+ &cam_sensor_rear_default>;
+ pinctrl-1 = <&cam_sensor_mclk0_sleep
+ &cam_sensor_rear_vdig_sleep_qm215
+ &cam_sensor_rear_sleep>;
+ gpios = <&tlmm 25 0>,
+ <&tlmm 26 0>,
+ <&tlmm 36 0>;
+
+ qcom,gpio-reset = <2>;
+ qcom,gpio-vdig = <0>;
+ qcom,gpio-req-tbl-num = <0 1 2 >;
+ qcom,gpio-req-tbl-flags = <1 0 0 >;
+ qcom,gpio-req-tbl-label = "CAM_VDIG",
+ "CAMIF_MCLK0",
+ "CAM_RESET0";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <0>;
+ clocks = <&gcc MCLK0_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@2 {
+ cell-index = <2>;
+ compatible = "qcom,camera";
+ reg = <0x01>;
+ qcom,csiphy-sd-index = <1>;
+ qcom,csid-sd-index = <1>;
+ qcom,eeprom-src = <&eeprom2>;
+ qcom,mount-angle = <270>;
+ cam_vana-supply = <&pm8916_l16>;
+ cam_vio-supply = <&pm8916_l6>;
+ cam_vaf-supply = <&pm8916_l10>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vaf";
+ qcom,cam-vreg-min-voltage = <0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <0 80000 100000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_default
+ &cam_sensor_rear_vdig_qm215
+ &cam_sensor_front1_default>;
+ pinctrl-1 = <&cam_sensor_mclk2_sleep
+ &cam_sensor_rear_vdig_sleep_qm215
+ &cam_sensor_front1_sleep>;
+ gpios = <&tlmm 25 0>,
+ <&tlmm 28 0>,
+ <&tlmm 40 0>;
+ qcom,gpio-reset = <2>;
+ qcom,gpio-vdig = <0>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAM_VDIG",
+ "CAMIF_MCLK2",
+ "CAM_RESET2";
+ qcom,sensor-position = <1>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <0>;
+ clocks = <&gcc MCLK2_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-camera.dtsi b/arch/arm64/boot/dts/vendor/qcom/qm215-camera.dtsi
new file mode 100755
index 0000000..d41f786
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qm215-camera.dtsi
@@ -0,0 +1,516 @@
+&soc {
+ qcom,msm-cam@1b00000 {
+ compatible = "qcom,msm-cam";
+ reg = <0x1b00000 0x40000>;
+ reg-names = "msm-cam";
+ status = "ok";
+ bus-vectors = "suspend", "svs", "nominal", "turbo";
+ qcom,bus-votes = <0 160000000 320000000 320000000>;
+ };
+
+ qcom,csiphy@1b34000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy";
+ reg = <0x1b34000 0x1000>,
+ <0x1b00030 0x4>;
+ reg-names = "csiphy", "csiphy_clk_mux";
+ interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csiphy";
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc CSI0PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
+ <&gcc CAMSS_TOP_AHB_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI0PHY_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",
+ "csiphy_timer_src_clk", "csiphy_timer_clk",
+ "camss_ahb_src", "csi_phy_clk",
+ "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 200000000 0 0 0 0>;
+ };
+
+ qcom,csiphy@1b35000 {
+ status = "ok";
+ cell-index = <1>;
+ compatible = "qcom,csiphy-v3.4.2", "qcom,csiphy";
+ reg = <0x1b35000 0x1000>,
+ <0x1b00038 0x4>;
+ reg-names = "csiphy", "csiphy_clk_mux";
+ interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csiphy";
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc CSI1PHYTIMER_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
+ <&gcc CAMSS_TOP_AHB_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI1PHY_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk", "ispif_ahb_clk",
+ "csiphy_timer_src_clk", "csiphy_timer_clk",
+ "camss_ahb_src", "csi_phy_clk",
+ "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 200000000 0 0 0 0>;
+ };
+
+ qcom,csid@1b30000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,csid-v3.4.3", "qcom,csid";
+ reg = <0x1b30000 0x400>;
+ reg-names = "csid";
+ interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid";
+ qcom,csi-vdd-voltage = <1088000>;
+ qcom,mipi-csi-vdd-supply = <&pm8916_l2>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
+ <&gcc CSI0_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI0_CLK>,
+ <&gcc GCC_CAMSS_CSI0PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI0RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk",
+ "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",
+ "csi_clk", "csi_pix_clk",
+ "csi_rdi_clk", "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0>;
+ };
+
+ qcom,csid@1b30400 {
+ status = "ok";
+ cell-index = <1>;
+ compatible = "qcom,csid-v3.4.3", "qcom,csid";
+ reg = <0x1b30400 0x400>;
+ reg-names = "csid";
+ interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid";
+ qcom,csi-vdd-voltage = <1088000>;
+ qcom,mipi-csi-vdd-supply = <&pm8916_l2>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
+ <&gcc CSI1_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI1_CLK>,
+ <&gcc GCC_CAMSS_CSI1PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI1RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk",
+ "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",
+ "csi_clk", "csi_pix_clk",
+ "csi_rdi_clk", "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0>;
+ };
+
+ qcom,csid@1b30800 {
+ status = "ok";
+ cell-index = <2>;
+ compatible = "qcom,csid-v3.4.3", "qcom,csid";
+ reg = <0x1b30800 0x400>;
+ reg-names = "csid";
+ interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid";
+ qcom,csi-vdd-voltage = <1088000>;
+ qcom,mipi-csi-vdd-supply = <&pm8916_l2>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_CSI2_AHB_CLK>,
+ <&gcc CSI2_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI2_CLK>,
+ <&gcc GCC_CAMSS_CSI2PIX_CLK>,
+ <&gcc GCC_CAMSS_CSI2RDI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk",
+ "ispif_ahb_clk", "csi_ahb_clk", "csi_src_clk",
+ "csi_clk", "csi_pix_clk",
+ "csi_rdi_clk", "camss_ahb_clk";
+ qcom,clock-rates = <0 61540000 0 200000000 0 0 0 0>;
+ };
+
+ qcom,ispif@1b31000 {
+ cell-index = <0>;
+ compatible = "qcom,ispif-v3.0", "qcom,ispif";
+ reg = <0x1b31000 0x500>,
+ <0x1b00020 0x10>;
+ reg-names = "ispif", "csi_clk_mux";
+ interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ispif";
+ qcom,num-isps = <0x2>;
+ vfe0-vdd-supply = <&gdsc_vfe>;
+ vfe1-vdd-supply = <&gdsc_vfe1>;
+ qcom,vdd-names = "vfe0-vdd", "vfe1-vdd";
+ clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc CAMSS_TOP_AHB_CLK_SRC>,
+ <&gcc CSI0_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI0_CLK>,
+ <&gcc GCC_CAMSS_CSI0RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI0PIX_CLK>,
+ <&gcc CSI1_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI1_CLK>,
+ <&gcc GCC_CAMSS_CSI1RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI1PIX_CLK>,
+ <&gcc CSI2_CLK_SRC>,
+ <&gcc GCC_CAMSS_CSI2_CLK>,
+ <&gcc GCC_CAMSS_CSI2RDI_CLK>,
+ <&gcc GCC_CAMSS_CSI2PIX_CLK>,
+ <&gcc VFE0_CLK_SRC>,
+ <&gcc GCC_CAMSS_VFE0_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
+ <&gcc VFE1_CLK_SRC>,
+ <&gcc GCC_CAMSS_VFE1_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE1_CLK>;
+ clock-names = "ispif_ahb_clk",
+ "camss_ahb_clk", "camss_top_ahb_clk",
+ "camss_ahb_src",
+ "csi0_src_clk", "csi0_clk",
+ "csi0_rdi_clk", "csi0_pix_clk",
+ "csi1_src_clk", "csi1_clk",
+ "csi1_rdi_clk", "csi1_pix_clk",
+ "csi2_src_clk", "csi2_clk",
+ "csi2_rdi_clk", "csi2_pix_clk",
+ "vfe0_clk_src", "camss_vfe_vfe0_clk",
+ "camss_csi_vfe0_clk", "vfe1_clk_src",
+ "camss_vfe_vfe1_clk", "camss_csi_vfe1_clk";
+ qcom,clock-rates = <61540000 0 0 0
+ 200000000 0 0 0
+ 200000000 0 0 0
+ 200000000 0 0 0
+ 0 0 0
+ 0 0 0>;
+ qcom,clock-cntl-support;
+ qcom,clock-control = "SET_RATE","NO_SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "NO_SET_RATE", "SET_RATE",
+ "NO_SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
+ "SET_RATE", "NO_SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "INIT_RATE", "NO_SET_RATE",
+ "NO_SET_RATE";
+ };
+
+ vfe0: qcom,vfe0@1b10000 {
+ cell-index = <0>;
+ compatible = "qcom,vfe40";
+ reg = <0x1b10000 0x1000>,
+ <0x1b40000 0x200>;
+ reg-names = "vfe", "vfe_vbif";
+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vfe";
+ vdd-supply = <&gdsc_vfe>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc VFE0_CLK_SRC>,
+ <&gcc GCC_CAMSS_VFE0_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
+ <&gcc GCC_CAMSS_VFE_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE_AXI_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk", "camss_ahb_clk",
+ "vfe_clk_src", "camss_vfe_vfe_clk",
+ "camss_csi_vfe_clk", "iface_clk",
+ "bus_clk", "iface_ahb_clk";
+ qcom,clock-rates = <0 0 266670000 0 0 0 0 0>;
+ qos-entries = <8>;
+ qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8
+ 0x2dc 0x2e0>;
+ qos-settings = <0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55>;
+ vbif-entries = <1>;
+ vbif-regs = <0x124>;
+ vbif-settings = <0x3>;
+ ds-entries = <17>;
+ ds-regs = <0x988 0x98c 0x990 0x994 0x998
+ 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0
+ 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>;
+ ds-settings = <0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0x00000110>;
+ max-clk-nominal = <400000000>;
+ max-clk-turbo = <432000000>;
+ };
+
+ vfe1: qcom,vfe1@1b14000 {
+ cell-index = <1>;
+ compatible = "qcom,vfe40";
+ reg = <0x1b14000 0x1000>,
+ <0x1ba0000 0x200>;
+ reg-names = "vfe", "vfe_vbif";
+ interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vfe";
+ vdd-supply = <&gdsc_vfe1>;
+ clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc VFE1_CLK_SRC>,
+ <&gcc GCC_CAMSS_VFE1_CLK>,
+ <&gcc GCC_CAMSS_CSI_VFE1_CLK>,
+ <&gcc GCC_CAMSS_VFE1_AHB_CLK>,
+ <&gcc GCC_CAMSS_VFE1_AXI_CLK>,
+ <&gcc GCC_CAMSS_ISPIF_AHB_CLK>;
+ clock-names = "camss_top_ahb_clk" , "camss_ahb_clk",
+ "vfe_clk_src", "camss_vfe_vfe_clk",
+ "camss_csi_vfe_clk", "iface_clk",
+ "bus_clk", "iface_ahb_clk";
+ qcom,clock-rates = <0 0 266670000 0 0 0 0 0>;
+ qos-entries = <8>;
+ qos-regs = <0x2c4 0x2c8 0x2cc 0x2d0 0x2d4 0x2d8
+ 0x2dc 0x2e0>;
+ qos-settings = <0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55 0xaa55aa55
+ 0xaa55aa55>;
+ vbif-entries = <1>;
+ vbif-regs = <0x124>;
+ vbif-settings = <0x3>;
+ ds-entries = <17>;
+ ds-regs = <0x988 0x98c 0x990 0x994 0x998
+ 0x99c 0x9a0 0x9a4 0x9a8 0x9ac 0x9b0
+ 0x9b4 0x9b8 0x9bc 0x9c0 0x9c4 0x9c8>;
+ ds-settings = <0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0xcccc1111
+ 0xcccc1111 0x00000110>;
+ max-clk-nominal = <400000000>;
+ max-clk-turbo = <432000000>;
+ };
+
+ qcom,vfe {
+ compatible = "qcom,vfe";
+ num_child = <2>;
+ };
+
+ qcom,cam_smmu {
+ status = "ok";
+ compatible = "qcom,msm-cam-smmu";
+ msm_cam_smmu_cb1: msm_cam_smmu_cb1 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_iommu 0x400 0x00>,
+ <&apps_iommu 0x2400 0x00>;
+ iommu-cells = <2>;
+ qcom,iommu-dma-addr-pool = <0x10000000 0x70000000>;
+ label = "vfe";
+ qcom,scratch-buf-support;
+ };
+
+ msm_cam_smmu_cb3: msm_cam_smmu_cb3 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_iommu 0x1c00 0x00>;
+ iommu-cells = <2>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0x78000000>;
+ label = "cpp";
+ };
+
+ msm_cam_smmu_cb4: msm_cam_smmu_cb4 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&apps_iommu 0x1800 0x00>;
+ iommu-cells = <2>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0x78000000>;
+ label = "jpeg_enc0";
+ };
+ };
+
+ qcom,jpeg@1b1c000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,jpeg";
+ reg = <0x1b1c000 0x400>,
+ <0x1b60000 0xc30>;
+ reg-names = "jpeg_hw", "jpeg_vbif";
+ interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "jpeg";
+ vdd-supply = <&gdsc_jpeg>;
+ qcom,vdd-names = "vdd";
+ clock-names = "core_clk", "iface_clk", "bus_clk0",
+ "camss_top_ahb_clk", "camss_ahb_clk";
+ clocks = <&gcc GCC_CAMSS_JPEG0_CLK>,
+ <&gcc GCC_CAMSS_JPEG_AHB_CLK>,
+ <&gcc GCC_CAMSS_JPEG_AXI_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ qcom,clock-rates = <266670000 0 0 0 0>;
+ qcom,qos-reg-settings = <0x28 0x0000555e>,
+ <0xc8 0x00005555>;
+ qcom,msm-bus,name = "msm_camera_jpeg0";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <62 512 0 0>,
+ <62 512 800000 800000>;
+ qcom,vbif-reg-settings = <0xc0 0x10101000>,
+ <0xb0 0x10100010>;
+ };
+
+ qcom,cpp@1b04000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,cpp";
+ reg = <0x1b04000 0x100>,
+ <0x1b80000 0x200>,
+ <0x1b18000 0x018>,
+ <0x1858078 0x4>;
+ reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp";
+ interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpp";
+ vdd-supply = <&gdsc_cpp>;
+ qcom,vdd-names = "vdd";
+ clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc CPP_CLK_SRC>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>,
+ <&gcc GCC_CAMSS_CPP_AHB_CLK>,
+ <&gcc GCC_CAMSS_CPP_AXI_CLK>,
+ <&gcc GCC_CAMSS_CPP_CLK>,
+ <&gcc GCC_CAMSS_MICRO_AHB_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>;
+ clock-names = "ispif_ahb_clk", "cpp_core_clk",
+ "camss_top_ahb_clk", "camss_vfe_cpp_ahb_clk",
+ "camss_vfe_cpp_axi_clk", "camss_vfe_cpp_clk",
+ "micro_iface_clk", "camss_ahb_clk";
+ qcom,clock-rates = <61540000 180000000 0 0 0 180000000 0 0>;
+ qcom,min-clock-rate = <133000000>;
+ resets = <&gcc GCC_CAMSS_MICRO_BCR>;
+ reset-names = "micro_iface_reset";
+ qcom,bus-master = <1>;
+ qcom,msm-bus,name = "msm_camera_cpp";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <106 512 0 0>,
+ <106 512 0 0>;
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,micro-reset;
+ qcom,src-clock-rates = <133333333 160000000 200000000
+ 266666667 308570000 320000000 360000000>;
+ qcom,cpp-fw-payload-info {
+ qcom,stripe-base = <156>;
+ qcom,plane-base = <141>;
+ qcom,stripe-size = <27>;
+ qcom,plane-size = <5>;
+ qcom,fe-ptr-off = <5>;
+ qcom,we-ptr-off = <11>;
+ };
+ };
+
+ cci: qcom,cci@1b0c000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,cci";
+ reg = <0x1b0c000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "cci";
+ interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cci";
+ clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
+ <&gcc CCI_CLK_SRC>,
+ <&gcc GCC_CAMSS_CCI_AHB_CLK>,
+ <&gcc GCC_CAMSS_CCI_CLK>,
+ <&gcc GCC_CAMSS_AHB_CLK>,
+ <&gcc GCC_CAMSS_TOP_AHB_CLK>;
+ clock-names = "ispif_ahb_clk", "cci_src_clk",
+ "cci_ahb_clk", "camss_cci_clk",
+ "camss_ahb_clk", "camss_top_ahb_clk";
+ qcom,clock-rates = <61540000 19200000 0 0 0 0>,
+ <61540000 37500000 0 0 0 0>;
+ pinctrl-names = "cci_default", "cci_suspend";
+ pinctrl-0 = <&cci0_active &cci1_active>;
+ pinctrl-1 = <&cci0_suspend &cci1_suspend>;
+ gpios = <&tlmm 29 0>,
+ <&tlmm 30 0>,
+ <&tlmm 31 0>,
+ <&tlmm 32 0>;
+ qcom,gpio-tbl-num = <0 1 2 3>;
+ qcom,gpio-tbl-flags = <1 1 1 1>;
+ qcom,gpio-tbl-label = "CCI_I2C_DATA0",
+ "CCI_I2C_CLK0",
+ "CCI_I2C_DATA1",
+ "CCI_I2C_CLK1";
+ i2c_freq_100Khz: qcom,i2c_standard_mode {
+ status = "disabled";
+ };
+
+ i2c_freq_400Khz: qcom,i2c_fast_mode {
+ status = "disabled";
+ };
+
+ i2c_freq_custom: qcom,i2c_custom_mode {
+ status = "disabled";
+ };
+
+ i2c_freq_1Mhz: qcom,i2c_fast_plus_mode {
+ status = "disabled";
+ };
+ };
+};
+
+&i2c_freq_100Khz {
+ qcom,hw-thigh = <78>;
+ qcom,hw-tlow = <114>;
+ qcom,hw-tsu-sto = <28>;
+ qcom,hw-tsu-sta = <28>;
+ qcom,hw-thd-dat = <10>;
+ qcom,hw-thd-sta = <77>;
+ qcom,hw-tbuf = <118>;
+ qcom,hw-scl-stretch-en = <0>;
+ qcom,hw-trdhld = <6>;
+ qcom,hw-tsp = <1>;
+};
+
+&i2c_freq_400Khz {
+ qcom,hw-thigh = <20>;
+ qcom,hw-tlow = <28>;
+ qcom,hw-tsu-sto = <21>;
+ qcom,hw-tsu-sta = <21>;
+ qcom,hw-thd-dat = <13>;
+ qcom,hw-thd-sta = <18>;
+ qcom,hw-tbuf = <32>;
+ qcom,hw-scl-stretch-en = <0>;
+ qcom,hw-trdhld = <6>;
+ qcom,hw-tsp = <3>;
+ status = "ok";
+};
+
+&i2c_freq_custom {
+ qcom,hw-thigh = <15>;
+ qcom,hw-tlow = <28>;
+ qcom,hw-tsu-sto = <21>;
+ qcom,hw-tsu-sta = <21>;
+ qcom,hw-thd-dat = <13>;
+ qcom,hw-thd-sta = <18>;
+ qcom,hw-tbuf = <25>;
+ qcom,hw-scl-stretch-en = <1>;
+ qcom,hw-trdhld = <6>;
+ qcom,hw-tsp = <3>;
+ status = "ok";
+};
+
+&i2c_freq_1Mhz {
+ qcom,hw-thigh = <16>;
+ qcom,hw-tlow = <22>;
+ qcom,hw-tsu-sto = <17>;
+ qcom,hw-tsu-sta = <18>;
+ qcom,hw-thd-dat = <16>;
+ qcom,hw-thd-sta = <15>;
+ qcom,hw-tbuf = <19>;
+ qcom,hw-scl-stretch-en = <1>;
+ qcom,hw-trdhld = <3>;
+ qcom,hw-tsp = <3>;
+ qcom,cci-clk-src = <37500000>;
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-pm8916.dtsi b/arch/arm64/boot/dts/vendor/qcom/qm215-pm8916.dtsi
new file mode 100755
index 0000000..9011107
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qm215-pm8916.dtsi
@@ -0,0 +1,588 @@
+/* delete PMIC specific nodes */
+&soc {
+ /* delete rpm-smd base node to delete all regulator in one shot */
+ /delete-node/ qcom,rpm-smd;
+
+ /* add rpm-smd node again */
+ rpm_bus: qcom,rpm-smd {
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ compatible = "qcom,rpm-smd";
+ rpm-channel-name = "rpm_requests";
+ rpm-channel-type = <15>; /* SMD_APPS_RPM */
+ };
+
+ /* delete all pmic nodes */
+ qcom,spmi@200f000 {
+ /delete-node/ qcom,pm8937@0;
+ /delete-node/ qcom,pm8937@1;
+ };
+};
+
+/* delete all node referring PM8937 */
+&soc {
+ thermal-zones {
+ /delete-node/ pa-therm1-adc;
+ /delete-node/ xo-therm-adc;
+ /delete-node/ xo-therm-buf-adc;
+ /delete-node/ case-therm-adc;
+ /delete-node/ pa-therm0-adc;
+ /delete-node/ pm8937_tz;
+
+ aoss0-lowf {
+ cooling-maps {
+ cx_vdd_cdev {
+ /delete-property/ cooling-device;
+ };
+ };
+ };
+ };
+
+ qcom,gcc@1800000 {
+ /delete-property/ vdd_cx-supply;
+ /delete-property/ vdd_hf_dig-supply;
+ /delete-property/ vdd_hf_pll-supply;
+ };
+
+ usb@78db000 {
+ /delete-property/ hsusb_vdd_dig-supply;
+ /delete-property/ HSUSB_1p8-supply;
+ /delete-property/ HSUSB_3p3-supply;
+ /delete-property/ vbus_otg-supply;
+ };
+
+ qcom,mss@4080000 {
+ /delete-property/ vdd_mss-supply;
+ /delete-property/ vdd_cx-supply;
+ /delete-property/ vdd_mx-supply;
+ /delete-property/ vdd_pll-supply;
+ vdd_mss-supply = <&pm8916_s1_level>;
+ vdd_cx-supply = <&pm8916_s1_level>;
+ vdd_mx-supply = <&pm8916_l2_level_ao>;
+ vdd_pll-supply = <&pm8916_l7>;
+ };
+
+ qcom,lpass@c200000 {
+ /delete-property/ vdd_cx-supply;
+ vdd_cx-supply = <&pm8916_s1_level>;
+ };
+
+ qcom,pronto@a21b000 {
+ /delete-property/ vdd_pronto_pll-supply;
+ vdd_pronto_pll-supply = <&pm8916_l7>;
+ };
+
+ qcom,wcnss-wlan@a000000 {
+ /delete-property/ qcom,has-vsys-adc-channel;
+ qcom,wcnss-adc_tm = <&pm8916_adc_tm>;
+ qcom,pronto-vddmx-supply = <&pm8916_l2_level_ao>;
+ qcom,pronto-vddcx-supply = <&pm8916_s1_level>;
+ qcom,pronto-vddpx-supply = <&pm8916_l7>;
+ qcom,iris-vddxo-supply = <&pm8916_l7>;
+ qcom,iris-vddrfa-supply = <&pm8916_l3>;
+ qcom,iris-vddpa-supply = <&pm8916_l9>;
+ qcom,iris-vdddig-supply = <&pm8916_l7>;
+
+ qcom,iris-vddxo-voltage-level = <1800000 0 1800000>;
+ qcom,iris-vddrfa-voltage-level = <1325000 0 1325000>;
+ qcom,iris-vddpa-voltage-level = <3300000 0 3300000>;
+ qcom,iris-vdddig-voltage-level = <1800000 0 1800000>;
+
+ qcom,vddmx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_NOM
+ RPM_SMD_REGULATOR_LEVEL_NONE
+ RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,vddcx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_NOM
+ RPM_SMD_REGULATOR_LEVEL_NONE
+ RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,vddpx-voltage-level = <1800000 0 1800000>;
+
+ qcom,iris-vddxo-current = <10000>;
+ qcom,iris-vddrfa-current = <100000>;
+ qcom,iris-vddpa-current = <515000>;
+ qcom,iris-vdddig-current = <10000>;
+
+ qcom,pronto-vddmx-current = <0>;
+ qcom,pronto-vddcx-current = <0>;
+ qcom,pronto-vddpx-current = <0>;
+ };
+
+ /* mem_acc */
+ /delete-node/ regulator@01946004;
+ /* apc vreg */
+ /delete-node/ regulator@b018000;
+ /delete-node/ eldo2;
+ /delete-node/ adv_vreg;
+};
+
+#include "pm8916-rpm-regulator.dtsi"
+#include "pm8916.dtsi"
+#include "qm215-regulator.dtsi"
+
+&spmi_bus {
+ pm8916@1 {
+ /delete-node/ msm8x16_wcd_codec@f000;
+ };
+};
+
+&pm8916_gpios {
+ disp_vdda_en_default: disp_vdda_en_default {
+ pins = "gpio3";
+ function = "normal";
+ power-source = <0>;
+ drive-strength = <8>;
+ output-high;
+ };
+};
+
+&soc {
+ disp_vdda_eldo1: gpio-regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0x00 0x00>;
+ regulator-name = "disp_vdda_eldo1";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-enable-ramp-delay = <135>;
+ enable-active-high;
+ gpio = <&pm8916_gpios 3 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&disp_vdda_en_default>;
+ vin-supply = <&pm8916_s3>;
+ };
+};
+
+&mdss_dsi0_pll {
+ vddio-supply = <&pm8916_l6>;
+};
+
+&mdss_dsi0 {
+ /delete-property/ vdd-supply;
+ vddio-supply = <&pm8916_l6>;
+};
+
+&mdss_dsi {
+ vdda-supply = <&pm8916_l6>;
+ vddio-supply = <&pm8916_l6>;
+
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1744000>;
+ qcom,supply-max-voltage = <1904000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+ };
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda";
+ qcom,supply-min-voltage = <1744000>;
+ qcom,supply-max-voltage = <1904000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+ };
+};
+
+&gcc {
+ vdd_cx-supply = <&pm8916_s1_level>;
+ vdd_hf_dig-supply = <&pm8916_s1_level_ao>;
+ vdd_hf_pll-supply = <&pm8916_l7_ao>;
+};
+
+&pm8916_vadc {
+ #thermal-sensor-cells = <1>;
+ usb_in {
+ reg = <VADC_USBIN>;
+ label = "usb_in";
+ qcom,pre-scaling = <1 10>;
+ };
+
+ ireg_fb {
+ reg = <VADC_VCHG_SNS>;
+ label = "ireg_fb";
+ qcom,pre-scaling = <10 81>;
+ };
+
+ vcoin {
+ reg = <VADC_VCOIN>;
+ label = "vcoin";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vbat_sns {
+ reg = <VADC_VBAT_SNS>;
+ label = "vbat_sns";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ vph_pwr {
+ reg = <VADC_VSYS>;
+ label = "vph_pwr";
+ qcom,pre-scaling = <1 3>;
+ };
+
+ chg_temp {
+ reg = <VADC_CHG_TEMP>;
+ label = "chg_temp";
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_therm {
+ reg = <VADC_P_MUX2_1_1>;
+ label = "skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ batt_therm {
+ reg = <VADC_LR_MUX1_BAT_THERM>;
+ label = "batt_therm";
+ qcom,calibration-type = "ratiometric";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <2000>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ batt_id {
+ reg = <VADC_LR_MUX2_BAT_ID>;
+ label = "batt_id";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <2000>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm0 {
+ reg = <VADC_LR_MUX7_HW_ID>;
+ label = "pa_therm0";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm {
+ reg = <VADC_LR_MUX3_XO_THERM>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm_buf {
+ reg = <VADC_LR_MUX3_BUF_XO_THERM>;
+ label = "xo_therm_buf";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8916_adc_tm_iio {
+ io-channels = <&pm8916_vadc VADC_LR_MUX3_BUF_XO_THERM>,
+ <&pm8916_vadc VADC_LR_MUX3_XO_THERM>,
+ <&pm8916_vadc VADC_LR_MUX7_HW_ID>,
+ <&pm8916_vadc VADC_P_MUX2_1_1>;
+ io-channel-names = "xo_therm_buf", "xo_therm", "pa_therm0",
+ "skin_therm";
+
+ pa_therm0 {
+ reg = <VADC_LR_MUX7_HW_ID>;
+ label = "pa_therm0";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm {
+ reg = <VADC_LR_MUX3_XO_THERM>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ xo_therm_buf {
+ reg = <VADC_LR_MUX3_BUF_XO_THERM>;
+ label = "xo_therm_buf";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_therm {
+ reg = <VADC_P_MUX2_1_1>;
+ label = "skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm8916_adc_tm {
+ /* Channel Nodes */
+ batt_therm {
+ reg = <VADC_LR_MUX1_BAT_THERM>;
+ label = "batt_therm";
+ io-channels = <&pm8916_vadc VADC_LR_MUX1_BAT_THERM>;
+ io-channel-names = "batt_therm";
+ qcom,pre-div-channel-scaling = <0>;
+ qcom,decimation = <0>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <0xb>;
+ qcom,scale-fn-type = <8>;
+ qcom,fast-avg-setup = <0x2>;
+ qcom,btm-channel-number = <0x48>;
+ };
+
+ vbat_sns {
+ reg = <VADC_VBAT_SNS>;
+ label = "vbat_sns";
+ io-channels = <&pm8916_vadc VADC_VBAT_SNS>;
+ io-channel-names = "vbat_sns";
+ qcom,pre-div-channel-scaling = <1>;
+ qcom,decimation = <0>;
+ qcom,hw-settle-time = <0xb>;
+ qcom,scale-fn-type = <0>;
+ qcom,fast-avg-setup = <0x2>;
+ qcom,btm-channel-number = <0x68>;
+ };
+};
+
+&soc {
+ thermal-zones {
+ xo-therm-buf-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8916_adc_tm_iio
+ VADC_LR_MUX3_BUF_XO_THERM>;
+ thermal-governor = "user_space";
+
+ trips {
+ active-config0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8916_adc_tm_iio
+ VADC_LR_MUX3_XO_THERM>;
+ thermal-governor = "user_space";
+
+ trips {
+ active-config0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa-therm0-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8916_adc_tm_iio
+ VADC_LR_MUX7_HW_ID>;
+ thermal-governor = "user_space";
+
+ trips {
+ active-config0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ skin-therm-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8916_adc_tm_iio
+ VADC_P_MUX2_1_1>;
+ thermal-governor = "user_space";
+
+ trips {
+ active-config0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ aoss0-lowf {
+ cooling-maps {
+ cx_vdd_cdev {
+ cooling-device = <&pm8916_cx_cdev 0 0>;
+ };
+ };
+ };
+
+ pm8916_tz {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm8916_tz>;
+
+ trips {
+ pm8916_trip0: pm8916-trip0 {
+ temperature = <105000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm8916_trip1: pm8916-trip1 {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ pm8916_trip2: pm8916-trip2 {
+ temperature = <145000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-step {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&pm8916_adc_tm_iio
+ VADC_LR_MUX3_XO_THERM>;
+ thermal-governor = "step_wise";
+
+ trips {
+ qm215_batt_trip0: qm215-batt-trip0 {
+ temperature = <41000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ qm215_modem_trip0: qm215-modem-trip0 {
+ temperature = <44000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ qm215_batt_trip1: qm215-batt-trip1 {
+ temperature = <45000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ qm215_modem_trip1: qm215-modem-trip1 {
+ temperature = <46000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ qm215_cpu_trip: qm215-cpu-trip {
+ temperature = <48000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ qm215_gpu_trip: qm215-gpu-trip {
+ temperature = <50000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ qm215_modem_trip2: qm215-modem-trip2 {
+ temperature = <60000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ skin_cpu0 {
+ trip = <&qm215_cpu_trip>;
+ /* throttle from fmax to 1094400KHz */
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ skin_cpu1 {
+ trip = <&qm215_cpu_trip>;
+ cooling-device = <&CPU1 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ skin_cpu2 {
+ trip = <&qm215_cpu_trip>;
+ cooling-device = <&CPU2 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ skin_cpu3 {
+ trip = <&qm215_cpu_trip>;
+ cooling-device = <&CPU3 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ skin_gpu {
+ trip = <&qm215_gpu_trip>;
+ /* throttle from fmax to 400000000Hz */
+ cooling-device = <&msm_gpu
+ THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem_lvl1 {
+ trip = <&qm215_modem_trip0>;
+ cooling-device = <&modem_pa 1 1>;
+ };
+
+ modem_lvl2 {
+ trip = <&qm215_modem_trip1>;
+ cooling-device = <&modem_pa 2 2>;
+ };
+
+ modem_lvl3 {
+ trip = <&qm215_modem_trip2>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ battery_lvl1 {
+ trip = <&qm215_batt_trip0>;
+ cooling-device = <&pm8916_chg 1 1>;
+ };
+
+ battery_lvl2 {
+ trip = <&qm215_batt_trip1>;
+ cooling-device = <&pm8916_chg 2 2>;
+ };
+ };
+ };
+ };
+};
+
+&soc {
+ usb_vdig_supply: usb_vdig_supply {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_vdig_supply";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+};
+
+&usb_otg {
+ hsusb_vdd_dig-supply = <&usb_vdig_supply>;
+ HSUSB_1p8-supply = <&pm8916_l7>;
+ HSUSB_3p3-supply = <&pm8916_l13>;
+ extcon = <&pm8916_chg>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-qrd-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/qm215-qrd-overlay.dts
new file mode 100755
index 0000000..6927ecf
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qm215-qrd-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+#include "qm215-qrd.dtsi"
+
+/ {
+ model = "QRD";
+ qcom,board-id = <0x01000b 4>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-qrd-smb1360-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/qm215-qrd-smb1360-overlay.dts
new file mode 100755
index 0000000..a42539a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qm215-qrd-smb1360-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+#include "qm215-qrd-smb1360.dtsi"
+
+/ {
+ model = "QRD + SMB1360";
+ qcom,board-id = <0x0b 5>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-qrd-smb1360.dts b/arch/arm64/boot/dts/vendor/qcom/qm215-qrd-smb1360.dts
new file mode 100755
index 0000000..b2e9e15
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qm215-qrd-smb1360.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "qm215.dtsi"
+#include "qm215-pm8916.dtsi"
+#include "qm215-qrd-smb1360.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. qm215 SMB1360 QRD";
+ compatible = "qcom,qm215-qrd", "qcom,qm215", "qcom,qrd";
+ qcom,board-id = <0x0b 5>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-qrd-smb1360.dtsi b/arch/arm64/boot/dts/vendor/qcom/qm215-qrd-smb1360.dtsi
new file mode 100755
index 0000000..9756870
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qm215-qrd-smb1360.dtsi
@@ -0,0 +1,83 @@
+#include "qm215-qrd.dtsi"
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&pm8916_chg {
+ qcom,use-external-charger;
+};
+
+&pm8916_bms {
+ qcom,disable-bms;
+};
+
+&tlmm {
+ /* SMB interrupt pin */
+ smb_int_pin {
+ smb_int_default: smb_int_default {
+ mux {
+ pins = "gpio13";
+ function ="gpio";
+ };
+
+ config {
+ pins = "gpio13";
+ bias-pull-up; /* PULL UP*/
+ input-enable;
+ };
+ };
+ };
+};
+
+&pm8916_gpios {
+ usb_id {
+ usb_id_default: usb_id_default {
+ pins = "gpio4";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+ };
+};
+
+&i2c_2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status ="ok";
+ smb1360_otg_supply: smb1360-chg-fg@14 {
+ compatible = "qcom,smb1360-chg-fg";
+ reg = <0x14>;
+ interrupts-extended = <&tlmm 13 8>,
+ <&spmi_bus 0 0xc3 0 3>;
+ interrupt-names = "smb1360_stat_irq",
+ "smb1360_usb_id_irq";
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_int_default>,
+ <&usb_id_default>;
+ qcom,empty-soc-disabled;
+ qcom,chg-inhibit-disabled;
+ qcom,float-voltage-mv = <4400>;
+ qcom,iterm-ma = <100>;
+ qcom,recharge-thresh-mv = <100>;
+ qcom,thermal-mitigation = <1500 700 600 0>;
+ qcom,fg-batt-capacity-mah = <2800>;
+ qcom,fg-cutoff-voltage-mv = <3400>;
+ qcom,fg-iterm-ma = <130>;
+ qcom,fg-delta-soc = <1>;
+ qcom,usb-id-gpio = <&pm8916_gpios 4 0>;
+ qcom,soft-jeita-supported;
+ qcom,warm-bat-decidegc = <450>;
+ qcom,cool-bat-decidegc = <150>;
+ qcom,warm-bat-mv = <4200>;
+ qcom,cool-bat-mv = <4200>;
+ qcom,warm-bat-ma = <1000>;
+ qcom,cool-bat-ma = <1000>;
+ io-channels = <&pm8916_vadc VADC_LR_MUX2_BAT_ID>;
+ io-channel-names = "batt_id";
+ status= "okay";
+ };
+};
+
+&usb_otg {
+ extcon = <&smb1360_otg_supply>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/qm215-qrd.dts
new file mode 100755
index 0000000..b8f63e4
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qm215-qrd.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+#include "qm215.dtsi"
+#include "qm215-pm8916.dtsi"
+#include "qm215-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. qm215 QRD";
+ compatible = "qcom,qm215-qrd", "qcom,qm215", "qcom,qrd";
+ qcom,board-id = <0x01000b 4>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/qm215-qrd.dtsi
new file mode 100755
index 0000000..5691040
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qm215-qrd.dtsi
@@ -0,0 +1,250 @@
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+
+&blsp1_uart2 {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart_console_active>;
+};
+
+#include <dt-bindings/clock/qcom,gcc-sdm429w.h>
+#include "qm215-camera-sensor-qrd.dtsi"
+
+&pm8916_chg {
+ status = "ok";
+ qcom,chgr-led-support;
+ qcom,vddmax-mv = <4400>;
+ qcom,vddsafe-mv = <4400>;
+ qcom,batt-hot-percentage = <35>;
+};
+
+&pm8916_bms {
+ status = "ok";
+ qcom,battery-data = <&qrd_batterydata>;
+ qcom,batt-aging-comp;
+ qcom,resume-soc = <99>;
+};
+
+&pm8916_vib {
+ status = "ok";
+};
+
+&pm8916_vadc {
+ batt_therm {
+ qcom,scale-fn-type = <ADC_SCALE_BATT_THERM_QRD_215>;
+ };
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_key_active>;
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&tlmm 91 0x1>;
+ linux,input-type = <1>;
+ linux,code = <115>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+ };
+
+ fpc1020 {
+ compatible = "fpc,fpc1020";
+ interrupt-parent = <&tlmm>;
+ interrupts = <48 0>;
+ fpc,gpio_rst = <&tlmm 124 0x0>;
+ fpc,gpio_irq = <&tlmm 48 0>;
+ vcc_spi-supply = <&pm8916_l5>;
+ vdd_io-supply = <&pm8916_l5>;
+ vdd_ana-supply = <&pm8916_l5>;
+ fpc,enable-on-boot;
+ pinctrl-names = "fpc1020_reset_reset",
+ "fpc1020_reset_active",
+ "fpc1020_irq_active";
+ pinctrl-0 = <&fpc_reset_low>;
+ pinctrl-1 = <&fpc_reset_high>;
+ pinctrl-2 = <&fpc_int_low>;
+ };
+};
+
+&sdhc_1 {
+ /* device core power supply */
+ vdd-supply = <&pm8916_l8>;
+ qcom,vdd-voltage-level = <2900000 2900000>;
+ qcom,vdd-current-level = <200 400000>;
+
+ /*
+ * device communication power is an external
+ * regulator eLDO3, which is enabled via L5A
+ */
+ vdd-io-supply = <&pm8916_l5>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <200 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000
+ 384000000>;
+ qcom,nonremovable;
+ qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ /* device core power supply */
+ vdd-supply = <&pm8916_l11>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <15000 800000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm8916_l12>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
+
+ cd-gpios = <&tlmm 67 0x0>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
+ 200000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
+ status = "ok";
+};
+
+&mdss_dsi_active {
+ mux {
+ pins = "gpio60", "gpio93", "gpio94";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio60", "gpio93", "gpio94";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable = <0>; /* no pull */
+ output-high;
+ };
+};
+
+&mdss_dsi_suspend {
+ mux {
+ pins = "gpio60", "gpio93", "gpio94";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio60", "gpio93", "gpio94";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* pull down */
+ };
+};
+
+#include "msm8937-mdss-panels.dtsi"
+
+&mdss_mdp {
+ qcom,mdss-pref-prim-intf = "dsi";
+};
+
+&dsi_panel_pwr_supply {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <1>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1744000>;
+ qcom,supply-max-voltage = <1904000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ /delete-node/ qcom,panel-supply-entry@1;
+ /delete-node/ qcom,panel-supply-entry@2;
+ /delete-node/ qcom,panel-supply-entry@3;
+};
+
+&pm8916_gpios {
+ nfc_clk {
+ nfc_clk_default: nfc_clk_default {
+ pins = "gpio2";
+ function = "normal";
+ input-enable;
+ power-source = <1>;
+ };
+ };
+};
+
+&i2c_5 { /* BLSP2 QUP1 (NFC) */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "ok";
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 17 0x00>;
+ qcom,nq-ven = <&tlmm 16 0x00>;
+ qcom,nq-firm = <&tlmm 130 0x00>;
+ qcom,nq-clkreq = <&pm8916_gpios 2 0x00>;
+ interrupt-parent = <&tlmm>;
+ qcom,clk-src = "BBCLK2";
+ interrupts = <17 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_disable_active
+ &nfc_clk_default>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_disable_suspend>;
+ clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>;
+ clock-names = "ref_clk";
+ };
+};
+
+&mdss_dsi {
+ hw-config = "single_dsi";
+};
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_hx8399c_hd_vid>;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+ pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+
+ qcom,platform-te-gpio = <&tlmm 24 0>;
+ qcom,platform-reset-gpio = <&tlmm 60 0>;
+ qcom,platform-bklight-en-gpio = <&tlmm 93 0>;
+ qcom,platform-enable-gpio = <&tlmm 94 0>;
+};
+
+&dsi_hx8399c_hd_vid {
+ qcom,mdss-dsi-panel-timings =
+ [e7 1c 12 00 42 42 18 20 17 03 04 00];
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8916_mpps 4 0>;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-status-read-length = <4>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ qcom,mdss-dsi-min-refresh-rate = <48>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update =
+ "dfps_immediate_porch_mode_vfp";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/qm215-regulator.dtsi
new file mode 100755
index 0000000..834859d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qm215-regulator.dtsi
@@ -0,0 +1,552 @@
+/* RPM controlled regulators */
+
+&rpm_bus {
+ /* PM8916 S1 VDD_CX supply */
+ rpm-regulator-smpa1 {
+ status = "okay";
+ pm8916_s1_level: regulator-s1-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_s1_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ pm8916_s1_level_ao: regulator-s1-level-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_s1_level_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ pm8916_s1_floor_level: regulator-s1-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_s1_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+
+ pm8916_cx_cdev: regulator-cx-cdev {
+ compatible = "qcom,regulator-cooling-device";
+ regulator-cdev-supply = <&pm8916_s1_floor_level>;
+ regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NOM_PLUS
+ RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ rpm-regulator-smpa3 {
+ status = "okay";
+ pm8916_s3: regulator-s3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1448000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpa4 {
+ status = "okay";
+ pm8916_s4: regulator-s4 {
+ regulator-min-microvolt = <1992000>;
+ regulator-max-microvolt = <2160000>;
+ qcom,init-voltage = <1992000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa1 {
+ status = "okay";
+ pm8916_l1: regulator-l1 {
+ regulator-min-microvolt = <968000>;
+ regulator-max-microvolt = <1152000>;
+ qcom,init-voltage = <968000>;
+ status = "okay";
+ };
+ };
+
+ /* PM8916 L2 VDD_MX supply */
+ rpm-regulator-ldoa2 {
+ status = "okay";
+ pm8916_l2: regulator-l2 {
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1088000>;
+ status = "okay";
+ };
+
+ pm8916_l2_level_ao: regulator-l2-level-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l2_level_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ };
+
+ pm8916_l2_level_so: regulator-l2-level-so {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l2_level_so";
+ qcom,set = <2>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ qcom,init-voltage-level =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ };
+ };
+
+ rpm-regulator-ldoa3 {
+ status = "okay";
+ pm8916_l3: regulator-l3 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1384000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa4 {
+ status = "okay";
+ pm8916_l4: regulator-l4 {
+ regulator-min-microvolt = <1744000>;
+ regulator-max-microvolt = <1896000>;
+ qcom,init-voltage = <1744000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa5 {
+ status = "okay";
+ pm8916_l5: regulator-l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa6 {
+ status = "okay";
+ pm8916_l6: regulator-l6 {
+ regulator-min-microvolt = <1744000>;
+ regulator-max-microvolt = <1904000>;
+ qcom,init-voltage = <1744000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa7 {
+ status = "okay";
+ pm8916_l7: regulator-l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1904000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+
+ pm8916_l7_ao: regulator-l7-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l7_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1904000>;
+ qcom,init-voltage = <1800000>;
+ };
+
+ pm8916_l7_so: regulator-l7-so {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "8916_l7_so";
+ qcom,set = <2>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1904000>;
+ qcom,init-enable = <0>;
+ };
+ };
+
+ rpm-regulator-ldoa8 {
+ status = "okay";
+ pm8916_l8: regulator-l8 {
+ regulator-min-microvolt = <2696000>;
+ regulator-max-microvolt = <3600000>;
+ qcom,init-voltage = <2696000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa9 {
+ status = "okay";
+ pm8916_l9: regulator-l9 {
+ regulator-min-microvolt = <2904000>;
+ regulator-max-microvolt = <3376000>;
+ qcom,init-voltage = <2904000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa10 {
+ status = "okay";
+ pm8916_l10: regulator-l10 {
+ regulator-min-microvolt = <2704000>;
+ regulator-max-microvolt = <3000000>;
+ qcom,init-voltage = <2704000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa11 {
+ status = "okay";
+ pm8916_l11: regulator-l11 {
+ regulator-min-microvolt = <2696000>;
+ regulator-max-microvolt = <3600000>;
+ qcom,init-voltage = <2696000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa12 {
+ status = "okay";
+ pm8916_l12: regulator-l12 {
+ regulator-min-microvolt = <1648000>;
+ regulator-max-microvolt = <3104000>;
+ qcom,init-voltage = <1648000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa13 {
+ status = "okay";
+ pm8916_l13: regulator-l13 {
+ regulator-min-microvolt = <2968000>;
+ regulator-max-microvolt = <3080000>;
+ qcom,init-voltage = <2968000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa14 {
+ status = "okay";
+ pm8916_l14: regulator-l14 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3056000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa15 {
+ status = "okay";
+ pm8916_l15: regulator-l15 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3056000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa16 {
+ status = "okay";
+ pm8916_l16: regulator-l16 {
+ regulator-min-microvolt = <2696000>;
+ regulator-max-microvolt = <2840000>;
+ qcom,init-voltage = <2696000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa17 {
+ status = "okay";
+ pm8916_l17: regulator-l17 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <3000000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa18 {
+ status = "okay";
+ pm8916_l18: regulator-l18 {
+ regulator-min-microvolt = <2600000>;
+ regulator-max-microvolt = <2800000>;
+ qcom,init-voltage = <2600000>;
+ status = "okay";
+ };
+ };
+};
+
+/* SPM controlled regulators */
+&spmi_bus {
+ pm8916@1 {
+ pm8916_s2: spm-regulator@1700 {
+ compatible = "qcom,spm-regulator";
+ regulator-name = "8916_s2";
+ reg = <0x1700 0x100>;
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1350000>;
+ };
+ };
+};
+
+/* CPR controlled regulator */
+
+&soc {
+ mem_acc_vreg_corner: regulator@01946004 {
+ compatible = "qcom,mem-acc-regulator";
+ reg = <0xa4000 0x1000>;
+ reg-names = "efuse_addr";
+ regulator-name = "mem_acc_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <3>;
+
+ qcom,acc-reg-addr-list =
+ <0x01942138 0x01942130 0x01942120 0x01942124>;
+
+ qcom,acc-init-reg-config = <1 0xff>, <2 0x5555>;
+
+ qcom,num-acc-corners = <3>;
+ qcom,boot-acc-corner = <2>;
+ qcom,corner1-reg-config =
+ /* SVS+ => SVS+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => TURBO/NOM+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x0>,
+ < 4 0x0>;
+
+ qcom,corner2-reg-config =
+ /* NOM => SVS+ */
+ < 3 0x30c30c3>, < 4 0x30c3>,
+ /* NOM => NOM */
+ <(-1) (-1)>, <(-1) (-1)>,
+ /* NOM => TURBO/NOM+ */
+ < 3 0x0>, < 4 0x0>;
+
+ qcom,corner3-reg-config =
+ /* TURBO/NOM+ => SVS+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>,
+ < 4 0x30c3>,
+ /* TURBO/NOM+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* TURBO/NOM+ => TURBO/NOM+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>;
+
+ qcom,override-acc-fuse-sel = <71 17 3 0>;
+ qcom,override-fuse-version-map = <1>,
+ <2>,
+ <3>,
+ <4>;
+ qcom,override-corner1-addr-val-map =
+ /* 1st fuse version tuple matched */
+ /* SVS+ => SVS+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => TURBO/NOM+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x1>,
+ < 4 0x0>,
+
+ /* 2nd fuse version tuple matched */
+ /* SVS+ => SVS+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => TURBO/NOM+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x3>,
+ < 4 0x0>,
+
+ /* 3rd fuse version tuple matched */
+ /* SVS+ => SVS+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => NOM */
+ < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => TURBO/NOM+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x0>,
+ < 4 0x0>,
+
+ /* 4th fuse version tuple matched */
+ /* SVS+ => SVS+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => NOM */
+ < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* SVS+ => TURBO/NOM+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x1>,
+ < 4 0x0>;
+
+ qcom,override-corner2-addr-val-map =
+ /* 1st fuse version tuple matched */
+ /* NOM => SVS+ */
+ < 3 0x30c30c3>, < 4 0x30c3>,
+ /* NOM => NOM */
+ <(-1) (-1)>, <(-1) (-1)>,
+ /* NOM => TURBO/NOM+ */
+ < 3 0x1>, < 4 0x0>,
+
+ /* 2nd fuse version tuple matched */
+ /* NOM => SVS+ */
+ < 3 0x30c30c3>, < 4 0x30c3>,
+ /* NOM => NOM */
+ <(-1) (-1)>, <(-1) (-1)>,
+ /* NOM => TURBO/NOM+ */
+ < 3 0x3>, < 4 0x0>,
+
+ /* 3rd fuse version tuple matched */
+ /* NOM => SVS+ */
+ < 3 0x30c30c3>, < 4 0x30c3>,
+ /* NOM => NOM */
+ <(-1) (-1)>, <(-1) (-1)>,
+ /* NOM => TURBO/NOM+ */
+ < 3 0x0>, < 4 0x0>,
+
+ /* 4th fuse version tuple matched */
+ /* NOM => SVS+ */
+ < 3 0x30c30c3>, < 4 0x30c3>,
+ /* NOM => NOM */
+ <(-1) (-1)>, <(-1) (-1)>,
+ /* NOM => TURBO/NOM+ */
+ < 3 0x1>, < 4 0x0>;
+
+ qcom,override-corner3-addr-val-map =
+ /* 1st fuse version tuple matched */
+ /* TURBO/NOM+ => SVS+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>,
+ < 4 0x30c3>,
+ /* TURBO/NOM+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* TURBO/NOM+ => TURBO/NOM+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+
+ /* 2nd fuse version tuple matched */
+ /* TURBO/NOM+ => SVS+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>,
+ < 4 0x30c3>,
+ /* TURBO/NOM+ => NOM */
+ < 3 0x1041041>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* TURBO/NOM+ => TURBO/NOM+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+
+ /* 3rd fuse version tuple matched */
+ /* TURBO/NOM+ => SVS+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>,
+ < 4 0x30c3>,
+ /* TURBO/NOM+ => NOM */
+ < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* TURBO/NOM+ => TURBO/NOM+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>,
+
+ /* 4th fuse version tuple matched */
+ /* TURBO/NOM+ => SVS+ */
+ < 3 0x1041041>, < 4 0x1041>, < 3 0x30c30c3>,
+ < 4 0x30c3>,
+ /* TURBO/NOM+ => NOM */
+ < 3 0x1041043>, < 4 0x1041>, <(-1) (-1)>,
+ <(-1) (-1)>,
+ /* TURBO/NOM+ => TURBO/NOM+ */
+ <(-1) (-1)>, <(-1) (-1)>, <(-1) (-1)>,
+ <(-1) (-1)>;
+ };
+
+ apc_vreg_corner: regulator@b018000 {
+ compatible = "qcom,cpr-regulator";
+ reg = <0xb018000 0x1000>, <0xb011064 0x4>, <0xa4000 0x1000>;
+ reg-names = "rbcpr", "rbcpr_clk", "efuse_addr";
+ interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+ regulator-name = "apc_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <5>;
+
+ qcom,cpr-fuse-corners = <3>;
+ qcom,cpr-voltage-ceiling = <1155000 1225000 1350000>;
+ qcom,cpr-voltage-floor = <1050000 1050000 1090000>;
+ vdd-apc-supply = <&pm8916_s2>;
+
+ mem-acc-supply = <&mem_acc_vreg_corner>;
+
+ qcom,cpr-ref-clk = <19200>;
+ qcom,cpr-timer-delay = <5000>;
+ qcom,cpr-timer-cons-up = <0>;
+ qcom,cpr-timer-cons-down = <2>;
+ qcom,cpr-irq-line = <0>;
+ qcom,cpr-step-quotient = <26>;
+ qcom,cpr-up-threshold = <0>;
+ qcom,cpr-down-threshold = <2>;
+ qcom,cpr-idle-clocks = <15>;
+ qcom,cpr-gcnt-time = <1>;
+ qcom,vdd-apc-step-up-limit = <1>;
+ qcom,vdd-apc-step-down-limit = <1>;
+ qcom,cpr-apc-volt-step = <12500>;
+
+ qcom,cpr-fuse-row = <67 0>;
+ qcom,cpr-fuse-target-quot = <42 24 6>;
+ qcom,cpr-fuse-ro-sel = <60 57 54>;
+ qcom,cpr-init-voltage-ref = <1155000 1225000 1350000>;
+ qcom,cpr-fuse-init-voltage =
+ <67 36 6 0>,
+ <67 18 6 0>,
+ <67 0 6 0>;
+ qcom,cpr-fuse-quot-offset =
+ <71 26 6 0>,
+ <71 20 6 0>,
+ <70 54 7 0>;
+ qcom,cpr-fuse-quot-offset-scale = <5 5 5>;
+ qcom,cpr-init-voltage-step = <10000>;
+ qcom,cpr-corner-map = <1 2 3 3 3>;
+ qcom,cpr-corner-frequency-map =
+ <1 960000000>,
+ <2 1094400000>,
+ <3 1248000000>,
+ <4 1305600000>,
+ <5 1401000000>;
+ qcom,speed-bin-fuse-sel = <37 34 3 0>;
+ qcom,cpr-speed-bin-max-corners =
+ <0 (-1) 1 2 5>,
+ <3 (-1) 1 2 5>;
+ qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>;
+ qcom,cpr-voltage-scaling-factor-max = <0 2000 2000>;
+ qcom,cpr-scaled-init-voltage-as-ceiling;
+ qcom,cpr-fuse-revision = <69 39 3 0>;
+ qcom,pvs-version-fuse-sel = <37 40 3 0>; /* foundry */
+ qcom,cpr-fuse-version-map =
+ <(-1) 1 (-1) (-1) (-1) (-1)>,
+ <(-1) (-1) (-1) (-1) (-1) (-1)>;
+ qcom,cpr-quotient-adjustment =
+ <30 20 0>,
+ <50 40 50>;
+ qcom,cpr-init-voltage-adjustment =
+ <0 0 0>,
+ <30000 5000 10000>;
+ qcom,cpr-enable;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215.dts b/arch/arm64/boot/dts/vendor/qcom/qm215.dts
new file mode 100755
index 0000000..e6ddd75
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qm215.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "qm215.dtsi"
+#include "qm215-pm8916.dtsi"
+#include "qm215-audio.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QM215";
+ compatible = "qcom,qm215";
+ qcom,pmic-name = "PM8916";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qm215.dtsi b/arch/arm64/boot/dts/vendor/qcom/qm215.dtsi
new file mode 100755
index 0000000..3efe165
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qm215.dtsi
@@ -0,0 +1,257 @@
+#include "msm8917.dtsi"
+#include "qm215-camera.dtsi"
+/ {
+ model = "Qualcomm Technologies, Inc. QM215";
+ compatible = "qcom,qm215";
+ qcom,msm-id = <386 0x0>;
+ qcom,msm-name = "QM215";
+};
+
+/ {
+ qrd_batterydata: qcom,batterydata {
+ qcom,rpull-up-kohm = <100>;
+ qcom,vref-batt-therm = <1800000>;
+
+ #include "vbms-batterydata-mlp356477-2800mah.dtsi"
+ };
+};
+
+&soc {
+ qcom,vidc@1d00000 {
+ qcom,allowed-clock-rates = <329140000 329140000
+ 308570000 270000000 200000000>;
+ };
+};
+
+&gcc {
+ compatible = "qcom,gcc-qm215", "syscon";
+};
+
+&msm_cpufreq {
+ /delete-property/qcom,cpufreq-table;
+ qcom,cpufreq-table =
+ < 960000 >,
+ < 1094400 >,
+ < 1209600 >,
+ < 1248000 >,
+ < 1305600 >;
+};
+
+/* GPU overrides */
+&msm_gpu {
+
+ qcom,gpu-speed-bin = <0x0164 0x00000600 9>;
+ /delete-property/qcom,gpu-speed-bin-vectors;
+ /delete-node/qcom,gpu-pwrlevel-bins;
+
+ qcom,gpu-pwrlevel-bins {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible="qcom,gpu-pwrlevel-bins";
+
+ qcom,gpu-pwrlevels-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <0>;
+ qcom,initial-pwrlevel = <3>;
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <598000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <7>;
+ };
+
+ /* NOM+ */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <523200000>;
+ qcom,bus-freq = <6>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <484800000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <6>;
+ };
+
+ /* SVS+ */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <270000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <1>;
+ qcom,bus-max = <3>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <1>;
+ qcom,initial-pwrlevel = <2>;
+
+ /* NOM+ */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <500000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <6>;
+ qcom,bus-max = <7>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ };
+
+ /* SVS+ */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <270000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <1>;
+ qcom,bus-max = <3>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <2>;
+ qcom,initial-pwrlevel = <1>;
+
+ /* NOM */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <7>;
+ };
+
+ /* SVS+ */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <270000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <1>;
+ qcom,bus-max = <3>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <3>;
+ qcom,initial-pwrlevel = <0>;
+
+ /* SVS+ */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <6>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <270000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <1>;
+ qcom,bus-max = <3>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+ };
+};
+
+&thermal_zones {
+ gpu0-step {
+ trips {
+ gpu-step-trip {
+ temperature = <85000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qrb5165-iot-rb5.dts b/arch/arm64/boot/dts/vendor/qcom/qrb5165-iot-rb5.dts
new file mode 100755
index 0000000..2acccf6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qrb5165-iot-rb5.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "qrb5165.dtsi"
+#include "kona-v2.1-iot-rb5.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. qrb5165 IOT RB5";
+ compatible = "qcom,kona-iot", "qcom,kona", "qcom,iot";
+ qcom,board-id = <11 3>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qrb5165.dtsi b/arch/arm64/boot/dts/vendor/qcom/qrb5165.dtsi
new file mode 100755
index 0000000..e2089e0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qrb5165.dtsi
@@ -0,0 +1,768 @@
+
+#include "kona-v2.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. qrb5165";
+ compatible = "qcom,kona";
+ qcom,msm-id = <455 0x20001>;
+};
+
+#include "kona-v2.1-gpu.dtsi"
+
+&soc {
+ qcom-thermal-qfprom {
+ compatible = "qcom,thermal-qfprom-device";
+ nvmem-cells = <&thermal_speed_bin>;
+ nvmem-cell-names = "thermal_speed_bin";
+ qcom,thermal-qfprom-bit-values = <0x1>;
+ qcom,thermal-zone-enable-list = "gpuss-max-iot-step",
+ "cpu-0-0-iot-step",
+ "cpu-0-1-iot-step",
+ "cpu-0-2-iot-step",
+ "cpu-0-3-iot-step",
+ "cpu-1-0-iot-step",
+ "cpu-1-1-iot-step",
+ "cpu-1-2-iot-step",
+ "cpu-1-3-iot-step",
+ "cpu-1-4-iot-step",
+ "cpu-1-5-iot-step",
+ "cpu-1-6-iot-step",
+ "cpu-1-7-iot-step",
+ "cwlan-iot-step",
+ "video-iot-step",
+ "ddr-iot-step",
+ "q6-hvx-iot-step",
+ "camera-iot-step",
+ "cmpss-iot-step",
+ "npu-iot-step";
+ qcom,thermal-zone-disable-list = "gpuss-max-step",
+ "cpu-0-0-step",
+ "cpu-0-1-step",
+ "cpu-0-2-step",
+ "cpu-0-3-step",
+ "cpu-1-0-step",
+ "cpu-1-1-step",
+ "cpu-1-2-step",
+ "cpu-1-3-step",
+ "cpu-1-4-step",
+ "cpu-1-5-step",
+ "cpu-1-6-step",
+ "cpu-1-7-step",
+ "cwlan-step",
+ "video-step",
+ "ddr-step",
+ "q6-hvx-step",
+ "camera-step",
+ "cmpss-step",
+ "npu-step";
+ };
+};
+
+&thermal_zones {
+ gpuss-max-iot-step {
+ polling-delay-passive = <10>;
+ polling-delay = <100>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+
+ trips {
+ gpu_iot_trip0: gpu-trip0 {
+ temperature = <110000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ gpu_cdev {
+ trip = <&gpu_iot_trip0>;
+ cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ pop-mem-step {
+ status = "disabled";
+ };
+
+ cpu-0-0-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 1>;
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ cpu00_iot_config: cpu00-config {
+ temperature = <122000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu00_cdev {
+ trip = <&cpu00_iot_config>;
+ cooling-device = <&cpu0_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-1-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 2>;
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ cpu01_iot_config: cpu01-config {
+ temperature = <122000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu01_cdev {
+ trip = <&cpu01_iot_config>;
+ cooling-device = <&cpu1_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-2-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 3>;
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ cpu02_iot_config: cpu02-config {
+ temperature = <122000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu02_cdev {
+ trip = <&cpu02_iot_config>;
+ cooling-device = <&cpu2_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-0-3-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 4>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ cpu03_iot_config: cpu03-config {
+ temperature = <122000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu03_cdev {
+ trip = <&cpu03_iot_config>;
+ cooling-device = <&cpu3_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-0-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 7>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ cpufreq_10_iot_config: cpufreq-10-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu10_iot_config: cpu10-config {
+ temperature = <122000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_10_iot_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu10_cdev {
+ trip = <&cpu10_iot_config>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-1-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 8>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ cpufreq_11_iot_config: cpufreq-11-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu11_iot_config: cpu11-config {
+ temperature = <122000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_11_iot_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu11_cdev {
+ trip = <&cpu11_iot_config>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-2-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 9>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ cpufreq_12_iot_config: cpufreq-12-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu12_iot_config: cpu12-config {
+ temperature = <122000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_12_iot_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu12_cdev {
+ trip = <&cpu12_iot_config>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-3-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 10>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ cpufreq_13_iot_config: cpufreq-13-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu13_iot_config: cpu13-config {
+ temperature = <122000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_13_iot_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu13_cdev {
+ trip = <&cpu13_iot_config>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-4-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 11>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ cpufreq_14_iot_config: cpufreq-14-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu14_iot_config: cpu14-config {
+ temperature = <122000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_14_iot_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu14_cdev {
+ trip = <&cpu14_iot_config>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-5-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 12>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ cpufreq_15_iot_config: cpufreq-15-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu15_iot_config: cpu15-config {
+ temperature = <122000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_15_iot_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu15_cdev {
+ trip = <&cpu15_iot_config>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-6-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 13>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ cpufreq_16_iot_config: cpufreq-16-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu16_iot_config: cpu16-config {
+ temperature = <122000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_16_iot_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu16_cdev {
+ trip = <&cpu16_iot_config>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-7-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens0 14>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ cpufreq_17_iot_config: cpufreq-17-config {
+ temperature = <75000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ cpu17_iot_config: cpu17-config {
+ temperature = <122000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpufreq_cdev {
+ trip = <&cpufreq_17_iot_config>;
+ cooling-device = <&cpu7_notify 1 1>;
+ };
+
+ cpu17_cdev {
+ trip = <&cpu17_iot_config>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ cwlan-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 1>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ cwlan_iot_trip0: cwlan-trip0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev {
+ trip = <&cwlan_iot_trip0>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&cwlan_iot_trip0>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&cwlan_iot_trip0>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&cwlan_iot_trip0>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&cwlan_iot_trip0>;
+ cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+ };
+ };
+
+ video-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 2>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ video_iot_trip0: video-trip0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev {
+ trip = <&video_iot_trip0>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&video_iot_trip0>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&video_iot_trip0>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&video_iot_trip0>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&video_iot_trip0>;
+ cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+ };
+ };
+
+ ddr-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 3>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ ddr_iot_trip0: ddr-trip0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev {
+ trip = <&ddr_iot_trip0>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&ddr_iot_trip0>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&ddr_iot_trip0>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&ddr_iot_trip0>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&ddr_iot_trip0>;
+ cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+ };
+ };
+
+ q6-hvx-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 4>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ q6_hvx_iot_trip0: q6-hvx-trip0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev {
+ trip = <&q6_hvx_iot_trip0>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&q6_hvx_iot_trip0>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&q6_hvx_iot_trip0>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&q6_hvx_iot_trip0>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&q6_hvx_iot_trip0>;
+ cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+ };
+ };
+
+ camera-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 5>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ camera_iot_trip0: camera-trip0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev {
+ trip = <&camera_iot_trip0>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&camera_iot_trip0>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&camera_iot_trip0>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&camera_iot_trip0>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&camera_iot_trip0>;
+ cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+ };
+ };
+
+ cmpss-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 6>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ cmpss_iot_trip0: cmpss-trip0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev {
+ trip = <&cmpss_iot_trip0>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&cmpss_iot_trip0>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&cmpss_iot_trip0>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&cmpss_iot_trip0>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&cmpss_iot_trip0>;
+ cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+ };
+ };
+
+ npu-iot-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens1 7>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ disable-thermal-zone;
+ trips {
+ npu_iot_trip0: npu-trip0 {
+ temperature = <120000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cdsp-cdev {
+ trip = <&npu_iot_trip0>;
+ cooling-device = <&msm_cdsp_rm 3 3>;
+ };
+
+ gpu-cdev {
+ trip = <&npu_iot_trip0>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-1)
+ (THERMAL_MAX_LIMIT-1)>;
+ };
+
+ modem-pa-cdev {
+ trip = <&npu_iot_trip0>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ modem-tj-cdev {
+ trip = <&npu_iot_trip0>;
+ cooling-device = <&modem_tj 3 3>;
+ };
+
+ npu_cdev {
+ trip = <&npu_iot_trip0>;
+ cooling-device = <&msm_npu (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qrb5165n-iot-rb5.dts b/arch/arm64/boot/dts/vendor/qcom/qrb5165n-iot-rb5.dts
new file mode 100755
index 0000000..b046e53
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qrb5165n-iot-rb5.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "qrb5165n.dtsi"
+#include "qrb5165n-iot-rb5.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QRB5165N IOT RB5";
+ compatible = "qcom,kona-iot", "qcom,kona", "qcom,iot";
+ qcom,board-id = <11 3>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/qrb5165n-iot-rb5.dtsi b/arch/arm64/boot/dts/vendor/qcom/qrb5165n-iot-rb5.dtsi
new file mode 100755
index 0000000..4a59978
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qrb5165n-iot-rb5.dtsi
@@ -0,0 +1,48 @@
+#include "kona-v2.1-iot-rb5.dtsi"
+
+&pcie0 {
+ /delete-property/ qcom,config-recovery;
+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
+ <0x100 &apps_smmu 0x1c01 0x1>,
+ <0x200 &apps_smmu 0x1c02 0x1>,
+ <0x210 &apps_smmu 0x1c03 0x1>,
+ <0x230 &apps_smmu 0x1c04 0x1>,
+ <0x270 &apps_smmu 0x1c05 0x1>,
+ <0x500 &apps_smmu 0x1c06 0x1>;
+};
+
+&pcie0_rp {
+ #address-cells = <5>;
+ #size-cells = <0>;
+
+ /delete-node/ cnss_pci;
+ asm2806_switch: asm2806_switch {
+ reg = <0x00010000 0x0 0x0 0x0 0x0>;
+ #address-cells = <5>;
+ #size-cells = <0>;
+
+ lane6: lane6 {
+ reg = <0x00023000 0x0 0x0 0x0 0x0>;
+ #address-cells = <5>;
+ #size-cells = <0>;
+
+ cnss_pci: cnss_pci {
+ reg = <0x00050000 0x0 0x0 0x0 0x0>;
+ qcom,iommu-group = <&cnss_pci_iommu_group>;
+ memory-region = <&cnss_wlan_mem>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cnss_pci_iommu_group: cnss_pci_iommu_group {
+ qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
+ qcom,iommu-dma = "fastmap";
+ qcom,iommu-pagetable = "coherent";
+ qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
+ "non-fatal";
+ };
+ };
+ };
+ };
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/qrb5165n.dtsi b/arch/arm64/boot/dts/vendor/qcom/qrb5165n.dtsi
new file mode 100755
index 0000000..ccd1c3e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/qrb5165n.dtsi
@@ -0,0 +1,7 @@
+#include "kona-v2.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QRB5165N";
+ compatible = "qcom,kona";
+ qcom,msm-id = <496 0x20001>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-2gb.dts
new file mode 100755
index 0000000..a5ae273
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-2gb.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "scuba-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba 2GB DDR SoC";
+ compatible = "qcom,scuba";
+ qcom,msm-id = <441 0x10000>, <471 0x10000>;
+ qcom,board-id = <0 0x400>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-audio-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-audio-overlay.dtsi
new file mode 100755
index 0000000..9ed32c7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-audio-overlay.dtsi
@@ -0,0 +1,319 @@
+#include <dt-bindings/clock/qcom,audio-ext-clk.h>
+#include <dt-bindings/sound/qcom,bolero-clk-rsc.h>
+#include <dt-bindings/sound/audio-codec-port-types.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&bolero {
+ qcom,num-macros = <3>;
+ qcom,bolero-version = <5>;
+ bolero-clk-rsc-mngr {
+ compatible = "qcom,bolero-clk-rsc-mngr";
+ qcom,fs-gen-sequence = <0x3000 0x1>,
+ <0x3004 0x1>, <0x3080 0x2>;
+ qcom,rx_mclk_mode_muxsel = <0x0a5640d8>;
+ qcom,va_mclk_mode_muxsel = <0x0a7a0000>;
+ clock-names = "tx_core_clk", "tx_npl_clk", "rx_core_clk", "rx_npl_clk",
+ "va_core_clk", "va_npl_clk";
+ clocks = <&clock_audio_tx_1 0>, <&clock_audio_tx_2 0>,
+ <&clock_audio_rx_1 0>, <&clock_audio_rx_2 0>,
+ <&clock_audio_va_1 0>, <&clock_audio_va_2 0>;
+ };
+
+ tx_macro: tx-macro@0a620000 {
+ compatible = "qcom,tx-macro";
+ reg = <0x0a620000 0x0>;
+ clock-names = "tx_core_clk", "tx_npl_clk";
+ clocks = <&clock_audio_tx_1 0>,
+ <&clock_audio_tx_2 0>;
+ qcom,tx-dmic-sample-rate = <2400000>;
+ qcom,is-used-swr-gpio = <0>;
+ };
+
+ rx_macro: rx-macro@0a600000 {
+ compatible = "qcom,rx-macro";
+ reg = <0x0a600000 0x0>;
+ clock-names = "rx_core_clk", "rx_npl_clk";
+ clocks = <&clock_audio_rx_1 0>,
+ <&clock_audio_rx_2 0>;
+ qcom,rx-swr-gpios = <&rx_swr_gpios>;
+ qcom,rx_mclk_mode_muxsel = <0x0a5640d8>;
+ qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x04 0x3E>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ swr1: rx_swr_master {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+ qcom,swr_master_id = <2>;
+ qcom,swrm-hctl-reg = <0x0a6a9098>;
+ qcom,mipi-sdw-block-packing-mode = <1>;
+ swrm-io-base = <0x0a610000 0x0>;
+ interrupts = <0 297 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq";
+ qcom,swr-num-ports = <5>;
+ qcom,disable-div2-clk-switch = <1>;
+ qcom,swr-port-mapping = <1 HPH_L 0x1>,
+ <1 HPH_R 0x2>, <2 CLSH 0x1>,
+ <3 COMP_L 0x1>, <3 COMP_R 0x2>,
+ <4 LO 0x1>, <5 DSD_L 0x1>,
+ <5 DSD_R 0x2>;
+ qcom,swr-num-dev = <1>;
+ qcom,swr-clock-stop-mode0 = <1>;
+ rouleur_rx_slave: rouleur-rx-slave {
+ compatible = "qcom,rouleur-slave";
+ reg = <0x0C 0x01170224>;
+ };
+ };
+ };
+
+ va_macro: va-macro@0a730000 {
+ compatible = "qcom,va-macro";
+ reg = <0x0a730000 0x0>;
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+ qcom,va-dmic-sample-rate = <600000>;
+ qcom,va-clk-mux-select = <1>;
+ qcom,va-island-mode-muxsel = <0x0a7a0000>;
+ qcom,default-clk-id = <TX_CORE_CLK>;
+ qcom,is-used-swr-gpio = <1>;
+ qcom,va-swr-gpios = <&va_swr_gpios>;
+ swr0: va_swr_master {
+ compatible = "qcom,swr-mstr";
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+ qcom,swr_master_id = <3>;
+ qcom,swrm-hctl-reg = <0x0a7ec100>;
+ qcom,mipi-sdw-block-packing-mode = <1>;
+ swrm-io-base = <0x0a740000 0x0>;
+ interrupts =
+ <0 296 IRQ_TYPE_LEVEL_HIGH>,
+ <0 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq", "swr_wake_irq";
+ qcom,swr-wakeup-required = <1>;
+ qcom,swr-num-ports = <3>;
+ qcom,swr-port-mapping = <1 ADC1 0x1>, <1 ADC2 0x2>,
+ <1 ADC3 0x4>, <1 ADC4 0x8>,
+ <2 DMIC0 0x1>, <2 DMIC1 0x2>,
+ <2 DMIC2 0x4>, <2 DMIC3 0x8>,
+ <3 DMIC4 0x1>, <3 DMIC5 0x2>,
+ <3 DMIC6 0x4>, <3 DMIC7 0x8>;
+ qcom,swr-num-dev = <1>;
+ qcom,swr-clock-stop-mode0 = <1>;
+ qcom,swr-mstr-irq-wakeup-capable = <1>;
+ rouleur_tx_slave: rouleur-tx-slave {
+ compatible = "qcom,rouleur-slave";
+ reg = <0x0C 0x01170223>;
+ };
+ };
+ };
+
+ rouleur_codec: rouleur-codec {
+ compatible = "qcom,rouleur-codec";
+ qcom,split-codec = <1>;
+ qcom,pmic-spmi-node = <&pm2250_cdc>;
+ qcom,wcd-reset-reg = <0x0000F3DB>;
+ qcom,foundry-id-reg = <0x0000704D>;
+ qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
+ <0 HPH_R 0x2 0 HPH_R>,
+ <1 COMP_L 0x1 0 COMP_L>, <1 COMP_R 0x2 0 COMP_R>;
+ qcom,tx_swr_ch_map = <0 ADC1 0x1 0 ADC1>,
+ <0 ADC2 0x2 0 ADC2>, <0 DMIC0 0x4 0 ADC3>,
+ <0 MBHC 0x8 0 ADC4>, <1 DMIC0 0x1 0 DMIC0>,
+ <1 DMIC1 0x2 0 DMIC1>, <1 ADC1 0x4 0 DMIC2>,
+ <1 MBHC 0x8 0 DMIC3>;
+
+ qcom,rx-slave = <&rouleur_rx_slave>;
+ qcom,tx-slave = <&rouleur_tx_slave>;
+
+ cdc-vdd-io-supply = <&L15A>;
+ qcom,cdc-vdd-io-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-io-current = <10000>;
+
+ cdc-vdd-cp-supply = <&S4A>;
+ qcom,cdc-vdd-cp-voltage = <2040000 2040000>;
+ qcom,cdc-vdd-cp-current = <300000>;
+
+ cdc-pa-vpos-supply = <&S4A>;
+ qcom,cdc-pa-vpos-voltage = <2040000 2040000>;
+ qcom,cdc-pa-vpos-current = <2400000>;
+
+ cdc-vdd-mic-bias-supply = <&L22A>;
+ qcom,cdc-vdd-mic-bias-voltage = <3000000 3304000>;
+ qcom,cdc-vdd-mic-bias-current = <50000>;
+ qcom,cdc-vdd-mic-bias-lpm-supported = <1>;
+
+ qcom,cdc-micbias1-mv = <1800>;
+ qcom,cdc-micbias2-mv = <1800>;
+ qcom,cdc-micbias3-mv = <1800>;
+
+ qcom,cdc-static-supplies = "cdc-vdd-cp",
+ "cdc-vdd-io",
+ "cdc-vdd-mic-bias";
+ qcom,cdc-on-demand-supplies = "cdc-pa-vpos";
+ };
+};
+
+&scuba_snd {
+ qcom,model = "bengal-scubaidp-snd-card";
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
+ qcom,wcn-btfm = <1>;
+ qcom,va-bolero-codec = <1>;
+ qcom,rxtx-bolero-codec = <1>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "TX DMIC0", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic0",
+ "TX DMIC1", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic1",
+ "TX DMIC2", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic2",
+ "TX DMIC3", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic3",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "SpkrMono WSA_IN", "LO",
+ "TX SWR_MIC0", "ADC1_OUTPUT",
+ "TX SWR_MIC1", "ADC2_OUTPUT",
+ "TX SWR_MIC2", "DMIC1_OUTPUT",
+ "TX SWR_MIC5", "DMIC2_OUTPUT",
+ "TX SWR_MIC0", "VA_TX_SWR_CLK",
+ "TX SWR_MIC1", "VA_TX_SWR_CLK",
+ "TX SWR_MIC2", "VA_TX_SWR_CLK",
+ "TX SWR_MIC3", "VA_TX_SWR_CLK",
+ "TX SWR_MIC4", "VA_TX_SWR_CLK",
+ "TX SWR_MIC5", "VA_TX_SWR_CLK",
+ "TX SWR_MIC6", "VA_TX_SWR_CLK",
+ "TX SWR_MIC7", "VA_TX_SWR_CLK",
+ "TX SWR_MIC8", "VA_TX_SWR_CLK",
+ "TX SWR_MIC9", "VA_TX_SWR_CLK",
+ "TX SWR_MIC10", "VA_TX_SWR_CLK",
+ "TX SWR_MIC11", "VA_TX_SWR_CLK",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "TX_AIF1 CAP", "VA_TX_SWR_CLK",
+ "TX_AIF2 CAP", "VA_TX_SWR_CLK",
+ "TX_AIF3 CAP", "VA_TX_SWR_CLK",
+ "VA DMIC0", "VA MIC BIAS3",
+ "VA DMIC1", "VA MIC BIAS3",
+ "VA DMIC2", "VA MIC BIAS1",
+ "VA DMIC3", "VA MIC BIAS1",
+ "VA MIC BIAS3", "Digital Mic0",
+ "VA MIC BIAS3", "Digital Mic1",
+ "VA MIC BIAS1", "Digital Mic2",
+ "VA MIC BIAS1", "Digital Mic3",
+ "VA SWR_MIC0", "ADC1_OUTPUT",
+ "VA SWR_MIC1", "ADC2_OUTPUT",
+ "VA SWR_MIC2", "DMIC1_OUTPUT",
+ "VA SWR_MIC5", "DMIC2_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
+ qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
+
+ nvmem-cells = <&adsp_variant>;
+ nvmem-cell-names = "adsp_variant";
+ asoc-codec = <&stub_codec>, <&bolero>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec";
+ qcom,wsa-max-devs = <1>;
+ qcom,wsa-devs = <&wsa881x_i2c_e>;
+ qcom,wsa-aux-dev-prefix = "SpkrMono";
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&rouleur_codec>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&bolero>,
+ <&lpi_tlmm>;
+};
+
+&qupv3_se1_i2c {
+ wsa881x_i2c_e: wsa881x-i2c-codec@e {
+ compatible = "qcom,wsa881x-i2c-codec";
+ reg = <0x0e>;
+ clock-names = "wsa_mclk";
+ clocks = <&wsa881x_analog_clk 0>;
+ qcom,wsa-analog-clk-gpio = <&wsa881x_analog_clk_gpio>;
+ qcom,wsa-analog-reset-gpio = <&wsa881x_analog_reset_gpio>;
+ };
+
+ wsa881x_i2c_44: wsa881x-i2c-codec@44 {
+ compatible = "qcom,wsa881x-i2c-codec";
+ reg = <0x044>;
+ };
+};
+
+&soc {
+ wsa881x_analog_reset_gpio: msm_cdc_pinctrl@106 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ pinctrl-1 = <&spkr_1_sd_n_sleep>;
+ };
+
+ wsa881x_analog_clk: wsa_ana_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
+ qcom,codec-lpass-ext-clk-freq = <9600000>;
+ qcom,codec-lpass-clk-id = <0x301>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_rx_1: rx_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
+ qcom,codec-lpass-ext-clk-freq = <22579200>;
+ qcom,codec-lpass-clk-id = <0x30E>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_rx_2: rx_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_5>;
+ qcom,codec-lpass-ext-clk-freq = <22579200>;
+ qcom,codec-lpass-clk-id = <0x30F>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_tx_1: tx_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30C>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_tx_2: tx_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_7>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30D>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_va_1: va_core_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x30B>;
+ #clock-cells = <1>;
+ };
+
+ clock_audio_va_2: va_npl_clk {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_8>;
+ qcom,codec-lpass-ext-clk-freq = <19200000>;
+ qcom,codec-lpass-clk-id = <0x310>;
+ #clock-cells = <1>;
+ };
+};
+
+&va_cdc_dma_0_tx {
+ qcom,msm-dai-is-island-supported = <1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-audio.dtsi
new file mode 100755
index 0000000..bc1bbc6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-audio.dtsi
@@ -0,0 +1,185 @@
+#include <dt-bindings/clock/qcom,audio-ext-clk.h>
+#include "msm-audio-lpass.dtsi"
+
+&msm_audio_ion {
+ iommus = <&apps_smmu 0x01c1 0x0>;
+ qcom,smmu-sid-mask = /bits/ 64 <0xf>;
+};
+
+&audio_apr {
+ q6core: qcom,q6core-audio {
+ compatible = "qcom,q6core-audio";
+
+ lpass_audio_hw_vote: vote_lpass_audio_hw {
+ compatible = "qcom,audio-ref-clk";
+ qcom,codec-ext-clk-src = <AUDIO_LPASS_AUDIO_HW_VOTE>;
+ #clock-cells = <1>;
+ };
+
+ };
+};
+
+#include "scuba-lpi.dtsi"
+
+&q6core {
+ cdc_dmic01_gpios: cdc_dmic01_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
+ pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ cdc_dmic23_gpios: cdc_dmic23_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
+ pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ rx_swr_gpios: rx_swr_clk_data_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
+ &rx_swr_data1_active>;
+ pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
+ &rx_swr_data1_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ va_swr_gpios: va_swr_clk_data_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&tx_swr_clk_active &tx_swr_data1_active
+ &tx_swr_data2_active>;
+ pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data1_sleep
+ &tx_swr_data2_sleep>;
+ qcom,lpi-gpios;
+ qcom,chip-wakeup-reg = <0x003ca064>;
+ qcom,chip-wakeup-maskbit = <0>;
+ qcom,chip-wakeup-default-val = <0x1>;
+ };
+
+ wsa881x_analog_clk_gpio: msm_cdc_pinctrl@18 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wsa_mclk_active>;
+ pinctrl-1 = <&wsa_mclk_sleep>;
+ qcom,lpi-gpios;
+ };
+};
+
+&q6core {
+ bolero: bolero-cdc {
+ compatible = "qcom,bolero-codec";
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+ bolero-clk-rsc-mngr {
+ compatible = "qcom,bolero-clk-rsc-mngr";
+ };
+
+ va_macro: va-macro@0a730000 {
+ swr0: va_swr_master {
+ };
+ };
+
+ rx_macro: rx-macro@0a600000 {
+ swr1: rx_swr_master {
+ };
+ };
+ };
+};
+
+&q6core {
+ scuba_snd: sound {
+ compatible = "qcom,bengal-asoc-snd";
+ qcom,mi2s-audio-intf = <0>;
+ qcom,auxpcm-audio-intf = <0>;
+ qcom,tdm-audio-intf = <0>;
+ qcom,wcn-btfm = <0>;
+ qcom,afe-rxtx-lb = <0>;
+
+ asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
+ <&loopback>, <&compress>, <&hostless>,
+ <&afe>, <&lsm>, <&routing>, <&compr>,
+ <&pcm_noirq>;
+ asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
+ "msm-pcm-dsp.2", "msm-voip-dsp",
+ "msm-pcm-voice", "msm-pcm-loopback",
+ "msm-compress-dsp", "msm-pcm-hostless",
+ "msm-pcm-afe", "msm-lsm-client",
+ "msm-pcm-routing", "msm-compr-dsp",
+ "msm-pcm-dsp-noirq";
+ asoc-cpu = <&dai_mi2s0>, <&dai_mi2s1>,
+ <&dai_mi2s2>, <&dai_mi2s3>,
+ <&dai_pri_auxpcm>,
+ <&dai_sec_auxpcm>, <&dai_tert_auxpcm>,
+ <&dai_quat_auxpcm>,
+ <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>,
+ <&afe_proxy_tx>, <&incall_record_rx>,
+ <&incall_record_tx>, <&incall_music_rx>,
+ <&incall_music_2_rx>,
+ <&proxy_rx>, <&proxy_tx>,
+ <&usb_audio_rx>, <&usb_audio_tx>,
+ <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>,
+ <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>,
+ <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>,
+ <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>,
+ <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>,
+ <&va_cdc_dma_0_tx>, <&va_cdc_dma_1_tx>,
+ <&va_cdc_dma_2_tx>,
+ <&rx_cdc_dma_0_rx>, <&tx_cdc_dma_0_tx>,
+ <&rx_cdc_dma_1_rx>, <&tx_cdc_dma_1_tx>,
+ <&rx_cdc_dma_2_rx>, <&tx_cdc_dma_2_tx>,
+ <&rx_cdc_dma_3_rx>, <&tx_cdc_dma_3_tx>,
+ <&rx_cdc_dma_4_rx>, <&tx_cdc_dma_4_tx>,
+ <&rx_cdc_dma_5_rx>, <&tx_cdc_dma_5_tx>,
+ <&rx_cdc_dma_6_rx>, <&rx_cdc_dma_7_rx>,
+ <&afe_loopback_tx>;
+ asoc-cpu-names = "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",
+ "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",
+ "msm-dai-q6-auxpcm.1",
+ "msm-dai-q6-auxpcm.2", "msm-dai-q6-auxpcm.3",
+ "msm-dai-q6-auxpcm.4", "msm-dai-q6-dev.224",
+ "msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
+ "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
+ "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
+ "msm-dai-q6-dev.32770",
+ "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195",
+ "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673",
+ "msm-dai-q6-dev.16398", "msm-dai-q6-dev.16399",
+ "msm-dai-q6-dev.16401",
+ "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865",
+ "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881",
+ "msm-dai-q6-tdm.36896", "msm-dai-q6-tdm.36897",
+ "msm-dai-q6-tdm.36912", "msm-dai-q6-tdm.36913",
+ "msm-dai-cdc-dma-dev.45089",
+ "msm-dai-cdc-dma-dev.45091",
+ "msm-dai-cdc-dma-dev.45093",
+ "msm-dai-cdc-dma-dev.45104",
+ "msm-dai-cdc-dma-dev.45105",
+ "msm-dai-cdc-dma-dev.45106",
+ "msm-dai-cdc-dma-dev.45107",
+ "msm-dai-cdc-dma-dev.45108",
+ "msm-dai-cdc-dma-dev.45109",
+ "msm-dai-cdc-dma-dev.45110",
+ "msm-dai-cdc-dma-dev.45111",
+ "msm-dai-cdc-dma-dev.45112",
+ "msm-dai-cdc-dma-dev.45113",
+ "msm-dai-cdc-dma-dev.45114",
+ "msm-dai-cdc-dma-dev.45115",
+ "msm-dai-cdc-dma-dev.45116",
+ "msm-dai-cdc-dma-dev.45118",
+ "msm-dai-q6-dev.24577";
+ fsa4480-i2c-handle = <&fsa4480>;
+ };
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ fsa4480: fsa4480@42 {
+ compatible = "qcom,fsa4480-i2c";
+ reg = <0x42>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-bus.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-bus.dtsi
new file mode 100755
index 0000000..81217ba
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-bus.dtsi
@@ -0,0 +1,1007 @@
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+
+&soc {
+ ad_hoc_bus: ad-hoc-bus {
+ compatible = "qcom,msm-bus-device";
+ reg = <0x1880000 0x60200>,
+ <0x4480000 0x80000>,
+ <0x1900000 0x8200>,
+ <0x1880000 0x600>,
+ <0x1880000 0x60200>,
+ <0x1880000 0x60200>;
+ reg-names = "sys_noc-base", "bimc-base",
+ "config_noc-base", "qup_virt-base",
+ "mmnrt_virt-base", "mmrt_virt-base";
+
+ /*Buses*/
+
+ fab_bimc: fab-bimc {
+ cell-id = <MSM_BUS_FAB_BIMC>;
+ label = "fab-bimc";
+ qcom,fab-dev;
+ qcom,base-name = "bimc-base";
+ qcom,bus-type = <2>;
+ qcom,util-fact = <153>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc BIMC_MSMBUS_CLK>,
+ <&rpmcc BIMC_MSMBUS_A_CLK>;
+ };
+
+ fab_config_noc: fab-config_noc {
+ cell-id = <MSM_BUS_FAB_CONFIG_NOC>;
+ label = "fab-config_noc";
+ qcom,fab-dev;
+ qcom,base-name = "config_noc-base";
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc CNOC_MSMBUS_CLK>,
+ <&rpmcc CNOC_MSMBUS_A_CLK>;
+ };
+
+ fab_qup_virt: fab-qup_virt {
+ cell-id = <MSM_BUS_FAB_QUP_VIRT>;
+ label = "fab-qup_virt";
+ qcom,fab-dev;
+ qcom,base-name = "qup_virt-base";
+ qcom,bypass-qos-prg;
+ qcom,bus-type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc RPM_SMD_QUP_CLK>,
+ <&rpmcc RPM_SMD_QUP_A_CLK>;
+ };
+
+ fab_sys_noc: fab-sys_noc {
+ cell-id = <MSM_BUS_FAB_SYS_NOC>;
+ label = "fab-sys_noc";
+ qcom,fab-dev;
+ qcom,base-name = "sys_noc-base";
+ qcom,bus-type = <3>;
+ qcom,base-offset = <0x15000>;
+ qcom,qos-off = <0x1000>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc SNOC_MSMBUS_CLK>,
+ <&rpmcc SNOC_MSMBUS_A_CLK>;
+ };
+
+ fab_mmnrt_virt: fab-mmnrt_virt {
+ cell-id = <MSM_BUS_FAB_MMNRT_VIRT>;
+ label = "fab-mmnrt_virt";
+ qcom,fab-dev;
+ qcom,base-name = "mmnrt_virt-base";
+ qcom,bus-type = <3>;
+ qcom,base-offset = <0x15000>;
+ qcom,qos-off = <0x1000>;
+ qcom,util-fact = <142>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc CPP_MMNRT_MSMBUS_CLK>,
+ <&rpmcc CPP_MMNRT_MSMBUS_A_CLK>;
+ };
+
+ fab_mmrt_virt: fab-mmrt_virt {
+ cell-id = <MSM_BUS_FAB_MMRT_VIRT>;
+ label = "fab-mmrt_virt";
+ qcom,fab-dev;
+ qcom,base-name = "mmrt_virt-base";
+ qcom,bus-type = <3>;
+ qcom,base-offset = <0x15000>;
+ qcom,qos-off = <0x1000>;
+ qcom,util-fact = <139>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&rpmcc MDP_MMRT_MSMBUS_CLK>,
+ <&rpmcc MDP_MMRT_MSMBUS_A_CLK>;
+ };
+
+ /*Masters*/
+
+ mas_apps_proc: mas-apps-proc {
+ cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
+ label = "mas-apps-proc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,util-fact = <159>;
+ qcom,vrail-comp = <96>;
+ qcom,qport = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,prio-lvl = <0>;
+ qcom,prio-rd = <0>;
+ qcom,prio-wr = <0>;
+ clock-names = "node_clk", "node_a_clk";
+ clocks = <&rpmcc RPM_SMD_CPUSS_GNOC_CLK>,
+ <&rpmcc RPM_SMD_CPUSS_GNOC_A_CLK>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_APPSS_PROC>;
+ };
+
+ mas_snoc_bimc_rt: mas-snoc-bimc-rt {
+ cell-id = <MSM_BUS_MASTER_SNOC_BIMC_RT>;
+ label = "mas-snoc-bimc-rt";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_ebi>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_RT>;
+ };
+
+ mas_snoc_bimc_nrt: mas-snoc-bimc-nrt {
+ cell-id = <MSM_BUS_MASTER_SNOC_BIMC_NRT>;
+ label = "mas-snoc-bimc-nrt";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <3>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_ebi>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC_NRT>;
+ };
+
+ mas_snoc_bimc: mas-snoc-bimc {
+ cell-id = <MSM_BUS_SNOC_BIMC_MAS>;
+ label = "mas-snoc-bimc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <6>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_ebi>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC>;
+ };
+
+ mas_tcu_0: mas-tcu-0 {
+ cell-id = <MSM_BUS_MASTER_TCU_0>;
+ label = "mas-tcu-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <4>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_ebi &slv_bimc_snoc>;
+ qcom,prio-lvl = <6>;
+ qcom,prio-rd = <6>;
+ qcom,prio-wr = <6>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_TCU_0>;
+ };
+
+ mas_snoc_cnoc: mas-snoc-cnoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_MAS>;
+ label = "mas-snoc-cnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_qhs_camera_rt_throttle_cfg
+ &slv_qhs_sdc2 &slv_qhs_sdc1
+ &slv_qhs_qm_cfg &slv_qhs_bimc_cfg
+ &slv_qhs_usb3 &slv_qhs_qm_mpu_cfg
+ &slv_qhs_camera_nrt_throttle_cfg
+ &slv_qhs_qdss_cfg &slv_qhs_pdm
+ &slv_qhs_ipa_cfg &slv_qhs_display_throttle_cfg
+ &slv_qhs_tcsr &slv_qhs_mesg_ram
+ &slv_qhs_pmic_arb &slv_qhs_lpass
+ &slv_qhs_disp_ss_cfg &slv_qhs_venus_cfg
+ &slv_qhs_gpu_cfg &slv_qhs_imem_cfg
+ &slv_snoc_cfg &slv_srvc_cnoc
+ &slv_qhs_venus_throttle_cfg
+ &slv_qhs_pka_wrapper &slv_qhs_hwkm
+ &slv_qhs_prng &slv_qhs_vsense_ctrl_cfg
+ &slv_qhs_crypto0_cfg &slv_qhs_pimem_cfg
+ &slv_qhs_qup0 &slv_qhs_camera_ss_cfg
+ &slv_qhs_clk_ctl &slv_qhs_qpic>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_CNOC>;
+ };
+
+ mas_xm_dap: mas-xm-dap {
+ cell-id = <MSM_BUS_MASTER_QDSS_DAP>;
+ label = "mas-xm-dap";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_qhs_camera_rt_throttle_cfg
+ &slv_qhs_sdc2 &slv_qhs_sdc1
+ &slv_qhs_qm_cfg &slv_qhs_bimc_cfg
+ &slv_qhs_usb3 &slv_qhs_qm_mpu_cfg
+ &slv_qhs_camera_nrt_throttle_cfg
+ &slv_qhs_qdss_cfg &slv_qhs_pdm
+ &slv_qhs_ipa_cfg &slv_qhs_display_throttle_cfg
+ &slv_qhs_tcsr &slv_qhs_mesg_ram
+ &slv_qhs_pmic_arb &slv_qhs_lpass
+ &slv_qhs_disp_ss_cfg &slv_qhs_venus_cfg
+ &slv_qhs_gpu_cfg &slv_qhs_imem_cfg
+ &slv_snoc_cfg &slv_srvc_cnoc
+ &slv_qhs_venus_throttle_cfg
+ &slv_qhs_pka_wrapper &slv_qhs_hwkm
+ &slv_qhs_prng &slv_qhs_vsense_ctrl_cfg
+ &slv_qhs_crypto0_cfg &slv_qhs_pimem_cfg
+ &slv_qhs_qup0 &slv_qhs_camera_ss_cfg
+ &slv_qhs_clk_ctl &slv_qhs_qpic>;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_DAP>;
+ };
+
+ mas_crypto_c0: mas-crypto-c0 {
+ cell-id = <MSM_BUS_MASTER_CRYPTO_CORE0>;
+ label = "mas-crypto-c0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <22>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ clock-names = "node_clk", "node_a_clk";
+ clocks = <&rpmcc CRYPTO_MSMBUS_SNOC_PERIPH_CLK>,
+ <&rpmcc CRYPTO_MSMBUS_SNOC_PERIPH_A_CLK>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO_CORE0>;
+ };
+
+ mas_qup_core_master_0: mas-qup-core-master-0 {
+ cell-id = <MSM_BUS_MASTER_QUP_CORE_0>;
+ label = "mas-qup-core-master-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qup_core_slave_0>;
+ qcom,bus-dev = <&fab_qup_virt>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QUP_CORE_0>;
+ };
+
+ mas_qnm_camera_nrt: mas-qnm-camera-nrt {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_SF>;
+ label = "mas-qnm-camera-nrt";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <4>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_snoc_bimc_nrt>;
+ qcom,prio = <3>;
+ qcom,bus-dev = <&fab_mmnrt_virt>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CAMNOC_SF>;
+ };
+
+ mas_qnm_camera_rt: mas-qnm-camera-rt {
+ cell-id = <MSM_BUS_MASTER_CAMNOC_HF>;
+ label = "mas-qnm-camera-rt";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <10>;
+ qcom,qos-mode = "fixed";
+ qcom,forwarding;
+ qcom,connections = <&slv_snoc_bimc_rt>;
+ qcom,prio = <3>;
+ qcom,bus-dev = <&fab_mmrt_virt>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CAMNOC_HF>;
+ };
+
+ mas_qxm_mdp0: mas-qxm-mdp0 {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT0>;
+ label = "mas-qxm-mdp0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <5>;
+ qcom,qos-mode = "fixed";
+ qcom,prio = <3>;
+ qcom,forwarding;
+ qcom,connections = <&slv_snoc_bimc_rt>;
+ qcom,bus-dev = <&fab_mmrt_virt>;
+ qcom,mas-rpm-id = <ICBID_MASTER_MDP0>;
+ };
+
+ mas_qxm_venus0: mas-qxm-venus0 {
+ cell-id = <MSM_BUS_MASTER_VIDEO_P0>;
+ label = "mas-qxm-venus0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <9>;
+ qcom,qos-mode = "fixed";
+ qcom,prio = <3>;
+ qcom,forwarding;
+ qcom,connections = <&slv_snoc_bimc_nrt>;
+ qcom,bus-dev = <&fab_mmnrt_virt>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VIDEO_P0>;
+ };
+
+ mas_qxm_venus_cpu: mas-qxm-venus-cpu {
+ cell-id = <MSM_BUS_MASTER_VIDEO_PROC>;
+ label = "mas-qxm-venus-cpu";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <13>;
+ qcom,qos-mode = "fixed";
+ qcom,prio = <4>;
+ qcom,connections = <&slv_snoc_bimc_nrt>;
+ qcom,bus-dev = <&fab_mmnrt_virt>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VIDEO_PROC>;
+ };
+
+ mas_snoc_cfg: mas-snoc-cfg {
+ cell-id = <MSM_BUS_MASTER_SNOC_CFG>;
+ label = "mas-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_srvc_snoc>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_CFG>;
+ };
+
+ mas_qhm_tic: mas-qhm-tic {
+ cell-id = <MSM_BUS_MASTER_TIC>;
+ label = "mas-qhm-tic";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ /* QoS priority for snoc_cnoc master */
+ qcom,prio = <2>;
+ qcom,qport = <8>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_qxs_pimem &slv_qxs_imem
+ &slv_qhs_apss &slv_snoc_bimc &slv_snoc_cnoc
+ &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_TIC>;
+ };
+
+ mas_anoc_snoc: mas-anoc-snoc {
+ cell-id = <MSM_BUS_MASTER_ANOC_SNOC>;
+ label = "mas-anoc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qxs_pimem &slv_qxs_imem
+ &slv_qhs_apss &slv_snoc_bimc
+ &slv_snoc_cnoc &slv_xs_sys_tcu_cfg
+ &slv_xs_qdss_stm>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_A0NOC_SNOC>;
+ };
+
+ mas_bimc_snoc: mas-bimc-snoc {
+ cell-id = <MSM_BUS_BIMC_SNOC_MAS>;
+ label = "mas-bimc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_qxs_pimem &slv_qxs_imem
+ &slv_qhs_apss &slv_snoc_cnoc
+ &slv_xs_sys_tcu_cfg &slv_xs_qdss_stm>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BIMC_SNOC>;
+ };
+
+ mas_qxm_pimem: mas-qxm-pimem {
+ cell-id = <MSM_BUS_MASTER_PIMEM>;
+ label = "mas-qxm-pimem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <20>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_qxs_imem &slv_snoc_bimc>;
+ qcom,prio = <2>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PIMEM>;
+ };
+
+
+ mas_qhm_qdss_bam: mas-qhm-qdss-bam {
+ cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
+ label = "mas-qhm-qdss-bam";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAM>;
+ };
+
+ mas_qhm_qup0: mas-qhm-qup0 {
+ cell-id = <MSM_BUS_MASTER_QUP_0>;
+ label = "mas-qhm-qup0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ clock-names = "node_clk", "node_a_clk";
+ clocks = <&rpmcc QUP0_MSMBUS_SNOC_PERIPH_CLK>,
+ <&rpmcc QUP0_MSMBUS_SNOC_PERIPH_A_CLK>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QUP_0>;
+ };
+
+ mas_qxm_ipa: mas-qxm-ipa {
+ cell-id = <MSM_BUS_MASTER_IPA>;
+ label = "mas-qxm-ipa";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <3>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_IPA>;
+ };
+
+ mas_xm_qdss_etr: mas-xm-qdss-etr {
+ cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
+ label = "mas-xm-qdss-etr";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <12>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>;
+ };
+
+ mas_xm_sdc1: mas-xm-sdc1 {
+ cell-id = <MSM_BUS_MASTER_SDCC_1>;
+ label = "mas-xm-sdc1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <17>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ clock-names = "node_clk", "node_a_clk";
+ clocks = <&rpmcc SDC1_MSMBUS_SNOC_PERIPH_CLK>,
+ <&rpmcc SDC1_MSMBUS_SNOC_PERIPH_A_CLK>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SDCC_1>;
+ };
+
+ mas_xm_sdc2: mas-xm-sdc2 {
+ cell-id = <MSM_BUS_MASTER_SDCC_2>;
+ label = "mas-xm-sdc2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <23>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ clock-names = "node_clk", "node_a_clk";
+ clocks = <&rpmcc SDC2_MSMBUS_SNOC_PERIPH_CLK>,
+ <&rpmcc SDC2_MSMBUS_SNOC_PERIPH_A_CLK>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SDCC_2>;
+ };
+
+ mas_qhm_qpic: mas-qhm-qpic {
+ cell-id = <MSM_BUS_MASTER_QPIC>;
+ label = "mas-qhm-qpic";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,prio = <2>;
+ qcom,qport = <1>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_USB3_0>;
+ };
+
+ mas_xm_usb3_0: mas-xm-usb3-0 {
+ cell-id = <MSM_BUS_MASTER_USB3>;
+ label = "mas-xm-usb3-0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <24>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_anoc_snoc>;
+ qcom,prio = <2>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_USB3_0>;
+ };
+
+ mas_qnm_gpu: mas-qnm-gpu {
+ cell-id = <MSM_BUS_MASTER_GRAPHICS_3D>;
+ label = "mas-qnm-gpu";
+ qcom,buswidth = <32>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,prio-lvl = <0>;
+ qcom,prio-rd = <0>;
+ qcom,prio-wr = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_ebi>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_GFX3D>;
+ };
+
+ /*Slaves*/
+
+ slv_ebi:slv-ebi {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ label = "slv-ebi";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_EBI1>;
+ };
+
+ slv_bimc_snoc:slv-bimc-snoc {
+ cell-id = <MSM_BUS_BIMC_SNOC_SLV>;
+ label = "slv-bimc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,connections = <&mas_bimc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_SNOC>;
+ };
+
+ slv_qhs_bimc_cfg:slv-qhs-bimc-cfg {
+ cell-id = <MSM_BUS_SLAVE_BIMC_CFG>;
+ label = "slv-qhs-bimc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_CFG>;
+ };
+
+ slv_qhs_camera_nrt_throttle_cfg:slv-qhs-camera-nrt-throtle-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_NRT_THROTTLE_CFG>;
+ label = "slv-qhs-camera-nrt-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_NRT_THROTTLE_CFG>;
+ };
+
+ slv_qhs_camera_rt_throttle_cfg:slv-qhs-camera-rt-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_RT_THROTTLE_CFG>;
+ label = "slv-qhs-camera-rt-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_RT_THROTTLE_CFG>;
+ };
+
+ slv_qhs_camera_ss_cfg:slv-qhs-camera-ss-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_CFG>;
+ label = "slv-qhs-camera-ss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_CFG>;
+ };
+
+ slv_qhs_clk_ctl:slv-qhs-clk-ctl {
+ cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
+ label = "slv-qhs-clk-ctl";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CLK_CTL>;
+ };
+
+ slv_qhs_crypto0_cfg:slv-qhs-crypto0-cfg {
+ cell-id = <MSM_BUS_SLAVE_CRYPTO_0_CFG>;
+ label = "slv-qhs-crypto0-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CRYPTO_0_CFG>;
+ };
+
+ slv_qhs_disp_ss_cfg:slv-qhs-disp-ss-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_CFG>;
+ label = "slv-qhs-disp-ss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_CFG>;
+ };
+
+ slv_qhs_display_throttle_cfg:slv-qhs-display-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG>;
+ label = "slv-qhs-display-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_THROTTLE_CFG>;
+ };
+
+ slv_qhs_gpu_cfg:slv-qhs-gpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_GPU_CFG>;
+ label = "slv-qhs-gpu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GPU_CFG>;
+ };
+
+ slv_qhs_hwkm:slv-qhs-hwkm {
+ cell-id = <MSM_BUS_SLAVE_HWKM>;
+ label = "slv-qhs-hwkm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_HWKM>;
+ };
+
+ slv_qhs_imem_cfg:slv-qhs-imem-cfg {
+ cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
+ label = "slv-qhs-imem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IMEM_CFG>;
+ };
+
+ slv_qhs_ipa_cfg:slv-qhs-ipa-cfg {
+ cell-id = <MSM_BUS_SLAVE_IPA_CFG>;
+ label = "slv-qhs-ipa-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IPA_CFG>;
+ };
+
+ slv_qhs_lpass:slv-qhs-lpass {
+ cell-id = <MSM_BUS_SLAVE_LPASS>;
+ label = "slv-qhs-lpass";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_LPASS>;
+ };
+
+ slv_qhs_mesg_ram:slv-qhs-mesg-ram {
+ cell-id = <MSM_BUS_SLAVE_MESSAGE_RAM>;
+ label = "slv-qhs-mesg-ram";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MESSAGE_RAM>;
+ };
+
+ slv_qhs_pdm:slv-qhs-pdm {
+ cell-id = <MSM_BUS_SLAVE_PDM>;
+ label = "slv-qhs-pdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PDM>;
+ };
+
+ slv_qhs_pimem_cfg:slv-qhs-pimem-cfg {
+ cell-id = <MSM_BUS_SLAVE_PIMEM_CFG>;
+ label = "slv-qhs-pimem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PIMEM_CFG>;
+ };
+
+ slv_qhs_pka_wrapper:slv-qhs-pka-wrapper {
+ cell-id = <MSM_BUS_SLAVE_PKA_WRAPPER>;
+ label = "slv-qhs-pka-wrapper";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PKA_WRAPPER>;
+ };
+
+ slv_qhs_pmic_arb:slv-qhs-pmic-arb {
+ cell-id = <MSM_BUS_SLAVE_PMIC_ARB>;
+ label = "slv-qhs-pmic-arb";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PMIC_ARB>;
+ };
+
+ slv_qhs_prng:slv-qhs-prng {
+ cell-id = <MSM_BUS_SLAVE_PRNG>;
+ label = "slv-qhs-prng";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>;
+ };
+
+ slv_qhs_qdss_cfg:slv-qhs-qdss-cfg {
+ cell-id = <MSM_BUS_SLAVE_QDSS_CFG>;
+ label = "slv-qhs-qdss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_CFG>;
+ };
+
+ slv_qhs_qm_cfg:slv-qhs-qm-cfg {
+ cell-id = <MSM_BUS_SLAVE_QM_CFG>;
+ label = "slv-qhs-qm-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QM_CFG>;
+ };
+
+ slv_qhs_qm_mpu_cfg:slv-qhs-qm-mpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_QM_MPU_CFG>;
+ label = "slv-qhs-qm-mpu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QM_MPU_CFG>;
+ };
+
+ slv_qhs_qpic:slv-qhs-qpic {
+ cell-id = <MSM_BUS_SLAVE_QPIC>;
+ label = "slv-qhs-qpic";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QPIC>;
+ };
+
+ slv_qhs_qup0:slv-qhs-qup0 {
+ cell-id = <MSM_BUS_SLAVE_QUP_0>;
+ label = "slv-qhs-qup0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QUP_0>;
+ };
+
+ slv_qhs_sdc1:slv-qhs-sdc1 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_1>;
+ label = "slv-qhs-sdc1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_1>;
+ };
+
+ slv_qhs_sdc2:slv-qhs-sdc2 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_2>;
+ label = "slv-qhs-sdc2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_2>;
+ };
+
+ slv_snoc_cfg:slv-snoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
+ label = "slv-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,connections = <&mas_snoc_cfg>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CFG>;
+ };
+
+ slv_qhs_tcsr:slv-qhs-tcsr {
+ cell-id = <MSM_BUS_SLAVE_TCSR>;
+ label = "slv-qhs-tcsr";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>;
+ };
+
+ slv_qhs_usb3:slv-qhs-usb3 {
+ cell-id = <MSM_BUS_SLAVE_USB3>;
+ label = "slv-qhs-usb3";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_USB3>;
+ };
+
+ slv_qhs_venus_cfg:slv-qhs-venus-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_CFG>;
+ label = "slv-qhs-venus-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_CFG>;
+ };
+
+ slv_qhs_venus_throttle_cfg:slv-qhs-venus-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_THROTTLE_CFG>;
+ label = "slv-qhs-venus-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_THROTTLE_CFG>;
+ };
+
+ slv_qhs_vsense_ctrl_cfg:slv-qhs-vsense-ctrl-cfg {
+ cell-id = <MSM_BUS_SLAVE_VSENSE_CTRL_CFG>;
+ label = "slv-qhs-vsense-ctrl-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VSENSE_CTRL_CFG>;
+ };
+
+ slv_srvc_cnoc:slv-srvc-cnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_CNOC>;
+ label = "slv-srvc-cnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_config_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_CNOC>;
+ };
+
+ slv_qup_core_slave_0:slv-qup-core-slave-0 {
+ cell-id = <MSM_BUS_SLAVE_QUP_CORE_0>;
+ label = "slv-qup-core-slave-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_qup_virt>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QUP_CORE_0>;
+ };
+
+ slv_snoc_bimc_nrt:slv-snoc-bimc-nrt {
+ cell-id = <MSM_BUS_SLAVE_SNOC_BIMC_NRT>;
+ label = "slv-snoc-bimc-nrt";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mmnrt_virt>;
+ qcom,connections = <&mas_snoc_bimc_nrt>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_NRT>;
+ };
+
+ slv_snoc_bimc_rt:slv-snoc-bimc-rt {
+ cell-id = <MSM_BUS_SLAVE_SNOC_BIMC_RT>;
+ label = "slv-snoc-bimc-rt";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mmrt_virt>;
+ qcom,connections = <&mas_snoc_bimc_rt>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC_RT>;
+ };
+
+ slv_qhs_apss:slv-qhs-apss {
+ cell-id = <MSM_BUS_SLAVE_APPSS>;
+ label = "slv-qhs-apss";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_APPSS>;
+ };
+
+ slv_snoc_cnoc:slv-snoc-cnoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_SLV>;
+ label = "slv-snoc-cnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,connections = <&mas_snoc_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CNOC>;
+ };
+
+ slv_qxs_imem:slv-qxs-imem {
+ cell-id = <MSM_BUS_SLAVE_OCIMEM>;
+ label = "slv-qxs-imem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IMEM>;
+ };
+
+ slv_qxs_pimem:slv-qxs-pimem {
+ cell-id = <MSM_BUS_SLAVE_PIMEM>;
+ label = "slv-qxs-pimem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PIMEM>;
+ };
+
+ slv_snoc_bimc:slv-snoc-bimc {
+ cell-id = <MSM_BUS_SNOC_BIMC_SLV>;
+ label = "slv-snoc-bimc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,connections = <&mas_snoc_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC>;
+ };
+
+ slv_srvc_snoc:slv-srvc-snoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_SNOC>;
+ label = "slv-srvc-snoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_SNOC>;
+ };
+
+ slv_xs_qdss_stm:slv-xs-qdss-stm {
+ cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
+ label = "slv-xs-qdss-stm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>;
+ };
+
+ slv_xs_sys_tcu_cfg:slv-xs-sys-tcu-cfg {
+ cell-id = <MSM_BUS_SLAVE_TCU>;
+ label = "slv-xs-sys-tcu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TCU>;
+ };
+
+ slv_anoc_snoc:slv-anoc-snoc {
+ cell-id = <MSM_BUS_SLAVE_ANOC_SNOC>;
+ label = "slv-anoc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_sys_noc>;
+ qcom,connections = <&mas_anoc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_A0NOC_SNOC>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-coresight.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-coresight.dtsi
new file mode 100755
index 0000000..bbcb275
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-coresight.dtsi
@@ -0,0 +1,1497 @@
+&soc {
+ hwevent {
+ compatible = "qcom,coresight-hwevent";
+
+ coresight-name = "coresight-hwevent";
+ coresight-csr = <&csr>;
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ apss_tgu: tgu@9900000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x0003b999>;
+ reg = <0x09900000 0x1000>;
+ reg-names = "tgu-base";
+ tgu-steps = <3>;
+ tgu-conditions = <4>;
+ tgu-regs = <8>;
+ tgu-timer-counters = <8>;
+ interrupts = <0 53 1>, <0 54 1>, <0 55 1>, <0 56 1>;
+ coresight-name = "coresight-tgu-apss";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ csr: csr@8001000 {
+ compatible = "qcom,coresight-csr";
+ reg = <0x8001000 0x1000>;
+ reg-names = "csr-base";
+
+ coresight-name = "coresight-csr";
+ qcom,usb-bam-support;
+ qcom,hwctrl-set-support;
+ qcom,set-byte-cntr-support;
+
+ qcom,blk-size = <1>;
+ };
+
+ swao_csr: csr@8a03000 {
+ compatible = "qcom,coresight-csr";
+ reg = <0x8a03000 0x1000>;
+ reg-names = "csr-base";
+
+ coresight-name = "coresight-swao-csr";
+
+ qcom,timestamp-support;
+ qcom,aodbg-csr-support;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ qcom,blk-size = <1>;
+ };
+
+ stm: stm@8002000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb962>;
+
+ reg = <0x8002000 0x1000>,
+ <0xe280000 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ coresight-name = "coresight-stm";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ port {
+ stm_out_funnel_in0: endpoint {
+ remote-endpoint = <&funnel_in0_in_stm>;
+ };
+ };
+
+ };
+
+ tpdm_center: tpdm@8b58000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8b58000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-center";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_dl_ct_out_tpda0: endpoint {
+ remote-endpoint =
+ <&tpda0_in_tpdm_dl_ct>;
+ };
+ };
+ };
+
+ tpdm_gpu: tpdm@8940000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8940000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-gpu";
+ status = "disabled";
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_gpu_out_funnel_gpu: endpoint {
+ remote-endpoint =
+ <&funnel_gpu_in_tpdm_gpu>;
+ };
+ };
+ };
+
+ modem_rfxe: modem_rfxe {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-modem-rfxe";
+ qcom,dummy-source;
+
+ port {
+ modem_rxfe_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_modem_rxfe>;
+ };
+ };
+ };
+
+ audio_etm0: audio_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+ coresight-name = "coresight-audio-etm0";
+
+ qcom,inst-id = <5>;
+
+ port {
+ audio_etm0_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_audio_etm0>;
+ };
+ };
+ };
+
+ tpdm_lpass_lpi: tpdm@8a26000 {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-tpdm-lpass-lpi";
+ qcom,dummy-source;
+
+ port {
+ tpdm_lpass_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_tpdm_lpass>;
+ };
+ };
+ };
+
+ tpdm_vsense: tpdm@8840000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8840000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-vsense";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_vsense_out_tpda7: endpoint {
+ remote-endpoint =
+ <&tpda7_in_tpdm_vsense>;
+ };
+ };
+ };
+
+ tpdm_dcc: tpdm@8870000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8870000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dcc";
+
+ qcom,hw-enable-check;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_dcc_out_tpda8: endpoint {
+ remote-endpoint =
+ <&tpda8_in_tpdm_dcc>;
+ };
+ };
+ };
+
+ tpdm_prng: tpdm@884c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x884c000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-prng";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_prng_out_tpda10: endpoint {
+ remote-endpoint =
+ <&tpda10_in_tpdm_prng>;
+ };
+ };
+ };
+
+ tpdm_qm: tpdm@89d0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x89d0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-qm";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_qm_out_tpda12: endpoint {
+ remote-endpoint =
+ <&tpda12_in_tpdm_qm>;
+ };
+ };
+ };
+
+ tpdm_west: tpdm@8a58000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8a58000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-west";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_west_out_tpda13: endpoint {
+ remote-endpoint =
+ <&tpda13_in_tpdm_west>;
+ };
+ };
+ };
+
+ tpdm_pimem: tpdm@8850000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8850000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-pimem";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_pimem_out_tpda15: endpoint {
+ remote-endpoint =
+ <&tpda15_in_tpdm_pimem>;
+ };
+ };
+ };
+
+ tpdm_mapss: tpdm@8a01000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x8a01000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-mapss";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_mapss_out_tpda_mapss: endpoint {
+ remote-endpoint =
+ <&tpda_mapss_in_tpdm_mapss>;
+ };
+ };
+ };
+
+ tpdm_wcss: tpdm@899c000 {
+ compatible = "qcom,coresight-dummy";
+
+ coresight-name = "coresight-tpdm-wcss";
+ qcom,dummy-source;
+
+ port {
+ tpdm_wcss_silver_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_tpdm_wcss_silver>;
+ };
+ };
+ };
+
+ modem_etm0: modem_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+ coresight-name = "coresight-modem-etm0";
+
+ qcom,inst-id = <2>;
+
+ port {
+ modem_etm0_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_modem_etm0>;
+ };
+ };
+ };
+
+ etm0: etm@9040000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x9040000 0x1000>;
+ cpu = <&CPU0>;
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm0_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_etm0>;
+ };
+ };
+ };
+
+ etm1: etm@9140000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x9140000 0x1000>;
+ cpu = <&CPU1>;
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm1";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm1_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_etm1>;
+ };
+ };
+ };
+
+ etm2: etm@9240000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x9240000 0x1000>;
+ cpu = <&CPU2>;
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm2";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm2_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_etm2>;
+ };
+ };
+ };
+
+ etm3: etm@9340000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+ reg = <0x9340000 0x1000>;
+ cpu = <&CPU3>;
+ qcom,tupwr-disable;
+ coresight-name = "coresight-etm3";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ etm3_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_etm3>;
+ };
+ };
+ };
+
+ tpdm_actpm: tpd@9830000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x9830000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-actpm";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_actpm_out_tpda_actpm: endpoint {
+ remote-endpoint =
+ <&tpda_actpm_in_tpdm_actpm>;
+ };
+ };
+ };
+
+ tpdm_llm_silver: tpdm@98a0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x98a0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-llm-silver";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_llm_silver_out_tpda_llm_silver: endpoint {
+ remote-endpoint =
+ <&tpda_llm_silver_in_tpdm_llm_silver>;
+ };
+ };
+ };
+
+ tpdm_apss: tpdm@9860000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb968>;
+ reg = <0x9860000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-apss";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ port {
+ tpdm_apss_out_tpda_apss: endpoint {
+ remote-endpoint =
+ <&tpda_apss_in_tpdm_apss>;
+ };
+ };
+ };
+
+ funnel_apss0: funnel@9800000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x9800000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-apss0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_apss0_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_funnel_apss0>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_apss0_in_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm0_out_funnel_apss0>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_apss0_in_etm1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm1_out_funnel_apss0>;
+ };
+ };
+
+ port@3 {
+ reg = <2>;
+ funnel_apss0_in_etm2: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm2_out_funnel_apss0>;
+ };
+ };
+
+ port@4 {
+ reg = <3>;
+ funnel_apss0_in_etm3: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm3_out_funnel_apss0>;
+ };
+ };
+
+ port@5 {
+ reg = <4>;
+ funnel_apss0_in_tpda_actpm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_actpm_out_funnel_apss0>;
+ };
+ };
+
+ port@6 {
+ reg = <5>;
+ funnel_apss0_in_tpda_llm_silver: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_llm_silver_out_funnel_apss0>;
+ };
+ };
+
+ port@7 {
+ reg = <6>;
+ funnel_apss0_in_tpda_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_apss_out_funnel_apss0>;
+ };
+ };
+
+ };
+ };
+
+ tpda_actpm: tpda@9832000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x9832000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-actpm";
+
+ qcom,tpda-atid = <77>;
+ qcom,cmb-elem-size = <0 32>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_actpm_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_tpda_actpm>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_actpm_in_tpdm_actpm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_actpm_out_tpda_actpm>;
+ };
+ };
+ };
+ };
+
+ tpda_apss: tpda@9862000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x9862000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-apss";
+
+
+ qcom,tpda-atid = <66>;
+ qcom,dsb-elem-size = <0 32>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_apss_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_tpda_apss>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_apss_in_tpdm_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_apss_out_tpda_apss>;
+ };
+ };
+ };
+ };
+
+
+ tpda_llm_silver: tpda@98c0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x98c0000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-llm-silver";
+
+ qcom,tpda-atid = <72>;
+ qcom,cmb-elem-size = <0 32>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_llm_silver_out_funnel_apss0: endpoint {
+ remote-endpoint =
+ <&funnel_apss0_in_tpda_llm_silver>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_llm_silver_in_tpdm_llm_silver: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_llm_silver_out_tpda_llm_silver>;
+ };
+ };
+ };
+ };
+
+ tpda_mapss: tpda@8a04000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x8a04000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-mapss";
+
+ qcom,tpda-atid = <76>;
+ qcom,cmb-elem-size = <0 32>;
+ qcom,dsb-elem-size = <0 32>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_mapss_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_tpda_mapss>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda_mapss_in_tpdm_mapss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_mapss_out_tpda_mapss>;
+ };
+ };
+ };
+ };
+
+ funnel_gpu: funnel@8944000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x8944000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-gpu";
+ status = "disabled";
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_gpu_out_tpda1: endpoint {
+ remote-endpoint =
+ <&tpda1_in_funnel_gpu>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_gpu_in_tpdm_gpu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_gpu_out_funnel_gpu>;
+ };
+ };
+
+ };
+ };
+
+ tpda: tpda@8004000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb969>;
+ reg = <0x8004000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda";
+
+ qcom,tpda-atid = <65>;
+ qcom,dsb-elem-size = <0 32>,
+ <1 32>,
+ <5 32>,
+ <12 32>,
+ <13 32>,
+ <15 32>;
+ qcom,cmb-elem-size = <7 32>,
+ <8 32>,
+ <10 32>,
+ <15 64>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_tpda>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tpda0_in_tpdm_dl_ct: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dl_ct_out_tpda0>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ tpda1_in_funnel_gpu: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_gpu_out_tpda1>;
+ };
+ };
+
+ port@3 {
+ reg = <7>;
+ tpda7_in_tpdm_vsense: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_vsense_out_tpda7>;
+ };
+ };
+
+ port@4 {
+ reg = <8>;
+ tpda8_in_tpdm_dcc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dcc_out_tpda8>;
+ };
+ };
+
+ port@5 {
+ reg = <10>;
+ tpda10_in_tpdm_prng: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_prng_out_tpda10>;
+ };
+ };
+
+ port@6 {
+ reg = <12>;
+ tpda12_in_tpdm_qm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_qm_out_tpda12>;
+ };
+ };
+
+ port@7 {
+ reg = <13>;
+ tpda13_in_tpdm_west: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_west_out_tpda13>;
+ };
+ };
+
+ port@8 {
+ reg = <15>;
+ tpda15_in_tpdm_pimem: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_pimem_out_tpda15>;
+ };
+ };
+
+ };
+ };
+
+ funnel_qatb: funnel@8005000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x8005000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-qatb";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_qatb_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_funnel_qatb>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_qatb_in_tpda: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_out_funnel_qatb>;
+ };
+ };
+
+ port@2 {
+ reg = <5>;
+ funnel_qatb_in_tpdm_lpass: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_lpass_out_funnel_qatb>;
+ };
+ };
+
+ port@3 {
+ reg = <5>;
+ funnel_qatb_in_audio_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&audio_etm0_out_funnel_qatb>;
+ };
+ };
+ };
+ };
+
+ funnel_in0: funnel@8041000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x8041000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-in0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_in0_out_funnel_merg: endpoint {
+ remote-endpoint =
+ <&funnel_merg_in_funnel_in0>;
+ };
+ };
+
+ port@1 {
+ reg = <6>;
+ funnel_in0_in_funnel_qatb: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_qatb_out_funnel_in0>;
+ };
+ };
+
+ port@2 {
+ reg = <7>;
+ funnel_in0_in_stm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&stm_out_funnel_in0>;
+ };
+ };
+
+ };
+ };
+
+ funnel_in1: funnel@8042000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x8042000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-in1";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_in1_out_funnel_merg: endpoint {
+ remote-endpoint =
+ <&funnel_merg_in_funnel_in1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ funnel_in1_in_tpda_mapss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_mapss_out_funnel_in1>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ funnel_in1_in_modem_rxfe: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&modem_rxfe_out_funnel_in1>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ funnel_in1_in_tpdm_wcss_silver: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_wcss_silver_out_funnel_in1>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ funnel_in1_in_modem_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&modem_etm0_out_funnel_in1>;
+ };
+ };
+
+ port@5 {
+ reg = <6>;
+ funnel_in1_in_funnel_apss0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_apss0_out_funnel_in1>;
+ };
+ };
+
+ };
+ };
+
+ funnel_merg: funnel@8045000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+ reg = <0x8045000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-merg";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ funnel_merg_out_tmc_etf: endpoint {
+ remote-endpoint =
+ <&tmc_etf_in_funnel_merg>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ funnel_merg_in_funnel_in0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_in0_out_funnel_merg>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ funnel_merg_in_funnel_in1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_in1_out_funnel_merg>;
+ };
+ };
+
+ };
+ };
+
+ tmc_etf: tmc@8047000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+ reg = <0x8047000 0x1000>;
+ reg-names = "tmc-base";
+
+ coresight-name = "coresight-tmc-etf";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tmc_etf_out_replicator_qdss: endpoint {
+ remote-endpoint =
+ <&replicator_qdss_in_tmc_etf>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ tmc_etf_in_funnel_merg: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_merg_out_tmc_etf>;
+ };
+ };
+
+ };
+ };
+
+ replicator_qdss: replicator@8046000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+ reg = <0x8046000 0x1000>;
+ reg-names = "replicator-base";
+
+ coresight-name = "coresight-replicator-qdss";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ replicator_qdss_out_tmc_etr: endpoint {
+ remote-endpoint =
+ <&tmc_etr_in_replicator_qdss>;
+ };
+ };
+
+ port@1 {
+ reg = <0>;
+ replicator_qdss_in_tmc_etf: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tmc_etf_out_replicator_qdss>;
+ };
+ };
+
+ };
+ };
+
+ tmc_etr: tmc@8048000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+ reg = <0x8048000 0x1000>,
+ <0x8064000 0x15000>;
+ reg-names = "tmc-base","bam-base";
+
+ coresight-name = "coresight-tmc-etr";
+
+ iommus = <&apps_smmu 0x0180 0>,
+ <&apps_smmu 0x0160 0>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ arm,buffer-size = <0x400000>;
+ arm,scatter-gather;
+
+ coresight-ctis = <&cti0>;
+ coresight-csr = <&csr>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ interrupts = <GIC_SPI 429 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "byte-cntr-irq";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tmc_etr_in_replicator_qdss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&replicator_qdss_out_tmc_etr>;
+ };
+ };
+
+ };
+ };
+
+ cti_cortex_m3: cti@8b30000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8b30000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cortex_m3";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_apss_cti0: cti@98e0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x98e0000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss-cti0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_apss_cti1: cti@98f0000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x98f0000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss-cti1";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_wcss_cti0: cti@89a4000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x89a4000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-wcss-cti0";
+
+ status = "disabled";
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_wcss_cti1: cti@89a5000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x89a5000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-wcss-cti1";
+
+ status = "disabled";
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_wcss_cti2: cti@89a6000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x89a6000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-wcss-cti2";
+
+ status = "disabled";
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_lpass_lpi: cti@8a21000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8a21000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-lpass-lpi";
+
+ status = "disabled";
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_lpass_q6: cti@8a2b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8a2b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-lpass-q6";
+
+ status = "disabled";
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_mss_q6: cti@8833000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8833000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-mss-q6";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_isdb_gpu: cti@8941000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8941000 0x1000>;
+ reg-names = "cti-base";
+ coresight-name = "coresight-cti-isdb-gpu";
+
+ status = "disabled";
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_mapss: cti@8a02000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8a02000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-mapss";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct_cti0: cti@8b59000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8b59000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct-cti0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct_cti1: cti@8b5a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8b5a000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct-cti1";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct_cti2: cti@8b5b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8b5b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct-cti2";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti_dlct_cti3: cti@8b5c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8b5c000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-dlct-cti3";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti0: cti@8010000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8010000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti0";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti1: cti@8011000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8011000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti1";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti2: cti@8012000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8012000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti2";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti3: cti@8013000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8013000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti3";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti4: cti@8014000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8014000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti4";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti5: cti@8015000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8015000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti5";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti6: cti@8016000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8016000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti6";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti7: cti@8017000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8017000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti7";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti8: cti@8018000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8018000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti8";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti9: cti@8019000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x8019000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti9";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti10: cti@801a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x801a000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti10";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti11: cti@801b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x801b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti11";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti12: cti@801c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x801c000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti12";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti13: cti@801d000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x801d000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti13";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti14: cti@801e000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x801e000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti14";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+
+ cti15: cti@801f000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x801f000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti15";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-gdsc.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-gdsc.dtsi
new file mode 100755
index 0000000..34a178a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-gdsc.dtsi
@@ -0,0 +1,111 @@
+&soc {
+ /* GDSCs in GCC */
+ gcc_camss_top_gdsc: qcom,gdsc@1458004 {
+ compatible = "qcom,gdsc";
+ reg = <0x1458004 0x4>;
+ regulator-name = "gcc_camss_top_gdsc";
+ status = "disabled";
+ };
+
+ gcc_usb30_prim_gdsc: qcom,gdsc@141a004 {
+ compatible = "qcom,gdsc";
+ reg = <0x141a004 0x4>;
+ regulator-name = "gcc_usb30_prim_gdsc";
+ status = "disabled";
+ };
+
+ gcc_vcodec0_gdsc: qcom,gdsc@1458098 {
+ compatible = "qcom,gdsc";
+ reg = <0x1458098 0x4>;
+ regulator-name = "gcc_vcodec0_gdsc";
+ status = "disabled";
+ };
+
+ gcc_venus_gdsc: qcom,gdsc@145807c {
+ compatible = "qcom,gdsc";
+ reg = <0x145807c 0x4>;
+ regulator-name = "gcc_venus_gdsc";
+ status = "disabled";
+ };
+
+ hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 {
+ compatible = "qcom,gdsc";
+ reg = <0x147d074 0x4>;
+ regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc";
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 {
+ compatible = "qcom,gdsc";
+ reg = <0x147d078 0x4>;
+ regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc";
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 {
+ compatible = "qcom,gdsc";
+ reg = <0x147d060 0x4>;
+ regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@147d07c {
+ compatible = "qcom,gdsc";
+ reg = <0x147d07c 0x4>;
+ regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";
+ qcom,no-status-check-on-disable;
+ qcom,gds-timeout = <500>;
+ status = "disabled";
+ };
+
+ /* GDSCs in DISPCC */
+ mdss_core_gdsc: qcom,gdsc@5f03000 {
+ compatible = "qcom,gdsc";
+ reg = <0x5f03000 0x4>;
+ regulator-name = "mdss_core_gdsc";
+ proxy-supply = <&mdss_core_gdsc>;
+ qcom,proxy-consumer-enable;
+ status = "disabled";
+ };
+
+ /* GDSCs in GPUCC */
+ gpu_cx_hw_ctrl: syscon@5991540 {
+ compatible = "syscon";
+ reg = <0x5991540 0x4>;
+ };
+
+ gpu_gx_sw_reset: syscon@5991008 {
+ compatible = "syscon";
+ reg = <0x5991008 0x4>;
+ };
+
+ gpu_gx_domain_addr: syscon@5991508 {
+ compatible = "syscon";
+ reg = <0x5991508 0x4>;
+ };
+
+ gpu_cx_gdsc: qcom,gdsc@599106c {
+ compatible = "qcom,gdsc";
+ reg = <0x599106c 0x4>;
+ regulator-name = "gpu_cx_gdsc";
+ hw-ctl-addr = <&gpu_cx_hw_ctrl>;
+ qcom,no-status-check-on-disable;
+ status = "disabled";
+ };
+
+ gpu_gx_gdsc: qcom,gdsc@599100c {
+ compatible = "qcom,gdsc";
+ reg = <0x599100c 0x4>;
+ regulator-name = "gpu_gx_gdsc";
+ sw-reset = <&gpu_gx_sw_reset>;
+ domain-addr = <&gpu_gx_domain_addr>;
+ qcom,reset-aon-logic;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-gpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-gpu.dtsi
new file mode 100755
index 0000000..e5df1e3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-gpu.dtsi
@@ -0,0 +1,564 @@
+&soc {
+ pil_gpu: qcom,kgsl-hyp {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <13>;
+ qcom,firmware-name = "a702_zap";
+ qcom,mas-crypto = <&mas_crypto_c0>;
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-1123200000 {
+ opp-hz = /bits/ 64 <1123200000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ opp-921600000 {
+ opp-hz = /bits/ 64 <921600000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ opp-844800000 {
+ opp-hz = /bits/ 64 <844800000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ opp-672000000 {
+ opp-hz = /bits/ 64 <672000000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ opp-537600000 {
+ opp-hz = /bits/ 64 <537600000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ opp-355200000 {
+ opp-hz = /bits/ 64 <355200000>;
+ opp-microvolt = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+ };
+
+ msm_bus: qcom,kgsl-busmon {
+ label = "kgsl-busmon";
+ compatible = "qcom,kgsl-busmon";
+ operating-points-v2 = <&gpu_opp_table>;
+ };
+
+ gpu_bw_tbl: gpu-bw-tbl {
+ compatible = "operating-points-v2";
+
+ opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */
+
+ opp-100 { opp-hz = /bits/ 64 < 762 >; }; /* 1.100 MHz */
+
+ opp-200 { opp-hz = /bits/ 64 < 1525 >; }; /* 2.200 MHz */
+
+ opp-300 { opp-hz = /bits/ 64 < 2288 >; }; /* 3.300 MHz */
+
+ opp-451 { opp-hz = /bits/ 64 < 3440 >; }; /* 4.451 MHz */
+
+ opp-547 { opp-hz = /bits/ 64 < 4173 >; }; /* 5.547 MHz */
+
+ opp-681 { opp-hz = /bits/ 64 < 5195 >; }; /* 6.681 MHz */
+
+ opp-768 { opp-hz = /bits/ 64 < 5859 >; }; /* 7.768 MHz */
+
+ opp-1017 { opp-hz = /bits/ 64 < 7759 >; }; /* 8.1017 MHz */
+
+ opp-1353 { opp-hz = /bits/ 64 < 10322 >; }; /* 9.1353 MHz */
+
+ opp-1555 { opp-hz = /bits/ 64 < 11863 >; }; /* 10.1555 MHz */
+
+ opp-1804 { opp-hz = /bits/ 64 < 13763 >; }; /* 11.1804 MHz */
+ };
+
+ gpubw: qcom,gpubw {
+ compatible = "qcom,devbw";
+ governor = "bw_vbif";
+ qcom,src-dst-ports = <26 512>;
+ operating-points-v2 = <&gpu_bw_tbl>;
+ };
+
+ msm_gpu: qcom,kgsl-3d0@5900000 {
+ label = "kgsl-3d0";
+ compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
+ status = "ok";
+
+ reg = <0x5900000 0x90000>,
+ <0x5961000 0x800>;
+ reg-names = "kgsl_3d0_reg_memory", "cx_dbgc";
+
+ interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+
+ qcom,id = <0>;
+ qcom,chipid = <0x07000200>;
+
+ qcom,initial-pwrlevel = <6>;
+ qcom,idle-timeout = <80>;
+
+ qcom,ubwc-mode = <2>;
+ qcom,min-access-length = <64>;
+ qcom,highest-bank-bit = <14>;
+
+ /* size in bytes */
+ qcom,snapshot-size = <1048576>;
+
+ /* base addr, size */
+ qcom,gpu-qdss-stm = <0xe1c0000 0x40000>;
+ #cooling-cells = <2>;
+
+ clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>,
+ <&gcc GCC_BIMC_GPU_AXI_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&rpmcc RPM_SMD_BIMC_GPU_CLK>;
+
+ clock-names = "core_clk", "rbbmtimer_clk", "mem_clk",
+ "iface_clk", "mem_iface_clk", "gmu_clk",
+ "smmu_vote", "bimc_gpu_clk";
+
+ /* Bus Scale Settings */
+ qcom,gpubw-dev = <&gpubw>;
+ qcom,bus-control;
+ qcom,msm-bus,name = "grp3d";
+ qcom,msm-bus,num-cases = <12>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <26 512 0 0>,
+ <26 512 0 800000>, /* 1 bus=100 (LOW SVS) */
+ <26 512 0 1600000>, /* 2 bus=200 (LOW SVS) */
+ <26 512 0 2400000>, /* 3 bus=300 (LOW SVS) */
+ <26 512 0 3608000>, /* 4 bus=451 (LOW SVS) */
+ <26 512 0 4376000>, /* 5 bus=547 (LOW SVS) */
+ <26 512 0 5448000>, /* 6 bus=681 (SVS) */
+ <26 512 0 6144000>, /* 7 bus=768 (SVS) */
+ <26 512 0 8136000>, /* 8 bus=1017 (SVS_L1) */
+ <26 512 0 10824000>, /* 9 bus=1353 (NOM) */
+ <26 512 0 12440000>, /* 10 bus=1555 (NOM) */
+ <26 512 0 14432000>; /* 11 bus=1804 (TURBO) */
+
+ /* GDSC regulator names */
+ regulator-names = "vddcx", "vdd";
+ /* GDSC oxili regulators */
+ vddcx-supply = <&gpu_cx_gdsc>;
+ vdd-supply = <&gpu_gx_gdsc>;
+
+ /* CPU latency parameter */
+ qcom,pm-qos-active-latency = <422>;
+ qcom,pm-qos-wakeup-latency = <422>;
+
+ /* Enable context aware freq. scaling */
+ qcom,enable-ca-jump;
+ /* Context aware jump busy penalty in us */
+ qcom,ca-busy-penalty = <12000>;
+ /* Context aware jump target power level */
+ qcom,ca-target-pwrlevel = <5>;
+
+ nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cell-names = "speed_bin";
+
+ qcom,gpu-cx-ipeak {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,gpu-cx-ipeak";
+
+ qcom,gpu-cx-ipeak@0 {
+ qcom,gpu-cx-ipeak = <&cx_ipeak_lm 4>;
+ qcom,gpu-cx-ipeak-freq = <1017600000>;
+ };
+ };
+
+ /* GPU Mempools */
+ qcom,gpu-mempools {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,gpu-mempools";
+
+ /* 4K Page Pool configuration */
+ qcom,gpu-mempool@0 {
+ reg = <0>;
+ qcom,mempool-page-size = <4096>;
+ qcom,mempool-allocate;
+ };
+ /* 8K Page Pool configuration */
+ qcom,gpu-mempool@1 {
+ reg = <1>;
+ qcom,mempool-page-size = <8192>;
+ qcom,mempool-allocate;
+ };
+ /* 64K Page Pool configuration */
+ qcom,gpu-mempool@2 {
+ reg = <2>;
+ qcom,mempool-page-size = <65536>;
+ qcom,mempool-reserved = <256>;
+ };
+ /* 1M Page Pool configuration */
+ qcom,gpu-mempool@3 {
+ reg = <3>;
+ qcom,mempool-page-size = <1048576>;
+ qcom,mempool-reserved = <32>;
+ };
+ };
+
+ /* GPU Mempool configuration for low memory SKUs */
+ qcom,gpu-mempools-lowmem {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,gpu-mempools-lowmem";
+
+ /* 4K Page Pool configuration */
+ qcom,gpu-mempool@0 {
+ reg = <0>;
+ qcom,mempool-page-size = <4096>;
+ qcom,mempool-allocate;
+ };
+ /* 8K Page Pool configuration */
+ qcom,gpu-mempool@1 {
+ reg = <1>;
+ qcom,mempool-page-size = <8192>;
+ qcom,mempool-allocate;
+ };
+ /* 64K Page Pool configuration */
+ qcom,gpu-mempool@2 {
+ reg = <2>;
+ qcom,mempool-page-size = <65536>;
+ qcom,mempool-allocate;
+ qcom,mempool-max-pages = <256>;
+ };
+ /* 1M Page Pool configuration */
+ qcom,gpu-mempool@3 {
+ reg = <3>;
+ qcom,mempool-page-size = <1048576>;
+ qcom,mempool-allocate;
+ qcom,mempool-max-pages = <32>;
+ };
+ };
+
+
+ /* Power Levels
+ * Speed-bin zero is default speed bin.
+ * For rest of the speed bins, speed-bin value
+ * is calculated as FMAX/4.8 MHz round up to zero
+ * decimal places plus two margin to account for
+ * clock jitters.
+ */
+ qcom,gpu-pwrlevel-bins {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "qcom,gpu-pwrlevel-bins";
+
+ qcom,gpu-pwrlevels-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <0>;
+
+ qcom,initial-pwrlevel = <6>;
+ qcom,ca-target-pwrlevel = <5>;
+ qcom,gpu-bimc-interface-clk-freq = <768000000>;
+
+ /* TURBO_L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <1123200000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <1017600000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* NOM_L1 */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <921600000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <844800000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <672000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <9>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <537600000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <355200000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <236>;
+
+ qcom,initial-pwrlevel = <6>;
+ qcom,ca-target-pwrlevel = <5>;
+ qcom,gpu-bimc-interface-clk-freq = <768000000>;
+
+ /* TURBO_L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <1123200000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <1017600000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* NOM_L1 */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <921600000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <844800000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <672000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <9>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <537600000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <355200000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <178>;
+
+ qcom,initial-pwrlevel = <3>;
+ qcom,ca-target-pwrlevel = <2>;
+
+
+ /* NOM */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <844800000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <11>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <672000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <10>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <537600000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <8>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <355200000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <142>;
+
+ qcom,initial-pwrlevel = <2>;
+ qcom,ca-target-pwrlevel = <1>;
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <672000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <11>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <537600000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <5>;
+ qcom,bus-max = <9>;
+ };
+
+ /* LOW SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <355200000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <0>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+
+ };
+ };
+
+ kgsl_msm_iommu: qcom,kgsl-iommu@59a0000 {
+ compatible = "qcom,kgsl-smmu-v2";
+
+ reg = <0x59a0000 0x10000>;
+ qcom,protect = <0xa0000 0x10000>;
+
+ clocks = <&gcc GCC_BIMC_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>;
+
+ clock-names = "mem_clk", "mem_iface_clk", "smmu_vote";
+
+ qcom,retention;
+ qcom,hyp_secure_alloc;
+
+ gfx3d_user: gfx3d_user {
+ compatible = "qcom,smmu-kgsl-cb";
+ label = "gfx3d_user";
+ iommus = <&kgsl_smmu 0 1>;
+ qcom,iommu-dma = "disabled";
+ qcom,gpu-offset = <0xa8000>;
+ };
+
+ gfx3d_secure: gfx3d_secure {
+ compatible = "qcom,smmu-kgsl-cb";
+ label = "gfx3d_secure";
+ iommus = <&kgsl_smmu 2 0>;
+ qcom,iommu-dma = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-idp-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-idp-2gb.dts
new file mode 100755
index 0000000..6f36490
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-idp-2gb.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "scuba-low-ram.dtsi"
+#include "scuba-idp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IDP 2GB DDR";
+ compatible = "qcom,scuba-idp", "qcom,scuba", "qcom,idp";
+ qcom,msm-id = <441 0x10000>;
+ qcom,board-id = <34 0x400>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-idp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-idp-overlay.dts
new file mode 100755
index 0000000..3aea4f0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-idp-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "scuba-idp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IDP";
+ compatible = "qcom,scuba-idp", "qcom,scuba", "qcom,idp";
+ qcom,msm-id = <441 0x10000>, <471 0x10000>;
+ qcom,board-id = <34 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-idp-usbc-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-idp-usbc-2gb.dts
new file mode 100755
index 0000000..986c783
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-idp-usbc-2gb.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+#include "scuba-low-ram.dtsi"
+#include "scuba-idp.dtsi"
+#include "scuba-idp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IDP USBC Audio 2GB DDR";
+ compatible = "qcom,scuba-idp", "qcom,scuba", "qcom,idp";
+ qcom,msm-id = <441 0x10000>;
+ qcom,board-id = <34 0x401>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-idp-usbc-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-idp-usbc-overlay.dts
new file mode 100755
index 0000000..6cfc22f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-idp-usbc-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "scuba-idp.dtsi"
+#include "scuba-idp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IDP USBC Audio";
+ compatible = "qcom,scuba-idp", "qcom,scuba", "qcom,idp";
+ qcom,msm-id = <441 0x10000>;
+ qcom,board-id = <34 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-idp-usbc.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-idp-usbc.dts
new file mode 100755
index 0000000..dc18e1f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-idp-usbc.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "scuba.dtsi"
+#include "scuba-idp.dtsi"
+#include "scuba-idp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IDP USBC Audio";
+ compatible = "qcom,scuba-idp", "qcom,scuba", "qcom,idp";
+ qcom,board-id = <34 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-idp-usbc.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-idp-usbc.dtsi
new file mode 100755
index 0000000..5f3495c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-idp-usbc.dtsi
@@ -0,0 +1,14 @@
+&scuba_snd {
+ qcom,msm-mbhc-usbc-audio-supported = <1>;
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+};
+
+&adsp_loader {
+ adsp-fuse-not-supported = <1>;
+ adsp-fw-name = "adsp2";
+};
+
+&va_cdc_dma_0_tx {
+ qcom,msm-dai-is-island-supported = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-idp.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-idp.dts
new file mode 100755
index 0000000..c9983eb
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-idp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "scuba.dtsi"
+#include "scuba-idp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IDP";
+ compatible = "qcom,scuba-idp", "qcom,scuba", "qcom,idp";
+ qcom,board-id = <34 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-idp.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-idp.dtsi
new file mode 100755
index 0000000..5b4e457
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-idp.dtsi
@@ -0,0 +1,207 @@
+#include "scuba-audio-overlay.dtsi"
+#include "scuba-thermal-overlay.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include "scuba-sde-display.dtsi"
+#include "camera/scuba-camera-sensor-idp.dtsi"
+
+&soc {
+ scuba_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "qg-batterydata-alium-3600mah.dtsi"
+ #include "qg-batterydata-atl466271_3300mAh.dtsi"
+ };
+};
+
+&pm2250_rg_leds {
+ status = "ok";
+};
+
+&pm2250_qg {
+ qcom,battery-data = <&scuba_batterydata>;
+ qcom,qg-iterm-ma = <150>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+ qcom,tcss-enable;
+ qcom,fvss-enable;
+ qcom,fvss-vbatt-mv = <3500>;
+ qcom,bass-enable;
+};
+
+&sdhc_1 {
+ vdd-supply = <&L20A>;
+ qcom,vdd-voltage-level = <2856000 2856000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L14A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&L21A>;
+ qcom,vdd-voltage-level = <2960000 3300000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L4A>;
+ qcom,vdd-io-voltage-level = <1800000 2960000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&pm2250_charger {
+ interrupts-extended = <&tlmm 89 0>;
+ interrupt-names = "usb_id_irq";
+ qcom,usb-id-gpio = <&tlmm 89 0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_id_interrupt>;
+
+ qcom,auto-recharge-soc = <98>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,battery-data = <&scuba_batterydata>;
+ io-channels = <&pm2250_vadc ADC_USB_IN_V_16>,
+ <&pm2250_vadc ADC_CHG_TEMP>;
+ io-channel-names = "usb_in_voltage",
+ "chg_temp";
+ qcom,thermal-mitigation = <2000000 1500000 1000000 500000>;
+};
+
+&pm2250_pwm3 {
+ status = "ok";
+};
+
+&dsi_nt36525_truly_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm2250_pwm3 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+ qcom,platform-reset-gpio-always-on;
+ qcom,platform-en-gpio = <&tlmm 105 0>;
+};
+
+&dsi_td4330_truly_v2_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm2250_pwm3 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+ qcom,platform-en-gpio = <&tlmm 105 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm2250_pwm3 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 81 0>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+ qcom,platform-en-gpio = <&tlmm 105 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_nt36525_truly_video>;
+};
+
+&qupv3_se2_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="novatek,NVT-ts";
+
+ novatek@62 {
+ compatible = "novatek,NVT-ts";
+ reg = <0x62>;
+ status = "ok";
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+
+ novatek,reset-gpio = <&tlmm 71 0x00>;
+ novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+ panel = <&dsi_nt36525_truly_video>;
+ };
+
+ synaptics_tcm@20 {
+ compatible = "synaptics,tcm-i2c";
+ reg = <0x20>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+ synaptics,irq-gpio = <&tlmm 80 0x2008>;
+ synaptics,irq-on-state = <0>;
+ synaptics,reset-gpio = <&tlmm 71 0x00>;
+ synaptics,reset-on-state = <0>;
+ synaptics,reset-active-ms = <20>;
+ synaptics,reset-delay-ms = <200>;
+ synaptics,power-delay-ms = <200>;
+ synaptics,ubl-i2c-addr = <0x20>;
+ synaptics,extend_report;
+ synaptics,firmware-name = "synaptics_firmware_k.img";
+
+ panel = <&dsi_td4330_truly_v2_video &dsi_td4330_truly_v2_cmd>;
+ };
+};
+
+&qusb_phy0 {
+ extcon = <&pm2250_charger>;
+};
+
+&usb0 {
+ extcon = <&qusb_phy0>, <&eud>;
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 70 0x00>;
+ qcom,nq-ven = <&tlmm 69 0x00>;
+ qcom,nq-firm = <&tlmm 31 0x00>;
+ qcom,nq-clkreq = <&tlmm 86 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <70 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-ion.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-ion.dtsi
new file mode 100755
index 0000000..cba6f83
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-ion.dtsi
@@ -0,0 +1,35 @@
+&soc {
+ qcom,ion {
+ compatible = "qcom,msm-ion";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ system_heap: qcom,ion-heap@25 {
+ reg = <25>;
+ qcom,ion-heap-type = "SYSTEM";
+ };
+
+ system_secure_heap: qcom,ion-heap@9 {
+ reg = <9>;
+ qcom,ion-heap-type = "SYSTEM_SECURE";
+ };
+
+ qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */
+ reg = <10>;
+ memory-region = <&secure_display_memory>;
+ qcom,ion-heap-type = "HYP_CMA";
+ };
+
+ qcom,ion-heap@27 { /* QSEECOM HEAP */
+ reg = <27>;
+ memory-region = <&qseecom_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@19 { /* QSEECOM HEAP */
+ reg = <19>;
+ memory-region = <&qseecom_ta_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-2gb.dts
new file mode 100755
index 0000000..feafc02
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-2gb.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "scuba-iot-low-ram.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IOT 2GB DDR SoC";
+ compatible = "qcom,scuba-iot";
+ qcom,msm-id = <473 0x10000>;
+ qcom,board-id = <0 0x400>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-2gb.dts
new file mode 100755
index 0000000..d4d31bc
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-2gb.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "scuba-iot-low-ram.dtsi"
+#include "scuba-iot-idp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IOT IDP 2GB DDR";
+ compatible = "qcom,scuba-idp", "qcom,scuba-iot", "qcom,idp";
+ qcom,msm-id = <473 0x10000>;
+ qcom,board-id = <34 0x400>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-overlay.dts
new file mode 100755
index 0000000..96adfa6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "scuba-iot-idp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IOT IDP";
+ compatible = "qcom,scuba-idp", "qcom,scuba-iot", "qcom,idp";
+ qcom,msm-id = <473 0x10000>, <474 0x10000>;
+ qcom,board-id = <34 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-usbc-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-usbc-2gb.dts
new file mode 100755
index 0000000..e8f6b0e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-usbc-2gb.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+#include "scuba-iot-low-ram.dtsi"
+#include "scuba-iot-idp.dtsi"
+#include "scuba-iot-idp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IOT IDP USBC Audio 2GB DDR";
+ compatible = "qcom,scuba-idp", "qcom,scuba-iot", "qcom,idp";
+ qcom,msm-id = <473 0x10000>;
+ qcom,board-id = <34 0x401>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-usbc-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-usbc-overlay.dts
new file mode 100755
index 0000000..89f9223
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-usbc-overlay.dts
@@ -0,0 +1,13 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "scuba-iot-idp.dtsi"
+#include "scuba-iot-idp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IOT IDP USBC Audio";
+ compatible = "qcom,scuba-idp", "qcom,scuba-iot", "qcom,idp";
+ qcom,msm-id = <473 0x10000>;
+ qcom,board-id = <34 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-usbc.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-usbc.dts
new file mode 100755
index 0000000..7e32504
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-usbc.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "scuba-iot.dtsi"
+#include "scuba-iot-idp.dtsi"
+#include "scuba-iot-idp-usbc.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IOT IDP USBC Audio";
+ compatible = "qcom,scuba-idp", "qcom,scuba-iot", "qcom,idp";
+ qcom,board-id = <34 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-usbc.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-usbc.dtsi
new file mode 100755
index 0000000..5f3495c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp-usbc.dtsi
@@ -0,0 +1,14 @@
+&scuba_snd {
+ qcom,msm-mbhc-usbc-audio-supported = <1>;
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+};
+
+&adsp_loader {
+ adsp-fuse-not-supported = <1>;
+ adsp-fw-name = "adsp2";
+};
+
+&va_cdc_dma_0_tx {
+ qcom,msm-dai-is-island-supported = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp.dts
new file mode 100755
index 0000000..0ca687e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "scuba-iot.dtsi"
+#include "scuba-iot-idp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IOT IDP";
+ compatible = "qcom,scuba-idp", "qcom,scuba-iot", "qcom,idp";
+ qcom,board-id = <34 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp.dtsi
new file mode 100755
index 0000000..dc25aa5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-idp.dtsi
@@ -0,0 +1,208 @@
+#include "scuba-audio-overlay.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include "scuba-thermal-overlay.dtsi"
+#include "scuba-sde-display.dtsi"
+#include "camera/scuba-camera-sensor-idp.dtsi"
+
+&soc {
+ scuba_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "qg-batterydata-alium-3600mah.dtsi"
+ #include "qg-batterydata-atl466271_3300mAh.dtsi"
+ };
+};
+
+&pm2250_rg_leds {
+ status = "ok";
+};
+
+
+&pm2250_qg {
+ qcom,battery-data = <&scuba_batterydata>;
+ qcom,qg-iterm-ma = <150>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+ qcom,tcss-enable;
+ qcom,fvss-enable;
+ qcom,fvss-vbatt-mv = <3500>;
+ qcom,bass-enable;
+};
+
+&sdhc_1 {
+ vdd-supply = <&L20A>;
+ qcom,vdd-voltage-level = <2856000 2856000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L14A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&L21A>;
+ qcom,vdd-voltage-level = <2960000 3300000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L4A>;
+ qcom,vdd-io-voltage-level = <1800000 2960000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 88 GPIO_ACTIVE_LOW>;
+
+ status = "ok";
+};
+
+&pm2250_charger {
+ interrupts-extended = <&tlmm 89 0>;
+ interrupt-names = "usb_id_irq";
+ qcom,usb-id-gpio = <&tlmm 89 0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_id_interrupt>;
+
+ qcom,auto-recharge-soc = <98>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,battery-data = <&scuba_batterydata>;
+ io-channels = <&pm2250_vadc ADC_USB_IN_V_16>,
+ <&pm2250_vadc ADC_CHG_TEMP>;
+ io-channel-names = "usb_in_voltage",
+ "chg_temp";
+ qcom,thermal-mitigation = <2000000 1500000 1000000 500000>;
+};
+
+&pm2250_pwm3 {
+ status = "ok";
+};
+
+&dsi_nt36525_truly_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm2250_pwm3 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+ qcom,platform-reset-gpio-always-on;
+ qcom,platform-en-gpio = <&tlmm 105 0>;
+};
+
+&dsi_td4330_truly_v2_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm2250_pwm3 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+ qcom,platform-en-gpio = <&tlmm 105 0>;
+};
+
+&dsi_td4330_truly_v2_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm2250_pwm3 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-te-gpio = <&tlmm 81 0>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+ qcom,platform-en-gpio = <&tlmm 105 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_nt36525_truly_video>;
+};
+
+&qupv3_se2_i2c {
+ status = "okay";
+ qcom,i2c-touch-active="novatek,NVT-ts";
+
+ novatek@62 {
+ compatible = "novatek,NVT-ts";
+ reg = <0x62>;
+ status = "ok";
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+
+ novatek,reset-gpio = <&tlmm 71 0x00>;
+ novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+ panel = <&dsi_nt36525_truly_video>;
+ };
+
+ synaptics_tcm@20 {
+ compatible = "synaptics,tcm-i2c";
+ reg = <0x20>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+ synaptics,irq-gpio = <&tlmm 80 0x2008>;
+ synaptics,irq-on-state = <0>;
+ synaptics,reset-gpio = <&tlmm 71 0x00>;
+ synaptics,reset-on-state = <0>;
+ synaptics,reset-active-ms = <20>;
+ synaptics,reset-delay-ms = <200>;
+ synaptics,power-delay-ms = <200>;
+ synaptics,ubl-i2c-addr = <0x20>;
+ synaptics,extend_report;
+ synaptics,firmware-name = "synaptics_firmware_k.img";
+
+ panel = <&dsi_td4330_truly_v2_video &dsi_td4330_truly_v2_cmd>;
+ };
+};
+
+&qusb_phy0 {
+ extcon = <&pm2250_charger>;
+};
+
+&usb0 {
+ extcon = <&qusb_phy0>, <&eud>;
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 70 0x00>;
+ qcom,nq-ven = <&tlmm 69 0x00>;
+ qcom,nq-firm = <&tlmm 31 0x00>;
+ qcom,nq-clkreq = <&tlmm 86 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <70 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-low-ram.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-low-ram.dtsi
new file mode 100755
index 0000000..ece705c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-low-ram.dtsi
@@ -0,0 +1,47 @@
+#include "scuba-iot.dtsi"
+/ {
+ reserved-memory {
+ /delete-node/ removed_region@60000000;
+ /delete-node/ qseecom_region;
+ /delete-node/ qseecom_ta_region;
+ /delete-node/ disp_rdump_region@5c000000;
+
+ tz_removed_region: tz_removed_region@60000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x60000000 0x0 0x100000>;
+ };
+
+ pimem_removed_region: pimem_removed_region@60100000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x60100000 0x0 0x1e00000>;
+ };
+
+ qseecom_mem: qseecom_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ qseecom_ta_mem: qseecom_ta_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x400000>;
+ };
+ };
+};
+
+&soc {
+ qcom_seecom: qseecom@61800000 {
+ reg = <0x61800000 0x700000>;
+ };
+
+ qcom_smcinvoke: smcinvoke@61800000 {
+ reg = <0x61800000 0x700000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qcs.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qcs.dtsi
new file mode 100755
index 0000000..0ca3139
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qcs.dtsi
@@ -0,0 +1,9 @@
+&soc {
+ qcom,rmnet-ipa {
+ status = "disabled";
+ };
+};
+
+&ipa_hw {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-eldo-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-eldo-overlay.dts
new file mode 100755
index 0000000..67881c4
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-eldo-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "scuba-iot-qrd-eldo.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba QRD IOT ELDO";
+ compatible = "qcom,scuba-qrd", "qcom,scuba-iot", "qcom,qrd";
+ qcom,msm-id = <473 0x10000>, <474 0x10000>;
+ qcom,board-id = <0x2000B 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-eldo.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-eldo.dts
new file mode 100755
index 0000000..b71ee09
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-eldo.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "scuba-iot.dtsi"
+#include "scuba-iot-qrd-eldo.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IOT QRD ELDO";
+ compatible = "qcom,scuba-qrd", "qcom,scuba-iot", "qcom,qrd";
+ qcom,board-id = <0x2000B 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-eldo.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-eldo.dtsi
new file mode 100755
index 0000000..14431ec
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-eldo.dtsi
@@ -0,0 +1,34 @@
+#include "scuba-iot-qrd.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+&pm2250_gpios {
+ vdd_3p1_en {
+ vdd_3p1_en_default: vdd_3p1_en_default {
+ pins = "gpio9";
+ function = "normal";
+ output-enable;
+ input-disable;
+ bias-disable;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_MED>;
+ };
+ };
+};
+
+&soc {
+ vreg_usb_3p1: vreg_usb_3p1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_usb_3p1";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_3p1_en_default>;
+ gpio = <&pm2250_gpios 9 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ };
+};
+
+&qusb_phy0 {
+ vdda33-supply = <&vreg_usb_3p1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-non-eldo-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-non-eldo-overlay.dts
new file mode 100755
index 0000000..e202578
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-non-eldo-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "scuba-iot-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IOT QRD NON ELDO";
+ compatible = "qcom,scuba-qrd", "qcom,scuba-iot", "qcom,qrd";
+ qcom,msm-id = <473 0x10000>, <474 0x10000>;
+ qcom,board-id = <0x1000B 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-non-eldo.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-non-eldo.dts
new file mode 100755
index 0000000..196801d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd-non-eldo.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "scuba-iot.dtsi"
+#include "scuba-iot-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IOT QRD NON ELDO";
+ compatible = "qcom,scuba-qrd", "qcom,scuba-iot", "qcom,qrd";
+ qcom,board-id = <0x1000B 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd.dtsi
new file mode 100755
index 0000000..446f0d7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot-qrd.dtsi
@@ -0,0 +1,369 @@
+#include "scuba-audio-overlay.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include "scuba-thermal-overlay.dtsi"
+#include "scuba-sde-display.dtsi"
+#include "camera/scuba-camera-sensor-idp.dtsi"
+
+&soc {
+ scuba_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "qg-batterydata-alium-3600mah.dtsi"
+ #include "qg-batterydata-atl466271_3300mAh.dtsi"
+ };
+};
+
+&pm2250_qg {
+ qcom,battery-data = <&scuba_batterydata>;
+ qcom,qg-iterm-ma = <150>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+ qcom,tcss-enable;
+ qcom,fvss-enable;
+ qcom,fvss-vbatt-mv = <3500>;
+ qcom,bass-enable;
+};
+
+&sdhc_1 {
+ vdd-supply = <&L20A>;
+ qcom,vdd-voltage-level = <2856000 2856000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L14A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&scuba_snd {
+ qcom,model = "bengal-scubaqrd-snd-card";
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
+ qcom,wcn-btfm = <1>;
+ qcom,ext-disp-audio-rx = <0>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic4",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "SpkrMono WSA_IN", "AUX",
+ "TX SWR_MIC0", "ADC1_OUTPUT",
+ "TX SWR_MIC1", "ADC2_OUTPUT",
+ "TX SWR_MIC5", "ADC3_OUTPUT",
+ "TX SWR_MIC0", "VA_TX_SWR_CLK",
+ "TX SWR_MIC1", "VA_TX_SWR_CLK",
+ "TX SWR_MIC2", "VA_TX_SWR_CLK",
+ "TX SWR_MIC3", "VA_TX_SWR_CLK",
+ "TX SWR_MIC4", "VA_TX_SWR_CLK",
+ "TX SWR_MIC5", "VA_TX_SWR_CLK",
+ "TX SWR_MIC6", "VA_TX_SWR_CLK",
+ "TX SWR_MIC7", "VA_TX_SWR_CLK",
+ "TX SWR_MIC8", "VA_TX_SWR_CLK",
+ "TX SWR_MIC9", "VA_TX_SWR_CLK",
+ "TX SWR_MIC10", "VA_TX_SWR_CLK",
+ "TX SWR_MIC11", "VA_TX_SWR_CLK",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "TX_AIF1 CAP", "VA_TX_SWR_CLK",
+ "TX_AIF2 CAP", "VA_TX_SWR_CLK",
+ "TX_AIF3 CAP", "VA_TX_SWR_CLK",
+ "VA SWR_MIC0", "ADC1_OUTPUT",
+ "VA SWR_MIC1", "ADC2_OUTPUT",
+ "VA SWR_MIC5", "ADC3_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ asoc-codec = <&stub_codec>, <&bolero>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec";
+ qcom,wsa-max-devs = <1>;
+ qcom,wsa-devs = <&wsa881x_i2c_e>;
+ qcom,wsa-aux-dev-prefix = "SpkrMono";
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&rouleur_codec>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&bolero>,
+ <&lpi_tlmm>;
+};
+
+&sdhc_2 {
+ vdd-supply = <&L21A>;
+ qcom,vdd-voltage-level = <2960000 3300000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L4A>;
+ qcom,vdd-io-voltage-level = <1800000 2960000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+
+ status = "ok";
+};
+
+&pm2250_charger {
+ qcom,auto-recharge-soc = <98>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,battery-data = <&scuba_batterydata>;
+ io-channels = <&pm2250_vadc ADC_USB_IN_V_16>,
+ <&pm2250_vadc ADC_CHG_TEMP>;
+ io-channel-names = "usb_in_voltage",
+ "chg_temp";
+ qcom,thermal-mitigation = <2000000 1500000 1000000 500000>;
+};
+
+&pm2250_pwm3 {
+ status = "ok";
+};
+
+&thermal_zones {
+ quiet-therm-usr {
+ polling-delay = <5000>;
+ };
+
+ quiet-therm-step {
+ polling-delay-passive = <2000>;
+ polling-delay = <5000>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm2250_adc_tm_iio ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ quiet_cpu0_trip: quiet-cpu0-trip {
+ temperature = <40000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ quiet_modem_trip0: quiet-modem-trip0 {
+ temperature = <40000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ quiet_modem_trip1: quiet-modem-trip1 {
+ temperature = <42000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ quiet_gpu_trip: quiet-gpu-trip {
+ temperature = <43000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ quiet_modem_trip2: quiet-modem-trip2 {
+ temperature = <43000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ quiet_modem_trip3: quiet-modem-trip3 {
+ temperature = <50000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ gpu-cdev {
+ trip = <&quiet_gpu_trip>;
+ cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT - 3)>;
+ };
+
+ cpu0-cdev {
+ trip = <&quiet_cpu0_trip>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT - 3)>;
+ };
+
+ modem-proc-cdev0 {
+ trip = <&quiet_modem_trip0>;
+ cooling-device = <&modem_proc 1 1>;
+ };
+
+ modem-proc-cdev1 {
+ trip = <&quiet_modem_trip3>;
+ cooling-device = <&modem_proc 3 3>;
+ };
+
+ modem-pa-cdev0 {
+ trip = <&quiet_modem_trip1>;
+ cooling-device = <&modem_pa 1 1>;
+ };
+
+ modem-pa-cdev1 {
+ trip = <&quiet_modem_trip2>;
+ cooling-device = <&modem_pa 2 2>;
+ };
+
+ modem-pa-cdev3 {
+ trip = <&quiet_modem_trip3>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+ };
+ };
+};
+
+&dsi_nt36525_truly_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm2250_pwm3 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+ qcom,platform-reset-gpio-always-on;
+ qcom,platform-en-gpio = <&tlmm 105 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_nt36525_truly_video>;
+};
+
+&qupv3_se2_i2c {
+ status = "ok";
+ qcom,i2c-touch-active = "novatek,NVT-ts";
+
+ novatek@62 {
+ compatible = "novatek,NVT-ts";
+ reg = <0x62>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+
+ novatek,reset-gpio = <&tlmm 71 0x00>;
+ novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+ panel = <&dsi_nt36525_truly_video>;
+ };
+};
+
+&qusb_phy0 {
+ extcon = <&pm2250_charger>;
+
+ qcom,qusb-phy-init-seq = <0xf8 0x80
+ 0xb3 0x84
+ 0x83 0x88
+ 0xc5 0x8c
+ 0x30 0x08
+ 0x79 0x0c
+ 0x21 0x10
+ 0x14 0x9c
+ 0x80 0x04
+ 0x9f 0x1c
+ 0x00 0x18>;
+};
+
+&usb0 {
+ extcon = <&qusb_phy0>, <&eud>;
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 70 0x00>;
+ qcom,nq-ven = <&tlmm 69 0x00>;
+ qcom,nq-firm = <&tlmm 31 0x00>;
+ qcom,nq-clkreq = <&tlmm 86 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <70 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&tlmm {
+ fpc_reset_int: fpc_reset_int {
+ fpc_reset_low: reset_low {
+ mux {
+ pins = "gpio104";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio104";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ fpc_reset_high: reset_high {
+ mux {
+ pins = "gpio104";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio104";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ fpc_int_low: int_low {
+ mux {
+ pins = "gpio97";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio97";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+ };
+ };
+};
+
+&soc {
+ fingerprint: fpc1020 {
+ compatible = "fpc,fpc1020";
+ interrupt-parent = <&tlmm>;
+ interrupts = <97 0>;
+ fpc,gpio_rst = <&tlmm 104 0>;
+ fpc,gpio_irq = <&tlmm 97 0>;
+ fpc,enable-on-boot;
+ pinctrl-names = "fpc1020_reset_reset",
+ "fpc1020_reset_active",
+ "fpc1020_irq_active";
+ pinctrl-0 = <&fpc_reset_low>;
+ pinctrl-1 = <&fpc_reset_high>;
+ pinctrl-2 = <&fpc_int_low>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-iot.dts
new file mode 100755
index 0000000..804c12b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "scuba-iot.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba IOT SoC";
+ compatible = "qcom,scuba-iot";
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-iot.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-iot.dtsi
new file mode 100755
index 0000000..ae5e6fb
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-iot.dtsi
@@ -0,0 +1,7 @@
+#include "scuba.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IOT SCUBA";
+ compatible = "qcom,scuba-iot";
+ qcom,msm-id = <473 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-low-ram.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-low-ram.dtsi
new file mode 100755
index 0000000..30f105a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-low-ram.dtsi
@@ -0,0 +1,56 @@
+#include "scuba.dtsi"
+/ {
+ reserved-memory {
+ /delete-node/ secure_display_region;
+ /delete-node/ removed_region@60000000;
+ /delete-node/ qseecom_region;
+ /delete-node/ qseecom_ta_region;
+ /delete-node/ disp_rdump_region@5c000000;
+
+ tz_removed_region: tz_removed_region@60000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x60000000 0x0 0x100000>;
+ };
+
+ pimem_removed_region: pimem_removed_region@60100000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x60100000 0x0 0x1e00000>;
+ };
+
+ qseecom_mem: qseecom_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ qseecom_ta_mem: qseecom_ta_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x400000>;
+ };
+
+ linux,cma {
+ size = <0x0 0x1000000>;
+ };
+ };
+};
+
+&soc {
+ qcom_seecom: qseecom@61800000 {
+ reg = <0x61800000 0x700000>;
+ };
+
+ qcom_smcinvoke: smcinvoke@61800000 {
+ reg = <0x61800000 0x700000>;
+ };
+
+ qcom,ion {
+ /delete-node/ qcom,ion-heap@10;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-lpi.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-lpi.dtsi
new file mode 100755
index 0000000..c38cae6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-lpi.dtsi
@@ -0,0 +1,1957 @@
+&q6core {
+ lpi_tlmm: lpi_pinctrl@0a7c0000 {
+ compatible = "qcom,lpi-pinctrl";
+ reg = <0x0a7c0000 0x0>;
+ qcom,slew-reg = <0x0a95a000 0x0>;
+ qcom,num-gpios = <19>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ qcom,lpi-offset-tbl = <0x00000000>, <0x00001000>,
+ <0x00002000>, <0x00003000>,
+ <0x00004000>, <0x00005000>,
+ <0x00006000>, <0x00007000>,
+ <0x00008000>, <0x00009000>,
+ <0x0000A000>, <0x0000B000>,
+ <0x0000C000>, <0x0000D000>,
+ <0x0000E000>, <0x0000F000>,
+ <0x00010000>, <0x00011000>,
+ <0x00012000>;
+ qcom,lpi-slew-offset-tbl = <0x00000000>, <0x00000002>,
+ <0x00000004>, <0x00000008>,
+ <0x0000000A>, <0x0000000C>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000000>, <0x00000000>,
+ <0x00000014>;
+
+ clock-names = "lpass_audio_hw_vote";
+ clocks = <&lpass_audio_hw_vote 0>;
+
+ quat_mi2s_sck {
+ quat_mi2s_sck_sleep: quat_mi2s_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sck_active: quat_mi2s_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_ws {
+ quat_mi2s_ws_sleep: quat_mi2s_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_ws_active: quat_mi2s_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd0 {
+ quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd0_active: quat_mi2s_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd1 {
+ quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd1_active: quat_mi2s_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd2 {
+ quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd2_active: quat_mi2s_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_mi2s_sd3 {
+ quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_mi2s_sd3_active: quat_mi2s_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sck {
+ lpi_i2s1_sck_sleep: lpi_i2s1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sck_active: lpi_i2s1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_ws {
+ lpi_i2s1_ws_sleep: lpi_i2s1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_ws_active: lpi_i2s1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sd0 {
+ lpi_i2s1_sd0_sleep: lpi_i2s1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sd0_active: lpi_i2s1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s1_sd1 {
+ lpi_i2s1_sd1_sleep: lpi_i2s1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s1_sd1_active: lpi_i2s1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sck {
+ lpi_i2s2_sck_sleep: lpi_i2s2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sck_active: lpi_i2s2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_ws {
+ lpi_i2s2_ws_sleep: lpi_i2s2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_ws_active: lpi_i2s2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sd0 {
+ lpi_i2s2_sd0_sleep: lpi_i2s2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sd0_active: lpi_i2s2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s2_sd1 {
+ lpi_i2s2_sd1_sleep: lpi_i2s2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s2_sd1_active: lpi_i2s2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s3_sck {
+ lpi_i2s3_sck_sleep: lpi_i2s3_sck_sleep {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s3_sck_active: lpi_i2s3_sck_active {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s3_ws {
+ lpi_i2s3_ws_sleep: lpi_i2s3_ws_sleep {
+ mux {
+ pins = "gpio15";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio15";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s3_ws_active: lpi_i2s3_ws_active {
+ mux {
+ pins = "gpio15";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio15";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s3_sd0 {
+ lpi_i2s3_sd0_sleep: lpi_i2s3_sd0_sleep {
+ mux {
+ pins = "gpio16";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s3_sd0_active: lpi_i2s3_sd0_active {
+ mux {
+ pins = "gpio16";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_i2s3_sd1 {
+ lpi_i2s3_sd1_sleep: lpi_i2s3_sd1_sleep {
+ mux {
+ pins = "gpio17";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_i2s3_sd1_active: lpi_i2s3_sd1_active {
+ mux {
+ pins = "gpio17";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sck {
+ quat_tdm_sck_sleep: quat_tdm_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sck_active: quat_tdm_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_ws {
+ quat_tdm_ws_sleep: quat_tdm_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_ws_active: quat_tdm_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd0 {
+ quat_tdm_sd0_sleep: quat_tdm_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd0_active: quat_tdm_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd1 {
+ quat_tdm_sd1_sleep: quat_tdm_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd1_active: quat_tdm_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd2 {
+ quat_tdm_sd2_sleep: quat_tdm_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd2_active: quat_tdm_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_tdm_sd3 {
+ quat_tdm_sd3_sleep: quat_tdm_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_tdm_sd3_active: quat_tdm_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sck {
+ lpi_tdm1_sck_sleep: lpi_tdm1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sck_active: lpi_tdm1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_ws {
+ lpi_tdm1_ws_sleep: lpi_tdm1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_ws_active: lpi_tdm1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sd0 {
+ lpi_tdm1_sd0_sleep: lpi_tdm1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sd0_active: lpi_tdm1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm1_sd1 {
+ lpi_tdm1_sd1_sleep: lpi_tdm1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm1_sd1_active: lpi_tdm1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sck {
+ lpi_tdm2_sck_sleep: lpi_tdm2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sck_active: lpi_tdm2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_ws {
+ lpi_tdm2_ws_sleep: lpi_tdm2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_ws_active: lpi_tdm2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sd0 {
+ lpi_tdm2_sd0_sleep: lpi_tdm2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sd0_active: lpi_tdm2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm2_sd1 {
+ lpi_tdm2_sd1_sleep: lpi_tdm2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm2_sd1_active: lpi_tdm2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm3_sck {
+ lpi_tdm3_sck_sleep: lpi_tdm3_sck_sleep {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm3_sck_active: lpi_tdm3_sck_active {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm3_ws {
+ lpi_tdm3_ws_sleep: lpi_tdm3_ws_sleep {
+ mux {
+ pins = "gpio15";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio15";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm3_ws_active: lpi_tdm3_ws_active {
+ mux {
+ pins = "gpio15";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio15";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm3_sd0 {
+ lpi_tdm3_sd0_sleep: lpi_tdm3_sd0_sleep {
+ mux {
+ pins = "gpio16";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm3_sd0_active: lpi_tdm3_sd0_active {
+ mux {
+ pins = "gpio16";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_tdm3_sd1 {
+ lpi_tdm3_sd1_sleep: lpi_tdm3_sd1_sleep {
+ mux {
+ pins = "gpio17";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_tdm3_sd1_active: lpi_tdm3_sd1_active {
+ mux {
+ pins = "gpio17";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sck {
+ quat_aux_sck_sleep: quat_aux_sck_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sck_active: quat_aux_sck_active {
+ mux {
+ pins = "gpio0";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_ws {
+ quat_aux_ws_sleep: quat_aux_ws_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_ws_active: quat_aux_ws_active {
+ mux {
+ pins = "gpio1";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd0 {
+ quat_aux_sd0_sleep: quat_aux_sd0_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd0_active: quat_aux_sd0_active {
+ mux {
+ pins = "gpio2";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd1 {
+ quat_aux_sd1_sleep: quat_aux_sd1_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd1_active: quat_aux_sd1_active {
+ mux {
+ pins = "gpio3";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd2 {
+ quat_aux_sd2_sleep: quat_aux_sd2_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd2_active: quat_aux_sd2_active {
+ mux {
+ pins = "gpio4";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ quat_aux_sd3 {
+ quat_aux_sd3_sleep: quat_aux_sd3_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ quat_aux_sd3_active: quat_aux_sd3_active {
+ mux {
+ pins = "gpio5";
+ function = "func3";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sck {
+ lpi_aux1_sck_sleep: lpi_aux1_sck_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sck_active: lpi_aux1_sck_active {
+ mux {
+ pins = "gpio6";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_ws {
+ lpi_aux1_ws_sleep: lpi_aux1_ws_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_ws_active: lpi_aux1_ws_active {
+ mux {
+ pins = "gpio7";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sd0 {
+ lpi_aux1_sd0_sleep: lpi_aux1_sd0_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sd0_active: lpi_aux1_sd0_active {
+ mux {
+ pins = "gpio8";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux1_sd1 {
+ lpi_aux1_sd1_sleep: lpi_aux1_sd1_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux1_sd1_active: lpi_aux1_sd1_active {
+ mux {
+ pins = "gpio9";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sck {
+ lpi_aux2_sck_sleep: lpi_aux2_sck_sleep {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sck_active: lpi_aux2_sck_active {
+ mux {
+ pins = "gpio10";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_ws {
+ lpi_aux2_ws_sleep: lpi_aux2_ws_sleep {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_ws_active: lpi_aux2_ws_active {
+ mux {
+ pins = "gpio11";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio11";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sd0 {
+ lpi_aux2_sd0_sleep: lpi_aux2_sd0_sleep {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sd0_active: lpi_aux2_sd0_active {
+ mux {
+ pins = "gpio12";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio12";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux2_sd1 {
+ lpi_aux2_sd1_sleep: lpi_aux2_sd1_sleep {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux2_sd1_active: lpi_aux2_sd1_active {
+ mux {
+ pins = "gpio13";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio13";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux3_sck {
+ lpi_aux3_sck_sleep: lpi_aux3_sck_sleep {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux3_sck_active: lpi_aux3_sck_active {
+ mux {
+ pins = "gpio14";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio14";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux3_ws {
+ lpi_aux3_ws_sleep: lpi_aux3_ws_sleep {
+ mux {
+ pins = "gpio15";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio15";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux3_ws_active: lpi_aux3_ws_active {
+ mux {
+ pins = "gpio15";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio15";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux3_sd0 {
+ lpi_aux3_sd0_sleep: lpi_aux3_sd0_sleep {
+ mux {
+ pins = "gpio16";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux3_sd0_active: lpi_aux3_sd0_active {
+ mux {
+ pins = "gpio16";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ lpi_aux3_sd1 {
+ lpi_aux3_sd1_sleep: lpi_aux3_sd1_sleep {
+ mux {
+ pins = "gpio17";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* PULL DOWN */
+ input-enable;
+ };
+ };
+
+ lpi_aux3_sd1_active: lpi_aux3_sd1_active {
+ mux {
+ pins = "gpio17";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio17";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable; /* NO PULL */
+ output-high;
+ };
+ };
+ };
+
+ tx_swr_clk_sleep: tx_swr_clk_sleep {
+ mux {
+ pins = "gpio0";
+ function = "func1";
+ input-enable;
+ bias-pull-down;
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <10>;
+ };
+ };
+
+ tx_swr_clk_active: tx_swr_clk_active {
+ mux {
+ pins = "gpio0";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio0";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-disable;
+ };
+ };
+
+ tx_swr_data1_sleep: tx_swr_data1_sleep {
+ mux {
+ pins = "gpio1";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <10>;
+ input-enable;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_data1_active: tx_swr_data1_active {
+ mux {
+ pins = "gpio1";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio1";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ tx_swr_data2_sleep: tx_swr_data2_sleep {
+ mux {
+ pins = "gpio2";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <10>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ tx_swr_data2_active: tx_swr_data2_active {
+ mux {
+ pins = "gpio2";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio2";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_clk_sleep: rx_swr_clk_sleep {
+ mux {
+ pins = "gpio3";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <10>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_clk_active: rx_swr_clk_active {
+ mux {
+ pins = "gpio3";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio3";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-disable;
+ };
+ };
+
+ rx_swr_data_sleep: rx_swr_data_sleep {
+ mux {
+ pins = "gpio4";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <10>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_data_active: rx_swr_data_active {
+ mux {
+ pins = "gpio4";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio4";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ rx_swr_data1_sleep: rx_swr_data1_sleep {
+ mux {
+ pins = "gpio5";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <10>;
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ rx_swr_data1_active: rx_swr_data1_active {
+ mux {
+ pins = "gpio5";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio5";
+ drive-strength = <10>;
+ slew-rate = <3>;
+ bias-bus-hold;
+ };
+ };
+
+ cdc_dmic01_clk_active: dmic01_clk_active {
+ mux {
+ pins = "gpio6";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic01_clk_sleep: dmic01_clk_sleep {
+ mux {
+ pins = "gpio6";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio6";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic01_data_active: dmic01_data_active {
+ mux {
+ pins = "gpio7";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic01_data_sleep: dmic01_data_sleep {
+ mux {
+ pins = "gpio7";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio7";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ cdc_dmic23_clk_active: dmic23_clk_active {
+ mux {
+ pins = "gpio8";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic23_clk_sleep: dmic23_clk_sleep {
+ mux {
+ pins = "gpio8";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio8";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic23_data_active: dmic23_data_active {
+ mux {
+ pins = "gpio9";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic23_data_sleep: dmic23_data_sleep {
+ mux {
+ pins = "gpio9";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+
+ wsa_mclk_sleep: wsa_mclk_sleep {
+ mux {
+ pins = "gpio18";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio18";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ };
+ };
+
+ wsa_mclk_active: wsa_mclk_active {
+ mux {
+ pins = "gpio18";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio18";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-pinctrl.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-pinctrl.dtsi
new file mode 100755
index 0000000..ee398146
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-pinctrl.dtsi
@@ -0,0 +1,1138 @@
+&soc {
+ tlmm: pinctrl@500000 {
+ compatible = "qcom,scuba-pinctrl";
+ reg = <0x500000 0x300000>;
+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ wakeup-parent = <&wakegpio>;
+ irqdomain-map = <0 0 &wakegpio 84 0>,
+ <3 0 &wakegpio 75 0>,
+ <4 0 &wakegpio 16 0>,
+ <6 0 &wakegpio 59 0>,
+ <8 0 &wakegpio 63 0>,
+ <11 0 &wakegpio 17 0>,
+ <13 0 &wakegpio 18 0>,
+ <14 0 &wakegpio 51 0>,
+ <17 0 &wakegpio 20 0>,
+ <18 0 &wakegpio 52 0>,
+ <19 0 &wakegpio 53 0>,
+ <24 0 &wakegpio 6 0>,
+ <25 0 &wakegpio 71 0>,
+ <27 0 &wakegpio 73 0>,
+ <28 0 &wakegpio 41 0>,
+ <31 0 &wakegpio 27 0>,
+ <32 0 &wakegpio 54 0>,
+ <33 0 &wakegpio 55 0>,
+ <34 0 &wakegpio 56 0>,
+ <35 0 &wakegpio 57 0>,
+ <36 0 &wakegpio 58 0>,
+ <39 0 &wakegpio 28 0>,
+ <46 0 &wakegpio 29 0>,
+ <62 0 &wakegpio 60 0>,
+ <63 0 &wakegpio 61 0>,
+ <64 0 &wakegpio 62 0>,
+ <69 0 &wakegpio 33 0>,
+ <70 0 &wakegpio 34 0>,
+ <72 0 &wakegpio 72 0>,
+ <75 0 &wakegpio 35 0>,
+ <79 0 &wakegpio 36 0>,
+ <80 0 &wakegpio 21 0>,
+ <81 0 &wakegpio 38 0>,
+ <86 0 &wakegpio 19 0>,
+ <87 0 &wakegpio 42 0>,
+ <88 0 &wakegpio 43 0>,
+ <89 0 &wakegpio 45 0>,
+ <91 0 &wakegpio 74 0>,
+ <94 0 &wakegpio 47 0>,
+ <95 0 &wakegpio 48 0>,
+ <96 0 &wakegpio 49 0>,
+ <97 0 &wakegpio 50 0>;
+ irqdomain-map-pass-thru = <0 0xff>;
+ irqdomain-map-mask = <0xff 0>;
+
+ qupv3_se4_2uart_pins: qupv3_se4_2uart_pins {
+ qupv3_se4_2uart_active: qupv3_se4_2uart_active {
+ mux {
+ pins = "gpio12", "gpio13";
+ function = "qup4";
+ };
+
+ config {
+ pins = "gpio12", "gpio13";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep {
+ mux {
+ pins = "gpio12", "gpio13";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio12", "gpio13";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+ /* SDC pin type */
+ sdc1_clk_on: sdc1_clk_on {
+ config {
+ pins = "sdc1_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc1_clk_off: sdc1_clk_off {
+ config {
+ pins = "sdc1_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_cmd_on: sdc1_cmd_on {
+ config {
+ pins = "sdc1_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc1_cmd_off: sdc1_cmd_off {
+ config {
+ pins = "sdc1_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_data_on: sdc1_data_on {
+ config {
+ pins = "sdc1_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc1_data_off: sdc1_data_off {
+ config {
+ pins = "sdc1_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_rclk_on: sdc1_rclk_on {
+ config {
+ pins = "sdc1_rclk";
+ bias-pull-down; /* pull down */
+ };
+ };
+
+ sdc1_rclk_off: sdc1_rclk_off {
+ config {
+ pins = "sdc1_rclk";
+ bias-pull-down; /* pull down */
+ };
+ };
+
+ sdc2_clk_on: sdc2_clk_on {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc2_clk_off: sdc2_clk_off {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_cmd_on: sdc2_cmd_on {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_cmd_off: sdc2_cmd_off {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_data_on: sdc2_data_on {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_data_off: sdc2_data_off {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_cd_on: cd_on {
+ mux {
+ pins = "gpio88";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio88";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_cd_off: cd_off {
+ mux {
+ pins = "gpio88";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio88";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ /* WSA speaker reset pin1 */
+ spkr_1_sd_n {
+ spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+ mux {
+ pins = "gpio106";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio106";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_1_sd_n_active: spkr_1_sd_n_active {
+ mux {
+ pins = "gpio106";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio106";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ fsa_usbc_ana_en_n@102 {
+ fsa_usbc_ana_en: fsa_usbc_ana_en {
+ mux {
+ pins = "gpio102";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio102";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+ };
+
+ qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
+ qupv3_se0_i2c_active: qupv3_se0_i2c_active {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "qup0";
+ };
+
+ config {
+ pins = "gpio0", "gpio1";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio0", "gpio1";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se0_spi_pins: qupv3_se0_spi_pins {
+ qupv3_se0_spi_active: qupv3_se0_spi_active {
+ mux {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ function = "qup0";
+ };
+
+ config {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
+ mux {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
+ qupv3_se1_i2c_active: qupv3_se1_i2c_active {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "qup1";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ nfc {
+ nfc_int_active: nfc_int_active {
+ /* active state */
+ mux {
+ /* GPIO 70 NFC Read Interrupt */
+ pins = "gpio70";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio70";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_int_suspend: nfc_int_suspend {
+ /* sleep state */
+ mux {
+ /* GPIO 70 NFC Read Interrupt */
+ pins = "gpio70";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio70";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_enable_active: nfc_enable_active {
+ /* active state */
+ mux {
+ /* 69: Enable 31: Firmware */
+ pins = "gpio69", "gpio31";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio69", "gpio31";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_enable_suspend: nfc_enable_suspend {
+ /* sleep state */
+ mux {
+ /* 69: Enable 31: Firmware */
+ pins = "gpio69", "gpio31";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio69", "gpio31";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable;
+ };
+ };
+
+ nfc_clk_req_active: nfc_clk_req_active {
+ /* active state */
+ mux {
+ /* GPIO 86: NFC CLOCK REQUEST */
+ pins = "gpio86";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio86";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_clk_req_suspend: nfc_clk_req_suspend {
+ /* sleep state */
+ mux {
+ /* GPIO 86: NFC CLOCK REQUEST */
+ pins = "gpio86";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio86";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se1_spi_pins: qupv3_se1_spi_pins {
+ qupv3_se1_spi_active: qupv3_se1_spi_active {
+ mux {
+ pins = "gpio4", "gpio5",
+ "gpio69", "gpio70";
+ function = "qup1";
+ };
+
+ config {
+ pins = "gpio4", "gpio5",
+ "gpio69", "gpio70";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
+ mux {
+ pins = "gpio4", "gpio5",
+ "gpio69", "gpio70";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio4", "gpio5",
+ "gpio69", "gpio70";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
+ qupv3_se2_i2c_active: qupv3_se2_i2c_active {
+ mux {
+ pins = "gpio6", "gpio7";
+ function = "qup2";
+ };
+
+ config {
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
+ mux {
+ pins = "gpio6", "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se2_spi_pins: qupv3_se2_spi_pins {
+ qupv3_se2_spi_active: qupv3_se2_spi_active {
+ mux {
+ pins = "gpio6", "gpio7",
+ "gpio71", "gpio80";
+ function = "qup2";
+ };
+
+ config {
+ pins = "gpio6", "gpio7",
+ "gpio71", "gpio80";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
+ mux {
+ pins = "gpio6", "gpio7",
+ "gpio71", "gpio80";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6", "gpio7",
+ "gpio71", "gpio80";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se3_4uart_pins: qupv3_se3_4uart_pins {
+ qupv3_se3_default_ctsrtsrx:
+ qupv3_se3_default_ctsrtsrx {
+ mux {
+ pins = "gpio8", "gpio9", "gpio11";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio8", "gpio9", "gpio11";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ qupv3_se3_default_tx:
+ qupv3_se3_default_tx {
+ mux {
+ pins = "gpio10";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se3_ctsrx: qupv3_se3_ctsrx {
+ mux {
+ pins = "gpio8", "gpio11";
+ function = "qup3";
+ };
+
+ config {
+ pins = "gpio8", "gpio11";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se3_rts: qupv3_se3_rts {
+ mux {
+ pins = "gpio9";
+ function = "qup3";
+ };
+
+ config {
+ pins = "gpio9";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ qupv3_se3_tx: qupv3_se3_tx {
+ mux {
+ pins = "gpio10";
+ function = "qup3";
+ };
+
+ config {
+ pins = "gpio10";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
+ qupv3_se5_i2c_active: qupv3_se5_i2c_active {
+ mux {
+ pins = "gpio14", "gpio15";
+ function = "qup5";
+ };
+
+ config {
+ pins = "gpio14", "gpio15";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
+ mux {
+ pins = "gpio14", "gpio15";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio14", "gpio15";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
+ qupv3_se5_spi_pins: qupv3_se5_spi_pins {
+ qupv3_se5_spi_active: qupv3_se5_spi_active {
+ mux {
+ pins = "gpio14", "gpio15",
+ "gpio16", "gpio17";
+ function = "qup5";
+ };
+
+ config {
+ pins = "gpio14", "gpio15",
+ "gpio16", "gpio17";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
+ mux {
+ pins = "gpio14", "gpio15",
+ "gpio16", "gpio17";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio14", "gpio15",
+ "gpio16", "gpio17";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+ pmx_sde: pmx_sde {
+ sde_dsi_active: sde_dsi_active {
+ mux {
+ pins = "gpio82", "gpio105";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio82", "gpio105";
+ drive-strength = <8>;
+ bias-disable = <0>;
+ };
+ };
+
+ sde_dsi_suspend: sde_dsi_suspend {
+ mux {
+ pins = "gpio82", "gpio105";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio82", "gpio105";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_sde_te {
+ sde_te_active: sde_te_active {
+ mux {
+ pins = "gpio81";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio81";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ sde_te_suspend: sde_te_suspend {
+ mux {
+ pins = "gpio81";
+ function = "mdp_vsync";
+ };
+
+ config {
+ pins = "gpio81";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_int_active {
+ ts_int_active: ts_int_active {
+ mux {
+ pins = "gpio80";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio80";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_int_suspend {
+ ts_int_suspend: ts_int_suspend {
+ mux {
+ pins = "gpio80";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio80";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_reset_active {
+ ts_reset_active: ts_reset_active {
+ mux {
+ pins = "gpio71";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio71";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_reset_suspend {
+ ts_reset_suspend: ts_reset_suspend {
+ mux {
+ pins = "gpio71";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio71";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pmx_ts_release {
+ ts_release: ts_release {
+ mux {
+ pins = "gpio80", "gpio71";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio80", "gpio71";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+
+ pm8008_interrupt: pm8008_interrupt {
+ mux {
+ pins = "gpio25";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio25";
+ bias-disable;
+ input-enable;
+ };
+ };
+
+ pm8008_active: pm8008_active {
+ mux {
+ pins = "gpio26";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio26";
+ bias-pull-up;
+ output-high;
+ drive-strength = <2>;
+ };
+ };
+
+ cci0_suspend: cci0_suspend {
+ mux {
+ /* CLK, DATA*/
+ pins = "gpio23", "gpio22";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio23", "gpio22";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci0_active: cci0_active {
+ mux {
+ /* CLK, DATA*/
+ pins = "gpio23", "gpio22";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio23", "gpio22";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci1_suspend: cci1_suspend {
+ mux {
+ /* CLK, DATA*/
+ pins = "gpio30", "gpio29";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio30", "gpio29";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci1_active: cci1_active {
+ mux {
+ /* CLK, DATA*/
+ pins = "gpio30", "gpio29";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio30", "gpio29";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk0_active: cam_sensor_mclk0_active {
+ /* MCLK 0*/
+ mux {
+ pins = "gpio20";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio20";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
+ /* MCLK 0*/
+ mux {
+ pins = "gpio20";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio20";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk1_active: cam_sensor_mclk1_active {
+ /* MCLK 1*/
+ mux {
+ pins = "gpio21";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio21";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
+ /* MCLK 1*/
+ mux {
+ pins = "gpio21";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio21";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk2_active: cam_sensor_mclk2_active {
+ /* MCLK 2*/
+ mux {
+ pins = "gpio27";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio27";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
+ /* MCLK 2*/
+ mux {
+ pins = "gpio27";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio27";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear0_reset_active: cam_sensor_rear0_reset_active {
+ /* RESET0 */
+ mux {
+ pins = "gpio18";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio18";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear0_reset_suspend: cam_sensor_rear0_reset_suspend {
+ /* RESET0 */
+ mux {
+ pins = "gpio18";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio18";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_rear1_reset_active: cam_sensor_rear1_reset_active {
+ /* RESET1 */
+ mux {
+ pins = "gpio19";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio19";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear1_reset_suspend: cam_sensor_rear1_reset_suspend {
+ /* RESET1 */
+ mux {
+ pins = "gpio19";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio19";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+
+ cam_sensor_front0_reset_active: cam_sensor_front0_reset_active {
+ /* RESET0 */
+ mux {
+ pins = "gpio24";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio24";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_front0_reset_suspend: cam_sensor_front0_reset_suspend {
+ /* RESET0 */
+ mux {
+ pins = "gpio24";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio24";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_csi_mux_oe_active: cam_sensor_csi_mux_oe_active {
+ /*CSIMUX_OE*/
+ mux {
+ pins = "gpio113";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio113";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_csi_mux_oe_suspend: cam_sensor_csi_mux_oe_suspend {
+ /* CSIMUX_OE */
+ mux {
+ pins = "gpio113";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio113";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ cam_sensor_csi_mux_sel_active: cam_sensor_csi_mux_sel_active {
+ /*CSIMUX_SEL*/
+ mux {
+ pins = "gpio114";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio114";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_csi_mux_sel_suspend: cam_sensor_csi_mux_sel_suspend {
+ /* CSIMUX_SEL */
+ mux {
+ pins = "gpio114";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio114";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ output-low;
+ };
+ };
+
+ gpio_vol_up: gpio_vol_up {
+ mux {
+ pins = "gpio96";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio96";
+ drive-strength = <2>;
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ usb_id_interrupt: usb_id_interrupt {
+ mux {
+ pins = "gpio89";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio89";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-pm.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-pm.dtsi
new file mode 100755
index 0000000..61c13bd
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-pm.dtsi
@@ -0,0 +1,85 @@
+&soc {
+
+ qcom,lpm-levels {
+ compatible = "qcom,lpm-levels";
+ qcom,use-psci;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,pm-cluster@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "l2";
+ qcom,psci-mode-shift = <4>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cluster-level@0 { /* D1 */
+ reg = <0>;
+ label = "l2-wfi";
+ qcom,psci-mode = <0x1>;
+ qcom,entry-latency-us = <38>;
+ qcom,exit-latency-us = <51>;
+ qcom,min-residency-us = <89>;
+ };
+
+ qcom,pm-cluster-level@1 { /* D4 */
+ reg = <1>;
+ label = "l2-rail-pc";
+ qcom,psci-mode = <0x4>;
+ qcom,entry-latency-us = <800>;
+ qcom,exit-latency-us = <2118>;
+ qcom,min-residency-us = <7376>;
+ qcom,min-child-idx = <1>;
+ qcom,is-reset;
+ qcom,notify-rpm;
+ };
+
+ qcom,pm-cpu {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+ qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ qcom,pm-cpu-level@0 { /* C1 */
+ reg = <0>;
+ label = "wfi";
+ qcom,psci-cpu-mode = <0x1>;
+ qcom,entry-latency-us = <49>;
+ qcom,exit-latency-us = <42>;
+ qcom,min-residency-us = <91>;
+ };
+
+ qcom,pm-cpu-level@1 { /* C3 */
+ reg = <1>;
+ label = "pc";
+ qcom,psci-cpu-mode = <0x3>;
+ qcom,entry-latency-us = <290>;
+ qcom,exit-latency-us = <376>;
+ qcom,min-residency-us = <1182>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+ };
+ };
+
+ };
+
+ qcom,rpm-stats@4600000 {
+ compatible = "qcom,rpm-stats";
+ reg = <0x04600000 0x1000>,
+ <0x04690014 0x4>,
+ <0x0469001c 0x4>;
+ reg-names = "phys_addr_base", "offset_addr",
+ "heap_phys_addrbase";
+ qcom,sleep-stats-version = <2>;
+ };
+
+ qcom,rpm-master-stats@45f0150 {
+ compatible = "qcom,rpm-master-stats";
+ reg = <0x45f0150 0x5000>;
+ qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ";
+ qcom,master-stats-version = <2>;
+ qcom,master-offset = <4096>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-eldo-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-eldo-overlay.dts
new file mode 100755
index 0000000..a9ae201
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-eldo-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "scuba-qrd-eldo.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba QRD ELDO";
+ compatible = "qcom,scuba-qrd", "qcom,scuba", "qcom,qrd";
+ qcom,msm-id = <441 0x10000>, <471 0x10000>;
+ qcom,board-id = <0x2000B 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-eldo.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-eldo.dts
new file mode 100755
index 0000000..95fdb5c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-eldo.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "scuba.dtsi"
+#include "scuba-qrd-eldo.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba QRD ELDO";
+ compatible = "qcom,scuba-qrd", "qcom,scuba", "qcom,qrd";
+ qcom,board-id = <0x2000B 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-eldo.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-eldo.dtsi
new file mode 100755
index 0000000..d3aed54
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-eldo.dtsi
@@ -0,0 +1,34 @@
+#include "scuba-qrd.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+
+&pm2250_gpios {
+ vdd_3p1_en {
+ vdd_3p1_en_default: vdd_3p1_en_default {
+ pins = "gpio9";
+ function = "normal";
+ output-enable;
+ input-disable;
+ bias-disable;
+ qcom,drive-strength = <PMIC_GPIO_STRENGTH_MED>;
+ };
+ };
+};
+
+&soc {
+ vreg_usb_3p1: vreg_usb_3p1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_usb_3p1";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_3p1_en_default>;
+ gpio = <&pm2250_gpios 9 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ };
+};
+
+&qusb_phy0 {
+ vdda33-supply = <&vreg_usb_3p1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-non-eldo-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-non-eldo-overlay.dts
new file mode 100755
index 0000000..ecb03db
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-non-eldo-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "scuba-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba QRD NON ELDO";
+ compatible = "qcom,scuba-qrd", "qcom,scuba", "qcom,qrd";
+ qcom,msm-id = <441 0x10000>, <471 0x10000>;
+ qcom,board-id = <0x1000B 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-non-eldo.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-non-eldo.dts
new file mode 100755
index 0000000..f6df860
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-qrd-non-eldo.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+
+#include "scuba.dtsi"
+#include "scuba-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba QRD NON ELDO";
+ compatible = "qcom,scuba-qrd", "qcom,scuba", "qcom,qrd";
+ qcom,board-id = <0x1000B 0>;
+};
+
+&qusb_phy0 {
+ notifier = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+ interrupts-extended = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+ interrupt-names = "notifier_irq";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-qrd.dtsi
new file mode 100755
index 0000000..427c8c7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-qrd.dtsi
@@ -0,0 +1,415 @@
+#include "scuba-audio-overlay.dtsi"
+#include "scuba-thermal-overlay.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/iio/qcom,spmi-vadc.h>
+#include "scuba-sde-display.dtsi"
+#include "camera/scuba-camera-sensor-idp.dtsi"
+
+&soc {
+ scuba_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "qg-batterydata-alium-3600mah.dtsi"
+ #include "qg-batterydata-atl466271_3300mAh.dtsi"
+ };
+};
+
+&pm2250_qg {
+ qcom,battery-data = <&scuba_batterydata>;
+ qcom,qg-iterm-ma = <150>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+ qcom,cl-feedback-on;
+ qcom,tcss-enable;
+ qcom,fvss-enable;
+ qcom,fvss-vbatt-mv = <3500>;
+ qcom,bass-enable;
+};
+
+&sdhc_1 {
+ vdd-supply = <&L20A>;
+ qcom,vdd-voltage-level = <2856000 2856000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L14A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&scuba_snd {
+ qcom,model = "bengal-scubaqrd-snd-card";
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
+ qcom,wcn-btfm = <1>;
+ qcom,ext-disp-audio-rx = <0>;
+ qcom,audio-routing =
+ "AMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Analog Mic1",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Analog Mic2",
+ "AMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic3",
+ "AMIC4", "MIC BIAS3",
+ "MIC BIAS3", "Analog Mic4",
+ "IN1_HPHL", "HPHL_OUT",
+ "IN2_HPHR", "HPHR_OUT",
+ "IN3_AUX", "AUX_OUT",
+ "SpkrMono WSA_IN", "AUX",
+ "TX SWR_MIC0", "ADC1_OUTPUT",
+ "TX SWR_MIC1", "ADC2_OUTPUT",
+ "TX SWR_MIC5", "ADC3_OUTPUT",
+ "TX SWR_MIC0", "VA_TX_SWR_CLK",
+ "TX SWR_MIC1", "VA_TX_SWR_CLK",
+ "TX SWR_MIC2", "VA_TX_SWR_CLK",
+ "TX SWR_MIC3", "VA_TX_SWR_CLK",
+ "TX SWR_MIC4", "VA_TX_SWR_CLK",
+ "TX SWR_MIC5", "VA_TX_SWR_CLK",
+ "TX SWR_MIC6", "VA_TX_SWR_CLK",
+ "TX SWR_MIC7", "VA_TX_SWR_CLK",
+ "TX SWR_MIC8", "VA_TX_SWR_CLK",
+ "TX SWR_MIC9", "VA_TX_SWR_CLK",
+ "TX SWR_MIC10", "VA_TX_SWR_CLK",
+ "TX SWR_MIC11", "VA_TX_SWR_CLK",
+ "RX_TX DEC0_INP", "TX DEC0 MUX",
+ "RX_TX DEC1_INP", "TX DEC1 MUX",
+ "RX_TX DEC2_INP", "TX DEC2 MUX",
+ "RX_TX DEC3_INP", "TX DEC3 MUX",
+ "TX_AIF1 CAP", "VA_TX_SWR_CLK",
+ "TX_AIF2 CAP", "VA_TX_SWR_CLK",
+ "TX_AIF3 CAP", "VA_TX_SWR_CLK",
+ "VA SWR_MIC0", "ADC1_OUTPUT",
+ "VA SWR_MIC1", "ADC2_OUTPUT",
+ "VA SWR_MIC5", "ADC3_OUTPUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ asoc-codec = <&stub_codec>, <&bolero>;
+ asoc-codec-names = "msm-stub-codec.1", "bolero_codec";
+ qcom,wsa-max-devs = <1>;
+ qcom,wsa-devs = <&wsa881x_i2c_e>;
+ qcom,wsa-aux-dev-prefix = "SpkrMono";
+ qcom,codec-max-aux-devs = <1>;
+ qcom,codec-aux-devs = <&rouleur_codec>;
+ qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&bolero>,
+ <&lpi_tlmm>;
+};
+
+&sdhc_2 {
+ vdd-supply = <&L21A>;
+ qcom,vdd-voltage-level = <2960000 3300000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L4A>;
+ qcom,vdd-io-voltage-level = <1800000 2960000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ cd-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+
+ status = "ok";
+};
+
+&pm2250_charger {
+ qcom,auto-recharge-soc = <98>;
+ qcom,suspend-input-on-debug-batt;
+ qcom,battery-data = <&scuba_batterydata>;
+ io-channels = <&pm2250_vadc ADC_USB_IN_V_16>,
+ <&pm2250_vadc ADC_CHG_TEMP>;
+ io-channel-names = "usb_in_voltage",
+ "chg_temp";
+ qcom,thermal-mitigation = <2000000 1500000 1000000 500000>;
+};
+
+&pm2250_pwm3 {
+ status = "ok";
+};
+
+&thermal_zones {
+ quiet-therm-usr {
+ polling-delay = <5000>;
+ };
+
+ quiet-therm-step {
+ polling-delay-passive = <2000>;
+ polling-delay = <5000>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm2250_adc_tm_iio ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ quiet_modem_trip0: quiet-modem-trip0 {
+ temperature = <40000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ quiet_batt_trip0: quiet-batt-trip0 {
+ temperature = <41000>;
+ hysteresis = <3000>;
+ type = "passive";
+ };
+
+ quiet_modem_trip1: quiet-modem-trip1 {
+ temperature = <42000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ quiet_batt_trip1: quiet-batt-trip1 {
+ temperature = <43000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ quiet_modem_trip2: quiet-modem-trip2 {
+ temperature = <43000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ quiet_cpu0_trip: quiet-cpu0-trip {
+ temperature = <44000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ quiet_batt_trip2: quiet-batt-trip2 {
+ temperature = <45000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ quiet_gpu_trip: quiet-gpu-trip {
+ temperature = <46000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ quiet_batt_trip3: quiet-batt-trip3 {
+ temperature = <47000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ quiet_modem_trip3: quiet-modem-trip3 {
+ temperature = <50000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ gpu-cdev {
+ trip = <&quiet_gpu_trip>;
+ /* throttle from fmax to 921600000Hz */
+ cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT - 4)>;
+ };
+
+ cpu0-cdev {
+ trip = <&quiet_cpu0_trip>;
+ /* throttle from fmax to 1420800KHz */
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT - 5)>;
+ };
+
+ modem-proc-cdev0 {
+ trip = <&quiet_modem_trip0>;
+ cooling-device = <&modem_proc 1 1>;
+ };
+
+ modem-proc-cdev1 {
+ trip = <&quiet_modem_trip3>;
+ cooling-device = <&modem_proc 3 3>;
+ };
+
+ modem-pa-cdev0 {
+ trip = <&quiet_modem_trip1>;
+ cooling-device = <&modem_pa 1 1>;
+ };
+
+ modem-pa-cdev1 {
+ trip = <&quiet_modem_trip2>;
+ cooling-device = <&modem_pa 2 2>;
+ };
+
+ modem-pa-cdev3 {
+ trip = <&quiet_modem_trip3>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ batt-cdev0 {
+ trip = <&quiet_batt_trip0>;
+ cooling-device = <&pm2250_charger 1 1>;
+ };
+
+ batt-cdev1 {
+ trip = <&quiet_batt_trip1>;
+ cooling-device = <&pm2250_charger 2 2>;
+ };
+
+ batt-cdev2 {
+ trip = <&quiet_batt_trip2>;
+ cooling-device = <&pm2250_charger 3 3>;
+ };
+
+ batt-cdev3 {
+ trip = <&quiet_batt_trip3>;
+ cooling-device = <&pm2250_charger 4 4>;
+ };
+ };
+ };
+};
+
+&dsi_nt36525_truly_video {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_no_labibb>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ pwms = <&pm2250_pwm3 0 0>;
+ qcom,bl-pmic-pwm-period-usecs = <100>;
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,platform-reset-gpio = <&tlmm 82 0>;
+ qcom,platform-reset-gpio-always-on;
+ qcom,platform-en-gpio = <&tlmm 105 0>;
+};
+
+&sde_dsi {
+ qcom,dsi-default-panel = <&dsi_nt36525_truly_video>;
+};
+
+&qupv3_se2_i2c {
+ status = "ok";
+ qcom,i2c-touch-active = "novatek,NVT-ts";
+
+ novatek@62 {
+ compatible = "novatek,NVT-ts";
+ reg = <0x62>;
+
+ interrupt-parent = <&tlmm>;
+ interrupts = <80 0x2008>;
+ pinctrl-names = "pmx_ts_active","pmx_ts_suspend",
+ "pmx_ts_release";
+ pinctrl-0 = <&ts_int_active &ts_reset_active>;
+ pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
+ pinctrl-2 = <&ts_release>;
+
+ novatek,reset-gpio = <&tlmm 71 0x00>;
+ novatek,irq-gpio = <&tlmm 80 0x2008>;
+
+ panel = <&dsi_nt36525_truly_video>;
+ };
+};
+
+&qusb_phy0 {
+ extcon = <&pm2250_charger>;
+
+ qcom,qusb-phy-init-seq = <0xf8 0x80
+ 0xb3 0x84
+ 0x83 0x88
+ 0xc5 0x8c
+ 0x30 0x08
+ 0x79 0x0c
+ 0x21 0x10
+ 0x14 0x9c
+ 0x80 0x04
+ 0x9f 0x1c
+ 0x00 0x18>;
+};
+
+&usb0 {
+ extcon = <&qusb_phy0>, <&eud>;
+};
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 70 0x00>;
+ qcom,nq-ven = <&tlmm 69 0x00>;
+ qcom,nq-firm = <&tlmm 31 0x00>;
+ qcom,nq-clkreq = <&tlmm 86 0x00>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <70 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_req_active>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend
+ &nfc_clk_req_suspend>;
+ };
+};
+
+&tlmm {
+ fpc_reset_int: fpc_reset_int {
+ fpc_reset_low: reset_low {
+ mux {
+ pins = "gpio104";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio104";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ fpc_reset_high: reset_high {
+ mux {
+ pins = "gpio104";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio104";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ fpc_int_low: int_low {
+ mux {
+ pins = "gpio97";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio97";
+ drive-strength = <2>;
+ bias-pull-down;
+ input-enable;
+ };
+ };
+ };
+};
+
+&soc {
+ fingerprint: fpc1020 {
+ compatible = "fpc,fpc1020";
+ interrupt-parent = <&tlmm>;
+ interrupts = <97 0>;
+ fpc,gpio_rst = <&tlmm 104 0>;
+ fpc,gpio_irq = <&tlmm 97 0>;
+ fpc,enable-on-boot;
+ pinctrl-names = "fpc1020_reset_reset",
+ "fpc1020_reset_active",
+ "fpc1020_irq_active";
+ pinctrl-0 = <&fpc_reset_low>;
+ pinctrl-1 = <&fpc_reset_high>;
+ pinctrl-2 = <&fpc_int_low>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-qupv3.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-qupv3.dtsi
new file mode 100755
index 0000000..3c08b790
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-qupv3.dtsi
@@ -0,0 +1,260 @@
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ /* QUPv3 SE Instances
+ * Qup0 0: SE 0
+ * Qup0 1: SE 1
+ * Qup0 2: SE 2
+ * Qup0 3: SE 3
+ * Qup0 4: SE 4
+ * Qup0 5: SE 5
+ */
+
+ /* QUPv3_0 wrapper instance */
+ qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {
+ compatible = "qcom,qupv3-geni-se";
+ reg = <0x4ac0000 0x2000>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-bus-ids =
+ <MSM_BUS_MASTER_QUP_CORE_0 MSM_BUS_SLAVE_QUP_CORE_0>,
+ <MSM_BUS_MASTER_QUP_0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,vote-for-bw;
+ iommus = <&apps_smmu 0xe3 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+ qcom,iommu-dma = "fastmap";
+ };
+
+ /* GPI Instance */
+ gpi_dma0: qcom,gpi-dma@4a00000 {
+ compatible = "qcom,gpi-dma";
+ #dma-cells = <5>;
+ reg = <0x4a00000 0x60000>;
+ reg-names = "gpi-top";
+ iommus = <&apps_smmu 0xf6 0x0>;
+ qcom,max-num-gpii = <10>;
+ interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,gpii-mask = <0x1f>;
+ qcom,ev-factor = <2>;
+ qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
+ qcom,gpi-ee-offset = <0x10000>;
+ status = "ok";
+ };
+
+ /* Debug UART Instance */
+ qupv3_se4_2uart: qcom,qup_uart@4a90000 {
+ compatible = "qcom,msm-geni-console";
+ reg = <0x4a90000 0x4000>;
+ reg-names = "se_phys";
+ interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se4_2uart_active>;
+ pinctrl-1 = <&qupv3_se4_2uart_sleep>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se0_i2c: i2c@4a80000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x4a80000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se0_i2c_active>;
+ pinctrl-1 = <&qupv3_se0_i2c_sleep>;
+ dmas = <&gpi_dma0 0 0 3 64 0>,
+ <&gpi_dma0 1 0 3 64 0>;
+ dma-names = "tx", "rx";
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se0_spi: spi@4a80000 {
+ compatible = "qcom,spi-geni";
+ reg = <0x4a80000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "se_phys";
+ interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se0_spi_active>;
+ pinctrl-1 = <&qupv3_se0_spi_sleep>;
+ dmas = <&gpi_dma0 0 0 1 64 0>,
+ <&gpi_dma0 1 0 1 64 0>;
+ dma-names = "tx", "rx";
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se1_i2c: i2c@4a84000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x4a84000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se1_i2c_active>;
+ pinctrl-1 = <&qupv3_se1_i2c_sleep>;
+ dmas = <&gpi_dma0 0 1 3 64 0>,
+ <&gpi_dma0 1 1 3 64 0>;
+ dma-names = "tx", "rx";
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se1_spi: spi@4a84000 {
+ compatible = "qcom,spi-geni";
+ reg = <0x4a84000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "se_phys";
+ interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se1_spi_active>;
+ pinctrl-1 = <&qupv3_se1_spi_sleep>;
+ dmas = <&gpi_dma0 0 1 1 64 0>,
+ <&gpi_dma0 1 1 1 64 0>;
+ dma-names = "tx", "rx";
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se2_i2c: i2c@4a88000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x4a88000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se2_i2c_active>;
+ pinctrl-1 = <&qupv3_se2_i2c_sleep>;
+ dmas = <&gpi_dma0 0 2 3 64 0>,
+ <&gpi_dma0 1 2 3 64 0>;
+ dma-names = "tx", "rx";
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se2_spi: spi@4a88000 {
+ compatible = "qcom,spi-geni";
+ reg = <0x4a88000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "se_phys";
+ interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se2_spi_active>;
+ pinctrl-1 = <&qupv3_se2_spi_sleep>;
+ dmas = <&gpi_dma0 0 2 1 64 0>,
+ <&gpi_dma0 1 2 1 64 0>;
+ dma-names = "tx", "rx";
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ /* HS UART Instance */
+ qupv3_se3_4uart: qcom,qup_uart@4a8c000 {
+ compatible = "qcom,msm-geni-serial-hs";
+ reg = <0x4a8c000 0x4000>;
+ reg-names = "se_phys";
+ interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 11 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "active", "sleep";
+ pinctrl-0 = <&qupv3_se3_default_ctsrtsrx>,
+ <&qupv3_se3_default_tx>;
+ pinctrl-1 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,
+ <&qupv3_se3_tx>;
+ pinctrl-2 = <&qupv3_se3_ctsrx>, <&qupv3_se3_rts>,
+ <&qupv3_se3_tx>;
+ qcom,wakeup-byte = <0xFD>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se5_i2c: i2c@4a94000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x4a94000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se5_i2c_active>;
+ pinctrl-1 = <&qupv3_se5_i2c_sleep>;
+ dmas = <&gpi_dma0 0 5 3 64 0>,
+ <&gpi_dma0 1 5 3 64 0>;
+ dma-names = "tx", "rx";
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+ qupv3_se5_spi: spi@4a94000 {
+ compatible = "qcom,spi-geni";
+ reg = <0x4a94000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "se_phys";
+ interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se-clk", "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qupv3_se5_spi_active>;
+ pinctrl-1 = <&qupv3_se5_spi_sleep>;
+ dmas = <&gpi_dma0 0 5 1 64 0>,
+ <&gpi_dma0 1 5 1 64 0>;
+ dma-names = "tx", "rx";
+ spi-max-frequency = <50000000>;
+ qcom,wrapper-core = <&qupv3_0>;
+ status = "disabled";
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-regulator.dtsi
new file mode 100755
index 0000000..a192f16
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-regulator.dtsi
@@ -0,0 +1,365 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+
+&rpm_bus {
+ /* PM2250 S2 - VDD_CX supply */
+ rpm-regulator-smpa2 {
+ status = "okay";
+ qcom,resource-name = "rwcx";
+ qcom,resource-id = <0>;
+
+ VDD_CX_LEVEL:
+ VDD_GFX_LEVEL:
+ VDD_MSS_LEVEL:
+ S2A_LEVEL: pm2250_s2_level: regulator-s2-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_s2_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ VDD_CX_FLOOR_LEVEL:
+ VDD_MSS_FLOOR_LEVEL:
+ S2A_FLOOR_LEVEL:
+ pm2250_s2_floor_level: regulator-s2-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_s2_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+
+ VDD_CX_LEVEL_AO:
+ VDD_MSS_LEVEL_AO:
+ S2A_LEVEL_AO: pm2250_s2_level_ao: regulator-s2-level-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_s2_level_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ cx_cdev: cx-cdev-lvl {
+ compatible = "qcom,regulator-cooling-device";
+ regulator-cdev-supply = <&VDD_CX_FLOOR_LEVEL>;
+ regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NOM
+ RPM_SMD_REGULATOR_LEVEL_NONE>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ /* PM2250 L1 - VDD_MX/WCSS_MX supply */
+ rpm-regulator-ldoa1 {
+ status = "okay";
+ qcom,resource-name = "rwmx";
+ qcom,resource-id = <0>;
+
+ VDD_MX_LEVEL:
+ L1A_LEVEL: pm2250_l1_level: regulator-l1-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l1_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ VDD_MX_FLOOR_LEVEL:
+ L1A_FLOOR_LEVEL:
+ pm2250_l1_floor_level: regulator-l1-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l1_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+
+ VDD_MX_LEVEL_AO:
+ L1A_LEVEL_AO: pm2250_l1_level_ao: regulator-l1-level-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l1_level_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ mx_cdev: mx-cdev-lvl {
+ compatible = "qcom,regulator-cooling-device";
+ regulator-cdev-supply = <&VDD_MX_LEVEL>;
+ regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NOM
+ RPM_SMD_REGULATOR_LEVEL_NONE>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ rpm-regulator-smpa3 {
+ status = "okay";
+ S3A: pm2250_s3: regulator-s3 {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1662500>;
+ qcom,init-voltage = <400000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpa4 {
+ status = "okay";
+ S4A: pm2250_s4: regulator-s4 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2350000>;
+ qcom,init-voltage = <1200000>;
+ status = "okay";
+ };
+ };
+
+ /* VDD_LPI_CX supply */
+ rpm-regulator-ldoa8 {
+ status = "okay";
+ qcom,resource-name = "rwlc";
+ qcom,resource-id = <0>;
+
+ VDD_LPI_CX_LEVEL:
+ L8A_LEVEL: pm2250_l8_level: regulator-l8-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l8_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ };
+
+ /* VDD_LPI_MX supply */
+ rpm-regulator-ldoa9 {
+ status = "okay";
+ qcom,resource-name = "rwlm";
+ qcom,resource-id = <0>;
+
+ VDD_LPI_MX_LEVEL:
+ L9A_LEVEL: pm2250_l9_level: regulator-l9-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm2250_l9_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+ };
+
+ rpm-regulator-ldoa2 {
+ status = "okay";
+ L2A: pm2250_l2: regulator-l2 {
+ regulator-min-microvolt = <1060000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,init-voltage = <1060000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa3 {
+ status = "okay";
+ L3A: pm2250_l3: regulator-l3 {
+ regulator-min-microvolt = <570000>;
+ regulator-max-microvolt = <650000>;
+ qcom,init-voltage = <570000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa4 {
+ status = "okay";
+ L4A: pm2250_l4: regulator-l4 {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3050000>;
+ qcom,init-voltage = <1650000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa5 {
+ status = "okay";
+ L5A: pm2250_l5: regulator-l5 {
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1312000>;
+ qcom,init-voltage = <1100000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa6 {
+ status = "okay";
+ L6A: pm2250_l6: regulator-l6 {
+ regulator-min-microvolt = <488000>;
+ regulator-max-microvolt = <1000000>;
+ qcom,init-voltage = <488000>;
+ status = "okay";
+ };
+ };
+
+ /* WCSS_CX */
+ rpm-regulator-ldoa7 {
+ status = "okay";
+ WCSS_CX:
+ L7A: pm2250_l7: regulator-l7 {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <728000>;
+ qcom,init-voltage = <400000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa10 {
+ status = "okay";
+ L10A: pm2250_l10: regulator-l10 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1380000>;
+ qcom,init-voltage = <1150000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa11 {
+ status = "okay";
+ L11A: pm2250_l11: regulator-l11 {
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1150000>;
+ qcom,init-voltage = <950000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa12 {
+ status = "okay";
+ L12A: pm2250_l12: regulator-l12 {
+ regulator-min-microvolt = <488000>;
+ regulator-max-microvolt = <1000000>;
+ qcom,init-voltage = <488000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa13 {
+ status = "okay";
+ L13A: pm2250_l13: regulator-l13 {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ qcom,init-voltage = <1650000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa14 {
+ status = "okay";
+ L14A: pm2250_l14: regulator-l14 {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1950000>;
+ qcom,init-voltage = <1700000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa15 {
+ status = "okay";
+ L15A: pm2250_l15: regulator-l15 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2000000>;
+ qcom,init-voltage = <1200000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa16 {
+ status = "okay";
+ L16A: pm2250_l16: regulator-l16 {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1950000>;
+ qcom,init-voltage = <1500000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa17 {
+ status = "okay";
+ L17A: pm2250_l17: regulator-l17 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3600000>;
+ qcom,init-voltage = <3000000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa18 {
+ status = "okay";
+ L18A: pm2250_l18: regulator-l18 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <1620000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa19 {
+ status = "okay";
+ L19A: pm2250_l19: regulator-l19 {
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <1620000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa20 {
+ status = "okay";
+ L20A: pm2250_l20: regulator-l20 {
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3600000>;
+ qcom,init-voltage = <2400000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa21 {
+ status = "okay";
+ L21A: pm2250_l21: regulator-l21 {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <2900000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa22 {
+ status = "okay";
+ L22A: pm2250_l22: regulator-l22 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3400000>;
+ qcom,init-voltage = <2850000>;
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-rumi-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-rumi-overlay.dts
new file mode 100755
index 0000000..9b225cf
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-rumi-overlay.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "scuba-rumi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba RUMI";
+ compatible = "qcom,scuba-rumi", "qcom,scuba", "qcom,rumi";
+ qcom,msm-id = <441 0x10000>;
+ qcom,board-id = <15 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-rumi.dts b/arch/arm64/boot/dts/vendor/qcom/scuba-rumi.dts
new file mode 100755
index 0000000..0562b20
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-rumi.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/memreserve/ 0x90000000 0x00000100;
+
+#include "scuba.dtsi"
+#include "scuba-rumi.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba RUMI";
+ compatible = "qcom,scuba-rumi", "qcom,scuba", "qcom,rumi";
+ qcom,board-id = <15 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-rumi.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-rumi.dtsi
new file mode 100755
index 0000000..8ccef09
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-rumi.dtsi
@@ -0,0 +1,111 @@
+&soc {
+ timer {
+ clock-frequency = <500000>;
+ };
+
+ timer@f120000 {
+ clock-frequency = <500000>;
+ };
+
+ wdog: qcom,wdt@f017000 {
+ status = "disabled";
+ };
+
+ usb_emu_phy: usb_emu_phy@4f20000 {
+ compatible = "qcom,usb-emu-phy";
+ reg = <0x04f20000 0x9500>,
+ <0x04ef8800 0x100>;
+ reg-names = "base", "qscratch_base";
+
+ qcom,emu-init-seq = <0xffff 0x4
+ 0xfff0 0x4
+ 0x100000 0x20
+ 0x0 0x20
+ 0x101f0 0x20
+ 0x100000 0x3c
+ 0x0 0x3c
+ 0x10060 0x3c
+ 0x0 0x4>;
+ };
+
+ bi_tcxo: bi_tcxo {
+ compatible = "fixed-factor-clock";
+ clock-mult = <1>;
+ clock-div = <2>;
+ clocks = <&xo_board>;
+ #clock-cells = <0>;
+ };
+
+ bi_tcxo_ao: bi_tcxo_ao {
+ compatible = "fixed-factor-clock";
+ clock-mult = <1>;
+ clock-div = <2>;
+ clocks = <&xo_board>;
+ #clock-cells = <0>;
+ };
+};
+
+&usb0 {
+ dwc3@4e00000 {
+ usb-phy = <&usb_emu_phy>, <&usb_nop_phy>;
+ maximum-speed = "high-speed";
+ dr_mode = "peripheral";
+ };
+};
+
+&sdhc_1 {
+ vdd-supply = <&L19A>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 570000>;
+
+ vdd-io-supply = <&L14A>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <0 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on
+ &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off
+ &sdc1_rclk_off>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000>;
+ qcom,bus-speed-mode = "DDR_1p8v";
+
+ /delete-property/qcom,devfreq,freq-table;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ vdd-supply = <&L21A>;
+ qcom,vdd-voltage-level = <2960000 2960000>;
+ qcom,vdd-current-level = <0 800000>;
+
+ vdd-io-supply = <&L4A>;
+ qcom,vdd-io-voltage-level = <1800000 2960000>;
+ qcom,vdd-io-current-level = <0 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50";
+
+ /delete-property/qcom,devfreq,freq-table;
+
+ status = "ok";
+};
+
+&rpmcc {
+ compatible = "qcom,dummycc";
+ clock-output-names = "rpmcc_clocks";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
+
+&qupv3_se1_i2c {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-sde-display.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-sde-display.dtsi
new file mode 100755
index 0000000..f6135d2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-sde-display.dtsi
@@ -0,0 +1,209 @@
+#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
+#include "dsi-panel-nt36525-truly-hd-plus-vid.dtsi"
+#include "dsi-panel-td4330-truly-v2-singlemipi-fhd-vid.dtsi"
+#include "dsi-panel-td4330-truly-v2-singlemipi-fhd-cmd.dtsi"
+
+&soc {
+ dsi_panel_pwr_supply: dsi_panel_pwr_supply {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <2000000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "lab";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@2 {
+ reg = <2>;
+ qcom,supply-name = "ibb";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+ };
+
+ dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <2000000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+ };
+
+ dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <2000000>;
+ qcom,supply-enable-load = <62000>;
+ qcom,supply-disable-load = <80>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "vdda-3p3";
+ qcom,supply-min-voltage = <3000000>;
+ qcom,supply-max-voltage = <3000000>;
+ qcom,supply-enable-load = <13200>;
+ qcom,supply-disable-load = <80>;
+ };
+ };
+
+ sde_dsi: qcom,dsi-display-primary {
+ compatible = "qcom,dsi-display";
+ label = "primary";
+ qcom,dsi-ctrl = <&mdss_dsi0>;
+ qcom,dsi-phy = <&mdss_dsi_phy0>;
+
+ clocks = <&mdss_dsi0_pll BYTE0_MUX_CLK>,
+ <&mdss_dsi0_pll PIX0_MUX_CLK>,
+ <&mdss_dsi0_pll BYTE0_SRC_CLK>,
+ <&mdss_dsi0_pll PIX0_SRC_CLK>,
+ <&mdss_dsi0_pll SHADOW_BYTE0_SRC_CLK>,
+ <&mdss_dsi0_pll SHADOW_PIX0_SRC_CLK>;
+ clock-names = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+ pinctrl-names = "panel_active", "panel_suspend";
+ pinctrl-0 = <&sde_dsi_active &sde_te_active>;
+ pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
+
+ qcom,platform-te-gpio = <&tlmm 81 0>;
+ qcom,panel-te-source = <0>;
+ vddio-supply = <&L15A>;
+ qcom,mdp = <&mdss_mdp>;
+
+ qcom,dsi-default-panel =
+ <&dsi_nt36525_truly_video>;
+ };
+};
+
+&mdss_mdp {
+ connectors = <&sde_dsi>;
+};
+
+&dsi_nt36525_truly_video {
+ qcom,mdss-dsi-t-clk-post = <0x0a>;
+ qcom,mdss-dsi-t-clk-pre = <0x21>;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,dsi-supported-dfps-list = <60 55 48>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update =
+ "dfps_immediate_porch_mode_vfp";
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+ qcom,dsi-dyn-clk-enable;
+ qcom,dsi-dyn-clk-list =
+ <502087680 504179712 506271744 508363776>;
+ qcom,dsi-dyn-clk-type = "constant-fps-adjust-vfp";
+
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings =
+ [1F 1B 05 06 03 02 04 a0
+ 1F 1B 05 06 03 02 04 a0
+ 1F 1B 05 06 03 02 04 a0
+ 1F 1B 05 06 03 02 04 a0
+ 1F 10 04 06 03 02 04 a0];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_td4330_truly_v2_video {
+ qcom,mdss-dsi-t-clk-post = <0x0e>;
+ qcom,mdss-dsi-t-clk-pre = <0x35>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0",
+ "src_byte_clk0", "src_pixel_clk0",
+ "shadow_byte_clk0", "shadow_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings =
+ [25 20 09 0A 06 03 04 a0
+ 25 20 09 0A 06 03 04 a0
+ 25 20 09 0A 06 03 04 a0
+ 25 20 09 0A 06 03 04 a0
+ 25 1F 09 0A 06 03 04 a0];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings =
+ [26 20 09 0B 06 02 04 a0
+ 26 20 09 0B 06 02 04 a0
+ 26 20 09 0B 06 02 04 a0
+ 26 20 09 0B 06 02 04 a0
+ 26 1F 09 0B 06 02 04 a0];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
+
+&dsi_td4330_truly_v2_cmd {
+ qcom,mdss-dsi-t-clk-post = <0x0e>;
+ qcom,mdss-dsi-t-clk-pre = <0x36>;
+ qcom,dsi-select-clocks = "mux_byte_clk0", "mux_pixel_clk0";
+ qcom,mdss-dsi-display-timings {
+ timing@0 {
+ qcom,mdss-dsi-panel-phy-timings =
+ [26 20 09 0B 06 02 04 a0
+ 26 20 09 0B 06 02 04 a0
+ 26 20 09 0B 06 02 04 a0
+ 26 20 09 0B 06 02 04 a0
+ 26 1F 09 0B 06 02 04 a0];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <40 40 40 40 40 40>;
+ };
+
+ timing@1 {
+ qcom,mdss-dsi-panel-phy-timings =
+ [25 20 09 0A 06 03 04 a0
+ 25 20 09 0A 06 03 04 a0
+ 25 20 09 0A 06 03 04 a0
+ 25 20 09 0A 06 03 04 a0
+ 25 1F 09 0A 06 03 04 a0];
+ qcom,display-topology = <1 0 1>;
+ qcom,default-topology-index = <0>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-sde-pll.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-sde-pll.dtsi
new file mode 100755
index 0000000..72e4bc6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-sde-pll.dtsi
@@ -0,0 +1,32 @@
+&soc {
+ mdss_dsi0_pll: qcom,mdss_dsi0_pll {
+ compatible = "qcom,mdss_dsi_pll_14nm";
+ label = "MDSS DSI 0 PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+ reg = <0x5e94400 0x588>,
+ <0x5f03000 0x8>,
+ <0x5e94200 0x100>;
+ reg-names = "pll_base", "gdsc_base",
+ "dynamic_pll_base";
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ memory-region = <&dfps_data_memory>;
+ gdsc-supply = <&mdss_core_gdsc>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-sde.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-sde.dtsi
new file mode 100755
index 0000000..957b9bd
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-sde.dtsi
@@ -0,0 +1,312 @@
+#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
+
+&soc {
+ mdss_mdp: qcom,mdss_mdp {
+ compatible = "qcom,sde-kms";
+ reg = <0x5e00000 0x8f030>,
+ <0x5eb0000 0x2008>,
+ <0x5e8f000 0x02c>,
+ <0xc125ba4 0x20>;
+ reg-names = "mdp_phys",
+ "vbif_phys",
+ "sid_phys",
+ "sde_imem_phys";
+
+ clocks =
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&gcc GCC_DISP_THROTTLE_CORE_CLK>,
+ <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
+ clock-names = "gcc_iface", "gcc_bus", "throttle_clk",
+ "div_clk",
+ "iface_clk", "core_clk", "vsync_clk",
+ "lut_clk";
+ clock-rate = <0 0 0 0 0 256000000 19200000 192000000>;
+ clock-max-rate = <0 0 0 0 0 384000000 19200000 384000000>;
+
+ sde-vdd-supply = <&mdss_core_gdsc>;
+
+ /* interrupt config */
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #power-domain-cells = <0>;
+
+ /* hw blocks */
+ qcom,sde-off = <0x1000>;
+ qcom,sde-len = <0x494>;
+
+ qcom,sde-ctl-off = <0x2000>;
+ qcom,sde-ctl-size = <0x1dc>;
+ qcom,sde-ctl-display-pref = "primary";
+
+ qcom,sde-mixer-off = <0x45000>;
+ qcom,sde-mixer-size = <0x320>;
+ qcom,sde-mixer-display-pref = "primary";
+
+ qcom,sde-dspp-top-off = <0x1300>;
+ qcom,sde-dspp-top-size = <0x80>;
+ qcom,sde-dspp-off = <0x55000>;
+ qcom,sde-dspp-size = <0xfe4>;
+
+ qcom,sde-intf-off = <0x0 0x6b800>;
+ qcom,sde-intf-size = <0x2b8>;
+ qcom,sde-intf-type = "none", "dsi";
+
+ qcom,sde-pp-off = <0x71000>;
+ qcom,sde-pp-size = <0xd4>;
+
+ qcom,sde-dither-off = <0x30e0>;
+ qcom,sde-dither-version = <0x00010000>;
+ qcom,sde-dither-size = <0x20>;
+
+ qcom,sde-sspp-type = "vig", "dma";
+
+ qcom,sde-sspp-off = <0x5000 0x25000>;
+ qcom,sde-sspp-src-size = <0x1f8>;
+
+ qcom,sde-sspp-xin-id = <0 1>;
+ qcom,sde-sspp-excl-rect = <1 1>;
+ qcom,sde-sspp-smart-dma-priority = <2 1>;
+ qcom,sde-smart-dma-rev = "smart_dma_v2p5";
+
+ qcom,sde-mixer-pair-mask = <0>;
+
+ qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
+ 0xb0 0xc8 0xe0 0xf8 0x110>;
+
+ qcom,sde-mixer-stage-base-layer;
+
+ qcom,sde-max-per-pipe-bw-kbps = <2700000 2700000>;
+
+ qcom,sde-max-per-pipe-bw-high-kbps = <2700000 2700000>;
+
+ /* offsets are relative to "mdp_phys + qcom,sde-off */
+ qcom,sde-sspp-clk-ctrl =
+ <0x2ac 0>, <0x2ac 8>;
+ qcom,sde-mixer-linewidth = <2048>;
+ qcom,sde-mixer-blendstages = <0x4>;
+ qcom,sde-panic-per-pipe;
+ qcom,sde-has-cdp;
+
+ qcom,sde-has-dim-layer;
+ qcom,sde-has-idle-pc;
+
+ qcom,sde-max-bw-low-kbps = <2700000>;
+ qcom,sde-max-bw-high-kbps = <2700000>;
+ qcom,sde-min-core-ib-kbps = <1300000>;
+ qcom,sde-min-llcc-ib-kbps = <0>;
+ qcom,sde-min-dram-ib-kbps = <1600000>;
+ qcom,sde-dram-channels = <2>;
+ qcom,sde-num-nrt-paths = <0>;
+
+ qcom,sde-vbif-off = <0>;
+ qcom,sde-vbif-size = <0x2008>;
+ qcom,sde-vbif-id = <0>;
+ qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
+ qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;
+
+ qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;
+
+ /*Pending macrotile & macrotile-qseed has the same configs */
+
+ qcom,sde-danger-lut = <0x000000ff 0x00000000
+ 0x00000000 0x00000000 0x00000000>;
+
+ qcom,sde-safe-lut-linear = <0 0xfff0>;
+
+ qcom,sde-qos-lut-linear = <0 0x00112222 0x22335777>;
+
+ qcom,sde-cdp-setting = <1 0>;
+
+ qcom,sde-qos-cpu-mask = <0x3>;
+ qcom,sde-qos-cpu-dma-latency = <300>;
+
+ qcom,sde-secure-sid-mask = <0x0000421>;
+ qcom,sde-num-mnoc-ports = <1>;
+ qcom,sde-axi-bus-width = <16>;
+
+ qcom,sde-dspp-blocks {
+ qcom,sde-dspp-igc = <0x0 0x00030001>;
+ qcom,sde-dspp-hsic = <0x800 0x00010007>;
+ qcom,sde-dspp-memcolor = <0x880 0x00010007>;
+ qcom,sde-dspp-hist = <0x800 0x00010007>;
+ qcom,sde-dspp-sixzone= <0x900 0x00010007>;
+ qcom,sde-dspp-vlut = <0xa00 0x00010008>;
+ qcom,sde-dspp-pcc = <0x1700 0x00040000>;
+ qcom,sde-dspp-gc = <0x17c0 0x00010008>;
+ qcom,sde-dspp-dither = <0x82c 0x00010007>;
+ };
+
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "sde-vdd";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
+ compatible = "qcom,smmu_sde_unsec";
+ iommus = <&apps_smmu 0x420 0x2>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-earlymap; /* for cont-splash */
+ };
+
+ smmu_sde_sec: qcom,smmu_sde_sec_cb {
+ compatible = "qcom,smmu_sde_sec";
+ iommus = <&apps_smmu 0x421 0x0>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xa>;
+ };
+
+ /* data and reg bus scale settings */
+ qcom,sde-data-bus {
+ qcom,msm-bus,name = "mdss_sde";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>,
+ <22 512 0 4800000>,
+ <22 512 0 4800000>;
+ };
+
+ qcom,sde-reg-bus {
+ qcom,msm-bus,name = "mdss_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 150000>,
+ <1 590 0 300000>;
+ };
+
+ qcom,sde-limits {
+ qcom,sde-linewidth-limits {
+ qcom,sde-limit-name = "sspp_linewidth_usecases";
+ qcom,sde-limit-cases = "vig", "dma";
+ qcom,sde-limit-ids= <0x1 0x2>;
+ qcom,sde-limit-values = <0x1 2160>,
+ <0x2 2160>;
+ };
+
+ qcom,sde-bw-limits {
+ qcom,sde-limit-name = "sde_bwlimit_usecases";
+ qcom,sde-limit-cases = "per_vig_pipe",
+ "per_dma_pipe",
+ "total_max_bw",
+ "camera_concurrency";
+ qcom,sde-limit-ids = <0x1 0x2 0x4 0x8>;
+ qcom,sde-limit-values = <0x1 2700000>,
+ <0x9 2700000>,
+ <0x2 2700000>,
+ <0xa 2700000>,
+ <0x4 2700000>,
+ <0xc 2700000>;
+ };
+ };
+ };
+
+ mdss_dsi0: qcom,mdss_dsi0_ctrl {
+ compatible = "qcom,dsi-ctrl-hw-v2.4";
+ label = "dsi-ctrl-0";
+ cell-index = <0>;
+ reg = <0x5e94000 0x400>,
+ <0x5f08000 0x4>;
+ reg-names = "dsi_ctrl", "disp_cc_base";
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <4 0>;
+ vdda-1p2-supply = <&L5A>;
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>;
+ clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
+ "pixel_clk", "pixel_clk_rcg",
+ "esc_clk";
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1232000>;
+ qcom,supply-max-voltage = <1312000>;
+ qcom,supply-enable-load = <21800>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "refgen";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dsi_phy0: qcom,mdss_dsi_phy0 {
+ compatible = "qcom,dsi-phy-v2.0";
+ label = "dsi-phy-0";
+ cell-index = <0>;
+ reg = <0x5e94400 0x588>,
+ <0x5e01400 0x100>,
+ <0x5e94200 0x100>;
+ reg-names = "dsi_phy", "phy_clamp_base",
+ "dyn_refresh_base";
+ vdda-0p9-supply = <&VDD_MX_LEVEL>;
+ qcom,platform-strength-ctrl = [ff 06
+ ff 06
+ ff 06
+ ff 06
+ ff 00];
+ qcom,platform-lane-config = [00 00 10 0f
+ 00 00 10 0f
+ 00 00 10 0f
+ 00 00 10 0f
+ 00 00 10 8f];
+ qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
+ qcom,panel-allow-phy-poweroff;
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage =
+ <RPM_SMD_REGULATOR_LEVEL_NOM>;
+ qcom,supply-max-voltage =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO_NO_CPR>;
+ qcom,supply-off-min-voltage =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-stub-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-stub-regulator.dtsi
new file mode 100755
index 0000000..a17cdda
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-stub-regulator.dtsi
@@ -0,0 +1,235 @@
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+
+&soc {
+ VDD_CX_LEVEL:
+ S2A_LEVEL: pm2250_s2_level: regulator-pm2250-s2-level {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_s2_level";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ VDD_CX_LEVEL_AO:
+ S2A_LEVEL_AO: pm2250_s2_level_ao: regulator-pm2250-s2-level-ao {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_s2_level_ao";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ cx_cdev: cx-cdev-lvl {
+ compatible = "qcom,regulator-cooling-device";
+ regulator-cdev-supply = <&VDD_CX_LEVEL_AO>;
+ regulator-levels = <RPMH_REGULATOR_LEVEL_NOM
+ RPMH_REGULATOR_LEVEL_RETENTION>;
+ #cooling-cells = <2>;
+ };
+
+ VDD_MX_LEVEL:
+ L1A_LEVEL: pm2250_l1_level: regulator-pm2250-l1-level {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l1_level";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ VDD_MX_LEVEL_AO:
+ L1A_LEVEL_AO: pm2250_l1_level_ao: regulator-pm2250-l1-level-ao {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l1_level_ao";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ mx_cdev: mx-cdev-lvl {
+ compatible = "qcom,regulator-cooling-device";
+ regulator-cdev-supply = <&VDD_MX_LEVEL>;
+ regulator-levels = <RPMH_REGULATOR_LEVEL_NOM
+ RPMH_REGULATOR_LEVEL_RETENTION>;
+ #cooling-cells = <2>;
+ };
+
+ S4A: pm2250_s4: regulator-pm2250-s4 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_s4";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <110000>;
+ regulator-max-microvolt = <2350000>;
+ };
+
+ VDD_LPI_CX_LEVEL:
+ L8A_LEVEL: pm2250_l8_level: regulator-pm2250-l8-level {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l8_level";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ VDD_LPI_MX_LEVEL:
+ L9A_LEVEL: pm2250_l9_level: regulator-pm2250-l9-level {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l9_level";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt = <RPMH_REGULATOR_LEVEL_MAX>;
+ };
+
+ L2A: pm2250_l2: regulator-pm2250-l2 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l2";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1060000>;
+ regulator-max-microvolt = <1300000>;
+ };
+
+ L3A: pm2250_l3: regulator-pm2250-l3 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l3";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <570000>;
+ regulator-max-microvolt = <650000>;
+ };
+
+ L4A: pm2250_l4: regulator-pm2250-l4 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l4";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <3050000>;
+ };
+
+ L5A: pm2250_l5: regulator-pm2250-l5 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l5";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1312000>;
+ };
+
+ L6A: pm2250_l6: regulator-pm2250-l6 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l6";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <488000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ /* WCSS_CX */
+ L7A: pm2250_l7: regulator-pm2250-l7 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l7";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <728000>;
+ };
+
+ L10A: pm2250_l10: regulator-pm2250-l10 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l10";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1380000>;
+ };
+
+ L11A: pm2250_l11: regulator-pm2250-l11 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l11";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1150000>;
+ };
+
+ L12A: pm2250_l12: regulator-pm2250-l12 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l12";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <488000>;
+ regulator-max-microvolt = <1000000>;
+ };
+
+ L13A: pm2250_l13: regulator-pm2250-l13 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l13";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ };
+
+ L14A: pm2250_l14: regulator-pm2250-l14 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l14";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <1950000>;
+ };
+
+ L15A: pm2250_l15: regulator-pm2250-l15 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l15";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ L16A: pm2250_l16: regulator-pm2250-l16 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l16";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1950000>;
+ };
+
+ L17A: pm2250_l17: regulator-pm2250-l17 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l17";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ L18A: pm2250_l18: regulator-pm2250-l18 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l18";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ L19A: pm2250_l19: regulator-pm2250-l19 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l19";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <1620000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ L20A: pm2250_l20: regulator-pm2250-l20 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l20";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <3600000>;
+ };
+
+ L21A: pm2250_l21: regulator-pm2250-l21 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l21";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <2921000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ L22A: pm2250_l22: regulator-pm2250-l22 {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "pm2250_l22";
+ qcom,hpm-min-load = <10000>;
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3400000>;
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-thermal-overlay.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-thermal-overlay.dtsi
new file mode 100755
index 0000000..a2039b5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-thermal-overlay.dtsi
@@ -0,0 +1,54 @@
+#include <dt-bindings/thermal/thermal.h>
+
+&thermal_zones {
+ pm2250-tz {
+ cooling-maps {
+ trip0_cpu0 {
+ trip = <&pm2250_trip0>;
+ cooling-device =
+ <&CPU0 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ trip1_cpu1 {
+ trip = <&pm2250_trip1>;
+ cooling-device = <&cpu1_isolate 1 1>;
+ };
+
+ trip1_cpu2 {
+ trip = <&pm2250_trip1>;
+ cooling-device = <&cpu2_isolate 1 1>;
+ };
+
+ trip1_cpu3 {
+ trip = <&pm2250_trip1>;
+ cooling-device = <&cpu3_isolate 1 1>;
+ };
+ };
+ };
+
+ soc {
+ cooling-maps {
+ soc_cpu0 {
+ trip = <&pm2250_low_soc>;
+ cooling-device =
+ <&CPU0 (THERMAL_MAX_LIMIT-4)
+ (THERMAL_MAX_LIMIT-4)>;
+ };
+
+ soc_cpu2 {
+ trip = <&pm2250_low_soc>;
+ cooling-device = <&cpu2_isolate 1 1>;
+ };
+
+ soc_cpu3 {
+ trip = <&pm2250_low_soc>;
+ cooling-device = <&cpu3_isolate 1 1>;
+ };
+ };
+ };
+};
+
+&mdss_mdp {
+ #cooling-cells = <2>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-thermal.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-thermal.dtsi
new file mode 100755
index 0000000..6123f3c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-thermal.dtsi
@@ -0,0 +1,661 @@
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/thermal/qmi_thermal.h>
+
+&cpufreq_hw {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ lmh_dcvs0: qcom,limits-dcvs@f550800 {
+ compatible = "qcom,msm-hw-limits";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,affinity = <0>;
+ reg = <0xf550800 0x1000>,
+ <0xf521000 0x1000>;
+ qcom,no-cooling-device-register;
+ };
+
+ qcom,cpu-isolation {
+ compatible = "qcom,cpu-isolate";
+ cpu0_isolate: cpu0-isolate {
+ qcom,cpu = <&CPU0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1_isolate: cpu1-isolate {
+ qcom,cpu = <&CPU1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2_isolate: cpu2-isolate {
+ qcom,cpu = <&CPU2>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3_isolate: cpu3-isolate {
+ qcom,cpu = <&CPU3>;
+ #cooling-cells = <2>;
+ };
+ };
+};
+
+&soc {
+ qmi-tmd-devices {
+ compatible = "qcom,qmi-cooling-devices";
+
+ modem {
+ qcom,instance-id = <QMI_MODEM_INST_ID>;
+
+ modem_pa: modem_pa {
+ qcom,qmi-dev-name = "pa";
+ #cooling-cells = <2>;
+ };
+
+ modem_proc: modem_proc {
+ qcom,qmi-dev-name = "modem";
+ #cooling-cells = <2>;
+ };
+
+ modem_current: modem_current {
+ qcom,qmi-dev-name = "modem_current";
+ #cooling-cells = <2>;
+ };
+
+ modem_skin: modem_skin {
+ qcom,qmi-dev-name = "modem_skin";
+ #cooling-cells = <2>;
+ };
+
+ modem_vdd: modem_vdd {
+ qcom,qmi-dev-name = "cpuv_restriction_cold";
+ #cooling-cells = <2>;
+ };
+
+ modem_wlan: modem_wlan {
+ qcom,qmi-dev-name = "wlan";
+ #cooling-cells = <2>;
+ };
+ };
+
+ adsp {
+ qcom,instance-id = <QMI_ADSP_INST_ID>;
+
+ adsp_vdd: adsp_vdd {
+ qcom,qmi-dev-name = "cpuv_restriction_cold";
+ #cooling-cells = <2>;
+ };
+ };
+ };
+
+ lmh_cpu_vdd: qcom,lmh-cpu-vdd@f550800 {
+ compatible = "qcom,lmh-cpu-vdd";
+ reg = <0xf550800 0x1000>;
+ #cooling-cells = <2>;
+ };
+
+ cxip_cdev: cxip-cdev@3ed000 {
+ compatible = "qcom,cxip-lm-cooling-device";
+ reg = <0x3ed000 0xc008>;
+ qcom,thermal-client-offset = <0x8000>;
+ /* 4th offset to bypass VICTIM1 */
+ qcom,bypass-client-list = <0x3004 0x4004 0x6004 0xc004>;
+ #cooling-cells = <2>;
+ };
+};
+
+&thermal_zones {
+ mapss-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 0>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ video-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 1>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ wlan-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 3>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 4>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 5>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 6>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpu-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 7>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ hm-center-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 8>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens0 9>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ xo-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm2250_adc_tm_iio ADC_XO_THERM_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ pa-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm2250_adc_tm_iio ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ quiet-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm2250_adc_tm_iio ADC_AMUX_THM2_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ msm-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm2250_adc_tm_iio ADC_AMUX_THM3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ chg-skin-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm2250_adc_tm_iio ADC_GPIO3_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ conn-therm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm2250_adc_tm_iio ADC_GPIO4_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ s3-die-temp-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm2250_adc_tm_iio ADC_SBUx>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpu-step {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 7>;
+ wake-capable-sensor;
+ trips {
+ gpu_cxip_trip: gpu-cxip-trip {
+ temperature = <95000>;
+ hysteresis = <20000>;
+ type = "passive";
+ };
+
+ gpu_step_trip: gpu-trip {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ gpu_cx_mon: gpu-cx-mon {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+
+ };
+
+ cooling-maps {
+ cxip-cdev {
+ trip = <&gpu_cxip_trip>;
+ cooling-device = <&cxip_cdev 1 1>;
+ };
+
+ gpu_cdev {
+ trip = <&gpu_step_trip>;
+ cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+
+ gpu-cx-cdev0 {
+ trip = <&gpu_cx_mon>;
+ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ gpu-cx-cdev1 {
+ trip = <&gpu_cx_mon>;
+ cooling-device = <&modem_proc 3 3>;
+ };
+
+ gpu-cx-cdev2 {
+ trip = <&gpu_cx_mon>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+ };
+ };
+
+ cpuss-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 3>;
+ wake-capable-sensor;
+
+ trips {
+ cpu0_2_config: cpu-0-2-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_cdev {
+ trip = <&cpu0_2_config>;
+ cooling-device = <&cpu0_isolate 1 1>;
+ };
+
+ cpu2_cdev {
+ trip = <&cpu0_2_config>;
+ cooling-device = <&cpu2_isolate 1 1>;
+ };
+ };
+ };
+
+ cpuss-1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 4>;
+ wake-capable-sensor;
+
+ trips {
+ cpu1_3_config: cpu-1-3-config {
+ temperature = <110000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu1_cdev {
+ trip = <&cpu1_3_config>;
+ cooling-device = <&cpu1_isolate 1 1>;
+ };
+
+ cpu3_cdev {
+ trip = <&cpu1_3_config>;
+ cooling-device = <&cpu3_isolate 1 1>;
+ };
+ };
+ };
+
+ mdm-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 5>;
+ wake-capable-sensor;
+ trips {
+ mdm0_cx_mon: mdm0-cx-mon {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ mdm0-cx-cdev0 {
+ trip = <&mdm0_cx_mon>;
+ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ mdm0-cx-cdev1 {
+ trip = <&mdm0_cx_mon>;
+ cooling-device = <&modem_proc 3 3>;
+ };
+
+ mdm0-cx-cdev2 {
+ trip = <&mdm0_cx_mon>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+ };
+ };
+
+ mdm-1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens0 6>;
+ wake-capable-sensor;
+ trips {
+ mdm1_cx_mon: mdm1-cx-mon {
+ temperature = <100000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ mdm1-cx-cdev0 {
+ trip = <&mdm1_cx_mon>;
+ cooling-device = <&msm_gpu THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ mdm1-cx-cdev1 {
+ trip = <&mdm1_cx_mon>;
+ cooling-device = <&modem_proc 3 3>;
+ };
+
+ mdm1-cx-cdev2 {
+ trip = <&mdm1_cx_mon>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+ };
+ };
+
+ mapss-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens0 0>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ mapss_trip: mapss-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cx_vdd_cdev {
+ trip = <&mapss_trip>;
+ cooling-device = <&cx_cdev 0 0>;
+ };
+
+ mx_vdd_cdev {
+ trip = <&mapss_trip>;
+ cooling-device = <&mx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&mapss_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+
+ adsp_vdd_cdev {
+ trip = <&mapss_trip>;
+ cooling-device = <&adsp_vdd 0 0>;
+ };
+ };
+ };
+
+ mapss-lowc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&tsens0 0>;
+ wake-capable-sensor;
+ tracks-low;
+
+ trips {
+ mapss_cap_trip: mapss-cap-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ lmh_cpu_cdev {
+ trip = <&mapss_cap_trip>;
+ cooling-device = <&lmh_cpu_vdd 1 1>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-usb.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-usb.dtsi
new file mode 100755
index 0000000..1ac6525
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-usb.dtsi
@@ -0,0 +1,322 @@
+#include <dt-bindings/clock/qcom,gcc-scuba.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/phy/qcom,usb3-11nm-qmp-combo.h>
+
+&soc {
+ /* Primary USB port related controller */
+ usb0: ssusb@4e00000 {
+ compatible = "qcom,dwc-usb3-msm";
+ reg = <0x4e00000 0x100000>;
+ reg-names = "core_base";
+
+ iommus = <&apps_smmu 0x0120 0x0>;
+ qcom,iommu-dma = "atomic";
+ qcom,iommu-dma-addr-pool = <0x50000000 0x60000000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event_irq", "ss_phy_irq", "hs_phy_irq";
+
+ clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
+ clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+ "xo", "sleep_clk", "utmi_clk";
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+ reset-names = "core_reset";
+
+ USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
+ dpdm-supply = <&qusb_phy0>;
+
+ qcom,core-clk-rate = <133333333>;
+ qcom,core-clk-rate-hs = <66666667>;
+ qcom,num-gsi-evt-buffs = <0x3>;
+ qcom,gsi-reg-offset =
+ <0x0fc /* GSI_GENERAL_CFG */
+ 0x110 /* GSI_DBL_ADDR_L */
+ 0x120 /* GSI_DBL_ADDR_H */
+ 0x130 /* GSI_RING_BASE_ADDR_L */
+ 0x144 /* GSI_RING_BASE_ADDR_H */
+ 0x1a4>; /* GSI_IF_STS */
+ qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
+ qcom,gsi-disable-io-coherency;
+
+ qcom,msm-bus,name = "usb0";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ /* suspend vote */
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 0>,
+
+ /* nominal vote */
+ <MSM_BUS_MASTER_USB3
+ MSM_BUS_SLAVE_EBI_CH0 1000000 1550000>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+ /* svs vote */
+ <MSM_BUS_MASTER_USB3
+ MSM_BUS_SLAVE_EBI_CH0 240000 700000>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 0 2400>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 0 40000>,
+
+ /* min vote */
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_EBI_CH0 1 1>,
+ <MSM_BUS_MASTER_USB3 MSM_BUS_SLAVE_IPA_CFG 1 1>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_USB3 1 1>;
+
+ dwc3@4e00000 {
+ compatible = "snps,dwc3";
+ reg = <0x4e00000 0xcd00>;
+ interrupt-parent = <&intc>;
+ interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ usb-phy = <&qusb_phy0>, <&usb_qmp_phy>;
+ tx-fifo-resize;
+ linux,sysdev_is_parent;
+ snps,disable-clk-gating;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ snps,usb3-u1u2-disable;
+ snps,usb3_lpm_capable;
+ usb-core-id = <0>;
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+
+ qcom,usbbam@0x04f04000 {
+ compatible = "qcom,usb-bam-msm";
+ reg = <0x04f04000 0x17000>;
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
+
+ qcom,usb-bam-fifo-baseaddr = <0xc121000>;
+ qcom,usb-bam-num-pipes = <4>;
+ qcom,disable-clk-gating;
+ qcom,usb-bam-override-threshold = <0x4001>;
+ qcom,usb-bam-max-mbps-highspeed = <400>;
+ qcom,usb-bam-max-mbps-superspeed = <3600>;
+ qcom,reset-bam-on-connect;
+
+ qcom,pipe0 {
+ label = "ssusb-qdss-in-0";
+ qcom,usb-bam-mem-type = <2>;
+ qcom,dir = <1>;
+ qcom,pipe-num = <0>;
+ qcom,peer-bam = <0>;
+ qcom,peer-bam-physical-address = <0x08064000>;
+ qcom,src-bam-pipe-index = <0>;
+ qcom,dst-bam-pipe-index = <0>;
+ qcom,data-fifo-offset = <0x0>;
+ qcom,data-fifo-size = <0x1800>;
+ qcom,descriptor-fifo-offset = <0x1800>;
+ qcom,descriptor-fifo-size = <0x800>;
+ };
+ };
+ };
+
+ /* Primary USB port related High Speed PHY */
+ qusb_phy0: qusb@1613000 {
+ compatible = "qcom,qusb2phy";
+ reg = <0x01613000 0x180>,
+ <0x003cb250 0x4>,
+ <0x01b40258 0x4>,
+ <0x01612000 0x4>;
+ reg-names = "qusb_phy_base",
+ "tcsr_clamp_dig_n_1p8",
+ "tune2_efuse_addr",
+ "eud_enable_reg";
+
+ vdd-supply = <&pm2250_l12>;
+ vdda18-supply = <&pm2250_l13>;
+ vdda33-supply = <&pm2250_l21>;
+ qcom,vdd-voltage-level = <0 925000 970000>;
+ qcom,tune2-efuse-bit-pos = <25>;
+ qcom,tune2-efuse-num-bits = <4>;
+ qcom,qusb-phy-init-seq = <0xf8 0x80
+ 0xb3 0x84
+ 0x83 0x88
+ 0xc0 0x8c
+ 0x30 0x08
+ 0x79 0x0c
+ 0x21 0x10
+ 0x14 0x9c
+ 0x80 0x04
+ 0x9f 0x1c
+ 0x00 0x18>;
+ phy_type = "utmi";
+ qcom,phy-clk-scheme = "cmos";
+ qcom,major-rev = <1>;
+
+ clocks = <&rpmcc CXO_SMD_OTG_CLK>,
+ <&gcc GCC_AHB2PHY_USB_CLK>;
+ clock-names = "ref_clk_src", "cfg_ahb_clk";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ reset-names = "phy_reset";
+ };
+
+ /* Primary USB port related QMP USB PHY */
+ usb_qmp_phy: ssphy@1615000 {
+ compatible = "qcom,usb-ssphy-qmp-usb3-or-dp";
+ reg = <0x01615000 0x1000>,
+ <0x03cb244 0x4>;
+ reg-names = "qmp_phy_base",
+ "vls_clamp_reg";
+
+ vdd-supply = <&pm2250_l12>;
+ core-supply = <&pm2250_l13>;
+ qcom,vdd-voltage-level = <0 925000 970000>;
+ qcom,core-voltage-level = <0 1800000 1800000>;
+ qcom,qmp-phy-init-seq =
+ /* <reg_offset, value, delay> */
+ <USB3PHY_QSERDES_COM_SYSCLK_EN_SEL 0x14 0x00
+ USB3PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x08 0x00
+ USB3PHY_QSERDES_COM_CLK_SELECT 0x30 0x00
+ USB3PHY_QSERDES_COM_SYS_CLK_CTRL 0x06 0x00
+ USB3PHY_QSERDES_COM_RESETSM_CNTRL 0x00 0x00
+ USB3PHY_QSERDES_COM_RESETSM_CNTRL2 0x08 0x00
+ USB3PHY_QSERDES_COM_BG_TRIM 0x0f 0x00
+ USB3PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x01 0x00
+ USB3PHY_QSERDES_COM_HSCLK_SEL 0x00 0x00
+ USB3PHY_QSERDES_COM_DEC_START_MODE0 0x82 0x00
+ USB3PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x55 0x00
+ USB3PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x55 0x00
+ USB3PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x03 0x00
+ USB3PHY_QSERDES_COM_CP_CTRL_MODE0 0x0b 0x00
+ USB3PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0x00
+ USB3PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x28 0x00
+ USB3PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x80 0x00
+ USB3PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x00 0x00
+ USB3PHY_QSERDES_COM_CORECLK_DIV 0x0a 0x00
+ USB3PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x15 0x00
+ USB3PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0x00
+ USB3PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x00 0x00
+ USB3PHY_QSERDES_COM_LOCK_CMP_EN 0x00 0x00
+ USB3PHY_QSERDES_COM_CORE_CLK_EN 0x00 0x00
+ USB3PHY_QSERDES_COM_LOCK_CMP_CFG 0x00 0x00
+ USB3PHY_QSERDES_COM_VCO_TUNE_MAP 0x00 0x00
+ USB3PHY_QSERDES_COM_BG_TIMER 0x0a 0x00
+ USB3PHY_QSERDES_COM_SSC_EN_CENTER 0x01 0x00
+ USB3PHY_QSERDES_COM_SSC_PER1 0x31 0x00
+ USB3PHY_QSERDES_COM_SSC_PER2 0x01 0x00
+ USB3PHY_QSERDES_COM_SSC_ADJ_PER1 0x00 0x00
+ USB3PHY_QSERDES_COM_SSC_ADJ_PER2 0x00 0x00
+ USB3PHY_QSERDES_COM_SSC_STEP_SIZE1 0xde 0x00
+ USB3PHY_QSERDES_COM_SSC_STEP_SIZE2 0x07 0x00
+ USB3PHY_QSERDES_COM_PLL_IVCO 0x0f 0x00
+ USB3PHY_QSERDES_COM_CMN_CONFIG 0x06 0x00
+ USB3PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x80 0x00
+ USB3PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x01 0x00
+ USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x0b 0x00
+ USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x0b 0x00
+ USB3PHY_QSERDES_RXA_UCDR_PI_CONTROLS 0x00 0x00
+ USB3PHY_QSERDES_RXB_UCDR_PI_CONTROLS 0x00 0x00
+ USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0x00 0x00
+ USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0x00 0x00
+ USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x00 0x00
+ USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x00 0x00
+ USB3PHY_QSERDES_RXA_UCDR_FO_GAIN 0x0a 0x00
+ USB3PHY_QSERDES_RXB_UCDR_FO_GAIN 0x0a 0x00
+ USB3PHY_QSERDES_RXA_UCDR_SO_GAIN 0x06 0x00
+ USB3PHY_QSERDES_RXB_UCDR_SO_GAIN 0x06 0x00
+ USB3PHY_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x75 0x00
+ USB3PHY_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x75 0x00
+ USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x02 0x00
+ USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x02 0x00
+ USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4e 0x00
+ USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4e 0x00
+ USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x18 0x00
+ USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x18 0x00
+ USB3PHY_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0x00
+ USB3PHY_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77 0x00
+ USB3PHY_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0x00
+ USB3PHY_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x80 0x00
+ USB3PHY_QSERDES_RXA_VGA_CAL_CNTRL2 0x0a 0x00
+ USB3PHY_QSERDES_RXB_VGA_CAL_CNTRL2 0x0a 0x00
+ USB3PHY_QSERDES_RXA_SIGDET_CNTRL 0x03 0x00
+ USB3PHY_QSERDES_RXB_SIGDET_CNTRL 0x03 0x00
+ USB3PHY_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x16 0x00
+ USB3PHY_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x16 0x00
+ USB3PHY_QSERDES_RXA_SIGDET_ENABLES 0x00 0x00
+ USB3PHY_QSERDES_RXB_SIGDET_ENABLES 0x00 0x00
+ USB3PHY_QSERDES_RXA_RX_MODE_00 0x00 0x00
+ USB3PHY_QSERDES_RXB_RX_MODE_00 0x00 0x00
+ USB3PHY_QSERDES_TXA_HIGHZ_DRVR_EN 0x10 0x00
+ USB3PHY_QSERDES_TXB_HIGHZ_DRVR_EN 0x10 0x00
+ USB3PHY_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0x00
+ USB3PHY_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0x00
+ USB3PHY_QSERDES_TXA_LANE_MODE_1 0xc6 0x00
+ USB3PHY_QSERDES_TXB_LANE_MODE_1 0xc6 0x00
+ USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x00 0x00
+ USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x00 0x00
+ USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x00 0x00
+ USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x00 0x00
+ USB3PHY_PCS_TXMGN_V0 0x9f 0x00
+ USB3PHY_PCS_TXDEEMPH_M6DB_V0 0x17 0x00
+ USB3PHY_PCS_TXDEEMPH_M3P5DB_V0 0x0f 0x00
+ USB3PHY_PCS_FLL_CNTRL2 0x83 0x00
+ USB3PHY_PCS_FLL_CNTRL1 0x02 0x00
+ USB3PHY_PCS_FLL_CNT_VAL_L 0x09 0x00
+ USB3PHY_PCS_FLL_CNT_VAL_H_TOL 0xa2 0x00
+ USB3PHY_PCS_FLL_MAN_CODE 0x85 0x00
+ USB3PHY_PCS_LOCK_DETECT_CONFIG1 0xd1 0x00
+ USB3PHY_PCS_LOCK_DETECT_CONFIG2 0x1f 0x00
+ USB3PHY_PCS_LOCK_DETECT_CONFIG3 0x47 0x00
+ USB3PHY_PCS_RXEQTRAINING_WAIT_TIME 0x75 0x00
+ USB3PHY_PCS_RXEQTRAINING_RUN_TIME 0x13 0x00
+ USB3PHY_PCS_LFPS_TX_ECSTART_EQTLOCK 0x86 0x00
+ USB3PHY_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x04 0x00
+ USB3PHY_PCS_TSYNC_RSYNC_TIME 0x44 0x00
+ USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7 0x00
+ USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0x00
+ USB3PHY_PCS_RCVR_DTCT_DLY_U3_L 0x40 0x00
+ USB3PHY_PCS_RCVR_DTCT_DLY_U3_H 0x00 0x00
+ USB3PHY_PCS_RX_SIGDET_LVL 0x88 0x00
+ 0xffffffff 0xffffffff 0x00>;
+
+ qcom,qmp-phy-reg-offset =
+ <0xd74 /* USB3_PHY_PCS_STATUS */
+ 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */
+ 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */
+ 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */
+ 0xc00 /* USB3_PHY_SW_RESET */
+ 0xc08 /* USB3_PHY_START */
+ 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&rpmcc CXO_SMD_OTG_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_AHB2PHY_USB_CLK>;
+
+ clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
+ "ref_clk", "cfg_ahb_clk";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
+ <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
+ reset-names = "phy_reset", "phy_phy_reset";
+ };
+
+ usb_nop_phy: usb_nop_phy {
+ compatible = "usb-nop-xceiv";
+ };
+
+ usb_audio_qmi_dev {
+ compatible = "qcom,usb-audio-qmi-dev";
+ iommus = <&apps_smmu 0x1cf 0x0>;
+ qcom,iommu-dma = "disabled";
+ qcom,usb-audio-stream-id = <0xf>;
+ qcom,usb-audio-intr-num = <2>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba-vidc.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba-vidc.dtsi
new file mode 100755
index 0000000..3e57fbb
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba-vidc.dtsi
@@ -0,0 +1,109 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ msm_vidc: qcom,vidc@5a00000 {
+ compatible = "qcom,msm-vidc", "qcom,scuba-vidc";
+ status = "ok";
+ reg = <0x5a00000 0x200000>;
+ interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+
+ /* Supply */
+ venus-supply = <&gcc_venus_gdsc>;
+ venus-core0-supply = <&gcc_vcodec0_gdsc>;
+
+ /* Clocks */
+ clock-names = "core_clk", "iface_clk", "bus_clk",
+ "core0_clk", "core0_bus_clk", "throttle_clk";
+ clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>,
+ <&gcc GCC_VIDEO_AHB_CLK>,
+ <&gcc GCC_VENUS_CTL_AXI_CLK>,
+ <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>,
+ <&gcc GCC_VCODEC0_AXI_CLK>,
+ <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>;
+ qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk",
+ "core0_clk", "core0_bus_clk", "throttle_clk";
+ qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0 0x0>;
+ qcom,allowed-clock-rates = <133330000 240000000>;
+
+ /* Buses */
+ bus_cnoc {
+ compatible = "qcom,msm-vidc,bus";
+ label = "cnoc";
+ qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <1000 1000>;
+ };
+
+ venus_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "vidc-ar50-ddr";
+ qcom,bus-range-kbps = <1000 2128000>;
+ };
+
+ arm9_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-arm9-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <1000 1000>;
+ };
+
+ /* MMUs */
+ non_secure_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_ns";
+ iommus =
+ <&apps_smmu 0x860 0x00>,
+ <&apps_smmu 0x880 0x00>;
+ qcom,iommu-dma-addr-pool = <0x70800000 0x6f800000>;
+ qcom,iommu-faults = "non-fatal";
+ buffer-types = <0xfff>;
+ virtual-addr-pool = <0x70800000 0x6f800000>;
+ };
+
+ secure_bitstream_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_bitstream";
+ iommus =
+ <&apps_smmu 0x861 0x04>;
+ qcom,iommu-dma-addr-pool = <0x4b000000 0x25800000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
+ buffer-types = <0x241>;
+ virtual-addr-pool = <0x4b000000 0x25800000>;
+ qcom,secure-context-bank;
+ };
+
+ secure_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_pixel";
+ iommus =
+ <&apps_smmu 0x863 0x0>;
+ qcom,iommu-dma-addr-pool = <0x25800000 0x25800000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
+ buffer-types = <0x106>;
+ virtual-addr-pool = <0x25800000 0x25800000>;
+ qcom,secure-context-bank;
+ };
+
+ secure_non_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_non_pixel";
+ iommus =
+ <&apps_smmu 0x804 0xE0>;
+ qcom,iommu-dma-addr-pool = <0x1000000 0x24800000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
+ buffer-types = <0x480>;
+ virtual-addr-pool = <0x1000000 0x24800000>;
+ qcom,secure-context-bank;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba.dts b/arch/arm64/boot/dts/vendor/qcom/scuba.dts
new file mode 100755
index 0000000..79e6891
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+
+#include "scuba.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scuba SoC";
+ compatible = "qcom,scuba";
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scuba.dtsi b/arch/arm64/boot/dts/vendor/qcom/scuba.dtsi
new file mode 100755
index 0000000..f185765
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scuba.dtsi
@@ -0,0 +1,2675 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,dispcc-scuba.h>
+#include <dt-bindings/clock/qcom,gcc-scuba.h>
+#include <dt-bindings/clock/qcom,gpucc-scuba.h>
+#include <dt-bindings/spmi/spmi.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/soc/qcom,dcc_v2.h>
+
+#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
+#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
+
+#define BW_OPP_ENTRY_DDR(mhz, w, ddrtype) opp-mhz {\
+ opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;\
+ opp-supported-hw = <ddrtype>;}
+
+#define DDR_TYPE_LPDDR3 5
+#define DDR_TYPE_LPDDR4X 7
+
+/ {
+ model = "Qualcomm Technologies, Inc. SCUBA";
+ compatible = "qcom,scuba";
+ qcom,msm-id = <441 0x10000>;
+ interrupt-parent = <&wakegic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ memory { device_type = "memory"; reg = <0 0 0 0>; };
+
+ mem-offline {
+ compatible = "qcom,mem-offline";
+ offline-sizes = <0x1 0x40000000 0x0 0x40000000>,
+ <0x1 0xc0000000 0x0 0x80000000>,
+ <0x2 0xc0000000 0x1 0x40000000>;
+ granule = <512>;
+ };
+
+ aliases {
+ sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
+ sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
+ swr0 = &swr0;
+ swr1 = &swr1;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0 4>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ #cooling-cells = <2>;
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ };
+
+ L1_I_0: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_0: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0 4>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+ L1_I_1: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_1: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0 4>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+ L1_I_2: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_2: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0 4>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+
+ L1_I_3: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_3: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ firmware: firmware {
+ android {
+ compatible = "android,firmware";
+ vbmeta {
+ compatible="android,vbmeta";
+ parts = "vbmeta,boot,system,vendor,dtbo,recovery";
+ };
+
+ fstab {
+ compatible = "android,fstab";
+ vendor {
+ compatible = "android,vendor";
+ dev = "/dev/block/platform/soc/4744000.sdhci/by-name/vendor";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,discard";
+ fsmgr_flags = "wait,slotselect,avb";
+ status = "ok";
+ };
+ };
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_region: hyp_region@45700000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45700000 0x0 0x600000>;
+ };
+
+ xbl_aop_mem: xbl_aop_mem@45e00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45e00000 0x0 0x100000>;
+ };
+
+ sec_apps_mem: sec_apps_region@45fff000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x45fff000 0x0 0x1000>;
+ };
+
+ smem_region: smem@46000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x46000000 0x0 0x200000>;
+ };
+
+ pil_modem_mem: modem_region@4ab00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x4ab00000 0x0 0x6900000>;
+ };
+
+ pil_video_mem: pil_video_region@51400000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51400000 0x0 0x500000>;
+ };
+
+ wlan_msa_mem: wlan_msa_region@51900000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51900000 0x0 0x100000>;
+ };
+
+ pil_adsp_mem: adsp_regions@51a00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x51a00000 0x0 0x1c00000>;
+ };
+
+ pil_ipa_fw_mem: ips_fw_region@53600000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x53600000 0x0 0x10000>;
+ };
+
+ pil_ipa_gsi_mem: ipa_gsi_region@53610000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x53610000 0x0 0x5000>;
+ };
+
+ pil_gpu_mem: gpu_region@53615000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x53615000 0x0 0x2000>;
+ };
+
+ removed_region: removed_region@60000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x60000000 0x0 0x3900000>;
+ };
+
+ adsp_mem: adsp_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x00000000 0 0xffffffff>;
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x800000>;
+ };
+
+ dump_mem: mem_dump_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ size = <0 0x800000>;
+ };
+
+ secure_display_memory: secure_display_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x00000000 0 0xffffffff>;
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x5c00000>;
+ };
+
+ cont_splash_memory: cont_splash_region@5c000000 {
+ reg = <0x0 0x5c000000 0x0 0x00f00000>;
+ label = "cont_splash_region";
+ };
+
+ dfps_data_memory: dfps_data_region@5cf00000 {
+ reg = <0x0 0x5cf00000 0x0 0x0100000>;
+ label = "dfps_data_region";
+ };
+
+ disp_rdump_memory: disp_rdump_region@5c000000 {
+ reg = <0x0 0x5c000000 0x0 0x00f00000>;
+ label = "disp_rdump_region";
+ };
+
+ qseecom_mem: qseecom_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1400000>;
+ };
+
+ qseecom_ta_mem: qseecom_ta_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1000000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x2000000>;
+ linux,cma-default;
+ };
+ };
+
+ chosen {
+ bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off";
+ };
+
+ soc: soc { };
+};
+
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ slim_aud: slim@a5c0000 {
+ cell-index = <1>;
+ compatible = "qcom,slim-ngd";
+ reg = <0xa5c0000 0x2c000>,
+ <0xa584000 0x20000>, <0xa66e000 0x2000>;
+ reg-names = "slimbus_physical",
+ "slimbus_bam_physical","slimbus_lpass_mem";
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "slimbus_irq", "slimbus_bam_irq";
+ qcom,apps-ch-pipes = <0x0>;
+ qcom,ea-pc = <0x360>;
+ status = "ok";
+
+ /* Slimbus Slave DT for WCN3990 */
+ btfmslim_codec: wcn3990 {
+ compatible = "qcom,btfmslim_slave";
+ elemental-addr = [00 01 20 02 17 02];
+ qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
+ qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
+ };
+ };
+
+ intc: interrupt-controller@f200000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ reg = <0xf200000 0x10000>, /* GICD */
+ <0xf300000 0x100000>; /* GICR * 8 */
+ interrupts = <1 9 4>;
+ };
+
+ wakegic: wake-gic {
+ compatible = "qcom,mpm-gic-scuba", "qcom,mpm-gic";
+ interrupts-extended = <&wakegic GIC_SPI 197
+ IRQ_TYPE_EDGE_RISING>;
+ reg = <0x45f01b8 0x1000>,
+ <0xf111008 0x4>; /* MSM_APCS_GCC_BASE 4K */
+ reg-names = "vmpm", "ipc";
+ qcom,num-mpm-irqs = <96>;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <3>;
+ };
+
+ wakegpio: wake-gpio {
+ compatible = "qcom,mpm-gpio";
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <2>;
+ };
+
+ jtag_mm0: jtagmm@9040000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9040000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU0>;
+ };
+
+ jtag_mm1: jtagmm@9140000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9140000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU1>;
+ };
+
+ jtag_mm2: jtagmm@9240000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9240000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU2>;
+ };
+
+ jtag_mm3: jtagmm@9340000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x9340000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "core_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU3>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 1 0xf08>,
+ <1 2 0xf08>,
+ <1 3 0xf08>,
+ <1 0 0xf08>;
+ clock-frequency = <19200000>;
+ };
+
+ dcc: dcc_v2@1be2000 {
+ compatible = "qcom,dcc-v2";
+ reg = <0x1be2000 0x1000>,
+ <0x1bee000 0x2000>;
+ reg-names = "dcc-base", "dcc-ram-base";
+ dcc-ram-offset = <0x2000>;
+
+ link_list1 {
+ qcom,curr-link-list = <3>;
+ qcom,data-sink = "sram";
+ qcom,link-list = <DCC_READ 0x0f1880b4 1 0>,
+ <DCC_READ 0x0f1980b4 1 0>,
+ <DCC_READ 0x0f1a80b4 1 0>,
+ <DCC_READ 0x0f1b80b4 1 0>,
+ <DCC_READ 0x0f1d1228 1 0>,
+ <DCC_READ 0x4488100 1 0>,
+ <DCC_READ 0x4488400 2 0>,
+ <DCC_READ 0x4488410 1 0>,
+ <DCC_READ 0x4488420 2 0>,
+ <DCC_READ 0x4488430 2 0>,
+ <DCC_READ 0x448c100 1 0>,
+ <DCC_READ 0x448c400 2 0>,
+ <DCC_READ 0x448c410 1 0>,
+ <DCC_READ 0x448c420 2 0>,
+ <DCC_READ 0x448c430 2 0>,
+ <DCC_READ 0x4490100 1 0>,
+ <DCC_READ 0x4490400 2 0>,
+ <DCC_READ 0x4490410 1 0>,
+ <DCC_READ 0x4490420 2 0>,
+ <DCC_READ 0x4490430 2 0>,
+ <DCC_READ 0x4494100 1 0>,
+ <DCC_READ 0x4494400 2 0>,
+ <DCC_READ 0x4494410 1 0>,
+ <DCC_READ 0x4494420 2 0>,
+ <DCC_READ 0x4494430 2 0>,
+ <DCC_READ 0x449810c 1 0>,
+ <DCC_READ 0x4498400 2 0>,
+ <DCC_READ 0x4498410 1 0>,
+ <DCC_READ 0x4498420 2 0>,
+ <DCC_READ 0x4498430 2 0>,
+ <DCC_READ 0x44a0100 1 0>,
+ <DCC_READ 0x44a0400 2 0>,
+ <DCC_READ 0x44a0410 1 0>,
+ <DCC_READ 0x44a0420 2 0>,
+ <DCC_READ 0x44a0430 2 0>,
+ <DCC_READ 0x44b0560 1 0>,
+ <DCC_READ 0x44b05a0 1 0>,
+ <DCC_READ 0x44b1800 1 0>,
+ <DCC_READ 0x44b408c 1 0>,
+ <DCC_READ 0x44b409c 1 0>,
+ <DCC_READ 0x44b0520 1 0>,
+ <DCC_READ 0x44b5070 2 0>,
+ <DCC_READ 0x44bc220 1 0>,
+ <DCC_READ 0x44bc400 7 0>,
+ <DCC_READ 0x44bc420 9 0>,
+ <DCC_READ 0x44bd800 1 0>,
+ <DCC_READ 0x44c5800 1 0>,
+ <DCC_READ 0x4480040 2 0>,
+ <DCC_READ 0x4480810 2 0>,
+ <DCC_READ 0x44b0a40 1 0>,
+ <DCC_READ 0x4506044 1 0>,
+ <DCC_READ 0x45061dc 1 0>,
+ <DCC_READ 0x45061ec 1 0>,
+ <DCC_READ 0x4506028 2 0>,
+ <DCC_READ 0x4506094 1 0>,
+ <DCC_READ 0x4506608 1 0>,
+ <DCC_READ 0x447d02c 4 0>,
+ <DCC_READ 0x447d040 1 0>,
+ <DCC_READ 0x450002c 2 0>,
+ <DCC_READ 0x4500094 1 0>,
+ <DCC_READ 0x450009c 1 0>,
+ <DCC_READ 0x45000c4 2 0>,
+ <DCC_READ 0x45003dc 1 0>,
+ <DCC_READ 0x45005d8 1 0>,
+ <DCC_READ 0x450102c 2 0>,
+ <DCC_READ 0x4501094 1 0>,
+ <DCC_READ 0x450109c 1 0>,
+ <DCC_READ 0x45010c4 2 0>,
+ <DCC_READ 0x45013dc 1 0>,
+ <DCC_READ 0x45015d8 1 0>,
+ <DCC_READ 0x450202c 2 0>,
+ <DCC_READ 0x4502094 1 0>,
+ <DCC_READ 0x450209c 1 0>,
+ <DCC_READ 0x45020c4 2 0>,
+ <DCC_READ 0x45023dc 1 0>,
+ <DCC_READ 0x45025d8 1 0>,
+ <DCC_READ 0x450302c 2 0>,
+ <DCC_READ 0x4503094 1 0>,
+ <DCC_READ 0x450309c 1 0>,
+ <DCC_READ 0x45030c4 2 0>,
+ <DCC_READ 0x45033dc 1 0>,
+ <DCC_READ 0x45035d8 1 0>,
+ <DCC_READ 0x450402c 2 0>,
+ <DCC_READ 0x4504094 1 0>,
+ <DCC_READ 0x450409c 1 0>,
+ <DCC_READ 0x45040c8 2 0>,
+ <DCC_READ 0x45043dc 1 0>,
+ <DCC_READ 0x45045d8 1 0>,
+ <DCC_READ 0x450502c 2 0>,
+ <DCC_READ 0x4505094 1 0>,
+ <DCC_READ 0x450509c 1 0>,
+ <DCC_READ 0x45050c4 2 0>,
+ <DCC_READ 0x45053dc 1 0>,
+ <DCC_READ 0x45055d8 1 0>,
+ <DCC_READ 0x1900010 1 0>,
+ <DCC_READ 0x1900020 1 0>,
+ <DCC_READ 0x1900024 1 0>,
+ <DCC_READ 0x1900028 1 0>,
+ <DCC_READ 0x190002c 1 0>,
+ <DCC_READ 0x1900030 1 0>,
+ <DCC_READ 0x1900034 1 0>,
+ <DCC_READ 0x1900038 1 0>,
+ <DCC_READ 0x190003c 1 0>,
+ <DCC_READ 0x1900240 1 0>,
+ <DCC_READ 0x1900244 1 0>,
+ <DCC_READ 0x1900248 1 0>,
+ <DCC_READ 0x190024c 1 0>,
+ <DCC_READ 0x1900250 1 0>,
+ <DCC_READ 0x1900258 1 0>,
+ <DCC_READ 0x1900290 1 0>,
+ <DCC_READ 0x1900300 1 0>,
+ <DCC_READ 0x1900304 1 0>,
+ <DCC_READ 0x1900308 1 0>,
+ <DCC_READ 0x190030c 1 0>,
+ <DCC_READ 0x1900310 1 0>,
+ <DCC_READ 0x1900314 1 0>,
+ <DCC_READ 0x1900318 1 0>,
+ <DCC_READ 0x1900900 1 0>,
+ <DCC_READ 0x1900904 1 0>,
+ <DCC_READ 0x1900d00 1 0>,
+ <DCC_READ 0x1909100 1 0>,
+ <DCC_READ 0x1909104 1 0>,
+ <DCC_READ 0x44b0120 1 0>,
+ <DCC_READ 0x44b0124 1 0>,
+ <DCC_READ 0x44b0128 1 0>,
+ <DCC_READ 0x44b012c 1 0>,
+ <DCC_READ 0x44b0130 1 0>,
+ <DCC_READ 0x44b0100 1 0>,
+ <DCC_READ 0x44b0020 1 0>,
+ <DCC_READ 0x44c4000 1 0>,
+ <DCC_READ 0x44c4020 1 0>,
+ <DCC_READ 0x44c4030 1 0>,
+ <DCC_READ 0x44c4100 1 0>,
+ <DCC_READ 0x44c410c 1 0>,
+ <DCC_READ 0x44c4400 1 0>,
+ <DCC_READ 0x44c4410 1 0>,
+ <DCC_READ 0x44c4420 1 0>,
+ <DCC_READ 0x1411004 1 0>,
+ <DCC_READ 0x1411028 1 0>,
+ <DCC_READ 0x1458004 1 0>,
+ <DCC_READ 0x1880108 1 0>,
+ <DCC_READ 0x1880110 1 0>,
+ <DCC_READ 0x1880120 1 0>,
+ <DCC_READ 0x1880124 1 0>,
+ <DCC_READ 0x1880128 1 0>,
+ <DCC_READ 0x188012c 1 0>,
+ <DCC_READ 0x1880130 1 0>,
+ <DCC_READ 0x1880134 1 0>,
+ <DCC_READ 0x1880138 1 0>,
+ <DCC_READ 0x188013c 1 0>,
+ <DCC_READ 0x1880240 1 0>,
+ <DCC_READ 0x1880248 1 0>,
+ <DCC_READ 0x1880290 1 0>,
+ <DCC_READ 0x1880300 1 0>,
+ <DCC_READ 0x1880304 1 0>,
+ <DCC_READ 0x1880308 1 0>,
+ <DCC_READ 0x188030c 1 0>,
+ <DCC_READ 0x1880310 1 0>,
+ <DCC_READ 0x1880314 1 0>,
+ <DCC_READ 0x1880318 1 0>,
+ <DCC_READ 0x188031c 1 0>,
+ <DCC_READ 0x1880700 1 0>,
+ <DCC_READ 0x1880704 1 0>,
+ <DCC_READ 0x1880708 1 0>,
+ <DCC_READ 0x188070c 1 0>,
+ <DCC_READ 0x1880710 1 0>,
+ <DCC_READ 0x1880714 1 0>,
+ <DCC_READ 0x1880718 1 0>,
+ <DCC_READ 0x188071c 1 0>,
+ <DCC_READ 0x1881100 1 0>,
+ <DCC_READ 0x1881104 1 0>,
+ <DCC_READ 0xf112000 1 0>,
+ <DCC_READ 0xf11200c 1 0>,
+ <DCC_READ 0xf112c0c 1 0>,
+ <DCC_READ 0xf112c10 1 0>,
+ <DCC_READ 0xf112c20 1 0>,
+ <DCC_READ 0xf1b9000 1 0>,
+ <DCC_READ 0xf1b900c 1 0>,
+ <DCC_READ 0xf1b9c0c 1 0>,
+ <DCC_READ 0xf1b9c10 1 0>,
+ <DCC_READ 0xf1b9c18 1 0>,
+ <DCC_READ 0xf1a9000 1 0>,
+ <DCC_READ 0xf1a900c 1 0>,
+ <DCC_READ 0xf1a9c0c 1 0>,
+ <DCC_READ 0xf1a9c10 1 0>,
+ <DCC_READ 0xf1a9c20 1 0>,
+ <DCC_READ 0xf199000 1 0>,
+ <DCC_READ 0xf19900c 1 0>,
+ <DCC_READ 0xf199c0c 1 0>,
+ <DCC_READ 0xf199c10 1 0>,
+ <DCC_READ 0xf199c20 1 0>,
+ <DCC_READ 0xf189000 1 0>,
+ <DCC_READ 0xf18900c 1 0>,
+ <DCC_READ 0xf189c0c 1 0>,
+ <DCC_READ 0xf189c10 1 0>,
+ <DCC_READ 0xf189c20 1 0>,
+ <DCC_READ 0xf111014 1 0>,
+ <DCC_READ 0xf111018 1 0>,
+ <DCC_READ 0xf111218 1 0>,
+ <DCC_READ 0xf111234 1 0>,
+ <DCC_READ 0xf111264 1 0>,
+ <DCC_READ 0xf111290 1 0>,
+ <DCC_READ 0x0f521700 1 0>,
+ <DCC_READ 0x0f112c18 1 0>,
+ <DCC_READ 0x0f513a84 1 0>,
+ <DCC_READ 0x01b60110 1 0>,
+ <DCC_READ 0x1400000 1 0>,
+ <DCC_READ 0x1400004 1 0>,
+ <DCC_READ 0x1400008 1 0>,
+ <DCC_READ 0x1400010 1 0>,
+ <DCC_READ 0x1400014 1 0>,
+ <DCC_READ 0x1400018 1 0>,
+ <DCC_READ 0x1400020 1 0>,
+ <DCC_READ 0x1400024 1 0>,
+ <DCC_READ 0x1401000 1 0>,
+ <DCC_READ 0x1401004 1 0>,
+ <DCC_READ 0x1401008 1 0>,
+ <DCC_READ 0x1401010 1 0>,
+ <DCC_READ 0x1401014 1 0>,
+ <DCC_READ 0x1401018 1 0>,
+ <DCC_READ 0x1401020 1 0>,
+ <DCC_READ 0x1401024 1 0>,
+ <DCC_READ 0x1402000 1 0>,
+ <DCC_READ 0x1402004 1 0>,
+ <DCC_READ 0x1402008 1 0>,
+ <DCC_READ 0x1402010 1 0>,
+ <DCC_READ 0x1402014 1 0>,
+ <DCC_READ 0x1402018 1 0>,
+ <DCC_READ 0x1402020 1 0>,
+ <DCC_READ 0x1402024 1 0>,
+ <DCC_READ 0x1403000 1 0>,
+ <DCC_READ 0x1403004 1 0>,
+ <DCC_READ 0x1403008 1 0>,
+ <DCC_READ 0x1403010 1 0>,
+ <DCC_READ 0x1403014 1 0>,
+ <DCC_READ 0x1403018 1 0>,
+ <DCC_READ 0x1403020 1 0>,
+ <DCC_READ 0x1403024 1 0>,
+ <DCC_READ 0x1404000 1 0>,
+ <DCC_READ 0x1404004 1 0>,
+ <DCC_READ 0x1404008 1 0>,
+ <DCC_READ 0x1404010 1 0>,
+ <DCC_READ 0x1404014 1 0>,
+ <DCC_READ 0x1404018 1 0>,
+ <DCC_READ 0x1404020 1 0>,
+ <DCC_READ 0x1404024 1 0>,
+ <DCC_READ 0x1405000 1 0>,
+ <DCC_READ 0x1405004 1 0>,
+ <DCC_READ 0x1405008 1 0>,
+ <DCC_READ 0x1405010 1 0>,
+ <DCC_READ 0x1405014 1 0>,
+ <DCC_READ 0x1405018 1 0>,
+ <DCC_READ 0x1405020 1 0>,
+ <DCC_READ 0x1405024 1 0>,
+ <DCC_READ 0x1406000 1 0>,
+ <DCC_READ 0x1406004 1 0>,
+ <DCC_READ 0x1406008 1 0>,
+ <DCC_READ 0x1406010 1 0>,
+ <DCC_READ 0x1406014 1 0>,
+ <DCC_READ 0x1406018 1 0>,
+ <DCC_READ 0x1406020 1 0>,
+ <DCC_READ 0x1406024 1 0>,
+ <DCC_READ 0x1407000 1 0>,
+ <DCC_READ 0x1407004 1 0>,
+ <DCC_READ 0x1407008 1 0>,
+ <DCC_READ 0x1407010 1 0>,
+ <DCC_READ 0x1407014 1 0>,
+ <DCC_READ 0x1407018 1 0>,
+ <DCC_READ 0x1407020 1 0>,
+ <DCC_READ 0x1407024 1 0>,
+ <DCC_READ 0x1407028 1 0>,
+ <DCC_READ 0x1408000 1 0>,
+ <DCC_READ 0x1408004 1 0>,
+ <DCC_READ 0x1408008 1 0>,
+ <DCC_READ 0x1408010 1 0>,
+ <DCC_READ 0x1408014 1 0>,
+ <DCC_READ 0x1408018 1 0>,
+ <DCC_READ 0x1408020 1 0>,
+ <DCC_READ 0x1408024 1 0>,
+ <DCC_READ 0x1409000 1 0>,
+ <DCC_READ 0x1409004 1 0>,
+ <DCC_READ 0x1409008 1 0>,
+ <DCC_READ 0x1409010 1 0>,
+ <DCC_READ 0x1409014 1 0>,
+ <DCC_READ 0x1409018 1 0>,
+ <DCC_READ 0x1409020 1 0>,
+ <DCC_READ 0x1414024 1 0>,
+ <DCC_READ 0x1416038 1 0>,
+ <DCC_READ 0x1415034 1 0>,
+ <DCC_READ 0x1417040 1 0>,
+ <DCC_READ 0x1420010 1 0>,
+ <DCC_READ 0x1420014 1 0>,
+ <DCC_READ 0x1426018 1 0>,
+ <DCC_READ 0x1426030 1 0>,
+ <DCC_READ 0x1426034 1 0>,
+ <DCC_READ 0x1427024 1 0>,
+ <DCC_READ 0x1428014 1 0>,
+ <DCC_READ 0x1428018 1 0>,
+ <DCC_READ 0x1428030 1 0>,
+ <DCC_READ 0x1429004 1 0>,
+ <DCC_READ 0x1429008 1 0>,
+ <DCC_READ 0x1429040 1 0>,
+ <DCC_READ 0x1429044 1 0>,
+ <DCC_READ 0x1446004 1 0>,
+ <DCC_READ 0x1446008 1 0>,
+ <DCC_READ 0x1446024 1 0>,
+ <DCC_READ 0x1446150 1 0>,
+ <DCC_READ 0x1442018 1 0>,
+ <DCC_READ 0x1442030 1 0>,
+ <DCC_READ 0x1442034 1 0>,
+ <DCC_READ 0x1432034 1 0>,
+ <DCC_READ 0x1438010 1 0>,
+ <DCC_READ 0x1438014 1 0>,
+ <DCC_READ 0x1438028 1 0>,
+ <DCC_READ 0x1445004 1 0>,
+ <DCC_READ 0x1445020 1 0>,
+ <DCC_READ 0x1451000 1 0>,
+ <DCC_READ 0x1451004 1 0>,
+ <DCC_READ 0x1451020 1 0>,
+ <DCC_READ 0x1451038 1 0>,
+ <DCC_READ 0x1451054 1 0>,
+ <DCC_READ 0x1451058 1 0>,
+ <DCC_READ 0x1452004 1 0>,
+ <DCC_READ 0x1452008 1 0>,
+ <DCC_READ 0x1452028 1 0>,
+ <DCC_READ 0x1455000 1 0>,
+ <DCC_READ 0x1455004 1 0>,
+ <DCC_READ 0x1448024 1 0>,
+ <DCC_READ 0x1475000 1 0>,
+ <DCC_READ 0x1475004 1 0>,
+ <DCC_READ 0x1477000 1 0>,
+ <DCC_READ 0x1477004 1 0>,
+ <DCC_READ 0x1479000 1 0>,
+ <DCC_READ 0x1479004 1 0>,
+ <DCC_READ 0x1457000 1 0>,
+ <DCC_READ 0x1457004 1 0>,
+ <DCC_READ 0x1457008 1 0>,
+ <DCC_READ 0x1457010 1 0>,
+ <DCC_READ 0x1469000 1 0>,
+ <DCC_READ 0x1469004 1 0>,
+ <DCC_READ 0x1469008 1 0>,
+ <DCC_READ 0x1469010 1 0>,
+ <DCC_READ 0x1495000 1 0>,
+ <DCC_READ 0x1495004 1 0>,
+ <DCC_READ 0x1463020 1 0>,
+ <DCC_READ 0x1478030 1 0>,
+ <DCC_READ 0x1490004 1 0>,
+ <DCC_READ 0x1490008 1 0>,
+ <DCC_READ 0x1490024 1 0>,
+ <DCC_READ 0x1490028 1 0>,
+ <DCC_READ 0x1407030 1 0>,
+ <DCC_READ 0x1407034 1 0>,
+ <DCC_READ 0x1432080 1 0>,
+ <DCC_READ 0xf017000 1 0>,
+ <DCC_READ 0xf01700c 1 0>,
+ <DCC_READ 0xf017010 1 0>,
+ <DCC_READ 0xf017014 1 0>,
+ <DCC_READ 0xf017018 1 0>,
+ <DCC_READ 0xf017020 1 0>,
+ <DCC_READ 0x1414008 1 0>,
+ <DCC_READ 0x1414004 1 0>,
+ <DCC_READ 0x5991554 1 0>,
+ <DCC_READ 0x5991544 1 0>,
+ <DCC_READ 0x599155c 1 0>,
+ <DCC_READ 0x440b00c 1 0>,
+ <DCC_READ 0x440b014 1 0>,
+ <DCC_READ 0x0f522c14 1 0>,
+ <DCC_READ 0x0f522c1c 1 0>,
+ <DCC_READ 0x0f522c10 1 0>,
+ <DCC_READ 0x0f521920 1 0>,
+ <DCC_READ 0x0f52102c 1 0>,
+ <DCC_READ 0x0f521044 1 0>,
+ <DCC_READ 0x0f521710 1 0>,
+ <DCC_READ 0x0f52176c 1 0>,
+ <DCC_READ 0x0f116000 1 0>,
+ <DCC_READ 0x0f116004 1 0>,
+ <DCC_READ 0x0f11602c 1 0>,
+ <DCC_READ 0x0f111250 1 0>,
+ <DCC_READ 0x0f111254 1 0>,
+ <DCC_READ 0x0f111258 1 0>,
+ <DCC_READ 0x0f11125c 1 0>,
+ <DCC_READ 0x0f111260 1 0>,
+ <DCC_READ 0x0f188078 1 0>,
+ <DCC_READ 0x0f188084 1 0>,
+ <DCC_READ 0x0f198078 1 0>,
+ <DCC_READ 0x0f198084 1 0>,
+ <DCC_READ 0x0f1a8078 1 0>,
+ <DCC_READ 0x0f1a8084 1 0>,
+ <DCC_READ 0x0f1b8078 1 0>,
+ <DCC_READ 0x0f1b8084 1 0>,
+ <DCC_READ 0x0f521818 1 0>,
+ <DCC_READ 0x0f52181c 1 0>,
+ <DCC_READ 0x0f521828 1 0>,
+ <DCC_READ 0x0f522c18 1 0>,
+ <DCC_READ 0x0f111310 1 0>,
+ <DCC_READ 0x0f111314 1 0>,
+ <DCC_READ 0x0f111318 1 0>,
+ <DCC_WRITE 0x9870010 0x14000 1>,
+ <DCC_WRITE 0x9870010 0x0 1>,
+ <DCC_READ 0x5c6f000 1 0>,
+ <DCC_READ 0x5c42000 1 0>,
+ <DCC_READ 0x5c42400 1 0>,
+ <DCC_READ 0x5c23000 1 0>;
+ };
+ };
+
+ timer@f120000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0xf120000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@f121000 {
+ frame-number = <0>;
+ interrupts = <0 8 0x4>,
+ <0 7 0x4>;
+ reg = <0xf121000 0x1000>,
+ <0xf122000 0x1000>;
+ };
+
+ frame@f123000 {
+ frame-number = <1>;
+ interrupts = <0 9 0x4>;
+ reg = <0xf123000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f124000 {
+ frame-number = <2>;
+ interrupts = <0 10 0x4>;
+ reg = <0xf124000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f125000 {
+ frame-number = <3>;
+ interrupts = <0 11 0x4>;
+ reg = <0xf125000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f126000 {
+ frame-number = <4>;
+ interrupts = <0 12 0x4>;
+ reg = <0xf126000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f127000 {
+ frame-number = <5>;
+ interrupts = <0 13 0x4>;
+ reg = <0xf127000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@f128000 {
+ frame-number = <6>;
+ interrupts = <0 14 0x4>;
+ reg = <0xf128000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ arm64_cpu_erp {
+ compatible = "arm,arm64-cpu-erp";
+ interrupt-names = "pri-dbe-irq",
+ "pri-ext-irq";
+ interrupts = <0 43 4>,
+ <0 41 4>;
+ poll-delay-ms = <5000>;
+ };
+
+ qcom,msm-imem@c125000 {
+ compatible = "qcom,msm-imem";
+ reg = <0xc125000 0x1000>;
+ ranges = <0x0 0xc125000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mem_dump_table@10 {
+ compatible = "qcom,msm-imem-mem_dump_table";
+ reg = <0x10 0x8>;
+ };
+
+ restart_reason@65c {
+ compatible = "qcom,msm-imem-restart_reason";
+ reg = <0x65c 0x4>;
+ };
+
+ dload_type@1c {
+ compatible = "qcom,msm-imem-dload-type";
+ reg = <0x1c 0x4>;
+ };
+
+ boot_stats@6b0 {
+ compatible = "qcom,msm-imem-boot_stats";
+ reg = <0x6b0 0x20>;
+ };
+
+ kaslr_offset@6d0 {
+ compatible = "qcom,msm-imem-kaslr_offset";
+ reg = <0x6d0 0xc>;
+ };
+
+ pil@94c {
+ compatible = "qcom,msm-imem-pil";
+ reg = <0x94c 0xc8>;
+ };
+
+ diag_dload@c8 {
+ compatible = "qcom,msm-imem-diag-dload";
+ reg = <0xc8 0xc8>;
+ };
+ };
+
+ restart@440b000 {
+ compatible = "qcom,pshold";
+ reg = <0x440b000 0x4>,
+ <0x03d3000 0x4>;
+ reg-names = "pshold-base", "tcsr-boot-misc-detect";
+ };
+
+ qcom_hwkm: hwkm@4440000 {
+ compatible = "qcom,hwkm";
+ reg = <0x4440000 0x9000>, <0x4750000 0x9000>;
+ reg-names = "km_master", "ice_slave";
+ qcom,enable-hwkm-clk;
+ clock-names = "km_clk_src";
+ clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
+ qcom,op-freq-hz = <75000000>;
+ };
+
+ qcom_seecom: qseecom@61800000 {
+ compatible = "qcom,qseecom";
+ reg = <0x61800000 0x2100000>;
+ reg-names = "secapp-region";
+ memory-region = <&qseecom_mem>;
+ qcom,hlos-num-ce-hw-instances = <1>;
+ qcom,hlos-ce-hw-instance = <0>;
+ qcom,qsee-ce-hw-instance = <0>;
+ qcom,disk-encrypt-pipe-pair = <2>;
+ qcom,support-fde;
+ qcom,fde-key-size;
+ qcom,appsbl-qseecom-support;
+ qcom,commonlib64-loaded-by-uefi;
+ qcom,msm-bus,name = "qseecom-noc";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 0 0>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 200000 400000>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 300000 800000>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 400000 1000000>;
+ clock-names =
+ "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks =
+ <&rpmcc QSEECOM_CE1_CLK>,
+ <&rpmcc QSEECOM_CE1_CLK>,
+ <&rpmcc QSEECOM_CE1_CLK>,
+ <&rpmcc QSEECOM_CE1_CLK>;
+ qcom,ce-opp-freq = <192000000>;
+ qcom,qsee-reentrancy-support = <2>;
+ };
+
+ qcom_smcinvoke: smcinvoke@61800000 {
+ compatible = "qcom,smcinvoke";
+ reg = <0x61800000 0x2100000>;
+ reg-names = "secapp-region";
+ };
+
+ qcom_tzlog: tz-log@c125720 {
+ compatible = "qcom,tz-log";
+ reg = <0xc125720 0x3000>;
+ qcom,hyplog-enabled;
+ hyplog-address-offset = <0x410>;
+ hyplog-size-offset = <0x414>;
+ };
+
+ qcom_rng: qrng@4453000 {
+ compatible = "qcom,msm-rng";
+ reg = <0x4453000 0x1000>;
+ qcom,msm-rng-hwkm-clk;
+ qcom,no-qrng-config;
+ qcom,msm-bus,name = "msm-rng-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_HWKM 0 0>, /* No vote */
+ <MSM_BUS_MASTER_AMPSS_M0
+ MSM_BUS_SLAVE_HWKM 0 300000>; /* 75 MHz */
+ clock-names = "km_clk_src";
+ clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
+ };
+
+ qcom_cedev: qcedev@1b20000 {
+ compatible = "qcom,qcedev";
+ reg = <0x1b20000 0x20000>,
+ <0x1b04000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <3>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,ce-hw-shared;
+ qcom,bam-ee = <0>;
+ qcom,msm-bus,name = "qcedev-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 0 0>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST 393600 393600>;
+ clock-names =
+ "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks =
+ <&rpmcc QCEDEV_CE1_CLK>,
+ <&rpmcc QCEDEV_CE1_CLK>,
+ <&rpmcc QCEDEV_CE1_CLK>,
+ <&rpmcc QCEDEV_CE1_CLK>;
+ qcom,ce-opp-freq = <192000000>;
+ qcom,smmu-s1-enable;
+ iommus = <&apps_smmu 0x0086 0x0011>,
+ <&apps_smmu 0x0096 0x0011>;
+ qcom,iommu-dma = "atomic";
+
+ qcom_cedev_ns_cb {
+ compatible = "qcom,qcedev,context-bank";
+ label = "ns_context";
+ iommus = <&apps_smmu 0x92 0>,
+ <&apps_smmu 0x98 0x1>,
+ <&apps_smmu 0x9F 0>;
+ };
+
+ qcom_cedev_s_cb {
+ compatible = "qcom,qcedev,context-bank";
+ label = "secure_context";
+ iommus = <&apps_smmu 0x93 0>,
+ <&apps_smmu 0x9C 0x1>,
+ <&apps_smmu 0x9E 0>;
+ qcom,iommu-vmid = <0x9>; /* VMID_CP_BITSTREAM */
+ qcom,secure-context-bank;
+ };
+ };
+
+ qcom_crypto: qcrypto@1b20000 {
+ compatible = "qcom,qcrypto";
+ reg = <0x1b20000 0x20000>,
+ <0x1b04000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <2>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,bam-ee = <0>;
+ qcom,ce-hw-shared;
+ qcom,clk-mgmt-sus-res;
+ qcom,msm-bus,name = "qcrypto-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST
+ 0 0>,
+ <MSM_BUS_MASTER_CRYPTO_CORE0
+ MSM_BUS_SLAVE_FIRST
+ 393600 393600>;
+ clock-names =
+ "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks =
+ <&rpmcc QCRYPTO_CE1_CLK>,
+ <&rpmcc QCRYPTO_CE1_CLK>,
+ <&rpmcc QCRYPTO_CE1_CLK>,
+ <&rpmcc QCRYPTO_CE1_CLK>;
+ qcom,use-sw-aes-cbc-ecb-ctr-algo;
+ qcom,use-sw-aes-xts-algo;
+ qcom,use-sw-aes-ccm-algo;
+ qcom,use-sw-ahash-algo;
+ qcom,use-sw-aead-algo;
+ qcom,use-sw-hmac-algo;
+ qcom,smmu-s1-enable;
+ iommus = <&apps_smmu 0x0084 0x0011>,
+ <&apps_smmu 0x0094 0x0011>;
+ qcom,iommu-dma = "atomic";
+ };
+
+ qcom,mpm2-sleep-counter@4403000 {
+ compatible = "qcom,mpm2-sleep-counter";
+ reg = <0x4403000 0x1000>;
+ clock-frequency = <32768>;
+ };
+
+ qcom,memshare {
+ compatible = "qcom,memshare";
+
+ qcom,client_1 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x0>;
+ qcom,client-id = <0>;
+ qcom,allocate-boot-time;
+ label = "modem";
+ };
+
+ qcom,client_2 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x0>;
+ qcom,client-id = <2>;
+ label = "modem";
+ };
+
+ mem_client_3_size: qcom,client_3 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x500000>;
+ qcom,client-id = <1>;
+ qcom,allocate-on-request;
+ label = "modem";
+ };
+ };
+
+ qcom,msm-rtb {
+ compatible = "qcom,msm-rtb";
+ qcom,rtb-size = <0x100000>;
+ };
+
+ cpu_pmu: cpu-pmu {
+ compatible = "arm,armv8-pmuv3";
+ qcom,irq-is-percpu;
+ interrupts = <1 6 4>;
+ };
+
+ qcom,chd_silver {
+ compatible = "qcom,core-hang-detect";
+ label = "silver";
+ qcom,threshold-arr = <0x0f1880b0 0x0f1980b0
+ 0x0f1a80b0 0x0f1b80b0>;
+ qcom,config-arr = <0x0f1880b8 0x0f1980b8
+ 0x0f1a80b8 0x0f1b80b8>;
+ };
+
+ eud: qcom,msm-eud@1610000 {
+ compatible = "qcom,msm-eud";
+ interrupt-names = "eud_irq";
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x1610000 0x2000>,
+ <0x1612000 0x1000>,
+ <0x3E5018 0x4>;
+ reg-names = "eud_base", "eud_mode_mgr2",
+ "eud_tcsr_check_reg";
+ qcom,secure-eud-en;
+ qcom,eud-tcsr-check-enable;
+ qcom,eud-clock-vote-req;
+ clocks = <&gcc GCC_AHB2PHY_USB_CLK>;
+ clock-names = "eud_ahb2phy_clk";
+ status = "ok";
+ };
+
+ wdog: qcom,wdt@f017000 {
+ compatible = "qcom,msm-watchdog";
+ reg = <0xf017000 0x1000>;
+ reg-names = "wdt-base";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bark-time = <11000>;
+ qcom,pet-time = <9360>;
+ qcom,ipi-ping;
+ qcom,wakeup-enable;
+ };
+
+ qfprom: qfprom@1b40000 {
+ compatible = "qcom,qfprom";
+ reg = <0x1b40000 0x7000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ read-only;
+ ranges;
+
+ feat_conf5: feat_conf5@6018 {
+ reg = <0x6018 0x4>;
+ };
+
+ gpu_speed_bin: gpu_speed_bin@6006 {
+ reg = <0x6006 0x2>;
+ bits = <5 8>;
+ };
+
+ adsp_variant: adsp_variant@6011 {
+ reg = <0x6011 0x1>;
+ bits = <3 1>;
+ };
+ };
+
+ qcom,sps {
+ compatible = "qcom,msm-sps-4k";
+ qcom,pipe-attr-ee;
+ };
+
+ qcom,lpass@ab00000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0xab00000 0x00100>;
+
+ clocks = <&rpmcc CXO_SMD_PIL_LPASS_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+ qcom,mas-crypto = <&mas_crypto_c0>;
+
+ vdd_lpi_cx-supply = <&VDD_LPI_CX_LEVEL>;
+ qcom,vdd_lpi_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ vdd_lpi_mx-supply = <&VDD_LPI_MX_LEVEL>;
+ qcom,vdd_lpi_mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
+ qcom,proxy-reg-names = "vdd_lpi_cx", "vdd_lpi_mx";
+
+ qcom,firmware-name = "adsp";
+ memory-region = <&pil_adsp_mem>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,sysmon-id = <1>;
+ qcom,minidump-id = <5>;
+ qcom,ssctl-instance-id = <0x14>;
+ qcom,pas-id = <1>;
+ qcom,smem-id = <423>;
+ qcom,complete-ramdump;
+ qcom,minidump-as-elf32;
+
+ /* Inputs from lpass */
+ interrupts-extended = <&intc 0 282 IRQ_TYPE_LEVEL_HIGH>,
+ <&adsp_smp2p_in 0 0>,
+ <&adsp_smp2p_in 2 0>,
+ <&adsp_smp2p_in 1 0>,
+ <&adsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack";
+
+ /* Outputs to lpass */
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+ };
+
+ qcom,venus@5ab0000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x5ab0000 0x20000>;
+
+ vdd-supply = <&gcc_venus_gdsc>;
+ qcom,proxy-reg-names = "vdd";
+
+ clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>,
+ <&gcc GCC_VENUS_CTL_AXI_CLK>,
+ <&gcc GCC_VIDEO_AHB_CLK>,
+ <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>;
+ clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk";
+ qcom,proxy-clock-names = "core_clk", "bus_clk", "iface_clk", "throttle_clk";
+ qcom,mas-crypto = <&mas_crypto_c0>;
+
+ qcom,core-freq = <240000000>;
+ qcom,ahb-freq = <240000000>;
+
+ qcom,pas-id = <9>;
+ qcom,msm-bus,name = "pil-venus";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <63 512 0 0>,
+ <63 512 0 304000>;
+ qcom,proxy-timeout-ms = <100>;
+ qcom,firmware-name = "venus";
+ memory-region = <&pil_video_mem>;
+ };
+
+ cx_ipeak_lm: cx_ipeak@3ed000 {
+ compatible = "qcom,cx-ipeak-v2";
+ reg = <0x3ed000 0xe008>;
+ interrupts = <0 415 IRQ_TYPE_EDGE_RISING>,
+ <0 416 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "cx_ipeak_danger", "cx_ipeak_safe";
+ victims_table = <4 0 844800000>;
+ };
+
+ pil_modem: qcom,mss@6080000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x6080000 0x100>;
+
+ clocks = <&rpmcc CXO_SMD_PIL_MSS_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+ qcom,mas-crypto = <&mas_crypto_c0>;
+
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,vdd_cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
+ qcom,proxy-reg-names = "vdd_cx";
+
+ qcom,firmware-name = "modem";
+ memory-region = <&pil_modem_mem>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,sysmon-id = <0>;
+ qcom,ssctl-instance-id = <0x12>;
+ qcom,pas-id = <4>;
+ qcom,smem-id = <421>;
+ qcom,minidump-id = <3>;
+ qcom,aux-minidump-ids = <4>;
+ qcom,complete-ramdump;
+ qcom,sequential-fw-load;
+
+ /* Inputs from mss */
+ interrupts-extended = <&intc 0 307 1>,
+ <&modem_smp2p_in 0 0>,
+ <&modem_smp2p_in 2 0>,
+ <&modem_smp2p_in 1 0>,
+ <&modem_smp2p_in 3 0>,
+ <&modem_smp2p_in 7 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack",
+ "qcom,shutdown-ack";
+
+ /* Outputs to mss */
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+ };
+
+ thermal_zones: thermal-zones { };
+
+ tsens0:tsens@04410000 {
+ compatible = "qcom,tsens24xx";
+ reg = <0x04410000 0x8>,
+ <0x04411000 0x1ff>;
+ reg-names = "tsens_srot_physical",
+ "tsens_tm_physical";
+ interrupts = <0 275 0>, <0 190 0>;
+ interrupt-names = "tsens-upper-lower", "tsens-critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ rpm_bus: qcom,rpm-smd {
+ compatible = "qcom,rpm-smd";
+ rpm-channel-name = "rpm_requests";
+ interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+ rpm-channel-type = <15>; /* SMD_APPS_RPM */
+ };
+
+ mem_dump {
+ compatible = "qcom,mem-dump";
+ memory-region = <&dump_mem>;
+
+ c0_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x0>;
+ };
+
+ c1_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x1>;
+ };
+
+ c2_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x2>;
+ };
+
+ c3_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x3>;
+ };
+
+ l1_icache0 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x60>;
+ };
+
+ l1_icache1 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x61>;
+ };
+
+ l1_icache2 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x62>;
+ };
+
+ l1_icache3 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x63>;
+ };
+
+ l1_dcache0 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x80>;
+ };
+
+ l1_dcache1 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x81>;
+ };
+
+ l1_dcache2 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x82>;
+ };
+
+ l1_dcache3 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x83>;
+ };
+
+ l2_tlb0 {
+ qcom,dump-size = <0x2000>;
+ qcom,dump-id = <0x120>;
+ };
+
+ l2_tlb1 {
+ qcom,dump-size = <0x2000>;
+ qcom,dump-id = <0x121>;
+ };
+
+ l2_tlb2 {
+ qcom,dump-size = <0x2000>;
+ qcom,dump-id = <0x122>;
+ };
+
+ l2_tlb3 {
+ qcom,dump-size = <0x2000>;
+ qcom,dump-id = <0x123>;
+ };
+
+ rpm_sw {
+ qcom,dump-size = <0x28000>;
+ qcom,dump-id = <0xea>;
+ };
+
+ pmic {
+ qcom,dump-size = <0x40000>;
+ qcom,dump-id = <0xe4>;
+ };
+
+ fcm {
+ qcom,dump-size = <0x8400>;
+ qcom,dump-id = <0xee>;
+ };
+
+ tmc_etf {
+ qcom,dump-size = <0x8000>;
+ qcom,dump-id = <0xf0>;
+ };
+
+ etr_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x100>;
+ };
+
+ etf_reg {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x101>;
+ };
+
+ misc_data {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xe8>;
+ };
+ };
+
+ sdhc_1: sdhci@4744000 {
+ compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe";
+ reg = <0x4744000 0x1000>, <0x4745000 0x1000>, <0x4748000 0x8000>;
+ reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";
+
+ interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <8>;
+ qcom,large-address-bus;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
+ 192000000 384000000>;
+ qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+
+ qcom,devfreq,freq-table = <50000000 200000000>;
+
+ qcom,scaling-lower-bus-speed-mode = "DDR52";
+
+ /* PM QoS */
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <43 43>;
+ qcom,pm-qos-cpu-groups = <0x0f>;
+ qcom,pm-qos-cmdq-latency-us = <43 43>;
+ qcom,pm-qos-legacy-latency-us = <43 43>;
+
+ qcom,msm-bus,name = "sdhc1";
+ qcom,msm-bus,num-cases = <9>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <78 512 0 0>, <1 606 0 0>,
+ /* 400 KB/s*/
+ <78 512 1046 1600>,
+ <1 606 1600 1600>,
+ /* 20 MB/s */
+ <78 512 20480 80000>,
+ <1 606 80000 80000>,
+ /* 25 MB/s */
+ <78 512 25600 250000>,
+ <1 606 50000 133320>,
+ /* 50 MB/s */
+ <78 512 51200 250000>,
+ <1 606 65000 133320>,
+ /* 100 MB/s */
+ <78 512 102400 250000>,
+ <1 606 65000 133320>,
+ /* 200 MB/s */
+ <78 512 204800 800000>,
+ <1 606 200000 300000>,
+ /* 400 MB/s */
+ <78 512 204800 800000>,
+ <1 606 200000 300000>,
+ /* Max. bandwidth */
+ <78 512 1338562 4096000>,
+ <1 606 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100750000 200000000 400000000 4294967295>;
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface_clk", "core_clk", "ice_core_clk";
+
+ qcom,ice-clk-rates = <300000000 100000000>;
+
+ /* Add support for gcc hw reset */
+ resets = <&gcc GCC_SDCC1_BCR>;
+ reset-names = "core_reset";
+
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x000f642c 0x0 0x0 0x00010800 0x80040868>;
+ qcom,nonremovable;
+ status = "disabled";
+ };
+
+ sdhc_2: sdhci@4784000 {
+ compatible = "qcom,sdhci-msm-v5";
+ reg = <0x4784000 0x1000>;
+ reg-names = "hc_mem";
+
+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <4>;
+ qcom,large-address-bus;
+
+ qcom,clk-rates = <400000 20000000 25000000
+ 50000000 100000000 202000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
+ "SDR104";
+
+ qcom,devfreq,freq-table = <50000000 202000000>;
+
+ /* PM QoS */
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <43 43>;
+ qcom,pm-qos-cpu-groups = <0x0f>;
+ qcom,pm-qos-legacy-latency-us = <43 43>;
+
+ qcom,msm-bus,name = "sdhc2";
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <81 512 0 0>, <1 608 0 0>,
+ /* 400 KB/s*/
+ <81 512 1046 3200>,
+ <1 608 1600 1600>,
+ /* 20 MB/s */
+ <81 512 52286 250000>,
+ <1 608 80000 133320>,
+ /* 25 MB/s */
+ <81 512 65360 250000>,
+ <1 608 100000 133320>,
+ /* 50 MB/s */
+ <81 512 130718 250000>,
+ <1 608 133320 133320>,
+ /* 100 MB/s */
+ <81 512 261438 250000>,
+ <1 608 150000 133320>,
+ /* 200 MB/s */
+ <81 512 261438 800000>,
+ <1 608 300000 300000>,
+ /* Max. bandwidth */
+ <81 512 1338562 4096000>,
+ <1 608 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100750000 200000000 4294967295>;
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>;
+ clock-names = "iface_clk", "core_clk";
+
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x0007642c 0x0 0x0 0x00010800 0x80040868>;
+
+ status = "disabled";
+ };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <38400000>;
+ clock-output-names = "xo_board";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32764>;
+ clock-output-names = "chip_sleep_clk";
+ #clock-cells = <0>;
+ };
+ };
+
+ rpmcc: qcom,rpmcc {
+ compatible = "qcom,rpmcc-scuba";
+ #clock-cells = <1>;
+ };
+
+ qcom,rmtfs_sharedmem@0 {
+ compatible = "qcom,sharedmem-uio";
+ reg = <0x0 0x200000>;
+ reg-names = "rmtfs";
+ qcom,client-id = <0x00000001>;
+ qcom,guard-memory;
+ qcom,vm-nav-path;
+ };
+
+ gcc: qcom,gcc@1400000 {
+ compatible = "qcom,scuba-gcc", "syscon";
+ reg = <0x1400000 0x1f0000>;
+ reg-names = "cc_base";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
+ vdd_mx-supply = <&VDD_MX_LEVEL>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ dispcc: qcom,dispcc@5f00000 {
+ compatible = "qcom,scuba-dispcc", "syscon";
+ reg = <0x5f00000 0x20000>;
+ reg-names = "cc_base";
+ clock-names = "cfg_ahb_clk";
+ clocks = <&gcc GCC_DISP_AHB_CLK>;
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gpucc: qcom,gpucc@5990000 {
+ compatible = "qcom,scuba-gpucc", "syscon";
+ reg = <0x5990000 0x9000>;
+ reg-names = "cc_base";
+ vdd_cx-supply = <&VDD_CX_LEVEL>;
+ qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ mccc_debug: syscon@447d200 {
+ compatible = "syscon";
+ reg = <0x447d200 0x100>;
+ };
+
+ cpucc_debug: syscon@f11101c {
+ compatible = "syscon";
+ reg = <0xf11101c 0x4>;
+ };
+
+ debugcc: qcom,cc-debug {
+ compatible = "qcom,scuba-debugcc";
+ qcom,gcc = <&gcc>;
+ qcom,dispcc = <&dispcc>;
+ qcom,gpucc = <&gpucc>;
+ qcom,mccc = <&mccc_debug>;
+ qcom,cpucc = <&cpucc_debug>;
+ clock-names = "xo_clk_src";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ #clock-cells = <1>;
+ };
+
+ cpufreq_hw: qcom,cpufreq-hw {
+ compatible = "qcom,cpufreq-hw";
+ reg = <0xf521000 0x1400>;
+ reg-names = "freq-domain0";
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+ qcom,no-accumulative-counter;
+ qcom,max-lut-entries = <12>;
+ #freq-domain-cells = <2>;
+ };
+
+ qcom,cpufreq-hw-debug@f521000 {
+ compatible = "qcom,cpufreq-hw-debug";
+ reg = <0xf521000 0x1400>;
+ reg-names = "domain-top";
+ qcom,freq-hw-domain = <&cpufreq_hw 0>;
+ };
+
+ ddr_bw_opp_table: ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY_DDR( 200, 8, 0xA0); /* 1525 MB/s */
+ BW_OPP_ENTRY_DDR( 300, 8, 0xA0); /* 2288 MB/s */
+ BW_OPP_ENTRY_DDR( 451, 8, 0xA0); /* 3440 MB/s */
+ BW_OPP_ENTRY_DDR( 547, 8, 0xA0); /* 4173 MB/s */
+ BW_OPP_ENTRY_DDR( 681, 8, 0xA0); /* 5195 MB/s */
+ BW_OPP_ENTRY_DDR( 768, 8, 0xA0); /* 5859 MB/s */
+ BW_OPP_ENTRY_DDR( 931, 8, 0x20); /* 7102 MB/s */
+ BW_OPP_ENTRY_DDR(1017, 8, 0x80); /* 7759 MB/s */
+ BW_OPP_ENTRY_DDR(1353, 8, 0x80); /*10322 MB/s */
+ BW_OPP_ENTRY_DDR(1555, 8, 0x80); /*11863 MB/s */
+ BW_OPP_ENTRY_DDR(1804, 8, 0x80); /*13763 MB/s */
+ };
+
+ suspendable_ddr_bw_opp_table: suspendable-ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY_DDR( 0, 8, 0xA0); /* 0 MB/s */
+ BW_OPP_ENTRY_DDR( 200, 8, 0xA0); /* 1525 MB/s */
+ BW_OPP_ENTRY_DDR( 300, 8, 0xA0); /* 2288 MB/s */
+ BW_OPP_ENTRY_DDR( 451, 8, 0xA0); /* 3440 MB/s */
+ BW_OPP_ENTRY_DDR( 547, 8, 0xA0); /* 4173 MB/s */
+ BW_OPP_ENTRY_DDR( 681, 8, 0xA0); /* 5195 MB/s */
+ BW_OPP_ENTRY_DDR( 768, 8, 0xA0); /* 5859 MB/s */
+ BW_OPP_ENTRY_DDR( 931, 8, 0x20); /* 7102 MB/s */
+ BW_OPP_ENTRY_DDR(1017, 8, 0x80); /* 7759 MB/s */
+ BW_OPP_ENTRY_DDR(1353, 8, 0x80); /*10322 MB/s */
+ BW_OPP_ENTRY_DDR(1555, 8, 0x80); /*11863 MB/s */
+ BW_OPP_ENTRY_DDR(1804, 8, 0x80); /*13763 MB/s */
+ };
+
+ cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@01b8e200 {
+ compatible = "qcom,bimc-bwmon4";
+ reg = <0x01b8e300 0x100>, <0x01b8e200 0x100>;
+ reg-names = "base", "global_base";
+ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&cpu_cpu_ddr_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat {
+ compatible = "qcom,devbw-ddr";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,target-dev = <&cpu0_cpu_ddr_lat>;
+ qcom,cachemiss-ev = <0x17>;
+ ddr3-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR3>;
+ qcom,core-dev-table =
+ < 614400 MHZ_TO_MBPS( 200, 8) >,
+ < 1017600 MHZ_TO_MBPS( 451, 8) >,
+ < 1420000 MHZ_TO_MBPS( 547, 8) >,
+ < 1612800 MHZ_TO_MBPS( 768, 8) >,
+ < 2000000 MHZ_TO_MBPS( 931, 8) >;
+ };
+
+ ddr4-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
+ qcom,core-dev-table =
+ < 614400 MHZ_TO_MBPS( 451, 8) >,
+ < 1017600 MHZ_TO_MBPS( 768, 8) >,
+ < 1420000 MHZ_TO_MBPS(1017, 8) >,
+ < 1612800 MHZ_TO_MBPS(1555, 8) >,
+ < 2000000 MHZ_TO_MBPS(1804, 8) >;
+ };
+ };
+
+ cpu0_computemon: qcom,cpu0-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
+ ddr3-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR3>;
+ qcom,core-dev-table =
+ < 864000 MHZ_TO_MBPS( 200, 8) >,
+ < 1017600 MHZ_TO_MBPS( 300, 8) >,
+ < 1420000 MHZ_TO_MBPS( 451, 8) >,
+ < 1804800 MHZ_TO_MBPS( 547, 8) >,
+ < 2000000 MHZ_TO_MBPS( 931, 8) >;
+ };
+
+ ddr4-map {
+ qcom,ddr-type = <DDR_TYPE_LPDDR4X>;
+ qcom,core-dev-table =
+ < 864000 MHZ_TO_MBPS( 300, 8) >,
+ < 1017600 MHZ_TO_MBPS( 547, 8) >,
+ < 1420000 MHZ_TO_MBPS( 768, 8) >,
+ < 1804800 MHZ_TO_MBPS(1017, 8) >,
+ < 2000000 MHZ_TO_MBPS(1804, 8) >;
+ };
+ };
+ };
+
+ tcsr_mutex_block: syscon@00340000 {
+ compatible = "syscon";
+ reg = <0x340000 0x20000>;
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_block 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ smem: qcom,smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_region>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ rpm_msg_ram: memory@045f0000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x45f0000 0x7000>;
+ };
+
+ apcs_glb: mailbox@0f111000 {
+ compatible = "qcom,scuba-apcs-hmss-global";
+ reg = <0xF111000 0x1000>;
+
+ #mbox-cells = <1>;
+ };
+
+ qcom,msm-adsprpc-mem {
+ compatible = "qcom,msm-adsprpc-mem-region";
+ memory-region = <&adsp_mem>;
+ restrict-access;
+ };
+
+ qcom,msm_fastrpc {
+ compatible = "qcom,msm-fastrpc-compute";
+ qcom,rpc-latency-us = <611>;
+ qcom,adsp-remoteheap-vmid = <22 37>;
+ qcom,fastrpc-adsp-audio-pdr;
+ qcom,fastrpc-adsp-sensors-pdr;
+
+ qcom,msm_fastrpc_compute_cb1 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C3 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb2 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C4 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb3 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C5 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb4 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C6 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ qcom,msm_fastrpc_compute_cb5 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&apps_smmu 0x01C7 0x0>;
+ qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
+ qcom,iommu-faults = "stall-disable", "HUPCF";
+ };
+
+ };
+
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ qcom,rpm_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_adsp>;
+ };
+
+ };
+
+ qcom,glink {
+ compatible = "qcom,glink";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ glink_modem: modem {
+ qcom,remote-pid = <1>;
+ transport = "smem";
+ mboxes = <&apcs_glb 12>;
+ mbox-names = "mpss_smem";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
+
+ label = "modem";
+ qcom,glink-label = "mpss";
+
+ qcom,modem_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,low-latency;
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,modem_ds {
+ qcom,glink-channels = "DS";
+ qcom,intents = <0x4000 2>;
+ };
+
+ qcom,modem_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_adsp>;
+ };
+ };
+
+ glink_adsp: adsp {
+ qcom,remote-pid = <2>;
+ transport = "smem";
+ mboxes = <&apcs_glb 8>;
+ mbox-names = "adsp_smem";
+ interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
+
+ label = "adsp";
+ qcom,glink-label = "lpass";
+
+ qcom,adsp_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,low-latency;
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,apr_tal_rpmsg {
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,intents = <0x200 20>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,adsp_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>;
+ };
+ };
+ };
+
+ qcom,glinkpkt {
+ compatible = "qcom,glinkpkt";
+
+ qcom,glinkpkt-at-mdm0 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DS";
+ qcom,glinkpkt-dev-name = "at_mdm0";
+ };
+
+ qcom,glinkpkt-apr-apps2 {
+ qcom,glinkpkt-edge = "adsp";
+ qcom,glinkpkt-ch-name = "apr_apps2";
+ qcom,glinkpkt-dev-name = "apr_apps2";
+ };
+
+ qcom,glinkpkt-data40-cntl {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA40_CNTL";
+ qcom,glinkpkt-dev-name = "smdcntl8";
+ };
+
+ qcom,glinkpkt-data1 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA1";
+ qcom,glinkpkt-dev-name = "smd7";
+ };
+
+ qcom,glinkpkt-data4 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA4";
+ qcom,glinkpkt-dev-name = "smd8";
+ };
+
+ qcom,glinkpkt-data11 {
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA11";
+ qcom,glinkpkt-dev-name = "smd11";
+ };
+ };
+
+ qcom,smp2p_sleepstate {
+ compatible = "qcom,smp2p-sleepstate";
+ qcom,smem-states = <&sleepstate_smp2p_out 0>;
+ interrupt-parent = <&sleepstate_smp2p_in>;
+ interrupts = <0 0>;
+ interrupt-names = "smp2p-sleepstate-in";
+ };
+
+ qcom,smp2p-modem {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 14>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ /* ipa - inbound entry from mss */
+ smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
+ qcom,entry-name = "wlan";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ };
+
+ qcom,smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 10>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
+ qcom,entry-name = "rdbg";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
+ qcom,entry-name = "rdbg";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sleepstate_smp2p_out: sleepstate-out {
+ qcom,entry-name = "sleepstate";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ sleepstate_smp2p_in: qcom,sleepstate-in {
+ qcom,entry-name = "sleepstate_see";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ spmi_bus: qcom,spmi@1c40000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x1c40000 0x1100>,
+ <0x1e00000 0x2000000>,
+ <0x3e00000 0x100000>,
+ <0x3f00000 0xa0000>,
+ <0x1c0a000 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
+ bluetooth: bt_wcn3990 {
+ compatible = "qca,wcn3990";
+ qca,bt-sw-ctrl-gpio = <&tlmm 87 0>; /* SW_CTRL */
+ qca,bt-vdd-io-supply = <&L15A>; /* IO */
+ qca,bt-vdd-core-supply = <&L10A>; /* RFA */
+ qca,bt-vdd-pa-supply = <&L22A>; /* CH0 */
+ qca,bt-vdd-xtal-supply = <&L13A>; /* XO */
+
+ qca,bt-vdd-io-voltage-level = <1700000 1900000>;
+ qca,bt-vdd-core-voltage-level = <1304000 1304000>;
+ /*To support 2.85V level for LDO22 at lower SOC level*/
+ qca,bt-vdd-pa-voltage-level = <2850000 3312000>;
+ qca,bt-vdd-xtal-voltage-level = <1700000 1900000>;
+
+ qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */
+ };
+
+ icnss: qcom,icnss@C800000 {
+ compatible = "qcom,icnss";
+ reg = <0xC800000 0x800000>,
+ <0xb0000000 0x10000>;
+ reg-names = "membase", "smmu_iova_ipa";
+ iommus = <&apps_smmu 0x1A0 0x1>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
+ <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
+ <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
+ <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH /* CE10 */ >,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH /* CE11 */ >;
+ qcom,iommu-dma = "fastmap";
+ qcom,psf-supported;
+ qcom,iommu-faults = "stall-disable", "HUPCF", "non-fatal";
+ qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
+ qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
+ vdd-cx-mx-supply = <&L7A>;
+ vdd-1.8-xo-supply = <&L13A>;
+ vdd-1.3-rfa-supply = <&L10A>;
+ vdd-3.3-ch0-supply = <&L22A>;
+ qcom,vdd-cx-mx-config = <640000 640000>;
+ /*To support 2.85V level for LDO22 at lower SOC level*/
+ qcom,vdd-3.3-ch0-config = <2850000 3312000>;
+ qcom,smp2p_map_wlan_1_in {
+ interrupts-extended = <&smp2p_wlan_1_in 0 0>,
+ <&smp2p_wlan_1_in 1 0>;
+ interrupt-names = "qcom,smp2p-force-fatal-error",
+ "qcom,smp2p-early-crash-ind";
+ };
+ };
+
+ qcom,msm_gsi {
+ compatible = "qcom,msm_gsi";
+ };
+
+ qcom,rmnet-ipa {
+ compatible = "qcom,rmnet-ipa3";
+ qcom,rmnet-ipa-ssr;
+ qcom,ipa-platform-type-msm;
+ qcom,ipa-advertise-sg-support;
+ qcom,ipa-napi-enable;
+ };
+
+ qcom,ipa_fws {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <0xf>;
+ qcom,firmware-name = "scuba_ipa_fws";
+ qcom,pil-force-shutdown;
+ memory-region = <&pil_ipa_fw_mem>;
+ };
+
+ ipa_hw: qcom,ipa@0x5800000 {
+ compatible = "qcom,ipa";
+ reg = <0x5800000 0x34000>,
+ <0x5804000 0x28000>;
+ reg-names = "ipa-base", "gsi-base";
+ interrupts = <0 257 0>, <0 259 0>;
+ interrupt-names = "ipa-irq", "gsi-irq";
+ qcom,ipa-hw-ver = <16>; /* IPA core version = IPAv4.2 */
+ qcom,ipa-hw-mode = <0>;
+ qcom,platform-type = <1>; /* MSM platform */
+ qcom,ee = <0>;
+ qcom,use-ipa-tethering-bridge;
+ qcom,modem-cfg-emb-pipe-flt;
+ qcom,ipa-wdi2;
+ qcom,ipa-wdi2_over_gsi;
+ qcom,ipa-endp-delay-wa;
+ qcom,use-ipa-pm;
+ qcom,arm-smmu;
+ qcom,smmu-fast-map;
+ qcom,use-64-bit-dma-mask;
+ qcom,ipa-fltrt-not-hashable;
+ qcom,skip-ieob-mask-wa;
+ qcom,msm-bus,name = "ipa";
+ qcom,use-gsi-ipa-fw = "scuba_ipa_fws";
+ clocks = <&rpmcc RPM_SMD_IPA_CLK>;
+ clock-names = "core_clk";
+ qcom,msm-bus,num-cases = <5>;
+ qcom,msm-bus,num-paths = <3>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 0 0>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 0 0>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 0 0>,
+ /* SVS2 */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 465000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 68570>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 30>,
+ /* SVS */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 80000 2000000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 80000 267461>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 80000 109890>,
+ /* NOMINAL */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 4000000>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 712961>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 491520>,
+ /* TURBO */
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_EBI_CH0 206000 5598900>,
+ <MSM_BUS_MASTER_IPA MSM_BUS_SLAVE_OCIMEM 206000 1436481>,
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_IPA_CFG 206000 491520>;
+ qcom,bus-vector-names =
+ "MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
+ qcom,throughput-threshold = <310 600 1000>;
+ qcom,scaling-exceptions = <>;
+
+ /* smp2p information */
+ qcom,smp2p_map_ipa_1_out {
+ compatible = "qcom,smp2p-map-ipa-1-out";
+ qcom,smem-states = <&smp2p_ipa_1_out 0>;
+ qcom,smem-state-names = "ipa-smp2p-out";
+ };
+
+ qcom,smp2p_map_ipa_1_in {
+ compatible = "qcom,smp2p-map-ipa-1-in";
+ interrupts-extended = <&smp2p_ipa_1_in 0 0>;
+ interrupt-names = "ipa-smp2p-in";
+ };
+ };
+
+ ipa_smmu_ap: ipa_smmu_ap {
+ compatible = "qcom,ipa-smmu-ap-cb";
+ iommus = <&apps_smmu 0x0140 0x0>;
+ qcom,iommu-dma-addr-pool = <0x10000000 0x30000000>;
+ /* modem tables in IMEM */
+ qcom,additional-mapping = <0x0c123000 0x0c123000 0x2000>;
+ qcom,iommu-dma = "fastmap";
+ qcom,iommu-geometry = <0 0xB0000000>;
+ };
+
+ ipa_smmu_wlan: ipa_smmu_wlan {
+ compatible = "qcom,ipa-smmu-wlan-cb";
+ iommus = <&apps_smmu 0x141 0x0>;
+ /* ipa-uc ram */
+ qcom,iommu-dma = "atomic";
+ };
+
+ ipa_smmu_uc: ipa_smmu_uc {
+ compatible = "qcom,ipa-smmu-uc-cb";
+ iommus = <&apps_smmu 0x0142 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40400000 0x1fc00000>;
+ };
+
+};
+
+#include "pm2250.dtsi"
+#include "scuba-thermal.dtsi"
+#include "scuba-coresight.dtsi"
+#include "scuba-pinctrl.dtsi"
+#include "scuba-ion.dtsi"
+#include "pm2250-rpm-regulator.dtsi"
+#include "scuba-regulator.dtsi"
+#include "scuba-gdsc.dtsi"
+#include "scuba-qupv3.dtsi"
+#include "scuba-audio.dtsi"
+#include "scuba-usb.dtsi"
+#include "msm-arm-smmu-scuba.dtsi"
+#include "scuba-bus.dtsi"
+#include "scuba-gpu.dtsi"
+#include "scuba-vidc.dtsi"
+
+&qupv3_se1_i2c {
+ status = "ok";
+ #include "pm8008.dtsi"
+};
+
+&pm8008_8 {
+ /* PM8008 IRQ STAT */
+ interrupt-parent = <&tlmm>;
+ interrupts = <25 IRQ_TYPE_EDGE_RISING>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pm8008_active &pm8008_interrupt>;
+};
+
+&pm8008_regulators {
+ vdd_l1_l2-supply = <&S3A>;
+};
+
+&L1P {
+ regulator-max-microvolt = <1260000>;
+ qcom,min-dropout-voltage = <75000>;
+};
+
+&L2P {
+ regulator-max-microvolt = <1150000>;
+ qcom,min-dropout-voltage = <187500>;
+};
+
+&L3P {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+};
+
+&L4P {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+};
+
+&L5P {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+};
+
+&L6P {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <2900000>;
+};
+
+&L7P {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1900000>;
+};
+
+&pm2250_vadc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&conn_therm_default &skin_therm_default>;
+
+ xo_therm {
+ reg = <ADC_XO_THERM_PU2>;
+ label = "xo_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ pa_therm {
+ reg = <ADC_AMUX_THM1_PU2>;
+ label = "pa_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ quiet_therm {
+ reg = <ADC_AMUX_THM2_PU2>;
+ label = "quiet_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ msm_therm {
+ reg = <ADC_AMUX_THM3_PU2>;
+ label = "msm_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ skin_therm {
+ reg = <ADC_GPIO3_PU2>;
+ label = "skin_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+
+ conn_therm {
+ reg = <ADC_GPIO4_PU2>;
+ label = "conn_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,pre-scaling = <1 1>;
+ };
+};
+
+&pm2250_gpios {
+ skin_therm {
+ skin_therm_default: skin_therm_default {
+ pins = "gpio5";
+ bias-high-impedance;
+ };
+ };
+
+ conn_therm {
+ conn_therm_default: conn_therm_default {
+ pins = "gpio6";
+ bias-high-impedance;
+ };
+ };
+};
+
+&spmi_bus {
+ qcom,pm2250@0 {
+ pm2250_adc_tm_iio: adc_tm@3400 {
+ compatible = "qcom,adc-tm5-iio";
+ reg = <0x3400 0x100>;
+ #thermal-sensor-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ io-channels = <&pm2250_vadc ADC_XO_THERM_PU2>,
+ <&pm2250_vadc ADC_AMUX_THM1_PU2>,
+ <&pm2250_vadc ADC_AMUX_THM2_PU2>,
+ <&pm2250_vadc ADC_AMUX_THM3_PU2>,
+ <&pm2250_vadc ADC_GPIO3_PU2>,
+ <&pm2250_vadc ADC_GPIO4_PU2>,
+ <&pm2250_vadc ADC_SBUx>;
+
+ xo_therm {
+ reg = <ADC_XO_THERM_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ pa_therm {
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ quiet_therm {
+ reg = <ADC_AMUX_THM2_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ msm_therm {
+ reg = <ADC_AMUX_THM3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ skin_therm {
+ reg = <ADC_GPIO3_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ conn_therm {
+ reg = <ADC_GPIO4_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ s3_die_temp {
+ reg = <ADC_SBUx>;
+ };
+ };
+ };
+};
+
+&gcc_camss_top_gdsc {
+ status = "ok";
+};
+
+&gcc_usb30_prim_gdsc {
+ status = "ok";
+};
+
+&gcc_vcodec0_gdsc {
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&gcc_venus_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_turing_mmu_tbu1_gdsc {
+ status = "ok";
+};
+
+&hlos1_vote_turing_mmu_tbu0_gdsc {
+ status = "ok";
+};
+
+&mdss_core_gdsc {
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&gpu_cx_gdsc {
+ status = "ok";
+};
+
+&gpu_gx_gdsc {
+ status = "ok";
+};
+
+&qupv3_se4_2uart {
+ status = "ok";
+};
+
+&qupv3_se3_4uart {
+ status = "ok";
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_vol_up>;
+
+ vol_up {
+ label = "vol_up";
+ gpios = <&tlmm 96 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ };
+ };
+};
+
+#include "scuba-pm.dtsi"
+#include "scuba-sde.dtsi"
+#include "scuba-sde-pll.dtsi"
+#include "camera/scuba-camera.dtsi"
+
+&msm_vidc {
+ qcom,cx-ipeak-data = <&cx_ipeak_lm 6>;
+ qcom,clock-freq-threshold = <240000000>;
+};
+
+#include "msm-rdbg-scuba.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/scubap-idp-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/scubap-idp-2gb.dts
new file mode 100755
index 0000000..83bec4b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scubap-idp-2gb.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "scuba-low-ram.dtsi"
+#include "scuba-idp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scubap IDP 2GB DDR";
+ compatible = "qcom,scuba-idp", "qcom,scuba", "qcom,idp";
+ qcom,msm-id = <471 0x10000>;
+ qcom,board-id = <34 0x400>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scubap-idp.dts b/arch/arm64/boot/dts/vendor/qcom/scubap-idp.dts
new file mode 100755
index 0000000..03b75e8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scubap-idp.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+#include "scuba.dtsi"
+#include "scuba-idp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scubap IDP";
+ compatible = "qcom,scuba-idp", "qcom,scuba", "qcom,idp";
+ qcom,msm-id = <471 0x10000>;
+ qcom,board-id = <34 0>;
+};
+
+&soc {
+ qcom,rmnet-ipa {
+ status = "disabled";
+ };
+};
+
+&ipa_hw {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scubap-iot-idp-2gb.dts b/arch/arm64/boot/dts/vendor/qcom/scubap-iot-idp-2gb.dts
new file mode 100755
index 0000000..47ae827
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scubap-iot-idp-2gb.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+#include "scuba-iot-low-ram.dtsi"
+#include "scuba-iot-idp.dtsi"
+#include "scuba-iot-qcs.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scubap IOT IDP 2GB DDR";
+ compatible = "qcom,scuba-idp", "qcom,scubap-iot", "qcom,idp";
+ qcom,msm-id = <474 0x10000>;
+ qcom,board-id = <34 0x400>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scubap-iot-idp.dts b/arch/arm64/boot/dts/vendor/qcom/scubap-iot-idp.dts
new file mode 100755
index 0000000..f0fc8e8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scubap-iot-idp.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+#include "scuba-iot.dtsi"
+#include "scuba-iot-idp.dtsi"
+#include "scuba-iot-qcs.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scubap IOT IDP";
+ compatible = "qcom,scuba-idp", "qcom,scubap-iot", "qcom,idp";
+ qcom,msm-id = <474 0x10000>;
+ qcom,board-id = <34 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scubap-iot.dts b/arch/arm64/boot/dts/vendor/qcom/scubap-iot.dts
new file mode 100755
index 0000000..5f2be84
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scubap-iot.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "scuba-iot.dtsi"
+#include "scuba-iot-qcs.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scubap IOT SoC";
+ compatible = "qcom,scubap-iot";
+ qcom,msm-id = <474 0x10000>;
+ qcom,board-id = <0 0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/scubap.dts b/arch/arm64/boot/dts/vendor/qcom/scubap.dts
new file mode 100755
index 0000000..04a4670
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/scubap.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+
+#include "scuba.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. Scubap SoC";
+ compatible = "qcom,scuba";
+ qcom,msm-id = <471 0x10000>;
+ qcom,board-id = <0 0>;
+};
+
+&soc {
+ qcom,rmnet-ipa {
+ status = "disabled";
+ };
+};
+
+&ipa_hw {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda429-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/sda429-cdp.dts
new file mode 100755
index 0000000..a83064d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda429-cdp.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sda429.dtsi"
+#include "sdm429-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA429 CDP";
+ compatible = "qcom,sda429-cdp", "qcom,sda429", "qcom,cdp";
+ qcom,board-id = <1 3>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda429-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/sda429-mtp.dts
new file mode 100755
index 0000000..737da2b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda429-mtp.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sda429.dtsi"
+#include "sdm429-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA429 MTP";
+ compatible = "qcom,sda429-mtp", "qcom,sda429", "qcom,mtp";
+ qcom,board-id = <8 2>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda429.dts b/arch/arm64/boot/dts/vendor/qcom/sda429.dts
new file mode 100755
index 0000000..dbc2e7d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda429.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "sda429.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA429 CDP";
+ compatible = "qcom,sda429-cdp", "qcom,sda429", "qcom,cdp";
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+ qcom.pmic-name = "PMI632";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda429.dtsi b/arch/arm64/boot/dts/vendor/qcom/sda429.dtsi
new file mode 100755
index 0000000..b1d8c97
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda429.dtsi
@@ -0,0 +1,8 @@
+#include "sdm429.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA429";
+ compatible = "qcom,sda429";
+ qcom,msm-id = <364 0x0>;
+ qcom,msm-name = "SDA429";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda439-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/sda439-cdp.dts
new file mode 100755
index 0000000..65606ba
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda439-cdp.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sda439.dtsi"
+#include "sdm439-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA439 CDP";
+ compatible = "qcom,sda439-cdp", "qcom,sda439", "qcom,cdp";
+ qcom,board-id = <1 2>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda439-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/sda439-mtp.dts
new file mode 100755
index 0000000..e68aa38
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda439-mtp.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sda439.dtsi"
+#include "sdm439-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA439 MTP";
+ compatible = "qcom,sda439-mtp", "qcom,sda439", "qcom,mtp";
+ qcom,board-id = <8 1>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda439.dts b/arch/arm64/boot/dts/vendor/qcom/sda439.dts
new file mode 100755
index 0000000..b20984d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda439.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "sda439.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA439";
+ compatible = "qcom,sda439";
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+ qcom.pmic-name = "PMI632";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda439.dtsi b/arch/arm64/boot/dts/vendor/qcom/sda439.dtsi
new file mode 100755
index 0000000..179250b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda439.dtsi
@@ -0,0 +1,8 @@
+#include "sdm439.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA439";
+ compatible = "qcom,sda439";
+ qcom,msm-id = <363 0x0>;
+ qcom,msm-name = "SDA439";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda660-cdp-external-codec-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sda660-cdp-external-codec-overlay.dts
new file mode 100755
index 0000000..4eda628
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda660-cdp-external-codec-overlay.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,cpu-osm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm660-cdp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA 660 Ext. Audio Codec CDP";
+ compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp";
+ qcom,msm-id = <324 0x0>;
+ qcom,board-id = <1 0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
+&tasha_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda660-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/sda660-cdp.dts
new file mode 100755
index 0000000..a95258d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda660-cdp.dts
@@ -0,0 +1,24 @@
+/dts-v1/;
+
+#include "sda660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660L CDP";
+ compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp";
+ qcom,board-id = <1 0>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
+&tasha_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda660-mtp-external-codec-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sda660-mtp-external-codec-overlay.dts
new file mode 100755
index 0000000..aef887a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda660-mtp-external-codec-overlay.dts
@@ -0,0 +1,22 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,cpu-osm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm660-mtp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA 660 Ext. Audio Codec MTP";
+ compatible = "qcom,sda660-mtp", "qcom,sda660", "qcom,mtp";
+ qcom,msm-id = <324 0x0>;
+ qcom,board-id = <8 0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-moist-cfg = <0>, <0>, <3>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda660-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/sda660-mtp.dts
new file mode 100755
index 0000000..81f0b03
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda660-mtp.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+#include "sda660.dtsi"
+#include "sdm660-mtp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660L MTP";
+ compatible = "qcom,sda660-mtp", "qcom,sda660", "qcom,mtp";
+ qcom,board-id = <8 0>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-moist-cfg = <0>, <0>, <3>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda660-pm660a-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/sda660-pm660a-cdp.dts
new file mode 100755
index 0000000..d6b0e12
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda660-pm660a-cdp.dts
@@ -0,0 +1,25 @@
+/dts-v1/;
+
+#include "sda660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "msm-pm660a.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660A CDP";
+ compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp";
+ qcom,board-id = <1 0>;
+ qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>,
+ <0x0001001b 0x0002001a 0x0 0x0>,
+ <0x0001001b 0x0202001a 0x0 0x0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
+&tasha_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda660-pm660a-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/sda660-pm660a-mtp.dts
new file mode 100755
index 0000000..f0f85e4
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda660-pm660a-mtp.dts
@@ -0,0 +1,19 @@
+/dts-v1/;
+
+#include "sda660.dtsi"
+#include "sdm660-mtp.dtsi"
+#include "msm-pm660a.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660A MTP";
+ compatible = "qcom,sda660-mtp", "qcom,sda660", "qcom,mtp";
+ qcom,board-id = <8 0>;
+ qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>,
+ <0x0001001b 0x0002001a 0x0 0x0>,
+ <0x0001001b 0x0202001a 0x0 0x0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-moist-cfg = <0>, <0>, <3>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda660-pm660a-qrd-hdk.dts b/arch/arm64/boot/dts/vendor/qcom/sda660-pm660a-qrd-hdk.dts
new file mode 100755
index 0000000..8037e6d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda660-pm660a-qrd-hdk.dts
@@ -0,0 +1,229 @@
+/dts-v1/;
+
+#include "sda660.dtsi"
+#include "sdm660-qrd.dtsi"
+#include "msm-pm660a.dtsi"
+
+&smb1351_charger {
+ status = "disabled";
+};
+
+&i2c_2 {
+ smb138x: qcom,smb138x@8 {
+ compatible = "qcom,i2c-pmic";
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ interrupt_names = "smb138x";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ qcom,periph-map = <0x10 0x11 0x12 0x13 0x14 0x16 0x36>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_int_default>;
+
+ smb138x_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ smb138x_tadc: qcom,tadc@3600 {
+ compatible = "qcom,tadc";
+ reg = <0x3600 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #io-channel-cells = <1>;
+ interrupt-parent = <&smb138x>;
+ interrupts = <0x36 0x0 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "eoc";
+
+ batt_temp@0 {
+ reg = <0>;
+ qcom,rbias = <68100>;
+ qcom,rtherm-at-25degc = <68000>;
+ qcom,beta-coefficient = <3450>;
+ };
+
+ skin_temp@1 {
+ reg = <1>;
+ qcom,rbias = <33000>;
+ qcom,rtherm-at-25degc = <68000>;
+ qcom,beta-coefficient = <3450>;
+ };
+
+ die_temp@2 {
+ reg = <2>;
+ qcom,scale = <(-1306)>;
+ qcom,offset = <397904>;
+ };
+
+ batt_i@3 {
+ reg = <3>;
+ qcom,channel = <3>;
+ qcom,scale = <(-20000000)>;
+ };
+
+ batt_v@4 {
+ reg = <4>;
+ qcom,scale = <5000000>;
+ };
+
+ input_i@5 {
+ reg = <5>;
+ qcom,scale = <14285714>;
+ };
+
+ input_v@6 {
+ reg = <6>;
+ qcom,scale = <25000000>;
+ };
+
+ otg_i@7 {
+ reg = <7>;
+ qcom,scale = <5714286>;
+ };
+ };
+
+ smb1381_charger: qcom,smb1381-charger@1000 {
+ compatible = "qcom,smb138x-parallel-slave";
+ qcom,pmic-revid = <&smb138x_revid>;
+ reg = <0x1000 0x700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&smb138x>;
+ io-channels =
+ <&smb138x_tadc 1>,
+ <&smb138x_tadc 2>,
+ <&smb138x_tadc 3>,
+ <&smb138x_tadc 14>,
+ <&smb138x_tadc 15>,
+ <&smb138x_tadc 16>,
+ <&smb138x_tadc 17>;
+ io-channel-names =
+ "connector_temp",
+ "charger_temp",
+ "batt_i",
+ "connector_temp_thr1",
+ "connector_temp_thr2",
+ "connector_temp_thr3",
+ "charger_temp_max";
+
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts = <0x10 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "chg-state-change";
+ };
+
+ qcom,chgr-misc@1600 {
+ reg = <0x1600 0x100>;
+ interrupts = <0x16 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x16 0x6 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog-bark",
+ "temperature-change";
+ };
+ };
+ };
+};
+
+&tlmm {
+ smb_int_default: smb_int_default {
+ mux {
+ pins = "gpio21";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio21";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+};
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660A QRD HDK660";
+ compatible = "qcom,sda660-qrd", "qcom,sda660", "qcom,qrd";
+ qcom,board-id = <0x0016000b 0>;
+ qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>,
+ <0x0001001b 0x0002001a 0x0 0x0>,
+ <0x0001001b 0x0202001a 0x0 0x0>;
+};
+
+&pm660a_oledb {
+ status = "okay";
+ qcom,oledb-default-voltage-mv = <6400>;
+};
+
+&mdss_mdp {
+ qcom,mdss-pref-prim-intf = "dsi";
+};
+
+&mdss_dp_ctrl {
+ pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
+ pinctrl-0 = <&mdss_dp_aux_active &mdss_dp_usbplug_cc_active>;
+ pinctrl-1 = <&mdss_dp_aux_suspend &mdss_dp_usbplug_cc_suspend>;
+ qcom,aux-en-gpio = <&tlmm 55 0>;
+ qcom,aux-sel-gpio = <&tlmm 56 0>;
+ qcom,usbplug-cc-gpio = <&tlmm 58 0>;
+};
+
+&mdss_dsi {
+ hw-config = "single_dsi";
+};
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_rm67195_amoled_fhd_cmd>;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+ pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+ lab-supply = <&lab_regulator>;
+ ibb-supply = <&ibb_regulator>;
+ qcom,platform-reset-gpio = <&tlmm 53 0>;
+ qcom,platform-te-gpio = <&tlmm 59 0>;
+};
+
+&dsi_rm67195_amoled_fhd_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>;
+};
+
+&tasha_snd {
+ qcom,audio-routing =
+ "AIF4 VI", "MCLK",
+ "RX_BIAS", "MCLK",
+ "MADINPUT", "MCLK",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Headset Mic",
+ "DMIC0", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic0",
+ "DMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic3",
+ "DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "SpkrLeft IN", "SPK1 OUT";
+ qcom,msm-mbhc-hphl-swh = <0>;
+};
+
+&usb2s {
+ status = "okay";
+};
+
+&qusb_phy0 {
+ reg = <0x0c012000 0x180>,
+ <0x00188018 0x4>;
+ reg-names = "qusb_phy_base",
+ "ref_clk_addr";
+ qcom,qusb-phy-init-seq = <0xf8 0x80
+ 0xb3 0x84
+ 0x83 0x88
+ 0xc7 0x8c
+ 0x30 0x08
+ 0x79 0x0c
+ 0x21 0x10
+ 0x14 0x9c
+ 0x9f 0x1c
+ 0x00 0x18>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda660-pm660a-rcm.dts b/arch/arm64/boot/dts/vendor/qcom/sda660-pm660a-rcm.dts
new file mode 100755
index 0000000..12508fa
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda660-pm660a-rcm.dts
@@ -0,0 +1,23 @@
+/dts-v1/;
+
+#include "sda660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "msm-pm660a.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660A RCM";
+ compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp";
+ qcom,board-id = <21 0>;
+ qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
+&tasha_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda660-pm660l.dts b/arch/arm64/boot/dts/vendor/qcom/sda660-pm660l.dts
new file mode 100755
index 0000000..3f7ec20
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda660-pm660l.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sda660.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA 660 PM660L SoC";
+ compatible = "qcom,sda660";
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda660-rcm-external-codec-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sda660-rcm-external-codec-overlay.dts
new file mode 100755
index 0000000..2919fbf
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda660-rcm-external-codec-overlay.dts
@@ -0,0 +1,29 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,cpu-osm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm660-cdp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA 660 Ext. Audio Codec RCM";
+ compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp";
+ qcom,msm-id = <324 0x0>;
+ qcom,board-id = <21 0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
+&tasha_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda660-rcm.dts b/arch/arm64/boot/dts/vendor/qcom/sda660-rcm.dts
new file mode 100755
index 0000000..43e307e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda660-rcm.dts
@@ -0,0 +1,23 @@
+/dts-v1/;
+
+#include "sda660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA 660 PM660 + PM660L RCM";
+ compatible = "qcom,sda660-cdp", "qcom,sda660", "qcom,cdp";
+ qcom,board-id = <21 0>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
+&tasha_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sda660.dtsi b/arch/arm64/boot/dts/vendor/qcom/sda660.dtsi
new file mode 100755
index 0000000..a61d758
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sda660.dtsi
@@ -0,0 +1,17 @@
+#include "sdm660.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDA 660";
+ compatible = "qcom,sda660";
+ qcom,msm-id = <324 0x0>;
+};
+
+&soc {
+ qcom,rmnet-ipa {
+ status = "disabled";
+ };
+};
+
+&ipa_hw {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm429-cdp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm429-cdp-overlay.dts
new file mode 100755
index 0000000..dfd4b9f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm429-cdp-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+#include "sdm429-cdp.dtsi"
+
+/ {
+ model = "CDP";
+ qcom,board-id = <1 3>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm429-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm429-cdp.dts
new file mode 100755
index 0000000..0620e57
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm429-cdp.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sdm429.dtsi"
+#include "sdm429-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM429 CDP";
+ compatible = "qcom,sdm429-cdp", "qcom,sdm429", "qcom,cdp";
+ qcom,board-id = <1 3>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm429-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm429-cdp.dtsi
new file mode 100755
index 0000000..c40c41f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm429-cdp.dtsi
@@ -0,0 +1,5 @@
+#include "sdm439-cdp.dtsi"
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_hx8399c_hd_vid>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm429-cpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm429-cpu.dtsi
new file mode 100755
index 0000000..944023a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm429-cpu.dtsi
@@ -0,0 +1,139 @@
+/ {
+ /delete-node/ cpus;
+ /delete-node/ energy-costs;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+ };
+
+ CPU0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_0>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L2_1: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ };
+
+ L1_I_100: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_100: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_0>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L1_I_101: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_101: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU2: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x102>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_0>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L1_I_102: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_102: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU3: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x103>;
+ enable-method = "psci";
+ cpu-release-addr = <0x0 0x90000000>;
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_0>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L1_I_103: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_103: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ };
+
+ energy_costs: energy-costs {
+
+ CPU_COST_0: core-cost0 {
+ busy-cost-data = <
+ 488 159
+ 663 207
+ 761 256
+ 868 327
+ 917 343
+ 995 445
+ 1024 470
+ >;
+ };
+ };
+};
+
+&soc {
+ cpuss_dump {
+ /delete-node/ qcom,l2_dump0;
+ /delete-node/ qcom,l1_i_cache0;
+ /delete-node/ qcom,l1_i_cache1;
+ /delete-node/ qcom,l1_i_cache2;
+ /delete-node/ qcom,l1_i_cache3;
+ /delete-node/ qcom,l1_d_cache0;
+ /delete-node/ qcom,l1_d_cache1;
+ /delete-node/ qcom,l1_d_cache2;
+ /delete-node/ qcom,l1_d_cache3;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm429-mtp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm429-mtp-overlay.dts
new file mode 100755
index 0000000..af05bb5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm429-mtp-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+#include "sdm429-mtp.dtsi"
+
+/ {
+ model = "MTP";
+ qcom,board-id = <8 2>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm429-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm429-mtp.dts
new file mode 100755
index 0000000..a51f6aa
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm429-mtp.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sdm429.dtsi"
+#include "sdm429-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM429 MTP";
+ compatible = "qcom,sdm429-mtp", "qcom,sdm429", "qcom,mtp";
+ qcom,board-id = <8 2>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm429-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm429-mtp.dtsi
new file mode 100755
index 0000000..0a637d0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm429-mtp.dtsi
@@ -0,0 +1,5 @@
+#include "sdm439-mtp.dtsi"
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_hx8399c_hd_vid>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm429-qrd-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm429-qrd-overlay.dts
new file mode 100755
index 0000000..7e4e599
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm429-qrd-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+#include "sdm429-qrd.dtsi"
+
+/ {
+ model = "QRD";
+ qcom,board-id = <0xb 3>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm429-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/sdm429-qrd.dts
new file mode 100755
index 0000000..ff82315
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm429-qrd.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sdm429.dtsi"
+#include "sdm429-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM429 QRD";
+ compatible = "qcom,sdm429-qrd", "qcom,sdm429", "qcom,qrd";
+ qcom,board-id = <0xb 3>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm429-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm429-qrd.dtsi
new file mode 100755
index 0000000..8598b22
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm429-qrd.dtsi
@@ -0,0 +1,5 @@
+#include "sdm439-qrd.dtsi"
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_hx8399c_hd_vid>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm429.dts b/arch/arm64/boot/dts/vendor/qcom/sdm429.dts
new file mode 100755
index 0000000..bd795bb
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm429.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "sdm429.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM429 MTP";
+ compatible = "qcom,sdm429";
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+ qcom.pmic-name = "PMI632";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm429.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm429.dtsi
new file mode 100755
index 0000000..bbe4452
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm429.dtsi
@@ -0,0 +1,256 @@
+#include "sdm439.dtsi"
+#include "sdm429-cpu.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM429";
+ compatible = "qcom,sdm429";
+ qcom,msm-id = <354 0x0>;
+};
+
+&soc {
+ /delete-node/ etm@619c000;
+ /delete-node/ etm@619d000;
+ /delete-node/ etm@619e000;
+ /delete-node/ etm@619f000;
+ /delete-node/ cti@6198000;
+ /delete-node/ cti@6199000;
+ /delete-node/ cti@619a000;
+ /delete-node/ cti@619b000;
+ /delete-node/ jtagmm@619c000;
+ /delete-node/ jtagmm@619d000;
+ /delete-node/ jtagmm@619e000;
+ /delete-node/ jtagmm@619f000;
+
+ qcom,spm@b1d2000 {
+ qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ };
+
+ qcom,lpm-levels {
+ qcom,pm-cluster@0 {
+ /delete-node/qcom,pm-cluster@1;
+ };
+ };
+
+ /delete-node/ syscon@0b11101c;
+ cpu_debug: syscon@0b01101c {
+ compatible = "syscon";
+ reg = <0x0b01101c 0x4>;
+ };
+
+ /delete-node/ qcom,msm-cpufreq;
+ msm_cpufreq: qcom,msm-cpufreq {
+ compatible = "qcom,msm-cpufreq";
+ clocks = <&apsscc APCS_MUX_CCI_CLK>,
+ <&apsscc APCS_MUX_C1_CLK>;
+ clock-names = "l2_clk", "cpu0_clk";
+
+ qcom,governor-per-policy;
+
+ qcom,cpufreq-table =
+ < 960000 >,
+ < 1305600 >,
+ < 1497600 >,
+ < 1708800 >,
+ < 1804800 >,
+ < 1958400 >,
+ < 2016000 >;
+ };
+
+ /delete-node/ qcom,cpu4-cpu-ddr-latfloor;
+
+ /delete-node/ qcom,cpu0-cpugrp;
+ cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ cpu0_computemon: qcom,cpu0-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 1305600 MHZ_TO_MBPS(384, 8) >,
+ < 1804800 MHZ_TO_MBPS(749, 8) >;
+ };
+ };
+
+ /delete-node/ qcom,cpu4-cpugrp;
+
+};
+
+&funnel_apss {
+ ports {
+ /delete-node/ port@1;
+ /delete-node/ port@2;
+ /delete-node/ port@3;
+ /delete-node/ port@4;
+ };
+};
+
+&thermal_zones {
+ hexa-cpu-max-step {
+ cooling-maps {
+ /delete-node/ cpu4_cdev;
+ /delete-node/ cpu5_cdev;
+ /delete-node/ cpu6_cdev;
+ /delete-node/ cpu7_cdev;
+ };
+ };
+
+ /delete-node/ cpuss0-step;
+
+ quiet-therm-step {
+ cooling-maps {
+ /delete-node/ skin_cpu4;
+ /delete-node/ skin_cpu5;
+ /delete-node/ skin_cpu6;
+ /delete-node/ skin_cpu7;
+ };
+ };
+};
+
+&gcc {
+ vdd_cx-supply = <&pm8953_s2_level>;
+};
+
+&debugcc {
+ compatible = "qcom,sdm429-debugcc";
+ qcom,cpu = <&cpu_debug>;
+};
+
+&soc {
+ /delete-node/ qcom,clock-cpu@b111050;
+ apsscc: qcom,clock-cpu@b111050 {
+ compatible = "qcom,cpu-clock-sdm429";
+ reg = <0xb011050 0x8>,
+ <0xb1d1050 0x8>,
+ <0xb016000 0x34>,
+ <0x00a412c 0x8>,
+ <0xb011200 0x100>;
+ reg-names = "apcs-c1-rcg-base",
+ "apcs-cci-rcg-base", "apcs_pll1", "efuse",
+ "spm_c1_base";
+ clocks = <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
+ <&gcc GPLL0_AO_OUT_MAIN>;
+ clock-names = "xo_ao", "gpll0_ao" ;
+ cpu-vdd-supply = <&apc_vreg_corner>;
+ vdd_dig_ao-supply = <&pm8953_s2_level_ao>;
+ vdd_hf_pll-supply = <&pm8953_l7_ao>;
+
+ qcom,speed0-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1305600000 1>,
+ < 1497600000 2>,
+ < 1708800000 3>,
+ < 1958400000 5>;
+
+ qcom,speed0-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+
+ qcom,speed1-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1305600000 1>,
+ < 1497600000 2>,
+ < 1708800000 3>,
+ < 1804800000 5>;
+
+ qcom,speed1-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+
+ qcom,speed4-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1305600000 1>,
+ < 1497600000 2>,
+ < 1708800000 3>,
+ < 1958400000 5>,
+ < 2016000000 6>;
+
+ qcom,speed4-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+
+ qcom,speed5-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1305600000 1>,
+ < 1497600000 2>,
+ < 1708800000 3>;
+
+ qcom,speed5-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+
+ #clock-cells = <1>;
+
+ qcom,cpu-isolation {
+ compatible = "qcom,cpu-isolate";
+ cpu0_isolate: cpu0-isolate {
+ qcom,cpu = <&CPU0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1_isolate: cpu1-isolate {
+ qcom,cpu = <&CPU1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2_isolate: cpu2-isolate {
+ qcom,cpu = <&CPU2>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3_isolate: cpu3-isolate {
+ qcom,cpu = <&CPU3>;
+ #cooling-cells = <2>;
+ };
+ };
+ };
+
+ /* Disable secure_mem node */
+ qcom,ion {
+ /delete-node/ qcom,ion-heap@8;
+ };
+ /* delete hypervisor node for GPU*/
+ /delete-node/ qcom,kgsl-hyp;
+};
+
+&secure_mem {
+ status = "disabled";
+};
+
+&qseecom_ta_mem {
+ size = <0 0x400000>;
+};
+
+&gcc_mdss {
+ compatible = "qcom,gcc-mdss-sdm439";
+ clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,
+ <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,
+ <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>,
+ <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>;
+ clock-names = "pclk0_src", "byte0_src", "pclk1_src",
+ "byte1_src";
+ #clock-cells = <1>;
+};
+
+/* GPU overrides */
+&msm_gpu {
+ /* Update GPU chip ID*/
+ qcom,chipid = <0x05000400>;
+
+ /* disable mem pools */
+ /delete-node/qcom,gpu-mempools;
+};
+
+/* Disable secure context for Graphics*/
+&kgsl_msm_iommu {
+ /delete-node/ gfx3d_secure;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-audio.dtsi
new file mode 100755
index 0000000..3c4bc7e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-audio.dtsi
@@ -0,0 +1,144 @@
+&soc {
+ int_codec: sound {
+ qcom,model = "sdm439-snd-card-mtp";
+ qcom,msm-hs-micbias-type = "internal";
+ qcom,msm-micbias2-ext-cap;
+
+ asoc-codec = <&stub_codec>, <&msm_digital_codec>,
+ <&pmic_analog_codec>;
+ asoc-codec-names = "msm-stub-codec.1", "msm-dig-codec",
+ "analog-codec";
+ msm-vdd-wsa-switch-supply = <&pm8953_l5>;
+ qcom,msm-vdd-wsa-switch-voltage = <1800000>;
+ qcom,msm-vdd-wsa-switch-current = <10000>;
+ };
+
+ clock_audio_native: audio_ext_clk_native {
+ status = "disabled";
+ compatible = "qcom,audio-ref-clk";
+ qcom,use-pinctrl = <1>;
+ qcom,codec-ext-clk-src = <2>;
+ #clock-cells = <1>;
+ qcom,codec-mclk-clk-freq = <11289600>;
+ qcom,audio-ref-clk-gpio = <&tlmm 66 0>;
+ qcom,lpass-mclk-id = "pri_mclk";
+ pinctrl-names = "sleep", "active";
+ pinctrl-0 = <&cdc_mclk2_sleep>;
+ pinctrl-1 = <&cdc_mclk2_active>;
+ };
+};
+
+
+&clock_audio {
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&tasha_mclk_default>;
+ pinctrl-1 = <&tasha_mclk_default>;
+ qcom,audio-ref-clk-gpio = <&pm8953_gpios 1 0>;
+};
+
+&wcd9335 {
+ cdc-vdd-buck-supply = <&dbu1>;
+ qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-buck-current = <650000>;
+
+ cdc-buck-sido-supply = <&dbu1>;
+ qcom,cdc-buck-sido-voltage = <1800000 1800000>;
+ qcom,cdc-buck-sido-current = <150000>;
+
+ cdc-vdd-tx-h-supply = <&dbu1>;
+ qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-tx-h-current = <25000>;
+
+ cdc-vdd-rx-h-supply = <&dbu1>;
+ qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-rx-h-current = <25000>;
+
+ cdc-vdd-px-supply = <&dbu1>;
+ qcom,cdc-vdd-px-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-px-current = <10000>;
+
+ cdc-vdd-mic-bias-supply = <&pm8953_l13>;
+ qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>;
+ qcom,cdc-vdd-mic-bias-current = <15000>;
+};
+
+&pm8953_gpios {
+ tasha_mclk {
+ tasha_mclk_default: tasha_mclk_default {
+ pins = "gpio1";
+ function = "func1";
+ qcom,drive-strength = <2>;
+ power-source = <0>;
+ bias-disable;
+ output-low;
+ };
+ };
+};
+
+&pm8953_1 {
+ pmic_analog_codec: anlg-cdc@f000 {
+ status = "okay";
+ compatible = "qcom,pmic-analog-codec";
+ reg = <0xf000 0x200>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-parent = <&spmi_bus>;
+ interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x1 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x2 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x3 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x4 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x5 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x6 IRQ_TYPE_NONE>,
+ <0x1 0xf0 0x7 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x0 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x1 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x2 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x3 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x4 IRQ_TYPE_NONE>,
+ <0x1 0xf1 0x5 IRQ_TYPE_NONE>;
+ interrupt-names = "spk_cnp_int",
+ "spk_clip_int",
+ "spk_ocp_int",
+ "ins_rem_det1",
+ "but_rel_det",
+ "but_press_det",
+ "ins_rem_det",
+ "mbhc_int",
+ "ear_ocp_int",
+ "hphr_ocp_int",
+ "hphl_ocp_det",
+ "ear_cnp_int",
+ "hphr_cnp_int",
+ "hphl_cnp_int";
+
+ cdc-vdda-cp-supply = <&pm8953_s4>;
+ qcom,cdc-vdda-cp-voltage = <1900000 2050000>;
+ qcom,cdc-vdda-cp-current = <500000>;
+
+ cdc-vdd-io-supply = <&pm8953_l5>;
+ qcom,cdc-vdd-io-voltage = <1800000 1800000>;
+ qcom,cdc-vdd-io-current = <5000>;
+
+ cdc-vdd-pa-supply = <&pm8953_s4>;
+ qcom,cdc-vdd-pa-voltage = <1900000 2050000>;
+ qcom,cdc-vdd-pa-current = <260000>;
+
+ cdc-vdd-mic-bias-supply = <&pm8953_l13>;
+ qcom,cdc-vdd-mic-bias-voltage = <3075000 3075000>;
+ qcom,cdc-vdd-mic-bias-current = <5000>;
+
+ qcom,cdc-mclk-clk-rate = <9600000>;
+
+ qcom,cdc-static-supplies = "cdc-vdd-io",
+ "cdc-vdd-pa",
+ "cdc-vdda-cp";
+
+ qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias";
+
+ msm_digital_codec: msm-dig-codec {
+ compatible = "qcom,msm-digital-codec";
+ reg = <0xc0f0000 0x0>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-cdp.dtsi
new file mode 100755
index 0000000..2702749
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-cdp.dtsi
@@ -0,0 +1,316 @@
+#include <dt-bindings/clock/qcom,gcc-sdm429w.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+
+&cci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ actuator0: qcom,actuator@0 {
+ cell-index = <0>;
+ reg = <0x0>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <0>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2850000>;
+ qcom,cam-vreg-max-voltage = <2850000>;
+ qcom,cam-vreg-op-mode = <80000>;
+ };
+
+ actuator1: qcom,actuator@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <1>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2850000>;
+ qcom,cam-vreg-max-voltage = <2850000>;
+ qcom,cam-vreg-op-mode = <80000>;
+ };
+
+ eeprom0: qcom,eeprom@0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ qcom,cci-master = <0>;
+ reg = <0x0>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ cam_vdig-supply = <&pm8953_l3>;
+ qcom,cam-vreg-name = "cam_vana",
+ "cam_vio", "cam_vdig", "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2800000 0 1200000 2850000>;
+ qcom,cam-vreg-max-voltage = <2800000 0 1200000 2850000>;
+ qcom,cam-vreg-op-mode = <80000 0 200000 100000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_default
+ &cam_sensor_rear_reset
+ &cam_sensor_rear_vana>;
+ pinctrl-1 = <&cam_sensor_mclk0_sleep
+ &cam_sensor_rear_reset_sleep
+ &cam_sensor_rear_vana_sleep>;
+ gpios = <&tlmm 26 0>,
+ <&tlmm 36 0>,
+ <&tlmm 35 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vana = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0",
+ "CAM_VANA";
+ status = "ok";
+ clocks = <&gcc MCLK0_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <19200000 0>;
+ };
+
+ eeprom1: qcom,eeprom@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ qcom,eeprom-name = "sunny_8865";
+ compatible = "qcom,eeprom";
+ qcom,slave-addr = <0x6c>;
+ qcom,cci-master = <0>;
+ qcom,num-blocks = <8>;
+
+ qcom,page0 = <1 0x0100 2 0x01 1 1>;
+ qcom,poll0 = <0 0x0 2 0x0 1 0>;
+ qcom,mem0 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page1 = <1 0x5002 2 0x00 1 0>;
+ qcom,poll1 = <0 0x0 2 0x0 1 0>;
+ qcom,mem1 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page2 = <1 0x3d84 2 0xc0 1 0>;
+ qcom,poll2 = <0 0x0 2 0x0 1 0>;
+ qcom,mem2 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page3 = <1 0x3d88 2 0x70 1 0>;
+ qcom,poll3 = <0 0x0 2 0x0 1 0>;
+ qcom,mem3 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page4 = <1 0x3d89 2 0x10 1 0>;
+ qcom,poll4 = <0 0x0 2 0x0 1 0>;
+ qcom,mem4 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page5 = <1 0x3d8a 2 0x70 1 0>;
+ qcom,poll5 = <0 0x0 2 0x0 1 0>;
+ qcom,mem5 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page6 = <1 0x3d8b 2 0xf4 1 0>;
+ qcom,poll6 = <0 0x0 2 0x0 1 0>;
+ qcom,mem6 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page7 = <1 0x3d81 2 0x01 1 10>;
+ qcom,poll7 = <0 0x0 2 0x0 1 1>;
+ qcom,mem7 = <1536 0x7010 2 0 1 0>;
+
+ cam_vdig-supply = <&pm8953_l23>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_vaf";
+ qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <105000 0 80000 100000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_default
+ &cam_sensor_front1_default>;
+ pinctrl-1 = <&cam_sensor_mclk2_sleep &cam_sensor_front1_sleep>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 40 0>,
+ <&tlmm 39 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-standby = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_STANDBY2";
+ qcom,cam-power-seq-type = "sensor_vreg", "sensor_vreg",
+ "sensor_vreg",
+ "sensor_gpio", "sensor_gpio" , "sensor_clk";
+ qcom,cam-power-seq-val = "cam_vdig", "cam_vana", "cam_vio",
+ "sensor_gpio_reset", "sensor_gpio_standby",
+ "sensor_cam_mclk";
+ qcom,cam-power-seq-cfg-val = <1 1 1 1 1 24000000>;
+ qcom,cam-power-seq-delay = <1 1 1 30 30 5>;
+ status = "ok";
+ clocks = <&gcc MCLK2_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <19200000 0>;
+ };
+
+ eeprom2: qcom,eeprom@2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ qcom,cci-master = <1>;
+ reg = <0x2>;
+ cam_vdig-supply = <&pm8953_l3>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_vaf";
+ qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <105000 0 80000 100000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_default
+ &cam_sensor_front1_default>;
+ pinctrl-1 = <&cam_sensor_mclk2_sleep
+ &cam_sensor_front1_sleep>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 40 0>,
+ <&tlmm 39 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-standby = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_STANDBY2";
+ status = "ok";
+ clocks = <&gcc MCLK2_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <19200000 0>;
+ };
+
+ qcom,camera@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera";
+ reg = <0x0>;
+ qcom,csiphy-sd-index = <0>;
+ qcom,csid-sd-index = <0>;
+ qcom,mount-angle = <270>;
+ qcom,led-flash-src = <&led_flash0>;
+ qcom,eeprom-src = <&eeprom0>;
+ qcom,actuator-src = <&actuator0>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ cam_vdig-supply = <&pm8953_l3>;
+ qcom,cam-vreg-name = "cam_vana",
+ "cam_vio", "cam_vdig", "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2800000 0 1200000 2850000>;
+ qcom,cam-vreg-max-voltage = <2800000 0 1200000 2850000>;
+ qcom,cam-vreg-op-mode = <80000 0 200000 100000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_default
+ &cam_sensor_rear_reset
+ &cam_sensor_rear_vana>;
+ pinctrl-1 = <&cam_sensor_mclk0_sleep
+ &cam_sensor_rear_reset_sleep
+ &cam_sensor_rear_vana_sleep>;
+ gpios = <&tlmm 26 0>,
+ <&tlmm 36 0>,
+ <&tlmm 35 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vana = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0",
+ "CAM_VANA";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc MCLK0_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera";
+ reg = <0x1>;
+ qcom,csiphy-sd-index = <1>;
+ qcom,csid-sd-index = <1>;
+ qcom,mount-angle = <90>;
+ cam_vdig-supply = <&pm8953_l3>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_vaf";
+ qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <200000 0 80000 100000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_default
+ &cam_sensor_front_default>;
+ pinctrl-1 = <&cam_sensor_mclk1_sleep
+ &cam_sensor_front_sleep>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 38 0>,
+ <&tlmm 50 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-standby = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1",
+ "CAM_STANDBY1";
+ qcom,sensor-position = <0x100>;
+ qcom,sensor-mode = <1>;
+ qcom,cci-master = <1>;
+ clocks = <&gcc MCLK1_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@2 {
+ cell-index = <2>;
+ compatible = "qcom,camera";
+ reg = <0x02>;
+ qcom,csiphy-sd-index = <1>;
+ qcom,csid-sd-index = <1>;
+ qcom,mount-angle = <90>;
+ qcom,eeprom-src = <&eeprom2>;
+ qcom,actuator-src = <&actuator1>;
+ cam_vdig-supply = <&pm8953_l3>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_vaf";
+ qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <105000 0 80000 100000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_default
+ &cam_sensor_front1_default>;
+ pinctrl-1 = <&cam_sensor_mclk2_sleep
+ &cam_sensor_front1_sleep>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 40 0>,
+ <&tlmm 39 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-standby = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_STANDBY2";
+ qcom,sensor-position = <1>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc MCLK2_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-mtp.dtsi
new file mode 100755
index 0000000..5835252
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-mtp.dtsi
@@ -0,0 +1,318 @@
+#include <dt-bindings/clock/qcom,gcc-sdm429w.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+
+&cci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ actuator0: qcom,actuator@0 {
+ cell-index = <0>;
+ reg = <0x0>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <0>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2850000>;
+ qcom,cam-vreg-max-voltage = <2850000>;
+ qcom,cam-vreg-op-mode = <80000>;
+ status = "ok";
+ };
+
+ actuator1: qcom,actuator@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <1>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2850000>;
+ qcom,cam-vreg-max-voltage = <2850000>;
+ qcom,cam-vreg-op-mode = <80000>;
+ status = "ok";
+ };
+
+ eeprom0: qcom,eeprom@0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ qcom,cci-master = <0>;
+ reg = <0x0>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ cam_vdig-supply = <&pm8953_l3>;
+ qcom,cam-vreg-name = "cam_vana",
+ "cam_vio", "cam_vdig", "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2800000 0 1200000 2850000>;
+ qcom,cam-vreg-max-voltage = <2800000 0 1200000 2850000>;
+ qcom,cam-vreg-op-mode = <80000 0 200000 100000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_default
+ &cam_sensor_rear_reset
+ &cam_sensor_rear_vana>;
+ pinctrl-1 = <&cam_sensor_mclk0_sleep
+ &cam_sensor_rear_reset_sleep
+ &cam_sensor_rear_vana_sleep>;
+ gpios = <&tlmm 26 0>,
+ <&tlmm 36 0>,
+ <&tlmm 35 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vana = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0",
+ "CAM_VANA";
+ status = "ok";
+ clocks = <&gcc MCLK0_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <19200000 0>;
+ };
+
+ eeprom1: qcom,eeprom@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ qcom,eeprom-name = "sunny_8865";
+ compatible = "qcom,eeprom";
+ qcom,slave-addr = <0x6c>;
+ qcom,cci-master = <0>;
+ qcom,num-blocks = <8>;
+
+ qcom,page0 = <1 0x0100 2 0x01 1 1>;
+ qcom,poll0 = <0 0x0 2 0x0 1 0>;
+ qcom,mem0 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page1 = <1 0x5002 2 0x00 1 0>;
+ qcom,poll1 = <0 0x0 2 0x0 1 0>;
+ qcom,mem1 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page2 = <1 0x3d84 2 0xc0 1 0>;
+ qcom,poll2 = <0 0x0 2 0x0 1 0>;
+ qcom,mem2 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page3 = <1 0x3d88 2 0x70 1 0>;
+ qcom,poll3 = <0 0x0 2 0x0 1 0>;
+ qcom,mem3 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page4 = <1 0x3d89 2 0x10 1 0>;
+ qcom,poll4 = <0 0x0 2 0x0 1 0>;
+ qcom,mem4 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page5 = <1 0x3d8a 2 0x70 1 0>;
+ qcom,poll5 = <0 0x0 2 0x0 1 0>;
+ qcom,mem5 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page6 = <1 0x3d8b 2 0xf4 1 0>;
+ qcom,poll6 = <0 0x0 2 0x0 1 0>;
+ qcom,mem6 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page7 = <1 0x3d81 2 0x01 1 10>;
+ qcom,poll7 = <0 0x0 2 0x0 1 1>;
+ qcom,mem7 = <1536 0x7010 2 0 1 0>;
+
+ cam_vdig-supply = <&pm8953_l23>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_vaf";
+ qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <105000 0 80000 100000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_default
+ &cam_sensor_front1_default>;
+ pinctrl-1 = <&cam_sensor_mclk2_sleep &cam_sensor_front1_sleep>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 40 0>,
+ <&tlmm 39 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-standby = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_STANDBY2";
+ qcom,cam-power-seq-type = "sensor_vreg", "sensor_vreg",
+ "sensor_vreg",
+ "sensor_gpio", "sensor_gpio" , "sensor_clk";
+ qcom,cam-power-seq-val = "cam_vdig", "cam_vana", "cam_vio",
+ "sensor_gpio_reset", "sensor_gpio_standby",
+ "sensor_cam_mclk";
+ qcom,cam-power-seq-cfg-val = <1 1 1 1 1 24000000>;
+ qcom,cam-power-seq-delay = <1 1 1 30 30 5>;
+ status = "ok";
+ clocks = <&gcc MCLK2_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <19200000 0>;
+ };
+
+ eeprom2: qcom,eeprom@2 {
+ cell-index = <2>;
+ compatible = "qcom,eeprom";
+ qcom,cci-master = <1>;
+ reg = <0x2>;
+ cam_vdig-supply = <&pm8953_l3>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_vaf";
+ qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <105000 0 80000 100000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_default
+ &cam_sensor_front1_default>;
+ pinctrl-1 = <&cam_sensor_mclk2_sleep
+ &cam_sensor_front1_sleep>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 40 0>,
+ <&tlmm 39 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-standby = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_STANDBY2";
+ status = "ok";
+ clocks = <&gcc MCLK2_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <19200000 0>;
+ };
+
+ qcom,camera@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera";
+ reg = <0x0>;
+ qcom,csiphy-sd-index = <0>;
+ qcom,csid-sd-index = <0>;
+ qcom,mount-angle = <270>;
+ qcom,led-flash-src = <&led_flash0>;
+ qcom,eeprom-src = <&eeprom0>;
+ qcom,actuator-src = <&actuator0>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ cam_vdig-supply = <&pm8953_l3>;
+ qcom,cam-vreg-name = "cam_vana",
+ "cam_vio", "cam_vdig", "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2800000 0 1200000 2850000>;
+ qcom,cam-vreg-max-voltage = <2800000 0 1200000 2850000>;
+ qcom,cam-vreg-op-mode = <80000 0 200000 100000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_default
+ &cam_sensor_rear_reset
+ &cam_sensor_rear_vana>;
+ pinctrl-1 = <&cam_sensor_mclk0_sleep
+ &cam_sensor_rear_reset_sleep
+ &cam_sensor_rear_vana_sleep>;
+ gpios = <&tlmm 26 0>,
+ <&tlmm 36 0>,
+ <&tlmm 35 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vana = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0",
+ "CAM_VANA";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc MCLK0_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera";
+ reg = <0x1>;
+ qcom,csiphy-sd-index = <1>;
+ qcom,csid-sd-index = <1>;
+ qcom,mount-angle = <90>;
+ cam_vdig-supply = <&pm8953_l3>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_vaf";
+ qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <200000 0 80000 100000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_default
+ &cam_sensor_front_default>;
+ pinctrl-1 = <&cam_sensor_mclk1_sleep
+ &cam_sensor_front_sleep>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 38 0>,
+ <&tlmm 50 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-standby = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1",
+ "CAM_STANDBY1";
+ qcom,sensor-position = <0x100>;
+ qcom,sensor-mode = <1>;
+ qcom,cci-master = <1>;
+ clocks = <&gcc MCLK1_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@2 {
+ cell-index = <2>;
+ compatible = "qcom,camera";
+ reg = <0x02>;
+ qcom,csiphy-sd-index = <1>;
+ qcom,csid-sd-index = <1>;
+ qcom,mount-angle = <90>;
+ qcom,eeprom-src = <&eeprom2>;
+ qcom,actuator-src = <&actuator1>;
+ cam_vdig-supply = <&pm8953_l3>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_vaf";
+ qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <105000 0 80000 100000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_default
+ &cam_sensor_front1_default>;
+ pinctrl-1 = <&cam_sensor_mclk2_sleep
+ &cam_sensor_front1_sleep>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 40 0>,
+ <&tlmm 39 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-standby = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_STANDBY2";
+ qcom,sensor-position = <1>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ status = "ok";
+ clocks = <&gcc MCLK2_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-qrd.dtsi
new file mode 100755
index 0000000..25882a4b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-camera-sensor-qrd.dtsi
@@ -0,0 +1,282 @@
+#include <dt-bindings/clock/qcom,gcc-sdm429w.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+
+&cci {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ actuator0: qcom,actuator@0 {
+ cell-index = <0>;
+ reg = <0x0>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <0>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2850000>;
+ qcom,cam-vreg-max-voltage = <2850000>;
+ qcom,cam-vreg-op-mode = <80000>;
+ status = "ok";
+ };
+
+ actuator1: qcom,actuator@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <0>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2850000>;
+ qcom,cam-vreg-max-voltage = <2850000>;
+ qcom,cam-vreg-op-mode = <80000>;
+ status = "ok";
+ };
+
+ eeprom0: qcom,eeprom@0 {
+ cell-index = <0>;
+ compatible = "qcom,eeprom";
+ qcom,cci-master = <0>;
+ reg = <0x0>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ cam_vdig-supply = <&pm8953_l3>;
+ qcom,cam-vreg-name = "cam_vana", "cam_vio",
+ "cam_vdig", "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2800000 0 1200000 2850000>;
+ qcom,cam-vreg-max-voltage = <2800000 0 1200000 2850000>;
+ qcom,cam-vreg-op-mode = <80000 0 200000 100000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_default
+ &cam_sensor_rear_reset
+ &cam_sensor_rear_vana>;
+ pinctrl-1 = <&cam_sensor_mclk0_sleep
+ &cam_sensor_rear_reset_sleep
+ &cam_sensor_rear_vana_sleep>;
+ gpios = <&tlmm 26 0>,
+ <&tlmm 36 0>,
+ <&tlmm 35 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vana = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0",
+ "CAM_VANA";
+ status = "ok";
+ clocks = <&gcc MCLK0_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <19200000 0>;
+ };
+
+ eeprom1: qcom,eeprom@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ qcom,eeprom-name = "sunny_8865";
+ compatible = "qcom,eeprom";
+ qcom,slave-addr = <0x6c>;
+ qcom,cci-master = <0>;
+ qcom,num-blocks = <8>;
+
+ qcom,page0 = <1 0x0100 2 0x01 1 1>;
+ qcom,poll0 = <0 0x0 2 0x0 1 0>;
+ qcom,mem0 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page1 = <1 0x5002 2 0x00 1 0>;
+ qcom,poll1 = <0 0x0 2 0x0 1 0>;
+ qcom,mem1 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page2 = <1 0x3d84 2 0xc0 1 0>;
+ qcom,poll2 = <0 0x0 2 0x0 1 0>;
+ qcom,mem2 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page3 = <1 0x3d88 2 0x70 1 0>;
+ qcom,poll3 = <0 0x0 2 0x0 1 0>;
+ qcom,mem3 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page4 = <1 0x3d89 2 0x10 1 0>;
+ qcom,poll4 = <0 0x0 2 0x0 1 0>;
+ qcom,mem4 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page5 = <1 0x3d8a 2 0x70 1 0>;
+ qcom,poll5 = <0 0x0 2 0x0 1 0>;
+ qcom,mem5 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page6 = <1 0x3d8b 2 0xf4 1 0>;
+ qcom,poll6 = <0 0x0 2 0x0 1 0>;
+ qcom,mem6 = <0 0x0 2 0x0 1 0>;
+
+ qcom,page7 = <1 0x3d81 2 0x01 1 10>;
+ qcom,poll7 = <0 0x0 2 0x0 1 1>;
+ qcom,mem7 = <1536 0x7010 2 0 1 0>;
+
+ cam_vdig-supply = <&pm8953_l23>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio",
+ "cam_vana", "cam_vaf";
+ qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <105000 0 80000 100000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_default
+ &cam_sensor_front1_default>;
+ pinctrl-1 = <&cam_sensor_mclk2_sleep
+ &cam_sensor_front1_sleep>;
+ gpios = <&tlmm 28 0>,
+ <&tlmm 40 0>,
+ <&tlmm 39 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-standby = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_STANDBY2";
+ qcom,cam-power-seq-type = "sensor_vreg", "sensor_vreg",
+ "sensor_vreg",
+ "sensor_gpio", "sensor_gpio" , "sensor_clk";
+ qcom,cam-power-seq-val = "cam_vdig", "cam_vana", "cam_vio",
+ "sensor_gpio_reset", "sensor_gpio_standby",
+ "sensor_cam_mclk";
+ qcom,cam-power-seq-cfg-val = <1 1 1 1 1 24000000>;
+ qcom,cam-power-seq-delay = <1 1 1 30 30 5>;
+ status = "ok";
+ clocks = <&gcc MCLK2_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <19200000 0>;
+ };
+
+ qcom,camera@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera";
+ reg = <0x0>;
+ qcom,csiphy-sd-index = <0>;
+ qcom,csid-sd-index = <0>;
+ qcom,mount-angle = <90>;
+ qcom,led-flash-src = <&led_flash0>;
+ qcom,eeprom-src = <&eeprom0>;
+ qcom,actuator-src = <&actuator0>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ cam_vdig-supply = <&pm8953_l3>;
+ qcom,cam-vreg-name = "cam_vana", "cam_vio",
+ "cam_vdig", "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2800000 0 1200000 2850000>;
+ qcom,cam-vreg-max-voltage = <2800000 0 1200000 2850000>;
+ qcom,cam-vreg-op-mode = <80000 0 200000 100000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_default
+ &cam_sensor_rear_reset
+ &cam_sensor_rear_vana>;
+ pinctrl-1 = <&cam_sensor_mclk0_sleep
+ &cam_sensor_rear_reset_sleep
+ &cam_sensor_rear_vana_sleep>;
+ gpios = <&tlmm 26 0>,
+ <&tlmm 36 0>,
+ <&tlmm 35 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vana = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0",
+ "CAM_VANA";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc MCLK0_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera";
+ reg = <0x1>;
+ qcom,csiphy-sd-index = <1>;
+ qcom,csid-sd-index = <1>;
+ qcom,mount-angle = <270>;
+ cam_vdig-supply = <&pm8953_l3>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_vaf";
+ qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <200000 0 80000 100000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_default
+ &cam_sensor_front_default>;
+ pinctrl-1 = <&cam_sensor_mclk1_sleep
+ &cam_sensor_front_sleep>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 38 0>,
+ <&tlmm 50 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-standby = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1",
+ "CAM_STANDBY1";
+ qcom,sensor-position = <0x100>;
+ qcom,sensor-mode = <1>;
+ qcom,cci-master = <1>;
+ clocks = <&gcc MCLK1_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@2 {
+ cell-index = <2>;
+ compatible = "qcom,camera";
+ reg = <0x02>;
+ qcom,csiphy-sd-index = <1>;
+ qcom,csid-sd-index = <1>;
+ qcom,mount-angle = <270>;
+ qcom,eeprom-src = <&eeprom1>;
+ qcom,actuator-src = <&actuator1>;
+ cam_vdig-supply = <&pm8953_l3>;
+ cam_vana-supply = <&pm8953_l22>;
+ cam_vio-supply = <&pm8953_l6>;
+ cam_vaf-supply = <&pm8953_l17>;
+ qcom,cam-vreg-name = "cam_vdig", "cam_vio", "cam_vana",
+ "cam_vaf";
+ qcom,cam-vreg-min-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-max-voltage = <1200000 0 2800000 2850000>;
+ qcom,cam-vreg-op-mode = <105000 0 80000 100000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_default
+ &cam_sensor_front1_default>;
+ pinctrl-1 = <&cam_sensor_mclk2_sleep
+ &cam_sensor_front1_sleep>;
+ gpios = <&tlmm 27 0>,
+ <&tlmm 38 0>,
+ <&tlmm 39 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-standby = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_STANDBY2";
+ qcom,sensor-position = <1>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <0>;
+ status = "ok";
+ clocks = <&gcc MCLK2_CLK_SRC>,
+ <&gcc GCC_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-cdp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm439-cdp-overlay.dts
new file mode 100755
index 0000000..fcd65e6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-cdp-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+#include "sdm439-cdp.dtsi"
+
+/ {
+ model = "CDP";
+ qcom,board-id = <1 2>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm439-cdp.dts
new file mode 100755
index 0000000..899cac7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-cdp.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sdm439.dtsi"
+#include "sdm439-cdp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM439 CDP";
+ compatible = "qcom,sdm439-cdp", "qcom,sdm439", "qcom,cdp";
+ qcom,board-id = <1 2>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-cdp.dtsi
new file mode 100755
index 0000000..6662178
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-cdp.dtsi
@@ -0,0 +1,586 @@
+#include "sdm439-camera-sensor-cdp.dtsi"
+
+&blsp1_uart2 {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart_console_active>;
+};
+
+&pm8953_gpios {
+ nfc_clk {
+ nfc_clk_default: nfc_clk_default {
+ pins = "gpio2";
+ function = "normal";
+ input-enable;
+ power-source = <1>;
+ };
+ };
+};
+
+&i2c_5 { /* BLSP2 QUP1 (NFC) */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "ok";
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 17 0x00>;
+ qcom,nq-ven = <&tlmm 16 0x00>;
+ qcom,nq-firm = <&tlmm 130 0x00>;
+ qcom,nq-clkreq = <&pm8953_gpios 2 0x00>;
+ qcom,nq-esepwr = <&tlmm 93 0x00>;
+ interrupt-parent = <&tlmm>;
+ qcom,clk-src = "BBCLK2";
+ interrupts = <17 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_disable_active
+ &nfc_clk_default>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_disable_suspend>;
+ clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>;
+ clock-names = "ref_clk";
+ };
+};
+
+&sdhc_1 {
+ /* device core power supply */
+ vdd-supply = <&pm8953_l8>;
+ qcom,vdd-voltage-level = <2900000 2900000>;
+ qcom,vdd-current-level = <200 570000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm8953_l5>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <200 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000
+ 384000000>;
+ qcom,nonremovable;
+ qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ /* device core power supply */
+ vdd-supply = <&pm8953_l11>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <15000 800000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm8953_l12>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
+
+ cd-gpios = <&tlmm 67 0x1>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
+ 200000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
+
+ status = "ok";
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_key_active>;
+
+ camera_focus {
+ label = "camera_focus";
+ gpios = <&tlmm 128 0x1>;
+ linux,input-type = <1>;
+ linux,code = <0x210>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+
+ camera_snapshot {
+ label = "camera_snapshot";
+ gpios = <&tlmm 127 0x1>;
+ linux,input-type = <1>;
+ linux,code = <0x2fe>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&tlmm 91 0x1>;
+ linux,input-type = <1>;
+ linux,code = <115>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+ };
+};
+
+&pm8953_gpios {
+ bklt_en {
+ bklt_en_default: bklt_en_default {
+ pins = "gpio4";
+ function = "normal";
+ power-source = <0>;
+ output-high;
+ };
+ };
+};
+
+&cdc_pdm_lines_2_act {
+ mux {
+ pins = "gpio70", "gpio71", "gpio72";
+ function = "cdc_pdm0";
+ };
+
+ config {
+ pins = "gpio70", "gpio71", "gpio72";
+ drive-strength = <16>;
+ };
+};
+
+&cdc_pdm_lines_act {
+ mux {
+ pins = "gpio69", "gpio73", "gpio74";
+ function = "cdc_pdm0";
+ };
+
+ config {
+ pins = "gpio69", "gpio73", "gpio74";
+ drive-strength = <16>;
+ };
+};
+
+&pm8953_pwm {
+ status = "ok";
+};
+
+#include "msm8937-mdss-panels.dtsi"
+
+&mdss_mdp {
+ qcom,mdss-pref-prim-intf = "dsi";
+};
+
+&mdss_dsi {
+ hw-config = "single_dsi";
+};
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_hx8399c_truly_vid>;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active &bklt_en_default>;
+ pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+
+ qcom,platform-bklight-en-gpio = <&pm8953_gpios 4 0>;
+ qcom,platform-te-gpio = <&tlmm 24 0>;
+ qcom,platform-reset-gpio = <&tlmm 60 0>;
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+};
+
+&mdss_dsi1 {
+ status = "disabled";
+};
+
+&dsi_hx8399c_truly_vid {
+ /delete-property/ qcom,mdss-dsi-panel-timings;
+ qcom,mdss-dsi-panel-timings-phy-12nm = [18 0a 10 06 03 08 06 0e];
+ qcom,mdss-dsi-t-clk-post = <0x02>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-status-read-length = <4>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ qcom,mdss-dsi-min-refresh-rate = <48>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update =
+ "dfps_immediate_porch_mode_vfp";
+};
+
+
+&dsi_hx8399c_hd_vid {
+ /delete-property/ qcom,mdss-dsi-panel-timings;
+ qcom,mdss-dsi-panel-timings-phy-12nm = [09 06 0a 02 00 05 02 08];
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-status-read-length = <4>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ qcom,mdss-dsi-min-refresh-rate = <48>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update =
+ "dfps_immediate_porch_mode_vfp";
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <2>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command =
+ [15 01 00 00 10 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 03 55
+ 15 01 00 00 00 00 02 05 50
+ 15 01 00 00 00 00 02 06 a8
+ 15 01 00 00 00 00 02 07 ad
+ 15 01 00 00 00 00 02 08 0c
+ 15 01 00 00 00 00 02 0b aa
+ 15 01 00 00 00 00 02 0c aa
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f b3
+ 15 01 00 00 00 00 02 11 28
+ 15 01 00 00 00 00 02 12 10
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 4a
+ 15 01 00 00 00 00 02 15 12
+ 15 01 00 00 00 00 02 16 12
+ 15 01 00 00 00 00 02 30 01
+ 15 01 00 00 00 00 02 72 11
+ 15 01 00 00 00 00 02 58 82
+ 15 01 00 00 00 00 02 59 00
+ 15 01 00 00 00 00 02 5a 02
+ 15 01 00 00 00 00 02 5b 00
+ 15 01 00 00 00 00 02 5c 82
+ 15 01 00 00 00 00 02 5d 80
+ 15 01 00 00 00 00 02 5e 02
+ 15 01 00 00 00 00 02 5f 00
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 89
+ 15 01 00 00 00 00 02 04 8a
+ 15 01 00 00 00 00 02 05 0f
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 1c
+ 15 01 00 00 00 00 02 09 00
+ 15 01 00 00 00 00 02 0a 00
+ 15 01 00 00 00 00 02 0b 00
+ 15 01 00 00 00 00 02 0c 00
+ 15 01 00 00 00 00 02 0d 13
+ 15 01 00 00 00 00 02 0e 15
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 01
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 89
+ 15 01 00 00 00 00 02 14 8a
+ 15 01 00 00 00 00 02 15 0f
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 1c
+ 15 01 00 00 00 00 02 19 00
+ 15 01 00 00 00 00 02 1a 00
+ 15 01 00 00 00 00 02 1b 00
+ 15 01 00 00 00 00 02 1c 00
+ 15 01 00 00 00 00 02 1d 13
+ 15 01 00 00 00 00 02 1e 15
+ 15 01 00 00 00 00 02 1f 17
+ 15 01 00 00 00 00 02 20 00
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 55 25
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 93 06
+ 15 01 00 00 00 00 02 94 06
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b 0f
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ 15 01 00 00 00 00 02 b6 21
+ 15 01 00 00 00 00 02 b7 22
+ 15 01 00 00 00 00 02 b8 07
+ 15 01 00 00 00 00 02 b9 07
+ 15 01 00 00 00 00 02 ba 22
+ 15 01 00 00 00 00 02 bd 20
+ 15 01 00 00 00 00 02 be 07
+ 15 01 00 00 00 00 02 bf 07
+ 15 01 00 00 00 00 02 c1 6d
+ 15 01 00 00 00 00 02 c4 24
+ 15 01 00 00 00 00 02 e3 00
+ 15 01 00 00 00 00 02 ec 00
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 14
+ 00 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 03 08 06 0e];
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>;
+ qcom,ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ /delete-node/ qcom,mdss-dsi-display-timings;
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-v-back-porch = <2>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command =
+ [15 01 00 00 10 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 03 55
+ 15 01 00 00 00 00 02 05 50
+ 15 01 00 00 00 00 02 06 a8
+ 15 01 00 00 00 00 02 07 ad
+ 15 01 00 00 00 00 02 08 0c
+ 15 01 00 00 00 00 02 0b aa
+ 15 01 00 00 00 00 02 0c aa
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f b3
+ 15 01 00 00 00 00 02 11 28
+ 15 01 00 00 00 00 02 12 10
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 4a
+ 15 01 00 00 00 00 02 15 12
+ 15 01 00 00 00 00 02 16 12
+ 15 01 00 00 00 00 02 30 01
+ 15 01 00 00 00 00 02 72 11
+ 15 01 00 00 00 00 02 58 82
+ 15 01 00 00 00 00 02 59 00
+ 15 01 00 00 00 00 02 5a 02
+ 15 01 00 00 00 00 02 5b 00
+ 15 01 00 00 00 00 02 5c 82
+ 15 01 00 00 00 00 02 5d 80
+ 15 01 00 00 00 00 02 5e 02
+ 15 01 00 00 00 00 02 5f 00
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 89
+ 15 01 00 00 00 00 02 04 8a
+ 15 01 00 00 00 00 02 05 0f
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 1c
+ 15 01 00 00 00 00 02 09 00
+ 15 01 00 00 00 00 02 0a 00
+ 15 01 00 00 00 00 02 0b 00
+ 15 01 00 00 00 00 02 0c 00
+ 15 01 00 00 00 00 02 0d 13
+ 15 01 00 00 00 00 02 0e 15
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 01
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 89
+ 15 01 00 00 00 00 02 14 8a
+ 15 01 00 00 00 00 02 15 0f
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 1c
+ 15 01 00 00 00 00 02 19 00
+ 15 01 00 00 00 00 02 1a 00
+ 15 01 00 00 00 00 02 1b 00
+ 15 01 00 00 00 00 02 1c 00
+ 15 01 00 00 00 00 02 1d 13
+ 15 01 00 00 00 00 02 1e 15
+ 15 01 00 00 00 00 02 1f 17
+ 15 01 00 00 00 00 02 20 00
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 55 25
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 93 06
+ 15 01 00 00 00 00 02 94 06
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b 0f
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ 15 01 00 00 00 00 02 b6 21
+ 15 01 00 00 00 00 02 b7 22
+ 15 01 00 00 00 00 02 b8 07
+ 15 01 00 00 00 00 02 b9 07
+ 15 01 00 00 00 00 02 ba 22
+ 15 01 00 00 00 00 02 bd 20
+ 15 01 00 00 00 00 02 be 07
+ 15 01 00 00 00 00 02 bf 07
+ 15 01 00 00 00 00 02 c1 6d
+ 15 01 00 00 00 00 02 c4 24
+ 15 01 00 00 00 00 02 e3 00
+ 15 01 00 00 00 00 02 ec 00
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bb 03
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00
+ 14 00 02 28 00 05 01 00 00 78 00
+ 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 03 08 06 0e];
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>;
+ /delete-node/ qcom,mdss-dsi-display-timings;
+};
+
+&dsi_truly_1080_vid {
+ /delete-property/ qcom,mdss-dsi-panel-timings;
+ qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 02 08 06 0e];
+ qcom,mdss-dsi-t-clk-post = <0x02>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_truly_1080_cmd {
+ /delete-property/ qcom,mdss-dsi-panel-timings;
+ qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 02 08 06 0e];
+ qcom,mdss-dsi-t-clk-post = <0x02>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-ext-audio-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-ext-audio-mtp.dtsi
new file mode 100755
index 0000000..ff2dc25
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-ext-audio-mtp.dtsi
@@ -0,0 +1,76 @@
+&int_codec {
+ status = "disabled";
+};
+
+&pmic_analog_codec {
+ status = "disabled";
+};
+
+&wsa881x_i2c_f {
+ status = "disabled";
+};
+
+&wsa881x_i2c_45 {
+ status = "disabled";
+};
+
+&wsa881x_analog_clk {
+ status = "disabled";
+};
+
+&cdc_pri_mi2s_gpios {
+ status = "disabled";
+};
+
+&wsa881x_analog_vi_gpio {
+ status = "disabled";
+};
+
+&wsa881x_analog_clk_gpio {
+ status = "disabled";
+};
+
+&wsa881x_analog_reset_gpio {
+ status = "disabled";
+};
+
+&slim_msm {
+ status = "okay";
+};
+
+&dai_slim {
+ status = "okay";
+};
+
+&wcd9xxx_intc {
+ status = "okay";
+};
+
+&clock_audio {
+ status = "okay";
+};
+
+&clock_audio_native {
+ status = "okay";
+};
+
+&wcd9335 {
+ status = "okay";
+};
+
+&cdc_us_euro_sw {
+ status = "okay";
+};
+
+&cdc_quin_mi2s_gpios {
+ status = "okay";
+};
+
+&wcd_rst_gpio {
+ status = "okay";
+};
+
+&ext_codec {
+ status = "okay";
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-external-codec-mtp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm439-external-codec-mtp-overlay.dts
new file mode 100755
index 0000000..58abc6e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-external-codec-mtp-overlay.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "sdm439-mtp.dtsi"
+#include "sdm439-external-codec.dtsi"
+
+/ {
+ model = "MTP";
+ qcom,board-id = <8 3>;
+ qcom,msm-id = <353 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-external-codec-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm439-external-codec-mtp.dts
new file mode 100755
index 0000000..056d78f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-external-codec-mtp.dts
@@ -0,0 +1,12 @@
+/dts-v1/;
+
+#include "sdm439.dtsi"
+#include "sdm439-mtp.dtsi"
+#include "sdm439-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM439 Audio Codec MTP";
+ compatible = "qcom,sdm439-mtp", "qcom,sdm439", "qcom,mtp";
+ qcom,board-id = <8 3>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-external-codec.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-external-codec.dtsi
new file mode 100755
index 0000000..24e2069
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-external-codec.dtsi
@@ -0,0 +1 @@
+#include "sdm439-ext-audio-mtp.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-mtp-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm439-mtp-overlay.dts
new file mode 100755
index 0000000..73f9f6e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-mtp-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+#include "sdm439-mtp.dtsi"
+
+/ {
+ model = "MTP";
+ qcom,board-id = <8 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm439-mtp.dts
new file mode 100755
index 0000000..da296b0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-mtp.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sdm439.dtsi"
+#include "sdm439-mtp.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM439 MTP";
+ compatible = "qcom,sdm439-mtp", "qcom,sdm439", "qcom,mtp";
+ qcom,board-id = <8 1>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-mtp.dtsi
new file mode 100755
index 0000000..1c1ac40
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-mtp.dtsi
@@ -0,0 +1,642 @@
+#include "sdm439-camera-sensor-mtp.dtsi"
+
+&blsp1_uart2 {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart_console_active>;
+};
+
+&pm8953_gpios {
+ nfc_clk {
+ nfc_clk_default: nfc_clk_default {
+ pins = "gpio2";
+ function = "normal";
+ input-enable;
+ power-source = <1>;
+ };
+ };
+};
+
+&i2c_5 { /* BLSP2 QUP1 (NFC) */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "ok";
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 17 0x00>;
+ qcom,nq-ven = <&tlmm 16 0x00>;
+ qcom,nq-firm = <&tlmm 130 0x00>;
+ qcom,nq-clkreq = <&pm8953_gpios 2 0x00>;
+ qcom,nq-esepwr = <&tlmm 93 0x00>;
+ interrupt-parent = <&tlmm>;
+ qcom,clk-src = "BBCLK2";
+ interrupts = <17 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_disable_active
+ &nfc_clk_default>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_disable_suspend>;
+ clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>;
+ clock-names = "ref_clk";
+ };
+};
+
+&sdhc_1 {
+ /* device core power supply */
+ vdd-supply = <&pm8953_l8>;
+ qcom,vdd-voltage-level = <2900000 2900000>;
+ qcom,vdd-current-level = <200 570000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm8953_l5>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <200 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000
+ 384000000>;
+ qcom,nonremovable;
+ qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ /* device core power supply */
+ vdd-supply = <&pm8953_l11>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <15000 800000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm8953_l12>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
+
+ cd-gpios = <&tlmm 67 0x1>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
+ 200000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
+
+ status = "ok";
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_key_active>;
+
+ camera_focus {
+ label = "camera_focus";
+ gpios = <&tlmm 128 0x1>;
+ linux,input-type = <1>;
+ linux,code = <0x210>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+
+ camera_snapshot {
+ label = "camera_snapshot";
+ gpios = <&tlmm 127 0x1>;
+ linux,input-type = <1>;
+ linux,code = <0x2fe>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&tlmm 91 0x1>;
+ linux,input-type = <1>;
+ linux,code = <115>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+ };
+};
+
+#include "msm8937-mdss-panels.dtsi"
+
+&pm8953_gpios {
+ bklt_en {
+ bklt_en_default: bklt_en_default {
+ pins = "gpio4";
+ function = "normal";
+ power-source = <0>;
+ output-high;
+ };
+ };
+};
+
+&pm8953_pwm {
+ status = "ok";
+};
+
+&mdss_mdp {
+ qcom,mdss-pref-prim-intf = "dsi";
+};
+
+&mdss_dsi {
+ hw-config = "single_dsi";
+};
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_hx8399c_truly_vid>;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active &bklt_en_default>;
+ pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+
+ qcom,platform-bklight-en-gpio = <&pm8953_gpios 4 0>;
+ qcom,platform-te-gpio = <&tlmm 24 0>;
+ qcom,platform-reset-gpio = <&tlmm 60 0>;
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+};
+
+&mdss_dsi1 {
+ status = "disabled";
+};
+
+&dsi_hx8399c_truly_vid {
+ /delete-property/ qcom,mdss-dsi-panel-timings;
+ qcom,mdss-dsi-panel-timings-phy-12nm = [18 0a 10 06 03 08 06 0e];
+ qcom,mdss-dsi-t-clk-post = <0x02>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-status-read-length = <4>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ qcom,mdss-dsi-min-refresh-rate = <48>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update =
+ "dfps_immediate_porch_mode_vfp";
+};
+
+&dsi_hx8399c_hd_vid {
+ /delete-property/ qcom,mdss-dsi-panel-timings;
+ qcom,mdss-dsi-panel-timings-phy-12nm = [09 06 0a 02 00 05 02 08];
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-status-read-length = <4>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ qcom,mdss-dsi-min-refresh-rate = <48>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update =
+ "dfps_immediate_porch_mode_vfp";
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-v-back-porch = <2>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command =
+ [15 01 00 00 10 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 03 55
+ 15 01 00 00 00 00 02 05 50
+ 15 01 00 00 00 00 02 06 a8
+ 15 01 00 00 00 00 02 07 ad
+ 15 01 00 00 00 00 02 08 0c
+ 15 01 00 00 00 00 02 0b aa
+ 15 01 00 00 00 00 02 0c aa
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f b3
+ 15 01 00 00 00 00 02 11 28
+ 15 01 00 00 00 00 02 12 10
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 4a
+ 15 01 00 00 00 00 02 15 12
+ 15 01 00 00 00 00 02 16 12
+ 15 01 00 00 00 00 02 30 01
+ 15 01 00 00 00 00 02 72 11
+ 15 01 00 00 00 00 02 58 82
+ 15 01 00 00 00 00 02 59 00
+ 15 01 00 00 00 00 02 5a 02
+ 15 01 00 00 00 00 02 5b 00
+ 15 01 00 00 00 00 02 5c 82
+ 15 01 00 00 00 00 02 5d 80
+ 15 01 00 00 00 00 02 5e 02
+ 15 01 00 00 00 00 02 5f 00
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 89
+ 15 01 00 00 00 00 02 04 8a
+ 15 01 00 00 00 00 02 05 0f
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 1c
+ 15 01 00 00 00 00 02 09 00
+ 15 01 00 00 00 00 02 0a 00
+ 15 01 00 00 00 00 02 0b 00
+ 15 01 00 00 00 00 02 0c 00
+ 15 01 00 00 00 00 02 0d 13
+ 15 01 00 00 00 00 02 0e 15
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 01
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 89
+ 15 01 00 00 00 00 02 14 8a
+ 15 01 00 00 00 00 02 15 0f
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 1c
+ 15 01 00 00 00 00 02 19 00
+ 15 01 00 00 00 00 02 1a 00
+ 15 01 00 00 00 00 02 1b 00
+ 15 01 00 00 00 00 02 1c 00
+ 15 01 00 00 00 00 02 1d 13
+ 15 01 00 00 00 00 02 1e 15
+ 15 01 00 00 00 00 02 1f 17
+ 15 01 00 00 00 00 02 20 00
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 55 25
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 93 06
+ 15 01 00 00 00 00 02 94 06
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b 0f
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ 15 01 00 00 00 00 02 b6 21
+ 15 01 00 00 00 00 02 b7 22
+ 15 01 00 00 00 00 02 b8 07
+ 15 01 00 00 00 00 02 b9 07
+ 15 01 00 00 00 00 02 ba 22
+ 15 01 00 00 00 00 02 bd 20
+ 15 01 00 00 00 00 02 be 07
+ 15 01 00 00 00 00 02 bf 07
+ 15 01 00 00 00 00 02 c1 6d
+ 15 01 00 00 00 00 02 c4 24
+ 15 01 00 00 00 00 02 e3 00
+ 15 01 00 00 00 00 02 ec 00
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bb 10
+ 15 01 00 00 00 00 02 35 00
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00 14
+ 00 02 28 00 05 01 00 00 78 00 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 03 08 06 0e];
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>;
+ qcom,ulps-enabled;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ /delete-node/ qcom,mdss-dsi-display-timings;
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,mdss-dsi-panel-width = <1080>;
+ qcom,mdss-dsi-panel-height = <1920>;
+ qcom,mdss-dsi-h-front-porch = <120>;
+ qcom,mdss-dsi-h-back-porch = <60>;
+ qcom,mdss-dsi-h-pulse-width = <12>;
+ qcom,mdss-dsi-h-sync-skew = <0>;
+ qcom,mdss-dsi-h-sync-pulse = <0>;
+ qcom,mdss-dsi-v-back-porch = <2>;
+ qcom,mdss-dsi-v-front-porch = <12>;
+ qcom,mdss-dsi-v-pulse-width = <2>;
+ qcom,mdss-dsi-h-left-border = <0>;
+ qcom,mdss-dsi-h-right-border = <0>;
+ qcom,mdss-dsi-v-top-border = <0>;
+ qcom,mdss-dsi-v-bottom-border = <0>;
+ qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-on-command =
+ [15 01 00 00 10 00 02 ff 20
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 55
+ 15 01 00 00 00 00 02 02 45
+ 15 01 00 00 00 00 02 03 55
+ 15 01 00 00 00 00 02 05 50
+ 15 01 00 00 00 00 02 06 a8
+ 15 01 00 00 00 00 02 07 ad
+ 15 01 00 00 00 00 02 08 0c
+ 15 01 00 00 00 00 02 0b aa
+ 15 01 00 00 00 00 02 0c aa
+ 15 01 00 00 00 00 02 0e b0
+ 15 01 00 00 00 00 02 0f b3
+ 15 01 00 00 00 00 02 11 28
+ 15 01 00 00 00 00 02 12 10
+ 15 01 00 00 00 00 02 13 01
+ 15 01 00 00 00 00 02 14 4a
+ 15 01 00 00 00 00 02 15 12
+ 15 01 00 00 00 00 02 16 12
+ 15 01 00 00 00 00 02 30 01
+ 15 01 00 00 00 00 02 72 11
+ 15 01 00 00 00 00 02 58 82
+ 15 01 00 00 00 00 02 59 00
+ 15 01 00 00 00 00 02 5a 02
+ 15 01 00 00 00 00 02 5b 00
+ 15 01 00 00 00 00 02 5c 82
+ 15 01 00 00 00 00 02 5d 80
+ 15 01 00 00 00 00 02 5e 02
+ 15 01 00 00 00 00 02 5f 00
+ 15 01 00 00 00 00 02 ff 24
+ 15 01 00 00 00 00 02 fb 01
+ 15 01 00 00 00 00 02 00 01
+ 15 01 00 00 00 00 02 01 0b
+ 15 01 00 00 00 00 02 02 0c
+ 15 01 00 00 00 00 02 03 89
+ 15 01 00 00 00 00 02 04 8a
+ 15 01 00 00 00 00 02 05 0f
+ 15 01 00 00 00 00 02 06 10
+ 15 01 00 00 00 00 02 07 10
+ 15 01 00 00 00 00 02 08 1c
+ 15 01 00 00 00 00 02 09 00
+ 15 01 00 00 00 00 02 0a 00
+ 15 01 00 00 00 00 02 0b 00
+ 15 01 00 00 00 00 02 0c 00
+ 15 01 00 00 00 00 02 0d 13
+ 15 01 00 00 00 00 02 0e 15
+ 15 01 00 00 00 00 02 0f 17
+ 15 01 00 00 00 00 02 10 01
+ 15 01 00 00 00 00 02 11 0b
+ 15 01 00 00 00 00 02 12 0c
+ 15 01 00 00 00 00 02 13 89
+ 15 01 00 00 00 00 02 14 8a
+ 15 01 00 00 00 00 02 15 0f
+ 15 01 00 00 00 00 02 16 10
+ 15 01 00 00 00 00 02 17 10
+ 15 01 00 00 00 00 02 18 1c
+ 15 01 00 00 00 00 02 19 00
+ 15 01 00 00 00 00 02 1a 00
+ 15 01 00 00 00 00 02 1b 00
+ 15 01 00 00 00 00 02 1c 00
+ 15 01 00 00 00 00 02 1d 13
+ 15 01 00 00 00 00 02 1e 15
+ 15 01 00 00 00 00 02 1f 17
+ 15 01 00 00 00 00 02 20 00
+ 15 01 00 00 00 00 02 21 01
+ 15 01 00 00 00 00 02 22 00
+ 15 01 00 00 00 00 02 23 40
+ 15 01 00 00 00 00 02 24 40
+ 15 01 00 00 00 00 02 25 6d
+ 15 01 00 00 00 00 02 26 40
+ 15 01 00 00 00 00 02 27 40
+ 15 01 00 00 00 00 02 29 d8
+ 15 01 00 00 00 00 02 2a 2a
+ 15 01 00 00 00 00 02 4b 03
+ 15 01 00 00 00 00 02 4c 11
+ 15 01 00 00 00 00 02 4d 10
+ 15 01 00 00 00 00 02 4e 01
+ 15 01 00 00 00 00 02 4f 01
+ 15 01 00 00 00 00 02 50 10
+ 15 01 00 00 00 00 02 51 00
+ 15 01 00 00 00 00 02 52 80
+ 15 01 00 00 00 00 02 53 00
+ 15 01 00 00 00 00 02 54 07
+ 15 01 00 00 00 00 02 55 25
+ 15 01 00 00 00 00 02 56 00
+ 15 01 00 00 00 00 02 58 07
+ 15 01 00 00 00 00 02 5b 43
+ 15 01 00 00 00 00 02 5c 00
+ 15 01 00 00 00 00 02 5f 73
+ 15 01 00 00 00 00 02 60 73
+ 15 01 00 00 00 00 02 63 22
+ 15 01 00 00 00 00 02 64 00
+ 15 01 00 00 00 00 02 67 08
+ 15 01 00 00 00 00 02 68 04
+ 15 01 00 00 00 00 02 7a 80
+ 15 01 00 00 00 00 02 7b 91
+ 15 01 00 00 00 00 02 7c d8
+ 15 01 00 00 00 00 02 7d 60
+ 15 01 00 00 00 00 02 93 06
+ 15 01 00 00 00 00 02 94 06
+ 15 01 00 00 00 00 02 8a 00
+ 15 01 00 00 00 00 02 9b 0f
+ 15 01 00 00 00 00 02 b3 c0
+ 15 01 00 00 00 00 02 b4 00
+ 15 01 00 00 00 00 02 b5 00
+ 15 01 00 00 00 00 02 b6 21
+ 15 01 00 00 00 00 02 b7 22
+ 15 01 00 00 00 00 02 b8 07
+ 15 01 00 00 00 00 02 b9 07
+ 15 01 00 00 00 00 02 ba 22
+ 15 01 00 00 00 00 02 bd 20
+ 15 01 00 00 00 00 02 be 07
+ 15 01 00 00 00 00 02 bf 07
+ 15 01 00 00 00 00 02 c1 6d
+ 15 01 00 00 00 00 02 c4 24
+ 15 01 00 00 00 00 02 e3 00
+ 15 01 00 00 00 00 02 ec 00
+ 15 01 00 00 00 00 02 ff 10
+ 15 01 00 00 00 00 02 bb 03
+ 05 01 00 00 78 00 02 11 00
+ 05 01 00 00 78 00 02 29 00];
+ qcom,mdss-dsi-off-command = [05 01 00 00
+ 14 00 02 28 00 05 01 00 00 78 00
+ 02 10 00];
+ qcom,mdss-dsi-on-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-off-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 03 08 06 0e];
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>;
+ /delete-node/ qcom,mdss-dsi-display-timings;
+};
+
+&dsi_truly_1080_vid {
+ /delete-property/ qcom,mdss-dsi-panel-timings;
+ qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 02 08 06 0e];
+ qcom,mdss-dsi-t-clk-post = <0x02>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_truly_1080_cmd {
+ /delete-property/ qcom,mdss-dsi-panel-timings;
+ qcom,mdss-dsi-panel-timings-phy-12nm = [17 0a 0f 06 02 08 06 0e];
+ qcom,mdss-dsi-t-clk-post = <0x02>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&i2c_2 {
+#address-cells = <1>;
+#size-cells = <0>;
+
+#include "smb1355.dtsi"
+};
+
+&pmi632_gpios {
+ smb_en {
+ smb_en_default: smb_en_default {
+ pins = "gpio2";
+ function = "func1";
+ output-enable;
+ };
+ };
+
+ pmi632_sense {
+ /* GPIO 7 and 8 are external-sense pins for PMI632 */
+ pmi632_sense_default: pmi632_sense_default {
+ pins = "gpio7", "gpio8";
+ bias-high-impedance; /* disable the GPIO */
+ bias-disable; /* no-pull */
+ };
+ };
+
+ pmi632_ctm {
+ /* Disable GPIO1 for h/w base mitigation */
+ pmi632_ctm_default: pmi632_ctm_default {
+ pins = "gpio1";
+ bias-high-impedance; /* disable the GPIO */
+ bias-disable; /* no-pull */
+ };
+ };
+};
+
+&tlmm {
+ smb_int_default: smb_int_default {
+ mux {
+ pins = "gpio61";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio61";
+ drive-strength = <2>;
+ bias-pull-up;
+ input-enable;
+ };
+ };
+};
+
+&smb1355 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_int_default
+ &smb_en_default &pmi632_sense_default &pmi632_ctm_default>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <61 IRQ_TYPE_LEVEL_LOW>;
+ status = "ok";
+ smb1355_charger: qcom,smb1355-charger@1000 {
+ status = "ok";
+ qcom,parallel-mode = <1>;
+ qcom,disable-ctm;
+ qcom,hw-die-temp-mitigation;
+ };
+};
+
+&smb1355_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_int_default
+ &smb_en_default &pmi632_sense_default &pmi632_ctm_default>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <61 IRQ_TYPE_LEVEL_LOW>;
+ status = "ok";
+ smb1355_charger_0: qcom,smb1355-charger@1000 {
+ status = "ok";
+ qcom,parallel-mode = <1>;
+ qcom,disable-ctm;
+ qcom,hw-die-temp-mitigation;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-pm8953.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-pm8953.dtsi
new file mode 100755
index 0000000..27b9179
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-pm8953.dtsi
@@ -0,0 +1,326 @@
+&rpm_bus {
+ /* Deleting all pm8937 regulators */
+ /delete-node/ rpm-regulator-smpa1;
+ /delete-node/ rpm-regulator-smpa2;
+ /delete-node/ rpm-regulator-smpa3;
+ /delete-node/ rpm-regulator-smpa4;
+ /delete-node/ rpm-regulator-ldoa2;
+ /delete-node/ rpm-regulator-ldoa3;
+ /delete-node/ rpm-regulator-ldoa5;
+ /delete-node/ rpm-regulator-ldoa6;
+ /delete-node/ rpm-regulator-ldoa7;
+ /delete-node/ rpm-regulator-ldoa8;
+ /delete-node/ rpm-regulator-ldoa9;
+ /delete-node/ rpm-regulator-ldoa10;
+ /delete-node/ rpm-regulator-ldoa11;
+ /delete-node/ rpm-regulator-ldoa12;
+ /delete-node/ rpm-regulator-ldoa13;
+ /delete-node/ rpm-regulator-ldoa14;
+ /delete-node/ rpm-regulator-ldoa15;
+ /delete-node/ rpm-regulator-ldoa16;
+ /delete-node/ rpm-regulator-ldoa17;
+ /delete-node/ rpm-regulator-ldoa19;
+ /delete-node/ rpm-regulator-ldoa22;
+ /delete-node/ rpm-regulator-ldoa23;
+};
+
+&spmi_bus {
+ /delete-node/ qcom,pm8937@0;
+ /delete-node/ qcom,pm8937@1;
+};
+
+&thermal_zones {
+ /delete-node/ pa-therm1-adc;
+ /delete-node/ xo-therm-adc;
+ /delete-node/ xo-therm-buf-adc;
+ /delete-node/ case-therm-adc;
+ /delete-node/ pa-therm0-adc;
+ /delete-node/ pm8937_tz;
+};
+
+&int_codec {
+ asoc-codec = <&stub_codec>;
+ asoc-codec-names = "msm-stub-codec.1";
+ /delete-property/ msm-vdd-wsa-switch-supply;
+};
+
+&clock_audio {
+ /delete-property/ qcom,audio-ref-clk-gpio;
+};
+
+&wcd9335 {
+ /delete-property/ cdc-vdd-buck-supply;
+ /delete-property/ cdc-buck-sido-supply;
+ /delete-property/ cdc-vdd-tx-h-supply;
+ /delete-property/ cdc-vdd-rx-h-supply;
+ /delete-property/ cdc-vdd-px-supply;
+ /delete-property/ cdc-vdd-mic-bias-supply;
+};
+
+&soc {
+ /delete-node/ regulator@01946004;
+ /delete-node/ regulator@b018000;
+ /delete-node/ eldo2;
+ /delete-node/ adv_vreg;
+
+ qcom,gcc@1800000 {
+ /delete-property/ vdd_cx-supply;
+ /delete-property/ vdd_sr2_dig-supply;
+ /delete-property/ vdd_sr2_pll-supply;
+ /delete-property/ vdd_hf_dig-supply;
+ /delete-property/ vdd_hf_pll-supply;
+ vdd_cx-supply = <&pm8953_s2_level>;
+ vdd_sr2_dig-supply = <&pm8953_s2_level_ao>;
+ vdd_sr2_pll-supply = <&pm8953_l7_ao>;
+ vdd_hf_dig-supply = <&pm8953_s2_level_ao>;
+ vdd_hf_pll-supply = <&pm8953_l7_ao>;
+ };
+
+ qcom,clock-cpu@b111050 {
+ /delete-property/ vdd-c0-supply;
+ /delete-property/ cpu-vdd-supply;
+ /delete-property/ vdd-cci-supply;
+ };
+
+ qcom,lpass@c200000 {
+ /delete-property/ vdd_cx-supply;
+ };
+
+ qcom,pronto@a21b000 {
+ /delete-property/ vdd_pronto_pll-supply;
+ };
+
+ qcom,wcnss-wlan@0a000000 {
+ /delete-property/ qcom,pronto-vddmx-supply;
+ /delete-property/ qcom,pronto-vddcx-supply;
+ /delete-property/ qcom,pronto-vddpx-supply;
+ /delete-property/ qcom,iris-vddxo-supply;
+ /delete-property/ qcom,iris-vddrfa-supply;
+ /delete-property/ qcom,iris-vddpa-supply;
+ /delete-property/ qcom,iris-vdddig-supply;
+ /delete-property/ qcom,wcnss-adc_tm;
+ };
+};
+
+&pil_mss {
+ /delete-property/ vdd_mss-supply;
+ /delete-property/ vdd_cx-supply;
+ /delete-property/ vdd_cx-voltage;
+ /delete-property/ vdd_mx-supply;
+ /delete-property/ vdd_mx-uV;
+ /delete-property/ vdd_pll-supply;
+};
+
+&mdss_dsi {
+ vdda-supply = <&pm8953_l23>;
+ vddio-supply = <&pm8953_l5>;
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda";
+ qcom,supply-min-voltage = <800000>;
+ qcom,supply-max-voltage = <800000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-post-on-sleep = <20>;
+ };
+ };
+};
+
+&usb_otg {
+ hsusb_vdd_dig-supply = <&pm8953_l23>;
+ HSUSB_1p8-supply = <&pm8953_l7>;
+ HSUSB_3p3-supply = <&pm8953_l13>;
+ qcom,vdd-voltage-level = <0 800000 800000>;
+};
+
+&mdss_dsi0_pll {
+ vddio-supply = <&pm8953_l6>;
+};
+
+&mdss_dsi1_pll {
+ vddio-supply = <&pm8953_l6>;
+};
+
+&mdss_dsi0 {
+ vdd-supply = <&pm8953_l17>;
+ vddio-supply = <&pm8953_l6>;
+};
+
+&mdss_dsi1 {
+ status = "disabled";
+ vdd-supply = <&pm8953_l17>;
+ vddio-supply = <&pm8953_l6>;
+};
+
+&int_codec {
+ /delete-property/ asoc-codec;
+ /delete-property/ msm-vdd-wsa-switch-supply;
+};
+
+&clock_audio {
+ /delete-property/ qcom,audio-ref-clk-gpio;
+};
+
+&wcd9335 {
+ /delete-property/ cdc-vdd-buck-supply;
+ /delete-property/ cdc-buck-sido-supply;
+ /delete-property/ cdc-vdd-tx-h-supply;
+ /delete-property/ cdc-vdd-rx-h-supply;
+ /delete-property/ cdc-vdd-px-supply;
+ /delete-property/ cdc-vdd-mic-bias-supply;
+};
+
+#include "pm8953.dtsi"
+#include "pm8953-rpm-regulator.dtsi"
+#include "sdm439-regulator.dtsi"
+
+&thermal_zones {
+ aoss0-lowf {
+ cooling-maps {
+ cx_vdd_cdev {
+ cooling-device = <&pm8953_cx_cdev 0 0>;
+ };
+ };
+ };
+
+ mdm-core-lowf {
+ cooling-maps {
+ cx_vdd_cdev {
+ cooling-device = <&pm8953_cx_cdev 0 0>;
+ };
+ };
+ };
+
+ lpass-lowf {
+ cooling-maps {
+ cx_vdd_cdev {
+ cooling-device = <&pm8953_cx_cdev 0 0>;
+ };
+ };
+ };
+
+ camera-lowf {
+ cooling-maps {
+ cx_vdd_cdev {
+ cooling-device = <&pm8953_cx_cdev 0 0>;
+ };
+ };
+ };
+
+ cpuss1-lowf {
+ cooling-maps {
+ cx_vdd_cdev {
+ cooling-device = <&pm8953_cx_cdev 0 0>;
+ };
+ };
+ };
+
+ apc1-cpu0-lowf {
+ cooling-maps {
+ cx_vdd_cdev {
+ cooling-device = <&pm8953_cx_cdev 0 0>;
+ };
+ };
+ };
+
+ apc1-cpu1-lowf {
+ cooling-maps {
+ cx_vdd_cdev {
+ cooling-device = <&pm8953_cx_cdev 0 0>;
+ };
+ };
+ };
+
+ apc1-cpu2-lowf {
+ cooling-maps {
+ cx_vdd_cdev {
+ cooling-device = <&pm8953_cx_cdev 0 0>;
+ };
+ };
+ };
+
+ apc1-cpu3-lowf {
+ cooling-maps {
+ cx_vdd_cdev {
+ cooling-device = <&pm8953_cx_cdev 0 0>;
+ };
+ };
+ };
+
+ cpuss0-lowf {
+ cooling-maps {
+ cx_vdd_cdev {
+ cooling-device = <&pm8953_cx_cdev 0 0>;
+ };
+ };
+ };
+
+ gpu-lowf {
+ cooling-maps {
+ cx_vdd_cdev {
+ cooling-device = <&pm8953_cx_cdev 0 0>;
+ };
+ };
+ };
+
+ pa-therm0 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pm8953_adc_tm VADC_LR_MUX7_HW_ID>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <65000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+};
+
+&pm8953_vadc {
+ pinctrl-0 = <&pa_therm1_default>;
+ /delete-node/ case_therm;
+};
+
+&pm8953_mpps {
+ /delete-node/ case_therm;
+};
+
+&pil_mss {
+ vdd_mss-supply = <&pm8953_s1>;
+ vdd_cx-supply = <&pm8953_s2_level>;
+ vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ vdd_mx-supply = <&pm8953_s7_level_ao>;
+ vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ vdd_pll-supply = <&pm8953_l7>;
+};
+
+&soc {
+ qcom,lpass@c200000 {
+ vdd_cx-supply = <&pm8953_s2_level>;
+ };
+
+ qcom,pronto@a21b000 {
+ vdd_pronto_pll-supply = <&pm8953_l7>;
+ };
+
+ qcom,wcnss-wlan@0a000000 {
+ qcom,pronto-vddmx-supply = <&pm8953_s7_level_ao>;
+ qcom,pronto-vddcx-supply = <&pm8953_s2_level>;
+ qcom,pronto-vddpx-supply = <&pm8953_l5>;
+ qcom,iris-vddxo-supply = <&pm8953_l7>;
+ qcom,iris-vddrfa-supply = <&pm8953_l19>;
+ qcom,iris-vddpa-supply = <&pm8953_l9>;
+ qcom,iris-vdddig-supply = <&pm8953_l5>;
+ qcom,wcnss-adc_tm = <&pm8953_adc_tm>;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-pmi632.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-pmi632.dtsi
new file mode 100755
index 0000000..e9a3d57
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-pmi632.dtsi
@@ -0,0 +1,361 @@
+#include "pmi632.dtsi"
+
+&pmi632_charger {
+ dpdm-supply = <&usb_otg>;
+ qcom,battery-data = <&mtp_batterydata>;
+ qcom,auto-recharge-soc = <98>;
+ qcom,flash-disable-soc = <10>;
+ qcom,sw-jeita-enable;
+ qcom,step-charging-enable;
+ qcom,hw-die-temp-mitigation;
+ qcom,hw-connector-mitigation;
+ qcom,connector-internal-pull-kohm = <100>;
+ qcom,thermal-mitigation
+ = <3000000 2500000 2000000 1500000
+ 1000000 500000>;
+};
+
+&usb_otg {
+ extcon = <&pmi632_charger>;
+};
+
+&pmi632_pon {
+ qcom,ps-hold-hard-reset-disable;
+ qcom,ps-hold-shutdown-disable;
+};
+
+&soc {
+ led_flash0: qcom,camera-flash {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ qcom,flash-type = <1>;
+ qcom,flash-source = <&pmi632_flash0 &pmi632_flash1>;
+ qcom,torch-source = <&pmi632_torch0 &pmi632_torch1>;
+ qcom,switch-source = <&pmi632_switch0>;
+ };
+};
+
+/ {
+ mtp_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "qg-batterydata-ascent-3450mah.dtsi"
+ #include "qg-batterydata-mlp356477-2800mah.dtsi"
+ };
+};
+
+&pmi632_qg {
+ qcom,battery-data = <&mtp_batterydata>;
+ qcom,qg-iterm-ma = <100>;
+ qcom,hold-soc-while-full;
+ qcom,linearize-soc;
+};
+
+&pmi632_vadc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&quiet_therm_default &smb_therm_default>;
+};
+
+&pmi632_gpios {
+ quiet_therm {
+ quiet_therm_default: quiet_therm_default {
+ pins = "gpio3";
+ bias-high-impedance;
+ };
+ };
+
+ smb_therm {
+ smb_therm_default: smb_therm_default {
+ pins = "gpio4";
+ bias-high-impedance;
+ };
+ };
+};
+
+&pm8953_typec {
+ status = "disabled";
+};
+
+&thermal_zones {
+ pmi-vbat-lvl0 {
+ cooling-maps {
+ vbat_map0 {
+ trip = <&pmi632_vbat_lvl0>;
+ cooling-device =
+ <&CPU0 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ vbat_map1 {
+ trip = <&pmi632_vbat_lvl0>;
+ cooling-device =
+ <&CPU1 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ vbat_map2 {
+ trip = <&pmi632_vbat_lvl0>;
+ cooling-device =
+ <&CPU2 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ vbat_map3 {
+ trip = <&pmi632_vbat_lvl0>;
+ cooling-device =
+ <&CPU3 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+
+ soc {
+ cooling-maps {
+ soc_map0 {
+ trip = <&pmi632_low_soc>;
+ cooling-device =
+ <&CPU0 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ soc_map1 {
+ trip = <&pmi632_low_soc>;
+ cooling-device =
+ <&CPU1 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ soc_map2 {
+ trip = <&pmi632_low_soc>;
+ cooling-device =
+ <&CPU2 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ soc_map3 {
+ trip = <&pmi632_low_soc>;
+ cooling-device =
+ <&CPU3 THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ };
+ };
+
+ quiet-therm-step {
+ polling-delay-passive = <1000>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmi632_adc_tm 0x53>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+
+ trips {
+ quiet_batt_439_trip1: quiet-batt-trip1 {
+ temperature = <38000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ quiet_batt_439_trip2: quiet-batt-trip2 {
+ temperature = <40000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ quiet_batt_439_trip3: quiet-batt-trip3 {
+ temperature = <42000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ quiet_batt_439_trip4: quiet-batt-trip4 {
+ temperature = <44000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ quiet_modem_439_trip1: quiet-modem-trip0 {
+ temperature = <44000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ quiet_modem_439_trip2: quiet-modem-trip1 {
+ temperature = <46000>;
+ hysteresis = <4000>;
+ type = "passive";
+ };
+
+ quiet_batt_439_trip5: quiet-batt-trip5 {
+ temperature = <46000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ quiet_439_batt_trip6_mdm_trip3: quiet-bt-trp6-mdm-trp3 {
+ temperature = <48000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ quiet_cpus_439_trip: quiet-cpus-trip {
+ temperature = <48000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ quiet_gpu_439_trip: quiet-gpu-trip {
+ temperature = <50000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ quiet_batt_439_trip7: quiet-batt-trip7 {
+ temperature = <50000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ quiet_modem_439_trip4: quiet-modem-trip3 {
+ temperature = <55000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ skin_cpu0 {
+ trip = <&quiet_cpus_439_trip>;
+ /* throttle from fmax to 1497600KHz */
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+
+ skin_cpu1 {
+ trip = <&quiet_cpus_439_trip>;
+ cooling-device = <&CPU1 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+
+ skin_cpu2 {
+ trip = <&quiet_cpus_439_trip>;
+ cooling-device = <&CPU2 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+
+ skin_cpu3 {
+ trip = <&quiet_cpus_439_trip>;
+ cooling-device = <&CPU3 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+
+ skin_cpu4 {
+ trip = <&quiet_cpus_439_trip>;
+ /* throttle from fmax to 1171200KHz */
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+
+ skin_cpu5 {
+ trip = <&quiet_cpus_439_trip>;
+ cooling-device = <&CPU5 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+
+ skin_cpu6 {
+ trip = <&quiet_cpus_439_trip>;
+ cooling-device = <&CPU6 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+
+ skin_cpu7 {
+ trip = <&quiet_cpus_439_trip>;
+ cooling-device = <&CPU7 THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+
+ skin_gpu {
+ trip = <&quiet_gpu_439_trip>;
+ /* throttle from fmax to 510000000Hz */
+ cooling-device = <&msm_gpu THERMAL_NO_LIMIT
+ (THERMAL_MAX_LIMIT-2)>;
+ };
+
+ modem_proc_lvl1 {
+ trip = <&quiet_modem_439_trip1>;
+ cooling-device = <&modem_proc 1 1>;
+ };
+
+ modem_proc_lvl2 {
+ trip = <&quiet_modem_439_trip4>;
+ cooling-device = <&modem_proc 3 3>;
+ };
+
+ modem_lvl1 {
+ trip = <&quiet_modem_439_trip2>;
+ cooling-device = <&modem_pa 1 1>;
+ };
+
+ modem_lvl2 {
+ trip = <&quiet_439_batt_trip6_mdm_trip3>;
+ cooling-device = <&modem_pa 2 2>;
+ };
+
+ modem_lvl3 {
+ trip = <&quiet_modem_439_trip4>;
+ cooling-device = <&modem_pa 3 3>;
+ };
+
+ battery_lvl1 {
+ trip = <&quiet_batt_439_trip1>;
+ cooling-device = <&pmi632_charger 1 1>;
+ };
+
+ battery_lvl2 {
+ trip = <&quiet_batt_439_trip2>;
+ cooling-device = <&pmi632_charger 2 2>;
+ };
+
+ battery_lvl3 {
+ trip = <&quiet_batt_439_trip3>;
+ cooling-device = <&pmi632_charger 3 3>;
+ };
+
+ battery_lvl4 {
+ trip = <&quiet_batt_439_trip4>;
+ cooling-device = <&pmi632_charger 4 4>;
+ };
+
+ battery_lvl5 {
+ trip = <&quiet_batt_439_trip5>;
+ cooling-device = <&pmi632_charger 5 5>;
+ };
+
+ battery_lvl6 {
+ trip = <&quiet_439_batt_trip6_mdm_trip3>;
+ cooling-device = <&pmi632_charger 6 6>;
+ };
+
+ battery_lvl7 {
+ trip = <&quiet_batt_439_trip7>;
+ cooling-device = <&pmi632_charger 7 7>;
+ };
+
+ };
+ };
+
+ quiet-therm-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&pmi632_adc_tm 0x53>;
+ thermal-governor = "user_space";
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <65000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-qrd-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm439-qrd-overlay.dts
new file mode 100755
index 0000000..e8729f8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-qrd-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+#include "sdm439-qrd.dtsi"
+
+/ {
+ model = "QRD";
+ qcom,board-id = <0xb 2>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/sdm439-qrd.dts
new file mode 100755
index 0000000..792d66c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-qrd.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sdm439.dtsi"
+#include "sdm439-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM439 QRD";
+ compatible = "qcom,sdm439-qrd", "qcom,sdm439", "qcom,qrd";
+ qcom,board-id = <0xb 2>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-qrd.dtsi
new file mode 100755
index 0000000..ddcaeb3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-qrd.dtsi
@@ -0,0 +1,426 @@
+#include "msm8937-mdss-panels.dtsi"
+#include "sdm439-camera-sensor-qrd.dtsi"
+
+&blsp1_uart2 {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart_console_active>;
+};
+
+&sdhc_1 {
+ /* device core power supply */
+ vdd-supply = <&pm8953_l8>;
+ qcom,vdd-voltage-level = <2900000 2900000>;
+ qcom,vdd-current-level = <200 570000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm8953_l5>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <200 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000
+ 384000000>;
+ qcom,nonremovable;
+ qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+
+ status = "ok";
+};
+
+&int_codec {
+ status = "okay";
+ qcom,model = "sdm439-sku1-snd-card";
+ qcom,msm-micbias1-ext-cap;
+ qcom,msm-micbias2-ext-cap;
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+ qcom,msm-hs-micbias-type = "external";
+ /delete-property/ qcom,quin-mi2s-gpios;
+};
+
+&cdc_quin_mi2s_gpios {
+ status = "disabled";
+};
+
+&wsa881x_i2c_f {
+ status = "okay";
+};
+
+&wsa881x_i2c_45 {
+ status = "okay";
+};
+
+&pm8953_gpios {
+ nfc_clk {
+ nfc_clk_default: nfc_clk_default {
+ pins = "gpio2";
+ function = "normal";
+ input-enable;
+ power-source = <1>;
+ };
+ };
+};
+
+&i2c_5 { /* BLSP2 QUP1 (NFC) */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "ok";
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 17 0x00>;
+ qcom,nq-ven = <&tlmm 16 0x00>;
+ qcom,nq-firm = <&tlmm 130 0x00>;
+ qcom,nq-clkreq = <&pm8953_gpios 2 0x00>;
+ qcom,nq-esepwr = <&tlmm 93 0x00>;
+ interrupt-parent = <&tlmm>;
+ qcom,clk-src = "BBCLK2";
+ interrupts = <17 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_disable_active
+ &nfc_clk_default>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_disable_suspend>;
+ clocks = <&rpmcc RPM_SMD_BB_CLK2_PIN>;
+ clock-names = "ref_clk";
+ };
+};
+
+&sdhc_2 {
+ /* device core power supply */
+ vdd-supply = <&pm8953_l11>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <15000 800000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm8953_l12>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
+
+ cd-gpios = <&tlmm 67 0x0>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
+ 200000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
+
+ status = "ok";
+};
+
+&soc {
+ gpio_keys: gpio_keys {
+ compatible = "gpio-keys";
+ label = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_key_active>;
+
+ vol_up: vol_up {
+ label = "volume_up";
+ gpios = <&tlmm 91 0x1>;
+ linux,input-type = <1>;
+ linux,code = <115>;
+ debounce-interval = <15>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ };
+ };
+
+ fpc1020 {
+ compatible = "fpc,fpc1020";
+ interrupt-parent = <&tlmm>;
+ interrupts = <48 0>; /* TBD */
+ fpc,gpio_rst = <&tlmm 124 0x0>;
+ fpc,gpio_irq = <&tlmm 48 0>;
+ vcc_spi-supply = <&pm8953_l5>;
+ vdd_io-supply = <&pm8953_l5>;
+ vdd_ana-supply = <&pm8953_l5>;
+ fpc,enable-on-boot;
+ pinctrl-names = "fpc1020_reset_reset",
+ "fpc1020_reset_active",
+ "fpc1020_irq_active";
+ pinctrl-0 = <&fpc_reset_low>;
+ pinctrl-1 = <&fpc_reset_high>;
+ pinctrl-2 = <&fpc_int_low>;
+ };
+};
+
+&tlmm {
+ pmx_ts_rst_active {
+ ts_rst_active: ts_rst_active {
+ mux {
+ pins = "gpio99";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio99";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_rst_suspend {
+ ts_rst_suspend: ts_rst_suspend {
+ mux {
+ pins = "gpio99";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio99";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+};
+
+&soc {
+ hbtp {
+ compatible = "qcom,hbtp-input";
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
+ pinctrl-0 = <&ts_rst_active>;
+ pinctrl-1 = <&ts_rst_suspend>;
+ vcc_ana-supply = <&pm8953_l10>;
+ vcc_dig-supply = <&pm8953_l5>;
+ qcom,afe-load = <20000>;
+ qcom,afe-vtg-min = <3000000>;
+ qcom,afe-vtg-max = <3000000>;
+ qcom,dig-load = <40000>;
+ qcom,dig-vtg-min = <1800000>;
+ qcom,dig-vtg-max = <1800000>;
+ qcom,fb-resume-delay-us = <1000>;
+ qcom,afe-force-power-on;
+ qcom,afe-power-on-delay-us = <6>;
+ qcom,afe-power-off-delay-us = <6>;
+ };
+};
+
+&tlmm {
+ pmx_mdss {
+ mdss_dsi_active: mdss_dsi_active {
+ mux {
+ pins = "gpio60";
+ };
+
+ config {
+ pins = "gpio60";
+ };
+ };
+
+ mdss_dsi_suspend: mdss_dsi_suspend {
+ mux {
+ pins = "gpio60";
+ };
+
+ config {
+ pins = "gpio60";
+ };
+ };
+ };
+};
+
+&dsi_panel_pwr_supply {
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "bklight_en";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1800000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@2 {
+ reg = <2>;
+ qcom,supply-name = "lab";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@3 {
+ reg = <3>;
+ qcom,supply-name = "ibb";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-post-on-sleep = <10>;
+ };
+};
+
+&mdss_dsi {
+ hw-config = "single_dsi";
+};
+
+&mdss_mdp {
+ qcom,mdss-pref-prim-intf = "dsi";
+};
+
+&mdss_dsi0 {
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+ bklight_en-supply = <&pm8953_l5>;
+ vddio-supply = <&pm8953_l6>;
+
+ qcom,dsi-pref-prim-pan = <&dsi_hx8399c_truly_vid>;
+ /delete-property/ qcom,platform-bklight-en-gpio;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+ pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+ qcom,platform-te-gpio = <&tlmm 24 0>;
+ qcom,platform-reset-gpio = <&tlmm 60 0>;
+};
+
+&mdss_dsi1 {
+ status = "disabled";
+};
+
+&pm8953_pwm {
+ status = "ok";
+};
+
+&dsi_hx8399c_truly_vid {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ /delete-property/ qcom,mdss-dsi-panel-timings;
+ qcom,mdss-dsi-panel-timings-phy-12nm = [18 0a 10 06 03 08 06 0e];
+ qcom,mdss-dsi-t-clk-post = <0x02>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-status-read-length = <4>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ qcom,mdss-dsi-min-refresh-rate = <48>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update =
+ "dfps_immediate_porch_mode_vfp";
+};
+
+&dsi_hx8399c_hd_vid {
+ /delete-property/ qcom,mdss-dsi-panel-timings;
+ qcom,mdss-dsi-panel-timings-phy-12nm = [09 06 0a 02 00 05 02 08];
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_pwm";
+ qcom,mdss-dsi-bl-pmic-pwm-frequency = <100>;
+ qcom,mdss-dsi-bl-pmic-bank-select = <0>;
+ qcom,mdss-dsi-pwm-gpio = <&pm8953_gpios 8 0>;
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-status-read-length = <4>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ qcom,mdss-dsi-min-refresh-rate = <48>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update =
+ "dfps_immediate_porch_mode_vfp";
+};
+
+&i2c_2 {
+#address-cells = <1>;
+#size-cells = <0>;
+
+#include "smb1355.dtsi"
+};
+
+&pmi632_gpios {
+ smb_en {
+ smb_en_default: smb_en_default {
+ pins = "gpio2";
+ function = "func1";
+ output-enable;
+ };
+ };
+
+ pmi632_sense {
+ /* GPIO 7 and 8 are external-sense pins for PMI632 */
+ pmi632_sense_default: pmi632_sense_default {
+ pins = "gpio7", "gpio8";
+ bias-high-impedance; /* disable the GPIO */
+ bias-disable; /* no-pull */
+ };
+ };
+
+ pmi632_ctm {
+ /* Disable GPIO1 for h/w base mitigation */
+ pmi632_ctm_default: pmi632_ctm_default {
+ pins = "gpio1";
+ bias-high-impedance; /* disable the GPIO */
+ bias-disable; /* no-pull */
+ };
+ };
+};
+
+&tlmm {
+ smb_int_default: smb_int_default {
+ mux {
+ pins = "gpio61";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio61";
+ drive-strength = <2>;
+ bias-pull-up;
+ input-enable;
+ };
+ };
+};
+
+&smb1355 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_int_default
+ &smb_en_default &pmi632_sense_default &pmi632_ctm_default>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <61 IRQ_TYPE_LEVEL_LOW>;
+ status = "ok";
+ smb1355_charger: qcom,smb1355-charger@1000 {
+ status = "ok";
+ qcom,parallel-mode = <1>;
+ qcom,disable-ctm;
+ qcom,hw-die-temp-mitigation;
+ };
+};
+
+&smb1355_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&smb_int_default
+ &smb_en_default &pmi632_sense_default &pmi632_ctm_default>;
+ interrupt-parent = <&tlmm>;
+ interrupts = <61 IRQ_TYPE_LEVEL_LOW>;
+ status = "ok";
+ smb1355_charger_0: qcom,smb1355-charger@1000 {
+ status = "ok";
+ qcom,parallel-mode = <1>;
+ qcom,disable-ctm;
+ qcom,hw-die-temp-mitigation;
+ };
+};
+
+&pmi632_charger {
+ qcom,thermal-mitigation = <4200000 3500000 3000000 2500000
+ 2000000 1500000 1000000 500000>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-rcm-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm439-rcm-overlay.dts
new file mode 100755
index 0000000..a8a4252
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-rcm-overlay.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+#include "sdm439-rcm.dtsi"
+
+/ {
+ model = "RCM";
+ qcom,board-id = <21 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-rcm.dts b/arch/arm64/boot/dts/vendor/qcom/sdm439-rcm.dts
new file mode 100755
index 0000000..a868997
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-rcm.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sdm439.dtsi"
+#include "sdm439-rcm.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM439 RCM";
+ compatible = "qcom,sdm439-cdp", "qcom,sdm439", "qcom,cdp";
+ qcom,board-id = <21 1>;
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-rcm.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-rcm.dtsi
new file mode 100755
index 0000000..26be67e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-rcm.dtsi
@@ -0,0 +1 @@
+#include "sdm439-cdp.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439-regulator.dtsi
new file mode 100755
index 0000000..a757744
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439-regulator.dtsi
@@ -0,0 +1,498 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&rpm_bus {
+ /* PM8953 regulators */
+ rpm-regulator-smpa1 {
+ status = "okay";
+ pm8953_s1: regulator-s1 {
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ status = "okay";
+ };
+ };
+
+ /* PM8953 S2 - VDD_CX supply */
+ rpm-regulator-smpa2 {
+ status = "okay";
+ pm8953_s2_level: regulator-s2-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_s2_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ pm8953_s2_floor_level: regulator-s2-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_s2_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+
+ pm8953_s2_level_ao: regulator-s2-level-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_s2_level_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ };
+
+ pm8953_cx_cdev: regulator-cx-cdev {
+ compatible = "qcom,regulator-cooling-device";
+ regulator-cdev-supply = <&pm8953_s2_floor_level>;
+ regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NOM_PLUS
+ RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ #cooling-cells = <2>;
+ };
+ };
+
+ rpm-regulator-smpa3 {
+ status = "okay";
+ pm8953_s3: regulator-s3 {
+ regulator-min-microvolt = <856000>;
+ regulator-max-microvolt = <1280000>;
+ qcom,init-voltage = <856000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpa4 {
+ status = "okay";
+ pm8953_s4: regulator-s4 {
+ regulator-min-microvolt = <1900000>;
+ regulator-max-microvolt = <2040000>;
+ qcom,init-voltage = <1900000>;
+ status = "okay";
+ };
+ };
+
+ /* VDD_MX supply */
+ rpm-regulator-smpa7 {
+ status = "okay";
+ pm8953_s7_level: regulator-s7-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_s7_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,init-voltage-level =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ qcom,use-voltage-level;
+ qcom,always-send-voltage;
+ };
+
+ pm8953_s7_level_ao: regulator-s7-level-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_s7_level_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,use-voltage-level;
+ qcom,always-send-voltage;
+ };
+
+ pm8953_s7_level_so: regulator-s7-level-so {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_s7_level_so";
+ qcom,set = <2>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_BINNING>;
+ qcom,init-voltage-level =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ qcom,use-voltage-level;
+ };
+ };
+
+ rpm-regulator-ldoa1 {
+ status = "okay";
+ pm8953_l1: regulator-l1 {
+ regulator-min-microvolt = <968000>;
+ regulator-max-microvolt = <1152000>;
+ qcom,init-voltage = <968000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa2 {
+ status = "okay";
+ pm8953_l2: regulator-l2 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ qcom,init-voltage = <1200000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa3 {
+ status = "okay";
+ pm8953_l3: regulator-l3 {
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1200000>;
+ qcom,init-voltage = <1140000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa4 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <4>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <10000>;
+ status = "okay";
+ pm8953_l4: regulator-l4 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l4";
+ qcom,set = <3>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa5 {
+ status = "okay";
+ pm8953_l5: regulator-l5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa6 {
+ status = "okay";
+ pm8953_l6: regulator-l6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa7 {
+ status = "okay";
+ pm8953_l7: regulator-l7 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+
+ pm8953_l7_ao: regulator-l7-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l7_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ };
+ };
+
+ rpm-regulator-ldoa8 {
+ status = "okay";
+ pm8953_l8: regulator-l8 {
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <2900000>;
+ qcom,init-voltage = <2900000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa9 {
+ status = "okay";
+ pm8953_l9: regulator-l9 {
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <3000000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa10 {
+ status = "okay";
+ pm8953_l10: regulator-l10 {
+ regulator-min-microvolt = <2948000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <2948000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa11 {
+ status = "okay";
+ pm8953_l11: regulator-l11 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ qcom,init-voltage = <2700000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa12 {
+ status = "okay";
+ pm8953_l12: regulator-l12 {
+ regulator-min-microvolt = <1648000>;
+ regulator-max-microvolt = <3100000>;
+ qcom,init-voltage = <1648000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa13 {
+ status = "okay";
+ pm8953_l13: regulator-l13 {
+ regulator-min-microvolt = <3050000>;
+ regulator-max-microvolt = <3100000>;
+ qcom,init-voltage = <3050000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa14 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <14>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <5000>;
+ status = "okay";
+ pm8953_l14: regulator-l14 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l14";
+ qcom,set = <3>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3052000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa15 {
+ compatible = "qcom,rpm-smd-regulator-resource";
+ qcom,resource-name = "ldoa";
+ qcom,resource-id = <15>;
+ qcom,regulator-type = <0>;
+ qcom,hpm-min-load = <5000>;
+ status = "okay";
+ pm8953_l15: regulator-l15 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm8953_l15";
+ qcom,set = <3>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3052000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa16 {
+ status = "okay";
+ pm8953_l16: regulator-l16 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ qcom,init-voltage = <1800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa17 {
+ status = "okay";
+ pm8953_l17: regulator-l17 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2900000>;
+ qcom,init-voltage = <2800000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa19 {
+ status = "okay";
+ pm8953_l19: regulator-l19 {
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1356000>;
+ qcom,init-voltage = <1224000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa22 {
+ status = "okay";
+ pm8953_l22: regulator-l22 {
+ regulator-min-microvolt = <2560000>;
+ regulator-max-microvolt = <2840000>;
+ qcom,init-voltage = <2560000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa23 {
+ status = "okay";
+ pm8953_l23: regulator-l23 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1000000>;
+ qcom,init-voltage = <800000>;
+ status = "okay";
+ };
+ };
+};
+
+&spmi_bus {
+ qcom,pm8953@1 {
+ /* PM8953 S5 + S6 = VDD_APC_supply */
+ pm8953_s5: spm-regulator@2000 {
+ compatible = "qcom,spm-regulator";
+ reg = <0x2000 0x100>;
+ regulator-name = "pm8953_s5";
+ regulator-min-microvolt = <490000>;
+ regulator-max-microvolt = <980000>;
+
+ pm8953_s5_limit: avs-limit-regulator {
+ regulator-name = "pm8953_s5_avs_limit";
+ regulator-min-microvolt = <490000>;
+ regulator-max-microvolt = <980000>;
+ };
+ };
+ };
+};
+
+&soc {
+ apc_mem_acc_vreg: apc-mem-acc-regulator {
+ compatible = "qcom,mem-acc-regulator";
+ regulator-name = "apc_mem_acc_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <2>;
+ qcom,acc-reg-addr-list = <0x01942138 0x01942130 0x01946004>;
+ qcom,acc-init-reg-config = <1 0xff>;
+ qcom,num-acc-corners = <2>;
+ qcom,boot-acc-corner = <1>;
+ qcom,corner1-reg-config =
+ /* 1 -> 1 */
+ <(-1) (-1)>, <(-1) (-1)>,
+ /* 1 -> 2 */
+ < 2 0xffff>, < 3 0xff>;
+ qcom,corner2-reg-config =
+ /* 2 -> 1 */
+ < 2 0x5555>, < 3 0x55>,
+ /* 2 -> 2 */
+ <(-1) (-1)>, <(-1) (-1)>;
+ };
+
+ apc_vreg_corner: regulator@b018000 {
+ compatible = "qcom,cpr-regulator";
+ reg = <0xb018000 0x1000>, <0xb011064 0x4>, <0xa4000 0x1000>;
+ reg-names = "rbcpr", "rbcpr_clk", "efuse_addr";
+ interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
+
+ regulator-name = "apc_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <6>;
+
+ qcom,cpr-fuse-corners = <3>;
+ qcom,cpr-voltage-ceiling = <810000 845000 980000>;
+ qcom,cpr-voltage-floor = <700000 700000 790000>;
+ vdd-apc-supply = <&pm8953_s5>;
+ mem-acc-supply = <&apc_mem_acc_vreg>;
+ qcom,mem-acc-corner-map = <1 1 1 1 2 2>;
+
+ qcom,cpr-ref-clk = <19200>;
+ qcom,cpr-timer-delay = <5000>;
+ qcom,cpr-timer-cons-up = <0>;
+ qcom,cpr-timer-cons-down = <2>;
+ qcom,cpr-irq-line = <0>;
+ qcom,cpr-step-quotient = <10>;
+ qcom,cpr-up-threshold = <2>;
+ qcom,cpr-down-threshold = <4>;
+ qcom,cpr-idle-clocks = <15>;
+ qcom,cpr-gcnt-time = <1>;
+ qcom,vdd-apc-step-up-limit = <1>;
+ qcom,vdd-apc-step-down-limit = <1>;
+ qcom,cpr-apc-volt-step = <5000>;
+
+ qcom,cpr-fuse-row = <67 0>;
+ qcom,cpr-fuse-target-quot = <42 24 6>;
+ qcom,cpr-fuse-ro-sel = <60 57 54>;
+ qcom,cpr-init-voltage-ref = <760000 795000 910000>;
+ qcom,cpr-fuse-init-voltage =
+ <67 36 6 0>,
+ <67 18 6 0>,
+ <67 0 6 0>;
+ qcom,cpr-fuse-quot-offset =
+ <71 26 6 0>,
+ <71 20 6 0>,
+ <70 54 7 0>;
+ qcom,cpr-fuse-quot-offset-scale = <5 5 5>;
+ qcom,cpr-init-voltage-step = <10000>;
+ qcom,cpr-corner-map = <1 2 3 3 3 3>;
+ qcom,cpr-corner-frequency-map =
+ <1 1305600000>,
+ <2 1497600000>,
+ <3 1708800000>,
+ <4 1804800000>,
+ <5 1958400000>,
+ <6 2016000000>;
+ qcom,speed-bin-fuse-sel = <37 34 3 0>;
+ qcom,cpr-speed-bin-max-corners =
+ <0 (-1) 1 2 5>,
+ <1 (-1) 1 2 5>,
+ <4 (-1) 1 2 6>,
+ <5 (-1) 1 2 6>;
+ qcom,cpr-fuse-revision = <69 39 3 0>;
+ qcom,cpr-quot-adjust-scaling-factor-max = <0 1400 1400>;
+ qcom,cpr-voltage-scaling-factor-max = <0 2000 2000>;
+ qcom,cpr-scaled-init-voltage-as-ceiling;
+
+ qcom,cpr-fuse-version-map =
+ /* <Speed-bin pvs-version cpr-rev ... ... ...> */
+ <(-1) (-1) ( 0) (-1) (-1) (-1)>,
+ <(-1) (-1) ( 1) (-1) (-1) (-1)>,
+ <(-1) (-1) (-1) (-1) (-1) (-1)>;
+
+ qcom,cpr-quotient-adjustment =
+ <66 77 66>, /* SVSP/NOM/TUR:30/35/30 mV */
+ <(-74) 0 (-30)>, /* SVSP/NOM/TUR:-34/0/-14 mV */
+ <0 0 0>;
+
+ qcom,cpr-floor-to-ceiling-max-range =
+ <50000 50000 65000 65000 65000 65000>,
+ <50000 50000 65000 65000 65000 65000>,
+ <50000 50000 65000 65000 65000 65000>;
+
+ qcom,cpr-voltage-ceiling-override =
+ <(-1) (-1) 810000 845000 885000 980000 980000 980000>;
+
+ qcom,cpr-virtual-corner-quotient-adjustment =
+ <0 0 0 0 0 0>,
+ <0 0 (-22) 0 0 0>, /* NOMP: -10 mV */
+ <0 0 0 0 0 0>;
+
+ qcom,cpr-enable;
+ };
+
+ dbu1: dbu1 {
+ compatible = "regulator-fixed";
+ regulator-name = "dbu1";
+ startup-delay-us = <0>;
+ enable-active-high;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439.dts b/arch/arm64/boot/dts/vendor/qcom/sdm439.dts
new file mode 100755
index 0000000..5ac98a1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439.dts
@@ -0,0 +1,10 @@
+/dts-v1/;
+
+#include "sdm439.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM439 MTP";
+ compatible = "qcom,sdm439";
+ qcom,pmic-id = <0x010016 0x25 0x0 0x0>;
+ qcom.pmic-name = "PMI632";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm439.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm439.dtsi
new file mode 100755
index 0000000..e0006c1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm439.dtsi
@@ -0,0 +1,685 @@
+#include "msm8937.dtsi"
+#include "sdm439-pm8953.dtsi"
+#include "sdm439-pmi632.dtsi"
+#include "sdm439-audio.dtsi"
+#include <dt-bindings/clock/mdss-12nm-pll-clk.h>
+/ {
+ model = "Qualcomm Technologies, Inc. SDM439";
+ compatible = "qcom,sdm439";
+ qcom,msm-id = <353 0x0>;
+};
+
+&soc {
+ qcom,csid@1b30000 {
+ qcom,csi-vdd-voltage = <800000>;
+ qcom,mipi-csi-vdd-supply = <&pm8953_l23>;
+ };
+
+ qcom,csid@1b30400 {
+ qcom,csi-vdd-voltage = <800000>;
+ qcom,mipi-csi-vdd-supply = <&pm8953_l23>;
+ };
+
+ qcom,csid@1b30800 {
+ qcom,csi-vdd-voltage = <800000>;
+ qcom,mipi-csi-vdd-supply = <&pm8953_l23>;
+ };
+
+ qcom,csiphy@1b34000 {
+ compatible = "qcom,csiphy-v10.00", "qcom,csiphy";
+ };
+
+ qcom,csiphy@1b35000 {
+ compatible = "qcom,csiphy-v10.00", "qcom,csiphy";
+ };
+
+ /delete-node/ qcom,msm-cpufreq;
+ msm_cpufreq: qcom,msm-cpufreq {
+ compatible = "qcom,msm-cpufreq";
+
+ clocks = <&apsscc APCS_MUX_CCI_CLK>,
+ <&apsscc APCS_MUX_C1_CLK>,
+ <&apsscc APCS_MUX_C0_CLK>;
+ clock-names = "l2_clk", "cpu0_clk", "cpu4_clk";
+
+ qcom,governor-per-policy;
+
+ qcom,cpufreq-table-0 =
+ < 960000 >,
+ < 1305600 >,
+ < 1497600 >,
+ < 1708800 >,
+ < 1804800 >,
+ < 1958400 >,
+ < 2016000 >;
+
+ qcom,cpufreq-table-4 =
+ < 768000 >,
+ < 998400 >,
+ < 1171200 >,
+ < 1305600 >,
+ < 1459200 >;
+ };
+
+ /delete-node/ ddr-bw-opp-table;
+ ddr_bw_opp_table: ddr-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 101, 8); /* 769 MB/s */
+ BW_OPP_ENTRY( 211, 8); /* 1611 MB/s */
+ BW_OPP_ENTRY( 278, 8); /* 2124 MB/s */
+ BW_OPP_ENTRY( 384, 8); /* 2929 MB/s */
+ BW_OPP_ENTRY( 422, 8); /* 3221 MB/s */
+ BW_OPP_ENTRY( 557, 8); /* 4248 MB/s */
+ BW_OPP_ENTRY( 662, 8); /* 5053 MB/s */
+ BW_OPP_ENTRY( 749, 8); /* 5712 MB/s */
+ BW_OPP_ENTRY( 797, 8); /* 6079 MB/s */
+ BW_OPP_ENTRY( 845, 8); /* 6445 MB/s */
+ BW_OPP_ENTRY( 931, 8); /* 7104 MB/s */
+ };
+
+ /delete-node/ qcom,cpu-cpu-ddr-bw;
+ cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ /delete-node/ qcom,cpu0-cpu-ddr-latfloor;
+ cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ /delete-node/ qcom,cpu4-cpu-ddr-latfloor;
+ cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&ddr_bw_opp_table>;
+ };
+
+ /delete-node/ qcom,cci;
+ cci_cache: qcom,cci {
+ compatible = "devfreq-simple-dev";
+ clock-names = "devfreq_clk";
+ clocks = <&apsscc APCS_MUX_CCI_CLK>;
+ governor = "performance";
+ freq-tbl-khz =
+ < 400000 >,
+ < 400000 >,
+ < 400000 >,
+ < 533000 >,
+ < 576000 >;
+ };
+
+ /delete-node/ qcom,cpu0-cpugrp;
+ cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ cpu0_computemon: qcom,cpu0-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 1305600 MHZ_TO_MBPS(384, 8) >,
+ < 1804800 MHZ_TO_MBPS(557, 8) >;
+ };
+ };
+
+ /delete-node/ qcom,cpu4-cpugrp;
+ cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+
+ cpu4_computemon: qcom,cpu4-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+ qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 1171200 MHZ_TO_MBPS(384, 8) >,
+ < 1459200 MHZ_TO_MBPS(749, 8) >;
+ };
+ };
+};
+
+
+/ {
+ /delete-node/ energy-costs;
+ energy_costs: energy-costs {
+
+ CPU_COST_0: core-cost0 {
+ busy-cost-data = <
+ 406 137
+ 663 207
+ 761 256
+ 868 327
+ 917 343
+ 995 445
+ 1024 470
+ >;
+ idle-cost-data = <
+ 100 80 60 40
+ >;
+ };
+
+ CPU_COST_1: core-cost1 {
+ busy-cost-data = <
+ 355 43
+ 461 56
+ 541 71
+ 603 89
+ 674 120
+ >;
+ };
+ };
+};
+
+&kgsl_smmu {
+ qcom,enable-static-cb;
+};
+
+&reserved_memory {
+ gpu_mem: gpu_region@0 {
+ compatible = "shared-dma-pool";
+ reusable;
+ alloc-ranges = <0x0 0x80000000 0x0 0x10000000>;
+ alignment = <0 0x400000>;
+ size = <0 0x800000>;
+ };
+};
+
+&modem_mem {
+ reg = <0x0 0x86800000 0x0 0x5500000>;
+};
+
+&adsp_fw_mem {
+ reg = <0x0 0x8bd00000 0x0 0x1100000>;
+};
+
+&wcnss_fw_mem {
+ reg = <0x0 0x8ce00000 0x0 0x700000>;
+};
+
+&soc {
+ pil_gpu: qcom,kgsl-hyp {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <13>;
+ qcom,firmware-name = "a506_zap";
+ memory-region = <&gpu_mem>;
+ qcom,mas-crypto = <&mas_crypto>;
+ clocks = <&gcc GCC_CRYPTO_CLK>,
+ <&gcc GCC_CRYPTO_AHB_CLK>,
+ <&gcc GCC_CRYPTO_AXI_CLK>,
+ <&gcc CRYPTO_CLK_SRC>;
+ clock-names = "scm_core_clk", "scm_iface_clk",
+ "scm_bus_clk", "scm_core_clk_src";
+ qcom,proxy-clock-names = "scm_core_clk", "scm_iface_clk",
+ "scm_bus_clk", "scm_core_clk_src";
+ qcom,scm_core_clk_src-freq = <80000000>;
+ };
+};
+
+&kgsl_msm_iommu {
+ gfx3d_secure: gfx3d_secure {
+ compatible = "qcom,smmu-kgsl-cb";
+ iommus = <&kgsl_smmu 2>;
+ memory-region = <&secure_mem>;
+ };
+};
+
+&apsscc {
+ cpu-vdd-supply = <&apc_vreg_corner>;
+ vdd_hf_pll-supply = <&pm8953_l7_ao>;
+ vdd_dig_ao-supply = <&pm8953_s2_level_ao>;
+ vdd_sr2_pll-supply = <&pm8953_l7_ao>;
+ vdd_sr2_dig_ao-supply = <&pm8953_s2_level_ao>;
+ qcom,speed0-bin-v0-c0 =
+ < 0 0>,
+ < 768000000 1>,
+ < 998400000 1>,
+ < 1171200000 2>,
+ < 1305600000 3>,
+ < 1459200000 5>;
+
+ qcom,speed0-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1305600000 1>,
+ < 1497600000 2>,
+ < 1708800000 3>,
+ < 1958400000 5>;
+
+ qcom,speed0-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+
+ qcom,speed1-bin-v0-c0 =
+ < 0 0>,
+ < 768000000 1>,
+ < 998400000 1>,
+ < 1171200000 2>,
+ < 1305600000 3>,
+ < 1459200000 5>;
+
+ qcom,speed1-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1305600000 1>,
+ < 1497600000 2>,
+ < 1708800000 3>,
+ < 1804800000 5>;
+
+ qcom,speed1-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+
+ qcom,speed4-bin-v0-c0 =
+ < 0 0>,
+ < 768000000 1>,
+ < 998400000 1>,
+ < 1171200000 2>,
+ < 1305600000 3>,
+ < 1459200000 5>;
+
+ qcom,speed4-bin-v0-c1 =
+ < 0 0>,
+ < 960000000 1>,
+ < 1305600000 1>,
+ < 1497600000 2>,
+ < 1708800000 3>,
+ < 1958400000 5>,
+ < 2016000000 6>;
+
+ qcom,speed4-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+
+ qcom,speed5-bin-v0-c0 =
+ < 0 0>,
+ < 768000000 1>,
+ < 998400000 1>,
+ < 1171200000 2>,
+ < 1305600000 3>,
+ < 1459200000 5>;
+
+ qcom,speed5-bin-v0-c1=
+ < 0 0>,
+ < 960000000 1>,
+ < 1305600000 1>,
+ < 1497600000 2>,
+ < 1708800000 3>;
+
+ qcom,speed5-bin-v0-cci =
+ < 0 0>,
+ < 400000000 1>,
+ < 533333333 3>;
+};
+
+&gcc {
+ vdd_cx-supply = <&pm8953_s2_level>;
+};
+
+&gcc_mdss {
+ compatible = "qcom,gcc-mdss-sdm439";
+ clocks = <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,
+ <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,
+ <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>,
+ <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>;
+ clock-names = "pclk0_src", "byte0_src", "pclk1_src",
+ "byte1_src";
+ #clock-cells = <1>;
+};
+
+&mdss_dsi0_pll {
+ compatible = "qcom,mdss_dsi_pll_12nm";
+ reg = <0x001a94400 0x400>,
+ <0x0184d074 0x8>;
+ reg-names = "pll_base", "gdsc_base";
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ qcom,ssc-frequency-hz = <31500>;
+ qcom,ssc-ppm = <5000>;
+};
+
+&mdss_dsi1_pll {
+ compatible = "qcom,mdss_dsi_pll_12nm";
+ reg = <0x001a96400 0x400>,
+ <0x0184d074 0x8>;
+ reg-names = "pll_base", "gdsc_base";
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ qcom,ssc-frequency-hz = <31500>;
+ qcom,ssc-ppm = <5000>;
+};
+
+&mdss_dsi {
+ ranges = <0x1a94000 0x1a94000 0x300
+ 0x1a94400 0x1a94400 0x400
+ 0x193e000 0x193e000 0x30
+ 0x1a96000 0x1a96000 0x300
+ 0x1a96400 0x1a96400 0x400
+ 0x193e000 0x193e000 0x30>;
+
+ clocks = <&gcc_mdss MDSS_MDP_VOTE_CLK>,
+ <&gcc GCC_MDSS_AHB_CLK>,
+ <&gcc GCC_MDSS_AXI_CLK>,
+ <&mdss_dsi0_pll BYTE_CLK_SRC_0_CLK>,
+ <&mdss_dsi1_pll BYTE_CLK_SRC_1_CLK>,
+ <&mdss_dsi0_pll PCLK_SRC_MUX_0_CLK>,
+ <&mdss_dsi1_pll PCLK_SRC_MUX_1_CLK>;
+
+ clock-names = "mdp_core_clk", "iface_clk", "bus_clk",
+ "ext_byte0_clk", "ext_byte1_clk", "ext_pixel0_clk",
+ "ext_pixel1_clk";
+
+};
+
+&mdss_dsi0 {
+ reg = <0x1a94000 0x300>,
+ <0x1a94400 0x400>,
+ <0x193e000 0x30>;
+ reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
+ /delete-property/ qcom,platform-strength-ctrl;
+ /delete-property/ qcom,platform-bist-ctrl;
+ /delete-property/ qcom,platform-regulator-settings;
+ /delete-property/ qcom,platform-lane-config;
+};
+
+&mdss_dsi1 {
+ reg = <0x1a96000 0x300>,
+ <0x1a96400 0x400>,
+ <0x193e000 0x30>;
+ reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
+ /delete-property/ qcom,platform-strength-ctrl;
+ /delete-property/ qcom,platform-bist-ctrl;
+ /delete-property/ qcom,platform-regulator-settings;
+ /delete-property/ qcom,platform-lane-config;
+};
+
+/* GPU Overrides */
+&soc {
+ /delete-node/ gpu-bw-tbl;
+ gpu_bw_tbl: gpu-bw-tbl {
+ compatible = "operating-points-v2";
+ opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */
+
+ opp-100 { opp-hz = /bits/ 64 < 769 >; }; /* 1. 100 MHz */
+
+ opp-211 { opp-hz = /bits/ 64 < 1611 >; }; /* 2. 211 MHz */
+
+ opp-298 { opp-hz = /bits/ 64 < 2273 >; }; /* 3. 298 MHz */
+
+ opp-384 { opp-hz = /bits/ 64 < 2929 >; }; /* 4. 384 MHz */
+
+ opp-557 { opp-hz = /bits/ 64 < 4248 >; }; /* 5. 557 MHz */
+
+ opp-700 { opp-hz = /bits/ 64 < 5346 >; }; /* 6. 700 MHz */
+
+ opp-748 { opp-hz = /bits/ 64 < 5712 >; }; /* 7. 748 MHz */
+
+ opp-806 { opp-hz = /bits/ 64 < 6150 >; }; /* 8. 806 MHz */
+
+ opp-931 { opp-hz = /bits/ 64 < 7105 >; }; /* 9. 931 MHz */
+ };
+};
+
+&msm_gpu {
+ /delete-property/qcom,msm-bus,num-cases;
+ qcom,msm-bus,num-cases = <10>;
+ /delete-property/qcom,msm-bus,vectors-KBps;
+ qcom,msm-bus,vectors-KBps =
+ <26 512 0 0>, /* off */
+ <26 512 0 806400>, /* 1. 100.80 MHz */
+ <26 512 0 1689600>, /* 2. 211.20 MHz */
+ <26 512 0 2380800>, /* 3. 297.60 MHz */
+ <26 512 0 3072000>, /* 4. 384.00 MHz */
+ <26 512 0 4454400>, /* 5. 556.80 MHz */
+ <26 512 0 5299200>, /* 6. 662.40 MHz */
+ <26 512 0 5990400>, /* 7. 748.80 MHz */
+ <26 512 0 6374400>, /* 8. 796.80 MHz */
+ <26 512 0 7449600>; /* 9. 931.20 MHz */
+
+ qcom,gpu-speed-bin-vectors =
+ <0x6004 0x00c00000 22>,
+ <0x6008 0x00000600 7>;
+
+ /delete-node/qcom,gpu-pwrlevels;
+ qcom,gpu-pwrlevel-bins {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible="qcom,gpu-pwrlevel-bins";
+
+ qcom,gpu-pwrlevels-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <0>;
+
+ qcom,initial-pwrlevel = <3>;
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <650000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <9>;
+ };
+
+ /* NOM+ */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <560000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <9>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <510000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <6>;
+ qcom,bus-max = <8>;
+ };
+
+ /* SVS+ */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <7>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <320000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <4>;
+
+ qcom,initial-pwrlevel = <2>;
+
+ /* NOM+ */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <560000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <7>;
+ qcom,bus-max = <9>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <510000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <6>;
+ qcom,bus-max = <8>;
+ };
+
+ /* SVS+ */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <7>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <320000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <5>;
+
+ qcom,initial-pwrlevel = <1>;
+
+ /* NOM */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <510000000>;
+ qcom,bus-freq = <7>;
+ qcom,bus-min = <6>;
+ qcom,bus-max = <8>;
+ };
+
+ /* SVS+ */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <5>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <7>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <320000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <10>;
+
+ qcom,initial-pwrlevel = <0>;
+
+ /* SVS */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <320000000>;
+ qcom,bus-freq = <4>;
+ qcom,bus-min = <4>;
+ qcom,bus-max = <8>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+ };
+};
+
+&sdhc_1 {
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x00076400 0x0 0x0 0x0 0x00040868>;
+
+};
+
+&sdhc_2 {
+ /* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
+ qcom,dll-hsr-list = <0x00076400 0x0 0x0 0x0 0x00040868>;
+
+};
+
+&mdss_mdp {
+ qcom,vbif-settings = <0xd0 0x20>;
+};
+
+&thermal_zones {
+ hexa-cpu-max-step {
+ trips {
+ cpu-trip {
+ temperature = <95000>;
+ };
+ };
+ };
+};
+
+&usb_otg {
+ qcom,hsusb-otg-phy-init-seq = <0x43 0x80 0x06 0x82 0xffffffff>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-audio.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-audio.dtsi
new file mode 100755
index 0000000..cb2c01e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-audio.dtsi
@@ -0,0 +1,491 @@
+#include "sdm660-wsa881x.dtsi"
+#include "sdm660-lpi.dtsi"
+
+&audio_apr {
+ q6core: qcom,q6core-audio {
+ compatible = "qcom,q6core-audio";
+ };
+};
+
+&q6core {
+ int_codec: sound {
+ status = "disabled";
+ compatible = "qcom,sdm660-asoc-snd";
+ qcom,model = "sdm660-snd-card";
+ qcom,mi2s-audio-intf;
+ qcom,auxpcm-audio-intf;
+ qcom,wcn-btfm;
+ qcom,ext-disp-audio-rx;
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
+ qcom,msm-mclk-freq = <9600000>;
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ qcom,msm-micbias2-ext-cap;
+ qcom,msm-hs-micbias-type = "external";
+ qcom,us-euro-gpios = <&us_euro_gpio>;
+ qcom,cdc-pdm-gpios = <&cdc_pdm_gpios>;
+ qcom,cdc-comp-gpios = <&cdc_comp_gpios>;
+ qcom,cdc-dmic-gpios = <&cdc_dmic_gpios>;
+ qcom,audio-routing = "RX_BIAS", "INT_MCLK0",
+ "SPK_RX_BIAS", "INT_MCLK0",
+ "INT_LDO_H", "INT_MCLK0",
+ "RX_I2S_CLK", "INT_MCLK0",
+ "TX_I2S_CLK", "INT_MCLK0",
+ "MIC BIAS External", "Handset Mic",
+ "MIC BIAS External2", "Headset Mic",
+ "MIC BIAS External", "Secondary Mic",
+ "AMIC1", "MIC BIAS External",
+ "AMIC2", "MIC BIAS External2",
+ "AMIC3", "MIC BIAS External",
+ "DMIC1", "MIC BIAS External",
+ "MIC BIAS External", "Digital Mic1",
+ "DMIC2", "MIC BIAS External",
+ "MIC BIAS External", "Digital Mic2",
+ "DMIC3", "MIC BIAS External",
+ "MIC BIAS External", "Digital Mic3",
+ "DMIC4", "MIC BIAS External",
+ "MIC BIAS External", "Digital Mic4",
+ "SpkrLeft IN", "SPK1 OUT",
+ "SpkrRight IN", "SPK2 OUT",
+ "PDM_IN_RX1", "PDM_OUT_RX1",
+ "PDM_IN_RX2", "PDM_OUT_RX2",
+ "PDM_IN_RX3", "PDM_OUT_RX3",
+ "ADC1_IN", "ADC1_OUT",
+ "ADC2_IN", "ADC2_OUT",
+ "ADC3_IN", "ADC3_OUT";
+ asoc-platform = <&pcm0>, <&pcm1>,
+ <&pcm2>, <&voip>,
+ <&voice>, <&loopback>,
+ <&compress>, <&hostless>,
+ <&afe>, <&lsm>,
+ <&routing>, <&pcm_noirq>;
+ asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
+ "msm-pcm-dsp.2", "msm-voip-dsp",
+ "msm-pcm-voice", "msm-pcm-loopback",
+ "msm-compress-dsp", "msm-pcm-hostless",
+ "msm-pcm-afe", "msm-lsm-client",
+ "msm-pcm-routing", "msm-pcm-dsp-noirq";
+ asoc-cpu = <&dai_dp>,
+ <&dai_mi2s0>, <&dai_mi2s1>,
+ <&dai_mi2s2>, <&dai_mi2s3>,
+ <&dai_mi2s4>,
+ <&dai_int_mi2s0>, <&dai_int_mi2s1>,
+ <&dai_int_mi2s2>, <&dai_int_mi2s3>,
+ <&dai_int_mi2s4>, <&dai_int_mi2s5>,
+ <&dai_pri_auxpcm>, <&dai_sec_auxpcm>,
+ <&dai_tert_auxpcm>, <&dai_quat_auxpcm>,
+ <&dai_quin_auxpcm>,
+ <&afe_pcm_rx>, <&afe_pcm_tx>,
+ <&afe_proxy_rx>, <&afe_proxy_tx>,
+ <&incall_record_rx>, <&incall_record_tx>,
+ <&incall_music_rx>, <&incall_music_2_rx>,
+ <&sb_7_rx>, <&sb_7_tx>,
+ <&sb_8_tx>, <&sb_8_rx>,
+ <&usb_audio_rx>, <&usb_audio_tx>,
+ <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>,
+ <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>,
+ <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>,
+ <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>,
+ <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>,
+ <&proxy_rx>, <&proxy_tx>;
+ asoc-cpu-names = "msm-dai-q6-dp.0",
+ "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1",
+ "msm-dai-q6-mi2s.2", "msm-dai-q6-mi2s.3",
+ "msm-dai-q6-mi2s.4", "msm-dai-q6-mi2s.7",
+ "msm-dai-q6-mi2s.8",
+ "msm-dai-q6-mi2s.9", "msm-dai-q6-mi2s.10",
+ "msm-dai-q6-mi2s.11", "msm-dai-q6-mi2s.12",
+ "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2",
+ "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4",
+ "msm-dai-q6-auxpcm.5", "msm-dai-q6-dev.224",
+ "msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
+ "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
+ "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
+ "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16398",
+ "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401",
+ "msm-dai-q6-dev.16400", "msm-dai-q6-dev.28672",
+ "msm-dai-q6-dev.28673", "msm-dai-q6-tdm.36864",
+ "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36880",
+ "msm-dai-q6-tdm.36881", "msm-dai-q6-tdm.36896",
+ "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36912",
+ "msm-dai-q6-tdm.36913", "msm-dai-q6-tdm.36928",
+ "msm-dai-q6-tdm.36929",
+ "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195";
+ asoc-codec = <&stub_codec>, <&msm_digital_codec>,
+ <&pmic_analog_codec>, <&msm_sdw_codec>,
+ <&ext_disp_audio_codec>;
+ asoc-codec-names = "msm-stub-codec.1", "msm-dig-codec",
+ "analog-codec", "msm_sdw_codec",
+ "msm-ext-disp-audio-codec-rx";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa881x_211_en>, <&wsa881x_212_en>,
+ <&wsa881x_213_en>, <&wsa881x_214_en>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+ "SpkrLeft", "SpkrRight";
+ };
+
+ tavil_snd: sound-tavil {
+ compatible = "qcom,sdm660-asoc-snd-tavil";
+ qcom,model = "sdm660-tavil-snd-card";
+ qcom,mi2s-audio-intf;
+ qcom,auxpcm-audio-intf;
+ qcom,wcn-btfm;
+ qcom,ext-disp-audio-rx;
+ qcom,msm-mi2s-master = <1>, <1>, <1>, <1>;
+ qcom,audio-routing =
+ "AIF4 VI", "MCLK",
+ "RX_BIAS", "MCLK",
+ "MADINPUT", "MCLK",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Headset Mic",
+ "AMIC3", "MIC BIAS2",
+ "MIC BIAS2", "ANCRight Headset Mic",
+ "AMIC4", "MIC BIAS2",
+ "MIC BIAS2", "ANCLeft Headset Mic",
+ "AMIC5", "MIC BIAS3",
+ "MIC BIAS3", "Handset Mic",
+ "DMIC0", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic0",
+ "DMIC1", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic1",
+ "DMIC2", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic2",
+ "DMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic3",
+ "DMIC4", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic4",
+ "DMIC5", "MIC BIAS4",
+ "MIC BIAS4", "Digital Mic5",
+ "SpkrLeft IN", "SPK1 OUT",
+ "SpkrRight IN", "SPK2 OUT";
+
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ qcom,us-euro-gpios = <&tavil_us_euro_sw>;
+ qcom,hph-en0-gpio = <&tavil_hph_en0>;
+ qcom,hph-en1-gpio = <&tavil_hph_en1>;
+ qcom,msm-mclk-freq = <9600000>;
+ qcom,usbc-analog-en1_gpio = <&wcd_usbc_analog_en1_gpio>;
+ qcom,usbc-analog-en2_n_gpio = <&wcd_usbc_analog_en2n_gpio>;
+ asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
+ <&loopback>, <&compress>, <&hostless>,
+ <&afe>, <&lsm>, <&routing>, <&cpe>, <&compr>,
+ <&pcm_noirq>;
+ asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1",
+ "msm-pcm-dsp.2", "msm-voip-dsp",
+ "msm-pcm-voice", "msm-pcm-loopback",
+ "msm-compress-dsp", "msm-pcm-hostless",
+ "msm-pcm-afe", "msm-lsm-client",
+ "msm-pcm-routing", "msm-cpe-lsm",
+ "msm-compr-dsp", "msm-pcm-dsp-noirq";
+ asoc-cpu = <&dai_dp>, <&dai_mi2s0>,
+ <&dai_mi2s1>, <&dai_mi2s2>,
+ <&dai_mi2s3>, <&dai_mi2s4>,
+ <&dai_pri_auxpcm>, <&dai_sec_auxpcm>,
+ <&dai_tert_auxpcm>, <&dai_quat_auxpcm>,
+ <&dai_quin_auxpcm>,
+ <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>,
+ <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>,
+ <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>,
+ <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>,
+ <&afe_proxy_tx>, <&incall_record_rx>,
+ <&incall_record_tx>, <&incall_music_rx>,
+ <&incall_music_2_rx>, <&sb_5_rx>, <&sb_6_rx>,
+ <&sb_7_rx>, <&sb_7_tx>, <&sb_8_tx>, <&sb_8_rx>,
+ <&usb_audio_rx>, <&usb_audio_tx>,
+ <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>,
+ <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>,
+ <&dai_tert_tdm_rx_0>, <&dai_tert_tdm_tx_0>,
+ <&dai_quat_tdm_rx_0>, <&dai_quat_tdm_tx_0>,
+ <&dai_quin_tdm_rx_0>, <&dai_quin_tdm_tx_0>,
+ <&proxy_rx>, <&proxy_tx>;
+ asoc-cpu-names = "msm-dai-q6-dp.0", "msm-dai-q6-mi2s.0",
+ "msm-dai-q6-mi2s.1", "msm-dai-q6-mi2s.2",
+ "msm-dai-q6-mi2s.3", "msm-dai-q6-mi2s.4",
+ "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2",
+ "msm-dai-q6-auxpcm.3", "msm-dai-q6-auxpcm.4",
+ "msm-dai-q6-auxpcm.5",
+ "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385",
+ "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387",
+ "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389",
+ "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391",
+ "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393",
+ "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224",
+ "msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
+ "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
+ "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
+ "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394",
+ "msm-dai-q6-dev.16396", "msm-dai-q6-dev.16398",
+ "msm-dai-q6-dev.16399", "msm-dai-q6-dev.16401",
+ "msm-dai-q6-dev.16400", "msm-dai-q6-dev.28672",
+ "msm-dai-q6-dev.28673", "msm-dai-q6-tdm.36864",
+ "msm-dai-q6-tdm.36865", "msm-dai-q6-tdm.36880",
+ "msm-dai-q6-tdm.36881", "msm-dai-q6-tdm.36896",
+ "msm-dai-q6-tdm.36897", "msm-dai-q6-tdm.36912",
+ "msm-dai-q6-tdm.36913", "msm-dai-q6-tdm.36928",
+ "msm-dai-q6-tdm.36929",
+ "msm-dai-q6-dev.8194", "msm-dai-q6-dev.8195";
+ asoc-codec = <&stub_codec>, <&ext_disp_audio_codec>;
+ asoc-codec-names = "msm-stub-codec.1",
+ "msm-ext-disp-audio-codec-rx";
+ qcom,wsa-max-devs = <2>;
+ qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>,
+ <&wsa881x_0213>, <&wsa881x_0214>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight",
+ "SpkrLeft", "SpkrRight";
+ };
+};
+
+&slim_aud {
+ status = "okay";
+ dai_slim: msm_dai_slim {
+ compatible = "qcom,msm-dai-slim";
+ elemental-addr = [ff ff ff fe 17 02];
+ };
+
+ wcd9335: tasha_codec {
+ status = "disabled";
+ compatible = "qcom,tasha-slim-pgd";
+ elemental-addr = [00 01 a0 01 17 02];
+
+ interrupt-parent = <&wcd9xxx_intc>;
+ interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+ 17 18 19 20 21 22 23 24 25 26 27 28 29
+ 30>;
+
+ qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
+
+ clock-names = "wcd_clk", "wcd_native_clk";
+ clocks = <&clock_audio 0>,
+ <&clock_audio_native 0>;
+
+ cdc-vdd-mic-bias-supply = <&pm660l_bob>;
+ qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>;
+ qcom,cdc-vdd-mic-bias-current = <30400>;
+
+ qcom,cdc-static-supplies = "cdc-vdd-mic-bias";
+
+ qcom,cdc-micbias1-mv = <1800>;
+ qcom,cdc-micbias2-mv = <1800>;
+ qcom,cdc-micbias3-mv = <1800>;
+ qcom,cdc-micbias4-mv = <1800>;
+
+ qcom,cdc-mclk-clk-rate = <9600000>;
+ qcom,cdc-slim-ifd = "tasha-slim-ifd";
+ qcom,cdc-slim-ifd-elemental-addr = [00 00 a0 01 17 02];
+ qcom,cdc-dmic-sample-rate = <4800000>;
+ qcom,cdc-mad-dmic-rate = <600000>;
+ };
+
+ wcd934x_cdc: tavil_codec {
+ compatible = "qcom,tavil-slim-pgd";
+ elemental-addr = [00 01 50 02 17 02];
+
+ interrupt-parent = <&wcd9xxx_intc>;
+ interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+ 17 18 19 20 21 22 23 24 25 26 27 28 29
+ 30 31>;
+
+ qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
+
+ clock-names = "wcd_clk";
+ clocks = <&clock_audio_lnbb 0>;
+
+ cdc-vdd-mic-bias-supply = <&pm660l_bob>;
+ qcom,cdc-vdd-mic-bias-voltage = <3300000 3300000>;
+ qcom,cdc-vdd-mic-bias-current = <30400>;
+
+ qcom,cdc-static-supplies = "cdc-vdd-mic-bias";
+
+ qcom,cdc-micbias1-mv = <1800>;
+ qcom,cdc-micbias2-mv = <1800>;
+ qcom,cdc-micbias3-mv = <1800>;
+ qcom,cdc-micbias4-mv = <1800>;
+
+ qcom,cdc-mclk-clk-rate = <9600000>;
+ qcom,cdc-slim-ifd = "tavil-slim-ifd";
+ qcom,cdc-slim-ifd-elemental-addr = [00 00 50 02 17 02];
+ qcom,cdc-dmic-sample-rate = <4800000>;
+ qcom,cdc-mad-dmic-rate = <600000>;
+
+ qcom,wdsp-cmpnt-dev-name = "tavil_codec";
+
+ wcd_spi_0: wcd_spi {
+ compatible = "qcom,wcd-spi-v2";
+ qcom,master-bus-num = <7>;
+ qcom,chip-select = <0>;
+ qcom,max-frequency = <24000000>;
+ qcom,mem-base-addr = <0x100000>;
+ };
+
+ wcd_usbc_analog_en1_gpio: msm_cdc_pinctrl_usbc_audio_en1 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wcd_usbc_analog_en1_active>;
+ pinctrl-1 = <&wcd_usbc_analog_en1_idle>;
+ };
+
+ wcd_usbc_analog_en2n_gpio: msm_cdc_pinctrl_usbc_audio_en2 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&wcd_usbc_analog_en2n_active>;
+ pinctrl-1 = <&wcd_usbc_analog_en2n_idle>;
+ };
+ };
+};
+
+&pm660l_3 {
+ pmic_analog_codec: anlg-cdc@f000 {
+ status = "disabled";
+ compatible = "qcom,pmic-analog-codec";
+ reg = <0xf000 0x200>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-parent = <&spmi_bus>;
+ interrupts = <0x3 0xf0 0x0 IRQ_TYPE_LEVEL_HIGH>,
+ <0x3 0xf0 0x1 IRQ_TYPE_LEVEL_HIGH>,
+ <0x3 0xf0 0x2 IRQ_TYPE_LEVEL_HIGH>,
+ <0x3 0xf0 0x3 IRQ_TYPE_LEVEL_HIGH>,
+ <0x3 0xf0 0x4 IRQ_TYPE_LEVEL_HIGH>,
+ <0x3 0xf0 0x5 IRQ_TYPE_LEVEL_HIGH>,
+ <0x3 0xf0 0x6 IRQ_TYPE_LEVEL_HIGH>,
+ <0x3 0xf0 0x7 IRQ_TYPE_LEVEL_HIGH>,
+ <0x3 0xf1 0x0 IRQ_TYPE_LEVEL_HIGH>,
+ <0x3 0xf1 0x1 IRQ_TYPE_LEVEL_HIGH>,
+ <0x3 0xf1 0x2 IRQ_TYPE_LEVEL_HIGH>,
+ <0x3 0xf1 0x3 IRQ_TYPE_LEVEL_HIGH>,
+ <0x3 0xf1 0x4 IRQ_TYPE_LEVEL_HIGH>,
+ <0x3 0xf1 0x5 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "spk_cnp_int",
+ "spk_clip_int",
+ "spk_ocp_int",
+ "ins_rem_det1",
+ "but_rel_det",
+ "but_press_det",
+ "ins_rem_det",
+ "mbhc_int",
+ "ear_ocp_int",
+ "hphr_ocp_int",
+ "hphl_ocp_det",
+ "ear_cnp_int",
+ "hphr_cnp_int",
+ "hphl_cnp_int";
+
+
+ cdc-vdda-cp-supply = <&pm660_s4>;
+ qcom,cdc-vdda-cp-voltage = <1900000 2050000>;
+ qcom,cdc-vdda-cp-current = <50000>;
+
+ cdc-vdd-pa-supply = <&pm660_s4>;
+ qcom,cdc-vdd-pa-voltage = <2040000 2040000>;
+ qcom,cdc-vdd-pa-current = <260000>;
+
+ cdc-vdd-mic-bias-supply = <&pm660l_l7>;
+ qcom,cdc-vdd-mic-bias-voltage = <3088000 3088000>;
+ qcom,cdc-vdd-mic-bias-current = <5000>;
+
+ qcom,cdc-mclk-clk-rate = <9600000>;
+
+ qcom,cdc-static-supplies = "cdc-vdda-cp",
+ "cdc-vdd-pa";
+
+ qcom,cdc-on-demand-supplies = "cdc-vdd-mic-bias";
+
+ /*
+ * Not marking address @ as driver searches this child
+ * with name msm-dig-codec
+ */
+ msm_digital_codec: msm-dig-codec {
+ compatible = "qcom,msm-digital-codec";
+ reg = <0x152c0000 0x0>;
+ };
+ };
+};
+
+&soc {
+ cdc_pdm_gpios: cdc_pdm_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_pdm_gpios_active &cdc_pdm_2_gpios_active>;
+ pinctrl-1 = <&cdc_pdm_gpios_sleep &cdc_pdm_2_gpios_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ cdc_comp_gpios: cdc_comp_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_comp_gpios_active>;
+ pinctrl-1 = <&cdc_comp_gpios_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ cdc_dmic_gpios: cdc_dmic_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&cdc_dmic12_gpios_active
+ &cdc_dmic34_gpios_active>;
+ pinctrl-1 = <&cdc_dmic12_gpios_sleep
+ &cdc_dmic34_gpios_sleep>;
+ qcom,lpi-gpios;
+ };
+
+ cdc_sdw_gpios: sdw_clk_data_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&sdw_clk_active &sdw_data_active>;
+ pinctrl-1 = <&sdw_clk_sleep &sdw_data_sleep>;
+ };
+
+ wsa_spkr_en1: wsa_spkr_en1_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ pinctrl-1 = <&spkr_1_sd_n_sleep>;
+ };
+
+ wsa_spkr_en2: wsa_spkr_en2_pinctrl {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&spkr_2_sd_n_active>;
+ pinctrl-1 = <&spkr_2_sd_n_sleep>;
+ };
+
+ msm_sdw_codec: msm-sdw-codec@152c1000 {
+ status = "disabled";
+ compatible = "qcom,msm-sdw-codec";
+ reg = <0x152c1000 0x0>;
+ interrupts = <0 161 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "swr_master_irq";
+ qcom,cdc-sdw-gpios = <&cdc_sdw_gpios>;
+
+ swr_master {
+ compatible = "qcom,swr-wcd";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ wsa881x_211_en: wsa881x_en@20170211 {
+ compatible = "qcom,wsa881x";
+ reg = <0x0 0x20170211>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+ };
+
+ wsa881x_212_en: wsa881x_en@20170212 {
+ compatible = "qcom,wsa881x";
+ reg = <0x0 0x20170212>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ };
+
+ wsa881x_213_en: wsa881x_en@21170213 {
+ compatible = "qcom,wsa881x";
+ reg = <0x0 0x21170213>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
+ };
+
+ wsa881x_214_en: wsa881x_en@21170214 {
+ compatible = "qcom,wsa881x";
+ reg = <0x0 0x21170214>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-blsp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-blsp.dtsi
new file mode 100755
index 0000000..a838d5f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-blsp.dtsi
@@ -0,0 +1,582 @@
+#include "sdm660-pinctrl.dtsi"
+
+/ {
+ aliases {
+ spi1 = &spi_1;
+ spi2 = &spi_2;
+ spi3 = &spi_3;
+ spi4 = &spi_4;
+ spi5 = &spi_5;
+ spi6 = &spi_6;
+ spi7 = &spi_7;
+ spi8 = &spi_8;
+ i2c1 = &i2c_1;
+ i2c2 = &i2c_2;
+ i2c3 = &i2c_3;
+ i2c4 = &i2c_4;
+ i2c5 = &i2c_5;
+ i2c6 = &i2c_6;
+ i2c7 = &i2c_7;
+ i2c8 = &i2c_8;
+ };
+};
+
+
+&soc {
+ i2c_1: i2c@c175000 { /* BLSP1 QUP1 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc175000 0x600>;
+ reg-names = "qup_phys_addr";
+ interrupt-names = "qup_irq";
+ interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma_blsp1 4 64 0x20000020 0x20>,
+ <&dma_blsp1 5 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ qcom,master-id = <86>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
+ <&clock_gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
+ qcom,i2c-dat = <&tlmm 2 0x00>;
+ qcom,i2c-clk = <&tlmm 3 0x00>;
+ pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang";
+ pinctrl-0 = <&i2c_1_active>;
+ pinctrl-1 = <&i2c_1_sleep>;
+ pinctrl-2 = <&i2c_1_bitbang>;
+ status = "disabled";
+ };
+
+ i2c_2: i2c@c176000 { /* BLSP1 QUP2 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc176000 0x600>;
+ reg-names = "qup_phys_addr";
+ interrupt-names = "qup_irq";
+ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma_blsp1 6 64 0x20000020 0x20>,
+ <&dma_blsp1 7 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ qcom,master-id = <86>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
+ <&clock_gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ qcom,i2c-dat = <&tlmm 6 0x00>;
+ qcom,i2c-clk = <&tlmm 7 0x00>;
+ pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang";
+ pinctrl-0 = <&i2c_2_active>;
+ pinctrl-1 = <&i2c_2_sleep>;
+ pinctrl-2 = <&i2c_2_bitbang>;
+ status = "disabled";
+ };
+
+ i2c_3: i2c@c177000 { /* BLSP1 QUP3 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc177000 0x600>;
+ reg-names = "qup_phys_addr";
+ interrupt-names = "qup_irq";
+ interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
+ <&dma_blsp1 9 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ qcom,master-id = <86>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
+ <&clock_gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+ qcom,i2c-dat = <&tlmm 10 0x00>;
+ qcom,i2c-clk = <&tlmm 11 0x00>;
+ pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang";
+ pinctrl-0 = <&i2c_3_active>;
+ pinctrl-1 = <&i2c_3_sleep>;
+ pinctrl-2 = <&i2c_3_bitbang>;
+ status = "disabled";
+ };
+
+ i2c_4: i2c@c178000 { /* BLSP1 QUP4 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc178000 0x600>;
+ reg-names = "qup_phys_addr";
+ interrupt-names = "qup_irq";
+ interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
+ <&dma_blsp1 11 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ qcom,master-id = <86>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
+ <&clock_gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
+ qcom,i2c-dat = <&tlmm 14 0x00>;
+ qcom,i2c-clk = <&tlmm 15 0x00>;
+ pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang";
+ pinctrl-0 = <&i2c_4_active>;
+ pinctrl-1 = <&i2c_4_sleep>;
+ pinctrl-2 = <&i2c_4_bitbang>;
+ status = "disabled";
+ };
+
+ i2c_5: i2c@c1b5000 { /* BLSP2 QUP1 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc1b5000 0x600>;
+ reg-names = "qup_phys_addr";
+ interrupt-names = "qup_irq";
+ interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma_blsp2 4 64 0x20000020 0x20>,
+ <&dma_blsp2 5 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ qcom,master-id = <84>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
+ <&clock_gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
+ qcom,i2c-dat = <&tlmm 18 0x00>;
+ qcom,i2c-clk = <&tlmm 19 0x00>;
+ pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang";
+ pinctrl-0 = <&i2c_5_active>;
+ pinctrl-1 = <&i2c_5_sleep>;
+ pinctrl-2 = <&i2c_5_bitbang>;
+ status = "disabled";
+ };
+
+ i2c_6: i2c@c1b6000 { /* BLSP2 QUP2 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc1b6000 0x600>;
+ reg-names = "qup_phys_addr";
+ interrupt-names = "qup_irq";
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma_blsp2 6 64 0x20000020 0x20>,
+ <&dma_blsp2 7 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ qcom,master-id = <84>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
+ <&clock_gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
+ qcom,i2c-dat = <&tlmm 22 0x00>;
+ qcom,i2c-clk = <&tlmm 23 0x00>;
+ pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang";
+ pinctrl-0 = <&i2c_6_active>;
+ pinctrl-1 = <&i2c_6_sleep>;
+ pinctrl-2 = <&i2c_6_bitbang>;
+ status = "disabled";
+ };
+
+ i2c_7: i2c@c1b7000 { /* BLSP2 QUP3 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc1b7000 0x600>;
+ reg-names = "qup_phys_addr";
+ interrupt-names = "qup_irq";
+ interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma_blsp2 8 64 0x20000020 0x20>,
+ <&dma_blsp2 9 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ qcom,master-id = <84>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
+ <&clock_gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
+ qcom,i2c-dat = <&tlmm 26 0x00>;
+ qcom,i2c-clk = <&tlmm 27 0x00>;
+ pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang";
+ pinctrl-0 = <&i2c_7_active>;
+ pinctrl-1 = <&i2c_7_sleep>;
+ pinctrl-2 = <&i2c_7_bitbang>;
+ status = "disabled";
+ };
+
+ i2c_8: i2c@c1b8000 { /* BLSP2 QUP4 */
+ compatible = "qcom,i2c-msm-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xc1b8000 0x600>;
+ reg-names = "qup_phys_addr";
+ interrupt-names = "qup_irq";
+ interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma_blsp2 10 64 0x20000020 0x20>,
+ <&dma_blsp2 11 32 0x20000020 0x20>;
+ dma-names = "tx", "rx";
+ qcom,master-id = <84>;
+ qcom,clk-freq-out = <400000>;
+ qcom,clk-freq-in = <19200000>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
+ <&clock_gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>;
+ qcom,i2c-dat = <&tlmm 30 0x00>;
+ qcom,i2c-clk = <&tlmm 31 0x00>;
+ pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang";
+ pinctrl-0 = <&i2c_8_active>;
+ pinctrl-1 = <&i2c_8_sleep>;
+ pinctrl-2 = <&i2c_8_bitbang>;
+ status = "disabled";
+ };
+
+ spi_1: spi@c175000 { /* BLSP1 QUP1 */
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "spi_physical", "spi_bam_physical";
+ reg = <0xc175000 0x600>,
+ <0xc144000 0x1f000>;
+ interrupt-names = "spi_irq", "spi_bam_irq";
+ interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>, <0 238 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,use-bam;
+ qcom,ver-reg-exists;
+ qcom,bam-consumer-pipe-index = <4>;
+ qcom,bam-producer-pipe-index = <5>;
+ qcom,master-id = <86>;
+ qcom,use-pinctrl;
+ pinctrl-names = "spi_default", "spi_sleep";
+ pinctrl-0 = <&spi_1_active>;
+ pinctrl-1 = <&spi_1_sleep>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
+ <&clock_gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
+ status = "disabled";
+ };
+
+ spi_2: spi@c176000 { /* BLSP1 QUP2 */
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "spi_physical", "spi_bam_physical";
+ reg = <0xc176000 0x600>,
+ <0xc144000 0x1f000>;
+ interrupt-names = "spi_irq", "spi_bam_irq";
+ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>, <0 238 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,use-bam;
+ qcom,ver-reg-exists;
+ qcom,bam-consumer-pipe-index = <6>;
+ qcom,bam-producer-pipe-index = <7>;
+ qcom,master-id = <86>;
+ qcom,use-pinctrl;
+ pinctrl-names = "spi_default", "spi_sleep";
+ pinctrl-0 = <&spi_2_active>;
+ pinctrl-1 = <&spi_2_sleep>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
+ <&clock_gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
+ status = "disabled";
+ };
+
+ spi_3: spi@c177000 { /* BLSP1 QUP3 */
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "spi_physical", "spi_bam_physical";
+ reg = <0xc177000 0x600>,
+ <0xc144000 0x1f000>;
+ interrupt-names = "spi_irq", "spi_bam_irq";
+ interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>, <0 238 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,use-bam;
+ qcom,ver-reg-exists;
+ qcom,bam-consumer-pipe-index = <8>;
+ qcom,bam-producer-pipe-index = <9>;
+ qcom,master-id = <86>;
+ qcom,use-pinctrl;
+ pinctrl-names = "spi_default", "spi_sleep";
+ pinctrl-0 = <&spi_3_active>;
+ pinctrl-1 = <&spi_3_sleep>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
+ <&clock_gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
+ status = "disabled";
+ };
+
+ spi_4: spi@c178000 { /* BLSP1 QUP4 */
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "spi_physical", "spi_bam_physical";
+ reg = <0xc178000 0x600>,
+ <0xc144000 0x1f000>;
+ interrupt-names = "spi_irq", "spi_bam_irq";
+ interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>, <0 238 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,use-bam;
+ qcom,ver-reg-exists;
+ qcom,bam-consumer-pipe-index = <10>;
+ qcom,bam-producer-pipe-index = <11>;
+ qcom,master-id = <86>;
+ qcom,use-pinctrl;
+ pinctrl-names = "spi_default", "spi_sleep";
+ pinctrl-0 = <&spi_4_active>;
+ pinctrl-1 = <&spi_4_sleep>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP1_AHB_CLK>,
+ <&clock_gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
+ status = "disabled";
+ };
+
+ spi_5: spi@c1b5000 { /* BLSP2 QUP1 */
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "spi_physical", "spi_bam_physical";
+ reg = <0xc1b5000 0x600>,
+ <0xc184000 0x1f000>;
+ interrupt-names = "spi_irq", "spi_bam_irq";
+ interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>, <0 239 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,use-bam;
+ qcom,ver-reg-exists;
+ qcom,bam-consumer-pipe-index = <4>;
+ qcom,bam-producer-pipe-index = <5>;
+ qcom,master-id = <84>;
+ qcom,use-pinctrl;
+ pinctrl-names = "spi_default", "spi_sleep";
+ pinctrl-0 = <&spi_5_active>;
+ pinctrl-1 = <&spi_5_sleep>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
+ <&clock_gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>;
+ status = "disabled";
+ };
+
+ spi_6: spi@c1b6000 { /* BLSP2 QUP2 */
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "spi_physical", "spi_bam_physical";
+ reg = <0xc1b6000 0x600>,
+ <0xc184000 0x1f000>;
+ interrupt-names = "spi_irq", "spi_bam_irq";
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>, <0 239 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,use-bam;
+ qcom,ver-reg-exists;
+ qcom,bam-consumer-pipe-index = <6>;
+ qcom,bam-producer-pipe-index = <7>;
+ qcom,master-id = <84>;
+ qcom,use-pinctrl;
+ pinctrl-names = "spi_default", "spi_sleep";
+ pinctrl-0 = <&spi_6_active>;
+ pinctrl-1 = <&spi_6_sleep>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
+ <&clock_gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>;
+ status = "disabled";
+ };
+
+ spi_7: spi@c1b7000 { /* BLSP2 QUP3 */
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "spi_physical", "spi_bam_physical";
+ reg = <0xc1b7000 0x600>,
+ <0xc184000 0x1f000>;
+ interrupt-names = "spi_irq", "spi_bam_irq";
+ interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>, <0 239 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,use-bam;
+ qcom,ver-reg-exists;
+ qcom,bam-consumer-pipe-index = <8>;
+ qcom,bam-producer-pipe-index = <9>;
+ qcom,master-id = <84>;
+ qcom,use-pinctrl;
+ pinctrl-names = "spi_default", "spi_sleep";
+ pinctrl-0 = <&spi_7_active>;
+ pinctrl-1 = <&spi_7_sleep>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
+ <&clock_gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>;
+ status = "disabled";
+ };
+
+ spi_8: spi@c1b8000 { /* BLSP2 QUP4 */
+ compatible = "qcom,spi-qup-v2";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "spi_physical", "spi_bam_physical";
+ reg = <0xc1b8000 0x600>,
+ <0xc184000 0x1f000>;
+ interrupt-names = "spi_irq", "spi_bam_irq";
+ interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>, <0 239 IRQ_TYPE_LEVEL_HIGH>;
+ spi-max-frequency = <50000000>;
+ qcom,use-bam;
+ qcom,ver-reg-exists;
+ qcom,bam-consumer-pipe-index = <10>;
+ qcom,bam-producer-pipe-index = <11>;
+ qcom,master-id = <84>;
+ qcom,use-pinctrl;
+ pinctrl-names = "spi_default", "spi_sleep";
+ pinctrl-0 = <&spi_8_active>;
+ pinctrl-1 = <&spi_8_sleep>;
+ clock-names = "iface_clk", "core_clk";
+ clocks = <&clock_gcc GCC_BLSP2_AHB_CLK>,
+ <&clock_gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>;
+ status = "disabled";
+ };
+
+ blsp1_uart1_hs: uart@c16f000 { /* BLSP1 UART1 */
+ compatible = "qcom,msm-hsuart-v14";
+ reg = <0xc16f000 0x200>,
+ <0xc144000 0x1f000>;
+ reg-names = "core_mem", "bam_mem";
+ interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
+ #address-cells = <0>;
+ interrupt-parent = <&blsp1_uart1_hs>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 0 107 0
+ 1 &intc 0 0 238 0
+ 2 &tlmm 1 0>;
+
+ qcom,inject-rx-on-wakeup;
+ qcom,rx-char-to-inject = <0xfd>;
+
+ qcom,bam-tx-ep-pipe-index = <0>;
+ qcom,bam-rx-ep-pipe-index = <1>;
+ qcom,master-id = <86>;
+ clock-names = "core_clk", "iface_clk";
+ clocks = <&clock_gcc GCC_BLSP1_UART1_APPS_CLK>,
+ <&clock_gcc GCC_BLSP1_AHB_CLK>;
+ pinctrl-names = "sleep", "default";
+ pinctrl-0 = <&blsp1_uart1_sleep>;
+ pinctrl-1 = <&blsp1_uart1_active>;
+
+ qcom,msm-bus,name = "buart1";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <86 512 0 0>,
+ <86 512 500 800>;
+ status = "disabled";
+ };
+
+ blsp1_uart2_hs: uart@c170000 { /* BLSP1 UART2 */
+ compatible = "qcom,msm-hsuart-v14";
+ reg = <0xc170000 0x200>,
+ <0xc144000 0x1f000>;
+ reg-names = "core_mem", "bam_mem";
+ interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
+ #address-cells = <0>;
+ interrupt-parent = <&blsp1_uart2_hs>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 0 108 0
+ 1 &intc 0 0 238 0
+ 2 &tlmm 5 0>;
+
+ qcom,inject-rx-on-wakeup;
+ qcom,rx-char-to-inject = <0xfd>;
+
+ qcom,bam-tx-ep-pipe-index = <2>;
+ qcom,bam-rx-ep-pipe-index = <3>;
+ qcom,master-id = <86>;
+ clock-names = "core_clk", "iface_clk";
+ clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&clock_gcc GCC_BLSP1_AHB_CLK>;
+ pinctrl-names = "sleep", "default";
+ pinctrl-0 = <&blsp1_uart2_sleep>;
+ pinctrl-1 = <&blsp1_uart2_active>;
+
+ qcom,msm-bus,name = "buart2";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <86 512 0 0>,
+ <86 512 500 800>;
+ status = "disabled";
+ };
+
+ blsp2_uart1_hs: uart@c1af000 { /* BLSP2 UART1 */
+ compatible = "qcom,msm-hsuart-v14";
+ reg = <0xc1af000 0x200>,
+ <0xc184000 0x1f000>;
+ reg-names = "core_mem", "bam_mem";
+ interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
+ #address-cells = <0>;
+ interrupt-parent = <&blsp2_uart1_hs>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 0 113 0
+ 1 &intc 0 0 239 0
+ 2 &tlmm 17 0>;
+
+ qcom,inject-rx-on-wakeup;
+ qcom,rx-char-to-inject = <0xfd>;
+
+ qcom,bam-tx-ep-pipe-index = <0>;
+ qcom,bam-rx-ep-pipe-index = <1>;
+ qcom,master-id = <84>;
+ clock-names = "core_clk", "iface_clk";
+ clocks = <&clock_gcc GCC_BLSP2_UART1_APPS_CLK>,
+ <&clock_gcc GCC_BLSP2_AHB_CLK>;
+ pinctrl-names = "sleep", "default";
+ pinctrl-0 = <&blsp2_uart1_tx_sleep>,
+ <&blsp2_uart1_rxcts_sleep>, <&blsp2_uart1_rfr_sleep>;
+ pinctrl-1 = <&blsp2_uart1_tx_active>,
+ <&blsp2_uart1_rxcts_active>, <&blsp2_uart1_rfr_active>;
+ qcom,msm-bus,name = "buart3";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <84 512 0 0>,
+ <84 512 500 800>;
+ status = "disabled";
+ };
+
+ blsp2_uart2_hs: uart@c1b0000 { /* BLSP2 UART2 */
+ compatible = "qcom,msm-hsuart-v14";
+ reg = <0xc1b0000 0x200>,
+ <0xc184000 0x1f000>;
+ reg-names = "core_mem", "bam_mem";
+ interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
+ #address-cells = <0>;
+ interrupt-parent = <&blsp2_uart2_hs>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 0 114 0
+ 1 &intc 0 0 239 0
+ 2 &tlmm 25 0>;
+
+ qcom,inject-rx-on-wakeup;
+ qcom,rx-char-to-inject = <0xfd>;
+
+ qcom,bam-tx-ep-pipe-index = <2>;
+ qcom,bam-rx-ep-pipe-index = <3>;
+ qcom,master-id = <84>;
+ clock-names = "core_clk", "iface_clk";
+ clocks = <&clock_gcc GCC_BLSP2_UART2_APPS_CLK>,
+ <&clock_gcc GCC_BLSP2_AHB_CLK>;
+ pinctrl-names = "sleep", "default";
+ pinctrl-0 = <&blsp2_uart2_sleep>;
+ pinctrl-1 = <&blsp2_uart2_active>;
+
+ qcom,msm-bus,name = "buart4";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <84 512 0 0>,
+ <84 512 500 800>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-bus.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-bus.dtsi
new file mode 100755
index 0000000..77b36ba
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-bus.dtsi
@@ -0,0 +1,1281 @@
+#include <dt-bindings/msm/msm-bus-ids.h>
+
+&soc {
+ ad_hoc_bus: ad-hoc-bus {
+ /*Version = 14 */
+ compatible = "qcom,msm-bus-device";
+ reg = <0x1620000 0x20000>,
+ <0x1000000 0x80000>,
+ <0x1500000 0x10000>,
+ <0x1700000 0x20000>,
+ <0x17900000 0xE000>,
+ <0x1740000 0x10000>,
+ <0x1740000 0x10000>;
+
+ reg-names = "snoc-base", "bimc-base", "cnoc-base",
+ "a2noc-base", "gnoc-base", "mmnoc-ahb-base", "mnoc-base";
+
+ /*Buses*/
+
+ fab_a2noc: fab-a2noc {
+ cell-id = <MSM_BUS_FAB_A2_NOC>;
+ label = "fab-a2noc";
+ qcom,fab-dev;
+ qcom,base-name = "a2noc-base";
+ qcom,bus-type = <1>;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <16384>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_rpmcc AGGR2_NOC_MSMBUS_CLK>,
+ <&clock_rpmcc AGGR2_NOC_MSMBUS_A_CLK>;
+ qcom,node-qos-clks {
+ clock-names =
+ "clk-ipa-clk",
+ "clk-ufs-axi-clk",
+ "clk-aggre2-ufs-axi-no-rate",
+ "clk-aggre2-usb3-axi-cfg-no-rate",
+ "clk-cfg-noc-usb2-axi-no-rate";
+ clocks =
+ <&clock_rpmcc RPM_SMD_IPA_CLK>,
+ <&clock_gcc GCC_UFS_AXI_CLK>,
+ <&clock_gcc GCC_AGGRE2_UFS_AXI_CLK>,
+ <&clock_gcc GCC_AGGRE2_USB3_AXI_CLK>,
+ <&clock_gcc GCC_CFG_NOC_USB2_AXI_CLK>;
+ };
+ };
+
+ fab_bimc: fab-bimc {
+ cell-id = <MSM_BUS_FAB_BIMC>;
+ label = "fab-bimc";
+ qcom,fab-dev;
+ qcom,base-name = "bimc-base";
+ qcom,bus-type = <2>;
+ qcom,util-fact = <153>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_rpmcc BIMC_MSMBUS_CLK>,
+ <&clock_rpmcc BIMC_MSMBUS_A_CLK>;
+ };
+
+ fab_cnoc: fab-cnoc {
+ cell-id = <MSM_BUS_FAB_CONFIG_NOC>;
+ label = "fab-cnoc";
+ qcom,fab-dev;
+ qcom,base-name = "cnoc-base";
+ qcom,bus-type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_rpmcc CNOC_MSMBUS_CLK>,
+ <&clock_rpmcc CNOC_MSMBUS_A_CLK>;
+ };
+
+ fab_gnoc: fab-gnoc {
+ cell-id = <MSM_BUS_FAB_GNOC>;
+ label = "fab-gnoc";
+ qcom,virt-dev;
+ qcom,base-name = "gnoc-base";
+ };
+
+ fab_mnoc: fab-mnoc {
+ cell-id = <MSM_BUS_FAB_MMSS_NOC>;
+ label = "fab-mnoc";
+ qcom,fab-dev;
+ qcom,base-name = "mnoc-base";
+ qcom,bus-type = <1>;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <20480>;
+ qcom,util-fact = <153>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_A_CLK>;
+ qcom,node-qos-clks {
+ clock-names =
+ "clk-mmssnoc-axi-no-rate",
+ "clk-mmss-noc-cfg-ahb-no-rate";
+ clocks =
+ <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_gcc GCC_MMSS_NOC_CFG_AHB_CLK>;
+ };
+ };
+
+ fab_snoc: fab-snoc {
+ cell-id = <MSM_BUS_FAB_SYS_NOC>;
+ label = "fab-snoc";
+ qcom,fab-dev;
+ qcom,base-name = "snoc-base";
+ qcom,bus-type = <1>;
+ qcom,qos-off = <4096>;
+ qcom,base-offset = <24576>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_rpmcc SNOC_MSMBUS_CLK>,
+ <&clock_rpmcc SNOC_MSMBUS_A_CLK>;
+ };
+
+ fab_mnoc_ahb: fab-mnoc-ahb {
+ cell-id = <MSM_BUS_FAB_MMSS_AHB>;
+ label = "fab-mnoc-ahb";
+ qcom,fab-dev;
+ qcom,base-name = "mmnoc-ahb-base";
+ qcom,setrate-only-clk;
+ qcom,bus-type = <1>;
+ clock-names = "bus_clk", "bus_a_clk";
+ clocks = <&clock_mmss AHB_CLK_SRC >,
+ <&clock_mmss AHB_CLK_SRC>;
+ };
+
+ /*Masters*/
+
+ mas_ipa: mas-ipa {
+ cell-id = <MSM_BUS_MASTER_IPA>;
+ label = "mas-ipa";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <3>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_IPA>;
+ };
+
+ mas_cnoc_a2noc: mas-cnoc-a2noc {
+ cell-id = <MSM_BUS_MASTER_CNOC_A2NOC>;
+ label = "mas-cnoc-a2noc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CNOC_A2NOC>;
+ qcom,blacklist = <&slv_snoc_cnoc>;
+ };
+
+ mas_sdcc_1: mas-sdcc-1 {
+ cell-id = <MSM_BUS_MASTER_SDCC_1>;
+ label = "mas-sdcc-1";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SDCC_1>;
+ };
+
+ mas_sdcc_2: mas-sdcc-2 {
+ cell-id = <MSM_BUS_MASTER_SDCC_2>;
+ label = "mas-sdcc-2";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SDCC_2>;
+ };
+
+ mas_blsp_1: mas-blsp-1 {
+ cell-id = <MSM_BUS_MASTER_BLSP_1>;
+ label = "mas-blsp-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BLSP_1>;
+ };
+
+ mas_blsp_2: mas-blsp-2 {
+ cell-id = <MSM_BUS_MASTER_BLSP_2>;
+ label = "mas-blsp-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BLSP_2>;
+ };
+
+ mas_ufs: mas-ufs {
+ cell-id = <MSM_BUS_MASTER_UFS>;
+ label = "mas-ufs";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <4>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_UFS>;
+ };
+
+ mas_usb_hs: mas-usb-hs {
+ cell-id = <MSM_BUS_MASTER_USB_HS>;
+ label = "mas-usb-hs";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_USB_HS>;
+ };
+
+ mas_usb3: mas-usb3 {
+ cell-id = <MSM_BUS_MASTER_USB3>;
+ label = "mas-usb3";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_USB3>;
+ };
+
+ mas_crypto_c0: mas-crypto-c0 {
+ cell-id = <MSM_BUS_MASTER_CRYPTO_CORE0>;
+ label = "mas-crypto-c0";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,qport = <11>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_a2noc_snoc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CRYPTO_CORE0>;
+ };
+
+ mas_gnoc_bimc: mas-gnoc-bimc {
+ cell-id = <MSM_BUS_MASTER_GNOC_BIMC>;
+ label = "mas-gnoc-bimc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_ebi>;
+ qcom,prio-lvl = <0>;
+ qcom,prio-rd = <0>;
+ qcom,prio-wr = <0>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_GNOC_BIMC>;
+ };
+
+ mas_oxili: mas-oxili {
+ cell-id = <MSM_BUS_MASTER_GRAPHICS_3D>;
+ label = "mas-oxili";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_hmss_l3
+ &slv_ebi &slv_bimc_snoc>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_GFX3D>;
+ };
+
+ mas_mnoc_bimc: mas-mnoc-bimc {
+ cell-id = <MSM_BUS_MNOC_BIMC_MAS>;
+ label = "mas-mnoc-bimc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_hmss_l3
+ &slv_ebi &slv_bimc_snoc>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_MNOC_BIMC>;
+ };
+
+ mas_snoc_bimc: mas-snoc-bimc {
+ cell-id = <MSM_BUS_SNOC_BIMC_MAS>;
+ label = "mas-snoc-bimc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,connections = <&slv_hmss_l3 &slv_ebi>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_BIMC>;
+ };
+
+ mas_pimem: mas-pimem {
+ cell-id = <MSM_BUS_MASTER_PIMEM>;
+ label = "mas-pimem";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,ap-owned;
+ qcom,qport = <4>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_hmss_l3 &slv_ebi>;
+ qcom,prio-lvl = <1>;
+ qcom,prio-rd = <1>;
+ qcom,prio-wr = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_PIMEM>;
+ };
+
+ mas_snoc_cnoc: mas-snoc-cnoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_MAS>;
+ label = "mas-snoc-cnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_clk_ctl
+ &slv_qdss_cfg &slv_qm_cfg
+ &slv_srvc_cnoc &slv_ufs_cfg
+ &slv_tcsr &slv_a2noc_smmu_cfg
+ &slv_snoc_cfg &slv_tlmm_south
+ &slv_mpm &slv_cnoc_mnoc_mmss_cfg
+ &slv_sdcc_2 &slv_sdcc_1
+ &slv_spdm &slv_pmic_arb
+ &slv_prng &slv_mss_cfg
+ &slv_gpuss_cfg &slv_imem_cfg
+ &slv_usb3_0 &slv_a2noc_cfg
+ &slv_tlmm_north &slv_usb_hs
+ &slv_pdm &slv_tlmm_center
+ &slv_ahb2phy &slv_blsp_2
+ &slv_blsp_1 &slv_pimem_cfg
+ &slv_glm &slv_message_ram
+ &slv_bimc_cfg &slv_cnoc_mnoc_cfg>;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_CNOC>;
+ };
+
+ mas_qdss_dap: mas-qdss-dap {
+ cell-id = <MSM_BUS_MASTER_QDSS_DAP>;
+ label = "mas-qdss-dap";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_clk_ctl
+ &slv_qdss_cfg &slv_qm_cfg
+ &slv_srvc_cnoc &slv_ufs_cfg
+ &slv_tcsr &slv_a2noc_smmu_cfg
+ &slv_snoc_cfg &slv_tlmm_south
+ &slv_mpm &slv_cnoc_mnoc_mmss_cfg
+ &slv_sdcc_2 &slv_sdcc_1
+ &slv_spdm &slv_pmic_arb
+ &slv_prng &slv_mss_cfg
+ &slv_gpuss_cfg &slv_imem_cfg
+ &slv_usb3_0 &slv_a2noc_cfg
+ &slv_tlmm_north &slv_usb_hs
+ &slv_pdm &slv_tlmm_center
+ &slv_ahb2phy &slv_blsp_2
+ &slv_blsp_1 &slv_pimem_cfg
+ &slv_glm &slv_message_ram
+ &slv_cnoc_a2noc &slv_bimc_cfg
+ &slv_cnoc_mnoc_cfg>;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_DAP>;
+ };
+
+ mas_apps_proc: mas-apps-proc {
+ cell-id = <MSM_BUS_MASTER_AMPSS_M0>;
+ label = "mas-apps-proc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_gnoc_snoc &slv_gnoc_bimc>;
+ qcom,bus-dev = <&fab_gnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_APPSS_PROC>;
+ };
+
+ mas_cnoc_mnoc_mmss_cfg: mas-cnoc-mnoc-mmss-cfg {
+ cell-id = <MSM_BUS_MASTER_CNOC_MNOC_MMSS_CFG>;
+ label = "mas-cnoc-mnoc-mmss-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_venus_throttle_cfg
+ &slv_venus_cfg &slv_camera_throttle_cfg
+ &slv_smmu_cfg &slv_camera_cfg &slv_csi_phy_cfg
+ &slv_display_throttle_cfg &slv_display_cfg
+ &slv_mmss_clk_cfg &slv_mnoc_mpu_cfg
+ &slv_misc_cfg &slv_mmss_clk_xpu_cfg>;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CNOC_MNOC_MMSS_CFG>;
+ };
+
+ mas_cnoc_mnoc_cfg: mas-cnoc-mnoc-cfg {
+ cell-id = <MSM_BUS_MASTER_CNOC_MNOC_CFG>;
+ label = "mas-cnoc-mnoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,connections = <&slv_srvc_mnoc>;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CNOC_MNOC_CFG>;
+ };
+
+ mas_cpp: mas-cpp {
+ cell-id = <MSM_BUS_MASTER_CPP>;
+ label = "mas-cpp";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <4>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_CPP>;
+ };
+
+ mas_jpeg: mas-jpeg {
+ cell-id = <MSM_BUS_MASTER_JPEG>;
+ label = "mas-jpeg";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <6>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_JPEG>;
+ };
+
+ mas_mdp_p0: mas-mdp-p0 {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT0>;
+ label = "mas-mdp-p0";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,vrail-comp = <50>;
+ qcom,mas-rpm-id = <ICBID_MASTER_MDP0>;
+ };
+
+ mas_mdp_p1: mas-mdp-p1 {
+ cell-id = <MSM_BUS_MASTER_MDP_PORT1>;
+ label = "mas-mdp-p1";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,vrail-comp = <50>;
+ qcom,mas-rpm-id = <ICBID_MASTER_MDP1>;
+ };
+
+ mas_venus: mas-venus {
+ cell-id = <MSM_BUS_MASTER_VIDEO_P0>;
+ label = "mas-venus";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <2>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VIDEO>;
+ };
+
+ mas_vfe: mas-vfe {
+ cell-id = <MSM_BUS_MASTER_VFE>;
+ label = "mas-vfe";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <5>;
+ qcom,qos-mode = "bypass";
+ qcom,connections = <&slv_mnoc_bimc>;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_VFE>;
+ };
+
+ mas_qdss_etr: mas-qdss-etr {
+ cell-id = <MSM_BUS_MASTER_QDSS_ETR>;
+ label = "mas-qdss-etr";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <1>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_pimem
+ &slv_imem &slv_snoc_cnoc
+ &slv_snoc_bimc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_ETR>;
+ };
+
+ mas_qdss_bam: mas-qdss-bam {
+ cell-id = <MSM_BUS_MASTER_QDSS_BAM>;
+ label = "mas-qdss-bam";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,qport = <0>;
+ qcom,qos-mode = "fixed";
+ qcom,connections = <&slv_pimem
+ &slv_imem &slv_snoc_cnoc
+ &slv_snoc_bimc>;
+ qcom,prio1 = <1>;
+ qcom,prio0 = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_QDSS_BAM>;
+ };
+
+ mas_snoc_cfg: mas-snoc-cfg {
+ cell-id = <MSM_BUS_MASTER_SNOC_CFG>;
+ label = "mas-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_srvc_snoc>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_SNOC_CFG>;
+ };
+
+ mas_bimc_snoc: mas-bimc-snoc {
+ cell-id = <MSM_BUS_BIMC_SNOC_MAS>;
+ label = "mas-bimc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_pimem
+ &slv_ipa &slv_qdss_stm
+ &slv_lpass &slv_hmss
+ &slv_cdsp &slv_snoc_cnoc
+ &slv_wlan &slv_imem>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_BIMC_SNOC>;
+ };
+
+ mas_a2noc_snoc: mas-a2noc-snoc {
+ cell-id = <MSM_BUS_A2NOC_SNOC_MAS>;
+ label = "mas-a2noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_pimem
+ &slv_ipa &slv_qdss_stm
+ &slv_lpass &slv_hmss
+ &slv_snoc_bimc &slv_cdsp
+ &slv_snoc_cnoc &slv_wlan
+ &slv_imem>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_A2NOC_SNOC>;
+ };
+
+ /*Internal nodes*/
+
+ /*Slaves*/
+
+ slv_a2noc_snoc:slv-a2noc-snoc {
+ cell-id = <MSM_BUS_A2NOC_SNOC_SLV>;
+ label = "slv-a2noc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_a2noc>;
+ qcom,connections = <&mas_a2noc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_A2NOC_SNOC>;
+ };
+
+ slv_ebi:slv-ebi {
+ cell-id = <MSM_BUS_SLAVE_EBI_CH0>;
+ label = "slv-ebi";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <2>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_EBI1>;
+ };
+
+ slv_hmss_l3:slv-hmss-l3 {
+ cell-id = <MSM_BUS_SLAVE_HMSS_L3>;
+ label = "slv-hmss-l3";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_HMSS_L3>;
+ };
+
+ slv_bimc_snoc:slv-bimc-snoc {
+ cell-id = <MSM_BUS_BIMC_SNOC_SLV>;
+ label = "slv-bimc-snoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_bimc>;
+ qcom,connections = <&mas_bimc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_SNOC>;
+ };
+
+ slv_cnoc_a2noc:slv-cnoc-a2noc {
+ cell-id = <MSM_BUS_SLAVE_CNOC_A2NOC>;
+ label = "slv-cnoc-a2noc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,connections = <&mas_cnoc_a2noc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_A2NOC>;
+ };
+
+ slv_mpm:slv-mpm {
+ cell-id = <MSM_BUS_SLAVE_MPM>;
+ label = "slv-mpm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MPM>;
+ };
+
+ slv_pmic_arb:slv-pmic-arb {
+ cell-id = <MSM_BUS_SLAVE_PMIC_ARB>;
+ label = "slv-pmic-arb";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PMIC_ARB>;
+ };
+
+ slv_tlmm_north:slv-tlmm-north {
+ cell-id = <MSM_BUS_SLAVE_TLMM_NORTH>;
+ label = "slv-tlmm-north";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TLMM_NORTH>;
+ };
+
+ slv_tcsr:slv-tcsr {
+ cell-id = <MSM_BUS_SLAVE_TCSR>;
+ label = "slv-tcsr";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TCSR>;
+ };
+
+ slv_pimem_cfg:slv-pimem-cfg {
+ cell-id = <MSM_BUS_SLAVE_PIMEM_CFG>;
+ label = "slv-pimem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PIMEM_CFG>;
+ };
+
+ slv_imem_cfg:slv-imem-cfg {
+ cell-id = <MSM_BUS_SLAVE_IMEM_CFG>;
+ label = "slv-imem-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IMEM_CFG>;
+ };
+
+ slv_message_ram:slv-message-ram {
+ cell-id = <MSM_BUS_SLAVE_MESSAGE_RAM>;
+ label = "slv-message-ram";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MESSAGE_RAM>;
+ };
+
+ slv_glm:slv-glm {
+ cell-id = <MSM_BUS_SLAVE_GLM>;
+ label = "slv-glm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GLM>;
+ };
+
+ slv_bimc_cfg:slv-bimc-cfg {
+ cell-id = <MSM_BUS_SLAVE_BIMC_CFG>;
+ label = "slv-bimc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BIMC_CFG>;
+ };
+
+ slv_prng:slv-prng {
+ cell-id = <MSM_BUS_SLAVE_PRNG>;
+ label = "slv-prng";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PRNG>;
+ };
+
+ slv_spdm:slv-spdm {
+ cell-id = <MSM_BUS_SLAVE_SPDM_WRAPPER>;
+ label = "slv-spdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SPDM_WRAPPER>;
+ };
+
+ slv_qdss_cfg:slv-qdss-cfg {
+ cell-id = <MSM_BUS_SLAVE_QDSS_CFG>;
+ label = "slv-qdss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_CFG>;
+ };
+
+ slv_cnoc_mnoc_cfg:slv-cnoc-mnoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_MNOC_CFG>;
+ label = "slv-cnoc-mnoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,connections = <&mas_cnoc_mnoc_cfg>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_MNOC_CFG>;
+ };
+
+ slv_snoc_cfg:slv-snoc-cfg {
+ cell-id = <MSM_BUS_SLAVE_SNOC_CFG>;
+ label = "slv-snoc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CFG>;
+ };
+
+ slv_qm_cfg:slv-qm-cfg {
+ cell-id = <MSM_BUS_SLAVE_QM_CFG>;
+ label = "slv-qm-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QM_CFG>;
+ };
+
+ slv_clk_ctl:slv-clk-ctl {
+ cell-id = <MSM_BUS_SLAVE_CLK_CTL>;
+ label = "slv-clk-ctl";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CLK_CTL>;
+ };
+
+ slv_mss_cfg:slv-mss-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_MSS>;
+ label = "slv-mss-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_MSS>;
+ };
+
+ slv_tlmm_south:slv-tlmm-south {
+ cell-id = <MSM_BUS_SLAVE_TLMM_SOUTH>;
+ label = "slv-tlmm-south";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TLMM_SOUTH>;
+ };
+
+ slv_ufs_cfg:slv-ufs-cfg {
+ cell-id = <MSM_BUS_SLAVE_UFS_CFG>;
+ label = "slv-ufs-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_UFS_CFG>;
+ };
+
+ slv_a2noc_cfg:slv-a2noc-cfg {
+ cell-id = <MSM_BUS_SLAVE_A2NOC_CFG>;
+ label = "slv-a2noc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_A2NOC_CFG>;
+ };
+
+ slv_a2noc_smmu_cfg:slv-a2noc-smmu-cfg {
+ cell-id = <MSM_BUS_SLAVE_A2NOC_SMMU_CFG>;
+ label = "slv-a2noc-smmu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_A2NOC_SMMU_CFG>;
+ };
+
+ slv_gpuss_cfg:slv-gpuss-cfg {
+ cell-id = <MSM_BUS_SLAVE_GRAPHICS_3D_CFG>;
+ label = "slv-gpuss-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GFX3D_CFG>;
+ };
+
+ slv_ahb2phy:slv-ahb2phy {
+ cell-id = <MSM_BUS_SLAVE_PCIE20_AHB2PHY>;
+ label = "slv-ahb2phy";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PCIE20_AHB2PHY>;
+ };
+
+ slv_blsp_1:slv-blsp-1 {
+ cell-id = <MSM_BUS_SLAVE_BLSP_1>;
+ label = "slv-blsp-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_1>;
+ };
+
+ slv_sdcc_1:slv-sdcc-1 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_1>;
+ label = "slv-sdcc-1";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_1>;
+ };
+
+ slv_sdcc_2:slv-sdcc-2 {
+ cell-id = <MSM_BUS_SLAVE_SDCC_2>;
+ label = "slv-sdcc-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SDCC_2>;
+ };
+
+ slv_tlmm_center:slv-tlmm-center {
+ cell-id = <MSM_BUS_SLAVE_TLMM_CENTER>;
+ label = "slv-tlmm-center";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_TLMM_CENTER>;
+ };
+
+ slv_blsp_2:slv-blsp-2 {
+ cell-id = <MSM_BUS_SLAVE_BLSP_2>;
+ label = "slv-blsp-2";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_BLSP_2>;
+ };
+
+ slv_pdm:slv-pdm {
+ cell-id = <MSM_BUS_SLAVE_PDM>;
+ label = "slv-pdm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PDM>;
+ };
+
+ slv_cnoc_mnoc_mmss_cfg:slv-cnoc-mnoc-mmss-cfg {
+ cell-id = <MSM_BUS_SLAVE_CNOC_MNOC_MMSS_CFG>;
+ label = "slv-cnoc-mnoc-mmss-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,connections = <&mas_cnoc_mnoc_mmss_cfg>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CNOC_MNOC_MMSS_CFG>;
+ };
+
+ slv_usb_hs:slv-usb-hs {
+ cell-id = <MSM_BUS_SLAVE_USB_HS>;
+ label = "slv-usb-hs";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_USB_HS>;
+ };
+
+ slv_usb3_0:slv-usb3-0 {
+ cell-id = <MSM_BUS_SLAVE_USB3>;
+ label = "slv-usb3-0";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_USB3_0>;
+ };
+
+ slv_srvc_cnoc:slv-srvc-cnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_CNOC>;
+ label = "slv-srvc-cnoc";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_CNOC>;
+ };
+
+
+ slv_gnoc_bimc:slv-gnoc-bimc {
+ cell-id = <MSM_BUS_SLAVE_GNOC_BIMC>;
+ label = "slv-gnoc-bimc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_gnoc>;
+ qcom,connections = <&mas_gnoc_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GNOC_BIMC>;
+ };
+
+ slv_gnoc_snoc:slv-gnoc-snoc {
+ cell-id = <MSM_BUS_SLAVE_GNOC_SNOC>;
+ label = "slv-gnoc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_gnoc>;
+ qcom,connections = <&mas_gnoc_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_GNOC_SNOC>;
+ };
+
+ mas_gnoc_snoc: mas-gnoc-snoc {
+ cell-id = <MSM_BUS_MASTER_GNOC_SNOC>;
+ label = "mas-gnoc-snoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,connections = <&slv_pimem
+ &slv_ipa &slv_qdss_stm
+ &slv_lpass &slv_hmss
+ &slv_cdsp &slv_snoc_cnoc
+ &slv_wlan &slv_imem>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,mas-rpm-id = <ICBID_MASTER_GNOC_SNOC>;
+ };
+
+ slv_camera_cfg:slv-camera-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_CFG>;
+ label = "slv-camera-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_CFG>;
+ };
+
+ slv_camera_throttle_cfg:slv-camera-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_CAMERA_THROTTLE_CFG>;
+ label = "slv-camera-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CAMERA_THROTTLE_CFG>;
+ };
+
+ slv_misc_cfg:slv-misc-cfg {
+ cell-id = <MSM_BUS_SLAVE_MISC_CFG>;
+ label = "slv-misc-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MISC_CFG>;
+ };
+
+ slv_venus_throttle_cfg:slv-venus-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_THROTTLE_CFG>;
+ label = "slv-venus-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_THROTTLE_CFG>;
+ };
+
+ slv_venus_cfg:slv-venus-cfg {
+ cell-id = <MSM_BUS_SLAVE_VENUS_CFG>;
+ label = "slv-venus-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_VENUS_CFG>;
+ };
+
+ slv_mmss_clk_xpu_cfg:slv-mmss-clk-xpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_MMSS_CLK_XPU_CFG>;
+ label = "slv-mmss-clk-xpu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MMSS_CLK_XPU_CFG>;
+ };
+
+ slv_mmss_clk_cfg:slv-mmss-clk-cfg {
+ cell-id = <MSM_BUS_SLAVE_MMSS_CLK_CFG>;
+ label = "slv-mmss-clk-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MMSS_CLK_CFG>;
+ };
+
+ slv_mnoc_mpu_cfg:slv-mnoc-mpu-cfg {
+ cell-id = <MSM_BUS_SLAVE_MNOC_MPU_CFG>;
+ label = "slv-mnoc-mpu-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MNOC_MPU_CFG>;
+ };
+
+ slv_display_cfg:slv-display-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_CFG>;
+ label = "slv-display-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_CFG>;
+ };
+
+ slv_csi_phy_cfg:slv-csi-phy-cfg {
+ cell-id = <MSM_BUS_SLAVE_CSI_PHY_CFG>;
+ label = "slv-csi-phy-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CSI_PHY_CFG>;
+ };
+
+ slv_display_throttle_cfg:slv-display-throttle-cfg {
+ cell-id = <MSM_BUS_SLAVE_DISPLAY_THROTTLE_CFG>;
+ label = "slv-display-throttle-cfg";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_DISPLAY_THROTTLE_CFG>;
+ };
+
+ slv_smmu_cfg:slv-smmu-cfg {
+ cell-id = <MSM_BUS_SLAVE_MMSS_SMMU_CFG>;
+ label = "slv-smmu-cfg";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MMSS_SMMU_CFG>;
+ };
+
+ slv_mnoc_bimc:slv-mnoc-bimc {
+ cell-id = <MSM_BUS_MNOC_BIMC_SLV>;
+ label = "slv-mnoc-bimc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <2>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc>;
+ qcom,connections = <&mas_mnoc_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_MNOC_BIMC>;
+ qcom,enable-only-clk;
+ clock-names = "node_clk";
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>;
+ };
+
+ slv_srvc_mnoc:slv-srvc-mnoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_MNOC>;
+ label = "slv-srvc-mnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_mnoc_ahb>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_MNOC>;
+ };
+
+ slv_hmss:slv-hmss {
+ cell-id = <MSM_BUS_SLAVE_APPSS>;
+ label = "slv-hmss";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_APPSS>;
+ };
+
+ slv_lpass:slv-lpass {
+ cell-id = <MSM_BUS_SLAVE_LPASS>;
+ label = "slv-lpass";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_LPASS>;
+ };
+
+ slv_wlan:slv-wlan {
+ cell-id = <MSM_BUS_SLAVE_WLAN>;
+ label = "slv-wlan";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_WLAN>;
+ };
+
+ slv_cdsp:slv-cdsp {
+ cell-id = <MSM_BUS_SLAVE_CDSP>;
+ label = "slv-cdsp";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_CDSP>;
+ };
+
+ slv_ipa:slv-ipa {
+ cell-id = <MSM_BUS_SLAVE_IPA_CFG>;
+ label = "slv-ipa";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,ap-owned;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IPA_CFG>;
+ };
+
+ slv_snoc_bimc:slv-snoc-bimc {
+ cell-id = <MSM_BUS_SNOC_BIMC_SLV>;
+ label = "slv-snoc-bimc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,connections = <&mas_snoc_bimc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_BIMC>;
+ };
+
+ slv_snoc_cnoc:slv-snoc-cnoc {
+ cell-id = <MSM_BUS_SNOC_CNOC_SLV>;
+ label = "slv-snoc-cnoc";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,connections = <&mas_snoc_cnoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SNOC_CNOC>;
+ };
+
+ slv_imem:slv-imem {
+ cell-id = <MSM_BUS_SLAVE_OCIMEM>;
+ label = "slv-imem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_IMEM>;
+ };
+
+ slv_pimem:slv-pimem {
+ cell-id = <MSM_BUS_SLAVE_PIMEM>;
+ label = "slv-pimem";
+ qcom,buswidth = <8>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_PIMEM>;
+ };
+
+ slv_qdss_stm:slv-qdss-stm {
+ cell-id = <MSM_BUS_SLAVE_QDSS_STM>;
+ label = "slv-qdss-stm";
+ qcom,buswidth = <4>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_QDSS_STM>;
+ };
+
+ slv_srvc_snoc:slv-srvc-snoc {
+ cell-id = <MSM_BUS_SLAVE_SERVICE_SNOC>;
+ label = "slv-srvc-snoc";
+ qcom,buswidth = <16>;
+ qcom,agg-ports = <1>;
+ qcom,bus-dev = <&fab_snoc>;
+ qcom,slv-rpm-id = <ICBID_SLAVE_SERVICE_SNOC>;
+ };
+ };
+
+ devfreq_spdm_cpu {
+ compatible = "qcom,devfreq_spdm";
+ qcom,msm-bus,name = "devfreq_spdm";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 512 0 0>,
+ <1 512 0 0>;
+ qcom,msm-bus,active-only;
+ qcom,spdm-client = <0>;
+
+ qcom,bw-upstep = <450>;
+ qcom,bw-dwnstep = <8200>;
+ qcom,max-vote = <8200>;
+ qcom,up-step-multp = <2>;
+ qcom,spdm-interval = <30>;
+
+ qcom,ports = <24>;
+ qcom,alpha-up = <8>;
+ qcom,alpha-down = <15>;
+ qcom,bucket-size = <8>;
+
+ /*max pl1 freq, max pl2 freq*/
+ qcom,pl-freqs = <210000 610000>;
+
+ /* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
+ qcom,reject-rate = <5000 5000 5000 5000 5000 5000>;
+ /* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
+ qcom,response-time-us = <5000 5000 5000 5000 5000 5000>;
+
+ /* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
+ qcom,cci-response-time-us = <10000 10000 10000
+ 10000 10000 10000>;
+ qcom,max-cci-freq = <1036800>;
+ };
+
+ devfreq_spdm_gov {
+ compatible = "qcom,gov_spdm_hyp";
+ interrupt-names = "spdm-irq";
+ interrupts = <0 192 IRQ_TYPE_EDGE_RISING>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-camera-sensor-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-camera-sensor-cdp.dtsi
new file mode 100755
index 0000000..72b71da
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-camera-sensor-cdp.dtsi
@@ -0,0 +1,391 @@
+&soc {
+ led_flash0: qcom,camera-flash@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>;
+ qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>;
+ qcom,switch-source = <&pm660l_switch0>;
+ status = "ok";
+ };
+
+ led_flash1: qcom,camera-flash@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera-flash";
+ qcom,flash-source = <&pm660l_flash2>;
+ qcom,torch-source = <&pm660l_torch2>;
+ qcom,switch-source = <&pm660l_switch1>;
+ status = "ok";
+ };
+
+ cam_actuator_regulator: cam_actuator_fixed_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "cam_actuator_regulator";
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+ enable-active-high;
+ gpio = <&tlmm 50 0>;
+ vin-supply = <&pm660l_bob>;
+ };
+};
+
+&cci {
+ actuator0: qcom,actuator@0 {
+ cell-index = <0>;
+ reg = <0x0>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <0>;
+ cam_vaf-supply = <&cam_actuator_regulator>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <3600000>;
+ qcom,cam-vreg-max-voltage = <3600000>;
+ qcom,cam-vreg-op-mode = <0>;
+ };
+
+ actuator1: qcom,actuator@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <1>;
+ cam_vaf-supply = <&cam_actuator_regulator>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <3600000>;
+ qcom,cam-vreg-max-voltage = <3600000>;
+ qcom,cam-vreg-op-mode = <0>;
+ };
+
+ actuator2: qcom,actuator@2 {
+ cell-index = <2>;
+ reg = <0x2>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <1>;
+ cam_vaf-supply = <&cam_actuator_regulator>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <3600000>;
+ qcom,cam-vreg-max-voltage = <3600000>;
+ qcom,cam-vreg-op-mode = <0>;
+ };
+
+ ois0: qcom,ois@0 {
+ cell-index = <0>;
+ reg = <0x0>;
+ compatible = "qcom,ois";
+ qcom,cci-master = <0>;
+ cam_vaf-supply = <&cam_actuator_regulator>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <3600000>;
+ qcom,cam-vreg-max-voltage = <3600000>;
+ qcom,cam-vreg-op-mode = <0>;
+ status = "disabled";
+ };
+
+ tof0: qcom,tof@29{
+ cell-index = <0>;
+ reg = <0x29>;
+ compatible = "st,stmvl53l0";
+ qcom,cci-master = <0>;
+ cam_laser-supply = <&cam_actuator_regulator>;
+ qcom,cam-vreg-name = "cam_laser";
+ qcom,cam-vreg-min-voltage = <3600000>;
+ qcom,cam-vreg-max-voltage = <3600000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_tof_active>;
+ pinctrl-1 = <&cam_tof_suspend>;
+ stm,irq-gpio = <&tlmm 45 0x2008>;
+ gpios = <&tlmm 42 0>;
+ qcom,gpio-req-tbl-num = <0>;
+ qcom,gpio-req-tbl-flags = <0>;
+ qcom,gpio-req-tbl-label = "RNG_EN";
+ };
+
+ eeprom0: qcom,eeprom@0 {
+ cell-index = <0>;
+ reg = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&pm660l_bob>;
+ cam_vdig-supply = <&pm660_s5>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
+ qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
+ qcom,cam-vreg-op-mode = <105000 80000 105000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear_active
+ &cam_sensor_eldo4_default
+ &cam_actuator_vaf_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear_suspend
+ &cam_actuator_vaf_suspend>;
+ gpios = <&tlmm 32 0>,
+ <&tlmm 46 0>,
+ <&pm660l_gpios 4 0>,
+ <&tlmm 51 0>,
+ <&tlmm 50 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vdig = <2>;
+ qcom,gpio-vana = <3>;
+ qcom,gpio-vaf = <4>;
+ qcom,gpio-req-tbl-num = <0 1 2 3 4>;
+ qcom,gpio-req-tbl-flags = <1 0 0 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0",
+ "CAM_VDIG",
+ "CAM_VANA",
+ "CAM_VAF";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK0_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ eeprom1: qcom,eeprom@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&pm660l_bob>;
+ cam_vdig-supply = <&pm660_s5>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
+ qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
+ qcom,cam-vreg-op-mode = <105000 80000 105000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_rear2_active
+ &cam_sensor_eldo3_default>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_rear2_suspend>;
+ gpios = <&tlmm 34 0>,
+ <&tlmm 48 0>,
+ <&pm660l_gpios 3 0>,
+ <&tlmm 51 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vdig = <2>;
+ qcom,gpio-vana = <3>;
+ qcom,gpio-req-tbl-num = <0 1 2 3>;
+ qcom,gpio-req-tbl-flags = <1 0 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK",
+ "CAM_RESET",
+ "CAM_VDIG",
+ "CAM_VANA";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK2_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ eeprom2: qcom,eeprom@2 {
+ cell-index = <2>;
+ reg = <0x2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&pm660l_bob>;
+ cam_vdig-supply = <&pm660_s5>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
+ qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
+ qcom,cam-vreg-op-mode = <105000 80000 105000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_front_active
+ &cam_actuator_vaf_active>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_front_suspend
+ &cam_actuator_vaf_suspend>;
+ gpios = <&tlmm 33 0>,
+ <&tlmm 47 0>,
+ <&pm660_gpios 3 0>,
+ <&tlmm 44 0>,
+ <&tlmm 50 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vdig = <2>;
+ qcom,gpio-vana = <3>;
+ qcom,gpio-vaf = <4>;
+ qcom,gpio-req-tbl-num = <0 1 2 3 4>;
+ qcom,gpio-req-tbl-flags = <1 0 0 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_VDIG",
+ "CAM_VANA",
+ "CAM_VAF";
+ qcom,sensor-position = <1>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK1_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera";
+ reg = <0x0>;
+ qcom,csiphy-sd-index = <0>;
+ qcom,csid-sd-index = <0>;
+ qcom,mount-angle = <90>;
+ qcom,led-flash-src = <&led_flash0>;
+ qcom,actuator-src = <&actuator0>;
+ qcom,ois-src = <&ois0>;
+ qcom,eeprom-src = <&eeprom0>;
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&pm660l_bob>;
+ cam_vdig-supply = <&pm660_s5>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
+ qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
+ qcom,cam-vreg-op-mode = <105000 80000 105000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear_active
+ &cam_sensor_eldo4_default>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear_suspend>;
+ gpios = <&tlmm 32 0>,
+ <&tlmm 46 0>,
+ <&pm660l_gpios 4 0>,
+ <&tlmm 51 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vdig = <2>;
+ qcom,gpio-vana = <3>;
+ qcom,gpio-req-tbl-num = <0 1 2 3>;
+ qcom,gpio-req-tbl-flags = <1 0 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0",
+ "CAM_VDIG",
+ "CAM_VANA";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK0_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera";
+ reg = <0x1>;
+ qcom,csiphy-sd-index = <1>;
+ qcom,csid-sd-index = <2>;
+ qcom,mount-angle = <90>;
+ qcom,led-flash-src = <&led_flash0>;
+ qcom,actuator-src = <&actuator1>;
+ qcom,eeprom-src = <&eeprom1>;
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&pm660l_bob>;
+ cam_vdig-supply = <&pm660_s5>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
+ qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
+ qcom,cam-vreg-op-mode = <105000 80000 105000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_rear2_active
+ &cam_sensor_eldo3_default>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_rear2_suspend>;
+ gpios = <&tlmm 34 0>,
+ <&tlmm 48 0>,
+ <&pm660l_gpios 3 0>,
+ <&tlmm 51 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vdig = <2>;
+ qcom,gpio-vana = <3>;
+ qcom,gpio-req-tbl-num = <0 1 2 3>;
+ qcom,gpio-req-tbl-flags = <1 0 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK",
+ "CAM_RESET",
+ "CAM_VDIG",
+ "CAM_VANA";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK2_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@2 {
+ cell-index = <2>;
+ compatible = "qcom,camera";
+ reg = <0x02>;
+ qcom,csiphy-sd-index = <2>;
+ qcom,csid-sd-index = <2>;
+ qcom,mount-angle = <90>;
+ qcom,actuator-src = <&actuator2>;
+ qcom,eeprom-src = <&eeprom2>;
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&pm660l_bob>;
+ cam_vdig-supply = <&pm660_s5>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>;
+ qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>;
+ qcom,cam-vreg-op-mode = <105000 80000 105000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_front_active
+ &cam_sensor_eldo3_default>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_front_suspend>;
+ gpios = <&tlmm 33 0>,
+ <&tlmm 47 0>,
+ <&pm660l_gpios 3 0>,
+ <&tlmm 51 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vdig = <2>;
+ qcom,gpio-vana = <3>;
+ qcom,gpio-req-tbl-num = <0 1 2 3>;
+ qcom,gpio-req-tbl-flags = <1 0 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_VDIG",
+ "CAM_VANA";
+ qcom,sensor-position = <1>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK1_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+};
+
+&pm660l_gpios {
+ cam_sensor_eldo3 {
+ cam_sensor_eldo3_default: cam_sensor_eldo3_default {
+ pins = "gpio3";
+ function = "normal";
+ output-enable;
+ bias-disable;
+ };
+ };
+ cam_sensor_eldo4 {
+ cam_sensor_eldo4_default: cam_sensor_eldo4_default {
+ pins = "gpio4";
+ function = "normal";
+ output-enable;
+ bias-disable;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-camera-sensor-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-camera-sensor-mtp.dtsi
new file mode 100755
index 0000000..4902dcd
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-camera-sensor-mtp.dtsi
@@ -0,0 +1,426 @@
+&soc {
+ led_flash0: qcom,camera-flash@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>;
+ qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>;
+ qcom,switch-source = <&pm660l_switch0>;
+ status = "ok";
+ };
+
+ led_flash1: qcom,camera-flash@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera-flash";
+ qcom,flash-source = <&pm660l_flash2>;
+ qcom,torch-source = <&pm660l_torch2>;
+ qcom,switch-source = <&pm660l_switch1>;
+ status = "ok";
+ };
+
+ cam_avdd_gpio_regulator: cam_avdd_fixed_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "cam_avdd_gpio_regulator";
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+ enable-active-high;
+ gpio = <&tlmm 51 0>;
+ vin-supply = <&pm660l_bob>;
+ };
+
+ cam_actuator_regulator: cam_actuator_fixed_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "cam_actuator_regulator";
+ regulator-min-microvolt = <3600000>;
+ regulator-max-microvolt = <3600000>;
+ enable-active-high;
+ gpio = <&tlmm 50 0>;
+ vin-supply = <&pm660l_bob>;
+ };
+
+ cam_dvdd_gpio_regulator: cam_dvdd_fixed_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "cam_dvdd_gpio_regulator";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ enable-active-high;
+ gpio = <&pm660l_gpios 3 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam_sensor_eldo3_default>;
+ vin-supply = <&pm660_s5>;
+ };
+
+ cam_rear_dvdd_gpio_regulator: cam_rear_dvdd_fixed_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "cam_rear_dvdd_gpio_regulator";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ enable-active-high;
+ gpio = <&pm660l_gpios 4 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam_sensor_eldo4_default>;
+ vin-supply = <&pm660_s5>;
+ };
+};
+
+&cci {
+ actuator0: qcom,actuator@0 {
+ cell-index = <0>;
+ reg = <0x0>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <0>;
+ cam_vaf-supply = <&cam_actuator_regulator>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <3600000>;
+ qcom,cam-vreg-max-voltage = <3600000>;
+ qcom,cam-vreg-op-mode = <0>;
+ };
+
+ actuator1: qcom,actuator@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <1>;
+ cam_vaf-supply = <&cam_actuator_regulator>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <3600000>;
+ qcom,cam-vreg-max-voltage = <3600000>;
+ qcom,cam-vreg-op-mode = <0>;
+ };
+
+ actuator2: qcom,actuator@2 {
+ cell-index = <2>;
+ reg = <0x2>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <1>;
+ cam_vaf-supply = <&cam_actuator_regulator>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <3600000>;
+ qcom,cam-vreg-max-voltage = <3600000>;
+ qcom,cam-vreg-op-mode = <0>;
+ };
+
+ ois0: qcom,ois@0 {
+ cell-index = <0>;
+ reg = <0x0>;
+ compatible = "qcom,ois";
+ qcom,cci-master = <0>;
+ cam_vaf-supply = <&cam_actuator_regulator>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <3600000>;
+ qcom,cam-vreg-max-voltage = <3600000>;
+ qcom,cam-vreg-op-mode = <0>;
+ status = "disabled";
+ };
+
+ tof0: qcom,tof@29{
+ cell-index = <0>;
+ reg = <0x29>;
+ compatible = "st,stmvl53l0";
+ qcom,cci-master = <0>;
+ cam_laser-supply = <&cam_actuator_regulator>;
+ qcom,cam-vreg-name = "cam_laser";
+ qcom,cam-vreg-min-voltage = <3600000>;
+ qcom,cam-vreg-max-voltage = <3600000>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_tof_active>;
+ pinctrl-1 = <&cam_tof_suspend>;
+ stm,irq-gpio = <&tlmm 45 0x2008>;
+ gpios = <&tlmm 42 0>;
+ qcom,gpio-req-tbl-num = <0>;
+ qcom,gpio-req-tbl-flags = <0>;
+ qcom,gpio-req-tbl-label = "RNG_EN";
+ };
+
+ eeprom0: qcom,eeprom@0 {
+ cell-index = <0>;
+ reg = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&cam_avdd_gpio_regulator>;
+ cam_vdig-supply = <&cam_rear_dvdd_gpio_regulator>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 0 0>;
+ qcom,cam-vreg-max-voltage = <1950000 0 0>;
+ qcom,cam-vreg-op-mode = <105000 0 0>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear_active
+ &cam_actuator_vaf_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear_suspend
+ &cam_actuator_vaf_suspend>;
+ gpios = <&tlmm 32 0>,
+ <&tlmm 46 0>,
+ <&tlmm 50 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vaf = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0",
+ "CAM_VAF";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK0_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ eeprom1: qcom,eeprom@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&cam_avdd_gpio_regulator>;
+ cam_vdig-supply = <&cam_dvdd_gpio_regulator>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 0 0>;
+ qcom,cam-vreg-max-voltage = <1950000 0 0>;
+ qcom,cam-vreg-op-mode = <105000 0 0>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_rear2_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_rear2_suspend>;
+ gpios = <&tlmm 34 0>,
+ <&tlmm 48 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-req-tbl-num = <0 1>;
+ qcom,gpio-req-tbl-flags = <1 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK",
+ "CAM_RESET";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK2_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ eeprom2: qcom,eeprom@2 {
+ cell-index = <2>;
+ reg = <0x2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&pm660l_bob>;
+ cam_vdig-supply = <&cam_dvdd_gpio_regulator>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 3300000 0>;
+ qcom,cam-vreg-max-voltage = <1950000 3600000 0>;
+ qcom,cam-vreg-op-mode = <105000 80000 0>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_front_active
+ &cam_actuator_vaf_active>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_front_suspend
+ &cam_actuator_vaf_suspend>;
+ gpios = <&tlmm 33 0>,
+ <&tlmm 47 0>,
+ <&tlmm 44 0>,
+ <&tlmm 50 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vana = <2>;
+ qcom,gpio-vaf = <3>;
+ qcom,gpio-req-tbl-num = <0 1 2 3>;
+ qcom,gpio-req-tbl-flags = <1 0 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_VANA",
+ "CAM_VAF";
+ qcom,sensor-position = <1>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK1_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera";
+ reg = <0x0>;
+ qcom,csiphy-sd-index = <0>;
+ qcom,csid-sd-index = <0>;
+ qcom,mount-angle = <90>;
+ qcom,led-flash-src = <&led_flash0>;
+ qcom,actuator-src = <&actuator0>;
+ qcom,ois-src = <&ois0>;
+ qcom,eeprom-src = <&eeprom0>;
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&cam_avdd_gpio_regulator>;
+ cam_vdig-supply = <&cam_rear_dvdd_gpio_regulator>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 0 0>;
+ qcom,cam-vreg-max-voltage = <1950000 0 0>;
+ qcom,cam-vreg-op-mode = <105000 0 0>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear_suspend>;
+ gpios = <&tlmm 32 0>,
+ <&tlmm 46 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-req-tbl-num = <0 1>;
+ qcom,gpio-req-tbl-flags = <1 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK0",
+ "CAM_RESET0";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK0_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera";
+ reg = <0x1>;
+ qcom,csiphy-sd-index = <1>;
+ qcom,csid-sd-index = <2>;
+ qcom,mount-angle = <90>;
+ qcom,led-flash-src = <&led_flash0>;
+ qcom,actuator-src = <&actuator1>;
+ qcom,eeprom-src = <&eeprom1>;
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&cam_avdd_gpio_regulator>;
+ cam_vdig-supply = <&cam_dvdd_gpio_regulator>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 0 0>;
+ qcom,cam-vreg-max-voltage = <1950000 0 0>;
+ qcom,cam-vreg-op-mode = <105000 0 0>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_rear2_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_rear2_suspend>;
+ gpios = <&tlmm 34 0>,
+ <&tlmm 48 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-req-tbl-num = <0 1>;
+ qcom,gpio-req-tbl-flags = <1 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK",
+ "CAM_RESET";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK2_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@2 {
+ cell-index = <2>;
+ compatible = "qcom,camera";
+ reg = <0x02>;
+ qcom,csiphy-sd-index = <2>;
+ qcom,csid-sd-index = <2>;
+ qcom,mount-angle = <90>;
+ qcom,actuator-src = <&actuator2>;
+ qcom,eeprom-src = <&eeprom2>;
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&cam_avdd_gpio_regulator>;
+ cam_vdig-supply = <&cam_dvdd_gpio_regulator>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 0 0>;
+ qcom,cam-vreg-max-voltage = <1950000 0 0>;
+ qcom,cam-vreg-op-mode = <105000 0 0>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_front_active>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_front_suspend>;
+ gpios = <&tlmm 33 0>,
+ <&tlmm 47 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-req-tbl-num = <0 1>;
+ qcom,gpio-req-tbl-flags = <1 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2";
+ qcom,sensor-position = <1>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK1_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@3 {
+ cell-index = <3>;
+ compatible = "qcom,camera";
+ reg = <0x03>;
+ qcom,csiphy-sd-index = <1>;
+ qcom,csid-sd-index = <1>;
+ qcom,mount-angle = <90>;
+ qcom,led-flash-src = <&led_flash1>;
+ qcom,actuator-src = <&actuator2>;
+ qcom,eeprom-src = <&eeprom2>;
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&cam_avdd_gpio_regulator>;
+ cam_vdig-supply = <&cam_dvdd_gpio_regulator>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 0 0>;
+ qcom,cam-vreg-max-voltage = <1950000 0 0>;
+ qcom,cam-vreg-op-mode = <105000 0 0>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk3_active
+ &cam_sensor_front_iris_active>;
+ pinctrl-1 = <&cam_sensor_mclk3_suspend
+ &cam_sensor_front_iris_suspend>;
+ gpios = <&tlmm 35 0>,
+ <&tlmm 52 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-req-tbl-num = <0 1>;
+ qcom,gpio-req-tbl-flags = <1 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK3",
+ "CAM_RESET3";
+ qcom,sensor-position = <1>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ clocks = <&clock_mmss MCLK3_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK3_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+};
+
+&pm660l_gpios {
+ cam_sensor_eldo3 {
+ cam_sensor_eldo3_default: cam_sensor_eldo3_default {
+ pins = "gpio3";
+ function = "normal";
+ output-high;
+ bias-disable;
+ };
+ };
+ cam_sensor_eldo4 {
+ cam_sensor_eldo4_default: cam_sensor_eldo4_default {
+ pins = "gpio4";
+ function = "normal";
+ output-low;
+ bias-disable;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-camera-sensor-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-camera-sensor-qrd.dtsi
new file mode 100755
index 0000000..5c79eaf
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-camera-sensor-qrd.dtsi
@@ -0,0 +1,415 @@
+&soc {
+ led_flash0: qcom,camera-flash@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera-flash";
+ qcom,flash-source = <&pm660l_flash0 &pm660l_flash1>;
+ qcom,torch-source = <&pm660l_torch0 &pm660l_torch1>;
+ qcom,switch-source = <&pm660l_switch0>;
+ status = "ok";
+ };
+
+ cam_avdd_gpio_regulator:cam_avdd_fixed_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "cam_vadd_gpio_regulator";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ enable-active-high;
+ gpio = <&tlmm 51 0>;
+ vin-supply = <&pm660l_bob>;
+ };
+
+ cam_vaf_gpio_regulator:cam_vaf_fixed_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "cam_vaf_gpio_regulator";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ enable-active-high;
+ gpio = <&tlmm 50 0>;
+ vin-supply = <&pm660l_bob>;
+ };
+
+ cam_rear_dvdd_gpio_regulator: cam_rear_dvdd_fixed_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "cam_rear_dvdd_gpio_regulator";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ enable-active-high;
+ gpio = <&pm660l_gpios 4 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cam_sensor_eldo4_default>;
+ vin-supply = <&pm660_s5>;
+ };
+};
+
+&tlmm {
+ cam_sensor_rear_active: cam_sensor_rear_active {
+ /* RESET */
+ mux {
+ pins = "gpio46";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio46";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear_suspend: cam_sensor_rear_suspend {
+ /* RESET */
+ mux {
+ pins = "gpio46";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio46";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear2_active: cam_sensor_rear2_active {
+ /* RESET */
+ mux {
+ pins = "gpio48";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio48";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear2_suspend: cam_sensor_rear2_suspend {
+ /* RESET */
+ mux {
+ pins = "gpio48";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio48";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_front_active: cam_sensor_front_active {
+ /* RESET */
+ mux {
+ pins = "gpio47";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio47";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_front_suspend: cam_sensor_front_suspend {
+ /* RESET */
+ mux {
+ pins = "gpio47";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio47";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+};
+
+&cci {
+ actuator0: qcom,actuator@0 {
+ cell-index = <0>;
+ reg = <0x0>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <0>;
+ cam_vaf-supply = <&cam_vaf_gpio_regulator>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2800000>;
+ qcom,cam-vreg-max-voltage = <2800000>;
+ qcom,cam-vreg-op-mode = <0>;
+ };
+
+ actuator1: qcom,actuator@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ compatible = "qcom,actuator";
+ qcom,cci-master = <1>;
+ cam_vaf-supply = <&cam_vaf_gpio_regulator>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2800000>;
+ qcom,cam-vreg-max-voltage = <2800000>;
+ qcom,cam-vreg-op-mode = <0>;
+ };
+
+ ois0: qcom,ois@0 {
+ cell-index = <0>;
+ reg = <0x0>;
+ compatible = "qcom,ois";
+ qcom,cci-master = <0>;
+ cam_vaf-supply = <&cam_vaf_gpio_regulator>;
+ qcom,cam-vreg-name = "cam_vaf";
+ qcom,cam-vreg-min-voltage = <2800000>;
+ qcom,cam-vreg-max-voltage = <2800000>;
+ qcom,cam-vreg-op-mode = <0>;
+ status = "disabled";
+ };
+
+ eeprom0: qcom,eeprom@0 {
+ cell-index = <0>;
+ reg = <0>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&cam_avdd_gpio_regulator>;
+ cam_vdig-supply = <&cam_rear_dvdd_gpio_regulator>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 0 0>;
+ qcom,cam-vreg-max-voltage = <1950000 0 0>;
+ qcom,cam-vreg-op-mode = <105000 0 105000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear_suspend>;
+ gpios = <&tlmm 32 0>,
+ <&tlmm 46 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-req-tbl-num = <0 1>;
+ qcom,gpio-req-tbl-flags = <1 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET0";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK0_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ eeprom1: qcom,eeprom@1 {
+ cell-index = <1>;
+ reg = <0x1>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&cam_avdd_gpio_regulator>;
+ cam_vdig-supply = <&cam_rear_dvdd_gpio_regulator>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 0 0>;
+ qcom,cam-vreg-max-voltage = <1950000 0 0>;
+ qcom,cam-vreg-op-mode = <105000 0 0>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_rear2_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_rear2_suspend>;
+ gpios = <&tlmm 34 0>,
+ <&tlmm 48 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-req-tbl-num = <0 1>;
+ qcom,gpio-req-tbl-flags = <1 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK2_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ eeprom2: qcom,eeprom@2 {
+ cell-index = <2>;
+ reg = <0x2>;
+ compatible = "qcom,eeprom";
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&cam_avdd_gpio_regulator>;
+ cam_vdig-supply = <&pm660_s5>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 0 1352000>;
+ qcom,cam-vreg-max-voltage = <1950000 0 1352000>;
+ qcom,cam-vreg-op-mode = <105000 0 105000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_front_active
+ &cam_sensor_eldo3_default>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_front_suspend>;
+ gpios = <&tlmm 33 0>,
+ <&tlmm 47 0>,
+ <&pm660l_gpios 3 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vdig = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_VDIG";
+ qcom,sensor-position = <1>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK1_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@0 {
+ cell-index = <0>;
+ compatible = "qcom,camera";
+ reg = <0x0>;
+ qcom,csiphy-sd-index = <0>;
+ qcom,csid-sd-index = <0>;
+ qcom,mount-angle = <270>;
+ qcom,led-flash-src = <&led_flash0>;
+ qcom,actuator-src = <&actuator0>;
+ qcom,ois-src = <&ois0>;
+ qcom,eeprom-src = <&eeprom0>;
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&cam_avdd_gpio_regulator>;
+ cam_vdig-supply = <&cam_rear_dvdd_gpio_regulator>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 0 0>;
+ qcom,cam-vreg-max-voltage = <1950000 0 0>;
+ qcom,cam-vreg-op-mode = <105000 0 0>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk0_active
+ &cam_sensor_rear_active>;
+ pinctrl-1 = <&cam_sensor_mclk0_suspend
+ &cam_sensor_rear_suspend>;
+ gpios = <&tlmm 32 0>,
+ <&tlmm 46 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-req-tbl-num = <0 1>;
+ qcom,gpio-req-tbl-flags = <1 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET0";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <0>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK0_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK0_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@1 {
+ cell-index = <1>;
+ compatible = "qcom,camera";
+ reg = <0x1>;
+ qcom,csiphy-sd-index = <1>;
+ qcom,csid-sd-index = <1>;
+ qcom,mount-angle = <270>;
+ qcom,led-flash-src = <&led_flash0>;
+ qcom,actuator-src = <&actuator1>;
+ qcom,eeprom-src = <&eeprom1>;
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&cam_avdd_gpio_regulator>;
+ cam_vdig-supply = <&cam_rear_dvdd_gpio_regulator>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 0 0>;
+ qcom,cam-vreg-max-voltage = <1950000 0 0>;
+ qcom,cam-vreg-op-mode = <105000 0 0>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk2_active
+ &cam_sensor_rear2_active>;
+ pinctrl-1 = <&cam_sensor_mclk2_suspend
+ &cam_sensor_rear2_suspend>;
+ gpios = <&tlmm 34 0>,
+ <&tlmm 48 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-req-tbl-num = <0 1>;
+ qcom,gpio-req-tbl-flags = <1 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK1",
+ "CAM_RESET1";
+ qcom,sensor-position = <0>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK2_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK2_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+
+ qcom,camera@2 {
+ cell-index = <2>;
+ compatible = "qcom,camera";
+ reg = <0x02>;
+ qcom,csiphy-sd-index = <2>;
+ qcom,csid-sd-index = <2>;
+ qcom,mount-angle = <270>;
+ qcom,eeprom-src = <&eeprom2>;
+ cam_vio-supply = <&pm660_l11>;
+ cam_vana-supply = <&cam_avdd_gpio_regulator>;
+ cam_vdig-supply = <&pm660_s5>;
+ qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig";
+ qcom,cam-vreg-min-voltage = <1780000 0 1350000>;
+ qcom,cam-vreg-max-voltage = <1950000 0 1350000>;
+ qcom,cam-vreg-op-mode = <105000 0 105000>;
+ qcom,gpio-no-mux = <0>;
+ pinctrl-names = "cam_default", "cam_suspend";
+ pinctrl-0 = <&cam_sensor_mclk1_active
+ &cam_sensor_front_active
+ &cam_sensor_eldo3_default>;
+ pinctrl-1 = <&cam_sensor_mclk1_suspend
+ &cam_sensor_front_suspend>;
+ gpios = <&tlmm 33 0>,
+ <&tlmm 47 0>,
+ <&pm660l_gpios 3 0>;
+ qcom,gpio-reset = <1>;
+ qcom,gpio-vdig = <2>;
+ qcom,gpio-req-tbl-num = <0 1 2>;
+ qcom,gpio-req-tbl-flags = <1 0 0>;
+ qcom,gpio-req-tbl-label = "CAMIF_MCLK2",
+ "CAM_RESET2",
+ "CAM_VDIG";
+ qcom,sensor-position = <1>;
+ qcom,sensor-mode = <0>;
+ qcom,cci-master = <1>;
+ status = "ok";
+ clocks = <&clock_mmss MCLK1_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_MCLK1_CLK>;
+ clock-names = "cam_src_clk", "cam_clk";
+ qcom,clock-rates = <24000000 0>;
+ };
+};
+
+&pm660l_gpios {
+ cam_sensor_eldo3 {
+ cam_sensor_eldo3_default: cam_sensor_eldo3_default {
+ pins = "gpio3";
+ function = "normal";
+ output-high;
+ bias-disable;
+ };
+ };
+ cam_sensor_eldo4 {
+ cam_sensor_eldo4_default: cam_sensor_eldo4_default {
+ pins = "gpio4";
+ function = "normal";
+ output-low;
+ bias-disable;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-camera.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-camera.dtsi
new file mode 100755
index 0000000..420102e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-camera.dtsi
@@ -0,0 +1,868 @@
+&soc {
+ qcom,msm-cam@ca00000 {
+ compatible = "qcom,msm-cam";
+ reg = <0xca00000 0x4000>;
+ reg-names = "msm-cam";
+ status = "ok";
+ bus-vectors = "suspend", "svs", "nominal", "turbo";
+ qcom,bus-votes = <0 150000000 320000000 320000000>;
+ qcom,gpu-limit = <700000000>;
+ };
+
+ qcom,csiphy@c824000 {
+ cell-index = <0>;
+ compatible = "qcom,csiphy-v3.5", "qcom,csiphy";
+ reg = <0xc824000 0x1000>,
+ <0xca00120 0x4>;
+ reg-names = "csiphy", "csiphy_clk_mux";
+ interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csiphy";
+ gdscr-supply = <&gdsc_camss_top>;
+ bimc_smmu-supply = <&gdsc_bimc_smmu>;
+ qcom,cam-vreg-name = "gdscr", "bimc_smmu";
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss CSI0_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CSI0_CLK>,
+ <&clock_mmss MMSS_CAMSS_CPHY_CSID0_CLK>,
+ <&clock_mmss CSI0PHYTIMER_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CSI0PHYTIMER_CLK>,
+ <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>,
+ <&clock_mmss CSIPHY_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CSIPHY0_CLK>,
+ <&clock_mmss MMSS_CSIPHY_AHB2CRIF_CLK>;
+ clock-names = "mmssnoc_axi", "mnoc_ahb",
+ "bmic_smmu_ahb", "bmic_smmu_axi",
+ "camss_ahb_clk", "camss_top_ahb_clk",
+ "csi_src_clk", "csi_clk", "cphy_csid_clk",
+ "csiphy_timer_src_clk", "csiphy_timer_clk",
+ "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk",
+ "csiphy_ahb2crif";
+ qcom,clock-rates = <0 0 0 0 0 0 310000000 0 0 269333333 0
+ 0 200000000 0 0>;
+ status = "ok";
+ };
+
+ qcom,csiphy@c825000 {
+ cell-index = <1>;
+ compatible = "qcom,csiphy-v3.5", "qcom,csiphy";
+ reg = <0xc825000 0x1000>,
+ <0xca00124 0x4>;
+ reg-names = "csiphy", "csiphy_clk_mux";
+ interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csiphy";
+ gdscr-supply = <&gdsc_camss_top>;
+ bimc_smmu-supply = <&gdsc_bimc_smmu>;
+ qcom,cam-vreg-name = "gdscr", "bimc_smmu";
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss CSI1_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CSI1_CLK>,
+ <&clock_mmss MMSS_CAMSS_CPHY_CSID1_CLK>,
+ <&clock_mmss CSI1PHYTIMER_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CSI1PHYTIMER_CLK>,
+ <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>,
+ <&clock_mmss CSIPHY_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CSIPHY1_CLK>,
+ <&clock_mmss MMSS_CSIPHY_AHB2CRIF_CLK>;
+ clock-names = "mmssnoc_axi", "mnoc_ahb",
+ "bmic_smmu_ahb", "bmic_smmu_axi",
+ "camss_ahb_clk", "camss_top_ahb_clk",
+ "csi_src_clk", "csi_clk", "cphy_csid_clk",
+ "csiphy_timer_src_clk", "csiphy_timer_clk",
+ "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk",
+ "csiphy_ahb2crif";
+ qcom,clock-rates = <0 0 0 0 0 0 310000000 0 0 269333333 0
+ 0 200000000 0 0>;
+ status = "ok";
+ };
+
+ qcom,csiphy@c826000 {
+ cell-index = <2>;
+ compatible = "qcom,csiphy-v3.5", "qcom,csiphy";
+ reg = <0xc826000 0x1000>,
+ <0xca00128 0x4>;
+ reg-names = "csiphy", "csiphy_clk_mux";
+ interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csiphy";
+ gdscr-supply = <&gdsc_camss_top>;
+ bimc_smmu-supply = <&gdsc_bimc_smmu>;
+ qcom,cam-vreg-name = "gdscr", "bimc_smmu";
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss CSI2_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CSI2_CLK>,
+ <&clock_mmss MMSS_CAMSS_CPHY_CSID2_CLK>,
+ <&clock_mmss CSI2PHYTIMER_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CSI2PHYTIMER_CLK>,
+ <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>,
+ <&clock_mmss CSIPHY_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CSIPHY2_CLK>,
+ <&clock_mmss MMSS_CSIPHY_AHB2CRIF_CLK>;
+ clock-names = "mmssnoc_axi", "mnoc_ahb",
+ "bmic_smmu_ahb", "bmic_smmu_axi",
+ "camss_ahb_clk", "camss_top_ahb_clk",
+ "csi_src_clk", "csi_clk", "cphy_csid_clk",
+ "csiphy_timer_src_clk", "csiphy_timer_clk",
+ "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk",
+ "csiphy_ahb2crif";
+ qcom,clock-rates = <0 0 0 0 0 0 310000000 0 0 269333333 0
+ 0 200000000 0 0>;
+ status = "ok";
+ };
+
+ qcom,csid@ca30000 {
+ cell-index = <0>;
+ compatible = "qcom,csid-v5.0", "qcom,csid";
+ reg = <0xca30000 0x400>;
+ reg-names = "csid";
+ interrupts = <0 296 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid";
+ qcom,csi-vdd-voltage = <1200000>;
+ qcom,mipi-csi-vdd-supply = <&pm660_l1>;
+ gdscr-supply = <&gdsc_camss_top>;
+ vdd_sec-supply = <&pm660l_l1>;
+ bimc_smmu-supply = <&gdsc_bimc_smmu>;
+ qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
+ qcom,cam-vreg-min-voltage = <925000 0 0>;
+ qcom,cam-vreg-max-voltage = <925000 0 0>;
+ qcom,cam-vreg-op-mode = <0 0 0>;
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>,
+ <&clock_mmss CSI0_CLK_SRC>,
+ <&clock_mmss CSIPHY_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CSI0_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI0_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI0RDI_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI0PIX_CLK>,
+ <&clock_mmss MMSS_CAMSS_CPHY_CSID0_CLK>;
+ clock-names = "mmssnoc_axi", "mnoc_ahb",
+ "bmic_smmu_ahb", "bmic_smmu_axi",
+ "camss_ahb_clk", "camss_top_ahb_clk",
+ "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
+ "csi_clk", "csi_ahb_clk", "csi_rdi_clk",
+ "csi_pix_clk", "cphy_csid_clk";
+ qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
+ 0 0 0 0 0>;
+ status = "ok";
+ };
+
+ qcom,csid@ca30400 {
+ cell-index = <1>;
+ compatible = "qcom,csid-v5.0", "qcom,csid";
+ reg = <0xca30400 0x400>;
+ reg-names = "csid";
+ interrupts = <0 297 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid";
+ qcom,csi-vdd-voltage = <1200000>;
+ qcom,mipi-csi-vdd-supply = <&pm660_l1>;
+ gdscr-supply = <&gdsc_camss_top>;
+ vdd_sec-supply = <&pm660l_l1>;
+ bimc_smmu-supply = <&gdsc_bimc_smmu>;
+ qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
+ qcom,cam-vreg-min-voltage = <925000 0 0>;
+ qcom,cam-vreg-max-voltage = <925000 0 0>;
+ qcom,cam-vreg-op-mode = <0 0 0>;
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>,
+ <&clock_mmss CSI1_CLK_SRC>,
+ <&clock_mmss CSIPHY_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CSI1_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI1_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI1RDI_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI1PIX_CLK>,
+ <&clock_mmss MMSS_CAMSS_CPHY_CSID1_CLK>;
+ clock-names = "mmssnoc_axi", "mnoc_ahb",
+ "bmic_smmu_ahb", "bmic_smmu_axi",
+ "camss_ahb_clk", "camss_top_ahb_clk",
+ "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
+ "csi_clk", "csi_ahb_clk", "csi_rdi_clk",
+ "csi_pix_clk", "cphy_csid_clk";
+ qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
+ 0 0 0 0 0>;
+ status = "ok";
+ };
+
+ qcom,csid@ca30800 {
+ cell-index = <2>;
+ compatible = "qcom,csid-v5.0", "qcom,csid";
+ reg = <0xca30800 0x400>;
+ reg-names = "csid";
+ interrupts = <0 298 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid";
+ qcom,csi-vdd-voltage = <1200000>;
+ qcom,mipi-csi-vdd-supply = <&pm660_l1>;
+ gdscr-supply = <&gdsc_camss_top>;
+ vdd_sec-supply = <&pm660l_l1>;
+ bimc_smmu-supply = <&gdsc_bimc_smmu>;
+ qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
+ qcom,cam-vreg-min-voltage = <925000 0 0>;
+ qcom,cam-vreg-max-voltage = <925000 0 0>;
+ qcom,cam-vreg-op-mode = <0 0 0>;
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>,
+ <&clock_mmss CSI2_CLK_SRC>,
+ <&clock_mmss CSIPHY_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CSI2_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI2_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI2RDI_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI2PIX_CLK>,
+ <&clock_mmss MMSS_CAMSS_CPHY_CSID2_CLK>;
+ clock-names = "mmssnoc_axi", "mnoc_ahb",
+ "bmic_smmu_ahb", "bmic_smmu_axi",
+ "camss_ahb_clk", "camss_top_ahb_clk",
+ "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
+ "csi_clk", "csi_ahb_clk", "csi_rdi_clk",
+ "csi_pix_clk", "cphy_csid_clk";
+ qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
+ 0 0 0 0 0>;
+ status = "ok";
+ };
+
+ qcom,csid@ca30c00 {
+ cell-index = <3>;
+ compatible = "qcom,csid-v5.0", "qcom,csid";
+ reg = <0xca30c00 0x400>;
+ reg-names = "csid";
+ interrupts = <0 299 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csid";
+ qcom,csi-vdd-voltage = <1200000>;
+ qcom,mipi-csi-vdd-supply = <&pm660_l1>;
+ gdscr-supply = <&gdsc_camss_top>;
+ vdd_sec-supply = <&pm660l_l1>;
+ bimc_smmu-supply = <&gdsc_bimc_smmu>;
+ qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
+ qcom,cam-vreg-min-voltage = <925000 0 0>;
+ qcom,cam-vreg-max-voltage = <925000 0 0>;
+ qcom,cam-vreg-op-mode = <0 0 0>;
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>,
+ <&clock_mmss CSI3_CLK_SRC>,
+ <&clock_mmss CSIPHY_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CSI3_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI3_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI3RDI_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI3PIX_CLK>,
+ <&clock_mmss MMSS_CAMSS_CPHY_CSID3_CLK>;
+ clock-names = "mmssnoc_axi", "mnoc_ahb",
+ "bmic_smmu_ahb", "bmic_smmu_axi",
+ "camss_ahb_clk", "camss_top_ahb_clk",
+ "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src",
+ "csi_clk", "csi_ahb_clk", "csi_rdi_clk",
+ "csi_pix_clk", "cphy_csid_clk";
+ qcom,clock-rates = <0 0 0 0 0 0 0 310000000 200000000
+ 0 0 0 0 0>;
+ status = "ok";
+ };
+
+ qcom,cam_smmu {
+ compatible = "qcom,msm-cam-smmu";
+ qcom,iommu-dma-addr-pool = <0x00020000 0x78000000>;
+ status = "ok";
+
+ msm_cam_smmu_cb1 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&mmss_bimc_smmu 0xc00>,
+ <&mmss_bimc_smmu 0xc01>,
+ <&mmss_bimc_smmu 0xc02>,
+ <&mmss_bimc_smmu 0xc03>;
+ iommu-cells = <1>;
+ label = "vfe";
+ qcom,scratch-buf-support;
+ };
+
+ msm_cam_smmu_cb2 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&mmss_bimc_smmu 0xa00>;
+ iommu-cells = <1>;
+ label = "cpp";
+ };
+
+ msm_cam_smmu_cb4 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&mmss_bimc_smmu 0x800>;
+ iommu-cells = <1>;
+ label = "jpeg_enc0";
+ };
+
+ msm_cam_smmu_cb5 {
+ compatible = "qcom,msm-cam-smmu-cb";
+ iommus = <&mmss_bimc_smmu 0x801>;
+ iommu-cells = <1>;
+ label = "jpeg_dma";
+ };
+ };
+
+ qcom,cpp@ca04000 {
+ cell-index = <0>;
+ compatible = "qcom,cpp";
+ reg = <0xca04000 0x100>,
+ <0xca80000 0x3000>,
+ <0xca18000 0x3000>,
+ <0xc8c36D4 0x4>;
+ reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp";
+ interrupts = <0 294 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpp";
+ smmu-vdd-supply = <&gdsc_bimc_smmu>;
+ camss-vdd-supply = <&gdsc_camss_top>;
+ vdd-supply = <&gdsc_cpp>;
+ qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd";
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss CPP_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CPP_CLK>,
+ <&clock_mmss MMSS_CAMSS_CPP_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_CPP_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_MICRO_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_CPP_VBIF_AHB_CLK>;
+ clock-names = "mmssnoc_axi_clk",
+ "mnoc_ahb_clk",
+ "camss_ahb_clk", "camss_top_ahb_clk",
+ "cpp_src_clk",
+ "cpp_core_clk", "camss_cpp_ahb_clk",
+ "camss_cpp_axi_clk", "micro_iface_clk",
+ "mmss_smmu_axi_clk", "cpp_vbif_ahb_clk";
+ qcom,clock-rates = <0 0 0 0 200000000 200000000 0 0 0 0 0>;
+ qcom,min-clock-rate = <200000000>;
+ qcom,bus-master = <1>;
+ qcom,vbif-qos-setting = <0x550 0x55555555>,
+ <0x554 0x55555555>,
+ <0x558 0x55555555>,
+ <0x55c 0x55555555>,
+ <0x560 0x55555555>,
+ <0x564 0x55555555>,
+ <0x568 0x55555555>,
+ <0x56c 0x55555555>,
+ <0x570 0x55555555>,
+ <0x574 0x55555555>,
+ <0x578 0x55555555>,
+ <0x57c 0x55555555>,
+ <0x580 0x55555555>,
+ <0x584 0x55555555>,
+ <0x588 0x55555555>,
+ <0x58c 0x55555555>;
+ status = "ok";
+ qcom,msm-bus,name = "msm_camera_cpp";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <106 512 0 0>,
+ <106 512 0 0>;
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,cpp-cx-ipeak = <&cx_ipeak_lm 2>;
+ resets = <&clock_mmss CAMSS_MICRO_BCR>;
+ reset-names = "micro_iface_reset";
+ qcom,src-clock-rates = <120000000 256000000 384000000
+ 480000000 540000000 576000000>;
+ qcom,micro-reset;
+ qcom,cpp-fw-payload-info {
+ qcom,stripe-base = <790>;
+ qcom,plane-base = <715>;
+ qcom,stripe-size = <63>;
+ qcom,plane-size = <25>;
+ qcom,fe-ptr-off = <11>;
+ qcom,we-ptr-off = <23>;
+ qcom,ref-fe-ptr-off = <17>;
+ qcom,ref-we-ptr-off = <36>;
+ qcom,we-meta-ptr-off = <42>;
+ qcom,fe-mmu-pf-ptr-off = <7>;
+ qcom,ref-fe-mmu-pf-ptr-off = <10>;
+ qcom,we-mmu-pf-ptr-off = <13>;
+ qcom,dup-we-mmu-pf-ptr-off = <18>;
+ qcom,ref-we-mmu-pf-ptr-off = <23>;
+ qcom,set-group-buffer-len = <135>;
+ qcom,dup-frame-indicator-off = <70>;
+ };
+ };
+
+ qcom,ispif@ca31000 {
+ cell-index = <0>;
+ compatible = "qcom,ispif-v3.0", "qcom,ispif";
+ reg = <0xca31000 0xc00>,
+ <0xca00020 0x4>;
+ reg-names = "ispif", "csi_clk_mux";
+ interrupts = <0 309 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ispif";
+ qcom,num-isps = <0x2>;
+ camss-vdd-supply = <&gdsc_camss_top>;
+ vfe0-vdd-supply = <&gdsc_vfe0>;
+ vfe1-vdd-supply = <&gdsc_vfe1>;
+ qcom,vdd-names = "camss-vdd", "vfe0-vdd",
+ "vfe1-vdd";
+ qcom,clock-cntl-support;
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>,
+ <&clock_mmss CSI0_CLK_SRC>,
+ <&clock_mmss CSI1_CLK_SRC>,
+ <&clock_mmss CSI2_CLK_SRC>,
+ <&clock_mmss CSI3_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CSI0RDI_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI1RDI_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI2RDI_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI3RDI_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI0PIX_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI1PIX_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI2PIX_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI3PIX_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI0_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI1_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI2_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI3_CLK>,
+ <&clock_mmss VFE0_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_VFE0_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>,
+ <&clock_mmss VFE1_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_VFE1_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>;
+ clock-names = "mmssnoc_axi", "mnoc_ahb_clk",
+ "camss_ahb_clk",
+ "camss_top_ahb_clk", "ispif_ahb_clk",
+ "csi0_src_clk", "csi1_src_clk",
+ "csi2_src_clk", "csi3_src_clk",
+ "csi0_rdi_clk", "csi1_rdi_clk",
+ "csi2_rdi_clk", "csi3_rdi_clk",
+ "csi0_pix_clk", "csi1_pix_clk",
+ "csi2_pix_clk", "csi3_pix_clk",
+ "camss_csi0_clk", "camss_csi1_clk",
+ "camss_csi2_clk", "camss_csi3_clk",
+ "vfe0_clk_src",
+ "camss_vfe_vfe0_clk",
+ "camss_csi_vfe0_clk",
+ "vfe1_clk_src",
+ "camss_vfe_vfe1_clk",
+ "camss_csi_vfe1_clk";
+ qcom,clock-rates = <0 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0 0
+ 0 0 0
+ 0 0 0>;
+ qcom,clock-control = "INIT_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE",
+ "INIT_RATE", "INIT_RATE",
+ "INIT_RATE", "INIT_RATE",
+ "NO_SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "NO_SET_RATE",
+ "NO_SET_RATE", "NO_SET_RATE",
+ "INIT_RATE",
+ "NO_SET_RATE", "NO_SET_RATE",
+ "INIT_RATE",
+ "NO_SET_RATE", "NO_SET_RATE";
+ status = "ok";
+ };
+
+ vfe0: qcom,vfe0@ca10000 {
+ cell-index = <0>;
+ compatible = "qcom,vfe48";
+ reg = <0xca10000 0x4000>,
+ <0xca40000 0x3000>;
+ reg-names = "vfe", "vfe_vbif";
+ interrupts = <0 314 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vfe";
+ vdd-supply = <&gdsc_vfe0>;
+ camss-vdd-supply = <&gdsc_camss_top>;
+ smmu-vdd-supply = <&gdsc_bimc_smmu>;
+ qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd";
+ clocks = <&clock_mmss MMSS_THROTTLE_CAMSS_AXI_CLK>,
+ <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss VFE0_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_VFE0_CLK>,
+ <&clock_mmss MMSS_CAMSS_VFE0_STREAM_CLK>,
+ <&clock_mmss MMSS_CAMSS_VFE0_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>;
+ clock-names = "mmss_throttle_camss_axi_clk", "mmssnoc_axi",
+ "mnoc_ahb_clk", "bimc_smmu_ahb_clk",
+ "bimc_smmu_axi_clk", "camss_ahb_clk",
+ "camss_top_ahb_clk", "vfe_clk_src",
+ "camss_vfe_clk", "camss_vfe_stream_clk",
+ "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk",
+ "camss_vfe_vbif_axi_clk",
+ "camss_csi_vfe_clk";
+ qcom,clock-rates = <0 0 0 0 0 0 0 404000000 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 480000000 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 576000000 0 0 0 0 0 0>;
+ status = "ok";
+ qos-entries = <8>;
+ qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418
+ 0x41c 0x420>;
+ qos-settings = <0xaaa5aaa5
+ 0xaaa5aaa5
+ 0xaaa5aaa5
+ 0xaa55aaa5
+ 0xaa55aa55
+ 0xaa55aa55
+ 0xaa55aa55
+ 0x0005aa55>;
+ vbif-entries = <3>;
+ vbif-regs = <0x124 0xac 0xd0>;
+ vbif-settings = <0x3 0x40 0x1010>;
+ ds-entries = <17>;
+ ds-regs = <0x424 0x428 0x42c 0x430 0x434
+ 0x438 0x43c 0x440 0x444 0x448 0x44c
+ 0x450 0x454 0x458 0x45c 0x460 0x464>;
+ ds-settings = <0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0x110>;
+ qcom,msm-bus,name = "msm_camera_vfe";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <29 512 0 0>,
+ <29 512 100000000 100000000>;
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,vfe-cx-ipeak = <&cx_ipeak_lm 2>;
+ };
+
+ vfe1: qcom,vfe1@ca14000 {
+ cell-index = <1>;
+ compatible = "qcom,vfe48";
+ reg = <0xca14000 0x4000>,
+ <0xca40000 0x3000>;
+ reg-names = "vfe", "vfe_vbif";
+ interrupts = <0 315 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vfe";
+ vdd-supply = <&gdsc_vfe1>;
+ camss-vdd-supply = <&gdsc_camss_top>;
+ smmu-vdd-supply = <&gdsc_bimc_smmu>;
+ qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd";
+ clocks = <&clock_mmss MMSS_THROTTLE_CAMSS_AXI_CLK>,
+ <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss VFE1_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_VFE1_CLK>,
+ <&clock_mmss MMSS_CAMSS_VFE1_STREAM_CLK>,
+ <&clock_mmss MMSS_CAMSS_VFE1_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>;
+ clock-names = "mmss_throttle_camss_axi_clk", "mmssnoc_axi",
+ "mnoc_ahb_clk", "bimc_smmu_ahb_clk",
+ "bimc_smmu_axi_clk", "camss_ahb_clk",
+ "camss_top_ahb_clk", "vfe_clk_src",
+ "camss_vfe_clk", "camss_vfe_stream_clk",
+ "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk",
+ "camss_vfe_vbif_axi_clk",
+ "camss_csi_vfe_clk";
+ qcom,clock-rates = <0 0 0 0 0 0 0 404000000 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 480000000 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 576000000 0 0 0 0 0 0>;
+ status = "ok";
+ qos-entries = <8>;
+ qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418
+ 0x41c 0x420>;
+ qos-settings = <0xaaa5aaa5
+ 0xaaa5aaa5
+ 0xaaa5aaa5
+ 0xaa55aaa5
+ 0xaa55aa55
+ 0xaa55aa55
+ 0xaa55aa55
+ 0x0005aa55>;
+ vbif-entries = <3>;
+ vbif-regs = <0x124 0xac 0xd0>;
+ vbif-settings = <0x3 0x40 0x1010>;
+ ds-entries = <17>;
+ ds-regs = <0x424 0x428 0x42c 0x430 0x434
+ 0x438 0x43c 0x440 0x444 0x448 0x44c
+ 0x450 0x454 0x458 0x45c 0x460 0x464>;
+ ds-settings = <0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0xcccc1111
+ 0x110>;
+ qcom,msm-bus,name = "msm_camera_vfe";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <29 512 0 0>,
+ <29 512 100000000 100000000>;
+ qcom,msm-bus-vector-dyn-vote;
+ qcom,vfe-cx-ipeak = <&cx_ipeak_lm 2>;
+ };
+
+ qcom,vfe {
+ compatible = "qcom,vfe";
+ num_child = <2>;
+ };
+
+ cci: qcom,cci@ca0c000 {
+ cell-index = <0>;
+ compatible = "qcom,cci";
+ reg = <0xca0c000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg-names = "cci";
+ interrupts = <0 295 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cci";
+ status = "ok";
+ mmagic-supply = <&gdsc_bimc_smmu>;
+ gdscr-supply = <&gdsc_camss_top>;
+ qcom,cam-vreg-name = "mmagic", "gdscr";
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss CCI_CLK_SRC>,
+ <&clock_mmss MMSS_CAMSS_CCI_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_CCI_CLK>;
+ clock-names = "mmssnoc_axi", "mnoc_ahb", "smmu_ahb", "smmu_axi",
+ "camss_ahb_clk", "camss_top_ahb_clk",
+ "cci_src_clk", "cci_ahb_clk", "camss_cci_clk";
+ qcom,clock-rates = <0 0 0 0 0 0 19200000 0 0>,
+ <0 0 0 0 0 0 37500000 0 0>;
+ pinctrl-names = "cci_default", "cci_suspend";
+ pinctrl-0 = <&cci0_active &cci1_active>;
+ pinctrl-1 = <&cci0_suspend &cci1_suspend>;
+ gpios = <&tlmm 36 0>,
+ <&tlmm 37 0>,
+ <&tlmm 38 0>,
+ <&tlmm 39 0>;
+ qcom,gpio-tbl-num = <0 1 2 3>;
+ qcom,gpio-tbl-flags = <1 1 1 1>;
+ qcom,gpio-tbl-label = "CCI_I2C_DATA0",
+ "CCI_I2C_CLK0",
+ "CCI_I2C_DATA1",
+ "CCI_I2C_CLK1";
+ i2c_freq_100Khz: qcom,i2c_standard_mode {
+ status = "disabled";
+ };
+ i2c_freq_400Khz: qcom,i2c_fast_mode {
+ status = "disabled";
+ };
+ i2c_freq_custom: qcom,i2c_custom_mode {
+ status = "disabled";
+ };
+ i2c_freq_1Mhz: qcom,i2c_fast_plus_mode {
+ status = "disabled";
+ };
+ };
+
+ qcom,jpeg@ca1c000 {
+ cell-index = <0>;
+ compatible = "qcom,jpeg";
+ reg = <0xca1c000 0x4000>,
+ <0xca60000 0x3000>;
+ reg-names = "jpeg_hw", "jpeg_vbif";
+ interrupts = <0 316 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "jpeg";
+ smmu-vdd-supply = <&gdsc_bimc_smmu>;
+ camss-vdd-supply = <&gdsc_camss_top>;
+ qcom,vdd-names = "smmu-vdd", "camss-vdd";
+ clock-names = "mmssnoc_axi",
+ "mmss_mnoc_ahb_clk",
+ "mmss_bimc_smmu_ahb_clk",
+ "mmss_bimc_smmu_axi_clk",
+ "mmss_camss_ahb_clk",
+ "mmss_camss_top_ahb_clk",
+ "core_clk",
+ "mmss_camss_jpeg_ahb_clk",
+ "mmss_camss_jpeg_axi_clk";
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_JPEG0_VOTE_CLK>,
+ <&clock_mmss MMSS_CAMSS_JPEG_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_JPEG_AXI_CLK >;
+ qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>;
+ qcom,vbif-reg-settings = <0x4 0x1>;
+ qcom,prefetch-reg-settings = <0x30c 0x1111>,
+ <0x318 0x31>,
+ <0x324 0x31>,
+ <0x330 0x31>,
+ <0x33c 0x0>;
+ qcom,msm-bus,name = "msm_camera_jpeg0";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <62 512 0 0>,
+ <62 512 1200000 1200000>;
+ status = "ok";
+ };
+
+ qcom,jpeg@caa0000 {
+ cell-index = <3>;
+ compatible = "qcom,jpegdma";
+ reg = <0xcaa0000 0x4000>,
+ <0xca60000 0x3000>;
+ reg-names = "jpeg_hw", "jpeg_vbif";
+ interrupts = <0 304 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "jpeg";
+ smmu-vdd-supply = <&gdsc_bimc_smmu>;
+ camss-vdd-supply = <&gdsc_camss_top>;
+ qcom,vdd-names = "smmu-vdd", "camss-vdd";
+ clock-names = "mmssnoc_axi",
+ "mmss_mnoc_ahb_clk",
+ "mmss_bimc_smmu_ahb_clk",
+ "mmss_bimc_smmu_axi_clk",
+ "mmss_camss_ahb_clk",
+ "mmss_camss_top_ahb_clk",
+ "core_clk",
+ "mmss_camss_jpeg_ahb_clk",
+ "mmss_camss_jpeg_axi_clk";
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
+ <&clock_mmss MMSS_CAMSS_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_JPEG0_DMA_VOTE_CLK>,
+ <&clock_mmss MMSS_CAMSS_JPEG_AHB_CLK>,
+ <&clock_mmss MMSS_CAMSS_JPEG_AXI_CLK>;
+ qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>;
+ qcom,vbif-reg-settings = <0x4 0x1>;
+ qcom,prefetch-reg-settings = <0x18c 0x11>,
+ <0x1a0 0x31>,
+ <0x1b0 0x31>;
+ qcom,msm-bus,name = "msm_camera_jpeg_dma";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps = <62 512 0 0>,
+ <62 512 1200000 1200000>;
+ qcom,max-ds-factor = <128>;
+ status = "ok";
+ };
+};
+
+&i2c_freq_100Khz {
+ qcom,hw-thigh = <201>;
+ qcom,hw-tlow = <174>;
+ qcom,hw-tsu-sto = <204>;
+ qcom,hw-tsu-sta = <231>;
+ qcom,hw-thd-dat = <22>;
+ qcom,hw-thd-sta = <162>;
+ qcom,hw-tbuf = <227>;
+ qcom,hw-scl-stretch-en = <0>;
+ qcom,hw-trdhld = <6>;
+ qcom,hw-tsp = <3>;
+ qcom,cci-clk-src = <37500000>;
+ status = "ok";
+};
+
+&i2c_freq_400Khz {
+ qcom,hw-thigh = <38>;
+ qcom,hw-tlow = <56>;
+ qcom,hw-tsu-sto = <40>;
+ qcom,hw-tsu-sta = <40>;
+ qcom,hw-thd-dat = <22>;
+ qcom,hw-thd-sta = <35>;
+ qcom,hw-tbuf = <62>;
+ qcom,hw-scl-stretch-en = <0>;
+ qcom,hw-trdhld = <6>;
+ qcom,hw-tsp = <3>;
+ qcom,cci-clk-src = <37500000>;
+ status = "ok";
+};
+
+&i2c_freq_custom {
+ qcom,hw-thigh = <38>;
+ qcom,hw-tlow = <56>;
+ qcom,hw-tsu-sto = <40>;
+ qcom,hw-tsu-sta = <40>;
+ qcom,hw-thd-dat = <22>;
+ qcom,hw-thd-sta = <35>;
+ qcom,hw-tbuf = <62>;
+ qcom,hw-scl-stretch-en = <1>;
+ qcom,hw-trdhld = <6>;
+ qcom,hw-tsp = <3>;
+ qcom,cci-clk-src = <37500000>;
+ status = "ok";
+};
+
+&i2c_freq_1Mhz {
+ qcom,hw-thigh = <16>;
+ qcom,hw-tlow = <22>;
+ qcom,hw-tsu-sto = <17>;
+ qcom,hw-tsu-sta = <18>;
+ qcom,hw-thd-dat = <16>;
+ qcom,hw-thd-sta = <15>;
+ qcom,hw-tbuf = <24>;
+ qcom,hw-scl-stretch-en = <0>;
+ qcom,hw-trdhld = <3>;
+ qcom,hw-tsp = <3>;
+ qcom,cci-clk-src = <37500000>;
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-cdp-external-codec-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-cdp-external-codec-overlay.dts
new file mode 100755
index 0000000..7d8eed8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-cdp-external-codec-overlay.dts
@@ -0,0 +1,27 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,cpu-osm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm660-cdp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 Ext. Audio Codec CDP";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <1 0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
+&tasha_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-cdp-internal-codec-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-cdp-internal-codec-overlay.dts
new file mode 100755
index 0000000..9b0ca33
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-cdp-internal-codec-overlay.dts
@@ -0,0 +1,17 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,cpu-osm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm660-cdp.dtsi"
+#include "sdm660-internal-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 Int. Audio Codec CDP";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <1 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-cdp.dts
new file mode 100755
index 0000000..078b778
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-cdp.dts
@@ -0,0 +1,24 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L CDP";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <1 0>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
+&tasha_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-cdp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-cdp.dtsi
new file mode 100755
index 0000000..6669065
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-cdp.dtsi
@@ -0,0 +1,261 @@
+#include "sdm660-camera-sensor-cdp.dtsi"
+/ {
+};
+
+&uartblsp1dm1 {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart_console_active>;
+};
+
+&ufsphy1 {
+ vdda-phy-supply = <&pm660l_l1>;
+ vdda-pll-supply = <&pm660_l10>;
+ vdda-phy-max-microamp = <51400>;
+ vdda-pll-max-microamp = <14200>;
+ status = "ok";
+};
+
+&ufs1 {
+ vdd-hba-supply = <&gdsc_ufs>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm660l_l4>;
+ vccq2-supply = <&pm660_l8>;
+ vcc-max-microamp = <500000>;
+ vccq2-max-microamp = <600000>;
+ qcom,vddp-ref-clk-supply = <&pm660_l1>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+
+ status = "ok";
+};
+
+&pm660_gpios {
+ /* GPIO 4 (NFC_CLK_REQ) */
+ nfc_clk {
+ nfc_clk_default: nfc_clk_default {
+ pins = "gpio4";
+ function = "normal";
+ input-enable;
+ power-source = <1>;
+ };
+ };
+};
+
+&i2c_6 { /* BLSP1 QUP6 (NFC) */
+ status = "okay";
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 28 0x00>;
+ qcom,nq-ven = <&tlmm 29 0x00>;
+ qcom,nq-firm = <&tlmm 30 0x00>;
+ qcom,nq-clkreq = <&pm660_gpios 4 0x00>;
+ qcom,nq-esepwr = <&tlmm 31 0x00>;
+ interrupt-parent = <&tlmm>;
+ qcom,clk-src = "BBCLK3";
+ interrupts = <28 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_default>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
+ clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK3_PIN>;
+ clock-names = "ref_clk";
+ };
+};
+
+&mdss_mdp {
+ qcom,mdss-pref-prim-intf = "dsi";
+};
+
+&mdss_dsi {
+ hw-config = "split_dsi";
+};
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+ pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+ qcom,platform-reset-gpio = <&tlmm 53 0>;
+ qcom,platform-te-gpio = <&tlmm 59 0>;
+};
+
+&mdss_dsi1 {
+ qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+ pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+ qcom,platform-reset-gpio = <&tlmm 53 0>;
+ qcom,platform-te-gpio = <&tlmm 59 0>;
+};
+
+&pm660l_wled {
+ qcom,string-cfg= <6>;
+ status = "ok";
+};
+
+&pm660l_lcdb {
+ status = "ok";
+};
+
+&dsi_dual_nt35597_truly_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_dual_nt35597_truly_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_dual_sharp_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_nt35597_truly_dsc_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_nt35597_truly_dsc_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_dual_nt35597_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_dual_nt35597_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <720 128 720 128 1440 128>;
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_truly_1080_vid {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_truly_1080_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+ qcom,partial-update-enabled = "single_roi";
+ qcom,panel-roi-alignment = <2 2 4 2 1080 2>;
+};
+
+&dsi_rm67195_amoled_fhd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>;
+};
+
+&dsi_lgd_incell_sw49106_fhd_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_hx8399c_truly_vid {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&mdss_dp_ctrl {
+ pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
+ pinctrl-0 = <&mdss_dp_aux_active &mdss_dp_usbplug_cc_active>;
+ pinctrl-1 = <&mdss_dp_aux_suspend &mdss_dp_usbplug_cc_suspend>;
+ qcom,aux-en-gpio = <&tlmm 55 0>;
+ qcom,aux-sel-gpio = <&tlmm 56 0>;
+ qcom,usbplug-cc-gpio = <&tlmm 58 0>;
+};
+
+&sdhc_1 {
+ /* device core power supply */
+ vdd-supply = <&pm660l_l4>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <200 570000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm660_l8>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <200 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ /* device core power supply */
+ vdd-supply = <&pm660l_l5>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <15000 800000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm660l_l2>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ #address-cells = <0>;
+ interrupt-parent = <&sdhc_2>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 0 125 0
+ 1 &intc 0 0 221 0
+ 2 &tlmm 54 0>;
+ interrupt-names = "hc_irq", "pwr_irq", "status_irq";
+ cd-gpios = <&tlmm 54 0x1>;
+
+ status = "ok";
+};
+
+&soc {
+ qcom,msm-ssc-sensors {
+ compatible = "qcom,msm-ssc-sensors";
+ };
+};
+
+&pm660_charger {
+ qcom,batteryless-platform;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-common.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-common.dtsi
new file mode 100755
index 0000000..e38f935
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-common.dtsi
@@ -0,0 +1,672 @@
+&soc {
+ ufsphy1: ufsphy@1da7000 {
+ compatible = "qcom,ufs-phy-qmp-v3-660";
+ reg = <0x1da7000 0xdb8>;
+ reg-names = "phy_mem";
+ #phy-cells = <0>;
+ clock-names = "ref_clk_src",
+ "ref_clk",
+ "ref_aux_clk";
+ clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK1>,
+ <&clock_gcc GCC_UFS_CLKREF_CLK>,
+ <&clock_gcc GCC_UFS_PHY_AUX_CLK>;
+ status = "disabled";
+ };
+
+ ufs_ice: ufsice@1db0000 {
+ compatible = "qcom,ice";
+ reg = <0x1db0000 0x8000>;
+ qcom,enable-ice-clk;
+ clock-names = "ufs_core_clk", "bus_clk",
+ "iface_clk", "ice_core_clk";
+ clocks = <&clock_gcc GCC_UFS_AXI_CLK>,
+ <&clock_gcc GCC_UFS_CLKREF_CLK>,
+ <&clock_gcc GCC_UFS_AHB_CLK>,
+ <&clock_gcc GCC_UFS_ICE_CORE_CLK>;
+ qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
+ vdd-hba-supply = <&gdsc_ufs>;
+ qcom,msm-bus,name = "ufs_ice_noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 650 0 0>, /* No vote */
+ <1 650 1000 0>; /* Max. bandwidth */
+ qcom,bus-vector-names = "MIN",
+ "MAX";
+ qcom,instance-type = "ufs";
+ };
+
+ sdcc1_ice: sdcc1ice@c0c8000 {
+ compatible = "qcom,ice";
+ reg = <0xc0c8000 0x8000>;
+ qcom,enable-ice-clk;
+ clock-names = "ice_core_clk_src", "ice_core_clk",
+ "bus_clk", "iface_clk";
+ clocks = <&clock_gcc SDCC1_ICE_CORE_CLK_SRC>,
+ <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>,
+ <&clock_gcc GCC_SDCC1_APPS_CLK>,
+ <&clock_gcc GCC_SDCC1_AHB_CLK>;
+ qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;
+ qcom,msm-bus,name = "sdcc_ice_noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <78 512 0 0>, /* No vote */
+ <78 512 1000 0>; /* Max. bandwidth */
+ qcom,bus-vector-names = "MIN",
+ "MAX";
+ qcom,instance-type = "sdcc";
+ };
+
+ ufs1: ufshc@1da4000 {
+ compatible = "qcom,ufshc";
+ reg = <0x1da4000 0x3000>, <0x1db0000 0x8000>;
+ reg-names = "ufs_mem", "ufs_ice";
+ interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufsphy1>;
+ phy-names = "ufsphy";
+
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "core_clk_ice",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk";
+ clocks =
+ <&clock_gcc GCC_UFS_AXI_CLK>,
+ <&clock_gcc GCC_AGGRE2_UFS_AXI_CLK>,
+ <&clock_gcc GCC_UFS_AHB_CLK>,
+ <&clock_gcc GCC_UFS_UNIPRO_CORE_CLK>,
+ <&clock_gcc GCC_UFS_ICE_CORE_CLK>,
+ <&clock_rpmcc RPM_SMD_LN_BB_CLK1>,
+ <&clock_gcc GCC_UFS_TX_SYMBOL_0_CLK>,
+ <&clock_gcc GCC_UFS_RX_SYMBOL_0_CLK>;
+ freq-table-hz =
+ <50000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <37500000 150000000>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ lanes-per-direction = <1>;
+
+ non-removable;
+ qcom,msm-bus,name = "ufs1";
+ qcom,msm-bus,num-cases = <12>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <95 512 0 0>, <1 650 0 0>, /* No vote */
+ <95 512 922 0>, <1 650 1000 0>, /* PWM G1 */
+ <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */
+ <95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */
+ <95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */
+ <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */
+ <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */
+ <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RA */
+ <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */
+ <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */
+ <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RB */
+ <95 512 7643136 0>, <1 650 307200 0>; /* Max. bandwidth */
+ qcom,bus-vector-names = "MIN",
+ "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
+ "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
+ "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
+ "MAX";
+
+ qcom,pm-qos-cpu-groups = <0x0F 0xF0>;
+ qcom,pm-qos-cpu-group-latency-us = <26 26>;
+ qcom,pm-qos-default-cpu = <0>;
+
+ resets = <&clock_gcc GCC_UFS_BCR>;
+ reset-names = "core_reset";
+
+ status = "disabled";
+ };
+
+ usb3: ssusb@a800000 {
+ compatible = "qcom,dwc-usb3-msm";
+ reg = <0x0a800000 0xfc100>,
+ <0x0c016000 0x400>;
+ reg-names = "core_base",
+ "ahb2phy_base";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH>, <0 243 IRQ_TYPE_LEVEL_HIGH>, <0 180 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq";
+
+ USB3_GDSC-supply = <&gdsc_usb30>;
+ dpdm-supply = <&qusb_phy0>;
+
+ qcom,msm-bus,name = "usb3";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <61 512 0 0>,
+ <61 512 240000 800000>;
+
+ qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
+ extcon = <&pm660_pdphy>;
+ qcom,pm-qos-latency = <41>; /* CPU-CLUSTER-WFI-LVL latency +1 */
+
+ clocks = <&clock_gcc GCC_USB30_MASTER_CLK>,
+ <&clock_gcc GCC_CFG_NOC_USB3_AXI_CLK>,
+ <&clock_gcc GCC_AGGRE2_USB3_AXI_CLK>,
+ <&clock_rpmcc AGGR2_NOC_USB_CLK>,
+ <&clock_gcc GCC_USB30_MOCK_UTMI_CLK>,
+ <&clock_gcc GCC_USB30_SLEEP_CLK>,
+ <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&clock_rpmcc CXO_DWC3_CLK>;
+
+ clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+ "noc_aggr_clk", "utmi_clk", "sleep_clk",
+ "cfg_ahb_clk", "xo";
+
+ qcom,core-clk-rate = <133330000>;
+ qcom,core-clk-rate-hs = <66666667>;
+
+ resets = <&clock_gcc GCC_USB_30_BCR>;
+ reset-names = "core_reset";
+
+ dwc3@a800000 {
+ compatible = "snps,dwc3";
+ reg = <0x0a800000 0xc8d0>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
+ usb-phy = <&qusb_phy0>, <&ssphy>;
+ tx-fifo-resize;
+ snps,usb3-u1u2-disable;
+ snps,disable-clk-gating;
+ snps,has-lpm-erratum;
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ dr_mode = "otg";
+ linux,sysdev_is_parent;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,usb3_lpm_capable;
+ usb-core-id = <0>;
+ maximum-speed = "super-speed";
+ };
+
+ qcom,usbbam@a904000 {
+ compatible = "qcom,usb-bam-msm";
+ reg = <0x0a904000 0x17000>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 132 IRQ_TYPE_LEVEL_HIGH>;
+
+ qcom,bam-type = <0>;
+ qcom,usb-bam-fifo-baseaddr = <0x146bb000>;
+ qcom,usb-bam-num-pipes = <8>;
+ qcom,ignore-core-reset-ack;
+ qcom,disable-clk-gating;
+ qcom,usb-bam-override-threshold = <0x4001>;
+ qcom,usb-bam-max-mbps-highspeed = <400>;
+ qcom,usb-bam-max-mbps-superspeed = <3600>;
+ qcom,reset-bam-on-connect;
+
+ qcom,pipe0 {
+ label = "ssusb-ipa-out-0";
+ qcom,usb-bam-mem-type = <1>;
+ qcom,dir = <0>;
+ qcom,pipe-num = <0>;
+ qcom,peer-bam = <1>;
+ qcom,src-bam-pipe-index = <1>;
+ qcom,data-fifo-size = <0x8000>;
+ qcom,descriptor-fifo-size = <0x2000>;
+ };
+ qcom,pipe1 {
+ label = "ssusb-ipa-in-0";
+ qcom,usb-bam-mem-type = <1>;
+ qcom,dir = <1>;
+ qcom,pipe-num = <0>;
+ qcom,peer-bam = <1>;
+ qcom,dst-bam-pipe-index = <0>;
+ qcom,data-fifo-size = <0x8000>;
+ qcom,descriptor-fifo-size = <0x2000>;
+ };
+ qcom,pipe2 {
+ label = "ssusb-qdss-in-0";
+ qcom,usb-bam-mem-type = <2>;
+ qcom,dir = <1>;
+ qcom,pipe-num = <0>;
+ qcom,peer-bam = <0>;
+ qcom,peer-bam-physical-address = <0x06064000>;
+ qcom,src-bam-pipe-index = <0>;
+ qcom,dst-bam-pipe-index = <3>;
+ qcom,data-fifo-offset = <0x0>;
+ qcom,data-fifo-size = <0x1800>;
+ qcom,descriptor-fifo-offset = <0x1800>;
+ qcom,descriptor-fifo-size = <0x800>;
+ };
+ qcom,pipe3 {
+ label = "ssusb-dpl-ipa-in-1";
+ qcom,usb-bam-mem-type = <1>;
+ qcom,dir = <1>;
+ qcom,pipe-num = <1>;
+ qcom,peer-bam = <1>;
+ qcom,dst-bam-pipe-index = <2>;
+ qcom,data-fifo-size = <0x8000>;
+ qcom,descriptor-fifo-size = <0x2000>;
+ };
+ };
+ };
+
+ qusb_phy0: qusb@c012000 {
+ compatible = "qcom,qusb2phy";
+ reg = <0x0c012000 0x180>,
+ <0x01fcb24c 0x4>,
+ <0x00780240 0x4>,
+ <0x00188018 0x4>;
+ reg-names = "qusb_phy_base",
+ "tcsr_clamp_dig_n_1p8",
+ "tune2_efuse_addr",
+ "ref_clk_addr";
+ vdd-supply = <&pm660l_l1>;
+ vdda18-supply = <&pm660_l10>;
+ vdda33-supply = <&pm660l_l7>;
+ qcom,vdd-voltage-level = <0 925000 925000>;
+ qcom,tune2-efuse-bit-pos = <25>;
+ qcom,tune2-efuse-num-bits = <4>;
+ qcom,qusb-phy-init-seq = <0xf8 0x80
+ 0xb3 0x84
+ 0x83 0x88
+ 0xc0 0x8c
+ 0x30 0x08
+ 0x79 0x0c
+ 0x21 0x10
+ 0x14 0x9c
+ 0x9f 0x1c
+ 0x00 0x18>;
+ phy_type= "utmi";
+ qcom,phy-clk-scheme = "cml";
+ qcom,major-rev = <1>;
+
+ clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK1>,
+ <&clock_gcc GCC_RX0_USB2_CLKREF_CLK>,
+ <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+
+ clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk";
+
+ resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;
+ reset-names = "phy_reset";
+ };
+
+ ssphy: ssphy@c010000 {
+ compatible = "qcom,usb-ssphy-qmp-usb3-or-dp";
+ reg = <0xc010000 0xe18>,
+ <0x01fcb244 0x4>,
+ <0x01fcb248 0x4>;
+ reg-names = "qmp_phy_base",
+ "vls_clamp_reg",
+ "tcsr_usb3_dp_phymode";
+ vdd-supply = <&pm660l_l1>;
+ core-supply = <&pm660_l10>;
+ qcom,vdd-voltage-level = <0 925000 925000>;
+ qcom,core-voltage-level = <0 1800000 1800000>;
+ qcom,vbus-valid-override;
+ qcom,qmp-phy-init-seq =
+ /* <reg_offset, value, delay> */
+ <0xac 0x14 0x00
+ 0x34 0x08 0x00
+ 0x174 0x30 0x00
+ 0x3c 0x06 0x00
+ 0xb4 0x00 0x00
+ 0xb8 0x08 0x00
+ 0x70 0x0f 0x00
+ 0x19c 0x01 0x00
+ 0x178 0x00 0x00
+ 0xd0 0x82 0x00
+ 0xdc 0x55 0x00
+ 0xe0 0x55 0x00
+ 0xe4 0x03 0x00
+ 0x78 0x0b 0x00
+ 0x84 0x16 0x00
+ 0x90 0x28 0x00
+ 0x108 0x80 0x00
+ 0x10c 0x00 0x00
+ 0x184 0x0a 0x00
+ 0x4c 0x15 0x00
+ 0x50 0x34 0x00
+ 0x54 0x00 0x00
+ 0xc8 0x00 0x00
+ 0x18c 0x00 0x00
+ 0xcc 0x00 0x00
+ 0x128 0x00 0x00
+ 0x0c 0x0a 0x00
+ 0x10 0x01 0x00
+ 0x1c 0x31 0x00
+ 0x20 0x01 0x00
+ 0x14 0x00 0x00
+ 0x18 0x00 0x00
+ 0x24 0xde 0x00
+ 0x28 0x07 0x00
+ 0x48 0x0f 0x00
+ 0x194 0x06 0x00
+ 0x100 0x80 0x00
+ 0xa8 0x01 0x00
+ 0x430 0x0b 0x00
+ 0x830 0x0b 0x00
+ 0x444 0x00 0x00
+ 0x844 0x00 0x00
+ 0x43c 0x00 0x00
+ 0x83c 0x00 0x00
+ 0x440 0x00 0x00
+ 0x840 0x00 0x00
+ 0x408 0x0a 0x00
+ 0x808 0x0a 0x00
+ 0x414 0x06 0x00
+ 0x814 0x06 0x00
+ 0x434 0x75 0x00
+ 0x834 0x75 0x00
+ 0x4d4 0x02 0x00
+ 0x8d4 0x02 0x00
+ 0x4d8 0x4e 0x00
+ 0x8d8 0x4e 0x00
+ 0x4dc 0x18 0x00
+ 0x8dc 0x18 0x00
+ 0x4f8 0x77 0x00
+ 0x8f8 0x77 0x00
+ 0x4fc 0x80 0x00
+ 0x8fc 0x80 0x00
+ 0x4c0 0x0a 0x00
+ 0x8c0 0x0a 0x00
+ 0x504 0x03 0x00
+ 0x904 0x03 0x00
+ 0x50c 0x16 0x00
+ 0x90c 0x16 0x00
+ 0x500 0x00 0x00
+ 0x900 0x00 0x00
+ 0x564 0x00 0x00
+ 0x964 0x00 0x00
+ 0x260 0x10 0x00
+ 0x660 0x10 0x00
+ 0x2a4 0x12 0x00
+ 0x6a4 0x12 0x00
+ 0x28c 0xc6 0x00
+ 0x68c 0xc6 0x00
+ 0x244 0x00 0x00
+ 0x644 0x00 0x00
+ 0x248 0x00 0x00
+ 0x648 0x00 0x00
+ 0xc0c 0x9f 0x00
+ 0xc24 0x17 0x00
+ 0xc28 0x0f 0x00
+ 0xcc8 0x83 0x00
+ 0xcc4 0x02 0x00
+ 0xccc 0x09 0x00
+ 0xcd0 0xa2 0x00
+ 0xcd4 0x85 0x00
+ 0xc80 0xd1 0x00
+ 0xc84 0x1f 0x00
+ 0xc88 0x47 0x00
+ 0xcb8 0x75 0x00
+ 0xcbc 0x13 0x00
+ 0xcb0 0x86 0x00
+ 0xca0 0x04 0x00
+ 0xc8c 0x44 0x00
+ 0xc70 0xe7 0x00
+ 0xc74 0x03 0x00
+ 0xc78 0x40 0x00
+ 0xc7c 0x00 0x00
+ 0xdd8 0x88 0x00
+ 0xffffffff 0xffffffff 0x00>;
+
+ qcom,qmp-phy-reg-offset =
+ <0xd74 /* USB3_PHY_PCS_STATUS */
+ 0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */
+ 0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */
+ 0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */
+ 0xc00 /* USB3_PHY_SW_RESET */
+ 0xc08 /* USB3_PHY_START */
+ 0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */
+
+ clocks = <&clock_gcc GCC_USB3_PHY_AUX_CLK>,
+ <&clock_gcc GCC_USB3_PHY_PIPE_CLK>,
+ <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&clock_rpmcc RPM_SMD_LN_BB_CLK1>,
+ <&clock_gcc GCC_USB3_CLKREF_CLK>;
+
+ clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk",
+ "ref_clk_src", "ref_clk";
+
+ resets = <&clock_gcc GCC_USB3_PHY_BCR>,
+ <&clock_gcc GCC_USB3PHY_PHY_BCR>;
+ reset-names = "phy_reset", "phy_phy_reset";
+ };
+
+ usb_audio_qmi_dev {
+ compatible = "qcom,usb-audio-qmi-dev";
+ iommus = <&lpass_q6_smmu 6>;
+ qcom,iommu-dma = "disabled";
+ qcom,usb-audio-stream-id = <6>;
+ qcom,usb-audio-intr-num = <2>;
+ };
+
+ usb2s: hsusb@c200000 {
+ compatible = "qcom,dwc-usb3-msm";
+ reg = <0x0c200000 0xfc000>,
+ <0x0c016000 0x400>;
+ reg-names = "core_base",
+ "ahb2phy_base";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>, <0 144 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq", "pwr_event_irq";
+
+ qcom,msm-bus,name = "usb-hs";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <87 512 0 0>,
+ <87 512 60000 800000>;
+
+ qcom,pm-qos-latency = <52>; /* CPU-CLUSTER-WFI-LVL latency +1 */
+ clocks = <&clock_gcc GCC_USB20_MASTER_CLK>,
+ <&clock_gcc GCC_CFG_NOC_USB2_AXI_CLK>,
+ <&clock_gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&clock_gcc GCC_USB20_SLEEP_CLK>,
+ <&clock_rpmcc CXO_DWC3_CLK>,
+ <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+ clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",
+ "xo", "cfg_ahb_clk";
+ qcom,core-clk-rate = <60000000>;
+ resets = <&clock_gcc GCC_USB_20_BCR>;
+ reset-names = "core_reset";
+
+ status = "disabled";
+ dwc3@c200000 {
+ compatible = "snps,dwc3";
+ reg = <0x0c200000 0xc8d0>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
+ usb-phy = <&qusb_phy1>, <&usb_nop_phy>;
+ maximum-speed = "high-speed";
+ snps,is-utmi-l1-suspend;
+ snps,hird-threshold = /bits/ 8 <0x0>;
+ dr_mode = "host";
+ linux,sysdev_is_parent;
+ snps,dis_enblslpm_quirk;
+ snps,dis_u2_susphy_quirk;
+ usb-core-id = <1>;
+ };
+ };
+
+ qusb_phy1: qusb@c014000 {
+ compatible = "qcom,qusb2phy";
+ reg = <0x0c014000 0x180>,
+ <0x00188014 0x4>;
+ reg-names = "qusb_phy_base",
+ "ref_clk_addr";
+ vdd-supply = <&pm660l_l1>;
+ vdda18-supply = <&pm660_l10>;
+ vdda33-supply = <&pm660l_l7>;
+ qcom,vdd-voltage-level = <0 925000 925000>;
+ qcom,qusb-phy-init-seq = <0xF8 0x80
+ 0xB3 0x84
+ 0x83 0x88
+ 0xC0 0x8C
+ 0x30 0x08
+ 0x79 0x0C
+ 0x21 0x10
+ 0x14 0x9C
+ 0x9F 0x1C
+ 0x00 0x18>;
+ phy_type = "utmi";
+ qcom,phy-clk-scheme = "cml";
+ qcom,major-rev = <1>;
+ qcom,hold-reset;
+
+ clocks = <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&clock_gcc GCC_RX1_USB2_CLKREF_CLK>,
+ <&clock_rpmcc RPM_SMD_LN_BB_CLK1>;
+ clock-names = "cfg_ahb_clk", "ref_clk", "ref_clk_src";
+
+ resets = <&clock_gcc GCC_QUSB2PHY_SEC_BCR>;
+ reset-names = "phy_reset";
+ };
+
+ usb_nop_phy: usb_nop_phy {
+ compatible = "usb-nop-xceiv";
+ };
+
+ sdhc_1: sdhci@c0c4000 {
+ compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe";
+ reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>,
+ <0xc0c8000 0x8000>;
+ reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";
+
+ interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>, <0 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <8>;
+ qcom,large-address-bus;
+
+ qcom,devfreq,freq-table = <50000000 200000000>;
+
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <43 518>;
+ qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
+ qcom,pm-qos-cmdq-latency-us = <43 518>, <40 518>;
+ qcom,pm-qos-legacy-latency-us = <43 518>, <40 518>;
+
+ qcom,msm-bus,name = "sdhc1";
+ qcom,msm-bus,num-cases = <9>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <78 512 0 0>, <1 606 0 0>,
+ /* 400 KB/s*/
+ <78 512 1046 1600>,
+ <1 606 1600 1600>,
+ /* 20 MB/s */
+ <78 512 52286 80000>,
+ <1 606 80000 80000>,
+ /* 25 MB/s */
+ <78 512 65360 100000>,
+ <1 606 100000 100000>,
+ /* 50 MB/s */
+ <78 512 130718 200000>,
+ <1 606 133320 133320>,
+ /* 100 MB/s */
+ <78 512 130718 200000>,
+ <1 606 150000 150000>,
+ /* 200 MB/s */
+ <78 512 261438 400000>,
+ <1 606 300000 300000>,
+ /* 400 MB/s */
+ <78 512 261438 400000>,
+ <1 606 300000 300000>,
+ /* Max. bandwidth */
+ <78 512 1338562 4096000>,
+ <1 606 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100000000 200000000 400000000 4294967295>;
+
+ clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,
+ <&clock_gcc GCC_SDCC1_APPS_CLK>,
+ <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface_clk", "core_clk", "ice_core_clk";
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
+ 192000000 384000000>;
+
+ qcom,nonremovable;
+ qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+
+ qcom,ice-clk-rates = <300000000 75000000>;
+
+ qcom,scaling-lower-bus-speed-mode = "DDR52";
+
+ status = "disabled";
+ };
+
+ sdhc_2: sdhci@c084000 {
+ compatible = "qcom,sdhci-msm-v5";
+ reg = <0xc084000 0x1000>;
+ reg-names = "hc_mem";
+
+ interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <4>;
+ qcom,large-address-bus;
+
+ qcom,msm-bus,name = "sdhc2";
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <81 512 0 0>, <1 608 0 0>,
+ /* 400 KB/s*/
+ <81 512 1046 1600>,
+ <1 608 1600 1600>,
+ /* 20 MB/s */
+ <81 512 52286 80000>,
+ <1 608 80000 80000>,
+ /* 25 MB/s */
+ <81 512 65360 100000>,
+ <1 608 100000 100000>,
+ /* 50 MB/s */
+ <81 512 130718 200000>,
+ <1 608 133320 133320>,
+ /* 100 MB/s */
+ <81 512 261438 200000>,
+ <1 608 150000 150000>,
+ /* 200 MB/s */
+ <81 512 261438 400000>,
+ <1 608 300000 300000>,
+ /* Max. bandwidth */
+ <81 512 1338562 4096000>,
+ <1 608 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100000000 200000000 4294967295>;
+
+ qcom,devfreq,freq-table = <50000000 200000000>;
+
+ qcom,pm-qos-irq-type = "affine_irq";
+ qcom,pm-qos-irq-latency = <43 518>;
+ qcom,pm-qos-cpu-groups = <0x0f 0xf0>;
+ qcom,pm-qos-legacy-latency-us = <43 518>, <40 518>;
+
+ clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
+ <&clock_gcc GCC_SDCC2_APPS_CLK>;
+ clock-names = "iface_clk", "core_clk";
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
+ 200000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
+ "SDR104";
+
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-coresight.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-coresight.dtsi
new file mode 100755
index 0000000..0758d73
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-coresight.dtsi
@@ -0,0 +1,1687 @@
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+#include <dt-bindings/clock/qcom,gpu-sdm660.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+
+&soc {
+ csr: csr@6001000 {
+ compatible = "qcom,coresight-csr";
+ reg = <0x6001000 0x1000>;
+ reg-names = "csr-base";
+
+ coresight-name = "coresight-csr";
+ qcom,usb-bam-support;
+ qcom,hwctrl-set-support;
+ qcom,set-byte-cntr-support;
+ qcom,blk-size = <1>;
+ };
+
+ tmc_etr: tmc@6048000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+
+ reg = <0x6048000 0x1000>,
+ <0x6064000 0x15000>;
+ reg-names = "tmc-base", "bam-base";
+
+ arm,buffer-size = <0x400000>;
+ arm,scatter-gather;
+ arm,default-sink;
+ coresight-csr = <&csr>;
+
+ coresight-ctis = <&cti0 &cti8>;
+
+ coresight-name = "coresight-tmc-etr";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ port{
+ tmc_etr_in_replicator: endpoint {
+ slave-mode;
+ remote-endpoint = <&replicator_out_tmc_etr>;
+ };
+ };
+ };
+
+ replicator_qdss: replicator@6046000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb909>;
+
+ reg = <0x6046000 0x1000>;
+ reg-names = "replicator-base";
+
+ coresight-name = "coresight-replicator-qdss";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ ports{
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ replicator_out_tmc_etr:endpoint {
+ remote-endpoint =
+ <&tmc_etr_in_replicator>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ replicator_in_tmc_etf:endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tmc_etf_out_replicator>;
+ };
+ };
+ };
+ };
+
+ tmc_etf: tmc@6047000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb961>;
+
+ reg = <0x6047000 0x1000>;
+ reg-names = "tmc-base";
+
+ coresight-name = "coresight-tmc-etf";
+
+ coresight-ctis = <&cti0 &cti8>;
+ coresight-csr = <&csr>;
+ arm,default-sink;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ ports{
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ tmc_etf_out_replicator:endpoint {
+ remote-endpoint =
+ <&replicator_in_tmc_etf>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ tmc_etf_in_funnel_merg:endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_merg_out_tmc_etf>;
+ };
+ };
+ };
+ };
+
+ funnel_merg: funnel@6045000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6045000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-merg";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_merg_out_tmc_etf:endpoint {
+ remote-endpoint =
+ <&tmc_etf_in_funnel_merg>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ funnel_merg_in_funnel_in0:endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_in0_out_funnel_merg>;
+ };
+ };
+ port@2 {
+ reg = <1>;
+ funnel_merg_in_funnel_in1:endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_in1_out_funnel_merg>;
+ };
+ };
+ };
+ };
+
+ funnel_in0: funnel@6041000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6041000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-in0";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_in0_out_funnel_merg: endpoint {
+ remote-endpoint =
+ <&funnel_merg_in_funnel_in0>;
+ };
+ };
+ port@2 {
+ reg = <6>;
+ funnel_in0_in_funnel_qatb: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_qatb_out_funnel_in0>;
+ };
+ };
+ port@3 {
+ reg = <7>;
+ funnel_in0_in_stm: endpoint {
+ slave-mode;
+ remote-endpoint = <&stm_out_funnel_in0>;
+ };
+ };
+ port@4 {
+ reg = <0>;
+ funnel_in0_in_rpm_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&rpm_etm0_out_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel_in1: funnel@6042000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6042000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-in1";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_in1_out_funnel_merg: endpoint {
+ remote-endpoint =
+ <&funnel_merg_in_funnel_in1>;
+ };
+ };
+ port@1 {
+ reg = <2>;
+ funnel_in1_in_tpda_nav: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_nav_out_funnel_in1>;
+ };
+ };
+ port@2 {
+ reg = <5>;
+ funnel_in1_in_modem_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&modem_etm0_out_funnel_in1>;
+ };
+ };
+ port@3 {
+ reg = <6>;
+ funnel_in1_in_funnel_apss_merg: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_apss_merg_out_funnel_in1>;
+ };
+ };
+ port@4 {
+ reg = <4>;
+ funnel_in1_in_turing_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&turing_etm0_out_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ funnel_apss_merg: funnel@7b70000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x7b70000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-apss-merg";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_apss_merg_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_funnel_apss_merg>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ funnel_apss_merg_in_funnel_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_apss_out_funnel_apss_merg>;
+ };
+ };
+ port@2 {
+ reg = <1>;
+ funnel_apss_merg_in_tpda_olc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_olc_out_funnel_apss_merg>;
+ };
+ };
+ port@3 {
+ reg = <3>;
+ funnel_apss_merg_in_tpda_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_apss_out_funnel_apss_merg>;
+ };
+ };
+ };
+ };
+
+ funnel_apss: funnel@7b60000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x7b60000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-apss";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_apss_out_funnel_apss_merg: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merg_in_funnel_apss>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ funnel_apss_in_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm0_out_funnel_apss>;
+ };
+ };
+ port@2 {
+ reg = <1>;
+ funnel_apss_in_etm1: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm1_out_funnel_apss>;
+ };
+ };
+ port@3 {
+ reg = <2>;
+ funnel_apss_in_etm2: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm2_out_funnel_apss>;
+ };
+ };
+ port@4 {
+ reg = <3>;
+ funnel_apss_in_etm3: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm3_out_funnel_apss>;
+ };
+ };
+ port@5 {
+ reg = <4>;
+ funnel_apss_in_etm4: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm4_out_funnel_apss>;
+ };
+ };
+ port@6 {
+ reg = <5>;
+ funnel_apss_in_etm5: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm5_out_funnel_apss>;
+ };
+ };
+ port@7 {
+ reg = <6>;
+ funnel_apss_in_etm6: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm6_out_funnel_apss>;
+ };
+ };
+ port@8 {
+ reg = <7>;
+ funnel_apss_in_etm7: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&etm7_out_funnel_apss>;
+ };
+ };
+ };
+ };
+
+ stm: stm@6002000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb962>;
+
+ reg = <0x6002000 0x1000>,
+ <0x16280000 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ coresight-name = "coresight-stm";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ port{
+ stm_out_funnel_in0: endpoint {
+ remote-endpoint = <&funnel_in0_in_stm>;
+ };
+ };
+ };
+
+ etm0: etm@7840000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7840000 0x1000>;
+ cpu = <&CPU0>;
+
+ coresight-name = "coresight-etm0";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ port{
+ etm0_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm0>;
+ };
+ };
+ };
+
+ etm1: etm@7940000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7940000 0x1000>;
+ cpu = <&CPU1>;
+
+ coresight-name = "coresight-etm1";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ port{
+ etm1_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm1>;
+ };
+ };
+ };
+
+ etm2: etm@7a40000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7a40000 0x1000>;
+ cpu = <&CPU2>;
+
+ coresight-name = "coresight-etm2";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ port{
+ etm2_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm2>;
+ };
+ };
+ };
+
+ etm3: etm@7b40000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7b40000 0x1000>;
+ cpu = <&CPU3>;
+
+ coresight-name = "coresight-etm3";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ port{
+ etm3_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm3>;
+ };
+ };
+ };
+
+ etm4: etm@7c40000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7c40000 0x1000>;
+ cpu = <&CPU4>;
+
+ coresight-name = "coresight-etm4";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ port{
+ etm4_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm4>;
+ };
+ };
+ };
+
+ etm5: etm@7d40000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7d40000 0x1000>;
+ cpu = <&CPU5>;
+
+ coresight-name = "coresight-etm5";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ port{
+ etm5_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm5>;
+ };
+ };
+ };
+
+ etm6: etm@7e40000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7e40000 0x1000>;
+ cpu = <&CPU6>;
+
+ coresight-name = "coresight-etm6";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ port{
+ etm6_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm6>;
+ };
+ };
+ };
+
+ etm7: etm@7f40000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb95d>;
+
+ reg = <0x7f40000 0x1000>;
+ cpu = <&CPU7>;
+
+ coresight-name = "coresight-etm7";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ port{
+ etm7_out_funnel_apss: endpoint {
+ remote-endpoint = <&funnel_apss_in_etm7>;
+ };
+ };
+ };
+
+ cti0: cti@6010000 {
+ compatible = "arm,primecell";
+ reg = <0x6010000 0x1000>;
+ arm,primecell-periphid = <0x000bb966>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti0";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti1: cti@6011000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6011000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti1";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti2: cti@6012000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6012000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti2";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ qcom,cti-gpio-trigout = <4>;
+ pinctrl-names = "cti-trigout-pctrl";
+ pinctrl-0 = <&trigout_a>;
+ };
+
+ cti3: cti@6013000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6013000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti3";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti4: cti@6014000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6014000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti4";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti5: cti@6015000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6015000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti5";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti6: cti@6016000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6016000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti6";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti7: cti@6017000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6017000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti7";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti8: cti@6018000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6018000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti8";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti9: cti@6019000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x6019000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti9";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti10: cti@601a000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601a000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti10";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti11: cti@601b000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601b000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti11";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti12: cti@601c000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601c000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti12";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti13: cti@601d000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601d000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti13";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti14: cti@601e000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601e000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti14";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti15: cti@601f000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x601f000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti15";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_cpu0: cti@7820000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+
+ reg = <0x7820000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu0";
+ cpu = <&CPU0>;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_cpu1: cti@7920000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7920000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu1";
+ cpu = <&CPU1>;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_cpu2: cti@7a20000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7a20000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu2";
+ cpu = <&CPU2>;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_cpu3: cti@7b20000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7b20000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu3";
+ cpu = <&CPU3>;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_cpu4: cti@7c20000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7c20000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu4";
+ cpu = <&CPU4>;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_cpu5: cti@7d20000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7d20000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu5";
+ cpu = <&CPU5>;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_cpu6: cti@7e20000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7e20000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu6";
+ cpu = <&CPU6>;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_cpu7: cti@7f20000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7f20000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-cpu7";
+ cpu = <&CPU7>;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_apss: cti@7b80000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7b80000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_apss_dl: cti@7bc1000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7bc1000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-apss-dl";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_olc: cti@7b91000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7b91000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-olc";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_turing: cti@7068000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7068000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-turing";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_wcss0: cti@71a4000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x71a4000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-wcss0";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ status = "disabled";
+ };
+
+ cti_wcss1: cti@71a5000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x71a5000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-wcss1";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ status = "disabled";
+ };
+
+ cti_wcss2: cti@71a6000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x71a6000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-wcss2";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ status = "disabled";
+ };
+
+ cti_mmss: cti@7188000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7188000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-mmss";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_isdb: cti@7121000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7121000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-isdb";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ status = "disabled";
+ };
+
+ cti_rpm: cti@7048000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7048000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-rpm";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ cti_mss: cti@7041000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb966>;
+ reg = <0x7041000 0x1000>;
+ reg-names = "cti-base";
+
+ coresight-name = "coresight-cti-mss";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+ };
+
+ funnel_qatb: funnel@6005000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x6005000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-qatb";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_qatb_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_funnel_qatb>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ funnel_qatb_in_tpda: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_out_funnel_qatb>;
+ };
+ };
+ port@2 {
+ reg = <3>;
+ funnel_qatb_in_funnel_dlct: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dlct_out_funnel_qatb>;
+ };
+ };
+ };
+ };
+
+ tpda: tpda@6004000 {
+ compatible = "qcom,coresight-tpda";
+ reg = <0x6004000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda";
+
+ qcom,tpda-atid = <65>;
+ qcom,bc-elem-size = <8 32>,
+ <10 32>;
+ qcom,tc-elem-size = <4 32>,
+ <7 32>,
+ <10 32>;
+ qcom,dsb-elem-size = <2 32>,
+ <8 32>,
+ <10 32>,
+ <11 32>;
+ qcom,cmb-elem-size = <4 32>,
+ <5 32>,
+ <6 32>,
+ <10 64>;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_tpda>;
+ };
+ };
+ port@2 {
+ reg = <2>;
+ tpda_in_funnel_dlct: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&funnel_dlct_out_tpda>;
+ };
+ };
+ port@3 {
+ reg = <4>;
+ tpda_in_tpdm_vsense: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_vsense_out_tpda>;
+ };
+ };
+ port@4 {
+ reg = <5>;
+ tpda_in_tpdm_dcc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dcc_out_tpda>;
+ };
+ };
+ port@5 {
+ reg = <6>;
+ tpda_in_tpdm_prng: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_prng_out_tpda>;
+ };
+ };
+ port@6 {
+ reg = <8>;
+ tpda_in_tpdm_qm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_qm_out_tpda>;
+ };
+ };
+ port@7 {
+ reg = <10>;
+ tpda_in_tpdm_pimem: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_pimem_out_tpda>;
+ };
+ };
+ port@8 {
+ reg = <11>;
+ tpda_in_tpdm: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_out_tpda>;
+ };
+ };
+ };
+ };
+
+ tpdm_vsense: tpdm@7038000 {
+ compatible = "qcom,coresight-tpdm";
+ reg = <0x7038000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-vsense";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ port{
+ tpdm_vsense_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_vsense>;
+ };
+ };
+ };
+
+ tpdm_dcc: tpdm@7054000 {
+ compatible = "qcom,coresight-tpdm";
+ reg = <0x7054000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dcc";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ port{
+ tpdm_dcc_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_dcc>;
+ };
+ };
+ };
+
+ tpdm_prng: tpdm@704c000 {
+ compatible = "qcom,coresight-tpdm";
+ reg = <0x704c000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-prng";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ port{
+ tpdm_prng_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_prng>;
+ };
+ };
+ };
+
+ tpdm_qm: tpdm@71d0000 {
+ compatible = "qcom,coresight-tpdm";
+ reg = <0x71d0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-qm";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ port{
+ tpdm_qm_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_qm>;
+ };
+ };
+ };
+
+ tpdm_pimem: tpdm@7050000 {
+ compatible = "qcom,coresight-tpdm";
+ reg = <0x7050000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-pimem";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ port{
+ tpdm_pimem_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm_pimem>;
+ };
+ };
+ };
+
+ tpdm: tpdm@6006000 {
+ compatible = "qcom,coresight-tpdm";
+ reg = <0x6006000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm";
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ port{
+ tpdm_out_tpda: endpoint {
+ remote-endpoint = <&tpda_in_tpdm>;
+ };
+ };
+ };
+
+ tpda_nav: tpda@7191000 {
+ compatible = "qcom,coresight-tpda";
+ reg = <0x7191000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-nav";
+
+ qcom,tpda-atid = <68>;
+ qcom,cmb-elem-size = <0 32>;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_nav_out_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel_in1_in_tpda_nav>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ tpda_nav_in_tpdm_nav: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_nav_out_tpda_nav>;
+ };
+ };
+ };
+ };
+
+ tpda_apss: tpda@7bc2000 {
+ compatible = "qcom,coresight-tpda";
+ reg = <0x7bc2000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-apss";
+
+ qcom,tpda-atid = <66>;
+ qcom,dsb-elem-size = <0 32>;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_apss_out_funnel_apss_merg: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merg_in_tpda_apss>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ tpda_apss_in_tpdm_apss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_apss_out_tpda_apss>;
+ };
+ };
+ };
+ };
+
+ tpdm_apss: tpdm@7bc0000 {
+ compatible = "qcom,coresight-tpdm";
+ reg = <0x7bc0000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-apss";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ port{
+ tpdm_apss_out_tpda_apss: endpoint {
+ remote-endpoint = <&tpda_apss_in_tpdm_apss>;
+ };
+ };
+ };
+
+ tpda_mss: tpda@7043000 {
+ compatible = "qcom,coresight-tpda";
+ reg = <0x7043000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-mss";
+
+ qcom,tpda-atid = <67>;
+ qcom,dsb-elem-size = <0 32>;
+ qcom,cmb-elem-size = <0 32>;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_mss_out_funnel_dlct: endpoint {
+ remote-endpoint =
+ <&funnel_dlct_in_tpda_mss>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ tpda_mss_in_tpdm_mss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_mss_out_tpda_mss>;
+ };
+ };
+ };
+ };
+
+ tpdm_mss: tpdm@7042000 {
+ compatible = "qcom,coresight-tpdm";
+ reg = <0x7042000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-mss";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ port{
+ tpdm_mss_out_tpda_mss: endpoint {
+ remote-endpoint = <&tpda_mss_in_tpdm_mss>;
+ };
+ };
+ };
+
+ tpdm_nav: tpdm@7190000 {
+ compatible = "qcom,coresight-tpdm";
+ reg = <0x7190000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-nav";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ port{
+ tpdm_nav_out_tpda_nav: endpoint {
+ remote-endpoint = <&tpda_nav_in_tpdm_nav>;
+ };
+ };
+ };
+
+ tpda_olc: tpda@7b92000 {
+ compatible = "qcom,coresight-tpda";
+ reg = <0x7b92000 0x1000>;
+ reg-names = "tpda-base";
+
+ coresight-name = "coresight-tpda-olc";
+
+ qcom,tpda-atid = <69>;
+ qcom,cmb-elem-size = <0 64>;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ tpda_olc_out_funnel_apss_merg: endpoint {
+ remote-endpoint =
+ <&funnel_apss_merg_in_tpda_olc>;
+ };
+ };
+ port@1 {
+ reg = <0>;
+ tpda_olc_in_tpdm_olc: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_olc_out_tpda_olc>;
+ };
+ };
+ };
+ };
+
+ tpdm_olc: tpdm@7b90000 {
+ compatible = "qcom,coresight-tpdm";
+ reg = <0x7b90000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-olc";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ port{
+ tpdm_olc_out_tpda_olc: endpoint {
+ remote-endpoint = <&tpda_olc_in_tpdm_olc>;
+ };
+ };
+ };
+
+ funnel_dlct: funnel@71c3000 {
+ compatible = "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0x71c3000 0x1000>;
+ reg-names = "funnel-base";
+
+ coresight-name = "coresight-funnel-dlct";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "core_a_clk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_dlct_out_tpda: endpoint {
+ remote-endpoint =
+ <&tpda_in_funnel_dlct>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ funnel_dlct_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_funnel_dlct>;
+ };
+ };
+ port@2 {
+ reg = <0>;
+ funnel_dlct_in_tpdm_dlct: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpdm_dlct_out_funnel_dlct>;
+ };
+ };
+ port@4 {
+ reg = <1>;
+ funnel_dlct_in_audio_etm0: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&audio_etm0_out_funnel_dlct>;
+ };
+ };
+ port@5 {
+ reg = <2>;
+ funnel_dlct_in_tpda_mss: endpoint {
+ slave-mode;
+ remote-endpoint =
+ <&tpda_mss_out_funnel_dlct>;
+ };
+ };
+ };
+ };
+
+ tpdm_dlct: tpdm@71c2000 {
+ compatible = "qcom,coresight-tpdm";
+ reg = <0x71c2000 0x1000>;
+ reg-names = "tpdm-base";
+
+ coresight-name = "coresight-tpdm-dlct";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ port{
+ tpdm_dlct_out_funnel_dlct: endpoint {
+ remote-endpoint = <&funnel_dlct_in_tpdm_dlct>;
+ };
+ };
+ };
+
+ hwevent: hwevent@158000 {
+ compatible = "qcom,coresight-hwevent";
+ reg = <0x158000 0x80>,
+ <0x17091000 0x80>,
+ <0x1730200c 0x4>,
+ <0xc90137c 0x4>,
+ <0xc828018 0x80>,
+ <0x1c00058 0x80>,
+ <0x5e02038 0x4>,
+ <0x5e02028 0x10>,
+ <0x1fcb360 0x80>,
+ <0x1fcb760 0x80>,
+ <0x1fcbf60 0x80>,
+ <0xa8f8860 0x4>,
+ <0x500c260 0x4>,
+ <0x500d040 0x4>,
+ <0x1da6400 0x80>;
+ reg-names = "gcc-ctrl", "lpass-stm", "lpass-qdsp", "mdss-mdp",
+ "mdss-misc", "pcie0-hwev", "ssc-en", "ssc-hwev",
+ "tcsr-qdss", "tcsr-mss0", "tcsr-mss1", "usb-ctrl",
+ "vbif-stm", "vbif-stm-en", "ufs-mux";
+
+ coresight-name = "coresight-hwevent";
+ coresight-csr = <&csr>;
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>,
+ <&clock_mmss MMSS_MISC_AHB_CLK>;
+ clock-names = "apb_pclk", "core_a_clk", "core_mmss_clk";
+
+ qcom,hwevent-clks = "core_mmss_clk";
+ };
+
+
+ modem_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-modem-etm0";
+ qcom,inst-id = <2>;
+
+ port{
+ modem_etm0_out_funnel_in1: endpoint {
+ remote-endpoint = <&funnel_in1_in_modem_etm0>;
+ };
+ };
+ };
+
+ audio_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-audio-etm0";
+ qcom,inst-id = <5>;
+
+ port{
+ audio_etm0_out_funnel_dlct: endpoint {
+ remote-endpoint = <&funnel_dlct_in_audio_etm0>;
+ };
+ };
+ };
+
+ rpm_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-rpm-etm0";
+ qcom,inst-id = <4>;
+
+ port{
+ rpm_etm0_out_funnel_in0: endpoint {
+ remote-endpoint = <&funnel_in0_in_rpm_etm0>;
+ };
+ };
+ };
+
+ turing_etm0 {
+ compatible = "qcom,coresight-remote-etm";
+
+ coresight-name = "coresight-turing-etm0";
+ qcom,inst-id = <13>;
+
+ port{
+ turing_etm0_out_funnel_in1: endpoint {
+ remote-endpoint = <&funnel_in1_in_turing_etm0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-external-codec.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-external-codec.dtsi
new file mode 100755
index 0000000..3830da9
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-external-codec.dtsi
@@ -0,0 +1,23 @@
+&cdc_pdm_gpios {
+ status = "disabled";
+};
+
+&cdc_comp_gpios {
+ status = "disabled";
+};
+
+&cdc_dmic_gpios {
+ status = "disabled";
+};
+
+&cdc_sdw_gpios {
+ status = "disabled";
+};
+
+&wsa_spkr_en1 {
+ status = "disabled";
+};
+
+&wsa_spkr_en2 {
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-gpu.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-gpu.dtsi
new file mode 100755
index 0000000..c8346e5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-gpu.dtsi
@@ -0,0 +1,692 @@
+&soc {
+ pil_gpu: qcom,kgsl-hyp {
+ compatible = "qcom,pil-tz-generic";
+ qcom,pas-id = <13>;
+ qcom,firmware-name = "a512_zap";
+ };
+
+ msm_bus: qcom,kgsl-busmon{
+ label = "kgsl-busmon";
+ compatible = "qcom,kgsl-busmon";
+ };
+
+ gpu_bw_tbl: gpu-bw-tbl {
+ compatible = "operating-points-v2";
+ opp-0 { opp-hz = /bits/ 64 < 0 >; }; /* OFF */
+ opp-100 { opp-hz = /bits/ 64 < 381 >; }; /* 1.100 MHz */
+ opp-150 { opp-hz = /bits/ 64 < 572 >; }; /* 2.150 MHz */
+ opp-200 { opp-hz = /bits/ 64 < 762 >; }; /* 3.200 MHz */
+ opp-300 { opp-hz = /bits/ 64 < 1144 >; }; /* 4.300 MHz */
+ opp-412 { opp-hz = /bits/ 64 < 1571 >; }; /* 5.412 MHz */
+ opp-547 { opp-hz = /bits/ 64 < 2086 >; }; /* 6.547 MHz */
+ opp-681 { opp-hz = /bits/ 64 < 2597 >; }; /* 7.681 MHz */
+ opp-768 { opp-hz = /bits/ 64 < 2929 >; }; /* 8.768 MHz */
+ opp-1017 { opp-hz = /bits/ 64 < 3879 >; }; /* 9.1017 MHz */
+ opp-1296 { opp-hz = /bits/ 64 < 4943 >; }; /* 10.1296 MHz */
+ opp-1353 { opp-hz = /bits/ 64 < 5161 >; }; /* 11.1353 MHz */
+ opp-1555 { opp-hz = /bits/ 64 < 5931 >; }; /* 12.1555 MHz */
+ opp-1804 { opp-hz = /bits/ 64 < 6881 >; }; /* 13.1804 MHz */
+ };
+
+ gpubw: qcom,gpubw {
+ compatible = "qcom,devbw";
+ governor = "bw_vbif";
+ qcom,src-dst-ports = <26 512>;
+ operating-points-v2 = <&gpu_bw_tbl>;
+ /*
+ * active-only flag is used while registering the bus
+ * governor. It helps release the bus vote when the CPU
+ * subsystem is inactive
+ */
+ qcom,active-only;
+ };
+
+ msm_gpu: qcom,kgsl-3d0@5000000 {
+ label = "kgsl-3d0";
+ compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";
+ status = "ok";
+ reg = <0x5000000 0x40000
+ 0x780000 0x6220>;
+ reg-names = "kgsl_3d0_reg_memory", "qfprom_memory";
+ interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "kgsl_3d0_irq";
+ qcom,id = <0>;
+
+ qcom,chipid = <0x05010200>;
+
+ qcom,initial-pwrlevel = <6>;
+
+ /* <HZ/12> */
+ qcom,idle-timeout = <80>;
+
+ qcom,highest-bank-bit = <14>;
+
+ /* size in bytes */
+ qcom,snapshot-size = <1048576>;
+ #cooling-cells = <2>;
+
+ clocks = <&clock_gfx GPUCC_GFX3D_CLK>,
+ <&clock_gcc GCC_GPU_CFG_AHB_CLK>,
+ <&clock_gfx GPUCC_RBBMTIMER_CLK>,
+ <&clock_gcc GCC_GPU_BIMC_GFX_CLK>,
+ <&clock_gcc GCC_BIMC_GFX_CLK>,
+ <&clock_gpu GPUCC_RBCPR_CLK>;
+
+ clock-names = "core_clk", "iface_clk", "rbbmtimer_clk",
+ "mem_clk", "alt_mem_iface_clk", "rbcpr_clk";
+
+ /* Bus Scale Settings */
+ qcom,gpubw-dev = <&gpubw>;
+ qcom,bus-control;
+ /* GPU to BIMC bus width, VBIF data transfer in 1 cycle */
+ qcom,msm-bus,name = "grp3d";
+ qcom,msm-bus,num-cases = <14>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <26 512 0 0>,
+
+ <26 512 0 400000>, /* 1 bus=100 */
+ <26 512 0 600000>, /* 2 bus=150 */
+ <26 512 0 800000>, /* 3 bus=200 */
+ <26 512 0 1200000>, /* 4 bus=300 */
+ <26 512 0 1648000>, /* 5 bus=412 */
+ <26 512 0 2188000>, /* 6 bus=547 */
+ <26 512 0 2724000>, /* 7 bus=681 */
+ <26 512 0 3072000>, /* 8 bus=768 */
+ <26 512 0 4068000>, /* 9 bus=1017 */
+ <26 512 0 5184000>, /* 10 bus=1296 */
+ <26 512 0 5412000>, /* 11 bus=1353 */
+ <26 512 0 6220000>, /* 12 bus=1555 */
+ <26 512 0 7216000>; /* 13 bus=1804 */
+
+ /* GDSC regulator names */
+ regulator-names = "vddcx", "vdd";
+ /* GDSC oxili regulators */
+ vddcx-supply = <&gdsc_gpu_cx>;
+ vdd-supply = <&gdsc_gpu_gx>;
+
+ /* Cx ipeak limit supprt */
+ qcom,gpu-cx-ipeak = <&cx_ipeak_lm 1>;
+ qcom,gpu-cx-ipeak-clk = <700000000>;
+
+ /* CPU latency parameter */
+ qcom,pm-qos-active-latency = <518>;
+ qcom,pm-qos-wakeup-latency = <518>;
+
+ /* Quirks */
+ qcom,gpu-quirk-dp2clockgating-disable;
+ qcom,gpu-quirk-lmloadkill-disable;
+
+ /* Enable context aware freq. scaling */
+ qcom,enable-ca-jump;
+
+ /* Context aware jump busy penalty in us */
+ qcom,ca-busy-penalty = <12000>;
+
+ /* Context aware jump target power level */
+ qcom,ca-target-pwrlevel = <4>;
+
+ qcom,gpu-speed-bin = <0x41a0 0x1fe00000 21>;
+
+ /* GPU Mempools */
+ qcom,gpu-mempools {
+ #address-cells= <1>;
+ #size-cells = <0>;
+ compatible = "qcom,gpu-mempools";
+
+ qcom,mempool-max-pages = <32768>;
+
+ /* 4K Page Pool configuration */
+ qcom,gpu-mempool@0 {
+ reg = <0>;
+ qcom,mempool-page-size = <4096>;
+ };
+ /* 64K Page Pool configuration */
+ qcom,gpu-mempool@1 {
+ reg = <1>;
+ qcom,mempool-page-size = <65536>;
+ qcom,mempool-allocate;
+ };
+ };
+
+ /*
+ * Speed-bin zero is default speed bin.
+ * For rest of the speed bins, speed-bin value
+ * is calulated as FMAX/4.8 MHz round up to zero
+ * decimal places.
+ */
+ qcom,gpu-pwrlevel-bins {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible="qcom,gpu-pwrlevel-bins";
+
+ qcom,gpu-pwrlevels-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <0>;
+
+ qcom,initial-pwrlevel = <6>;
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <750000000>;
+ qcom,bus-freq = <13>;
+ qcom,bus-min = <12>;
+ qcom,bus-max = <13>;
+ };
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <700000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <11>;
+ qcom,bus-max = <13>;
+ };
+
+ /* NOM_L1 */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <647000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <12>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <588000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <12>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <11>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <370000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <6>;
+ qcom,bus-max = <9>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <266000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <6>;
+ };
+
+ /* Min SVS */
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <160000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@8 {
+ reg = <8>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <157>;
+
+ qcom,initial-pwrlevel = <6>;
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <750000000>;
+ qcom,bus-freq = <13>;
+ qcom,bus-min = <12>;
+ qcom,bus-max = <13>;
+ };
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <700000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <11>;
+ qcom,bus-max = <13>;
+ };
+
+ /* NOM_L1 */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <647000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <12>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <588000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <12>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <11>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <370000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <6>;
+ qcom,bus-max = <9>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <266000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <6>;
+ };
+
+ /* Min SVS */
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <160000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@8 {
+ reg = <8>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <146>;
+
+ qcom,initial-pwrlevel = <5>;
+
+ /* TURBO */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <700000000>;
+ qcom,bus-freq = <13>;
+ qcom,bus-min = <12>;
+ qcom,bus-max = <13>;
+ };
+
+ /* NOM_L1 */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <647000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <12>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <588000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <12>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <11>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <370000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <6>;
+ qcom,bus-max = <9>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <266000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <6>;
+ };
+
+ /* Min SVS */
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <160000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <135>;
+
+ qcom,initial-pwrlevel = <4>;
+
+ /* NOM_L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <647000000>;
+ qcom,bus-freq = <13>;
+ qcom,bus-min = <12>;
+ qcom,bus-max = <13>;
+ };
+
+ /* NOM */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <588000000>;
+ qcom,bus-freq = <10>;
+ qcom,bus-min = <9>;
+ qcom,bus-max = <12>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <11>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <370000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <6>;
+ qcom,bus-max = <9>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <266000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <6>;
+ };
+
+ /* Min SVS */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <160000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <78>;
+
+ qcom,initial-pwrlevel = <1>;
+
+ /* SVS */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <370000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <6>;
+ qcom,bus-max = <11>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <266000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <6>;
+ };
+
+ /* Min SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <160000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <90>;
+
+ qcom,initial-pwrlevel = <2>;
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <430000000>;
+ qcom,bus-freq = <11>;
+ qcom,bus-min = <10>;
+ qcom,bus-max = <11>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <370000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <6>;
+ qcom,bus-max = <11>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <266000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <6>;
+ };
+
+ /* Min SVS */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <160000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+
+ qcom,gpu-pwrlevels-6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,speed-bin = <122>;
+
+ qcom,initial-pwrlevel = <3>;
+
+ /* NOM */
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <585000000>;
+ qcom,bus-freq = <12>;
+ qcom,bus-min = <11>;
+ qcom,bus-max = <12>;
+ };
+
+ /* SVS_L1 */
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <465000000>;
+ qcom,bus-freq = <9>;
+ qcom,bus-min = <8>;
+ qcom,bus-max = <11>;
+ };
+
+ /* SVS */
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <370000000>;
+ qcom,bus-freq = <8>;
+ qcom,bus-min = <6>;
+ qcom,bus-max = <9>;
+ };
+
+ /* Low SVS */
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <266000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <6>;
+ };
+
+ /* Min SVS */
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <160000000>;
+ qcom,bus-freq = <3>;
+ qcom,bus-min = <3>;
+ qcom,bus-max = <5>;
+ };
+
+ /* XO */
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ qcom,bus-min = <0>;
+ qcom,bus-max = <0>;
+ };
+ };
+ };
+ };
+
+ kgsl_msm_iommu: qcom,kgsl-iommu {
+ compatible = "qcom,kgsl-smmu-v2";
+
+ reg = <0x05040000 0x10000>;
+ qcom,protect = <0x40000 0x10000>;
+ qcom,micro-mmu-control = <0x6000>;
+
+ clocks =<&clock_gcc GCC_GPU_CFG_AHB_CLK>,
+ <&clock_gcc GCC_GPU_BIMC_GFX_CLK>,
+ <&clock_gcc GCC_BIMC_GFX_CLK>;
+
+ clock-names = "iface_clk", "mem_clk", "alt_mem_iface_clk";
+
+ qcom,secure_align_mask = <0xfff>;
+ qcom,retention;
+ qcom,hyp_secure_alloc;
+
+ gfx3d_user: gfx3d_user {
+ compatible = "qcom,smmu-kgsl-cb";
+ label = "gfx3d_user";
+ iommus = <&kgsl_smmu 0>;
+ qcom,iommu-dma = "disabled";
+ qcom,gpu-offset = <0x48000>;
+ };
+
+ gfx3d_secure: gfx3d_secure {
+ compatible = "qcom,smmu-kgsl-cb";
+ iommus = <&kgsl_smmu 2>;
+ qcom,iommu-dma = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-headset-jacktype-no-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-headset-jacktype-no-cdp.dts
new file mode 100755
index 0000000..68c7a25
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-headset-jacktype-no-cdp.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L, Headset
+ Jacktype NO, CDP";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <1 2>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-headset-jacktype-no-rcm.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-headset-jacktype-no-rcm.dts
new file mode 100755
index 0000000..19f1311
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-headset-jacktype-no-rcm.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L, Headset
+ Jacktype NO, RCM";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <21 2>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-cdp.dts
new file mode 100755
index 0000000..334f46b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-cdp.dts
@@ -0,0 +1,15 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "sdm660-internal-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L Int. Audio
+ Codec CDP";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <1 1>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-mtp.dts
new file mode 100755
index 0000000..d71a98e
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-mtp.dts
@@ -0,0 +1,19 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-mtp.dtsi"
+#include "sdm660-internal-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L Int. Audio
+ Codec MTP";
+ compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp";
+ qcom,board-id = <8 1>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>;
+};
+
+&int_codec {
+ qcom,model = "sdm660-snd-card-mtp";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-pm660a-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-pm660a-cdp.dts
new file mode 100755
index 0000000..e6fc46c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-pm660a-cdp.dts
@@ -0,0 +1,16 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "msm-pm660a.dtsi"
+#include "sdm660-internal-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A Int. Audio
+ Codec CDP";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <1 1>;
+ qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>,
+ <0x0001001b 0x0002001a 0x0 0x0>,
+ <0x0001001b 0x0202001a 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-pm660a-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-pm660a-mtp.dts
new file mode 100755
index 0000000..ac850e7
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-pm660a-mtp.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-mtp.dtsi"
+#include "msm-pm660a.dtsi"
+#include "sdm660-internal-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A Int. Audio
+ Codec MTP";
+ compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp";
+ qcom,board-id = <8 1>;
+ qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>,
+ <0x0001001b 0x0002001a 0x0 0x0>,
+ <0x0001001b 0x0202001a 0x0 0x0>;
+};
+
+&int_codec {
+ qcom,model = "sdm660-snd-card-mtp";
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-pm660a-rcm.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-pm660a-rcm.dts
new file mode 100755
index 0000000..516fb5c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-pm660a-rcm.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "msm-pm660a.dtsi"
+#include "sdm660-internal-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A Int. Audio
+ Codec RCM";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <21 1>;
+ qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-rcm.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-rcm.dts
new file mode 100755
index 0000000..60628b2
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec-rcm.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "sdm660-internal-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L Int. Audio
+ Codec RCM";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <21 1>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec.dtsi
new file mode 100755
index 0000000..9c899be
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-internal-codec.dtsi
@@ -0,0 +1,63 @@
+&slim_aud {
+ status = "disabled";
+};
+
+&dai_slim {
+ status = "disabled";
+};
+
+&wcd9335 {
+ status = "disabled";
+};
+
+&wcd934x_cdc {
+ status = "disabled";
+};
+
+&clock_audio {
+ status = "disabled";
+};
+
+&wcd_rst_gpio {
+ status = "disabled";
+};
+
+&wcd9xxx_intc {
+ status = "disabled";
+};
+
+&tasha_snd {
+ status = "disabled";
+};
+
+&tavil_snd {
+ status = "disabled";
+};
+
+&spi_7 {
+ status = "disabled";
+};
+
+&wdsp_mgr {
+ status = "disabled";
+};
+
+&wdsp_glink {
+ status = "disabled";
+};
+
+&glink_spi_xprt_wdsp {
+ status = "disabled";
+};
+
+&int_codec {
+ status = "okay";
+};
+
+&pmic_analog_codec {
+ status = "okay";
+};
+
+&msm_sdw_codec {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-ion.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-ion.dtsi
new file mode 100755
index 0000000..e7d0cb0
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-ion.dtsi
@@ -0,0 +1,35 @@
+&soc {
+ qcom,ion {
+ compatible = "qcom,msm-ion";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ system_heap: qcom,ion-heap@25 {
+ reg = <25>;
+ qcom,ion-heap-type = "SYSTEM";
+ };
+
+ qcom,ion-heap@22 { /* ADSP HEAP */
+ reg = <22>;
+ memory-region = <&adsp_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@27 { /* QSEECOM HEAP */
+ reg = <27>;
+ memory-region = <&qseecom_mem>;
+ qcom,ion-heap-type = "DMA";
+ };
+
+ qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */
+ reg = <10>;
+ memory-region = <&secure_display_memory>;
+ qcom,ion-heap-type = "HYP_CMA";
+ };
+
+ qcom,ion-heap@9 {
+ reg = <9>;
+ qcom,ion-heap-type = "SYSTEM_SECURE";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-lpi.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-lpi.dtsi
new file mode 100755
index 0000000..418b420
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-lpi.dtsi
@@ -0,0 +1,217 @@
+&soc {
+ lpi_tlmm: lpi_pinctrl@15070000 {
+ compatible = "qcom,lpi-pinctrl";
+ reg = <0x15070000 0x0>;
+ qcom,num-gpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ qcom,lpi-offset-tbl =
+ <0x00000000>, <0x00001000>,
+ <0x00002000>, <0x00002010>,
+ <0x00003000>, <0x00003010>,
+ <0x00004000>, <0x00004010>,
+ <0x00005000>, <0x00005010>,
+ <0x00005020>, <0x00005030>,
+ <0x00006000>, <0x00006010>,
+ <0x00007000>, <0x00007010>,
+ <0x00005040>, <0x00005050>,
+ <0x00008000>, <0x00008010>,
+ <0x00008020>, <0x00008030>,
+ <0x00008040>, <0x00008050>,
+ <0x00008060>, <0x00008070>,
+ <0x00009000>, <0x00009010>,
+ <0x0000A000>, <0x0000A010>,
+ <0x0000B000>, <0x0000B010>;
+
+ lpi_mclk0_active: lpi_mclk0_active {
+ mux {
+ pins = "gpio18";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio18";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ lpi_mclk0_sleep: lpi_mclk0_sleep {
+ mux {
+ pins = "gpio18";
+ function = "func2";
+ };
+
+ config {
+ pins = "gpio18";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cdc_pdm_gpios_active: cdc_pdm_gpios_active {
+ mux {
+ pins = "gpio18", "gpio19",
+ "gpio21", "gpio23",
+ "gpio25";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio18", "gpio19",
+ "gpio21", "gpio23",
+ "gpio25";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_pdm_gpios_sleep: cdc_pdm_gpios_sleep {
+ mux {
+ pins = "gpio18", "gpio19",
+ "gpio21", "gpio23",
+ "gpio25";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio18", "gpio19",
+ "gpio21", "gpio23",
+ "gpio25";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_pdm_2_gpios_active: cdc_pdm_2_gpios_active {
+ mux {
+ pins = "gpio20";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio20";
+ drive-strength = <8>;
+ };
+ };
+
+ cdc_pdm_2_gpios_sleep: cdc_pdm_2_gpios_sleep {
+ mux {
+ pins = "gpio20";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio20";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ cdc_comp_gpios_active: cdc_pdm_comp_gpios_active {
+ mux {
+ pins = "gpio22", "gpio24";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio22", "gpio24";
+ drive-strength = <8>;
+ };
+ };
+
+ cdc_comp_gpios_sleep: cdc_pdm_comp_gpios_sleep {
+ mux {
+ pins = "gpio22", "gpio24";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio22", "gpio24";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ lpi_cdc_reset_active: lpi_cdc_reset_active {
+ mux {
+ pins = "gpio24";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio24";
+ drive-strength = <16>;
+ output-high;
+ };
+ };
+
+ lpi_cdc_reset_sleep: lpi_cdc_reset_sleep {
+ mux {
+ pins = "gpio24";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio24";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic12_gpios_active: dmic12_gpios_active {
+ mux {
+ pins = "gpio26", "gpio28";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio26", "gpio28";
+ drive-strength = <8>;
+ output-high;
+ };
+ };
+
+ cdc_dmic12_gpios_sleep: dmic12_gpios_sleep {
+ mux {
+ pins = "gpio26", "gpio28";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio26", "gpio28";
+ drive-strength = <2>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ cdc_dmic34_gpios_active: dmic34_gpios_active {
+ mux {
+ pins = "gpio27", "gpio29";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio27", "gpio29";
+ drive-strength = <8>;
+ input-enable;
+ };
+ };
+
+ cdc_dmic34_gpios_sleep: dmic34_gpios_sleep {
+ mux {
+ pins = "gpio27", "gpio29";
+ function = "func1";
+ };
+
+ config {
+ pins = "gpio27", "gpio29";
+ drive-strength = <2>;
+ pull-down;
+ input-enable;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-mdss-panels.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-mdss-panels.dtsi
new file mode 100755
index 0000000..0b8d3ff
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-mdss-panels.dtsi
@@ -0,0 +1,357 @@
+#include "dsi-panel-sim-video.dtsi"
+#include "dsi-panel-sim-dualmipi-video.dtsi"
+#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
+#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
+#include "dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi"
+#include "dsi-panel-sharp-dualmipi-wqxga-video.dtsi"
+#include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi"
+#include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi"
+#include "dsi-panel-nt35597-dualmipi-wqxga-video.dtsi"
+#include "dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi"
+#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
+#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
+#include "dsi-panel-truly-1080p-cmd.dtsi"
+#include "dsi-panel-truly-1080p-video.dtsi"
+#include "dsi-panel-rm67195-amoled-fhd-cmd.dtsi"
+#include "dsi-panel-lgd-incell-sw49106-fhd-video.dtsi"
+#include "dsi-panel-hx8399c-fhd-plus-video.dtsi"
+
+&soc {
+ dsi_panel_pwr_supply: dsi_panel_pwr_supply {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "wqhd-vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1950000>;
+ qcom,supply-enable-load = <32000>;
+ qcom,supply-disable-load = <80>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "lab";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@2 {
+ reg = <2>;
+ qcom,supply-name = "ibb";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6000000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ qcom,supply-post-on-sleep = <10>;
+ };
+ };
+
+ dsi_panel_pwr_supply_labibb_amoled:
+ dsi_panel_pwr_supply_labibb_amoled {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "wqhd-vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1950000>;
+ qcom,supply-enable-load = <32000>;
+ qcom,supply-disable-load = <80>;
+ };
+
+ qcom,panel-supply-entry@1 {
+ reg = <1>;
+ qcom,supply-name = "vdda-3p3";
+ qcom,supply-min-voltage = <3300000>;
+ qcom,supply-max-voltage = <3300000>;
+ qcom,supply-enable-load = <13200>;
+ qcom,supply-disable-load = <80>;
+ };
+
+ qcom,panel-supply-entry@2 {
+ reg = <2>;
+ qcom,supply-name = "lab";
+ qcom,supply-min-voltage = <4600000>;
+ qcom,supply-max-voltage = <6100000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@3 {
+ reg = <3>;
+ qcom,supply-name = "ibb";
+ qcom,supply-min-voltage = <4000000>;
+ qcom,supply-max-voltage = <6300000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+
+ qcom,panel-supply-entry@4 {
+ reg = <4>;
+ qcom,supply-name = "oledb";
+ qcom,supply-min-voltage = <5000000>;
+ qcom,supply-max-voltage = <8100000>;
+ qcom,supply-enable-load = <100000>;
+ qcom,supply-disable-load = <100>;
+ };
+ };
+
+ dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,panel-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "wqhd-vddio";
+ qcom,supply-min-voltage = <1800000>;
+ qcom,supply-max-voltage = <1950000>;
+ qcom,supply-enable-load = <32000>;
+ qcom,supply-disable-load = <80>;
+ };
+ };
+};
+
+&dsi_dual_nt35597_truly_video {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 18 07 08 04 03 04 a0];
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ qcom,mdss-dsi-min-refresh-rate = <53>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-bitclk;
+ qcom,mdss-dsi-dynamic-bitclk_freq = <798240576 801594528 804948480
+ 808302432 811656384>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-t-clk-post = <0x0d>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+};
+
+&dsi_dual_nt35597_truly_cmd {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 18 07 08 04 03 04 a0];
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ qcom,mdss-dsi-tx-eot-append;
+ qcom,mdss-dsi-t-clk-post = <0x0d>;
+ qcom,mdss-dsi-t-clk-pre = <0x2d>;
+ qcom,ulps-enabled;
+};
+
+&dsi_dual_nt36850_truly_cmd {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [24 1f 08 09 05 03 04 a0
+ 24 1f 08 09 05 03 04 a0
+ 24 1f 08 09 05 03 04 a0
+ 24 1f 08 09 05 03 04 a0
+ 24 1c 08 09 05 03 04 a0];
+ qcom,mdss-dsi-t-clk-post = <0x0e>;
+ qcom,mdss-dsi-t-clk-pre = <0x31>;
+};
+
+&dsi_dual_sharp_video {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [23 20 06 09 05 03 04 a0
+ 23 20 06 09 05 03 04 a0
+ 23 20 06 09 05 03 04 a0
+ 23 20 06 09 05 03 04 a0
+ 23 2e 06 08 05 03 04 a0];
+ qcom,mdss-dsi-min-refresh-rate = <53>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+};
+
+&dsi_nt35597_truly_dsc_video {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [20 1d 05 07 03 03 04 a0
+ 20 1d 05 07 03 03 04 a0
+ 20 1d 05 07 03 03 04 a0
+ 20 1d 05 07 03 03 04 a0
+ 20 12 05 06 03 13 04 a0];
+ qcom,mdss-dsi-min-refresh-rate = <53>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+};
+
+&dsi_nt35597_truly_dsc_cmd {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [20 1d 05 07 03 03 04 a0
+ 20 1d 05 07 03 03 04 a0
+ 20 1d 05 07 03 03 04 a0
+ 20 1d 05 07 03 03 04 a0
+ 20 12 05 06 03 13 04 a0];
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+};
+
+&dsi_dual_nt35597_video {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 18 07 08 04 03 04 a0];
+ qcom,mdss-dsi-min-refresh-rate = <53>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+};
+
+&dsi_dual_nt35597_cmd {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 1e 07 08 05 03 04 a0
+ 23 18 07 08 04 03 04 a0];
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [24 1e 08 09 05 03 04 a0
+ 24 1e 08 09 05 03 04 a0
+ 24 1e 08 09 05 03 04 a0
+ 24 1e 08 09 05 03 04 a0
+ 24 1a 08 09 05 03 04 a0];
+ qcom,mdss-dsi-min-refresh-rate = <48>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [24 1e 08 09 05 03 04 a0
+ 24 1e 08 09 05 03 04 a0
+ 24 1e 08 09 05 03 04 a0
+ 24 1e 08 09 05 03 04 a0
+ 24 1a 08 09 05 03 04 a0];
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+};
+
+&dsi_truly_1080_vid {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 08 09 05 03 04 a0
+ 23 1e 08 09 05 03 04 a0
+ 23 1e 08 09 05 03 04 a0
+ 23 1e 08 09 05 03 04 a0
+ 23 1a 08 09 05 03 04 a0];
+ qcom,mdss-dsi-min-refresh-rate = <48>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update = "dfps_immediate_porch_mode_vfp";
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x1c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x1c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+
+};
+
+&dsi_truly_1080_cmd {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [23 1e 08 09 05 03 04 a0
+ 23 1e 08 09 05 03 04 a0
+ 23 1e 08 09 05 03 04 a0
+ 23 1e 08 09 05 03 04 a0
+ 23 1a 08 09 05 03 04 a0];
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
+ qcom,mdss-dsi-panel-status-value = <0x1c>;
+ qcom,mdss-dsi-panel-on-check-value = <0x1c>;
+ qcom,mdss-dsi-panel-status-read-length = <1>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+
+};
+
+&dsi_rm67195_amoled_fhd_cmd {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [24 1f 08 09 05 03 04 a0
+ 24 1f 08 09 05 03 04 a0
+ 24 1f 08 09 05 03 04 a0
+ 24 1f 08 09 05 03 04 a0
+ 24 1a 08 09 05 03 04 a0];
+ qcom,mdss-dsi-t-clk-post = <0x0d>;
+ qcom,mdss-dsi-t-clk-pre = <0x2f>;
+};
+
+
+&dsi_lgd_incell_sw49106_fhd_video {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [24 1f 08 09 05 03 04 a0
+ 24 1f 08 09 05 03 04 a0
+ 24 1f 08 09 05 03 04 a0
+ 24 1f 08 09 05 03 04 a0
+ 24 1b 08 09 05 03 04 a0];
+ qcom,mdss-dsi-t-clk-post = <0x0d>;
+ qcom,mdss-dsi-t-clk-pre = <0x30>;
+};
+
+&dsi_hx8399c_truly_vid {
+ qcom,mdss-dsi-panel-timings-phy-v2 = [24 1f 08 09 05 03 04 a0
+ 24 1f 08 09 05 03 04 a0
+ 24 1f 08 09 05 03 04 a0
+ 24 1f 08 09 05 03 04 a0
+ 24 1c 08 09 05 03 04 a0];
+ qcom,esd-check-enabled;
+ qcom,mdss-dsi-panel-status-check-mode = "reg_read";
+ qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
+ qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
+ qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>;
+ qcom,mdss-dsi-panel-status-read-length = <4>;
+ qcom,mdss-dsi-panel-max-error-count = <3>;
+ qcom,mdss-dsi-min-refresh-rate = <48>;
+ qcom,mdss-dsi-max-refresh-rate = <60>;
+ qcom,mdss-dsi-pan-enable-dynamic-fps;
+ qcom,mdss-dsi-pan-fps-update =
+ "dfps_immediate_porch_mode_vfp";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-mdss-pll.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-mdss-pll.dtsi
new file mode 100755
index 0000000..b6768c5
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-mdss-pll.dtsi
@@ -0,0 +1,108 @@
+&soc {
+ mdss_dsi0_pll: qcom,mdss_dsi_pll@c994400 {
+ compatible = "qcom,mdss_dsi_pll_sdm660";
+ status = "ok";
+ label = "MDSS DSI 0 PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+
+ reg = <0xc994400 0x588>,
+ <0xc8c2300 0x8>,
+ <0xc994200 0x98>;
+ reg-names = "pll_base", "gdsc_base", "dynamic_pll_base";
+
+ gdsc-supply = <&gdsc_mdss>;
+
+ clocks = <&clock_mmss MMSS_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+ memory-region = <&dfps_data_mem>;
+
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+
+ };
+ };
+
+ mdss_dsi1_pll: qcom,mdss_dsi_pll@c996400 {
+ compatible = "qcom,mdss_dsi_pll_sdm660";
+ status = "ok";
+ label = "MDSS DSI 1 PLL";
+ cell-index = <1>;
+ #clock-cells = <1>;
+
+ reg = <0xc996400 0x588>,
+ <0xc8c2300 0x8>,
+ <0xc996200 0x98>;
+ reg-names = "pll_base", "gdsc_base", "dynamic_pll_base";
+
+ gdsc-supply = <&gdsc_mdss>;
+
+ clocks = <&clock_mmss MMSS_MDSS_AHB_CLK>;
+ clock-names = "iface_clk";
+ clock-rate = <0>;
+ qcom,dsi-pll-ssc-en;
+ qcom,dsi-pll-ssc-mode = "down-spread";
+
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+
+ mdss_dp_pll: qcom,mdss_dp_pll@c011000 {
+ compatible = "qcom,mdss_dp_pll_sdm660";
+ status = "ok";
+ label = "MDSS DP PLL";
+ cell-index = <0>;
+ #clock-cells = <1>;
+
+ reg = <0xc011c00 0x190>,
+ <0xc011000 0x910>,
+ <0x0c8c2300 0x8>;
+ reg-names = "pll_base", "phy_base", "gdsc_base";
+
+ gdsc-supply = <&gdsc_mdss>;
+
+ clocks = <&clock_mmss MMSS_MDSS_AHB_CLK>,
+ <&clock_rpmcc RPM_SMD_LN_BB_CLK1>,
+ <&clock_gcc GCC_USB3_CLKREF_CLK>;
+ clock-names = "iface_clk", "ref_clk_src", "ref_clk";
+ clock-rate = <0>;
+
+ qcom,platform-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,platform-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-mdss.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-mdss.dtsi
new file mode 100755
index 0000000..0389edca
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-mdss.dtsi
@@ -0,0 +1,639 @@
+#include <dt-bindings/clock/mdss-14nm-pll-clk.h>
+
+&soc {
+ mdss_mdp: qcom,mdss_mdp@c900000 {
+ compatible = "qcom,mdss_mdp";
+ status = "ok";
+ reg = <0x0c900000 0x90000>,
+ <0x0c9b0000 0x1040>;
+ reg-names = "mdp_phys", "vbif_phys";
+ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #list-cells = <1>;
+
+ vdd-supply = <&gdsc_mdss>;
+
+ /* Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_mdp";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>, <23 512 0 0>,
+ <22 512 0 6400000>, <23 512 0 6400000>,
+ <22 512 0 6400000>, <23 512 0 6400000>;
+
+ /* Fudge factors */
+ qcom,mdss-ab-factor = <1 1>; /* 1 time */
+ qcom,mdss-ib-factor = <1 1>; /* 1 time */
+ qcom,mdss-clk-factor = <105 100>; /* 1.05 times */
+
+ qcom,max-mixer-width = <2560>;
+ qcom,max-pipe-width = <2560>;
+
+ qcom,max-dest-scaler-input-width = <2048>;
+ qcom,max-dest-scaler-output-width = <2560>;
+
+ /* VBIF QoS remapper settings*/
+ qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>;
+ qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>;
+ qcom,vbif-settings = <0x00ac 0x00008040>,
+ <0x00d0 0x00002828>;
+
+ qcom,mdss-cx-ipeak = <&cx_ipeak_lm 3>;
+ qcom,mdss-has-panic-ctrl;
+ qcom,mdss-per-pipe-panic-luts = <0x000f>,
+ <0xffff>,
+ <0xfffc>,
+ <0xff00>;
+
+ qcom,mdss-mdp-reg-offset = <0x00001000>;
+ qcom,max-bandwidth-low-kbps = <6600000>;
+ qcom,max-bandwidth-high-kbps = <6600000>;
+ qcom,max-bandwidth-per-pipe-kbps = <3100000>;
+ qcom,max-clk-rate = <412500000>;
+ qcom,mdss-default-ot-rd-limit = <32>;
+ qcom,mdss-default-ot-wr-limit = <32>;
+ qcom,mdss-dram-channels = <2>;
+
+ /* Bandwidth limit settings */
+ qcom,max-bw-settings = <1 6600000>, /* Default */
+ <2 4500000>; /* Camera */
+
+ qcom,mdss-pipe-vig-off = <0x00005000 0x00007000>;
+ qcom,mdss-pipe-dma-off = <0x00025000 0x00027000
+ 0x00029000>;
+ qcom,mdss-pipe-cursor-off = <0x00035000>;
+
+ qcom,mdss-pipe-vig-xin-id = <0 4>;
+ qcom,mdss-pipe-dma-xin-id = <1 5 9>;
+ qcom,mdss-pipe-cursor-xin-id = <2>;
+
+ /* These Offsets are relative to */
+ /* "mdp_phys + mdp-reg-offset" address */
+
+ qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2ac 0 0>,
+ <0x2b4 0 0>;
+ qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2ac 8 12>,
+ <0x2b4 8 12>,
+ <0x2c4 8 12>;
+ qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3a8 16 15>;
+
+ qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400
+ 0x00002600 0x00002800>;
+ qcom,mdss-mixer-intf-off = <0x00045000 0x00046000
+ 0x00047000 0x0004a000>;
+ qcom,mdss-dspp-off = <0x00055000 0x00057000>;
+ qcom,mdss-wb-off = <0x00066000>;
+ qcom,mdss-intf-off = <0x0006b000 0x0006b800
+ 0x0006c000 0x0006c800>;
+ qcom,mdss-pingpong-off = <0x00071000 0x00071800
+ 0x00072000 0x00072800>;
+ qcom,mdss-slave-pingpong-off = <0x00073000>;
+ qcom,mdss-ppb-ctl-off = <0x00000330 0x00000338 0x00000370
+ 0x00000374> ;
+ qcom,mdss-ppb-cfg-off = <0x00000334 0x0000033C>;
+ qcom,mdss-has-pingpong-split;
+ qcom,mdss-has-separate-rotator;
+
+ qcom,mdss-ad-off = <0x0079000 0x00079800>;
+ qcom,mdss-cdm-off = <0x0007a200>;
+ qcom,mdss-dsc-off = <0x00081000 0x00081400>;
+ qcom,mdss-wfd-mode = "intf";
+ qcom,mdss-has-source-split;
+ qcom,mdss-highest-bank-bit = <0x1>;
+ qcom,mdss-has-decimation;
+ qcom,mdss-idle-power-collapse-enabled;
+ clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_MDSS_AHB_CLK>,
+ <&clock_mmss MMSS_MDSS_AXI_CLK>,
+ <&clock_mmss MMSS_THROTTLE_MDSS_AXI_CLK>,
+ <&clock_mmss MDP_CLK_SRC>,
+ <&clock_mmss MMSS_MDSS_MDP_CLK>,
+ <&clock_mmss MMSS_MDSS_VSYNC_CLK>,
+ <&clock_mmss MDP_CLK_SRC>;
+ clock-names = "mnoc_clk", "iface_clk", "bus_clk",
+ "throttle_bus_clk", "core_clk_src",
+ "core_clk", "vsync_clk", "lut_clk";
+
+ qcom,mdp-settings = <0x01190 0x00000000>,
+ <0x012ac 0xc0000ccc>,
+ <0x012b4 0xc0000ccc>,
+ <0x012bc 0x00cccccc>,
+ <0x012c4 0x0000cccc>,
+ <0x013a8 0x0cccc0c0>,
+ <0x013b0 0xccccc0c0>,
+ <0x013b8 0xcccc0000>,
+ <0x013d0 0x00cc0000>,
+ <0x0506c 0x00000000>,
+ <0x0706c 0x00000000>,
+ <0x0906c 0x00000000>,
+ <0x0b06c 0x00000000>,
+ <0x1506c 0x00000000>,
+ <0x1706c 0x00000000>,
+ <0x1906c 0x00000000>,
+ <0x1b06c 0x00000000>,
+ <0x2506c 0x00000000>,
+ <0x2706c 0x00000000>;
+
+ qcom,regs-dump-mdp = <0x01000 0x01458>,
+ <0x02000 0x02094>,
+ <0x02200 0x02294>,
+ <0x02400 0x02494>,
+ <0x02600 0x02694>,
+ <0x02800 0x02894>,
+ <0x05000 0x05154>,
+ <0x05a00 0x05b00>,
+ <0x07000 0x07154>,
+ <0x07a00 0x07b00>,
+ <0x25000 0x25184>,
+ <0x27000 0x27184>,
+ <0x29000 0x29184>,
+ <0x35000 0x35150>,
+ <0x45000 0x452bc>,
+ <0x46000 0x462bc>,
+ <0x47000 0x472bc>,
+ <0x4a000 0x4a2bc>,
+ <0x55000 0x5522c>,
+ <0x57000 0x5722c>,
+ <0x66000 0x662c0>,
+ <0x6b000 0x6b268>,
+ <0x6b800 0x6ba68>,
+ <0x6c000 0x6c268>,
+ <0x71000 0x710d4>,
+ <0x71800 0x718d4>,
+ <0x73000 0x730d4>,
+ <0x81000 0x81140>,
+ <0x81400 0x81540>;
+
+ qcom,regs-dump-names-mdp = "MDP",
+ "CTL_0", "CTL_1", "CTL_2", "CTL_3", "CTL_4",
+ "VIG0_SSPP", "VIG0", "VIG1_SSPP", "VIG1",
+ "DMA0_SSPP", "DMA1_SSPP","DMA2_SSPP",
+ "CURSOR0_SSPP",
+ "LAYER_0", "LAYER_1", "LAYER_2",
+ "LAYER_5",
+ "DSPP_0", "DSPP_1",
+ "WB_2",
+ "INTF_0", "INTF_1", "INTF_2",
+ "PP_0", "PP_1", "PP_4",
+ "DSC_0", "DSC_1";
+
+ /* buffer parameters to calculate prefill bandwidth */
+ qcom,mdss-prefill-outstanding-buffer-bytes = <0>;
+ qcom,mdss-prefill-y-buffer-bytes = <0>;
+ qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>;
+ qcom,mdss-prefill-scaler-buffer-lines-caf = <4>;
+ qcom,mdss-prefill-post-scaler-buffer-pixels = <2560>;
+ qcom,mdss-prefill-pingpong-buffer-pixels = <5120>;
+
+ qcom,mdss-reg-bus {
+ /* Reg Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 160000>,
+ <1 590 0 320000>;
+ };
+
+ qcom,mdss-pp-offsets {
+ qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>;
+ qcom,mdss-sspp-vig-pcc-off = <0x1b00>;
+ qcom,mdss-sspp-rgb-pcc-off = <0x380>;
+ qcom,mdss-sspp-dma-pcc-off = <0x380>;
+ qcom,mdss-lm-pgc-off = <0x3c0>;
+ qcom,mdss-dspp-gamut-off = <0x1600>;
+ qcom,mdss-dspp-pcc-off = <0x1700>;
+ qcom,mdss-dspp-pgc-off = <0x17c0>;
+ };
+
+ qcom,mdss-scaler-offsets {
+ qcom,mdss-vig-scaler-off = <0xa00>;
+ qcom,mdss-vig-scaler-lut-off = <0xb00>;
+ qcom,mdss-has-dest-scaler;
+ qcom,mdss-dest-block-off = <0x00061000>;
+ qcom,mdss-dest-scaler-off = <0x800 0x1000>;
+ qcom,mdss-dest-scaler-lut-off = <0x900 0x1100>;
+ };
+
+ smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb {
+ compatible = "qcom,smmu_mdp_unsec";
+ iommus = <&mmss_bimc_smmu 0>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-earlymap; /* for cont-splash */
+ gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>;
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
+ clock-names = "mmss_noc_axi_clk",
+ "mmss_noc_ahb_clk",
+ "mmss_smmu_ahb_clk",
+ "mmss_smmu_axi_clk";
+ };
+
+ smmu_mdp_sec: qcom,smmu_mdp_sec_cb {
+ compatible = "qcom,smmu_mdp_sec";
+ iommus = <&mmss_bimc_smmu 1>;
+ qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
+ qcom,iommu-vmid = <0xa>;
+ gdsc-mmagic-mdss-supply = <&gdsc_bimc_smmu>;
+ clocks = <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
+ clock-names = "mmss_noc_axi_clk",
+ "mmss_noc_ahb_clk",
+ "mmss_smmu_ahb_clk",
+ "mmss_smmu_axi_clk";
+ };
+
+ mdss_fb0: qcom,mdss_fb_primary {
+ cell-index = <0>;
+ compatible = "qcom,mdss-fb";
+ qcom,cont-splash-memory {
+ linux,contiguous-region = <&cont_splash_mem>;
+ };
+ };
+
+ mdss_fb1: qcom,mdss_fb_wfd {
+ cell-index = <1>;
+ compatible = "qcom,mdss-fb";
+ };
+
+ mdss_fb2: qcom,mdss_fb_dp {
+ cell-index = <2>;
+ compatible = "qcom,mdss-fb";
+ qcom,mdss-intf = <&mdss_dp_ctrl>;
+ };
+
+ };
+
+ mdss_dsi: qcom,mdss_dsi@0 {
+ compatible = "qcom,mdss-dsi";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ gdsc-supply = <&gdsc_mdss>;
+ vdda-1p2-supply = <&pm660_l1>;
+ vdda-0p9-supply = <&pm660l_l1>;
+ ranges = <0xc994000 0xc994000 0x400
+ 0xc994400 0xc994400 0x588
+ 0xc828000 0xc828000 0xac
+ 0xc996000 0xc996000 0x400
+ 0xc996400 0xc996400 0x588
+ 0xc828000 0xc828000 0xac>;
+
+ /* Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_dsi";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>,
+ <22 512 0 1000>;
+
+ qcom,mmss-ulp-clamp-ctrl-offset = <0x14>;
+
+ clocks = <&clock_mmss MMSS_MDSS_MDP_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_MDSS_AHB_CLK>,
+ <&clock_mmss MMSS_MDSS_AXI_CLK>,
+ <&clock_mmss MMSS_MISC_AHB_CLK>,
+ <&mdss_dsi0_pll BYTE0_MUX_CLK>,
+ <&mdss_dsi1_pll BYTE1_MUX_CLK>,
+ <&mdss_dsi0_pll PIX0_MUX_CLK>,
+ <&mdss_dsi1_pll PIX1_MUX_CLK>;
+ clock-names = "mdp_core_clk",
+ "mnoc_clk", "iface_clk",
+ "bus_clk", "core_mmss_clk",
+ "ext_byte0_clk", "ext_byte1_clk",
+ "ext_pixel0_clk", "ext_pixel1_clk";
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p2";
+ qcom,supply-min-voltage = <1200000>;
+ qcom,supply-max-voltage = <1250000>;
+ qcom,supply-enable-load = <12560>;
+ qcom,supply-disable-load = <4>;
+ };
+ };
+
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <880000>;
+ qcom,supply-max-voltage = <925000>;
+ qcom,supply-enable-load = <73400>;
+ qcom,supply-disable-load = <32>;
+ };
+ };
+
+ mdss_dsi0: qcom,mdss_dsi_ctrl0@c994000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ label = "MDSS DSI CTRL->0";
+ cell-index = <0>;
+ reg = <0xc994000 0x400>,
+ <0xc994400 0x588>,
+ <0xc828000 0xac>;
+ reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
+
+ qcom,timing-db-mode;
+ wqhd-vddio-supply = <&pm660_l11>;
+ vdda-3p3-supply = <&pm660l_l6>;
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+ qcom,mdss-mdp = <&mdss_mdp>;
+ qcom,mdss-fb-map = <&mdss_fb0>;
+
+ clocks = <&clock_mmss MMSS_MDSS_BYTE0_CLK>,
+ <&clock_mmss MMSS_MDSS_PCLK0_CLK>,
+ <&clock_mmss MMSS_MDSS_ESC0_CLK>,
+ <&clock_mmss BYTE0_CLK_SRC>,
+ <&clock_mmss PCLK0_CLK_SRC>,
+ <&clock_mmss MMSS_MDSS_BYTE0_INTF_CLK>,
+ <&mdss_dsi0_pll BYTE0_MUX_CLK>,
+ <&mdss_dsi0_pll PIX0_MUX_CLK>,
+ <&mdss_dsi0_pll BYTE0_SRC_CLK>,
+ <&mdss_dsi0_pll PIX0_SRC_CLK>,
+ <&mdss_dsi0_pll SHADOW_BYTE0_SRC_CLK>,
+ <&mdss_dsi0_pll SHADOW_PIX0_SRC_CLK>;
+ clock-names = "byte_clk", "pixel_clk", "core_clk",
+ "byte_clk_rcg", "pixel_clk_rcg",
+ "byte_intf_clk", "pll_byte_clk_mux",
+ "pll_pixel_clk_mux", "pll_byte_clk_src",
+ "pll_pixel_clk_src", "pll_shadow_byte_clk_src",
+ "pll_shadow_pixel_clk_src";
+
+ qcom,null-insertion-enabled;
+ qcom,platform-strength-ctrl = [ff 06
+ ff 06
+ ff 06
+ ff 06
+ ff 00];
+ qcom,platform-regulator-settings = [1d
+ 1d 1d 1d 1d];
+ qcom,platform-lane-config = [00 00 10 0f
+ 00 00 10 0f
+ 00 00 10 0f
+ 00 00 10 0f
+ 00 00 10 8f];
+ };
+
+ mdss_dsi1: qcom,mdss_dsi_ctrl1@c996000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ label = "MDSS DSI CTRL->1";
+ cell-index = <1>;
+ reg = <0xc996000 0x400>,
+ <0xc996400 0x588>,
+ <0xc828000 0xac>;
+ reg-names = "dsi_ctrl", "dsi_phy", "mmss_misc_phys";
+
+ qcom,timing-db-mode;
+ wqhd-vddio-supply = <&pm660_l11>;
+ lab-supply = <&lcdb_ldo_vreg>;
+ ibb-supply = <&lcdb_ncp_vreg>;
+ qcom,mdss-mdp = <&mdss_mdp>;
+ qcom,mdss-fb-map = <&mdss_fb0>;
+
+ clocks = <&clock_mmss MMSS_MDSS_BYTE1_CLK>,
+ <&clock_mmss MMSS_MDSS_PCLK1_CLK>,
+ <&clock_mmss MMSS_MDSS_ESC1_CLK>,
+ <&clock_mmss BYTE1_CLK_SRC>,
+ <&clock_mmss PCLK1_CLK_SRC>,
+ <&clock_mmss MMSS_MDSS_BYTE1_INTF_CLK>,
+ <&mdss_dsi1_pll BYTE1_MUX_CLK>,
+ <&mdss_dsi1_pll PIX1_MUX_CLK>,
+ <&mdss_dsi1_pll BYTE1_SRC_CLK>,
+ <&mdss_dsi1_pll PIX1_SRC_CLK>,
+ <&mdss_dsi1_pll SHADOW_BYTE1_SRC_CLK>,
+ <&mdss_dsi1_pll SHADOW_PIX1_SRC_CLK>;
+ clock-names = "byte_clk", "pixel_clk", "core_clk",
+ "byte_clk_rcg", "pixel_clk_rcg",
+ "byte_intf_clk", "pll_byte_clk_mux",
+ "pll_pixel_clk_mux", "pll_byte_clk_src",
+ "pll_pixel_clk_src", "pll_shadow_byte_clk_src",
+ "pll_shadow_pixel_clk_src";
+
+ qcom,null-insertion-enabled;
+ qcom,platform-strength-ctrl = [ff 06
+ ff 06
+ ff 06
+ ff 06
+ ff 00];
+ qcom,platform-regulator-settings = [1d
+ 1d 1d 1d 1d];
+ qcom,platform-lane-config = [00 00 10 0f
+ 00 00 10 0f
+ 00 00 10 0f
+ 00 00 10 0f
+ 00 00 10 8f];
+ };
+ };
+
+ qcom,mdss_wb_panel {
+ compatible = "qcom,mdss_wb";
+ qcom,mdss_pan_res = <640 480>;
+ qcom,mdss_pan_bpp = <24>;
+ qcom,mdss-fb-map = <&mdss_fb1>;
+ };
+
+ msm_ext_disp: qcom,msm-ext-disp {
+ status = "ok";
+ compatible = "qcom,msm-ext-disp";
+
+ ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
+ compatible = "qcom,msm-ext-disp-audio-codec-rx";
+ qcom,msm-ext-disp = <&msm_ext_disp>;
+ };
+ };
+
+ mdss_dp_ctrl: qcom,dp_ctrl@c990000 {
+ status = "ok";
+ cell-index = <0>;
+ compatible = "qcom,mdss-dp";
+ qcom,mdss-fb-map = <&mdss_fb2>;
+
+ gdsc-supply = <&gdsc_mdss>;
+ vdda-1p8-supply = <&pm660_l10>;
+ vdda-0p9-supply = <&pm660l_l1>;
+
+ reg = <0xc990000 0xa8c>,
+ <0xc011000 0x910>,
+ <0x1fcb200 0x050>,
+ <0xc8c2200 0x1a0>,
+ <0x780000 0x621c>,
+ <0xc9e1000 0x02c>;
+ reg-names = "dp_ctrl", "dp_phy", "tcsr_regs", "dp_mmss_cc",
+ "qfprom_physical","hdcp_physical";
+
+ clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_MDSS_AHB_CLK>,
+ <&clock_mmss MMSS_MDSS_AXI_CLK>,
+ <&clock_mmss MMSS_MDSS_MDP_CLK>,
+ <&clock_mmss MMSS_MDSS_HDMI_DP_AHB_CLK>,
+ <&clock_mmss MMSS_MDSS_DP_AUX_CLK>,
+ <&clock_rpmcc RPM_SMD_LN_BB_CLK1>,
+ <&clock_gcc GCC_USB3_CLKREF_CLK>,
+ <&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&clock_mmss MMSS_MDSS_DP_LINK_CLK>,
+ <&clock_mmss MMSS_MDSS_DP_LINK_INTF_CLK>,
+ <&clock_mmss MMSS_MDSS_DP_CRYPTO_CLK>,
+ <&clock_mmss MMSS_MDSS_DP_PIXEL_CLK>,
+ <&clock_mmss DP_PIXEL_CLK_SRC>,
+ <&mdss_dp_pll DP_PHY_PLL_VCO_DIV_CLK>;
+ clock-names = "core_mnoc_clk", "core_iface_clk", "core_bus_clk",
+ "core_mdp_core_clk", "core_alt_iface_clk",
+ "core_aux_clk", "core_ref_clk_src", "core_ref_clk",
+ "core_ahb_phy_clk", "ctrl_link_clk",
+ "ctrl_link_iface_clk", "ctrl_crypto_clk",
+ "ctrl_pixel_clk", "pixel_clk_rcg", "pixel_parent";
+
+ qcom,dp-usbpd-detection = <&pm660_pdphy>;
+
+ qcom,msm_ext_disp = <&msm_ext_disp>;
+
+ qcom,aux-cfg0-settings = [20 00];
+ qcom,aux-cfg1-settings = [24 13 23 1d];
+ qcom,aux-cfg2-settings = [28 00];
+ qcom,aux-cfg3-settings = [2c 00];
+ qcom,aux-cfg4-settings = [30 0a];
+ qcom,aux-cfg5-settings = [34 28];
+ qcom,aux-cfg6-settings = [38 0a];
+ qcom,aux-cfg7-settings = [3c 03];
+ qcom,aux-cfg8-settings = [40 b7];
+ qcom,aux-cfg9-settings = [44 03];
+ qcom,logical2physical-lane-map = [00 01 02 03];
+ qcom,phy-register-offset = <0x4>;
+ qcom,max-pclk-frequency-khz = <300000>;
+
+ qcom,core-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,core-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "gdsc";
+ qcom,supply-min-voltage = <0>;
+ qcom,supply-max-voltage = <0>;
+ qcom,supply-enable-load = <0>;
+ qcom,supply-disable-load = <0>;
+ };
+ };
+
+ qcom,ctrl-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,ctrl-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-1p8";
+ qcom,supply-min-voltage = <1780000>;
+ qcom,supply-max-voltage = <1950000>;
+ qcom,supply-enable-load = <12560>;
+ qcom,supply-disable-load = <4>;
+ };
+ };
+
+ qcom,phy-supply-entries {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qcom,phy-supply-entry@0 {
+ reg = <0>;
+ qcom,supply-name = "vdda-0p9";
+ qcom,supply-min-voltage = <880000>;
+ qcom,supply-max-voltage = <925000>;
+ qcom,supply-enable-load = <73400>;
+ qcom,supply-disable-load = <32>;
+ };
+ };
+ };
+
+ mdss_rotator: qcom,mdss_rotator {
+ compatible = "qcom,sde_rotator";
+ reg = <0x0c900000 0xab100>,
+ <0x0c9b0000 0x1040>;
+ reg-names = "mdp_phys",
+ "rot_vbif_phys";
+
+ #list-cells = <1>;
+
+ qcom,mdss-rot-mode = <1>;
+ qcom,mdss-highest-bank-bit = <0x1>;
+
+ /* Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_rotator";
+ qcom,msm-bus,num-cases = <3>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <22 512 0 0>,
+ <22 512 0 6400000>,
+ <22 512 0 6400000>;
+
+ rot-vdd-supply = <&gdsc_mdss>;
+ qcom,supply-names = "rot-vdd";
+
+ clocks = <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_MDSS_AHB_CLK>,
+ <&clock_mmss ROT_CLK_SRC>,
+ <&clock_mmss MMSS_MDSS_ROT_CLK>,
+ <&clock_mmss MMSS_MDSS_AXI_CLK>;
+ clock-names = "mnoc_clk",
+ "iface_clk", "rot_core_clk",
+ "rot_clk", "axi_clk";
+
+ interrupt-parent = <&mdss_mdp>;
+ interrupts = <2 0>;
+
+ qcom,mdss-rot-parent = <&mdss_mdp 0>;
+ /* VBIF QoS remapper settings*/
+ qcom,mdss-rot-vbif-qos-setting = <1 1 1 1>;
+ qcom,mdss-rot-xin-id = <14 15>;
+
+ qcom,mdss-default-ot-rd-limit = <32>;
+ qcom,mdss-default-ot-wr-limit = <32>;
+
+ qcom,sde-reg-bus {
+ /* Reg Bus Scale Settings */
+ qcom,msm-bus,name = "mdss_rot_reg";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,active-only;
+ qcom,msm-bus,vectors-KBps =
+ <1 590 0 0>,
+ <1 590 0 76800>,
+ <1 590 0 160000>,
+ <1 590 0 320000>;
+ };
+ };
+
+};
+
+#include "sdm660-mdss-panels.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-mtp-external-codec-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-mtp-external-codec-overlay.dts
new file mode 100755
index 0000000..a65ec9d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-mtp-external-codec-overlay.dts
@@ -0,0 +1,30 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,cpu-osm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm660-mtp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 Ext. Audio Codec MTP";
+ compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp";
+ qcom,board-id = <8 0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-moist-cfg = <0>, <0>, <3>;
+};
+
+&slim_aud {
+ /delete-node/tasha_codec;
+};
+
+&soc {
+ /delete-node/sound-9335;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-mtp-internal-codec-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-mtp-internal-codec-overlay.dts
new file mode 100755
index 0000000..0996310
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-mtp-internal-codec-overlay.dts
@@ -0,0 +1,21 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,cpu-osm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm660-mtp.dtsi"
+#include "sdm660-internal-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 Int. Audio Codec MTP";
+ compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp";
+ qcom,board-id = <8 1>;
+};
+
+&int_codec {
+ qcom,model = "sdm660-snd-card-mtp";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-mtp.dts
new file mode 100755
index 0000000..7ac88a8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-mtp.dts
@@ -0,0 +1,26 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-mtp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L MTP";
+ compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp";
+ qcom,board-id = <8 0>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-moist-cfg = <0>, <0>, <3>;
+};
+
+&slim_aud {
+ /delete-node/tasha_codec;
+};
+
+&soc {
+ /delete-node/sound-9335;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-mtp.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-mtp.dtsi
new file mode 100755
index 0000000..e3421e3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-mtp.dtsi
@@ -0,0 +1,262 @@
+#include "sdm660-camera-sensor-mtp.dtsi"
+
+&vendor {
+ mtp_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+ #include "fg-gen3-batterydata-itech-3000mah.dtsi"
+ #include "fg-gen3-batterydata-ascent-3450mah.dtsi"
+ };
+};
+
+&uartblsp1dm1 {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart_console_active>;
+};
+
+&ufsphy1 {
+ vdda-phy-supply = <&pm660l_l1>;
+ vdda-pll-supply = <&pm660_l10>;
+ vdda-phy-max-microamp = <51400>;
+ vdda-pll-max-microamp = <14200>;
+ status = "ok";
+};
+
+&ufs1 {
+ vdd-hba-supply = <&gdsc_ufs>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm660l_l4>;
+ vccq2-supply = <&pm660_l8>;
+ vcc-max-microamp = <500000>;
+ vccq2-max-microamp = <600000>;
+ qcom,vddp-ref-clk-supply = <&pm660_l1>;
+ qcom,vddp-ref-clk-max-microamp = <100>;
+
+ status = "ok";
+};
+
+&pm660_gpios {
+ /* GPIO 4 (NFC_CLK_REQ) */
+ nfc_clk {
+ nfc_clk_default: nfc_clk_default {
+ pins = "gpio4";
+ function = "normal";
+ input-enable;
+ power-source = <1>;
+ };
+ };
+
+ /* GPIO 11 for Home Key */
+ home_key {
+ home_key_default: home_key_default {
+ pins = "gpio11";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ };
+ };
+};
+
+&i2c_6 { /* BLSP1 QUP6 (NFC) */
+ status = "okay";
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 28 0x00>;
+ qcom,nq-ven = <&tlmm 29 0x00>;
+ qcom,nq-firm = <&tlmm 30 0x00>;
+ qcom,nq-clkreq = <&pm660_gpios 4 0x00>;
+ qcom,nq-esepwr = <&tlmm 31 0x00>;
+ interrupt-parent = <&tlmm>;
+ qcom,clk-src = "BBCLK3";
+ interrupts = <28 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_default>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
+ clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK3_PIN>;
+ clock-names = "ref_clk";
+ };
+};
+
+&mdss_mdp {
+ qcom,mdss-pref-prim-intf = "dsi";
+};
+
+&mdss_dsi {
+ hw-config = "split_dsi";
+};
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+ pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+ qcom,platform-reset-gpio = <&tlmm 53 0>;
+ qcom,platform-te-gpio = <&tlmm 59 0>;
+};
+
+&mdss_dsi1 {
+ qcom,dsi-pref-prim-pan = <&dsi_dual_nt35597_truly_video>;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+ pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+ qcom,platform-reset-gpio = <&tlmm 53 0>;
+ qcom,platform-te-gpio = <&tlmm 59 0>;
+};
+
+&mdss_dp_ctrl {
+ pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
+ pinctrl-0 = <&mdss_dp_aux_active &mdss_dp_usbplug_cc_active>;
+ pinctrl-1 = <&mdss_dp_aux_suspend &mdss_dp_usbplug_cc_suspend>;
+ qcom,aux-en-gpio = <&tlmm 55 0>;
+ qcom,aux-sel-gpio = <&tlmm 56 0>;
+ qcom,usbplug-cc-gpio = <&tlmm 58 0>;
+};
+
+&pm660l_wled {
+ qcom,string-cfg= <6>;
+ status = "ok";
+};
+
+&pm660l_lcdb {
+ status = "ok";
+};
+
+&dsi_dual_nt35597_truly_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_dual_nt35597_truly_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,mdss-dsi-mode-sel-gpio-state = "dual_port";
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_dual_sharp_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_nt35597_truly_dsc_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_nt35597_truly_dsc_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_nt35695b_truly_fhd_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_nt35695b_truly_fhd_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&dsi_rm67195_amoled_fhd_cmd {
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>;
+};
+
+&dsi_lgd_incell_sw49106_fhd_video {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&sdhc_1 {
+ /* device core power supply */
+ vdd-supply = <&pm660l_l4>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <200 570000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm660_l8>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <200 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ /* device core power supply */
+ vdd-supply = <&pm660l_l5>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <15000 800000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm660l_l2>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ #address-cells = <0>;
+ interrupt-parent = <&sdhc_2>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 0 125 0
+ 1 &intc 0 0 221 0
+ 2 &tlmm 54 0>;
+ interrupt-names = "hc_irq", "pwr_irq", "status_irq";
+ cd-gpios = <&tlmm 54 0x1>;
+
+ status = "ok";
+};
+
+&soc {
+ qcom,msm-ssc-sensors {
+ compatible = "qcom,msm-ssc-sensors";
+ };
+};
+
+&mem_client_3_size {
+ qcom,peripheral-size = <0xf00000>;
+};
+
+&pm660_fg {
+ qcom,battery-data = <&mtp_batterydata>;
+};
+
+&i2c_2 {
+ status = "ok";
+ smb1351-charger@1d {
+ compatible = "qcom,smb1351-charger";
+ reg = <0x1d>;
+ qcom,parallel-charger;
+ qcom,float-voltage-mv = <4400>;
+ qcom,recharge-mv = <100>;
+ qcom,parallel-en-pin-polarity = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-pinctrl.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-pinctrl.dtsi
new file mode 100755
index 0000000..8532a1c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-pinctrl.dtsi
@@ -0,0 +1,1895 @@
+&soc {
+ tlmm: pinctrl@03000000 {
+ compatible = "qcom,sdm660-pinctrl";
+ reg = <0x03000000 0xc00000>;
+ reg-names = "pinctrl", "spi_cfg";
+ interrupts-extended = <&wakegic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ wakeup-parent = <&wakegpio>;
+ #interrupt-cells = <2>;
+ irqdomain-map = <1 0 &wakegpio 3 0>,
+ <5 0 &wakegpio 4 0>,
+ <9 0 &wakegpio 5 0>,
+ <10 0 &wakegpio 6 0>,
+ <66 0 &wakegpio 7 0>,
+ <22 0 &wakegpio 8 0>,
+ <25 0 &wakegpio 9 0>,
+ <28 0 &wakegpio 10 0>,
+ <58 0 &wakegpio 11 0>,
+ <41 0 &wakegpio 13 0>,
+ <43 0 &wakegpio 14 0>,
+ <40 0 &wakegpio 15 0>,
+ <42 0 &wakegpio 16 0>,
+ <46 0 &wakegpio 17 0>,
+ <50 0 &wakegpio 18 0>,
+ <44 0 &wakegpio 19 0>,
+ <56 0 &wakegpio 21 0>,
+ <45 0 &wakegpio 22 0>,
+ <68 0 &wakegpio 23 0>,
+ <69 0 &wakegpio 24 0>,
+ <70 0 &wakegpio 25 0>,
+ <71 0 &wakegpio 26 0>,
+ <72 0 &wakegpio 27 0>,
+ <73 0 &wakegpio 28 0>,
+ <64 0 &wakegpio 29 0>,
+ <2 0 &wakegpio 30 0>,
+ <13 0 &wakegpio 31 0>,
+ <111 0 &wakegpio 32 0>,
+ <74 0 &wakegpio 33 0>,
+ <75 0 &wakegpio 34 0>,
+ <76 0 &wakegpio 35 0>,
+ <82 0 &wakegpio 36 0>,
+ <17 0 &wakegpio 37 0>,
+ <77 0 &wakegpio 38 0>,
+ <47 0 &wakegpio 39 0>,
+ <54 0 &wakegpio 40 0>,
+ <48 0 &wakegpio 41 0>,
+ <101 0 &wakegpio 42 0>,
+ <49 0 &wakegpio 43 0>,
+ <51 0 &wakegpio 44 0>,
+ <86 0 &wakegpio 45 0>,
+ <90 0 &wakegpio 46 0>,
+ <91 0 &wakegpio 47 0>,
+ <52 0 &wakegpio 48 0>,
+ <55 0 &wakegpio 50 0>,
+ <6 0 &wakegpio 51 0>,
+ <65 0 &wakegpio 53 0>,
+ <67 0 &wakegpio 55 0>,
+ <83 0 &wakegpio 56 0>,
+ <84 0 &wakegpio 57 0>,
+ <85 0 &wakegpio 58 0>,
+ <87 0 &wakegpio 59 0>,
+ <21 0 &wakegpio 63 0>,
+ <78 0 &wakegpio 64 0>,
+ <113 0 &wakegpio 65 0>,
+ <60 0 &wakegpio 66 0>,
+ <98 0 &wakegpio 67 0>,
+ <30 0 &wakegpio 68 0>,
+ <31 0 &wakegpio 70 0>,
+ <29 0 &wakegpio 71 0>,
+ <107 0 &wakegpio 76 0>,
+ <109 0 &wakegpio 83 0>,
+ <103 0 &wakegpio 84 0>,
+ <105 0 &wakegpio 85 0>;
+ irqdomain-map-pass-thru = <0 0xff>;
+ irqdomain-map-mask = <0xff 0>;
+
+
+ uart_console_active: uart_console_active {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart2";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ led_enable: led_enable {
+ mux {
+ pins = "gpio40";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio40";
+ drive_strength = <2>;
+ output-high;
+ bias-disable;
+ };
+ };
+
+ led_disable: led_disable {
+ mux {
+ pins = "gpio40";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio40";
+ drive_strength = <2>;
+ output-low;
+ bias-disable;
+ };
+ };
+
+ trigout_a: trigout_a {
+ mux {
+ pins = "gpio49";
+ function = "qdss_cti0_a";
+ };
+
+ config {
+ pins = "gpio49";
+ drive-strength = <16>;
+ bias-disable;
+ output-low;
+ };
+ };
+
+ ufs_dev_reset_assert: ufs_dev_reset_assert {
+ config {
+ pins = "ufs_reset";
+ bias-pull-down; /* default: pull down */
+ /*
+ * UFS_RESET driver strengths are having
+ * different values/steps compared to typical
+ * GPIO drive strengths.
+ *
+ * Following table clarifies:
+ *
+ * HDRV value | UFS_RESET | Typical GPIO
+ * (dec) | (mA) | (mA)
+ * 0 | 0.8 | 2
+ * 1 | 1.55 | 4
+ * 2 | 2.35 | 6
+ * 3 | 3.1 | 8
+ * 4 | 3.9 | 10
+ * 5 | 4.65 | 12
+ * 6 | 5.4 | 14
+ * 7 | 6.15 | 16
+ *
+ * POR value for UFS_RESET HDRV is 3 which means
+ * 3.1mA and we want to use that. Hence just
+ * specify 8mA to "drive-strength" binding and
+ * that should result into writing 3 to HDRV
+ * field.
+ */
+ drive-strength = <8>; /* default: 3.1 mA */
+ output-low; /* active low reset */
+ };
+ };
+
+ ufs_dev_reset_deassert: ufs_dev_reset_deassert {
+ config {
+ pins = "ufs_reset";
+ bias-pull-down; /* default: pull down */
+ /*
+ * default: 3.1 mA
+ * check comments under ufs_dev_reset_assert
+ */
+ drive-strength = <8>;
+ output-high; /* active low reset */
+ };
+ };
+
+ /* SDC pin type */
+ sdc1_clk_on: sdc1_clk_on {
+ config {
+ pins = "sdc1_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <16>; /* 16 MA */
+ };
+ };
+
+ sdc1_clk_off: sdc1_clk_off {
+ config {
+ pins = "sdc1_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_cmd_on: sdc1_cmd_on {
+ config {
+ pins = "sdc1_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc1_cmd_off: sdc1_cmd_off {
+ config {
+ pins = "sdc1_cmd";
+ num-grp-pins = <1>;
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_data_on: sdc1_data_on {
+ config {
+ pins = "sdc1_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc1_data_off: sdc1_data_off {
+ config {
+ pins = "sdc1_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc1_rclk_on: sdc1_rclk_on {
+ config {
+ pins = "sdc1_rclk";
+ bias-pull-down; /* pull down */
+ };
+ };
+
+ sdc1_rclk_off: sdc1_rclk_off {
+ config {
+ pins = "sdc1_rclk";
+ bias-pull-down; /* pull down */
+ };
+ };
+
+ sdc2_clk_on: sdc2_clk_on {
+ config {
+ pins = "sdc2_clk";
+ drive-strength = <16>; /* 16 MA */
+ bias-disable; /* NO pull */
+ };
+ };
+
+ sdc2_clk_off: sdc2_clk_off {
+ config {
+ pins = "sdc2_clk";
+ bias-disable; /* NO pull */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_cmd_on: sdc2_cmd_on {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_cmd_off: sdc2_cmd_off {
+ config {
+ pins = "sdc2_cmd";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_data_on: sdc2_data_on {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <10>; /* 10 MA */
+ };
+ };
+
+ sdc2_data_off: sdc2_data_off {
+ config {
+ pins = "sdc2_data";
+ bias-pull-up; /* pull up */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ sdc2_cd_on: cd_on {
+ mux {
+ pins = "gpio54";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ sdc2_cd_off: cd_off {
+ mux {
+ pins = "gpio54";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ /* I2C CONFIGURATION */
+ i2c_1 {
+ i2c_1_active: i2c_1_active {
+ mux {
+ pins = "gpio2", "gpio3";
+ function = "blsp_i2c1";
+ };
+
+ config {
+ pins = "gpio2", "gpio3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_1_sleep: i2c_1_sleep {
+ mux {
+ pins = "gpio2", "gpio3";
+ function = "blsp_i2c1";
+ };
+
+ config {
+ pins = "gpio2", "gpio3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ i2c_1_bitbang: i2c_1_bitbang {
+ mux {
+ pins = "gpio2", "gpio3";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio2", "gpio3";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ i2c_2 {
+ i2c_2_active: i2c_2_active {
+ mux {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+ };
+
+ config {
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_2_sleep: i2c_2_sleep {
+ mux {
+ pins = "gpio6", "gpio7";
+ function = "blsp_i2c2";
+ };
+
+ config {
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ i2c_2_bitbang: i2c_2_bitbang {
+ mux {
+ pins = "gpio6", "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ i2c_3 {
+ i2c_3_active: i2c_3_active {
+ mux {
+ pins = "gpio10", "gpio11";
+ function = "blsp_i2c3";
+ };
+
+ config {
+ pins = "gpio10", "gpio11";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_3_sleep: i2c_3_sleep {
+ mux {
+ pins = "gpio10", "gpio11";
+ function = "blsp_i2c3";
+ };
+
+ config {
+ pins = "gpio10", "gpio11";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ i2c_3_bitbang: i2c_3_bitbang {
+ mux {
+ pins = "gpio10", "gpio11";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio10", "gpio11";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ i2c_4 {
+ i2c_4_active: i2c_4_active {
+ mux {
+ pins = "gpio14", "gpio15";
+ function = "blsp_i2c4";
+ };
+
+ config {
+ pins = "gpio14", "gpio15";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_4_sleep: i2c_4_sleep {
+ mux {
+ pins = "gpio14", "gpio15";
+ function = "blsp_i2c4";
+ };
+
+ config {
+ pins = "gpio14", "gpio15";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ i2c_4_bitbang: i2c_4_bitbang {
+ mux {
+ pins = "gpio14", "gpio15";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio14", "gpio15";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ i2c_5 {
+ i2c_5_active: i2c_5_active {
+ mux {
+ pins = "gpio18", "gpio19";
+ function = "blsp_i2c5";
+ };
+
+ config {
+ pins = "gpio18", "gpio19";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_5_sleep: i2c_5_sleep {
+ mux {
+ pins = "gpio18", "gpio19";
+ function = "blsp_i2c5";
+ };
+
+ config {
+ pins = "gpio18", "gpio19";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ i2c_5_bitbang: i2c_5_bitbang {
+ mux {
+ pins = "gpio18", "gpio19";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio18", "gpio19";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ i2c_6 {
+ i2c_6_active: i2c_6_active {
+ mux {
+ pins = "gpio22", "gpio23";
+ function = "blsp_i2c6";
+ };
+
+ config {
+ pins = "gpio22", "gpio23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_6_sleep: i2c_6_sleep {
+ mux {
+ pins = "gpio22", "gpio23";
+ function = "blsp_i2c6";
+ };
+
+ config {
+ pins = "gpio22", "gpio23";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ i2c_6_bitbang: i2c_6_bitbang {
+ mux {
+ pins = "gpio22", "gpio23";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio22", "gpio23";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ nfc {
+ nfc_int_active: nfc_int_active {
+ /* active state */
+ mux {
+ /* GPIO 28 NFC Read Interrupt */
+ pins = "gpio28";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio28";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_int_suspend: nfc_int_suspend {
+ /* sleep state */
+ mux {
+ /* GPIO 28 NFC Read Interrupt */
+ pins = "gpio28";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio28";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_enable_active: nfc_enable_active {
+ /* active state */
+ mux {
+ /* 29: NFC ENABLE 30:FW DNLD */
+ /* 31:ESE Enable */
+ pins = "gpio29", "gpio30", "gpio31";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio29", "gpio30", "gpio31";
+ drive-strength = <2>; /* 2 MA */
+ bias-pull-up;
+ };
+ };
+
+ nfc_enable_suspend: nfc_enable_suspend {
+ /* sleep state */
+ mux {
+ /* 29: NFC ENABLE 30:FW DNLD */
+ /* 31:ESE Enable */
+ pins = "gpio29", "gpio30", "gpio31";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio29", "gpio30", "gpio31";
+ drive-strength = <2>; /* 2 MA */
+ bias-disable;
+ };
+ };
+ };
+
+ i2c_7 {
+ i2c_7_active: i2c_7_active {
+ mux {
+ pins = "gpio26", "gpio27";
+ function = "blsp_i2c7";
+ };
+
+ config {
+ pins = "gpio26", "gpio27";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_7_sleep: i2c_7_sleep {
+ mux {
+ pins = "gpio26", "gpio27";
+ function = "blsp_i2c7";
+ };
+
+ config {
+ pins = "gpio26", "gpio27";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ i2c_7_bitbang: i2c_7_bitbang {
+ mux {
+ pins = "gpio26", "gpio27";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio26", "gpio27";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ i2c_8 {
+ i2c_8_active: i2c_8_active {
+ mux {
+ pins = "gpio30", "gpio31";
+ function = "blsp_i2c8_a";
+ };
+
+ config {
+ pins = "gpio30", "gpio31";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c_8_sleep: i2c_8_sleep {
+ mux {
+ pins = "gpio30", "gpio31";
+ function = "blsp_i2c8_a";
+ };
+
+ config {
+ pins = "gpio30", "gpio31";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ i2c_8_bitbang: i2c_8_bitbang {
+ mux {
+ pins = "gpio30", "gpio31";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio30", "gpio31";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ /* SPI CONFIGURATION */
+ spi_1 {
+ spi_1_active: spi_1_active {
+ mux {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ function = "blsp_spi1";
+ };
+
+ config {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ spi_1_sleep: spi_1_sleep {
+ mux {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ function = "blsp_spi1";
+ };
+
+ config {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ spi_2 {
+ spi_2_active: spi_2_active {
+ mux {
+ pins = "gpio4", "gpio5",
+ "gpio6", "gpio7";
+ function = "blsp_spi2";
+ };
+
+ config {
+ pins = "gpio4", "gpio5",
+ "gpio6", "gpio7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ spi_2_sleep: spi_2_sleep {
+ mux {
+ pins = "gpio4", "gpio5",
+ "gpio6", "gpio7";
+ function = "blsp_spi2";
+ };
+
+ config {
+ pins = "gpio4", "gpio5",
+ "gpio6", "gpio7";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ spi_3 {
+ spi_3_active: spi_3_active {
+ mux {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ function = "blsp_spi3";
+ };
+
+ config {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ spi_3_sleep: spi_3_sleep {
+ mux {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ function = "blsp_spi3";
+ };
+
+ config {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ spi_4 {
+ spi_4_active: spi_4_active {
+ mux {
+ pins = "gpio12", "gpio13",
+ "gpio14", "gpio15";
+ function = "blsp_spi4";
+ };
+
+ config {
+ pins = "gpio12", "gpio13",
+ "gpio14", "gpio15";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ spi_4_sleep: spi_4_sleep {
+ mux {
+ pins = "gpio12", "gpio13",
+ "gpio14", "gpio15";
+ function = "blsp_spi4";
+ };
+
+ config {
+ pins = "gpio12", "gpio13",
+ "gpio14", "gpio15";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ spi_5 {
+ spi_5_active: spi_5_active {
+ mux {
+ pins = "gpio16", "gpio17",
+ "gpio18", "gpio19";
+ function = "blsp_spi5";
+ };
+
+ config {
+ pins = "gpio16", "gpio17",
+ "gpio18", "gpio19";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ spi_5_sleep: spi_5_sleep {
+ mux {
+ pins = "gpio16", "gpio17",
+ "gpio18", "gpio19";
+ function = "blsp_spi5";
+ };
+
+ config {
+ pins = "gpio16", "gpio17",
+ "gpio18", "gpio19";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ spi_6 {
+ spi_6_active: spi_6_active {
+ mux {
+ pins = "gpio49", "gpio52",
+ "gpio22", "gpio23";
+ function = "blsp_spi6";
+ };
+
+ config {
+ pins = "gpio49", "gpio52",
+ "gpio22", "gpio23";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ spi_6_sleep: spi_6_sleep {
+ mux {
+ pins = "gpio49", "gpio52",
+ "gpio22", "gpio23";
+ function = "blsp_spi6";
+ };
+
+ config {
+ pins = "gpio49", "gpio52",
+ "gpio22", "gpio23";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ spi_7 {
+ spi_7_active: spi_7_active {
+ mux {
+ pins = "gpio24", "gpio25",
+ "gpio26", "gpio27";
+ function = "blsp_spi7";
+ };
+
+ config {
+ pins = "gpio24", "gpio25",
+ "gpio26", "gpio27";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ spi_7_sleep: spi_7_sleep {
+ mux {
+ pins = "gpio24", "gpio25",
+ "gpio26", "gpio27";
+ function = "blsp_spi7";
+ };
+
+ config {
+ pins = "gpio24", "gpio25",
+ "gpio26", "gpio27";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+
+ spi_8 {
+ spi_8_active: spi_8_active {
+ mux {
+ pins = "gpio28", "gpio29",
+ "gpio30", "gpio31";
+ function = "blsp_spi8_a";
+ };
+
+ config {
+ pins = "gpio28", "gpio29",
+ "gpio30", "gpio31";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+
+ spi_8_sleep: spi_8_sleep {
+ mux {
+ pins = "gpio28", "gpio29",
+ "gpio30", "gpio31";
+ function = "blsp_spi8_a";
+ };
+
+ config {
+ pins = "gpio28", "gpio29",
+ "gpio30", "gpio31";
+ drive-strength = <6>;
+ bias-disable;
+ };
+ };
+ };
+ /* USB C analog configuration */
+ wcd_usbc_analog_en1 {
+ wcd_usbc_analog_en1_idle: wcd_usbc_ana_en1_idle {
+ mux {
+ pins = "gpio80";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio80";
+ drive-strength = <2>;
+ bias-pull-down;
+ output-low;
+ };
+ };
+
+ wcd_usbc_analog_en1_active: wcd_usbc_ana_en1_active {
+ mux {
+ pins = "gpio80";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio80";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ wcd_usbc_analog_en2n {
+ wcd_usbc_analog_en2n_idle: wcd_usbc_ana_en2n_idle {
+ mux {
+ pins = "gpio77";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio77";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+
+ wcd_usbc_analog_en2n_active: wcd_usbc_ana_en2n_active {
+ mux {
+ pins = "gpio77";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio77";
+ drive-strength = <2>;
+ bias-pull-down;
+ output-low;
+ };
+ };
+ };
+
+ sdw_clk_pin {
+ sdw_clk_sleep: sdw_clk_sleep {
+ mux {
+ pins = "gpio24";
+ function = "sndwire_clk";
+ };
+
+ config {
+ pins = "gpio24";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+ };
+
+ sdw_clk_active: sdw_clk_active {
+ mux {
+ pins = "gpio24";
+ function = "sndwire_clk";
+ };
+
+ config {
+ pins = "gpio24";
+ drive-strength = <2>;
+ bias-bus-hold;
+ };
+ };
+ };
+
+ sdw_clk_data {
+ sdw_data_sleep: sdw_data_sleep {
+ mux {
+ pins = "gpio25";
+ function = "sndwire_data";
+ };
+
+ config {
+ pins = "gpio25";
+ drive-strength = <4>;
+ bias-bus-hold;
+ };
+ };
+
+ sdw_data_active: sdw_data_active {
+ mux {
+ pins = "gpio25";
+ function = "sndwire_data";
+ };
+
+ config {
+ pins = "gpio25";
+ drive-strength = <4>;
+ bias-bus-hold;
+ };
+ };
+ };
+
+ /* WSA speaker reset pins */
+ spkr_1_sd_n {
+ spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+ mux {
+ pins = "gpio26";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio26";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_1_sd_n_active: spkr_1_sd_n_active {
+ mux {
+ pins = "gpio26";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio26";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ spkr_2_sd_n {
+ spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
+ mux {
+ pins = "gpio27";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio27";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down;
+ input-enable;
+ };
+ };
+
+ spkr_2_sd_n_active: spkr_2_sd_n_active {
+ mux {
+ pins = "gpio27";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio27";
+ drive-strength = <16>; /* 16 mA */
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ wcd_gnd_mic_swap {
+ wcd_gnd_mic_swap_idle: wcd_gnd_mic_swap_idle {
+ mux {
+ pins = "gpio63";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio63";
+ drive-strength = <2>;
+ bias-pull-down;
+ output-low;
+ };
+ };
+
+ wcd_gnd_mic_swap_active: wcd_gnd_mic_swap_active {
+ mux {
+ pins = "gpio63";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio63";
+ drive-strength = <2>;
+ bias-disable;
+ output-high;
+ };
+ };
+ };
+
+ msm_hph_en0 {
+ hph_en0_sleep: hph_en0_sleep {
+ mux {
+ pins = "gpio24";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio24";
+ output-low;
+ };
+ };
+
+ hph_en0_active: hph_en0_active {
+ mux {
+ pins = "gpio24";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio24";
+ output-high;
+ };
+ };
+ };
+
+ msm_hph_en1 {
+ hph_en1_sleep: hph_en1_sleep {
+ mux {
+ pins = "gpio25";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio25";
+ output-low;
+ };
+ };
+
+ hph_en1_active: hph_en1_active {
+ mux {
+ pins = "gpio25";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio25";
+ output-high;
+ };
+ };
+ };
+
+ cci0_active: cci0_active {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio36","gpio37"; // Only 2
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio36","gpio37";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci0_suspend: cci0_suspend {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio36","gpio37";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio36","gpio37";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci1_active: cci1_active {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio38","gpio39";
+ function = "cci_i2c";
+ };
+
+ config {
+ pins = "gpio38","gpio39";
+ bias-pull-up; /* PULL UP*/
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cci1_suspend: cci1_suspend {
+ mux {
+ /* CLK, DATA */
+ pins = "gpio38","gpio39";
+ function = "cci_i2c";
+ };
+
+
+ config {
+ pins = "gpio38","gpio39";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_actuator_vaf_active: cam_actuator_vaf_active {
+ /* ACTUATOR POWER */
+ mux {
+ pins = "gpio50";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio50";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_actuator_vaf_suspend: cam_actuator_vaf_suspend {
+ /* ACTUATOR POWER */
+ mux {
+ pins = "gpio50";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio50";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_tof_active: cam_tof_active {
+ /* LASER */
+ mux {
+ pins = "gpio50", "gpio42", "gpio45";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio50", "gpio42", "gpio45";
+ bias-pull-up;
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_tof_suspend: cam_tof_suspend {
+ /* LASER */
+ mux {
+ pins = "gpio50", "gpio42", "gpio45";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio50", "gpio42", "gpio45";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk0_active: cam_sensor_mclk0_active {
+ /* MCLK0 */
+ mux {
+ /* CLK */
+ pins = "gpio32";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio32";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend {
+ /* MCLK0 */
+ mux {
+ /* CLK */
+ pins = "gpio32";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio32";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear_active: cam_sensor_rear_active {
+ /* RESET, STANDBY */
+ mux {
+ pins = "gpio46","gpio44";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio46","gpio44";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear_suspend: cam_sensor_rear_suspend {
+ /* RESET, STANDBY */
+ mux {
+ pins = "gpio46","gpio44";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio46","gpio44";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk1_active: cam_sensor_mclk1_active {
+ /* MCLK1 */
+ mux {
+ /* CLK */
+ pins = "gpio33";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio33";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend {
+ /* MCLK1 */
+ mux {
+ /* CLK */
+ pins = "gpio33";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio33";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear2_active: cam_sensor_rear2_active {
+ /* RESET, STANDBY */
+ mux {
+ pins = "gpio48","gpio51";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio48","gpio51";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_rear2_suspend: cam_sensor_rear2_suspend {
+ /* RESET, STANDBY */
+ mux {
+ pins = "gpio48","gpio51";
+ function = "gpio";
+ };
+ config {
+ pins = "gpio48","gpio51";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk2_active: cam_sensor_mclk2_active {
+ /* MCLK1 */
+ mux {
+ /* CLK */
+ pins = "gpio34";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio34";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend {
+ /* MCLK1 */
+ mux {
+ /* CLK */
+ pins = "gpio34";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio34";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_front_active: cam_sensor_front_active {
+ /* RESET VANA*/
+ mux {
+ pins = "gpio47", "gpio44";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio47", "gpio44";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_front_suspend: cam_sensor_front_suspend {
+ /* RESET */
+ mux {
+ pins = "gpio47";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio47";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk3_active: cam_sensor_mclk3_active {
+ /* MCLK3 */
+ mux {
+ /* CLK */
+ pins = "gpio35";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio35";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend {
+ /* MCLK3 */
+ mux {
+ /* CLK */
+ pins = "gpio35";
+ function = "cam_mclk";
+ };
+
+ config {
+ pins = "gpio35";
+ bias-pull-down; /* PULL DOWN */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_front_iris_active: cam_sensor_front_iris_active {
+ /* RESET */
+ mux {
+ pins = "gpio52";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio52";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ cam_sensor_front_iris_suspend: cam_sensor_front_iris_suspend {
+ /* RESET */
+ mux {
+ pins = "gpio52";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio52";
+ bias-disable; /* No PULL */
+ drive-strength = <2>; /* 2 MA */
+ };
+ };
+
+ /* HS UART CONFIGURATION */
+ blsp1_uart1_active: blsp1_uart1_active {
+ mux {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "blsp_uart1";
+ };
+
+ config {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp1_uart1_sleep: blsp1_uart1_sleep {
+ mux {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp1_uart2_active: blsp1_uart2_active {
+ mux {
+ pins = "gpio4", "gpio5", "gpio6", "gpio7";
+ function = "blsp_uart2 ";
+ };
+
+ config {
+ pins = "gpio4", "gpio5", "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp1_uart2_sleep: blsp1_uart2_sleep {
+ mux {
+ pins = "gpio4", "gpio5", "gpio6", "gpio7";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio4", "gpio5", "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp2_uart1: blsp2_uart1 {
+ blsp2_uart1_tx_active: blsp2_uart1_tx_active {
+ mux {
+ pins = "gpio16";
+ function = "blsp_uart5";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp2_uart1_tx_sleep: blsp2_uart1_tx_sleep {
+ mux {
+ pins = "gpio16";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio16";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ blsp2_uart1_rxcts_active: blsp2_uart1_rxcts_active {
+ mux {
+ pins = "gpio17", "gpio18";
+ function = "blsp_uart5";
+ };
+
+ config {
+ pins = "gpio17", "gpio18";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp2_uart1_rxcts_sleep: blsp2_uart1_rxcts_sleep {
+ mux {
+ pins = "gpio17", "gpio18";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio17", "gpio18";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+
+ blsp2_uart1_rfr_active: blsp2_uart1_rfr_active {
+ mux {
+ pins = "gpio19";
+ function = "blsp_uart5";
+ };
+
+ config {
+ pins = "gpio19";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp2_uart1_rfr_sleep: blsp2_uart1_rfr_sleep {
+ mux {
+ pins = "gpio19";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio19";
+ drive-strength = <2>;
+ bias-no-pull;
+ };
+ };
+ };
+
+ blsp2_uart2_active: blsp2_uart2_active {
+ mux {
+ pins = "gpio24", "gpio25", "gpio26", "gpio27";
+ function = "blsp_uart6_a";
+ };
+
+ config {
+ pins = "gpio24", "gpio25", "gpio26", "gpio27";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ blsp2_uart2_sleep: blsp2_uart2_sleep {
+ mux {
+ pins = "gpio24", "gpio25", "gpio26", "gpio27";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio24", "gpio25", "gpio26", "gpio27";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ tlmm_gpio_key {
+ gpio_key_active: gpio_key_active {
+ mux {
+ pins = "gpio64", "gpio113";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio64", "gpio113";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ gpio_key_suspend: gpio_key_suspend {
+ mux {
+ pins = "gpio64", "gpio113";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio64", "gpio113";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_mdss: pmx_mdss {
+ mdss_dsi_active: mdss_dsi_active {
+ mux {
+ pins = "gpio53";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio53";
+ drive-strength = <8>; /* 8 mA */
+ bias-disable = <0>; /* no pull */
+ };
+ };
+ mdss_dsi_suspend: mdss_dsi_suspend {
+ mux {
+ pins = "gpio53";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio53";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* pull down */
+ };
+ };
+ };
+
+ pmx_mdss_te {
+ mdss_te_active: mdss_te_active {
+ mux {
+ pins = "gpio59";
+ function = "mdp_vsync";
+ };
+ config {
+ pins = "gpio59";
+ drive-strength = <2>; /* 8 mA */
+ bias-pull-down; /* pull down*/
+ };
+ };
+
+ mdss_te_suspend: mdss_te_suspend {
+ mux {
+ pins = "gpio59";
+ function = "mdp_vsync";
+ };
+ config {
+ pins = "gpio59";
+ drive-strength = <2>; /* 2 mA */
+ bias-pull-down; /* pull down */
+ };
+ };
+ };
+
+ mdss_dp_aux_active: mdss_dp_aux_active {
+ mux {
+ pins = "gpio55", "gpio56";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio55", "gpio56";
+ bias-disable = <0>; /* no pull */
+ drive-strength = <8>;
+ };
+ };
+
+ mdss_dp_aux_suspend: mdss_dp_aux_suspend {
+ mux {
+ pins = "gpio55", "gpio56";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio55", "gpio56";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+ };
+
+ mdss_dp_usbplug_cc_active: mdss_dp_usbplug_cc_active {
+ mux {
+ pins = "gpio58";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio58";
+ bias-disable;
+ drive-strength = <16>;
+ };
+ };
+
+ mdss_dp_usbplug_cc_suspend: mdss_dp_usbplug_cc_suspend {
+ mux {
+ pins = "gpio58";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio58";
+ bias-pull-down;
+ drive-strength = <2>;
+ };
+ };
+
+ ts_mux {
+ ts_active: ts_active {
+ mux {
+ pins = "gpio66", "gpio67";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio66", "gpio67";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+
+ ts_reset_suspend: ts_reset_suspend {
+ mux {
+ pins = "gpio66";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio66";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ ts_int_suspend: ts_int_suspend {
+ mux {
+ pins = "gpio67";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio67";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-pm.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm.dtsi
new file mode 100755
index 0000000..60e3d0a
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm.dtsi
@@ -0,0 +1,286 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+ qcom,spm@178120000 {
+ compatible = "qcom,spm-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x17812000 0x1000>;
+ qcom,name = "gold-l2"; /* Gold L2 SAW */
+ qcom,saw2-ver-reg = <0xfd0>;
+ qcom,cpu-vctl-list = <&CPU4 &CPU5 &CPU6 &CPU7>;
+ qcom,vctl-timeout-us = <500>;
+ qcom,vctl-port = <0x0>;
+ qcom,phase-port = <0x1>;
+ qcom,saw2-avs-ctl = <0x1010031>;
+ qcom,saw2-avs-limit = <0x4580458>;
+ qcom,pfm-port = <0x2>;
+ };
+
+ qcom,spm@179120000 {
+ compatible = "qcom,spm-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x17912000 0x1000>;
+ qcom,name = "silver-l2"; /* Silver L2 SAW */
+ qcom,saw2-ver-reg = <0xfd0>;
+ qcom,cpu-vctl-list = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,vctl-timeout-us = <500>;
+ qcom,vctl-port = <0x0>;
+ qcom,phase-port = <0x1>;
+ qcom,saw2-avs-ctl = <0x1010031>;
+ qcom,saw2-avs-limit = <0x4580458>;
+ qcom,pfm-port = <0x2>;
+ };
+
+ qcom,lpm-levels {
+ compatible = "qcom,lpm-levels";
+ qcom,use-psci;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,pm-cluster@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "system";
+ qcom,spm-device-names = "cci";
+ qcom,psci-mode-shift = <8>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cluster-level@0{
+ reg = <0>;
+ label = "system-wfi";
+ qcom,psci-mode = <0x0>;
+ qcom,entry-latency-us = <640>;
+ qcom,exit-latency-us = <1654>;
+ qcom,min-residency-us = <2294>;
+ };
+
+ qcom,pm-cluster-level@1{ /* E3 */
+ reg = <1>;
+ label = "system-pc";
+ qcom,psci-mode = <0x3>;
+ qcom,entry-latency-us = <10831>;
+ qcom,exit-latency-us = <4506>;
+ qcom,min-residency-us = <15337>;
+ qcom,min-child-idx = <3>;
+ qcom,is-reset;
+ qcom,notify-rpm;
+ };
+
+ qcom,pm-cluster@0{
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "pwr";
+ qcom,spm-device-names = "l2";
+ qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,psci-mode-shift = <4>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cluster-level@0{ /* D1 */
+ reg = <0>;
+ label = "pwr-l2-wfi";
+ qcom,psci-mode = <0x1>;
+ qcom,entry-latency-us = <38>;
+ qcom,exit-latency-us = <51>;
+ qcom,min-residency-us = <89>;
+ };
+ qcom,pm-cluster-level@1{ /* D2D */
+ reg = <1>;
+ label = "pwr-l2-dynret";
+ qcom,psci-mode = <0x2>;
+ qcom,entry-latency-us = <360>;
+ qcom,exit-latency-us = <421>;
+ qcom,min-residency-us = <781>;
+ qcom,min-child-idx = <1>;
+ };
+
+ qcom,pm-cluster-level@2{ /* D2E */
+ reg = <2>;
+ label = "pwr-l2-ret";
+ qcom,psci-mode = <0x3>;
+ qcom,entry-latency-us = <800>;
+ qcom,exit-latency-us = <517>;
+ qcom,min-residency-us = <922>;
+ qcom,min-child-idx = <2>;
+ };
+
+ qcom,pm-cluster-level@3{ /* D4 */
+ reg = <3>;
+ label = "pwr-l2-pc";
+ qcom,psci-mode = <0x4>;
+ qcom,entry-latency-us = <800>;
+ qcom,exit-latency-us = <2118>;
+ qcom,min-residency-us = <2918>;
+ qcom,min-child-idx = <2>;
+ qcom,is-reset;
+ };
+
+ qcom,pm-cpu {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+ qcom,disable-ipi-prediction;
+ qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ qcom,pm-cpu-level@0 { /* C1 */
+ reg = <0>;
+ label = "wfi";
+ qcom,psci-cpu-mode = <0x1>;
+ qcom,entry-latency-us = <49>;
+ qcom,exit-latency-us = <42>;
+ qcom,min-residency-us = <91>;
+ };
+
+ qcom,pm-cpu-level@1 { /* C2D */
+ reg = <1>;
+ qcom,psci-cpu-mode = <2>;
+ label = "ret";
+ qcom,entry-latency-us = <70>;
+ qcom,exit-latency-us = <63>;
+ qcom,min-residency-us = <172>;
+ };
+
+ qcom,pm-cpu-level@2 { /* C3 */
+ reg = <2>;
+ label = "pc";
+ qcom,psci-cpu-mode = <0x3>;
+ qcom,entry-latency-us = <290>;
+ qcom,exit-latency-us = <376>;
+ qcom,min-residency-us = <666>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+ };
+ };
+
+ qcom,pm-cluster@1{
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "perf";
+ qcom,spm-device-names = "l2";
+ qcom,psci-mode-shift = <4>;
+ qcom,psci-mode-mask = <0xf>;
+
+ qcom,pm-cluster-level@0{ /* D1 */
+ reg = <0>;
+ label = "perf-l2-wfi";
+ qcom,psci-mode = <0x1>;
+ qcom,entry-latency-us = <38>;
+ qcom,exit-latency-us = <51>;
+ qcom,min-residency-us = <89>;
+ };
+
+ qcom,pm-cluster-level@1{ /* D2D */
+ reg = <1>;
+ label = "perf-l2-dynret";
+ qcom,psci-mode = <2>;
+ qcom,entry-latency-us = <314>;
+ qcom,exit-latency-us = <345>;
+ qcom,min-residency-us = <659>;
+ qcom,min-child-idx = <1>;
+ };
+
+ qcom,pm-cluster-level@2{ /* D2E */
+ reg = <2>;
+ label = "perf-l2-ret";
+ qcom,psci-mode = <3>;
+ qcom,entry-latency-us = <375>;
+ qcom,exit-latency-us = <419>;
+ qcom,min-residency-us = <737>;
+ qcom,min-child-idx = <2>;
+ };
+
+ qcom,pm-cluster-level@3{ /* D4 */
+ reg = <3>;
+ label = "perf-l2-pc";
+ qcom,psci-mode = <0x4>;
+ qcom,entry-latency-us = <640>;
+ qcom,exit-latency-us = <1654>;
+ qcom,min-residency-us = <2294>;
+ qcom,min-child-idx = <2>;
+ qcom,is-reset;
+ };
+
+ qcom,pm-cpu {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,psci-mode-shift = <0>;
+ qcom,psci-mode-mask = <0xf>;
+ qcom,disable-ipi-prediction;
+ qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>;
+
+ qcom,pm-cpu-level@0 { /* C1 */
+ reg = <0>;
+ label = "wfi";
+ qcom,psci-cpu-mode = <0x1>;
+ qcom,entry-latency-us = <29>;
+ qcom,exit-latency-us = <39>;
+ qcom,min-residency-us = <68>;
+ };
+
+ qcom,pm-cpu-level@1 { /* C2D */
+ reg = <1>;
+ qcom,psci-cpu-mode = <2>;
+ label = "ret";
+ qcom,entry-latency-us = <50>;
+ qcom,exit-latency-us = <60>;
+ qcom,min-residency-us = <181>;
+ };
+
+ qcom,pm-cpu-level@2 { /* C3 */
+ reg = <2>;
+ label = "pc";
+ qcom,psci-cpu-mode = <0x3>;
+ qcom,entry-latency-us = <297>;
+ qcom,exit-latency-us = <324>;
+ qcom,min-residency-us = <621>;
+ qcom,is-reset;
+ qcom,use-broadcast-timer;
+ };
+ };
+ };
+ };
+ };
+
+ qcom,rpm-stats@200000 {
+ compatible = "qcom,rpm-stats";
+ reg = <0x200000 0x1000>,
+ <0x290014 0x4>,
+ <0x29001c 0x4>;
+ reg-names = "phys_addr_base",
+ "offset_addr",
+ "heap_phys_addrbase";
+ qcom,sleep-stats-version = <2>;
+ };
+
+ qcom,rpm-master-stats@778150 {
+ compatible = "qcom,rpm-master-stats";
+ reg = <0x778150 0x5000>;
+ qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ";
+ qcom,master-stats-version = <2>;
+ qcom,master-offset = <4096>;
+ };
+
+/* TODO review changed values */
+ rpm_msg_ram: memory@0x778000 {
+ compatible = "qcom,rpm-msg-ram";
+ reg = <0x778000 0x7000>;
+ };
+
+ rpm_code_ram: rpm-memory@0x778000 {
+ compatible = "qcom,rpm-code-ram";
+ reg = <0x778000 0x5000>;
+ };
+
+ qcom,system-stats {
+ compatible = "qcom,system-stats";
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ qcom,rpm-code-ram = <&rpm_code_ram>;
+ qcom,masters = "APSS", "MPSS", "ADSP", "CDSP", "TZ";
+ };
+
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-cdp.dts
new file mode 100755
index 0000000..e65a5d1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-cdp.dts
@@ -0,0 +1,43 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "msm-pm660a.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A CDP";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <1 0>;
+ qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>,
+ <0x0001001b 0x0002001a 0x0 0x0>,
+ <0x0001001b 0x0202001a 0x0 0x0>;
+};
+
+&mdss_dsi {
+ hw-config = "single_dsi";
+};
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_rm67195_amoled_fhd_cmd>;
+ oledb-supply = <&pm660a_oledb>;
+ lab-supply = <&lab_regulator>;
+ ibb-supply = <&ibb_regulator>;
+};
+
+&mdss_dsi1 {
+ status = "disabled";
+ oledb-supply = <&pm660a_oledb>;
+ lab-supply = <&lab_regulator>;
+ ibb-supply = <&ibb_regulator>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
+&tasha_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-headset-jacktype-no-cdp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-headset-jacktype-no-cdp.dts
new file mode 100755
index 0000000..fba7a22
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-headset-jacktype-no-cdp.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "msm-pm660a.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A, Headset
+ Jacktype NO, CDP";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <1 2>;
+ qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>,
+ <0x0001001b 0x0002001a 0x0 0x0>,
+ <0x0001001b 0x0202001a 0x0 0x0>;
+};
+
+&mdss_dsi0 {
+ oledb-supply = <&pm660a_oledb>;
+ lab-supply = <&lab_regulator>;
+ ibb-supply = <&ibb_regulator>;
+};
+
+&mdss_dsi1 {
+ oledb-supply = <&pm660a_oledb>;
+ lab-supply = <&lab_regulator>;
+ ibb-supply = <&ibb_regulator>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-headset-jacktype-no-rcm.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-headset-jacktype-no-rcm.dts
new file mode 100755
index 0000000..fd7347b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-headset-jacktype-no-rcm.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "msm-pm660a.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A, Headset
+ Jacktype NO, RCM";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <21 2>;
+ qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-mtp.dts
new file mode 100755
index 0000000..971e8d1
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-mtp.dts
@@ -0,0 +1,37 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-mtp.dtsi"
+#include "msm-pm660a.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A MTP";
+ compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp";
+ qcom,board-id = <8 0>;
+ qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>,
+ <0x0001001b 0x0002001a 0x0 0x0>,
+ <0x0001001b 0x0202001a 0x0 0x0>;
+};
+
+&mdss_dsi {
+ hw-config = "single_dsi";
+};
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_rm67195_amoled_fhd_cmd>;
+ oledb-supply = <&pm660a_oledb>;
+ lab-supply = <&lab_regulator>;
+ ibb-supply = <&ibb_regulator>;
+};
+
+&mdss_dsi1 {
+ status = "disabled";
+ oledb-supply = <&pm660a_oledb>;
+ lab-supply = <&lab_regulator>;
+ ibb-supply = <&ibb_regulator>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-moist-cfg = <0>, <0>, <3>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-qrd.dts
new file mode 100755
index 0000000..a580211
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-qrd.dts
@@ -0,0 +1,45 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-qrd.dtsi"
+#include "msm-pm660a.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A QRD";
+ compatible = "qcom,sdm660-qrd", "qcom,sdm660", "qcom,qrd";
+ qcom,board-id = <0x0012000b 0>;
+ qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>,
+ <0x0001001b 0x0002001a 0x0 0x0>,
+ <0x0001001b 0x0202001a 0x0 0x0>;
+};
+
+&pm660a_oledb {
+ status = "okay";
+ qcom,oledb-default-voltage-mv = <6400>;
+};
+
+&mdss_mdp {
+ qcom,mdss-pref-prim-intf = "dsi";
+};
+
+&mdss_dsi {
+ hw-config = "single_dsi";
+};
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_rm67195_amoled_fhd_cmd>;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+ pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+ lab-supply = <&lab_regulator>;
+ ibb-supply = <&ibb_regulator>;
+ qcom,platform-reset-gpio = <&tlmm 53 0>;
+ qcom,platform-te-gpio = <&tlmm 59 0>;
+};
+
+&dsi_rm67195_amoled_fhd_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <255>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply_labibb_amoled>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-rcm.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-rcm.dts
new file mode 100755
index 0000000..86df1b8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-rcm.dts
@@ -0,0 +1,23 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "msm-pm660a.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A RCM";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <21 0>;
+ qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
+&tasha_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-sim.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-sim.dts
new file mode 100755
index 0000000..0690856
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660a-sim.dts
@@ -0,0 +1,98 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-pinctrl.dtsi"
+#include "msm-pm660a.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660A SIM";
+ compatible = "qcom,sdm660-sim", "qcom,sdm660", "qcom,sim";
+ qcom,board-id = <16 0>;
+ qcom,pmic-id = <0x0001001b 0x0001011a 0x0 0x0>;
+
+ chosen {
+ bootargs = "lpm_levels.sleep_disabled=1";
+ };
+};
+
+&usb3 {
+ reg = <0xa800000 0xfc000>;
+ reg-names = "core_base";
+ /delete-property/ extcon;
+ dwc3@a800000 {
+ maximum-speed = "high-speed";
+ };
+};
+
+&ssphy {
+ compatible = "usb-nop-xceiv";
+};
+
+&qusb_phy0 {
+ compatible = "usb-nop-xceiv";
+};
+
+&uartblsp1dm1 {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart_console_active>;
+};
+
+&sdhc_1 {
+ /* device core power supply */
+ vdd-supply = <&pm660l_l4>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <200 570000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm660_l8>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <200 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 192000000
+ 384000000>;
+
+ qcom,nonremovable;
+ qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+
+ status = "ok";
+};
+
+&pm660_charger {
+ status = "disabled";
+};
+
+&pm660_fg {
+ status = "disabled";
+};
+
+&pm660_pdphy {
+ status = "disabled";
+};
+
+&ufsphy1 {
+ vdda-phy-supply = <&pm660l_l1>;
+ vdda-pll-supply = <&pm660_l10>;
+ vddp-ref-clk-supply = <&pm660_l1>;
+ vdda-phy-max-microamp = <51400>;
+ vdda-pll-max-microamp = <14200>;
+ vddp-ref-clk-max-microamp = <100>;
+ vddp-ref-clk-always-on;
+ status = "ok";
+};
+
+&ufs1 {
+ vdd-hba-supply = <&gdsc_ufs>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm660l_l4>;
+ vccq2-supply = <&pm660_l8>;
+ vcc-max-microamp = <500000>;
+ vccq2-max-microamp = <600000>;
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660l.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660l.dts
new file mode 100755
index 0000000..9f39885
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-pm660l.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660L SoC";
+ compatible = "qcom,sdm660";
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-qrd-external-codec-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-qrd-external-codec-overlay.dts
new file mode 100755
index 0000000..cda7513
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-qrd-external-codec-overlay.dts
@@ -0,0 +1,88 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,cpu-osm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm660-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 Ext. Audio Codec QRD";
+ compatible = "qcom,sdm660-qrd", "qcom,sdm660", "qcom,qrd";
+ qcom,board-id = <0x1000b 0>;
+};
+
+&mdss_mdp {
+ qcom,mdss-pref-prim-intf = "dsi";
+};
+
+&mdss_fb0 {
+ qcom,mdss-mixer-swap;
+};
+
+&mdss_dsi {
+ hw-config = "split_dsi";
+};
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_dual_nt36850_truly_cmd>;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+ pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+ qcom,platform-reset-gpio = <&tlmm 53 0>;
+ qcom,platform-te-gpio = <&tlmm 59 0>;
+};
+
+&mdss_dsi1 {
+ qcom,dsi-pref-prim-pan = <&dsi_dual_nt36850_truly_cmd>;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+ pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+ qcom,platform-reset-gpio = <&tlmm 53 0>;
+ qcom,platform-te-gpio = <&tlmm 59 0>;
+};
+
+&dsi_dual_nt36850_truly_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&pm660l_wled {
+ qcom,string-cfg = <3>;
+ status = "ok";
+};
+
+&soc {
+ hbtp {
+ compatible = "qcom,hbtp-input";
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
+ pinctrl-0 = <&ts_rst_active>;
+ pinctrl-1 = <&ts_rst_suspend>;
+ vcc_ana-supply = <&pm660l_l3>;
+ vcc_dig-supply = <&pm660_l13>;
+ qcom,afe-load = <20000>;
+ qcom,afe-vtg-min = <3008000>;
+ qcom,afe-vtg-max = <3008000>;
+ qcom,dig-load = <40000>;
+ qcom,dig-vtg-min = <1808000>;
+ qcom,dig-vtg-max = <1808000>;
+ qcom,fb-resume-delay-us = <10000>;
+ qcom,afe-force-power-on;
+ qcom,afe-power-on-delay-us = <1000>;
+ qcom,afe-power-off-delay-us = <6>;
+ };
+};
+
+&slim_aud {
+ /delete-node/wcd934x_cdc;
+};
+
+&soc {
+ /delete-node/sound-tavil;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-qrd.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-qrd.dts
new file mode 100755
index 0000000..2504c6b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-qrd.dts
@@ -0,0 +1,89 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-qrd.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L QRD";
+ compatible = "qcom,sdm660-qrd", "qcom,sdm660", "qcom,qrd";
+ qcom,board-id = <0x1000b 0>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>;
+};
+
+&mdss_mdp {
+ qcom,mdss-pref-prim-intf = "dsi";
+};
+
+&mdss_fb0 {
+ qcom,mdss-mixer-swap;
+};
+
+&mdss_dsi {
+ hw-config = "split_dsi";
+};
+
+&mdss_dsi0 {
+ qcom,dsi-pref-prim-pan = <&dsi_dual_nt36850_truly_cmd>;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+ pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+ qcom,platform-reset-gpio = <&tlmm 53 0>;
+ qcom,platform-te-gpio = <&tlmm 59 0>;
+};
+
+&mdss_dsi1 {
+ qcom,dsi-pref-prim-pan = <&dsi_dual_nt36850_truly_cmd>;
+ pinctrl-names = "mdss_default", "mdss_sleep";
+ pinctrl-0 = <&mdss_dsi_active &mdss_te_active>;
+ pinctrl-1 = <&mdss_dsi_suspend &mdss_te_suspend>;
+ qcom,platform-reset-gpio = <&tlmm 53 0>;
+ qcom,platform-te-gpio = <&tlmm 59 0>;
+};
+
+&dsi_dual_nt36850_truly_cmd {
+ qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled";
+ qcom,mdss-dsi-bl-min-level = <1>;
+ qcom,mdss-dsi-bl-max-level = <4095>;
+ qcom,panel-supply-entries = <&dsi_panel_pwr_supply>;
+};
+
+&pm660l_wled {
+ qcom,string-cfg= <6>;
+ status = "ok";
+};
+
+&pm660l_lcdb {
+ status = "ok";
+};
+
+&soc {
+ hbtp {
+ compatible = "qcom,hbtp-input";
+ pinctrl-names = "pmx_ts_active", "pmx_ts_suspend";
+ pinctrl-0 = <&ts_rst_active>;
+ pinctrl-1 = <&ts_rst_suspend>;
+ vcc_ana-supply = <&pm660l_l3>;
+ vcc_dig-supply = <&pm660_l13>;
+ qcom,afe-load = <20000>;
+ qcom,afe-vtg-min = <3008000>;
+ qcom,afe-vtg-max = <3008000>;
+ qcom,dig-load = <40000>;
+ qcom,dig-vtg-min = <1808000>;
+ qcom,dig-vtg-max = <1808000>;
+ qcom,fb-resume-delay-us = <10000>;
+ qcom,afe-force-power-on;
+ qcom,afe-power-on-delay-us = <1000>;
+ qcom,afe-power-off-delay-us = <6>;
+ };
+};
+
+&slim_aud {
+ /delete-node/wcd934x_cdc;
+};
+
+&soc {
+ /delete-node/sound-tavil;
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-qrd.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-qrd.dtsi
new file mode 100755
index 0000000..fc292ee
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-qrd.dtsi
@@ -0,0 +1,297 @@
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "sdm660-camera-sensor-qrd.dtsi"
+#include "sdm660-external-codec.dtsi"
+/ {
+};
+
+&blsp2_uart1_hs {
+ status = "ok";
+};
+
+&uartblsp1dm1 {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart_console_active>;
+};
+
+&sdhc_1 {
+ /* device core power supply */
+ vdd-supply = <&pm660l_l4>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <200 570000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm660_l8>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <200 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdc2_cd_on {
+ config {
+ /delete-property/ bias-pull-up;
+ bias-disable;
+ };
+};
+
+&sdhc_2 {
+ /* device core power supply */
+ vdd-supply = <&pm660l_l5>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <15000 800000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm660l_l2>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ #address-cells = <0>;
+ interrupt-parent = <&sdhc_2>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 0 125 0
+ 1 &intc 0 0 221 0
+ 2 &tlmm 54 0>;
+ interrupt-names = "hc_irq", "pwr_irq", "status_irq";
+ cd-gpios = <&tlmm 54 0x0>;
+
+ status = "ok";
+};
+
+&ufsphy1 {
+ vdda-phy-supply = <&pm660l_l1>;
+ vdda-pll-supply = <&pm660_l10>;
+ vddp-ref-clk-supply = <&pm660_l1>;
+ vdda-phy-max-microamp = <51400>;
+ vdda-pll-max-microamp = <14200>;
+ vddp-ref-clk-max-microamp = <100>;
+ vddp-ref-clk-always-on;
+ status = "ok";
+};
+
+&ufs1 {
+ vdd-hba-supply = <&gdsc_ufs>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm660l_l4>;
+ vccq2-supply = <&pm660_l8>;
+ vcc-max-microamp = <500000>;
+ vccq2-max-microamp = <600000>;
+ status = "ok";
+};
+
+&soc {
+ qcom,msm-ssc-sensors {
+ compatible = "qcom,msm-ssc-sensors";
+ };
+};
+
+&qusb_phy0 {
+ qcom,qusb-phy-init-seq = <0xf8 0x80
+ 0x83 0x84
+ 0x83 0x88
+ 0xc3 0x8c
+ 0x30 0x08
+ 0x79 0x0c
+ 0x21 0x10
+ 0x14 0x9c
+ 0x9f 0x1c
+ 0x00 0x18>;
+};
+
+&pm660_gpios {
+ /* GPIO 4 (NFC_CLK_REQ) */
+ nfc_clk {
+ nfc_clk_default: nfc_clk_default {
+ pins = "gpio4";
+ function = "normal";
+ input-enable;
+ power-source = <1>;
+ };
+ };
+};
+
+&i2c_6 { /* BLSP1 QUP6 (NFC) */
+ status = "okay";
+ nq@28 {
+ compatible = "qcom,nq-nci";
+ reg = <0x28>;
+ qcom,nq-irq = <&tlmm 28 0x00>;
+ qcom,nq-ven = <&tlmm 29 0x00>;
+ qcom,nq-firm = <&tlmm 30 0x00>;
+ qcom,nq-clkreq = <&pm660_gpios 4 0x00>;
+ qcom,nq-esepwr = <&tlmm 31 0x00>;
+ interrupt-parent = <&tlmm>;
+ qcom,clk-src = "BBCLK3";
+ interrupts = <28 0>;
+ interrupt-names = "nfc_irq";
+ pinctrl-names = "nfc_active", "nfc_suspend";
+ pinctrl-0 = <&nfc_int_active &nfc_enable_active
+ &nfc_clk_default>;
+ pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>;
+ clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK3_PIN>;
+ clock-names = "ref_clk";
+ };
+};
+
+&pm660l_gpios {
+ /* GPIO 7 for VOL_UP */
+ key_vol_up {
+ key_vol_up_default: key_vol_up_default {
+ pins = "gpio7";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ };
+ };
+};
+
+&tlmm {
+ pmx_ts_rst_active {
+ ts_rst_active: ts_rst_active {
+ mux {
+ pins = "gpio66";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio66";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+ };
+ };
+
+ pmx_ts_rst_suspend {
+ ts_rst_suspend: ts_rst_suspend {
+ mux {
+ pins = "gpio66";
+ function = "gpio";
+ };
+
+ config {
+ pins = "gpio66";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
+};
+
+&ssphy {
+ fpc-redrive-supply = <&pm660_l11>;
+ qcom,redrive-voltage-level = <0 1800000 1950000>;
+ qcom,redrive-load = <105000>;
+};
+
+&soc {
+ gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&key_vol_up_default>;
+ status = "ok";
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ linux,code = <KEY_VOLUMEUP>;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ };
+ };
+};
+
+/ {
+ qrd_batterydata: qcom,battery-data {
+ qcom,batt-id-range-pct = <15>;
+
+ #include "fg-gen3-batterydata-qrd-skuk-4v4-3000mah.dtsi"
+ };
+};
+
+&pm660_fg {
+ qcom,battery-data = <&qrd_batterydata>;
+ qcom,fg-jeita-thresholds = <0 5 55 55>;
+ qcom,battery-thermal-coefficients = [9d 50 ff];
+};
+
+&pm660_haptics {
+ qcom,vmax-mv = <1800>;
+};
+
+&i2c_2 {
+ status = "ok";
+ smb1351_charger: smb1351-charger@1d {
+ compatible = "qcom,smb1351-charger";
+ reg = <0x1d>;
+ qcom,parallel-charger;
+ qcom,float-voltage-mv = <4400>;
+ qcom,recharge-mv = <100>;
+ qcom,parallel-en-pin-polarity = <1>;
+ };
+};
+
+&wcd934x_cdc {
+ status = "disabled";
+};
+
+&tavil_snd {
+ status = "disabled";
+};
+
+&clock_audio_lnbb {
+ status = "disabled";
+};
+
+&clock_audio {
+ status = "ok";
+};
+
+&clock_audio_native {
+ status = "ok";
+};
+
+&wcd9335 {
+ status = "ok";
+};
+
+&tasha_snd {
+ status = "ok";
+ qcom,model = "sdm660-tasha-skus-snd-card";
+ qcom,audio-routing =
+ "AIF4 VI", "MCLK",
+ "RX_BIAS", "MCLK",
+ "MADINPUT", "MCLK",
+ "AMIC2", "MIC BIAS2",
+ "MIC BIAS2", "Headset Mic",
+ "DMIC0", "MIC BIAS1",
+ "MIC BIAS1", "Digital Mic0",
+ "DMIC3", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic3",
+ "DMIC5", "MIC BIAS3",
+ "MIC BIAS3", "Digital Mic5",
+ "SpkrLeft IN", "SPK1 OUT";
+ qcom,msm-mbhc-hphl-swh = <1>;
+ qcom,msm-mbhc-gnd-swh = <1>;
+ /delete-property/ qcom,us-euro-gpios;
+ /delete-property/ qcom,hph-en0-gpio;
+ /delete-property/ qcom,hph-en1-gpio;
+ qcom,wsa-max-devs = <1>;
+ qcom,wsa-devs = <&wsa881x_211>, <&wsa881x_213>;
+ qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrLeft";
+};
+
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-rcm-external-codec-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-rcm-external-codec-overlay.dts
new file mode 100755
index 0000000..1f4d02f
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-rcm-external-codec-overlay.dts
@@ -0,0 +1,28 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,cpu-osm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm660-cdp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 Ext. Audio Codec RCM";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <21 0>;
+};
+
+
+&tavil_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
+&tasha_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-rcm-internal-codec-overlay.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-rcm-internal-codec-overlay.dts
new file mode 100755
index 0000000..2138183
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-rcm-internal-codec-overlay.dts
@@ -0,0 +1,17 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,cpu-osm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "sdm660-cdp.dtsi"
+#include "sdm660-internal-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 Int. Audio Codec RCM";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <21 1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-rcm.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-rcm.dts
new file mode 100755
index 0000000..73a8166
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-rcm.dts
@@ -0,0 +1,23 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L RCM";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <21 0>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
+
+&tasha_snd {
+ qcom,msm-mbhc-hphl-swh = <0>;
+ qcom,msm-mbhc-gnd-swh = <0>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-regulator.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-regulator.dtsi
new file mode 100755
index 0000000..bc317a3
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-regulator.dtsi
@@ -0,0 +1,949 @@
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+#include <dt-bindings/clock/qcom,gpu-sdm660.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&rpm_bus {
+ rpm-regulator-smpa4 {
+ status = "okay";
+ pm660_s4: regulator-s4 {
+ regulator-min-microvolt = <1805000>;
+ regulator-max-microvolt = <2040000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpa5 {
+ status = "okay";
+ pm660_s5: regulator-s5 {
+ regulator-min-microvolt = <1224000>;
+ regulator-max-microvolt = <1350000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpa6 {
+ status = "okay";
+ pm660_s6: regulator-s6 {
+ regulator-min-microvolt = <504000>;
+ regulator-max-microvolt = <992000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpb1 {
+ status = "okay";
+ pm660l_s1: regulator-s1 {
+ regulator-min-microvolt = <1125000>;
+ regulator-max-microvolt = <1125000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-smpb2 {
+ status = "okay";
+ pm660l_s2: regulator-s2 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ status = "okay";
+ };
+ };
+
+ /* PM660L S3 + S4 - VDD_CX supply */
+ rpm-regulator-smpb3 {
+ status = "okay";
+ pm660l_s3_level: regulator-s3-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_s3_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ };
+
+ pm660l_s3_floor_level: regulator-s3-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_s3_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+
+ pm660l_s3_level_ao: regulator-s3-level-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_s3_level_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ };
+
+ cx_cdev: cx-cdev {
+ compatible = "qcom,regulator-cooling-device";
+ regulator-cdev-supply = <&pm660l_s3_floor_level>;
+ regulator-levels = <RPM_SMD_REGULATOR_LEVEL_NOM
+ RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ #cooling-cells = <2>;
+ };
+
+ };
+
+ /* PM660L S5 - VDD_MX supply */
+ rpm-regulator-smpb5 {
+ status = "okay";
+ pm660l_s5_level: regulator-s5-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_s5_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ };
+
+ pm660l_s5_floor_level: regulator-s5-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_s5_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+
+ pm660l_s5_level_ao: regulator-s5-level-ao {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_s5_level_ao";
+ qcom,set = <1>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ };
+ };
+
+ rpm-regulator-ldoa1 {
+ status = "okay";
+ pm660_l1: regulator-l1 {
+ regulator-min-microvolt = <1150000>;
+ regulator-max-microvolt = <1250000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa2 {
+ status = "okay";
+ pm660_l2: regulator-l2 {
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1010000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa3 {
+ status = "okay";
+ pm660_l3: regulator-l3 {
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1010000>;
+ status = "okay";
+ };
+ };
+
+ /* TODO: remove if ADRASTEA CX/MX not voted from APPS */
+ rpm-regulator-ldoa5 {
+ status = "okay";
+ pm660_l5: regulator-l5 {
+ regulator-min-microvolt = <525000>;
+ regulator-max-microvolt = <950000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa6 {
+ status = "okay";
+ pm660_l6: regulator-l6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1370000>;
+ status = "okay";
+ };
+
+ pm660_l6_pin_ctrl: regulator-l6-pin-ctrl {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l6_pin_ctrl";
+ qcom,set = <3>;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1370000>;
+ /* Force NPM follows HW_EN1 */
+ qcom,init-pin-ctrl-mode = <2>;
+ /* Enable follows HW_EN1 */
+ qcom,enable-with-pin-ctrl = <0 2>;
+ };
+ };
+
+ rpm-regulator-ldoa7 {
+ status = "okay";
+ pm660_l7: regulator-l7 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa8 {
+ status = "okay";
+ pm660_l8: regulator-l8 {
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <1900000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa9 {
+ status = "okay";
+ pm660_l9: regulator-l9 {
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <1900000>;
+ status = "okay";
+ };
+
+ pm660_l9_pin_ctrl: regulator-l9-pin-ctrl {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l9_pin_ctrl";
+ qcom,set = <3>;
+ regulator-min-microvolt = <1750000>;
+ regulator-max-microvolt = <1900000>;
+ /* Force NPM follows HW_EN1 */
+ qcom,init-pin-ctrl-mode = <2>;
+ /* Enable follows HW_EN1 */
+ qcom,enable-with-pin-ctrl = <0 2>;
+ };
+ };
+
+ rpm-regulator-ldoa10 {
+ status = "okay";
+ pm660_l10: regulator-l10 {
+ proxy-supply = <&pm660_l10>;
+ qcom,proxy-consumer-enable;
+ qcom,proxy-consumer-current = <14000>;
+ regulator-min-microvolt = <1780000>;
+ regulator-max-microvolt = <1950000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa11 {
+ status = "okay";
+ pm660_l11: regulator-l11 {
+ regulator-min-microvolt = <1780000>;
+ regulator-max-microvolt = <1950000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa12 {
+ status = "okay";
+ pm660_l12: regulator-l12 {
+ regulator-min-microvolt = <1780000>;
+ regulator-max-microvolt = <1950000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa13 {
+ status = "okay";
+ pm660_l13: regulator-l13 {
+ regulator-min-microvolt = <1780000>;
+ regulator-max-microvolt = <1950000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa14 {
+ status = "okay";
+ pm660_l14: regulator-l14 {
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1900000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa15 {
+ status = "okay";
+ pm660_l15: regulator-l15 {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2950000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa17 {
+ status = "okay";
+ pm660_l17: regulator-l17 {
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2950000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldoa19 {
+ status = "okay";
+ pm660_l19: regulator-l19 {
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3400000>;
+ status = "okay";
+ };
+
+ pm660_l19_pin_ctrl: regulator-l19-pin-ctrl {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660_l19_pin_ctrl";
+ qcom,set = <3>;
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3400000>;
+ /* Force NPM follows HW_EN1 */
+ qcom,init-pin-ctrl-mode = <2>;
+ /* Enable follows HW_EN1 */
+ qcom,enable-with-pin-ctrl = <0 2>;
+ };
+ };
+
+ rpm-regulator-ldob1 {
+ status = "okay";
+ pm660l_l1: regulator-l1 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <925000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldob2 {
+ status = "okay";
+ pm660l_l2: regulator-l2 {
+ regulator-min-microvolt = <350000>;
+ regulator-max-microvolt = <3100000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldob3 {
+ status = "okay";
+ pm660l_l3: regulator-l3 {
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <3600000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldob4 {
+ status = "okay";
+ pm660l_l4: regulator-l4 {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <2950000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldob5 {
+ status = "okay";
+ pm660l_l5: regulator-l5 {
+ regulator-min-microvolt = <1721000>;
+ regulator-max-microvolt = <3600000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldob6 {
+ status = "okay";
+ pm660l_l6: regulator-l6 {
+ regulator-min-microvolt = <1700000>;
+ regulator-max-microvolt = <3300000>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldob7 {
+ status = "okay";
+ pm660l_l7: regulator-l7 {
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3125000>;
+ parent-supply = <&pm660_l10>;
+ status = "okay";
+ };
+ };
+
+ rpm-regulator-ldob8 {
+ status = "okay";
+ pm660l_l8: regulator-l8 {
+ regulator-min-microvolt = <3200000>;
+ regulator-max-microvolt = <3400000>;
+ status = "okay";
+ };
+ };
+
+ /* PM660L L9 = VDD_SSC_CX supply */
+ rpm-regulator-ldob9 {
+ status = "okay";
+ pm660l_l9_level: regulator-l9-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_l9_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ };
+
+ pm660l_l9_floor_level: regulator-l9-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_l9_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+ };
+
+ /* PM660L L10 = VDD_SSC_MX supply */
+ rpm-regulator-ldob10 {
+ status = "okay";
+ pm660l_l10_level: regulator-l10-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_l10_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-level;
+ };
+
+ pm660l_l10_floor_level: regulator-l10-floor-level {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_l10_floor_level";
+ qcom,set = <3>;
+ regulator-min-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_RETENTION>;
+ regulator-max-microvolt =
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,use-voltage-floor-level;
+ qcom,always-send-voltage;
+ };
+ };
+
+ rpm-regulator-bobb {
+ status = "okay";
+ pm660l_bob: regulator-bob {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3600000>;
+ qcom,pwm-threshold-current = <2000000>;
+ qcom,init-bob-mode = <2>;
+ status = "okay";
+ };
+
+ pm660l_bob_pin1: regulator-bob-pin1 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_bob_pin1";
+ qcom,set = <3>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3600000>;
+ qcom,pwm-threshold-current = <2000000>;
+ qcom,init-bob-mode = <2>;
+ qcom,use-pin-ctrl-voltage1;
+ };
+
+ pm660l_bob_pin2: regulator-bob-pin2 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_bob_pin2";
+ qcom,set = <3>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3600000>;
+ qcom,pwm-threshold-current = <2000000>;
+ qcom,init-bob-mode = <2>;
+ qcom,use-pin-ctrl-voltage2;
+ };
+
+ pm660l_bob_pin3: regulator-bob-pin3 {
+ compatible = "qcom,rpm-smd-regulator";
+ regulator-name = "pm660l_bob_pin3";
+ qcom,set = <3>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3600000>;
+ qcom,pwm-threshold-current = <2000000>;
+ qcom,init-bob-mode = <2>;
+ qcom,use-pin-ctrl-voltage3;
+ };
+ };
+};
+
+&pm660_charger {
+ smb2_vbus: qcom,smb2-vbus {
+ regulator-name = "smb2-vbus";
+ };
+
+ smb2_vconn: qcom,smb2-vconn {
+ regulator-name = "smb2-vconn";
+ };
+};
+
+/* Stub regulators */
+/ {
+ /* GFX Supply */
+ gfx_stub_vreg: regulator-gfx-stub {
+ compatible = "qcom,stub-regulator";
+ regulator-name = "gfx_stub_corner";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1070000>;
+ };
+};
+
+&soc {
+ /* MEM ACC regulators */
+ gfx_mem_acc_vreg: regulator@01fcf004 {
+ compatible = "qcom,mem-acc-regulator";
+ reg = <0x01fcf004 0x4>;
+ reg-names = "acc-sel-l1";
+ regulator-name = "gfx_mem_acc_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <2>;
+
+ qcom,corner-acc-map = <0x1 0x0>;
+ qcom,acc-sel-l1-bit-pos = <0>;
+ qcom,acc-sel-l1-bit-size = <1>;
+ };
+
+ gfx_ldo_vreg: ldo@0506e000 {
+ compatible = "qcom,sdm660-gfx-ldo";
+ reg = <0x0506e000 0x34>;
+ reg-names = "ldo_addr";
+ regulator-name = "msm_gfx_ldo";
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <925000>;
+ };
+
+/* CPR controller regulators */
+ /* MMSS CPR Controller node */
+ gfx_cpr: cpr4-ctrl@05061000 {
+ compatible = "qcom,cpr4-sdm660-mmss-ldo-regulator";
+ reg = <0x05061000 0x4000>, <0x00784000 0x1000>;
+ reg-names = "cpr_ctrl", "fuse_base";
+ clocks = <&clock_gpu GPUCC_RBCPR_CLK>,
+ <&clock_rpmcc RPM_SMD_CNOC_CLK>;
+ clock-names = "core_clk", "bus_clk";
+ interrupts = <GIC_SPI 285 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "cpr";
+ qcom,cpr-ctrl-name = "gfx";
+
+
+ qcom,cpr-sensor-time = <1000>;
+ qcom,cpr-loop-time = <5000000>;
+ qcom,cpr-idle-cycles = <15>;
+ qcom,cpr-step-quot-init-min = <12>;
+ qcom,cpr-step-quot-init-max = <14>;
+ qcom,cpr-count-mode = <0>; /* All at once */
+ qcom,cpr-count-repeat = <14>;
+ qcom,cpr-reset-step-quot-loop-en;
+
+ vdd-supply = <&gfx_stub_vreg>;
+ mem-acc-supply = <&gfx_mem_acc_vreg>;
+ system-supply = <&pm660l_s3_level>; /* vdd_cx */
+ qcom,voltage-step = <5000>;
+ vdd-thread0-ldo-supply = <&gfx_ldo_vreg>;
+
+ thread@0 {
+ qcom,cpr-thread-id = <0>;
+ qcom,cpr-consecutive-up = <0>;
+ qcom,cpr-consecutive-down = <2>;
+ qcom,cpr-up-threshold = <2>;
+ qcom,cpr-down-threshold = <2>;
+
+ gfx_vreg_corner: regulator {
+ regulator-name = "gfx_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <7>;
+
+ qcom,cpr-fuse-corners = <6>;
+ qcom,cpr-fuse-combos = <8>;
+ qcom,cpr-corners = <7>;
+
+ qcom,cpr-corner-fmax-map = <1 2 3 4 5 6>;
+
+ qcom,cpr-voltage-ceiling =
+ <585000 645000 725000 790000
+ 870000 925000 1070000>;
+ qcom,cpr-voltage-floor =
+ <504000 504000 596000 652000
+ 712000 744000 1070000>;
+
+ qcom,mem-acc-voltage = <1 1 1 2 2 2 2>;
+ qcom,system-voltage =
+ <RPM_SMD_REGULATOR_LEVEL_LOW_SVS>,
+ <RPM_SMD_REGULATOR_LEVEL_LOW_SVS>,
+ <RPM_SMD_REGULATOR_LEVEL_SVS>,
+ <RPM_SMD_REGULATOR_LEVEL_SVS_PLUS>,
+ <RPM_SMD_REGULATOR_LEVEL_NOM>,
+ <RPM_SMD_REGULATOR_LEVEL_NOM_PLUS>,
+ <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+
+ qcom,corner-frequencies =
+ <160000000 266000000 370000000
+ 465000000 588000000 647000000
+ 750000000>;
+
+ qcom,cpr-target-quotients =
+ <0 0 0 0 0 0 174 167
+ 294 292 303 313 0 0 0 0>,
+ <0 0 0 0 0 0 263 247
+ 413 397 415 412 0 0 0 0>,
+ <0 0 0 0 0 0 375 354
+ 554 519 573 554 0 0 0 0>,
+ <0 0 0 0 0 0 412 380
+ 597 562 612 591 0 0 0 0>,
+ <0 0 0 0 0 0 513 476
+ 722 680 738 718 0 0 0 0>,
+ <0 0 0 0 0 0 595 553
+ 811 768 837 811 0 0 0 0>,
+ <0 0 0 0 0 0 0 0
+ 0 0 0 0 0 0 0 0>;
+
+ qcom,cpr-ro-scaling-factor =
+ < 0 0 0 0 0 0 1790 1760
+ 1990 1900 2140 2020 0 0 0 0>,
+ < 0 0 0 0 0 0 1790 1760
+ 1990 1900 2140 2020 0 0 0 0>,
+ < 0 0 0 0 0 0 1790 1760
+ 1990 1900 2140 2020 0 0 0 0>,
+ < 0 0 0 0 0 0 1790 1760
+ 1990 1900 2140 2020 0 0 0 0>,
+ < 0 0 0 0 0 0 1790 1760
+ 1990 1900 2140 2020 0 0 0 0>,
+ < 0 0 0 0 0 0 1790 1760
+ 1990 1900 2140 2020 0 0 0 0>,
+ < 0 0 0 0 0 0 1790 1760
+ 1990 1900 2140 2020 0 0 0 0>;
+
+ qcom,cpr-scaled-open-loop-voltage-as-ceiling;
+ qcom,cpr-corner-allow-ldo-mode =
+ <0 0 0 0 0 0 0>;
+ qcom,cpr-corner-allow-closed-loop =
+ <0 0 0 0 0 0 0>;
+ };
+ };
+ };
+
+ /* APC0 CPR Controller node for Silver cluster */
+ apc0_cpr: cprh-ctrl@179c8000 {
+ compatible = "qcom,cprh-sdm660-kbss-regulator";
+ reg = <0x179c8000 0x4000>, <0x00784000 0x1000>;
+ reg-names = "cpr_ctrl", "fuse_base";
+ clocks = <&clock_gcc GCC_HMSS_RBCPR_CLK>;
+ clock-names = "core_clk";
+ qcom,cpr-ctrl-name = "apc0";
+ qcom,cpr-controller-id = <0>;
+
+ qcom,cpr-sensor-time = <1000>;
+ qcom,cpr-loop-time = <5000000>;
+ qcom,cpr-idle-cycles = <15>;
+ qcom,cpr-up-down-delay-time = <3000>;
+ qcom,cpr-step-quot-init-min = <12>;
+ qcom,cpr-step-quot-init-max = <14>;
+ qcom,cpr-count-mode = <0>; /* All at once */
+ qcom,cpr-count-repeat = <14>;
+ qcom,cpr-down-error-step-limit = <1>;
+ qcom,cpr-up-error-step-limit = <1>;
+ qcom,cpr-corner-switch-delay-time = <1042>;
+ qcom,cpr-voltage-settling-time = <1760>;
+
+ qcom,apm-threshold-voltage = <872000>;
+ qcom,apm-crossover-voltage = <872000>;
+ qcom,apm-hysteresis-voltage = <20000>;
+ qcom,voltage-step = <4000>;
+ qcom,voltage-base = <400000>;
+ qcom,cpr-saw-use-unit-mV;
+ qcom,cpr-reset-step-quot-loop-en;
+
+ qcom,cpr-panic-reg-addr-list =
+ <0x179cbaa4 0x17912c18>;
+ qcom,cpr-panic-reg-name-list =
+ "PWR_CPRH_STATUS", "APCLUS0_L2_SAW4_PMIC_STS";
+
+ qcom,cpr-enable;
+ qcom,cpr-hw-closed-loop;
+
+ thread@0 {
+ qcom,cpr-thread-id = <0>;
+ qcom,cpr-consecutive-up = <0>;
+ qcom,cpr-consecutive-down = <2>;
+ qcom,cpr-up-threshold = <2>;
+ qcom,cpr-down-threshold = <2>;
+
+ apc0_pwrcl_vreg: regulator {
+ regulator-name = "apc0_pwrcl_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <8>;
+
+ qcom,cpr-fuse-corners = <5>;
+ qcom,cpr-fuse-combos = <40>;
+ qcom,cpr-speed-bins = <5>;
+ qcom,cpr-speed-bin-corners = <8 8 0 8 8>;
+ qcom,cpr-corners =
+ /* Speed bin 0 */
+ <8 8 8 8 8 8 8 8>,
+
+ /* Speed bin 1 */
+ <8 8 8 8 8 8 8 8>,
+
+ /* Speed bin 2 */
+ <0 0 0 0 0 0 0 0>,
+
+ /* Speed bin 3 */
+ <8 8 8 8 8 8 8 8>,
+
+ /* Speed bin 4 */
+ <8 8 8 8 8 8 8 8>;
+
+ qcom,cpr-corner-fmax-map =
+ /* Speed bin 0 */
+ <2 3 4 5 8>,
+
+ /* Speed bin 1 */
+ <2 3 4 5 8>,
+
+ /* Speed bin 2 */
+ <0 0 0 0 0>,
+
+ /* Speed bin 3 */
+ <2 3 4 5 8>,
+
+ /* Speed bin 4 */
+ <2 3 4 5 8>;
+
+ qcom,cpr-voltage-ceiling =
+ < 724000 724000 724000 788000 868000
+ 1068000 1068000 1068000>;
+
+ qcom,cpr-voltage-floor =
+ <588000 588000 596000 652000 712000
+ 744000 784000 844000>;
+
+ qcom,corner-frequencies =
+ /* Speed bin 0 */
+ <300000000 633600000 902400000
+ 1113600000 1401600000 1536000000
+ 1747200000 1843200000>,
+
+ /* Speed bin 1 */
+ <300000000 633600000 902400000
+ 1113600000 1401600000 1536000000
+ 1747200000 1843200000>,
+
+ /* Speed bin 3 */
+ <300000000 633600000 902400000
+ 1113600000 1401600000 1536000000
+ 1612800000 1843200000>,
+
+ /* Speed bin 4 */
+ <300000000 633600000 902400000
+ 1113600000 1401600000 1536000000
+ 1747200000 1843200000>;
+
+ qcom,allow-voltage-interpolation;
+ qcom,allow-quotient-interpolation;
+ qcom,cpr-scaled-open-loop-voltage-as-ceiling;
+
+ qcom,cpr-ro-scaling-factor =
+ <3600 3600 3830 2430 2520 2700 1790
+ 1760 1970 1880 2110 2010 2510 4900
+ 4370 4780>,
+ <3600 3600 3830 2430 2520 2700 1790
+ 1760 1970 1880 2110 2010 2510 4900
+ 4370 4780>,
+ <3600 3600 3830 2430 2520 2700 1790
+ 1760 1970 1880 2110 2010 2510 4900
+ 4370 4780>,
+ <3600 3600 3830 2430 2520 2700 1790
+ 1760 1970 1880 2110 2010 2510 4900
+ 4370 4780>,
+ <3600 3600 3830 2430 2520 2700 1790
+ 1760 1970 1880 2110 2010 2510 4900
+ 4370 4780>;
+
+ qcom,cpr-open-loop-voltage-fuse-adjustment =
+ < (-4000) 4000 7000 19000 (-8000)>;
+
+ qcom,cpr-closed-loop-voltage-fuse-adjustment =
+ <(-32000) (-30000) (-29000) (-23000)
+ (-21000)>;
+
+ qcom,cpr-floor-to-ceiling-max-range =
+ <32000 32000 32000 40000 44000
+ 40000 40000 40000>;
+ };
+ };
+ };
+
+ /* APC1 CPR Controller node for Gold cluster */
+ apc1_cpr: cprh-ctrl@179c4000 {
+ compatible = "qcom,cprh-sdm660-kbss-regulator";
+ reg = <0x179c4000 0x4000>, <0x00784000 0x1000>;
+ reg-names = "cpr_ctrl", "fuse_base";
+ clocks = <&clock_gcc GCC_HMSS_RBCPR_CLK>;
+ clock-names = "core_clk";
+ qcom,cpr-ctrl-name = "apc1";
+ qcom,cpr-controller-id = <1>;
+
+ qcom,cpr-sensor-time = <1000>;
+ qcom,cpr-loop-time = <5000000>;
+ qcom,cpr-idle-cycles = <15>;
+ qcom,cpr-up-down-delay-time = <3000>;
+ qcom,cpr-step-quot-init-min = <12>;
+ qcom,cpr-step-quot-init-max = <14>;
+ qcom,cpr-count-mode = <0>; /* All at once */
+ qcom,cpr-count-repeat = <14>;
+ qcom,cpr-down-error-step-limit = <1>;
+ qcom,cpr-up-error-step-limit = <1>;
+ qcom,cpr-corner-switch-delay-time = <1042>;
+ qcom,cpr-voltage-settling-time = <1760>;
+
+ qcom,apm-threshold-voltage = <872000>;
+ qcom,apm-crossover-voltage = <872000>;
+ qcom,apm-hysteresis-voltage = <20000>;
+ qcom,voltage-step = <4000>;
+ qcom,voltage-base = <400000>;
+ qcom,cpr-saw-use-unit-mV;
+ qcom,cpr-reset-step-quot-loop-en;
+
+ qcom,cpr-panic-reg-addr-list =
+ <0x179c7aa4 0x17812c18>;
+ qcom,cpr-panic-reg-name-list =
+ "PERF_CPRH_STATUS", "APCLUS1_L2_SAW4_PMIC_STS";
+
+ qcom,cpr-enable;
+ qcom,cpr-hw-closed-loop;
+
+ thread@0 {
+ qcom,cpr-thread-id = <0>;
+ qcom,cpr-consecutive-up = <0>;
+ qcom,cpr-consecutive-down = <2>;
+ qcom,cpr-up-threshold = <2>;
+ qcom,cpr-down-threshold = <2>;
+
+ apc1_perfcl_vreg: regulator {
+ regulator-name = "apc1_perfcl_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <7>;
+
+ qcom,cpr-fuse-corners = <5>;
+ qcom,cpr-fuse-combos = <40>;
+ qcom,cpr-speed-bins = <5>;
+ qcom,cpr-speed-bin-corners = <7 7 0 7 7>;
+ qcom,cpr-corners =
+ /* Speed-bin 0 */
+ <7 7 7 7 7 7 7 7>,
+
+ /* Speed-bin 1 */
+ <7 7 7 7 7 7 7 7>,
+
+ /* Speed-bin 1 */
+ <0 0 0 0 0 0 0 0>,
+
+ /* Speed-bin 3 */
+ <7 7 7 7 7 7 7 7>,
+
+ /* Speed-bin 4 */
+ <7 7 7 7 7 7 7 7>;
+
+ qcom,cpr-corner-fmax-map =
+ /* Speed-bin 0 */
+ <2 3 4 6 7>,
+
+ /* Speed-bin 1 */
+ <2 3 4 6 7>,
+
+ /* Speed-bin 2 */
+ <0 0 0 0 0>,
+
+ /* Speed-bin 3 */
+ <2 3 4 6 7>,
+
+ /* Speed-bin 4 */
+ <2 3 4 6 7>;
+
+ qcom,cpr-voltage-ceiling =
+ <724000 724000 788000 868000
+ 988000 988000 1068000>;
+
+ qcom,cpr-voltage-floor =
+ <588000 596000 652000 712000
+ 744000 784000 844000>;
+
+ qcom,corner-frequencies =
+ /* Speed bin 0 */
+ <300000000 1113600000 1401600000
+ 1747200000 1958400000 2150400000
+ 2457600000>,
+
+ /* Speed bin 1 */
+ <300000000 1113600000 1401600000
+ 1747200000 1958400000 2150400000
+ 2208000000>,
+
+ /* Speed bin 3 */
+ <300000000 1113600000 1401600000
+ 1747200000 1804800000 2150400000
+ 2208000000>,
+
+ /* Speed bin 4 */
+ <300000000 1113600000 1401600000
+ 1747200000 1958400000 2150400000
+ 2208000000>;
+
+ qcom,allow-voltage-interpolation;
+ qcom,allow-quotient-interpolation;
+ qcom,cpr-scaled-open-loop-voltage-as-ceiling;
+
+ qcom,cpr-ro-scaling-factor =
+ <4040 4230 0000 2210 2560 2450 2230
+ 2220 2410 2300 2560 2470 1600 3120
+ 2620 2280>,
+ <4040 4230 0000 2210 2560 2450 2230
+ 2220 2410 2300 2560 2470 1600 3120
+ 2620 2280>,
+ <4040 4230 0000 2210 2560 2450 2230
+ 2220 2410 2300 2560 2470 1600 3120
+ 2620 2280>,
+ <4040 4230 0000 2210 2560 2450 2230
+ 2220 2410 2300 2560 2470 1600 3120
+ 2620 2280>,
+ <4040 4230 0000 2210 2560 2450 2230
+ 2220 2410 2300 2560 2470 1600 3120
+ 2620 2280>;
+
+ qcom,cpr-open-loop-voltage-fuse-adjustment =
+ <16000 27000 39000 39000 20000>;
+
+ qcom,cpr-closed-loop-voltage-fuse-adjustment =
+ <(-22000) (-9000) (-7000) (-2000)
+ 11000>;
+
+ qcom,cpr-floor-to-ceiling-max-range =
+ <40000 40000 40000 40000
+ 66000 66000 40000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-sim.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-sim.dts
new file mode 100755
index 0000000..01658e9
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-sim.dts
@@ -0,0 +1,121 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-pinctrl.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L SIM";
+ compatible = "qcom,sdm660-sim", "qcom,sdm660", "qcom,sim";
+ qcom,board-id = <16 0>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>;
+
+ chosen {
+ bootargs = "lpm_levels.sleep_disabled=1";
+ };
+};
+
+&usb3 {
+ reg = <0xa800000 0xfc000>;
+ reg-names = "core_base";
+ /delete-property/ extcon;
+ dwc3@a800000 {
+ maximum-speed = "high-speed";
+ };
+};
+
+&ssphy {
+ compatible = "usb-nop-xceiv";
+};
+
+&qusb_phy0 {
+ compatible = "usb-nop-xceiv";
+};
+
+&uartblsp1dm1 {
+ status = "ok";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart_console_active>;
+};
+
+&sdhc_1 {
+ /* device core power supply */
+ vdd-supply = <&pm660l_l4>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <200 570000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm660_l8>;
+ qcom,vdd-io-always-on;
+ qcom,vdd-io-lpm-sup;
+ qcom,vdd-io-voltage-level = <1800000 1800000>;
+ qcom,vdd-io-current-level = <200 325000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
+ pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
+
+ status = "ok";
+};
+
+&sdhc_2 {
+ /* device core power supply */
+ vdd-supply = <&pm660l_l5>;
+ qcom,vdd-voltage-level = <2950000 2950000>;
+ qcom,vdd-current-level = <15000 800000>;
+
+ /* device communication power supply */
+ vdd-io-supply = <&pm660l_l2>;
+ qcom,vdd-io-voltage-level = <1800000 2950000>;
+ qcom,vdd-io-current-level = <200 22000>;
+
+ pinctrl-names = "active", "sleep";
+ pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>;
+ pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>;
+
+ #address-cells = <0>;
+ interrupt-parent = <&sdhc_2>;
+ interrupts = <0 1 2>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xffffffff>;
+ interrupt-map = <0 &intc 0 0 125 0
+ 1 &intc 0 0 221 0
+ 2 &tlmm 54 0>;
+ interrupt-names = "hc_irq", "pwr_irq", "status_irq";
+ cd-gpios = <&tlmm 54 0x1>;
+
+ status = "ok";
+};
+
+&pm660_charger {
+ status = "disabled";
+};
+
+&pm660_fg {
+ status = "disabled";
+};
+
+&pm660_pdphy {
+ status = "disabled";
+};
+
+&ufsphy1 {
+ vdda-phy-supply = <&pm660l_l1>;
+ vdda-pll-supply = <&pm660_l10>;
+ vddp-ref-clk-supply = <&pm660_l1>;
+ vdda-phy-max-microamp = <51400>;
+ vdda-pll-max-microamp = <14200>;
+ vddp-ref-clk-max-microamp = <100>;
+ vddp-ref-clk-always-on;
+ status = "ok";
+};
+
+&ufs1 {
+ vdd-hba-supply = <&gdsc_ufs>;
+ vdd-hba-fixed-regulator;
+ vcc-supply = <&pm660l_l4>;
+ vccq2-supply = <&pm660_l8>;
+ vcc-max-microamp = <500000>;
+ vccq2-max-microamp = <600000>;
+ status = "ok";
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-thermal.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-thermal.dtsi
new file mode 100755
index 0000000..813a8e6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-thermal.dtsi
@@ -0,0 +1,915 @@
+#include <dt-bindings/thermal/thermal.h>
+
+&clock_cpu {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ lmh_dcvs0: qcom,limits-dcvs@179ce800 {
+ compatible = "qcom,msm-hw-limits";
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,affinity = <0>;
+ reg = <0x179ce800 0x1000>,
+ <0x179c1400 0x1000>;
+ qcom,legacy-lmh-enable;
+ qcom,no-cooling-device-register;
+ };
+
+ lmh_dcvs1: qcom,limits-dcvs@0x179cc808 {
+ compatible = "qcom,msm-hw-limits";
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,affinity = <1>;
+ reg = <0x179cc800 0x1000>,
+ <0x179c3400 0x1000>;
+ qcom,legacy-lmh-enable;
+ qcom,no-cooling-device-register;
+ };
+
+ qcom,cpu-isolation {
+ compatible = "qcom,cpu-isolate";
+ cpu0_isolate: cpu0-isolate {
+ qcom,cpu = <&CPU0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1_isolate: cpu1-isolate {
+ qcom,cpu = <&CPU1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2_isolate: cpu2-isolate {
+ qcom,cpu = <&CPU2>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3_isolate: cpu3-isolate {
+ qcom,cpu = <&CPU3>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4_isolate: cpu4-isolate {
+ qcom,cpu = <&CPU4>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5_isolate: cpu5-isolate {
+ qcom,cpu = <&CPU5>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6_isolate: cpu6-isolate {
+ qcom,cpu = <&CPU6>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7_isolate: cpu7-isolate {
+ qcom,cpu = <&CPU7>;
+ #cooling-cells = <2>;
+ };
+ };
+};
+
+&soc {
+ qmi-tmd-devices {
+ compatible = "qcom,qmi-cooling-devices";
+
+ modem {
+ qcom,instance-id = <0x0>;
+
+ modem_pa: modem_pa {
+ qcom,qmi-dev-name = "pa";
+ #cooling-cells = <2>;
+ };
+
+ modem_proc: modem_proc {
+ qcom,qmi-dev-name = "modem";
+ #cooling-cells = <2>;
+ };
+
+ modem_current: modem_current {
+ qcom,qmi-dev-name = "modem_current";
+ #cooling-cells = <2>;
+ };
+
+ modem_skin: modem_skin {
+ qcom,qmi-dev-name = "modem_skin";
+ #cooling-cells = <2>;
+ };
+
+ modem_vdd: modem_vdd {
+ qcom,qmi-dev-name = "cpuv_restriction_cold";
+ #cooling-cells = <2>;
+ };
+ };
+
+ adsp {
+ qcom,instance-id = <0x1>;
+
+ adsp_vdd: adsp_vdd {
+ qcom,qmi-dev-name = "cpuv_restriction_cold";
+ #cooling-cells = <2>;
+ };
+ };
+
+ cdsp {
+ qcom,instance-id = <0x43>;
+
+ cdsp_vdd: cdsp_vdd {
+ qcom,qmi-dev-name = "cpuv_restriction_cold";
+ #cooling-cells = <2>;
+ };
+ };
+ };
+};
+
+&thermal_zones {
+ xo-therm-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm660_adc_tm ADC_XO_THERM_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ msm-therm-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm660_adc_tm ADC_AMUX_THM1_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ quiet-therm-adc {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&pm660_adc_tm ADC_AMUX_THM5_PU2>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+ ibat-high {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&bcl_sensor 0>;
+
+ trips {
+ pm660_ibat_high: ibat-high {
+ temperature = <4200>;
+ hysteresis = <200>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ ibat_map6 {
+ trip = <&pm660_ibat_high>;
+ cooling-device =
+ <&cpu6_isolate THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ ibat_map7 {
+ trip = <&pm660_ibat_high>;
+ cooling-device =
+ <&cpu7_isolate THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+
+ ibat-vhigh {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&bcl_sensor 1>;
+
+ trips {
+ pm660_ibat_vhigh: ibat-vhigh {
+ temperature = <4300>;
+ hysteresis = <100>;
+ type = "passive";
+ };
+ };
+ };
+
+ vbat_adc {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&bcl_sensor 2>;
+ tracks-low;
+
+ trips {
+ pm660_vbat_adc: vbat-adc {
+ temperature = <3500>;
+ hysteresis = <100>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ vbat_map4 {
+ trip = <&pm660_vbat_adc>;
+ cooling-device =
+ <&cpu4_isolate THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ vbat_map5 {
+ trip = <&pm660_vbat_adc>;
+ cooling-device =
+ <&cpu5_isolate THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ vbat_map6 {
+ trip = <&pm660_vbat_adc>;
+ cooling-device =
+ <&cpu6_isolate THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ vbat_map7 {
+ trip = <&pm660_vbat_adc>;
+ cooling-device =
+ <&cpu7_isolate THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+
+ vbat_low {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&bcl_sensor 3>;
+ tracks-low;
+
+ trips {
+ pm660_vbat_low: vbat-low {
+ temperature = <2800>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+
+ vbat_too_low {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&bcl_sensor 4>;
+ tracks-low;
+
+ trips {
+ pm660_vbat_too_low: vbat-too-low {
+ temperature = <2600>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+ };
+
+ mpm-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens 0>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens 1>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens 2>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens 3>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens 4>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens 5>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpu-1-3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens 6>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens 7>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpu-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens 8>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ video-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens 9>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ mdm-core-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens 10>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ camera-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens 11>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cpuss-3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens 12>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ cdsp-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&tsens 13>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+
+ reset-mon-cfg {
+ temperature = <115000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+ };
+
+ gpu-step {
+ polling-delay-passive = <10>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens 8>;
+ wake-capable-sensor;
+ trips {
+ gpu_trip: gpu-trip {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ gpu_cdev0 {
+ trip = <&gpu_trip>;
+ cooling-device =
+ <&msm_gpu THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ quiet-therm-step {
+ polling-delay-passive = <2000>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&pm660_adc_tm ADC_AMUX_THM5_PU2>;
+ wake-capable-sensor;
+ trips {
+ gold_trip: gold-trip {
+ temperature = <50000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+
+ silver_trip: silver-trip {
+ temperature = <53000>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ /* throttle from fmax to 1536000KHz */
+ skin_cpu0 {
+ trip = <&silver_trip>;
+ cooling-device = <&CPU0 THERMAL_NO_LIMIT 3>;
+ };
+
+ skin_cpu4 {
+ trip = <&gold_trip>;
+ /* throttle from fmax to 1747200KHz */
+ cooling-device = <&CPU4 THERMAL_NO_LIMIT 5>;
+ };
+ };
+ };
+
+ cpuss-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "step_wise";
+ thermal-sensors = <&tsens 1>;
+ wake-capable-sensor;
+ trips {
+ cpu_03_config: cpu_03-config {
+ temperature = <105000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_cdev {
+ trip = <&cpu_03_config>;
+ cooling-device = <&cpu0_isolate 1 1>;
+ };
+
+ cpu1_cdev {
+ trip = <&cpu_03_config>;
+ cooling-device = <&cpu1_isolate 1 1>;
+ };
+
+ cpu2_cdev {
+ trip = <&cpu_03_config>;
+ cooling-device = <&cpu2_isolate 1 1>;
+ };
+
+ cpu3_cdev {
+ trip = <&cpu_03_config>;
+ cooling-device = <&cpu3_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-0-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 3>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu4_0_config: cpu4-0-config {
+ temperature = <105000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu4_cdev {
+ trip = <&cpu4_0_config>;
+ cooling-device = <&cpu4_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-1-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 4>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu5_0_config: cpu5-0-config {
+ temperature = <105000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu5_cdev {
+ trip = <&cpu5_0_config>;
+ cooling-device = <&cpu5_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-2-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 5>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu6_0_config: cpu6-0-config {
+ temperature = <105000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu6_cdev {
+ trip = <&cpu6_0_config>;
+ cooling-device = <&cpu6_isolate 1 1>;
+ };
+ };
+ };
+
+ cpu-1-3-step {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tsens 6>;
+ thermal-governor = "step_wise";
+ wake-capable-sensor;
+ trips {
+ cpu7_1_config: cpu7-1-config {
+ temperature = <105000>;
+ hysteresis = <10000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu7_cdev {
+ trip = <&cpu7_1_config>;
+ cooling-device = <&cpu7_isolate 1 1>;
+ };
+ };
+ };
+
+ mpm-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens 0>;
+ wake-capable-sensor;
+ tracks-low;
+ trips {
+ mpm_trip: mpm-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_cdev {
+ trip = <&mpm_trip>;
+ cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-4)
+ (THERMAL_MAX_LIMIT-4)>;
+ };
+
+ cpu4_cdev {
+ trip = <&mpm_trip>;
+ cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+
+ gpu_vdd_cdev {
+ trip = <&mpm_trip>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-4)
+ (THERMAL_MAX_LIMIT-4)>;
+ };
+
+ cx_vdd_cdev {
+ trip = <&mpm_trip>;
+ cooling-device = <&cx_cdev 0 0>;
+ };
+
+ modem_vdd_cdev {
+ trip = <&mpm_trip>;
+ cooling-device = <&modem_vdd 0 0>;
+ };
+ };
+ };
+
+ camera-lowf {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_floor";
+ thermal-sensors = <&tsens 11>;
+ tracks-low;
+ trips {
+ camera_trip: camera-trip {
+ temperature = <5000>;
+ hysteresis = <5000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ cpu0_cdev {
+ trip = <&camera_trip>;
+ cooling-device = <&CPU0 (THERMAL_MAX_LIMIT-4)
+ (THERMAL_MAX_LIMIT-4)>;
+ };
+
+ cpu4_cdev {
+ trip = <&camera_trip>;
+ cooling-device = <&CPU4 (THERMAL_MAX_LIMIT-3)
+ (THERMAL_MAX_LIMIT-3)>;
+ };
+
+ gpu_vdd_cdev {
+ trip = <&camera_trip>;
+ cooling-device = <&msm_gpu (THERMAL_MAX_LIMIT-4)
+ (THERMAL_MAX_LIMIT-4)>;
+ };
+
+ cx_vdd_cdev {
+ trip = <&camera_trip>;
+ cooling-device = <&cx_cdev 0 0>;
+ };
+ };
+ };
+
+ soc {
+ polling-delay-passive = <100>;
+ polling-delay = <0>;
+ thermal-governor = "low_limits_cap";
+ thermal-sensors = <&bcl_sensor 5>;
+ tracks-low;
+
+ trips {
+ pm660_low_soc: low-soc {
+ temperature = <10>;
+ hysteresis = <0>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ soc_map4 {
+ trip = <&pm660_low_soc>;
+ cooling-device =
+ <&cpu4_isolate THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ soc_map5 {
+ trip = <&pm660_low_soc>;
+ cooling-device =
+ <&cpu5_isolate THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ soc_map6 {
+ trip = <&pm660_low_soc>;
+ cooling-device =
+ <&cpu6_isolate THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+
+ soc_map7 {
+ trip = <&pm660_low_soc>;
+ cooling-device =
+ <&cpu7_isolate THERMAL_MAX_LIMIT
+ THERMAL_MAX_LIMIT>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-usbc-audio-mtp.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-usbc-audio-mtp.dts
new file mode 100755
index 0000000..22d2315
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-usbc-audio-mtp.dts
@@ -0,0 +1,20 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-mtp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L, USBC
+ Audio MTP";
+ compatible = "qcom,sdm660-mtp", "qcom,sdm660", "qcom,mtp";
+ qcom,board-id = <8 2>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>,
+ <0x0001001b 0x0102001a 0x0 0x0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-moist-cfg = <0>, <0>, <3>;
+ qcom,msm-mbhc-usbc-audio-supported = <1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-usbc-audio-rcm.dts b/arch/arm64/boot/dts/vendor/qcom/sdm660-usbc-audio-rcm.dts
new file mode 100755
index 0000000..0536331
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-usbc-audio-rcm.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+#include "sdm660.dtsi"
+#include "sdm660-cdp.dtsi"
+#include "sdm660-external-codec.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660 PM660 + PM660L, USBC
+ Audio, RCM";
+ compatible = "qcom,sdm660-cdp", "qcom,sdm660", "qcom,cdp";
+ qcom,board-id = <21 3>;
+ qcom,pmic-id = <0x0001001b 0x0101011a 0x0 0x0>,
+ <0x0001001b 0x0201011a 0x0 0x0>;
+};
+
+&tavil_snd {
+ qcom,msm-mbhc-usbc-audio-supported = <1>;
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-vidc.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-vidc.dtsi
new file mode 100755
index 0000000..6bcf1fe
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-vidc.dtsi
@@ -0,0 +1,258 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+
+
+&soc {
+ msm_vidc: qcom,vidc@cc00000 {
+ compatible = "qcom,msm-vidc";
+ status = "ok";
+ reg = <0xcc00000 0x100000>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,hfi = "venus";
+ qcom,hfi-version = "3xx";
+ qcom,firmware-name = "venus";
+ qcom,sw-power-collapse;
+ qcom,max-secure-instances = <5>;
+ qcom,reg-presets =
+ <0x80010 0x001f001f>,
+ <0x80018 0x00000156>,
+ <0x8001c 0x00000156>;
+
+ qcom,max-hw-load = <1036800>; /* Full 4k @ 30 */
+ qcom,allowed-clock-rates =
+ /* TURBO NOM+ NOM
+ * SVS+ SVS SVS-
+ */
+ <518400000 441600000 404000000
+ 320000000 269330000 133330000>;
+
+ qcom,dcvs-tbl =
+ /* Dec UHD@30 All decoder - NOM to SVS+ */
+ <897600 783360 979200 0x3f00000c>,
+
+ /* Dec DCI@24 HEVC - NOM to SVS+ */
+ <816000 734400 829440 0x0c000000>,
+
+ /* Enc UHD@30 H264/HEVC - TURBO to NOM+ */
+ <897600 897600 979200 0x4000004>;
+ qcom,dcvs-limit =
+ <32400 30>, /* Encoder UHD */
+ <32400 24>; /* Decoder UHD */
+
+ /* Regulators */
+ smmu-vdd-supply = <&gdsc_bimc_smmu>;
+ venus-supply = <&gdsc_venus>;
+ venus-core0-supply = <&gdsc_venus_core0>;
+
+ /* Clocks */
+ clock-names = "gcc_mmss_sys_noc_axi_clk",
+ "mmssnoc_axi_clk", "mmss_throttle_video_axi_clk",
+ "mmss_mnoc_ahb_clk", "mmss_bimc_smmu_ahb_clk",
+ "mmss_bimc_smmu_axi_clk", "mmss_video_core_clk",
+ "mmss_video_ahb_clk", "mmss_video_axi_clk",
+ "mmss_video_core0_clk";
+ clocks = <&clock_gcc GCC_MMSS_SYS_NOC_AXI_CLK>,
+ <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_THROTTLE_VIDEO_AXI_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>,
+ <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>,
+ <&clock_mmss MMSS_VIDEO_CORE_CLK>,
+ <&clock_mmss MMSS_VIDEO_AHB_CLK>,
+ <&clock_mmss MMSS_VIDEO_AXI_CLK>,
+ <&clock_mmss MMSS_VIDEO_SUBCORE0_CLK>;
+ qcom,clock-configs = <0x0 0x0 0x0 0x0 0x0 0x0
+ 0x3 0x0 0x2 0x3>;
+
+ /* Buses */
+ bus_cnoc {
+ compatible = "qcom,msm-vidc,bus";
+ label = "cnoc";
+ qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <1 1>;
+ };
+
+ venus_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "venus-ddr";
+ qcom,bus-range-kbps = <1000 2365000>;
+ };
+
+ arm9_bus_ddr {
+ compatible = "qcom,msm-vidc,bus";
+ label = "venus-arm9-ddr";
+ qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
+ qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,mode = "performance";
+ qcom,bus-range-kbps = <1 1>;
+ };
+
+ qcom,clock-freq-tbl {
+ qcom,profile-enc {
+ qcom,codec-mask = <0x55555555>;
+ qcom,cycles-per-mb = <931>;
+ qcom,low-power-mode-factor = <33286>;
+ };
+ qcom,profile-dec {
+ qcom,codec-mask = <0xf3ffffff>;
+ qcom,cycles-per-mb = <355>;
+ };
+ qcom,profile-hevcdec {
+ qcom,codec-mask = <0x0c000000>;
+ qcom,cycles-per-mb = <400>;
+ };
+ };
+
+ venus-ddr-gov {
+ compatible = "qcom,msm-vidc,governor,table";
+ name = "venus-ddr-gov";
+ status = "ok";
+ qcom,bus-freq-table {
+ qcom,profile-enc {
+ qcom,codec-mask = <0x55555555>;
+ qcom,load-busfreq-tbl =
+ <979200 1044000>, /* UHD30E */
+ <864000 887000>, /* 720p240LPE */
+ <489600 666000>, /* 1080p60E */
+ <432000 578000>, /* 720p120E */
+ <244800 346000>, /* 1080p30E */
+ <216000 293000>, /* 720p60E */
+ <108000 151000>, /* 720p30E */
+ <0 0>;
+ };
+ qcom,profile-dec {
+ qcom,codec-mask = <0xffffffff>;
+ qcom,load-busfreq-tbl =
+ <979200 2365000>, /* UHD30D */
+ <864000 1978000>, /* 720p240D */
+ <489600 1133000>, /* 1080p60D */
+ <432000 994000>, /* 720p120D */
+ <244800 580000>, /* 1080p30D */
+ <216000 501000>, /* 720p60E */
+ <108000 255000>, /* 720p30D */
+ <0 0>;
+ };
+ qcom,profile-dec-ubwc {
+ qcom,codec-mask = <0xffffffff>;
+ qcom,ubwc-mode;
+ qcom,load-busfreq-tbl =
+ <979200 1892000>, /* UHD30D */
+ <864000 1554000>, /* 720p240D */
+ <489600 895000>, /* 1080p60D */
+ <432000 781000>, /* 720p120D */
+ <244800 460000>, /* 1080p30D */
+ <216000 301000>, /* 720p60E */
+ <108000 202000>, /* 720p30D */
+ <0 0>;
+ };
+ qcom,profile-dec-ubwc-10bit {
+ qcom,codec-mask = <0xffffffff>;
+ qcom,ubwc-10bit;
+ qcom,load-busfreq-tbl =
+ <979200 2446336>, /* UHD30D */
+ <864000 2108416>, /* 720p240D */
+ <489600 1207296>, /* 1080p60D */
+ <432000 1058816>, /* 720p120D */
+ <244800 616448>, /* 1080p30D */
+ <216000 534528>, /* 720p60D */
+ <108000 271360>, /* 720p30D */
+ <0 0>;
+ };
+ };
+ };
+
+
+ /* MMUs */
+ non_secure_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_ns";
+ iommus =
+ <&mmss_bimc_smmu 0x400>,
+ <&mmss_bimc_smmu 0x401>,
+ <&mmss_bimc_smmu 0x40a>,
+ <&mmss_bimc_smmu 0x407>,
+ <&mmss_bimc_smmu 0x40e>,
+ <&mmss_bimc_smmu 0x40f>,
+ <&mmss_bimc_smmu 0x408>,
+ <&mmss_bimc_smmu 0x409>,
+ <&mmss_bimc_smmu 0x40b>,
+ <&mmss_bimc_smmu 0x40c>,
+ <&mmss_bimc_smmu 0x40d>,
+ <&mmss_bimc_smmu 0x410>,
+ <&mmss_bimc_smmu 0x421>,
+ <&mmss_bimc_smmu 0x428>,
+ <&mmss_bimc_smmu 0x429>,
+ <&mmss_bimc_smmu 0x42b>,
+ <&mmss_bimc_smmu 0x42c>,
+ <&mmss_bimc_smmu 0x42d>,
+ <&mmss_bimc_smmu 0x411>,
+ <&mmss_bimc_smmu 0x431>;
+ qcom,iommu-dma-addr-pool = <0x79000000 0x60000000>;
+ buffer-types = <0xfff>;
+ virtual-addr-pool = <0x79000000 0x60000000>;
+ };
+
+ secure_bitstream_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_bitstream";
+ iommus = <&mmss_bimc_smmu 0x500>,
+ <&mmss_bimc_smmu 0x502>,
+ <&mmss_bimc_smmu 0x509>,
+ <&mmss_bimc_smmu 0x50a>,
+ <&mmss_bimc_smmu 0x50b>,
+ <&mmss_bimc_smmu 0x50e>,
+ <&mmss_bimc_smmu 0x526>,
+ <&mmss_bimc_smmu 0x529>,
+ <&mmss_bimc_smmu 0x52b>;
+ qcom,iommu-dma-addr-pool = <0x51000000 0x28000000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/
+ buffer-types = <0x241>;
+ virtual-addr-pool = <0x51000000 0x28000000>;
+ qcom,secure-context-bank;
+ };
+
+ venus_secure_pixel_cb: secure_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_pixel";
+ iommus = <&mmss_bimc_smmu 0x504>,
+ <&mmss_bimc_smmu 0x50c>,
+ <&mmss_bimc_smmu 0x510>,
+ <&mmss_bimc_smmu 0x52c>;
+ qcom,iommu-dma-addr-pool = <0x29000000 0x28000000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/
+ buffer-types = <0x106>;
+ virtual-addr-pool = <0x29000000 0x28000000>;
+ qcom,secure-context-bank;
+ };
+
+ venus_secure_non_pixel_cb: secure_non_pixel_cb {
+ compatible = "qcom,msm-vidc,context-bank";
+ label = "venus_sec_non_pixel";
+ iommus = <&mmss_bimc_smmu 0x505>,
+ <&mmss_bimc_smmu 0x507>,
+ <&mmss_bimc_smmu 0x508>,
+ <&mmss_bimc_smmu 0x50d>,
+ <&mmss_bimc_smmu 0x50f>,
+ <&mmss_bimc_smmu 0x525>,
+ <&mmss_bimc_smmu 0x528>,
+ <&mmss_bimc_smmu 0x52d>,
+ <&mmss_bimc_smmu 0x540>;
+ qcom,iommu-dma-addr-pool = <0x1000000 0x28000000>;
+ qcom,iommu-faults = "non-fatal";
+ qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/
+ buffer-types = <0x480>;
+ virtual-addr-pool = <0x1000000 0x28000000>;
+ qcom,secure-context-bank;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-wcd.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-wcd.dtsi
new file mode 100755
index 0000000..ce5025b
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-wcd.dtsi
@@ -0,0 +1,185 @@
+&slim_aud {
+ tasha_codec {
+ wsa_spkr_sd1: msm_cdc_pinctrll {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&spkr_1_sd_n_active>;
+ pinctrl-1 = <&spkr_1_sd_n_sleep>;
+ };
+
+ wsa_spkr_sd2: msm_cdc_pinctrlr {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&spkr_2_sd_n_active>;
+ pinctrl-1 = <&spkr_2_sd_n_sleep>;
+ };
+
+ tasha_hph_en0: msm_cdc_pinctrl_hph_en0 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&hph_en0_active>;
+ pinctrl-1 = <&hph_en0_sleep>;
+ };
+
+ tasha_hph_en1: msm_cdc_pinctrl_hph_en1 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&hph_en1_active>;
+ pinctrl-1 = <&hph_en1_sleep>;
+ };
+ };
+
+ tavil_codec {
+ wcd: wcd_pinctrl@5 {
+ compatible = "qcom,wcd-pinctrl";
+ qcom,num-gpios = <5>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ us_euro_sw_wcd_active: us_euro_sw_wcd_active {
+ mux {
+ pins = "gpio1";
+ };
+
+ config {
+ pins = "gpio1";
+ output-high;
+ };
+ };
+
+ us_euro_sw_wcd_sleep: us_euro_sw_wcd_sleep {
+ mux {
+ pins = "gpio1";
+ };
+
+ config {
+ pins = "gpio1";
+ output-low;
+ };
+ };
+
+ spkr_1_wcd_en_active: spkr_1_wcd_en_active {
+ mux {
+ pins = "gpio2";
+ };
+
+ config {
+ pins = "gpio2";
+ output-high;
+ };
+ };
+
+ spkr_1_wcd_en_sleep: spkr_1_wcd_en_sleep {
+ mux {
+ pins = "gpio2";
+ };
+
+ config {
+ pins = "gpio2";
+ input-enable;
+ };
+ };
+
+ spkr_2_wcd_en_active: spkr_2_sd_n_active {
+ mux {
+ pins = "gpio3";
+ };
+
+ config {
+ pins = "gpio3";
+ output-high;
+ };
+ };
+
+ spkr_2_wcd_en_sleep: spkr_2_sd_n_sleep {
+ mux {
+ pins = "gpio3";
+ };
+
+ config {
+ pins = "gpio3";
+ input-enable;
+ };
+ };
+
+ hph_en0_wcd_active: hph_en0_wcd_active {
+ mux {
+ pins = "gpio4";
+ };
+
+ config {
+ pins = "gpio4";
+ output-high;
+ };
+ };
+
+ hph_en0_wcd_sleep: hph_en0_wcd_sleep {
+ mux {
+ pins = "gpio4";
+ };
+
+ config {
+ pins = "gpio4";
+ output-low;
+ };
+ };
+
+ hph_en1_wcd_active: hph_en1_wcd_active {
+ mux {
+ pins = "gpio5";
+ };
+
+ config {
+ pins = "gpio5";
+ output-high;
+ };
+ };
+
+ hph_en1_wcd_sleep: hph_en1_wcd_sleep {
+ mux {
+ pins = "gpio5";
+ };
+
+ config {
+ pins = "gpio5";
+ output-low;
+ };
+ };
+ };
+
+ wsa_spkr_wcd_sd1: msm_cdc_pinctrll {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&spkr_1_wcd_en_active>;
+ pinctrl-1 = <&spkr_1_wcd_en_sleep>;
+ };
+
+ wsa_spkr_wcd_sd2: msm_cdc_pinctrlr {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&spkr_2_wcd_en_active>;
+ pinctrl-1 = <&spkr_2_wcd_en_sleep>;
+ };
+
+ tavil_us_euro_sw: msm_cdc_pinctrl_us_euro_sw {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&us_euro_sw_wcd_active>;
+ pinctrl-1 = <&us_euro_sw_wcd_sleep>;
+ };
+
+ tavil_hph_en0: msm_cdc_pinctrl_hph_en0 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&hph_en0_wcd_active>;
+ pinctrl-1 = <&hph_en0_wcd_sleep>;
+ };
+
+ tavil_hph_en1: msm_cdc_pinctrl_hph_en1 {
+ compatible = "qcom,msm-cdc-pinctrl";
+ pinctrl-names = "aud_active", "aud_sleep";
+ pinctrl-0 = <&hph_en1_wcd_active>;
+ pinctrl-1 = <&hph_en1_wcd_sleep>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660-wsa881x.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660-wsa881x.dtsi
new file mode 100755
index 0000000..9259ccc
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660-wsa881x.dtsi
@@ -0,0 +1,67 @@
+#include "sdm660-wcd.dtsi"
+
+&slim_aud {
+ tasha_codec {
+ swr_master {
+ compatible = "qcom,swr-wcd";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ wsa881x_211: wsa881x@20170211 {
+ compatible = "qcom,wsa881x";
+ reg = <0x0 0x20170211>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_sd1>;
+ };
+
+ wsa881x_212: wsa881x@20170212 {
+ compatible = "qcom,wsa881x";
+ reg = <0x0 0x20170212>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_sd2>;
+ };
+
+ wsa881x_213: wsa881x@21170213 {
+ compatible = "qcom,wsa881x";
+ reg = <0x0 0x21170213>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_sd1>;
+ };
+
+ wsa881x_214: wsa881x@21170214 {
+ compatible = "qcom,wsa881x";
+ reg = <0x0 0x21170214>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_sd2>;
+ };
+ };
+ };
+
+ tavil_codec {
+ swr_master {
+ compatible = "qcom,swr-wcd";
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ wsa881x_0211: wsa881x@20170211 {
+ compatible = "qcom,wsa881x";
+ reg = <0x0 0x20170211>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>;
+ };
+
+ wsa881x_0212: wsa881x@20170212 {
+ compatible = "qcom,wsa881x";
+ reg = <0x0 0x20170212>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>;
+ };
+
+ wsa881x_0213: wsa881x@21170213 {
+ compatible = "qcom,wsa881x";
+ reg = <0x0 0x21170213>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>;
+ };
+
+ wsa881x_0214: wsa881x@21170214 {
+ compatible = "qcom,wsa881x";
+ reg = <0x0 0x21170214>;
+ qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>;
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdm660.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdm660.dtsi
new file mode 100755
index 0000000..7bfc1f8
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdm660.dtsi
@@ -0,0 +1,2923 @@
+#include "skeleton64.dtsi"
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
+#include <dt-bindings/clock/qcom,gpu-sdm660.h>
+#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/clock/qcom,audio-ext-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
+#include <dt-bindings/msm/msm-bus-ids.h>
+#include <dt-bindings/clock/qcom,cpu-osm.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
+#define BW_OPP_ENTRY(mhz, w) opp-mhz {opp-hz = /bits/ 64 <MHZ_TO_MBPS(mhz, w)>;}
+#define DDR_TYPE_LPDDR3 5
+#define DDR_TYPE_LPDDR4X 7
+
+/ {
+ model = "Qualcomm Technologies, Inc. SDM 660";
+ compatible = "qcom,sdm660";
+ qcom,msm-id = <317 0x0>;
+ interrupt-parent = <&wakegic>;
+
+ aliases {
+ serial0 = &uartblsp1dm1;
+ sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
+ sdhc2 = &sdhc_2; /* SDC2 for SD card */
+ };
+
+ chosen {
+ stdout-path = "serial0";
+ bootargs = "rcupdate.rcu_expedited=1";
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_0>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ efficiency = <1024>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ /* A53 L2 dump not supported */
+ qcom,dump-size = <0x0>;
+ };
+
+ L1_I_0: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+
+ L1_D_0: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_0>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ #cooling-cells = <2>;
+ efficiency = <1024>;
+ next-level-cache = <&L2_0>;
+ L1_I_1: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+ L1_D_1: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_0>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ efficiency = <1024>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ L1_I_2: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+ L1_D_2: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ sched-energy-costs = <&CPU_COST_0>;
+ qcom,lmh-dcvs = <&lmh_dcvs0>;
+ efficiency = <1024>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ L1_I_3: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+ L1_D_3: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1638>;
+ sched-energy-costs = <&CPU_COST_1>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+ efficiency = <1638>;
+ next-level-cache = <&L2_1>;
+ #cooling-cells = <2>;
+ L2_1: l2-cache {
+ compatible = "arm,arch-cache";
+ cache-level = <2>;
+ };
+ L1_I_100: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+ L1_D_100: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1638>;
+ sched-energy-costs = <&CPU_COST_1>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+ #cooling-cells = <2>;
+ efficiency = <1638>;
+ next-level-cache = <&L2_1>;
+ L1_I_101: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+ L1_D_101: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1638>;
+ sched-energy-costs = <&CPU_COST_1>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+ #cooling-cells = <2>;
+ efficiency = <1638>;
+ next-level-cache = <&L2_1>;
+ L1_I_102: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+ L1_D_102: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1638>;
+ sched-energy-costs = <&CPU_COST_1>;
+ qcom,lmh-dcvs = <&lmh_dcvs1>;
+ #cooling-cells = <2>;
+ efficiency = <1638>;
+ next-level-cache = <&L2_1>;
+ L1_I_103: l1-icache {
+ compatible = "arm,arch-cache";
+ };
+ L1_D_103: l1-dcache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU4>;
+ };
+
+ core1 {
+ cpu = <&CPU5>;
+ };
+
+ core2 {
+ cpu = <&CPU6>;
+ };
+
+ core3 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+ };
+
+ energy_costs: energy-costs {
+ compatible = "sched-energy";
+
+ CPU_COST_0: core-cost0 {
+ busy-cost-data = <
+ 633600 41
+ 902400 70
+ 1113600 83
+ 1401600 146
+ 1536000 158
+ 1747200 228
+ 1843200 285
+ >;
+ };
+
+ CPU_COST_1: core-cost1 {
+ busy-cost-data = <
+ 1113600 307
+ 1401600 485
+ 1747200 857
+ 1804800 883
+ 1958400 1222
+ 2150400 1592
+ 2208000 1632
+ 2457600 2080
+ >;
+ };
+ };
+
+ clocks {
+ xo_board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <19200000>;
+ clock-output-names = "xo_board";
+ };
+
+ sleep_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32764>;
+ clock-output-names = "sleep_clk";
+ };
+ };
+
+ soc: soc { };
+
+ vendor: vendor {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+ };
+
+ firmware: firmware {
+ android {
+ compatible = "android,firmware";
+
+ vbmeta {
+ compatible = "android,vbmeta";
+ parts = "vbmeta,boot,system,vendor,dtbo";
+ };
+
+ fstab {
+ compatible = "android,fstab";
+ vendor {
+ compatible = "android,vendor";
+ dev = "/dev/block/platform/soc/c0c4000.sdhci/by-name/vendor";
+ type = "ext4";
+ mnt_flags = "ro,barrier=1,discard";
+ fsmgr_flags = "wait,slotselect,avb";
+ status = "ok";
+ };
+ };
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ wlan_msa_guard: wlan_msa_guard@85600000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x85600000 0x0 0x100000>;
+ };
+
+ wlan_msa_mem: wlan_msa_mem@85700000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x85700000 0x0 0x100000>;
+ };
+
+ smem_mem: smem-mem@86000000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86000000 0x0 0x200000>;
+ };
+
+ removed_regions: removed_regions@85800000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x85800000 0x0 0x800000>;
+ };
+
+ removed_regions1: removed_regions@86200000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x86200000 0x0 0x2d00000>;
+ };
+
+ modem_fw_mem: modem_fw_region@8ac00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x8ac00000 0x0 0x7e00000>;
+ };
+
+ adsp_fw_mem: adsp_fw_region@92a00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x92a00000 0x0 0x1e00000>;
+ };
+
+ pil_mba_mem: pil_mba_region@94800000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x94800000 0x0 0x200000>;
+ };
+
+ cdsp_fw_mem: cdsp_fw_region@94a00000 {
+ compatible = "removed-dma-pool";
+ no-map;
+ reg = <0x0 0x94a00000 0x0 0x600000>;
+ };
+
+ dump_mem: mem_dump_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1a0000>;
+ };
+
+ venus_fw_mem: venus_fw_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x80000000 0x0 0x20000000>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x800000>;
+ };
+
+ adsp_mem: adsp_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x800000>;
+ };
+
+ qseecom_mem: qseecom_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x1400000>;
+ };
+
+ secure_display_memory: secure_region {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
+ reusable;
+ alignment = <0x0 0x400000>;
+ size = <0x0 0x5c00000>;
+ };
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x00000000 0 0xffffffff>;
+ reusable;
+ alignment = <0 0x400000>;
+ size = <0 0x2c00000>;
+ linux,cma-default;
+ };
+
+ cont_splash_mem: splash_region@9d400000 {
+ reg = <0x0 0x9d400000 0x0 0x2300000>;
+ label = "cont_splash_mem";
+ };
+
+ dfps_data_mem: dfps_data_mem@0x9f700000 {
+ reg = <0x0 0x9f700000 0x0 0x00100000>;
+ label = "dfps_data_mem";
+ };
+ };
+
+
+ bluetooth: bt_wcn3990 {
+ compatible = "qca,wcn3990";
+ qca,bt-vdd-core-supply = <&pm660_l9>;
+ qca,bt-vdd-pa-supply = <&pm660_l6>;
+ qca,bt-vdd-ldo-supply = <&pm660_l19>;
+ qca,bt-chip-pwd-supply = <&pm660l_bob_pin1>;
+ clocks = <&clock_rpmcc RPM_SMD_RF_CLK1_PIN>;
+ clock-names = "rf_clk1";
+
+ qca,bt-vdd-core-voltage-level = <1800000 1900000>;
+ qca,bt-vdd-pa-voltage-level = <1304000 1370000>;
+ qca,bt-vdd-ldo-voltage-level = <3312000 3400000>;
+ qca,bt-chip-pwd-voltage-level = <3600000 3600000>;
+
+ qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
+ qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */
+ };
+};
+
+#include "sdm660-coresight.dtsi"
+&soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0xffffffff>;
+ compatible = "simple-bus";
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ reg = <0x17a00000 0x10000>, /* GICD */
+ <0x17b00000 0x100000>; /* GICR * 8 */
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ interrupts = <1 9 4>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 1 0xf08>,
+ <1 2 0xf08>,
+ <1 3 0xf08>,
+ <1 0 0xf08>;
+ clock-frequency = <19200000>;
+ };
+
+ dma_blsp1: qcom,sps-dma@0xc144000{ /* BLSP1 */
+ #dma-cells = <4>;
+ compatible = "qcom,sps-dma";
+ reg = <0xc144000 0x1F000>;
+ interrupts = <0 238 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,summing-threshold = <0x10>;
+ };
+
+ dma_blsp2: qcom,sps-dma@0xc184000{ /* BLSP2 */
+ #dma-cells = <4>;
+ compatible = "qcom,sps-dma";
+ reg = <0xc184000 0x1F000>;
+ interrupts = <0 239 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,summing-threshold = <0x10>;
+ };
+
+ restart@10ac000 {
+ compatible = "qcom,pshold";
+ reg = <0x10ac000 0x4>,
+ <0x1fd3000 0x4>;
+ reg-names = "pshold-base", "tcsr-boot-misc-detect";
+ };
+
+ spmi_bus: qcom,spmi@800f000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x800f000 0x1000>,
+ <0x8400000 0x1000000>,
+ <0x9400000 0x1000000>,
+ <0xa400000 0x220000>,
+ <0x800a000 0x3000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ qcom,reserved-chan = <511>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ status = "ok";
+ };
+
+ mem_dump {
+ compatible = "qcom,mem-dump";
+ memory-region = <&dump_mem>;
+
+ rpm_sw_dump {
+ qcom,dump-size = <0x28000>;
+ qcom,dump-id = <0xea>;
+ };
+
+ pmic_dump {
+ qcom,dump-size = <0x10000>;
+ qcom,dump-id = <0xe4>;
+ };
+
+ vsense_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xe9>;
+ };
+
+ tmc_etf_dump {
+ qcom,dump-size = <0x10000>;
+ qcom,dump-id = <0xf0>;
+ };
+
+ tmc_etr_reg_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x100>;
+ };
+
+ tmc_etf_reg_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0x101>;
+ };
+
+ misc_data_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xe8>;
+ };
+
+ dcc_reg_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xe6>;
+ };
+
+ dcc_sram_dump {
+ qcom,dump-size = <0x2000>;
+ qcom,dump-id = <0xe7>;
+ };
+
+ log_buf_dump {
+ qcom,dump-size = <0x10000>;
+ qcom,dump-id = <0x110>;
+ };
+
+ log_buf_first_idx_dump {
+ qcom,dump-size = <0x0>;
+ qcom,dump-id = <0x111>;
+ };
+
+ etm_reg0_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xa0>;
+ };
+
+ etm_reg1_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xa1>;
+ };
+
+ etm_reg2_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xa2>;
+ };
+
+ etm_reg3_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xa3>;
+ };
+
+ etm_reg4_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xa4>;
+ };
+
+ etm_reg5_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xa5>;
+ };
+
+ etm_reg6_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xa6>;
+ };
+
+ etm_reg7_dump {
+ qcom,dump-size = <0x1000>;
+ qcom,dump-id = <0xa7>;
+ };
+
+ c_scandump {
+ qcom,dump-size = <0x40000>;
+ qcom,dump-id = <0xeb>;
+ };
+
+ c0_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x0>;
+ };
+
+ c100_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x1>;
+ };
+
+ c200_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x2>;
+ };
+
+ c300_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x3>;
+ };
+
+ c400_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x4>;
+ };
+
+ c500_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x5>;
+ };
+
+ c600_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x6>;
+ };
+
+ c700_context {
+ qcom,dump-size = <0x800>;
+ qcom,dump-id = <0x7>;
+ };
+
+ l1_i_cache0 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x60>;
+ };
+
+ l1_i_cache1 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x61>;
+ };
+
+ l1_i_cache2 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x62>;
+ };
+
+ l1_i_cache3 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x63>;
+ };
+
+ l1_i_cache100 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x64>;
+ };
+
+ l1_i_cache101 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x65>;
+ };
+
+ l1_i_cache102 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x66>;
+ };
+
+ l1_i_cache103 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x67>;
+ };
+
+ l1_d_cache0 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x80>;
+ };
+
+ l1_d_cache1 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x81>;
+ };
+
+ l1_d_cache2 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x82>;
+ };
+
+ l1_d_cache3 {
+ qcom,dump-size = <0x9040>;
+ qcom,dump-id = <0x83>;
+ };
+
+ l1_d_cache100 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x84>;
+ };
+
+ l1_d_cache101 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x85>;
+ };
+
+ l1_d_cache102 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x86>;
+ };
+
+ l1_d_cache103 {
+ qcom,dump-size = <0x12000>;
+ qcom,dump-id = <0x87>;
+ };
+
+ l1_tlb_dump0 {
+ qcom,dump-size = <0x2800>;
+ qcom,dump-id = <0x20>;
+ };
+
+ l1_tlb_dump1 {
+ qcom,dump-size = <0x2800>;
+ qcom,dump-id = <0x21>;
+ };
+
+ l1_tlb_dump2 {
+ qcom,dump-size = <0x2800>;
+ qcom,dump-id = <0x22>;
+ };
+
+ l1_tlb_dump3 {
+ qcom,dump-size = <0x2800>;
+ qcom,dump-id = <0x23>;
+ };
+
+ l1_tlb_dump100 {
+ qcom,dump-size = <0x4800>;
+ qcom,dump-id = <0x24>;
+ };
+
+ l1_tlb_dump101 {
+ qcom,dump-size = <0x4800>;
+ qcom,dump-id = <0x25>;
+ };
+
+ l1_tlb_dump102 {
+ qcom,dump-size = <0x4800>;
+ qcom,dump-id = <0x26>;
+ };
+
+ l1_tlb_dump103 {
+ qcom,dump-size = <0x4800>;
+ qcom,dump-id = <0x27>;
+ };
+ };
+
+ wdog: qcom,wdt@17817000 {
+ compatible = "qcom,msm-watchdog";
+ reg = <0x17817000 0x1000>;
+ reg-names = "wdt-base";
+ interrupts = <0 3 IRQ_TYPE_EDGE_RISING>,
+ <0 4 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bark-time = <11000>;
+ qcom,pet-time = <10000>;
+ qcom,ipi-ping;
+ qcom,wakeup-enable;
+ };
+
+ qcom,sps {
+ compatible = "qcom,msm-sps-4k";
+ qcom,pipe-attr-ee;
+ };
+
+ wakegic: wake-gic {
+ compatible = "qcom,mpm-gic-sdm660", "qcom,mpm-gic";
+ interrupts-extended = <&wakegic GIC_SPI 171
+ IRQ_TYPE_EDGE_RISING>;
+ reg = <0x7781b8 0x1000>, /* MSM_RPM_MPM_BASE 4K */
+ <0x17911008 0x4>; /* MSM_APCS_GCC_BASE 4K */
+ reg-names = "vmpm", "ipc";
+ qcom,num-mpm-irqs = <96>;
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <3>;
+ };
+
+ wakegpio: wake-gpio {
+ compatible = "qcom,mpm-gpio";
+ interrupt-controller;
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <2>;
+ };
+
+ qcom,memshare {
+ compatible = "qcom,memshare";
+
+ qcom,client_1 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x200000>;
+ qcom,client-id = <0>;
+ qcom,allocate-boot-time;
+ label = "modem";
+ };
+
+ qcom,client_2 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x300000>;
+ qcom,client-id = <2>;
+ label = "modem";
+ };
+
+ mem_client_3_size: qcom,client_3 {
+ compatible = "qcom,memshare-peripheral";
+ qcom,peripheral-size = <0x0>;
+ qcom,client-id = <1>;
+ qcom,allocate-on-request;
+ label = "modem";
+ };
+ };
+
+ tsens: tsens@10ad000 {
+ compatible = "qcom,sdm660-tsens";
+ reg = <0x10ad000 0x8>,
+ <0x10ae000 0x1ff>;
+ reg-names = "tsens_srot_physical",
+ "tsens_tm_physical";
+ interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>,
+ <0 430 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tsens-upper-lower", "tsens-critical";
+ #thermal-sensor-cells = <1>;
+ qcom,client-id = <0 1 2 3 4 5 6 7 8 9 10 11 12 13>;
+ qcom,sensor-id = <0 10 11 4 5 6 7 8 13 2 3 12 9 1>;
+ qcom,sensors = <14>;
+ qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200
+ 3200 3200 3200 3200 3200 3200>;
+ };
+
+ thermal_zones: thermal-zones { };
+
+ uartblsp1dm1: serial@0c170000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xc170000 0x1000>;
+ interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&clock_gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ };
+
+ qcom,qbt1000 {
+ compatible = "qcom,qbt1000";
+ clock-names = "core", "iface";
+ clocks = <&clock_gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
+ <&clock_gcc GCC_BLSP1_AHB_CLK>;
+ clock-frequency = <15000000>;
+ qcom,ipc-gpio = <&tlmm 72 0>;
+ qcom,finger-detect-gpio = <&pm660_gpios 11 0>;
+ };
+
+ cx_ipeak_lm: cx_ipeak@1fe5040 {
+ compatible = "qcom,cx-ipeak-v1";
+ reg = <0x1fe5040 0x28>;
+ };
+
+ uartblsp2dm1: serial@0c1b0000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xc1b0000 0x1000>;
+ interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ clocks = <&clock_gcc GCC_BLSP2_UART2_APPS_CLK>,
+ <&clock_gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
+ };
+
+ slim_aud: slim@151c0000 {
+ cell-index = <1>;
+ compatible = "qcom,slim-ngd";
+ reg = <0x151c0000 0x2c000>,
+ <0x15184000 0x2a000>;
+ reg-names = "slimbus_physical", "slimbus_bam_physical";
+ interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>,
+ <0 164 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "slimbus_irq", "slimbus_bam_irq";
+ qcom,apps-ch-pipes = <0x7e0000>;
+ qcom,ea-pc = <0x260>;
+ qcom,arm-smmu;
+ iommus = <&anoc2_smmu 0x188b 0x0>,
+ <&anoc2_smmu 0x188c 0x0>,
+ <&anoc2_smmu 0x1892 0x0>,
+ <&anoc2_smmu 0x1893 0x0>,
+ <&anoc2_smmu 0x1894 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0xC0000000>;
+ qcom,use-64-bit-dma-mask;
+ qcom,iommu-dma = "bypass";
+ qcom,iommu-s1-bypass;
+ status = "disabled";
+ };
+
+ slim_qca: slim@15240000 {
+ cell-index = <3>;
+ compatible = "qcom,slim-ngd";
+ reg = <0x15240000 0x2c000>,
+ <0x15204000 0x20000>;
+ reg-names = "slimbus_physical", "slimbus_bam_physical";
+ interrupts = <0 291 IRQ_TYPE_LEVEL_HIGH>,
+ <0 292 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "slimbus_irq", "slimbus_bam_irq";
+ qcom,apps-ch-pipes = <0x1800>;
+
+ /* Slimbus Slave DT for WCN3990 */
+ btfmslim_codec: wcn3990 {
+ compatible = "qcom,btfmslim_slave";
+ elemental-addr = [00 01 20 02 17 02];
+ qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
+ qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
+ };
+ };
+
+ timer@17920000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x17920000 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@17921000 {
+ frame-number = <0>;
+ interrupts = <0 8 0x4>,
+ <0 7 0x4>;
+ reg = <0x17921000 0x1000>,
+ <0x17922000 0x1000>;
+ };
+
+ frame@17923000 {
+ frame-number = <1>;
+ interrupts = <0 9 0x4>;
+ reg = <0x17923000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17924000 {
+ frame-number = <2>;
+ interrupts = <0 10 0x4>;
+ reg = <0x17924000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17925000 {
+ frame-number = <3>;
+ interrupts = <0 11 0x4>;
+ reg = <0x17925000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17926000 {
+ frame-number = <4>;
+ interrupts = <0 12 0x4>;
+ reg = <0x17926000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17927000 {
+ frame-number = <5>;
+ interrupts = <0 13 0x4>;
+ reg = <0x17927000 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17928000 {
+ frame-number = <6>;
+ interrupts = <0 14 0x4>;
+ reg = <0x17928000 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ arm64-cpu-erp {
+ compatible = "arm,arm64-cpu-erp";
+ interrupts = <0 43 4>,
+ <0 44 4>,
+ <0 41 4>,
+ <0 42 4>;
+
+ interrupt-names = "pri-dbe-irq",
+ "sec-dbe-irq",
+ "pri-ext-irq",
+ "sec-ext-irq";
+
+ poll-delay-ms = <5000>;
+ };
+
+ clock_rpmcc: qcom,rpmcc {
+ compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
+ #clock-cells = <1>;
+ };
+
+ clock_gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sdm660", "syscon";
+ reg = <0x100000 0x94000>;
+ vdd_dig-supply = <&pm660l_s3_level>;
+ vdd_dig_ao-supply = <&pm660l_s3_level_ao>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ clock_mmss: clock-controller@c8c0000 {
+ compatible = "qcom,mmcc-sdm660", "syscon";
+ reg = <0xc8c0000 0x40000>;
+ vdd_mx_mmss-supply = <&pm660l_s5_level>;
+ vdd_dig_mmss-supply = <&pm660l_s3_level>;
+ vdda-supply = <&pm660_l10>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ clock_gpu: clock-controller@5065000 {
+ compatible = "qcom,gpu-sdm660", "syscon";
+ reg = <0x5065000 0x10000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ clock_gfx: gfx@5065000 {
+ compatible = "qcom,gpucc-sdm660", "syscon";
+ reg = <0x5065000 0x10000>;
+ vdd_dig_gfx-supply = <&pm660l_s3_level>;
+ vdd_mx_gfx-supply = <&pm660l_s5_level>;
+ vdd_gfx-supply = <&gfx_vreg_corner>;
+ qcom,gpucc_gfx3d_clk-opp-handle = <&msm_gpu>;
+ qcom,gfxfreq-corner =
+ < 0 0>,
+ < 160000000 1>, /* MinSVS */
+ < 266000000 2>, /* LowSVS */
+ < 370000000 3>, /* SVS */
+ < 465000000 4>, /* SVS_L1 */
+ < 588000000 5>, /* NOM */
+ < 647000000 6>, /* NOM_L1 */
+ < 700000000 7>, /* TURBO */
+ < 750000000 7>; /* TURBO */
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cpu_debug: syscon@1791101c {
+ compatible = "syscon";
+ reg = <0x1791101c 0x4>;
+ };
+
+ gpu_debug: syscon@05065120 {
+ compatible = "syscon";
+ reg = <0x05065120 0x4>;
+ };
+
+ mmss_debug: syscon@c8c0900 {
+ compatible = "syscon";
+ reg = <0xc8c0900 0x4>;
+ };
+
+ clock_debug: qcom,cc-debug@62000 {
+ compatible = "qcom,sdm660-debugcc";
+ qcom,gcc = <&clock_gcc>;
+ qcom,cpu = <&cpu_debug>;
+ qcom,mmss = <&clock_mmss>;
+ qcom,gpu = <&clock_gfx>;
+ clock-names = "xo_clk_src";
+ clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>;
+ #clock-cells = <1>;
+ };
+
+ generic_bw_opp_table: generic-bw-opp-table {
+ compatible = "operating-points-v2";
+ BW_OPP_ENTRY( 100, 4); /* 381 MB/s */
+ BW_OPP_ENTRY( 150, 4); /* 572 MB/s */
+ BW_OPP_ENTRY( 200, 4); /* 762 MB/s */
+ BW_OPP_ENTRY( 300, 4); /* 1144 MB/s */
+ BW_OPP_ENTRY( 412, 4); /* 1571 MB/s */
+ BW_OPP_ENTRY( 547, 4); /* 2086 MB/s */
+ BW_OPP_ENTRY( 681, 4); /* 2597 MB/s */
+ BW_OPP_ENTRY( 768, 4); /* 2929 MB/s */
+ BW_OPP_ENTRY(1017, 4); /* 3879 MB/s */
+ BW_OPP_ENTRY(1296, 4); /* 4943 MB/s */
+ BW_OPP_ENTRY(1353, 4); /* 5163 MB/s */
+ BW_OPP_ENTRY(1555, 4); /* 5931 MB/s */
+ BW_OPP_ENTRY(1804, 4); /* 6881 MB/s */
+ };
+
+ cpu_cpu_ddr_bw: qcom,cpu-cpu-ddr-bw {
+ compatible = "qcom,devbw";
+ governor = "performance";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&generic_bw_opp_table>;
+ };
+
+ cpu_cpu_ddr_bwmon: qcom,cpu-cpu-ddr-bwmon@01008000 {
+ compatible = "qcom,bimc-bwmon4";
+ reg = <0x01008000 0x300>, <0x01001000 0x200>;
+ reg-names = "base", "global_base";
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,mport = <0>;
+ qcom,hw-timer-hz = <19200000>;
+ qcom,target-dev = <&cpu_cpu_ddr_bw>;
+ qcom,count-unit = <0x10000>;
+ };
+
+ cpu0_cpu_ddr_latfloor: qcom,cpu0-cpu-ddr-latfloor {
+ compatible = "qcom,devbw";
+ governor = "powersave";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&generic_bw_opp_table>;
+ };
+
+ cpu4_cpu_ddr_latfloor: qcom,cpu4-cpu-ddr-latfloor {
+ compatible = "qcom,devbw";
+ governor = "powersave";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&generic_bw_opp_table>;
+ };
+
+ cpu0_cpu_ddr_lat: qcom,cpu0-cpu-ddr-lat {
+ compatible = "qcom,devbw";
+ governor = "powersave";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&generic_bw_opp_table>;
+ };
+
+ cpu4_cpu_ddr_lat: qcom,cpu4-cpu-ddr-lat {
+ compatible = "qcom,devbw";
+ governor = "powersave";
+ qcom,src-dst-ports =
+ <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_EBI_CH0>;
+ qcom,active-only;
+ operating-points-v2 = <&generic_bw_opp_table>;
+ };
+
+ cpu0_memlat_cpugrp: qcom,cpu0-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+
+ cpu0_cpu_ddr_latmon: qcom,cpu0-cpu-ddr-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,target-dev = <&cpu0_cpu_ddr_lat>;
+ qcom,cachemiss-ev = <0x17>;
+ qcom,core-dev-table =
+ < 902400 MHZ_TO_MBPS(200, 4) >,
+ < 1401600 MHZ_TO_MBPS(547, 4) >,
+ < 1881600 MHZ_TO_MBPS(1017, 4) >;
+ };
+
+ cpu0_computemon: qcom,cpu0-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
+ qcom,target-dev = <&cpu0_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 633600 MHZ_TO_MBPS(200, 4) >,
+ < 1401600 MHZ_TO_MBPS(412, 4) >,
+ < 1881600 MHZ_TO_MBPS(768, 4) >;
+ };
+ };
+
+ cpu4_memlat_cpugrp: qcom,cpu4-cpugrp {
+ compatible = "qcom,arm-memlat-cpugrp";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+
+ cpu4_cpu_ddr_latmon: qcom,cpu4-cpu-ddr-latmon {
+ compatible = "qcom,arm-memlat-mon";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+ qcom,target-dev = <&cpu4_cpu_ddr_lat>;
+ qcom,cachemiss-ev = <0x17>;
+ qcom,core-dev-table =
+ < 1113600 MHZ_TO_MBPS(200, 4) >,
+ < 1401600 MHZ_TO_MBPS(1017, 4) >,
+ < 2150400 MHZ_TO_MBPS(1555, 4) >,
+ < 2457600 MHZ_TO_MBPS(1804, 4) >;
+ };
+
+ cpu4_computemon: qcom,cpu4-computemon {
+ compatible = "qcom,arm-compute-mon";
+ qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
+ qcom,target-dev = <&cpu4_cpu_ddr_latfloor>;
+ qcom,core-dev-table =
+ < 1113600 MHZ_TO_MBPS(200, 4) >,
+ < 1401600 MHZ_TO_MBPS(547, 4) >,
+ < 1747200 MHZ_TO_MBPS(768, 4) >,
+ < 2150400 MHZ_TO_MBPS(1017, 4) >,
+ < 2457600 MHZ_TO_MBPS(1804, 4) >;
+ };
+ };
+
+
+ clock_cpu: qcom,clk-cpu-660@179c0000 {
+ compatible = "qcom,clk-cpu-osm";
+ reg = <0x179c0000 0x4000>, <0x17916000 0x1000>,
+ <0x17816000 0x1000>, <0x179d1000 0x1000>,
+ <0x00784130 0x8>, <0x00784130 0x8>;
+ reg-names = "osm", "pwrcl_pll", "perfcl_pll",
+ "apcs_common", "pwrcl_efuse",
+ "perfcl_efuse";
+
+ vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
+ vdd-perfcl-supply = <&apc1_perfcl_vreg>;
+
+ interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "pwrcl-irq", "perfcl-irq";
+
+ qcom,pwrcl-speedbin0-v0 =
+ < 300000000 0x0004000f 0x01200020 0x1 1 >,
+ < 633600000 0x05040021 0x03200020 0x1 2 >,
+ < 902400000 0x0404002f 0x04260026 0x1 3 >,
+ < 1113600000 0x0404003a 0x052e002e 0x2 4 >,
+ < 1401600000 0x04040049 0x073a003a 0x2 5 >,
+ < 1536000000 0x04040050 0x08400040 0x2 6 >,
+ < 1747200000 0x0404005b 0x09480048 0x2 7 >,
+ < 1843200000 0x04040060 0x094c004c 0x3 8 >;
+
+ qcom,pwrcl-speedbin1-v0 =
+ < 300000000 0x0004000f 0x01200020 0x1 1 >,
+ < 633600000 0x05040021 0x03200020 0x1 2 >,
+ < 902400000 0x0404002f 0x04260026 0x1 3 >,
+ < 1113600000 0x0404003a 0x052e002e 0x2 4 >,
+ < 1401600000 0x04040049 0x073a003a 0x2 5 >,
+ < 1536000000 0x04040050 0x08400040 0x2 6 >,
+ < 1747200000 0x0404005b 0x09480048 0x2 7 >,
+ < 1843200000 0x04040060 0x094c004c 0x3 8 >;
+
+ qcom,pwrcl-speedbin3-v0 =
+ < 300000000 0x0004000f 0x01200020 0x1 1 >,
+ < 633600000 0x05040021 0x03200020 0x1 2 >,
+ < 902400000 0x0404002f 0x04260026 0x1 3 >,
+ < 1113600000 0x0404003a 0x052e002e 0x2 4 >,
+ < 1401600000 0x04040049 0x073a003a 0x2 5 >,
+ < 1536000000 0x04040050 0x08400040 0x2 6 >,
+ < 1612800000 0x04040054 0x09430043 0x2 7 >;
+
+ qcom,pwrcl-speedbin4-v0 =
+ < 300000000 0x0004000f 0x01200020 0x1 1 >,
+ < 633600000 0x05040021 0x03200020 0x1 2 >,
+ < 902400000 0x0404002f 0x04260026 0x1 3 >,
+ < 1113600000 0x0404003a 0x052e002e 0x2 4 >,
+ < 1401600000 0x04040049 0x073a003a 0x2 5 >,
+ < 1536000000 0x04040050 0x08400040 0x2 6 >,
+ < 1747200000 0x0404005b 0x09480048 0x2 7 >,
+ < 1843200000 0x04040060 0x094c004c 0x3 8 >;
+
+ qcom,perfcl-speedbin0-v0 =
+ < 300000000 0x0004000f 0x01200020 0x1 1 >,
+ < 1113600000 0x0404003a 0x052e002e 0x1 2 >,
+ < 1401600000 0x04040049 0x073a003a 0x2 3 >,
+ < 1747200000 0x0404005b 0x09480048 0x2 4 >,
+ < 1958400000 0x04040066 0x0a510051 0x2 5 >,
+ < 2150400000 0x04040070 0x0b590059 0x2 6 >,
+ < 2457600000 0x04040080 0x0c660066 0x3 7 >;
+
+ qcom,perfcl-speedbin1-v0 =
+ < 300000000 0x0004000f 0x01200020 0x1 1 >,
+ < 1113600000 0x0404003a 0x052e002e 0x1 2 >,
+ < 1401600000 0x04040049 0x073a003a 0x2 3 >,
+ < 1747200000 0x0404005b 0x09480048 0x2 4 >,
+ < 1958400000 0x04040066 0x0a510051 0x2 5 >,
+ < 2150400000 0x04040070 0x0b590059 0x2 6 >,
+ < 2208000000 0x04040073 0x0b5c005c 0x3 7 >;
+
+ qcom,perfcl-speedbin3-v0 =
+ < 300000000 0x0004000f 0x01200020 0x1 1 >,
+ < 1113600000 0x0404003a 0x052e002e 0x1 2 >,
+ < 1401600000 0x04040049 0x073a003a 0x2 3 >,
+ < 1747200000 0x0404005b 0x09480048 0x2 4 >,
+ < 1804800000 0x0404005e 0x094b004b 0x2 5 >;
+
+ qcom,perfcl-speedbin4-v0 =
+ < 300000000 0x0004000f 0x01200020 0x1 1 >,
+ < 1113600000 0x0404003a 0x052e002e 0x1 2 >,
+ < 1401600000 0x04040049 0x073a003a 0x2 3 >,
+ < 1747200000 0x0404005b 0x09480048 0x2 4 >,
+ < 1958400000 0x04040066 0x0a510051 0x2 5 >;
+
+ qcom,up-timer = <1000 1000>;
+ qcom,down-timer = <1000 1000>;
+ qcom,set-ret-inactive;
+ qcom,enable-llm-freq-vote;
+ qcom,llm-freq-up-timer = <327675 327675>;
+ qcom,llm-freq-down-timer = <327675 327675>;
+ qcom,enable-llm-volt-vote;
+ qcom,llm-volt-up-timer = <327675 327675>;
+ qcom,llm-volt-down-timer = <327675 327675>;
+ qcom,cc-reads = <10>;
+ qcom,cc-delay = <5>;
+ qcom,cc-factor = <100>;
+ qcom,osm-clk-rate = <200000000>;
+ qcom,xo-clk-rate = <19200000>;
+
+ qcom,l-val-base = <0x17916004 0x17816004>;
+ qcom,apcs-itm-present = <0x179d143c 0x179d143c>;
+ qcom,apcs-pll-user-ctl = <0x1791600c 0x1781600c>;
+ qcom,apcs-cfg-rcgr = <0x17911054 0x17811054>;
+ qcom,apcs-cmd-rcgr = <0x17911050 0x17811050>;
+ qcom,apm-mode-ctl = <0x179d0004 0x179d0010>;
+ qcom,apm-ctrl-status = <0x179d000c 0x179d0018>;
+
+ qcom,apm-threshold-voltage = <872000>;
+ qcom,boost-fsm-en;
+ qcom,safe-fsm-en;
+ qcom,ps-fsm-en;
+ qcom,droop-fsm-en;
+ qcom,wfx-fsm-en;
+ qcom,pc-fsm-en;
+
+ clock-names = "aux_clk", "xo_a";
+ clocks = <&clock_gcc HMSS_GPLL0_CLK_SRC>,
+ <&clock_rpmcc RPM_SMD_XO_A_CLK_SRC>;
+
+ #clock-cells = <1>;
+ };
+
+ msm_cpufreq: qcom,msm-cpufreq {
+ compatible = "qcom,msm-cpufreq";
+ clock-names = "cpu0_clk", "cpu4_clk";
+ clocks = <&clock_cpu PWRCL_CLK>,
+ <&clock_cpu PERFCL_CLK>;
+
+ qcom,governor-per-policy;
+
+ qcom,cpufreq-table-0 =
+ < 633600 >,
+ < 902400 >,
+ < 1113600 >,
+ < 1401600 >,
+ < 1536000 >,
+ < 1612800 >,
+ < 1747200 >,
+ < 1843200 >;
+
+ qcom,cpufreq-table-4 =
+ < 1113600 >,
+ < 1401600 >,
+ < 1747200 >,
+ < 1804800 >,
+ < 1958400 >,
+ < 2150400 >,
+ < 2208000 >,
+ < 2457600 >;
+ };
+
+ sdhc_1: sdhci@c0c4000 {
+ compatible = "qcom,sdhci-msm-v5", "qcom,sdhci-msm-cqe";
+ reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>,
+ <0xc0c8000 0x8000>;
+ reg-names = "hc_mem", "cqhci_mem", "cqhci_ice";
+
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <8>;
+ qcom,large-address-bus;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000 192000000
+ 384000000>;
+
+ qcom,nonremovable;
+ qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
+ qcom,devfreq,freq-table = <50000000 200000000>;
+
+ qcom,msm-bus,name = "sdhc1";
+ qcom,msm-bus,num-cases = <9>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <78 512 0 0>, <1 606 0 0>,
+ /* 400 KB/s*/
+ <78 512 1046 1600>,
+ <1 606 1600 1600>,
+ /* 20 MB/s */
+ <78 512 52286 80000>,
+ <1 606 80000 80000>,
+ /* 25 MB/s */
+ <78 512 65360 100000>,
+ <1 606 100000 100000>,
+ /* 50 MB/s */
+ <78 512 130718 200000>,
+ <1 606 133320 133320>,
+ /* 100 MB/s */
+ <78 512 130718 200000>,
+ <1 606 150000 150000>,
+ /* 200 MB/s */
+ <78 512 261438 400000>,
+ <1 606 300000 300000>,
+ /* 400 MB/s */
+ <78 512 261438 400000>,
+ <1 606 300000 300000>,
+ /* Max. bandwidth */
+ <78 512 1338562 4096000>,
+ <1 606 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100000000 200000000 400000000 4294967295>;
+
+ clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,
+ <&clock_gcc GCC_SDCC1_APPS_CLK>,
+ <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>;
+ clock-names = "iface_clk", "core_clk", "ice_core_clk";
+ qcom,ice-clk-rates = <300000000 75000000>;
+
+ status = "disabled";
+ };
+
+ sdhc_2: sdhci@c084000 {
+ compatible = "qcom,sdhci-msm-v5";
+ reg = <0xc084000 0x1000>;
+ reg-names = "hc_mem";
+
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ qcom,bus-width = <4>;
+ qcom,large-address-bus;
+
+ qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
+ 200000000>;
+ qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
+
+ qcom,msm-bus,name = "sdhc2";
+ qcom,msm-bus,num-cases = <8>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <81 512 0 0>, <1 608 0 0>,
+ /* 400 KB/s*/
+ <81 512 1046 1600>,
+ <1 608 1600 1600>,
+ /* 20 MB/s */
+ <81 512 52286 80000>,
+ <1 608 80000 80000>,
+ /* 25 MB/s */
+ <81 512 65360 100000>,
+ <1 608 100000 100000>,
+ /* 50 MB/s */
+ <81 512 130718 200000>,
+ <1 608 133320 133320>,
+ /* 100 MB/s */
+ <81 512 261438 200000>,
+ <1 608 150000 150000>,
+ /* 200 MB/s */
+ <81 512 261438 400000>,
+ <1 608 300000 300000>,
+ /* Max. bandwidth */
+ <81 512 1338562 4096000>,
+ <1 608 1338562 4096000>;
+ qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
+ 100000000 200000000 4294967295>;
+
+ qcom,devfreq,freq-table = <50000000 200000000>;
+ clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
+ <&clock_gcc GCC_SDCC2_APPS_CLK>;
+ clock-names = "iface_clk", "core_clk";
+
+ status = "disabled";
+ };
+
+ ipa_hw: qcom,ipa@14780000 {
+ compatible = "qcom,ipa";
+ reg = <0x14780000 0x4effc>, <0x14784000 0x26934>;
+ reg-names = "ipa-base", "bam-base";
+ interrupts = <0 333 IRQ_TYPE_LEVEL_HIGH>,
+ <0 432 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ipa-irq", "bam-irq";
+ qcom,ipa-hw-ver = <6>; /* IPA core version = IPAv2.6L */
+ qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */
+ qcom,wan-rx-ring-size = <192>; /* IPA WAN-rx-ring-size*/
+ qcom,lan-rx-ring-size = <192>; /* IPA LAN-rx-ring-size*/
+ clocks = <&clock_rpmcc RPM_SMD_IPA_CLK>,
+ <&clock_rpmcc AGGR2_NOC_SMMU_CLK>;
+ clock-names = "core_clk", "smmu_clk";
+ qcom,arm-smmu;
+ qcom,smmu-disable-htw;
+ qcom,smmu-s1-bypass;
+ qcom,ee = <0>;
+ qcom,use-ipa-tethering-bridge;
+ qcom,modem-cfg-emb-pipe-flt;
+ qcom,ipa-wdi2;
+ qcom,use-dma-zone;
+ qcom,msm-bus,name = "ipa";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ /* No vote */
+ <90 512 0 0>,
+ <1 676 0 0>,
+ /* SVS */
+ <90 512 80000 640000>,
+ <1 676 80000 80000>,
+ /* NOMINAL */
+ <90 512 206000 960000>,
+ <1 676 206000 160000>,
+ /* TURBO */
+ <90 512 206000 960000>,
+ <1 676 206000 160000>;
+ qcom,bus-vector-names = "MIN", "SVS", "PERF", "TURBO";
+ qcom,rx-polling-sleep-ms = <1>; /* Polling sleep interval */
+ qcom,ipa-polling-iteration = <40>; /* Polling Iteration */
+ ipa_smmu_ap: ipa_smmu_ap {
+ compatible = "qcom,ipa-smmu-ap-cb";
+ iommus = <&anoc2_smmu 0x19C0 0x0>;
+ qcom,iommu-dma-addr-pool = <0x10000000 0x40000000>;
+ qcom,iommu-dma = "bypass";
+ };
+
+ ipa_smmu_wlan: ipa_smmu_wlan {
+ status = "disabled";
+ compatible = "qcom,ipa-smmu-wlan-cb";
+ iommus = <&anoc2_smmu 0x19C1 0x0>;
+ qcom,iommu-dma = "bypass";
+ };
+
+ ipa_smmu_uc: ipa_smmu_uc {
+ compatible = "qcom,ipa-smmu-uc-cb";
+ iommus = <&anoc2_smmu 0x19C2 0x0>;
+ qcom,iommu-dma-addr-pool = <0x40000000 0x20000000>;
+ qcom,iommu-dma = "bypass";
+ };
+ };
+
+ qcom,rmtfs_sharedmem@0 {
+ compatible = "qcom,sharedmem-uio";
+ reg = <0x0 0x200000>;
+ reg-names = "rmtfs";
+ qcom,client-id = <0x00000001>;
+ qcom,guard-memory;
+ };
+
+ qcom,rmnet-ipa {
+ compatible = "qcom,rmnet-ipa";
+ qcom,rmnet-ipa-ssr;
+ qcom,ipa-platform-type-msm;
+ qcom,ipa-advertise-sg-support;
+ qcom,ipa-napi-enable;
+ };
+
+ qcom,ipc-spinlock@1f40000 {
+ compatible = "qcom,ipc-spinlock-sfpb";
+ reg = <0x1f40000 0x8000>;
+ qcom,num-locks = <8>;
+ };
+
+ qcom,msm-cdsp-loader {
+ compatible = "qcom,cdsp-loader";
+ qcom,proc-img-to-load = "cdsp";
+ };
+
+ qcom,msm-adsprpc-mem {
+ compatible = "qcom,msm-adsprpc-mem-region";
+ memory-region = <&adsp_mem>;
+ restrict-access;
+ };
+
+ qcom,msm_fastrpc {
+ compatible = "qcom,msm-fastrpc-compute";
+ qcom,adsp-remoteheap-vmid = <33>;
+ qcom,rpc-latency-us = <611>;
+ qcom,fastrpc-adsp-audio-pdr;
+ qcom,fastrpc-adsp-sensors-pdr;
+
+ qcom,msm_fastrpc_compute_cb1 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&lpass_q6_smmu 3>;
+ dma-coherent;
+ };
+ qcom,msm_fastrpc_compute_cb2 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&lpass_q6_smmu 7>;
+ dma-coherent;
+ };
+ qcom,msm_fastrpc_compute_cb3 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&lpass_q6_smmu 8>;
+ dma-coherent;
+ };
+ qcom,msm_fastrpc_compute_cb4 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "adsprpc-smd";
+ iommus = <&lpass_q6_smmu 9>;
+ dma-coherent;
+ };
+ qcom,msm_fastrpc_compute_cb5 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&turing_q6_smmu 3>;
+ dma-coherent;
+ };
+ qcom,msm_fastrpc_compute_cb6 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&turing_q6_smmu 4>;
+ dma-coherent;
+ };
+ qcom,msm_fastrpc_compute_cb7 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&turing_q6_smmu 5>;
+ dma-coherent;
+ };
+
+ qcom,msm_fastrpc_compute_cb8 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&turing_q6_smmu 6>;
+ dma-coherent;
+ };
+ qcom,msm_fastrpc_compute_cb9 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&turing_q6_smmu 7>;
+ dma-coherent;
+ };
+ qcom,msm_fastrpc_compute_cb10 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&turing_q6_smmu 8>;
+ dma-coherent;
+ };
+ qcom,msm_fastrpc_compute_cb11 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&turing_q6_smmu 9>;
+ dma-coherent;
+ };
+ qcom,msm_fastrpc_compute_cb12 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&turing_q6_smmu 10>;
+ dma-coherent;
+ };
+ qcom,msm_fastrpc_compute_cb13 {
+ compatible = "qcom,msm-fastrpc-compute-cb";
+ label = "cdsprpc-smd";
+ iommus = <&turing_q6_smmu 11>;
+ dma-coherent;
+ };
+ };
+
+
+ dcc: dcc@10b3000 {
+ compatible = "qcom,dcc";
+ reg = <0x10b3000 0x1000>,
+ <0x10b4000 0x2000>;
+ reg-names = "dcc-base", "dcc-ram-base";
+
+ clocks = <&clock_gcc GCC_DCC_AHB_CLK>;
+ clock-names = "dcc_clk";
+ };
+
+ tcsr_mutex_block: syscon@1f40000 {
+ compatible = "syscon";
+ reg = <0x1f40000 0x20000>;
+ };
+
+ tcsr_mutex: hwlock {
+ compatible = "qcom,tcsr-mutex";
+ syscon = <&tcsr_mutex_block 0 0x1000>;
+ #hwlock-cells = <1>;
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ apcs_glb: mailbox@17911000 {
+ compatible = "qcom,sdm660-apcs-hmss-global";
+ reg = <0x17911000 0x1000>;
+ #mbox-cells = <1>;
+ };
+
+ rpm-glink {
+ compatible = "qcom,glink-rpm";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ qcom,rpm-msg-ram = <&rpm_msg_ram>;
+ mboxes = <&apcs_glb 0>;
+
+ qcom,rpm_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_adsp>,
+ <&glink_cdsp>;
+ };
+
+ };
+
+ qcom,glink {
+ compatible = "qcom,glink";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ glink_modem: modem {
+ qcom,remote-pid = <1>;
+ transport = "smem";
+ mboxes = <&apcs_glb 15>;
+ mbox-names = "mpss_smem";
+ interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>;
+
+ label = "modem";
+ qcom,glink-label = "mpss";
+
+ qcom,modem_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,low-latency;
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,modem_ds {
+ qcom,glink-channels = "DS";
+ qcom,intents = <0x4000 0x2>;
+ };
+
+ qcom,modem_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_adsp>,
+ <&glink_cdsp>;
+ };
+ };
+
+ glink_adsp: adsp {
+ qcom,remote-pid = <2>;
+ transport = "smem";
+ mboxes = <&apcs_glb 9>;
+ mbox-names = "adsp_smem";
+ interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
+
+ label = "adsp";
+ qcom,glink-label = "lpass";
+ cpu-affinity = <1 2>;
+
+ qcom,adsp_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,apr_tal_rpmsg {
+ qcom,glink-channels = "apr_audio_svc";
+ qcom,intents = <0x200 20>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,adsp_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_cdsp>;
+ };
+ };
+
+
+ glink_cdsp: cdsp {
+ qcom,remote-pid = <5>;
+ transport = "smem";
+ mboxes = <&apcs_glb 29>;
+ mbox-names = "cdsp_smem";
+ interrupts = <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>;
+
+ label = "cdsp";
+ qcom,glink-label = "cdsp";
+
+ qcom,cdsp_qrtr {
+ qcom,glink-channels = "IPCRTR";
+ qcom,intents = <0x800 5
+ 0x2000 3
+ 0x4400 2>;
+ };
+
+ qcom,msm_fastrpc_rpmsg {
+ compatible = "qcom,msm-fastrpc-rpmsg";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+ qcom,intents = <0x64 64>;
+ };
+
+ qcom,msm_cdsprm_rpmsg {
+ compatible = "qcom,msm-cdsprm-rpmsg";
+ qcom,glink-channels = "cdsprmglink-apps-dsp";
+ qcom,intents = <0x20 12>;
+
+ msm_cdsp_rm: qcom,msm_cdsp_rm {
+ compatible = "qcom,msm-cdsp-rm";
+ qcom,qos-latency-us = <44>;
+ qcom,qos-maxhold-ms = <20>;
+ #cooling-cells = <2>;
+ };
+
+ msm_hvx_rm: qcom,msm_hvx_rm {
+ compatible = "qcom,msm-hvx-rm";
+ #cooling-cells = <2>;
+ };
+ };
+
+ qcom,cdsp_glink_ssr {
+ qcom,glink-channels = "glink_ssr";
+ qcom,notify-edges = <&glink_modem>,
+ <&glink_adsp>;
+ };
+ };
+
+ glink_spi_xprt_wdsp: wdsp {
+ transport = "spi";
+ tx-descriptors = <0x12000 0x12004>;
+ rx-descriptors = <0x1200c 0x12010>;
+
+ label = "wdsp";
+ qcom,glink-label = "wdsp";
+
+ qcom,wdsp_ctrl {
+ qcom,glink-channels = "g_glink_ctrl";
+ qcom,intents = <0x400 1>;
+ };
+
+ qcom,wdsp_ild {
+ qcom,glink-channels =
+ "g_glink_persistent_data_ild";
+ };
+
+ qcom,wdsp_nild {
+ qcom,glink-channels =
+ "g_glink_persistent_data_nild";
+ };
+
+ qcom,wdsp_data {
+ qcom,glink-channels = "g_glink_audio_data";
+ qcom,intents = <0x1000 2>;
+ };
+
+ qcom,diag_data {
+ qcom,glink-channels = "DIAG_DATA";
+ qcom,intents = <0x4000 2>;
+ };
+
+ qcom,diag_ctrl {
+ qcom,glink-channels = "DIAG_CTRL";
+ qcom,intents = <0x4000 1>;
+ };
+
+ qcom,diag_cmd {
+ qcom,glink-channels = "DIAG_CMD";
+ qcom,intents = <0x4000 1 >;
+ };
+ };
+ };
+
+ qcom,glink_pkt {
+ compatible = "qcom,glinkpkt";
+
+ qcom,glinkpkt-at-mdm0 {
+ qcom,glinkpkt-transport = "smem";
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DS";
+ qcom,glinkpkt-dev-name = "at_mdm0";
+ };
+
+ qcom,glinkpkt-loopback_cntl {
+ qcom,glinkpkt-transport = "lloop";
+ qcom,glinkpkt-edge = "local";
+ qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
+ qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
+ };
+
+ qcom,glinkpkt-loopback_data {
+ qcom,glinkpkt-transport = "lloop";
+ qcom,glinkpkt-edge = "local";
+ qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
+ qcom,glinkpkt-dev-name = "glink_pkt_loopback";
+ };
+
+ qcom,glinkpkt-apr-apps2 {
+ qcom,glinkpkt-transport = "smem";
+ qcom,glinkpkt-edge = "adsp";
+ qcom,glinkpkt-ch-name = "apr_apps2";
+ qcom,glinkpkt-dev-name = "apr_apps2";
+ };
+
+ qcom,glinkpkt-data40-cntl {
+ qcom,glinkpkt-transport = "smem";
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA40_CNTL";
+ qcom,glinkpkt-dev-name = "smdcntl8";
+ };
+
+ qcom,glinkpkt-data1 {
+ qcom,glinkpkt-transport = "smem";
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA1";
+ qcom,glinkpkt-dev-name = "smd7";
+ };
+
+ qcom,glinkpkt-data4 {
+ qcom,glinkpkt-transport = "smem";
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA4";
+ qcom,glinkpkt-dev-name = "smd8";
+ };
+
+ qcom,glinkpkt-data11 {
+ qcom,glinkpkt-transport = "smem";
+ qcom,glinkpkt-edge = "mpss";
+ qcom,glinkpkt-ch-name = "DATA11";
+ qcom,glinkpkt-dev-name = "smd11";
+ };
+ };
+
+ qcom,smp2p_sleepstate {
+ compatible = "qcom,smp2p-sleepstate";
+ qcom,smem-states = <&sleepstate_smp2p_out 0>;
+ interrupt-parent = <&sleepstate_smp2p_in>;
+ interrupts = <0 0>;
+ interrupt-names = "smp2p-sleepstate-in";
+ };
+
+ qcom,smp2p-modem {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+ interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 14>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
+ qcom,entry-name = "ipa";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ /* ipa - inbound entry from mss */
+ smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
+ qcom,entry-name = "ipa";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
+ qcom,entry-name = "wlan";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p-adsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <443>, <429>;
+ interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 10>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ adsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ adsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
+ qcom,entry-name = "rdbg";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
+ qcom,entry-name = "rdbg";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ sleepstate_smp2p_out: sleepstate-out {
+ qcom,entry-name = "sleepstate";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ sleepstate_smp2p_in: qcom,sleepstate-in {
+ qcom,entry-name = "sleepstate_see";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ qcom,smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+ interrupts = <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&apcs_glb 30>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
+ qcom,entry-name = "rdbg";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
+ qcom,entry-name = "rdbg";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ rpm_bus: qcom,rpm-smd {
+ compatible = "qcom,rpm-smd";
+ rpm-channel-name = "rpm_requests";
+ interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+ rpm-channel-type = <15>; /* SMD_APPS_RPM */
+ };
+
+ qcom,venus@cce0000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0xcce0000 0x4000>;
+
+ vdd-supply = <&gdsc_venus>;
+ qcom,proxy-reg-names = "vdd";
+
+ clocks = <&clock_mmss MMSS_VIDEO_CORE_CLK>,
+ <&clock_mmss MMSS_MNOC_AHB_CLK>,
+ <&clock_mmss MMSS_VIDEO_AHB_CLK>,
+ <&clock_rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
+ <&clock_mmss MMSS_VIDEO_AXI_CLK>;
+ clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk",
+ "noc_axi_clk", "bus_clk";
+ qcom,proxy-clock-names = "core_clk", "mnoc_ahb_clk",
+ "iface_clk", "noc_axi_clk", "bus_clk";
+
+ qcom,msm-bus,name = "pil-venus";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <63 512 0 0>,
+ <63 512 0 304000>;
+
+ qcom,pas-id = <9>;
+ qcom,mas-crypto = <&mas_crypto_c0>;
+ qcom,proxy-timeout-ms = <100>;
+ qcom,firmware-name = "venus";
+ memory-region = <&venus_fw_mem>;
+ status = "ok";
+ };
+
+ qcom,icnss@18800000 {
+ compatible = "qcom,icnss";
+ reg = <0x18800000 0x800000>,
+ <0xb0000000 0x10000>;
+ reg-names = "membase", "smmu_iova_ipa";
+ iommus = <&anoc2_smmu 0x1a00>,
+ <&anoc2_smmu 0x1a01>;
+ clocks = <&clock_rpmcc RPM_SMD_RF_CLK1_PIN>;
+ clock-names = "cxo_ref_clk_pin";
+ interrupts = <0 413 IRQ_TYPE_LEVEL_HIGH>, /* CE0 */
+ <0 414 IRQ_TYPE_LEVEL_HIGH>, /* CE1 */
+ <0 415 IRQ_TYPE_LEVEL_HIGH>, /* CE2 */
+ <0 416 IRQ_TYPE_LEVEL_HIGH>, /* CE3 */
+ <0 417 IRQ_TYPE_LEVEL_HIGH>, /* CE4 */
+ <0 418 IRQ_TYPE_LEVEL_HIGH>, /* CE5 */
+ <0 420 IRQ_TYPE_LEVEL_HIGH>, /* CE6 */
+ <0 421 IRQ_TYPE_LEVEL_HIGH>, /* CE7 */
+ <0 422 IRQ_TYPE_LEVEL_HIGH>, /* CE8 */
+ <0 423 IRQ_TYPE_LEVEL_HIGH>, /* CE9 */
+ <0 424 IRQ_TYPE_LEVEL_HIGH>, /* CE10 */
+ <0 425 IRQ_TYPE_LEVEL_HIGH>; /* CE11 */
+ qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
+ qcom,iommu-dma = "bypass";
+ qcom,iommu-faults = "stall-disable";
+ qcom,hyp_enabled;
+ vdd-cx-mx-supply = <&pm660_l5>;
+ vdd-1.8-xo-supply = <&pm660_l9_pin_ctrl>;
+ vdd-1.3-rfa-supply = <&pm660_l6_pin_ctrl>;
+ vdd-3.3-ch0-supply = <&pm660_l19_pin_ctrl>;
+ qcom,vdd-cx-mx-config = <848000 848000>;
+ qcom,vdd-1.8-xo-config = <1750000 1900000>;
+ qcom,vdd-1.3-rfa-config = <1200000 1370000>;
+ qcom,vdd-3.3-ch0-config = <3200000 3400000>;
+ qcom,wlan-msa-memory = <0x100000>;
+ qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
+ qcom,smp2p_map_wlan_1_in {
+ interrupts-extended = <&smp2p_wlan_1_in 0 0>,
+ <&smp2p_wlan_1_in 1 0>;
+ interrupt-names = "qcom,smp2p-force-fatal-error",
+ "qcom,smp2p-early-crash-ind";
+ };
+ };
+
+ qcom,lpass@15700000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x15700000 0x00100>;
+ reg-names = "base_reg";
+
+ vdd_cx-supply = <&pm660l_l9_level>;
+ qcom,proxy-reg-names = "vdd_cx";
+ qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
+
+ clocks = <&clock_rpmcc CXO_SMD_PIL_LPASS_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+
+ qcom,pas-id = <1>;
+ qcom,mas-crypto = <&mas_crypto_c0>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <423>;
+ qcom,sysmon-id = <1>;
+ qcom,ssctl-instance-id = <0x14>;
+ qcom,firmware-name = "adsp";
+ memory-region = <&adsp_fw_mem>;
+
+ /* GPIO inputs from lpass */
+ interrupts-extended = <&wakegic 0 162 1>,
+ <&adsp_smp2p_in 0 0>,
+ <&adsp_smp2p_in 2 0>,
+ <&adsp_smp2p_in 1 0>,
+ <&adsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack";
+
+ /* GPIO output to lpass */
+ qcom,smem-states = <&adsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+ status = "ok";
+ };
+
+ qcom,turing@1a300000 {
+ compatible = "qcom,pil-tz-generic";
+ reg = <0x1a300000 0x00100>;
+ reg-names = "base_reg";
+
+ vdd_cx-supply = <&pm660l_s3_level>;
+ qcom,proxy-reg-names = "vdd_cx";
+ qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
+
+ clocks = <&clock_rpmcc CXO_SMD_PIL_CDSP_CLK>;
+ clock-names = "xo";
+ qcom,proxy-clock-names = "xo";
+
+ qcom,pas-id = <18>;
+ qcom,mas-crypto = <&mas_crypto_c0>;
+ qcom,proxy-timeout-ms = <10000>;
+ qcom,smem-id = <601>;
+ qcom,sysmon-id = <7>;
+ qcom,ssctl-instance-id = <0x17>;
+ qcom,firmware-name = "cdsp";
+ memory-region = <&cdsp_fw_mem>;
+
+ /* Inputs from turing */
+ interrupts-extended = <&wakegic 0 518 1>,
+ <&cdsp_smp2p_in 0 0>,
+ <&cdsp_smp2p_in 2 0>,
+ <&cdsp_smp2p_in 1 0>,
+ <&cdsp_smp2p_in 3 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack";
+
+ /* Outputs to turing */
+ qcom,smem-states = <&cdsp_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+ status = "ok";
+ };
+
+ pil_modem: qcom,mss@4080000 {
+ compatible = "qcom,pil-q6v55-mss";
+ reg = <0x4080000 0x100>,
+ <0x1f63000 0x008>,
+ <0x1f65000 0x008>,
+ <0x1f64000 0x008>,
+ <0x4180000 0x040>,
+ <0x00179000 0x004>,
+ <0x01fe5048 0x004>;
+ reg-names = "qdsp6_base", "halt_q6", "halt_modem",
+ "halt_nc", "rmb_base", "restart_reg",
+ "cxip_lm_vote_clear";
+
+ clocks = <&clock_rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&clock_gcc GCC_MSS_CFG_AHB_CLK>,
+ <&clock_gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
+ <&clock_gcc GCC_BOOT_ROM_AHB_CLK>,
+ <&clock_gcc GPLL0_OUT_MSSCC>,
+ <&clock_gcc GCC_MSS_SNOC_AXI_CLK>,
+ <&clock_gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_CLK>;
+ clock-names = "xo", "iface_clk", "bus_clk",
+ "mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
+ "mnoc_axi_clk", "qdss_clk";
+ qcom,proxy-clock-names = "xo", "qdss_clk";
+ qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
+ "gpll0_mss_clk", "snoc_axi_clk",
+ "mnoc_axi_clk";
+
+ qcom,sequential-fw-load;
+ vdd_cx-supply = <&pm660l_s3_level>;
+ vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ vdd_mx-supply = <&pm660l_s5_level>;
+ vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
+ qcom,firmware-name = "modem";
+ qcom,pil-self-auth;
+ qcom,sysmon-id = <0>;
+ qcom,ssctl-instance-id = <0x12>;
+ qcom,qdsp6v62-1-5;
+ memory-region = <&modem_fw_mem>;
+ qcom,mem-protect-id = <0xF>;
+ qcom,complete-ramdump;
+ qcom,cx-ipeak-vote;
+
+ /* Inputs from mss */
+ interrupts-extended = <&wakegic 0 448 1>,
+ <&modem_smp2p_in 0 0>,
+ <&modem_smp2p_in 2 0>,
+ <&modem_smp2p_in 1 0>,
+ <&modem_smp2p_in 3 0>,
+ <&modem_smp2p_in 7 0>;
+
+ interrupt-names = "qcom,wdog",
+ "qcom,err-fatal",
+ "qcom,proxy-unvote",
+ "qcom,err-ready",
+ "qcom,stop-ack",
+ "qcom,shutdown-ack";
+
+ /* Outputs to mss */
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "qcom,force-stop";
+
+ status = "ok";
+ qcom,mba-mem@0 {
+ compatible = "qcom,pil-mba-mem";
+ memory-region = <&pil_mba_mem>;
+ };
+ };
+
+ qcom,msm-rtb {
+ compatible = "qcom,msm-rtb";
+ qcom,rtb-size = <0x100000>;
+ };
+
+ qcom,mpm2-sleep-counter@10a3000 {
+ compatible = "qcom,mpm2-sleep-counter";
+ reg = <0x10a3000 0x1000>;
+ clock-frequency = <32768>;
+ };
+
+ qcom,msm-imem@146bf000 {
+ compatible = "qcom,msm-imem";
+ reg = <0x146bf000 0x1000>;
+ ranges = <0x0 0x146bf000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ mem_dump_table@10 {
+ compatible = "qcom,msm-imem-mem_dump_table";
+ reg = <0x10 8>;
+ };
+
+ dload_type@1c {
+ compatible = "qcom,msm-imem-dload-type";
+ reg = <0x1c 4>;
+ };
+
+ restart_reason@65c {
+ compatible = "qcom,msm-imem-restart_reason";
+ reg = <0x65c 4>;
+ };
+
+ boot_stats@6b0 {
+ compatible = "qcom,msm-imem-boot_stats";
+ reg = <0x6b0 32>;
+ };
+
+ kaslr_offset@6d0 {
+ compatible = "qcom,msm-imem-kaslr_offset";
+ reg = <0x6d0 12>;
+ };
+
+ pil@94c {
+ compatible = "qcom,msm-imem-pil";
+ reg = <0x94c 200>;
+ };
+
+ diag_dload@c8 {
+ compatible = "qcom,msm-imem-diag-dload";
+ reg = <0xc8 200>;
+ };
+
+ ss_mdump@b88 {
+ compatible = "qcom,msm-imem-minidump";
+ reg = <0xb88 28>;
+ };
+ };
+
+ qcom,ghd {
+ compatible = "qcom,gladiator-hang-detect";
+ qcom,threshold-arr = <0x179d141c 0x179d1420
+ 0x179d1424 0x179d1428
+ 0x179d142c 0x179d1430>;
+ qcom,config-reg = <0x179d1434>;
+ };
+
+ qcom,msm-gladiator-v2@17900000 {
+ compatible = "qcom,msm-gladiator-v2";
+ reg = <0x17900000 0xe000>;
+ reg-names = "gladiator_base";
+ interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "atb_clk";
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>;
+ };
+
+ cpu_pmu: cpu-pmu {
+ compatible = "arm,armv8-pmuv3";
+ qcom,irq-is-percpu;
+ interrupts = <1 6 4>;
+ };
+
+ qcom_seecom: qseecom@86d00000 {
+ compatible = "qcom,qseecom";
+ reg = <0x86d00000 0x2200000>;
+ reg-names = "secapp-region";
+ qcom,hlos-num-ce-hw-instances = <1>;
+ qcom,hlos-ce-hw-instance = <0>;
+ qcom,qsee-ce-hw-instance = <0>;
+ qcom,disk-encrypt-pipe-pair = <2>;
+ qcom,support-fde;
+ qcom,fde-key-size;
+ qcom,no-clock-support;
+ qcom,msm-bus,name = "qseecom-noc";
+ qcom,msm-bus,num-cases = <4>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <55 512 0 0>,
+ <55 512 200000 400000>,
+ <55 512 300000 800000>,
+ <55 512 400000 1000000>;
+ clock-names = "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks = <&clock_rpmcc QSEECOM_CE1_CLK>,
+ <&clock_rpmcc QSEECOM_CE1_CLK>,
+ <&clock_rpmcc QSEECOM_CE1_CLK>,
+ <&clock_rpmcc QSEECOM_CE1_CLK>;
+ qcom,ce-opp-freq = <171430000>;
+ qcom,qsee-reentrancy-support = <2>;
+ };
+
+ qcom_cedev: qcedev@1de0000{
+ compatible = "qcom,qcedev";
+ reg = <0x1de0000 0x20000>,
+ <0x1dc4000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <0 206 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <1>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,ce-hw-shared;
+ qcom,bam-ee = <0>;
+ qcom,msm-bus,name = "qcedev-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <55 512 0 0>,
+ <55 512 393600 393600>;
+ clock-names = "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks = <&clock_rpmcc QCEDEV_CE1_CLK>,
+ <&clock_rpmcc QCEDEV_CE1_CLK>,
+ <&clock_rpmcc QCEDEV_CE1_CLK>,
+ <&clock_rpmcc QCEDEV_CE1_CLK>;
+ qcom,ce-opp-freq = <171430000>;
+ };
+
+ qcom_crypto: qcrypto@1de0000 {
+ compatible = "qcom,qcrypto";
+ reg = <0x1de0000 0x20000>,
+ <0x1dc4000 0x24000>;
+ reg-names = "crypto-base","crypto-bam-base";
+ interrupts = <0 206 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,bam-pipe-pair = <2>;
+ qcom,ce-hw-instance = <0>;
+ qcom,ce-device = <0>;
+ qcom,bam-ee = <0>;
+ qcom,ce-hw-shared;
+ qcom,clk-mgmt-sus-res;
+ qcom,msm-bus,name = "qcrypto-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <55 512 0 0>,
+ <55 512 393600 393600>;
+ clock-names = "core_clk_src", "core_clk",
+ "iface_clk", "bus_clk";
+ clocks = <&clock_rpmcc QCRYPTO_CE1_CLK>,
+ <&clock_rpmcc QCRYPTO_CE1_CLK>,
+ <&clock_rpmcc QCRYPTO_CE1_CLK>,
+ <&clock_rpmcc QCRYPTO_CE1_CLK>;
+ qcom,ce-opp-freq = <171430000>;
+ qcom,use-sw-aes-cbc-ecb-ctr-algo;
+ qcom,use-sw-aes-xts-algo;
+ qcom,use-sw-aes-ccm-algo;
+ qcom,use-sw-ahash-algo;
+ qcom,use-sw-aead-algo;
+ qcom,use-sw-hmac-algo;
+ };
+
+ qcom_tzlog: tz-log@146bf720 {
+ compatible = "qcom,tz-log";
+ reg = <0x146bf720 0x3000>;
+ qcom,hyplog-enabled;
+ hyplog-address-offset = <0x410>;
+ hyplog-size-offset = <0x414>;
+ };
+
+ qcom_rng: qrng@793000 {
+ compatible = "qcom,msm-rng";
+ reg = <0x793000 0x1000>;
+ qcom,msm-rng-iface-clk;
+ qcom,no-qrng-config;
+ qcom,msm-bus,name = "msm-rng-noc";
+ qcom,msm-bus,num-cases = <2>;
+ qcom,msm-bus,num-paths = <1>;
+ qcom,msm-bus,vectors-KBps =
+ <1 618 0 0>, /* No vote */
+ <1 618 0 800>; /* 100 KHz */
+ clocks = <&clock_gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "iface_clk";
+ };
+
+ qcom,chd_silver {
+ compatible = "qcom,core-hang-detect";
+ label = "silver";
+ qcom,threshold-arr = <0x179880b0 0x179980b0
+ 0x179a80b0 0x179b80b0>;
+ qcom,config-arr = <0x179880b8 0x179980b8
+ 0x179a80b8 0x179b80b8>;
+ };
+
+ qcom,chd_gold {
+ compatible = "qcom,core-hang-detect";
+ label = "gold";
+ qcom,threshold-arr = <0x178880b0 0x178980b0
+ 0x178a80b0 0x178b80b0>;
+ qcom,config-arr = <0x178880b8 0x178980b8
+ 0x178a80b8 0x178b80b8>;
+ };
+
+ ufsphy1: ufsphy@1da7000 {
+ compatible = "qcom,ufs-phy-qmp-v3-660";
+ reg = <0x1da7000 0xdb8>;
+ reg-names = "phy_mem";
+ #phy-cells = <0>;
+ clock-names = "ref_clk_src",
+ "ref_clk",
+ "ref_aux_clk";
+ clocks = <&clock_rpmcc RPM_SMD_LN_BB_CLK1>,
+ <&clock_gcc GCC_UFS_CLKREF_CLK>,
+ <&clock_gcc GCC_UFS_PHY_AUX_CLK>;
+ status = "disabled";
+ };
+
+ ufs1: ufshc@1da4000 {
+ compatible = "qcom,ufshc";
+ reg = <0x1da4000 0x3000>, <0x1db0000 0x8000>;
+ reg-names = "ufs_mem", "ufs_ice";
+ interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufsphy1>;
+ phy-names = "ufsphy";
+
+ clock-names =
+ "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "core_clk_ice",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk";
+ clocks =
+ <&clock_gcc GCC_UFS_AXI_CLK>,
+ <&clock_gcc GCC_AGGRE2_UFS_AXI_CLK>,
+ <&clock_gcc GCC_UFS_AHB_CLK>,
+ <&clock_gcc GCC_UFS_UNIPRO_CORE_CLK>,
+ <&clock_gcc GCC_UFS_ICE_CORE_CLK>,
+ <&clock_rpmcc RPM_SMD_LN_BB_CLK1>,
+ <&clock_gcc GCC_UFS_TX_SYMBOL_0_CLK>,
+ <&clock_gcc GCC_UFS_RX_SYMBOL_0_CLK>;
+ freq-table-hz =
+ <50000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <37500000 150000000>,
+ <75000000 300000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ lanes-per-direction = <1>;
+ spm-level = <5>;
+ dev-ref-clk-freq = <0>; /* 19.2 MHz */
+
+ non-removable;
+ qcom,msm-bus,name = "ufs1";
+ qcom,msm-bus,num-cases = <12>;
+ qcom,msm-bus,num-paths = <2>;
+ qcom,msm-bus,vectors-KBps =
+ <95 512 0 0>, <1 650 0 0>, /* No vote */
+ <95 512 922 0>, <1 650 1000 0>, /* PWM G1 */
+ <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */
+ <95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */
+ <95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */
+ <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */
+ <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */
+ <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RA */
+ <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */
+ <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */
+ <95 512 2097152 0>, <1 650 102400 0>, /* HS G3 RB */
+ <95 512 7643136 0>, <1 650 307200 0>; /* Max. bandwidth */
+ qcom,bus-vector-names = "MIN",
+ "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
+ "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
+ "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
+ "MAX";
+
+ pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
+ pinctrl-0 = <&ufs_dev_reset_assert>;
+ pinctrl-1 = <&ufs_dev_reset_deassert>;
+
+ resets = <&clock_gcc GCC_UFS_BCR>;
+ reset-names = "core_reset";
+
+ status = "disabled";
+ };
+
+ jtag_fuse: jtagfuse@786040 {
+ compatible = "qcom,jtag-fuse-v4";
+ reg = <0x786040 0x8>;
+ reg-names = "fuse-base";
+ };
+
+ jtag_mm0: jtagmm@7840000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7840000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU0>;
+ };
+
+ jtag_mm1: jtagmm@7940000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7940000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU1>;
+ };
+
+ jtag_mm2: jtagmm@7a40000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7a40000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU2>;
+ };
+
+ jtag_mm3: jtagmm@7b40000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7b40000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU3>;
+ };
+
+ jtag_mm4: jtagmm@7c40000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7c40000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU4>;
+ };
+
+ jtag_mm5: jtagmm@7d40000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7d40000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU5>;
+ };
+
+ jtag_mm6: jtagmm@7e40000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7e40000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU6>;
+ };
+
+ jtag_mm7: jtagmm@7f40000 {
+ compatible = "qcom,jtagv8-mm";
+ reg = <0x7f40000 0x1000>;
+ reg-names = "etm-base";
+
+ clocks = <&clock_rpmcc RPM_SMD_QDSS_CLK>,
+ <&clock_rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "core_clk", "core_a_clk";
+
+ qcom,coresight-jtagmm-cpu = <&CPU7>;
+ };
+};
+
+#include "sdm660-ion.dtsi"
+#include "sdm660-bus.dtsi"
+#include "pm660.dtsi"
+#include "pm660l.dtsi"
+#include "pm660-rpm-regulator.dtsi"
+#include "pm660l-rpm-regulator.dtsi"
+#include "sdm660-regulator.dtsi"
+#include "msm-gdsc-660.dtsi"
+#include "sdm660-gpu.dtsi"
+#include "sdm660-pm.dtsi"
+#include "sdm660-thermal.dtsi"
+
+&gdsc_usb30 {
+ status = "ok";
+};
+
+&gdsc_ufs {
+ status = "ok";
+};
+
+&gdsc_bimc_smmu {
+ clock-names = "bus_clk";
+ clocks = <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
+ proxy-supply = <&gdsc_bimc_smmu>;
+ qcom,proxy-consumer-enable;
+ status = "ok";
+};
+
+&gdsc_hlos1_vote_lpass_adsp {
+ status = "ok";
+};
+
+&gdsc_hlos1_vote_turing_adsp {
+ status = "ok";
+};
+
+&gdsc_hlos2_vote_turing_adsp {
+ status = "ok";
+};
+
+&gdsc_venus {
+ status = "ok";
+};
+
+&gdsc_venus_core0 {
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&gdsc_camss_top {
+ status = "ok";
+};
+
+&gdsc_vfe0 {
+ parent-supply = <&gdsc_camss_top>;
+ status = "ok";
+};
+
+&gdsc_vfe1 {
+ parent-supply = <&gdsc_camss_top>;
+ status = "ok";
+};
+
+&gdsc_cpp {
+ parent-supply = <&gdsc_camss_top>;
+ qcom,support-hw-trigger;
+ status = "ok";
+};
+
+&gdsc_mdss {
+ proxy-supply = <&gdsc_mdss>;
+ qcom,proxy-consumer-enable;
+ status = "ok";
+};
+
+&gdsc_gpu_gx {
+ clock-names = "core_root_clk";
+ clocks = <&clock_gfx GFX3D_CLK_SRC>;
+ qcom,force-enable-root-clk;
+ parent-supply = <&gfx_vreg_corner>;
+ status = "ok";
+};
+
+&gdsc_gpu_cx {
+ status = "ok";
+};
+
+
+#include "msm-arm-smmu-660.dtsi"
+#include "msm-arm-smmu-impl-defs-660.dtsi"
+#include "sdm660-common.dtsi"
+#include "sdm660-blsp.dtsi"
+#include "msm-rdbg.dtsi"
+#include "sdm660-camera.dtsi"
+#include "sdm660-vidc.dtsi"
+#include "msm-audio.dtsi"
+#include "sdm660-audio.dtsi"
+
+&pm660l_gpios {
+ /* GPIO 7 for VOL_UP */
+ key_vol_up {
+ key_vol_up_default: key_vol_up_default {
+ pins = "gpio7";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+ };
+};
+
+&msm_vidc {
+ qcom,cx-ipeak-data = <&cx_ipeak_lm 4>;
+ qcom,clock-freq-threshold = <518400000>;
+};
+
+&soc {
+ gpio_keys {
+ status = "okay";
+ compatible = "gpio-keys";
+ input-name = "gpio-keys";
+ pinctrl-names = "tlmm_gpio_key_active","tlmm_gpio_key_suspend",
+ "default";
+ pinctrl-0 = <&gpio_key_active &key_vol_up_default>;
+ pinctrl-1 = <&gpio_key_suspend>;
+
+ camera_focus {
+ label = "camera_focus";
+ gpios = <&tlmm 64 0x1>;
+ linux,input-type = <1>;
+ linux,code = <0x210>;
+ debounce-interval = <15>;
+ };
+
+ camera_snapshot {
+ label = "camera_snapshot";
+ gpios = <&tlmm 113 0x1>;
+ linux,input-type = <1>;
+ linux,code = <0x2fe>;
+ debounce-interval = <15>;
+ };
+
+ vol_up {
+ label = "volume_up";
+ gpios = <&pm660l_gpios 7 0x1>;
+ linux,input-type = <1>;
+ linux,code = <115>;
+ linux,can-disable;
+ gpio-key,wakeup;
+ debounce-interval = <15>;
+ };
+ };
+};
+
+&blsp2_uart1_hs {
+ status = "ok";
+};
+
+&pm660_adc_tm {
+ io-channels = <&pm660_vadc ADC_XO_THERM_PU2>,
+ <&pm660_vadc ADC_AMUX_THM1_PU2>,
+ <&pm660_vadc ADC_AMUX_THM5_PU2>;
+
+ /* Channel nodes */
+ xo_therm {
+ reg = <ADC_XO_THERM_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ msm_therm{
+ reg = <ADC_AMUX_THM1_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+
+ quiet_therm{
+ reg = <ADC_AMUX_THM5_PU2>;
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ };
+};
+
+#include "sdm660-mdss.dtsi"
+#include "sdm660-mdss-pll.dtsi"
diff --git a/arch/arm64/boot/dts/vendor/qcom/sdxprairie-thermal-integrated.dtsi b/arch/arm64/boot/dts/vendor/qcom/sdxprairie-thermal-integrated.dtsi
new file mode 100755
index 0000000..45518cf
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/sdxprairie-thermal-integrated.dtsi
@@ -0,0 +1,440 @@
+#include <dt-bindings/thermal/qmi_thermal.h>
+
+&soc {
+ qmi-tmd-devices {
+ compatible = "qcom,qmi-cooling-devices";
+
+ modem {
+ qcom,instance-id = <QMI_MODEM_INST_ID>;
+
+ modem_pa: modem_pa {
+ qcom,qmi-dev-name = "pa";
+ #cooling-cells = <2>;
+ };
+
+ modem_pa_fr1: modem_pa_fr1 {
+ qcom,qmi-dev-name = "pa_fr1";
+ #cooling-cells = <2>;
+ };
+
+ modem_tj: modem_tj {
+ qcom,qmi-dev-name = "modem";
+ #cooling-cells = <2>;
+ };
+
+ modem_current: modem_current {
+ qcom,qmi-dev-name = "modem_current";
+ #cooling-cells = <2>;
+ };
+
+ modem_skin: modem_skin {
+ qcom,qmi-dev-name = "modem_skin";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw_skin0: modem_mmw_skin0 {
+ qcom,qmi-dev-name = "mmw_skin0";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw_skin1: modem_mmw_skin1 {
+ qcom,qmi-dev-name = "mmw_skin1";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw_skin2: modem_mmw_skin2 {
+ qcom,qmi-dev-name = "mmw_skin2";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw_skin3: modem_mmw_skin3 {
+ qcom,qmi-dev-name = "mmw_skin3";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw0: modem_mmw0 {
+ qcom,qmi-dev-name = "mmw0";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw1: modem_mmw1 {
+ qcom,qmi-dev-name = "mmw1";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw2: modem_mmw2 {
+ qcom,qmi-dev-name = "mmw2";
+ #cooling-cells = <2>;
+ };
+
+ modem_mmw3: modem_mmw3 {
+ qcom,qmi-dev-name = "mmw3";
+ #cooling-cells = <2>;
+ };
+
+ modem_bcl: modem_bcl {
+ qcom,qmi-dev-name = "vbatt_low";
+ #cooling-cells = <2>;
+ };
+
+ modem_charge_state: modem_charge_state {
+ qcom,qmi-dev-name = "charge_state";
+ #cooling-cells = <2>;
+ };
+
+ modem_vdd: modem_vdd {
+ qcom,qmi-dev-name = "cpuv_restriction_cold";
+ #cooling-cells = <2>;
+ };
+
+ modem_wlan: modem_wlan {
+ qcom,qmi-dev-name = "wlan";
+ #cooling-cells = <2>;
+ };
+ };
+ };
+
+ qmi_sensor: qmi-ts-sensors {
+ compatible = "qcom,qmi-sensors";
+ #thermal-sensor-cells = <1>;
+
+ modem {
+ qcom,instance-id = <QMI_MODEM_INST_ID>;
+ qcom,qmi-sensor-names = "pa",
+ "pa_1",
+ "qfe_wtr0",
+ "modem_tsens",
+ "qfe_mmw0",
+ "qfe_mmw1",
+ "qfe_mmw2",
+ "qfe_mmw3",
+ "xo_therm",
+ "qfe_mmw_streamer0",
+ "qfe_mmw0_mod",
+ "qfe_mmw1_mod",
+ "qfe_mmw2_mod",
+ "qfe_mmw3_mod",
+ "qfe_ret_pa0",
+ "qfe_wtr_pa0",
+ "qfe_wtr_pa1",
+ "qfe_wtr_pa2",
+ "qfe_wtr_pa3",
+ "sys_therm1",
+ "sys_therm2",
+ "modem_tsens1",
+ "BEAMER_W_THERM",
+ "BEAMER_N_THERM",
+ "BEAMER_E_THERM";
+ };
+ };
+};
+
+&thermal_zones {
+ modem-lte-sub6-pa1 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_PA)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-lte-sub6-pa2 {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_PA_1)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_QFE_MMW_0)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_QFE_MMW_1)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_QFE_MMW_2)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_QFE_MMW_3)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-skin-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_XO_THERM)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-wifi-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_SYS_THERM_1)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-ambient-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_SYS_THERM_2)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-0-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_MODEM_TSENS)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_MODEM_TSENS_1)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-streamer-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_QFE_MMW_STREAMER_0)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw0-mod-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_QFE_MMW_0_MOD)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw1-mod-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_QFE_MMW_1_MOD)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw2-mod-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_QFE_MMW_2_MOD)>;
+ wake-capable-sensor;
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw3-mod-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_QFE_MMW_3_MOD)>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw-pa1-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_BEAMER_W_THERM)>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw-pa2-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_BEAMER_N_THERM)>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+
+ modem-mmw-pa3-usr {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-governor = "user_space";
+ thermal-sensors = <&qmi_sensor
+ (QMI_MODEM_INST_ID+QMI_BEAMER_E_THERM)>;
+ wake-capable-sensor;
+
+ trips {
+ active-config0 {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/skeleton64.dtsi b/arch/arm64/boot/dts/vendor/qcom/skeleton64.dtsi
new file mode 100755
index 0000000..1f8ba28
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/skeleton64.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Skeleton device tree in the 64 bits version; the bare minimum
+ * needed to boot; just include and add a compatible value. The
+ * bootloader will typically populate the memory node.
+ */
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ cpus { };
+ soc { };
+ chosen { };
+ aliases { };
+ memory { device_type = "memory"; reg = <0 0 0 0>; };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/smb1355.dtsi b/arch/arm64/boot/dts/vendor/qcom/smb1355.dtsi
new file mode 100755
index 0000000..f244a0d
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/smb1355.dtsi
@@ -0,0 +1,87 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+
+smb1355: qcom,smb1355@c {
+ compatible = "qcom,i2c-pmic";
+ reg = <0xc>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&spmi_bus>;
+ interrupts = <0x2 0xC5 0x0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt_names = "smb1355";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ qcom,periph-map = <0x10 0x12 0x13 0x16>;
+ status = "disabled";
+
+ smb1355_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ smb1355_charger: qcom,smb1355-charger@1000 {
+ compatible = "qcom,smb1355";
+ qcom,pmic-revid = <&smb1355_revid>;
+ reg = <0x1000 0x700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&smb1355>;
+ status = "disabled";
+
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts = <0x10 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "chg-state-change";
+ };
+
+ qcom,chgr-misc@1600 {
+ reg = <0x1600 0x100>;
+ interrupts = <0x16 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x16 0x6 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog-bark",
+ "temperature-change";
+ };
+ };
+};
+
+smb1355_0: qcom,smb1355@8 {
+ compatible = "qcom,i2c-pmic";
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&spmi_bus>;
+ interrupts = <0x0 0xd1 0x0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt_names = "smb1355_0";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ qcom,periph-map = <0x10 0x12 0x13 0x16>;
+ status = "disabled";
+
+ smb1355_revid_0: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100 0x100>;
+ };
+
+ smb1355_charger_0: qcom,smb1355-charger@1000 {
+ compatible = "qcom,smb1355";
+ qcom,pmic-revid = <&smb1355_revid_0>;
+ reg = <0x1000 0x700>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&smb1355_0>;
+ status = "disabled";
+
+ qcom,chgr@1000 {
+ reg = <0x1000 0x100>;
+ interrupts = <0x10 0x1 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "chg-state-change";
+ };
+
+ qcom,chgr-misc@1600 {
+ reg = <0x1600 0x100>;
+ interrupts = <0x16 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x16 0x6 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog-bark",
+ "temperature-change";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/smb1390.dtsi b/arch/arm64/boot/dts/vendor/qcom/smb1390.dtsi
new file mode 100755
index 0000000..0996782
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/smb1390.dtsi
@@ -0,0 +1,60 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+
+smb1390: qcom,smb1390@10 {
+ compatible = "qcom,i2c-pmic";
+ reg = <0x10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&spmi_bus>;
+ interrupts = <0x2 0xC5 0x0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt_names = "smb1390";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ qcom,periph-map = <0x10>;
+ status = "disabled";
+
+ smb1390_revid: qcom,revid@100 {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100>;
+ };
+
+ smb1390_charger: qcom,charge_pump {
+ compatible = "qcom,smb1390-charger-psy";
+ qcom,pmic-revid = <&smb1390_revid>;
+ interrupt-parent = <&smb1390>;
+ status = "disabled";
+
+ qcom,core {
+ interrupts = <0x10 0x0 IRQ_TYPE_EDGE_BOTH>,
+ <0x10 0x1 IRQ_TYPE_EDGE_BOTH>,
+ <0x10 0x2 IRQ_TYPE_EDGE_BOTH>,
+ <0x10 0x3 IRQ_TYPE_EDGE_BOTH>,
+ <0x10 0x4 IRQ_TYPE_EDGE_BOTH>,
+ <0x10 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x10 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x10 0x7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "switcher-off-window",
+ "switcher-off-fault",
+ "tsd-fault",
+ "irev-fault",
+ "vph-ov-hard",
+ "vph-ov-soft",
+ "ilim",
+ "temp-alarm";
+ };
+ };
+};
+
+smb1390_slave: qcom,smb1390_slave@18 {
+ compatible = "qcom,i2c-pmic";
+ reg = <0x18>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ qcom,periph-map = <0x10>;
+ status = "disabled";
+
+ smb1390_slave_charger: qcom,charge_pump_slave {
+ compatible = "qcom,smb1390-slave";
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/smb1394.dtsi b/arch/arm64/boot/dts/vendor/qcom/smb1394.dtsi
new file mode 100755
index 0000000..23d03b6
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/smb1394.dtsi
@@ -0,0 +1,40 @@
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+smb1394: qcom,smb1394@34 {
+ compatible = "qcom,i2c-pmic";
+ reg = <0x34>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ qcom,periph-map = <0x6 0x26 0x27>;
+ status = "disabled";
+
+ smb1394_revid: qcom,revid {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100>;
+ };
+
+ smb1394_div2_cp_primary: qcom,div2_cp_pry {
+ compatible = "qcom,smb1394-div2-cp-primary";
+ qcom,pmic-revid = <&smb1394_revid>;
+ #io-channel-cells = <1>;
+ interrupts = <0x26 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x26 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x26 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x26 0x7 IRQ_TYPE_EDGE_RISING>,
+ <0x27 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x27 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x27 0x7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "temp-shdwn",
+ "div2-irev",
+ "usbin-uv",
+ "usbin-ov",
+ "div2-ilim",
+ "div2-win-uv",
+ "div2-win-ov";
+ qcom,div2-cp-min-ilim-ua = <1000000>;
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/smb1398.dtsi b/arch/arm64/boot/dts/vendor/qcom/smb1398.dtsi
new file mode 100755
index 0000000..91d172c
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/smb1398.dtsi
@@ -0,0 +1,63 @@
+#include <dt-bindings/interrupt-controller/irq.h>
+
+smb1396: qcom,smb1396@34 {
+ compatible = "qcom,i2c-pmic";
+ reg = <0x34>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ qcom,periph-map = <0x6 0x26 0x27>;
+ status = "disabled";
+
+ smb1396_revid: qcom,revid {
+ compatible = "qcom,qpnp-revid";
+ reg = <0x100>;
+ };
+
+ smb1396_div2_cp_master: qcom,div2_cp {
+ compatible = "qcom,smb1396-div2-cp-master";
+ qcom,pmic-revid = <&smb1396_revid>;
+ io-channels = <&pm7250b_vadc ADC_AMUX_THM2>;
+ io-channel-names = "die_temp";
+ interrupts = <0x26 0x1 IRQ_TYPE_EDGE_RISING>,
+ <0x26 0x3 IRQ_TYPE_EDGE_RISING>,
+ <0x26 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x26 0x7 IRQ_TYPE_EDGE_RISING>,
+ <0x27 0x5 IRQ_TYPE_EDGE_RISING>,
+ <0x27 0x6 IRQ_TYPE_EDGE_RISING>,
+ <0x27 0x7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "temp-shdwn",
+ "div2-irev",
+ "usbin-uv",
+ "usbin-ov",
+ "div2-ilim",
+ "div2-win-uv",
+ "div2-win-ov";
+ status = "disabled";
+ };
+};
+
+smb1396_slave: qcom,smb1396@35 {
+ compatible = "qcom,i2c-pmic";
+ reg = <0x35>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ smb1396_div2_cp_slave: qcom,div2_cp_slave {
+ compatible = "qcom,smb1396-div2-cp-slave";
+ status = "disabled";
+ };
+};
+
+smb1398: qcom,smb1398@36 {
+ compatible = "qcom,i2c-pmic";
+ reg = <0x36>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ smb1398_pre_regulator: qcom,pre_regulator {
+ compatible = "qcom,smb1398-pre-regulator";
+ status = "disabled";
+ };
+};
diff --git a/arch/arm64/boot/dts/vendor/qcom/vbms-batterydata-mlp356477-2800mah.dtsi b/arch/arm64/boot/dts/vendor/qcom/vbms-batterydata-mlp356477-2800mah.dtsi
new file mode 100755
index 0000000..b8a1124
--- /dev/null
+++ b/arch/arm64/boot/dts/vendor/qcom/vbms-batterydata-mlp356477-2800mah.dtsi
@@ -0,0 +1,106 @@
+qcom,mlp356477_2800mah {
+ qcom,fcc-mah = <4200>;
+ qcom,batt-id-kohm = <82>;
+ qcom,rbatt-capacitive-mohm = <50>;
+ qcom,default-rbatt-mohm = <148>;
+ qcom,max-voltage-uv = <4400000>;
+ qcom,v-cutoff-uv = <3400000>;
+ qcom,chg-term-ua = <100000>;
+ qcom,battery-type = "mlp356477_2800mah";
+
+ qcom,fcc-temp-lut {
+ qcom,lut-col-legend = <(-20) 0 25 40 60>;
+ qcom,lut-data = <2863 2856 2854 2852 2841>;
+ };
+
+ qcom,ibat-acc-lut {
+ qcom,lut-col-legend = <(-20) 0 25>;
+ qcom,lut-row-legend = <0 250 500 1000>;
+ qcom,lut-data = <2792 2798 2797>,
+ <618 2712 2780>,
+ <128 2440 2766>,
+ <14 1806 2724>;
+ };
+
+ qcom,pc-temp-ocv-lut {
+ qcom,lut-col-legend = <(-20) 0 25 40 60>;
+ qcom,lut-row-legend = <100 95 90 85 80>,
+ <75 70 65 60 55>,
+ <50 45 40 35 30>,
+ <25 20 16 13 11>,
+ <10 9 8 7 6>,
+ <5 4 3 2 1>,
+ <0>;
+ qcom,lut-data = <4390 4384 4378 4374 4366>,
+ <4252 4302 4314 4313 4307>,
+ <4160 4238 4256 4255 4250>,
+ <4103 4179 4200 4198 4194>,
+ <4014 4126 4144 4144 4138>,
+ <3962 4077 4092 4090 4086>,
+ <3913 4022 4042 4042 4037>,
+ <3875 3960 3993 3995 3992>,
+ <3850 3914 3946 3948 3946>,
+ <3832 3872 3892 3894 3892>,
+ <3816 3839 3858 3860 3859>,
+ <3802 3814 3832 3834 3832>,
+ <3787 3798 3810 3812 3811>,
+ <3771 3785 3792 3794 3792>,
+ <3754 3772 3774 3774 3768>,
+ <3734 3756 3756 3749 3738>,
+ <3712 3734 3734 3726 3714>,
+ <3692 3712 3712 3704 3690>,
+ <3672 3698 3692 3684 3674>,
+ <3656 3689 3686 3680 3669>,
+ <3646 3685 3685 3679 3668>,
+ <3634 3681 3683 3678 3666>,
+ <3620 3676 3680 3676 3664>,
+ <3604 3668 3676 3670 3654>,
+ <3580 3651 3660 3652 3630>,
+ <3550 3620 3625 3614 3590>,
+ <3508 3574 3575 3565 3538>,
+ <3445 3510 3510 3500 3470>,
+ <3350 3420 3421 3413 3377>,
+ <3182 3274 3282 3266 3232>,
+ <3000 3000 3000 3000 3000>;
+ };
+
+ qcom,rbatt-sf-lut {
+ qcom,lut-col-legend = <(-20) 0 25 40 60>;
+ qcom,lut-row-legend = <100 95 90 85 80>,
+ <75 70 65 60 55>,
+ <50 45 40 35 30>,
+ <25 20 16 13 11>,
+ <10 9 8 7 6>,
+ <5 4 3 2 1>;
+ qcom,lut-data = <1593 376 99 75 68>,
+ <1591 376 99 75 68>,
+ <1455 370 99 75 68>,
+ <1391 362 99 76 67>,
+ <1280 358 99 76 69>,
+ <1245 363 102 78 70>,
+ <1213 358 107 80 72>,
+ <1200 330 112 84 74>,
+ <1207 322 116 89 77>,
+ <1228 311 97 76 68>,
+ <1261 309 94 74 68>,
+ <1309 312 94 74 68>,
+ <1411 320 96 76 70>,
+ <1588 337 97 78 72>,
+ <1827 364 99 79 71>,
+ <2133 397 97 75 69>,
+ <2536 438 97 74 69>,
+ <2964 476 100 76 68>,
+ <3313 509 100 74 68>,
+ <3539 520 100 76 68>,
+ <3793 536 101 76 70>,
+ <4098 558 104 78 72>,
+ <4461 581 108 82 76>,
+ <4893 605 112 84 77>,
+ <5421 626 114 82 72>,
+ <6107 646 111 79 72>,
+ <7007 676 114 80 72>,
+ <8309 727 119 82 76>,
+ <10285 857 130 89 84>,
+ <14336 1715 261 178 168>;
+ };
+};