blob: f851474fe0663db4e5448c9ed65368b844704bd8 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
Daniel Vetter618563e2012-04-01 13:38:50 +020027#include <linux/dmi.h>
Jesse Barnesc1c7af62009-09-10 15:28:03 -070028#include <linux/module.h>
29#include <linux/input.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080030#include <linux/i2c.h>
Shaohua Li7662c8b2009-06-26 11:23:55 +080031#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Jesse Barnes9cce37f2010-08-13 15:11:26 -070033#include <linux/vgaarb.h>
Wu Fengguange0dac652011-09-05 14:25:34 +080034#include <drm/drm_edid.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080035#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
Jesse Barnese5510fa2010-07-01 16:48:37 -070039#include "i915_trace.h"
Dave Airlieab2c0672009-12-04 10:55:24 +100040#include "drm_dp_helper.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080041#include "drm_crtc_helper.h"
Keith Packardc0f372b32011-11-16 22:24:52 -080042#include <linux/dma_remapping.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080043
Zhenyu Wang32f9d652009-07-24 01:00:32 +080044#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
Akshay Joshi0206e352011-08-16 15:34:10 -040046bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
Daniel Vetter3dec0092010-08-20 21:40:52 +020047static void intel_increase_pllclock(struct drm_crtc *crtc);
Chris Wilson6b383a72010-09-13 13:54:26 +010048static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
Jesse Barnes79e53942008-11-07 14:24:08 -080049
50typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040051 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
Jesse Barnes79e53942008-11-07 14:24:08 -080060} intel_clock_t;
61
62typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040063 int min, max;
Jesse Barnes79e53942008-11-07 14:24:08 -080064} intel_range_t;
65
66typedef struct {
Akshay Joshi0206e352011-08-16 15:34:10 -040067 int dot_limit;
68 int p2_slow, p2_fast;
Jesse Barnes79e53942008-11-07 14:24:08 -080069} intel_p2_t;
70
71#define INTEL_P2_NUM 2
Ma Lingd4906092009-03-18 20:13:27 +080072typedef struct intel_limit intel_limit_t;
73struct intel_limit {
Akshay Joshi0206e352011-08-16 15:34:10 -040074 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
Sean Paulcec2f352012-01-10 15:09:36 -080077 int, int, intel_clock_t *, intel_clock_t *);
Ma Lingd4906092009-03-18 20:13:27 +080078};
Jesse Barnes79e53942008-11-07 14:24:08 -080079
Jesse Barnes2377b742010-07-07 14:06:43 -070080/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
Ma Lingd4906092009-03-18 20:13:27 +080083static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080085 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
Ma Lingd4906092009-03-18 20:13:27 +080087static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080089 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
Jesse Barnes79e53942008-11-07 14:24:08 -080091
Keith Packarda4fc5ed2009-04-07 16:16:42 -070092static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080094 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +080096static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -050097intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -080098 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700100
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
Chris Wilson021357a2010-09-07 20:54:59 +0100106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
Chris Wilson8b99e682010-10-13 09:59:17 +0100109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
Chris Wilson021357a2010-09-07 20:54:59 +0100114}
115
Keith Packarde4b36692009-06-05 19:22:17 -0700116static const intel_limit_t intel_limits_i8xx_dvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
Ma Lingd4906092009-03-18 20:13:27 +0800127 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800141 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700142};
Eric Anholt273e27c2011-03-30 13:01:10 -0700143
Keith Packarde4b36692009-06-05 19:22:17 -0700144static const intel_limit_t intel_limits_i9xx_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800155 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
Ma Lingd4906092009-03-18 20:13:27 +0800169 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700170};
171
Eric Anholt273e27c2011-03-30 13:01:10 -0700172
Keith Packarde4b36692009-06-05 19:22:17 -0700173static const intel_limit_t intel_limits_g4x_sdvo = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
Ma Ling044c7c42009-03-18 20:13:23 +0800185 },
Ma Lingd4906092009-03-18 20:13:27 +0800186 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
Ma Lingd4906092009-03-18 20:13:27 +0800200 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
Ma Ling044c7c42009-03-18 20:13:23 +0800214 },
Ma Lingd4906092009-03-18 20:13:27 +0800215 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
Ma Ling044c7c42009-03-18 20:13:23 +0800229 },
Ma Lingd4906092009-03-18 20:13:27 +0800230 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
Eric Anholt273e27c2011-03-30 13:01:10 -0700243 .p2_slow = 10, .p2_fast = 10 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400244 .find_pll = intel_find_pll_g4x_dp,
Keith Packarde4b36692009-06-05 19:22:17 -0700245};
246
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500247static const intel_limit_t intel_limits_pineview_sdvo = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700250 /* Pineview's Ncounter is a ring counter */
Akshay Joshi0206e352011-08-16 15:34:10 -0400251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700253 /* Pineview only has one combined m divider, which we treat as m2. */
Akshay Joshi0206e352011-08-16 15:34:10 -0400254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
Shaohua Li61157072009-04-03 15:24:43 +0800260 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700261};
262
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500263static const intel_limit_t intel_limits_pineview_lvds = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
Shaohua Li61157072009-04-03 15:24:43 +0800274 .find_pll = intel_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700275};
276
Eric Anholt273e27c2011-03-30 13:01:10 -0700277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800282static const intel_limit_t intel_limits_ironlake_dac = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
Zhao Yakui45476682009-12-31 16:06:04 +0800293 .find_pll = intel_g4x_find_best_PLL,
Keith Packarde4b36692009-06-05 19:22:17 -0700294};
295
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800296static const intel_limit_t intel_limits_ironlake_single_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800321 .find_pll = intel_g4x_find_best_PLL,
322};
323
Eric Anholt273e27c2011-03-30 13:01:10 -0700324/* LVDS 100mhz refclk limits. */
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400333 .p1 = { .min = 2, .max = 8 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
Eric Anholt273e27c2011-03-30 13:01:10 -0700340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400347 .p1 = { .min = 2, .max = 6 },
Eric Anholt273e27c2011-03-30 13:01:10 -0700348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
Zhao Yakui45476682009-12-31 16:06:04 +0800350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
Akshay Joshi0206e352011-08-16 15:34:10 -0400354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
Eric Anholt273e27c2011-03-30 13:01:10 -0700363 .p2_slow = 10, .p2_fast = 10 },
Akshay Joshi0206e352011-08-16 15:34:10 -0400364 .find_pll = intel_find_pll_ironlake_dp,
Jesse Barnes79e53942008-11-07 14:24:08 -0800365};
366
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
Jesse Barnes57f350b2012-03-28 13:39:25 -0700409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
Jesse Barnes57f350b2012-03-28 13:39:25 -0700456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
Daniel Vetter618563e2012-04-01 13:38:50 +0200467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
Takashi Iwaib0354382012-03-20 13:07:05 +0100485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
Takashi Iwai121d5272012-03-20 13:07:06 +0100490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
Daniel Vetter618563e2012-04-01 13:38:50 +0200494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
Takashi Iwaib0354382012-03-20 13:07:05 +0100497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
Seth Forshee14d94a32012-06-13 13:46:58 -0500506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
Takashi Iwaib0354382012-03-20 13:07:05 +0100507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
Chris Wilson1b894b52010-12-14 20:04:54 +0000513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
Zhenyu Wang2c072452009-06-05 15:38:42 +0800515{
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800518 const intel_limit_t *limit;
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Takashi Iwaib0354382012-03-20 13:07:05 +0100521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800522 /* LVDS dual channel */
Chris Wilson1b894b52010-12-14 20:04:54 +0000523 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
Chris Wilson1b894b52010-12-14 20:04:54 +0000528 if (refclk == 100000)
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
Zhao Yakui45476682009-12-31 16:06:04 +0800534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800536 else
Zhenyu Wangb91ad0e2010-02-05 09:14:17 +0800537 limit = &intel_limits_ironlake_dac;
Zhenyu Wang2c072452009-06-05 15:38:42 +0800538
539 return limit;
540}
541
Ma Ling044c7c42009-03-18 20:13:23 +0800542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Takashi Iwaib0354382012-03-20 13:07:05 +0100549 if (is_dual_link_lvds(dev_priv, LVDS))
Ma Ling044c7c42009-03-18 20:13:23 +0800550 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700551 limit = &intel_limits_g4x_dual_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800552 else
553 /* LVDS with dual channel */
Keith Packarde4b36692009-06-05 19:22:17 -0700554 limit = &intel_limits_g4x_single_channel_lvds;
Ma Ling044c7c42009-03-18 20:13:23 +0800555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700557 limit = &intel_limits_g4x_hdmi;
Ma Ling044c7c42009-03-18 20:13:23 +0800558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700559 limit = &intel_limits_g4x_sdvo;
Akshay Joshi0206e352011-08-16 15:34:10 -0400560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
Keith Packarde4b36692009-06-05 19:22:17 -0700561 limit = &intel_limits_g4x_display_port;
Ma Ling044c7c42009-03-18 20:13:23 +0800562 } else /* The option is for other outputs */
Keith Packarde4b36692009-06-05 19:22:17 -0700563 limit = &intel_limits_i9xx_sdvo;
Ma Ling044c7c42009-03-18 20:13:23 +0800564
565 return limit;
566}
567
Chris Wilson1b894b52010-12-14 20:04:54 +0000568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
Jesse Barnes79e53942008-11-07 14:24:08 -0800569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
Eric Anholtbad720f2009-10-22 16:11:14 -0700573 if (HAS_PCH_SPLIT(dev))
Chris Wilson1b894b52010-12-14 20:04:54 +0000574 limit = intel_ironlake_limit(crtc, refclk);
Zhenyu Wang2c072452009-06-05 15:38:42 +0800575 else if (IS_G4X(dev)) {
Ma Ling044c7c42009-03-18 20:13:23 +0800576 limit = intel_g4x_limit(crtc);
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500577 } else if (IS_PINEVIEW(dev)) {
Shaohua Li21778322009-02-23 15:19:16 +0800578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500579 limit = &intel_limits_pineview_lvds;
Shaohua Li21778322009-02-23 15:19:16 +0800580 else
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500581 limit = &intel_limits_pineview_sdvo;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
Chris Wilsona6c45cf2010-09-17 00:32:17 +0100589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
Keith Packarde4b36692009-06-05 19:22:17 -0700596 limit = &intel_limits_i8xx_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -0800597 else
Keith Packarde4b36692009-06-05 19:22:17 -0700598 limit = &intel_limits_i8xx_dvo;
Jesse Barnes79e53942008-11-07 14:24:08 -0800599 }
600 return limit;
601}
602
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800605{
Shaohua Li21778322009-02-23 15:19:16 +0800606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
Shaohua Li21778322009-02-23 15:19:16 +0800616 return;
617 }
Jesse Barnes79e53942008-11-07 14:24:08 -0800618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
Jesse Barnes79e53942008-11-07 14:24:08 -0800624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
Chris Wilson4ef69c72010-09-09 15:14:28 +0100627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
Jesse Barnes79e53942008-11-07 14:24:08 -0800628{
Chris Wilson4ef69c72010-09-09 15:14:28 +0100629 struct drm_device *dev = crtc->dev;
Chris Wilson4ef69c72010-09-09 15:14:28 +0100630 struct intel_encoder *encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -0800631
Daniel Vetter6c2b7c122012-07-05 09:50:24 +0200632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
Chris Wilson4ef69c72010-09-09 15:14:28 +0100634 return true;
635
636 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -0800637}
638
Jesse Barnes7c04d1d2009-02-23 15:36:40 -0800639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
Jesse Barnes79e53942008-11-07 14:24:08 -0800640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
Chris Wilson1b894b52010-12-14 20:04:54 +0000645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
Jesse Barnes79e53942008-11-07 14:24:08 -0800648{
Jesse Barnes79e53942008-11-07 14:24:08 -0800649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400650 INTELPllInvalid("p1 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800651 if (clock->p < limit->p.min || limit->p.max < clock->p)
Akshay Joshi0206e352011-08-16 15:34:10 -0400652 INTELPllInvalid("p out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
Akshay Joshi0206e352011-08-16 15:34:10 -0400654 INTELPllInvalid("m2 out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
Akshay Joshi0206e352011-08-16 15:34:10 -0400656 INTELPllInvalid("m1 out of range\n");
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
Akshay Joshi0206e352011-08-16 15:34:10 -0400658 INTELPllInvalid("m1 <= m2\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800659 if (clock->m < limit->m.min || limit->m.max < clock->m)
Akshay Joshi0206e352011-08-16 15:34:10 -0400660 INTELPllInvalid("m out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800661 if (clock->n < limit->n.min || limit->n.max < clock->n)
Akshay Joshi0206e352011-08-16 15:34:10 -0400662 INTELPllInvalid("n out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
Akshay Joshi0206e352011-08-16 15:34:10 -0400664 INTELPllInvalid("vco out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
Akshay Joshi0206e352011-08-16 15:34:10 -0400669 INTELPllInvalid("dot out of range\n");
Jesse Barnes79e53942008-11-07 14:24:08 -0800670
671 return true;
672}
673
Ma Lingd4906092009-03-18 20:13:27 +0800674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800678
Jesse Barnes79e53942008-11-07 14:24:08 -0800679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
Jesse Barnes79e53942008-11-07 14:24:08 -0800683 int err = target;
684
Bruno Prémontbc5e5712009-08-08 13:01:17 +0200685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Florian Mickler832cc282009-07-13 18:40:32 +0800686 (I915_READ(LVDS)) != 0) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
Takashi Iwaib0354382012-03-20 13:07:05 +0100693 if (is_dual_link_lvds(dev_priv, LVDS))
Jesse Barnes79e53942008-11-07 14:24:08 -0800694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
Akshay Joshi0206e352011-08-16 15:34:10 -0400704 memset(best_clock, 0, sizeof(*best_clock));
Jesse Barnes79e53942008-11-07 14:24:08 -0800705
Zhao Yakui42158662009-11-20 11:24:18 +0800706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
Zhao Yakui42158662009-11-20 11:24:18 +0800712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
Jesse Barnes79e53942008-11-07 14:24:08 -0800717 int this_err;
718
Shaohua Li21778322009-02-23 15:19:16 +0800719 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
Jesse Barnes79e53942008-11-07 14:24:08 -0800722 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
Jesse Barnes79e53942008-11-07 14:24:08 -0800726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
Ma Lingd4906092009-03-18 20:13:27 +0800740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
Ma Lingd4906092009-03-18 20:13:27 +0800744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
Adam Jackson6ba770d2010-07-02 16:43:30 -0400750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
Ma Lingd4906092009-03-18 20:13:27 +0800752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
Zhao Yakui45476682009-12-31 16:06:04 +0800755 int lvds_reg;
756
Eric Anholtc619eed2010-01-28 16:45:52 -0800757 if (HAS_PCH_SPLIT(dev))
Zhao Yakui45476682009-12-31 16:06:04 +0800758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
Ma Lingd4906092009-03-18 20:13:27 +0800762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200775 /* based on hardware requirement, prefer smaller n to precision */
Ma Lingd4906092009-03-18 20:13:27 +0800776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
Gilles Espinassef77f13e2010-03-29 15:41:47 +0200777 /* based on hardware requirement, prefere larger m1,m2 */
Ma Lingd4906092009-03-18 20:13:27 +0800778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
Shaohua Li21778322009-02-23 15:19:16 +0800786 intel_clock(dev, refclk, &clock);
Chris Wilson1b894b52010-12-14 20:04:54 +0000787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
Ma Lingd4906092009-03-18 20:13:27 +0800789 continue;
Sean Paulcec2f352012-01-10 15:09:36 -0800790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
Chris Wilson1b894b52010-12-14 20:04:54 +0000793
794 this_err = abs(clock.dot - target);
Ma Lingd4906092009-03-18 20:13:27 +0800795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
Zhenyu Wang2c072452009-06-05 15:38:42 +0800805 return found;
806}
Ma Lingd4906092009-03-18 20:13:27 +0800807
Zhenyu Wang2c072452009-06-05 15:38:42 +0800808static bool
Adam Jacksonf2b115e2009-12-03 17:14:42 -0500809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
Zhao Yakui45476682009-12-31 16:06:04 +0800815
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
Sean Paulcec2f352012-01-10 15:09:36 -0800837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700839{
Chris Wilson5eddb702010-09-11 13:48:45 +0100840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700860}
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
Alan Coxaf447bd2012-07-25 13:49:18 +0100872 flag = 0;
Jesse Barnesa0c4da22012-06-15 11:55:13 -0700873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700929
Paulo Zanonia928d532012-05-04 17:18:15 -0300930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -0800950{
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700951 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800952 int pipestat_reg = PIPESTAT(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700953
Paulo Zanonia928d532012-05-04 17:18:15 -0300954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
Chris Wilson300387c2010-09-05 20:25:43 +0100959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700975 /* Wait for vblank interrupt bit to set */
Chris Wilson481b6af2010-08-23 17:43:35 +0100976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
Keith Packardab7ad7f2010-10-03 00:33:06 -0700982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
Keith Packardab7ad7f2010-10-03 00:33:06 -0700991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
Chris Wilson58e10eb2010-10-03 10:56:11 +0100997 *
Jesse Barnes9d0498a2010-08-18 13:20:54 -0700998 */
Chris Wilson58e10eb2010-10-03 10:56:11 +0100999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001002
Keith Packardab7ad7f2010-10-03 00:33:06 -07001003 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson58e10eb2010-10-03 10:56:11 +01001004 int reg = PIPECONF(pipe);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07001005
Keith Packardab7ad7f2010-10-03 00:33:06 -07001006 /* Wait for the Pipe State to go off */
Chris Wilson58e10eb2010-10-03 10:56:11 +01001007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
Keith Packardab7ad7f2010-10-03 00:33:06 -07001009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010 } else {
Paulo Zanoni837ba002012-05-04 17:18:14 -03001011 u32 last_line, line_mask;
Chris Wilson58e10eb2010-10-03 10:56:11 +01001012 int reg = PIPEDSL(pipe);
Keith Packardab7ad7f2010-10-03 00:33:06 -07001013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
Paulo Zanoni837ba002012-05-04 17:18:14 -03001015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
Keith Packardab7ad7f2010-10-03 00:33:06 -07001020 /* Wait for the display line to settle */
1021 do {
Paulo Zanoni837ba002012-05-04 17:18:14 -03001022 last_line = I915_READ(reg) & line_mask;
Keith Packardab7ad7f2010-10-03 00:33:06 -07001023 mdelay(5);
Paulo Zanoni837ba002012-05-04 17:18:14 -03001024 } while (((I915_READ(reg) & line_mask) != last_line) &&
Keith Packardab7ad7f2010-10-03 00:33:06 -07001025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028 }
Jesse Barnes79e53942008-11-07 14:24:08 -08001029}
1030
Jesse Barnesb24e7172011-01-04 15:09:30 -08001031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
Jesse Barnes040484a2011-01-03 12:14:26 -08001054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
Chris Wilson92b27b02012-05-20 18:10:50 +01001056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
Jesse Barnes040484a2011-01-03 12:14:26 -08001059{
Jesse Barnes040484a2011-01-03 12:14:26 -08001060 u32 val;
1061 bool cur_state;
1062
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
Chris Wilson92b27b02012-05-20 18:10:50 +01001068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001070 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001071
Chris Wilson92b27b02012-05-20 18:10:50 +01001072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
Jesse Barnesd3ccbe82011-10-12 09:27:42 -07001080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
Chris Wilson92b27b02012-05-20 18:10:50 +01001083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
Jesse Barnesd3ccbe82011-10-12 09:27:42 -07001095 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001096}
Chris Wilson92b27b02012-05-20 18:10:50 +01001097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
Jesse Barnes040484a2011-01-03 12:14:26 -08001099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03001156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
Jesse Barnes040484a2011-01-03 12:14:26 -08001160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
Jesse Barnesea0760c2011-01-04 15:09:32 -08001180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
Thomas Jarosch0de3b482011-08-25 15:37:45 +02001186 bool locked = true;
Jesse Barnesea0760c2011-01-04 15:09:32 -08001187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001206 pipe_name(pipe));
Jesse Barnesea0760c2011-01-04 15:09:32 -08001207}
1208
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001211{
1212 int reg;
1213 u32 val;
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001214 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001215
Daniel Vetter8e636782012-01-22 01:36:48 +01001216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
Jesse Barnesb24e7172011-01-04 15:09:30 -08001220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001225 pipe_name(pipe), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001226}
1227
Chris Wilson931872f2012-01-16 23:01:13 +00001228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001230{
1231 int reg;
1232 u32 val;
Chris Wilson931872f2012-01-16 23:01:13 +00001233 bool cur_state;
Jesse Barnesb24e7172011-01-04 15:09:30 -08001234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
Chris Wilson931872f2012-01-16 23:01:13 +00001237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001241}
1242
Chris Wilson931872f2012-01-16 23:01:13 +00001243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
Jesse Barnesb24e7172011-01-04 15:09:30 -08001246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
Jesse Barnes19ec1352011-02-02 12:28:02 -08001253 /* Planes are fixed to pipes on ILK+ */
Adam Jackson28c057942011-10-07 14:38:42 -04001254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
Jesse Barnes19ec1352011-02-02 12:28:02 -08001260 return;
Adam Jackson28c057942011-10-07 14:38:42 -04001261 }
Jesse Barnes19ec1352011-02-02 12:28:02 -08001262
Jesse Barnesb24e7172011-01-04 15:09:30 -08001263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
Jesse Barnesb24e7172011-01-04 15:09:30 -08001272 }
1273}
1274
Jesse Barnes92f25842011-01-04 15:09:34 -08001275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03001280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
Jesse Barnes92f25842011-01-04 15:09:34 -08001285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
Jesse Barnes92f25842011-01-04 15:09:34 -08001304}
1305
Keith Packard4e634382011-08-06 10:39:45 -07001306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
Keith Packardf0575e92011-07-25 22:12:43 -07001308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
Keith Packard1519b992011-08-06 10:35:34 -07001324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
Jesse Barnes291906f2011-02-02 12:28:03 -08001371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001372 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes291906f2011-02-02 12:28:03 -08001373{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001374 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001377 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001381}
1382
1383static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385{
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001386 u32 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
Adam Jackson23c99e72011-10-07 14:38:43 -04001388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001389 reg, pipe_name(pipe));
Daniel Vetterde9a35a2012-06-05 11:03:40 +02001390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
Jesse Barnes291906f2011-02-02 12:28:03 -08001393}
1394
1395static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
1398 int reg;
1399 u32 val;
Jesse Barnes291906f2011-02-02 12:28:03 -08001400
Keith Packardf0575e92011-07-25 22:12:43 -07001401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes291906f2011-02-02 12:28:03 -08001404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001408 "PCH VGA enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001409 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
Jesse Barnes291906f2011-02-02 12:28:03 -08001414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001415 pipe_name(pipe));
Jesse Barnes291906f2011-02-02 12:28:03 -08001416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420}
1421
Jesse Barnesb24e7172011-01-04 15:09:30 -08001422/**
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
Thomas Richter7434a252012-07-18 19:22:30 +02001432 *
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001434 */
Daniel Vettera37b9b32012-08-12 19:27:09 +02001435static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001436{
1437 int reg;
1438 u32 val;
1439
1440 /* No really, not for ILK+ */
Jesse Barnesa0c4da22012-06-15 11:55:13 -07001441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001442
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1456 POSTING_READ(reg);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1459 POSTING_READ(reg);
1460 udelay(150); /* wait for warmup */
1461}
1462
1463/**
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1467 *
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 *
1470 * Note! This is for pre-ILK only.
1471 */
1472static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479 return;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1488 POSTING_READ(reg);
1489}
1490
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001491/* SBI access */
1492static void
1493intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494{
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 goto out_unlock;
1502 }
1503
1504 I915_WRITE(SBI_ADDR,
1505 (reg << 16));
1506 I915_WRITE(SBI_DATA,
1507 value);
1508 I915_WRITE(SBI_CTL_STAT,
1509 SBI_BUSY |
1510 SBI_CTL_OP_CRWR);
1511
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001513 100)) {
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515 goto out_unlock;
1516 }
1517
1518out_unlock:
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520}
1521
1522static u32
1523intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524{
1525 unsigned long flags;
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001526 u32 value = 0;
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001527
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001530 100)) {
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 goto out_unlock;
1533 }
1534
1535 I915_WRITE(SBI_ADDR,
1536 (reg << 16));
1537 I915_WRITE(SBI_CTL_STAT,
1538 SBI_BUSY |
1539 SBI_CTL_OP_CRRD);
1540
Eugeni Dodonov39fb50f2012-06-08 16:43:19 -03001541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
Eugeni Dodonova416ede2012-05-09 15:37:10 -03001542 100)) {
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 goto out_unlock;
1545 }
1546
1547 value = I915_READ(SBI_DATA);
1548
1549out_unlock:
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551 return value;
1552}
1553
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08001554/**
Jesse Barnes92f25842011-01-04 15:09:34 -08001555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1558 *
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1561 */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001562static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001563{
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
Chris Wilson48da64a2012-05-13 20:16:12 +01001565 struct intel_pch_pll *pll;
Jesse Barnes92f25842011-01-04 15:09:34 -08001566 int reg;
1567 u32 val;
1568
Chris Wilson48da64a2012-05-13 20:16:12 +01001569 /* PCH PLLs only available on ILK, SNB and IVB */
Jesse Barnes92f25842011-01-04 15:09:34 -08001570 BUG_ON(dev_priv->info->gen < 5);
Chris Wilson48da64a2012-05-13 20:16:12 +01001571 pll = intel_crtc->pch_pll;
1572 if (pll == NULL)
1573 return;
1574
1575 if (WARN_ON(pll->refcount == 0))
1576 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001577
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
Jesse Barnes92f25842011-01-04 15:09:34 -08001581
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1584
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001585 if (pll->active++ && pll->on) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001586 assert_pch_pll_enabled(dev_priv, pll, NULL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001587 return;
1588 }
1589
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592 reg = pll->pll_reg;
Jesse Barnes92f25842011-01-04 15:09:34 -08001593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1596 POSTING_READ(reg);
1597 udelay(200);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001598
1599 pll->on = true;
Jesse Barnes92f25842011-01-04 15:09:34 -08001600}
1601
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001602static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
Jesse Barnes92f25842011-01-04 15:09:34 -08001603{
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
Jesse Barnes92f25842011-01-04 15:09:34 -08001606 int reg;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001607 u32 val;
Jesse Barnes4c609cb2011-09-02 12:52:11 -07001608
Jesse Barnes92f25842011-01-04 15:09:34 -08001609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001611 if (pll == NULL)
1612 return;
1613
Chris Wilson48da64a2012-05-13 20:16:12 +01001614 if (WARN_ON(pll->refcount == 0))
1615 return;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001616
1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
1620
Chris Wilson48da64a2012-05-13 20:16:12 +01001621 if (WARN_ON(pll->active == 0)) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001622 assert_pch_pll_disabled(dev_priv, pll, NULL);
Chris Wilson48da64a2012-05-13 20:16:12 +01001623 return;
1624 }
1625
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001626 if (--pll->active) {
Chris Wilson92b27b02012-05-20 18:10:50 +01001627 assert_pch_pll_enabled(dev_priv, pll, NULL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001628 return;
1629 }
1630
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
Jesse Barnes92f25842011-01-04 15:09:34 -08001632
1633 /* Make sure transcoder isn't still depending on us */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
Jesse Barnes92f25842011-01-04 15:09:34 -08001635
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001636 reg = pll->pll_reg;
Jesse Barnes92f25842011-01-04 15:09:34 -08001637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1640 POSTING_READ(reg);
1641 udelay(200);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01001642
1643 pll->on = false;
Jesse Barnes92f25842011-01-04 15:09:34 -08001644}
1645
Jesse Barnes040484a2011-01-03 12:14:26 -08001646static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647 enum pipe pipe)
1648{
1649 int reg;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001650 u32 val, pipeconf_val;
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
Jesse Barnes040484a2011-01-03 12:14:26 -08001652
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1655
1656 /* Make sure PCH DPLL is enabled */
Chris Wilson92b27b02012-05-20 18:10:50 +01001657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
Jesse Barnes040484a2011-01-03 12:14:26 -08001660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1664
Eugeni Dodonov59c859d2012-05-09 15:37:19 -03001665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 return;
1668 }
Jesse Barnes040484a2011-01-03 12:14:26 -08001669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001671 pipeconf_val = I915_READ(PIPECONF(pipe));
Jesse Barnese9bcff52011-06-24 12:19:20 -07001672
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1674 /*
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1677 */
1678 val &= ~PIPE_BPC_MASK;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001679 val |= pipeconf_val & PIPE_BPC_MASK;
Jesse Barnese9bcff52011-06-24 12:19:20 -07001680 }
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001681
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
Paulo Zanoni7c26e5c2012-02-14 17:07:09 -02001684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1687 else
1688 val |= TRANS_INTERLACED;
Paulo Zanoni5f7f7262012-02-03 17:47:15 -02001689 else
1690 val |= TRANS_PROGRESSIVE;
1691
Jesse Barnes040484a2011-01-03 12:14:26 -08001692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695}
1696
1697static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698 enum pipe pipe)
1699{
1700 int reg;
1701 u32 val;
1702
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1706
Jesse Barnes291906f2011-02-02 12:28:03 -08001707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1709
Jesse Barnes040484a2011-01-03 12:14:26 -08001710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
Jesse Barnes4c9c18c2011-10-13 09:46:32 -07001716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001717}
1718
Jesse Barnes92f25842011-01-04 15:09:34 -08001719/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001720 * intel_enable_pipe - enable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
Jesse Barnes040484a2011-01-03 12:14:26 -08001723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
Jesse Barnesb24e7172011-01-04 15:09:30 -08001724 *
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 * returning.
1732 */
Jesse Barnes040484a2011-01-03 12:14:26 -08001733static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734 bool pch_port)
Jesse Barnesb24e7172011-01-04 15:09:30 -08001735{
1736 int reg;
1737 u32 val;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08001746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751 }
1752 /* FIXME: assert CPU port conditions for SNB+ */
1753 }
Jesse Barnesb24e7172011-01-04 15:09:30 -08001754
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001757 if (val & PIPECONF_ENABLE)
1758 return;
1759
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001761 intel_wait_for_vblank(dev_priv->dev, pipe);
1762}
1763
1764/**
Chris Wilson309cfea2011-01-28 13:54:53 +00001765 * intel_disable_pipe - disable a pipe, asserting requirements
Jesse Barnesb24e7172011-01-04 15:09:30 -08001766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1768 *
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771 *
1772 * @pipe should be %PIPE_A or %PIPE_B.
1773 *
1774 * Will wait until the pipe has shut down before returning.
1775 */
1776static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777 enum pipe pipe)
1778{
1779 int reg;
1780 u32 val;
1781
1782 /*
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1785 */
1786 assert_planes_disabled(dev_priv, pipe);
1787
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790 return;
1791
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001794 if ((val & PIPECONF_ENABLE) == 0)
1795 return;
1796
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799}
1800
Keith Packardd74362c2011-07-28 14:47:14 -07001801/*
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1804 */
Eugeni Dodonov6f1d69b2012-04-18 15:29:25 -03001805void intel_flush_display_plane(struct drm_i915_private *dev_priv,
Keith Packardd74362c2011-07-28 14:47:14 -07001806 enum plane plane)
1807{
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810}
1811
Jesse Barnesb24e7172011-01-04 15:09:30 -08001812/**
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1817 *
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1819 */
1820static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1822{
1823 int reg;
1824 u32 val;
1825
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1828
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001831 if (val & DISPLAY_PLANE_ENABLE)
1832 return;
1833
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
Keith Packardd74362c2011-07-28 14:47:14 -07001835 intel_flush_display_plane(dev_priv, plane);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001836 intel_wait_for_vblank(dev_priv->dev, pipe);
1837}
1838
Jesse Barnesb24e7172011-01-04 15:09:30 -08001839/**
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1844 *
1845 * Disable @plane; should be an independent operation.
1846 */
1847static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1849{
1850 int reg;
1851 u32 val;
1852
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
Chris Wilson00d70b12011-03-17 07:18:29 +00001855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
Jesse Barnesb24e7172011-01-04 15:09:30 -08001859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1861}
1862
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001863static void disable_pch_dp(struct drm_i915_private *dev_priv,
Keith Packardf0575e92011-07-25 22:12:43 -07001864 enum pipe pipe, int reg, u32 port_sel)
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001865{
1866 u32 val = I915_READ(reg);
Keith Packard4e634382011-08-06 10:39:45 -07001867 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
Keith Packardf0575e92011-07-25 22:12:43 -07001868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001869 I915_WRITE(reg, val & ~DP_PORT_EN);
Keith Packardf0575e92011-07-25 22:12:43 -07001870 }
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001871}
1872
1873static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874 enum pipe pipe, int reg)
1875{
1876 u32 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
Keith Packardf0575e92011-07-25 22:12:43 -07001878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879 reg, pipe);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001880 I915_WRITE(reg, val & ~PORT_ENABLE);
Keith Packardf0575e92011-07-25 22:12:43 -07001881 }
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001882}
1883
1884/* Disable any ports connected to this transcoder */
1885static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887{
1888 u32 reg, val;
1889
1890 val = I915_READ(PCH_PP_CONTROL);
1891 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
Keith Packardf0575e92011-07-25 22:12:43 -07001893 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001896
1897 reg = PCH_ADPA;
1898 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001899 if (adpa_pipe_enabled(dev_priv, pipe, val))
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902 reg = PCH_LVDS;
1903 val = I915_READ(reg);
Xu, Anhuae9a851e2012-08-13 03:08:33 +00001904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
Keith Packard1519b992011-08-06 10:35:34 -07001905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
Jesse Barnes47a05ec2011-02-07 13:46:40 -08001906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907 POSTING_READ(reg);
1908 udelay(100);
1909 }
1910
1911 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913 disable_pch_hdmi(dev_priv, pipe, HDMID);
1914}
1915
Chris Wilson127bd2a2010-07-23 23:32:05 +01001916int
Chris Wilson48b956c2010-09-14 12:50:34 +01001917intel_pin_and_fence_fb_obj(struct drm_device *dev,
Chris Wilson05394f32010-11-08 19:18:58 +00001918 struct drm_i915_gem_object *obj,
Chris Wilson919926a2010-11-12 13:42:53 +00001919 struct intel_ring_buffer *pipelined)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001920{
Chris Wilsonce453d82011-02-21 14:43:56 +00001921 struct drm_i915_private *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001922 u32 alignment;
1923 int ret;
1924
Chris Wilson05394f32010-11-08 19:18:58 +00001925 switch (obj->tiling_mode) {
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001926 case I915_TILING_NONE:
Chris Wilson534843d2010-07-05 18:01:46 +01001927 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928 alignment = 128 * 1024;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001929 else if (INTEL_INFO(dev)->gen >= 4)
Chris Wilson534843d2010-07-05 18:01:46 +01001930 alignment = 4 * 1024;
1931 else
1932 alignment = 64 * 1024;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001933 break;
1934 case I915_TILING_X:
1935 /* pin() will align the object as required by fence */
1936 alignment = 0;
1937 break;
1938 case I915_TILING_Y:
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941 return -EINVAL;
1942 default:
1943 BUG();
1944 }
1945
Chris Wilsonce453d82011-02-21 14:43:56 +00001946 dev_priv->mm.interruptible = false;
Chris Wilson2da3b9b2011-04-14 09:41:17 +01001947 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
Chris Wilson48b956c2010-09-14 12:50:34 +01001948 if (ret)
Chris Wilsonce453d82011-02-21 14:43:56 +00001949 goto err_interruptible;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001950
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1955 */
Chris Wilson06d98132012-04-17 15:31:24 +01001956 ret = i915_gem_object_get_fence(obj);
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001957 if (ret)
1958 goto err_unpin;
Chris Wilson1690e1e2011-12-14 13:57:08 +01001959
Chris Wilson9a5a53b2012-03-22 15:10:00 +00001960 i915_gem_object_pin_fence(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001961
Chris Wilsonce453d82011-02-21 14:43:56 +00001962 dev_priv->mm.interruptible = true;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001963 return 0;
Chris Wilson48b956c2010-09-14 12:50:34 +01001964
1965err_unpin:
1966 i915_gem_object_unpin(obj);
Chris Wilsonce453d82011-02-21 14:43:56 +00001967err_interruptible:
1968 dev_priv->mm.interruptible = true;
Chris Wilson48b956c2010-09-14 12:50:34 +01001969 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05001970}
1971
Chris Wilson1690e1e2011-12-14 13:57:08 +01001972void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973{
1974 i915_gem_object_unpin_fence(obj);
1975 i915_gem_object_unpin(obj);
1976}
1977
Daniel Vetterc2c75132012-07-05 12:17:30 +02001978/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981 unsigned int bpp,
1982 unsigned int pitch)
1983{
1984 int tile_rows, tiles;
1985
1986 tile_rows = *y / 8;
1987 *y %= 8;
1988 tiles = *x / (512/bpp);
1989 *x %= 512/bpp;
1990
1991 return tile_rows * pitch * 8 + tiles * 4096;
1992}
1993
Jesse Barnes17638cd2011-06-24 12:19:23 -07001994static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995 int x, int y)
Jesse Barnes81255562010-08-02 12:07:50 -07001996{
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00002001 struct drm_i915_gem_object *obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002002 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002003 unsigned long linear_offset;
Jesse Barnes81255562010-08-02 12:07:50 -07002004 u32 dspcntr;
Chris Wilson5eddb702010-09-11 13:48:45 +01002005 u32 reg;
Jesse Barnes81255562010-08-02 12:07:50 -07002006
2007 switch (plane) {
2008 case 0:
2009 case 1:
2010 break;
2011 default:
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
Jesse Barnes81255562010-08-02 12:07:50 -07002018
Chris Wilson5eddb702010-09-11 13:48:45 +01002019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023 switch (fb->bits_per_pixel) {
2024 case 8:
2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
2027 case 16:
2028 if (fb->depth == 15)
2029 dspcntr |= DISPPLANE_15_16BPP;
2030 else
2031 dspcntr |= DISPPLANE_16BPP;
2032 break;
2033 case 24:
2034 case 32:
2035 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036 break;
2037 default:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002038 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
Jesse Barnes81255562010-08-02 12:07:50 -07002039 return -EINVAL;
2040 }
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002041 if (INTEL_INFO(dev)->gen >= 4) {
Chris Wilson05394f32010-11-08 19:18:58 +00002042 if (obj->tiling_mode != I915_TILING_NONE)
Jesse Barnes81255562010-08-02 12:07:50 -07002043 dspcntr |= DISPPLANE_TILED;
2044 else
2045 dspcntr &= ~DISPPLANE_TILED;
2046 }
2047
Chris Wilson5eddb702010-09-11 13:48:45 +01002048 I915_WRITE(reg, dspcntr);
Jesse Barnes81255562010-08-02 12:07:50 -07002049
Daniel Vettere506a0c2012-07-05 12:17:29 +02002050 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Jesse Barnes81255562010-08-02 12:07:50 -07002051
Daniel Vetterc2c75132012-07-05 12:17:30 +02002052 if (INTEL_INFO(dev)->gen >= 4) {
2053 intel_crtc->dspaddr_offset =
2054 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055 fb->bits_per_pixel / 8,
2056 fb->pitches[0]);
2057 linear_offset -= intel_crtc->dspaddr_offset;
2058 } else {
Daniel Vettere506a0c2012-07-05 12:17:29 +02002059 intel_crtc->dspaddr_offset = linear_offset;
Daniel Vetterc2c75132012-07-05 12:17:30 +02002060 }
Daniel Vettere506a0c2012-07-05 12:17:29 +02002061
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002064 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002065 if (INTEL_INFO(dev)->gen >= 4) {
Daniel Vetterc2c75132012-07-05 12:17:30 +02002066 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067 obj->gtt_offset + intel_crtc->dspaddr_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002069 I915_WRITE(DSPLINOFF(plane), linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002070 } else
Daniel Vettere506a0c2012-07-05 12:17:29 +02002071 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
Chris Wilson5eddb702010-09-11 13:48:45 +01002072 POSTING_READ(reg);
Jesse Barnes81255562010-08-02 12:07:50 -07002073
Jesse Barnes17638cd2011-06-24 12:19:23 -07002074 return 0;
2075}
2076
2077static int ironlake_update_plane(struct drm_crtc *crtc,
2078 struct drm_framebuffer *fb, int x, int y)
2079{
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
2084 struct drm_i915_gem_object *obj;
2085 int plane = intel_crtc->plane;
Daniel Vettere506a0c2012-07-05 12:17:29 +02002086 unsigned long linear_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002087 u32 dspcntr;
2088 u32 reg;
2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
Jesse Barnes27f82272011-09-02 12:54:37 -07002093 case 2:
Jesse Barnes17638cd2011-06-24 12:19:23 -07002094 break;
2095 default:
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097 return -EINVAL;
2098 }
2099
2100 intel_fb = to_intel_framebuffer(fb);
2101 obj = intel_fb->obj;
2102
2103 reg = DSPCNTR(plane);
2104 dspcntr = I915_READ(reg);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107 switch (fb->bits_per_pixel) {
2108 case 8:
2109 dspcntr |= DISPPLANE_8BPP;
2110 break;
2111 case 16:
2112 if (fb->depth != 16)
2113 return -EINVAL;
2114
2115 dspcntr |= DISPPLANE_16BPP;
2116 break;
2117 case 24:
2118 case 32:
2119 if (fb->depth == 24)
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 else if (fb->depth == 30)
2122 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123 else
2124 return -EINVAL;
2125 break;
2126 default:
2127 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128 return -EINVAL;
2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
2136 /* must disable */
2137 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139 I915_WRITE(reg, dspcntr);
2140
Daniel Vettere506a0c2012-07-05 12:17:29 +02002141 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002142 intel_crtc->dspaddr_offset =
2143 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144 fb->bits_per_pixel / 8,
2145 fb->pitches[0]);
2146 linear_offset -= intel_crtc->dspaddr_offset;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002147
Daniel Vettere506a0c2012-07-05 12:17:29 +02002148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02002150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02002151 I915_MODIFY_DISPBASE(DSPSURF(plane),
2152 obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
Daniel Vettere506a0c2012-07-05 12:17:29 +02002154 I915_WRITE(DSPLINOFF(plane), linear_offset);
Jesse Barnes17638cd2011-06-24 12:19:23 -07002155 POSTING_READ(reg);
2156
2157 return 0;
2158}
2159
2160/* Assume fb object is pinned & idle & fenced and just update base pointers */
2161static int
2162intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163 int x, int y, enum mode_set_atomic state)
2164{
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes17638cd2011-06-24 12:19:23 -07002167
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002168 if (dev_priv->display.disable_fbc)
2169 dev_priv->display.disable_fbc(dev);
Daniel Vetter3dec0092010-08-20 21:40:52 +02002170 intel_increase_pllclock(crtc);
Jesse Barnes81255562010-08-02 12:07:50 -07002171
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002172 return dev_priv->display.update_plane(crtc, fb, x, y);
Jesse Barnes81255562010-08-02 12:07:50 -07002173}
2174
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05002175static int
Chris Wilson14667a42012-04-03 17:58:35 +01002176intel_finish_fb(struct drm_framebuffer *old_fb)
2177{
2178 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180 bool was_interruptible = dev_priv->mm.interruptible;
2181 int ret;
2182
2183 wait_event(dev_priv->pending_flip_queue,
2184 atomic_read(&dev_priv->mm.wedged) ||
2185 atomic_read(&obj->pending_flip) == 0);
2186
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2190 * framebuffer.
2191 *
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2194 */
2195 dev_priv->mm.interruptible = false;
2196 ret = i915_gem_object_finish_gpu(obj);
2197 dev_priv->mm.interruptible = was_interruptible;
2198
2199 return ret;
2200}
2201
2202static int
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002203intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08002205{
2206 struct drm_device *dev = crtc->dev;
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002207 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08002208 struct drm_i915_master_private *master_priv;
2209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002210 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002211
2212 /* no fb bound */
2213 if (!crtc->fb) {
Jesse Barnesa5071c22011-07-19 15:38:56 -07002214 DRM_ERROR("No FB bound\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002215 return 0;
2216 }
2217
Eugeni Dodonov5826eca2012-05-09 15:37:12 -03002218 if(intel_crtc->plane > dev_priv->num_pipe) {
2219 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2220 intel_crtc->plane,
2221 dev_priv->num_pipe);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002222 return -EINVAL;
Jesse Barnes79e53942008-11-07 14:24:08 -08002223 }
2224
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002225 mutex_lock(&dev->struct_mutex);
Chris Wilson265db952010-09-20 15:41:01 +01002226 ret = intel_pin_and_fence_fb_obj(dev,
2227 to_intel_framebuffer(crtc->fb)->obj,
Chris Wilson919926a2010-11-12 13:42:53 +00002228 NULL);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002229 if (ret != 0) {
2230 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002231 DRM_ERROR("pin & fence failed\n");
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002232 return ret;
2233 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002234
Chris Wilson14667a42012-04-03 17:58:35 +01002235 if (old_fb)
2236 intel_finish_fb(old_fb);
Chris Wilson265db952010-09-20 15:41:01 +01002237
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002238 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002239 if (ret) {
Chris Wilson1690e1e2011-12-14 13:57:08 +01002240 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002241 mutex_unlock(&dev->struct_mutex);
Jesse Barnesa5071c22011-07-19 15:38:56 -07002242 DRM_ERROR("failed to update base address\n");
Chris Wilson4e6cfef2010-08-08 13:20:19 +01002243 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08002244 }
Kristian Høgsberg3c4fdcf2008-12-17 22:14:46 -05002245
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002246 if (old_fb) {
2247 intel_wait_for_vblank(dev, intel_crtc->pipe);
Chris Wilson1690e1e2011-12-14 13:57:08 +01002248 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
Chris Wilsonb7f1de22010-12-14 16:09:31 +00002249 }
Jesse Barnes652c3932009-08-17 13:31:43 -07002250
Chris Wilson6b8e6ed2012-04-17 15:08:19 +01002251 intel_update_fbc(dev);
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002252 mutex_unlock(&dev->struct_mutex);
Jesse Barnes79e53942008-11-07 14:24:08 -08002253
2254 if (!dev->primary->master)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002255 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002256
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002259 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002260
Chris Wilson265db952010-09-20 15:41:01 +01002261 if (intel_crtc->pipe) {
Jesse Barnes79e53942008-11-07 14:24:08 -08002262 master_priv->sarea_priv->pipeB_x = x;
2263 master_priv->sarea_priv->pipeB_y = y;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002264 } else {
2265 master_priv->sarea_priv->pipeA_x = x;
2266 master_priv->sarea_priv->pipeA_y = y;
Jesse Barnes79e53942008-11-07 14:24:08 -08002267 }
Chris Wilson5c3b82e2009-02-11 13:25:09 +00002268
2269 return 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08002270}
2271
Chris Wilson5eddb702010-09-11 13:48:45 +01002272static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002273{
2274 struct drm_device *dev = crtc->dev;
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276 u32 dpa_ctl;
2277
Zhao Yakui28c97732009-10-09 11:39:41 +08002278 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002279 dpa_ctl = I915_READ(DP_A);
2280 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2281
2282 if (clock < 200000) {
2283 u32 temp;
2284 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2285 /* workaround for 160Mhz:
2286 1) program 0x4600c bits 15:0 = 0x8124
2287 2) program 0x46010 bit 0 = 1
2288 3) program 0x46034 bit 24 = 1
2289 4) program 0x64000 bit 14 = 1
2290 */
2291 temp = I915_READ(0x4600c);
2292 temp &= 0xffff0000;
2293 I915_WRITE(0x4600c, temp | 0x8124);
2294
2295 temp = I915_READ(0x46010);
2296 I915_WRITE(0x46010, temp | 1);
2297
2298 temp = I915_READ(0x46034);
2299 I915_WRITE(0x46034, temp | (1 << 24));
2300 } else {
2301 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2302 }
2303 I915_WRITE(DP_A, dpa_ctl);
2304
Chris Wilson5eddb702010-09-11 13:48:45 +01002305 POSTING_READ(DP_A);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08002306 udelay(500);
2307}
2308
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002309static void intel_fdi_normal_train(struct drm_crtc *crtc)
2310{
2311 struct drm_device *dev = crtc->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314 int pipe = intel_crtc->pipe;
2315 u32 reg, temp;
2316
2317 /* enable normal train */
2318 reg = FDI_TX_CTL(pipe);
2319 temp = I915_READ(reg);
Keith Packard61e499b2011-05-17 16:13:52 -07002320 if (IS_IVYBRIDGE(dev)) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002321 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2322 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
Keith Packard61e499b2011-05-17 16:13:52 -07002323 } else {
2324 temp &= ~FDI_LINK_TRAIN_NONE;
2325 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
Jesse Barnes357555c2011-04-28 15:09:55 -07002326 }
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002327 I915_WRITE(reg, temp);
2328
2329 reg = FDI_RX_CTL(pipe);
2330 temp = I915_READ(reg);
2331 if (HAS_PCH_CPT(dev)) {
2332 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2333 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2334 } else {
2335 temp &= ~FDI_LINK_TRAIN_NONE;
2336 temp |= FDI_LINK_TRAIN_NONE;
2337 }
2338 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2339
2340 /* wait one idle pattern time */
2341 POSTING_READ(reg);
2342 udelay(1000);
Jesse Barnes357555c2011-04-28 15:09:55 -07002343
2344 /* IVB wants error correction enabled */
2345 if (IS_IVYBRIDGE(dev))
2346 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2347 FDI_FE_ERRC_ENABLE);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08002348}
2349
Jesse Barnes291427f2011-07-29 12:42:37 -07002350static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2351{
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 u32 flags = I915_READ(SOUTH_CHICKEN1);
2354
2355 flags |= FDI_PHASE_SYNC_OVR(pipe);
2356 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2357 flags |= FDI_PHASE_SYNC_EN(pipe);
2358 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2359 POSTING_READ(SOUTH_CHICKEN1);
2360}
2361
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002362/* The FDI link training functions for ILK/Ibexpeak. */
2363static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2364{
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002369 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01002370 u32 reg, temp, tries;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002371
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002372 /* FDI needs bits from pipe & plane first */
2373 assert_pipe_enabled(dev_priv, pipe);
2374 assert_plane_enabled(dev_priv, plane);
2375
Adam Jacksone1a44742010-06-25 15:32:14 -04002376 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2377 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002378 reg = FDI_RX_IMR(pipe);
2379 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002380 temp &= ~FDI_RX_SYMBOL_LOCK;
2381 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002382 I915_WRITE(reg, temp);
2383 I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002384 udelay(150);
2385
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002386 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002387 reg = FDI_TX_CTL(pipe);
2388 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002389 temp &= ~(7 << 19);
2390 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002391 temp &= ~FDI_LINK_TRAIN_NONE;
2392 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002393 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002394
Chris Wilson5eddb702010-09-11 13:48:45 +01002395 reg = FDI_RX_CTL(pipe);
2396 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002397 temp &= ~FDI_LINK_TRAIN_NONE;
2398 temp |= FDI_LINK_TRAIN_PATTERN_1;
Chris Wilson5eddb702010-09-11 13:48:45 +01002399 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002402 udelay(150);
2403
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002404 /* Ironlake workaround, enable clock pointer after FDI enable*/
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002405 if (HAS_PCH_IBX(dev)) {
2406 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2408 FDI_RX_PHASE_SYNC_POINTER_EN);
2409 }
Jesse Barnes5b2adf82010-10-07 16:01:15 -07002410
Chris Wilson5eddb702010-09-11 13:48:45 +01002411 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002412 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002413 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416 if ((temp & FDI_RX_BIT_LOCK)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01002418 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002419 break;
2420 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002421 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002422 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002423 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002424
2425 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002430 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002431
Chris Wilson5eddb702010-09-11 13:48:45 +01002432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002434 temp &= ~FDI_LINK_TRAIN_NONE;
2435 temp |= FDI_LINK_TRAIN_PATTERN_2;
Chris Wilson5eddb702010-09-11 13:48:45 +01002436 I915_WRITE(reg, temp);
2437
2438 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002439 udelay(150);
2440
Chris Wilson5eddb702010-09-11 13:48:45 +01002441 reg = FDI_RX_IIR(pipe);
Adam Jacksone1a44742010-06-25 15:32:14 -04002442 for (tries = 0; tries < 5; tries++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002443 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446 if (temp & FDI_RX_SYMBOL_LOCK) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002447 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2449 break;
2450 }
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002451 }
Adam Jacksone1a44742010-06-25 15:32:14 -04002452 if (tries == 5)
Chris Wilson5eddb702010-09-11 13:48:45 +01002453 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002454
2455 DRM_DEBUG_KMS("FDI train done\n");
Jesse Barnes5c5313c2010-10-07 16:01:11 -07002456
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002457}
2458
Akshay Joshi0206e352011-08-16 15:34:10 -04002459static const int snb_b_fdi_train_param[] = {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002460 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464};
2465
2466/* The FDI link training functions for SNB/Cougarpoint. */
2467static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468{
2469 struct drm_device *dev = crtc->dev;
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472 int pipe = intel_crtc->pipe;
Sean Paulfa37d392012-03-02 12:53:39 -05002473 u32 reg, temp, i, retry;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002474
Adam Jacksone1a44742010-06-25 15:32:14 -04002475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476 for train result */
Chris Wilson5eddb702010-09-11 13:48:45 +01002477 reg = FDI_RX_IMR(pipe);
2478 temp = I915_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002479 temp &= ~FDI_RX_SYMBOL_LOCK;
2480 temp &= ~FDI_RX_BIT_LOCK;
Chris Wilson5eddb702010-09-11 13:48:45 +01002481 I915_WRITE(reg, temp);
2482
2483 POSTING_READ(reg);
Adam Jacksone1a44742010-06-25 15:32:14 -04002484 udelay(150);
2485
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002486 /* enable CPU FDI TX and PCH FDI RX */
Chris Wilson5eddb702010-09-11 13:48:45 +01002487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
Adam Jackson77ffb592010-04-12 11:38:44 -04002489 temp &= ~(7 << 19);
2490 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494 /* SNB-B */
2495 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Chris Wilson5eddb702010-09-11 13:48:45 +01002496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002497
Chris Wilson5eddb702010-09-11 13:48:45 +01002498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002500 if (HAS_PCH_CPT(dev)) {
2501 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503 } else {
2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002507 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002510 udelay(150);
2511
Jesse Barnes291427f2011-07-29 12:42:37 -07002512 if (HAS_PCH_CPT(dev))
2513 cpt_phase_pointer_enable(dev, pipe);
2514
Akshay Joshi0206e352011-08-16 15:34:10 -04002515 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002523 udelay(500);
2524
Sean Paulfa37d392012-03-02 12:53:39 -05002525 for (retry = 0; retry < 5; retry++) {
2526 reg = FDI_RX_IIR(pipe);
2527 temp = I915_READ(reg);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529 if (temp & FDI_RX_BIT_LOCK) {
2530 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532 break;
2533 }
2534 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002535 }
Sean Paulfa37d392012-03-02 12:53:39 -05002536 if (retry < 5)
2537 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002538 }
2539 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002540 DRM_ERROR("FDI train 1 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002541
2542 /* Train 2 */
Chris Wilson5eddb702010-09-11 13:48:45 +01002543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2547 if (IS_GEN6(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549 /* SNB-B */
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002552 I915_WRITE(reg, temp);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002553
Chris Wilson5eddb702010-09-11 13:48:45 +01002554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2559 } else {
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_2;
2562 }
Chris Wilson5eddb702010-09-11 13:48:45 +01002563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002566 udelay(150);
2567
Akshay Joshi0206e352011-08-16 15:34:10 -04002568 for (i = 0; i < 4; i++) {
Chris Wilson5eddb702010-09-11 13:48:45 +01002569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
Chris Wilson5eddb702010-09-11 13:48:45 +01002573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002576 udelay(500);
2577
Sean Paulfa37d392012-03-02 12:53:39 -05002578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_SYMBOL_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585 break;
2586 }
2587 udelay(50);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002588 }
Sean Paulfa37d392012-03-02 12:53:39 -05002589 if (retry < 5)
2590 break;
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002591 }
2592 if (i == 4)
Chris Wilson5eddb702010-09-11 13:48:45 +01002593 DRM_ERROR("FDI train 2 fail!\n");
Zhenyu Wang8db9d772010-04-07 16:15:54 +08002594
2595 DRM_DEBUG_KMS("FDI train done.\n");
2596}
2597
Jesse Barnes357555c2011-04-28 15:09:55 -07002598/* Manual link training for Ivy Bridge A0 parts */
2599static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2600{
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604 int pipe = intel_crtc->pipe;
2605 u32 reg, temp, i;
2606
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608 for train result */
2609 reg = FDI_RX_IMR(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_RX_SYMBOL_LOCK;
2612 temp &= ~FDI_RX_BIT_LOCK;
2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
2618 /* enable CPU FDI TX and PCH FDI RX */
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~(7 << 19);
2622 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2623 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002627 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002628 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2629
2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 temp &= ~FDI_LINK_TRAIN_AUTO;
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
Jesse Barnesc4f9c4c2011-10-10 14:28:52 -07002635 temp |= FDI_COMPOSITE_SYNC;
Jesse Barnes357555c2011-04-28 15:09:55 -07002636 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
Jesse Barnes291427f2011-07-29 12:42:37 -07002641 if (HAS_PCH_CPT(dev))
2642 cpt_phase_pointer_enable(dev, pipe);
2643
Akshay Joshi0206e352011-08-16 15:34:10 -04002644 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
2649 I915_WRITE(reg, temp);
2650
2651 POSTING_READ(reg);
2652 udelay(500);
2653
2654 reg = FDI_RX_IIR(pipe);
2655 temp = I915_READ(reg);
2656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2657
2658 if (temp & FDI_RX_BIT_LOCK ||
2659 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2660 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2662 break;
2663 }
2664 }
2665 if (i == 4)
2666 DRM_ERROR("FDI train 1 fail!\n");
2667
2668 /* Train 2 */
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2672 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2673 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675 I915_WRITE(reg, temp);
2676
2677 reg = FDI_RX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2681 I915_WRITE(reg, temp);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
Akshay Joshi0206e352011-08-16 15:34:10 -04002686 for (i = 0; i < 4; i++) {
Jesse Barnes357555c2011-04-28 15:09:55 -07002687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_SYMBOL_LOCK) {
2701 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2702 DRM_DEBUG_KMS("FDI train 2 done.\n");
2703 break;
2704 }
2705 }
2706 if (i == 4)
2707 DRM_ERROR("FDI train 2 fail!\n");
2708
2709 DRM_DEBUG_KMS("FDI train done.\n");
2710}
2711
2712static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
Jesse Barnes0e23b992010-09-10 11:10:00 -07002713{
2714 struct drm_device *dev = crtc->dev;
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2717 int pipe = intel_crtc->pipe;
Chris Wilson5eddb702010-09-11 13:48:45 +01002718 u32 reg, temp;
Jesse Barnes0e23b992010-09-10 11:10:00 -07002719
Jesse Barnesc64e3112010-09-10 11:27:03 -07002720 /* Write the TU size bits so error detection works */
Chris Wilson5eddb702010-09-11 13:48:45 +01002721 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2722 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
Jesse Barnesc64e3112010-09-10 11:27:03 -07002723
Jesse Barnes0e23b992010-09-10 11:10:00 -07002724 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
Chris Wilson5eddb702010-09-11 13:48:45 +01002725 reg = FDI_RX_CTL(pipe);
2726 temp = I915_READ(reg);
2727 temp &= ~((0x7 << 19) | (0x7 << 16));
Jesse Barnes0e23b992010-09-10 11:10:00 -07002728 temp |= (intel_crtc->fdi_lanes - 1) << 19;
Chris Wilson5eddb702010-09-11 13:48:45 +01002729 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2730 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2731
2732 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002733 udelay(200);
2734
2735 /* Switch from Rawclk to PCDclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01002736 temp = I915_READ(reg);
2737 I915_WRITE(reg, temp | FDI_PCDCLK);
2738
2739 POSTING_READ(reg);
Jesse Barnes0e23b992010-09-10 11:10:00 -07002740 udelay(200);
2741
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03002742 /* On Haswell, the PLL configuration for ports and pipes is handled
2743 * separately, as part of DDI setup */
2744 if (!IS_HASWELL(dev)) {
2745 /* Enable CPU FDI TX PLL, always on for Ironlake */
2746 reg = FDI_TX_CTL(pipe);
2747 temp = I915_READ(reg);
2748 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2749 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
Chris Wilson5eddb702010-09-11 13:48:45 +01002750
Eugeni Dodonovbf507ef2012-05-09 15:37:18 -03002751 POSTING_READ(reg);
2752 udelay(100);
2753 }
Jesse Barnes0e23b992010-09-10 11:10:00 -07002754 }
2755}
2756
Jesse Barnes291427f2011-07-29 12:42:37 -07002757static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2758{
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 u32 flags = I915_READ(SOUTH_CHICKEN1);
2761
2762 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2763 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2764 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2765 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2766 POSTING_READ(SOUTH_CHICKEN1);
2767}
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002768static void ironlake_fdi_disable(struct drm_crtc *crtc)
2769{
2770 struct drm_device *dev = crtc->dev;
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2773 int pipe = intel_crtc->pipe;
2774 u32 reg, temp;
2775
2776 /* disable CPU FDI tx and PCH FDI rx */
2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2780 POSTING_READ(reg);
2781
2782 reg = FDI_RX_CTL(pipe);
2783 temp = I915_READ(reg);
2784 temp &= ~(0x7 << 16);
2785 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2786 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2787
2788 POSTING_READ(reg);
2789 udelay(100);
2790
2791 /* Ironlake workaround, disable clock pointer after downing FDI */
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002792 if (HAS_PCH_IBX(dev)) {
2793 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002794 I915_WRITE(FDI_RX_CHICKEN(pipe),
2795 I915_READ(FDI_RX_CHICKEN(pipe) &
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002796 ~FDI_RX_PHASE_SYNC_POINTER_EN));
Jesse Barnes291427f2011-07-29 12:42:37 -07002797 } else if (HAS_PCH_CPT(dev)) {
2798 cpt_phase_pointer_disable(dev, pipe);
Jesse Barnes6f06ce12011-01-04 15:09:38 -08002799 }
Jesse Barnes0fc932b2011-01-04 15:09:37 -08002800
2801 /* still set train pattern 1 */
2802 reg = FDI_TX_CTL(pipe);
2803 temp = I915_READ(reg);
2804 temp &= ~FDI_LINK_TRAIN_NONE;
2805 temp |= FDI_LINK_TRAIN_PATTERN_1;
2806 I915_WRITE(reg, temp);
2807
2808 reg = FDI_RX_CTL(pipe);
2809 temp = I915_READ(reg);
2810 if (HAS_PCH_CPT(dev)) {
2811 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2812 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2813 } else {
2814 temp &= ~FDI_LINK_TRAIN_NONE;
2815 temp |= FDI_LINK_TRAIN_PATTERN_1;
2816 }
2817 /* BPC in FDI rx is consistent with that in PIPECONF */
2818 temp &= ~(0x07 << 16);
2819 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2820 I915_WRITE(reg, temp);
2821
2822 POSTING_READ(reg);
2823 udelay(100);
2824}
2825
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002826static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2827{
Chris Wilson0f911282012-04-17 10:05:38 +01002828 struct drm_device *dev = crtc->dev;
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002829
2830 if (crtc->fb == NULL)
2831 return;
2832
Chris Wilson0f911282012-04-17 10:05:38 +01002833 mutex_lock(&dev->struct_mutex);
2834 intel_finish_fb(crtc->fb);
2835 mutex_unlock(&dev->struct_mutex);
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01002836}
2837
Jesse Barnes040484a2011-01-03 12:14:26 -08002838static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2839{
2840 struct drm_device *dev = crtc->dev;
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002841 struct intel_encoder *intel_encoder;
Jesse Barnes040484a2011-01-03 12:14:26 -08002842
2843 /*
2844 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2845 * must be driven by its own crtc; no sharing is possible.
2846 */
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002847 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002848
Eugeni Dodonov6ee8bab2012-05-09 20:30:31 -03002849 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2850 * CPU handles all others */
2851 if (IS_HASWELL(dev)) {
2852 /* It is still unclear how this will work on PPT, so throw up a warning */
2853 WARN_ON(!HAS_PCH_LPT(dev));
2854
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002855 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
Eugeni Dodonov6ee8bab2012-05-09 20:30:31 -03002856 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2857 return true;
2858 } else {
2859 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002860 intel_encoder->type);
Eugeni Dodonov6ee8bab2012-05-09 20:30:31 -03002861 return false;
2862 }
2863 }
2864
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002865 switch (intel_encoder->type) {
Jesse Barnes040484a2011-01-03 12:14:26 -08002866 case INTEL_OUTPUT_EDP:
Paulo Zanoni228d3e32012-08-10 10:05:10 -03002867 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
Jesse Barnes040484a2011-01-03 12:14:26 -08002868 return false;
2869 continue;
2870 }
2871 }
2872
2873 return true;
2874}
2875
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002876/* Program iCLKIP clock to the desired frequency */
2877static void lpt_program_iclkip(struct drm_crtc *crtc)
2878{
2879 struct drm_device *dev = crtc->dev;
2880 struct drm_i915_private *dev_priv = dev->dev_private;
2881 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2882 u32 temp;
2883
2884 /* It is necessary to ungate the pixclk gate prior to programming
2885 * the divisors, and gate it back when it is done.
2886 */
2887 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2888
2889 /* Disable SSCCTL */
2890 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2891 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2892 SBI_SSCCTL_DISABLE);
2893
2894 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2895 if (crtc->mode.clock == 20000) {
2896 auxdiv = 1;
2897 divsel = 0x41;
2898 phaseinc = 0x20;
2899 } else {
2900 /* The iCLK virtual clock root frequency is in MHz,
2901 * but the crtc->mode.clock in in KHz. To get the divisors,
2902 * it is necessary to divide one by another, so we
2903 * convert the virtual clock precision to KHz here for higher
2904 * precision.
2905 */
2906 u32 iclk_virtual_root_freq = 172800 * 1000;
2907 u32 iclk_pi_range = 64;
2908 u32 desired_divisor, msb_divisor_value, pi_value;
2909
2910 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2911 msb_divisor_value = desired_divisor / iclk_pi_range;
2912 pi_value = desired_divisor % iclk_pi_range;
2913
2914 auxdiv = 0;
2915 divsel = msb_divisor_value - 2;
2916 phaseinc = pi_value;
2917 }
2918
2919 /* This should not happen with any sane values */
2920 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2921 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2922 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2923 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2924
2925 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2926 crtc->mode.clock,
2927 auxdiv,
2928 divsel,
2929 phasedir,
2930 phaseinc);
2931
2932 /* Program SSCDIVINTPHASE6 */
2933 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2934 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2935 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2936 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2937 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2938 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2939 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2940
2941 intel_sbi_write(dev_priv,
2942 SBI_SSCDIVINTPHASE6,
2943 temp);
2944
2945 /* Program SSCAUXDIV */
2946 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2947 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2948 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2949 intel_sbi_write(dev_priv,
2950 SBI_SSCAUXDIV6,
2951 temp);
2952
2953
2954 /* Enable modulator and associated divider */
2955 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2956 temp &= ~SBI_SSCCTL_DISABLE;
2957 intel_sbi_write(dev_priv,
2958 SBI_SSCCTL6,
2959 temp);
2960
2961 /* Wait for initialization time */
2962 udelay(24);
2963
2964 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2965}
2966
Jesse Barnesf67a5592011-01-05 10:31:48 -08002967/*
2968 * Enable PCH resources required for PCH ports:
2969 * - PCH PLLs
2970 * - FDI training & RX/TX
2971 * - update transcoder timings
2972 * - DP transcoding bits
2973 * - transcoder
2974 */
2975static void ironlake_pch_enable(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08002976{
2977 struct drm_device *dev = crtc->dev;
Zhenyu Wang2c072452009-06-05 15:38:42 +08002978 struct drm_i915_private *dev_priv = dev->dev_private;
2979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2980 int pipe = intel_crtc->pipe;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01002981 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07002982
Chris Wilsone7e164d2012-05-11 09:21:25 +01002983 assert_transcoder_disabled(dev_priv, pipe);
2984
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002985 /* For PCH output, training FDI link */
Jesse Barnes674cf962011-04-28 14:27:04 -07002986 dev_priv->display.fdi_link_train(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07002987
Chris Wilson6f13b7b2012-05-13 09:54:09 +01002988 intel_enable_pch_pll(intel_crtc);
2989
Eugeni Dodonove615efe2012-05-09 15:37:26 -03002990 if (HAS_PCH_LPT(dev)) {
2991 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2992 lpt_program_iclkip(crtc);
2993 } else if (HAS_PCH_CPT(dev)) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01002994 u32 sel;
Jesse Barnes4b645f12011-10-12 09:51:31 -07002995
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07002996 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01002997 switch (pipe) {
2998 default:
2999 case 0:
3000 temp |= TRANSA_DPLL_ENABLE;
3001 sel = TRANSA_DPLLB_SEL;
3002 break;
3003 case 1:
3004 temp |= TRANSB_DPLL_ENABLE;
3005 sel = TRANSB_DPLLB_SEL;
3006 break;
3007 case 2:
3008 temp |= TRANSC_DPLL_ENABLE;
3009 sel = TRANSC_DPLLB_SEL;
3010 break;
Jesse Barnesd64311a2011-10-12 15:01:33 -07003011 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003012 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3013 temp |= sel;
3014 else
3015 temp &= ~sel;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003016 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003017 }
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003018
Jesse Barnesd9b6cb52011-01-04 15:09:35 -08003019 /* set transcoder timing, panel must allow it */
3020 assert_panel_unlocked(dev_priv, pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +01003021 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3022 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3023 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3024
3025 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3026 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3027 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
Daniel Vetter0529a0d2012-01-28 14:49:24 +01003028 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003029
Eugeni Dodonovf57e1e32012-05-09 15:37:14 -03003030 if (!IS_HASWELL(dev))
3031 intel_fdi_normal_train(crtc);
Zhenyu Wang5e84e1a2010-10-28 16:38:08 +08003032
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003033 /* For PCH DP, enable TRANS_DP_CTL */
3034 if (HAS_PCH_CPT(dev) &&
Keith Packard417e8222011-11-01 19:54:11 -07003035 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3036 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003037 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
Chris Wilson5eddb702010-09-11 13:48:45 +01003038 reg = TRANS_DP_CTL(pipe);
3039 temp = I915_READ(reg);
3040 temp &= ~(TRANS_DP_PORT_SEL_MASK |
Eric Anholt220cad32010-11-18 09:32:58 +08003041 TRANS_DP_SYNC_MASK |
3042 TRANS_DP_BPC_MASK);
Chris Wilson5eddb702010-09-11 13:48:45 +01003043 temp |= (TRANS_DP_OUTPUT_ENABLE |
3044 TRANS_DP_ENH_FRAMING);
Jesse Barnes9325c9f2011-06-24 12:19:21 -07003045 temp |= bpc << 9; /* same format but at 11:9 */
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003046
3047 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003048 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003049 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
Chris Wilson5eddb702010-09-11 13:48:45 +01003050 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003051
3052 switch (intel_trans_dp_port_sel(crtc)) {
3053 case PCH_DP_B:
Chris Wilson5eddb702010-09-11 13:48:45 +01003054 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003055 break;
3056 case PCH_DP_C:
Chris Wilson5eddb702010-09-11 13:48:45 +01003057 temp |= TRANS_DP_PORT_SEL_C;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003058 break;
3059 case PCH_DP_D:
Chris Wilson5eddb702010-09-11 13:48:45 +01003060 temp |= TRANS_DP_PORT_SEL_D;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003061 break;
3062 default:
3063 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
Chris Wilson5eddb702010-09-11 13:48:45 +01003064 temp |= TRANS_DP_PORT_SEL_B;
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003065 break;
3066 }
3067
Chris Wilson5eddb702010-09-11 13:48:45 +01003068 I915_WRITE(reg, temp);
Jesse Barnesc98e9dc2010-09-10 10:57:18 -07003069 }
3070
Jesse Barnes040484a2011-01-03 12:14:26 -08003071 intel_enable_transcoder(dev_priv, pipe);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003072}
3073
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003074static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3075{
3076 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3077
3078 if (pll == NULL)
3079 return;
3080
3081 if (pll->refcount == 0) {
3082 WARN(1, "bad PCH PLL refcount\n");
3083 return;
3084 }
3085
3086 --pll->refcount;
3087 intel_crtc->pch_pll = NULL;
3088}
3089
3090static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3091{
3092 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3093 struct intel_pch_pll *pll;
3094 int i;
3095
3096 pll = intel_crtc->pch_pll;
3097 if (pll) {
3098 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3099 intel_crtc->base.base.id, pll->pll_reg);
3100 goto prepare;
3101 }
3102
Daniel Vetter98b6bd92012-05-20 20:00:25 +02003103 if (HAS_PCH_IBX(dev_priv->dev)) {
3104 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3105 i = intel_crtc->pipe;
3106 pll = &dev_priv->pch_plls[i];
3107
3108 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3109 intel_crtc->base.base.id, pll->pll_reg);
3110
3111 goto found;
3112 }
3113
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003114 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3115 pll = &dev_priv->pch_plls[i];
3116
3117 /* Only want to check enabled timings first */
3118 if (pll->refcount == 0)
3119 continue;
3120
3121 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3122 fp == I915_READ(pll->fp0_reg)) {
3123 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3124 intel_crtc->base.base.id,
3125 pll->pll_reg, pll->refcount, pll->active);
3126
3127 goto found;
3128 }
3129 }
3130
3131 /* Ok no matching timings, maybe there's a free one? */
3132 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3133 pll = &dev_priv->pch_plls[i];
3134 if (pll->refcount == 0) {
3135 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3136 intel_crtc->base.base.id, pll->pll_reg);
3137 goto found;
3138 }
3139 }
3140
3141 return NULL;
3142
3143found:
3144 intel_crtc->pch_pll = pll;
3145 pll->refcount++;
3146 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3147prepare: /* separate function? */
3148 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003149
Chris Wilsone04c7352012-05-02 20:43:56 +01003150 /* Wait for the clocks to stabilize before rewriting the regs */
3151 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003152 POSTING_READ(pll->pll_reg);
3153 udelay(150);
Chris Wilsone04c7352012-05-02 20:43:56 +01003154
3155 I915_WRITE(pll->fp0_reg, fp);
3156 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003157 pll->on = false;
3158 return pll;
3159}
3160
Jesse Barnesd4270e52011-10-11 10:43:02 -07003161void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3162{
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3165 u32 temp;
3166
3167 temp = I915_READ(dslreg);
3168 udelay(500);
3169 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3170 /* Without this, mode sets may fail silently on FDI */
3171 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3172 udelay(250);
3173 I915_WRITE(tc2reg, 0);
3174 if (wait_for(I915_READ(dslreg) != temp, 5))
3175 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3176 }
3177}
3178
Jesse Barnesf67a5592011-01-05 10:31:48 -08003179static void ironlake_crtc_enable(struct drm_crtc *crtc)
3180{
3181 struct drm_device *dev = crtc->dev;
3182 struct drm_i915_private *dev_priv = dev->dev_private;
3183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3184 int pipe = intel_crtc->pipe;
3185 int plane = intel_crtc->plane;
3186 u32 temp;
3187 bool is_pch_port;
3188
3189 if (intel_crtc->active)
3190 return;
3191
3192 intel_crtc->active = true;
3193 intel_update_watermarks(dev);
3194
3195 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3196 temp = I915_READ(PCH_LVDS);
3197 if ((temp & LVDS_PORT_EN) == 0)
3198 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3199 }
3200
3201 is_pch_port = intel_crtc_driving_pch(crtc);
3202
3203 if (is_pch_port)
Jesse Barnes357555c2011-04-28 15:09:55 -07003204 ironlake_fdi_pll_enable(crtc);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003205 else
3206 ironlake_fdi_disable(crtc);
3207
3208 /* Enable panel fitting for LVDS */
3209 if (dev_priv->pch_pf_size &&
3210 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3211 /* Force use of hard-coded filter coefficients
3212 * as some pre-programmed values are broken,
3213 * e.g. x201.
3214 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003215 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3216 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3217 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
Jesse Barnesf67a5592011-01-05 10:31:48 -08003218 }
3219
Jesse Barnes9c54c0d2011-06-15 23:32:33 +02003220 /*
3221 * On ILK+ LUT must be loaded before the pipe is running but with
3222 * clocks enabled
3223 */
3224 intel_crtc_load_lut(crtc);
3225
Jesse Barnesf67a5592011-01-05 10:31:48 -08003226 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3227 intel_enable_plane(dev_priv, plane, pipe);
3228
3229 if (is_pch_port)
3230 ironlake_pch_enable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003231
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003232 mutex_lock(&dev->struct_mutex);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003233 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003234 mutex_unlock(&dev->struct_mutex);
3235
Chris Wilson6b383a72010-09-13 13:54:26 +01003236 intel_crtc_update_cursor(crtc, true);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003237}
3238
3239static void ironlake_crtc_disable(struct drm_crtc *crtc)
3240{
3241 struct drm_device *dev = crtc->dev;
3242 struct drm_i915_private *dev_priv = dev->dev_private;
3243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3244 int pipe = intel_crtc->pipe;
3245 int plane = intel_crtc->plane;
Chris Wilson5eddb702010-09-11 13:48:45 +01003246 u32 reg, temp;
Jesse Barnes6be4a602010-09-10 10:26:01 -07003247
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003248 if (!intel_crtc->active)
3249 return;
3250
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003251 intel_crtc_wait_for_pending_flips(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003252 drm_vblank_off(dev, pipe);
Chris Wilson6b383a72010-09-13 13:54:26 +01003253 intel_crtc_update_cursor(crtc, false);
Chris Wilson5eddb702010-09-11 13:48:45 +01003254
Jesse Barnesb24e7172011-01-04 15:09:30 -08003255 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003256
Chris Wilson973d04f2011-07-08 12:22:37 +01003257 if (dev_priv->cfb_plane == plane)
3258 intel_disable_fbc(dev);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003259
Jesse Barnesb24e7172011-01-04 15:09:30 -08003260 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003261
Jesse Barnes6be4a602010-09-10 10:26:01 -07003262 /* Disable PF */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003263 I915_WRITE(PF_CTL(pipe), 0);
3264 I915_WRITE(PF_WIN_SZ(pipe), 0);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003265
Jesse Barnes0fc932b2011-01-04 15:09:37 -08003266 ironlake_fdi_disable(crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003267
Jesse Barnes47a05ec2011-02-07 13:46:40 -08003268 /* This is a horrible layering violation; we should be doing this in
3269 * the connector/encoder ->prepare instead, but we don't always have
3270 * enough information there about the config to know whether it will
3271 * actually be necessary or just cause undesired flicker.
3272 */
3273 intel_disable_pch_ports(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003274
Jesse Barnes040484a2011-01-03 12:14:26 -08003275 intel_disable_transcoder(dev_priv, pipe);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003276
Jesse Barnes6be4a602010-09-10 10:26:01 -07003277 if (HAS_PCH_CPT(dev)) {
3278 /* disable TRANS_DP_CTL */
Chris Wilson5eddb702010-09-11 13:48:45 +01003279 reg = TRANS_DP_CTL(pipe);
3280 temp = I915_READ(reg);
3281 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
Eric Anholtcb3543c2011-02-02 12:08:07 -08003282 temp |= TRANS_DP_PORT_SEL_NONE;
Chris Wilson5eddb702010-09-11 13:48:45 +01003283 I915_WRITE(reg, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003284
3285 /* disable DPLL_SEL */
3286 temp = I915_READ(PCH_DPLL_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003287 switch (pipe) {
3288 case 0:
Jesse Barnesd64311a2011-10-12 15:01:33 -07003289 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003290 break;
3291 case 1:
Jesse Barnes6be4a602010-09-10 10:26:01 -07003292 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003293 break;
3294 case 2:
Jesse Barnes4b645f12011-10-12 09:51:31 -07003295 /* C shares PLL A or B */
Jesse Barnesd64311a2011-10-12 15:01:33 -07003296 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003297 break;
3298 default:
3299 BUG(); /* wtf */
3300 }
Jesse Barnes6be4a602010-09-10 10:26:01 -07003301 I915_WRITE(PCH_DPLL_SEL, temp);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003302 }
3303
3304 /* disable PCH DPLL */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003305 intel_disable_pch_pll(intel_crtc);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003306
3307 /* Switch from PCDclk to Rawclk */
Chris Wilson5eddb702010-09-11 13:48:45 +01003308 reg = FDI_RX_CTL(pipe);
3309 temp = I915_READ(reg);
3310 I915_WRITE(reg, temp & ~FDI_PCDCLK);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003311
3312 /* Disable CPU FDI TX PLL */
Chris Wilson5eddb702010-09-11 13:48:45 +01003313 reg = FDI_TX_CTL(pipe);
3314 temp = I915_READ(reg);
3315 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3316
3317 POSTING_READ(reg);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003318 udelay(100);
3319
Chris Wilson5eddb702010-09-11 13:48:45 +01003320 reg = FDI_RX_CTL(pipe);
3321 temp = I915_READ(reg);
3322 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003323
3324 /* Wait for the clocks to turn off. */
Chris Wilson5eddb702010-09-11 13:48:45 +01003325 POSTING_READ(reg);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003326 udelay(100);
Chris Wilson6b383a72010-09-13 13:54:26 +01003327
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003328 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003329 intel_update_watermarks(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003330
3331 mutex_lock(&dev->struct_mutex);
Chris Wilson6b383a72010-09-13 13:54:26 +01003332 intel_update_fbc(dev);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +01003333 mutex_unlock(&dev->struct_mutex);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003334}
3335
3336static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3337{
3338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3339 int pipe = intel_crtc->pipe;
3340 int plane = intel_crtc->plane;
3341
Zhenyu Wang2c072452009-06-05 15:38:42 +08003342 /* XXX: When our outputs are all unaware of DPMS modes other than off
3343 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3344 */
3345 switch (mode) {
3346 case DRM_MODE_DPMS_ON:
3347 case DRM_MODE_DPMS_STANDBY:
3348 case DRM_MODE_DPMS_SUSPEND:
Chris Wilson868dc582010-08-07 11:01:31 +01003349 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003350 ironlake_crtc_enable(crtc);
Chris Wilson868dc582010-08-07 11:01:31 +01003351 break;
Zhao Yakuib52eb4d2010-06-12 14:32:27 +08003352
Zhenyu Wang2c072452009-06-05 15:38:42 +08003353 case DRM_MODE_DPMS_OFF:
Chris Wilson868dc582010-08-07 11:01:31 +01003354 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
Jesse Barnes6be4a602010-09-10 10:26:01 -07003355 ironlake_crtc_disable(crtc);
Zhenyu Wang2c072452009-06-05 15:38:42 +08003356 break;
3357 }
3358}
3359
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003360static void ironlake_crtc_off(struct drm_crtc *crtc)
3361{
3362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3363 intel_put_pch_pll(intel_crtc);
3364}
3365
Daniel Vetter02e792f2009-09-15 22:57:34 +02003366static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3367{
Daniel Vetter02e792f2009-09-15 22:57:34 +02003368 if (!enable && intel_crtc->overlay) {
Chris Wilson23f09ce2010-08-12 13:53:37 +01003369 struct drm_device *dev = intel_crtc->base.dev;
Chris Wilsonce453d82011-02-21 14:43:56 +00003370 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter03f77ea2009-09-15 22:57:37 +02003371
Chris Wilson23f09ce2010-08-12 13:53:37 +01003372 mutex_lock(&dev->struct_mutex);
Chris Wilsonce453d82011-02-21 14:43:56 +00003373 dev_priv->mm.interruptible = false;
3374 (void) intel_overlay_switch_off(intel_crtc->overlay);
3375 dev_priv->mm.interruptible = true;
Chris Wilson23f09ce2010-08-12 13:53:37 +01003376 mutex_unlock(&dev->struct_mutex);
Daniel Vetter02e792f2009-09-15 22:57:34 +02003377 }
Daniel Vetter02e792f2009-09-15 22:57:34 +02003378
Chris Wilson5dcdbcb2010-08-12 13:50:28 +01003379 /* Let userspace switch the overlay on again. In most cases userspace
3380 * has to recompute where to put it anyway.
3381 */
Daniel Vetter02e792f2009-09-15 22:57:34 +02003382}
3383
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003384static void i9xx_crtc_enable(struct drm_crtc *crtc)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003385{
3386 struct drm_device *dev = crtc->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08003387 struct drm_i915_private *dev_priv = dev->dev_private;
3388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3389 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07003390 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08003391
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003392 if (intel_crtc->active)
3393 return;
3394
3395 intel_crtc->active = true;
Chris Wilson6b383a72010-09-13 13:54:26 +01003396 intel_update_watermarks(dev);
3397
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003398 intel_enable_pll(dev_priv, pipe);
Jesse Barnes040484a2011-01-03 12:14:26 -08003399 intel_enable_pipe(dev_priv, pipe, false);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003400 intel_enable_plane(dev_priv, plane, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003401
3402 intel_crtc_load_lut(crtc);
Chris Wilsonbed4a672010-09-11 10:47:47 +01003403 intel_update_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003404
3405 /* Give the overlay scaler a chance to enable if it's on this pipe */
3406 intel_crtc_dpms_overlay(intel_crtc, true);
Chris Wilson6b383a72010-09-13 13:54:26 +01003407 intel_crtc_update_cursor(crtc, true);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003408}
3409
3410static void i9xx_crtc_disable(struct drm_crtc *crtc)
3411{
3412 struct drm_device *dev = crtc->dev;
3413 struct drm_i915_private *dev_priv = dev->dev_private;
3414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3415 int pipe = intel_crtc->pipe;
3416 int plane = intel_crtc->plane;
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003417
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003418 if (!intel_crtc->active)
3419 return;
3420
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003421 /* Give the overlay scaler a chance to disable if it's on this pipe */
Chris Wilsone6c3a2a2010-09-23 23:04:43 +01003422 intel_crtc_wait_for_pending_flips(crtc);
3423 drm_vblank_off(dev, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003424 intel_crtc_dpms_overlay(intel_crtc, false);
Chris Wilson6b383a72010-09-13 13:54:26 +01003425 intel_crtc_update_cursor(crtc, false);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003426
Chris Wilson973d04f2011-07-08 12:22:37 +01003427 if (dev_priv->cfb_plane == plane)
3428 intel_disable_fbc(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003429
Jesse Barnesb24e7172011-01-04 15:09:30 -08003430 intel_disable_plane(dev_priv, plane, pipe);
Jesse Barnesb24e7172011-01-04 15:09:30 -08003431 intel_disable_pipe(dev_priv, pipe);
Jesse Barnes63d7bbe2011-01-04 15:09:33 -08003432 intel_disable_pll(dev_priv, pipe);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003433
Chris Wilsonf7abfe82010-09-13 14:19:16 +01003434 intel_crtc->active = false;
Chris Wilson6b383a72010-09-13 13:54:26 +01003435 intel_update_fbc(dev);
3436 intel_update_watermarks(dev);
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003437}
3438
3439static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3440{
Jesse Barnes79e53942008-11-07 14:24:08 -08003441 /* XXX: When our outputs are all unaware of DPMS modes other than off
3442 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3443 */
3444 switch (mode) {
3445 case DRM_MODE_DPMS_ON:
3446 case DRM_MODE_DPMS_STANDBY:
3447 case DRM_MODE_DPMS_SUSPEND:
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003448 i9xx_crtc_enable(crtc);
3449 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08003450 case DRM_MODE_DPMS_OFF:
Jesse Barnes0b8765c62010-09-10 10:31:34 -07003451 i9xx_crtc_disable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003452 break;
3453 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08003454}
3455
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003456static void i9xx_crtc_off(struct drm_crtc *crtc)
3457{
3458}
3459
Zhenyu Wang2c072452009-06-05 15:38:42 +08003460/**
3461 * Sets the power management mode of the pipe and plane.
Zhenyu Wang2c072452009-06-05 15:38:42 +08003462 */
3463static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3464{
3465 struct drm_device *dev = crtc->dev;
Jesse Barnese70236a2009-09-21 10:42:27 -07003466 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003467 struct drm_i915_master_private *master_priv;
3468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3469 int pipe = intel_crtc->pipe;
3470 bool enabled;
3471
Chris Wilson032d2a02010-09-06 16:17:22 +01003472 if (intel_crtc->dpms_mode == mode)
3473 return;
3474
Chris Wilsondebcadd2010-08-07 11:01:33 +01003475 intel_crtc->dpms_mode = mode;
Chris Wilsondebcadd2010-08-07 11:01:33 +01003476
Jesse Barnese70236a2009-09-21 10:42:27 -07003477 dev_priv->display.dpms(crtc, mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08003478
3479 if (!dev->primary->master)
3480 return;
3481
3482 master_priv = dev->primary->master->driver_priv;
3483 if (!master_priv->sarea_priv)
3484 return;
3485
3486 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3487
3488 switch (pipe) {
3489 case 0:
3490 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3491 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3492 break;
3493 case 1:
3494 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3495 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3496 break;
3497 default:
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08003498 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08003499 break;
3500 }
Jesse Barnes79e53942008-11-07 14:24:08 -08003501}
3502
Chris Wilsoncdd59982010-09-08 16:30:16 +01003503static void intel_crtc_disable(struct drm_crtc *crtc)
3504{
3505 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3506 struct drm_device *dev = crtc->dev;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003507 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsoncdd59982010-09-08 16:30:16 +01003508
3509 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
Jesse Barnesee7b9f92012-04-20 17:11:53 +01003510 dev_priv->display.off(crtc);
3511
Chris Wilson931872f2012-01-16 23:01:13 +00003512 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3513 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003514
3515 if (crtc->fb) {
3516 mutex_lock(&dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01003517 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
Chris Wilsoncdd59982010-09-08 16:30:16 +01003518 mutex_unlock(&dev->struct_mutex);
3519 }
3520}
3521
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003522/* Prepare for a mode set.
3523 *
3524 * Note we could be a lot smarter here. We need to figure out which outputs
3525 * will be enabled, which disabled (in short, how the config will changes)
3526 * and perform the minimum necessary steps to accomplish that, e.g. updating
3527 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3528 * panel fitting is in the proper state, etc.
3529 */
3530static void i9xx_crtc_prepare(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003531{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003532 i9xx_crtc_disable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003533}
3534
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003535static void i9xx_crtc_commit(struct drm_crtc *crtc)
Jesse Barnes79e53942008-11-07 14:24:08 -08003536{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003537 i9xx_crtc_enable(crtc);
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003538}
3539
3540static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3541{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003542 ironlake_crtc_disable(crtc);
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003543}
3544
3545static void ironlake_crtc_commit(struct drm_crtc *crtc)
3546{
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07003547 ironlake_crtc_enable(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08003548}
3549
Akshay Joshi0206e352011-08-16 15:34:10 -04003550void intel_encoder_prepare(struct drm_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08003551{
3552 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3553 /* lvds has its own version of prepare see intel_lvds_prepare */
3554 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3555}
3556
Akshay Joshi0206e352011-08-16 15:34:10 -04003557void intel_encoder_commit(struct drm_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08003558{
3559 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
Jesse Barnesd4270e52011-10-11 10:43:02 -07003560 struct drm_device *dev = encoder->dev;
Paulo Zanonid47d7cb2012-05-04 17:18:23 -03003561 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003562
Jesse Barnes79e53942008-11-07 14:24:08 -08003563 /* lvds has its own version of commit see intel_lvds_commit */
3564 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
Jesse Barnesd4270e52011-10-11 10:43:02 -07003565
3566 if (HAS_PCH_CPT(dev))
3567 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08003568}
3569
Chris Wilsonea5b2132010-08-04 13:50:23 +01003570void intel_encoder_destroy(struct drm_encoder *encoder)
3571{
Chris Wilson4ef69c72010-09-09 15:14:28 +01003572 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003573
Chris Wilsonea5b2132010-08-04 13:50:23 +01003574 drm_encoder_cleanup(encoder);
3575 kfree(intel_encoder);
3576}
3577
Jesse Barnes79e53942008-11-07 14:24:08 -08003578static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
Daniel Vetter35313cd2012-07-20 10:30:45 +02003579 const struct drm_display_mode *mode,
Jesse Barnes79e53942008-11-07 14:24:08 -08003580 struct drm_display_mode *adjusted_mode)
3581{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003582 struct drm_device *dev = crtc->dev;
Chris Wilson89749352010-09-12 18:25:19 +01003583
Eric Anholtbad720f2009-10-22 16:11:14 -07003584 if (HAS_PCH_SPLIT(dev)) {
Zhenyu Wang2c072452009-06-05 15:38:42 +08003585 /* FDI link clock is fixed at 2.7G */
Jesse Barnes2377b742010-07-07 14:06:43 -07003586 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3587 return false;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003588 }
Chris Wilson89749352010-09-12 18:25:19 +01003589
Daniel Vetterf9bef082012-04-15 19:53:19 +02003590 /* All interlaced capable intel hw wants timings in frames. Note though
3591 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3592 * timings, so we need to be careful not to clobber these.*/
3593 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3594 drm_mode_set_crtcinfo(adjusted_mode, 0);
Chris Wilson89749352010-09-12 18:25:19 +01003595
Jesse Barnes79e53942008-11-07 14:24:08 -08003596 return true;
3597}
3598
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07003599static int valleyview_get_display_clock_speed(struct drm_device *dev)
3600{
3601 return 400000; /* FIXME */
3602}
3603
Jesse Barnese70236a2009-09-21 10:42:27 -07003604static int i945_get_display_clock_speed(struct drm_device *dev)
Jesse Barnes79e53942008-11-07 14:24:08 -08003605{
Jesse Barnese70236a2009-09-21 10:42:27 -07003606 return 400000;
3607}
Jesse Barnes79e53942008-11-07 14:24:08 -08003608
Jesse Barnese70236a2009-09-21 10:42:27 -07003609static int i915_get_display_clock_speed(struct drm_device *dev)
3610{
3611 return 333000;
3612}
Jesse Barnes79e53942008-11-07 14:24:08 -08003613
Jesse Barnese70236a2009-09-21 10:42:27 -07003614static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3615{
3616 return 200000;
3617}
Jesse Barnes79e53942008-11-07 14:24:08 -08003618
Jesse Barnese70236a2009-09-21 10:42:27 -07003619static int i915gm_get_display_clock_speed(struct drm_device *dev)
3620{
3621 u16 gcfgc = 0;
3622
3623 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3624
3625 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
Jesse Barnes79e53942008-11-07 14:24:08 -08003626 return 133000;
Jesse Barnese70236a2009-09-21 10:42:27 -07003627 else {
3628 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3629 case GC_DISPLAY_CLOCK_333_MHZ:
3630 return 333000;
3631 default:
3632 case GC_DISPLAY_CLOCK_190_200_MHZ:
3633 return 190000;
3634 }
3635 }
3636}
Jesse Barnes79e53942008-11-07 14:24:08 -08003637
Jesse Barnese70236a2009-09-21 10:42:27 -07003638static int i865_get_display_clock_speed(struct drm_device *dev)
3639{
3640 return 266000;
3641}
3642
3643static int i855_get_display_clock_speed(struct drm_device *dev)
3644{
3645 u16 hpllcc = 0;
3646 /* Assume that the hardware is in the high speed state. This
3647 * should be the default.
3648 */
3649 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3650 case GC_CLOCK_133_200:
3651 case GC_CLOCK_100_200:
3652 return 200000;
3653 case GC_CLOCK_166_250:
3654 return 250000;
3655 case GC_CLOCK_100_133:
3656 return 133000;
3657 }
3658
3659 /* Shouldn't happen */
3660 return 0;
3661}
3662
3663static int i830_get_display_clock_speed(struct drm_device *dev)
3664{
3665 return 133000;
Jesse Barnes79e53942008-11-07 14:24:08 -08003666}
3667
Zhenyu Wang2c072452009-06-05 15:38:42 +08003668struct fdi_m_n {
3669 u32 tu;
3670 u32 gmch_m;
3671 u32 gmch_n;
3672 u32 link_m;
3673 u32 link_n;
3674};
3675
3676static void
3677fdi_reduce_ratio(u32 *num, u32 *den)
3678{
3679 while (*num > 0xffffff || *den > 0xffffff) {
3680 *num >>= 1;
3681 *den >>= 1;
3682 }
3683}
3684
Zhenyu Wang2c072452009-06-05 15:38:42 +08003685static void
Adam Jacksonf2b115e2009-12-03 17:14:42 -05003686ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3687 int link_clock, struct fdi_m_n *m_n)
Zhenyu Wang2c072452009-06-05 15:38:42 +08003688{
Zhenyu Wang2c072452009-06-05 15:38:42 +08003689 m_n->tu = 64; /* default size */
3690
Chris Wilson22ed1112010-12-04 01:01:29 +00003691 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3692 m_n->gmch_m = bits_per_pixel * pixel_clock;
3693 m_n->gmch_n = link_clock * nlanes * 8;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003694 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3695
Chris Wilson22ed1112010-12-04 01:01:29 +00003696 m_n->link_m = pixel_clock;
3697 m_n->link_n = link_clock;
Zhenyu Wang2c072452009-06-05 15:38:42 +08003698 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3699}
3700
Chris Wilsona7615032011-01-12 17:04:08 +00003701static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3702{
Keith Packard72bbe582011-09-26 16:09:45 -07003703 if (i915_panel_use_ssc >= 0)
3704 return i915_panel_use_ssc != 0;
3705 return dev_priv->lvds_use_ssc
Keith Packard435793d2011-07-12 14:56:22 -07003706 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
Chris Wilsona7615032011-01-12 17:04:08 +00003707}
3708
Jesse Barnes5a354202011-06-24 12:19:22 -07003709/**
3710 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3711 * @crtc: CRTC structure
Adam Jackson3b5c78a2011-12-13 15:41:00 -08003712 * @mode: requested mode
Jesse Barnes5a354202011-06-24 12:19:22 -07003713 *
3714 * A pipe may be connected to one or more outputs. Based on the depth of the
3715 * attached framebuffer, choose a good color depth to use on the pipe.
3716 *
3717 * If possible, match the pipe depth to the fb depth. In some cases, this
3718 * isn't ideal, because the connected output supports a lesser or restricted
3719 * set of depths. Resolve that here:
3720 * LVDS typically supports only 6bpc, so clamp down in that case
3721 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3722 * Displays may support a restricted set as well, check EDID and clamp as
3723 * appropriate.
Adam Jackson3b5c78a2011-12-13 15:41:00 -08003724 * DP may want to dither down to 6bpc to fit larger modes
Jesse Barnes5a354202011-06-24 12:19:22 -07003725 *
3726 * RETURNS:
3727 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3728 * true if they don't match).
3729 */
3730static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
Adam Jackson3b5c78a2011-12-13 15:41:00 -08003731 unsigned int *pipe_bpp,
3732 struct drm_display_mode *mode)
Jesse Barnes5a354202011-06-24 12:19:22 -07003733{
3734 struct drm_device *dev = crtc->dev;
3735 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes5a354202011-06-24 12:19:22 -07003736 struct drm_connector *connector;
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02003737 struct intel_encoder *intel_encoder;
Jesse Barnes5a354202011-06-24 12:19:22 -07003738 unsigned int display_bpc = UINT_MAX, bpc;
3739
3740 /* Walk the encoders & connectors on this crtc, get min bpc */
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02003741 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
Jesse Barnes5a354202011-06-24 12:19:22 -07003742
3743 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3744 unsigned int lvds_bpc;
3745
3746 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3747 LVDS_A3_POWER_UP)
3748 lvds_bpc = 8;
3749 else
3750 lvds_bpc = 6;
3751
3752 if (lvds_bpc < display_bpc) {
Adam Jackson82820492011-10-10 16:33:34 -04003753 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07003754 display_bpc = lvds_bpc;
3755 }
3756 continue;
3757 }
3758
Jesse Barnes5a354202011-06-24 12:19:22 -07003759 /* Not one of the known troublemakers, check the EDID */
3760 list_for_each_entry(connector, &dev->mode_config.connector_list,
3761 head) {
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02003762 if (connector->encoder != &intel_encoder->base)
Jesse Barnes5a354202011-06-24 12:19:22 -07003763 continue;
3764
Jesse Barnes62ac41a2011-07-28 12:55:14 -07003765 /* Don't use an invalid EDID bpc value */
3766 if (connector->display_info.bpc &&
3767 connector->display_info.bpc < display_bpc) {
Adam Jackson82820492011-10-10 16:33:34 -04003768 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07003769 display_bpc = connector->display_info.bpc;
3770 }
3771 }
3772
3773 /*
3774 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3775 * through, clamp it down. (Note: >12bpc will be caught below.)
3776 */
3777 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3778 if (display_bpc > 8 && display_bpc < 12) {
Adam Jackson82820492011-10-10 16:33:34 -04003779 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
Jesse Barnes5a354202011-06-24 12:19:22 -07003780 display_bpc = 12;
3781 } else {
Adam Jackson82820492011-10-10 16:33:34 -04003782 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
Jesse Barnes5a354202011-06-24 12:19:22 -07003783 display_bpc = 8;
3784 }
3785 }
3786 }
3787
Adam Jackson3b5c78a2011-12-13 15:41:00 -08003788 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3789 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3790 display_bpc = 6;
3791 }
3792
Jesse Barnes5a354202011-06-24 12:19:22 -07003793 /*
3794 * We could just drive the pipe at the highest bpc all the time and
3795 * enable dithering as needed, but that costs bandwidth. So choose
3796 * the minimum value that expresses the full color range of the fb but
3797 * also stays within the max display bpc discovered above.
3798 */
3799
3800 switch (crtc->fb->depth) {
3801 case 8:
3802 bpc = 8; /* since we go through a colormap */
3803 break;
3804 case 15:
3805 case 16:
3806 bpc = 6; /* min is 18bpp */
3807 break;
3808 case 24:
Keith Packard578393c2011-09-05 11:53:21 -07003809 bpc = 8;
Jesse Barnes5a354202011-06-24 12:19:22 -07003810 break;
3811 case 30:
Keith Packard578393c2011-09-05 11:53:21 -07003812 bpc = 10;
Jesse Barnes5a354202011-06-24 12:19:22 -07003813 break;
3814 case 48:
Keith Packard578393c2011-09-05 11:53:21 -07003815 bpc = 12;
Jesse Barnes5a354202011-06-24 12:19:22 -07003816 break;
3817 default:
3818 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3819 bpc = min((unsigned int)8, display_bpc);
3820 break;
3821 }
3822
Keith Packard578393c2011-09-05 11:53:21 -07003823 display_bpc = min(display_bpc, bpc);
3824
Adam Jackson82820492011-10-10 16:33:34 -04003825 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3826 bpc, display_bpc);
Jesse Barnes5a354202011-06-24 12:19:22 -07003827
Keith Packard578393c2011-09-05 11:53:21 -07003828 *pipe_bpp = display_bpc * 3;
Jesse Barnes5a354202011-06-24 12:19:22 -07003829
3830 return display_bpc != bpc;
3831}
3832
Jesse Barnesa0c4da22012-06-15 11:55:13 -07003833static int vlv_get_refclk(struct drm_crtc *crtc)
3834{
3835 struct drm_device *dev = crtc->dev;
3836 struct drm_i915_private *dev_priv = dev->dev_private;
3837 int refclk = 27000; /* for DP & HDMI */
3838
3839 return 100000; /* only one validated so far */
3840
3841 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3842 refclk = 96000;
3843 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3844 if (intel_panel_use_ssc(dev_priv))
3845 refclk = 100000;
3846 else
3847 refclk = 96000;
3848 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3849 refclk = 100000;
3850 }
3851
3852 return refclk;
3853}
3854
Jesse Barnesc65d77d2011-12-15 12:30:36 -08003855static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3856{
3857 struct drm_device *dev = crtc->dev;
3858 struct drm_i915_private *dev_priv = dev->dev_private;
3859 int refclk;
3860
Jesse Barnesa0c4da22012-06-15 11:55:13 -07003861 if (IS_VALLEYVIEW(dev)) {
3862 refclk = vlv_get_refclk(crtc);
3863 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
Jesse Barnesc65d77d2011-12-15 12:30:36 -08003864 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3865 refclk = dev_priv->lvds_ssc_freq * 1000;
3866 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3867 refclk / 1000);
3868 } else if (!IS_GEN2(dev)) {
3869 refclk = 96000;
3870 } else {
3871 refclk = 48000;
3872 }
3873
3874 return refclk;
3875}
3876
3877static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3878 intel_clock_t *clock)
3879{
3880 /* SDVO TV has fixed PLL values depend on its clock range,
3881 this mirrors vbios setting. */
3882 if (adjusted_mode->clock >= 100000
3883 && adjusted_mode->clock < 140500) {
3884 clock->p1 = 2;
3885 clock->p2 = 10;
3886 clock->n = 3;
3887 clock->m1 = 16;
3888 clock->m2 = 8;
3889 } else if (adjusted_mode->clock >= 140500
3890 && adjusted_mode->clock <= 200000) {
3891 clock->p1 = 1;
3892 clock->p2 = 10;
3893 clock->n = 6;
3894 clock->m1 = 12;
3895 clock->m2 = 8;
3896 }
3897}
3898
Jesse Barnesa7516a02011-12-15 12:30:37 -08003899static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3900 intel_clock_t *clock,
3901 intel_clock_t *reduced_clock)
3902{
3903 struct drm_device *dev = crtc->dev;
3904 struct drm_i915_private *dev_priv = dev->dev_private;
3905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3906 int pipe = intel_crtc->pipe;
3907 u32 fp, fp2 = 0;
3908
3909 if (IS_PINEVIEW(dev)) {
3910 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3911 if (reduced_clock)
3912 fp2 = (1 << reduced_clock->n) << 16 |
3913 reduced_clock->m1 << 8 | reduced_clock->m2;
3914 } else {
3915 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3916 if (reduced_clock)
3917 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3918 reduced_clock->m2;
3919 }
3920
3921 I915_WRITE(FP0(pipe), fp);
3922
3923 intel_crtc->lowfreq_avail = false;
3924 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3925 reduced_clock && i915_powersave) {
3926 I915_WRITE(FP1(pipe), fp2);
3927 intel_crtc->lowfreq_avail = true;
3928 } else {
3929 I915_WRITE(FP1(pipe), fp);
3930 }
3931}
3932
Daniel Vetter93e537a2012-03-28 23:11:26 +02003933static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3934 struct drm_display_mode *adjusted_mode)
3935{
3936 struct drm_device *dev = crtc->dev;
3937 struct drm_i915_private *dev_priv = dev->dev_private;
3938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3939 int pipe = intel_crtc->pipe;
Chris Wilson284d5df2012-04-14 17:41:59 +01003940 u32 temp;
Daniel Vetter93e537a2012-03-28 23:11:26 +02003941
3942 temp = I915_READ(LVDS);
3943 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3944 if (pipe == 1) {
3945 temp |= LVDS_PIPEB_SELECT;
3946 } else {
3947 temp &= ~LVDS_PIPEB_SELECT;
3948 }
3949 /* set the corresponsding LVDS_BORDER bit */
3950 temp |= dev_priv->lvds_border_bits;
3951 /* Set the B0-B3 data pairs corresponding to whether we're going to
3952 * set the DPLLs for dual-channel mode or not.
3953 */
3954 if (clock->p2 == 7)
3955 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3956 else
3957 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3958
3959 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3960 * appropriately here, but we need to look more thoroughly into how
3961 * panels behave in the two modes.
3962 */
3963 /* set the dithering flag on LVDS as needed */
3964 if (INTEL_INFO(dev)->gen >= 4) {
3965 if (dev_priv->lvds_dither)
3966 temp |= LVDS_ENABLE_DITHER;
3967 else
3968 temp &= ~LVDS_ENABLE_DITHER;
3969 }
Chris Wilson284d5df2012-04-14 17:41:59 +01003970 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
Daniel Vetter93e537a2012-03-28 23:11:26 +02003971 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01003972 temp |= LVDS_HSYNC_POLARITY;
Daniel Vetter93e537a2012-03-28 23:11:26 +02003973 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01003974 temp |= LVDS_VSYNC_POLARITY;
Daniel Vetter93e537a2012-03-28 23:11:26 +02003975 I915_WRITE(LVDS, temp);
3976}
3977
Jesse Barnesa0c4da22012-06-15 11:55:13 -07003978static void vlv_update_pll(struct drm_crtc *crtc,
3979 struct drm_display_mode *mode,
3980 struct drm_display_mode *adjusted_mode,
3981 intel_clock_t *clock, intel_clock_t *reduced_clock,
3982 int refclk, int num_connectors)
3983{
3984 struct drm_device *dev = crtc->dev;
3985 struct drm_i915_private *dev_priv = dev->dev_private;
3986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3987 int pipe = intel_crtc->pipe;
3988 u32 dpll, mdiv, pdiv;
3989 u32 bestn, bestm1, bestm2, bestp1, bestp2;
3990 bool is_hdmi;
3991
3992 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3993
3994 bestn = clock->n;
3995 bestm1 = clock->m1;
3996 bestm2 = clock->m2;
3997 bestp1 = clock->p1;
3998 bestp2 = clock->p2;
3999
4000 /* Enable DPIO clock input */
4001 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4002 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4003 I915_WRITE(DPLL(pipe), dpll);
4004 POSTING_READ(DPLL(pipe));
4005
4006 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4007 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4008 mdiv |= ((bestn << DPIO_N_SHIFT));
4009 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4010 mdiv |= (1 << DPIO_K_SHIFT);
4011 mdiv |= DPIO_ENABLE_CALIBRATION;
4012 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4013
4014 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4015
4016 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4017 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4018 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4019 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4020
4021 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4022
4023 dpll |= DPLL_VCO_ENABLE;
4024 I915_WRITE(DPLL(pipe), dpll);
4025 POSTING_READ(DPLL(pipe));
4026 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4027 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4028
4029 if (is_hdmi) {
4030 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4031
4032 if (temp > 1)
4033 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4034 else
4035 temp = 0;
4036
4037 I915_WRITE(DPLL_MD(pipe), temp);
4038 POSTING_READ(DPLL_MD(pipe));
4039 }
4040
4041 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4042}
4043
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004044static void i9xx_update_pll(struct drm_crtc *crtc,
4045 struct drm_display_mode *mode,
4046 struct drm_display_mode *adjusted_mode,
4047 intel_clock_t *clock, intel_clock_t *reduced_clock,
4048 int num_connectors)
4049{
4050 struct drm_device *dev = crtc->dev;
4051 struct drm_i915_private *dev_priv = dev->dev_private;
4052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4053 int pipe = intel_crtc->pipe;
4054 u32 dpll;
4055 bool is_sdvo;
4056
4057 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4058 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4059
4060 dpll = DPLL_VGA_MODE_DIS;
4061
4062 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4063 dpll |= DPLLB_MODE_LVDS;
4064 else
4065 dpll |= DPLLB_MODE_DAC_SERIAL;
4066 if (is_sdvo) {
4067 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4068 if (pixel_multiplier > 1) {
4069 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4070 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4071 }
4072 dpll |= DPLL_DVO_HIGH_SPEED;
4073 }
4074 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4075 dpll |= DPLL_DVO_HIGH_SPEED;
4076
4077 /* compute bitmask from p1 value */
4078 if (IS_PINEVIEW(dev))
4079 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4080 else {
4081 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4082 if (IS_G4X(dev) && reduced_clock)
4083 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4084 }
4085 switch (clock->p2) {
4086 case 5:
4087 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4088 break;
4089 case 7:
4090 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4091 break;
4092 case 10:
4093 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4094 break;
4095 case 14:
4096 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4097 break;
4098 }
4099 if (INTEL_INFO(dev)->gen >= 4)
4100 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4101
4102 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4103 dpll |= PLL_REF_INPUT_TVCLKINBC;
4104 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4105 /* XXX: just matching BIOS for now */
4106 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4107 dpll |= 3;
4108 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4109 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4110 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4111 else
4112 dpll |= PLL_REF_INPUT_DREFCLK;
4113
4114 dpll |= DPLL_VCO_ENABLE;
4115 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4116 POSTING_READ(DPLL(pipe));
4117 udelay(150);
4118
4119 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4120 * This is an exception to the general rule that mode_set doesn't turn
4121 * things on.
4122 */
4123 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4124 intel_update_lvds(crtc, clock, adjusted_mode);
4125
4126 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4127 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4128
4129 I915_WRITE(DPLL(pipe), dpll);
4130
4131 /* Wait for the clocks to stabilize. */
4132 POSTING_READ(DPLL(pipe));
4133 udelay(150);
4134
4135 if (INTEL_INFO(dev)->gen >= 4) {
4136 u32 temp = 0;
4137 if (is_sdvo) {
4138 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4139 if (temp > 1)
4140 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4141 else
4142 temp = 0;
4143 }
4144 I915_WRITE(DPLL_MD(pipe), temp);
4145 } else {
4146 /* The pixel multiplier can only be updated once the
4147 * DPLL is enabled and the clocks are stable.
4148 *
4149 * So write it again.
4150 */
4151 I915_WRITE(DPLL(pipe), dpll);
4152 }
4153}
4154
4155static void i8xx_update_pll(struct drm_crtc *crtc,
4156 struct drm_display_mode *adjusted_mode,
4157 intel_clock_t *clock,
4158 int num_connectors)
4159{
4160 struct drm_device *dev = crtc->dev;
4161 struct drm_i915_private *dev_priv = dev->dev_private;
4162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4163 int pipe = intel_crtc->pipe;
4164 u32 dpll;
4165
4166 dpll = DPLL_VGA_MODE_DIS;
4167
4168 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4169 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4170 } else {
4171 if (clock->p1 == 2)
4172 dpll |= PLL_P1_DIVIDE_BY_TWO;
4173 else
4174 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4175 if (clock->p2 == 4)
4176 dpll |= PLL_P2_DIVIDE_BY_4;
4177 }
4178
4179 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4180 /* XXX: just matching BIOS for now */
4181 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4182 dpll |= 3;
4183 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4184 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4185 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4186 else
4187 dpll |= PLL_REF_INPUT_DREFCLK;
4188
4189 dpll |= DPLL_VCO_ENABLE;
4190 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4191 POSTING_READ(DPLL(pipe));
4192 udelay(150);
4193
4194 I915_WRITE(DPLL(pipe), dpll);
4195
4196 /* Wait for the clocks to stabilize. */
4197 POSTING_READ(DPLL(pipe));
4198 udelay(150);
4199
4200 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4201 * This is an exception to the general rule that mode_set doesn't turn
4202 * things on.
4203 */
4204 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4205 intel_update_lvds(crtc, clock, adjusted_mode);
4206
4207 /* The pixel multiplier can only be updated once the
4208 * DPLL is enabled and the clocks are stable.
4209 *
4210 * So write it again.
4211 */
4212 I915_WRITE(DPLL(pipe), dpll);
4213}
4214
Eric Anholtf564048e2011-03-30 13:01:02 -07004215static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4216 struct drm_display_mode *mode,
4217 struct drm_display_mode *adjusted_mode,
4218 int x, int y,
4219 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08004220{
4221 struct drm_device *dev = crtc->dev;
4222 struct drm_i915_private *dev_priv = dev->dev_private;
4223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4224 int pipe = intel_crtc->pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07004225 int plane = intel_crtc->plane;
Eric Anholtc751ce42010-03-25 11:48:48 -07004226 int refclk, num_connectors = 0;
Jesse Barnes652c3932009-08-17 13:31:43 -07004227 intel_clock_t clock, reduced_clock;
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004228 u32 dspcntr, pipeconf, vsyncshift;
4229 bool ok, has_reduced_clock = false, is_sdvo = false;
4230 bool is_lvds = false, is_tv = false, is_dp = false;
Chris Wilson5eddb702010-09-11 13:48:45 +01004231 struct intel_encoder *encoder;
Ma Lingd4906092009-03-18 20:13:27 +08004232 const intel_limit_t *limit;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004233 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08004234
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02004235 for_each_encoder_on_crtc(dev, crtc, encoder) {
Chris Wilson5eddb702010-09-11 13:48:45 +01004236 switch (encoder->type) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004237 case INTEL_OUTPUT_LVDS:
4238 is_lvds = true;
4239 break;
4240 case INTEL_OUTPUT_SDVO:
Eric Anholt7d573822009-01-02 13:33:00 -08004241 case INTEL_OUTPUT_HDMI:
Jesse Barnes79e53942008-11-07 14:24:08 -08004242 is_sdvo = true;
Chris Wilson5eddb702010-09-11 13:48:45 +01004243 if (encoder->needs_tv_clock)
Jesse Barnese2f0ba92009-02-02 15:11:52 -08004244 is_tv = true;
Jesse Barnes79e53942008-11-07 14:24:08 -08004245 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004246 case INTEL_OUTPUT_TVOUT:
4247 is_tv = true;
4248 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004249 case INTEL_OUTPUT_DISPLAYPORT:
4250 is_dp = true;
4251 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004252 }
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004253
Eric Anholtc751ce42010-03-25 11:48:48 -07004254 num_connectors++;
Jesse Barnes79e53942008-11-07 14:24:08 -08004255 }
4256
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004257 refclk = i9xx_get_refclk(crtc, num_connectors);
Jesse Barnes79e53942008-11-07 14:24:08 -08004258
Ma Lingd4906092009-03-18 20:13:27 +08004259 /*
4260 * Returns a set of divisors for the desired target clock with the given
4261 * refclk, or FALSE. The returned values represent the clock equation:
4262 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4263 */
Chris Wilson1b894b52010-12-14 20:04:54 +00004264 limit = intel_limit(crtc, refclk);
Sean Paulcec2f352012-01-10 15:09:36 -08004265 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4266 &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004267 if (!ok) {
4268 DRM_ERROR("Couldn't find PLL settings for mode!\n");
Eric Anholtf564048e2011-03-30 13:01:02 -07004269 return -EINVAL;
4270 }
4271
4272 /* Ensure that the cursor is valid for the new mode before changing... */
4273 intel_crtc_update_cursor(crtc, true);
4274
4275 if (is_lvds && dev_priv->lvds_downclock_avail) {
Sean Paulcec2f352012-01-10 15:09:36 -08004276 /*
4277 * Ensure we match the reduced clock's P to the target clock.
4278 * If the clocks don't match, we can't switch the display clock
4279 * by using the FP0/FP1. In such case we will disable the LVDS
4280 * downclock feature.
4281 */
Eric Anholtf564048e2011-03-30 13:01:02 -07004282 has_reduced_clock = limit->find_pll(limit, crtc,
4283 dev_priv->lvds_downclock,
4284 refclk,
Sean Paulcec2f352012-01-10 15:09:36 -08004285 &clock,
Eric Anholtf564048e2011-03-30 13:01:02 -07004286 &reduced_clock);
Eric Anholtf564048e2011-03-30 13:01:02 -07004287 }
4288
Jesse Barnesc65d77d2011-12-15 12:30:36 -08004289 if (is_sdvo && is_tv)
4290 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
Eric Anholtf564048e2011-03-30 13:01:02 -07004291
Jesse Barnesa7516a02011-12-15 12:30:37 -08004292 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4293 &reduced_clock : NULL);
Eric Anholtf564048e2011-03-30 13:01:02 -07004294
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004295 if (IS_GEN2(dev))
4296 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
Jesse Barnesa0c4da22012-06-15 11:55:13 -07004297 else if (IS_VALLEYVIEW(dev))
4298 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4299 refclk, num_connectors);
Eric Anholtf564048e2011-03-30 13:01:02 -07004300 else
Daniel Vettereb1cbe42012-03-28 23:12:16 +02004301 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4302 has_reduced_clock ? &reduced_clock : NULL,
4303 num_connectors);
Eric Anholtf564048e2011-03-30 13:01:02 -07004304
4305 /* setup pipeconf */
4306 pipeconf = I915_READ(PIPECONF(pipe));
4307
4308 /* Set up the display plane register */
4309 dspcntr = DISPPLANE_GAMMA_ENABLE;
4310
Eric Anholt929c77f2011-03-30 13:01:04 -07004311 if (pipe == 0)
4312 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4313 else
4314 dspcntr |= DISPPLANE_SEL_PIPE_B;
Eric Anholtf564048e2011-03-30 13:01:02 -07004315
4316 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4317 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4318 * core speed.
4319 *
4320 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4321 * pipe == 0 check?
4322 */
4323 if (mode->clock >
4324 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4325 pipeconf |= PIPECONF_DOUBLE_WIDE;
4326 else
4327 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4328 }
4329
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004330 /* default to 8bpc */
4331 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4332 if (is_dp) {
4333 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4334 pipeconf |= PIPECONF_BPP_6 |
4335 PIPECONF_DITHER_EN |
4336 PIPECONF_DITHER_TYPE_SP;
4337 }
4338 }
4339
Eric Anholtf564048e2011-03-30 13:01:02 -07004340 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4341 drm_mode_debug_printmodeline(mode);
4342
Jesse Barnesa7516a02011-12-15 12:30:37 -08004343 if (HAS_PIPE_CXSR(dev)) {
4344 if (intel_crtc->lowfreq_avail) {
Eric Anholtf564048e2011-03-30 13:01:02 -07004345 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4346 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
Jesse Barnesa7516a02011-12-15 12:30:37 -08004347 } else {
Eric Anholtf564048e2011-03-30 13:01:02 -07004348 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4349 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4350 }
4351 }
4352
Keith Packard617cf882012-02-08 13:53:38 -08004353 pipeconf &= ~PIPECONF_INTERLACE_MASK;
Daniel Vetterdbb02572012-01-28 14:49:23 +01004354 if (!IS_GEN2(dev) &&
4355 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Eric Anholtf564048e2011-03-30 13:01:02 -07004356 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4357 /* the chip adds 2 halflines automatically */
Eric Anholtf564048e2011-03-30 13:01:02 -07004358 adjusted_mode->crtc_vtotal -= 1;
Eric Anholtf564048e2011-03-30 13:01:02 -07004359 adjusted_mode->crtc_vblank_end -= 1;
Daniel Vetter0529a0d2012-01-28 14:49:24 +01004360 vsyncshift = adjusted_mode->crtc_hsync_start
4361 - adjusted_mode->crtc_htotal/2;
4362 } else {
Keith Packard617cf882012-02-08 13:53:38 -08004363 pipeconf |= PIPECONF_PROGRESSIVE;
Daniel Vetter0529a0d2012-01-28 14:49:24 +01004364 vsyncshift = 0;
4365 }
4366
4367 if (!IS_GEN3(dev))
4368 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
Eric Anholtf564048e2011-03-30 13:01:02 -07004369
4370 I915_WRITE(HTOTAL(pipe),
4371 (adjusted_mode->crtc_hdisplay - 1) |
4372 ((adjusted_mode->crtc_htotal - 1) << 16));
4373 I915_WRITE(HBLANK(pipe),
4374 (adjusted_mode->crtc_hblank_start - 1) |
4375 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4376 I915_WRITE(HSYNC(pipe),
4377 (adjusted_mode->crtc_hsync_start - 1) |
4378 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4379
4380 I915_WRITE(VTOTAL(pipe),
4381 (adjusted_mode->crtc_vdisplay - 1) |
4382 ((adjusted_mode->crtc_vtotal - 1) << 16));
4383 I915_WRITE(VBLANK(pipe),
4384 (adjusted_mode->crtc_vblank_start - 1) |
4385 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4386 I915_WRITE(VSYNC(pipe),
4387 (adjusted_mode->crtc_vsync_start - 1) |
4388 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4389
4390 /* pipesrc and dspsize control the size that is scaled from,
4391 * which should always be the user's requested size.
4392 */
Eric Anholt929c77f2011-03-30 13:01:04 -07004393 I915_WRITE(DSPSIZE(plane),
4394 ((mode->vdisplay - 1) << 16) |
4395 (mode->hdisplay - 1));
4396 I915_WRITE(DSPPOS(plane), 0);
Eric Anholtf564048e2011-03-30 13:01:02 -07004397 I915_WRITE(PIPESRC(pipe),
4398 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4399
Eric Anholtf564048e2011-03-30 13:01:02 -07004400 I915_WRITE(PIPECONF(pipe), pipeconf);
4401 POSTING_READ(PIPECONF(pipe));
Eric Anholt929c77f2011-03-30 13:01:04 -07004402 intel_enable_pipe(dev_priv, pipe, false);
Eric Anholtf564048e2011-03-30 13:01:02 -07004403
4404 intel_wait_for_vblank(dev, pipe);
4405
Eric Anholtf564048e2011-03-30 13:01:02 -07004406 I915_WRITE(DSPCNTR(plane), dspcntr);
4407 POSTING_READ(DSPCNTR(plane));
4408
4409 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4410
4411 intel_update_watermarks(dev);
4412
Eric Anholtf564048e2011-03-30 13:01:02 -07004413 return ret;
4414}
4415
Keith Packard9fb526d2011-09-26 22:24:57 -07004416/*
4417 * Initialize reference clocks when the driver loads
4418 */
4419void ironlake_init_pch_refclk(struct drm_device *dev)
Jesse Barnes13d83a62011-08-03 12:59:20 -07004420{
4421 struct drm_i915_private *dev_priv = dev->dev_private;
4422 struct drm_mode_config *mode_config = &dev->mode_config;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004423 struct intel_encoder *encoder;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004424 u32 temp;
4425 bool has_lvds = false;
Keith Packard199e5d72011-09-22 12:01:57 -07004426 bool has_cpu_edp = false;
4427 bool has_pch_edp = false;
4428 bool has_panel = false;
Keith Packard99eb6a02011-09-26 14:29:12 -07004429 bool has_ck505 = false;
4430 bool can_ssc = false;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004431
4432 /* We need to take the global config into account */
Keith Packard199e5d72011-09-22 12:01:57 -07004433 list_for_each_entry(encoder, &mode_config->encoder_list,
4434 base.head) {
4435 switch (encoder->type) {
4436 case INTEL_OUTPUT_LVDS:
4437 has_panel = true;
4438 has_lvds = true;
4439 break;
4440 case INTEL_OUTPUT_EDP:
4441 has_panel = true;
4442 if (intel_encoder_is_pch_edp(&encoder->base))
4443 has_pch_edp = true;
4444 else
4445 has_cpu_edp = true;
4446 break;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004447 }
4448 }
4449
Keith Packard99eb6a02011-09-26 14:29:12 -07004450 if (HAS_PCH_IBX(dev)) {
4451 has_ck505 = dev_priv->display_clock_mode;
4452 can_ssc = has_ck505;
4453 } else {
4454 has_ck505 = false;
4455 can_ssc = true;
4456 }
4457
4458 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4459 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4460 has_ck505);
Jesse Barnes13d83a62011-08-03 12:59:20 -07004461
4462 /* Ironlake: try to setup display ref clock before DPLL
4463 * enabling. This is only under driver's control after
4464 * PCH B stepping, previous chipset stepping should be
4465 * ignoring this setting.
4466 */
4467 temp = I915_READ(PCH_DREF_CONTROL);
4468 /* Always enable nonspread source */
4469 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004470
Keith Packard99eb6a02011-09-26 14:29:12 -07004471 if (has_ck505)
4472 temp |= DREF_NONSPREAD_CK505_ENABLE;
4473 else
4474 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004475
Keith Packard199e5d72011-09-22 12:01:57 -07004476 if (has_panel) {
4477 temp &= ~DREF_SSC_SOURCE_MASK;
4478 temp |= DREF_SSC_SOURCE_ENABLE;
Jesse Barnes13d83a62011-08-03 12:59:20 -07004479
Keith Packard199e5d72011-09-22 12:01:57 -07004480 /* SSC must be turned on before enabling the CPU output */
Keith Packard99eb6a02011-09-26 14:29:12 -07004481 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07004482 DRM_DEBUG_KMS("Using SSC on panel\n");
Jesse Barnes13d83a62011-08-03 12:59:20 -07004483 temp |= DREF_SSC1_ENABLE;
Daniel Vettere77166b2012-03-30 22:14:05 +02004484 } else
4485 temp &= ~DREF_SSC1_ENABLE;
Keith Packard199e5d72011-09-22 12:01:57 -07004486
4487 /* Get SSC going before enabling the outputs */
4488 I915_WRITE(PCH_DREF_CONTROL, temp);
4489 POSTING_READ(PCH_DREF_CONTROL);
4490 udelay(200);
4491
Jesse Barnes13d83a62011-08-03 12:59:20 -07004492 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4493
4494 /* Enable CPU source on CPU attached eDP */
Keith Packard199e5d72011-09-22 12:01:57 -07004495 if (has_cpu_edp) {
Keith Packard99eb6a02011-09-26 14:29:12 -07004496 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
Keith Packard199e5d72011-09-22 12:01:57 -07004497 DRM_DEBUG_KMS("Using SSC on eDP\n");
Jesse Barnes13d83a62011-08-03 12:59:20 -07004498 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07004499 }
Jesse Barnes13d83a62011-08-03 12:59:20 -07004500 else
4501 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
Keith Packard199e5d72011-09-22 12:01:57 -07004502 } else
4503 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4504
4505 I915_WRITE(PCH_DREF_CONTROL, temp);
4506 POSTING_READ(PCH_DREF_CONTROL);
4507 udelay(200);
4508 } else {
4509 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4510
4511 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4512
4513 /* Turn off CPU output */
4514 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4515
4516 I915_WRITE(PCH_DREF_CONTROL, temp);
4517 POSTING_READ(PCH_DREF_CONTROL);
4518 udelay(200);
4519
4520 /* Turn off the SSC source */
4521 temp &= ~DREF_SSC_SOURCE_MASK;
4522 temp |= DREF_SSC_SOURCE_DISABLE;
4523
4524 /* Turn off SSC1 */
4525 temp &= ~ DREF_SSC1_ENABLE;
4526
Jesse Barnes13d83a62011-08-03 12:59:20 -07004527 I915_WRITE(PCH_DREF_CONTROL, temp);
4528 POSTING_READ(PCH_DREF_CONTROL);
4529 udelay(200);
4530 }
4531}
4532
Jesse Barnesd9d444c2011-09-02 13:03:05 -07004533static int ironlake_get_refclk(struct drm_crtc *crtc)
4534{
4535 struct drm_device *dev = crtc->dev;
4536 struct drm_i915_private *dev_priv = dev->dev_private;
4537 struct intel_encoder *encoder;
Jesse Barnesd9d444c2011-09-02 13:03:05 -07004538 struct intel_encoder *edp_encoder = NULL;
4539 int num_connectors = 0;
4540 bool is_lvds = false;
4541
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02004542 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnesd9d444c2011-09-02 13:03:05 -07004543 switch (encoder->type) {
4544 case INTEL_OUTPUT_LVDS:
4545 is_lvds = true;
4546 break;
4547 case INTEL_OUTPUT_EDP:
4548 edp_encoder = encoder;
4549 break;
4550 }
4551 num_connectors++;
4552 }
4553
4554 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4555 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4556 dev_priv->lvds_ssc_freq);
4557 return dev_priv->lvds_ssc_freq * 1000;
4558 }
4559
4560 return 120000;
4561}
4562
Eric Anholtf564048e2011-03-30 13:01:02 -07004563static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4564 struct drm_display_mode *mode,
4565 struct drm_display_mode *adjusted_mode,
4566 int x, int y,
4567 struct drm_framebuffer *old_fb)
Jesse Barnes79e53942008-11-07 14:24:08 -08004568{
4569 struct drm_device *dev = crtc->dev;
4570 struct drm_i915_private *dev_priv = dev->dev_private;
4571 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4572 int pipe = intel_crtc->pipe;
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004573 int plane = intel_crtc->plane;
Jesse Barnes79e53942008-11-07 14:24:08 -08004574 int refclk, num_connectors = 0;
4575 intel_clock_t clock, reduced_clock;
4576 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
Eric Anholta07d6782011-03-30 13:01:08 -07004577 bool ok, has_reduced_clock = false, is_sdvo = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08004578 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
Jesse Barnese3aef172012-04-10 11:58:03 -07004579 struct intel_encoder *encoder, *edp_encoder = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08004580 const intel_limit_t *limit;
4581 int ret;
4582 struct fdi_m_n m_n = {0};
Eric Anholtfae14982011-03-30 13:01:09 -07004583 u32 temp;
Jesse Barnes5a354202011-06-24 12:19:22 -07004584 int target_clock, pixel_multiplier, lane, link_bw, factor;
4585 unsigned int pipe_bpp;
4586 bool dither;
Jesse Barnese3aef172012-04-10 11:58:03 -07004587 bool is_cpu_edp = false, is_pch_edp = false;
Jesse Barnes79e53942008-11-07 14:24:08 -08004588
Daniel Vetter6c2b7c122012-07-05 09:50:24 +02004589 for_each_encoder_on_crtc(dev, crtc, encoder) {
Jesse Barnes79e53942008-11-07 14:24:08 -08004590 switch (encoder->type) {
4591 case INTEL_OUTPUT_LVDS:
4592 is_lvds = true;
4593 break;
4594 case INTEL_OUTPUT_SDVO:
4595 case INTEL_OUTPUT_HDMI:
4596 is_sdvo = true;
4597 if (encoder->needs_tv_clock)
4598 is_tv = true;
4599 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004600 case INTEL_OUTPUT_TVOUT:
4601 is_tv = true;
4602 break;
4603 case INTEL_OUTPUT_ANALOG:
4604 is_crt = true;
4605 break;
4606 case INTEL_OUTPUT_DISPLAYPORT:
4607 is_dp = true;
4608 break;
4609 case INTEL_OUTPUT_EDP:
Jesse Barnese3aef172012-04-10 11:58:03 -07004610 is_dp = true;
4611 if (intel_encoder_is_pch_edp(&encoder->base))
4612 is_pch_edp = true;
4613 else
4614 is_cpu_edp = true;
4615 edp_encoder = encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08004616 break;
4617 }
4618
Kristian Høgsberg43565a02009-02-13 20:56:52 -05004619 num_connectors++;
4620 }
4621
Jesse Barnesd9d444c2011-09-02 13:03:05 -07004622 refclk = ironlake_get_refclk(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08004623
4624 /*
4625 * Returns a set of divisors for the desired target clock with the given
4626 * refclk, or FALSE. The returned values represent the clock equation:
4627 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4628 */
4629 limit = intel_limit(crtc, refclk);
Sean Paulcec2f352012-01-10 15:09:36 -08004630 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4631 &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08004632 if (!ok) {
4633 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4634 return -EINVAL;
4635 }
4636
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004637 /* Ensure that the cursor is valid for the new mode before changing... */
Chris Wilson6b383a72010-09-13 13:54:26 +01004638 intel_crtc_update_cursor(crtc, true);
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01004639
Zhao Yakuiddc90032010-01-06 22:05:56 +08004640 if (is_lvds && dev_priv->lvds_downclock_avail) {
Sean Paulcec2f352012-01-10 15:09:36 -08004641 /*
4642 * Ensure we match the reduced clock's P to the target clock.
4643 * If the clocks don't match, we can't switch the display clock
4644 * by using the FP0/FP1. In such case we will disable the LVDS
4645 * downclock feature.
4646 */
Zhao Yakuiddc90032010-01-06 22:05:56 +08004647 has_reduced_clock = limit->find_pll(limit, crtc,
Chris Wilson5eddb702010-09-11 13:48:45 +01004648 dev_priv->lvds_downclock,
4649 refclk,
Sean Paulcec2f352012-01-10 15:09:36 -08004650 &clock,
Chris Wilson5eddb702010-09-11 13:48:45 +01004651 &reduced_clock);
Jesse Barnes652c3932009-08-17 13:31:43 -07004652 }
Daniel Vetter61e96532012-05-30 14:52:26 +02004653
4654 if (is_sdvo && is_tv)
4655 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4656
Zhenyu Wang7026d4a2009-03-24 14:02:43 +08004657
Zhenyu Wang2c072452009-06-05 15:38:42 +08004658 /* FDI link */
Eric Anholt8febb292011-03-30 13:01:07 -07004659 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4660 lane = 0;
4661 /* CPU eDP doesn't require FDI link, so just set DP M/N
4662 according to current link config */
Jesse Barnese3aef172012-04-10 11:58:03 -07004663 if (is_cpu_edp) {
Jesse Barnese3aef172012-04-10 11:58:03 -07004664 intel_edp_link_config(edp_encoder, &lane, &link_bw);
Eric Anholt8febb292011-03-30 13:01:07 -07004665 } else {
Eric Anholt8febb292011-03-30 13:01:07 -07004666 /* FDI is a binary signal running at ~2.7GHz, encoding
4667 * each output octet as 10 bits. The actual frequency
4668 * is stored as a divider into a 100MHz clock, and the
4669 * mode pixel clock is stored in units of 1KHz.
4670 * Hence the bw of each lane in terms of the mode signal
4671 * is:
4672 */
4673 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004674 }
Zhenyu Wang2c072452009-06-05 15:38:42 +08004675
Daniel Vetter94bf2ce2012-06-04 18:39:19 +02004676 /* [e]DP over FDI requires target mode clock instead of link clock. */
4677 if (edp_encoder)
4678 target_clock = intel_edp_target_clock(edp_encoder, mode);
4679 else if (is_dp)
4680 target_clock = mode->clock;
4681 else
4682 target_clock = adjusted_mode->clock;
4683
Eric Anholt8febb292011-03-30 13:01:07 -07004684 /* determine panel color depth */
4685 temp = I915_READ(PIPECONF(pipe));
4686 temp &= ~PIPE_BPC_MASK;
Adam Jackson3b5c78a2011-12-13 15:41:00 -08004687 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
Jesse Barnes5a354202011-06-24 12:19:22 -07004688 switch (pipe_bpp) {
4689 case 18:
4690 temp |= PIPE_6BPC;
4691 break;
4692 case 24:
Eric Anholt8febb292011-03-30 13:01:07 -07004693 temp |= PIPE_8BPC;
Eric Anholt8febb292011-03-30 13:01:07 -07004694 break;
Jesse Barnes5a354202011-06-24 12:19:22 -07004695 case 30:
4696 temp |= PIPE_10BPC;
Eric Anholt8febb292011-03-30 13:01:07 -07004697 break;
Jesse Barnes5a354202011-06-24 12:19:22 -07004698 case 36:
4699 temp |= PIPE_12BPC;
Eric Anholt8febb292011-03-30 13:01:07 -07004700 break;
4701 default:
Jesse Barnes62ac41a2011-07-28 12:55:14 -07004702 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4703 pipe_bpp);
Jesse Barnes5a354202011-06-24 12:19:22 -07004704 temp |= PIPE_8BPC;
4705 pipe_bpp = 24;
4706 break;
Eric Anholt8febb292011-03-30 13:01:07 -07004707 }
4708
Jesse Barnes5a354202011-06-24 12:19:22 -07004709 intel_crtc->bpp = pipe_bpp;
4710 I915_WRITE(PIPECONF(pipe), temp);
4711
Eric Anholt8febb292011-03-30 13:01:07 -07004712 if (!lane) {
4713 /*
4714 * Account for spread spectrum to avoid
4715 * oversubscribing the link. Max center spread
4716 * is 2.5%; use 5% for safety's sake.
4717 */
Jesse Barnes5a354202011-06-24 12:19:22 -07004718 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
Eric Anholt8febb292011-03-30 13:01:07 -07004719 lane = bps / (link_bw * 8) + 1;
4720 }
4721
4722 intel_crtc->fdi_lanes = lane;
4723
4724 if (pixel_multiplier > 1)
4725 link_bw *= pixel_multiplier;
Jesse Barnes5a354202011-06-24 12:19:22 -07004726 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4727 &m_n);
Eric Anholt8febb292011-03-30 13:01:07 -07004728
Eric Anholta07d6782011-03-30 13:01:08 -07004729 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4730 if (has_reduced_clock)
4731 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4732 reduced_clock.m2;
Jesse Barnes79e53942008-11-07 14:24:08 -08004733
Chris Wilsonc1858122010-12-03 21:35:48 +00004734 /* Enable autotuning of the PLL clock (if permissible) */
Eric Anholt8febb292011-03-30 13:01:07 -07004735 factor = 21;
4736 if (is_lvds) {
4737 if ((intel_panel_use_ssc(dev_priv) &&
4738 dev_priv->lvds_ssc_freq == 100) ||
4739 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4740 factor = 25;
4741 } else if (is_sdvo && is_tv)
4742 factor = 20;
Chris Wilsonc1858122010-12-03 21:35:48 +00004743
Jesse Barnescb0e0932011-07-28 14:50:30 -07004744 if (clock.m < factor * clock.n)
Eric Anholt8febb292011-03-30 13:01:07 -07004745 fp |= FP_CB_TUNE;
Chris Wilsonc1858122010-12-03 21:35:48 +00004746
Chris Wilson5eddb702010-09-11 13:48:45 +01004747 dpll = 0;
Zhenyu Wang2c072452009-06-05 15:38:42 +08004748
Eric Anholta07d6782011-03-30 13:01:08 -07004749 if (is_lvds)
4750 dpll |= DPLLB_MODE_LVDS;
4751 else
4752 dpll |= DPLLB_MODE_DAC_SERIAL;
4753 if (is_sdvo) {
4754 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4755 if (pixel_multiplier > 1) {
4756 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
Jesse Barnes79e53942008-11-07 14:24:08 -08004757 }
Eric Anholta07d6782011-03-30 13:01:08 -07004758 dpll |= DPLL_DVO_HIGH_SPEED;
4759 }
Jesse Barnese3aef172012-04-10 11:58:03 -07004760 if (is_dp && !is_cpu_edp)
Eric Anholta07d6782011-03-30 13:01:08 -07004761 dpll |= DPLL_DVO_HIGH_SPEED;
Jesse Barnes79e53942008-11-07 14:24:08 -08004762
Eric Anholta07d6782011-03-30 13:01:08 -07004763 /* compute bitmask from p1 value */
4764 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4765 /* also FPA1 */
4766 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4767
4768 switch (clock.p2) {
4769 case 5:
4770 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4771 break;
4772 case 7:
4773 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4774 break;
4775 case 10:
4776 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4777 break;
4778 case 14:
4779 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4780 break;
Jesse Barnes79e53942008-11-07 14:24:08 -08004781 }
4782
4783 if (is_sdvo && is_tv)
4784 dpll |= PLL_REF_INPUT_TVCLKINBC;
4785 else if (is_tv)
4786 /* XXX: just matching BIOS for now */
4787 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4788 dpll |= 3;
Chris Wilsona7615032011-01-12 17:04:08 +00004789 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
Jesse Barnes79e53942008-11-07 14:24:08 -08004790 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4791 else
4792 dpll |= PLL_REF_INPUT_DREFCLK;
4793
4794 /* setup pipeconf */
Chris Wilson5eddb702010-09-11 13:48:45 +01004795 pipeconf = I915_READ(PIPECONF(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004796
4797 /* Set up the display plane register */
4798 dspcntr = DISPPLANE_GAMMA_ENABLE;
4799
Jesse Barnesf7cb34d2011-10-12 10:49:14 -07004800 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08004801 drm_mode_debug_printmodeline(mode);
4802
Eugeni Dodonov9d82aa12012-05-09 15:37:17 -03004803 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4804 * pre-Haswell/LPT generation */
4805 if (HAS_PCH_LPT(dev)) {
4806 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4807 pipe);
4808 } else if (!is_cpu_edp) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004809 struct intel_pch_pll *pll;
Chris Wilson5eddb702010-09-11 13:48:45 +01004810
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004811 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4812 if (pll == NULL) {
4813 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4814 pipe);
Jesse Barnes4b645f12011-10-12 09:51:31 -07004815 return -EINVAL;
4816 }
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004817 } else
4818 intel_put_pch_pll(intel_crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08004819
4820 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4821 * This is an exception to the general rule that mode_set doesn't turn
4822 * things on.
4823 */
4824 if (is_lvds) {
Eric Anholtfae14982011-03-30 13:01:09 -07004825 temp = I915_READ(PCH_LVDS);
Chris Wilson5eddb702010-09-11 13:48:45 +01004826 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
Jesse Barnes7885d202012-01-12 14:51:17 -08004827 if (HAS_PCH_CPT(dev)) {
4828 temp &= ~PORT_TRANS_SEL_MASK;
Jesse Barnes4b645f12011-10-12 09:51:31 -07004829 temp |= PORT_TRANS_SEL_CPT(pipe);
Jesse Barnes7885d202012-01-12 14:51:17 -08004830 } else {
4831 if (pipe == 1)
4832 temp |= LVDS_PIPEB_SELECT;
4833 else
4834 temp &= ~LVDS_PIPEB_SELECT;
4835 }
Jesse Barnes4b645f12011-10-12 09:51:31 -07004836
Zhao Yakuia3e17eb2009-10-10 10:42:37 +08004837 /* set the corresponsding LVDS_BORDER bit */
Chris Wilson5eddb702010-09-11 13:48:45 +01004838 temp |= dev_priv->lvds_border_bits;
Jesse Barnes79e53942008-11-07 14:24:08 -08004839 /* Set the B0-B3 data pairs corresponding to whether we're going to
4840 * set the DPLLs for dual-channel mode or not.
4841 */
4842 if (clock.p2 == 7)
Chris Wilson5eddb702010-09-11 13:48:45 +01004843 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
Jesse Barnes79e53942008-11-07 14:24:08 -08004844 else
Chris Wilson5eddb702010-09-11 13:48:45 +01004845 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
Jesse Barnes79e53942008-11-07 14:24:08 -08004846
4847 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4848 * appropriately here, but we need to look more thoroughly into how
4849 * panels behave in the two modes.
4850 */
Chris Wilson284d5df2012-04-14 17:41:59 +01004851 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
Bryan Freedaa9b5002011-01-12 13:43:19 -08004852 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01004853 temp |= LVDS_HSYNC_POLARITY;
Bryan Freedaa9b5002011-01-12 13:43:19 -08004854 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
Chris Wilson284d5df2012-04-14 17:41:59 +01004855 temp |= LVDS_VSYNC_POLARITY;
Eric Anholtfae14982011-03-30 13:01:09 -07004856 I915_WRITE(PCH_LVDS, temp);
Jesse Barnes79e53942008-11-07 14:24:08 -08004857 }
Jesse Barnes434ed092010-09-07 14:48:06 -07004858
Eric Anholt8febb292011-03-30 13:01:07 -07004859 pipeconf &= ~PIPECONF_DITHER_EN;
4860 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
Jesse Barnes5a354202011-06-24 12:19:22 -07004861 if ((is_lvds && dev_priv->lvds_dither) || dither) {
Eric Anholt8febb292011-03-30 13:01:07 -07004862 pipeconf |= PIPECONF_DITHER_EN;
Daniel Vetterf74974c2011-10-11 17:27:51 +02004863 pipeconf |= PIPECONF_DITHER_TYPE_SP;
Jesse Barnes434ed092010-09-07 14:48:06 -07004864 }
Jesse Barnese3aef172012-04-10 11:58:03 -07004865 if (is_dp && !is_cpu_edp) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004866 intel_dp_set_m_n(crtc, mode, adjusted_mode);
Eric Anholt8febb292011-03-30 13:01:07 -07004867 } else {
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004868 /* For non-DP output, clear any trans DP clock recovery setting.*/
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08004869 I915_WRITE(TRANSDATA_M1(pipe), 0);
4870 I915_WRITE(TRANSDATA_N1(pipe), 0);
4871 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4872 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
Zhenyu Wang8db9d772010-04-07 16:15:54 +08004873 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004874
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004875 if (intel_crtc->pch_pll) {
4876 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
Chris Wilson5eddb702010-09-11 13:48:45 +01004877
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004878 /* Wait for the clocks to stabilize. */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004879 POSTING_READ(intel_crtc->pch_pll->pll_reg);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004880 udelay(150);
4881
Eric Anholt8febb292011-03-30 13:01:07 -07004882 /* The pixel multiplier can only be updated once the
4883 * DPLL is enabled and the clocks are stable.
4884 *
4885 * So write it again.
4886 */
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004887 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
Jesse Barnes79e53942008-11-07 14:24:08 -08004888 }
Jesse Barnes79e53942008-11-07 14:24:08 -08004889
Chris Wilson5eddb702010-09-11 13:48:45 +01004890 intel_crtc->lowfreq_avail = false;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004891 if (intel_crtc->pch_pll) {
Jesse Barnes4b645f12011-10-12 09:51:31 -07004892 if (is_lvds && has_reduced_clock && i915_powersave) {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004893 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
Jesse Barnes4b645f12011-10-12 09:51:31 -07004894 intel_crtc->lowfreq_avail = true;
Jesse Barnes4b645f12011-10-12 09:51:31 -07004895 } else {
Jesse Barnesee7b9f92012-04-20 17:11:53 +01004896 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
Jesse Barnes652c3932009-08-17 13:31:43 -07004897 }
4898 }
4899
Keith Packard617cf882012-02-08 13:53:38 -08004900 pipeconf &= ~PIPECONF_INTERLACE_MASK;
Krzysztof Halasa734b4152010-05-25 18:41:46 +02004901 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
Daniel Vetter5def4742012-01-28 14:49:22 +01004902 pipeconf |= PIPECONF_INTERLACED_ILK;
Krzysztof Halasa734b4152010-05-25 18:41:46 +02004903 /* the chip adds 2 halflines automatically */
Krzysztof Halasa734b4152010-05-25 18:41:46 +02004904 adjusted_mode->crtc_vtotal -= 1;
Krzysztof Halasa734b4152010-05-25 18:41:46 +02004905 adjusted_mode->crtc_vblank_end -= 1;
Daniel Vetter0529a0d2012-01-28 14:49:24 +01004906 I915_WRITE(VSYNCSHIFT(pipe),
4907 adjusted_mode->crtc_hsync_start
4908 - adjusted_mode->crtc_htotal/2);
4909 } else {
Keith Packard617cf882012-02-08 13:53:38 -08004910 pipeconf |= PIPECONF_PROGRESSIVE;
Daniel Vetter0529a0d2012-01-28 14:49:24 +01004911 I915_WRITE(VSYNCSHIFT(pipe), 0);
4912 }
Krzysztof Halasa734b4152010-05-25 18:41:46 +02004913
Chris Wilson5eddb702010-09-11 13:48:45 +01004914 I915_WRITE(HTOTAL(pipe),
4915 (adjusted_mode->crtc_hdisplay - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004916 ((adjusted_mode->crtc_htotal - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004917 I915_WRITE(HBLANK(pipe),
4918 (adjusted_mode->crtc_hblank_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004919 ((adjusted_mode->crtc_hblank_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004920 I915_WRITE(HSYNC(pipe),
4921 (adjusted_mode->crtc_hsync_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004922 ((adjusted_mode->crtc_hsync_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004923
4924 I915_WRITE(VTOTAL(pipe),
4925 (adjusted_mode->crtc_vdisplay - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004926 ((adjusted_mode->crtc_vtotal - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004927 I915_WRITE(VBLANK(pipe),
4928 (adjusted_mode->crtc_vblank_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004929 ((adjusted_mode->crtc_vblank_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004930 I915_WRITE(VSYNC(pipe),
4931 (adjusted_mode->crtc_vsync_start - 1) |
Jesse Barnes79e53942008-11-07 14:24:08 -08004932 ((adjusted_mode->crtc_vsync_end - 1) << 16));
Chris Wilson5eddb702010-09-11 13:48:45 +01004933
Eric Anholt8febb292011-03-30 13:01:07 -07004934 /* pipesrc controls the size that is scaled from, which should
4935 * always be the user's requested size.
Jesse Barnes79e53942008-11-07 14:24:08 -08004936 */
Chris Wilson5eddb702010-09-11 13:48:45 +01004937 I915_WRITE(PIPESRC(pipe),
4938 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
Zhenyu Wang2c072452009-06-05 15:38:42 +08004939
Eric Anholt8febb292011-03-30 13:01:07 -07004940 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4941 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4942 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4943 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
Zhenyu Wang2c072452009-06-05 15:38:42 +08004944
Jesse Barnese3aef172012-04-10 11:58:03 -07004945 if (is_cpu_edp)
Eric Anholt8febb292011-03-30 13:01:07 -07004946 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
Zhenyu Wang2c072452009-06-05 15:38:42 +08004947
Chris Wilson5eddb702010-09-11 13:48:45 +01004948 I915_WRITE(PIPECONF(pipe), pipeconf);
4949 POSTING_READ(PIPECONF(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08004950
Jesse Barnes9d0498a2010-08-18 13:20:54 -07004951 intel_wait_for_vblank(dev, pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08004952
Chris Wilson5eddb702010-09-11 13:48:45 +01004953 I915_WRITE(DSPCNTR(plane), dspcntr);
Jesse Barnesb24e7172011-01-04 15:09:30 -08004954 POSTING_READ(DSPCNTR(plane));
Jesse Barnes79e53942008-11-07 14:24:08 -08004955
Chris Wilson5c3b82e2009-02-11 13:25:09 +00004956 ret = intel_pipe_set_base(crtc, x, y, old_fb);
Shaohua Li7662c8b2009-06-26 11:23:55 +08004957
4958 intel_update_watermarks(dev);
4959
Eugeni Dodonov1f8eeab2012-05-09 15:37:24 -03004960 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4961
Chris Wilson1f803ee2009-06-06 09:45:59 +01004962 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08004963}
4964
Eric Anholtf564048e2011-03-30 13:01:02 -07004965static int intel_crtc_mode_set(struct drm_crtc *crtc,
4966 struct drm_display_mode *mode,
4967 struct drm_display_mode *adjusted_mode,
4968 int x, int y,
4969 struct drm_framebuffer *old_fb)
4970{
4971 struct drm_device *dev = crtc->dev;
4972 struct drm_i915_private *dev_priv = dev->dev_private;
Eric Anholt0b701d22011-03-30 13:01:03 -07004973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4974 int pipe = intel_crtc->pipe;
Eric Anholtf564048e2011-03-30 13:01:02 -07004975 int ret;
4976
Eric Anholt0b701d22011-03-30 13:01:03 -07004977 drm_vblank_pre_modeset(dev, pipe);
4978
Eric Anholtf564048e2011-03-30 13:01:02 -07004979 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4980 x, y, old_fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08004981 drm_vblank_post_modeset(dev, pipe);
4982
Jesse Barnesd8e70a22011-11-15 10:28:54 -08004983 if (ret)
4984 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4985 else
4986 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
Keith Packard120eced2011-07-27 01:21:40 -07004987
Jesse Barnes79e53942008-11-07 14:24:08 -08004988 return ret;
4989}
4990
Wu Fengguang3a9627f2011-12-09 20:42:19 +08004991static bool intel_eld_uptodate(struct drm_connector *connector,
4992 int reg_eldv, uint32_t bits_eldv,
4993 int reg_elda, uint32_t bits_elda,
4994 int reg_edid)
4995{
4996 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4997 uint8_t *eld = connector->eld;
4998 uint32_t i;
4999
5000 i = I915_READ(reg_eldv);
5001 i &= bits_eldv;
5002
5003 if (!eld[0])
5004 return !i;
5005
5006 if (!i)
5007 return false;
5008
5009 i = I915_READ(reg_elda);
5010 i &= ~bits_elda;
5011 I915_WRITE(reg_elda, i);
5012
5013 for (i = 0; i < eld[2]; i++)
5014 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5015 return false;
5016
5017 return true;
5018}
5019
Wu Fengguange0dac652011-09-05 14:25:34 +08005020static void g4x_write_eld(struct drm_connector *connector,
5021 struct drm_crtc *crtc)
5022{
5023 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5024 uint8_t *eld = connector->eld;
5025 uint32_t eldv;
5026 uint32_t len;
5027 uint32_t i;
5028
5029 i = I915_READ(G4X_AUD_VID_DID);
5030
5031 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5032 eldv = G4X_ELDV_DEVCL_DEVBLC;
5033 else
5034 eldv = G4X_ELDV_DEVCTG;
5035
Wu Fengguang3a9627f2011-12-09 20:42:19 +08005036 if (intel_eld_uptodate(connector,
5037 G4X_AUD_CNTL_ST, eldv,
5038 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5039 G4X_HDMIW_HDMIEDID))
5040 return;
5041
Wu Fengguange0dac652011-09-05 14:25:34 +08005042 i = I915_READ(G4X_AUD_CNTL_ST);
5043 i &= ~(eldv | G4X_ELD_ADDR);
5044 len = (i >> 9) & 0x1f; /* ELD buffer size */
5045 I915_WRITE(G4X_AUD_CNTL_ST, i);
5046
5047 if (!eld[0])
5048 return;
5049
5050 len = min_t(uint8_t, eld[2], len);
5051 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5052 for (i = 0; i < len; i++)
5053 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5054
5055 i = I915_READ(G4X_AUD_CNTL_ST);
5056 i |= eldv;
5057 I915_WRITE(G4X_AUD_CNTL_ST, i);
5058}
5059
5060static void ironlake_write_eld(struct drm_connector *connector,
5061 struct drm_crtc *crtc)
5062{
5063 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5064 uint8_t *eld = connector->eld;
5065 uint32_t eldv;
5066 uint32_t i;
5067 int len;
5068 int hdmiw_hdmiedid;
Wu Fengguangb6daa022012-01-06 14:41:31 -06005069 int aud_config;
Wu Fengguange0dac652011-09-05 14:25:34 +08005070 int aud_cntl_st;
5071 int aud_cntrl_st2;
5072
Wu Fengguangb3f33cb2011-12-09 20:42:17 +08005073 if (HAS_PCH_IBX(connector->dev)) {
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005074 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
Wu Fengguangb6daa022012-01-06 14:41:31 -06005075 aud_config = IBX_AUD_CONFIG_A;
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005076 aud_cntl_st = IBX_AUD_CNTL_ST_A;
5077 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08005078 } else {
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005079 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
Wu Fengguangb6daa022012-01-06 14:41:31 -06005080 aud_config = CPT_AUD_CONFIG_A;
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005081 aud_cntl_st = CPT_AUD_CNTL_ST_A;
5082 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
Wu Fengguange0dac652011-09-05 14:25:34 +08005083 }
5084
5085 i = to_intel_crtc(crtc)->pipe;
5086 hdmiw_hdmiedid += i * 0x100;
5087 aud_cntl_st += i * 0x100;
Wu Fengguangb6daa022012-01-06 14:41:31 -06005088 aud_config += i * 0x100;
Wu Fengguange0dac652011-09-05 14:25:34 +08005089
5090 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5091
5092 i = I915_READ(aud_cntl_st);
5093 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5094 if (!i) {
5095 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5096 /* operate blindly on all ports */
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005097 eldv = IBX_ELD_VALIDB;
5098 eldv |= IBX_ELD_VALIDB << 4;
5099 eldv |= IBX_ELD_VALIDB << 8;
Wu Fengguange0dac652011-09-05 14:25:34 +08005100 } else {
5101 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005102 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
Wu Fengguange0dac652011-09-05 14:25:34 +08005103 }
5104
Wu Fengguang3a9627f2011-12-09 20:42:19 +08005105 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5106 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5107 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
Wu Fengguangb6daa022012-01-06 14:41:31 -06005108 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5109 } else
5110 I915_WRITE(aud_config, 0);
Wu Fengguang3a9627f2011-12-09 20:42:19 +08005111
5112 if (intel_eld_uptodate(connector,
5113 aud_cntrl_st2, eldv,
5114 aud_cntl_st, IBX_ELD_ADDRESS,
5115 hdmiw_hdmiedid))
5116 return;
5117
Wu Fengguange0dac652011-09-05 14:25:34 +08005118 i = I915_READ(aud_cntrl_st2);
5119 i &= ~eldv;
5120 I915_WRITE(aud_cntrl_st2, i);
5121
5122 if (!eld[0])
5123 return;
5124
Wu Fengguange0dac652011-09-05 14:25:34 +08005125 i = I915_READ(aud_cntl_st);
Wu Fengguang1202b4c62011-12-09 20:42:18 +08005126 i &= ~IBX_ELD_ADDRESS;
Wu Fengguange0dac652011-09-05 14:25:34 +08005127 I915_WRITE(aud_cntl_st, i);
5128
5129 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5130 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5131 for (i = 0; i < len; i++)
5132 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5133
5134 i = I915_READ(aud_cntrl_st2);
5135 i |= eldv;
5136 I915_WRITE(aud_cntrl_st2, i);
5137}
5138
5139void intel_write_eld(struct drm_encoder *encoder,
5140 struct drm_display_mode *mode)
5141{
5142 struct drm_crtc *crtc = encoder->crtc;
5143 struct drm_connector *connector;
5144 struct drm_device *dev = encoder->dev;
5145 struct drm_i915_private *dev_priv = dev->dev_private;
5146
5147 connector = drm_select_eld(encoder, mode);
5148 if (!connector)
5149 return;
5150
5151 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5152 connector->base.id,
5153 drm_get_connector_name(connector),
5154 connector->encoder->base.id,
5155 drm_get_encoder_name(connector->encoder));
5156
5157 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5158
5159 if (dev_priv->display.write_eld)
5160 dev_priv->display.write_eld(connector, crtc);
5161}
5162
Jesse Barnes79e53942008-11-07 14:24:08 -08005163/** Loads the palette/gamma unit for the CRTC with the prepared values */
5164void intel_crtc_load_lut(struct drm_crtc *crtc)
5165{
5166 struct drm_device *dev = crtc->dev;
5167 struct drm_i915_private *dev_priv = dev->dev_private;
5168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005169 int palreg = PALETTE(intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005170 int i;
5171
5172 /* The clocks have to be on to load the palette. */
Alban Browaeysaed3f092012-02-24 17:12:45 +00005173 if (!crtc->enabled || !intel_crtc->active)
Jesse Barnes79e53942008-11-07 14:24:08 -08005174 return;
5175
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005176 /* use legacy palette for Ironlake */
Eric Anholtbad720f2009-10-22 16:11:14 -07005177 if (HAS_PCH_SPLIT(dev))
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005178 palreg = LGC_PALETTE(intel_crtc->pipe);
Zhenyu Wang2c072452009-06-05 15:38:42 +08005179
Jesse Barnes79e53942008-11-07 14:24:08 -08005180 for (i = 0; i < 256; i++) {
5181 I915_WRITE(palreg + 4 * i,
5182 (intel_crtc->lut_r[i] << 16) |
5183 (intel_crtc->lut_g[i] << 8) |
5184 intel_crtc->lut_b[i]);
5185 }
5186}
5187
Chris Wilson560b85b2010-08-07 11:01:38 +01005188static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5189{
5190 struct drm_device *dev = crtc->dev;
5191 struct drm_i915_private *dev_priv = dev->dev_private;
5192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5193 bool visible = base != 0;
5194 u32 cntl;
5195
5196 if (intel_crtc->cursor_visible == visible)
5197 return;
5198
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005199 cntl = I915_READ(_CURACNTR);
Chris Wilson560b85b2010-08-07 11:01:38 +01005200 if (visible) {
5201 /* On these chipsets we can only modify the base whilst
5202 * the cursor is disabled.
5203 */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005204 I915_WRITE(_CURABASE, base);
Chris Wilson560b85b2010-08-07 11:01:38 +01005205
5206 cntl &= ~(CURSOR_FORMAT_MASK);
5207 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5208 cntl |= CURSOR_ENABLE |
5209 CURSOR_GAMMA_ENABLE |
5210 CURSOR_FORMAT_ARGB;
5211 } else
5212 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005213 I915_WRITE(_CURACNTR, cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01005214
5215 intel_crtc->cursor_visible = visible;
5216}
5217
5218static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5219{
5220 struct drm_device *dev = crtc->dev;
5221 struct drm_i915_private *dev_priv = dev->dev_private;
5222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5223 int pipe = intel_crtc->pipe;
5224 bool visible = base != 0;
5225
5226 if (intel_crtc->cursor_visible != visible) {
Jesse Barnes548f2452011-02-17 10:40:53 -08005227 uint32_t cntl = I915_READ(CURCNTR(pipe));
Chris Wilson560b85b2010-08-07 11:01:38 +01005228 if (base) {
5229 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5230 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5231 cntl |= pipe << 28; /* Connect to correct pipe */
5232 } else {
5233 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5234 cntl |= CURSOR_MODE_DISABLE;
5235 }
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005236 I915_WRITE(CURCNTR(pipe), cntl);
Chris Wilson560b85b2010-08-07 11:01:38 +01005237
5238 intel_crtc->cursor_visible = visible;
5239 }
5240 /* and commit changes on next vblank */
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08005241 I915_WRITE(CURBASE(pipe), base);
Chris Wilson560b85b2010-08-07 11:01:38 +01005242}
5243
Jesse Barnes65a21cd2011-10-12 11:10:21 -07005244static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5245{
5246 struct drm_device *dev = crtc->dev;
5247 struct drm_i915_private *dev_priv = dev->dev_private;
5248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5249 int pipe = intel_crtc->pipe;
5250 bool visible = base != 0;
5251
5252 if (intel_crtc->cursor_visible != visible) {
5253 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5254 if (base) {
5255 cntl &= ~CURSOR_MODE;
5256 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5257 } else {
5258 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5259 cntl |= CURSOR_MODE_DISABLE;
5260 }
5261 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5262
5263 intel_crtc->cursor_visible = visible;
5264 }
5265 /* and commit changes on next vblank */
5266 I915_WRITE(CURBASE_IVB(pipe), base);
5267}
5268
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005269/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
Chris Wilson6b383a72010-09-13 13:54:26 +01005270static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5271 bool on)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005272{
5273 struct drm_device *dev = crtc->dev;
5274 struct drm_i915_private *dev_priv = dev->dev_private;
5275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5276 int pipe = intel_crtc->pipe;
5277 int x = intel_crtc->cursor_x;
5278 int y = intel_crtc->cursor_y;
Chris Wilson560b85b2010-08-07 11:01:38 +01005279 u32 base, pos;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005280 bool visible;
5281
5282 pos = 0;
5283
Chris Wilson6b383a72010-09-13 13:54:26 +01005284 if (on && crtc->enabled && crtc->fb) {
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005285 base = intel_crtc->cursor_addr;
5286 if (x > (int) crtc->fb->width)
5287 base = 0;
5288
5289 if (y > (int) crtc->fb->height)
5290 base = 0;
5291 } else
5292 base = 0;
5293
5294 if (x < 0) {
5295 if (x + intel_crtc->cursor_width < 0)
5296 base = 0;
5297
5298 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5299 x = -x;
5300 }
5301 pos |= x << CURSOR_X_SHIFT;
5302
5303 if (y < 0) {
5304 if (y + intel_crtc->cursor_height < 0)
5305 base = 0;
5306
5307 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5308 y = -y;
5309 }
5310 pos |= y << CURSOR_Y_SHIFT;
5311
5312 visible = base != 0;
Chris Wilson560b85b2010-08-07 11:01:38 +01005313 if (!visible && !intel_crtc->cursor_visible)
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005314 return;
5315
Eugeni Dodonov0cd83aa2012-04-13 17:08:48 -03005316 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
Jesse Barnes65a21cd2011-10-12 11:10:21 -07005317 I915_WRITE(CURPOS_IVB(pipe), pos);
5318 ivb_update_cursor(crtc, base);
5319 } else {
5320 I915_WRITE(CURPOS(pipe), pos);
5321 if (IS_845G(dev) || IS_I865G(dev))
5322 i845_update_cursor(crtc, base);
5323 else
5324 i9xx_update_cursor(crtc, base);
5325 }
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005326}
5327
Jesse Barnes79e53942008-11-07 14:24:08 -08005328static int intel_crtc_cursor_set(struct drm_crtc *crtc,
Chris Wilson05394f32010-11-08 19:18:58 +00005329 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08005330 uint32_t handle,
5331 uint32_t width, uint32_t height)
5332{
5333 struct drm_device *dev = crtc->dev;
5334 struct drm_i915_private *dev_priv = dev->dev_private;
5335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Chris Wilson05394f32010-11-08 19:18:58 +00005336 struct drm_i915_gem_object *obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005337 uint32_t addr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005338 int ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005339
Zhao Yakui28c97732009-10-09 11:39:41 +08005340 DRM_DEBUG_KMS("\n");
Jesse Barnes79e53942008-11-07 14:24:08 -08005341
5342 /* if we want to turn off the cursor ignore width and height */
5343 if (!handle) {
Zhao Yakui28c97732009-10-09 11:39:41 +08005344 DRM_DEBUG_KMS("cursor off\n");
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005345 addr = 0;
Chris Wilson05394f32010-11-08 19:18:58 +00005346 obj = NULL;
Pierre Willenbrock50044172009-02-23 10:12:15 +10005347 mutex_lock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005348 goto finish;
Jesse Barnes79e53942008-11-07 14:24:08 -08005349 }
5350
5351 /* Currently we only support 64x64 cursors */
5352 if (width != 64 || height != 64) {
5353 DRM_ERROR("we currently only support 64x64 cursors\n");
5354 return -EINVAL;
5355 }
5356
Chris Wilson05394f32010-11-08 19:18:58 +00005357 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
Chris Wilsonc8725222011-02-19 11:31:06 +00005358 if (&obj->base == NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -08005359 return -ENOENT;
5360
Chris Wilson05394f32010-11-08 19:18:58 +00005361 if (obj->base.size < width * height * 4) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005362 DRM_ERROR("buffer is to small\n");
Dave Airlie34b8686e2009-01-15 14:03:07 +10005363 ret = -ENOMEM;
5364 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08005365 }
5366
Dave Airlie71acb5e2008-12-30 20:31:46 +10005367 /* we only need to pin inside GTT if cursor is non-phy */
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005368 mutex_lock(&dev->struct_mutex);
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05005369 if (!dev_priv->info->cursor_needs_physical) {
Chris Wilsond9e86c02010-11-10 16:40:20 +00005370 if (obj->tiling_mode) {
5371 DRM_ERROR("cursor cannot be tiled\n");
5372 ret = -EINVAL;
5373 goto fail_locked;
5374 }
5375
Chris Wilson2da3b9b2011-04-14 09:41:17 +01005376 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
Chris Wilsone7b526b2010-06-02 08:30:48 +01005377 if (ret) {
5378 DRM_ERROR("failed to move cursor bo into the GTT\n");
Chris Wilson2da3b9b2011-04-14 09:41:17 +01005379 goto fail_locked;
Chris Wilsone7b526b2010-06-02 08:30:48 +01005380 }
5381
Chris Wilsond9e86c02010-11-10 16:40:20 +00005382 ret = i915_gem_object_put_fence(obj);
5383 if (ret) {
Chris Wilson2da3b9b2011-04-14 09:41:17 +01005384 DRM_ERROR("failed to release fence for cursor");
Chris Wilsond9e86c02010-11-10 16:40:20 +00005385 goto fail_unpin;
5386 }
5387
Chris Wilson05394f32010-11-08 19:18:58 +00005388 addr = obj->gtt_offset;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005389 } else {
Chris Wilson6eeefaf2010-08-07 11:01:39 +01005390 int align = IS_I830(dev) ? 16 * 1024 : 256;
Chris Wilson05394f32010-11-08 19:18:58 +00005391 ret = i915_gem_attach_phys_object(dev, obj,
Chris Wilson6eeefaf2010-08-07 11:01:39 +01005392 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5393 align);
Dave Airlie71acb5e2008-12-30 20:31:46 +10005394 if (ret) {
5395 DRM_ERROR("failed to attach phys object\n");
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005396 goto fail_locked;
Dave Airlie71acb5e2008-12-30 20:31:46 +10005397 }
Chris Wilson05394f32010-11-08 19:18:58 +00005398 addr = obj->phys_obj->handle->busaddr;
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005399 }
5400
Chris Wilsona6c45cf2010-09-17 00:32:17 +01005401 if (IS_GEN2(dev))
Jesse Barnes14b60392009-05-20 16:47:08 -04005402 I915_WRITE(CURSIZE, (height << 12) | width);
5403
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005404 finish:
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005405 if (intel_crtc->cursor_bo) {
Kristian Høgsbergb295d1b2009-12-16 15:16:17 -05005406 if (dev_priv->info->cursor_needs_physical) {
Chris Wilson05394f32010-11-08 19:18:58 +00005407 if (intel_crtc->cursor_bo != obj)
Dave Airlie71acb5e2008-12-30 20:31:46 +10005408 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5409 } else
5410 i915_gem_object_unpin(intel_crtc->cursor_bo);
Chris Wilson05394f32010-11-08 19:18:58 +00005411 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005412 }
Jesse Barnes80824002009-09-10 15:28:06 -07005413
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005414 mutex_unlock(&dev->struct_mutex);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005415
5416 intel_crtc->cursor_addr = addr;
Chris Wilson05394f32010-11-08 19:18:58 +00005417 intel_crtc->cursor_bo = obj;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005418 intel_crtc->cursor_width = width;
5419 intel_crtc->cursor_height = height;
5420
Chris Wilson6b383a72010-09-13 13:54:26 +01005421 intel_crtc_update_cursor(crtc, true);
Kristian Høgsberg3f8bc372008-12-17 22:14:59 -05005422
Jesse Barnes79e53942008-11-07 14:24:08 -08005423 return 0;
Chris Wilsone7b526b2010-06-02 08:30:48 +01005424fail_unpin:
Chris Wilson05394f32010-11-08 19:18:58 +00005425 i915_gem_object_unpin(obj);
Kristian Høgsberg7f9872e2009-02-13 20:56:49 -05005426fail_locked:
Dave Airlie34b8686e2009-01-15 14:03:07 +10005427 mutex_unlock(&dev->struct_mutex);
Luca Barbieribc9025b2010-02-09 05:49:12 +00005428fail:
Chris Wilson05394f32010-11-08 19:18:58 +00005429 drm_gem_object_unreference_unlocked(&obj->base);
Dave Airlie34b8686e2009-01-15 14:03:07 +10005430 return ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08005431}
5432
5433static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5434{
Jesse Barnes79e53942008-11-07 14:24:08 -08005435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005436
Chris Wilsoncda4b7d2010-07-09 08:45:04 +01005437 intel_crtc->cursor_x = x;
5438 intel_crtc->cursor_y = y;
Jesse Barnes652c3932009-08-17 13:31:43 -07005439
Chris Wilson6b383a72010-09-13 13:54:26 +01005440 intel_crtc_update_cursor(crtc, true);
Jesse Barnes79e53942008-11-07 14:24:08 -08005441
5442 return 0;
5443}
5444
5445/** Sets the color ramps on behalf of RandR */
5446void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5447 u16 blue, int regno)
5448{
5449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5450
5451 intel_crtc->lut_r[regno] = red >> 8;
5452 intel_crtc->lut_g[regno] = green >> 8;
5453 intel_crtc->lut_b[regno] = blue >> 8;
5454}
5455
Dave Airlieb8c00ac2009-10-06 13:54:01 +10005456void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5457 u16 *blue, int regno)
5458{
5459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5460
5461 *red = intel_crtc->lut_r[regno] << 8;
5462 *green = intel_crtc->lut_g[regno] << 8;
5463 *blue = intel_crtc->lut_b[regno] << 8;
5464}
5465
Jesse Barnes79e53942008-11-07 14:24:08 -08005466static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
James Simmons72034252010-08-03 01:33:19 +01005467 u16 *blue, uint32_t start, uint32_t size)
Jesse Barnes79e53942008-11-07 14:24:08 -08005468{
James Simmons72034252010-08-03 01:33:19 +01005469 int end = (start + size > 256) ? 256 : start + size, i;
Jesse Barnes79e53942008-11-07 14:24:08 -08005470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes79e53942008-11-07 14:24:08 -08005471
James Simmons72034252010-08-03 01:33:19 +01005472 for (i = start; i < end; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08005473 intel_crtc->lut_r[i] = red[i] >> 8;
5474 intel_crtc->lut_g[i] = green[i] >> 8;
5475 intel_crtc->lut_b[i] = blue[i] >> 8;
5476 }
5477
5478 intel_crtc_load_lut(crtc);
5479}
5480
5481/**
5482 * Get a pipe with a simple mode set on it for doing load-based monitor
5483 * detection.
5484 *
5485 * It will be up to the load-detect code to adjust the pipe as appropriate for
Eric Anholtc751ce42010-03-25 11:48:48 -07005486 * its requirements. The pipe will be connected to no other encoders.
Jesse Barnes79e53942008-11-07 14:24:08 -08005487 *
Eric Anholtc751ce42010-03-25 11:48:48 -07005488 * Currently this code will only succeed if there is a pipe with no encoders
Jesse Barnes79e53942008-11-07 14:24:08 -08005489 * configured for it. In the future, it could choose to temporarily disable
5490 * some outputs to free up a pipe for its use.
5491 *
5492 * \return crtc, or NULL if no pipes are available.
5493 */
5494
5495/* VESA 640x480x72Hz mode to set on the pipe */
5496static struct drm_display_mode load_detect_mode = {
5497 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5498 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5499};
5500
Chris Wilsond2dff872011-04-19 08:36:26 +01005501static struct drm_framebuffer *
5502intel_framebuffer_create(struct drm_device *dev,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08005503 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilsond2dff872011-04-19 08:36:26 +01005504 struct drm_i915_gem_object *obj)
5505{
5506 struct intel_framebuffer *intel_fb;
5507 int ret;
5508
5509 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5510 if (!intel_fb) {
5511 drm_gem_object_unreference_unlocked(&obj->base);
5512 return ERR_PTR(-ENOMEM);
5513 }
5514
5515 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5516 if (ret) {
5517 drm_gem_object_unreference_unlocked(&obj->base);
5518 kfree(intel_fb);
5519 return ERR_PTR(ret);
5520 }
5521
5522 return &intel_fb->base;
5523}
5524
5525static u32
5526intel_framebuffer_pitch_for_width(int width, int bpp)
5527{
5528 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5529 return ALIGN(pitch, 64);
5530}
5531
5532static u32
5533intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5534{
5535 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5536 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5537}
5538
5539static struct drm_framebuffer *
5540intel_framebuffer_create_for_mode(struct drm_device *dev,
5541 struct drm_display_mode *mode,
5542 int depth, int bpp)
5543{
5544 struct drm_i915_gem_object *obj;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08005545 struct drm_mode_fb_cmd2 mode_cmd;
Chris Wilsond2dff872011-04-19 08:36:26 +01005546
5547 obj = i915_gem_alloc_object(dev,
5548 intel_framebuffer_size_for_mode(mode, bpp));
5549 if (obj == NULL)
5550 return ERR_PTR(-ENOMEM);
5551
5552 mode_cmd.width = mode->hdisplay;
5553 mode_cmd.height = mode->vdisplay;
Jesse Barnes308e5bc2011-11-14 14:51:28 -08005554 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5555 bpp);
Dave Airlie5ca0c342012-02-23 15:33:40 +00005556 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
Chris Wilsond2dff872011-04-19 08:36:26 +01005557
5558 return intel_framebuffer_create(dev, &mode_cmd, obj);
5559}
5560
5561static struct drm_framebuffer *
5562mode_fits_in_fbdev(struct drm_device *dev,
5563 struct drm_display_mode *mode)
5564{
5565 struct drm_i915_private *dev_priv = dev->dev_private;
5566 struct drm_i915_gem_object *obj;
5567 struct drm_framebuffer *fb;
5568
5569 if (dev_priv->fbdev == NULL)
5570 return NULL;
5571
5572 obj = dev_priv->fbdev->ifb.obj;
5573 if (obj == NULL)
5574 return NULL;
5575
5576 fb = &dev_priv->fbdev->ifb.base;
Ville Syrjälä01f2c772011-12-20 00:06:49 +02005577 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5578 fb->bits_per_pixel))
Chris Wilsond2dff872011-04-19 08:36:26 +01005579 return NULL;
5580
Ville Syrjälä01f2c772011-12-20 00:06:49 +02005581 if (obj->base.size < mode->vdisplay * fb->pitches[0])
Chris Wilsond2dff872011-04-19 08:36:26 +01005582 return NULL;
5583
5584 return fb;
5585}
5586
Chris Wilson71731882011-04-19 23:10:58 +01005587bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5588 struct drm_connector *connector,
5589 struct drm_display_mode *mode,
Chris Wilson8261b192011-04-19 23:18:09 +01005590 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08005591{
5592 struct intel_crtc *intel_crtc;
5593 struct drm_crtc *possible_crtc;
Chris Wilson4ef69c72010-09-09 15:14:28 +01005594 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08005595 struct drm_crtc *crtc = NULL;
5596 struct drm_device *dev = encoder->dev;
Chris Wilsond2dff872011-04-19 08:36:26 +01005597 struct drm_framebuffer *old_fb;
Jesse Barnes79e53942008-11-07 14:24:08 -08005598 int i = -1;
5599
Chris Wilsond2dff872011-04-19 08:36:26 +01005600 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5601 connector->base.id, drm_get_connector_name(connector),
5602 encoder->base.id, drm_get_encoder_name(encoder));
5603
Jesse Barnes79e53942008-11-07 14:24:08 -08005604 /*
5605 * Algorithm gets a little messy:
Chris Wilson7a5e4802011-04-19 23:21:12 +01005606 *
Jesse Barnes79e53942008-11-07 14:24:08 -08005607 * - if the connector already has an assigned crtc, use it (but make
5608 * sure it's on first)
Chris Wilson7a5e4802011-04-19 23:21:12 +01005609 *
Jesse Barnes79e53942008-11-07 14:24:08 -08005610 * - try to find the first unused crtc that can drive this connector,
5611 * and use that if we find one
Jesse Barnes79e53942008-11-07 14:24:08 -08005612 */
5613
5614 /* See if we already have a CRTC for this connector */
5615 if (encoder->crtc) {
5616 crtc = encoder->crtc;
Chris Wilson8261b192011-04-19 23:18:09 +01005617
Daniel Vetter24218aa2012-08-12 19:27:11 +02005618 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01005619 old->load_detect_temp = false;
5620
5621 /* Make sure the crtc and connector are running */
Daniel Vetter24218aa2012-08-12 19:27:11 +02005622 if (connector->dpms != DRM_MODE_DPMS_ON)
5623 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
Chris Wilson8261b192011-04-19 23:18:09 +01005624
Chris Wilson71731882011-04-19 23:10:58 +01005625 return true;
Jesse Barnes79e53942008-11-07 14:24:08 -08005626 }
5627
5628 /* Find an unused one (if possible) */
5629 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5630 i++;
5631 if (!(encoder->possible_crtcs & (1 << i)))
5632 continue;
5633 if (!possible_crtc->enabled) {
5634 crtc = possible_crtc;
5635 break;
5636 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005637 }
5638
5639 /*
5640 * If we didn't find an unused CRTC, don't use any.
5641 */
5642 if (!crtc) {
Chris Wilson71731882011-04-19 23:10:58 +01005643 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5644 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005645 }
5646
5647 encoder->crtc = crtc;
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005648 connector->encoder = encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08005649
5650 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter24218aa2012-08-12 19:27:11 +02005651 old->dpms_mode = connector->dpms;
Chris Wilson8261b192011-04-19 23:18:09 +01005652 old->load_detect_temp = true;
Chris Wilsond2dff872011-04-19 08:36:26 +01005653 old->release_fb = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08005654
Chris Wilson64927112011-04-20 07:25:26 +01005655 if (!mode)
5656 mode = &load_detect_mode;
Jesse Barnes79e53942008-11-07 14:24:08 -08005657
Chris Wilsond2dff872011-04-19 08:36:26 +01005658 old_fb = crtc->fb;
5659
5660 /* We need a framebuffer large enough to accommodate all accesses
5661 * that the plane may generate whilst we perform load detection.
5662 * We can not rely on the fbcon either being present (we get called
5663 * during its initialisation to detect all boot displays, or it may
5664 * not even exist) or that it is large enough to satisfy the
5665 * requested mode.
5666 */
5667 crtc->fb = mode_fits_in_fbdev(dev, mode);
5668 if (crtc->fb == NULL) {
5669 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5670 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5671 old->release_fb = crtc->fb;
5672 } else
5673 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5674 if (IS_ERR(crtc->fb)) {
5675 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
Daniel Vetter24218aa2012-08-12 19:27:11 +02005676 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08005677 }
Chris Wilsond2dff872011-04-19 08:36:26 +01005678
5679 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
Chris Wilson64927112011-04-20 07:25:26 +01005680 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
Chris Wilsond2dff872011-04-19 08:36:26 +01005681 if (old->release_fb)
5682 old->release_fb->funcs->destroy(old->release_fb);
Daniel Vetter24218aa2012-08-12 19:27:11 +02005683 goto fail;
Jesse Barnes79e53942008-11-07 14:24:08 -08005684 }
Chris Wilson71731882011-04-19 23:10:58 +01005685
Jesse Barnes79e53942008-11-07 14:24:08 -08005686 /* let the connector get through one full cycle before testing */
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005687 intel_wait_for_vblank(dev, intel_crtc->pipe);
Jesse Barnes79e53942008-11-07 14:24:08 -08005688
Chris Wilson71731882011-04-19 23:10:58 +01005689 return true;
Daniel Vetter24218aa2012-08-12 19:27:11 +02005690fail:
5691 connector->encoder = NULL;
5692 encoder->crtc = NULL;
5693 crtc->fb = old_fb;
5694 return false;
Jesse Barnes79e53942008-11-07 14:24:08 -08005695}
5696
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005697void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
Chris Wilson8261b192011-04-19 23:18:09 +01005698 struct drm_connector *connector,
5699 struct intel_load_detect_pipe *old)
Jesse Barnes79e53942008-11-07 14:24:08 -08005700{
Chris Wilson4ef69c72010-09-09 15:14:28 +01005701 struct drm_encoder *encoder = &intel_encoder->base;
Jesse Barnes79e53942008-11-07 14:24:08 -08005702 struct drm_device *dev = encoder->dev;
Jesse Barnes79e53942008-11-07 14:24:08 -08005703
Chris Wilsond2dff872011-04-19 08:36:26 +01005704 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5705 connector->base.id, drm_get_connector_name(connector),
5706 encoder->base.id, drm_get_encoder_name(encoder));
5707
Chris Wilson8261b192011-04-19 23:18:09 +01005708 if (old->load_detect_temp) {
Zhenyu Wangc1c43972010-03-30 14:39:30 +08005709 connector->encoder = NULL;
Daniel Vetter24218aa2012-08-12 19:27:11 +02005710 encoder->crtc = NULL;
Jesse Barnes79e53942008-11-07 14:24:08 -08005711 drm_helper_disable_unused_functions(dev);
Chris Wilsond2dff872011-04-19 08:36:26 +01005712
5713 if (old->release_fb)
5714 old->release_fb->funcs->destroy(old->release_fb);
5715
Chris Wilson0622a532011-04-21 09:32:11 +01005716 return;
Jesse Barnes79e53942008-11-07 14:24:08 -08005717 }
5718
Eric Anholtc751ce42010-03-25 11:48:48 -07005719 /* Switch crtc and encoder back off if necessary */
Daniel Vetter24218aa2012-08-12 19:27:11 +02005720 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5721 connector->funcs->dpms(connector, old->dpms_mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08005722}
5723
5724/* Returns the clock of the currently programmed mode of the given pipe. */
5725static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5726{
5727 struct drm_i915_private *dev_priv = dev->dev_private;
5728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5729 int pipe = intel_crtc->pipe;
Jesse Barnes548f2452011-02-17 10:40:53 -08005730 u32 dpll = I915_READ(DPLL(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005731 u32 fp;
5732 intel_clock_t clock;
5733
5734 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
Chris Wilson39adb7a2011-04-22 22:17:21 +01005735 fp = I915_READ(FP0(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005736 else
Chris Wilson39adb7a2011-04-22 22:17:21 +01005737 fp = I915_READ(FP1(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005738
5739 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005740 if (IS_PINEVIEW(dev)) {
5741 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5742 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
Shaohua Li21778322009-02-23 15:19:16 +08005743 } else {
5744 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5745 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5746 }
5747
Chris Wilsona6c45cf2010-09-17 00:32:17 +01005748 if (!IS_GEN2(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05005749 if (IS_PINEVIEW(dev))
5750 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5751 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
Shaohua Li21778322009-02-23 15:19:16 +08005752 else
5753 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
Jesse Barnes79e53942008-11-07 14:24:08 -08005754 DPLL_FPA01_P1_POST_DIV_SHIFT);
5755
5756 switch (dpll & DPLL_MODE_MASK) {
5757 case DPLLB_MODE_DAC_SERIAL:
5758 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5759 5 : 10;
5760 break;
5761 case DPLLB_MODE_LVDS:
5762 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5763 7 : 14;
5764 break;
5765 default:
Zhao Yakui28c97732009-10-09 11:39:41 +08005766 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
Jesse Barnes79e53942008-11-07 14:24:08 -08005767 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5768 return 0;
5769 }
5770
5771 /* XXX: Handle the 100Mhz refclk */
Shaohua Li21778322009-02-23 15:19:16 +08005772 intel_clock(dev, 96000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005773 } else {
5774 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5775
5776 if (is_lvds) {
5777 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5778 DPLL_FPA01_P1_POST_DIV_SHIFT);
5779 clock.p2 = 14;
5780
5781 if ((dpll & PLL_REF_INPUT_MASK) ==
5782 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5783 /* XXX: might not be 66MHz */
Shaohua Li21778322009-02-23 15:19:16 +08005784 intel_clock(dev, 66000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005785 } else
Shaohua Li21778322009-02-23 15:19:16 +08005786 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005787 } else {
5788 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5789 clock.p1 = 2;
5790 else {
5791 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5792 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5793 }
5794 if (dpll & PLL_P2_DIVIDE_BY_4)
5795 clock.p2 = 4;
5796 else
5797 clock.p2 = 2;
5798
Shaohua Li21778322009-02-23 15:19:16 +08005799 intel_clock(dev, 48000, &clock);
Jesse Barnes79e53942008-11-07 14:24:08 -08005800 }
5801 }
5802
5803 /* XXX: It would be nice to validate the clocks, but we can't reuse
5804 * i830PllIsValid() because it relies on the xf86_config connector
5805 * configuration being accurate, which it isn't necessarily.
5806 */
5807
5808 return clock.dot;
5809}
5810
5811/** Returns the currently programmed mode of the given pipe. */
5812struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5813 struct drm_crtc *crtc)
5814{
Jesse Barnes548f2452011-02-17 10:40:53 -08005815 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08005816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5817 int pipe = intel_crtc->pipe;
5818 struct drm_display_mode *mode;
Jesse Barnes548f2452011-02-17 10:40:53 -08005819 int htot = I915_READ(HTOTAL(pipe));
5820 int hsync = I915_READ(HSYNC(pipe));
5821 int vtot = I915_READ(VTOTAL(pipe));
5822 int vsync = I915_READ(VSYNC(pipe));
Jesse Barnes79e53942008-11-07 14:24:08 -08005823
5824 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5825 if (!mode)
5826 return NULL;
5827
5828 mode->clock = intel_crtc_clock_get(dev, crtc);
5829 mode->hdisplay = (htot & 0xffff) + 1;
5830 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5831 mode->hsync_start = (hsync & 0xffff) + 1;
5832 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5833 mode->vdisplay = (vtot & 0xffff) + 1;
5834 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5835 mode->vsync_start = (vsync & 0xffff) + 1;
5836 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5837
5838 drm_mode_set_name(mode);
Jesse Barnes79e53942008-11-07 14:24:08 -08005839
5840 return mode;
5841}
5842
Daniel Vetter3dec0092010-08-20 21:40:52 +02005843static void intel_increase_pllclock(struct drm_crtc *crtc)
Jesse Barnes652c3932009-08-17 13:31:43 -07005844{
5845 struct drm_device *dev = crtc->dev;
5846 drm_i915_private_t *dev_priv = dev->dev_private;
5847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5848 int pipe = intel_crtc->pipe;
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005849 int dpll_reg = DPLL(pipe);
5850 int dpll;
Jesse Barnes652c3932009-08-17 13:31:43 -07005851
Eric Anholtbad720f2009-10-22 16:11:14 -07005852 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07005853 return;
5854
5855 if (!dev_priv->lvds_downclock_avail)
5856 return;
5857
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005858 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07005859 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
Zhao Yakui44d98a62009-10-09 11:39:40 +08005860 DRM_DEBUG_DRIVER("upclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005861
Sean Paul8ac5a6d2012-02-13 13:14:51 -05005862 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07005863
5864 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5865 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005866 intel_wait_for_vblank(dev, pipe);
Jesse Barnesdbdc6472010-12-30 09:36:39 -08005867
Jesse Barnes652c3932009-08-17 13:31:43 -07005868 dpll = I915_READ(dpll_reg);
5869 if (dpll & DISPLAY_RATE_SELECT_FPA1)
Zhao Yakui44d98a62009-10-09 11:39:40 +08005870 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005871 }
Jesse Barnes652c3932009-08-17 13:31:43 -07005872}
5873
5874static void intel_decrease_pllclock(struct drm_crtc *crtc)
5875{
5876 struct drm_device *dev = crtc->dev;
5877 drm_i915_private_t *dev_priv = dev->dev_private;
5878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07005879
Eric Anholtbad720f2009-10-22 16:11:14 -07005880 if (HAS_PCH_SPLIT(dev))
Jesse Barnes652c3932009-08-17 13:31:43 -07005881 return;
5882
5883 if (!dev_priv->lvds_downclock_avail)
5884 return;
5885
5886 /*
5887 * Since this is called by a timer, we should never get here in
5888 * the manual case.
5889 */
5890 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
Chris Wilson074b5e12012-05-02 12:07:06 +01005891 int pipe = intel_crtc->pipe;
5892 int dpll_reg = DPLL(pipe);
Daniel Vetterdc257cf2012-05-07 11:30:46 +02005893 int dpll;
Chris Wilson074b5e12012-05-02 12:07:06 +01005894
Zhao Yakui44d98a62009-10-09 11:39:40 +08005895 DRM_DEBUG_DRIVER("downclocking LVDS\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005896
Sean Paul8ac5a6d2012-02-13 13:14:51 -05005897 assert_panel_unlocked(dev_priv, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07005898
Chris Wilson074b5e12012-05-02 12:07:06 +01005899 dpll = I915_READ(dpll_reg);
Jesse Barnes652c3932009-08-17 13:31:43 -07005900 dpll |= DISPLAY_RATE_SELECT_FPA1;
5901 I915_WRITE(dpll_reg, dpll);
Jesse Barnes9d0498a2010-08-18 13:20:54 -07005902 intel_wait_for_vblank(dev, pipe);
Jesse Barnes652c3932009-08-17 13:31:43 -07005903 dpll = I915_READ(dpll_reg);
5904 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
Zhao Yakui44d98a62009-10-09 11:39:40 +08005905 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
Jesse Barnes652c3932009-08-17 13:31:43 -07005906 }
5907
5908}
5909
Chris Wilsonf047e392012-07-21 12:31:41 +01005910void intel_mark_busy(struct drm_device *dev)
Jesse Barnes652c3932009-08-17 13:31:43 -07005911{
Chris Wilsonf047e392012-07-21 12:31:41 +01005912 i915_update_gfx_val(dev->dev_private);
5913}
5914
5915void intel_mark_idle(struct drm_device *dev)
5916{
Chris Wilsonf047e392012-07-21 12:31:41 +01005917}
5918
5919void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
5920{
5921 struct drm_device *dev = obj->base.dev;
Jesse Barnes652c3932009-08-17 13:31:43 -07005922 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07005923
5924 if (!i915_powersave)
5925 return;
5926
Jesse Barnes652c3932009-08-17 13:31:43 -07005927 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
Jesse Barnes652c3932009-08-17 13:31:43 -07005928 if (!crtc->fb)
5929 continue;
5930
Chris Wilsonf047e392012-07-21 12:31:41 +01005931 if (to_intel_framebuffer(crtc->fb)->obj == obj)
5932 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07005933 }
Jesse Barnes652c3932009-08-17 13:31:43 -07005934}
5935
Chris Wilsonf047e392012-07-21 12:31:41 +01005936void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
Jesse Barnes652c3932009-08-17 13:31:43 -07005937{
Chris Wilsonf047e392012-07-21 12:31:41 +01005938 struct drm_device *dev = obj->base.dev;
5939 struct drm_crtc *crtc;
Jesse Barnes652c3932009-08-17 13:31:43 -07005940
Chris Wilsonf047e392012-07-21 12:31:41 +01005941 if (!i915_powersave)
Chris Wilsonacb87df2012-05-03 15:47:57 +01005942 return;
5943
Jesse Barnes652c3932009-08-17 13:31:43 -07005944 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5945 if (!crtc->fb)
5946 continue;
5947
Chris Wilsonf047e392012-07-21 12:31:41 +01005948 if (to_intel_framebuffer(crtc->fb)->obj == obj)
5949 intel_decrease_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07005950 }
5951}
5952
Jesse Barnes79e53942008-11-07 14:24:08 -08005953static void intel_crtc_destroy(struct drm_crtc *crtc)
5954{
5955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02005956 struct drm_device *dev = crtc->dev;
5957 struct intel_unpin_work *work;
5958 unsigned long flags;
5959
5960 spin_lock_irqsave(&dev->event_lock, flags);
5961 work = intel_crtc->unpin_work;
5962 intel_crtc->unpin_work = NULL;
5963 spin_unlock_irqrestore(&dev->event_lock, flags);
5964
5965 if (work) {
5966 cancel_work_sync(&work->work);
5967 kfree(work);
5968 }
Jesse Barnes79e53942008-11-07 14:24:08 -08005969
5970 drm_crtc_cleanup(crtc);
Daniel Vetter67e77c52010-08-20 22:26:30 +02005971
Jesse Barnes79e53942008-11-07 14:24:08 -08005972 kfree(intel_crtc);
5973}
5974
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005975static void intel_unpin_work_fn(struct work_struct *__work)
5976{
5977 struct intel_unpin_work *work =
5978 container_of(__work, struct intel_unpin_work, work);
5979
5980 mutex_lock(&work->dev->struct_mutex);
Chris Wilson1690e1e2011-12-14 13:57:08 +01005981 intel_unpin_fb_obj(work->old_fb_obj);
Chris Wilson05394f32010-11-08 19:18:58 +00005982 drm_gem_object_unreference(&work->pending_flip_obj->base);
5983 drm_gem_object_unreference(&work->old_fb_obj->base);
Chris Wilsond9e86c02010-11-10 16:40:20 +00005984
Chris Wilson7782de32011-07-08 12:22:41 +01005985 intel_update_fbc(work->dev);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005986 mutex_unlock(&work->dev->struct_mutex);
5987 kfree(work);
5988}
5989
Jesse Barnes1afe3e92010-03-26 10:35:20 -07005990static void do_intel_finish_page_flip(struct drm_device *dev,
Mario Kleiner49b14a52010-12-09 07:00:07 +01005991 struct drm_crtc *crtc)
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005992{
5993 drm_i915_private_t *dev_priv = dev->dev_private;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5995 struct intel_unpin_work *work;
Chris Wilson05394f32010-11-08 19:18:58 +00005996 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005997 struct drm_pending_vblank_event *e;
Mario Kleiner49b14a52010-12-09 07:00:07 +01005998 struct timeval tnow, tvbl;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05005999 unsigned long flags;
6000
6001 /* Ignore early vblank irqs */
6002 if (intel_crtc == NULL)
6003 return;
6004
Mario Kleiner49b14a52010-12-09 07:00:07 +01006005 do_gettimeofday(&tnow);
6006
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006007 spin_lock_irqsave(&dev->event_lock, flags);
6008 work = intel_crtc->unpin_work;
6009 if (work == NULL || !work->pending) {
6010 spin_unlock_irqrestore(&dev->event_lock, flags);
6011 return;
6012 }
6013
6014 intel_crtc->unpin_work = NULL;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006015
6016 if (work->event) {
6017 e = work->event;
Mario Kleiner49b14a52010-12-09 07:00:07 +01006018 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006019
6020 /* Called before vblank count and timestamps have
6021 * been updated for the vblank interval of flip
6022 * completion? Need to increment vblank count and
6023 * add one videorefresh duration to returned timestamp
Mario Kleiner49b14a52010-12-09 07:00:07 +01006024 * to account for this. We assume this happened if we
6025 * get called over 0.9 frame durations after the last
6026 * timestamped vblank.
6027 *
6028 * This calculation can not be used with vrefresh rates
6029 * below 5Hz (10Hz to be on the safe side) without
6030 * promoting to 64 integers.
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006031 */
Mario Kleiner49b14a52010-12-09 07:00:07 +01006032 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6033 9 * crtc->framedur_ns) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006034 e->event.sequence++;
Mario Kleiner49b14a52010-12-09 07:00:07 +01006035 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6036 crtc->framedur_ns);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006037 }
6038
Mario Kleiner49b14a52010-12-09 07:00:07 +01006039 e->event.tv_sec = tvbl.tv_sec;
6040 e->event.tv_usec = tvbl.tv_usec;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006041
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006042 list_add_tail(&e->base.link,
6043 &e->base.file_priv->event_list);
6044 wake_up_interruptible(&e->base.file_priv->event_wait);
6045 }
6046
Mario Kleiner0af7e4d2010-12-08 04:07:19 +01006047 drm_vblank_put(dev, intel_crtc->pipe);
6048
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006049 spin_unlock_irqrestore(&dev->event_lock, flags);
6050
Chris Wilson05394f32010-11-08 19:18:58 +00006051 obj = work->old_fb_obj;
Chris Wilsond9e86c02010-11-10 16:40:20 +00006052
Chris Wilsone59f2ba2010-10-07 17:28:15 +01006053 atomic_clear_mask(1 << intel_crtc->plane,
Chris Wilson05394f32010-11-08 19:18:58 +00006054 &obj->pending_flip.counter);
6055 if (atomic_read(&obj->pending_flip) == 0)
Chris Wilsonf787a5f2010-09-24 16:02:42 +01006056 wake_up(&dev_priv->pending_flip_queue);
Chris Wilsond9e86c02010-11-10 16:40:20 +00006057
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006058 schedule_work(&work->work);
Jesse Barnese5510fa2010-07-01 16:48:37 -07006059
6060 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006061}
6062
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006063void intel_finish_page_flip(struct drm_device *dev, int pipe)
6064{
6065 drm_i915_private_t *dev_priv = dev->dev_private;
6066 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6067
Mario Kleiner49b14a52010-12-09 07:00:07 +01006068 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006069}
6070
6071void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6072{
6073 drm_i915_private_t *dev_priv = dev->dev_private;
6074 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6075
Mario Kleiner49b14a52010-12-09 07:00:07 +01006076 do_intel_finish_page_flip(dev, crtc);
Jesse Barnes1afe3e92010-03-26 10:35:20 -07006077}
6078
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006079void intel_prepare_page_flip(struct drm_device *dev, int plane)
6080{
6081 drm_i915_private_t *dev_priv = dev->dev_private;
6082 struct intel_crtc *intel_crtc =
6083 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6084 unsigned long flags;
6085
6086 spin_lock_irqsave(&dev->event_lock, flags);
Jesse Barnesde3f4402010-01-14 13:18:02 -08006087 if (intel_crtc->unpin_work) {
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01006088 if ((++intel_crtc->unpin_work->pending) > 1)
6089 DRM_ERROR("Prepared flip multiple times\n");
Jesse Barnesde3f4402010-01-14 13:18:02 -08006090 } else {
6091 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6092 }
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006093 spin_unlock_irqrestore(&dev->event_lock, flags);
6094}
6095
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006096static int intel_gen2_queue_flip(struct drm_device *dev,
6097 struct drm_crtc *crtc,
6098 struct drm_framebuffer *fb,
6099 struct drm_i915_gem_object *obj)
6100{
6101 struct drm_i915_private *dev_priv = dev->dev_private;
6102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006103 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006104 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006105 int ret;
6106
Daniel Vetter6d90c952012-04-26 23:28:05 +02006107 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006108 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006109 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006110
Daniel Vetter6d90c952012-04-26 23:28:05 +02006111 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006112 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006113 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006114
6115 /* Can't queue multiple flips, so wait for the previous
6116 * one to finish before executing the next.
6117 */
6118 if (intel_crtc->plane)
6119 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6120 else
6121 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006122 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6123 intel_ring_emit(ring, MI_NOOP);
6124 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6125 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6126 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vettere506a0c2012-07-05 12:17:29 +02006127 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02006128 intel_ring_emit(ring, 0); /* aux display base address, unused */
6129 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006130 return 0;
6131
6132err_unpin:
6133 intel_unpin_fb_obj(obj);
6134err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006135 return ret;
6136}
6137
6138static int intel_gen3_queue_flip(struct drm_device *dev,
6139 struct drm_crtc *crtc,
6140 struct drm_framebuffer *fb,
6141 struct drm_i915_gem_object *obj)
6142{
6143 struct drm_i915_private *dev_priv = dev->dev_private;
6144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006145 u32 flip_mask;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006146 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006147 int ret;
6148
Daniel Vetter6d90c952012-04-26 23:28:05 +02006149 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006150 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006151 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006152
Daniel Vetter6d90c952012-04-26 23:28:05 +02006153 ret = intel_ring_begin(ring, 6);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006154 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006155 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006156
6157 if (intel_crtc->plane)
6158 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6159 else
6160 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006161 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6162 intel_ring_emit(ring, MI_NOOP);
6163 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6164 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6165 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vettere506a0c2012-07-05 12:17:29 +02006166 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Daniel Vetter6d90c952012-04-26 23:28:05 +02006167 intel_ring_emit(ring, MI_NOOP);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006168
Daniel Vetter6d90c952012-04-26 23:28:05 +02006169 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006170 return 0;
6171
6172err_unpin:
6173 intel_unpin_fb_obj(obj);
6174err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006175 return ret;
6176}
6177
6178static int intel_gen4_queue_flip(struct drm_device *dev,
6179 struct drm_crtc *crtc,
6180 struct drm_framebuffer *fb,
6181 struct drm_i915_gem_object *obj)
6182{
6183 struct drm_i915_private *dev_priv = dev->dev_private;
6184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6185 uint32_t pf, pipesrc;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006186 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006187 int ret;
6188
Daniel Vetter6d90c952012-04-26 23:28:05 +02006189 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006190 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006191 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006192
Daniel Vetter6d90c952012-04-26 23:28:05 +02006193 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006194 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006195 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006196
6197 /* i965+ uses the linear or tiled offsets from the
6198 * Display Registers (which do not change across a page-flip)
6199 * so we need only reprogram the base address.
6200 */
Daniel Vetter6d90c952012-04-26 23:28:05 +02006201 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6202 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6203 intel_ring_emit(ring, fb->pitches[0]);
Daniel Vetterc2c75132012-07-05 12:17:30 +02006204 intel_ring_emit(ring,
6205 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6206 obj->tiling_mode);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006207
6208 /* XXX Enabling the panel-fitter across page-flip is so far
6209 * untested on non-native modes, so ignore it for now.
6210 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6211 */
6212 pf = 0;
6213 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006214 intel_ring_emit(ring, pf | pipesrc);
6215 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006216 return 0;
6217
6218err_unpin:
6219 intel_unpin_fb_obj(obj);
6220err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006221 return ret;
6222}
6223
6224static int intel_gen6_queue_flip(struct drm_device *dev,
6225 struct drm_crtc *crtc,
6226 struct drm_framebuffer *fb,
6227 struct drm_i915_gem_object *obj)
6228{
6229 struct drm_i915_private *dev_priv = dev->dev_private;
6230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Daniel Vetter6d90c952012-04-26 23:28:05 +02006231 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006232 uint32_t pf, pipesrc;
6233 int ret;
6234
Daniel Vetter6d90c952012-04-26 23:28:05 +02006235 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006236 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006237 goto err;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006238
Daniel Vetter6d90c952012-04-26 23:28:05 +02006239 ret = intel_ring_begin(ring, 4);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006240 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006241 goto err_unpin;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006242
Daniel Vetter6d90c952012-04-26 23:28:05 +02006243 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6244 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6245 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
Daniel Vetterc2c75132012-07-05 12:17:30 +02006246 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006247
Chris Wilson99d9acd2012-04-17 20:37:00 +01006248 /* Contrary to the suggestions in the documentation,
6249 * "Enable Panel Fitter" does not seem to be required when page
6250 * flipping with a non-native mode, and worse causes a normal
6251 * modeset to fail.
6252 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6253 */
6254 pf = 0;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006255 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
Daniel Vetter6d90c952012-04-26 23:28:05 +02006256 intel_ring_emit(ring, pf | pipesrc);
6257 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006258 return 0;
6259
6260err_unpin:
6261 intel_unpin_fb_obj(obj);
6262err:
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006263 return ret;
6264}
6265
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006266/*
6267 * On gen7 we currently use the blit ring because (in early silicon at least)
6268 * the render ring doesn't give us interrpts for page flip completion, which
6269 * means clients will hang after the first flip is queued. Fortunately the
6270 * blit ring generates interrupts properly, so use it instead.
6271 */
6272static int intel_gen7_queue_flip(struct drm_device *dev,
6273 struct drm_crtc *crtc,
6274 struct drm_framebuffer *fb,
6275 struct drm_i915_gem_object *obj)
6276{
6277 struct drm_i915_private *dev_priv = dev->dev_private;
6278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6279 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
Daniel Vettercb05d8d2012-05-23 14:02:00 +02006280 uint32_t plane_bit = 0;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006281 int ret;
6282
6283 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6284 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006285 goto err;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006286
Daniel Vettercb05d8d2012-05-23 14:02:00 +02006287 switch(intel_crtc->plane) {
6288 case PLANE_A:
6289 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6290 break;
6291 case PLANE_B:
6292 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6293 break;
6294 case PLANE_C:
6295 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6296 break;
6297 default:
6298 WARN_ONCE(1, "unknown plane in flip command\n");
6299 ret = -ENODEV;
Eugeni Dodonovab3951e2012-06-18 19:03:38 -03006300 goto err_unpin;
Daniel Vettercb05d8d2012-05-23 14:02:00 +02006301 }
6302
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006303 ret = intel_ring_begin(ring, 4);
6304 if (ret)
Chris Wilson83d40922012-04-17 19:35:53 +01006305 goto err_unpin;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006306
Daniel Vettercb05d8d2012-05-23 14:02:00 +02006307 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
Ville Syrjälä01f2c772011-12-20 00:06:49 +02006308 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
Daniel Vetterc2c75132012-07-05 12:17:30 +02006309 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006310 intel_ring_emit(ring, (MI_NOOP));
6311 intel_ring_advance(ring);
Chris Wilson83d40922012-04-17 19:35:53 +01006312 return 0;
6313
6314err_unpin:
6315 intel_unpin_fb_obj(obj);
6316err:
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006317 return ret;
6318}
6319
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006320static int intel_default_queue_flip(struct drm_device *dev,
6321 struct drm_crtc *crtc,
6322 struct drm_framebuffer *fb,
6323 struct drm_i915_gem_object *obj)
6324{
6325 return -ENODEV;
6326}
6327
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006328static int intel_crtc_page_flip(struct drm_crtc *crtc,
6329 struct drm_framebuffer *fb,
6330 struct drm_pending_vblank_event *event)
6331{
6332 struct drm_device *dev = crtc->dev;
6333 struct drm_i915_private *dev_priv = dev->dev_private;
6334 struct intel_framebuffer *intel_fb;
Chris Wilson05394f32010-11-08 19:18:58 +00006335 struct drm_i915_gem_object *obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6337 struct intel_unpin_work *work;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006338 unsigned long flags;
Chris Wilson52e68632010-08-08 10:15:59 +01006339 int ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006340
Ville Syrjäläe6a595d2012-05-24 21:08:59 +03006341 /* Can't change pixel format via MI display flips. */
6342 if (fb->pixel_format != crtc->fb->pixel_format)
6343 return -EINVAL;
6344
6345 /*
6346 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6347 * Note that pitch changes could also affect these register.
6348 */
6349 if (INTEL_INFO(dev)->gen > 3 &&
6350 (fb->offsets[0] != crtc->fb->offsets[0] ||
6351 fb->pitches[0] != crtc->fb->pitches[0]))
6352 return -EINVAL;
6353
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006354 work = kzalloc(sizeof *work, GFP_KERNEL);
6355 if (work == NULL)
6356 return -ENOMEM;
6357
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006358 work->event = event;
6359 work->dev = crtc->dev;
6360 intel_fb = to_intel_framebuffer(crtc->fb);
Jesse Barnesb1b87f62010-01-26 14:40:05 -08006361 work->old_fb_obj = intel_fb->obj;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006362 INIT_WORK(&work->work, intel_unpin_work_fn);
6363
Jesse Barnes7317c75e62011-08-29 09:45:28 -07006364 ret = drm_vblank_get(dev, intel_crtc->pipe);
6365 if (ret)
6366 goto free_work;
6367
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006368 /* We borrow the event spin lock for protecting unpin_work */
6369 spin_lock_irqsave(&dev->event_lock, flags);
6370 if (intel_crtc->unpin_work) {
6371 spin_unlock_irqrestore(&dev->event_lock, flags);
6372 kfree(work);
Jesse Barnes7317c75e62011-08-29 09:45:28 -07006373 drm_vblank_put(dev, intel_crtc->pipe);
Chris Wilson468f0b42010-05-27 13:18:13 +01006374
6375 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006376 return -EBUSY;
6377 }
6378 intel_crtc->unpin_work = work;
6379 spin_unlock_irqrestore(&dev->event_lock, flags);
6380
6381 intel_fb = to_intel_framebuffer(fb);
6382 obj = intel_fb->obj;
6383
Chris Wilson79158102012-05-23 11:13:58 +01006384 ret = i915_mutex_lock_interruptible(dev);
6385 if (ret)
6386 goto cleanup;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006387
Jesse Barnes75dfca82010-02-10 15:09:44 -08006388 /* Reference the objects for the scheduled work. */
Chris Wilson05394f32010-11-08 19:18:58 +00006389 drm_gem_object_reference(&work->old_fb_obj->base);
6390 drm_gem_object_reference(&obj->base);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006391
6392 crtc->fb = fb;
Chris Wilson96b099f2010-06-07 14:03:04 +01006393
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006394 work->pending_flip_obj = obj;
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006395
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01006396 work->enable_stall_check = true;
6397
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006398 /* Block clients from rendering to the new back buffer until
6399 * the flip occurs and the object is no longer visible.
6400 */
Chris Wilson05394f32010-11-08 19:18:58 +00006401 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilsone1f99ce2010-10-27 12:45:26 +01006402
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006403 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6404 if (ret)
6405 goto cleanup_pending;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006406
Chris Wilson7782de32011-07-08 12:22:41 +01006407 intel_disable_fbc(dev);
Chris Wilsonf047e392012-07-21 12:31:41 +01006408 intel_mark_fb_busy(obj);
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006409 mutex_unlock(&dev->struct_mutex);
6410
Jesse Barnese5510fa2010-07-01 16:48:37 -07006411 trace_i915_flip_request(intel_crtc->plane, obj);
6412
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006413 return 0;
Chris Wilson96b099f2010-06-07 14:03:04 +01006414
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006415cleanup_pending:
6416 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
Chris Wilson05394f32010-11-08 19:18:58 +00006417 drm_gem_object_unreference(&work->old_fb_obj->base);
6418 drm_gem_object_unreference(&obj->base);
Chris Wilson96b099f2010-06-07 14:03:04 +01006419 mutex_unlock(&dev->struct_mutex);
6420
Chris Wilson79158102012-05-23 11:13:58 +01006421cleanup:
Chris Wilson96b099f2010-06-07 14:03:04 +01006422 spin_lock_irqsave(&dev->event_lock, flags);
6423 intel_crtc->unpin_work = NULL;
6424 spin_unlock_irqrestore(&dev->event_lock, flags);
6425
Jesse Barnes7317c75e62011-08-29 09:45:28 -07006426 drm_vblank_put(dev, intel_crtc->pipe);
6427free_work:
Chris Wilson96b099f2010-06-07 14:03:04 +01006428 kfree(work);
6429
6430 return ret;
Kristian Høgsberg6b95a202009-11-18 11:25:18 -05006431}
6432
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006433static void intel_sanitize_modesetting(struct drm_device *dev,
6434 int pipe, int plane)
6435{
6436 struct drm_i915_private *dev_priv = dev->dev_private;
6437 u32 reg, val;
Daniel Vettera9dcf842012-05-13 22:29:25 +02006438 int i;
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006439
Chris Wilsonf47166d2012-03-22 15:00:50 +00006440 /* Clear any frame start delays used for debugging left by the BIOS */
Daniel Vettera9dcf842012-05-13 22:29:25 +02006441 for_each_pipe(i) {
6442 reg = PIPECONF(i);
Chris Wilsonf47166d2012-03-22 15:00:50 +00006443 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6444 }
6445
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006446 if (HAS_PCH_SPLIT(dev))
6447 return;
6448
6449 /* Who knows what state these registers were left in by the BIOS or
6450 * grub?
6451 *
6452 * If we leave the registers in a conflicting state (e.g. with the
6453 * display plane reading from the other pipe than the one we intend
6454 * to use) then when we attempt to teardown the active mode, we will
6455 * not disable the pipes and planes in the correct order -- leaving
6456 * a plane reading from a disabled pipe and possibly leading to
6457 * undefined behaviour.
6458 */
6459
6460 reg = DSPCNTR(plane);
6461 val = I915_READ(reg);
6462
6463 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6464 return;
6465 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6466 return;
6467
6468 /* This display plane is active and attached to the other CPU pipe. */
6469 pipe = !pipe;
6470
6471 /* Disable the plane and wait for it to stop reading from the pipe. */
Jesse Barnesb24e7172011-01-04 15:09:30 -08006472 intel_disable_plane(dev_priv, plane, pipe);
6473 intel_disable_pipe(dev_priv, pipe);
Chris Wilson47f1c6c2010-12-03 15:37:31 +00006474}
Jesse Barnes79e53942008-11-07 14:24:08 -08006475
Chris Wilsonf6e5b162011-04-12 18:06:51 +01006476static void intel_crtc_reset(struct drm_crtc *crtc)
6477{
6478 struct drm_device *dev = crtc->dev;
6479 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6480
6481 /* Reset flags back to the 'unknown' status so that they
6482 * will be correctly set on the initial modeset.
6483 */
6484 intel_crtc->dpms_mode = -1;
6485
6486 /* We need to fix up any BIOS configuration that conflicts with
6487 * our expectations.
6488 */
6489 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6490}
6491
6492static struct drm_crtc_helper_funcs intel_helper_funcs = {
6493 .dpms = intel_crtc_dpms,
6494 .mode_fixup = intel_crtc_mode_fixup,
6495 .mode_set = intel_crtc_mode_set,
6496 .mode_set_base = intel_pipe_set_base,
6497 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6498 .load_lut = intel_crtc_load_lut,
6499 .disable = intel_crtc_disable,
6500};
6501
6502static const struct drm_crtc_funcs intel_crtc_funcs = {
6503 .reset = intel_crtc_reset,
6504 .cursor_set = intel_crtc_cursor_set,
6505 .cursor_move = intel_crtc_cursor_move,
6506 .gamma_set = intel_crtc_gamma_set,
6507 .set_config = drm_crtc_helper_set_config,
6508 .destroy = intel_crtc_destroy,
6509 .page_flip = intel_crtc_page_flip,
6510};
6511
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006512static void intel_pch_pll_init(struct drm_device *dev)
6513{
6514 drm_i915_private_t *dev_priv = dev->dev_private;
6515 int i;
6516
6517 if (dev_priv->num_pch_pll == 0) {
6518 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6519 return;
6520 }
6521
6522 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6523 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6524 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6525 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6526 }
6527}
6528
Hannes Ederb358d0a2008-12-18 21:18:47 +01006529static void intel_crtc_init(struct drm_device *dev, int pipe)
Jesse Barnes79e53942008-11-07 14:24:08 -08006530{
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08006531 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes79e53942008-11-07 14:24:08 -08006532 struct intel_crtc *intel_crtc;
6533 int i;
6534
6535 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6536 if (intel_crtc == NULL)
6537 return;
6538
6539 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6540
6541 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
Jesse Barnes79e53942008-11-07 14:24:08 -08006542 for (i = 0; i < 256; i++) {
6543 intel_crtc->lut_r[i] = i;
6544 intel_crtc->lut_g[i] = i;
6545 intel_crtc->lut_b[i] = i;
6546 }
6547
Jesse Barnes80824002009-09-10 15:28:06 -07006548 /* Swap pipes & planes for FBC on pre-965 */
6549 intel_crtc->pipe = pipe;
6550 intel_crtc->plane = pipe;
Chris Wilsone2e767a2010-09-13 16:53:12 +01006551 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
Zhao Yakui28c97732009-10-09 11:39:41 +08006552 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
Chris Wilsone2e767a2010-09-13 16:53:12 +01006553 intel_crtc->plane = !pipe;
Jesse Barnes80824002009-09-10 15:28:06 -07006554 }
6555
Jesse Barnes22fd0fa2009-12-02 13:42:53 -08006556 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6557 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6558 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6559 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6560
Chris Wilson5d1d0cc2011-01-24 15:02:15 +00006561 intel_crtc_reset(&intel_crtc->base);
Chris Wilson04dbff52011-02-10 17:38:35 +00006562 intel_crtc->active = true; /* force the pipe off on setup_init_config */
Jesse Barnes5a354202011-06-24 12:19:22 -07006563 intel_crtc->bpp = 24; /* default for pre-Ironlake */
Jesse Barnes7e7d76c2010-09-10 10:47:20 -07006564
6565 if (HAS_PCH_SPLIT(dev)) {
6566 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6567 intel_helper_funcs.commit = ironlake_crtc_commit;
6568 } else {
6569 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6570 intel_helper_funcs.commit = i9xx_crtc_commit;
6571 }
6572
Jesse Barnes79e53942008-11-07 14:24:08 -08006573 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
Jesse Barnes79e53942008-11-07 14:24:08 -08006574}
6575
Carl Worth08d7b3d2009-04-29 14:43:54 -07006576int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
Chris Wilson05394f32010-11-08 19:18:58 +00006577 struct drm_file *file)
Carl Worth08d7b3d2009-04-29 14:43:54 -07006578{
Carl Worth08d7b3d2009-04-29 14:43:54 -07006579 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
Daniel Vetterc05422d2009-08-11 16:05:30 +02006580 struct drm_mode_object *drmmode_obj;
6581 struct intel_crtc *crtc;
Carl Worth08d7b3d2009-04-29 14:43:54 -07006582
Daniel Vetter1cff8f62012-04-24 09:55:08 +02006583 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6584 return -ENODEV;
Carl Worth08d7b3d2009-04-29 14:43:54 -07006585
Daniel Vetterc05422d2009-08-11 16:05:30 +02006586 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6587 DRM_MODE_OBJECT_CRTC);
Carl Worth08d7b3d2009-04-29 14:43:54 -07006588
Daniel Vetterc05422d2009-08-11 16:05:30 +02006589 if (!drmmode_obj) {
Carl Worth08d7b3d2009-04-29 14:43:54 -07006590 DRM_ERROR("no such CRTC id\n");
6591 return -EINVAL;
6592 }
6593
Daniel Vetterc05422d2009-08-11 16:05:30 +02006594 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6595 pipe_from_crtc_id->pipe = crtc->pipe;
Carl Worth08d7b3d2009-04-29 14:43:54 -07006596
Daniel Vetterc05422d2009-08-11 16:05:30 +02006597 return 0;
Carl Worth08d7b3d2009-04-29 14:43:54 -07006598}
6599
Daniel Vetter66a92782012-07-12 20:08:18 +02006600static int intel_encoder_clones(struct intel_encoder *encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08006601{
Daniel Vetter66a92782012-07-12 20:08:18 +02006602 struct drm_device *dev = encoder->base.dev;
6603 struct intel_encoder *source_encoder;
Jesse Barnes79e53942008-11-07 14:24:08 -08006604 int index_mask = 0;
Jesse Barnes79e53942008-11-07 14:24:08 -08006605 int entry = 0;
6606
Daniel Vetter66a92782012-07-12 20:08:18 +02006607 list_for_each_entry(source_encoder,
6608 &dev->mode_config.encoder_list, base.head) {
6609
6610 if (encoder == source_encoder)
Jesse Barnes79e53942008-11-07 14:24:08 -08006611 index_mask |= (1 << entry);
Daniel Vetter66a92782012-07-12 20:08:18 +02006612
6613 /* Intel hw has only one MUX where enocoders could be cloned. */
6614 if (encoder->cloneable && source_encoder->cloneable)
6615 index_mask |= (1 << entry);
6616
Jesse Barnes79e53942008-11-07 14:24:08 -08006617 entry++;
6618 }
Chris Wilson4ef69c72010-09-09 15:14:28 +01006619
Jesse Barnes79e53942008-11-07 14:24:08 -08006620 return index_mask;
6621}
6622
Chris Wilson4d302442010-12-14 19:21:29 +00006623static bool has_edp_a(struct drm_device *dev)
6624{
6625 struct drm_i915_private *dev_priv = dev->dev_private;
6626
6627 if (!IS_MOBILE(dev))
6628 return false;
6629
6630 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6631 return false;
6632
6633 if (IS_GEN5(dev) &&
6634 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6635 return false;
6636
6637 return true;
6638}
6639
Jesse Barnes79e53942008-11-07 14:24:08 -08006640static void intel_setup_outputs(struct drm_device *dev)
6641{
Eric Anholt725e30a2009-01-22 13:01:02 -08006642 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson4ef69c72010-09-09 15:14:28 +01006643 struct intel_encoder *encoder;
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006644 bool dpd_is_edp = false;
Chris Wilsonf3cfcba2012-02-09 09:35:53 +00006645 bool has_lvds;
Jesse Barnes79e53942008-11-07 14:24:08 -08006646
Chris Wilsonf3cfcba2012-02-09 09:35:53 +00006647 has_lvds = intel_lvds_init(dev);
Chris Wilsonc5d1b512010-11-29 18:00:23 +00006648 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6649 /* disable the panel fitter on everything but LVDS */
6650 I915_WRITE(PFIT_CONTROL, 0);
6651 }
Jesse Barnes79e53942008-11-07 14:24:08 -08006652
Eric Anholtbad720f2009-10-22 16:11:14 -07006653 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006654 dpd_is_edp = intel_dpd_is_edp(dev);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006655
Chris Wilson4d302442010-12-14 19:21:29 +00006656 if (has_edp_a(dev))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03006657 intel_dp_init(dev, DP_A, PORT_A);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08006658
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006659 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03006660 intel_dp_init(dev, PCH_DP_D, PORT_D);
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006661 }
6662
6663 intel_crt_init(dev);
6664
Eugeni Dodonov0e72a5b2012-05-09 15:37:27 -03006665 if (IS_HASWELL(dev)) {
6666 int found;
6667
6668 /* Haswell uses DDI functions to detect digital outputs */
6669 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6670 /* DDI A only supports eDP */
6671 if (found)
6672 intel_ddi_init(dev, PORT_A);
6673
6674 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6675 * register */
6676 found = I915_READ(SFUSE_STRAP);
6677
6678 if (found & SFUSE_STRAP_DDIB_DETECTED)
6679 intel_ddi_init(dev, PORT_B);
6680 if (found & SFUSE_STRAP_DDIC_DETECTED)
6681 intel_ddi_init(dev, PORT_C);
6682 if (found & SFUSE_STRAP_DDID_DETECTED)
6683 intel_ddi_init(dev, PORT_D);
6684 } else if (HAS_PCH_SPLIT(dev)) {
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006685 int found;
6686
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006687 if (I915_READ(HDMIB) & PORT_DETECTED) {
Zhao Yakui461ed3c2010-03-30 15:11:33 +08006688 /* PCH SDVOB multiplex with HDMIB */
Daniel Vettereef4eac2012-03-23 23:43:35 +01006689 found = intel_sdvo_init(dev, PCH_SDVOB, true);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006690 if (!found)
Daniel Vetter08d644a2012-07-12 20:19:59 +02006691 intel_hdmi_init(dev, HDMIB, PORT_B);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006692 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03006693 intel_dp_init(dev, PCH_DP_B, PORT_B);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006694 }
6695
6696 if (I915_READ(HDMIC) & PORT_DETECTED)
Daniel Vetter08d644a2012-07-12 20:19:59 +02006697 intel_hdmi_init(dev, HDMIC, PORT_C);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006698
Jesse Barnesb708a1d2012-06-11 14:39:56 -04006699 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
Daniel Vetter08d644a2012-07-12 20:19:59 +02006700 intel_hdmi_init(dev, HDMID, PORT_D);
Zhenyu Wang30ad48b2009-06-05 15:38:43 +08006701
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006702 if (I915_READ(PCH_DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03006703 intel_dp_init(dev, PCH_DP_C, PORT_C);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006704
Adam Jacksoncb0953d2010-07-16 14:46:29 -04006705 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03006706 intel_dp_init(dev, PCH_DP_D, PORT_D);
Jesse Barnes4a87d652012-06-15 11:55:16 -07006707 } else if (IS_VALLEYVIEW(dev)) {
6708 int found;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08006709
Jesse Barnes4a87d652012-06-15 11:55:16 -07006710 if (I915_READ(SDVOB) & PORT_DETECTED) {
6711 /* SDVOB multiplex with HDMIB */
6712 found = intel_sdvo_init(dev, SDVOB, true);
6713 if (!found)
Daniel Vetter08d644a2012-07-12 20:19:59 +02006714 intel_hdmi_init(dev, SDVOB, PORT_B);
Jesse Barnes4a87d652012-06-15 11:55:16 -07006715 if (!found && (I915_READ(DP_B) & DP_DETECTED))
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03006716 intel_dp_init(dev, DP_B, PORT_B);
Jesse Barnes4a87d652012-06-15 11:55:16 -07006717 }
6718
6719 if (I915_READ(SDVOC) & PORT_DETECTED)
Daniel Vetter08d644a2012-07-12 20:19:59 +02006720 intel_hdmi_init(dev, SDVOC, PORT_C);
Jesse Barnes4a87d652012-06-15 11:55:16 -07006721
6722 /* Shares lanes with HDMI on SDVOC */
6723 if (I915_READ(DP_C) & DP_DETECTED)
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03006724 intel_dp_init(dev, DP_C, PORT_C);
Zhenyu Wang103a1962009-11-27 11:44:36 +08006725 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
Ma Ling27185ae2009-08-24 13:50:23 +08006726 bool found = false;
Eric Anholt7d573822009-01-02 13:33:00 -08006727
Eric Anholt725e30a2009-01-22 13:01:02 -08006728 if (I915_READ(SDVOB) & SDVO_DETECTED) {
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006729 DRM_DEBUG_KMS("probing SDVOB\n");
Daniel Vettereef4eac2012-03-23 23:43:35 +01006730 found = intel_sdvo_init(dev, SDVOB, true);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006731 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6732 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
Daniel Vetter08d644a2012-07-12 20:19:59 +02006733 intel_hdmi_init(dev, SDVOB, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006734 }
Ma Ling27185ae2009-08-24 13:50:23 +08006735
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006736 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6737 DRM_DEBUG_KMS("probing DP_B\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03006738 intel_dp_init(dev, DP_B, PORT_B);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006739 }
Eric Anholt725e30a2009-01-22 13:01:02 -08006740 }
Kristian Høgsberg13520b02009-03-13 15:42:14 -04006741
6742 /* Before G4X SDVOC doesn't have its own detect register */
Kristian Høgsberg13520b02009-03-13 15:42:14 -04006743
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006744 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6745 DRM_DEBUG_KMS("probing SDVOC\n");
Daniel Vettereef4eac2012-03-23 23:43:35 +01006746 found = intel_sdvo_init(dev, SDVOC, false);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006747 }
Ma Ling27185ae2009-08-24 13:50:23 +08006748
6749 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6750
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006751 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6752 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
Daniel Vetter08d644a2012-07-12 20:19:59 +02006753 intel_hdmi_init(dev, SDVOC, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006754 }
6755 if (SUPPORTS_INTEGRATED_DP(dev)) {
6756 DRM_DEBUG_KMS("probing DP_C\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03006757 intel_dp_init(dev, DP_C, PORT_C);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006758 }
Eric Anholt725e30a2009-01-22 13:01:02 -08006759 }
Ma Ling27185ae2009-08-24 13:50:23 +08006760
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006761 if (SUPPORTS_INTEGRATED_DP(dev) &&
6762 (I915_READ(DP_D) & DP_DETECTED)) {
6763 DRM_DEBUG_KMS("probing DP_D\n");
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03006764 intel_dp_init(dev, DP_D, PORT_D);
Jesse Barnesb01f2c32009-12-11 11:07:17 -08006765 }
Eric Anholtbad720f2009-10-22 16:11:14 -07006766 } else if (IS_GEN2(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08006767 intel_dvo_init(dev);
6768
Zhenyu Wang103a1962009-11-27 11:44:36 +08006769 if (SUPPORTS_TV(dev))
Jesse Barnes79e53942008-11-07 14:24:08 -08006770 intel_tv_init(dev);
6771
Chris Wilson4ef69c72010-09-09 15:14:28 +01006772 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6773 encoder->base.possible_crtcs = encoder->crtc_mask;
6774 encoder->base.possible_clones =
Daniel Vetter66a92782012-07-12 20:08:18 +02006775 intel_encoder_clones(encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -08006776 }
Chris Wilson47356eb2011-01-11 17:06:04 +00006777
Chris Wilson2c7111d2011-03-29 10:40:27 +01006778 /* disable all the possible outputs/crtcs before entering KMS mode */
6779 drm_helper_disable_unused_functions(dev);
Keith Packard9fb526d2011-09-26 22:24:57 -07006780
Paulo Zanoni40579ab2012-07-03 15:57:33 -03006781 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
Keith Packard9fb526d2011-09-26 22:24:57 -07006782 ironlake_init_pch_refclk(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08006783}
6784
6785static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6786{
6787 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Jesse Barnes79e53942008-11-07 14:24:08 -08006788
6789 drm_framebuffer_cleanup(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00006790 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08006791
6792 kfree(intel_fb);
6793}
6794
6795static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
Chris Wilson05394f32010-11-08 19:18:58 +00006796 struct drm_file *file,
Jesse Barnes79e53942008-11-07 14:24:08 -08006797 unsigned int *handle)
6798{
6799 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
Chris Wilson05394f32010-11-08 19:18:58 +00006800 struct drm_i915_gem_object *obj = intel_fb->obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08006801
Chris Wilson05394f32010-11-08 19:18:58 +00006802 return drm_gem_handle_create(file, &obj->base, handle);
Jesse Barnes79e53942008-11-07 14:24:08 -08006803}
6804
6805static const struct drm_framebuffer_funcs intel_fb_funcs = {
6806 .destroy = intel_user_framebuffer_destroy,
6807 .create_handle = intel_user_framebuffer_create_handle,
6808};
6809
Dave Airlie38651672010-03-30 05:34:13 +00006810int intel_framebuffer_init(struct drm_device *dev,
6811 struct intel_framebuffer *intel_fb,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006812 struct drm_mode_fb_cmd2 *mode_cmd,
Chris Wilson05394f32010-11-08 19:18:58 +00006813 struct drm_i915_gem_object *obj)
Jesse Barnes79e53942008-11-07 14:24:08 -08006814{
Jesse Barnes79e53942008-11-07 14:24:08 -08006815 int ret;
6816
Chris Wilson05394f32010-11-08 19:18:58 +00006817 if (obj->tiling_mode == I915_TILING_Y)
Chris Wilson57cd6502010-08-08 12:34:44 +01006818 return -EINVAL;
6819
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006820 if (mode_cmd->pitches[0] & 63)
Chris Wilson57cd6502010-08-08 12:34:44 +01006821 return -EINVAL;
6822
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006823 switch (mode_cmd->pixel_format) {
Ville Syrjälä04b39242011-11-17 18:05:13 +02006824 case DRM_FORMAT_RGB332:
6825 case DRM_FORMAT_RGB565:
6826 case DRM_FORMAT_XRGB8888:
Jesse Barnesb250da72012-03-07 08:49:29 -08006827 case DRM_FORMAT_XBGR8888:
Ville Syrjälä04b39242011-11-17 18:05:13 +02006828 case DRM_FORMAT_ARGB8888:
6829 case DRM_FORMAT_XRGB2101010:
6830 case DRM_FORMAT_ARGB2101010:
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006831 /* RGB formats are common across chipsets */
Jesse Barnesb5626742011-06-24 12:19:27 -07006832 break;
Ville Syrjälä04b39242011-11-17 18:05:13 +02006833 case DRM_FORMAT_YUYV:
6834 case DRM_FORMAT_UYVY:
6835 case DRM_FORMAT_YVYU:
6836 case DRM_FORMAT_VYUY:
Chris Wilson57cd6502010-08-08 12:34:44 +01006837 break;
6838 default:
Eugeni Dodonovaca25842012-01-17 15:25:45 -02006839 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6840 mode_cmd->pixel_format);
Chris Wilson57cd6502010-08-08 12:34:44 +01006841 return -EINVAL;
6842 }
6843
Jesse Barnes79e53942008-11-07 14:24:08 -08006844 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6845 if (ret) {
6846 DRM_ERROR("framebuffer init failed %d\n", ret);
6847 return ret;
6848 }
6849
6850 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
Jesse Barnes79e53942008-11-07 14:24:08 -08006851 intel_fb->obj = obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08006852 return 0;
6853}
6854
Jesse Barnes79e53942008-11-07 14:24:08 -08006855static struct drm_framebuffer *
6856intel_user_framebuffer_create(struct drm_device *dev,
6857 struct drm_file *filp,
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006858 struct drm_mode_fb_cmd2 *mode_cmd)
Jesse Barnes79e53942008-11-07 14:24:08 -08006859{
Chris Wilson05394f32010-11-08 19:18:58 +00006860 struct drm_i915_gem_object *obj;
Jesse Barnes79e53942008-11-07 14:24:08 -08006861
Jesse Barnes308e5bc2011-11-14 14:51:28 -08006862 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6863 mode_cmd->handles[0]));
Chris Wilsonc8725222011-02-19 11:31:06 +00006864 if (&obj->base == NULL)
Chris Wilsoncce13ff2010-08-08 13:36:38 +01006865 return ERR_PTR(-ENOENT);
Jesse Barnes79e53942008-11-07 14:24:08 -08006866
Chris Wilsond2dff872011-04-19 08:36:26 +01006867 return intel_framebuffer_create(dev, mode_cmd, obj);
Jesse Barnes79e53942008-11-07 14:24:08 -08006868}
6869
Jesse Barnes79e53942008-11-07 14:24:08 -08006870static const struct drm_mode_config_funcs intel_mode_funcs = {
Jesse Barnes79e53942008-11-07 14:24:08 -08006871 .fb_create = intel_user_framebuffer_create,
Dave Airlieeb1f8e42010-05-07 06:42:51 +00006872 .output_poll_changed = intel_fb_output_poll_changed,
Jesse Barnes79e53942008-11-07 14:24:08 -08006873};
6874
Jesse Barnese70236a2009-09-21 10:42:27 -07006875/* Set up chip specific display functions */
6876static void intel_init_display(struct drm_device *dev)
6877{
6878 struct drm_i915_private *dev_priv = dev->dev_private;
6879
6880 /* We always want a DPMS function */
Eric Anholtf564048e2011-03-30 13:01:02 -07006881 if (HAS_PCH_SPLIT(dev)) {
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006882 dev_priv->display.dpms = ironlake_crtc_dpms;
Eric Anholtf564048e2011-03-30 13:01:02 -07006883 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006884 dev_priv->display.off = ironlake_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -07006885 dev_priv->display.update_plane = ironlake_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07006886 } else {
Jesse Barnese70236a2009-09-21 10:42:27 -07006887 dev_priv->display.dpms = i9xx_crtc_dpms;
Eric Anholtf564048e2011-03-30 13:01:02 -07006888 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
Jesse Barnesee7b9f92012-04-20 17:11:53 +01006889 dev_priv->display.off = i9xx_crtc_off;
Jesse Barnes17638cd2011-06-24 12:19:23 -07006890 dev_priv->display.update_plane = i9xx_update_plane;
Eric Anholtf564048e2011-03-30 13:01:02 -07006891 }
Jesse Barnese70236a2009-09-21 10:42:27 -07006892
Jesse Barnese70236a2009-09-21 10:42:27 -07006893 /* Returns the core display clock speed */
Jesse Barnes25eb05fc2012-03-28 13:39:23 -07006894 if (IS_VALLEYVIEW(dev))
6895 dev_priv->display.get_display_clock_speed =
6896 valleyview_get_display_clock_speed;
6897 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
Jesse Barnese70236a2009-09-21 10:42:27 -07006898 dev_priv->display.get_display_clock_speed =
6899 i945_get_display_clock_speed;
6900 else if (IS_I915G(dev))
6901 dev_priv->display.get_display_clock_speed =
6902 i915_get_display_clock_speed;
Adam Jacksonf2b115e2009-12-03 17:14:42 -05006903 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07006904 dev_priv->display.get_display_clock_speed =
6905 i9xx_misc_get_display_clock_speed;
6906 else if (IS_I915GM(dev))
6907 dev_priv->display.get_display_clock_speed =
6908 i915gm_get_display_clock_speed;
6909 else if (IS_I865G(dev))
6910 dev_priv->display.get_display_clock_speed =
6911 i865_get_display_clock_speed;
Daniel Vetterf0f8a9c2009-09-15 22:57:33 +02006912 else if (IS_I85X(dev))
Jesse Barnese70236a2009-09-21 10:42:27 -07006913 dev_priv->display.get_display_clock_speed =
6914 i855_get_display_clock_speed;
6915 else /* 852, 830 */
6916 dev_priv->display.get_display_clock_speed =
6917 i830_get_display_clock_speed;
6918
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006919 if (HAS_PCH_SPLIT(dev)) {
Chris Wilsonf00a3dd2010-10-21 14:57:17 +01006920 if (IS_GEN5(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -07006921 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08006922 dev_priv->display.write_eld = ironlake_write_eld;
Yuanhan Liu13982612010-12-15 15:42:31 +08006923 } else if (IS_GEN6(dev)) {
Jesse Barnes674cf962011-04-28 14:27:04 -07006924 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08006925 dev_priv->display.write_eld = ironlake_write_eld;
Jesse Barnes357555c2011-04-28 15:09:55 -07006926 } else if (IS_IVYBRIDGE(dev)) {
6927 /* FIXME: detect B0+ stepping and use auto training */
6928 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
Wu Fengguange0dac652011-09-05 14:25:34 +08006929 dev_priv->display.write_eld = ironlake_write_eld;
Eugeni Dodonovc82e4d22012-05-09 15:37:21 -03006930 } else if (IS_HASWELL(dev)) {
6931 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
Eugeni Dodonov4abb3c82012-05-09 15:37:22 -03006932 dev_priv->display.write_eld = ironlake_write_eld;
Zhenyu Wang7f8a8562010-04-01 13:07:53 +08006933 } else
6934 dev_priv->display.update_wm = NULL;
Jesse Barnes6067aae2011-04-28 15:04:31 -07006935 } else if (IS_G4X(dev)) {
Wu Fengguange0dac652011-09-05 14:25:34 +08006936 dev_priv->display.write_eld = g4x_write_eld;
Jesse Barnese70236a2009-09-21 10:42:27 -07006937 }
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006938
6939 /* Default just returns -ENODEV to indicate unsupported */
6940 dev_priv->display.queue_flip = intel_default_queue_flip;
6941
6942 switch (INTEL_INFO(dev)->gen) {
6943 case 2:
6944 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6945 break;
6946
6947 case 3:
6948 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6949 break;
6950
6951 case 4:
6952 case 5:
6953 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6954 break;
6955
6956 case 6:
6957 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6958 break;
Jesse Barnes7c9017e2011-06-16 12:18:54 -07006959 case 7:
6960 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6961 break;
Jesse Barnes8c9f3aa2011-06-16 09:19:13 -07006962 }
Jesse Barnese70236a2009-09-21 10:42:27 -07006963}
6964
Jesse Barnesb690e962010-07-19 13:53:12 -07006965/*
6966 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6967 * resume, or other times. This quirk makes sure that's the case for
6968 * affected systems.
6969 */
Akshay Joshi0206e352011-08-16 15:34:10 -04006970static void quirk_pipea_force(struct drm_device *dev)
Jesse Barnesb690e962010-07-19 13:53:12 -07006971{
6972 struct drm_i915_private *dev_priv = dev->dev_private;
6973
6974 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02006975 DRM_INFO("applying pipe a force quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -07006976}
6977
Keith Packard435793d2011-07-12 14:56:22 -07006978/*
6979 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6980 */
6981static void quirk_ssc_force_disable(struct drm_device *dev)
6982{
6983 struct drm_i915_private *dev_priv = dev->dev_private;
6984 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02006985 DRM_INFO("applying lvds SSC disable quirk\n");
Keith Packard435793d2011-07-12 14:56:22 -07006986}
6987
Carsten Emde4dca20e2012-03-15 15:56:26 +01006988/*
Carsten Emde5a15ab52012-03-15 15:56:27 +01006989 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6990 * brightness value
Carsten Emde4dca20e2012-03-15 15:56:26 +01006991 */
6992static void quirk_invert_brightness(struct drm_device *dev)
6993{
6994 struct drm_i915_private *dev_priv = dev->dev_private;
6995 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
Daniel Vetterbc0daf42012-04-01 13:16:49 +02006996 DRM_INFO("applying inverted panel brightness quirk\n");
Jesse Barnesb690e962010-07-19 13:53:12 -07006997}
6998
6999struct intel_quirk {
7000 int device;
7001 int subsystem_vendor;
7002 int subsystem_device;
7003 void (*hook)(struct drm_device *dev);
7004};
7005
Ben Widawskyc43b5632012-04-16 14:07:40 -07007006static struct intel_quirk intel_quirks[] = {
Jesse Barnesb690e962010-07-19 13:53:12 -07007007 /* HP Mini needs pipe A force quirk (LP: #322104) */
Akshay Joshi0206e352011-08-16 15:34:10 -04007008 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
Jesse Barnesb690e962010-07-19 13:53:12 -07007009
Jesse Barnesb690e962010-07-19 13:53:12 -07007010 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7011 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7012
Jesse Barnesb690e962010-07-19 13:53:12 -07007013 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7014 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7015
7016 /* 855 & before need to leave pipe A & dpll A up */
7017 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7018 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Daniel Vetterdcdaed62012-08-12 21:19:34 +02007019 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
Keith Packard435793d2011-07-12 14:56:22 -07007020
7021 /* Lenovo U160 cannot use SSC on LVDS */
7022 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
Michel Alexandre Salim070d3292011-07-28 18:52:06 +02007023
7024 /* Sony Vaio Y cannot use SSC on LVDS */
7025 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
Carsten Emde5a15ab52012-03-15 15:56:27 +01007026
7027 /* Acer Aspire 5734Z must invert backlight brightness */
7028 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
Jesse Barnesb690e962010-07-19 13:53:12 -07007029};
7030
7031static void intel_init_quirks(struct drm_device *dev)
7032{
7033 struct pci_dev *d = dev->pdev;
7034 int i;
7035
7036 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7037 struct intel_quirk *q = &intel_quirks[i];
7038
7039 if (d->device == q->device &&
7040 (d->subsystem_vendor == q->subsystem_vendor ||
7041 q->subsystem_vendor == PCI_ANY_ID) &&
7042 (d->subsystem_device == q->subsystem_device ||
7043 q->subsystem_device == PCI_ANY_ID))
7044 q->hook(dev);
7045 }
7046}
7047
Jesse Barnes9cce37f2010-08-13 15:11:26 -07007048/* Disable the VGA plane that we never use */
7049static void i915_disable_vga(struct drm_device *dev)
7050{
7051 struct drm_i915_private *dev_priv = dev->dev_private;
7052 u8 sr1;
7053 u32 vga_reg;
7054
7055 if (HAS_PCH_SPLIT(dev))
7056 vga_reg = CPU_VGACNTRL;
7057 else
7058 vga_reg = VGACNTRL;
7059
7060 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
Jesse Barnes3fdcf432012-04-06 11:46:27 -07007061 outb(SR01, VGA_SR_INDEX);
Jesse Barnes9cce37f2010-08-13 15:11:26 -07007062 sr1 = inb(VGA_SR_DATA);
7063 outb(sr1 | 1<<5, VGA_SR_DATA);
7064 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7065 udelay(300);
7066
7067 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7068 POSTING_READ(vga_reg);
7069}
7070
Daniel Vetterf8175862012-04-10 15:50:11 +02007071void intel_modeset_init_hw(struct drm_device *dev)
7072{
Eugeni Dodonov0232e922012-07-06 15:42:36 -03007073 /* We attempt to init the necessary power wells early in the initialization
7074 * time, so the subsystems that expect power to be enabled can work.
7075 */
7076 intel_init_power_wells(dev);
7077
Eugeni Dodonova8f78b52012-06-28 15:55:35 -03007078 intel_prepare_ddi(dev);
7079
Daniel Vetterf8175862012-04-10 15:50:11 +02007080 intel_init_clock_gating(dev);
7081
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02007082 mutex_lock(&dev->struct_mutex);
Daniel Vetter8090c6b2012-06-24 16:42:32 +02007083 intel_enable_gt_powersave(dev);
Daniel Vetter79f5b2c2012-06-24 16:42:33 +02007084 mutex_unlock(&dev->struct_mutex);
Daniel Vetterf8175862012-04-10 15:50:11 +02007085}
7086
Jesse Barnes79e53942008-11-07 14:24:08 -08007087void intel_modeset_init(struct drm_device *dev)
7088{
Jesse Barnes652c3932009-08-17 13:31:43 -07007089 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08007090 int i, ret;
Jesse Barnes79e53942008-11-07 14:24:08 -08007091
7092 drm_mode_config_init(dev);
7093
7094 dev->mode_config.min_width = 0;
7095 dev->mode_config.min_height = 0;
7096
Dave Airlie019d96c2011-09-29 16:20:42 +01007097 dev->mode_config.preferred_depth = 24;
7098 dev->mode_config.prefer_shadow = 1;
7099
Laurent Pincharte6ecefa2012-05-17 13:27:23 +02007100 dev->mode_config.funcs = &intel_mode_funcs;
Jesse Barnes79e53942008-11-07 14:24:08 -08007101
Jesse Barnesb690e962010-07-19 13:53:12 -07007102 intel_init_quirks(dev);
7103
Eugeni Dodonov1fa61102012-04-18 15:29:26 -03007104 intel_init_pm(dev);
7105
Jesse Barnese70236a2009-09-21 10:42:27 -07007106 intel_init_display(dev);
7107
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007108 if (IS_GEN2(dev)) {
7109 dev->mode_config.max_width = 2048;
7110 dev->mode_config.max_height = 2048;
7111 } else if (IS_GEN3(dev)) {
Keith Packard5e4d6fa2009-07-12 23:53:17 -07007112 dev->mode_config.max_width = 4096;
7113 dev->mode_config.max_height = 4096;
Jesse Barnes79e53942008-11-07 14:24:08 -08007114 } else {
Chris Wilsona6c45cf2010-09-17 00:32:17 +01007115 dev->mode_config.max_width = 8192;
7116 dev->mode_config.max_height = 8192;
Jesse Barnes79e53942008-11-07 14:24:08 -08007117 }
Daniel Vetterdd2757f2012-06-07 15:55:57 +02007118 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
Jesse Barnes79e53942008-11-07 14:24:08 -08007119
Zhao Yakui28c97732009-10-09 11:39:41 +08007120 DRM_DEBUG_KMS("%d display pipe%s available.\n",
Dave Airliea3524f12010-06-06 18:59:41 +10007121 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
Jesse Barnes79e53942008-11-07 14:24:08 -08007122
Dave Airliea3524f12010-06-06 18:59:41 +10007123 for (i = 0; i < dev_priv->num_pipe; i++) {
Jesse Barnes79e53942008-11-07 14:24:08 -08007124 intel_crtc_init(dev, i);
Jesse Barnes00c2064b2012-01-13 15:48:39 -08007125 ret = intel_plane_init(dev, i);
7126 if (ret)
7127 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
Jesse Barnes79e53942008-11-07 14:24:08 -08007128 }
7129
Jesse Barnesee7b9f92012-04-20 17:11:53 +01007130 intel_pch_pll_init(dev);
7131
Jesse Barnes9cce37f2010-08-13 15:11:26 -07007132 /* Just disable it once at startup */
7133 i915_disable_vga(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08007134 intel_setup_outputs(dev);
Chris Wilson2c7111d2011-03-29 10:40:27 +01007135}
7136
7137void intel_modeset_gem_init(struct drm_device *dev)
7138{
Chris Wilson1833b132012-05-09 11:56:28 +01007139 intel_modeset_init_hw(dev);
Daniel Vetter02e792f2009-09-15 22:57:34 +02007140
7141 intel_setup_overlay(dev);
Jesse Barnes79e53942008-11-07 14:24:08 -08007142}
7143
7144void intel_modeset_cleanup(struct drm_device *dev)
7145{
Jesse Barnes652c3932009-08-17 13:31:43 -07007146 struct drm_i915_private *dev_priv = dev->dev_private;
7147 struct drm_crtc *crtc;
7148 struct intel_crtc *intel_crtc;
7149
Keith Packardf87ea762010-10-03 19:36:26 -07007150 drm_kms_helper_poll_fini(dev);
Jesse Barnes652c3932009-08-17 13:31:43 -07007151 mutex_lock(&dev->struct_mutex);
7152
Jesse Barnes723bfd72010-10-07 16:01:13 -07007153 intel_unregister_dsm_handler();
7154
7155
Jesse Barnes652c3932009-08-17 13:31:43 -07007156 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7157 /* Skip inactive CRTCs */
7158 if (!crtc->fb)
7159 continue;
7160
7161 intel_crtc = to_intel_crtc(crtc);
Daniel Vetter3dec0092010-08-20 21:40:52 +02007162 intel_increase_pllclock(crtc);
Jesse Barnes652c3932009-08-17 13:31:43 -07007163 }
7164
Chris Wilson973d04f2011-07-08 12:22:37 +01007165 intel_disable_fbc(dev);
Jesse Barnese70236a2009-09-21 10:42:27 -07007166
Daniel Vetter8090c6b2012-06-24 16:42:32 +02007167 intel_disable_gt_powersave(dev);
Chris Wilson0cdab212010-12-05 17:27:06 +00007168
Daniel Vetter930ebb42012-06-29 23:32:16 +02007169 ironlake_teardown_rc6(dev);
7170
Jesse Barnes57f350b2012-03-28 13:39:25 -07007171 if (IS_VALLEYVIEW(dev))
7172 vlv_init_dpio(dev);
7173
Kristian Høgsberg69341a52009-11-11 12:19:17 -05007174 mutex_unlock(&dev->struct_mutex);
7175
Daniel Vetter6c0d93502010-08-20 18:26:46 +02007176 /* Disable the irq before mode object teardown, for the irq might
7177 * enqueue unpin/hotplug work. */
7178 drm_irq_uninstall(dev);
7179 cancel_work_sync(&dev_priv->hotplug_work);
Daniel Vetterc6a828d2012-08-08 23:35:35 +02007180 cancel_work_sync(&dev_priv->rps.work);
Daniel Vetter6c0d93502010-08-20 18:26:46 +02007181
Chris Wilson1630fe72011-07-08 12:22:42 +01007182 /* flush any delayed tasks or pending work */
7183 flush_scheduled_work();
7184
Jesse Barnes79e53942008-11-07 14:24:08 -08007185 drm_mode_config_cleanup(dev);
7186}
7187
Dave Airlie28d52042009-09-21 14:33:58 +10007188/*
Zhenyu Wangf1c79df2010-03-30 14:39:29 +08007189 * Return which encoder is currently attached for connector.
7190 */
Chris Wilsondf0e9242010-09-09 16:20:55 +01007191struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
Jesse Barnes79e53942008-11-07 14:24:08 -08007192{
Chris Wilsondf0e9242010-09-09 16:20:55 +01007193 return &intel_attached_encoder(connector)->base;
7194}
Jesse Barnes79e53942008-11-07 14:24:08 -08007195
Chris Wilsondf0e9242010-09-09 16:20:55 +01007196void intel_connector_attach_encoder(struct intel_connector *connector,
7197 struct intel_encoder *encoder)
7198{
7199 connector->encoder = encoder;
7200 drm_mode_connector_attach_encoder(&connector->base,
7201 &encoder->base);
Jesse Barnes79e53942008-11-07 14:24:08 -08007202}
Dave Airlie28d52042009-09-21 14:33:58 +10007203
7204/*
7205 * set vga decode state - true == enable VGA decode
7206 */
7207int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7208{
7209 struct drm_i915_private *dev_priv = dev->dev_private;
7210 u16 gmch_ctrl;
7211
7212 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7213 if (state)
7214 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7215 else
7216 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7217 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7218 return 0;
7219}
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00007220
7221#ifdef CONFIG_DEBUG_FS
7222#include <linux/seq_file.h>
7223
7224struct intel_display_error_state {
7225 struct intel_cursor_error_state {
7226 u32 control;
7227 u32 position;
7228 u32 base;
7229 u32 size;
7230 } cursor[2];
7231
7232 struct intel_pipe_error_state {
7233 u32 conf;
7234 u32 source;
7235
7236 u32 htotal;
7237 u32 hblank;
7238 u32 hsync;
7239 u32 vtotal;
7240 u32 vblank;
7241 u32 vsync;
7242 } pipe[2];
7243
7244 struct intel_plane_error_state {
7245 u32 control;
7246 u32 stride;
7247 u32 size;
7248 u32 pos;
7249 u32 addr;
7250 u32 surface;
7251 u32 tile_offset;
7252 } plane[2];
7253};
7254
7255struct intel_display_error_state *
7256intel_display_capture_error_state(struct drm_device *dev)
7257{
Akshay Joshi0206e352011-08-16 15:34:10 -04007258 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00007259 struct intel_display_error_state *error;
7260 int i;
7261
7262 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7263 if (error == NULL)
7264 return NULL;
7265
7266 for (i = 0; i < 2; i++) {
7267 error->cursor[i].control = I915_READ(CURCNTR(i));
7268 error->cursor[i].position = I915_READ(CURPOS(i));
7269 error->cursor[i].base = I915_READ(CURBASE(i));
7270
7271 error->plane[i].control = I915_READ(DSPCNTR(i));
7272 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7273 error->plane[i].size = I915_READ(DSPSIZE(i));
Akshay Joshi0206e352011-08-16 15:34:10 -04007274 error->plane[i].pos = I915_READ(DSPPOS(i));
Chris Wilsonc4a1d9e2010-11-21 13:12:35 +00007275 error->plane[i].addr = I915_READ(DSPADDR(i));
7276 if (INTEL_INFO(dev)->gen >= 4) {
7277 error->plane[i].surface = I915_READ(DSPSURF(i));
7278 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7279 }
7280
7281 error->pipe[i].conf = I915_READ(PIPECONF(i));
7282 error->pipe[i].source = I915_READ(PIPESRC(i));
7283 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7284 error->pipe[i].hblank = I915_READ(HBLANK(i));
7285 error->pipe[i].hsync = I915_READ(HSYNC(i));
7286 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7287 error->pipe[i].vblank = I915_READ(VBLANK(i));
7288 error->pipe[i].vsync = I915_READ(VSYNC(i));
7289 }
7290
7291 return error;
7292}
7293
7294void
7295intel_display_print_error_state(struct seq_file *m,
7296 struct drm_device *dev,
7297 struct intel_display_error_state *error)
7298{
7299 int i;
7300
7301 for (i = 0; i < 2; i++) {
7302 seq_printf(m, "Pipe [%d]:\n", i);
7303 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7304 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7305 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7306 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7307 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7308 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7309 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7310 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7311
7312 seq_printf(m, "Plane [%d]:\n", i);
7313 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7314 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7315 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7316 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7317 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7318 if (INTEL_INFO(dev)->gen >= 4) {
7319 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7320 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7321 }
7322
7323 seq_printf(m, "Cursor [%d]:\n", i);
7324 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7325 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7326 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7327 }
7328}
7329#endif