Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 35 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include <linux/pci.h> |
Zhenyu Wang | f8f235e | 2010-08-27 11:08:57 +0800 | [diff] [blame] | 37 | #include <linux/intel-gtt.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 38 | |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 40 | |
| 41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
| 42 | bool pipelined); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
| 44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
| 46 | int write); |
| 47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 48 | uint64_t offset, |
| 49 | uint64_t size); |
| 50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
| 52 | bool interruptible); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 54 | unsigned alignment, bool mappable); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 57 | struct drm_i915_gem_pwrite *args, |
| 58 | struct drm_file *file_priv); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 60 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 61 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
| 62 | int nr_to_scan, |
| 63 | gfp_t gfp_mask); |
| 64 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 65 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 66 | /* some bookkeeping */ |
| 67 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, |
| 68 | size_t size) |
| 69 | { |
| 70 | dev_priv->mm.object_count++; |
| 71 | dev_priv->mm.object_memory += size; |
| 72 | } |
| 73 | |
| 74 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, |
| 75 | size_t size) |
| 76 | { |
| 77 | dev_priv->mm.object_count--; |
| 78 | dev_priv->mm.object_memory -= size; |
| 79 | } |
| 80 | |
| 81 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 82 | struct drm_gem_object *obj) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 83 | { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 84 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 85 | dev_priv->mm.gtt_count++; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 86 | dev_priv->mm.gtt_memory += obj->size; |
| 87 | if (obj_priv->gtt_offset < dev_priv->mm.gtt_mappable_end) { |
| 88 | dev_priv->mm.mappable_gtt_used += |
| 89 | min_t(size_t, obj->size, |
| 90 | dev_priv->mm.gtt_mappable_end |
| 91 | - obj_priv->gtt_offset); |
| 92 | } |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 93 | } |
| 94 | |
| 95 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 96 | struct drm_gem_object *obj) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 97 | { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 98 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 99 | dev_priv->mm.gtt_count--; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 100 | dev_priv->mm.gtt_memory -= obj->size; |
| 101 | if (obj_priv->gtt_offset < dev_priv->mm.gtt_mappable_end) { |
| 102 | dev_priv->mm.mappable_gtt_used -= |
| 103 | min_t(size_t, obj->size, |
| 104 | dev_priv->mm.gtt_mappable_end |
| 105 | - obj_priv->gtt_offset); |
| 106 | } |
| 107 | } |
| 108 | |
| 109 | /** |
| 110 | * Update the mappable working set counters. Call _only_ when there is a change |
| 111 | * in one of (pin|fault)_mappable and update *_mappable _before_ calling. |
| 112 | * @mappable: new state the changed mappable flag (either pin_ or fault_). |
| 113 | */ |
| 114 | static void |
| 115 | i915_gem_info_update_mappable(struct drm_i915_private *dev_priv, |
| 116 | struct drm_gem_object *obj, |
| 117 | bool mappable) |
| 118 | { |
| 119 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
| 120 | |
| 121 | if (mappable) { |
| 122 | if (obj_priv->pin_mappable && obj_priv->fault_mappable) |
| 123 | /* Combined state was already mappable. */ |
| 124 | return; |
| 125 | dev_priv->mm.gtt_mappable_count++; |
| 126 | dev_priv->mm.gtt_mappable_memory += obj->size; |
| 127 | } else { |
| 128 | if (obj_priv->pin_mappable || obj_priv->fault_mappable) |
| 129 | /* Combined state still mappable. */ |
| 130 | return; |
| 131 | dev_priv->mm.gtt_mappable_count--; |
| 132 | dev_priv->mm.gtt_mappable_memory -= obj->size; |
| 133 | } |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 134 | } |
| 135 | |
| 136 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 137 | struct drm_gem_object *obj, |
| 138 | bool mappable) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 139 | { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 140 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 141 | dev_priv->mm.pin_count++; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 142 | dev_priv->mm.pin_memory += obj->size; |
| 143 | if (mappable) { |
| 144 | obj_priv->pin_mappable = true; |
| 145 | i915_gem_info_update_mappable(dev_priv, obj, true); |
| 146 | } |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 147 | } |
| 148 | |
| 149 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 150 | struct drm_gem_object *obj) |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 151 | { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 152 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 153 | dev_priv->mm.pin_count--; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 154 | dev_priv->mm.pin_memory -= obj->size; |
| 155 | if (obj_priv->pin_mappable) { |
| 156 | obj_priv->pin_mappable = false; |
| 157 | i915_gem_info_update_mappable(dev_priv, obj, false); |
| 158 | } |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 159 | } |
| 160 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 161 | int |
| 162 | i915_gem_check_is_wedged(struct drm_device *dev) |
| 163 | { |
| 164 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 165 | struct completion *x = &dev_priv->error_completion; |
| 166 | unsigned long flags; |
| 167 | int ret; |
| 168 | |
| 169 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 170 | return 0; |
| 171 | |
| 172 | ret = wait_for_completion_interruptible(x); |
| 173 | if (ret) |
| 174 | return ret; |
| 175 | |
| 176 | /* Success, we reset the GPU! */ |
| 177 | if (!atomic_read(&dev_priv->mm.wedged)) |
| 178 | return 0; |
| 179 | |
| 180 | /* GPU is hung, bump the completion count to account for |
| 181 | * the token we just consumed so that we never hit zero and |
| 182 | * end up waiting upon a subsequent completion event that |
| 183 | * will never happen. |
| 184 | */ |
| 185 | spin_lock_irqsave(&x->wait.lock, flags); |
| 186 | x->done++; |
| 187 | spin_unlock_irqrestore(&x->wait.lock, flags); |
| 188 | return -EIO; |
| 189 | } |
| 190 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 191 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
| 192 | { |
| 193 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 194 | int ret; |
| 195 | |
| 196 | ret = i915_gem_check_is_wedged(dev); |
| 197 | if (ret) |
| 198 | return ret; |
| 199 | |
| 200 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 201 | if (ret) |
| 202 | return ret; |
| 203 | |
| 204 | if (atomic_read(&dev_priv->mm.wedged)) { |
| 205 | mutex_unlock(&dev->struct_mutex); |
| 206 | return -EAGAIN; |
| 207 | } |
| 208 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 209 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 210 | return 0; |
| 211 | } |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 212 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 213 | static inline bool |
| 214 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) |
| 215 | { |
| 216 | return obj_priv->gtt_space && |
| 217 | !obj_priv->active && |
| 218 | obj_priv->pin_count == 0; |
| 219 | } |
| 220 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 221 | int i915_gem_do_init(struct drm_device *dev, |
| 222 | unsigned long start, |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 223 | unsigned long mappable_end, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 224 | unsigned long end) |
| 225 | { |
| 226 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 227 | |
| 228 | if (start >= end || |
| 229 | (start & (PAGE_SIZE - 1)) != 0 || |
| 230 | (end & (PAGE_SIZE - 1)) != 0) { |
| 231 | return -EINVAL; |
| 232 | } |
| 233 | |
| 234 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
| 235 | end - start); |
| 236 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 237 | dev_priv->mm.gtt_total = end - start; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 238 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 239 | dev_priv->mm.gtt_mappable_end = mappable_end; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 240 | |
| 241 | return 0; |
| 242 | } |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 243 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 244 | int |
| 245 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 246 | struct drm_file *file_priv) |
| 247 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 248 | struct drm_i915_gem_init *args = data; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 249 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 250 | |
| 251 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 5398463 | 2010-09-22 23:44:24 +0200 | [diff] [blame] | 252 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 253 | mutex_unlock(&dev->struct_mutex); |
| 254 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 255 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 256 | } |
| 257 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 258 | int |
| 259 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 260 | struct drm_file *file_priv) |
| 261 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 262 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 263 | struct drm_i915_gem_get_aperture *args = data; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 264 | |
| 265 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 266 | return -ENODEV; |
| 267 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 268 | mutex_lock(&dev->struct_mutex); |
| 269 | args->aper_size = dev_priv->mm.gtt_total; |
| 270 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; |
| 271 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 272 | |
| 273 | return 0; |
| 274 | } |
| 275 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 276 | |
| 277 | /** |
| 278 | * Creates a new mm object and returns a handle to it. |
| 279 | */ |
| 280 | int |
| 281 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 282 | struct drm_file *file_priv) |
| 283 | { |
| 284 | struct drm_i915_gem_create *args = data; |
| 285 | struct drm_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 286 | int ret; |
| 287 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 288 | |
| 289 | args->size = roundup(args->size, PAGE_SIZE); |
| 290 | |
| 291 | /* Allocate the new object */ |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 292 | obj = i915_gem_alloc_object(dev, args->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 293 | if (obj == NULL) |
| 294 | return -ENOMEM; |
| 295 | |
| 296 | ret = drm_gem_handle_create(file_priv, obj, &handle); |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 297 | if (ret) { |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 298 | drm_gem_object_release(obj); |
| 299 | i915_gem_info_remove_obj(dev->dev_private, obj->size); |
| 300 | kfree(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 301 | return ret; |
Chris Wilson | 1dfd975 | 2010-09-06 14:44:14 +0100 | [diff] [blame] | 302 | } |
| 303 | |
Chris Wilson | 202f2fe | 2010-10-14 13:20:40 +0100 | [diff] [blame] | 304 | /* drop reference from allocate - handle holds it now */ |
| 305 | drm_gem_object_unreference(obj); |
| 306 | trace_i915_gem_object_create(obj); |
| 307 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 308 | args->handle = handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 309 | return 0; |
| 310 | } |
| 311 | |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 312 | static bool |
| 313 | i915_gem_object_cpu_accessible(struct drm_i915_gem_object *obj) |
| 314 | { |
| 315 | struct drm_device *dev = obj->base.dev; |
| 316 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 317 | |
| 318 | return obj->gtt_space == NULL || |
| 319 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
| 320 | } |
| 321 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 322 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
| 323 | { |
| 324 | drm_i915_private_t *dev_priv = obj->dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 325 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 326 | |
| 327 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 328 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 329 | } |
| 330 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 331 | static inline void |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 332 | slow_shmem_copy(struct page *dst_page, |
| 333 | int dst_offset, |
| 334 | struct page *src_page, |
| 335 | int src_offset, |
| 336 | int length) |
| 337 | { |
| 338 | char *dst_vaddr, *src_vaddr; |
| 339 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 340 | dst_vaddr = kmap(dst_page); |
| 341 | src_vaddr = kmap(src_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 342 | |
| 343 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
| 344 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 345 | kunmap(src_page); |
| 346 | kunmap(dst_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 347 | } |
| 348 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 349 | static inline void |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 350 | slow_shmem_bit17_copy(struct page *gpu_page, |
| 351 | int gpu_offset, |
| 352 | struct page *cpu_page, |
| 353 | int cpu_offset, |
| 354 | int length, |
| 355 | int is_read) |
| 356 | { |
| 357 | char *gpu_vaddr, *cpu_vaddr; |
| 358 | |
| 359 | /* Use the unswizzled path if this page isn't affected. */ |
| 360 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
| 361 | if (is_read) |
| 362 | return slow_shmem_copy(cpu_page, cpu_offset, |
| 363 | gpu_page, gpu_offset, length); |
| 364 | else |
| 365 | return slow_shmem_copy(gpu_page, gpu_offset, |
| 366 | cpu_page, cpu_offset, length); |
| 367 | } |
| 368 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 369 | gpu_vaddr = kmap(gpu_page); |
| 370 | cpu_vaddr = kmap(cpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 371 | |
| 372 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
| 373 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
| 374 | */ |
| 375 | while (length > 0) { |
| 376 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 377 | int this_length = min(cacheline_end - gpu_offset, length); |
| 378 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 379 | |
| 380 | if (is_read) { |
| 381 | memcpy(cpu_vaddr + cpu_offset, |
| 382 | gpu_vaddr + swizzled_gpu_offset, |
| 383 | this_length); |
| 384 | } else { |
| 385 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
| 386 | cpu_vaddr + cpu_offset, |
| 387 | this_length); |
| 388 | } |
| 389 | cpu_offset += this_length; |
| 390 | gpu_offset += this_length; |
| 391 | length -= this_length; |
| 392 | } |
| 393 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 394 | kunmap(cpu_page); |
| 395 | kunmap(gpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 396 | } |
| 397 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 398 | /** |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 399 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
| 400 | * from the backing pages of the object to the user's address space. On a |
| 401 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
| 402 | */ |
| 403 | static int |
| 404 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 405 | struct drm_i915_gem_pread *args, |
| 406 | struct drm_file *file_priv) |
| 407 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 408 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 409 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 410 | ssize_t remain; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 411 | loff_t offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 412 | char __user *user_data; |
| 413 | int page_offset, page_length; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 414 | |
| 415 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 416 | remain = args->size; |
| 417 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 418 | obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 419 | offset = args->offset; |
| 420 | |
| 421 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 422 | struct page *page; |
| 423 | char *vaddr; |
| 424 | int ret; |
| 425 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 426 | /* Operation in this page |
| 427 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 428 | * page_offset = offset within page |
| 429 | * page_length = bytes to copy for this page |
| 430 | */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 431 | page_offset = offset & (PAGE_SIZE-1); |
| 432 | page_length = remain; |
| 433 | if ((page_offset + remain) > PAGE_SIZE) |
| 434 | page_length = PAGE_SIZE - page_offset; |
| 435 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 436 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 437 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 438 | if (IS_ERR(page)) |
| 439 | return PTR_ERR(page); |
| 440 | |
| 441 | vaddr = kmap_atomic(page); |
| 442 | ret = __copy_to_user_inatomic(user_data, |
| 443 | vaddr + page_offset, |
| 444 | page_length); |
| 445 | kunmap_atomic(vaddr); |
| 446 | |
| 447 | mark_page_accessed(page); |
| 448 | page_cache_release(page); |
| 449 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 450 | return -EFAULT; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 451 | |
| 452 | remain -= page_length; |
| 453 | user_data += page_length; |
| 454 | offset += page_length; |
| 455 | } |
| 456 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 457 | return 0; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 458 | } |
| 459 | |
| 460 | /** |
| 461 | * This is the fallback shmem pread path, which allocates temporary storage |
| 462 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
| 463 | * can copy out of the object's backing pages while holding the struct mutex |
| 464 | * and not take page faults. |
| 465 | */ |
| 466 | static int |
| 467 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 468 | struct drm_i915_gem_pread *args, |
| 469 | struct drm_file *file_priv) |
| 470 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 471 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 472 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 473 | struct mm_struct *mm = current->mm; |
| 474 | struct page **user_pages; |
| 475 | ssize_t remain; |
| 476 | loff_t offset, pinned_pages, i; |
| 477 | loff_t first_data_page, last_data_page, num_pages; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 478 | int shmem_page_offset; |
| 479 | int data_page_index, data_page_offset; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 480 | int page_length; |
| 481 | int ret; |
| 482 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 483 | int do_bit17_swizzling; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 484 | |
| 485 | remain = args->size; |
| 486 | |
| 487 | /* Pin the user pages containing the data. We can't fault while |
| 488 | * holding the struct mutex, yet we want to hold it while |
| 489 | * dereferencing the user data. |
| 490 | */ |
| 491 | first_data_page = data_ptr / PAGE_SIZE; |
| 492 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 493 | num_pages = last_data_page - first_data_page + 1; |
| 494 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 495 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 496 | if (user_pages == NULL) |
| 497 | return -ENOMEM; |
| 498 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 499 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 500 | down_read(&mm->mmap_sem); |
| 501 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
Eric Anholt | e5e9ecd | 2009-04-07 16:01:22 -0700 | [diff] [blame] | 502 | num_pages, 1, 0, user_pages, NULL); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 503 | up_read(&mm->mmap_sem); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 504 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 505 | if (pinned_pages < num_pages) { |
| 506 | ret = -EFAULT; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 507 | goto out; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 508 | } |
| 509 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 510 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 511 | args->offset, |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 512 | args->size); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 513 | if (ret) |
| 514 | goto out; |
| 515 | |
| 516 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 517 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 518 | obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 519 | offset = args->offset; |
| 520 | |
| 521 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 522 | struct page *page; |
| 523 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 524 | /* Operation in this page |
| 525 | * |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 526 | * shmem_page_offset = offset within page in shmem file |
| 527 | * data_page_index = page number in get_user_pages return |
| 528 | * data_page_offset = offset with data_page_index page. |
| 529 | * page_length = bytes to copy for this page |
| 530 | */ |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 531 | shmem_page_offset = offset & ~PAGE_MASK; |
| 532 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 533 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 534 | |
| 535 | page_length = remain; |
| 536 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 537 | page_length = PAGE_SIZE - shmem_page_offset; |
| 538 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 539 | page_length = PAGE_SIZE - data_page_offset; |
| 540 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 541 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 542 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 543 | if (IS_ERR(page)) |
| 544 | return PTR_ERR(page); |
| 545 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 546 | if (do_bit17_swizzling) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 547 | slow_shmem_bit17_copy(page, |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 548 | shmem_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 549 | user_pages[data_page_index], |
| 550 | data_page_offset, |
| 551 | page_length, |
| 552 | 1); |
| 553 | } else { |
| 554 | slow_shmem_copy(user_pages[data_page_index], |
| 555 | data_page_offset, |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 556 | page, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 557 | shmem_page_offset, |
| 558 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 559 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 560 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 561 | mark_page_accessed(page); |
| 562 | page_cache_release(page); |
| 563 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 564 | remain -= page_length; |
| 565 | data_ptr += page_length; |
| 566 | offset += page_length; |
| 567 | } |
| 568 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 569 | out: |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 570 | for (i = 0; i < pinned_pages; i++) { |
| 571 | SetPageDirty(user_pages[i]); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 572 | mark_page_accessed(user_pages[i]); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 573 | page_cache_release(user_pages[i]); |
| 574 | } |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 575 | drm_free_large(user_pages); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 576 | |
| 577 | return ret; |
| 578 | } |
| 579 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 580 | /** |
| 581 | * Reads data from the object referenced by handle. |
| 582 | * |
| 583 | * On error, the contents of *data are undefined. |
| 584 | */ |
| 585 | int |
| 586 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 587 | struct drm_file *file_priv) |
| 588 | { |
| 589 | struct drm_i915_gem_pread *args = data; |
| 590 | struct drm_gem_object *obj; |
| 591 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 592 | int ret = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 593 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 594 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 595 | if (ret) |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 596 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 597 | |
| 598 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 599 | if (obj == NULL) { |
| 600 | ret = -ENOENT; |
| 601 | goto unlock; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 602 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 603 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 604 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 605 | /* Bounds check source. */ |
| 606 | if (args->offset > obj->size || args->size > obj->size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 607 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 608 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 609 | } |
| 610 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 611 | if (args->size == 0) |
| 612 | goto out; |
| 613 | |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 614 | if (!access_ok(VERIFY_WRITE, |
| 615 | (char __user *)(uintptr_t)args->data_ptr, |
| 616 | args->size)) { |
| 617 | ret = -EFAULT; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 618 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 619 | } |
| 620 | |
Chris Wilson | b5e4feb | 2010-10-14 13:47:43 +0100 | [diff] [blame] | 621 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
| 622 | args->size); |
| 623 | if (ret) { |
| 624 | ret = -EFAULT; |
| 625 | goto out; |
| 626 | } |
| 627 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 628 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
| 629 | args->offset, |
| 630 | args->size); |
| 631 | if (ret) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 632 | goto out; |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 633 | |
| 634 | ret = -EFAULT; |
| 635 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 636 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 637 | if (ret == -EFAULT) |
| 638 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 639 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 640 | out: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 641 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 642 | unlock: |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 643 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 644 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 645 | } |
| 646 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 647 | /* This is the fast write path which cannot handle |
| 648 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 649 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 650 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 651 | static inline int |
| 652 | fast_user_write(struct io_mapping *mapping, |
| 653 | loff_t page_base, int page_offset, |
| 654 | char __user *user_data, |
| 655 | int length) |
| 656 | { |
| 657 | char *vaddr_atomic; |
| 658 | unsigned long unwritten; |
| 659 | |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 660 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 661 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 662 | user_data, length); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 663 | io_mapping_unmap_atomic(vaddr_atomic); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 664 | return unwritten; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 665 | } |
| 666 | |
| 667 | /* Here's the write path which can sleep for |
| 668 | * page faults |
| 669 | */ |
| 670 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 671 | static inline void |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 672 | slow_kernel_write(struct io_mapping *mapping, |
| 673 | loff_t gtt_base, int gtt_offset, |
| 674 | struct page *user_page, int user_offset, |
| 675 | int length) |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 676 | { |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 677 | char __iomem *dst_vaddr; |
| 678 | char *src_vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 679 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 680 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
| 681 | src_vaddr = kmap(user_page); |
| 682 | |
| 683 | memcpy_toio(dst_vaddr + gtt_offset, |
| 684 | src_vaddr + user_offset, |
| 685 | length); |
| 686 | |
| 687 | kunmap(user_page); |
| 688 | io_mapping_unmap(dst_vaddr); |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 689 | } |
| 690 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 691 | /** |
| 692 | * This is the fast pwrite path, where we copy the data directly from the |
| 693 | * user into the GTT, uncached. |
| 694 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 695 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 696 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 697 | struct drm_i915_gem_pwrite *args, |
| 698 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 699 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 700 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 701 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 702 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 703 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 704 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 705 | int page_offset, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 706 | |
| 707 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 708 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 709 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 710 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 711 | offset = obj_priv->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 712 | |
| 713 | while (remain > 0) { |
| 714 | /* Operation in this page |
| 715 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 716 | * page_base = page offset within aperture |
| 717 | * page_offset = offset within page |
| 718 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 719 | */ |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 720 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 721 | page_offset = offset & (PAGE_SIZE-1); |
| 722 | page_length = remain; |
| 723 | if ((page_offset + remain) > PAGE_SIZE) |
| 724 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 725 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 726 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 727 | * source page isn't available. Return the error and we'll |
| 728 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 729 | */ |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 730 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
| 731 | page_offset, user_data, page_length)) |
| 732 | |
| 733 | return -EFAULT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 734 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 735 | remain -= page_length; |
| 736 | user_data += page_length; |
| 737 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 738 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 739 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 740 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 741 | } |
| 742 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 743 | /** |
| 744 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin |
| 745 | * the memory and maps it using kmap_atomic for copying. |
| 746 | * |
| 747 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU |
| 748 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). |
| 749 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 750 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 751 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 752 | struct drm_i915_gem_pwrite *args, |
| 753 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 754 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 755 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 756 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 757 | ssize_t remain; |
| 758 | loff_t gtt_page_base, offset; |
| 759 | loff_t first_data_page, last_data_page, num_pages; |
| 760 | loff_t pinned_pages, i; |
| 761 | struct page **user_pages; |
| 762 | struct mm_struct *mm = current->mm; |
| 763 | int gtt_page_offset, data_page_offset, data_page_index, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 764 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 765 | uint64_t data_ptr = args->data_ptr; |
| 766 | |
| 767 | remain = args->size; |
| 768 | |
| 769 | /* Pin the user pages containing the data. We can't fault while |
| 770 | * holding the struct mutex, and all of the pwrite implementations |
| 771 | * want to hold it while dereferencing the user data. |
| 772 | */ |
| 773 | first_data_page = data_ptr / PAGE_SIZE; |
| 774 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 775 | num_pages = last_data_page - first_data_page + 1; |
| 776 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 777 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 778 | if (user_pages == NULL) |
| 779 | return -ENOMEM; |
| 780 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 781 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 782 | down_read(&mm->mmap_sem); |
| 783 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 784 | num_pages, 0, 0, user_pages, NULL); |
| 785 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 786 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 787 | if (pinned_pages < num_pages) { |
| 788 | ret = -EFAULT; |
| 789 | goto out_unpin_pages; |
| 790 | } |
| 791 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 792 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 793 | if (ret) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 794 | goto out_unpin_pages; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 795 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 796 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 797 | offset = obj_priv->gtt_offset + args->offset; |
| 798 | |
| 799 | while (remain > 0) { |
| 800 | /* Operation in this page |
| 801 | * |
| 802 | * gtt_page_base = page offset within aperture |
| 803 | * gtt_page_offset = offset within page in aperture |
| 804 | * data_page_index = page number in get_user_pages return |
| 805 | * data_page_offset = offset with data_page_index page. |
| 806 | * page_length = bytes to copy for this page |
| 807 | */ |
| 808 | gtt_page_base = offset & PAGE_MASK; |
| 809 | gtt_page_offset = offset & ~PAGE_MASK; |
| 810 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 811 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 812 | |
| 813 | page_length = remain; |
| 814 | if ((gtt_page_offset + page_length) > PAGE_SIZE) |
| 815 | page_length = PAGE_SIZE - gtt_page_offset; |
| 816 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 817 | page_length = PAGE_SIZE - data_page_offset; |
| 818 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 819 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
| 820 | gtt_page_base, gtt_page_offset, |
| 821 | user_pages[data_page_index], |
| 822 | data_page_offset, |
| 823 | page_length); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 824 | |
| 825 | remain -= page_length; |
| 826 | offset += page_length; |
| 827 | data_ptr += page_length; |
| 828 | } |
| 829 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 830 | out_unpin_pages: |
| 831 | for (i = 0; i < pinned_pages; i++) |
| 832 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 833 | drm_free_large(user_pages); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 834 | |
| 835 | return ret; |
| 836 | } |
| 837 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 838 | /** |
| 839 | * This is the fast shmem pwrite path, which attempts to directly |
| 840 | * copy_from_user into the kmapped pages backing the object. |
| 841 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 842 | static int |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 843 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 844 | struct drm_i915_gem_pwrite *args, |
| 845 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 846 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 847 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 848 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 849 | ssize_t remain; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 850 | loff_t offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 851 | char __user *user_data; |
| 852 | int page_offset, page_length; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 853 | |
| 854 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 855 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 856 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 857 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 858 | offset = args->offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 859 | obj_priv->dirty = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 860 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 861 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 862 | struct page *page; |
| 863 | char *vaddr; |
| 864 | int ret; |
| 865 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 866 | /* Operation in this page |
| 867 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 868 | * page_offset = offset within page |
| 869 | * page_length = bytes to copy for this page |
| 870 | */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 871 | page_offset = offset & (PAGE_SIZE-1); |
| 872 | page_length = remain; |
| 873 | if ((page_offset + remain) > PAGE_SIZE) |
| 874 | page_length = PAGE_SIZE - page_offset; |
| 875 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 876 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 877 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 878 | if (IS_ERR(page)) |
| 879 | return PTR_ERR(page); |
| 880 | |
| 881 | vaddr = kmap_atomic(page, KM_USER0); |
| 882 | ret = __copy_from_user_inatomic(vaddr + page_offset, |
| 883 | user_data, |
| 884 | page_length); |
| 885 | kunmap_atomic(vaddr, KM_USER0); |
| 886 | |
| 887 | set_page_dirty(page); |
| 888 | mark_page_accessed(page); |
| 889 | page_cache_release(page); |
| 890 | |
| 891 | /* If we get a fault while copying data, then (presumably) our |
| 892 | * source page isn't available. Return the error and we'll |
| 893 | * retry in the slow path. |
| 894 | */ |
| 895 | if (ret) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 896 | return -EFAULT; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 897 | |
| 898 | remain -= page_length; |
| 899 | user_data += page_length; |
| 900 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 901 | } |
| 902 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 903 | return 0; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 904 | } |
| 905 | |
| 906 | /** |
| 907 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin |
| 908 | * the memory and maps it using kmap_atomic for copying. |
| 909 | * |
| 910 | * This avoids taking mmap_sem for faulting on the user's address while the |
| 911 | * struct_mutex is held. |
| 912 | */ |
| 913 | static int |
| 914 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 915 | struct drm_i915_gem_pwrite *args, |
| 916 | struct drm_file *file_priv) |
| 917 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 918 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 919 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 920 | struct mm_struct *mm = current->mm; |
| 921 | struct page **user_pages; |
| 922 | ssize_t remain; |
| 923 | loff_t offset, pinned_pages, i; |
| 924 | loff_t first_data_page, last_data_page, num_pages; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 925 | int shmem_page_offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 926 | int data_page_index, data_page_offset; |
| 927 | int page_length; |
| 928 | int ret; |
| 929 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 930 | int do_bit17_swizzling; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 931 | |
| 932 | remain = args->size; |
| 933 | |
| 934 | /* Pin the user pages containing the data. We can't fault while |
| 935 | * holding the struct mutex, and all of the pwrite implementations |
| 936 | * want to hold it while dereferencing the user data. |
| 937 | */ |
| 938 | first_data_page = data_ptr / PAGE_SIZE; |
| 939 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 940 | num_pages = last_data_page - first_data_page + 1; |
| 941 | |
Chris Wilson | 4f27b75 | 2010-10-14 15:26:45 +0100 | [diff] [blame] | 942 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 943 | if (user_pages == NULL) |
| 944 | return -ENOMEM; |
| 945 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 946 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 947 | down_read(&mm->mmap_sem); |
| 948 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 949 | num_pages, 0, 0, user_pages, NULL); |
| 950 | up_read(&mm->mmap_sem); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 951 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 952 | if (pinned_pages < num_pages) { |
| 953 | ret = -EFAULT; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 954 | goto out; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 955 | } |
| 956 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 957 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 958 | if (ret) |
| 959 | goto out; |
| 960 | |
| 961 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 962 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 963 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 964 | offset = args->offset; |
| 965 | obj_priv->dirty = 1; |
| 966 | |
| 967 | while (remain > 0) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 968 | struct page *page; |
| 969 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 970 | /* Operation in this page |
| 971 | * |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 972 | * shmem_page_offset = offset within page in shmem file |
| 973 | * data_page_index = page number in get_user_pages return |
| 974 | * data_page_offset = offset with data_page_index page. |
| 975 | * page_length = bytes to copy for this page |
| 976 | */ |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 977 | shmem_page_offset = offset & ~PAGE_MASK; |
| 978 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 979 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 980 | |
| 981 | page_length = remain; |
| 982 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 983 | page_length = PAGE_SIZE - shmem_page_offset; |
| 984 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 985 | page_length = PAGE_SIZE - data_page_offset; |
| 986 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 987 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
| 988 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 989 | if (IS_ERR(page)) { |
| 990 | ret = PTR_ERR(page); |
| 991 | goto out; |
| 992 | } |
| 993 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 994 | if (do_bit17_swizzling) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 995 | slow_shmem_bit17_copy(page, |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 996 | shmem_page_offset, |
| 997 | user_pages[data_page_index], |
| 998 | data_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 999 | page_length, |
| 1000 | 0); |
| 1001 | } else { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1002 | slow_shmem_copy(page, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 1003 | shmem_page_offset, |
| 1004 | user_pages[data_page_index], |
| 1005 | data_page_offset, |
| 1006 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1007 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1008 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1009 | set_page_dirty(page); |
| 1010 | mark_page_accessed(page); |
| 1011 | page_cache_release(page); |
| 1012 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1013 | remain -= page_length; |
| 1014 | data_ptr += page_length; |
| 1015 | offset += page_length; |
| 1016 | } |
| 1017 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1018 | out: |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1019 | for (i = 0; i < pinned_pages; i++) |
| 1020 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 1021 | drm_free_large(user_pages); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1022 | |
| 1023 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1024 | } |
| 1025 | |
| 1026 | /** |
| 1027 | * Writes data to the object referenced by handle. |
| 1028 | * |
| 1029 | * On error, the contents of the buffer that were to be modified are undefined. |
| 1030 | */ |
| 1031 | int |
| 1032 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1033 | struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1034 | { |
| 1035 | struct drm_i915_gem_pwrite *args = data; |
| 1036 | struct drm_gem_object *obj; |
| 1037 | struct drm_i915_gem_object *obj_priv; |
| 1038 | int ret = 0; |
| 1039 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1040 | ret = i915_mutex_lock_interruptible(dev); |
| 1041 | if (ret) |
| 1042 | return ret; |
| 1043 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1044 | obj = drm_gem_object_lookup(dev, file, args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1045 | if (obj == NULL) { |
| 1046 | ret = -ENOENT; |
| 1047 | goto unlock; |
| 1048 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1049 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1050 | |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1051 | |
Chris Wilson | 7dcd249 | 2010-09-26 20:21:44 +0100 | [diff] [blame] | 1052 | /* Bounds check destination. */ |
| 1053 | if (args->offset > obj->size || args->size > obj->size - args->offset) { |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1054 | ret = -EINVAL; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1055 | goto out; |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1056 | } |
| 1057 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1058 | if (args->size == 0) |
| 1059 | goto out; |
| 1060 | |
Chris Wilson | ce9d419 | 2010-09-26 20:50:05 +0100 | [diff] [blame] | 1061 | if (!access_ok(VERIFY_READ, |
| 1062 | (char __user *)(uintptr_t)args->data_ptr, |
| 1063 | args->size)) { |
| 1064 | ret = -EFAULT; |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1065 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1066 | } |
| 1067 | |
Chris Wilson | b5e4feb | 2010-10-14 13:47:43 +0100 | [diff] [blame] | 1068 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
| 1069 | args->size); |
| 1070 | if (ret) { |
| 1071 | ret = -EFAULT; |
| 1072 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1073 | } |
| 1074 | |
| 1075 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 1076 | * it would end up going through the fenced access, and we'll get |
| 1077 | * different detiling behavior between reading and writing. |
| 1078 | * pread/pwrite currently are reading and writing from the CPU |
| 1079 | * perspective, requiring manual detiling by the client. |
| 1080 | */ |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1081 | if (obj_priv->phys_obj) |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1082 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 1083 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1084 | obj_priv->gtt_space && |
Chris Wilson | 9b8c4a0 | 2010-05-27 14:21:01 +0100 | [diff] [blame] | 1085 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 1086 | ret = i915_gem_object_pin(obj, 0, true); |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1087 | if (ret) |
| 1088 | goto out; |
| 1089 | |
| 1090 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 1091 | if (ret) |
| 1092 | goto out_unpin; |
| 1093 | |
| 1094 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
| 1095 | if (ret == -EFAULT) |
| 1096 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); |
| 1097 | |
| 1098 | out_unpin: |
| 1099 | i915_gem_object_unpin(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1100 | } else { |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1101 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 1102 | if (ret) |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1103 | goto out; |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1104 | |
| 1105 | ret = -EFAULT; |
| 1106 | if (!i915_gem_object_needs_bit17_swizzle(obj)) |
| 1107 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); |
| 1108 | if (ret == -EFAULT) |
| 1109 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 1110 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1111 | |
Chris Wilson | 35b62a8 | 2010-09-26 20:23:38 +0100 | [diff] [blame] | 1112 | out: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1113 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1114 | unlock: |
Chris Wilson | fbd5a26 | 2010-10-14 15:03:58 +0100 | [diff] [blame] | 1115 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1116 | return ret; |
| 1117 | } |
| 1118 | |
| 1119 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1120 | * Called when user space prepares to use an object with the CPU, either |
| 1121 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1122 | */ |
| 1123 | int |
| 1124 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1125 | struct drm_file *file_priv) |
| 1126 | { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1127 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1128 | struct drm_i915_gem_set_domain *args = data; |
| 1129 | struct drm_gem_object *obj; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1130 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1131 | uint32_t read_domains = args->read_domains; |
| 1132 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1133 | int ret; |
| 1134 | |
| 1135 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1136 | return -ENODEV; |
| 1137 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1138 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1139 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1140 | return -EINVAL; |
| 1141 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1142 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1143 | return -EINVAL; |
| 1144 | |
| 1145 | /* Having something in the write domain implies it's in the read |
| 1146 | * domain, and only that read domain. Enforce that in the request. |
| 1147 | */ |
| 1148 | if (write_domain != 0 && read_domains != write_domain) |
| 1149 | return -EINVAL; |
| 1150 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1151 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1152 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1153 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1154 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1155 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1156 | if (obj == NULL) { |
| 1157 | ret = -ENOENT; |
| 1158 | goto unlock; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1159 | } |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1160 | obj_priv = to_intel_bo(obj); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1161 | |
| 1162 | intel_mark_busy(dev, obj); |
| 1163 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1164 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1165 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1166 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1167 | /* Update the LRU on the fence for the CPU access that's |
| 1168 | * about to occur. |
| 1169 | */ |
| 1170 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1171 | struct drm_i915_fence_reg *reg = |
| 1172 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 1173 | list_move_tail(®->lru_list, |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1174 | &dev_priv->mm.fence_list); |
| 1175 | } |
| 1176 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1177 | /* Silently promote "you're not bound, there was nothing to do" |
| 1178 | * to success, since the client was just asking us to |
| 1179 | * make sure everything was done. |
| 1180 | */ |
| 1181 | if (ret == -EINVAL) |
| 1182 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1183 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1184 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1185 | } |
| 1186 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1187 | /* Maintain LRU order of "inactive" objects */ |
| 1188 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1189 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1190 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1191 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1192 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1193 | mutex_unlock(&dev->struct_mutex); |
| 1194 | return ret; |
| 1195 | } |
| 1196 | |
| 1197 | /** |
| 1198 | * Called when user space has done writes to this buffer |
| 1199 | */ |
| 1200 | int |
| 1201 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1202 | struct drm_file *file_priv) |
| 1203 | { |
| 1204 | struct drm_i915_gem_sw_finish *args = data; |
| 1205 | struct drm_gem_object *obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1206 | int ret = 0; |
| 1207 | |
| 1208 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1209 | return -ENODEV; |
| 1210 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1211 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1212 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1213 | return ret; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1214 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1215 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1216 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1217 | ret = -ENOENT; |
| 1218 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1219 | } |
| 1220 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1221 | /* Pinned buffers may be scanout, so flush the cache */ |
Chris Wilson | 3d2a812 | 2010-09-29 11:39:53 +0100 | [diff] [blame] | 1222 | if (to_intel_bo(obj)->pin_count) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1223 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1224 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1225 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1226 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1227 | mutex_unlock(&dev->struct_mutex); |
| 1228 | return ret; |
| 1229 | } |
| 1230 | |
| 1231 | /** |
| 1232 | * Maps the contents of an object, returning the address it is mapped |
| 1233 | * into. |
| 1234 | * |
| 1235 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1236 | * imply a ref on the object itself. |
| 1237 | */ |
| 1238 | int |
| 1239 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1240 | struct drm_file *file_priv) |
| 1241 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1242 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1243 | struct drm_i915_gem_mmap *args = data; |
| 1244 | struct drm_gem_object *obj; |
| 1245 | loff_t offset; |
| 1246 | unsigned long addr; |
| 1247 | |
| 1248 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1249 | return -ENODEV; |
| 1250 | |
| 1251 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1252 | if (obj == NULL) |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 1253 | return -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1254 | |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1255 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
| 1256 | drm_gem_object_unreference_unlocked(obj); |
| 1257 | return -E2BIG; |
| 1258 | } |
| 1259 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1260 | offset = args->offset; |
| 1261 | |
| 1262 | down_write(¤t->mm->mmap_sem); |
| 1263 | addr = do_mmap(obj->filp, 0, args->size, |
| 1264 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1265 | args->offset); |
| 1266 | up_write(¤t->mm->mmap_sem); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1267 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1268 | if (IS_ERR((void *)addr)) |
| 1269 | return addr; |
| 1270 | |
| 1271 | args->addr_ptr = (uint64_t) addr; |
| 1272 | |
| 1273 | return 0; |
| 1274 | } |
| 1275 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1276 | /** |
| 1277 | * i915_gem_fault - fault a page into the GTT |
| 1278 | * vma: VMA in question |
| 1279 | * vmf: fault info |
| 1280 | * |
| 1281 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1282 | * from userspace. The fault handler takes care of binding the object to |
| 1283 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1284 | * only if needed based on whether the old reg is still valid or the object |
| 1285 | * is tiled) and inserting a new PTE into the faulting process. |
| 1286 | * |
| 1287 | * Note that the faulting process may involve evicting existing objects |
| 1288 | * from the GTT and/or fence registers to make room. So performance may |
| 1289 | * suffer if the GTT working set is large or there are few fence registers |
| 1290 | * left. |
| 1291 | */ |
| 1292 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1293 | { |
| 1294 | struct drm_gem_object *obj = vma->vm_private_data; |
| 1295 | struct drm_device *dev = obj->dev; |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1296 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1297 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1298 | pgoff_t page_offset; |
| 1299 | unsigned long pfn; |
| 1300 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1301 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1302 | |
| 1303 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1304 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1305 | PAGE_SHIFT; |
| 1306 | |
| 1307 | /* Now bind it into the GTT if needed */ |
| 1308 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1309 | BUG_ON(obj_priv->pin_count && !obj_priv->pin_mappable); |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 1310 | if (!i915_gem_object_cpu_accessible(obj_priv)) |
| 1311 | i915_gem_object_unbind(obj); |
| 1312 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1313 | if (!obj_priv->gtt_space) { |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 1314 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1315 | if (ret) |
| 1316 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1317 | } |
| 1318 | |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame^] | 1319 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
| 1320 | if (ret) |
| 1321 | goto unlock; |
| 1322 | |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1323 | if (!obj_priv->fault_mappable) { |
| 1324 | obj_priv->fault_mappable = true; |
| 1325 | i915_gem_info_update_mappable(dev_priv, obj, true); |
| 1326 | } |
| 1327 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1328 | /* Need a new fence register? */ |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1329 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 1330 | ret = i915_gem_object_get_fence_reg(obj, true); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1331 | if (ret) |
| 1332 | goto unlock; |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1333 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1334 | |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1335 | if (i915_gem_object_is_inactive(obj_priv)) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1336 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
Chris Wilson | 7d1c480 | 2010-08-07 21:45:03 +0100 | [diff] [blame] | 1337 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1338 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
| 1339 | page_offset; |
| 1340 | |
| 1341 | /* Finally, remap it using the new GTT offset */ |
| 1342 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1343 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1344 | mutex_unlock(&dev->struct_mutex); |
| 1345 | |
| 1346 | switch (ret) { |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1347 | case 0: |
| 1348 | case -ERESTARTSYS: |
| 1349 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1350 | case -ENOMEM: |
| 1351 | case -EAGAIN: |
| 1352 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1353 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1354 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1355 | } |
| 1356 | } |
| 1357 | |
| 1358 | /** |
| 1359 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 1360 | * @obj: obj in question |
| 1361 | * |
| 1362 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 1363 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 1364 | * up the object based on the offset and sets up the various memory mapping |
| 1365 | * structures. |
| 1366 | * |
| 1367 | * This routine allocates and attaches a fake offset for @obj. |
| 1368 | */ |
| 1369 | static int |
| 1370 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) |
| 1371 | { |
| 1372 | struct drm_device *dev = obj->dev; |
| 1373 | struct drm_gem_mm *mm = dev->mm_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1374 | struct drm_map_list *list; |
Benjamin Herrenschmidt | f77d390 | 2009-02-02 16:55:46 +1100 | [diff] [blame] | 1375 | struct drm_local_map *map; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1376 | int ret = 0; |
| 1377 | |
| 1378 | /* Set the object up for mmap'ing */ |
| 1379 | list = &obj->map_list; |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1380 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1381 | if (!list->map) |
| 1382 | return -ENOMEM; |
| 1383 | |
| 1384 | map = list->map; |
| 1385 | map->type = _DRM_GEM; |
| 1386 | map->size = obj->size; |
| 1387 | map->handle = obj; |
| 1388 | |
| 1389 | /* Get a DRM GEM mmap offset allocated... */ |
| 1390 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
| 1391 | obj->size / PAGE_SIZE, 0, 0); |
| 1392 | if (!list->file_offset_node) { |
| 1393 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1394 | ret = -ENOSPC; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1395 | goto out_free_list; |
| 1396 | } |
| 1397 | |
| 1398 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
| 1399 | obj->size / PAGE_SIZE, 0); |
| 1400 | if (!list->file_offset_node) { |
| 1401 | ret = -ENOMEM; |
| 1402 | goto out_free_list; |
| 1403 | } |
| 1404 | |
| 1405 | list->hash.key = list->file_offset_node->start; |
Chris Wilson | 9e0ae534 | 2010-09-21 15:05:24 +0100 | [diff] [blame] | 1406 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
| 1407 | if (ret) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1408 | DRM_ERROR("failed to add to map hash\n"); |
| 1409 | goto out_free_mm; |
| 1410 | } |
| 1411 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1412 | return 0; |
| 1413 | |
| 1414 | out_free_mm: |
| 1415 | drm_mm_put_block(list->file_offset_node); |
| 1416 | out_free_list: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1417 | kfree(list->map); |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1418 | list->map = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1419 | |
| 1420 | return ret; |
| 1421 | } |
| 1422 | |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1423 | /** |
| 1424 | * i915_gem_release_mmap - remove physical page mappings |
| 1425 | * @obj: obj in question |
| 1426 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1427 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1428 | * relinquish ownership of the pages back to the system. |
| 1429 | * |
| 1430 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1431 | * object through the GTT and then lose the fence register due to |
| 1432 | * resource pressure. Similarly if the object has been moved out of the |
| 1433 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1434 | * mapping will then trigger a page fault on the next user access, allowing |
| 1435 | * fixup by i915_gem_fault(). |
| 1436 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1437 | void |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1438 | i915_gem_release_mmap(struct drm_gem_object *obj) |
| 1439 | { |
| 1440 | struct drm_device *dev = obj->dev; |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1441 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1442 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1443 | |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1444 | if (unlikely(obj->map_list.map && dev->dev_mapping)) |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1445 | unmap_mapping_range(dev->dev_mapping, |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1446 | (loff_t)obj->map_list.hash.key<<PAGE_SHIFT, |
| 1447 | obj->size, 1); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 1448 | |
| 1449 | if (obj_priv->fault_mappable) { |
| 1450 | obj_priv->fault_mappable = false; |
| 1451 | i915_gem_info_update_mappable(dev_priv, obj, false); |
| 1452 | } |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1453 | } |
| 1454 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1455 | static void |
| 1456 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) |
| 1457 | { |
| 1458 | struct drm_device *dev = obj->dev; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1459 | struct drm_gem_mm *mm = dev->mm_private; |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1460 | struct drm_map_list *list = &obj->map_list; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1461 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1462 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1463 | drm_mm_put_block(list->file_offset_node); |
| 1464 | kfree(list->map); |
| 1465 | list->map = NULL; |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1466 | } |
| 1467 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1468 | /** |
| 1469 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1470 | * @obj: object to check |
| 1471 | * |
| 1472 | * Return the required GTT alignment for an object, taking into account |
| 1473 | * potential fence register mapping if needed. |
| 1474 | */ |
| 1475 | static uint32_t |
| 1476 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) |
| 1477 | { |
| 1478 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1479 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1480 | int start, i; |
| 1481 | |
| 1482 | /* |
| 1483 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1484 | * if a fence register is needed for the object. |
| 1485 | */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1486 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1487 | return 4096; |
| 1488 | |
| 1489 | /* |
| 1490 | * Previous chips need to be aligned to the size of the smallest |
| 1491 | * fence register that can contain the object. |
| 1492 | */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1493 | if (INTEL_INFO(dev)->gen == 3) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1494 | start = 1024*1024; |
| 1495 | else |
| 1496 | start = 512*1024; |
| 1497 | |
| 1498 | for (i = start; i < obj->size; i <<= 1) |
| 1499 | ; |
| 1500 | |
| 1501 | return i; |
| 1502 | } |
| 1503 | |
| 1504 | /** |
| 1505 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1506 | * @dev: DRM device |
| 1507 | * @data: GTT mapping ioctl data |
| 1508 | * @file_priv: GEM object info |
| 1509 | * |
| 1510 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1511 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1512 | * up so we can get faults in the handler above. |
| 1513 | * |
| 1514 | * The fault handler will take care of binding the object into the GTT |
| 1515 | * (since it may have been evicted to make room for something), allocating |
| 1516 | * a fence register, and mapping the appropriate aperture address into |
| 1517 | * userspace. |
| 1518 | */ |
| 1519 | int |
| 1520 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1521 | struct drm_file *file_priv) |
| 1522 | { |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1523 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1524 | struct drm_i915_gem_mmap_gtt *args = data; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1525 | struct drm_gem_object *obj; |
| 1526 | struct drm_i915_gem_object *obj_priv; |
| 1527 | int ret; |
| 1528 | |
| 1529 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1530 | return -ENODEV; |
| 1531 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1532 | ret = i915_mutex_lock_interruptible(dev); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1533 | if (ret) |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 1534 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1535 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1536 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1537 | if (obj == NULL) { |
| 1538 | ret = -ENOENT; |
| 1539 | goto unlock; |
| 1540 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1541 | obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1542 | |
Chris Wilson | da761a6 | 2010-10-27 17:37:08 +0100 | [diff] [blame] | 1543 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
| 1544 | ret = -E2BIG; |
| 1545 | goto unlock; |
| 1546 | } |
| 1547 | |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1548 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 1549 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1550 | ret = -EINVAL; |
| 1551 | goto out; |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1552 | } |
| 1553 | |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1554 | if (!obj->map_list.map) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1555 | ret = i915_gem_create_mmap_offset(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1556 | if (ret) |
| 1557 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1558 | } |
| 1559 | |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 1560 | args->offset = (u64)obj->map_list.hash.key << PAGE_SHIFT; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1561 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1562 | out: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1563 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1564 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1565 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 1566 | return ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1567 | } |
| 1568 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1569 | static int |
| 1570 | i915_gem_object_get_pages_gtt(struct drm_gem_object *obj, |
| 1571 | gfp_t gfpmask) |
| 1572 | { |
| 1573 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
| 1574 | int page_count, i; |
| 1575 | struct address_space *mapping; |
| 1576 | struct inode *inode; |
| 1577 | struct page *page; |
| 1578 | |
| 1579 | /* Get the list of pages out of our struct file. They'll be pinned |
| 1580 | * at this point until we release them. |
| 1581 | */ |
| 1582 | page_count = obj->size / PAGE_SIZE; |
| 1583 | BUG_ON(obj_priv->pages != NULL); |
| 1584 | obj_priv->pages = drm_malloc_ab(page_count, sizeof(struct page *)); |
| 1585 | if (obj_priv->pages == NULL) |
| 1586 | return -ENOMEM; |
| 1587 | |
| 1588 | inode = obj->filp->f_path.dentry->d_inode; |
| 1589 | mapping = inode->i_mapping; |
| 1590 | for (i = 0; i < page_count; i++) { |
| 1591 | page = read_cache_page_gfp(mapping, i, |
| 1592 | GFP_HIGHUSER | |
| 1593 | __GFP_COLD | |
| 1594 | __GFP_RECLAIMABLE | |
| 1595 | gfpmask); |
| 1596 | if (IS_ERR(page)) |
| 1597 | goto err_pages; |
| 1598 | |
| 1599 | obj_priv->pages[i] = page; |
| 1600 | } |
| 1601 | |
| 1602 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1603 | i915_gem_object_do_bit_17_swizzle(obj); |
| 1604 | |
| 1605 | return 0; |
| 1606 | |
| 1607 | err_pages: |
| 1608 | while (i--) |
| 1609 | page_cache_release(obj_priv->pages[i]); |
| 1610 | |
| 1611 | drm_free_large(obj_priv->pages); |
| 1612 | obj_priv->pages = NULL; |
| 1613 | return PTR_ERR(page); |
| 1614 | } |
| 1615 | |
Chris Wilson | 5cdf588 | 2010-09-27 15:51:07 +0100 | [diff] [blame] | 1616 | static void |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 1617 | i915_gem_object_put_pages_gtt(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1618 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1619 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1620 | int page_count = obj->size / PAGE_SIZE; |
| 1621 | int i; |
| 1622 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1623 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1624 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1625 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1626 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1627 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1628 | if (obj_priv->madv == I915_MADV_DONTNEED) |
Chris Wilson | 13a05fd | 2009-09-20 23:03:19 +0100 | [diff] [blame] | 1629 | obj_priv->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1630 | |
| 1631 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1632 | if (obj_priv->dirty) |
| 1633 | set_page_dirty(obj_priv->pages[i]); |
| 1634 | |
| 1635 | if (obj_priv->madv == I915_MADV_WILLNEED) |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1636 | mark_page_accessed(obj_priv->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1637 | |
| 1638 | page_cache_release(obj_priv->pages[i]); |
| 1639 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1640 | obj_priv->dirty = 0; |
| 1641 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 1642 | drm_free_large(obj_priv->pages); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1643 | obj_priv->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1644 | } |
| 1645 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1646 | static uint32_t |
| 1647 | i915_gem_next_request_seqno(struct drm_device *dev, |
| 1648 | struct intel_ring_buffer *ring) |
| 1649 | { |
| 1650 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1651 | |
| 1652 | ring->outstanding_lazy_request = true; |
| 1653 | return dev_priv->next_seqno; |
| 1654 | } |
| 1655 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1656 | static void |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1657 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1658 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1659 | { |
| 1660 | struct drm_device *dev = obj->dev; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1661 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1662 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1663 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1664 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1665 | BUG_ON(ring == NULL); |
| 1666 | obj_priv->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1667 | |
| 1668 | /* Add a reference if we're newly entering the active list. */ |
| 1669 | if (!obj_priv->active) { |
| 1670 | drm_gem_object_reference(obj); |
| 1671 | obj_priv->active = 1; |
| 1672 | } |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 1673 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1674 | /* Move from whatever list we were on to the tail of execution. */ |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1675 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list); |
| 1676 | list_move_tail(&obj_priv->ring_list, &ring->active_list); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1677 | obj_priv->last_rendering_seqno = seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1678 | } |
| 1679 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1680 | static void |
| 1681 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) |
| 1682 | { |
| 1683 | struct drm_device *dev = obj->dev; |
| 1684 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1685 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1686 | |
| 1687 | BUG_ON(!obj_priv->active); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1688 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list); |
| 1689 | list_del_init(&obj_priv->ring_list); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1690 | obj_priv->last_rendering_seqno = 0; |
| 1691 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1692 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1693 | /* Immediately discard the backing storage */ |
| 1694 | static void |
| 1695 | i915_gem_object_truncate(struct drm_gem_object *obj) |
| 1696 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1697 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1698 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1699 | |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1700 | /* Our goal here is to return as much of the memory as |
| 1701 | * is possible back to the system as we are called from OOM. |
| 1702 | * To do this we must instruct the shmfs to drop all of its |
| 1703 | * backing pages, *now*. Here we mirror the actions taken |
| 1704 | * when by shmem_delete_inode() to release the backing store. |
| 1705 | */ |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1706 | inode = obj->filp->f_path.dentry->d_inode; |
Chris Wilson | ae9fed6 | 2010-08-07 11:01:30 +0100 | [diff] [blame] | 1707 | truncate_inode_pages(inode->i_mapping, 0); |
| 1708 | if (inode->i_op->truncate_range) |
| 1709 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1710 | |
| 1711 | obj_priv->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1712 | } |
| 1713 | |
| 1714 | static inline int |
| 1715 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) |
| 1716 | { |
| 1717 | return obj_priv->madv == I915_MADV_DONTNEED; |
| 1718 | } |
| 1719 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1720 | static void |
| 1721 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) |
| 1722 | { |
| 1723 | struct drm_device *dev = obj->dev; |
| 1724 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1725 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1726 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1727 | if (obj_priv->pin_count != 0) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1728 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1729 | else |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1730 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
| 1731 | list_del_init(&obj_priv->ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1732 | |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 1733 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
| 1734 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1735 | obj_priv->last_rendering_seqno = 0; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1736 | obj_priv->ring = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1737 | if (obj_priv->active) { |
| 1738 | obj_priv->active = 0; |
| 1739 | drm_gem_object_unreference(obj); |
| 1740 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1741 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1742 | } |
| 1743 | |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1744 | static void |
| 1745 | i915_gem_process_flushing_list(struct drm_device *dev, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1746 | uint32_t flush_domains, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1747 | struct intel_ring_buffer *ring) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1748 | { |
| 1749 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1750 | struct drm_i915_gem_object *obj_priv, *next; |
| 1751 | |
| 1752 | list_for_each_entry_safe(obj_priv, next, |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1753 | &ring->gpu_write_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1754 | gpu_write_list) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 1755 | struct drm_gem_object *obj = &obj_priv->base; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1756 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 1757 | if (obj->write_domain & flush_domains) { |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1758 | uint32_t old_write_domain = obj->write_domain; |
| 1759 | |
| 1760 | obj->write_domain = 0; |
| 1761 | list_del_init(&obj_priv->gpu_write_list); |
Daniel Vetter | 617dbe2 | 2010-02-11 22:16:02 +0100 | [diff] [blame] | 1762 | i915_gem_object_move_to_active(obj, ring); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1763 | |
| 1764 | /* update the fence lru list */ |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1765 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
| 1766 | struct drm_i915_fence_reg *reg = |
| 1767 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 1768 | list_move_tail(®->lru_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1769 | &dev_priv->mm.fence_list); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1770 | } |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1771 | |
| 1772 | trace_i915_gem_object_change_domain(obj, |
| 1773 | obj->read_domains, |
| 1774 | old_write_domain); |
| 1775 | } |
| 1776 | } |
| 1777 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1778 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1779 | int |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1780 | i915_add_request(struct drm_device *dev, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1781 | struct drm_file *file, |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 1782 | struct drm_i915_gem_request *request, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1783 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1784 | { |
| 1785 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1786 | struct drm_i915_file_private *file_priv = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1787 | uint32_t seqno; |
| 1788 | int was_empty; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1789 | int ret; |
| 1790 | |
| 1791 | BUG_ON(request == NULL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1792 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1793 | if (file != NULL) |
| 1794 | file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1795 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1796 | ret = ring->add_request(ring, &seqno); |
| 1797 | if (ret) |
| 1798 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1799 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 1800 | ring->outstanding_lazy_request = false; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1801 | |
| 1802 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1803 | request->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1804 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1805 | was_empty = list_empty(&ring->request_list); |
| 1806 | list_add_tail(&request->list, &ring->request_list); |
| 1807 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1808 | if (file_priv) { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1809 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1810 | request->file_priv = file_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1811 | list_add_tail(&request->client_list, |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1812 | &file_priv->mm.request_list); |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1813 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1814 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1815 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1816 | if (!dev_priv->mm.suspended) { |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1817 | mod_timer(&dev_priv->hangcheck_timer, |
| 1818 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1819 | if (was_empty) |
Chris Wilson | b3b079d | 2010-09-13 23:44:34 +0100 | [diff] [blame] | 1820 | queue_delayed_work(dev_priv->wq, |
| 1821 | &dev_priv->mm.retire_work, HZ); |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1822 | } |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 1823 | return 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1824 | } |
| 1825 | |
| 1826 | /** |
| 1827 | * Command execution barrier |
| 1828 | * |
| 1829 | * Ensures that all commands in the ring are finished |
| 1830 | * before signalling the CPU |
| 1831 | */ |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 1832 | static void |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1833 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1834 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1835 | uint32_t flush_domains = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1836 | |
| 1837 | /* The sampler always gets flushed on i965 (sigh) */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1838 | if (INTEL_INFO(dev)->gen >= 4) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1839 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1840 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1841 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1842 | } |
| 1843 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1844 | static inline void |
| 1845 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1846 | { |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1847 | struct drm_i915_file_private *file_priv = request->file_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1848 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1849 | if (!file_priv) |
| 1850 | return; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1851 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 1852 | spin_lock(&file_priv->mm.lock); |
| 1853 | list_del(&request->client_list); |
| 1854 | request->file_priv = NULL; |
| 1855 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1856 | } |
| 1857 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1858 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
| 1859 | struct intel_ring_buffer *ring) |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1860 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1861 | while (!list_empty(&ring->request_list)) { |
| 1862 | struct drm_i915_gem_request *request; |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1863 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1864 | request = list_first_entry(&ring->request_list, |
| 1865 | struct drm_i915_gem_request, |
| 1866 | list); |
| 1867 | |
| 1868 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1869 | i915_gem_request_remove_from_client(request); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1870 | kfree(request); |
| 1871 | } |
| 1872 | |
| 1873 | while (!list_empty(&ring->active_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1874 | struct drm_i915_gem_object *obj_priv; |
| 1875 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1876 | obj_priv = list_first_entry(&ring->active_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1877 | struct drm_i915_gem_object, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1878 | ring_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1879 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1880 | obj_priv->base.write_domain = 0; |
| 1881 | list_del_init(&obj_priv->gpu_write_list); |
| 1882 | i915_gem_object_move_to_inactive(&obj_priv->base); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1883 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1884 | } |
| 1885 | |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1886 | void i915_gem_reset(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1887 | { |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1888 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1889 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1890 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1891 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1892 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 1893 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1894 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1895 | |
| 1896 | /* Remove anything from the flushing lists. The GPU cache is likely |
| 1897 | * to be lost on reset along with the data, so simply move the |
| 1898 | * lost bo to the inactive list. |
| 1899 | */ |
| 1900 | while (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1901 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, |
| 1902 | struct drm_i915_gem_object, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1903 | mm_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1904 | |
| 1905 | obj_priv->base.write_domain = 0; |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1906 | list_del_init(&obj_priv->gpu_write_list); |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1907 | i915_gem_object_move_to_inactive(&obj_priv->base); |
| 1908 | } |
Chris Wilson | 9375e44 | 2010-09-19 12:21:28 +0100 | [diff] [blame] | 1909 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1910 | /* Move everything out of the GPU domains to ensure we do any |
| 1911 | * necessary invalidation upon reuse. |
| 1912 | */ |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1913 | list_for_each_entry(obj_priv, |
| 1914 | &dev_priv->mm.inactive_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1915 | mm_list) |
Chris Wilson | 77f0123 | 2010-09-19 12:31:36 +0100 | [diff] [blame] | 1916 | { |
| 1917 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
| 1918 | } |
Chris Wilson | 069efc1 | 2010-09-30 16:53:18 +0100 | [diff] [blame] | 1919 | |
| 1920 | /* The fence registers are invalidated so clear them out */ |
| 1921 | for (i = 0; i < 16; i++) { |
| 1922 | struct drm_i915_fence_reg *reg; |
| 1923 | |
| 1924 | reg = &dev_priv->fence_regs[i]; |
| 1925 | if (!reg->obj) |
| 1926 | continue; |
| 1927 | |
| 1928 | i915_gem_clear_fence_reg(reg->obj); |
| 1929 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1930 | } |
| 1931 | |
| 1932 | /** |
| 1933 | * This function clears the request list as sequence numbers are passed. |
| 1934 | */ |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1935 | static void |
| 1936 | i915_gem_retire_requests_ring(struct drm_device *dev, |
| 1937 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1938 | { |
| 1939 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1940 | uint32_t seqno; |
| 1941 | |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1942 | if (!ring->status_page.page_addr || |
| 1943 | list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1944 | return; |
| 1945 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1946 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1947 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1948 | seqno = ring->get_seqno(ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1949 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1950 | struct drm_i915_gem_request *request; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1951 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1952 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1953 | struct drm_i915_gem_request, |
| 1954 | list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1955 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1956 | if (!i915_seqno_passed(seqno, request->seqno)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1957 | break; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1958 | |
| 1959 | trace_i915_gem_request_retire(dev, request->seqno); |
| 1960 | |
| 1961 | list_del(&request->list); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 1962 | i915_gem_request_remove_from_client(request); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1963 | kfree(request); |
| 1964 | } |
| 1965 | |
| 1966 | /* Move any buffers on the active list that are no longer referenced |
| 1967 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1968 | */ |
| 1969 | while (!list_empty(&ring->active_list)) { |
| 1970 | struct drm_gem_object *obj; |
| 1971 | struct drm_i915_gem_object *obj_priv; |
| 1972 | |
| 1973 | obj_priv = list_first_entry(&ring->active_list, |
| 1974 | struct drm_i915_gem_object, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 1975 | ring_list); |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1976 | |
Chris Wilson | dfaae39 | 2010-09-22 10:31:52 +0100 | [diff] [blame] | 1977 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1978 | break; |
| 1979 | |
| 1980 | obj = &obj_priv->base; |
Chris Wilson | b84d5f0 | 2010-09-18 01:38:04 +0100 | [diff] [blame] | 1981 | if (obj->write_domain != 0) |
| 1982 | i915_gem_object_move_to_flushing(obj); |
| 1983 | else |
| 1984 | i915_gem_object_move_to_inactive(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1985 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1986 | |
| 1987 | if (unlikely (dev_priv->trace_irq_seqno && |
| 1988 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1989 | ring->user_irq_put(ring); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1990 | dev_priv->trace_irq_seqno = 0; |
| 1991 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 1992 | |
| 1993 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1994 | } |
| 1995 | |
| 1996 | void |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 1997 | i915_gem_retire_requests(struct drm_device *dev) |
| 1998 | { |
| 1999 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2000 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 2001 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
| 2002 | struct drm_i915_gem_object *obj_priv, *tmp; |
| 2003 | |
| 2004 | /* We must be careful that during unbind() we do not |
| 2005 | * accidentally infinitely recurse into retire requests. |
| 2006 | * Currently: |
| 2007 | * retire -> free -> unbind -> wait -> retire_ring |
| 2008 | */ |
| 2009 | list_for_each_entry_safe(obj_priv, tmp, |
| 2010 | &dev_priv->mm.deferred_free_list, |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2011 | mm_list) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 2012 | i915_gem_free_object_tail(&obj_priv->base); |
| 2013 | } |
| 2014 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2015 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 2016 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2017 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2018 | } |
| 2019 | |
Daniel Vetter | 75ef9da | 2010-08-21 00:25:16 +0200 | [diff] [blame] | 2020 | static void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2021 | i915_gem_retire_work_handler(struct work_struct *work) |
| 2022 | { |
| 2023 | drm_i915_private_t *dev_priv; |
| 2024 | struct drm_device *dev; |
| 2025 | |
| 2026 | dev_priv = container_of(work, drm_i915_private_t, |
| 2027 | mm.retire_work.work); |
| 2028 | dev = dev_priv->dev; |
| 2029 | |
Chris Wilson | 891b48c | 2010-09-29 12:26:37 +0100 | [diff] [blame] | 2030 | /* Come back later if the device is busy... */ |
| 2031 | if (!mutex_trylock(&dev->struct_mutex)) { |
| 2032 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 2033 | return; |
| 2034 | } |
| 2035 | |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2036 | i915_gem_retire_requests(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2037 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 2038 | if (!dev_priv->mm.suspended && |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2039 | (!list_empty(&dev_priv->render_ring.request_list) || |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2040 | !list_empty(&dev_priv->bsd_ring.request_list) || |
| 2041 | !list_empty(&dev_priv->blt_ring.request_list))) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 2042 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2043 | mutex_unlock(&dev->struct_mutex); |
| 2044 | } |
| 2045 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 2046 | int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2047 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2048 | bool interruptible, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2049 | { |
| 2050 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 2051 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2052 | int ret = 0; |
| 2053 | |
| 2054 | BUG_ON(seqno == 0); |
| 2055 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2056 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 2057 | return -EAGAIN; |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 2058 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2059 | if (ring->outstanding_lazy_request) { |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2060 | struct drm_i915_gem_request *request; |
| 2061 | |
| 2062 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 2063 | if (request == NULL) |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2064 | return -ENOMEM; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 2065 | |
| 2066 | ret = i915_add_request(dev, NULL, request, ring); |
| 2067 | if (ret) { |
| 2068 | kfree(request); |
| 2069 | return ret; |
| 2070 | } |
| 2071 | |
| 2072 | seqno = request->seqno; |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2073 | } |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2074 | BUG_ON(seqno == dev_priv->next_seqno); |
Daniel Vetter | e35a41d | 2010-02-11 22:13:59 +0100 | [diff] [blame] | 2075 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2076 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 2077 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 2078 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 2079 | else |
| 2080 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 2081 | if (!ier) { |
| 2082 | DRM_ERROR("something (likely vbetool) disabled " |
| 2083 | "interrupts, re-enabling\n"); |
| 2084 | i915_driver_irq_preinstall(dev); |
| 2085 | i915_driver_irq_postinstall(dev); |
| 2086 | } |
| 2087 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2088 | trace_i915_gem_request_wait_begin(dev, seqno); |
| 2089 | |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 2090 | ring->waiting_seqno = seqno; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2091 | ring->user_irq_get(ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2092 | if (interruptible) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2093 | ret = wait_event_interruptible(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2094 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2095 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2096 | else |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2097 | wait_event(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2098 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2099 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2100 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2101 | ring->user_irq_put(ring); |
Chris Wilson | b222349 | 2010-10-27 15:27:33 +0100 | [diff] [blame] | 2102 | ring->waiting_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2103 | |
| 2104 | trace_i915_gem_request_wait_end(dev, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2105 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 2106 | if (atomic_read(&dev_priv->mm.wedged)) |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 2107 | ret = -EAGAIN; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2108 | |
| 2109 | if (ret && ret != -ERESTARTSYS) |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2110 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2111 | __func__, ret, seqno, ring->get_seqno(ring), |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2112 | dev_priv->next_seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2113 | |
| 2114 | /* Directly dispatch request retiring. While we have the work queue |
| 2115 | * to handle this, the waiter on a request often wants an associated |
| 2116 | * buffer to have made it to the inactive list, and we would need |
| 2117 | * a separate wait queue to handle that. |
| 2118 | */ |
| 2119 | if (ret == 0) |
Chris Wilson | b09a1fe | 2010-07-23 23:18:49 +0100 | [diff] [blame] | 2120 | i915_gem_retire_requests_ring(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2121 | |
| 2122 | return ret; |
| 2123 | } |
| 2124 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2125 | /** |
| 2126 | * Waits for a sequence number to be signaled, and cleans up the |
| 2127 | * request and object lists appropriately for that event. |
| 2128 | */ |
| 2129 | static int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2130 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2131 | struct intel_ring_buffer *ring) |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2132 | { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2133 | return i915_do_wait_request(dev, seqno, 1, ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 2134 | } |
| 2135 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2136 | static void |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2137 | i915_gem_flush_ring(struct drm_device *dev, |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2138 | struct drm_file *file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2139 | struct intel_ring_buffer *ring, |
| 2140 | uint32_t invalidate_domains, |
| 2141 | uint32_t flush_domains) |
| 2142 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 2143 | ring->flush(ring, invalidate_domains, flush_domains); |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2144 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
| 2145 | } |
| 2146 | |
| 2147 | static void |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2148 | i915_gem_flush(struct drm_device *dev, |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2149 | struct drm_file *file_priv, |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2150 | uint32_t invalidate_domains, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2151 | uint32_t flush_domains, |
| 2152 | uint32_t flush_rings) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2153 | { |
| 2154 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 8bff917 | 2010-02-11 22:19:40 +0100 | [diff] [blame] | 2155 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2156 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
| 2157 | drm_agp_chipset_flush(dev); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2158 | |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2159 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
| 2160 | if (flush_rings & RING_RENDER) |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2161 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2162 | &dev_priv->render_ring, |
| 2163 | invalidate_domains, flush_domains); |
| 2164 | if (flush_rings & RING_BSD) |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2165 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2166 | &dev_priv->bsd_ring, |
| 2167 | invalidate_domains, flush_domains); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2168 | if (flush_rings & RING_BLT) |
| 2169 | i915_gem_flush_ring(dev, file_priv, |
| 2170 | &dev_priv->blt_ring, |
| 2171 | invalidate_domains, flush_domains); |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2172 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 2173 | } |
| 2174 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2175 | /** |
| 2176 | * Ensures that all rendering to the object has completed and the object is |
| 2177 | * safe to unbind from the GTT or access from the CPU. |
| 2178 | */ |
| 2179 | static int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2180 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
| 2181 | bool interruptible) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2182 | { |
| 2183 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2184 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2185 | int ret; |
| 2186 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2187 | /* This function only exists to support waiting for existing rendering, |
| 2188 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2189 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2190 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2191 | |
| 2192 | /* If there is rendering queued on the buffer being evicted, wait for |
| 2193 | * it. |
| 2194 | */ |
| 2195 | if (obj_priv->active) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2196 | ret = i915_do_wait_request(dev, |
| 2197 | obj_priv->last_rendering_seqno, |
| 2198 | interruptible, |
| 2199 | obj_priv->ring); |
| 2200 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2201 | return ret; |
| 2202 | } |
| 2203 | |
| 2204 | return 0; |
| 2205 | } |
| 2206 | |
| 2207 | /** |
| 2208 | * Unbinds an object from the GTT aperture. |
| 2209 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2210 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2211 | i915_gem_object_unbind(struct drm_gem_object *obj) |
| 2212 | { |
| 2213 | struct drm_device *dev = obj->dev; |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2214 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2215 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2216 | int ret = 0; |
| 2217 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2218 | if (obj_priv->gtt_space == NULL) |
| 2219 | return 0; |
| 2220 | |
| 2221 | if (obj_priv->pin_count != 0) { |
| 2222 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 2223 | return -EINVAL; |
| 2224 | } |
| 2225 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 2226 | /* blow away mappings if mapped through GTT */ |
| 2227 | i915_gem_release_mmap(obj); |
| 2228 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2229 | /* Move the object to the CPU domain to ensure that |
| 2230 | * any possible CPU writes while it's not in the GTT |
| 2231 | * are flushed when we go to remap it. This will |
| 2232 | * also ensure that all pending GPU writes are finished |
| 2233 | * before we unbind. |
| 2234 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2235 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2236 | if (ret == -ERESTARTSYS) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2237 | return ret; |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2238 | /* Continue on if we fail due to EIO, the GPU is hung so we |
| 2239 | * should be safe and we need to cleanup or else we might |
| 2240 | * cause memory corruption through use-after-free. |
| 2241 | */ |
Chris Wilson | 812ed492 | 2010-09-30 15:08:57 +0100 | [diff] [blame] | 2242 | if (ret) { |
| 2243 | i915_gem_clflush_object(obj); |
| 2244 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 2245 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2246 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2247 | /* release the fence reg _after_ flushing */ |
| 2248 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) |
| 2249 | i915_gem_clear_fence_reg(obj); |
| 2250 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2251 | drm_unbind_agp(obj_priv->agp_mem); |
| 2252 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2253 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2254 | i915_gem_object_put_pages_gtt(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2255 | |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 2256 | i915_gem_info_remove_gtt(dev_priv, obj); |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2257 | list_del_init(&obj_priv->mm_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2258 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 2259 | drm_mm_put_block(obj_priv->gtt_space); |
| 2260 | obj_priv->gtt_space = NULL; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 2261 | obj_priv->gtt_offset = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2262 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2263 | if (i915_gem_object_is_purgeable(obj_priv)) |
| 2264 | i915_gem_object_truncate(obj); |
| 2265 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2266 | trace_i915_gem_object_unbind(obj); |
| 2267 | |
Chris Wilson | 8dc1775 | 2010-07-23 23:18:51 +0100 | [diff] [blame] | 2268 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2269 | } |
| 2270 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2271 | static int i915_ring_idle(struct drm_device *dev, |
| 2272 | struct intel_ring_buffer *ring) |
| 2273 | { |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 2274 | if (list_empty(&ring->gpu_write_list)) |
| 2275 | return 0; |
| 2276 | |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2277 | i915_gem_flush_ring(dev, NULL, ring, |
| 2278 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 2279 | return i915_wait_request(dev, |
| 2280 | i915_gem_next_request_seqno(dev, ring), |
| 2281 | ring); |
| 2282 | } |
| 2283 | |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 2284 | int |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2285 | i915_gpu_idle(struct drm_device *dev) |
| 2286 | { |
| 2287 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2288 | bool lists_empty; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2289 | int ret; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2290 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2291 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
| 2292 | list_empty(&dev_priv->render_ring.active_list) && |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2293 | list_empty(&dev_priv->bsd_ring.active_list) && |
| 2294 | list_empty(&dev_priv->blt_ring.active_list)); |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2295 | if (lists_empty) |
| 2296 | return 0; |
| 2297 | |
| 2298 | /* Flush everything onto the inactive list. */ |
Chris Wilson | a56ba56 | 2010-09-28 10:07:56 +0100 | [diff] [blame] | 2299 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2300 | if (ret) |
| 2301 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2302 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 2303 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
| 2304 | if (ret) |
| 2305 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2306 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 2307 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
| 2308 | if (ret) |
| 2309 | return ret; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2310 | |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 2311 | return 0; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2312 | } |
| 2313 | |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2314 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2315 | { |
| 2316 | struct drm_gem_object *obj = reg->obj; |
| 2317 | struct drm_device *dev = obj->dev; |
| 2318 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2319 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2320 | int regnum = obj_priv->fence_reg; |
| 2321 | uint64_t val; |
| 2322 | |
| 2323 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2324 | 0xfffff000) << 32; |
| 2325 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2326 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << |
| 2327 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2328 | |
| 2329 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2330 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2331 | val |= I965_FENCE_REG_VALID; |
| 2332 | |
| 2333 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); |
| 2334 | } |
| 2335 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2336 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2337 | { |
| 2338 | struct drm_gem_object *obj = reg->obj; |
| 2339 | struct drm_device *dev = obj->dev; |
| 2340 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2341 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2342 | int regnum = obj_priv->fence_reg; |
| 2343 | uint64_t val; |
| 2344 | |
| 2345 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2346 | 0xfffff000) << 32; |
| 2347 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2348 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2349 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2350 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2351 | val |= I965_FENCE_REG_VALID; |
| 2352 | |
| 2353 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); |
| 2354 | } |
| 2355 | |
| 2356 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2357 | { |
| 2358 | struct drm_gem_object *obj = reg->obj; |
| 2359 | struct drm_device *dev = obj->dev; |
| 2360 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2361 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2362 | int regnum = obj_priv->fence_reg; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2363 | int tile_width; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2364 | uint32_t fence_reg, val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2365 | uint32_t pitch_val; |
| 2366 | |
| 2367 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2368 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Linus Torvalds | f06da26 | 2009-02-09 08:57:29 -0800 | [diff] [blame] | 2369 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2370 | __func__, obj_priv->gtt_offset, obj->size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2371 | return; |
| 2372 | } |
| 2373 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2374 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2375 | HAS_128_BYTE_Y_TILING(dev)) |
| 2376 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2377 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2378 | tile_width = 512; |
| 2379 | |
| 2380 | /* Note: pitch better be a power of two tile widths */ |
| 2381 | pitch_val = obj_priv->stride / tile_width; |
| 2382 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2383 | |
Daniel Vetter | c36a2a6 | 2010-04-17 15:12:03 +0200 | [diff] [blame] | 2384 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2385 | HAS_128_BYTE_Y_TILING(dev)) |
| 2386 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2387 | else |
| 2388 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); |
| 2389 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2390 | val = obj_priv->gtt_offset; |
| 2391 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2392 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2393 | val |= I915_FENCE_SIZE_BITS(obj->size); |
| 2394 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2395 | val |= I830_FENCE_REG_VALID; |
| 2396 | |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2397 | if (regnum < 8) |
| 2398 | fence_reg = FENCE_REG_830_0 + (regnum * 4); |
| 2399 | else |
| 2400 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); |
| 2401 | I915_WRITE(fence_reg, val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2402 | } |
| 2403 | |
| 2404 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2405 | { |
| 2406 | struct drm_gem_object *obj = reg->obj; |
| 2407 | struct drm_device *dev = obj->dev; |
| 2408 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2409 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2410 | int regnum = obj_priv->fence_reg; |
| 2411 | uint32_t val; |
| 2412 | uint32_t pitch_val; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2413 | uint32_t fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2414 | |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2415 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2416 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2417 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2418 | __func__, obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2419 | return; |
| 2420 | } |
| 2421 | |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2422 | pitch_val = obj_priv->stride / 128; |
| 2423 | pitch_val = ffs(pitch_val) - 1; |
| 2424 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2425 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2426 | val = obj_priv->gtt_offset; |
| 2427 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2428 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2429 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
| 2430 | WARN_ON(fence_size_bits & ~0x00000f00); |
| 2431 | val |= fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2432 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2433 | val |= I830_FENCE_REG_VALID; |
| 2434 | |
| 2435 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2436 | } |
| 2437 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2438 | static int i915_find_fence_reg(struct drm_device *dev, |
| 2439 | bool interruptible) |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2440 | { |
| 2441 | struct drm_i915_fence_reg *reg = NULL; |
| 2442 | struct drm_i915_gem_object *obj_priv = NULL; |
| 2443 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2444 | struct drm_gem_object *obj = NULL; |
| 2445 | int i, avail, ret; |
| 2446 | |
| 2447 | /* First try to find a free reg */ |
| 2448 | avail = 0; |
| 2449 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2450 | reg = &dev_priv->fence_regs[i]; |
| 2451 | if (!reg->obj) |
| 2452 | return i; |
| 2453 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2454 | obj_priv = to_intel_bo(reg->obj); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2455 | if (!obj_priv->pin_count) |
| 2456 | avail++; |
| 2457 | } |
| 2458 | |
| 2459 | if (avail == 0) |
| 2460 | return -ENOSPC; |
| 2461 | |
| 2462 | /* None available, try to steal one or wait for a user to finish */ |
| 2463 | i = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2464 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
| 2465 | lru_list) { |
| 2466 | obj = reg->obj; |
| 2467 | obj_priv = to_intel_bo(obj); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2468 | |
| 2469 | if (obj_priv->pin_count) |
| 2470 | continue; |
| 2471 | |
| 2472 | /* found one! */ |
| 2473 | i = obj_priv->fence_reg; |
| 2474 | break; |
| 2475 | } |
| 2476 | |
| 2477 | BUG_ON(i == I915_FENCE_REG_NONE); |
| 2478 | |
| 2479 | /* We only have a reference on obj from the active list. put_fence_reg |
| 2480 | * might drop that one, causing a use-after-free in it. So hold a |
| 2481 | * private reference to obj like the other callers of put_fence_reg |
| 2482 | * (set_tiling ioctl) do. */ |
| 2483 | drm_gem_object_reference(obj); |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2484 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2485 | drm_gem_object_unreference(obj); |
| 2486 | if (ret != 0) |
| 2487 | return ret; |
| 2488 | |
| 2489 | return i; |
| 2490 | } |
| 2491 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2492 | /** |
| 2493 | * i915_gem_object_get_fence_reg - set up a fence reg for an object |
| 2494 | * @obj: object to map through a fence reg |
| 2495 | * |
| 2496 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2497 | * to them without having to worry about swizzling if the object is tiled. |
| 2498 | * |
| 2499 | * This function walks the fence regs looking for a free one for @obj, |
| 2500 | * stealing one if it can't find any. |
| 2501 | * |
| 2502 | * It then sets up the reg based on the object's properties: address, pitch |
| 2503 | * and tiling format. |
| 2504 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2505 | int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2506 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
| 2507 | bool interruptible) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2508 | { |
| 2509 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2510 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2511 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2512 | struct drm_i915_fence_reg *reg = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2513 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2514 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2515 | /* Just update our place in the LRU if our fence is getting used. */ |
| 2516 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2517 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 2518 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2519 | return 0; |
| 2520 | } |
| 2521 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2522 | switch (obj_priv->tiling_mode) { |
| 2523 | case I915_TILING_NONE: |
| 2524 | WARN(1, "allocating a fence for non-tiled object?\n"); |
| 2525 | break; |
| 2526 | case I915_TILING_X: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2527 | if (!obj_priv->stride) |
| 2528 | return -EINVAL; |
| 2529 | WARN((obj_priv->stride & (512 - 1)), |
| 2530 | "object 0x%08x is X tiled but has non-512B pitch\n", |
| 2531 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2532 | break; |
| 2533 | case I915_TILING_Y: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2534 | if (!obj_priv->stride) |
| 2535 | return -EINVAL; |
| 2536 | WARN((obj_priv->stride & (128 - 1)), |
| 2537 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
| 2538 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2539 | break; |
| 2540 | } |
| 2541 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2542 | ret = i915_find_fence_reg(dev, interruptible); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2543 | if (ret < 0) |
| 2544 | return ret; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2545 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2546 | obj_priv->fence_reg = ret; |
| 2547 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2548 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2549 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2550 | reg->obj = obj; |
| 2551 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2552 | switch (INTEL_INFO(dev)->gen) { |
| 2553 | case 6: |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2554 | sandybridge_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2555 | break; |
| 2556 | case 5: |
| 2557 | case 4: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2558 | i965_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2559 | break; |
| 2560 | case 3: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2561 | i915_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2562 | break; |
| 2563 | case 2: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2564 | i830_write_fence_reg(reg); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2565 | break; |
| 2566 | } |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2567 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2568 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
| 2569 | obj_priv->tiling_mode); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2570 | |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2571 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2572 | } |
| 2573 | |
| 2574 | /** |
| 2575 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2576 | * @obj: object to clear |
| 2577 | * |
| 2578 | * Zeroes out the fence register itself and clears out the associated |
| 2579 | * data structures in dev_priv and obj_priv. |
| 2580 | */ |
| 2581 | static void |
| 2582 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) |
| 2583 | { |
| 2584 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2585 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2586 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2587 | struct drm_i915_fence_reg *reg = |
| 2588 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2589 | uint32_t fence_reg; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2590 | |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2591 | switch (INTEL_INFO(dev)->gen) { |
| 2592 | case 6: |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2593 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
| 2594 | (obj_priv->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2595 | break; |
| 2596 | case 5: |
| 2597 | case 4: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2598 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2599 | break; |
| 2600 | case 3: |
Chris Wilson | 9b74f73 | 2010-09-22 19:10:44 +0100 | [diff] [blame] | 2601 | if (obj_priv->fence_reg >= 8) |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2602 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2603 | else |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2604 | case 2: |
| 2605 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2606 | |
| 2607 | I915_WRITE(fence_reg, 0); |
Chris Wilson | e259bef | 2010-09-17 00:32:02 +0100 | [diff] [blame] | 2608 | break; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2609 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2610 | |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2611 | reg->obj = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2612 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2613 | list_del_init(®->lru_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2614 | } |
| 2615 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2616 | /** |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2617 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access |
| 2618 | * to the buffer to finish, and then resets the fence register. |
| 2619 | * @obj: tiled object holding a fence register. |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2620 | * @bool: whether the wait upon the fence is interruptible |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2621 | * |
| 2622 | * Zeroes out the fence register itself and clears out the associated |
| 2623 | * data structures in dev_priv and obj_priv. |
| 2624 | */ |
| 2625 | int |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2626 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
| 2627 | bool interruptible) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2628 | { |
| 2629 | struct drm_device *dev = obj->dev; |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2630 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2631 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2632 | struct drm_i915_fence_reg *reg; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2633 | |
| 2634 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) |
| 2635 | return 0; |
| 2636 | |
Daniel Vetter | 10ae9bd | 2010-02-01 13:59:17 +0100 | [diff] [blame] | 2637 | /* If we've changed tiling, GTT-mappings of the object |
| 2638 | * need to re-fault to ensure that the correct fence register |
| 2639 | * setup is in place. |
| 2640 | */ |
| 2641 | i915_gem_release_mmap(obj); |
| 2642 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2643 | /* On the i915, GPU access to tiled buffers is via a fence, |
| 2644 | * therefore we must wait for any outstanding access to complete |
| 2645 | * before clearing the fence. |
| 2646 | */ |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2647 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 2648 | if (reg->gpu) { |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2649 | int ret; |
| 2650 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2651 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2652 | if (ret) |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2653 | return ret; |
| 2654 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2655 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2656 | if (ret) |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2657 | return ret; |
Chris Wilson | 53640e1 | 2010-09-20 11:40:50 +0100 | [diff] [blame] | 2658 | |
| 2659 | reg->gpu = false; |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2660 | } |
| 2661 | |
Daniel Vetter | 4a72661 | 2010-02-01 13:59:16 +0100 | [diff] [blame] | 2662 | i915_gem_object_flush_gtt_write_domain(obj); |
Chris Wilson | 0bc23aa | 2010-09-14 10:22:23 +0100 | [diff] [blame] | 2663 | i915_gem_clear_fence_reg(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2664 | |
| 2665 | return 0; |
| 2666 | } |
| 2667 | |
| 2668 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2669 | * Finds free space in the GTT aperture and binds the object there. |
| 2670 | */ |
| 2671 | static int |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2672 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
| 2673 | unsigned alignment, |
| 2674 | bool mappable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2675 | { |
| 2676 | struct drm_device *dev = obj->dev; |
| 2677 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2678 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2679 | struct drm_mm_node *free_space; |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2680 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2681 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2682 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 2683 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2684 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2685 | return -EINVAL; |
| 2686 | } |
| 2687 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2688 | if (alignment == 0) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2689 | alignment = i915_gem_get_gtt_alignment(obj); |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2690 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2691 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2692 | return -EINVAL; |
| 2693 | } |
| 2694 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2695 | /* If the object is bigger than the entire aperture, reject it early |
| 2696 | * before evicting everything in a vain attempt to find space. |
| 2697 | */ |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2698 | if (obj->size > |
| 2699 | (mappable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2700 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2701 | return -E2BIG; |
| 2702 | } |
| 2703 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2704 | search_free: |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2705 | if (mappable) |
| 2706 | free_space = |
| 2707 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, |
| 2708 | obj->size, alignment, 0, |
| 2709 | dev_priv->mm.gtt_mappable_end, |
| 2710 | 0); |
| 2711 | else |
| 2712 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
| 2713 | obj->size, alignment, 0); |
| 2714 | |
| 2715 | if (free_space != NULL) { |
| 2716 | if (mappable) |
| 2717 | obj_priv->gtt_space = |
| 2718 | drm_mm_get_block_range_generic(free_space, |
| 2719 | obj->size, |
| 2720 | alignment, 0, |
| 2721 | dev_priv->mm.gtt_mappable_end, |
| 2722 | 0); |
| 2723 | else |
| 2724 | obj_priv->gtt_space = |
| 2725 | drm_mm_get_block(free_space, obj->size, |
| 2726 | alignment); |
| 2727 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2728 | if (obj_priv->gtt_space == NULL) { |
| 2729 | /* If the gtt is empty and we're still having trouble |
| 2730 | * fitting our object in, we're out of memory. |
| 2731 | */ |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2732 | ret = i915_gem_evict_something(dev, obj->size, alignment, |
| 2733 | mappable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2734 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2735 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2736 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2737 | goto search_free; |
| 2738 | } |
| 2739 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2740 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2741 | if (ret) { |
| 2742 | drm_mm_put_block(obj_priv->gtt_space); |
| 2743 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2744 | |
| 2745 | if (ret == -ENOMEM) { |
| 2746 | /* first try to clear up some space from the GTT */ |
Daniel Vetter | 0108a3e | 2010-08-07 11:01:21 +0100 | [diff] [blame] | 2747 | ret = i915_gem_evict_something(dev, obj->size, |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2748 | alignment, mappable); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2749 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2750 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2751 | if (gfpmask) { |
| 2752 | gfpmask = 0; |
| 2753 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2754 | } |
| 2755 | |
| 2756 | return ret; |
| 2757 | } |
| 2758 | |
| 2759 | goto search_free; |
| 2760 | } |
| 2761 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2762 | return ret; |
| 2763 | } |
| 2764 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2765 | /* Create an AGP memory structure pointing at our pages, and bind it |
| 2766 | * into the GTT. |
| 2767 | */ |
| 2768 | obj_priv->agp_mem = drm_agp_bind_pages(dev, |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2769 | obj_priv->pages, |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2770 | obj->size >> PAGE_SHIFT, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 2771 | obj_priv->gtt_space->start, |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 2772 | obj_priv->agp_type); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2773 | if (obj_priv->agp_mem == NULL) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 2774 | i915_gem_object_put_pages_gtt(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2775 | drm_mm_put_block(obj_priv->gtt_space); |
| 2776 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2777 | |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 2778 | ret = i915_gem_evict_something(dev, obj->size, alignment, |
| 2779 | mappable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2780 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2781 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2782 | |
| 2783 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2784 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2785 | |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 2786 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
| 2787 | |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2788 | /* keep track of bounds object by adding it to the inactive list */ |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 2789 | list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 2790 | i915_gem_info_add_gtt(dev_priv, obj); |
Chris Wilson | bf1a109 | 2010-08-07 11:01:20 +0100 | [diff] [blame] | 2791 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2792 | /* Assert that the object is not currently in any GPU domain. As it |
| 2793 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2794 | * a GPU cache |
| 2795 | */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 2796 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
| 2797 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2798 | |
Daniel Vetter | ec57d26 | 2010-09-30 23:42:15 +0200 | [diff] [blame] | 2799 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset, mappable); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2800 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2801 | return 0; |
| 2802 | } |
| 2803 | |
| 2804 | void |
| 2805 | i915_gem_clflush_object(struct drm_gem_object *obj) |
| 2806 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2807 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2808 | |
| 2809 | /* If we don't have a page list set up, then we're not pinned |
| 2810 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2811 | * again at bind time. |
| 2812 | */ |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2813 | if (obj_priv->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2814 | return; |
| 2815 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2816 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2817 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2818 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2819 | } |
| 2820 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2821 | /** Flushes any GPU write domain for the object if it's dirty. */ |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2822 | static int |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2823 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
| 2824 | bool pipelined) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2825 | { |
| 2826 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2827 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2828 | |
| 2829 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2830 | return 0; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2831 | |
| 2832 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2833 | old_write_domain = obj->write_domain; |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2834 | i915_gem_flush_ring(dev, NULL, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 2835 | to_intel_bo(obj)->ring, |
| 2836 | 0, obj->write_domain); |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2837 | BUG_ON(obj->write_domain); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2838 | |
| 2839 | trace_i915_gem_object_change_domain(obj, |
| 2840 | obj->read_domains, |
| 2841 | old_write_domain); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2842 | |
| 2843 | if (pipelined) |
| 2844 | return 0; |
| 2845 | |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2846 | return i915_gem_object_wait_rendering(obj, true); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2847 | } |
| 2848 | |
| 2849 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2850 | static void |
| 2851 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) |
| 2852 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2853 | uint32_t old_write_domain; |
| 2854 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2855 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
| 2856 | return; |
| 2857 | |
| 2858 | /* No actual flushing is required for the GTT write domain. Writes |
| 2859 | * to it immediately go to main memory as far as we know, so there's |
| 2860 | * no chipset flush. It also doesn't land in render cache. |
| 2861 | */ |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame^] | 2862 | i915_gem_release_mmap(obj); |
| 2863 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2864 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2865 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2866 | |
| 2867 | trace_i915_gem_object_change_domain(obj, |
| 2868 | obj->read_domains, |
| 2869 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2870 | } |
| 2871 | |
| 2872 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2873 | static void |
| 2874 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) |
| 2875 | { |
| 2876 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2877 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2878 | |
| 2879 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) |
| 2880 | return; |
| 2881 | |
| 2882 | i915_gem_clflush_object(obj); |
| 2883 | drm_agp_chipset_flush(dev); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2884 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2885 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2886 | |
| 2887 | trace_i915_gem_object_change_domain(obj, |
| 2888 | obj->read_domains, |
| 2889 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2890 | } |
| 2891 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2892 | /** |
| 2893 | * Moves a single object to the GTT read, and possibly write domain. |
| 2894 | * |
| 2895 | * This function returns when the move is complete, including waiting on |
| 2896 | * flushes to occur. |
| 2897 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2898 | int |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2899 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
| 2900 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2901 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2902 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2903 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2904 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2905 | /* Not valid to be called on unbound objects. */ |
| 2906 | if (obj_priv->gtt_space == NULL) |
| 2907 | return -EINVAL; |
| 2908 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2909 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2910 | if (ret != 0) |
| 2911 | return ret; |
| 2912 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2913 | i915_gem_object_flush_cpu_write_domain(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2914 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2915 | if (write) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 2916 | ret = i915_gem_object_wait_rendering(obj, true); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2917 | if (ret) |
| 2918 | return ret; |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2919 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2920 | |
| 2921 | old_write_domain = obj->write_domain; |
| 2922 | old_read_domains = obj->read_domains; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2923 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2924 | /* It should now be out of any other write domains, and we can update |
| 2925 | * the domain values for our changes. |
| 2926 | */ |
| 2927 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2928 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2929 | if (write) { |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 2930 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2931 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2932 | obj_priv->dirty = 1; |
| 2933 | } |
| 2934 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2935 | trace_i915_gem_object_change_domain(obj, |
| 2936 | old_read_domains, |
| 2937 | old_write_domain); |
| 2938 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2939 | return 0; |
| 2940 | } |
| 2941 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2942 | /* |
| 2943 | * Prepare buffer for display plane. Use uninterruptible for possible flush |
| 2944 | * wait, as in modesetting process we're not supposed to be interrupted. |
| 2945 | */ |
| 2946 | int |
Chris Wilson | 48b956c | 2010-09-14 12:50:34 +0100 | [diff] [blame] | 2947 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
| 2948 | bool pipelined) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2949 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2950 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2951 | uint32_t old_read_domains; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2952 | int ret; |
| 2953 | |
| 2954 | /* Not valid to be called on unbound objects. */ |
| 2955 | if (obj_priv->gtt_space == NULL) |
| 2956 | return -EINVAL; |
| 2957 | |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 2958 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
Chris Wilson | 2dafb1e | 2010-06-07 14:03:05 +0100 | [diff] [blame] | 2959 | if (ret) |
| 2960 | return ret; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2961 | |
Chris Wilson | ced270f | 2010-09-26 22:47:46 +0100 | [diff] [blame] | 2962 | /* Currently, we are always called from an non-interruptible context. */ |
| 2963 | if (!pipelined) { |
| 2964 | ret = i915_gem_object_wait_rendering(obj, false); |
| 2965 | if (ret) |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2966 | return ret; |
| 2967 | } |
| 2968 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 2969 | i915_gem_object_flush_cpu_write_domain(obj); |
| 2970 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2971 | old_read_domains = obj->read_domains; |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 2972 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2973 | |
| 2974 | trace_i915_gem_object_change_domain(obj, |
| 2975 | old_read_domains, |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2976 | obj->write_domain); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2977 | |
| 2978 | return 0; |
| 2979 | } |
| 2980 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2981 | /** |
| 2982 | * Moves a single object to the CPU read, and possibly write domain. |
| 2983 | * |
| 2984 | * This function returns when the move is complete, including waiting on |
| 2985 | * flushes to occur. |
| 2986 | */ |
| 2987 | static int |
| 2988 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) |
| 2989 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2990 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2991 | int ret; |
| 2992 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 2993 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2994 | if (ret != 0) |
| 2995 | return ret; |
| 2996 | |
| 2997 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2998 | |
| 2999 | /* If we have a partially-valid cache of the object in the CPU, |
| 3000 | * finish invalidating it and free the per-page flags. |
| 3001 | */ |
| 3002 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 3003 | |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 3004 | if (write) { |
Chris Wilson | 2cf34d7 | 2010-09-14 13:03:28 +0100 | [diff] [blame] | 3005 | ret = i915_gem_object_wait_rendering(obj, true); |
Chris Wilson | 7213342 | 2010-09-13 23:56:38 +0100 | [diff] [blame] | 3006 | if (ret) |
| 3007 | return ret; |
| 3008 | } |
| 3009 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3010 | old_write_domain = obj->write_domain; |
| 3011 | old_read_domains = obj->read_domains; |
| 3012 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3013 | /* Flush the CPU cache if it's still invalid. */ |
| 3014 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
| 3015 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3016 | |
| 3017 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 3018 | } |
| 3019 | |
| 3020 | /* It should now be out of any other write domains, and we can update |
| 3021 | * the domain values for our changes. |
| 3022 | */ |
| 3023 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 3024 | |
| 3025 | /* If we're writing through the CPU, then the GPU read domains will |
| 3026 | * need to be invalidated at next use. |
| 3027 | */ |
| 3028 | if (write) { |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 3029 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3030 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 3031 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3032 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3033 | trace_i915_gem_object_change_domain(obj, |
| 3034 | old_read_domains, |
| 3035 | old_write_domain); |
| 3036 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3037 | return 0; |
| 3038 | } |
| 3039 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3040 | /* |
| 3041 | * Set the next domain for the specified object. This |
| 3042 | * may not actually perform the necessary flushing/invaliding though, |
| 3043 | * as that may want to be batched with other set_domain operations |
| 3044 | * |
| 3045 | * This is (we hope) the only really tricky part of gem. The goal |
| 3046 | * is fairly simple -- track which caches hold bits of the object |
| 3047 | * and make sure they remain coherent. A few concrete examples may |
| 3048 | * help to explain how it works. For shorthand, we use the notation |
| 3049 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 3050 | * a pair of read and write domain masks. |
| 3051 | * |
| 3052 | * Case 1: the batch buffer |
| 3053 | * |
| 3054 | * 1. Allocated |
| 3055 | * 2. Written by CPU |
| 3056 | * 3. Mapped to GTT |
| 3057 | * 4. Read by GPU |
| 3058 | * 5. Unmapped from GTT |
| 3059 | * 6. Freed |
| 3060 | * |
| 3061 | * Let's take these a step at a time |
| 3062 | * |
| 3063 | * 1. Allocated |
| 3064 | * Pages allocated from the kernel may still have |
| 3065 | * cache contents, so we set them to (CPU, CPU) always. |
| 3066 | * 2. Written by CPU (using pwrite) |
| 3067 | * The pwrite function calls set_domain (CPU, CPU) and |
| 3068 | * this function does nothing (as nothing changes) |
| 3069 | * 3. Mapped by GTT |
| 3070 | * This function asserts that the object is not |
| 3071 | * currently in any GPU-based read or write domains |
| 3072 | * 4. Read by GPU |
| 3073 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 3074 | * As write_domain is zero, this function adds in the |
| 3075 | * current read domains (CPU+COMMAND, 0). |
| 3076 | * flush_domains is set to CPU. |
| 3077 | * invalidate_domains is set to COMMAND |
| 3078 | * clflush is run to get data out of the CPU caches |
| 3079 | * then i915_dev_set_domain calls i915_gem_flush to |
| 3080 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 3081 | * 5. Unmapped from GTT |
| 3082 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 3083 | * flush_domains and invalidate_domains end up both zero |
| 3084 | * so no flushing/invalidating happens |
| 3085 | * 6. Freed |
| 3086 | * yay, done |
| 3087 | * |
| 3088 | * Case 2: The shared render buffer |
| 3089 | * |
| 3090 | * 1. Allocated |
| 3091 | * 2. Mapped to GTT |
| 3092 | * 3. Read/written by GPU |
| 3093 | * 4. set_domain to (CPU,CPU) |
| 3094 | * 5. Read/written by CPU |
| 3095 | * 6. Read/written by GPU |
| 3096 | * |
| 3097 | * 1. Allocated |
| 3098 | * Same as last example, (CPU, CPU) |
| 3099 | * 2. Mapped to GTT |
| 3100 | * Nothing changes (assertions find that it is not in the GPU) |
| 3101 | * 3. Read/written by GPU |
| 3102 | * execbuffer calls set_domain (RENDER, RENDER) |
| 3103 | * flush_domains gets CPU |
| 3104 | * invalidate_domains gets GPU |
| 3105 | * clflush (obj) |
| 3106 | * MI_FLUSH and drm_agp_chipset_flush |
| 3107 | * 4. set_domain (CPU, CPU) |
| 3108 | * flush_domains gets GPU |
| 3109 | * invalidate_domains gets CPU |
| 3110 | * wait_rendering (obj) to make sure all drawing is complete. |
| 3111 | * This will include an MI_FLUSH to get the data from GPU |
| 3112 | * to memory |
| 3113 | * clflush (obj) to invalidate the CPU cache |
| 3114 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 3115 | * 5. Read/written by CPU |
| 3116 | * cache lines are loaded and dirtied |
| 3117 | * 6. Read written by GPU |
| 3118 | * Same as last GPU access |
| 3119 | * |
| 3120 | * Case 3: The constant buffer |
| 3121 | * |
| 3122 | * 1. Allocated |
| 3123 | * 2. Written by CPU |
| 3124 | * 3. Read by GPU |
| 3125 | * 4. Updated (written) by CPU again |
| 3126 | * 5. Read by GPU |
| 3127 | * |
| 3128 | * 1. Allocated |
| 3129 | * (CPU, CPU) |
| 3130 | * 2. Written by CPU |
| 3131 | * (CPU, CPU) |
| 3132 | * 3. Read by GPU |
| 3133 | * (CPU+RENDER, 0) |
| 3134 | * flush_domains = CPU |
| 3135 | * invalidate_domains = RENDER |
| 3136 | * clflush (obj) |
| 3137 | * MI_FLUSH |
| 3138 | * drm_agp_chipset_flush |
| 3139 | * 4. Updated (written) by CPU again |
| 3140 | * (CPU, CPU) |
| 3141 | * flush_domains = 0 (no previous write domain) |
| 3142 | * invalidate_domains = 0 (no new read domains) |
| 3143 | * 5. Read by GPU |
| 3144 | * (CPU+RENDER, 0) |
| 3145 | * flush_domains = CPU |
| 3146 | * invalidate_domains = RENDER |
| 3147 | * clflush (obj) |
| 3148 | * MI_FLUSH |
| 3149 | * drm_agp_chipset_flush |
| 3150 | */ |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 3151 | static void |
Chris Wilson | b665145 | 2010-10-23 10:15:06 +0100 | [diff] [blame] | 3152 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, |
| 3153 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3154 | { |
| 3155 | struct drm_device *dev = obj->dev; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3156 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3157 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3158 | uint32_t invalidate_domains = 0; |
| 3159 | uint32_t flush_domains = 0; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3160 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3161 | /* |
| 3162 | * If the object isn't moving to a new write domain, |
| 3163 | * let the object stay in multiple read domains |
| 3164 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3165 | if (obj->pending_write_domain == 0) |
| 3166 | obj->pending_read_domains |= obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3167 | |
| 3168 | /* |
| 3169 | * Flush the current write domain if |
| 3170 | * the new read domains don't match. Invalidate |
| 3171 | * any read domains which differ from the old |
| 3172 | * write domain |
| 3173 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3174 | if (obj->write_domain && |
| 3175 | obj->write_domain != obj->pending_read_domains) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3176 | flush_domains |= obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3177 | invalidate_domains |= |
| 3178 | obj->pending_read_domains & ~obj->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3179 | } |
| 3180 | /* |
| 3181 | * Invalidate any read caches which may have |
| 3182 | * stale data. That is, any new read domains. |
| 3183 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3184 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
Chris Wilson | 3d2a812 | 2010-09-29 11:39:53 +0100 | [diff] [blame] | 3185 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3186 | i915_gem_clflush_object(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3187 | |
Chris Wilson | 4a684a4 | 2010-10-28 14:44:08 +0100 | [diff] [blame^] | 3188 | /* blow away mappings if mapped through GTT */ |
| 3189 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT) |
| 3190 | i915_gem_release_mmap(obj); |
| 3191 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3192 | /* The actual obj->write_domain will be updated with |
| 3193 | * pending_write_domain after we emit the accumulated flush for all |
| 3194 | * of our domain changes in execbuffers (which clears objects' |
| 3195 | * write_domains). So if we have a current write domain that we |
| 3196 | * aren't changing, set pending_write_domain to that. |
| 3197 | */ |
| 3198 | if (flush_domains == 0 && obj->pending_write_domain == 0) |
| 3199 | obj->pending_write_domain = obj->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3200 | |
| 3201 | dev->invalidate_domains |= invalidate_domains; |
| 3202 | dev->flush_domains |= flush_domains; |
Chris Wilson | b665145 | 2010-10-23 10:15:06 +0100 | [diff] [blame] | 3203 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3204 | dev_priv->mm.flush_rings |= obj_priv->ring->id; |
Chris Wilson | b665145 | 2010-10-23 10:15:06 +0100 | [diff] [blame] | 3205 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
| 3206 | dev_priv->mm.flush_rings |= ring->id; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3207 | } |
| 3208 | |
| 3209 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3210 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3211 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3212 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 3213 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 3214 | */ |
| 3215 | static void |
| 3216 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) |
| 3217 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3218 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3219 | |
| 3220 | if (!obj_priv->page_cpu_valid) |
| 3221 | return; |
| 3222 | |
| 3223 | /* If we're partially in the CPU read domain, finish moving it in. |
| 3224 | */ |
| 3225 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3226 | int i; |
| 3227 | |
| 3228 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { |
| 3229 | if (obj_priv->page_cpu_valid[i]) |
| 3230 | continue; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3231 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3232 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3233 | } |
| 3234 | |
| 3235 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 3236 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 3237 | */ |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3238 | kfree(obj_priv->page_cpu_valid); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3239 | obj_priv->page_cpu_valid = NULL; |
| 3240 | } |
| 3241 | |
| 3242 | /** |
| 3243 | * Set the CPU read domain on a range of the object. |
| 3244 | * |
| 3245 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 3246 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 3247 | * pages have been flushed, and will be respected by |
| 3248 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 3249 | * of the whole object. |
| 3250 | * |
| 3251 | * This function returns when the move is complete, including waiting on |
| 3252 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3253 | */ |
| 3254 | static int |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3255 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 3256 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3257 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3258 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3259 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3260 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3261 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3262 | if (offset == 0 && size == obj->size) |
| 3263 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 3264 | |
Daniel Vetter | ba3d8d7 | 2010-02-11 22:37:04 +0100 | [diff] [blame] | 3265 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3266 | if (ret != 0) |
| 3267 | return ret; |
| 3268 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3269 | |
| 3270 | /* If we're already fully in the CPU read domain, we're done. */ |
| 3271 | if (obj_priv->page_cpu_valid == NULL && |
| 3272 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3273 | return 0; |
| 3274 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3275 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 3276 | * newly adding I915_GEM_DOMAIN_CPU |
| 3277 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3278 | if (obj_priv->page_cpu_valid == NULL) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3279 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
| 3280 | GFP_KERNEL); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3281 | if (obj_priv->page_cpu_valid == NULL) |
| 3282 | return -ENOMEM; |
| 3283 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 3284 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3285 | |
| 3286 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 3287 | * perspective. |
| 3288 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3289 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 3290 | i++) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3291 | if (obj_priv->page_cpu_valid[i]) |
| 3292 | continue; |
| 3293 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3294 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3295 | |
| 3296 | obj_priv->page_cpu_valid[i] = 1; |
| 3297 | } |
| 3298 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3299 | /* It should now be out of any other write domains, and we can update |
| 3300 | * the domain values for our changes. |
| 3301 | */ |
| 3302 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 3303 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3304 | old_read_domains = obj->read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3305 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 3306 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3307 | trace_i915_gem_object_change_domain(obj, |
| 3308 | old_read_domains, |
| 3309 | obj->write_domain); |
| 3310 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3311 | return 0; |
| 3312 | } |
| 3313 | |
| 3314 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3315 | * Pin an object to the GTT and evaluate the relocations landing in it. |
| 3316 | */ |
| 3317 | static int |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3318 | i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj, |
| 3319 | struct drm_file *file_priv, |
| 3320 | struct drm_i915_gem_exec_object2 *entry) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3321 | { |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3322 | struct drm_device *dev = obj->base.dev; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3323 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3324 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3325 | struct drm_gem_object *target_obj = NULL; |
| 3326 | uint32_t target_handle = 0; |
| 3327 | int i, ret = 0; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3328 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3329 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3330 | for (i = 0; i < entry->relocation_count; i++) { |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3331 | struct drm_i915_gem_relocation_entry reloc; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3332 | uint32_t target_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3333 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3334 | if (__copy_from_user_inatomic(&reloc, |
| 3335 | user_relocs+i, |
| 3336 | sizeof(reloc))) { |
| 3337 | ret = -EFAULT; |
| 3338 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3339 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3340 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3341 | if (reloc.target_handle != target_handle) { |
| 3342 | drm_gem_object_unreference(target_obj); |
| 3343 | |
| 3344 | target_obj = drm_gem_object_lookup(dev, file_priv, |
| 3345 | reloc.target_handle); |
| 3346 | if (target_obj == NULL) { |
| 3347 | ret = -ENOENT; |
| 3348 | break; |
| 3349 | } |
| 3350 | |
| 3351 | target_handle = reloc.target_handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3352 | } |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3353 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3354 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3355 | #if WATCH_RELOC |
| 3356 | DRM_INFO("%s: obj %p offset %08x target %d " |
| 3357 | "read %08x write %08x gtt %08x " |
| 3358 | "presumed %08x delta %08x\n", |
| 3359 | __func__, |
| 3360 | obj, |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3361 | (int) reloc.offset, |
| 3362 | (int) reloc.target_handle, |
| 3363 | (int) reloc.read_domains, |
| 3364 | (int) reloc.write_domain, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3365 | (int) target_offset, |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3366 | (int) reloc.presumed_offset, |
| 3367 | reloc.delta); |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3368 | #endif |
| 3369 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3370 | /* The target buffer should have appeared before us in the |
| 3371 | * exec_object list, so it should have a GTT space bound by now. |
| 3372 | */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3373 | if (target_offset == 0) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3374 | DRM_ERROR("No GTT space found for object %d\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3375 | reloc.target_handle); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3376 | ret = -EINVAL; |
| 3377 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3378 | } |
| 3379 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3380 | /* Validate that the target is in a valid r/w GPU domain */ |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3381 | if (reloc.write_domain & (reloc.write_domain - 1)) { |
Daniel Vetter | 16edd55 | 2010-02-19 11:52:02 +0100 | [diff] [blame] | 3382 | DRM_ERROR("reloc with multiple write domains: " |
| 3383 | "obj %p target %d offset %d " |
| 3384 | "read %08x write %08x", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3385 | obj, reloc.target_handle, |
| 3386 | (int) reloc.offset, |
| 3387 | reloc.read_domains, |
| 3388 | reloc.write_domain); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3389 | ret = -EINVAL; |
| 3390 | break; |
Daniel Vetter | 16edd55 | 2010-02-19 11:52:02 +0100 | [diff] [blame] | 3391 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3392 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
| 3393 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3394 | DRM_ERROR("reloc with read/write CPU domains: " |
| 3395 | "obj %p target %d offset %d " |
| 3396 | "read %08x write %08x", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3397 | obj, reloc.target_handle, |
| 3398 | (int) reloc.offset, |
| 3399 | reloc.read_domains, |
| 3400 | reloc.write_domain); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3401 | ret = -EINVAL; |
| 3402 | break; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3403 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3404 | if (reloc.write_domain && target_obj->pending_write_domain && |
| 3405 | reloc.write_domain != target_obj->pending_write_domain) { |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3406 | DRM_ERROR("Write domain conflict: " |
| 3407 | "obj %p target %d offset %d " |
| 3408 | "new %08x old %08x\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3409 | obj, reloc.target_handle, |
| 3410 | (int) reloc.offset, |
| 3411 | reloc.write_domain, |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3412 | target_obj->pending_write_domain); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3413 | ret = -EINVAL; |
| 3414 | break; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3415 | } |
| 3416 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3417 | target_obj->pending_read_domains |= reloc.read_domains; |
Chris Wilson | 878a3c3 | 2010-10-22 10:48:12 +0100 | [diff] [blame] | 3418 | target_obj->pending_write_domain |= reloc.write_domain; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3419 | |
| 3420 | /* If the relocation already has the right value in it, no |
| 3421 | * more work needs to be done. |
| 3422 | */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3423 | if (target_offset == reloc.presumed_offset) |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3424 | continue; |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3425 | |
| 3426 | /* Check that the relocation address is valid... */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3427 | if (reloc.offset > obj->base.size - 4) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3428 | DRM_ERROR("Relocation beyond object bounds: " |
| 3429 | "obj %p target %d offset %d size %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3430 | obj, reloc.target_handle, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3431 | (int) reloc.offset, (int) obj->base.size); |
| 3432 | ret = -EINVAL; |
| 3433 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3434 | } |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3435 | if (reloc.offset & 3) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3436 | DRM_ERROR("Relocation not 4-byte aligned: " |
| 3437 | "obj %p target %d offset %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3438 | obj, reloc.target_handle, |
| 3439 | (int) reloc.offset); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3440 | ret = -EINVAL; |
| 3441 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3442 | } |
| 3443 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3444 | /* and points to somewhere within the target object. */ |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3445 | if (reloc.delta >= target_obj->size) { |
Chris Wilson | cd0b9fb | 2009-09-15 23:23:18 +0100 | [diff] [blame] | 3446 | DRM_ERROR("Relocation beyond target object bounds: " |
| 3447 | "obj %p target %d delta %d size %d.\n", |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3448 | obj, reloc.target_handle, |
| 3449 | (int) reloc.delta, (int) target_obj->size); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3450 | ret = -EINVAL; |
| 3451 | break; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3452 | } |
| 3453 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3454 | reloc.delta += target_offset; |
| 3455 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3456 | uint32_t page_offset = reloc.offset & ~PAGE_MASK; |
| 3457 | char *vaddr; |
| 3458 | |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 3459 | vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]); |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3460 | *(uint32_t *)(vaddr + page_offset) = reloc.delta; |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 3461 | kunmap_atomic(vaddr); |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3462 | } else { |
| 3463 | uint32_t __iomem *reloc_entry; |
| 3464 | void __iomem *reloc_page; |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3465 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3466 | ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1); |
| 3467 | if (ret) |
| 3468 | break; |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3469 | |
| 3470 | /* Map the page containing the relocation we're going to perform. */ |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3471 | reloc.offset += obj->gtt_offset; |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3472 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 3473 | reloc.offset & PAGE_MASK); |
Chris Wilson | f0c43d9 | 2010-10-14 12:44:48 +0100 | [diff] [blame] | 3474 | reloc_entry = (uint32_t __iomem *) |
| 3475 | (reloc_page + (reloc.offset & ~PAGE_MASK)); |
| 3476 | iowrite32(reloc.delta, reloc_entry); |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 3477 | io_mapping_unmap_atomic(reloc_page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3478 | } |
| 3479 | |
Chris Wilson | b5dc608 | 2010-10-20 20:59:57 +0100 | [diff] [blame] | 3480 | /* and update the user's relocation entry */ |
| 3481 | reloc.presumed_offset = target_offset; |
| 3482 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, |
| 3483 | &reloc.presumed_offset, |
| 3484 | sizeof(reloc.presumed_offset))) { |
| 3485 | ret = -EFAULT; |
| 3486 | break; |
| 3487 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3488 | } |
| 3489 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3490 | drm_gem_object_unreference(target_obj); |
| 3491 | return ret; |
| 3492 | } |
| 3493 | |
| 3494 | static int |
| 3495 | i915_gem_execbuffer_pin(struct drm_device *dev, |
| 3496 | struct drm_file *file, |
| 3497 | struct drm_gem_object **object_list, |
| 3498 | struct drm_i915_gem_exec_object2 *exec_list, |
| 3499 | int count) |
| 3500 | { |
| 3501 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3502 | int ret, i, retry; |
| 3503 | |
| 3504 | /* attempt to pin all of the buffers into the GTT */ |
| 3505 | for (retry = 0; retry < 2; retry++) { |
| 3506 | ret = 0; |
| 3507 | for (i = 0; i < count; i++) { |
| 3508 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 3509 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3510 | bool need_fence = |
| 3511 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3512 | obj->tiling_mode != I915_TILING_NONE; |
| 3513 | |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 3514 | /* g33/pnv can't fence buffers in the unmappable part */ |
| 3515 | bool need_mappable = |
| 3516 | entry->relocation_count ? true : need_fence; |
| 3517 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3518 | /* Check fence reg constraints and rebind if necessary */ |
| 3519 | if (need_fence && |
| 3520 | !i915_gem_object_fence_offset_ok(&obj->base, |
| 3521 | obj->tiling_mode)) { |
| 3522 | ret = i915_gem_object_unbind(&obj->base); |
| 3523 | if (ret) |
| 3524 | break; |
| 3525 | } |
| 3526 | |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 3527 | ret = i915_gem_object_pin(&obj->base, |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 3528 | entry->alignment, |
| 3529 | need_mappable); |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3530 | if (ret) |
| 3531 | break; |
| 3532 | |
| 3533 | /* |
| 3534 | * Pre-965 chips need a fence register set up in order |
| 3535 | * to properly handle blits to/from tiled surfaces. |
| 3536 | */ |
| 3537 | if (need_fence) { |
| 3538 | ret = i915_gem_object_get_fence_reg(&obj->base, true); |
| 3539 | if (ret) { |
| 3540 | i915_gem_object_unpin(&obj->base); |
| 3541 | break; |
| 3542 | } |
| 3543 | |
| 3544 | dev_priv->fence_regs[obj->fence_reg].gpu = true; |
| 3545 | } |
| 3546 | |
| 3547 | entry->offset = obj->gtt_offset; |
| 3548 | } |
| 3549 | |
| 3550 | while (i--) |
| 3551 | i915_gem_object_unpin(object_list[i]); |
| 3552 | |
| 3553 | if (ret == 0) |
| 3554 | break; |
| 3555 | |
| 3556 | if (ret != -ENOSPC || retry) |
| 3557 | return ret; |
| 3558 | |
| 3559 | ret = i915_gem_evict_everything(dev); |
| 3560 | if (ret) |
| 3561 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3562 | } |
| 3563 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3564 | return 0; |
| 3565 | } |
| 3566 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3567 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3568 | * emitted over 20 msec ago. |
| 3569 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3570 | * Note that if we were to use the current jiffies each time around the loop, |
| 3571 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3572 | * render a frame was over 20ms. |
| 3573 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3574 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3575 | * relatively low latency when blocking on a particular request to finish. |
| 3576 | */ |
| 3577 | static int |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3578 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3579 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3580 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3581 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3582 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3583 | struct drm_i915_gem_request *request; |
| 3584 | struct intel_ring_buffer *ring = NULL; |
| 3585 | u32 seqno = 0; |
| 3586 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3587 | |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3588 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3589 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3590 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3591 | break; |
| 3592 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3593 | ring = request->ring; |
| 3594 | seqno = request->seqno; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3595 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 3596 | spin_unlock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3597 | |
| 3598 | if (seqno == 0) |
| 3599 | return 0; |
| 3600 | |
| 3601 | ret = 0; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3602 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3603 | /* And wait for the seqno passing without holding any locks and |
| 3604 | * causing extra latency for others. This is safe as the irq |
| 3605 | * generation is designed to be run atomically and so is |
| 3606 | * lockless. |
| 3607 | */ |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3608 | ring->user_irq_get(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3609 | ret = wait_event_interruptible(ring->irq_queue, |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3610 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3611 | || atomic_read(&dev_priv->mm.wedged)); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3612 | ring->user_irq_put(ring); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 3613 | |
| 3614 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
| 3615 | ret = -EIO; |
| 3616 | } |
| 3617 | |
| 3618 | if (ret == 0) |
| 3619 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3620 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3621 | return ret; |
| 3622 | } |
| 3623 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3624 | static int |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3625 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
| 3626 | uint64_t exec_offset) |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3627 | { |
| 3628 | uint32_t exec_start, exec_len; |
| 3629 | |
| 3630 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3631 | exec_len = (uint32_t) exec->batch_len; |
| 3632 | |
| 3633 | if ((exec_start | exec_len) & 0x7) |
| 3634 | return -EINVAL; |
| 3635 | |
| 3636 | if (!exec_start) |
| 3637 | return -EINVAL; |
| 3638 | |
| 3639 | return 0; |
| 3640 | } |
| 3641 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3642 | static int |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3643 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
| 3644 | int count) |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3645 | { |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3646 | int i; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3647 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3648 | for (i = 0; i < count; i++) { |
| 3649 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; |
| 3650 | size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3651 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3652 | if (!access_ok(VERIFY_READ, ptr, length)) |
| 3653 | return -EFAULT; |
| 3654 | |
Chris Wilson | b5dc608 | 2010-10-20 20:59:57 +0100 | [diff] [blame] | 3655 | /* we may also need to update the presumed offsets */ |
| 3656 | if (!access_ok(VERIFY_WRITE, ptr, length)) |
| 3657 | return -EFAULT; |
| 3658 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3659 | if (fault_in_pages_readable(ptr, length)) |
| 3660 | return -EFAULT; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3661 | } |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3662 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3663 | return 0; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3664 | } |
| 3665 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3666 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3667 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3668 | struct drm_file *file, |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3669 | struct drm_i915_gem_execbuffer2 *args, |
| 3670 | struct drm_i915_gem_exec_object2 *exec_list) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3671 | { |
| 3672 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3673 | struct drm_gem_object **object_list = NULL; |
| 3674 | struct drm_gem_object *batch_obj; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3675 | struct drm_clip_rect *cliprects = NULL; |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3676 | struct drm_i915_gem_request *request = NULL; |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3677 | int ret, i, flips; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3678 | uint64_t exec_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3679 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3680 | struct intel_ring_buffer *ring = NULL; |
| 3681 | |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 3682 | ret = i915_gem_check_is_wedged(dev); |
| 3683 | if (ret) |
| 3684 | return ret; |
| 3685 | |
Chris Wilson | 2549d6c | 2010-10-14 12:10:41 +0100 | [diff] [blame] | 3686 | ret = validate_exec_list(exec_list, args->buffer_count); |
| 3687 | if (ret) |
| 3688 | return ret; |
| 3689 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3690 | #if WATCH_EXEC |
| 3691 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3692 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3693 | #endif |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3694 | switch (args->flags & I915_EXEC_RING_MASK) { |
| 3695 | case I915_EXEC_DEFAULT: |
| 3696 | case I915_EXEC_RENDER: |
| 3697 | ring = &dev_priv->render_ring; |
| 3698 | break; |
| 3699 | case I915_EXEC_BSD: |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3700 | if (!HAS_BSD(dev)) { |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3701 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3702 | return -EINVAL; |
| 3703 | } |
| 3704 | ring = &dev_priv->bsd_ring; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 3705 | break; |
| 3706 | case I915_EXEC_BLT: |
| 3707 | if (!HAS_BLT(dev)) { |
| 3708 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); |
| 3709 | return -EINVAL; |
| 3710 | } |
| 3711 | ring = &dev_priv->blt_ring; |
| 3712 | break; |
| 3713 | default: |
| 3714 | DRM_ERROR("execbuf with unknown ring: %d\n", |
| 3715 | (int)(args->flags & I915_EXEC_RING_MASK)); |
| 3716 | return -EINVAL; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3717 | } |
| 3718 | |
Eric Anholt | 4f481ed | 2008-09-10 14:22:49 -0700 | [diff] [blame] | 3719 | if (args->buffer_count < 1) { |
| 3720 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3721 | return -EINVAL; |
| 3722 | } |
Eric Anholt | c8e0f93 | 2009-11-22 03:49:37 +0100 | [diff] [blame] | 3723 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3724 | if (object_list == NULL) { |
| 3725 | DRM_ERROR("Failed to allocate object list for %d buffers\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3726 | args->buffer_count); |
| 3727 | ret = -ENOMEM; |
| 3728 | goto pre_mutex_err; |
| 3729 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3730 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3731 | if (args->num_cliprects != 0) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3732 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
| 3733 | GFP_KERNEL); |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3734 | if (cliprects == NULL) { |
| 3735 | ret = -ENOMEM; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3736 | goto pre_mutex_err; |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3737 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3738 | |
| 3739 | ret = copy_from_user(cliprects, |
| 3740 | (struct drm_clip_rect __user *) |
| 3741 | (uintptr_t) args->cliprects_ptr, |
| 3742 | sizeof(*cliprects) * args->num_cliprects); |
| 3743 | if (ret != 0) { |
| 3744 | DRM_ERROR("copy %d cliprects failed: %d\n", |
| 3745 | args->num_cliprects, ret); |
Dan Carpenter | c877cdc | 2010-06-23 19:03:01 +0200 | [diff] [blame] | 3746 | ret = -EFAULT; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3747 | goto pre_mutex_err; |
| 3748 | } |
| 3749 | } |
| 3750 | |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3751 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
| 3752 | if (request == NULL) { |
| 3753 | ret = -ENOMEM; |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3754 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3755 | } |
| 3756 | |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 3757 | ret = i915_mutex_lock_interruptible(dev); |
| 3758 | if (ret) |
| 3759 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3760 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3761 | if (dev_priv->mm.suspended) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3762 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3763 | ret = -EBUSY; |
| 3764 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3765 | } |
| 3766 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3767 | /* Look up object handles */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3768 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 3769 | struct drm_i915_gem_object *obj_priv; |
| 3770 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3771 | object_list[i] = drm_gem_object_lookup(dev, file, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3772 | exec_list[i].handle); |
| 3773 | if (object_list[i] == NULL) { |
| 3774 | DRM_ERROR("Invalid object handle %d at index %d\n", |
| 3775 | exec_list[i].handle, i); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3776 | /* prevent error path from reading uninitialized data */ |
| 3777 | args->buffer_count = i + 1; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 3778 | ret = -ENOENT; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3779 | goto err; |
| 3780 | } |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3781 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3782 | obj_priv = to_intel_bo(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3783 | if (obj_priv->in_execbuffer) { |
| 3784 | DRM_ERROR("Object %p appears more than once in object list\n", |
| 3785 | object_list[i]); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3786 | /* prevent error path from reading uninitialized data */ |
| 3787 | args->buffer_count = i + 1; |
Chris Wilson | bf79cb9 | 2010-08-04 14:19:46 +0100 | [diff] [blame] | 3788 | ret = -EINVAL; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3789 | goto err; |
| 3790 | } |
| 3791 | obj_priv->in_execbuffer = true; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3792 | } |
| 3793 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3794 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
| 3795 | ret = i915_gem_execbuffer_pin(dev, file, |
| 3796 | object_list, exec_list, |
| 3797 | args->buffer_count); |
| 3798 | if (ret) |
| 3799 | goto err; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3800 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3801 | /* The objects are in their final locations, apply the relocations. */ |
| 3802 | for (i = 0; i < args->buffer_count; i++) { |
| 3803 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); |
| 3804 | obj->base.pending_read_domains = 0; |
| 3805 | obj->base.pending_write_domain = 0; |
| 3806 | ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3807 | if (ret) |
| 3808 | goto err; |
| 3809 | } |
| 3810 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3811 | /* Set the pending read domains for the batch buffer to COMMAND */ |
| 3812 | batch_obj = object_list[args->buffer_count-1]; |
Chris Wilson | 5f26a2c | 2009-06-06 09:45:58 +0100 | [diff] [blame] | 3813 | if (batch_obj->pending_write_domain) { |
| 3814 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); |
| 3815 | ret = -EINVAL; |
| 3816 | goto err; |
| 3817 | } |
| 3818 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3819 | |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3820 | /* Sanity check the batch buffer */ |
| 3821 | exec_offset = to_intel_bo(batch_obj)->gtt_offset; |
| 3822 | ret = i915_gem_check_execbuffer(args, exec_offset); |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3823 | if (ret != 0) { |
| 3824 | DRM_ERROR("execbuf with invalid offset/length\n"); |
| 3825 | goto err; |
| 3826 | } |
| 3827 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3828 | /* Zero the global flush/invalidate flags. These |
| 3829 | * will be modified as new domains are computed |
| 3830 | * for each object |
| 3831 | */ |
| 3832 | dev->invalidate_domains = 0; |
| 3833 | dev->flush_domains = 0; |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3834 | dev_priv->mm.flush_rings = 0; |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 3835 | for (i = 0; i < args->buffer_count; i++) |
| 3836 | i915_gem_object_set_to_gpu_domain(object_list[i], ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3837 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3838 | if (dev->invalidate_domains | dev->flush_domains) { |
| 3839 | #if WATCH_EXEC |
| 3840 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", |
| 3841 | __func__, |
| 3842 | dev->invalidate_domains, |
| 3843 | dev->flush_domains); |
| 3844 | #endif |
Chris Wilson | 9af90d1 | 2010-10-17 10:01:56 +0100 | [diff] [blame] | 3845 | i915_gem_flush(dev, file, |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3846 | dev->invalidate_domains, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 3847 | dev->flush_domains, |
| 3848 | dev_priv->mm.flush_rings); |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3849 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3850 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3851 | #if WATCH_COHERENCY |
| 3852 | for (i = 0; i < args->buffer_count; i++) { |
| 3853 | i915_gem_object_check_coherency(object_list[i], |
| 3854 | exec_list[i].handle); |
| 3855 | } |
| 3856 | #endif |
| 3857 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3858 | #if WATCH_EXEC |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 3859 | i915_gem_dump_object(batch_obj, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3860 | args->batch_len, |
| 3861 | __func__, |
| 3862 | ~0); |
| 3863 | #endif |
| 3864 | |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 3865 | /* Check for any pending flips. As we only maintain a flip queue depth |
| 3866 | * of 1, we can simply insert a WAIT for the next display flip prior |
| 3867 | * to executing the batch and avoid stalling the CPU. |
| 3868 | */ |
| 3869 | flips = 0; |
| 3870 | for (i = 0; i < args->buffer_count; i++) { |
| 3871 | if (object_list[i]->write_domain) |
| 3872 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); |
| 3873 | } |
| 3874 | if (flips) { |
| 3875 | int plane, flip_mask; |
| 3876 | |
| 3877 | for (plane = 0; flips >> plane; plane++) { |
| 3878 | if (((flips >> plane) & 1) == 0) |
| 3879 | continue; |
| 3880 | |
| 3881 | if (plane) |
| 3882 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; |
| 3883 | else |
| 3884 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; |
| 3885 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 3886 | ret = intel_ring_begin(ring, 2); |
| 3887 | if (ret) |
| 3888 | goto err; |
| 3889 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3890 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
| 3891 | intel_ring_emit(ring, MI_NOOP); |
| 3892 | intel_ring_advance(ring); |
Chris Wilson | e59f2ba | 2010-10-07 17:28:15 +0100 | [diff] [blame] | 3893 | } |
| 3894 | } |
| 3895 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3896 | /* Exec the batchbuffer */ |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 3897 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3898 | if (ret) { |
| 3899 | DRM_ERROR("dispatch failed %d\n", ret); |
| 3900 | goto err; |
| 3901 | } |
| 3902 | |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 3903 | for (i = 0; i < args->buffer_count; i++) { |
| 3904 | struct drm_gem_object *obj = object_list[i]; |
| 3905 | |
| 3906 | obj->read_domains = obj->pending_read_domains; |
| 3907 | obj->write_domain = obj->pending_write_domain; |
| 3908 | |
| 3909 | i915_gem_object_move_to_active(obj, ring); |
| 3910 | if (obj->write_domain) { |
| 3911 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
| 3912 | obj_priv->dirty = 1; |
| 3913 | list_move_tail(&obj_priv->gpu_write_list, |
| 3914 | &ring->gpu_write_list); |
| 3915 | intel_mark_busy(dev, obj); |
| 3916 | } |
| 3917 | |
| 3918 | trace_i915_gem_object_change_domain(obj, |
| 3919 | obj->read_domains, |
| 3920 | obj->write_domain); |
| 3921 | } |
| 3922 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3923 | /* |
| 3924 | * Ensure that the commands in the batch buffer are |
| 3925 | * finished before the interrupt fires |
| 3926 | */ |
Daniel Vetter | 8a1a49f | 2010-02-11 22:29:04 +0100 | [diff] [blame] | 3927 | i915_retire_commands(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3928 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 3929 | if (i915_add_request(dev, file, request, ring)) |
| 3930 | ring->outstanding_lazy_request = true; |
| 3931 | else |
| 3932 | request = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3933 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3934 | err: |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3935 | for (i = 0; i < args->buffer_count; i++) { |
Chris Wilson | 7e318e1 | 2010-10-27 13:43:39 +0100 | [diff] [blame] | 3936 | if (object_list[i] == NULL) |
| 3937 | break; |
| 3938 | |
| 3939 | to_intel_bo(object_list[i])->in_execbuffer = false; |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3940 | drm_gem_object_unreference(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3941 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3942 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3943 | mutex_unlock(&dev->struct_mutex); |
| 3944 | |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 3945 | pre_mutex_err: |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3946 | drm_free_large(object_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3947 | kfree(cliprects); |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 3948 | kfree(request); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3949 | |
| 3950 | return ret; |
| 3951 | } |
| 3952 | |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3953 | /* |
| 3954 | * Legacy execbuffer just creates an exec2 list from the original exec object |
| 3955 | * list array and passes it to the real function. |
| 3956 | */ |
| 3957 | int |
| 3958 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 3959 | struct drm_file *file_priv) |
| 3960 | { |
| 3961 | struct drm_i915_gem_execbuffer *args = data; |
| 3962 | struct drm_i915_gem_execbuffer2 exec2; |
| 3963 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 3964 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 3965 | int ret, i; |
| 3966 | |
| 3967 | #if WATCH_EXEC |
| 3968 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3969 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3970 | #endif |
| 3971 | |
| 3972 | if (args->buffer_count < 1) { |
| 3973 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3974 | return -EINVAL; |
| 3975 | } |
| 3976 | |
| 3977 | /* Copy in the exec list from userland */ |
| 3978 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); |
| 3979 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 3980 | if (exec_list == NULL || exec2_list == NULL) { |
| 3981 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 3982 | args->buffer_count); |
| 3983 | drm_free_large(exec_list); |
| 3984 | drm_free_large(exec2_list); |
| 3985 | return -ENOMEM; |
| 3986 | } |
| 3987 | ret = copy_from_user(exec_list, |
| 3988 | (struct drm_i915_relocation_entry __user *) |
| 3989 | (uintptr_t) args->buffers_ptr, |
| 3990 | sizeof(*exec_list) * args->buffer_count); |
| 3991 | if (ret != 0) { |
| 3992 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 3993 | args->buffer_count, ret); |
| 3994 | drm_free_large(exec_list); |
| 3995 | drm_free_large(exec2_list); |
| 3996 | return -EFAULT; |
| 3997 | } |
| 3998 | |
| 3999 | for (i = 0; i < args->buffer_count; i++) { |
| 4000 | exec2_list[i].handle = exec_list[i].handle; |
| 4001 | exec2_list[i].relocation_count = exec_list[i].relocation_count; |
| 4002 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; |
| 4003 | exec2_list[i].alignment = exec_list[i].alignment; |
| 4004 | exec2_list[i].offset = exec_list[i].offset; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4005 | if (INTEL_INFO(dev)->gen < 4) |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4006 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
| 4007 | else |
| 4008 | exec2_list[i].flags = 0; |
| 4009 | } |
| 4010 | |
| 4011 | exec2.buffers_ptr = args->buffers_ptr; |
| 4012 | exec2.buffer_count = args->buffer_count; |
| 4013 | exec2.batch_start_offset = args->batch_start_offset; |
| 4014 | exec2.batch_len = args->batch_len; |
| 4015 | exec2.DR1 = args->DR1; |
| 4016 | exec2.DR4 = args->DR4; |
| 4017 | exec2.num_cliprects = args->num_cliprects; |
| 4018 | exec2.cliprects_ptr = args->cliprects_ptr; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4019 | exec2.flags = I915_EXEC_RENDER; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4020 | |
| 4021 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); |
| 4022 | if (!ret) { |
| 4023 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4024 | for (i = 0; i < args->buffer_count; i++) |
| 4025 | exec_list[i].offset = exec2_list[i].offset; |
| 4026 | /* ... and back out to userspace */ |
| 4027 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4028 | (uintptr_t) args->buffers_ptr, |
| 4029 | exec_list, |
| 4030 | sizeof(*exec_list) * args->buffer_count); |
| 4031 | if (ret) { |
| 4032 | ret = -EFAULT; |
| 4033 | DRM_ERROR("failed to copy %d exec entries " |
| 4034 | "back to user (%d)\n", |
| 4035 | args->buffer_count, ret); |
| 4036 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4037 | } |
| 4038 | |
| 4039 | drm_free_large(exec_list); |
| 4040 | drm_free_large(exec2_list); |
| 4041 | return ret; |
| 4042 | } |
| 4043 | |
| 4044 | int |
| 4045 | i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 4046 | struct drm_file *file_priv) |
| 4047 | { |
| 4048 | struct drm_i915_gem_execbuffer2 *args = data; |
| 4049 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 4050 | int ret; |
| 4051 | |
| 4052 | #if WATCH_EXEC |
| 4053 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 4054 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 4055 | #endif |
| 4056 | |
| 4057 | if (args->buffer_count < 1) { |
| 4058 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); |
| 4059 | return -EINVAL; |
| 4060 | } |
| 4061 | |
| 4062 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 4063 | if (exec2_list == NULL) { |
| 4064 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 4065 | args->buffer_count); |
| 4066 | return -ENOMEM; |
| 4067 | } |
| 4068 | ret = copy_from_user(exec2_list, |
| 4069 | (struct drm_i915_relocation_entry __user *) |
| 4070 | (uintptr_t) args->buffers_ptr, |
| 4071 | sizeof(*exec2_list) * args->buffer_count); |
| 4072 | if (ret != 0) { |
| 4073 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 4074 | args->buffer_count, ret); |
| 4075 | drm_free_large(exec2_list); |
| 4076 | return -EFAULT; |
| 4077 | } |
| 4078 | |
| 4079 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); |
| 4080 | if (!ret) { |
| 4081 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4082 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4083 | (uintptr_t) args->buffers_ptr, |
| 4084 | exec2_list, |
| 4085 | sizeof(*exec2_list) * args->buffer_count); |
| 4086 | if (ret) { |
| 4087 | ret = -EFAULT; |
| 4088 | DRM_ERROR("failed to copy %d exec entries " |
| 4089 | "back to user (%d)\n", |
| 4090 | args->buffer_count, ret); |
| 4091 | } |
| 4092 | } |
| 4093 | |
| 4094 | drm_free_large(exec2_list); |
| 4095 | return ret; |
| 4096 | } |
| 4097 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4098 | int |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 4099 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment, |
| 4100 | bool mappable) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4101 | { |
| 4102 | struct drm_device *dev = obj->dev; |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4103 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4104 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4105 | int ret; |
| 4106 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 4107 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4108 | WARN_ON(i915_verify_lists(dev)); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4109 | |
| 4110 | if (obj_priv->gtt_space != NULL) { |
| 4111 | if (alignment == 0) |
| 4112 | alignment = i915_gem_get_gtt_alignment(obj); |
Daniel Vetter | 16e809a | 2010-09-16 19:37:04 +0200 | [diff] [blame] | 4113 | if (obj_priv->gtt_offset & (alignment - 1) || |
| 4114 | (mappable && !i915_gem_object_cpu_accessible(obj_priv))) { |
Chris Wilson | ae7d49d | 2010-08-04 12:37:41 +0100 | [diff] [blame] | 4115 | WARN(obj_priv->pin_count, |
| 4116 | "bo is already pinned with incorrect alignment:" |
| 4117 | " offset=%x, req.alignment=%x\n", |
| 4118 | obj_priv->gtt_offset, alignment); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4119 | ret = i915_gem_object_unbind(obj); |
| 4120 | if (ret) |
| 4121 | return ret; |
| 4122 | } |
| 4123 | } |
| 4124 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4125 | if (obj_priv->gtt_space == NULL) { |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 4126 | ret = i915_gem_object_bind_to_gtt(obj, alignment, mappable); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 4127 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4128 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 4129 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4130 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4131 | obj_priv->pin_count++; |
| 4132 | |
| 4133 | /* If the object is not active and not pending a flush, |
| 4134 | * remove it from the inactive list |
| 4135 | */ |
| 4136 | if (obj_priv->pin_count == 1) { |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 4137 | i915_gem_info_add_pin(dev_priv, obj, mappable); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4138 | if (!obj_priv->active) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4139 | list_move_tail(&obj_priv->mm_list, |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4140 | &dev_priv->mm.pinned_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4141 | } |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 4142 | BUG_ON(!obj_priv->pin_mappable && mappable); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4143 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4144 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4145 | return 0; |
| 4146 | } |
| 4147 | |
| 4148 | void |
| 4149 | i915_gem_object_unpin(struct drm_gem_object *obj) |
| 4150 | { |
| 4151 | struct drm_device *dev = obj->dev; |
| 4152 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4153 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4154 | |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4155 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4156 | obj_priv->pin_count--; |
| 4157 | BUG_ON(obj_priv->pin_count < 0); |
| 4158 | BUG_ON(obj_priv->gtt_space == NULL); |
| 4159 | |
| 4160 | /* If the object is no longer pinned, and is |
| 4161 | * neither active nor being flushed, then stick it on |
| 4162 | * the inactive list |
| 4163 | */ |
| 4164 | if (obj_priv->pin_count == 0) { |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4165 | if (!obj_priv->active) |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4166 | list_move_tail(&obj_priv->mm_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4167 | &dev_priv->mm.inactive_list); |
Daniel Vetter | fb7d516 | 2010-10-01 22:05:20 +0200 | [diff] [blame] | 4168 | i915_gem_info_remove_pin(dev_priv, obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4169 | } |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 4170 | WARN_ON(i915_verify_lists(dev)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4171 | } |
| 4172 | |
| 4173 | int |
| 4174 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 4175 | struct drm_file *file_priv) |
| 4176 | { |
| 4177 | struct drm_i915_gem_pin *args = data; |
| 4178 | struct drm_gem_object *obj; |
| 4179 | struct drm_i915_gem_object *obj_priv; |
| 4180 | int ret; |
| 4181 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4182 | ret = i915_mutex_lock_interruptible(dev); |
| 4183 | if (ret) |
| 4184 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4185 | |
| 4186 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4187 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4188 | ret = -ENOENT; |
| 4189 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4190 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4191 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4192 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4193 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 4194 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4195 | ret = -EINVAL; |
| 4196 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4197 | } |
| 4198 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4199 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
| 4200 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 4201 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4202 | ret = -EINVAL; |
| 4203 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4204 | } |
| 4205 | |
| 4206 | obj_priv->user_pin_count++; |
| 4207 | obj_priv->pin_filp = file_priv; |
| 4208 | if (obj_priv->user_pin_count == 1) { |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 4209 | ret = i915_gem_object_pin(obj, args->alignment, true); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4210 | if (ret) |
| 4211 | goto out; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4212 | } |
| 4213 | |
| 4214 | /* XXX - flush the CPU caches for pinned objects |
| 4215 | * as the X server doesn't manage domains yet |
| 4216 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4217 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4218 | args->offset = obj_priv->gtt_offset; |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4219 | out: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4220 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4221 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4222 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4223 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4224 | } |
| 4225 | |
| 4226 | int |
| 4227 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 4228 | struct drm_file *file_priv) |
| 4229 | { |
| 4230 | struct drm_i915_gem_pin *args = data; |
| 4231 | struct drm_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4232 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4233 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4234 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4235 | ret = i915_mutex_lock_interruptible(dev); |
| 4236 | if (ret) |
| 4237 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4238 | |
| 4239 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4240 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4241 | ret = -ENOENT; |
| 4242 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4243 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4244 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4245 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4246 | if (obj_priv->pin_filp != file_priv) { |
| 4247 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 4248 | args->handle); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4249 | ret = -EINVAL; |
| 4250 | goto out; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4251 | } |
| 4252 | obj_priv->user_pin_count--; |
| 4253 | if (obj_priv->user_pin_count == 0) { |
| 4254 | obj_priv->pin_filp = NULL; |
| 4255 | i915_gem_object_unpin(obj); |
| 4256 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4257 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4258 | out: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4259 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4260 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4261 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4262 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4263 | } |
| 4264 | |
| 4265 | int |
| 4266 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 4267 | struct drm_file *file_priv) |
| 4268 | { |
| 4269 | struct drm_i915_gem_busy *args = data; |
| 4270 | struct drm_gem_object *obj; |
| 4271 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4272 | int ret; |
| 4273 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4274 | ret = i915_mutex_lock_interruptible(dev); |
| 4275 | if (ret) |
| 4276 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4277 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4278 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4279 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4280 | ret = -ENOENT; |
| 4281 | goto unlock; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4282 | } |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4283 | obj_priv = to_intel_bo(obj); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4284 | |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4285 | /* Count all active objects as busy, even if they are currently not used |
| 4286 | * by the gpu. Users of this interface expect objects to eventually |
| 4287 | * become non-busy without any further actions, therefore emit any |
| 4288 | * necessary flushes here. |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4289 | */ |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4290 | args->busy = obj_priv->active; |
| 4291 | if (args->busy) { |
| 4292 | /* Unconditionally flush objects, even when the gpu still uses this |
| 4293 | * object. Userspace calling this function indicates that it wants to |
| 4294 | * use this buffer rather sooner than later, so issuing the required |
| 4295 | * flush earlier is beneficial. |
| 4296 | */ |
Chris Wilson | c78ec30 | 2010-09-20 12:50:23 +0100 | [diff] [blame] | 4297 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
| 4298 | i915_gem_flush_ring(dev, file_priv, |
Chris Wilson | 9220434 | 2010-09-18 11:02:01 +0100 | [diff] [blame] | 4299 | obj_priv->ring, |
| 4300 | 0, obj->write_domain); |
Chris Wilson | 0be555b | 2010-08-04 15:36:30 +0100 | [diff] [blame] | 4301 | |
| 4302 | /* Update the active list for the hardware's current position. |
| 4303 | * Otherwise this only updates on a delayed timer or when irqs |
| 4304 | * are actually unmasked, and our working set ends up being |
| 4305 | * larger than required. |
| 4306 | */ |
| 4307 | i915_gem_retire_requests_ring(dev, obj_priv->ring); |
| 4308 | |
| 4309 | args->busy = obj_priv->active; |
| 4310 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4311 | |
| 4312 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4313 | unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4314 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4315 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4316 | } |
| 4317 | |
| 4318 | int |
| 4319 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4320 | struct drm_file *file_priv) |
| 4321 | { |
| 4322 | return i915_gem_ring_throttle(dev, file_priv); |
| 4323 | } |
| 4324 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4325 | int |
| 4326 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4327 | struct drm_file *file_priv) |
| 4328 | { |
| 4329 | struct drm_i915_gem_madvise *args = data; |
| 4330 | struct drm_gem_object *obj; |
| 4331 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 76c1dec | 2010-09-25 11:22:51 +0100 | [diff] [blame] | 4332 | int ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4333 | |
| 4334 | switch (args->madv) { |
| 4335 | case I915_MADV_DONTNEED: |
| 4336 | case I915_MADV_WILLNEED: |
| 4337 | break; |
| 4338 | default: |
| 4339 | return -EINVAL; |
| 4340 | } |
| 4341 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4342 | ret = i915_mutex_lock_interruptible(dev); |
| 4343 | if (ret) |
| 4344 | return ret; |
| 4345 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4346 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4347 | if (obj == NULL) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4348 | ret = -ENOENT; |
| 4349 | goto unlock; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4350 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4351 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4352 | |
| 4353 | if (obj_priv->pin_count) { |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4354 | ret = -EINVAL; |
| 4355 | goto out; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4356 | } |
| 4357 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4358 | if (obj_priv->madv != __I915_MADV_PURGED) |
| 4359 | obj_priv->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4360 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4361 | /* if the object is no longer bound, discard its backing storage */ |
| 4362 | if (i915_gem_object_is_purgeable(obj_priv) && |
| 4363 | obj_priv->gtt_space == NULL) |
| 4364 | i915_gem_object_truncate(obj); |
| 4365 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4366 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
| 4367 | |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4368 | out: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4369 | drm_gem_object_unreference(obj); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4370 | unlock: |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4371 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | 1d7cfea | 2010-10-17 09:45:41 +0100 | [diff] [blame] | 4372 | return ret; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4373 | } |
| 4374 | |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4375 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
| 4376 | size_t size) |
| 4377 | { |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4378 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4379 | struct drm_i915_gem_object *obj; |
| 4380 | |
| 4381 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 4382 | if (obj == NULL) |
| 4383 | return NULL; |
| 4384 | |
| 4385 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 4386 | kfree(obj); |
| 4387 | return NULL; |
| 4388 | } |
| 4389 | |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4390 | i915_gem_info_add_obj(dev_priv, size); |
| 4391 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4392 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4393 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4394 | |
| 4395 | obj->agp_type = AGP_USER_MEMORY; |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 4396 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4397 | obj->fence_reg = I915_FENCE_REG_NONE; |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4398 | INIT_LIST_HEAD(&obj->mm_list); |
| 4399 | INIT_LIST_HEAD(&obj->ring_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4400 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4401 | obj->madv = I915_MADV_WILLNEED; |
| 4402 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4403 | return &obj->base; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4404 | } |
| 4405 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4406 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 4407 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4408 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4409 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4410 | return 0; |
| 4411 | } |
| 4412 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4413 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
| 4414 | { |
| 4415 | struct drm_device *dev = obj->dev; |
| 4416 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4417 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
| 4418 | int ret; |
| 4419 | |
| 4420 | ret = i915_gem_object_unbind(obj); |
| 4421 | if (ret == -ERESTARTSYS) { |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4422 | list_move(&obj_priv->mm_list, |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4423 | &dev_priv->mm.deferred_free_list); |
| 4424 | return; |
| 4425 | } |
| 4426 | |
Chris Wilson | 39a01d1 | 2010-10-28 13:03:06 +0100 | [diff] [blame] | 4427 | if (obj->map_list.map) |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4428 | i915_gem_free_mmap_offset(obj); |
| 4429 | |
| 4430 | drm_gem_object_release(obj); |
Chris Wilson | 73aa808 | 2010-09-30 11:46:12 +0100 | [diff] [blame] | 4431 | i915_gem_info_remove_obj(dev_priv, obj->size); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4432 | |
| 4433 | kfree(obj_priv->page_cpu_valid); |
| 4434 | kfree(obj_priv->bit_17); |
| 4435 | kfree(obj_priv); |
| 4436 | } |
| 4437 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4438 | void i915_gem_free_object(struct drm_gem_object *obj) |
| 4439 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4440 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4441 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4442 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4443 | trace_i915_gem_object_destroy(obj); |
| 4444 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4445 | while (obj_priv->pin_count > 0) |
| 4446 | i915_gem_object_unpin(obj); |
| 4447 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4448 | if (obj_priv->phys_obj) |
| 4449 | i915_gem_detach_phys_object(dev, obj); |
| 4450 | |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4451 | i915_gem_free_object_tail(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4452 | } |
| 4453 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4454 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4455 | i915_gem_idle(struct drm_device *dev) |
| 4456 | { |
| 4457 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4458 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4459 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4460 | mutex_lock(&dev->struct_mutex); |
| 4461 | |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4462 | if (dev_priv->mm.suspended) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4463 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4464 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4465 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4466 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4467 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4468 | if (ret) { |
| 4469 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4470 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4471 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4472 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4473 | /* Under UMS, be paranoid and evict. */ |
| 4474 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
Chris Wilson | b47eb4a | 2010-08-07 11:01:23 +0100 | [diff] [blame] | 4475 | ret = i915_gem_evict_inactive(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4476 | if (ret) { |
| 4477 | mutex_unlock(&dev->struct_mutex); |
| 4478 | return ret; |
| 4479 | } |
| 4480 | } |
| 4481 | |
| 4482 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4483 | * We need to replace this with a semaphore, or something. |
| 4484 | * And not confound mm.suspended! |
| 4485 | */ |
| 4486 | dev_priv->mm.suspended = 1; |
Daniel Vetter | bc0c7f1 | 2010-08-20 18:18:48 +0200 | [diff] [blame] | 4487 | del_timer_sync(&dev_priv->hangcheck_timer); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4488 | |
| 4489 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4490 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4491 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4492 | mutex_unlock(&dev->struct_mutex); |
| 4493 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4494 | /* Cancel the retire work handler, which should be idle now. */ |
| 4495 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4496 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4497 | return 0; |
| 4498 | } |
| 4499 | |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4500 | /* |
| 4501 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 4502 | * over cache flushing. |
| 4503 | */ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4504 | static int |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4505 | i915_gem_init_pipe_control(struct drm_device *dev) |
| 4506 | { |
| 4507 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4508 | struct drm_gem_object *obj; |
| 4509 | struct drm_i915_gem_object *obj_priv; |
| 4510 | int ret; |
| 4511 | |
Eric Anholt | 34dc4d4 | 2010-05-07 14:30:03 -0700 | [diff] [blame] | 4512 | obj = i915_gem_alloc_object(dev, 4096); |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4513 | if (obj == NULL) { |
| 4514 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 4515 | ret = -ENOMEM; |
| 4516 | goto err; |
| 4517 | } |
| 4518 | obj_priv = to_intel_bo(obj); |
| 4519 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
| 4520 | |
Daniel Vetter | 920afa7 | 2010-09-16 17:54:23 +0200 | [diff] [blame] | 4521 | ret = i915_gem_object_pin(obj, 4096, true); |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4522 | if (ret) |
| 4523 | goto err_unref; |
| 4524 | |
| 4525 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; |
| 4526 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); |
| 4527 | if (dev_priv->seqno_page == NULL) |
| 4528 | goto err_unpin; |
| 4529 | |
| 4530 | dev_priv->seqno_obj = obj; |
| 4531 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); |
| 4532 | |
| 4533 | return 0; |
| 4534 | |
| 4535 | err_unpin: |
| 4536 | i915_gem_object_unpin(obj); |
| 4537 | err_unref: |
| 4538 | drm_gem_object_unreference(obj); |
| 4539 | err: |
| 4540 | return ret; |
| 4541 | } |
| 4542 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4543 | |
| 4544 | static void |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4545 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
| 4546 | { |
| 4547 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4548 | struct drm_gem_object *obj; |
| 4549 | struct drm_i915_gem_object *obj_priv; |
| 4550 | |
| 4551 | obj = dev_priv->seqno_obj; |
| 4552 | obj_priv = to_intel_bo(obj); |
| 4553 | kunmap(obj_priv->pages[0]); |
| 4554 | i915_gem_object_unpin(obj); |
| 4555 | drm_gem_object_unreference(obj); |
| 4556 | dev_priv->seqno_obj = NULL; |
| 4557 | |
| 4558 | dev_priv->seqno_page = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4559 | } |
| 4560 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4561 | int |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4562 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 4563 | { |
| 4564 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4565 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4566 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4567 | if (HAS_PIPE_CONTROL(dev)) { |
| 4568 | ret = i915_gem_init_pipe_control(dev); |
| 4569 | if (ret) |
| 4570 | return ret; |
| 4571 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4572 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4573 | ret = intel_init_render_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4574 | if (ret) |
| 4575 | goto cleanup_pipe_control; |
| 4576 | |
| 4577 | if (HAS_BSD(dev)) { |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 4578 | ret = intel_init_bsd_ring_buffer(dev); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4579 | if (ret) |
| 4580 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4581 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4582 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4583 | if (HAS_BLT(dev)) { |
| 4584 | ret = intel_init_blt_ring_buffer(dev); |
| 4585 | if (ret) |
| 4586 | goto cleanup_bsd_ring; |
| 4587 | } |
| 4588 | |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 4589 | dev_priv->next_seqno = 1; |
| 4590 | |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4591 | return 0; |
| 4592 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4593 | cleanup_bsd_ring: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4594 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4595 | cleanup_render_ring: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4596 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4597 | cleanup_pipe_control: |
| 4598 | if (HAS_PIPE_CONTROL(dev)) |
| 4599 | i915_gem_cleanup_pipe_control(dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4600 | return ret; |
| 4601 | } |
| 4602 | |
| 4603 | void |
| 4604 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4605 | { |
| 4606 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4607 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 4608 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
| 4609 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
| 4610 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4611 | if (HAS_PIPE_CONTROL(dev)) |
| 4612 | i915_gem_cleanup_pipe_control(dev); |
| 4613 | } |
| 4614 | |
| 4615 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4616 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4617 | struct drm_file *file_priv) |
| 4618 | { |
| 4619 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4620 | int ret; |
| 4621 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4622 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4623 | return 0; |
| 4624 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4625 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4626 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4627 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4628 | } |
| 4629 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4630 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4631 | dev_priv->mm.suspended = 0; |
| 4632 | |
| 4633 | ret = i915_gem_init_ringbuffer(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4634 | if (ret != 0) { |
| 4635 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4636 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4637 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4638 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4639 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4640 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4641 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4642 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4643 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 4644 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4645 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
Chris Wilson | 87acb0a | 2010-10-19 10:13:00 +0100 | [diff] [blame] | 4646 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 4647 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4648 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4649 | |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4650 | ret = drm_irq_install(dev); |
| 4651 | if (ret) |
| 4652 | goto cleanup_ringbuffer; |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4653 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4654 | return 0; |
Chris Wilson | 5f35308 | 2010-06-07 14:03:03 +0100 | [diff] [blame] | 4655 | |
| 4656 | cleanup_ringbuffer: |
| 4657 | mutex_lock(&dev->struct_mutex); |
| 4658 | i915_gem_cleanup_ringbuffer(dev); |
| 4659 | dev_priv->mm.suspended = 1; |
| 4660 | mutex_unlock(&dev->struct_mutex); |
| 4661 | |
| 4662 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4663 | } |
| 4664 | |
| 4665 | int |
| 4666 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4667 | struct drm_file *file_priv) |
| 4668 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4669 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4670 | return 0; |
| 4671 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4672 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 4673 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4674 | } |
| 4675 | |
| 4676 | void |
| 4677 | i915_gem_lastclose(struct drm_device *dev) |
| 4678 | { |
| 4679 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4680 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4681 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4682 | return; |
| 4683 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4684 | ret = i915_gem_idle(dev); |
| 4685 | if (ret) |
| 4686 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4687 | } |
| 4688 | |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4689 | static void |
| 4690 | init_ring_lists(struct intel_ring_buffer *ring) |
| 4691 | { |
| 4692 | INIT_LIST_HEAD(&ring->active_list); |
| 4693 | INIT_LIST_HEAD(&ring->request_list); |
| 4694 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 4695 | } |
| 4696 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4697 | void |
| 4698 | i915_gem_load(struct drm_device *dev) |
| 4699 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4700 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4701 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4702 | |
Chris Wilson | 69dc498 | 2010-10-19 10:36:51 +0100 | [diff] [blame] | 4703 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4704 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
| 4705 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Chris Wilson | f13d3f7 | 2010-09-20 17:36:15 +0100 | [diff] [blame] | 4706 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4707 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Chris Wilson | be72615 | 2010-07-23 23:18:50 +0100 | [diff] [blame] | 4708 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 4709 | init_ring_lists(&dev_priv->render_ring); |
| 4710 | init_ring_lists(&dev_priv->bsd_ring); |
| 4711 | init_ring_lists(&dev_priv->blt_ring); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4712 | for (i = 0; i < 16; i++) |
| 4713 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4714 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4715 | i915_gem_retire_work_handler); |
Chris Wilson | 30dbf0c | 2010-09-25 10:19:17 +0100 | [diff] [blame] | 4716 | init_completion(&dev_priv->error_completion); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4717 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame] | 4718 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4719 | if (IS_GEN3(dev)) { |
| 4720 | u32 tmp = I915_READ(MI_ARB_STATE); |
| 4721 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
| 4722 | /* arb state is a masked write, so set bit + bit in mask */ |
| 4723 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
| 4724 | I915_WRITE(MI_ARB_STATE, tmp); |
| 4725 | } |
| 4726 | } |
| 4727 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4728 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4729 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4730 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4731 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4732 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4733 | dev_priv->num_fence_regs = 16; |
| 4734 | else |
| 4735 | dev_priv->num_fence_regs = 8; |
| 4736 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4737 | /* Initialize fence registers to zero */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4738 | switch (INTEL_INFO(dev)->gen) { |
| 4739 | case 6: |
| 4740 | for (i = 0; i < 16; i++) |
| 4741 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); |
| 4742 | break; |
| 4743 | case 5: |
| 4744 | case 4: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4745 | for (i = 0; i < 16; i++) |
| 4746 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4747 | break; |
| 4748 | case 3: |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4749 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 4750 | for (i = 0; i < 8; i++) |
| 4751 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 4752 | case 2: |
| 4753 | for (i = 0; i < 8; i++) |
| 4754 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); |
| 4755 | break; |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4756 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4757 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4758 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4759 | |
| 4760 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
| 4761 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
| 4762 | register_shrinker(&dev_priv->mm.inactive_shrinker); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4763 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4764 | |
| 4765 | /* |
| 4766 | * Create a physically contiguous memory object for this object |
| 4767 | * e.g. for cursor + overlay regs |
| 4768 | */ |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4769 | static int i915_gem_init_phys_object(struct drm_device *dev, |
| 4770 | int id, int size, int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4771 | { |
| 4772 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4773 | struct drm_i915_gem_phys_object *phys_obj; |
| 4774 | int ret; |
| 4775 | |
| 4776 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4777 | return 0; |
| 4778 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4779 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4780 | if (!phys_obj) |
| 4781 | return -ENOMEM; |
| 4782 | |
| 4783 | phys_obj->id = id; |
| 4784 | |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4785 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4786 | if (!phys_obj->handle) { |
| 4787 | ret = -ENOMEM; |
| 4788 | goto kfree_obj; |
| 4789 | } |
| 4790 | #ifdef CONFIG_X86 |
| 4791 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4792 | #endif |
| 4793 | |
| 4794 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4795 | |
| 4796 | return 0; |
| 4797 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4798 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4799 | return ret; |
| 4800 | } |
| 4801 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 4802 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4803 | { |
| 4804 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4805 | struct drm_i915_gem_phys_object *phys_obj; |
| 4806 | |
| 4807 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4808 | return; |
| 4809 | |
| 4810 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4811 | if (phys_obj->cur_obj) { |
| 4812 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4813 | } |
| 4814 | |
| 4815 | #ifdef CONFIG_X86 |
| 4816 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4817 | #endif |
| 4818 | drm_pci_free(dev, phys_obj->handle); |
| 4819 | kfree(phys_obj); |
| 4820 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4821 | } |
| 4822 | |
| 4823 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4824 | { |
| 4825 | int i; |
| 4826 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4827 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4828 | i915_gem_free_phys_object(dev, i); |
| 4829 | } |
| 4830 | |
| 4831 | void i915_gem_detach_phys_object(struct drm_device *dev, |
| 4832 | struct drm_gem_object *obj) |
| 4833 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4834 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
| 4835 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
| 4836 | char *vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4837 | int i; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4838 | int page_count; |
| 4839 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4840 | if (!obj_priv->phys_obj) |
| 4841 | return; |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4842 | vaddr = obj_priv->phys_obj->handle->vaddr; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4843 | |
| 4844 | page_count = obj->size / PAGE_SIZE; |
| 4845 | |
| 4846 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4847 | struct page *page = read_cache_page_gfp(mapping, i, |
| 4848 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 4849 | if (!IS_ERR(page)) { |
| 4850 | char *dst = kmap_atomic(page); |
| 4851 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); |
| 4852 | kunmap_atomic(dst); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4853 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4854 | drm_clflush_pages(&page, 1); |
| 4855 | |
| 4856 | set_page_dirty(page); |
| 4857 | mark_page_accessed(page); |
| 4858 | page_cache_release(page); |
| 4859 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4860 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4861 | drm_agp_chipset_flush(dev); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4862 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4863 | obj_priv->phys_obj->cur_obj = NULL; |
| 4864 | obj_priv->phys_obj = NULL; |
| 4865 | } |
| 4866 | |
| 4867 | int |
| 4868 | i915_gem_attach_phys_object(struct drm_device *dev, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4869 | struct drm_gem_object *obj, |
| 4870 | int id, |
| 4871 | int align) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4872 | { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4873 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4874 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4875 | struct drm_i915_gem_object *obj_priv; |
| 4876 | int ret = 0; |
| 4877 | int page_count; |
| 4878 | int i; |
| 4879 | |
| 4880 | if (id > I915_MAX_PHYS_OBJECT) |
| 4881 | return -EINVAL; |
| 4882 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4883 | obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4884 | |
| 4885 | if (obj_priv->phys_obj) { |
| 4886 | if (obj_priv->phys_obj->id == id) |
| 4887 | return 0; |
| 4888 | i915_gem_detach_phys_object(dev, obj); |
| 4889 | } |
| 4890 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4891 | /* create a new object */ |
| 4892 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4893 | ret = i915_gem_init_phys_object(dev, id, |
Chris Wilson | 6eeefaf | 2010-08-07 11:01:39 +0100 | [diff] [blame] | 4894 | obj->size, align); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4895 | if (ret) { |
Linus Torvalds | aeb565d | 2009-01-26 10:01:53 -0800 | [diff] [blame] | 4896 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4897 | return ret; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4898 | } |
| 4899 | } |
| 4900 | |
| 4901 | /* bind to the object */ |
| 4902 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4903 | obj_priv->phys_obj->cur_obj = obj; |
| 4904 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4905 | page_count = obj->size / PAGE_SIZE; |
| 4906 | |
| 4907 | for (i = 0; i < page_count; i++) { |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4908 | struct page *page; |
| 4909 | char *dst, *src; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4910 | |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4911 | page = read_cache_page_gfp(mapping, i, |
| 4912 | GFP_HIGHUSER | __GFP_RECLAIMABLE); |
| 4913 | if (IS_ERR(page)) |
| 4914 | return PTR_ERR(page); |
| 4915 | |
| 4916 | src = kmap_atomic(obj_priv->pages[i]); |
| 4917 | dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4918 | memcpy(dst, src, PAGE_SIZE); |
Peter Zijlstra | 3e4d3af | 2010-10-26 14:21:51 -0700 | [diff] [blame] | 4919 | kunmap_atomic(src); |
Chris Wilson | e5281cc | 2010-10-28 13:45:36 +0100 | [diff] [blame] | 4920 | |
| 4921 | mark_page_accessed(page); |
| 4922 | page_cache_release(page); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4923 | } |
| 4924 | |
| 4925 | return 0; |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4926 | } |
| 4927 | |
| 4928 | static int |
| 4929 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 4930 | struct drm_i915_gem_pwrite *args, |
| 4931 | struct drm_file *file_priv) |
| 4932 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4933 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4934 | void *obj_addr; |
| 4935 | int ret; |
| 4936 | char __user *user_data; |
| 4937 | |
| 4938 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 4939 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; |
| 4940 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4941 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4942 | ret = copy_from_user(obj_addr, user_data, args->size); |
| 4943 | if (ret) |
| 4944 | return -EFAULT; |
| 4945 | |
| 4946 | drm_agp_chipset_flush(dev); |
| 4947 | return 0; |
| 4948 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4949 | |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4950 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4951 | { |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4952 | struct drm_i915_file_private *file_priv = file->driver_priv; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4953 | |
| 4954 | /* Clean up our request list when the client is going away, so that |
| 4955 | * later retire_requests won't dereference our soon-to-be-gone |
| 4956 | * file_priv. |
| 4957 | */ |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4958 | spin_lock(&file_priv->mm.lock); |
Chris Wilson | f787a5f | 2010-09-24 16:02:42 +0100 | [diff] [blame] | 4959 | while (!list_empty(&file_priv->mm.request_list)) { |
| 4960 | struct drm_i915_gem_request *request; |
| 4961 | |
| 4962 | request = list_first_entry(&file_priv->mm.request_list, |
| 4963 | struct drm_i915_gem_request, |
| 4964 | client_list); |
| 4965 | list_del(&request->client_list); |
| 4966 | request->file_priv = NULL; |
| 4967 | } |
Chris Wilson | 1c25595 | 2010-09-26 11:03:27 +0100 | [diff] [blame] | 4968 | spin_unlock(&file_priv->mm.lock); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4969 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4970 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4971 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4972 | i915_gpu_is_active(struct drm_device *dev) |
| 4973 | { |
| 4974 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4975 | int lists_empty; |
| 4976 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4977 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4978 | list_empty(&dev_priv->mm.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4979 | |
| 4980 | return !lists_empty; |
| 4981 | } |
| 4982 | |
| 4983 | static int |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4984 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
| 4985 | int nr_to_scan, |
| 4986 | gfp_t gfp_mask) |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4987 | { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 4988 | struct drm_i915_private *dev_priv = |
| 4989 | container_of(shrinker, |
| 4990 | struct drm_i915_private, |
| 4991 | mm.inactive_shrinker); |
| 4992 | struct drm_device *dev = dev_priv->dev; |
| 4993 | struct drm_i915_gem_object *obj, *next; |
| 4994 | int cnt; |
| 4995 | |
| 4996 | if (!mutex_trylock(&dev->struct_mutex)) |
| 4997 | return nr_to_scan ? 0 : -1; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4998 | |
| 4999 | /* "fast-path" to count number of available objects */ |
| 5000 | if (nr_to_scan == 0) { |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5001 | cnt = 0; |
| 5002 | list_for_each_entry(obj, |
| 5003 | &dev_priv->mm.inactive_list, |
| 5004 | mm_list) |
| 5005 | cnt++; |
| 5006 | mutex_unlock(&dev->struct_mutex); |
| 5007 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5008 | } |
| 5009 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5010 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5011 | /* first scan for clean buffers */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5012 | i915_gem_retire_requests(dev); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5013 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5014 | list_for_each_entry_safe(obj, next, |
| 5015 | &dev_priv->mm.inactive_list, |
| 5016 | mm_list) { |
| 5017 | if (i915_gem_object_is_purgeable(obj)) { |
| 5018 | i915_gem_object_unbind(&obj->base); |
| 5019 | if (--nr_to_scan == 0) |
| 5020 | break; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5021 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5022 | } |
| 5023 | |
| 5024 | /* second pass, evict/count anything still on the inactive list */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5025 | cnt = 0; |
| 5026 | list_for_each_entry_safe(obj, next, |
| 5027 | &dev_priv->mm.inactive_list, |
| 5028 | mm_list) { |
| 5029 | if (nr_to_scan) { |
| 5030 | i915_gem_object_unbind(&obj->base); |
| 5031 | nr_to_scan--; |
| 5032 | } else |
| 5033 | cnt++; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5034 | } |
| 5035 | |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5036 | if (nr_to_scan && i915_gpu_is_active(dev)) { |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5037 | /* |
| 5038 | * We are desperate for pages, so as a last resort, wait |
| 5039 | * for the GPU to finish and discard whatever we can. |
| 5040 | * This has a dramatic impact to reduce the number of |
| 5041 | * OOM-killer events whilst running the GPU aggressively. |
| 5042 | */ |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5043 | if (i915_gpu_idle(dev) == 0) |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5044 | goto rescan; |
| 5045 | } |
Chris Wilson | 17250b7 | 2010-10-28 12:51:39 +0100 | [diff] [blame] | 5046 | mutex_unlock(&dev->struct_mutex); |
| 5047 | return cnt / 100 * sysctl_vfs_cache_pressure; |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5048 | } |