blob: 013727b20417226249ca942d28708164a497c2dc [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090044#include <linux/dmi.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090045#include <linux/gfp.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070046#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050047#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048#include <linux/libata.h>
Anton Vorontsov365cfa12010-03-28 00:22:14 -040049#include "ahci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070050
51#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090052#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070053
Linus Torvalds1da177e2005-04-16 15:20:36 -070054enum {
55 AHCI_PCI_BAR = 5,
Tejun Heo441577e2010-03-29 10:32:39 +090056};
Linus Torvalds1da177e2005-04-16 15:20:36 -070057
Tejun Heo441577e2010-03-29 10:32:39 +090058enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
Tejun Heo5f173102010-07-24 16:53:48 +020063 board_ahci_yes_fbs,
Tejun Heo441577e2010-03-29 10:32:39 +090064
65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
Tejun Heo83f2b962010-03-30 10:28:32 +090067 board_ahci_mcp77,
68 board_ahci_mcp89,
Tejun Heo441577e2010-03-29 10:32:39 +090069 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
Tejun Heo83f2b962010-03-30 10:28:32 +090078 board_ahci_mcp79 = board_ahci_mcp77,
Linus Torvalds1da177e2005-04-16 15:20:36 -070079};
80
Jeff Garzik2dcb4072007-10-19 06:42:56 -040081static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Shane Huangbd172432008-06-10 15:52:04 +080082static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
Tejun Heoa1efdab2008-03-25 12:22:50 +090084static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
Tejun Heo438ac6d2007-03-02 17:31:26 +090088#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +090089static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +090091#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070092
Tejun Heo029cfd62008-03-25 12:22:49 +090093static struct ata_port_operations ahci_vt8251_ops = {
94 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +090095 .hardreset = ahci_vt8251_hardreset,
Tejun Heoad616ff2006-11-01 18:00:24 +090096};
97
Tejun Heo029cfd62008-03-25 12:22:49 +090098static struct ata_port_operations ahci_p5wdh_ops = {
99 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900100 .hardreset = ahci_p5wdh_hardreset,
Tejun Heoedc93052007-10-25 14:59:16 +0900101};
102
Shane Huangbd172432008-06-10 15:52:04 +0800103static struct ata_port_operations ahci_sb600_ops = {
104 .inherits = &ahci_ops,
105 .softreset = ahci_sb600_softreset,
106 .pmp_softreset = ahci_sb600_softreset,
107};
108
Tejun Heo417a1a62007-09-23 13:19:55 +0900109#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
110
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100111static const struct ata_port_info ahci_port_info[] = {
Tejun Heo441577e2010-03-29 10:32:39 +0900112 /* by features */
Jeff Garzik4da646b2009-04-08 02:00:13 -0400113 [board_ahci] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900115 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100116 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400117 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700118 .port_ops = &ahci_ops,
119 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400120 [board_ahci_ign_iferr] =
Tejun Heo41669552006-11-29 11:33:14 +0900121 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900122 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
123 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100124 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400125 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900126 .port_ops = &ahci_ops,
127 },
Tejun Heo441577e2010-03-29 10:32:39 +0900128 [board_ahci_nosntf] =
129 {
130 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
135 },
Tejun Heo5f173102010-07-24 16:53:48 +0200136 [board_ahci_yes_fbs] =
137 {
138 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
139 .flags = AHCI_FLAG_COMMON,
140 .pio_mask = ATA_PIO4,
141 .udma_mask = ATA_UDMA6,
142 .port_ops = &ahci_ops,
143 },
Tejun Heo441577e2010-03-29 10:32:39 +0900144 /* by chipsets */
145 [board_ahci_mcp65] =
146 {
Tejun Heo83f2b962010-03-30 10:28:32 +0900147 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
148 AHCI_HFLAG_YES_NCQ),
149 .flags = AHCI_FLAG_COMMON,
150 .pio_mask = ATA_PIO4,
151 .udma_mask = ATA_UDMA6,
152 .port_ops = &ahci_ops,
153 },
154 [board_ahci_mcp77] =
155 {
156 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
157 .flags = AHCI_FLAG_COMMON,
158 .pio_mask = ATA_PIO4,
159 .udma_mask = ATA_UDMA6,
160 .port_ops = &ahci_ops,
161 },
162 [board_ahci_mcp89] =
163 {
164 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
Tejun Heo441577e2010-03-29 10:32:39 +0900165 .flags = AHCI_FLAG_COMMON,
166 .pio_mask = ATA_PIO4,
167 .udma_mask = ATA_UDMA6,
168 .port_ops = &ahci_ops,
169 },
170 [board_ahci_mv] =
171 {
172 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
173 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
174 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
175 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
176 .pio_mask = ATA_PIO4,
177 .udma_mask = ATA_UDMA6,
178 .port_ops = &ahci_ops,
179 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400180 [board_ahci_sb600] =
Conke Hu55a61602007-03-27 18:33:05 +0800181 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900182 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900183 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
184 AHCI_HFLAG_32BIT_ONLY),
Tejun Heo417a1a62007-09-23 13:19:55 +0900185 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100186 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400187 .udma_mask = ATA_UDMA6,
Shane Huangbd172432008-06-10 15:52:04 +0800188 .port_ops = &ahci_sb600_ops,
Conke Hu55a61602007-03-27 18:33:05 +0800189 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400190 [board_ahci_sb700] = /* for SB700 and SB800 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800191 {
Shane Huangbd172432008-06-10 15:52:04 +0800192 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
Shane Huange39fc8c2008-02-22 05:00:31 -0800193 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100194 .pio_mask = ATA_PIO4,
Shane Huange39fc8c2008-02-22 05:00:31 -0800195 .udma_mask = ATA_UDMA6,
Shane Huangbd172432008-06-10 15:52:04 +0800196 .port_ops = &ahci_sb600_ops,
Shane Huange39fc8c2008-02-22 05:00:31 -0800197 },
Tejun Heo441577e2010-03-29 10:32:39 +0900198 [board_ahci_vt8251] =
Tejun Heoe297d992008-06-10 00:13:04 +0900199 {
Tejun Heo441577e2010-03-29 10:32:39 +0900200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heoe297d992008-06-10 00:13:04 +0900201 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100202 .pio_mask = ATA_PIO4,
Tejun Heoe297d992008-06-10 00:13:04 +0900203 .udma_mask = ATA_UDMA6,
Tejun Heo441577e2010-03-29 10:32:39 +0900204 .port_ops = &ahci_vt8251_ops,
Shaohua Li1b677af2009-11-16 09:56:05 +0800205 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206};
207
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500208static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400209 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400210 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
211 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
212 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
213 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
214 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900215 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400216 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
217 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
218 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
219 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900220 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
Shaohua Li1b677af2009-11-16 09:56:05 +0800221 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
Tejun Heo7a234af2007-09-03 12:44:57 +0900222 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
223 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
224 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
225 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
236 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400237 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
238 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800239 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
Mark Goodwinb2dde6a2009-06-26 10:44:11 -0500240 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800241 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
David Milburnc1f57d92009-07-22 15:15:56 -0500242 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
243 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700244 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700245 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500246 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700247 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700248 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500249 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
Seth Heasley5623cab2010-01-12 17:00:18 -0800250 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
251 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
252 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
253 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
254 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
255 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400256
Tejun Heoe34bb372007-02-26 20:24:03 +0900257 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
258 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
259 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400260
261 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800262 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800263 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
264 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
265 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
266 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
267 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
268 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400269
Shane Huange2dd90b2009-07-29 11:34:49 +0800270 /* AMD */
Shane Huang5deab532009-10-13 11:14:00 +0800271 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
Shane Huange2dd90b2009-07-29 11:34:49 +0800272 /* AMD is using RAID class only for ahci controllers */
273 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
274 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
275
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400276 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400277 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900278 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400279
280 /* NVIDIA */
Tejun Heoe297d992008-06-10 00:13:04 +0900281 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
282 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
283 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
284 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
285 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
286 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
287 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
288 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
Tejun Heo441577e2010-03-29 10:32:39 +0900289 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
290 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
291 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
292 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
293 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
294 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
295 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
296 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
302 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
303 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
304 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
305 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
306 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
307 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
308 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
318 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
319 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
320 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
321 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
322 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
323 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
324 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
330 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
331 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
332 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
333 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
334 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
335 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
342 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
343 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
344 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
345 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
346 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
347 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
348 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
354 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
355 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
356 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
357 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
358 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
359 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
360 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400365
Jeff Garzik95916ed2006-07-29 04:10:14 -0400366 /* SiS */
Tejun Heo20e2de42008-08-01 12:51:43 +0900367 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
368 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
369 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400370
Jeff Garzikcd70c262007-07-08 02:29:42 -0400371 /* Marvell */
372 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100373 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
Tejun Heo5f173102010-07-24 16:53:48 +0200374 { PCI_DEVICE(0x1b4b, 0x9123),
375 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
Jeff Garzikcd70c262007-07-08 02:29:42 -0400376
Mark Nelsonc77a0362008-10-23 14:08:16 +1100377 /* Promise */
378 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
379
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500380 /* Generic, PCI class code for AHCI */
381 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500382 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500383
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384 { } /* terminate list */
385};
386
387
388static struct pci_driver ahci_pci_driver = {
389 .name = DRV_NAME,
390 .id_table = ahci_pci_tbl,
391 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900392 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900393#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900394 .suspend = ahci_pci_device_suspend,
395 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900396#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700397};
398
Alan Cox5b66c822008-09-03 14:48:34 +0100399#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
400static int marvell_enable;
401#else
402static int marvell_enable = 1;
403#endif
404module_param(marvell_enable, int, 0644);
405MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
406
407
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300408static void ahci_pci_save_initial_config(struct pci_dev *pdev,
409 struct ahci_host_priv *hpriv)
410{
411 unsigned int force_port_map = 0;
412 unsigned int mask_port_map = 0;
413
414 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
415 dev_info(&pdev->dev, "JMB361 has only one port\n");
416 force_port_map = 1;
417 }
418
419 /*
420 * Temporary Marvell 6145 hack: PATA port presence
421 * is asserted through the standard AHCI port
422 * presence register, as bit 4 (counting from 0)
423 */
424 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
425 if (pdev->device == 0x6121)
426 mask_port_map = 0x3;
427 else
428 mask_port_map = 0xf;
429 dev_info(&pdev->dev,
430 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
431 }
432
Anton Vorontsov1d513352010-03-03 20:17:37 +0300433 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
434 mask_port_map);
Anton Vorontsov394d6e52010-03-03 20:17:36 +0300435}
436
Anton Vorontsov33030402010-03-03 20:17:39 +0300437static int ahci_pci_reset_controller(struct ata_host *host)
438{
439 struct pci_dev *pdev = to_pci_dev(host->dev);
440
441 ahci_reset_controller(host);
442
Tejun Heod91542c2006-07-26 15:59:26 +0900443 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
Anton Vorontsov33030402010-03-03 20:17:39 +0300444 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heod91542c2006-07-26 15:59:26 +0900445 u16 tmp16;
446
447 /* configure PCS */
448 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +0900449 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
450 tmp16 |= hpriv->port_map;
451 pci_write_config_word(pdev, 0x92, tmp16);
452 }
Tejun Heod91542c2006-07-26 15:59:26 +0900453 }
454
455 return 0;
456}
457
Anton Vorontsov781d6552010-03-03 20:17:42 +0300458static void ahci_pci_init_controller(struct ata_host *host)
459{
460 struct ahci_host_priv *hpriv = host->private_data;
461 struct pci_dev *pdev = to_pci_dev(host->dev);
462 void __iomem *port_mmio;
463 u32 tmp;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100464 int mv;
Tejun Heod91542c2006-07-26 15:59:26 +0900465
Tejun Heo417a1a62007-09-23 13:19:55 +0900466 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100467 if (pdev->device == 0x6121)
468 mv = 2;
469 else
470 mv = 4;
471 port_mmio = __ahci_port_base(host, mv);
Jeff Garzikcd70c262007-07-08 02:29:42 -0400472
473 writel(0, port_mmio + PORT_IRQ_MASK);
474
475 /* clear port IRQ */
476 tmp = readl(port_mmio + PORT_IRQ_STAT);
477 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
478 if (tmp)
479 writel(tmp, port_mmio + PORT_IRQ_STAT);
480 }
481
Anton Vorontsov781d6552010-03-03 20:17:42 +0300482 ahci_init_controller(host);
Tejun Heod91542c2006-07-26 15:59:26 +0900483}
484
Shane Huangbd172432008-06-10 15:52:04 +0800485static int ahci_sb600_check_ready(struct ata_link *link)
486{
487 void __iomem *port_mmio = ahci_port_base(link->ap);
488 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
489 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
490
491 /*
492 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
493 * which can save timeout delay.
494 */
495 if (irq_status & PORT_IRQ_BAD_PMP)
496 return -EIO;
497
498 return ata_check_ready(status);
499}
500
501static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
502 unsigned long deadline)
503{
504 struct ata_port *ap = link->ap;
505 void __iomem *port_mmio = ahci_port_base(ap);
506 int pmp = sata_srst_pmp(link);
507 int rc;
508 u32 irq_sts;
509
510 DPRINTK("ENTER\n");
511
512 rc = ahci_do_softreset(link, class, pmp, deadline,
513 ahci_sb600_check_ready);
514
515 /*
516 * Soft reset fails on some ATI chips with IPMS set when PMP
517 * is enabled but SATA HDD/ODD is connected to SATA port,
518 * do soft reset again to port 0.
519 */
520 if (rc == -EIO) {
521 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
522 if (irq_sts & PORT_IRQ_BAD_PMP) {
523 ata_link_printk(link, KERN_WARNING,
Shane Huangb6931c12009-08-05 10:10:41 +0800524 "applying SB600 PMP SRST workaround "
525 "and retrying\n");
Shane Huangbd172432008-06-10 15:52:04 +0800526 rc = ahci_do_softreset(link, class, 0, deadline,
527 ahci_check_ready);
528 }
529 }
530
531 return rc;
532}
533
Tejun Heocc0680a2007-08-06 18:36:23 +0900534static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +0900535 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +0900536{
Tejun Heocc0680a2007-08-06 18:36:23 +0900537 struct ata_port *ap = link->ap;
Tejun Heo9dadd452008-04-07 22:47:19 +0900538 bool online;
Tejun Heoad616ff2006-11-01 18:00:24 +0900539 int rc;
540
541 DPRINTK("ENTER\n");
542
Tejun Heo4447d352007-04-17 23:44:08 +0900543 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900544
Tejun Heocc0680a2007-08-06 18:36:23 +0900545 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +0900546 deadline, &online, NULL);
Tejun Heoad616ff2006-11-01 18:00:24 +0900547
Tejun Heo4447d352007-04-17 23:44:08 +0900548 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900549
550 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
551
552 /* vt8251 doesn't clear BSY on signature FIS reception,
553 * request follow-up softreset.
554 */
Tejun Heo9dadd452008-04-07 22:47:19 +0900555 return online ? -EAGAIN : rc;
Tejun Heoad616ff2006-11-01 18:00:24 +0900556}
557
Tejun Heoedc93052007-10-25 14:59:16 +0900558static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
559 unsigned long deadline)
560{
561 struct ata_port *ap = link->ap;
562 struct ahci_port_priv *pp = ap->private_data;
563 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
564 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +0900565 bool online;
Tejun Heoedc93052007-10-25 14:59:16 +0900566 int rc;
567
568 ahci_stop_engine(ap);
569
570 /* clear D2H reception area to properly wait for D2H FIS */
571 ata_tf_init(link->device, &tf);
572 tf.command = 0x80;
573 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
574
575 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +0900576 deadline, &online, NULL);
Tejun Heoedc93052007-10-25 14:59:16 +0900577
578 ahci_start_engine(ap);
579
Tejun Heoedc93052007-10-25 14:59:16 +0900580 /* The pseudo configuration device on SIMG4726 attached to
581 * ASUS P5W-DH Deluxe doesn't send signature FIS after
582 * hardreset if no device is attached to the first downstream
583 * port && the pseudo device locks up on SRST w/ PMP==0. To
584 * work around this, wait for !BSY only briefly. If BSY isn't
585 * cleared, perform CLO and proceed to IDENTIFY (achieved by
586 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
587 *
588 * Wait for two seconds. Devices attached to downstream port
589 * which can't process the following IDENTIFY after this will
590 * have to be reset again. For most cases, this should
591 * suffice while making probing snappish enough.
592 */
Tejun Heo9dadd452008-04-07 22:47:19 +0900593 if (online) {
594 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
595 ahci_check_ready);
596 if (rc)
Shane Huang78d5ae32009-08-07 15:05:52 +0800597 ahci_kick_engine(ap);
Tejun Heo9dadd452008-04-07 22:47:19 +0900598 }
Tejun Heo9dadd452008-04-07 22:47:19 +0900599 return rc;
Tejun Heoedc93052007-10-25 14:59:16 +0900600}
601
Tejun Heo438ac6d2007-03-02 17:31:26 +0900602#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900603static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
604{
Jeff Garzikcca39742006-08-24 03:19:22 -0400605 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo9b10ae82009-05-30 20:50:12 +0900606 struct ahci_host_priv *hpriv = host->private_data;
Anton Vorontsovd8993342010-03-03 20:17:34 +0300607 void __iomem *mmio = hpriv->mmio;
Tejun Heoc1332872006-07-26 15:59:26 +0900608 u32 ctl;
609
Tejun Heo9b10ae82009-05-30 20:50:12 +0900610 if (mesg.event & PM_EVENT_SUSPEND &&
611 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
612 dev_printk(KERN_ERR, &pdev->dev,
613 "BIOS update required for suspend/resume\n");
614 return -EIO;
615 }
616
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +0100617 if (mesg.event & PM_EVENT_SLEEP) {
Tejun Heoc1332872006-07-26 15:59:26 +0900618 /* AHCI spec rev1.1 section 8.3.3:
619 * Software must disable interrupts prior to requesting a
620 * transition of the HBA to D3 state.
621 */
622 ctl = readl(mmio + HOST_CTL);
623 ctl &= ~HOST_IRQ_EN;
624 writel(ctl, mmio + HOST_CTL);
625 readl(mmio + HOST_CTL); /* flush */
626 }
627
628 return ata_pci_device_suspend(pdev, mesg);
629}
630
631static int ahci_pci_device_resume(struct pci_dev *pdev)
632{
Jeff Garzikcca39742006-08-24 03:19:22 -0400633 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +0900634 int rc;
635
Tejun Heo553c4aa2006-12-26 19:39:50 +0900636 rc = ata_pci_device_do_resume(pdev);
637 if (rc)
638 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +0900639
640 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Anton Vorontsov33030402010-03-03 20:17:39 +0300641 rc = ahci_pci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900642 if (rc)
643 return rc;
644
Anton Vorontsov781d6552010-03-03 20:17:42 +0300645 ahci_pci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900646 }
647
Jeff Garzikcca39742006-08-24 03:19:22 -0400648 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +0900649
650 return 0;
651}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900652#endif
Tejun Heoc1332872006-07-26 15:59:26 +0900653
Tejun Heo4447d352007-04-17 23:44:08 +0900654static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700656 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658 if (using_dac &&
Yang Hongyang6a355282009-04-06 19:01:13 -0700659 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
660 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661 if (rc) {
Yang Hongyang284901a2009-04-06 19:01:15 -0700662 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700663 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500664 dev_printk(KERN_ERR, &pdev->dev,
665 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700666 return rc;
667 }
668 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -0700670 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500672 dev_printk(KERN_ERR, &pdev->dev,
673 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700674 return rc;
675 }
Yang Hongyang284901a2009-04-06 19:01:15 -0700676 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -0500678 dev_printk(KERN_ERR, &pdev->dev,
679 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680 return rc;
681 }
682 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700683 return 0;
684}
685
Anton Vorontsov439fcae2010-03-03 20:17:43 +0300686static void ahci_pci_print_info(struct ata_host *host)
687{
688 struct pci_dev *pdev = to_pci_dev(host->dev);
689 u16 cc;
690 const char *scc_s;
691
692 pci_read_config_word(pdev, 0x0a, &cc);
693 if (cc == PCI_CLASS_STORAGE_IDE)
694 scc_s = "IDE";
695 else if (cc == PCI_CLASS_STORAGE_SATA)
696 scc_s = "SATA";
697 else if (cc == PCI_CLASS_STORAGE_RAID)
698 scc_s = "RAID";
699 else
700 scc_s = "unknown";
701
702 ahci_print_info(host, scc_s);
703}
704
Tejun Heoedc93052007-10-25 14:59:16 +0900705/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
706 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
707 * support PMP and the 4726 either directly exports the device
708 * attached to the first downstream port or acts as a hardware storage
709 * controller and emulate a single ATA device (can be RAID 0/1 or some
710 * other configuration).
711 *
712 * When there's no device attached to the first downstream port of the
713 * 4726, "Config Disk" appears, which is a pseudo ATA device to
714 * configure the 4726. However, ATA emulation of the device is very
715 * lame. It doesn't send signature D2H Reg FIS after the initial
716 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
717 *
718 * The following function works around the problem by always using
719 * hardreset on the port and not depending on receiving signature FIS
720 * afterward. If signature FIS isn't received soon, ATA class is
721 * assumed without follow-up softreset.
722 */
723static void ahci_p5wdh_workaround(struct ata_host *host)
724{
725 static struct dmi_system_id sysids[] = {
726 {
727 .ident = "P5W DH Deluxe",
728 .matches = {
729 DMI_MATCH(DMI_SYS_VENDOR,
730 "ASUSTEK COMPUTER INC"),
731 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
732 },
733 },
734 { }
735 };
736 struct pci_dev *pdev = to_pci_dev(host->dev);
737
738 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
739 dmi_check_system(sysids)) {
740 struct ata_port *ap = host->ports[1];
741
742 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
743 "Deluxe on-board SIMG4726 workaround\n");
744
745 ap->ops = &ahci_p5wdh_ops;
746 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
747 }
748}
749
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900750/* only some SB600 ahci controllers can do 64bit DMA */
751static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
Shane Huang58a09b32009-05-27 15:04:43 +0800752{
753 static const struct dmi_system_id sysids[] = {
Tejun Heo03d783b2009-08-16 21:04:02 +0900754 /*
755 * The oldest version known to be broken is 0901 and
756 * working is 1501 which was released on 2007-10-26.
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900757 * Enable 64bit DMA on 1501 and anything newer.
758 *
Tejun Heo03d783b2009-08-16 21:04:02 +0900759 * Please read bko#9412 for more info.
760 */
Shane Huang58a09b32009-05-27 15:04:43 +0800761 {
762 .ident = "ASUS M2A-VM",
763 .matches = {
764 DMI_MATCH(DMI_BOARD_VENDOR,
765 "ASUSTeK Computer INC."),
766 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
767 },
Tejun Heo03d783b2009-08-16 21:04:02 +0900768 .driver_data = "20071026", /* yyyymmdd */
Shane Huang58a09b32009-05-27 15:04:43 +0800769 },
Mark Nelsone65cc192009-11-03 20:06:48 +1100770 /*
771 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
772 * support 64bit DMA.
773 *
774 * BIOS versions earlier than 1.5 had the Manufacturer DMI
775 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
776 * This spelling mistake was fixed in BIOS version 1.5, so
777 * 1.5 and later have the Manufacturer as
778 * "MICRO-STAR INTERNATIONAL CO.,LTD".
779 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
780 *
781 * BIOS versions earlier than 1.9 had a Board Product Name
782 * DMI field of "MS-7376". This was changed to be
783 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
784 * match on DMI_BOARD_NAME of "MS-7376".
785 */
786 {
787 .ident = "MSI K9A2 Platinum",
788 .matches = {
789 DMI_MATCH(DMI_BOARD_VENDOR,
790 "MICRO-STAR INTER"),
791 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
792 },
793 },
Shane Huang58a09b32009-05-27 15:04:43 +0800794 { }
795 };
Tejun Heo03d783b2009-08-16 21:04:02 +0900796 const struct dmi_system_id *match;
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900797 int year, month, date;
798 char buf[9];
Shane Huang58a09b32009-05-27 15:04:43 +0800799
Tejun Heo03d783b2009-08-16 21:04:02 +0900800 match = dmi_first_match(sysids);
Shane Huang58a09b32009-05-27 15:04:43 +0800801 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
Tejun Heo03d783b2009-08-16 21:04:02 +0900802 !match)
Shane Huang58a09b32009-05-27 15:04:43 +0800803 return false;
804
Mark Nelsone65cc192009-11-03 20:06:48 +1100805 if (!match->driver_data)
806 goto enable_64bit;
807
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900808 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
809 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Shane Huang58a09b32009-05-27 15:04:43 +0800810
Mark Nelsone65cc192009-11-03 20:06:48 +1100811 if (strcmp(buf, match->driver_data) >= 0)
812 goto enable_64bit;
813 else {
Tejun Heo03d783b2009-08-16 21:04:02 +0900814 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
815 "forcing 32bit DMA, update BIOS\n", match->ident);
Tejun Heo2fcad9d2009-10-03 18:27:29 +0900816 return false;
817 }
Mark Nelsone65cc192009-11-03 20:06:48 +1100818
819enable_64bit:
820 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
821 match->ident);
822 return true;
Shane Huang58a09b32009-05-27 15:04:43 +0800823}
824
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +0100825static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
826{
827 static const struct dmi_system_id broken_systems[] = {
828 {
829 .ident = "HP Compaq nx6310",
830 .matches = {
831 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
832 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
833 },
834 /* PCI slot number of the controller */
835 .driver_data = (void *)0x1FUL,
836 },
Maciej Ruteckid2f9c062009-03-20 00:06:46 +0100837 {
838 .ident = "HP Compaq 6720s",
839 .matches = {
840 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
841 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
842 },
843 /* PCI slot number of the controller */
844 .driver_data = (void *)0x1FUL,
845 },
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +0100846
847 { } /* terminate list */
848 };
849 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
850
851 if (dmi) {
852 unsigned long slot = (unsigned long)dmi->driver_data;
853 /* apply the quirk only to on-board controllers */
854 return slot == PCI_SLOT(pdev->devfn);
855 }
856
857 return false;
858}
859
Tejun Heo9b10ae82009-05-30 20:50:12 +0900860static bool ahci_broken_suspend(struct pci_dev *pdev)
861{
862 static const struct dmi_system_id sysids[] = {
863 /*
864 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
865 * to the harddisk doesn't become online after
866 * resuming from STR. Warn and fail suspend.
Tejun Heo9deb3432010-03-16 09:50:26 +0900867 *
868 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
869 *
870 * Use dates instead of versions to match as HP is
871 * apparently recycling both product and version
872 * strings.
873 *
874 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
Tejun Heo9b10ae82009-05-30 20:50:12 +0900875 */
876 {
877 .ident = "dv4",
878 .matches = {
879 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
880 DMI_MATCH(DMI_PRODUCT_NAME,
881 "HP Pavilion dv4 Notebook PC"),
882 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900883 .driver_data = "20090105", /* F.30 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900884 },
885 {
886 .ident = "dv5",
887 .matches = {
888 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
889 DMI_MATCH(DMI_PRODUCT_NAME,
890 "HP Pavilion dv5 Notebook PC"),
891 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900892 .driver_data = "20090506", /* F.16 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900893 },
894 {
895 .ident = "dv6",
896 .matches = {
897 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
898 DMI_MATCH(DMI_PRODUCT_NAME,
899 "HP Pavilion dv6 Notebook PC"),
900 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900901 .driver_data = "20090423", /* F.21 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900902 },
903 {
904 .ident = "HDX18",
905 .matches = {
906 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
907 DMI_MATCH(DMI_PRODUCT_NAME,
908 "HP HDX18 Notebook PC"),
909 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900910 .driver_data = "20090430", /* F.23 */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900911 },
Tejun Heocedc9bf2010-01-28 16:04:15 +0900912 /*
913 * Acer eMachines G725 has the same problem. BIOS
914 * V1.03 is known to be broken. V3.04 is known to
915 * work. Inbetween, there are V1.06, V2.06 and V3.03
916 * that we don't have much idea about. For now,
917 * blacklist anything older than V3.04.
Tejun Heo9deb3432010-03-16 09:50:26 +0900918 *
919 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
Tejun Heocedc9bf2010-01-28 16:04:15 +0900920 */
921 {
922 .ident = "G725",
923 .matches = {
924 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
925 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
926 },
Tejun Heo9deb3432010-03-16 09:50:26 +0900927 .driver_data = "20091216", /* V3.04 */
Tejun Heocedc9bf2010-01-28 16:04:15 +0900928 },
Tejun Heo9b10ae82009-05-30 20:50:12 +0900929 { } /* terminate list */
930 };
931 const struct dmi_system_id *dmi = dmi_first_match(sysids);
Tejun Heo9deb3432010-03-16 09:50:26 +0900932 int year, month, date;
933 char buf[9];
Tejun Heo9b10ae82009-05-30 20:50:12 +0900934
935 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
936 return false;
937
Tejun Heo9deb3432010-03-16 09:50:26 +0900938 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
939 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
Tejun Heo9b10ae82009-05-30 20:50:12 +0900940
Tejun Heo9deb3432010-03-16 09:50:26 +0900941 return strcmp(buf, dmi->driver_data) < 0;
Tejun Heo9b10ae82009-05-30 20:50:12 +0900942}
943
Tejun Heo55946392009-08-04 14:30:08 +0900944static bool ahci_broken_online(struct pci_dev *pdev)
945{
946#define ENCODE_BUSDEVFN(bus, slot, func) \
947 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
948 static const struct dmi_system_id sysids[] = {
949 /*
950 * There are several gigabyte boards which use
951 * SIMG5723s configured as hardware RAID. Certain
952 * 5723 firmware revisions shipped there keep the link
953 * online but fail to answer properly to SRST or
954 * IDENTIFY when no device is attached downstream
955 * causing libata to retry quite a few times leading
956 * to excessive detection delay.
957 *
958 * As these firmwares respond to the second reset try
959 * with invalid device signature, considering unknown
960 * sig as offline works around the problem acceptably.
961 */
962 {
963 .ident = "EP45-DQ6",
964 .matches = {
965 DMI_MATCH(DMI_BOARD_VENDOR,
966 "Gigabyte Technology Co., Ltd."),
967 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
968 },
969 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
970 },
971 {
972 .ident = "EP45-DS5",
973 .matches = {
974 DMI_MATCH(DMI_BOARD_VENDOR,
975 "Gigabyte Technology Co., Ltd."),
976 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
977 },
978 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
979 },
980 { } /* terminate list */
981 };
982#undef ENCODE_BUSDEVFN
983 const struct dmi_system_id *dmi = dmi_first_match(sysids);
984 unsigned int val;
985
986 if (!dmi)
987 return false;
988
989 val = (unsigned long)dmi->driver_data;
990
991 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
992}
993
Markus Trippelsdorf8e513212009-10-09 05:41:47 +0200994#ifdef CONFIG_ATA_ACPI
Tejun Heof80ae7e2009-09-16 04:18:03 +0900995static void ahci_gtf_filter_workaround(struct ata_host *host)
996{
997 static const struct dmi_system_id sysids[] = {
998 /*
999 * Aspire 3810T issues a bunch of SATA enable commands
1000 * via _GTF including an invalid one and one which is
1001 * rejected by the device. Among the successful ones
1002 * is FPDMA non-zero offset enable which when enabled
1003 * only on the drive side leads to NCQ command
1004 * failures. Filter it out.
1005 */
1006 {
1007 .ident = "Aspire 3810T",
1008 .matches = {
1009 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1010 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1011 },
1012 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1013 },
1014 { }
1015 };
1016 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1017 unsigned int filter;
1018 int i;
1019
1020 if (!dmi)
1021 return;
1022
1023 filter = (unsigned long)dmi->driver_data;
1024 dev_printk(KERN_INFO, host->dev,
1025 "applying extra ACPI _GTF filter 0x%x for %s\n",
1026 filter, dmi->ident);
1027
1028 for (i = 0; i < host->n_ports; i++) {
1029 struct ata_port *ap = host->ports[i];
1030 struct ata_link *link;
1031 struct ata_device *dev;
1032
1033 ata_for_each_link(link, ap, EDGE)
1034 ata_for_each_dev(dev, link, ALL)
1035 dev->gtf_filter |= filter;
1036 }
1037}
Markus Trippelsdorf8e513212009-10-09 05:41:47 +02001038#else
1039static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1040{}
1041#endif
Tejun Heof80ae7e2009-09-16 04:18:03 +09001042
Tejun Heo24dc5f32007-01-20 16:00:28 +09001043static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001044{
1045 static int printed_version;
Tejun Heoe297d992008-06-10 00:13:04 +09001046 unsigned int board_id = ent->driver_data;
1047 struct ata_port_info pi = ahci_port_info[board_id];
Tejun Heo4447d352007-04-17 23:44:08 +09001048 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09001049 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001050 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09001051 struct ata_host *host;
Tejun Heo837f5f82008-02-06 15:13:51 +09001052 int n_ports, i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001053
1054 VPRINTK("ENTER\n");
1055
Justin P. Mattockb429dd52010-07-03 07:29:25 -07001056 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001057
Linus Torvalds1da177e2005-04-16 15:20:36 -07001058 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05001059 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001060
Alan Cox5b66c822008-09-03 14:48:34 +01001061 /* The AHCI driver can only drive the SATA ports, the PATA driver
1062 can drive them all so if both drivers are selected make sure
1063 AHCI stays out of the way */
1064 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1065 return -ENODEV;
1066
Tejun Heoc6353b42010-06-17 11:42:22 +02001067 /*
1068 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1069 * ahci, use ata_generic instead.
1070 */
1071 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1072 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1073 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1074 pdev->subsystem_device == 0xcb89)
1075 return -ENODEV;
1076
Mark Nelson7a022672009-11-22 12:07:41 +11001077 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1078 * At the moment, we can only use the AHCI mode. Let the users know
1079 * that for SAS drives they're out of luck.
1080 */
1081 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1082 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1083 "can only drive SATA devices with this driver\n");
1084
Tejun Heo4447d352007-04-17 23:44:08 +09001085 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09001086 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001087 if (rc)
1088 return rc;
1089
Tejun Heodea55132008-03-11 19:52:31 +09001090 /* AHCI controllers often implement SFF compatible interface.
1091 * Grab all PCI BARs just in case.
1092 */
1093 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001094 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001095 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001096 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001097 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098
Tejun Heoc4f77922007-12-06 15:09:43 +09001099 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1100 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1101 u8 map;
1102
1103 /* ICH6s share the same PCI ID for both piix and ahci
1104 * modes. Enabling ahci mode while MAP indicates
1105 * combined mode is a bad idea. Yield to ata_piix.
1106 */
1107 pci_read_config_byte(pdev, ICH_MAP, &map);
1108 if (map & 0x3) {
1109 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1110 "combined mode, can't enable AHCI mode\n");
1111 return -ENODEV;
1112 }
1113 }
1114
Tejun Heo24dc5f32007-01-20 16:00:28 +09001115 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1116 if (!hpriv)
1117 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09001118 hpriv->flags |= (unsigned long)pi.private_data;
1119
Tejun Heoe297d992008-06-10 00:13:04 +09001120 /* MCP65 revision A1 and A2 can't do MSI */
1121 if (board_id == board_ahci_mcp65 &&
1122 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1123 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1124
Shane Huange427fe02008-12-30 10:53:41 +08001125 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1126 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1127 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1128
Tejun Heo2fcad9d2009-10-03 18:27:29 +09001129 /* only some SB600s can do 64bit DMA */
1130 if (ahci_sb600_enable_64bit(pdev))
1131 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
Shane Huang58a09b32009-05-27 15:04:43 +08001132
Tejun Heo31b239a2009-09-17 00:34:39 +09001133 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1134 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001135
Anton Vorontsovd8993342010-03-03 20:17:34 +03001136 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1137
Tejun Heo4447d352007-04-17 23:44:08 +09001138 /* save initial config */
Anton Vorontsov394d6e52010-03-03 20:17:36 +03001139 ahci_pci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140
Tejun Heo4447d352007-04-17 23:44:08 +09001141 /* prepare host */
Robert Hancock453d3132010-01-26 22:33:23 -06001142 if (hpriv->cap & HOST_CAP_NCQ) {
1143 pi.flags |= ATA_FLAG_NCQ;
Tejun Heo83f2b962010-03-30 10:28:32 +09001144 /*
1145 * Auto-activate optimization is supposed to be
1146 * supported on all AHCI controllers indicating NCQ
1147 * capability, but it seems to be broken on some
1148 * chipsets including NVIDIAs.
1149 */
1150 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
Robert Hancock453d3132010-01-26 22:33:23 -06001151 pi.flags |= ATA_FLAG_FPDMA_AA;
1152 }
Tejun Heo4447d352007-04-17 23:44:08 +09001153
Tejun Heo7d50b602007-09-23 13:19:54 +09001154 if (hpriv->cap & HOST_CAP_PMP)
1155 pi.flags |= ATA_FLAG_PMP;
1156
Anton Vorontsov0cbb0e72010-03-03 20:17:45 +03001157 ahci_set_em_messages(hpriv, &pi);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001158
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01001159 if (ahci_broken_system_poweroff(pdev)) {
1160 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1161 dev_info(&pdev->dev,
1162 "quirky BIOS, skipping spindown on poweroff\n");
1163 }
1164
Tejun Heo9b10ae82009-05-30 20:50:12 +09001165 if (ahci_broken_suspend(pdev)) {
1166 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1167 dev_printk(KERN_WARNING, &pdev->dev,
1168 "BIOS update required for suspend/resume\n");
1169 }
1170
Tejun Heo55946392009-08-04 14:30:08 +09001171 if (ahci_broken_online(pdev)) {
1172 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1173 dev_info(&pdev->dev,
1174 "online status unreliable, applying workaround\n");
1175 }
1176
Tejun Heo837f5f82008-02-06 15:13:51 +09001177 /* CAP.NP sometimes indicate the index of the last enabled
1178 * port, at other times, that of the last possible port, so
1179 * determining the maximum port number requires looking at
1180 * both CAP.NP and port_map.
1181 */
1182 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1183
1184 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09001185 if (!host)
1186 return -ENOMEM;
Tejun Heo4447d352007-04-17 23:44:08 +09001187 host->private_data = hpriv;
1188
Arjan van de Venf3d7f232009-01-26 02:05:44 -08001189 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
Arjan van de Ven886ad092009-01-09 15:54:07 -08001190 host->flags |= ATA_HOST_PARALLEL_SCAN;
Arjan van de Venf3d7f232009-01-26 02:05:44 -08001191 else
1192 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
Arjan van de Ven886ad092009-01-09 15:54:07 -08001193
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001194 if (pi.flags & ATA_FLAG_EM)
1195 ahci_reset_em(host);
1196
Tejun Heo4447d352007-04-17 23:44:08 +09001197 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04001198 struct ata_port *ap = host->ports[i];
Tejun Heo4447d352007-04-17 23:44:08 +09001199
Tejun Heocbcdd872007-08-18 13:14:55 +09001200 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1201 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1202 0x100 + ap->port_no * 0x80, "port");
1203
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04001204 /* set initial link pm policy */
1205 ap->pm_policy = NOT_AVAILABLE;
1206
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001207 /* set enclosure management message type */
1208 if (ap->flags & ATA_FLAG_EM)
Harry Zhang008dbd62010-04-23 17:27:19 +08001209 ap->em_message_type = hpriv->em_msg_type;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001210
1211
Jeff Garzikdab632e2007-05-28 08:33:01 -04001212 /* disabled/not-implemented port */
Tejun Heo350756f2008-04-07 22:47:21 +09001213 if (!(hpriv->port_map & (1 << i)))
Jeff Garzikdab632e2007-05-28 08:33:01 -04001214 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09001215 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001216
Tejun Heoedc93052007-10-25 14:59:16 +09001217 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1218 ahci_p5wdh_workaround(host);
1219
Tejun Heof80ae7e2009-09-16 04:18:03 +09001220 /* apply gtf filter quirk */
1221 ahci_gtf_filter_workaround(host);
1222
Linus Torvalds1da177e2005-04-16 15:20:36 -07001223 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09001224 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001225 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09001226 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227
Anton Vorontsov33030402010-03-03 20:17:39 +03001228 rc = ahci_pci_reset_controller(host);
Tejun Heo4447d352007-04-17 23:44:08 +09001229 if (rc)
1230 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09001231
Anton Vorontsov781d6552010-03-03 20:17:42 +03001232 ahci_pci_init_controller(host);
Anton Vorontsov439fcae2010-03-03 20:17:43 +03001233 ahci_pci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001234
Tejun Heo4447d352007-04-17 23:44:08 +09001235 pci_set_master(pdev);
1236 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1237 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04001238}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001239
1240static int __init ahci_init(void)
1241{
Pavel Roskinb7887192006-08-10 18:13:18 +09001242 return pci_register_driver(&ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001243}
1244
Linus Torvalds1da177e2005-04-16 15:20:36 -07001245static void __exit ahci_exit(void)
1246{
1247 pci_unregister_driver(&ahci_pci_driver);
1248}
1249
1250
1251MODULE_AUTHOR("Jeff Garzik");
1252MODULE_DESCRIPTION("AHCI SATA low-level driver");
1253MODULE_LICENSE("GPL");
1254MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04001255MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001256
1257module_init(ahci_init);
1258module_exit(ahci_exit);