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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090044#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050046#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <linux/libata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090050#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
Kristen Carlson Accardi31556592007-10-25 01:33:26 -040052static int ahci_enable_alpm(struct ata_port *ap,
53 enum link_pm policy);
54static void ahci_disable_alpm(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -070055
56enum {
57 AHCI_PCI_BAR = 5,
Tejun Heo648a88b2006-11-09 15:08:40 +090058 AHCI_MAX_PORTS = 32,
Linus Torvalds1da177e2005-04-16 15:20:36 -070059 AHCI_MAX_SG = 168, /* hardware max is 64K */
60 AHCI_DMA_BOUNDARY = 0xffffffff,
Jens Axboebe5d8212007-05-22 09:45:39 +020061 AHCI_USE_CLUSTERING = 1,
Tejun Heo12fad3f2006-05-15 21:03:55 +090062 AHCI_MAX_CMDS = 32,
Tejun Heodd410ff2006-05-15 21:03:50 +090063 AHCI_CMD_SZ = 32,
Tejun Heo12fad3f2006-05-15 21:03:55 +090064 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
Linus Torvalds1da177e2005-04-16 15:20:36 -070065 AHCI_RX_FIS_SZ = 256,
Jeff Garzika0ea7322005-06-04 01:13:15 -040066 AHCI_CMD_TBL_CDB = 0x40,
Tejun Heodd410ff2006-05-15 21:03:50 +090067 AHCI_CMD_TBL_HDR_SZ = 0x80,
68 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
69 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
70 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
Linus Torvalds1da177e2005-04-16 15:20:36 -070071 AHCI_RX_FIS_SZ,
72 AHCI_IRQ_ON_SG = (1 << 31),
73 AHCI_CMD_ATAPI = (1 << 5),
74 AHCI_CMD_WRITE = (1 << 6),
Tejun Heo4b10e552006-03-12 11:25:27 +090075 AHCI_CMD_PREFETCH = (1 << 7),
Tejun Heo22b49982006-01-23 21:38:44 +090076 AHCI_CMD_RESET = (1 << 8),
77 AHCI_CMD_CLR_BUSY = (1 << 10),
Linus Torvalds1da177e2005-04-16 15:20:36 -070078
79 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
Tejun Heo0291f952007-01-25 19:16:28 +090080 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
Tejun Heo78cd52d2006-05-15 20:58:29 +090081 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -070082
83 board_ahci = 0,
Tejun Heo7a234af2007-09-03 12:44:57 +090084 board_ahci_vt8251 = 1,
85 board_ahci_ign_iferr = 2,
86 board_ahci_sb600 = 3,
87 board_ahci_mv = 4,
Linus Torvalds1da177e2005-04-16 15:20:36 -070088
89 /* global controller registers */
90 HOST_CAP = 0x00, /* host capabilities */
91 HOST_CTL = 0x04, /* global host control */
92 HOST_IRQ_STAT = 0x08, /* interrupt status */
93 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
94 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
95
96 /* HOST_CTL bits */
97 HOST_RESET = (1 << 0), /* reset controller; self-clear */
98 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
99 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
100
101 /* HOST_CAP bits */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900102 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
Tejun Heo7d50b602007-09-23 13:19:54 +0900103 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
Tejun Heo22b49982006-01-23 21:38:44 +0900104 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400105 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900106 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900107 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
Tejun Heo979db802006-05-15 21:03:52 +0900108 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
Tejun Heodd410ff2006-05-15 21:03:50 +0900109 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700110
111 /* registers for each SATA port */
112 PORT_LST_ADDR = 0x00, /* command list DMA addr */
113 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
114 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
115 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
116 PORT_IRQ_STAT = 0x10, /* interrupt status */
117 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
118 PORT_CMD = 0x18, /* port command */
119 PORT_TFDATA = 0x20, /* taskfile data */
120 PORT_SIG = 0x24, /* device TF signature */
121 PORT_CMD_ISSUE = 0x38, /* command issue */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
123 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
124 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
125 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900126 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700127
128 /* PORT_IRQ_{STAT,MASK} bits */
129 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
130 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
131 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
132 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
133 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
134 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
135 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
136 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
137
138 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
139 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
140 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
141 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
142 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
143 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
144 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
145 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
146 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
147
Tejun Heo78cd52d2006-05-15 20:58:29 +0900148 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
149 PORT_IRQ_IF_ERR |
150 PORT_IRQ_CONNECT |
Tejun Heo42969712006-05-31 18:28:18 +0900151 PORT_IRQ_PHYRDY |
Tejun Heo7d50b602007-09-23 13:19:54 +0900152 PORT_IRQ_UNK_FIS |
153 PORT_IRQ_BAD_PMP,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900154 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
155 PORT_IRQ_TF_ERR |
156 PORT_IRQ_HBUS_DATA_ERR,
157 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
158 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
159 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160
161 /* PORT_CMD bits */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400162 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
163 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500164 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Tejun Heo7d50b602007-09-23 13:19:54 +0900165 PORT_CMD_PMP = (1 << 17), /* PMP attached */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
167 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
168 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
Tejun Heo22b49982006-01-23 21:38:44 +0900169 PORT_CMD_CLO = (1 << 3), /* Command list override */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
171 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
172 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
173
Tejun Heo0be0aa92006-07-26 15:59:26 +0900174 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
176 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
177 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400178
Tejun Heo417a1a62007-09-23 13:19:55 +0900179 /* hpriv->flags bits */
180 AHCI_HFLAG_NO_NCQ = (1 << 0),
181 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
182 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
183 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
184 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
185 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
Tejun Heo6949b912007-09-23 13:19:55 +0900186 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400187 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
Tejun Heo417a1a62007-09-23 13:19:55 +0900188
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200189 /* ap->flags bits */
Tejun Heo1188c0d2007-04-23 02:41:05 +0900190
191 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
192 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400193 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
194 ATA_FLAG_IPM,
Tejun Heo0c887582007-08-06 18:36:23 +0900195 AHCI_LFLAG_COMMON = ATA_LFLAG_SKIP_D2H_BSY,
Tejun Heoc4f77922007-12-06 15:09:43 +0900196
197 ICH_MAP = 0x90, /* ICH MAP register */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700198};
199
200struct ahci_cmd_hdr {
Al Viro4ca4e432007-12-30 09:32:22 +0000201 __le32 opts;
202 __le32 status;
203 __le32 tbl_addr;
204 __le32 tbl_addr_hi;
205 __le32 reserved[4];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206};
207
208struct ahci_sg {
Al Viro4ca4e432007-12-30 09:32:22 +0000209 __le32 addr;
210 __le32 addr_hi;
211 __le32 reserved;
212 __le32 flags_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700213};
214
215struct ahci_host_priv {
Tejun Heo417a1a62007-09-23 13:19:55 +0900216 unsigned int flags; /* AHCI_HFLAG_* */
Tejun Heod447df12007-03-18 22:15:33 +0900217 u32 cap; /* cap to use */
218 u32 port_map; /* port map to use */
219 u32 saved_cap; /* saved initial cap */
220 u32 saved_port_map; /* saved initial port_map */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221};
222
223struct ahci_port_priv {
Tejun Heo7d50b602007-09-23 13:19:54 +0900224 struct ata_link *active_link;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225 struct ahci_cmd_hdr *cmd_slot;
226 dma_addr_t cmd_slot_dma;
227 void *cmd_tbl;
228 dma_addr_t cmd_tbl_dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229 void *rx_fis;
230 dma_addr_t rx_fis_dma;
Tejun Heo0291f952007-01-25 19:16:28 +0900231 /* for NCQ spurious interrupt analysis */
Tejun Heo0291f952007-01-25 19:16:28 +0900232 unsigned int ncq_saw_d2h:1;
233 unsigned int ncq_saw_dmas:1;
Tejun Heoafb2d552007-02-27 13:24:19 +0900234 unsigned int ncq_saw_sdb:1;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -0700235 u32 intr_mask; /* interrupts to enable */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236};
237
Tejun Heoda3dbb12007-07-16 14:29:40 +0900238static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val);
239static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400240static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900241static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242static void ahci_irq_clear(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700243static int ahci_port_start(struct ata_port *ap);
244static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
246static void ahci_qc_prep(struct ata_queued_cmd *qc);
247static u8 ahci_check_status(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900248static void ahci_freeze(struct ata_port *ap);
249static void ahci_thaw(struct ata_port *ap);
Tejun Heo7d50b602007-09-23 13:19:54 +0900250static void ahci_pmp_attach(struct ata_port *ap);
251static void ahci_pmp_detach(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900252static void ahci_error_handler(struct ata_port *ap);
Tejun Heoad616ff2006-11-01 18:00:24 +0900253static void ahci_vt8251_error_handler(struct ata_port *ap);
Tejun Heoedc93052007-10-25 14:59:16 +0900254static void ahci_p5wdh_error_handler(struct ata_port *ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900255static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400256static int ahci_port_resume(struct ata_port *ap);
Jeff Garzikdab632e2007-05-28 08:33:01 -0400257static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl);
258static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
259 u32 opts);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900260#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900261static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
Tejun Heoc1332872006-07-26 15:59:26 +0900262static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
263static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900264#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700265
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400266static struct class_device_attribute *ahci_shost_attrs[] = {
267 &class_device_attr_link_power_management_policy,
268 NULL
269};
270
Jeff Garzik193515d2005-11-07 00:59:37 -0500271static struct scsi_host_template ahci_sht = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 .module = THIS_MODULE,
273 .name = DRV_NAME,
274 .ioctl = ata_scsi_ioctl,
275 .queuecommand = ata_scsi_queuecmd,
Tejun Heo12fad3f2006-05-15 21:03:55 +0900276 .change_queue_depth = ata_scsi_change_queue_depth,
277 .can_queue = AHCI_MAX_CMDS - 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278 .this_id = ATA_SHT_THIS_ID,
279 .sg_tablesize = AHCI_MAX_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
281 .emulated = ATA_SHT_EMULATED,
282 .use_clustering = AHCI_USE_CLUSTERING,
283 .proc_name = DRV_NAME,
284 .dma_boundary = AHCI_DMA_BOUNDARY,
285 .slave_configure = ata_scsi_slave_config,
Tejun Heoccf68c32006-05-31 18:28:09 +0900286 .slave_destroy = ata_scsi_slave_destroy,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287 .bios_param = ata_std_bios_param,
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400288 .shost_attrs = ahci_shost_attrs,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289};
290
Jeff Garzik057ace52005-10-22 14:27:05 -0400291static const struct ata_port_operations ahci_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700292 .check_status = ahci_check_status,
293 .check_altstatus = ahci_check_status,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294 .dev_select = ata_noop_dev_select,
295
296 .tf_read = ahci_tf_read,
297
Tejun Heo7d50b602007-09-23 13:19:54 +0900298 .qc_defer = sata_pmp_qc_defer_cmd_switch,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700299 .qc_prep = ahci_qc_prep,
300 .qc_issue = ahci_qc_issue,
301
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302 .irq_clear = ahci_irq_clear,
303
304 .scr_read = ahci_scr_read,
305 .scr_write = ahci_scr_write,
306
Tejun Heo78cd52d2006-05-15 20:58:29 +0900307 .freeze = ahci_freeze,
308 .thaw = ahci_thaw,
309
310 .error_handler = ahci_error_handler,
311 .post_internal_cmd = ahci_post_internal_cmd,
312
Tejun Heo7d50b602007-09-23 13:19:54 +0900313 .pmp_attach = ahci_pmp_attach,
314 .pmp_detach = ahci_pmp_detach,
Tejun Heo7d50b602007-09-23 13:19:54 +0900315
Tejun Heo438ac6d2007-03-02 17:31:26 +0900316#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900317 .port_suspend = ahci_port_suspend,
318 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900319#endif
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400320 .enable_pm = ahci_enable_alpm,
321 .disable_pm = ahci_disable_alpm,
Tejun Heoc1332872006-07-26 15:59:26 +0900322
Linus Torvalds1da177e2005-04-16 15:20:36 -0700323 .port_start = ahci_port_start,
324 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325};
326
Tejun Heoad616ff2006-11-01 18:00:24 +0900327static const struct ata_port_operations ahci_vt8251_ops = {
Tejun Heoad616ff2006-11-01 18:00:24 +0900328 .check_status = ahci_check_status,
329 .check_altstatus = ahci_check_status,
330 .dev_select = ata_noop_dev_select,
331
332 .tf_read = ahci_tf_read,
333
Tejun Heo7d50b602007-09-23 13:19:54 +0900334 .qc_defer = sata_pmp_qc_defer_cmd_switch,
Tejun Heoad616ff2006-11-01 18:00:24 +0900335 .qc_prep = ahci_qc_prep,
336 .qc_issue = ahci_qc_issue,
337
Tejun Heoad616ff2006-11-01 18:00:24 +0900338 .irq_clear = ahci_irq_clear,
339
340 .scr_read = ahci_scr_read,
341 .scr_write = ahci_scr_write,
342
343 .freeze = ahci_freeze,
344 .thaw = ahci_thaw,
345
346 .error_handler = ahci_vt8251_error_handler,
347 .post_internal_cmd = ahci_post_internal_cmd,
348
Tejun Heo7d50b602007-09-23 13:19:54 +0900349 .pmp_attach = ahci_pmp_attach,
350 .pmp_detach = ahci_pmp_detach,
Tejun Heo7d50b602007-09-23 13:19:54 +0900351
Tejun Heo438ac6d2007-03-02 17:31:26 +0900352#ifdef CONFIG_PM
Tejun Heoad616ff2006-11-01 18:00:24 +0900353 .port_suspend = ahci_port_suspend,
354 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900355#endif
Tejun Heoad616ff2006-11-01 18:00:24 +0900356
357 .port_start = ahci_port_start,
358 .port_stop = ahci_port_stop,
359};
360
Tejun Heoedc93052007-10-25 14:59:16 +0900361static const struct ata_port_operations ahci_p5wdh_ops = {
362 .check_status = ahci_check_status,
363 .check_altstatus = ahci_check_status,
364 .dev_select = ata_noop_dev_select,
365
366 .tf_read = ahci_tf_read,
367
368 .qc_defer = sata_pmp_qc_defer_cmd_switch,
369 .qc_prep = ahci_qc_prep,
370 .qc_issue = ahci_qc_issue,
371
372 .irq_clear = ahci_irq_clear,
373
374 .scr_read = ahci_scr_read,
375 .scr_write = ahci_scr_write,
376
377 .freeze = ahci_freeze,
378 .thaw = ahci_thaw,
379
380 .error_handler = ahci_p5wdh_error_handler,
381 .post_internal_cmd = ahci_post_internal_cmd,
382
383 .pmp_attach = ahci_pmp_attach,
384 .pmp_detach = ahci_pmp_detach,
385
386#ifdef CONFIG_PM
387 .port_suspend = ahci_port_suspend,
388 .port_resume = ahci_port_resume,
389#endif
390
391 .port_start = ahci_port_start,
392 .port_stop = ahci_port_stop,
393};
394
Tejun Heo417a1a62007-09-23 13:19:55 +0900395#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
396
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100397static const struct ata_port_info ahci_port_info[] = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398 /* board_ahci */
399 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900400 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900401 .link_flags = AHCI_LFLAG_COMMON,
Brett Russ7da79312005-09-01 21:53:34 -0400402 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400403 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700404 .port_ops = &ahci_ops,
405 },
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200406 /* board_ahci_vt8251 */
407 {
Tejun Heo6949b912007-09-23 13:19:55 +0900408 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heo417a1a62007-09-23 13:19:55 +0900409 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900410 .link_flags = AHCI_LFLAG_COMMON | ATA_LFLAG_HRST_TO_RESUME,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200411 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400412 .udma_mask = ATA_UDMA6,
Tejun Heoad616ff2006-11-01 18:00:24 +0900413 .port_ops = &ahci_vt8251_ops,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200414 },
Tejun Heo41669552006-11-29 11:33:14 +0900415 /* board_ahci_ign_iferr */
416 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900417 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
418 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900419 .link_flags = AHCI_LFLAG_COMMON,
Tejun Heo41669552006-11-29 11:33:14 +0900420 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400421 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900422 .port_ops = &ahci_ops,
423 },
Conke Hu55a61602007-03-27 18:33:05 +0800424 /* board_ahci_sb600 */
425 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900426 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Tejun Heo6949b912007-09-23 13:19:55 +0900427 AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_PMP),
Tejun Heo417a1a62007-09-23 13:19:55 +0900428 .flags = AHCI_FLAG_COMMON,
Tejun Heo0c887582007-08-06 18:36:23 +0900429 .link_flags = AHCI_LFLAG_COMMON,
Conke Hu55a61602007-03-27 18:33:05 +0800430 .pio_mask = 0x1f, /* pio0-4 */
Jeff Garzik469248a2007-07-08 01:13:16 -0400431 .udma_mask = ATA_UDMA6,
Conke Hu55a61602007-03-27 18:33:05 +0800432 .port_ops = &ahci_ops,
433 },
Jeff Garzikcd70c262007-07-08 02:29:42 -0400434 /* board_ahci_mv */
435 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900436 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
437 AHCI_HFLAG_MV_PATA),
Jeff Garzikcd70c262007-07-08 02:29:42 -0400438 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heo417a1a62007-09-23 13:19:55 +0900439 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
Tejun Heo0c887582007-08-06 18:36:23 +0900440 .link_flags = AHCI_LFLAG_COMMON,
Jeff Garzikcd70c262007-07-08 02:29:42 -0400441 .pio_mask = 0x1f, /* pio0-4 */
442 .udma_mask = ATA_UDMA6,
443 .port_ops = &ahci_ops,
444 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445};
446
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500447static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400448 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400449 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
450 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
451 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
452 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
453 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900454 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400455 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
456 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
457 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
458 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900459 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
460 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
461 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
462 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
463 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
464 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
465 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
466 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
467 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
468 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
469 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
470 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
471 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
472 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
473 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
474 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
475 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400476 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
477 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800478 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
479 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400480
Tejun Heoe34bb372007-02-26 20:24:03 +0900481 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
482 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
483 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400484
485 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800486 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
henry suc69c0892007-09-20 16:07:33 -0400487 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb600 }, /* ATI SB700/800 */
488 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb600 }, /* ATI SB700/800 */
489 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb600 }, /* ATI SB700/800 */
490 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb600 }, /* ATI SB700/800 */
491 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb600 }, /* ATI SB700/800 */
492 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb600 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400493
494 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400495 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900496 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400497
498 /* NVIDIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400499 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci }, /* MCP65 */
500 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci }, /* MCP65 */
501 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci }, /* MCP65 */
502 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci }, /* MCP65 */
Peer Chen6fbf5ba2006-12-20 14:18:00 -0500503 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci }, /* MCP65 */
504 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci }, /* MCP65 */
505 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci }, /* MCP65 */
506 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci }, /* MCP65 */
507 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci }, /* MCP67 */
508 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci }, /* MCP67 */
509 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci }, /* MCP67 */
510 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci }, /* MCP67 */
Peer Chen895663c2006-11-02 17:59:46 -0500511 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci }, /* MCP67 */
512 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci }, /* MCP67 */
513 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci }, /* MCP67 */
514 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci }, /* MCP67 */
515 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci }, /* MCP67 */
516 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci }, /* MCP67 */
517 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci }, /* MCP67 */
518 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci }, /* MCP67 */
Peer Chen0522b282007-06-07 18:05:12 +0800519 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci }, /* MCP73 */
520 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci }, /* MCP73 */
521 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci }, /* MCP73 */
522 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci }, /* MCP73 */
523 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci }, /* MCP73 */
524 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci }, /* MCP73 */
525 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci }, /* MCP73 */
526 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci }, /* MCP73 */
527 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci }, /* MCP73 */
528 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci }, /* MCP73 */
529 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci }, /* MCP73 */
530 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci }, /* MCP73 */
531 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
532 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
533 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
534 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
535 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
536 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
537 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
538 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
539 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
540 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
541 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
542 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
peerchen6ba86952007-12-03 22:20:37 +0800543 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
544 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
545 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
546 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
Peer Chen71008192007-09-24 10:16:25 +0800547 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
548 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
549 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
550 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
551 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
552 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
553 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
554 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400555
Jeff Garzik95916ed2006-07-29 04:10:14 -0400556 /* SiS */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400557 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
558 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 966 */
559 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400560
Jeff Garzikcd70c262007-07-08 02:29:42 -0400561 /* Marvell */
562 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
563
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500564 /* Generic, PCI class code for AHCI */
565 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500566 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500567
Linus Torvalds1da177e2005-04-16 15:20:36 -0700568 { } /* terminate list */
569};
570
571
572static struct pci_driver ahci_pci_driver = {
573 .name = DRV_NAME,
574 .id_table = ahci_pci_tbl,
575 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900576 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900577#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900578 .suspend = ahci_pci_device_suspend,
579 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900580#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581};
582
583
Tejun Heo98fa4b62006-11-02 12:17:23 +0900584static inline int ahci_nr_ports(u32 cap)
585{
586 return (cap & 0x1f) + 1;
587}
588
Jeff Garzikdab632e2007-05-28 08:33:01 -0400589static inline void __iomem *__ahci_port_base(struct ata_host *host,
590 unsigned int port_no)
591{
592 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
593
594 return mmio + 0x100 + (port_no * 0x80);
595}
596
Tejun Heo4447d352007-04-17 23:44:08 +0900597static inline void __iomem *ahci_port_base(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700598{
Jeff Garzikdab632e2007-05-28 08:33:01 -0400599 return __ahci_port_base(ap->host, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700600}
601
Tejun Heob710a1f2008-01-05 23:11:57 +0900602static void ahci_enable_ahci(void __iomem *mmio)
603{
604 u32 tmp;
605
606 /* turn on AHCI_EN */
607 tmp = readl(mmio + HOST_CTL);
608 if (!(tmp & HOST_AHCI_EN)) {
609 tmp |= HOST_AHCI_EN;
610 writel(tmp, mmio + HOST_CTL);
611 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
612 WARN_ON(!(tmp & HOST_AHCI_EN));
613 }
614}
615
Tejun Heod447df12007-03-18 22:15:33 +0900616/**
617 * ahci_save_initial_config - Save and fixup initial config values
Tejun Heo4447d352007-04-17 23:44:08 +0900618 * @pdev: target PCI device
Tejun Heo4447d352007-04-17 23:44:08 +0900619 * @hpriv: host private area to store config values
Tejun Heod447df12007-03-18 22:15:33 +0900620 *
621 * Some registers containing configuration info might be setup by
622 * BIOS and might be cleared on reset. This function saves the
623 * initial values of those registers into @hpriv such that they
624 * can be restored after controller reset.
625 *
626 * If inconsistent, config values are fixed up by this function.
627 *
628 * LOCKING:
629 * None.
630 */
Tejun Heo4447d352007-04-17 23:44:08 +0900631static void ahci_save_initial_config(struct pci_dev *pdev,
Tejun Heo4447d352007-04-17 23:44:08 +0900632 struct ahci_host_priv *hpriv)
Tejun Heod447df12007-03-18 22:15:33 +0900633{
Tejun Heo4447d352007-04-17 23:44:08 +0900634 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900635 u32 cap, port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900636 int i;
Tejun Heod447df12007-03-18 22:15:33 +0900637
Tejun Heob710a1f2008-01-05 23:11:57 +0900638 /* make sure AHCI mode is enabled before accessing CAP */
639 ahci_enable_ahci(mmio);
640
Tejun Heod447df12007-03-18 22:15:33 +0900641 /* Values prefixed with saved_ are written back to host after
642 * reset. Values without are used for driver operation.
643 */
644 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
645 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
646
Tejun Heo274c1fd2007-07-16 14:29:40 +0900647 /* some chips have errata preventing 64bit use */
Tejun Heo417a1a62007-09-23 13:19:55 +0900648 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
Tejun Heoc7a42152007-05-18 16:23:19 +0200649 dev_printk(KERN_INFO, &pdev->dev,
650 "controller can't do 64bit DMA, forcing 32bit\n");
651 cap &= ~HOST_CAP_64;
652 }
653
Tejun Heo417a1a62007-09-23 13:19:55 +0900654 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
Tejun Heo274c1fd2007-07-16 14:29:40 +0900655 dev_printk(KERN_INFO, &pdev->dev,
656 "controller can't do NCQ, turning off CAP_NCQ\n");
657 cap &= ~HOST_CAP_NCQ;
658 }
659
Tejun Heo6949b912007-09-23 13:19:55 +0900660 if ((cap && HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
661 dev_printk(KERN_INFO, &pdev->dev,
662 "controller can't do PMP, turning off CAP_PMP\n");
663 cap &= ~HOST_CAP_PMP;
664 }
665
Jeff Garzikcd70c262007-07-08 02:29:42 -0400666 /*
667 * Temporary Marvell 6145 hack: PATA port presence
668 * is asserted through the standard AHCI port
669 * presence register, as bit 4 (counting from 0)
670 */
Tejun Heo417a1a62007-09-23 13:19:55 +0900671 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jeff Garzikcd70c262007-07-08 02:29:42 -0400672 dev_printk(KERN_ERR, &pdev->dev,
673 "MV_AHCI HACK: port_map %x -> %x\n",
674 hpriv->port_map,
675 hpriv->port_map & 0xf);
676
677 port_map &= 0xf;
678 }
679
Tejun Heo17199b12007-03-18 22:26:53 +0900680 /* cross check port_map and cap.n_ports */
Tejun Heo7a234af2007-09-03 12:44:57 +0900681 if (port_map) {
Tejun Heo837f5f82008-02-06 15:13:51 +0900682 int map_ports = 0;
Tejun Heo17199b12007-03-18 22:26:53 +0900683
Tejun Heo837f5f82008-02-06 15:13:51 +0900684 for (i = 0; i < AHCI_MAX_PORTS; i++)
685 if (port_map & (1 << i))
686 map_ports++;
Tejun Heo17199b12007-03-18 22:26:53 +0900687
Tejun Heo837f5f82008-02-06 15:13:51 +0900688 /* If PI has more ports than n_ports, whine, clear
689 * port_map and let it be generated from n_ports.
Tejun Heo17199b12007-03-18 22:26:53 +0900690 */
Tejun Heo837f5f82008-02-06 15:13:51 +0900691 if (map_ports > ahci_nr_ports(cap)) {
Tejun Heo4447d352007-04-17 23:44:08 +0900692 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heo837f5f82008-02-06 15:13:51 +0900693 "implemented port map (0x%x) contains more "
694 "ports than nr_ports (%u), using nr_ports\n",
695 port_map, ahci_nr_ports(cap));
Tejun Heo7a234af2007-09-03 12:44:57 +0900696 port_map = 0;
697 }
698 }
699
700 /* fabricate port_map from cap.nr_ports */
701 if (!port_map) {
Tejun Heo17199b12007-03-18 22:26:53 +0900702 port_map = (1 << ahci_nr_ports(cap)) - 1;
Tejun Heo7a234af2007-09-03 12:44:57 +0900703 dev_printk(KERN_WARNING, &pdev->dev,
704 "forcing PORTS_IMPL to 0x%x\n", port_map);
705
706 /* write the fixed up value to the PI register */
707 hpriv->saved_port_map = port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900708 }
709
Tejun Heod447df12007-03-18 22:15:33 +0900710 /* record values to use during operation */
711 hpriv->cap = cap;
712 hpriv->port_map = port_map;
713}
714
715/**
716 * ahci_restore_initial_config - Restore initial config
Tejun Heo4447d352007-04-17 23:44:08 +0900717 * @host: target ATA host
Tejun Heod447df12007-03-18 22:15:33 +0900718 *
719 * Restore initial config stored by ahci_save_initial_config().
720 *
721 * LOCKING:
722 * None.
723 */
Tejun Heo4447d352007-04-17 23:44:08 +0900724static void ahci_restore_initial_config(struct ata_host *host)
Tejun Heod447df12007-03-18 22:15:33 +0900725{
Tejun Heo4447d352007-04-17 23:44:08 +0900726 struct ahci_host_priv *hpriv = host->private_data;
727 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
728
Tejun Heod447df12007-03-18 22:15:33 +0900729 writel(hpriv->saved_cap, mmio + HOST_CAP);
730 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
731 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
732}
733
Tejun Heo203ef6c2007-07-16 14:29:40 +0900734static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700735{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900736 static const int offset[] = {
737 [SCR_STATUS] = PORT_SCR_STAT,
738 [SCR_CONTROL] = PORT_SCR_CTL,
739 [SCR_ERROR] = PORT_SCR_ERR,
740 [SCR_ACTIVE] = PORT_SCR_ACT,
741 [SCR_NOTIFICATION] = PORT_SCR_NTF,
742 };
743 struct ahci_host_priv *hpriv = ap->host->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700744
Tejun Heo203ef6c2007-07-16 14:29:40 +0900745 if (sc_reg < ARRAY_SIZE(offset) &&
746 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
747 return offset[sc_reg];
Tejun Heoda3dbb12007-07-16 14:29:40 +0900748 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700749}
750
Tejun Heo203ef6c2007-07-16 14:29:40 +0900751static int ahci_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700752{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900753 void __iomem *port_mmio = ahci_port_base(ap);
754 int offset = ahci_scr_offset(ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700755
Tejun Heo203ef6c2007-07-16 14:29:40 +0900756 if (offset) {
757 *val = readl(port_mmio + offset);
758 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700759 }
Tejun Heo203ef6c2007-07-16 14:29:40 +0900760 return -EINVAL;
761}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700762
Tejun Heo203ef6c2007-07-16 14:29:40 +0900763static int ahci_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val)
764{
765 void __iomem *port_mmio = ahci_port_base(ap);
766 int offset = ahci_scr_offset(ap, sc_reg);
767
768 if (offset) {
769 writel(val, port_mmio + offset);
770 return 0;
771 }
772 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700773}
774
Tejun Heo4447d352007-04-17 23:44:08 +0900775static void ahci_start_engine(struct ata_port *ap)
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900776{
Tejun Heo4447d352007-04-17 23:44:08 +0900777 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900778 u32 tmp;
779
Tejun Heod8fcd112006-07-26 15:59:25 +0900780 /* start DMA */
Tejun Heo9f592052006-07-26 15:59:26 +0900781 tmp = readl(port_mmio + PORT_CMD);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900782 tmp |= PORT_CMD_START;
783 writel(tmp, port_mmio + PORT_CMD);
784 readl(port_mmio + PORT_CMD); /* flush */
785}
786
Tejun Heo4447d352007-04-17 23:44:08 +0900787static int ahci_stop_engine(struct ata_port *ap)
Tejun Heo254950c2006-07-26 15:59:25 +0900788{
Tejun Heo4447d352007-04-17 23:44:08 +0900789 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo254950c2006-07-26 15:59:25 +0900790 u32 tmp;
791
792 tmp = readl(port_mmio + PORT_CMD);
793
Tejun Heod8fcd112006-07-26 15:59:25 +0900794 /* check if the HBA is idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900795 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
796 return 0;
797
Tejun Heod8fcd112006-07-26 15:59:25 +0900798 /* setting HBA to idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900799 tmp &= ~PORT_CMD_START;
800 writel(tmp, port_mmio + PORT_CMD);
801
Tejun Heod8fcd112006-07-26 15:59:25 +0900802 /* wait for engine to stop. This could be as long as 500 msec */
Tejun Heo254950c2006-07-26 15:59:25 +0900803 tmp = ata_wait_register(port_mmio + PORT_CMD,
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400804 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
Tejun Heod8fcd112006-07-26 15:59:25 +0900805 if (tmp & PORT_CMD_LIST_ON)
Tejun Heo254950c2006-07-26 15:59:25 +0900806 return -EIO;
807
808 return 0;
809}
810
Tejun Heo4447d352007-04-17 23:44:08 +0900811static void ahci_start_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900812{
Tejun Heo4447d352007-04-17 23:44:08 +0900813 void __iomem *port_mmio = ahci_port_base(ap);
814 struct ahci_host_priv *hpriv = ap->host->private_data;
815 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo0be0aa92006-07-26 15:59:26 +0900816 u32 tmp;
817
818 /* set FIS registers */
Tejun Heo4447d352007-04-17 23:44:08 +0900819 if (hpriv->cap & HOST_CAP_64)
820 writel((pp->cmd_slot_dma >> 16) >> 16,
821 port_mmio + PORT_LST_ADDR_HI);
822 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900823
Tejun Heo4447d352007-04-17 23:44:08 +0900824 if (hpriv->cap & HOST_CAP_64)
825 writel((pp->rx_fis_dma >> 16) >> 16,
826 port_mmio + PORT_FIS_ADDR_HI);
827 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900828
829 /* enable FIS reception */
830 tmp = readl(port_mmio + PORT_CMD);
831 tmp |= PORT_CMD_FIS_RX;
832 writel(tmp, port_mmio + PORT_CMD);
833
834 /* flush */
835 readl(port_mmio + PORT_CMD);
836}
837
Tejun Heo4447d352007-04-17 23:44:08 +0900838static int ahci_stop_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900839{
Tejun Heo4447d352007-04-17 23:44:08 +0900840 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900841 u32 tmp;
842
843 /* disable FIS reception */
844 tmp = readl(port_mmio + PORT_CMD);
845 tmp &= ~PORT_CMD_FIS_RX;
846 writel(tmp, port_mmio + PORT_CMD);
847
848 /* wait for completion, spec says 500ms, give it 1000 */
849 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
850 PORT_CMD_FIS_ON, 10, 1000);
851 if (tmp & PORT_CMD_FIS_ON)
852 return -EBUSY;
853
854 return 0;
855}
856
Tejun Heo4447d352007-04-17 23:44:08 +0900857static void ahci_power_up(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900858{
Tejun Heo4447d352007-04-17 23:44:08 +0900859 struct ahci_host_priv *hpriv = ap->host->private_data;
860 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900861 u32 cmd;
862
863 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
864
865 /* spin up device */
Tejun Heo4447d352007-04-17 23:44:08 +0900866 if (hpriv->cap & HOST_CAP_SSS) {
Tejun Heo0be0aa92006-07-26 15:59:26 +0900867 cmd |= PORT_CMD_SPIN_UP;
868 writel(cmd, port_mmio + PORT_CMD);
869 }
870
871 /* wake up link */
872 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
873}
874
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400875static void ahci_disable_alpm(struct ata_port *ap)
876{
877 struct ahci_host_priv *hpriv = ap->host->private_data;
878 void __iomem *port_mmio = ahci_port_base(ap);
879 u32 cmd;
880 struct ahci_port_priv *pp = ap->private_data;
881
882 /* IPM bits should be disabled by libata-core */
883 /* get the existing command bits */
884 cmd = readl(port_mmio + PORT_CMD);
885
886 /* disable ALPM and ASP */
887 cmd &= ~PORT_CMD_ASP;
888 cmd &= ~PORT_CMD_ALPE;
889
890 /* force the interface back to active */
891 cmd |= PORT_CMD_ICC_ACTIVE;
892
893 /* write out new cmd value */
894 writel(cmd, port_mmio + PORT_CMD);
895 cmd = readl(port_mmio + PORT_CMD);
896
897 /* wait 10ms to be sure we've come out of any low power state */
898 msleep(10);
899
900 /* clear out any PhyRdy stuff from interrupt status */
901 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
902
903 /* go ahead and clean out PhyRdy Change from Serror too */
904 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
905
906 /*
907 * Clear flag to indicate that we should ignore all PhyRdy
908 * state changes
909 */
910 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
911
912 /*
913 * Enable interrupts on Phy Ready.
914 */
915 pp->intr_mask |= PORT_IRQ_PHYRDY;
916 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
917
918 /*
919 * don't change the link pm policy - we can be called
920 * just to turn of link pm temporarily
921 */
922}
923
924static int ahci_enable_alpm(struct ata_port *ap,
925 enum link_pm policy)
926{
927 struct ahci_host_priv *hpriv = ap->host->private_data;
928 void __iomem *port_mmio = ahci_port_base(ap);
929 u32 cmd;
930 struct ahci_port_priv *pp = ap->private_data;
931 u32 asp;
932
933 /* Make sure the host is capable of link power management */
934 if (!(hpriv->cap & HOST_CAP_ALPM))
935 return -EINVAL;
936
937 switch (policy) {
938 case MAX_PERFORMANCE:
939 case NOT_AVAILABLE:
940 /*
941 * if we came here with NOT_AVAILABLE,
942 * it just means this is the first time we
943 * have tried to enable - default to max performance,
944 * and let the user go to lower power modes on request.
945 */
946 ahci_disable_alpm(ap);
947 return 0;
948 case MIN_POWER:
949 /* configure HBA to enter SLUMBER */
950 asp = PORT_CMD_ASP;
951 break;
952 case MEDIUM_POWER:
953 /* configure HBA to enter PARTIAL */
954 asp = 0;
955 break;
956 default:
957 return -EINVAL;
958 }
959
960 /*
961 * Disable interrupts on Phy Ready. This keeps us from
962 * getting woken up due to spurious phy ready interrupts
963 * TBD - Hot plug should be done via polling now, is
964 * that even supported?
965 */
966 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
967 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
968
969 /*
970 * Set a flag to indicate that we should ignore all PhyRdy
971 * state changes since these can happen now whenever we
972 * change link state
973 */
974 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
975
976 /* get the existing command bits */
977 cmd = readl(port_mmio + PORT_CMD);
978
979 /*
980 * Set ASP based on Policy
981 */
982 cmd |= asp;
983
984 /*
985 * Setting this bit will instruct the HBA to aggressively
986 * enter a lower power link state when it's appropriate and
987 * based on the value set above for ASP
988 */
989 cmd |= PORT_CMD_ALPE;
990
991 /* write out new cmd value */
992 writel(cmd, port_mmio + PORT_CMD);
993 cmd = readl(port_mmio + PORT_CMD);
994
995 /* IPM bits should be set by libata-core */
996 return 0;
997}
998
Tejun Heo438ac6d2007-03-02 17:31:26 +0900999#ifdef CONFIG_PM
Tejun Heo4447d352007-04-17 23:44:08 +09001000static void ahci_power_down(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001001{
Tejun Heo4447d352007-04-17 23:44:08 +09001002 struct ahci_host_priv *hpriv = ap->host->private_data;
1003 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001004 u32 cmd, scontrol;
1005
Tejun Heo4447d352007-04-17 23:44:08 +09001006 if (!(hpriv->cap & HOST_CAP_SSS))
Tejun Heo07c53da2007-01-21 02:10:11 +09001007 return;
1008
1009 /* put device into listen mode, first set PxSCTL.DET to 0 */
1010 scontrol = readl(port_mmio + PORT_SCR_CTL);
1011 scontrol &= ~0xf;
1012 writel(scontrol, port_mmio + PORT_SCR_CTL);
1013
1014 /* then set PxCMD.SUD to 0 */
Tejun Heo0be0aa92006-07-26 15:59:26 +09001015 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
Tejun Heo07c53da2007-01-21 02:10:11 +09001016 cmd &= ~PORT_CMD_SPIN_UP;
1017 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001018}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001019#endif
Tejun Heo0be0aa92006-07-26 15:59:26 +09001020
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001021static void ahci_start_port(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001022{
Tejun Heo0be0aa92006-07-26 15:59:26 +09001023 /* enable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001024 ahci_start_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001025
1026 /* enable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001027 ahci_start_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001028}
1029
Tejun Heo4447d352007-04-17 23:44:08 +09001030static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001031{
1032 int rc;
1033
1034 /* disable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001035 rc = ahci_stop_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001036 if (rc) {
1037 *emsg = "failed to stop engine";
1038 return rc;
1039 }
1040
1041 /* disable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001042 rc = ahci_stop_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001043 if (rc) {
1044 *emsg = "failed stop FIS RX";
1045 return rc;
1046 }
1047
Tejun Heo0be0aa92006-07-26 15:59:26 +09001048 return 0;
1049}
1050
Tejun Heo4447d352007-04-17 23:44:08 +09001051static int ahci_reset_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001052{
Tejun Heo4447d352007-04-17 23:44:08 +09001053 struct pci_dev *pdev = to_pci_dev(host->dev);
Tejun Heo49f29092007-11-19 16:03:44 +09001054 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001055 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +09001056 u32 tmp;
Tejun Heod91542c2006-07-26 15:59:26 +09001057
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001058 /* we must be in AHCI mode, before using anything
1059 * AHCI-specific, such as HOST_RESET.
1060 */
Tejun Heob710a1f2008-01-05 23:11:57 +09001061 ahci_enable_ahci(mmio);
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001062
1063 /* global controller reset */
Tejun Heob710a1f2008-01-05 23:11:57 +09001064 tmp = readl(mmio + HOST_CTL);
Tejun Heod91542c2006-07-26 15:59:26 +09001065 if ((tmp & HOST_RESET) == 0) {
1066 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1067 readl(mmio + HOST_CTL); /* flush */
1068 }
1069
1070 /* reset must complete within 1 second, or
1071 * the hardware should be considered fried.
1072 */
1073 ssleep(1);
1074
1075 tmp = readl(mmio + HOST_CTL);
1076 if (tmp & HOST_RESET) {
Tejun Heo4447d352007-04-17 23:44:08 +09001077 dev_printk(KERN_ERR, host->dev,
Tejun Heod91542c2006-07-26 15:59:26 +09001078 "controller reset failed (0x%x)\n", tmp);
1079 return -EIO;
1080 }
1081
Tejun Heo98fa4b62006-11-02 12:17:23 +09001082 /* turn on AHCI mode */
Tejun Heob710a1f2008-01-05 23:11:57 +09001083 ahci_enable_ahci(mmio);
Tejun Heo98fa4b62006-11-02 12:17:23 +09001084
Tejun Heod447df12007-03-18 22:15:33 +09001085 /* some registers might be cleared on reset. restore initial values */
Tejun Heo4447d352007-04-17 23:44:08 +09001086 ahci_restore_initial_config(host);
Tejun Heod91542c2006-07-26 15:59:26 +09001087
1088 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1089 u16 tmp16;
1090
1091 /* configure PCS */
1092 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +09001093 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1094 tmp16 |= hpriv->port_map;
1095 pci_write_config_word(pdev, 0x92, tmp16);
1096 }
Tejun Heod91542c2006-07-26 15:59:26 +09001097 }
1098
1099 return 0;
1100}
1101
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001102static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1103 int port_no, void __iomem *mmio,
1104 void __iomem *port_mmio)
1105{
1106 const char *emsg = NULL;
1107 int rc;
1108 u32 tmp;
1109
1110 /* make sure port is not active */
1111 rc = ahci_deinit_port(ap, &emsg);
1112 if (rc)
1113 dev_printk(KERN_WARNING, &pdev->dev,
1114 "%s (%d)\n", emsg, rc);
1115
1116 /* clear SError */
1117 tmp = readl(port_mmio + PORT_SCR_ERR);
1118 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1119 writel(tmp, port_mmio + PORT_SCR_ERR);
1120
1121 /* clear port IRQ */
1122 tmp = readl(port_mmio + PORT_IRQ_STAT);
1123 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1124 if (tmp)
1125 writel(tmp, port_mmio + PORT_IRQ_STAT);
1126
1127 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1128}
1129
Tejun Heo4447d352007-04-17 23:44:08 +09001130static void ahci_init_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001131{
Tejun Heo417a1a62007-09-23 13:19:55 +09001132 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001133 struct pci_dev *pdev = to_pci_dev(host->dev);
1134 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001135 int i;
Jeff Garzikcd70c262007-07-08 02:29:42 -04001136 void __iomem *port_mmio;
Tejun Heod91542c2006-07-26 15:59:26 +09001137 u32 tmp;
1138
Tejun Heo417a1a62007-09-23 13:19:55 +09001139 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jeff Garzikcd70c262007-07-08 02:29:42 -04001140 port_mmio = __ahci_port_base(host, 4);
1141
1142 writel(0, port_mmio + PORT_IRQ_MASK);
1143
1144 /* clear port IRQ */
1145 tmp = readl(port_mmio + PORT_IRQ_STAT);
1146 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1147 if (tmp)
1148 writel(tmp, port_mmio + PORT_IRQ_STAT);
1149 }
1150
Tejun Heo4447d352007-04-17 23:44:08 +09001151 for (i = 0; i < host->n_ports; i++) {
1152 struct ata_port *ap = host->ports[i];
Tejun Heod91542c2006-07-26 15:59:26 +09001153
Jeff Garzikcd70c262007-07-08 02:29:42 -04001154 port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +09001155 if (ata_port_is_dummy(ap))
Tejun Heod91542c2006-07-26 15:59:26 +09001156 continue;
Tejun Heod91542c2006-07-26 15:59:26 +09001157
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001158 ahci_port_init(pdev, ap, i, mmio, port_mmio);
Tejun Heod91542c2006-07-26 15:59:26 +09001159 }
1160
1161 tmp = readl(mmio + HOST_CTL);
1162 VPRINTK("HOST_CTL 0x%x\n", tmp);
1163 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1164 tmp = readl(mmio + HOST_CTL);
1165 VPRINTK("HOST_CTL 0x%x\n", tmp);
1166}
1167
Tejun Heo422b7592005-12-19 22:37:17 +09001168static unsigned int ahci_dev_classify(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001169{
Tejun Heo4447d352007-04-17 23:44:08 +09001170 void __iomem *port_mmio = ahci_port_base(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001171 struct ata_taskfile tf;
Tejun Heo422b7592005-12-19 22:37:17 +09001172 u32 tmp;
1173
1174 tmp = readl(port_mmio + PORT_SIG);
1175 tf.lbah = (tmp >> 24) & 0xff;
1176 tf.lbam = (tmp >> 16) & 0xff;
1177 tf.lbal = (tmp >> 8) & 0xff;
1178 tf.nsect = (tmp) & 0xff;
1179
1180 return ata_dev_classify(&tf);
1181}
1182
Tejun Heo12fad3f2006-05-15 21:03:55 +09001183static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1184 u32 opts)
Tejun Heocc9278e2006-02-10 17:25:47 +09001185{
Tejun Heo12fad3f2006-05-15 21:03:55 +09001186 dma_addr_t cmd_tbl_dma;
1187
1188 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1189
1190 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1191 pp->cmd_slot[tag].status = 0;
1192 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1193 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
Tejun Heocc9278e2006-02-10 17:25:47 +09001194}
1195
Tejun Heod2e75df2007-07-16 14:29:39 +09001196static int ahci_kick_engine(struct ata_port *ap, int force_restart)
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001197{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001198 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
Jeff Garzikcca39742006-08-24 03:19:22 -04001199 struct ahci_host_priv *hpriv = ap->host->private_data;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001200 u32 tmp;
Tejun Heod2e75df2007-07-16 14:29:39 +09001201 int busy, rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001202
Tejun Heod2e75df2007-07-16 14:29:39 +09001203 /* do we need to kick the port? */
1204 busy = ahci_check_status(ap) & (ATA_BUSY | ATA_DRQ);
1205 if (!busy && !force_restart)
1206 return 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001207
Tejun Heod2e75df2007-07-16 14:29:39 +09001208 /* stop engine */
1209 rc = ahci_stop_engine(ap);
1210 if (rc)
1211 goto out_restart;
1212
1213 /* need to do CLO? */
1214 if (!busy) {
1215 rc = 0;
1216 goto out_restart;
1217 }
1218
1219 if (!(hpriv->cap & HOST_CAP_CLO)) {
1220 rc = -EOPNOTSUPP;
1221 goto out_restart;
1222 }
1223
1224 /* perform CLO */
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001225 tmp = readl(port_mmio + PORT_CMD);
1226 tmp |= PORT_CMD_CLO;
1227 writel(tmp, port_mmio + PORT_CMD);
1228
Tejun Heod2e75df2007-07-16 14:29:39 +09001229 rc = 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001230 tmp = ata_wait_register(port_mmio + PORT_CMD,
1231 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1232 if (tmp & PORT_CMD_CLO)
Tejun Heod2e75df2007-07-16 14:29:39 +09001233 rc = -EIO;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001234
Tejun Heod2e75df2007-07-16 14:29:39 +09001235 /* restart engine */
1236 out_restart:
1237 ahci_start_engine(ap);
1238 return rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001239}
1240
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001241static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1242 struct ata_taskfile *tf, int is_cmd, u16 flags,
1243 unsigned long timeout_msec)
1244{
1245 const u32 cmd_fis_len = 5; /* five dwords */
1246 struct ahci_port_priv *pp = ap->private_data;
1247 void __iomem *port_mmio = ahci_port_base(ap);
1248 u8 *fis = pp->cmd_tbl;
1249 u32 tmp;
1250
1251 /* prep the command */
1252 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1253 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1254
1255 /* issue & wait */
1256 writel(1, port_mmio + PORT_CMD_ISSUE);
1257
1258 if (timeout_msec) {
1259 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1260 1, timeout_msec);
1261 if (tmp & 0x1) {
1262 ahci_kick_engine(ap, 1);
1263 return -EBUSY;
1264 }
1265 } else
1266 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1267
1268 return 0;
1269}
1270
Tejun Heocc0680a2007-08-06 18:36:23 +09001271static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001272 int pmp, unsigned long deadline)
Tejun Heo4658f792006-03-22 21:07:03 +09001273{
Tejun Heocc0680a2007-08-06 18:36:23 +09001274 struct ata_port *ap = link->ap;
Tejun Heo4658f792006-03-22 21:07:03 +09001275 const char *reason = NULL;
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001276 unsigned long now, msecs;
Tejun Heo4658f792006-03-22 21:07:03 +09001277 struct ata_taskfile tf;
Tejun Heo4658f792006-03-22 21:07:03 +09001278 int rc;
1279
1280 DPRINTK("ENTER\n");
1281
Tejun Heocc0680a2007-08-06 18:36:23 +09001282 if (ata_link_offline(link)) {
Tejun Heoc2a65852006-04-03 01:58:06 +09001283 DPRINTK("PHY reports no device\n");
1284 *class = ATA_DEV_NONE;
1285 return 0;
1286 }
1287
Tejun Heo4658f792006-03-22 21:07:03 +09001288 /* prepare for SRST (AHCI-1.1 10.4.1) */
Tejun Heod2e75df2007-07-16 14:29:39 +09001289 rc = ahci_kick_engine(ap, 1);
Tejun Heo994056d2007-12-06 15:02:48 +09001290 if (rc && rc != -EOPNOTSUPP)
Tejun Heocc0680a2007-08-06 18:36:23 +09001291 ata_link_printk(link, KERN_WARNING,
Tejun Heo994056d2007-12-06 15:02:48 +09001292 "failed to reset engine (errno=%d)\n", rc);
Tejun Heo4658f792006-03-22 21:07:03 +09001293
Tejun Heocc0680a2007-08-06 18:36:23 +09001294 ata_tf_init(link->device, &tf);
Tejun Heo4658f792006-03-22 21:07:03 +09001295
1296 /* issue the first D2H Register FIS */
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001297 msecs = 0;
1298 now = jiffies;
1299 if (time_after(now, deadline))
1300 msecs = jiffies_to_msecs(deadline - now);
1301
Tejun Heo4658f792006-03-22 21:07:03 +09001302 tf.ctl |= ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001303 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001304 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
Tejun Heo4658f792006-03-22 21:07:03 +09001305 rc = -EIO;
1306 reason = "1st FIS failed";
1307 goto fail;
1308 }
1309
1310 /* spec says at least 5us, but be generous and sleep for 1ms */
1311 msleep(1);
1312
1313 /* issue the second D2H Register FIS */
Tejun Heo4658f792006-03-22 21:07:03 +09001314 tf.ctl &= ~ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001315 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
Tejun Heo4658f792006-03-22 21:07:03 +09001316
Tejun Heo88ff6ea2007-10-16 14:21:24 -07001317 /* wait a while before checking status */
1318 ata_wait_after_reset(ap, deadline);
Tejun Heo4658f792006-03-22 21:07:03 +09001319
Tejun Heo9b893912007-02-02 16:50:52 +09001320 rc = ata_wait_ready(ap, deadline);
1321 /* link occupied, -ENODEV too is an error */
1322 if (rc) {
1323 reason = "device not ready";
1324 goto fail;
Tejun Heo4658f792006-03-22 21:07:03 +09001325 }
Tejun Heo9b893912007-02-02 16:50:52 +09001326 *class = ahci_dev_classify(ap);
Tejun Heo4658f792006-03-22 21:07:03 +09001327
1328 DPRINTK("EXIT, class=%u\n", *class);
1329 return 0;
1330
Tejun Heo4658f792006-03-22 21:07:03 +09001331 fail:
Tejun Heocc0680a2007-08-06 18:36:23 +09001332 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
Tejun Heo4658f792006-03-22 21:07:03 +09001333 return rc;
1334}
1335
Tejun Heocc0680a2007-08-06 18:36:23 +09001336static int ahci_softreset(struct ata_link *link, unsigned int *class,
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001337 unsigned long deadline)
1338{
Tejun Heo7d50b602007-09-23 13:19:54 +09001339 int pmp = 0;
1340
1341 if (link->ap->flags & ATA_FLAG_PMP)
1342 pmp = SATA_PMP_CTRL_PORT;
1343
1344 return ahci_do_softreset(link, class, pmp, deadline);
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001345}
1346
Tejun Heocc0680a2007-08-06 18:36:23 +09001347static int ahci_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001348 unsigned long deadline)
Tejun Heo422b7592005-12-19 22:37:17 +09001349{
Tejun Heocc0680a2007-08-06 18:36:23 +09001350 struct ata_port *ap = link->ap;
Tejun Heo42969712006-05-31 18:28:18 +09001351 struct ahci_port_priv *pp = ap->private_data;
1352 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1353 struct ata_taskfile tf;
Tejun Heo4bd00f62006-02-11 16:26:02 +09001354 int rc;
1355
1356 DPRINTK("ENTER\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001357
Tejun Heo4447d352007-04-17 23:44:08 +09001358 ahci_stop_engine(ap);
Tejun Heo42969712006-05-31 18:28:18 +09001359
1360 /* clear D2H reception area to properly wait for D2H FIS */
Tejun Heocc0680a2007-08-06 18:36:23 +09001361 ata_tf_init(link->device, &tf);
Tejun Heodfd7a3d2007-01-26 15:37:20 +09001362 tf.command = 0x80;
Tejun Heo99771262007-07-16 14:29:38 +09001363 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
Tejun Heo42969712006-05-31 18:28:18 +09001364
Tejun Heocc0680a2007-08-06 18:36:23 +09001365 rc = sata_std_hardreset(link, class, deadline);
Tejun Heo42969712006-05-31 18:28:18 +09001366
Tejun Heo4447d352007-04-17 23:44:08 +09001367 ahci_start_engine(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001368
Tejun Heocc0680a2007-08-06 18:36:23 +09001369 if (rc == 0 && ata_link_online(link))
Tejun Heo4bd00f62006-02-11 16:26:02 +09001370 *class = ahci_dev_classify(ap);
Tejun Heo7d50b602007-09-23 13:19:54 +09001371 if (rc != -EAGAIN && *class == ATA_DEV_UNKNOWN)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001372 *class = ATA_DEV_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001373
Tejun Heo4bd00f62006-02-11 16:26:02 +09001374 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1375 return rc;
1376}
1377
Tejun Heocc0680a2007-08-06 18:36:23 +09001378static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001379 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +09001380{
Tejun Heocc0680a2007-08-06 18:36:23 +09001381 struct ata_port *ap = link->ap;
Tejun Heoda3dbb12007-07-16 14:29:40 +09001382 u32 serror;
Tejun Heoad616ff2006-11-01 18:00:24 +09001383 int rc;
1384
1385 DPRINTK("ENTER\n");
1386
Tejun Heo4447d352007-04-17 23:44:08 +09001387 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001388
Tejun Heocc0680a2007-08-06 18:36:23 +09001389 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heod4b2bab2007-02-02 16:50:52 +09001390 deadline);
Tejun Heoad616ff2006-11-01 18:00:24 +09001391
1392 /* vt8251 needs SError cleared for the port to operate */
Tejun Heoda3dbb12007-07-16 14:29:40 +09001393 ahci_scr_read(ap, SCR_ERROR, &serror);
1394 ahci_scr_write(ap, SCR_ERROR, serror);
Tejun Heoad616ff2006-11-01 18:00:24 +09001395
Tejun Heo4447d352007-04-17 23:44:08 +09001396 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001397
1398 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1399
1400 /* vt8251 doesn't clear BSY on signature FIS reception,
1401 * request follow-up softreset.
1402 */
1403 return rc ?: -EAGAIN;
1404}
1405
Tejun Heoedc93052007-10-25 14:59:16 +09001406static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1407 unsigned long deadline)
1408{
1409 struct ata_port *ap = link->ap;
1410 struct ahci_port_priv *pp = ap->private_data;
1411 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1412 struct ata_taskfile tf;
1413 int rc;
1414
1415 ahci_stop_engine(ap);
1416
1417 /* clear D2H reception area to properly wait for D2H FIS */
1418 ata_tf_init(link->device, &tf);
1419 tf.command = 0x80;
1420 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1421
1422 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
1423 deadline);
1424
1425 ahci_start_engine(ap);
1426
1427 if (rc || ata_link_offline(link))
1428 return rc;
1429
1430 /* spec mandates ">= 2ms" before checking status */
1431 msleep(150);
1432
1433 /* The pseudo configuration device on SIMG4726 attached to
1434 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1435 * hardreset if no device is attached to the first downstream
1436 * port && the pseudo device locks up on SRST w/ PMP==0. To
1437 * work around this, wait for !BSY only briefly. If BSY isn't
1438 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1439 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1440 *
1441 * Wait for two seconds. Devices attached to downstream port
1442 * which can't process the following IDENTIFY after this will
1443 * have to be reset again. For most cases, this should
1444 * suffice while making probing snappish enough.
1445 */
1446 rc = ata_wait_ready(ap, jiffies + 2 * HZ);
1447 if (rc)
1448 ahci_kick_engine(ap, 0);
1449
1450 return 0;
1451}
1452
Tejun Heocc0680a2007-08-06 18:36:23 +09001453static void ahci_postreset(struct ata_link *link, unsigned int *class)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001454{
Tejun Heocc0680a2007-08-06 18:36:23 +09001455 struct ata_port *ap = link->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001456 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001457 u32 new_tmp, tmp;
1458
Tejun Heocc0680a2007-08-06 18:36:23 +09001459 ata_std_postreset(link, class);
Jeff Garzik02eaa662005-11-12 01:32:19 -05001460
1461 /* Make sure port's ATAPI bit is set appropriately */
1462 new_tmp = tmp = readl(port_mmio + PORT_CMD);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001463 if (*class == ATA_DEV_ATAPI)
Jeff Garzik02eaa662005-11-12 01:32:19 -05001464 new_tmp |= PORT_CMD_ATAPI;
1465 else
1466 new_tmp &= ~PORT_CMD_ATAPI;
1467 if (new_tmp != tmp) {
1468 writel(new_tmp, port_mmio + PORT_CMD);
1469 readl(port_mmio + PORT_CMD); /* flush */
1470 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001471}
1472
Tejun Heo7d50b602007-09-23 13:19:54 +09001473static int ahci_pmp_softreset(struct ata_link *link, unsigned int *class,
1474 unsigned long deadline)
1475{
1476 return ahci_do_softreset(link, class, link->pmp, deadline);
1477}
1478
Linus Torvalds1da177e2005-04-16 15:20:36 -07001479static u8 ahci_check_status(struct ata_port *ap)
1480{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001481 void __iomem *mmio = ap->ioaddr.cmd_addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001482
1483 return readl(mmio + PORT_TFDATA) & 0xFF;
1484}
1485
Linus Torvalds1da177e2005-04-16 15:20:36 -07001486static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1487{
1488 struct ahci_port_priv *pp = ap->private_data;
1489 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1490
1491 ata_tf_from_fis(d2h_fis, tf);
1492}
1493
Tejun Heo12fad3f2006-05-15 21:03:55 +09001494static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001495{
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001496 struct scatterlist *sg;
Tejun Heoff2aeb12007-12-05 16:43:11 +09001497 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1498 unsigned int si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001499
1500 VPRINTK("ENTER\n");
1501
1502 /*
1503 * Next, the S/G list.
1504 */
Tejun Heoff2aeb12007-12-05 16:43:11 +09001505 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001506 dma_addr_t addr = sg_dma_address(sg);
1507 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001508
Tejun Heoff2aeb12007-12-05 16:43:11 +09001509 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1510 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1511 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001512 }
Jeff Garzik828d09d2005-11-12 01:27:07 -05001513
Tejun Heoff2aeb12007-12-05 16:43:11 +09001514 return si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001515}
1516
1517static void ahci_qc_prep(struct ata_queued_cmd *qc)
1518{
Jeff Garzika0ea7322005-06-04 01:13:15 -04001519 struct ata_port *ap = qc->ap;
1520 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo405e66b2007-11-27 19:28:53 +09001521 int is_atapi = ata_is_atapi(qc->tf.protocol);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001522 void *cmd_tbl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001523 u32 opts;
1524 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -05001525 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001526
1527 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001528 * Fill in command table information. First, the header,
1529 * a SATA Register - Host to Device command FIS.
1530 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09001531 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1532
Tejun Heo7d50b602007-09-23 13:19:54 +09001533 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
Tejun Heocc9278e2006-02-10 17:25:47 +09001534 if (is_atapi) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09001535 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1536 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
Jeff Garzika0ea7322005-06-04 01:13:15 -04001537 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001538
Tejun Heocc9278e2006-02-10 17:25:47 +09001539 n_elem = 0;
1540 if (qc->flags & ATA_QCFLAG_DMAMAP)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001541 n_elem = ahci_fill_sg(qc, cmd_tbl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001542
Tejun Heocc9278e2006-02-10 17:25:47 +09001543 /*
1544 * Fill in command slot information.
1545 */
Tejun Heo7d50b602007-09-23 13:19:54 +09001546 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
Tejun Heocc9278e2006-02-10 17:25:47 +09001547 if (qc->tf.flags & ATA_TFLAG_WRITE)
1548 opts |= AHCI_CMD_WRITE;
1549 if (is_atapi)
Tejun Heo4b10e552006-03-12 11:25:27 +09001550 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
Jeff Garzik828d09d2005-11-12 01:27:07 -05001551
Tejun Heo12fad3f2006-05-15 21:03:55 +09001552 ahci_fill_cmd_slot(pp, qc->tag, opts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001553}
1554
Tejun Heo78cd52d2006-05-15 20:58:29 +09001555static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001556{
Tejun Heo417a1a62007-09-23 13:19:55 +09001557 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001558 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09001559 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1560 struct ata_link *link = NULL;
1561 struct ata_queued_cmd *active_qc;
1562 struct ata_eh_info *active_ehi;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001563 u32 serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001564
Tejun Heo7d50b602007-09-23 13:19:54 +09001565 /* determine active link */
1566 ata_port_for_each_link(link, ap)
1567 if (ata_link_active(link))
1568 break;
1569 if (!link)
1570 link = &ap->link;
1571
1572 active_qc = ata_qc_from_tag(ap, link->active_tag);
1573 active_ehi = &link->eh_info;
1574
1575 /* record irq stat */
1576 ata_ehi_clear_desc(host_ehi);
1577 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
Jeff Garzik9f68a242005-11-15 14:03:47 -05001578
Tejun Heo78cd52d2006-05-15 20:58:29 +09001579 /* AHCI needs SError cleared; otherwise, it might lock up */
Tejun Heoda3dbb12007-07-16 14:29:40 +09001580 ahci_scr_read(ap, SCR_ERROR, &serror);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001581 ahci_scr_write(ap, SCR_ERROR, serror);
Tejun Heo7d50b602007-09-23 13:19:54 +09001582 host_ehi->serror |= serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001583
Tejun Heo41669552006-11-29 11:33:14 +09001584 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
Tejun Heo417a1a62007-09-23 13:19:55 +09001585 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
Tejun Heo41669552006-11-29 11:33:14 +09001586 irq_stat &= ~PORT_IRQ_IF_ERR;
1587
Conke Hu55a61602007-03-27 18:33:05 +08001588 if (irq_stat & PORT_IRQ_TF_ERR) {
Tejun Heo7d50b602007-09-23 13:19:54 +09001589 /* If qc is active, charge it; otherwise, the active
1590 * link. There's no active qc on NCQ errors. It will
1591 * be determined by EH by reading log page 10h.
1592 */
1593 if (active_qc)
1594 active_qc->err_mask |= AC_ERR_DEV;
1595 else
1596 active_ehi->err_mask |= AC_ERR_DEV;
1597
Tejun Heo417a1a62007-09-23 13:19:55 +09001598 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
Tejun Heo7d50b602007-09-23 13:19:54 +09001599 host_ehi->serror &= ~SERR_INTERNAL;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001600 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001601
Tejun Heo78cd52d2006-05-15 20:58:29 +09001602 if (irq_stat & PORT_IRQ_UNK_FIS) {
1603 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001604
Tejun Heo7d50b602007-09-23 13:19:54 +09001605 active_ehi->err_mask |= AC_ERR_HSM;
1606 active_ehi->action |= ATA_EH_SOFTRESET;
1607 ata_ehi_push_desc(active_ehi,
1608 "unknown FIS %08x %08x %08x %08x" ,
Tejun Heo78cd52d2006-05-15 20:58:29 +09001609 unk[0], unk[1], unk[2], unk[3]);
1610 }
Jeff Garzikb8f61532005-08-25 22:01:20 -04001611
Tejun Heo7d50b602007-09-23 13:19:54 +09001612 if (ap->nr_pmp_links && (irq_stat & PORT_IRQ_BAD_PMP)) {
1613 active_ehi->err_mask |= AC_ERR_HSM;
1614 active_ehi->action |= ATA_EH_SOFTRESET;
1615 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1616 }
Tejun Heo78cd52d2006-05-15 20:58:29 +09001617
Tejun Heo7d50b602007-09-23 13:19:54 +09001618 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1619 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1620 host_ehi->action |= ATA_EH_SOFTRESET;
1621 ata_ehi_push_desc(host_ehi, "host bus error");
1622 }
1623
1624 if (irq_stat & PORT_IRQ_IF_ERR) {
1625 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1626 host_ehi->action |= ATA_EH_SOFTRESET;
1627 ata_ehi_push_desc(host_ehi, "interface fatal error");
1628 }
1629
1630 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1631 ata_ehi_hotplugged(host_ehi);
1632 ata_ehi_push_desc(host_ehi, "%s",
1633 irq_stat & PORT_IRQ_CONNECT ?
1634 "connection status changed" : "PHY RDY changed");
1635 }
1636
1637 /* okay, let's hand over to EH */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001638
Tejun Heo78cd52d2006-05-15 20:58:29 +09001639 if (irq_stat & PORT_IRQ_FREEZE)
1640 ata_port_freeze(ap);
1641 else
1642 ata_port_abort(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001643}
1644
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001645static void ahci_port_intr(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001646{
Tejun Heo4447d352007-04-17 23:44:08 +09001647 void __iomem *port_mmio = ap->ioaddr.cmd_addr;
Tejun Heo9af5c9c2007-08-06 18:36:22 +09001648 struct ata_eh_info *ehi = &ap->link.eh_info;
Tejun Heo0291f952007-01-25 19:16:28 +09001649 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo5f226c62007-10-09 15:02:23 +09001650 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heob06ce3e2007-10-09 15:06:48 +09001651 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001652 u32 status, qc_active;
Tejun Heo459ad682007-12-07 12:46:23 +09001653 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001654
1655 status = readl(port_mmio + PORT_IRQ_STAT);
1656 writel(status, port_mmio + PORT_IRQ_STAT);
1657
Tejun Heob06ce3e2007-10-09 15:06:48 +09001658 /* ignore BAD_PMP while resetting */
1659 if (unlikely(resetting))
1660 status &= ~PORT_IRQ_BAD_PMP;
1661
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04001662 /* If we are getting PhyRdy, this is
1663 * just a power state change, we should
1664 * clear out this, plus the PhyRdy/Comm
1665 * Wake bits from Serror
1666 */
1667 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
1668 (status & PORT_IRQ_PHYRDY)) {
1669 status &= ~PORT_IRQ_PHYRDY;
1670 ahci_scr_write(ap, SCR_ERROR, ((1 << 16) | (1 << 18)));
1671 }
1672
Tejun Heo78cd52d2006-05-15 20:58:29 +09001673 if (unlikely(status & PORT_IRQ_ERROR)) {
1674 ahci_error_intr(ap, status);
1675 return;
1676 }
1677
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04001678 if (status & PORT_IRQ_SDB_FIS) {
Tejun Heo5f226c62007-10-09 15:02:23 +09001679 /* If SNotification is available, leave notification
1680 * handling to sata_async_notification(). If not,
1681 * emulate it by snooping SDB FIS RX area.
1682 *
1683 * Snooping FIS RX area is probably cheaper than
1684 * poking SNotification but some constrollers which
1685 * implement SNotification, ICH9 for example, don't
1686 * store AN SDB FIS into receive area.
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04001687 */
Tejun Heo5f226c62007-10-09 15:02:23 +09001688 if (hpriv->cap & HOST_CAP_SNTF)
Tejun Heo7d77b242007-09-23 13:14:13 +09001689 sata_async_notification(ap);
Tejun Heo5f226c62007-10-09 15:02:23 +09001690 else {
1691 /* If the 'N' bit in word 0 of the FIS is set,
1692 * we just received asynchronous notification.
1693 * Tell libata about it.
1694 */
1695 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1696 u32 f0 = le32_to_cpu(f[0]);
1697
1698 if (f0 & (1 << 15))
1699 sata_async_notification(ap);
1700 }
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04001701 }
1702
Tejun Heo7d50b602007-09-23 13:19:54 +09001703 /* pp->active_link is valid iff any command is in flight */
1704 if (ap->qc_active && pp->active_link->sactive)
Tejun Heo12fad3f2006-05-15 21:03:55 +09001705 qc_active = readl(port_mmio + PORT_SCR_ACT);
1706 else
1707 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1708
1709 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
Tejun Heob06ce3e2007-10-09 15:06:48 +09001710
Tejun Heo459ad682007-12-07 12:46:23 +09001711 /* while resetting, invalid completions are expected */
1712 if (unlikely(rc < 0 && !resetting)) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09001713 ehi->err_mask |= AC_ERR_HSM;
1714 ehi->action |= ATA_EH_SOFTRESET;
1715 ata_port_freeze(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001716 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001717}
1718
1719static void ahci_irq_clear(struct ata_port *ap)
1720{
1721 /* TODO */
1722}
1723
David Howells7d12e782006-10-05 14:55:46 +01001724static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001725{
Jeff Garzikcca39742006-08-24 03:19:22 -04001726 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001727 struct ahci_host_priv *hpriv;
1728 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -04001729 void __iomem *mmio;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001730 u32 irq_stat, irq_ack = 0;
1731
1732 VPRINTK("ENTER\n");
1733
Jeff Garzikcca39742006-08-24 03:19:22 -04001734 hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09001735 mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001736
1737 /* sigh. 0xffffffff is a valid return from h/w */
1738 irq_stat = readl(mmio + HOST_IRQ_STAT);
1739 irq_stat &= hpriv->port_map;
1740 if (!irq_stat)
1741 return IRQ_NONE;
1742
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001743 spin_lock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001744
Jeff Garzik2dcb4072007-10-19 06:42:56 -04001745 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001746 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001747
Jeff Garzik67846b32005-10-05 02:58:32 -04001748 if (!(irq_stat & (1 << i)))
1749 continue;
1750
Jeff Garzikcca39742006-08-24 03:19:22 -04001751 ap = host->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -04001752 if (ap) {
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001753 ahci_port_intr(ap);
Jeff Garzik67846b32005-10-05 02:58:32 -04001754 VPRINTK("port %u\n", i);
1755 } else {
1756 VPRINTK("port %u (no irq)\n", i);
Tejun Heo6971ed12006-03-11 12:47:54 +09001757 if (ata_ratelimit())
Jeff Garzikcca39742006-08-24 03:19:22 -04001758 dev_printk(KERN_WARNING, host->dev,
Jeff Garzika9524a72005-10-30 14:39:11 -05001759 "interrupt on disabled port %u\n", i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001760 }
Jeff Garzik67846b32005-10-05 02:58:32 -04001761
1762 irq_ack |= (1 << i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001763 }
1764
1765 if (irq_ack) {
1766 writel(irq_ack, mmio + HOST_IRQ_STAT);
1767 handled = 1;
1768 }
1769
Jeff Garzikcca39742006-08-24 03:19:22 -04001770 spin_unlock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001771
1772 VPRINTK("EXIT\n");
1773
1774 return IRQ_RETVAL(handled);
1775}
1776
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09001777static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001778{
1779 struct ata_port *ap = qc->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001780 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7d50b602007-09-23 13:19:54 +09001781 struct ahci_port_priv *pp = ap->private_data;
1782
1783 /* Keep track of the currently active link. It will be used
1784 * in completion path to determine whether NCQ phase is in
1785 * progress.
1786 */
1787 pp->active_link = qc->dev->link;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001788
Tejun Heo12fad3f2006-05-15 21:03:55 +09001789 if (qc->tf.protocol == ATA_PROT_NCQ)
1790 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1791 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001792 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1793
1794 return 0;
1795}
1796
Tejun Heo78cd52d2006-05-15 20:58:29 +09001797static void ahci_freeze(struct ata_port *ap)
1798{
Tejun Heo4447d352007-04-17 23:44:08 +09001799 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001800
1801 /* turn IRQ off */
1802 writel(0, port_mmio + PORT_IRQ_MASK);
1803}
1804
1805static void ahci_thaw(struct ata_port *ap)
1806{
Tejun Heo0d5ff562007-02-01 15:06:36 +09001807 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
Tejun Heo4447d352007-04-17 23:44:08 +09001808 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001809 u32 tmp;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07001810 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09001811
1812 /* clear IRQ */
1813 tmp = readl(port_mmio + PORT_IRQ_STAT);
1814 writel(tmp, port_mmio + PORT_IRQ_STAT);
Tejun Heoa7187282007-01-27 11:04:26 +09001815 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001816
Tejun Heo1c954a42007-10-09 15:01:37 +09001817 /* turn IRQ back on */
1818 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001819}
1820
1821static void ahci_error_handler(struct ata_port *ap)
1822{
Tejun Heob51e9e52006-06-29 01:29:30 +09001823 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
Tejun Heo78cd52d2006-05-15 20:58:29 +09001824 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09001825 ahci_stop_engine(ap);
1826 ahci_start_engine(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001827 }
1828
1829 /* perform recovery */
Tejun Heo7d50b602007-09-23 13:19:54 +09001830 sata_pmp_do_eh(ap, ata_std_prereset, ahci_softreset,
1831 ahci_hardreset, ahci_postreset,
1832 sata_pmp_std_prereset, ahci_pmp_softreset,
1833 sata_pmp_std_hardreset, sata_pmp_std_postreset);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001834}
1835
Tejun Heoad616ff2006-11-01 18:00:24 +09001836static void ahci_vt8251_error_handler(struct ata_port *ap)
1837{
Tejun Heoad616ff2006-11-01 18:00:24 +09001838 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1839 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09001840 ahci_stop_engine(ap);
1841 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001842 }
1843
1844 /* perform recovery */
1845 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_vt8251_hardreset,
1846 ahci_postreset);
1847}
1848
Tejun Heoedc93052007-10-25 14:59:16 +09001849static void ahci_p5wdh_error_handler(struct ata_port *ap)
1850{
1851 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
1852 /* restart engine */
1853 ahci_stop_engine(ap);
1854 ahci_start_engine(ap);
1855 }
1856
1857 /* perform recovery */
1858 ata_do_eh(ap, ata_std_prereset, ahci_softreset, ahci_p5wdh_hardreset,
1859 ahci_postreset);
1860}
1861
Tejun Heo78cd52d2006-05-15 20:58:29 +09001862static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
1863{
1864 struct ata_port *ap = qc->ap;
1865
Tejun Heod2e75df2007-07-16 14:29:39 +09001866 /* make DMA engine forget about the failed command */
1867 if (qc->flags & ATA_QCFLAG_FAILED)
1868 ahci_kick_engine(ap, 1);
Tejun Heo78cd52d2006-05-15 20:58:29 +09001869}
1870
Tejun Heo7d50b602007-09-23 13:19:54 +09001871static void ahci_pmp_attach(struct ata_port *ap)
1872{
1873 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09001874 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09001875 u32 cmd;
1876
1877 cmd = readl(port_mmio + PORT_CMD);
1878 cmd |= PORT_CMD_PMP;
1879 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09001880
1881 pp->intr_mask |= PORT_IRQ_BAD_PMP;
1882 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09001883}
1884
1885static void ahci_pmp_detach(struct ata_port *ap)
1886{
1887 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09001888 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09001889 u32 cmd;
1890
1891 cmd = readl(port_mmio + PORT_CMD);
1892 cmd &= ~PORT_CMD_PMP;
1893 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09001894
1895 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
1896 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09001897}
1898
Alexey Dobriyan028a2592007-07-17 23:48:48 +04001899static int ahci_port_resume(struct ata_port *ap)
1900{
1901 ahci_power_up(ap);
1902 ahci_start_port(ap);
1903
Tejun Heo7d50b602007-09-23 13:19:54 +09001904 if (ap->nr_pmp_links)
1905 ahci_pmp_attach(ap);
1906 else
1907 ahci_pmp_detach(ap);
1908
Alexey Dobriyan028a2592007-07-17 23:48:48 +04001909 return 0;
1910}
1911
Tejun Heo438ac6d2007-03-02 17:31:26 +09001912#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +09001913static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
1914{
Tejun Heoc1332872006-07-26 15:59:26 +09001915 const char *emsg = NULL;
1916 int rc;
1917
Tejun Heo4447d352007-04-17 23:44:08 +09001918 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo8e16f942006-11-20 15:42:36 +09001919 if (rc == 0)
Tejun Heo4447d352007-04-17 23:44:08 +09001920 ahci_power_down(ap);
Tejun Heo8e16f942006-11-20 15:42:36 +09001921 else {
Tejun Heoc1332872006-07-26 15:59:26 +09001922 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001923 ahci_start_port(ap);
Tejun Heoc1332872006-07-26 15:59:26 +09001924 }
1925
1926 return rc;
1927}
1928
Tejun Heoc1332872006-07-26 15:59:26 +09001929static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1930{
Jeff Garzikcca39742006-08-24 03:19:22 -04001931 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09001932 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heoc1332872006-07-26 15:59:26 +09001933 u32 ctl;
1934
1935 if (mesg.event == PM_EVENT_SUSPEND) {
1936 /* AHCI spec rev1.1 section 8.3.3:
1937 * Software must disable interrupts prior to requesting a
1938 * transition of the HBA to D3 state.
1939 */
1940 ctl = readl(mmio + HOST_CTL);
1941 ctl &= ~HOST_IRQ_EN;
1942 writel(ctl, mmio + HOST_CTL);
1943 readl(mmio + HOST_CTL); /* flush */
1944 }
1945
1946 return ata_pci_device_suspend(pdev, mesg);
1947}
1948
1949static int ahci_pci_device_resume(struct pci_dev *pdev)
1950{
Jeff Garzikcca39742006-08-24 03:19:22 -04001951 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +09001952 int rc;
1953
Tejun Heo553c4aa2006-12-26 19:39:50 +09001954 rc = ata_pci_device_do_resume(pdev);
1955 if (rc)
1956 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +09001957
1958 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Tejun Heo4447d352007-04-17 23:44:08 +09001959 rc = ahci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001960 if (rc)
1961 return rc;
1962
Tejun Heo4447d352007-04-17 23:44:08 +09001963 ahci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001964 }
1965
Jeff Garzikcca39742006-08-24 03:19:22 -04001966 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +09001967
1968 return 0;
1969}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001970#endif
Tejun Heoc1332872006-07-26 15:59:26 +09001971
Tejun Heo254950c2006-07-26 15:59:25 +09001972static int ahci_port_start(struct ata_port *ap)
1973{
Jeff Garzikcca39742006-08-24 03:19:22 -04001974 struct device *dev = ap->host->dev;
Tejun Heo254950c2006-07-26 15:59:25 +09001975 struct ahci_port_priv *pp;
Tejun Heo254950c2006-07-26 15:59:25 +09001976 void *mem;
1977 dma_addr_t mem_dma;
1978 int rc;
1979
Tejun Heo24dc5f32007-01-20 16:00:28 +09001980 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Tejun Heo254950c2006-07-26 15:59:25 +09001981 if (!pp)
1982 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09001983
1984 rc = ata_pad_alloc(ap, dev);
Tejun Heo24dc5f32007-01-20 16:00:28 +09001985 if (rc)
Tejun Heo254950c2006-07-26 15:59:25 +09001986 return rc;
Tejun Heo254950c2006-07-26 15:59:25 +09001987
Tejun Heo24dc5f32007-01-20 16:00:28 +09001988 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
1989 GFP_KERNEL);
1990 if (!mem)
Tejun Heo254950c2006-07-26 15:59:25 +09001991 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09001992 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1993
1994 /*
1995 * First item in chunk of DMA memory: 32-slot command table,
1996 * 32 bytes each in size
1997 */
1998 pp->cmd_slot = mem;
1999 pp->cmd_slot_dma = mem_dma;
2000
2001 mem += AHCI_CMD_SLOT_SZ;
2002 mem_dma += AHCI_CMD_SLOT_SZ;
2003
2004 /*
2005 * Second item: Received-FIS area
2006 */
2007 pp->rx_fis = mem;
2008 pp->rx_fis_dma = mem_dma;
2009
2010 mem += AHCI_RX_FIS_SZ;
2011 mem_dma += AHCI_RX_FIS_SZ;
2012
2013 /*
2014 * Third item: data area for storing a single command
2015 * and its scatter-gather table
2016 */
2017 pp->cmd_tbl = mem;
2018 pp->cmd_tbl_dma = mem_dma;
2019
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002020 /*
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002021 * Save off initial list of interrupts to be enabled.
2022 * This could be changed later
2023 */
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002024 pp->intr_mask = DEF_PORT_IRQ;
2025
Tejun Heo254950c2006-07-26 15:59:25 +09002026 ap->private_data = pp;
2027
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002028 /* engage engines, captain */
2029 return ahci_port_resume(ap);
Tejun Heo254950c2006-07-26 15:59:25 +09002030}
2031
2032static void ahci_port_stop(struct ata_port *ap)
2033{
Tejun Heo0be0aa92006-07-26 15:59:26 +09002034 const char *emsg = NULL;
2035 int rc;
Tejun Heo254950c2006-07-26 15:59:25 +09002036
Tejun Heo0be0aa92006-07-26 15:59:26 +09002037 /* de-initialize port */
Tejun Heo4447d352007-04-17 23:44:08 +09002038 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo0be0aa92006-07-26 15:59:26 +09002039 if (rc)
2040 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
Tejun Heo254950c2006-07-26 15:59:25 +09002041}
2042
Tejun Heo4447d352007-04-17 23:44:08 +09002043static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002044{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002045 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002046
Linus Torvalds1da177e2005-04-16 15:20:36 -07002047 if (using_dac &&
2048 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2049 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
2050 if (rc) {
2051 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2052 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002053 dev_printk(KERN_ERR, &pdev->dev,
2054 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002055 return rc;
2056 }
2057 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002058 } else {
2059 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2060 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002061 dev_printk(KERN_ERR, &pdev->dev,
2062 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002063 return rc;
2064 }
2065 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2066 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002067 dev_printk(KERN_ERR, &pdev->dev,
2068 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002069 return rc;
2070 }
2071 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002072 return 0;
2073}
2074
Tejun Heo4447d352007-04-17 23:44:08 +09002075static void ahci_print_info(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002076{
Tejun Heo4447d352007-04-17 23:44:08 +09002077 struct ahci_host_priv *hpriv = host->private_data;
2078 struct pci_dev *pdev = to_pci_dev(host->dev);
2079 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002080 u32 vers, cap, impl, speed;
2081 const char *speed_s;
2082 u16 cc;
2083 const char *scc_s;
2084
2085 vers = readl(mmio + HOST_VERSION);
2086 cap = hpriv->cap;
2087 impl = hpriv->port_map;
2088
2089 speed = (cap >> 20) & 0xf;
2090 if (speed == 1)
2091 speed_s = "1.5";
2092 else if (speed == 2)
2093 speed_s = "3";
2094 else
2095 speed_s = "?";
2096
2097 pci_read_config_word(pdev, 0x0a, &cc);
Conke Huc9f89472007-01-09 05:32:51 -05002098 if (cc == PCI_CLASS_STORAGE_IDE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002099 scc_s = "IDE";
Conke Huc9f89472007-01-09 05:32:51 -05002100 else if (cc == PCI_CLASS_STORAGE_SATA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002101 scc_s = "SATA";
Conke Huc9f89472007-01-09 05:32:51 -05002102 else if (cc == PCI_CLASS_STORAGE_RAID)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002103 scc_s = "RAID";
2104 else
2105 scc_s = "unknown";
2106
Jeff Garzika9524a72005-10-30 14:39:11 -05002107 dev_printk(KERN_INFO, &pdev->dev,
2108 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -07002109 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002110 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002111
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002112 (vers >> 24) & 0xff,
2113 (vers >> 16) & 0xff,
2114 (vers >> 8) & 0xff,
2115 vers & 0xff,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002116
2117 ((cap >> 8) & 0x1f) + 1,
2118 (cap & 0x1f) + 1,
2119 speed_s,
2120 impl,
2121 scc_s);
2122
Jeff Garzika9524a72005-10-30 14:39:11 -05002123 dev_printk(KERN_INFO, &pdev->dev,
2124 "flags: "
Tejun Heo203ef6c2007-07-16 14:29:40 +09002125 "%s%s%s%s%s%s%s"
2126 "%s%s%s%s%s%s%s\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002127 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002128
2129 cap & (1 << 31) ? "64bit " : "",
2130 cap & (1 << 30) ? "ncq " : "",
Tejun Heo203ef6c2007-07-16 14:29:40 +09002131 cap & (1 << 29) ? "sntf " : "",
Linus Torvalds1da177e2005-04-16 15:20:36 -07002132 cap & (1 << 28) ? "ilck " : "",
2133 cap & (1 << 27) ? "stag " : "",
2134 cap & (1 << 26) ? "pm " : "",
2135 cap & (1 << 25) ? "led " : "",
2136
2137 cap & (1 << 24) ? "clo " : "",
2138 cap & (1 << 19) ? "nz " : "",
2139 cap & (1 << 18) ? "only " : "",
2140 cap & (1 << 17) ? "pmp " : "",
2141 cap & (1 << 15) ? "pio " : "",
2142 cap & (1 << 14) ? "slum " : "",
2143 cap & (1 << 13) ? "part " : ""
2144 );
2145}
2146
Tejun Heoedc93052007-10-25 14:59:16 +09002147/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2148 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2149 * support PMP and the 4726 either directly exports the device
2150 * attached to the first downstream port or acts as a hardware storage
2151 * controller and emulate a single ATA device (can be RAID 0/1 or some
2152 * other configuration).
2153 *
2154 * When there's no device attached to the first downstream port of the
2155 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2156 * configure the 4726. However, ATA emulation of the device is very
2157 * lame. It doesn't send signature D2H Reg FIS after the initial
2158 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2159 *
2160 * The following function works around the problem by always using
2161 * hardreset on the port and not depending on receiving signature FIS
2162 * afterward. If signature FIS isn't received soon, ATA class is
2163 * assumed without follow-up softreset.
2164 */
2165static void ahci_p5wdh_workaround(struct ata_host *host)
2166{
2167 static struct dmi_system_id sysids[] = {
2168 {
2169 .ident = "P5W DH Deluxe",
2170 .matches = {
2171 DMI_MATCH(DMI_SYS_VENDOR,
2172 "ASUSTEK COMPUTER INC"),
2173 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2174 },
2175 },
2176 { }
2177 };
2178 struct pci_dev *pdev = to_pci_dev(host->dev);
2179
2180 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2181 dmi_check_system(sysids)) {
2182 struct ata_port *ap = host->ports[1];
2183
2184 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2185 "Deluxe on-board SIMG4726 workaround\n");
2186
2187 ap->ops = &ahci_p5wdh_ops;
2188 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2189 }
2190}
2191
Tejun Heo24dc5f32007-01-20 16:00:28 +09002192static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002193{
2194 static int printed_version;
Tejun Heo4447d352007-04-17 23:44:08 +09002195 struct ata_port_info pi = ahci_port_info[ent->driver_data];
2196 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09002197 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002198 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09002199 struct ata_host *host;
Tejun Heo837f5f82008-02-06 15:13:51 +09002200 int n_ports, i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002201
2202 VPRINTK("ENTER\n");
2203
Tejun Heo12fad3f2006-05-15 21:03:55 +09002204 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2205
Linus Torvalds1da177e2005-04-16 15:20:36 -07002206 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05002207 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002208
Tejun Heo4447d352007-04-17 23:44:08 +09002209 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09002210 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002211 if (rc)
2212 return rc;
2213
Tejun Heo0d5ff562007-02-01 15:06:36 +09002214 rc = pcim_iomap_regions(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
2215 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002216 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002217 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002218 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002219
Tejun Heoc4f77922007-12-06 15:09:43 +09002220 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2221 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2222 u8 map;
2223
2224 /* ICH6s share the same PCI ID for both piix and ahci
2225 * modes. Enabling ahci mode while MAP indicates
2226 * combined mode is a bad idea. Yield to ata_piix.
2227 */
2228 pci_read_config_byte(pdev, ICH_MAP, &map);
2229 if (map & 0x3) {
2230 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2231 "combined mode, can't enable AHCI mode\n");
2232 return -ENODEV;
2233 }
2234 }
2235
Tejun Heo24dc5f32007-01-20 16:00:28 +09002236 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2237 if (!hpriv)
2238 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09002239 hpriv->flags |= (unsigned long)pi.private_data;
2240
2241 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
2242 pci_intx(pdev, 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002243
Tejun Heo4447d352007-04-17 23:44:08 +09002244 /* save initial config */
Tejun Heo417a1a62007-09-23 13:19:55 +09002245 ahci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002246
Tejun Heo4447d352007-04-17 23:44:08 +09002247 /* prepare host */
Tejun Heo274c1fd2007-07-16 14:29:40 +09002248 if (hpriv->cap & HOST_CAP_NCQ)
Tejun Heo4447d352007-04-17 23:44:08 +09002249 pi.flags |= ATA_FLAG_NCQ;
2250
Tejun Heo7d50b602007-09-23 13:19:54 +09002251 if (hpriv->cap & HOST_CAP_PMP)
2252 pi.flags |= ATA_FLAG_PMP;
2253
Tejun Heo837f5f82008-02-06 15:13:51 +09002254 /* CAP.NP sometimes indicate the index of the last enabled
2255 * port, at other times, that of the last possible port, so
2256 * determining the maximum port number requires looking at
2257 * both CAP.NP and port_map.
2258 */
2259 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2260
2261 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09002262 if (!host)
2263 return -ENOMEM;
2264 host->iomap = pcim_iomap_table(pdev);
2265 host->private_data = hpriv;
2266
2267 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04002268 struct ata_port *ap = host->ports[i];
2269 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +09002270
Tejun Heocbcdd872007-08-18 13:14:55 +09002271 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
2272 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
2273 0x100 + ap->port_no * 0x80, "port");
2274
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002275 /* set initial link pm policy */
2276 ap->pm_policy = NOT_AVAILABLE;
2277
Jeff Garzikdab632e2007-05-28 08:33:01 -04002278 /* standard SATA port setup */
Tejun Heo203ef6c2007-07-16 14:29:40 +09002279 if (hpriv->port_map & (1 << i))
Tejun Heo4447d352007-04-17 23:44:08 +09002280 ap->ioaddr.cmd_addr = port_mmio;
Jeff Garzikdab632e2007-05-28 08:33:01 -04002281
2282 /* disabled/not-implemented port */
2283 else
2284 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09002285 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002286
Tejun Heoedc93052007-10-25 14:59:16 +09002287 /* apply workaround for ASUS P5W DH Deluxe mainboard */
2288 ahci_p5wdh_workaround(host);
2289
Linus Torvalds1da177e2005-04-16 15:20:36 -07002290 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09002291 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002292 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002293 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002294
Tejun Heo4447d352007-04-17 23:44:08 +09002295 rc = ahci_reset_controller(host);
2296 if (rc)
2297 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09002298
Tejun Heo4447d352007-04-17 23:44:08 +09002299 ahci_init_controller(host);
2300 ahci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002301
Tejun Heo4447d352007-04-17 23:44:08 +09002302 pci_set_master(pdev);
2303 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
2304 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04002305}
Linus Torvalds1da177e2005-04-16 15:20:36 -07002306
2307static int __init ahci_init(void)
2308{
Pavel Roskinb7887192006-08-10 18:13:18 +09002309 return pci_register_driver(&ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002310}
2311
Linus Torvalds1da177e2005-04-16 15:20:36 -07002312static void __exit ahci_exit(void)
2313{
2314 pci_unregister_driver(&ahci_pci_driver);
2315}
2316
2317
2318MODULE_AUTHOR("Jeff Garzik");
2319MODULE_DESCRIPTION("AHCI SATA low-level driver");
2320MODULE_LICENSE("GPL");
2321MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04002322MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002323
2324module_init(ahci_init);
2325module_exit(ahci_exit);