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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ahci.c - AHCI SATA support
3 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04004 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
Linus Torvalds1da177e2005-04-16 15:20:36 -07007 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -04008 * Copyright 2004-2005 Red Hat, Inc.
Linus Torvalds1da177e2005-04-16 15:20:36 -07009 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
Linus Torvalds1da177e2005-04-16 15:20:36 -070030 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
Jeff Garzikaf36d7f2005-08-28 20:18:39 -040031 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
Linus Torvalds1da177e2005-04-16 15:20:36 -070032 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
domen@coderock.org87507cf2005-04-08 09:53:06 +020042#include <linux/dma-mapping.h>
Jeff Garzika9524a72005-10-30 14:39:11 -050043#include <linux/device.h>
Tejun Heoedc93052007-10-25 14:59:16 +090044#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070045#include <scsi/scsi_host.h>
Jeff Garzik193515d2005-11-07 00:59:37 -050046#include <scsi/scsi_cmnd.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070047#include <linux/libata.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49#define DRV_NAME "ahci"
Tejun Heo7d50b602007-09-23 13:19:54 +090050#define DRV_VERSION "3.0"
Linus Torvalds1da177e2005-04-16 15:20:36 -070051
David Milburn87943ac2008-10-13 14:38:36 -050052/* Enclosure Management Control */
53#define EM_CTRL_MSG_TYPE 0x000f0000
54
55/* Enclosure Management LED Message Type */
56#define EM_MSG_LED_HBA_PORT 0x0000000f
57#define EM_MSG_LED_PMP_SLOT 0x0000ff00
58#define EM_MSG_LED_VALUE 0xffff0000
59#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
60#define EM_MSG_LED_VALUE_OFF 0xfff80000
61#define EM_MSG_LED_VALUE_ON 0x00010000
62
Tejun Heoa22e6442008-03-10 10:25:25 +090063static int ahci_skip_host_reset;
Arjan van de Venf3d7f232009-01-26 02:05:44 -080064static int ahci_ignore_sss;
65
Tejun Heoa22e6442008-03-10 10:25:25 +090066module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
67MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
68
Arjan van de Venf3d7f232009-01-26 02:05:44 -080069module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
70MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
71
Kristen Carlson Accardi31556592007-10-25 01:33:26 -040072static int ahci_enable_alpm(struct ata_port *ap,
73 enum link_pm policy);
74static void ahci_disable_alpm(struct ata_port *ap);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -070075static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
76static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
77 size_t size);
78static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
79 ssize_t size);
Linus Torvalds1da177e2005-04-16 15:20:36 -070080
81enum {
82 AHCI_PCI_BAR = 5,
Tejun Heo648a88b2006-11-09 15:08:40 +090083 AHCI_MAX_PORTS = 32,
Linus Torvalds1da177e2005-04-16 15:20:36 -070084 AHCI_MAX_SG = 168, /* hardware max is 64K */
85 AHCI_DMA_BOUNDARY = 0xffffffff,
Tejun Heo12fad3f2006-05-15 21:03:55 +090086 AHCI_MAX_CMDS = 32,
Tejun Heodd410ff2006-05-15 21:03:50 +090087 AHCI_CMD_SZ = 32,
Tejun Heo12fad3f2006-05-15 21:03:55 +090088 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 AHCI_RX_FIS_SZ = 256,
Jeff Garzika0ea7322005-06-04 01:13:15 -040090 AHCI_CMD_TBL_CDB = 0x40,
Tejun Heodd410ff2006-05-15 21:03:50 +090091 AHCI_CMD_TBL_HDR_SZ = 0x80,
92 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
93 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
94 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 AHCI_RX_FIS_SZ,
96 AHCI_IRQ_ON_SG = (1 << 31),
97 AHCI_CMD_ATAPI = (1 << 5),
98 AHCI_CMD_WRITE = (1 << 6),
Tejun Heo4b10e552006-03-12 11:25:27 +090099 AHCI_CMD_PREFETCH = (1 << 7),
Tejun Heo22b49982006-01-23 21:38:44 +0900100 AHCI_CMD_RESET = (1 << 8),
101 AHCI_CMD_CLR_BUSY = (1 << 10),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102
103 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
Tejun Heo0291f952007-01-25 19:16:28 +0900104 RX_FIS_SDB = 0x58, /* offset of SDB FIS data */
Tejun Heo78cd52d2006-05-15 20:58:29 +0900105 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700106
107 board_ahci = 0,
Tejun Heo7a234af2007-09-03 12:44:57 +0900108 board_ahci_vt8251 = 1,
109 board_ahci_ign_iferr = 2,
110 board_ahci_sb600 = 3,
111 board_ahci_mv = 4,
Shane Huange427fe02008-12-30 10:53:41 +0800112 board_ahci_sb700 = 5, /* for SB700 and SB800 */
Tejun Heoe297d992008-06-10 00:13:04 +0900113 board_ahci_mcp65 = 6,
Tejun Heo9a3b1032008-06-18 20:56:58 -0400114 board_ahci_nopmp = 7,
Tejun Heoaa431dd2009-04-08 14:25:31 -0700115 board_ahci_yesncq = 8,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700116
117 /* global controller registers */
118 HOST_CAP = 0x00, /* host capabilities */
119 HOST_CTL = 0x04, /* global host control */
120 HOST_IRQ_STAT = 0x08, /* interrupt status */
121 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
122 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700123 HOST_EM_LOC = 0x1c, /* Enclosure Management location */
124 HOST_EM_CTL = 0x20, /* Enclosure Management Control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700125
126 /* HOST_CTL bits */
127 HOST_RESET = (1 << 0), /* reset controller; self-clear */
128 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
129 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
130
131 /* HOST_CAP bits */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700132 HOST_CAP_EMS = (1 << 6), /* Enclosure Management support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900133 HOST_CAP_SSC = (1 << 14), /* Slumber capable */
Tejun Heo7d50b602007-09-23 13:19:54 +0900134 HOST_CAP_PMP = (1 << 17), /* Port Multiplier support */
Tejun Heo22b49982006-01-23 21:38:44 +0900135 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400136 HOST_CAP_ALPM = (1 << 26), /* Aggressive Link PM support */
Tejun Heo0be0aa92006-07-26 15:59:26 +0900137 HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900138 HOST_CAP_SNTF = (1 << 29), /* SNotification register */
Tejun Heo979db802006-05-15 21:03:52 +0900139 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
Tejun Heodd410ff2006-05-15 21:03:50 +0900140 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700141
142 /* registers for each SATA port */
143 PORT_LST_ADDR = 0x00, /* command list DMA addr */
144 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
145 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
146 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
147 PORT_IRQ_STAT = 0x10, /* interrupt status */
148 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
149 PORT_CMD = 0x18, /* port command */
150 PORT_TFDATA = 0x20, /* taskfile data */
151 PORT_SIG = 0x24, /* device TF signature */
152 PORT_CMD_ISSUE = 0x38, /* command issue */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700153 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
154 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
155 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
156 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
Tejun Heo203ef6c2007-07-16 14:29:40 +0900157 PORT_SCR_NTF = 0x3c, /* SATA phy register: SNotification */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700158
159 /* PORT_IRQ_{STAT,MASK} bits */
160 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
161 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
162 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
163 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
164 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
165 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
166 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
167 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
168
169 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
170 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
171 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
172 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
173 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
174 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
175 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
176 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
177 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
178
Tejun Heo78cd52d2006-05-15 20:58:29 +0900179 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
180 PORT_IRQ_IF_ERR |
181 PORT_IRQ_CONNECT |
Tejun Heo42969712006-05-31 18:28:18 +0900182 PORT_IRQ_PHYRDY |
Tejun Heo7d50b602007-09-23 13:19:54 +0900183 PORT_IRQ_UNK_FIS |
184 PORT_IRQ_BAD_PMP,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900185 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
186 PORT_IRQ_TF_ERR |
187 PORT_IRQ_HBUS_DATA_ERR,
188 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
189 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
190 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191
192 /* PORT_CMD bits */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400193 PORT_CMD_ASP = (1 << 27), /* Aggressive Slumber/Partial */
194 PORT_CMD_ALPE = (1 << 26), /* Aggressive Link PM enable */
Jeff Garzik02eaa662005-11-12 01:32:19 -0500195 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
Tejun Heo7d50b602007-09-23 13:19:54 +0900196 PORT_CMD_PMP = (1 << 17), /* PMP attached */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
198 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
199 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
Tejun Heo22b49982006-01-23 21:38:44 +0900200 PORT_CMD_CLO = (1 << 3), /* Command list override */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
202 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
203 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
204
Tejun Heo0be0aa92006-07-26 15:59:26 +0900205 PORT_CMD_ICC_MASK = (0xf << 28), /* i/f ICC state mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
207 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
208 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
Jeff Garzik4b0060f2005-06-04 00:50:22 -0400209
Tejun Heo417a1a62007-09-23 13:19:55 +0900210 /* hpriv->flags bits */
211 AHCI_HFLAG_NO_NCQ = (1 << 0),
212 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1), /* ignore IRQ_IF_ERR */
213 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2), /* ignore SERR_INTERNAL */
214 AHCI_HFLAG_32BIT_ONLY = (1 << 3), /* force 32bit */
215 AHCI_HFLAG_MV_PATA = (1 << 4), /* PATA port */
216 AHCI_HFLAG_NO_MSI = (1 << 5), /* no PCI MSI */
Tejun Heo6949b912007-09-23 13:19:55 +0900217 AHCI_HFLAG_NO_PMP = (1 << 6), /* no PMP */
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400218 AHCI_HFLAG_NO_HOTPLUG = (1 << 7), /* ignore PxSERR.DIAG.N */
Jeff Garzika8785392008-02-28 15:43:48 -0500219 AHCI_HFLAG_SECT255 = (1 << 8), /* max 255 sectors */
Tejun Heoe297d992008-06-10 00:13:04 +0900220 AHCI_HFLAG_YES_NCQ = (1 << 9), /* force NCQ cap on */
Tejun Heo9b10ae82009-05-30 20:50:12 +0900221 AHCI_HFLAG_NO_SUSPEND = (1 << 10), /* don't suspend */
Tejun Heo55946392009-08-04 14:30:08 +0900222 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11), /* treat SRST timeout as
223 link offline */
Tejun Heo417a1a62007-09-23 13:19:55 +0900224
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200225 /* ap->flags bits */
Tejun Heo1188c0d2007-04-23 02:41:05 +0900226
227 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
228 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400229 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN |
230 ATA_FLAG_IPM,
Tejun Heoc4f77922007-12-06 15:09:43 +0900231
232 ICH_MAP = 0x90, /* ICH MAP register */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700233
Tejun Heod50ce072009-05-12 10:57:41 +0900234 /* em constants */
235 EM_MAX_SLOTS = 8,
236 EM_MAX_RETRY = 5,
237
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700238 /* em_ctl bits */
239 EM_CTL_RST = (1 << 9), /* Reset */
240 EM_CTL_TM = (1 << 8), /* Transmit Message */
241 EM_CTL_ALHD = (1 << 26), /* Activity LED */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242};
243
244struct ahci_cmd_hdr {
Al Viro4ca4e432007-12-30 09:32:22 +0000245 __le32 opts;
246 __le32 status;
247 __le32 tbl_addr;
248 __le32 tbl_addr_hi;
249 __le32 reserved[4];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700250};
251
252struct ahci_sg {
Al Viro4ca4e432007-12-30 09:32:22 +0000253 __le32 addr;
254 __le32 addr_hi;
255 __le32 reserved;
256 __le32 flags_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257};
258
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700259struct ahci_em_priv {
260 enum sw_activity blink_policy;
261 struct timer_list timer;
262 unsigned long saved_activity;
263 unsigned long activity;
264 unsigned long led_state;
265};
266
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267struct ahci_host_priv {
Tejun Heo417a1a62007-09-23 13:19:55 +0900268 unsigned int flags; /* AHCI_HFLAG_* */
Tejun Heod447df12007-03-18 22:15:33 +0900269 u32 cap; /* cap to use */
270 u32 port_map; /* port map to use */
271 u32 saved_cap; /* saved initial cap */
272 u32 saved_port_map; /* saved initial port_map */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700273 u32 em_loc; /* enclosure management location */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274};
275
276struct ahci_port_priv {
Tejun Heo7d50b602007-09-23 13:19:54 +0900277 struct ata_link *active_link;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278 struct ahci_cmd_hdr *cmd_slot;
279 dma_addr_t cmd_slot_dma;
280 void *cmd_tbl;
281 dma_addr_t cmd_tbl_dma;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282 void *rx_fis;
283 dma_addr_t rx_fis_dma;
Tejun Heo0291f952007-01-25 19:16:28 +0900284 /* for NCQ spurious interrupt analysis */
Tejun Heo0291f952007-01-25 19:16:28 +0900285 unsigned int ncq_saw_d2h:1;
286 unsigned int ncq_saw_dmas:1;
Tejun Heoafb2d552007-02-27 13:24:19 +0900287 unsigned int ncq_saw_sdb:1;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -0700288 u32 intr_mask; /* interrupts to enable */
Tejun Heod50ce072009-05-12 10:57:41 +0900289 /* enclosure management info per PM slot */
290 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700291};
292
Tejun Heo82ef04f2008-07-31 17:02:40 +0900293static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
294static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400295static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
Tejun Heo9a3d9eb2006-01-23 13:09:36 +0900296static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
Tejun Heo4c9bf4e2008-04-07 22:47:20 +0900297static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700298static int ahci_port_start(struct ata_port *ap);
299static void ahci_port_stop(struct ata_port *ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300static void ahci_qc_prep(struct ata_queued_cmd *qc);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900301static void ahci_freeze(struct ata_port *ap);
302static void ahci_thaw(struct ata_port *ap);
Tejun Heo7d50b602007-09-23 13:19:54 +0900303static void ahci_pmp_attach(struct ata_port *ap);
304static void ahci_pmp_detach(struct ata_port *ap);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900305static int ahci_softreset(struct ata_link *link, unsigned int *class,
306 unsigned long deadline);
Shane Huangbd172432008-06-10 15:52:04 +0800307static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
308 unsigned long deadline);
Tejun Heoa1efdab2008-03-25 12:22:50 +0900309static int ahci_hardreset(struct ata_link *link, unsigned int *class,
310 unsigned long deadline);
311static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
312 unsigned long deadline);
313static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
314 unsigned long deadline);
315static void ahci_postreset(struct ata_link *link, unsigned int *class);
Tejun Heo78cd52d2006-05-15 20:58:29 +0900316static void ahci_error_handler(struct ata_port *ap);
317static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -0400318static int ahci_port_resume(struct ata_port *ap);
Jeff Garzika8785392008-02-28 15:43:48 -0500319static void ahci_dev_config(struct ata_device *dev);
Jeff Garzikdab632e2007-05-28 08:33:01 -0400320static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
321 u32 opts);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900322#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900323static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
Tejun Heoc1332872006-07-26 15:59:26 +0900324static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
325static int ahci_pci_device_resume(struct pci_dev *pdev);
Tejun Heo438ac6d2007-03-02 17:31:26 +0900326#endif
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700327static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
328static ssize_t ahci_activity_store(struct ata_device *dev,
329 enum sw_activity val);
330static void ahci_init_sw_activity(struct ata_link *link);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331
Matthew Garrett77cdec12009-07-17 19:13:47 +0100332static ssize_t ahci_show_host_caps(struct device *dev,
333 struct device_attribute *attr, char *buf);
334static ssize_t ahci_show_host_version(struct device *dev,
335 struct device_attribute *attr, char *buf);
336static ssize_t ahci_show_port_cmd(struct device *dev,
337 struct device_attribute *attr, char *buf);
338
339DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
340DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
341DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
342
Tony Jonesee959b02008-02-22 00:13:36 +0100343static struct device_attribute *ahci_shost_attrs[] = {
344 &dev_attr_link_power_management_policy,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700345 &dev_attr_em_message_type,
346 &dev_attr_em_message,
Matthew Garrett77cdec12009-07-17 19:13:47 +0100347 &dev_attr_ahci_host_caps,
348 &dev_attr_ahci_host_version,
349 &dev_attr_ahci_port_cmd,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700350 NULL
351};
352
353static struct device_attribute *ahci_sdev_attrs[] = {
354 &dev_attr_sw_activity,
Elias Oltmanns45fabbb2008-09-21 11:54:08 +0200355 &dev_attr_unload_heads,
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400356 NULL
357};
358
Jeff Garzik193515d2005-11-07 00:59:37 -0500359static struct scsi_host_template ahci_sht = {
Tejun Heo68d1d072008-03-25 12:22:49 +0900360 ATA_NCQ_SHT(DRV_NAME),
Tejun Heo12fad3f2006-05-15 21:03:55 +0900361 .can_queue = AHCI_MAX_CMDS - 1,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700362 .sg_tablesize = AHCI_MAX_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363 .dma_boundary = AHCI_DMA_BOUNDARY,
Kristen Carlson Accardi31556592007-10-25 01:33:26 -0400364 .shost_attrs = ahci_shost_attrs,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700365 .sdev_attrs = ahci_sdev_attrs,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700366};
367
Tejun Heo029cfd62008-03-25 12:22:49 +0900368static struct ata_port_operations ahci_ops = {
369 .inherits = &sata_pmp_port_ops,
370
Tejun Heo7d50b602007-09-23 13:19:54 +0900371 .qc_defer = sata_pmp_qc_defer_cmd_switch,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700372 .qc_prep = ahci_qc_prep,
373 .qc_issue = ahci_qc_issue,
Tejun Heo4c9bf4e2008-04-07 22:47:20 +0900374 .qc_fill_rtf = ahci_qc_fill_rtf,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375
Tejun Heo78cd52d2006-05-15 20:58:29 +0900376 .freeze = ahci_freeze,
377 .thaw = ahci_thaw,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900378 .softreset = ahci_softreset,
379 .hardreset = ahci_hardreset,
380 .postreset = ahci_postreset,
Tejun Heo071f44b2008-04-07 22:47:22 +0900381 .pmp_softreset = ahci_softreset,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900382 .error_handler = ahci_error_handler,
383 .post_internal_cmd = ahci_post_internal_cmd,
Tejun Heo029cfd62008-03-25 12:22:49 +0900384 .dev_config = ahci_dev_config,
Tejun Heo78cd52d2006-05-15 20:58:29 +0900385
Tejun Heo029cfd62008-03-25 12:22:49 +0900386 .scr_read = ahci_scr_read,
387 .scr_write = ahci_scr_write,
Tejun Heo7d50b602007-09-23 13:19:54 +0900388 .pmp_attach = ahci_pmp_attach,
389 .pmp_detach = ahci_pmp_detach,
Tejun Heo7d50b602007-09-23 13:19:54 +0900390
Tejun Heo029cfd62008-03-25 12:22:49 +0900391 .enable_pm = ahci_enable_alpm,
392 .disable_pm = ahci_disable_alpm,
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700393 .em_show = ahci_led_show,
394 .em_store = ahci_led_store,
395 .sw_activity_show = ahci_activity_show,
396 .sw_activity_store = ahci_activity_store,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900397#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900398 .port_suspend = ahci_port_suspend,
399 .port_resume = ahci_port_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900400#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700401 .port_start = ahci_port_start,
402 .port_stop = ahci_port_stop,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403};
404
Tejun Heo029cfd62008-03-25 12:22:49 +0900405static struct ata_port_operations ahci_vt8251_ops = {
406 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900407 .hardreset = ahci_vt8251_hardreset,
Tejun Heoad616ff2006-11-01 18:00:24 +0900408};
409
Tejun Heo029cfd62008-03-25 12:22:49 +0900410static struct ata_port_operations ahci_p5wdh_ops = {
411 .inherits = &ahci_ops,
Tejun Heoa1efdab2008-03-25 12:22:50 +0900412 .hardreset = ahci_p5wdh_hardreset,
Tejun Heoedc93052007-10-25 14:59:16 +0900413};
414
Shane Huangbd172432008-06-10 15:52:04 +0800415static struct ata_port_operations ahci_sb600_ops = {
416 .inherits = &ahci_ops,
417 .softreset = ahci_sb600_softreset,
418 .pmp_softreset = ahci_sb600_softreset,
419};
420
Tejun Heo417a1a62007-09-23 13:19:55 +0900421#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
422
Arjan van de Ven98ac62d2005-11-28 10:06:23 +0100423static const struct ata_port_info ahci_port_info[] = {
Jeff Garzik4da646b2009-04-08 02:00:13 -0400424 [board_ahci] =
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425 {
Tejun Heo1188c0d2007-04-23 02:41:05 +0900426 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100427 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400428 .udma_mask = ATA_UDMA6,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700429 .port_ops = &ahci_ops,
430 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400431 [board_ahci_vt8251] =
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200432 {
Tejun Heo6949b912007-09-23 13:19:55 +0900433 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
Tejun Heo417a1a62007-09-23 13:19:55 +0900434 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100435 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400436 .udma_mask = ATA_UDMA6,
Tejun Heoad616ff2006-11-01 18:00:24 +0900437 .port_ops = &ahci_vt8251_ops,
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +0200438 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400439 [board_ahci_ign_iferr] =
Tejun Heo41669552006-11-29 11:33:14 +0900440 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900441 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
442 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100443 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400444 .udma_mask = ATA_UDMA6,
Tejun Heo41669552006-11-29 11:33:14 +0900445 .port_ops = &ahci_ops,
446 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400447 [board_ahci_sb600] =
Conke Hu55a61602007-03-27 18:33:05 +0800448 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900449 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
Shane Huang58a09b32009-05-27 15:04:43 +0800450 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255),
Tejun Heo417a1a62007-09-23 13:19:55 +0900451 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100452 .pio_mask = ATA_PIO4,
Jeff Garzik469248a2007-07-08 01:13:16 -0400453 .udma_mask = ATA_UDMA6,
Shane Huangbd172432008-06-10 15:52:04 +0800454 .port_ops = &ahci_sb600_ops,
Conke Hu55a61602007-03-27 18:33:05 +0800455 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400456 [board_ahci_mv] =
Jeff Garzikcd70c262007-07-08 02:29:42 -0400457 {
Tejun Heo417a1a62007-09-23 13:19:55 +0900458 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
Tejun Heo17248462008-08-29 16:03:59 +0200459 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
Jeff Garzikcd70c262007-07-08 02:29:42 -0400460 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
Tejun Heo417a1a62007-09-23 13:19:55 +0900461 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100462 .pio_mask = ATA_PIO4,
Jeff Garzikcd70c262007-07-08 02:29:42 -0400463 .udma_mask = ATA_UDMA6,
464 .port_ops = &ahci_ops,
465 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400466 [board_ahci_sb700] = /* for SB700 and SB800 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800467 {
Shane Huangbd172432008-06-10 15:52:04 +0800468 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
Shane Huange39fc8c2008-02-22 05:00:31 -0800469 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100470 .pio_mask = ATA_PIO4,
Shane Huange39fc8c2008-02-22 05:00:31 -0800471 .udma_mask = ATA_UDMA6,
Shane Huangbd172432008-06-10 15:52:04 +0800472 .port_ops = &ahci_sb600_ops,
Shane Huange39fc8c2008-02-22 05:00:31 -0800473 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400474 [board_ahci_mcp65] =
Tejun Heoe297d992008-06-10 00:13:04 +0900475 {
476 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
477 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100478 .pio_mask = ATA_PIO4,
Tejun Heoe297d992008-06-10 00:13:04 +0900479 .udma_mask = ATA_UDMA6,
480 .port_ops = &ahci_ops,
481 },
Jeff Garzik4da646b2009-04-08 02:00:13 -0400482 [board_ahci_nopmp] =
Tejun Heo9a3b1032008-06-18 20:56:58 -0400483 {
484 AHCI_HFLAGS (AHCI_HFLAG_NO_PMP),
485 .flags = AHCI_FLAG_COMMON,
Erik Inge Bolsø14bdef92009-03-14 21:38:24 +0100486 .pio_mask = ATA_PIO4,
Tejun Heo9a3b1032008-06-18 20:56:58 -0400487 .udma_mask = ATA_UDMA6,
488 .port_ops = &ahci_ops,
489 },
Tejun Heoaa431dd2009-04-08 14:25:31 -0700490 /* board_ahci_yesncq */
491 {
492 AHCI_HFLAGS (AHCI_HFLAG_YES_NCQ),
493 .flags = AHCI_FLAG_COMMON,
494 .pio_mask = ATA_PIO4,
495 .udma_mask = ATA_UDMA6,
496 .port_ops = &ahci_ops,
497 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498};
499
Jeff Garzik3b7d6972005-11-10 11:04:11 -0500500static const struct pci_device_id ahci_pci_tbl[] = {
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400501 /* Intel */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400502 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
503 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
504 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
505 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
506 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
Tejun Heo82490c02007-01-23 15:13:39 +0900507 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400508 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
509 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
510 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
511 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
Tejun Heo7a234af2007-09-03 12:44:57 +0900512 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
513 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
514 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
515 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
516 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
517 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
518 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
519 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
520 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
521 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
522 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
523 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
524 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
525 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
526 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
527 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
528 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
Jason Gastond4155e62007-09-20 17:35:00 -0400529 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
530 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800531 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
Mark Goodwinb2dde6a2009-06-26 10:44:11 -0500532 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
Jason Gaston16ad1ad2008-01-28 17:34:14 -0800533 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
David Milburnc1f57d92009-07-22 15:15:56 -0500534 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
535 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700536 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700537 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500538 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
Seth Heasleyadcb5302008-08-11 17:03:09 -0700539 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
Seth Heasley8e48b6b2008-08-27 16:47:22 -0700540 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
David Milburnc1f57d92009-07-22 15:15:56 -0500541 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400542
Tejun Heoe34bb372007-02-26 20:24:03 +0900543 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
544 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
545 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400546
547 /* ATI */
Conke Huc65ec1c2007-04-11 18:23:14 +0800548 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
Shane Huange39fc8c2008-02-22 05:00:31 -0800549 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
550 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
551 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
552 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
553 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
554 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400555
Shane Huange2dd90b2009-07-29 11:34:49 +0800556 /* AMD */
557 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD SB900 */
558 /* AMD is using RAID class only for ahci controllers */
559 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
560 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
561
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400562 /* VIA */
Jeff Garzik54bb3a942006-09-27 22:20:11 -0400563 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
Tejun Heobf335542007-04-11 17:27:14 +0900564 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400565
566 /* NVIDIA */
Tejun Heoe297d992008-06-10 00:13:04 +0900567 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
568 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
569 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
570 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
571 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
572 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
573 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
574 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
Tejun Heoaa431dd2009-04-08 14:25:31 -0700575 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_yesncq }, /* MCP67 */
576 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_yesncq }, /* MCP67 */
577 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_yesncq }, /* MCP67 */
578 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_yesncq }, /* MCP67 */
579 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_yesncq }, /* MCP67 */
580 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_yesncq }, /* MCP67 */
581 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_yesncq }, /* MCP67 */
582 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_yesncq }, /* MCP67 */
583 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_yesncq }, /* MCP67 */
584 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_yesncq }, /* MCP67 */
585 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_yesncq }, /* MCP67 */
586 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_yesncq }, /* MCP67 */
587 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_yesncq }, /* MCP73 */
588 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_yesncq }, /* MCP73 */
589 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_yesncq }, /* MCP73 */
590 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_yesncq }, /* MCP73 */
591 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_yesncq }, /* MCP73 */
592 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_yesncq }, /* MCP73 */
593 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_yesncq }, /* MCP73 */
594 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_yesncq }, /* MCP73 */
595 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_yesncq }, /* MCP73 */
596 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_yesncq }, /* MCP73 */
597 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_yesncq }, /* MCP73 */
598 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_yesncq }, /* MCP73 */
Peer Chen0522b282007-06-07 18:05:12 +0800599 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci }, /* MCP77 */
600 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci }, /* MCP77 */
601 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci }, /* MCP77 */
602 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci }, /* MCP77 */
603 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci }, /* MCP77 */
604 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci }, /* MCP77 */
605 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci }, /* MCP77 */
606 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci }, /* MCP77 */
607 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci }, /* MCP77 */
608 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci }, /* MCP77 */
609 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci }, /* MCP77 */
610 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci }, /* MCP77 */
peerchen6ba86952007-12-03 22:20:37 +0800611 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci }, /* MCP79 */
612 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci }, /* MCP79 */
613 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci }, /* MCP79 */
614 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci }, /* MCP79 */
Peer Chen71008192007-09-24 10:16:25 +0800615 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci }, /* MCP79 */
616 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci }, /* MCP79 */
617 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci }, /* MCP79 */
618 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci }, /* MCP79 */
619 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci }, /* MCP79 */
620 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */
621 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */
622 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */
peerchen7adbe462009-02-27 16:58:41 +0800623 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */
624 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */
625 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */
626 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */
627 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */
628 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */
629 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */
630 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */
631 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */
632 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */
633 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */
634 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */
Jeff Garzikfe7fa312006-06-22 23:05:36 -0400635
Jeff Garzik95916ed2006-07-29 04:10:14 -0400636 /* SiS */
Tejun Heo20e2de42008-08-01 12:51:43 +0900637 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
638 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
639 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
Jeff Garzik95916ed2006-07-29 04:10:14 -0400640
Jeff Garzikcd70c262007-07-08 02:29:42 -0400641 /* Marvell */
642 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100643 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
Jeff Garzikcd70c262007-07-08 02:29:42 -0400644
Mark Nelsonc77a0362008-10-23 14:08:16 +1100645 /* Promise */
646 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
647
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500648 /* Generic, PCI class code for AHCI */
649 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
Conke Huc9f89472007-01-09 05:32:51 -0500650 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
Jeff Garzik415ae2b2006-11-01 05:10:42 -0500651
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652 { } /* terminate list */
653};
654
655
656static struct pci_driver ahci_pci_driver = {
657 .name = DRV_NAME,
658 .id_table = ahci_pci_tbl,
659 .probe = ahci_init_one,
Tejun Heo24dc5f32007-01-20 16:00:28 +0900660 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900661#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +0900662 .suspend = ahci_pci_device_suspend,
663 .resume = ahci_pci_device_resume,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900664#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665};
666
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -0700667static int ahci_em_messages = 1;
668module_param(ahci_em_messages, int, 0444);
669/* add other LED protocol types when they become supported */
670MODULE_PARM_DESC(ahci_em_messages,
671 "Set AHCI Enclosure Management Message type (0 = disabled, 1 = LED");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700672
Alan Cox5b66c822008-09-03 14:48:34 +0100673#if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
674static int marvell_enable;
675#else
676static int marvell_enable = 1;
677#endif
678module_param(marvell_enable, int, 0644);
679MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
680
681
Tejun Heo98fa4b62006-11-02 12:17:23 +0900682static inline int ahci_nr_ports(u32 cap)
683{
684 return (cap & 0x1f) + 1;
685}
686
Jeff Garzikdab632e2007-05-28 08:33:01 -0400687static inline void __iomem *__ahci_port_base(struct ata_host *host,
688 unsigned int port_no)
689{
690 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
691
692 return mmio + 0x100 + (port_no * 0x80);
693}
694
Tejun Heo4447d352007-04-17 23:44:08 +0900695static inline void __iomem *ahci_port_base(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696{
Jeff Garzikdab632e2007-05-28 08:33:01 -0400697 return __ahci_port_base(ap->host, ap->port_no);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698}
699
Tejun Heob710a1f2008-01-05 23:11:57 +0900700static void ahci_enable_ahci(void __iomem *mmio)
701{
Tejun Heo15fe9822008-04-23 20:52:58 +0900702 int i;
Tejun Heob710a1f2008-01-05 23:11:57 +0900703 u32 tmp;
704
705 /* turn on AHCI_EN */
706 tmp = readl(mmio + HOST_CTL);
Tejun Heo15fe9822008-04-23 20:52:58 +0900707 if (tmp & HOST_AHCI_EN)
708 return;
709
710 /* Some controllers need AHCI_EN to be written multiple times.
711 * Try a few times before giving up.
712 */
713 for (i = 0; i < 5; i++) {
Tejun Heob710a1f2008-01-05 23:11:57 +0900714 tmp |= HOST_AHCI_EN;
715 writel(tmp, mmio + HOST_CTL);
716 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
Tejun Heo15fe9822008-04-23 20:52:58 +0900717 if (tmp & HOST_AHCI_EN)
718 return;
719 msleep(10);
Tejun Heob710a1f2008-01-05 23:11:57 +0900720 }
Tejun Heo15fe9822008-04-23 20:52:58 +0900721
722 WARN_ON(1);
Tejun Heob710a1f2008-01-05 23:11:57 +0900723}
724
Matthew Garrett77cdec12009-07-17 19:13:47 +0100725static ssize_t ahci_show_host_caps(struct device *dev,
726 struct device_attribute *attr, char *buf)
727{
728 struct Scsi_Host *shost = class_to_shost(dev);
729 struct ata_port *ap = ata_shost_to_port(shost);
730 struct ahci_host_priv *hpriv = ap->host->private_data;
731
732 return sprintf(buf, "%x\n", hpriv->cap);
733}
734
735static ssize_t ahci_show_host_version(struct device *dev,
736 struct device_attribute *attr, char *buf)
737{
738 struct Scsi_Host *shost = class_to_shost(dev);
739 struct ata_port *ap = ata_shost_to_port(shost);
740 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
741
742 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
743}
744
745static ssize_t ahci_show_port_cmd(struct device *dev,
746 struct device_attribute *attr, char *buf)
747{
748 struct Scsi_Host *shost = class_to_shost(dev);
749 struct ata_port *ap = ata_shost_to_port(shost);
750 void __iomem *port_mmio = ahci_port_base(ap);
751
752 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
753}
754
Tejun Heod447df12007-03-18 22:15:33 +0900755/**
756 * ahci_save_initial_config - Save and fixup initial config values
Tejun Heo4447d352007-04-17 23:44:08 +0900757 * @pdev: target PCI device
Tejun Heo4447d352007-04-17 23:44:08 +0900758 * @hpriv: host private area to store config values
Tejun Heod447df12007-03-18 22:15:33 +0900759 *
760 * Some registers containing configuration info might be setup by
761 * BIOS and might be cleared on reset. This function saves the
762 * initial values of those registers into @hpriv such that they
763 * can be restored after controller reset.
764 *
765 * If inconsistent, config values are fixed up by this function.
766 *
767 * LOCKING:
768 * None.
769 */
Tejun Heo4447d352007-04-17 23:44:08 +0900770static void ahci_save_initial_config(struct pci_dev *pdev,
Tejun Heo4447d352007-04-17 23:44:08 +0900771 struct ahci_host_priv *hpriv)
Tejun Heod447df12007-03-18 22:15:33 +0900772{
Tejun Heo4447d352007-04-17 23:44:08 +0900773 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +0900774 u32 cap, port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900775 int i;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100776 int mv;
Tejun Heod447df12007-03-18 22:15:33 +0900777
Tejun Heob710a1f2008-01-05 23:11:57 +0900778 /* make sure AHCI mode is enabled before accessing CAP */
779 ahci_enable_ahci(mmio);
780
Tejun Heod447df12007-03-18 22:15:33 +0900781 /* Values prefixed with saved_ are written back to host after
782 * reset. Values without are used for driver operation.
783 */
784 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
785 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
786
Tejun Heo274c1fd2007-07-16 14:29:40 +0900787 /* some chips have errata preventing 64bit use */
Tejun Heo417a1a62007-09-23 13:19:55 +0900788 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
Tejun Heoc7a42152007-05-18 16:23:19 +0200789 dev_printk(KERN_INFO, &pdev->dev,
790 "controller can't do 64bit DMA, forcing 32bit\n");
791 cap &= ~HOST_CAP_64;
792 }
793
Tejun Heo417a1a62007-09-23 13:19:55 +0900794 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
Tejun Heo274c1fd2007-07-16 14:29:40 +0900795 dev_printk(KERN_INFO, &pdev->dev,
796 "controller can't do NCQ, turning off CAP_NCQ\n");
797 cap &= ~HOST_CAP_NCQ;
798 }
799
Tejun Heoe297d992008-06-10 00:13:04 +0900800 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
801 dev_printk(KERN_INFO, &pdev->dev,
802 "controller can do NCQ, turning on CAP_NCQ\n");
803 cap |= HOST_CAP_NCQ;
804 }
805
Roel Kluin258cd842008-03-09 21:42:40 +0100806 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
Tejun Heo6949b912007-09-23 13:19:55 +0900807 dev_printk(KERN_INFO, &pdev->dev,
808 "controller can't do PMP, turning off CAP_PMP\n");
809 cap &= ~HOST_CAP_PMP;
810 }
811
Tejun Heod799e082008-06-17 12:46:30 +0900812 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
813 port_map != 1) {
814 dev_printk(KERN_INFO, &pdev->dev,
815 "JMB361 has only one port, port_map 0x%x -> 0x%x\n",
816 port_map, 1);
817 port_map = 1;
818 }
819
Jeff Garzikcd70c262007-07-08 02:29:42 -0400820 /*
821 * Temporary Marvell 6145 hack: PATA port presence
822 * is asserted through the standard AHCI port
823 * presence register, as bit 4 (counting from 0)
824 */
Tejun Heo417a1a62007-09-23 13:19:55 +0900825 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100826 if (pdev->device == 0x6121)
827 mv = 0x3;
828 else
829 mv = 0xf;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400830 dev_printk(KERN_ERR, &pdev->dev,
831 "MV_AHCI HACK: port_map %x -> %x\n",
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100832 port_map,
833 port_map & mv);
Alan Cox5b66c822008-09-03 14:48:34 +0100834 dev_printk(KERN_ERR, &pdev->dev,
835 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
Jeff Garzikcd70c262007-07-08 02:29:42 -0400836
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +0100837 port_map &= mv;
Jeff Garzikcd70c262007-07-08 02:29:42 -0400838 }
839
Tejun Heo17199b12007-03-18 22:26:53 +0900840 /* cross check port_map and cap.n_ports */
Tejun Heo7a234af2007-09-03 12:44:57 +0900841 if (port_map) {
Tejun Heo837f5f82008-02-06 15:13:51 +0900842 int map_ports = 0;
Tejun Heo17199b12007-03-18 22:26:53 +0900843
Tejun Heo837f5f82008-02-06 15:13:51 +0900844 for (i = 0; i < AHCI_MAX_PORTS; i++)
845 if (port_map & (1 << i))
846 map_ports++;
Tejun Heo17199b12007-03-18 22:26:53 +0900847
Tejun Heo837f5f82008-02-06 15:13:51 +0900848 /* If PI has more ports than n_ports, whine, clear
849 * port_map and let it be generated from n_ports.
Tejun Heo17199b12007-03-18 22:26:53 +0900850 */
Tejun Heo837f5f82008-02-06 15:13:51 +0900851 if (map_ports > ahci_nr_ports(cap)) {
Tejun Heo4447d352007-04-17 23:44:08 +0900852 dev_printk(KERN_WARNING, &pdev->dev,
Tejun Heo837f5f82008-02-06 15:13:51 +0900853 "implemented port map (0x%x) contains more "
854 "ports than nr_ports (%u), using nr_ports\n",
855 port_map, ahci_nr_ports(cap));
Tejun Heo7a234af2007-09-03 12:44:57 +0900856 port_map = 0;
857 }
858 }
859
860 /* fabricate port_map from cap.nr_ports */
861 if (!port_map) {
Tejun Heo17199b12007-03-18 22:26:53 +0900862 port_map = (1 << ahci_nr_ports(cap)) - 1;
Tejun Heo7a234af2007-09-03 12:44:57 +0900863 dev_printk(KERN_WARNING, &pdev->dev,
864 "forcing PORTS_IMPL to 0x%x\n", port_map);
865
866 /* write the fixed up value to the PI register */
867 hpriv->saved_port_map = port_map;
Tejun Heo17199b12007-03-18 22:26:53 +0900868 }
869
Tejun Heod447df12007-03-18 22:15:33 +0900870 /* record values to use during operation */
871 hpriv->cap = cap;
872 hpriv->port_map = port_map;
873}
874
875/**
876 * ahci_restore_initial_config - Restore initial config
Tejun Heo4447d352007-04-17 23:44:08 +0900877 * @host: target ATA host
Tejun Heod447df12007-03-18 22:15:33 +0900878 *
879 * Restore initial config stored by ahci_save_initial_config().
880 *
881 * LOCKING:
882 * None.
883 */
Tejun Heo4447d352007-04-17 23:44:08 +0900884static void ahci_restore_initial_config(struct ata_host *host)
Tejun Heod447df12007-03-18 22:15:33 +0900885{
Tejun Heo4447d352007-04-17 23:44:08 +0900886 struct ahci_host_priv *hpriv = host->private_data;
887 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
888
Tejun Heod447df12007-03-18 22:15:33 +0900889 writel(hpriv->saved_cap, mmio + HOST_CAP);
890 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
891 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
892}
893
Tejun Heo203ef6c2007-07-16 14:29:40 +0900894static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700895{
Tejun Heo203ef6c2007-07-16 14:29:40 +0900896 static const int offset[] = {
897 [SCR_STATUS] = PORT_SCR_STAT,
898 [SCR_CONTROL] = PORT_SCR_CTL,
899 [SCR_ERROR] = PORT_SCR_ERR,
900 [SCR_ACTIVE] = PORT_SCR_ACT,
901 [SCR_NOTIFICATION] = PORT_SCR_NTF,
902 };
903 struct ahci_host_priv *hpriv = ap->host->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700904
Tejun Heo203ef6c2007-07-16 14:29:40 +0900905 if (sc_reg < ARRAY_SIZE(offset) &&
906 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
907 return offset[sc_reg];
Tejun Heoda3dbb12007-07-16 14:29:40 +0900908 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700909}
910
Tejun Heo82ef04f2008-07-31 17:02:40 +0900911static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700912{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900913 void __iomem *port_mmio = ahci_port_base(link->ap);
914 int offset = ahci_scr_offset(link->ap, sc_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700915
Tejun Heo203ef6c2007-07-16 14:29:40 +0900916 if (offset) {
917 *val = readl(port_mmio + offset);
918 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700919 }
Tejun Heo203ef6c2007-07-16 14:29:40 +0900920 return -EINVAL;
921}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700922
Tejun Heo82ef04f2008-07-31 17:02:40 +0900923static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
Tejun Heo203ef6c2007-07-16 14:29:40 +0900924{
Tejun Heo82ef04f2008-07-31 17:02:40 +0900925 void __iomem *port_mmio = ahci_port_base(link->ap);
926 int offset = ahci_scr_offset(link->ap, sc_reg);
Tejun Heo203ef6c2007-07-16 14:29:40 +0900927
928 if (offset) {
929 writel(val, port_mmio + offset);
930 return 0;
931 }
932 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933}
934
Tejun Heo4447d352007-04-17 23:44:08 +0900935static void ahci_start_engine(struct ata_port *ap)
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900936{
Tejun Heo4447d352007-04-17 23:44:08 +0900937 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900938 u32 tmp;
939
Tejun Heod8fcd112006-07-26 15:59:25 +0900940 /* start DMA */
Tejun Heo9f592052006-07-26 15:59:26 +0900941 tmp = readl(port_mmio + PORT_CMD);
Tejun Heo7c76d1e2005-12-19 22:36:34 +0900942 tmp |= PORT_CMD_START;
943 writel(tmp, port_mmio + PORT_CMD);
944 readl(port_mmio + PORT_CMD); /* flush */
945}
946
Tejun Heo4447d352007-04-17 23:44:08 +0900947static int ahci_stop_engine(struct ata_port *ap)
Tejun Heo254950c2006-07-26 15:59:25 +0900948{
Tejun Heo4447d352007-04-17 23:44:08 +0900949 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo254950c2006-07-26 15:59:25 +0900950 u32 tmp;
951
952 tmp = readl(port_mmio + PORT_CMD);
953
Tejun Heod8fcd112006-07-26 15:59:25 +0900954 /* check if the HBA is idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900955 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
956 return 0;
957
Tejun Heod8fcd112006-07-26 15:59:25 +0900958 /* setting HBA to idle */
Tejun Heo254950c2006-07-26 15:59:25 +0900959 tmp &= ~PORT_CMD_START;
960 writel(tmp, port_mmio + PORT_CMD);
961
Tejun Heod8fcd112006-07-26 15:59:25 +0900962 /* wait for engine to stop. This could be as long as 500 msec */
Tejun Heo254950c2006-07-26 15:59:25 +0900963 tmp = ata_wait_register(port_mmio + PORT_CMD,
Jeff Garzik2dcb4072007-10-19 06:42:56 -0400964 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
Tejun Heod8fcd112006-07-26 15:59:25 +0900965 if (tmp & PORT_CMD_LIST_ON)
Tejun Heo254950c2006-07-26 15:59:25 +0900966 return -EIO;
967
968 return 0;
969}
970
Tejun Heo4447d352007-04-17 23:44:08 +0900971static void ahci_start_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900972{
Tejun Heo4447d352007-04-17 23:44:08 +0900973 void __iomem *port_mmio = ahci_port_base(ap);
974 struct ahci_host_priv *hpriv = ap->host->private_data;
975 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo0be0aa92006-07-26 15:59:26 +0900976 u32 tmp;
977
978 /* set FIS registers */
Tejun Heo4447d352007-04-17 23:44:08 +0900979 if (hpriv->cap & HOST_CAP_64)
980 writel((pp->cmd_slot_dma >> 16) >> 16,
981 port_mmio + PORT_LST_ADDR_HI);
982 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900983
Tejun Heo4447d352007-04-17 23:44:08 +0900984 if (hpriv->cap & HOST_CAP_64)
985 writel((pp->rx_fis_dma >> 16) >> 16,
986 port_mmio + PORT_FIS_ADDR_HI);
987 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
Tejun Heo0be0aa92006-07-26 15:59:26 +0900988
989 /* enable FIS reception */
990 tmp = readl(port_mmio + PORT_CMD);
991 tmp |= PORT_CMD_FIS_RX;
992 writel(tmp, port_mmio + PORT_CMD);
993
994 /* flush */
995 readl(port_mmio + PORT_CMD);
996}
997
Tejun Heo4447d352007-04-17 23:44:08 +0900998static int ahci_stop_fis_rx(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +0900999{
Tejun Heo4447d352007-04-17 23:44:08 +09001000 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001001 u32 tmp;
1002
1003 /* disable FIS reception */
1004 tmp = readl(port_mmio + PORT_CMD);
1005 tmp &= ~PORT_CMD_FIS_RX;
1006 writel(tmp, port_mmio + PORT_CMD);
1007
1008 /* wait for completion, spec says 500ms, give it 1000 */
1009 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
1010 PORT_CMD_FIS_ON, 10, 1000);
1011 if (tmp & PORT_CMD_FIS_ON)
1012 return -EBUSY;
1013
1014 return 0;
1015}
1016
Tejun Heo4447d352007-04-17 23:44:08 +09001017static void ahci_power_up(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001018{
Tejun Heo4447d352007-04-17 23:44:08 +09001019 struct ahci_host_priv *hpriv = ap->host->private_data;
1020 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001021 u32 cmd;
1022
1023 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
1024
1025 /* spin up device */
Tejun Heo4447d352007-04-17 23:44:08 +09001026 if (hpriv->cap & HOST_CAP_SSS) {
Tejun Heo0be0aa92006-07-26 15:59:26 +09001027 cmd |= PORT_CMD_SPIN_UP;
1028 writel(cmd, port_mmio + PORT_CMD);
1029 }
1030
1031 /* wake up link */
1032 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
1033}
1034
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04001035static void ahci_disable_alpm(struct ata_port *ap)
1036{
1037 struct ahci_host_priv *hpriv = ap->host->private_data;
1038 void __iomem *port_mmio = ahci_port_base(ap);
1039 u32 cmd;
1040 struct ahci_port_priv *pp = ap->private_data;
1041
1042 /* IPM bits should be disabled by libata-core */
1043 /* get the existing command bits */
1044 cmd = readl(port_mmio + PORT_CMD);
1045
1046 /* disable ALPM and ASP */
1047 cmd &= ~PORT_CMD_ASP;
1048 cmd &= ~PORT_CMD_ALPE;
1049
1050 /* force the interface back to active */
1051 cmd |= PORT_CMD_ICC_ACTIVE;
1052
1053 /* write out new cmd value */
1054 writel(cmd, port_mmio + PORT_CMD);
1055 cmd = readl(port_mmio + PORT_CMD);
1056
1057 /* wait 10ms to be sure we've come out of any low power state */
1058 msleep(10);
1059
1060 /* clear out any PhyRdy stuff from interrupt status */
1061 writel(PORT_IRQ_PHYRDY, port_mmio + PORT_IRQ_STAT);
1062
1063 /* go ahead and clean out PhyRdy Change from Serror too */
Tejun Heo82ef04f2008-07-31 17:02:40 +09001064 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04001065
1066 /*
1067 * Clear flag to indicate that we should ignore all PhyRdy
1068 * state changes
1069 */
1070 hpriv->flags &= ~AHCI_HFLAG_NO_HOTPLUG;
1071
1072 /*
1073 * Enable interrupts on Phy Ready.
1074 */
1075 pp->intr_mask |= PORT_IRQ_PHYRDY;
1076 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1077
1078 /*
1079 * don't change the link pm policy - we can be called
1080 * just to turn of link pm temporarily
1081 */
1082}
1083
1084static int ahci_enable_alpm(struct ata_port *ap,
1085 enum link_pm policy)
1086{
1087 struct ahci_host_priv *hpriv = ap->host->private_data;
1088 void __iomem *port_mmio = ahci_port_base(ap);
1089 u32 cmd;
1090 struct ahci_port_priv *pp = ap->private_data;
1091 u32 asp;
1092
1093 /* Make sure the host is capable of link power management */
1094 if (!(hpriv->cap & HOST_CAP_ALPM))
1095 return -EINVAL;
1096
1097 switch (policy) {
1098 case MAX_PERFORMANCE:
1099 case NOT_AVAILABLE:
1100 /*
1101 * if we came here with NOT_AVAILABLE,
1102 * it just means this is the first time we
1103 * have tried to enable - default to max performance,
1104 * and let the user go to lower power modes on request.
1105 */
1106 ahci_disable_alpm(ap);
1107 return 0;
1108 case MIN_POWER:
1109 /* configure HBA to enter SLUMBER */
1110 asp = PORT_CMD_ASP;
1111 break;
1112 case MEDIUM_POWER:
1113 /* configure HBA to enter PARTIAL */
1114 asp = 0;
1115 break;
1116 default:
1117 return -EINVAL;
1118 }
1119
1120 /*
1121 * Disable interrupts on Phy Ready. This keeps us from
1122 * getting woken up due to spurious phy ready interrupts
1123 * TBD - Hot plug should be done via polling now, is
1124 * that even supported?
1125 */
1126 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
1127 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1128
1129 /*
1130 * Set a flag to indicate that we should ignore all PhyRdy
1131 * state changes since these can happen now whenever we
1132 * change link state
1133 */
1134 hpriv->flags |= AHCI_HFLAG_NO_HOTPLUG;
1135
1136 /* get the existing command bits */
1137 cmd = readl(port_mmio + PORT_CMD);
1138
1139 /*
1140 * Set ASP based on Policy
1141 */
1142 cmd |= asp;
1143
1144 /*
1145 * Setting this bit will instruct the HBA to aggressively
1146 * enter a lower power link state when it's appropriate and
1147 * based on the value set above for ASP
1148 */
1149 cmd |= PORT_CMD_ALPE;
1150
1151 /* write out new cmd value */
1152 writel(cmd, port_mmio + PORT_CMD);
1153 cmd = readl(port_mmio + PORT_CMD);
1154
1155 /* IPM bits should be set by libata-core */
1156 return 0;
1157}
1158
Tejun Heo438ac6d2007-03-02 17:31:26 +09001159#ifdef CONFIG_PM
Tejun Heo4447d352007-04-17 23:44:08 +09001160static void ahci_power_down(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001161{
Tejun Heo4447d352007-04-17 23:44:08 +09001162 struct ahci_host_priv *hpriv = ap->host->private_data;
1163 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001164 u32 cmd, scontrol;
1165
Tejun Heo4447d352007-04-17 23:44:08 +09001166 if (!(hpriv->cap & HOST_CAP_SSS))
Tejun Heo07c53da2007-01-21 02:10:11 +09001167 return;
1168
1169 /* put device into listen mode, first set PxSCTL.DET to 0 */
1170 scontrol = readl(port_mmio + PORT_SCR_CTL);
1171 scontrol &= ~0xf;
1172 writel(scontrol, port_mmio + PORT_SCR_CTL);
1173
1174 /* then set PxCMD.SUD to 0 */
Tejun Heo0be0aa92006-07-26 15:59:26 +09001175 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
Tejun Heo07c53da2007-01-21 02:10:11 +09001176 cmd &= ~PORT_CMD_SPIN_UP;
1177 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001178}
Tejun Heo438ac6d2007-03-02 17:31:26 +09001179#endif
Tejun Heo0be0aa92006-07-26 15:59:26 +09001180
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04001181static void ahci_start_port(struct ata_port *ap)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001182{
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001183 struct ahci_port_priv *pp = ap->private_data;
1184 struct ata_link *link;
1185 struct ahci_em_priv *emp;
David Milburn4c1e9aa2009-04-03 15:36:41 -05001186 ssize_t rc;
1187 int i;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001188
Tejun Heo0be0aa92006-07-26 15:59:26 +09001189 /* enable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001190 ahci_start_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001191
1192 /* enable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001193 ahci_start_engine(ap);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001194
1195 /* turn on LEDs */
1196 if (ap->flags & ATA_FLAG_EM) {
Tejun Heo1eca4362008-11-03 20:03:17 +09001197 ata_for_each_link(link, ap, EDGE) {
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001198 emp = &pp->em_priv[link->pmp];
David Milburn4c1e9aa2009-04-03 15:36:41 -05001199
1200 /* EM Transmit bit maybe busy during init */
Tejun Heod50ce072009-05-12 10:57:41 +09001201 for (i = 0; i < EM_MAX_RETRY; i++) {
David Milburn4c1e9aa2009-04-03 15:36:41 -05001202 rc = ahci_transmit_led_message(ap,
1203 emp->led_state,
1204 4);
1205 if (rc == -EBUSY)
Tejun Heod50ce072009-05-12 10:57:41 +09001206 msleep(1);
David Milburn4c1e9aa2009-04-03 15:36:41 -05001207 else
1208 break;
1209 }
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001210 }
1211 }
1212
1213 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
Tejun Heo1eca4362008-11-03 20:03:17 +09001214 ata_for_each_link(link, ap, EDGE)
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001215 ahci_init_sw_activity(link);
1216
Tejun Heo0be0aa92006-07-26 15:59:26 +09001217}
1218
Tejun Heo4447d352007-04-17 23:44:08 +09001219static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
Tejun Heo0be0aa92006-07-26 15:59:26 +09001220{
1221 int rc;
1222
1223 /* disable DMA */
Tejun Heo4447d352007-04-17 23:44:08 +09001224 rc = ahci_stop_engine(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001225 if (rc) {
1226 *emsg = "failed to stop engine";
1227 return rc;
1228 }
1229
1230 /* disable FIS reception */
Tejun Heo4447d352007-04-17 23:44:08 +09001231 rc = ahci_stop_fis_rx(ap);
Tejun Heo0be0aa92006-07-26 15:59:26 +09001232 if (rc) {
1233 *emsg = "failed stop FIS RX";
1234 return rc;
1235 }
1236
Tejun Heo0be0aa92006-07-26 15:59:26 +09001237 return 0;
1238}
1239
Tejun Heo4447d352007-04-17 23:44:08 +09001240static int ahci_reset_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001241{
Tejun Heo4447d352007-04-17 23:44:08 +09001242 struct pci_dev *pdev = to_pci_dev(host->dev);
Tejun Heo49f29092007-11-19 16:03:44 +09001243 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001244 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heod447df12007-03-18 22:15:33 +09001245 u32 tmp;
Tejun Heod91542c2006-07-26 15:59:26 +09001246
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001247 /* we must be in AHCI mode, before using anything
1248 * AHCI-specific, such as HOST_RESET.
1249 */
Tejun Heob710a1f2008-01-05 23:11:57 +09001250 ahci_enable_ahci(mmio);
Jeff Garzik3cc3eb12007-09-26 00:02:41 -04001251
1252 /* global controller reset */
Tejun Heoa22e6442008-03-10 10:25:25 +09001253 if (!ahci_skip_host_reset) {
1254 tmp = readl(mmio + HOST_CTL);
1255 if ((tmp & HOST_RESET) == 0) {
1256 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1257 readl(mmio + HOST_CTL); /* flush */
1258 }
Tejun Heod91542c2006-07-26 15:59:26 +09001259
Zhang Rui24920c82008-07-04 13:32:17 +08001260 /*
1261 * to perform host reset, OS should set HOST_RESET
1262 * and poll until this bit is read to be "0".
1263 * reset must complete within 1 second, or
Tejun Heoa22e6442008-03-10 10:25:25 +09001264 * the hardware should be considered fried.
1265 */
Zhang Rui24920c82008-07-04 13:32:17 +08001266 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
1267 HOST_RESET, 10, 1000);
Tejun Heod91542c2006-07-26 15:59:26 +09001268
Tejun Heoa22e6442008-03-10 10:25:25 +09001269 if (tmp & HOST_RESET) {
1270 dev_printk(KERN_ERR, host->dev,
1271 "controller reset failed (0x%x)\n", tmp);
1272 return -EIO;
1273 }
Tejun Heod91542c2006-07-26 15:59:26 +09001274
Tejun Heoa22e6442008-03-10 10:25:25 +09001275 /* turn on AHCI mode */
1276 ahci_enable_ahci(mmio);
Tejun Heo98fa4b62006-11-02 12:17:23 +09001277
Tejun Heoa22e6442008-03-10 10:25:25 +09001278 /* Some registers might be cleared on reset. Restore
1279 * initial values.
1280 */
1281 ahci_restore_initial_config(host);
1282 } else
1283 dev_printk(KERN_INFO, host->dev,
1284 "skipping global host reset\n");
Tejun Heod91542c2006-07-26 15:59:26 +09001285
1286 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1287 u16 tmp16;
1288
1289 /* configure PCS */
1290 pci_read_config_word(pdev, 0x92, &tmp16);
Tejun Heo49f29092007-11-19 16:03:44 +09001291 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
1292 tmp16 |= hpriv->port_map;
1293 pci_write_config_word(pdev, 0x92, tmp16);
1294 }
Tejun Heod91542c2006-07-26 15:59:26 +09001295 }
1296
1297 return 0;
1298}
1299
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001300static void ahci_sw_activity(struct ata_link *link)
1301{
1302 struct ata_port *ap = link->ap;
1303 struct ahci_port_priv *pp = ap->private_data;
1304 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1305
1306 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
1307 return;
1308
1309 emp->activity++;
1310 if (!timer_pending(&emp->timer))
1311 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
1312}
1313
1314static void ahci_sw_activity_blink(unsigned long arg)
1315{
1316 struct ata_link *link = (struct ata_link *)arg;
1317 struct ata_port *ap = link->ap;
1318 struct ahci_port_priv *pp = ap->private_data;
1319 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1320 unsigned long led_message = emp->led_state;
1321 u32 activity_led_state;
David Milburneb409632008-10-16 09:26:19 -05001322 unsigned long flags;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001323
David Milburn87943ac2008-10-13 14:38:36 -05001324 led_message &= EM_MSG_LED_VALUE;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001325 led_message |= ap->port_no | (link->pmp << 8);
1326
1327 /* check to see if we've had activity. If so,
1328 * toggle state of LED and reset timer. If not,
1329 * turn LED to desired idle state.
1330 */
David Milburneb409632008-10-16 09:26:19 -05001331 spin_lock_irqsave(ap->lock, flags);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001332 if (emp->saved_activity != emp->activity) {
1333 emp->saved_activity = emp->activity;
1334 /* get the current LED state */
David Milburn87943ac2008-10-13 14:38:36 -05001335 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001336
1337 if (activity_led_state)
1338 activity_led_state = 0;
1339 else
1340 activity_led_state = 1;
1341
1342 /* clear old state */
David Milburn87943ac2008-10-13 14:38:36 -05001343 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001344
1345 /* toggle state */
1346 led_message |= (activity_led_state << 16);
1347 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
1348 } else {
1349 /* switch to idle */
David Milburn87943ac2008-10-13 14:38:36 -05001350 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001351 if (emp->blink_policy == BLINK_OFF)
1352 led_message |= (1 << 16);
1353 }
David Milburneb409632008-10-16 09:26:19 -05001354 spin_unlock_irqrestore(ap->lock, flags);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001355 ahci_transmit_led_message(ap, led_message, 4);
1356}
1357
1358static void ahci_init_sw_activity(struct ata_link *link)
1359{
1360 struct ata_port *ap = link->ap;
1361 struct ahci_port_priv *pp = ap->private_data;
1362 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1363
1364 /* init activity stats, setup timer */
1365 emp->saved_activity = emp->activity = 0;
1366 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
1367
1368 /* check our blink policy and set flag for link if it's enabled */
1369 if (emp->blink_policy)
1370 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1371}
1372
1373static int ahci_reset_em(struct ata_host *host)
1374{
1375 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
1376 u32 em_ctl;
1377
1378 em_ctl = readl(mmio + HOST_EM_CTL);
1379 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
1380 return -EINVAL;
1381
1382 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
1383 return 0;
1384}
1385
1386static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
1387 ssize_t size)
1388{
1389 struct ahci_host_priv *hpriv = ap->host->private_data;
1390 struct ahci_port_priv *pp = ap->private_data;
1391 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
1392 u32 em_ctl;
1393 u32 message[] = {0, 0};
Linus Torvalds93082f02008-07-25 10:56:36 -07001394 unsigned long flags;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001395 int pmp;
1396 struct ahci_em_priv *emp;
1397
1398 /* get the slot number from the message */
David Milburn87943ac2008-10-13 14:38:36 -05001399 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
Tejun Heod50ce072009-05-12 10:57:41 +09001400 if (pmp < EM_MAX_SLOTS)
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001401 emp = &pp->em_priv[pmp];
1402 else
1403 return -EINVAL;
1404
1405 spin_lock_irqsave(ap->lock, flags);
1406
1407 /*
1408 * if we are still busy transmitting a previous message,
1409 * do not allow
1410 */
1411 em_ctl = readl(mmio + HOST_EM_CTL);
1412 if (em_ctl & EM_CTL_TM) {
1413 spin_unlock_irqrestore(ap->lock, flags);
David Milburn4c1e9aa2009-04-03 15:36:41 -05001414 return -EBUSY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001415 }
1416
1417 /*
1418 * create message header - this is all zero except for
1419 * the message size, which is 4 bytes.
1420 */
1421 message[0] |= (4 << 8);
1422
1423 /* ignore 0:4 of byte zero, fill in port info yourself */
David Milburn87943ac2008-10-13 14:38:36 -05001424 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001425
1426 /* write message to EM_LOC */
1427 writel(message[0], mmio + hpriv->em_loc);
1428 writel(message[1], mmio + hpriv->em_loc+4);
1429
1430 /* save off new led state for port/slot */
David Milburn208f2a82009-03-20 14:14:23 -05001431 emp->led_state = state;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001432
1433 /*
1434 * tell hardware to transmit the message
1435 */
1436 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1437
1438 spin_unlock_irqrestore(ap->lock, flags);
1439 return size;
1440}
1441
1442static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1443{
1444 struct ahci_port_priv *pp = ap->private_data;
1445 struct ata_link *link;
1446 struct ahci_em_priv *emp;
1447 int rc = 0;
1448
Tejun Heo1eca4362008-11-03 20:03:17 +09001449 ata_for_each_link(link, ap, EDGE) {
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001450 emp = &pp->em_priv[link->pmp];
1451 rc += sprintf(buf, "%lx\n", emp->led_state);
1452 }
1453 return rc;
1454}
1455
1456static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1457 size_t size)
1458{
1459 int state;
1460 int pmp;
1461 struct ahci_port_priv *pp = ap->private_data;
1462 struct ahci_em_priv *emp;
1463
1464 state = simple_strtoul(buf, NULL, 0);
1465
1466 /* get the slot number from the message */
David Milburn87943ac2008-10-13 14:38:36 -05001467 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
Tejun Heod50ce072009-05-12 10:57:41 +09001468 if (pmp < EM_MAX_SLOTS)
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001469 emp = &pp->em_priv[pmp];
1470 else
1471 return -EINVAL;
1472
1473 /* mask off the activity bits if we are in sw_activity
1474 * mode, user should turn off sw_activity before setting
1475 * activity led through em_message
1476 */
1477 if (emp->blink_policy)
David Milburn87943ac2008-10-13 14:38:36 -05001478 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001479
1480 return ahci_transmit_led_message(ap, state, size);
1481}
1482
1483static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1484{
1485 struct ata_link *link = dev->link;
1486 struct ata_port *ap = link->ap;
1487 struct ahci_port_priv *pp = ap->private_data;
1488 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1489 u32 port_led_state = emp->led_state;
1490
1491 /* save the desired Activity LED behavior */
1492 if (val == OFF) {
1493 /* clear LFLAG */
1494 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1495
1496 /* set the LED to OFF */
David Milburn87943ac2008-10-13 14:38:36 -05001497 port_led_state &= EM_MSG_LED_VALUE_OFF;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001498 port_led_state |= (ap->port_no | (link->pmp << 8));
1499 ahci_transmit_led_message(ap, port_led_state, 4);
1500 } else {
1501 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1502 if (val == BLINK_OFF) {
1503 /* set LED to ON for idle */
David Milburn87943ac2008-10-13 14:38:36 -05001504 port_led_state &= EM_MSG_LED_VALUE_OFF;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001505 port_led_state |= (ap->port_no | (link->pmp << 8));
David Milburn87943ac2008-10-13 14:38:36 -05001506 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07001507 ahci_transmit_led_message(ap, port_led_state, 4);
1508 }
1509 }
1510 emp->blink_policy = val;
1511 return 0;
1512}
1513
1514static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1515{
1516 struct ata_link *link = dev->link;
1517 struct ata_port *ap = link->ap;
1518 struct ahci_port_priv *pp = ap->private_data;
1519 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1520
1521 /* display the saved value of activity behavior for this
1522 * disk.
1523 */
1524 return sprintf(buf, "%d\n", emp->blink_policy);
1525}
1526
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001527static void ahci_port_init(struct pci_dev *pdev, struct ata_port *ap,
1528 int port_no, void __iomem *mmio,
1529 void __iomem *port_mmio)
1530{
1531 const char *emsg = NULL;
1532 int rc;
1533 u32 tmp;
1534
1535 /* make sure port is not active */
1536 rc = ahci_deinit_port(ap, &emsg);
1537 if (rc)
1538 dev_printk(KERN_WARNING, &pdev->dev,
1539 "%s (%d)\n", emsg, rc);
1540
1541 /* clear SError */
1542 tmp = readl(port_mmio + PORT_SCR_ERR);
1543 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1544 writel(tmp, port_mmio + PORT_SCR_ERR);
1545
1546 /* clear port IRQ */
1547 tmp = readl(port_mmio + PORT_IRQ_STAT);
1548 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1549 if (tmp)
1550 writel(tmp, port_mmio + PORT_IRQ_STAT);
1551
1552 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1553}
1554
Tejun Heo4447d352007-04-17 23:44:08 +09001555static void ahci_init_controller(struct ata_host *host)
Tejun Heod91542c2006-07-26 15:59:26 +09001556{
Tejun Heo417a1a62007-09-23 13:19:55 +09001557 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo4447d352007-04-17 23:44:08 +09001558 struct pci_dev *pdev = to_pci_dev(host->dev);
1559 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001560 int i;
Jeff Garzikcd70c262007-07-08 02:29:42 -04001561 void __iomem *port_mmio;
Tejun Heod91542c2006-07-26 15:59:26 +09001562 u32 tmp;
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +01001563 int mv;
Tejun Heod91542c2006-07-26 15:59:26 +09001564
Tejun Heo417a1a62007-09-23 13:19:55 +09001565 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
Jose Alberto Regueroc40e7cb2008-03-13 23:22:24 +01001566 if (pdev->device == 0x6121)
1567 mv = 2;
1568 else
1569 mv = 4;
1570 port_mmio = __ahci_port_base(host, mv);
Jeff Garzikcd70c262007-07-08 02:29:42 -04001571
1572 writel(0, port_mmio + PORT_IRQ_MASK);
1573
1574 /* clear port IRQ */
1575 tmp = readl(port_mmio + PORT_IRQ_STAT);
1576 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1577 if (tmp)
1578 writel(tmp, port_mmio + PORT_IRQ_STAT);
1579 }
1580
Tejun Heo4447d352007-04-17 23:44:08 +09001581 for (i = 0; i < host->n_ports; i++) {
1582 struct ata_port *ap = host->ports[i];
Tejun Heod91542c2006-07-26 15:59:26 +09001583
Jeff Garzikcd70c262007-07-08 02:29:42 -04001584 port_mmio = ahci_port_base(ap);
Tejun Heo4447d352007-04-17 23:44:08 +09001585 if (ata_port_is_dummy(ap))
Tejun Heod91542c2006-07-26 15:59:26 +09001586 continue;
Tejun Heod91542c2006-07-26 15:59:26 +09001587
Jeff Garzik2bcd8662007-05-28 07:45:27 -04001588 ahci_port_init(pdev, ap, i, mmio, port_mmio);
Tejun Heod91542c2006-07-26 15:59:26 +09001589 }
1590
1591 tmp = readl(mmio + HOST_CTL);
1592 VPRINTK("HOST_CTL 0x%x\n", tmp);
1593 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1594 tmp = readl(mmio + HOST_CTL);
1595 VPRINTK("HOST_CTL 0x%x\n", tmp);
1596}
1597
Jeff Garzika8785392008-02-28 15:43:48 -05001598static void ahci_dev_config(struct ata_device *dev)
1599{
1600 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1601
Jeff Garzik4cde32f2008-03-24 22:40:40 -04001602 if (hpriv->flags & AHCI_HFLAG_SECT255) {
Jeff Garzika8785392008-02-28 15:43:48 -05001603 dev->max_sectors = 255;
Jeff Garzik4cde32f2008-03-24 22:40:40 -04001604 ata_dev_printk(dev, KERN_INFO,
1605 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1606 }
Jeff Garzika8785392008-02-28 15:43:48 -05001607}
1608
Tejun Heo422b7592005-12-19 22:37:17 +09001609static unsigned int ahci_dev_classify(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001610{
Tejun Heo4447d352007-04-17 23:44:08 +09001611 void __iomem *port_mmio = ahci_port_base(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001612 struct ata_taskfile tf;
Tejun Heo422b7592005-12-19 22:37:17 +09001613 u32 tmp;
1614
1615 tmp = readl(port_mmio + PORT_SIG);
1616 tf.lbah = (tmp >> 24) & 0xff;
1617 tf.lbam = (tmp >> 16) & 0xff;
1618 tf.lbal = (tmp >> 8) & 0xff;
1619 tf.nsect = (tmp) & 0xff;
1620
1621 return ata_dev_classify(&tf);
1622}
1623
Tejun Heo12fad3f2006-05-15 21:03:55 +09001624static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1625 u32 opts)
Tejun Heocc9278e2006-02-10 17:25:47 +09001626{
Tejun Heo12fad3f2006-05-15 21:03:55 +09001627 dma_addr_t cmd_tbl_dma;
1628
1629 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1630
1631 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1632 pp->cmd_slot[tag].status = 0;
1633 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1634 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
Tejun Heocc9278e2006-02-10 17:25:47 +09001635}
1636
Shane Huang78d5ae32009-08-07 15:05:52 +08001637static int ahci_kick_engine(struct ata_port *ap)
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001638{
Tejun Heo350756f2008-04-07 22:47:21 +09001639 void __iomem *port_mmio = ahci_port_base(ap);
Jeff Garzikcca39742006-08-24 03:19:22 -04001640 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo520d06f2008-04-07 22:47:21 +09001641 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001642 u32 tmp;
Tejun Heod2e75df2007-07-16 14:29:39 +09001643 int busy, rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001644
Tejun Heod2e75df2007-07-16 14:29:39 +09001645 /* stop engine */
1646 rc = ahci_stop_engine(ap);
1647 if (rc)
1648 goto out_restart;
1649
Shane Huang78d5ae32009-08-07 15:05:52 +08001650 /* need to do CLO?
1651 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1652 */
1653 busy = status & (ATA_BUSY | ATA_DRQ);
1654 if (!busy && !sata_pmp_attached(ap)) {
Tejun Heod2e75df2007-07-16 14:29:39 +09001655 rc = 0;
1656 goto out_restart;
1657 }
1658
1659 if (!(hpriv->cap & HOST_CAP_CLO)) {
1660 rc = -EOPNOTSUPP;
1661 goto out_restart;
1662 }
1663
1664 /* perform CLO */
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001665 tmp = readl(port_mmio + PORT_CMD);
1666 tmp |= PORT_CMD_CLO;
1667 writel(tmp, port_mmio + PORT_CMD);
1668
Tejun Heod2e75df2007-07-16 14:29:39 +09001669 rc = 0;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001670 tmp = ata_wait_register(port_mmio + PORT_CMD,
1671 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1672 if (tmp & PORT_CMD_CLO)
Tejun Heod2e75df2007-07-16 14:29:39 +09001673 rc = -EIO;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001674
Tejun Heod2e75df2007-07-16 14:29:39 +09001675 /* restart engine */
1676 out_restart:
1677 ahci_start_engine(ap);
1678 return rc;
Bastiaan Jacquesbf2af2a2006-04-17 14:17:59 +02001679}
1680
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001681static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1682 struct ata_taskfile *tf, int is_cmd, u16 flags,
1683 unsigned long timeout_msec)
1684{
1685 const u32 cmd_fis_len = 5; /* five dwords */
1686 struct ahci_port_priv *pp = ap->private_data;
1687 void __iomem *port_mmio = ahci_port_base(ap);
1688 u8 *fis = pp->cmd_tbl;
1689 u32 tmp;
1690
1691 /* prep the command */
1692 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1693 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1694
1695 /* issue & wait */
1696 writel(1, port_mmio + PORT_CMD_ISSUE);
1697
1698 if (timeout_msec) {
1699 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1700 1, timeout_msec);
1701 if (tmp & 0x1) {
Shane Huang78d5ae32009-08-07 15:05:52 +08001702 ahci_kick_engine(ap);
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001703 return -EBUSY;
1704 }
1705 } else
1706 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1707
1708 return 0;
1709}
1710
Shane Huangbd172432008-06-10 15:52:04 +08001711static int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1712 int pmp, unsigned long deadline,
1713 int (*check_ready)(struct ata_link *link))
Tejun Heo4658f792006-03-22 21:07:03 +09001714{
Tejun Heocc0680a2007-08-06 18:36:23 +09001715 struct ata_port *ap = link->ap;
Tejun Heo55946392009-08-04 14:30:08 +09001716 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo4658f792006-03-22 21:07:03 +09001717 const char *reason = NULL;
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001718 unsigned long now, msecs;
Tejun Heo4658f792006-03-22 21:07:03 +09001719 struct ata_taskfile tf;
Tejun Heo4658f792006-03-22 21:07:03 +09001720 int rc;
1721
1722 DPRINTK("ENTER\n");
1723
1724 /* prepare for SRST (AHCI-1.1 10.4.1) */
Shane Huang78d5ae32009-08-07 15:05:52 +08001725 rc = ahci_kick_engine(ap);
Tejun Heo994056d2007-12-06 15:02:48 +09001726 if (rc && rc != -EOPNOTSUPP)
Tejun Heocc0680a2007-08-06 18:36:23 +09001727 ata_link_printk(link, KERN_WARNING,
Tejun Heo994056d2007-12-06 15:02:48 +09001728 "failed to reset engine (errno=%d)\n", rc);
Tejun Heo4658f792006-03-22 21:07:03 +09001729
Tejun Heocc0680a2007-08-06 18:36:23 +09001730 ata_tf_init(link->device, &tf);
Tejun Heo4658f792006-03-22 21:07:03 +09001731
1732 /* issue the first D2H Register FIS */
Tejun Heo2cbb79e2007-07-16 14:29:38 +09001733 msecs = 0;
1734 now = jiffies;
1735 if (time_after(now, deadline))
1736 msecs = jiffies_to_msecs(deadline - now);
1737
Tejun Heo4658f792006-03-22 21:07:03 +09001738 tf.ctl |= ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001739 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
Tejun Heo91c4a2e2007-07-16 14:29:39 +09001740 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
Tejun Heo4658f792006-03-22 21:07:03 +09001741 rc = -EIO;
1742 reason = "1st FIS failed";
1743 goto fail;
1744 }
1745
1746 /* spec says at least 5us, but be generous and sleep for 1ms */
1747 msleep(1);
1748
1749 /* issue the second D2H Register FIS */
Tejun Heo4658f792006-03-22 21:07:03 +09001750 tf.ctl &= ~ATA_SRST;
Tejun Heoa9cf5e82007-07-16 14:29:39 +09001751 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
Tejun Heo4658f792006-03-22 21:07:03 +09001752
Tejun Heo705e76b2008-04-07 22:47:19 +09001753 /* wait for link to become ready */
Shane Huangbd172432008-06-10 15:52:04 +08001754 rc = ata_wait_after_reset(link, deadline, check_ready);
Tejun Heo55946392009-08-04 14:30:08 +09001755 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1756 /*
1757 * Workaround for cases where link online status can't
1758 * be trusted. Treat device readiness timeout as link
1759 * offline.
1760 */
1761 ata_link_printk(link, KERN_INFO,
1762 "device not ready, treating as offline\n");
1763 *class = ATA_DEV_NONE;
1764 } else if (rc) {
1765 /* link occupied, -ENODEV too is an error */
Tejun Heo9b893912007-02-02 16:50:52 +09001766 reason = "device not ready";
1767 goto fail;
Tejun Heo55946392009-08-04 14:30:08 +09001768 } else
1769 *class = ahci_dev_classify(ap);
Tejun Heo4658f792006-03-22 21:07:03 +09001770
1771 DPRINTK("EXIT, class=%u\n", *class);
1772 return 0;
1773
Tejun Heo4658f792006-03-22 21:07:03 +09001774 fail:
Tejun Heocc0680a2007-08-06 18:36:23 +09001775 ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason);
Tejun Heo4658f792006-03-22 21:07:03 +09001776 return rc;
1777}
1778
Shane Huangbd172432008-06-10 15:52:04 +08001779static int ahci_check_ready(struct ata_link *link)
1780{
1781 void __iomem *port_mmio = ahci_port_base(link->ap);
1782 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1783
1784 return ata_check_ready(status);
1785}
1786
1787static int ahci_softreset(struct ata_link *link, unsigned int *class,
1788 unsigned long deadline)
1789{
1790 int pmp = sata_srst_pmp(link);
1791
1792 DPRINTK("ENTER\n");
1793
1794 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1795}
1796
1797static int ahci_sb600_check_ready(struct ata_link *link)
1798{
1799 void __iomem *port_mmio = ahci_port_base(link->ap);
1800 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1801 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1802
1803 /*
1804 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1805 * which can save timeout delay.
1806 */
1807 if (irq_status & PORT_IRQ_BAD_PMP)
1808 return -EIO;
1809
1810 return ata_check_ready(status);
1811}
1812
1813static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
1814 unsigned long deadline)
1815{
1816 struct ata_port *ap = link->ap;
1817 void __iomem *port_mmio = ahci_port_base(ap);
1818 int pmp = sata_srst_pmp(link);
1819 int rc;
1820 u32 irq_sts;
1821
1822 DPRINTK("ENTER\n");
1823
1824 rc = ahci_do_softreset(link, class, pmp, deadline,
1825 ahci_sb600_check_ready);
1826
1827 /*
1828 * Soft reset fails on some ATI chips with IPMS set when PMP
1829 * is enabled but SATA HDD/ODD is connected to SATA port,
1830 * do soft reset again to port 0.
1831 */
1832 if (rc == -EIO) {
1833 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1834 if (irq_sts & PORT_IRQ_BAD_PMP) {
1835 ata_link_printk(link, KERN_WARNING,
Shane Huangb6931c12009-08-05 10:10:41 +08001836 "applying SB600 PMP SRST workaround "
1837 "and retrying\n");
Shane Huangbd172432008-06-10 15:52:04 +08001838 rc = ahci_do_softreset(link, class, 0, deadline,
1839 ahci_check_ready);
1840 }
1841 }
1842
1843 return rc;
1844}
1845
Tejun Heocc0680a2007-08-06 18:36:23 +09001846static int ahci_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001847 unsigned long deadline)
Tejun Heo422b7592005-12-19 22:37:17 +09001848{
Tejun Heo9dadd452008-04-07 22:47:19 +09001849 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
Tejun Heocc0680a2007-08-06 18:36:23 +09001850 struct ata_port *ap = link->ap;
Tejun Heo42969712006-05-31 18:28:18 +09001851 struct ahci_port_priv *pp = ap->private_data;
1852 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1853 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +09001854 bool online;
Tejun Heo4bd00f62006-02-11 16:26:02 +09001855 int rc;
1856
1857 DPRINTK("ENTER\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001858
Tejun Heo4447d352007-04-17 23:44:08 +09001859 ahci_stop_engine(ap);
Tejun Heo42969712006-05-31 18:28:18 +09001860
1861 /* clear D2H reception area to properly wait for D2H FIS */
Tejun Heocc0680a2007-08-06 18:36:23 +09001862 ata_tf_init(link->device, &tf);
Tejun Heodfd7a3d2007-01-26 15:37:20 +09001863 tf.command = 0x80;
Tejun Heo99771262007-07-16 14:29:38 +09001864 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
Tejun Heo42969712006-05-31 18:28:18 +09001865
Tejun Heo9dadd452008-04-07 22:47:19 +09001866 rc = sata_link_hardreset(link, timing, deadline, &online,
1867 ahci_check_ready);
Tejun Heo42969712006-05-31 18:28:18 +09001868
Tejun Heo4447d352007-04-17 23:44:08 +09001869 ahci_start_engine(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001870
Tejun Heo9dadd452008-04-07 22:47:19 +09001871 if (online)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001872 *class = ahci_dev_classify(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001873
Tejun Heo4bd00f62006-02-11 16:26:02 +09001874 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1875 return rc;
1876}
1877
Tejun Heocc0680a2007-08-06 18:36:23 +09001878static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
Tejun Heod4b2bab2007-02-02 16:50:52 +09001879 unsigned long deadline)
Tejun Heoad616ff2006-11-01 18:00:24 +09001880{
Tejun Heocc0680a2007-08-06 18:36:23 +09001881 struct ata_port *ap = link->ap;
Tejun Heo9dadd452008-04-07 22:47:19 +09001882 bool online;
Tejun Heoad616ff2006-11-01 18:00:24 +09001883 int rc;
1884
1885 DPRINTK("ENTER\n");
1886
Tejun Heo4447d352007-04-17 23:44:08 +09001887 ahci_stop_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001888
Tejun Heocc0680a2007-08-06 18:36:23 +09001889 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +09001890 deadline, &online, NULL);
Tejun Heoad616ff2006-11-01 18:00:24 +09001891
Tejun Heo4447d352007-04-17 23:44:08 +09001892 ahci_start_engine(ap);
Tejun Heoad616ff2006-11-01 18:00:24 +09001893
1894 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1895
1896 /* vt8251 doesn't clear BSY on signature FIS reception,
1897 * request follow-up softreset.
1898 */
Tejun Heo9dadd452008-04-07 22:47:19 +09001899 return online ? -EAGAIN : rc;
Tejun Heoad616ff2006-11-01 18:00:24 +09001900}
1901
Tejun Heoedc93052007-10-25 14:59:16 +09001902static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
1903 unsigned long deadline)
1904{
1905 struct ata_port *ap = link->ap;
1906 struct ahci_port_priv *pp = ap->private_data;
1907 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1908 struct ata_taskfile tf;
Tejun Heo9dadd452008-04-07 22:47:19 +09001909 bool online;
Tejun Heoedc93052007-10-25 14:59:16 +09001910 int rc;
1911
1912 ahci_stop_engine(ap);
1913
1914 /* clear D2H reception area to properly wait for D2H FIS */
1915 ata_tf_init(link->device, &tf);
1916 tf.command = 0x80;
1917 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1918
1919 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
Tejun Heo9dadd452008-04-07 22:47:19 +09001920 deadline, &online, NULL);
Tejun Heoedc93052007-10-25 14:59:16 +09001921
1922 ahci_start_engine(ap);
1923
Tejun Heoedc93052007-10-25 14:59:16 +09001924 /* The pseudo configuration device on SIMG4726 attached to
1925 * ASUS P5W-DH Deluxe doesn't send signature FIS after
1926 * hardreset if no device is attached to the first downstream
1927 * port && the pseudo device locks up on SRST w/ PMP==0. To
1928 * work around this, wait for !BSY only briefly. If BSY isn't
1929 * cleared, perform CLO and proceed to IDENTIFY (achieved by
1930 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
1931 *
1932 * Wait for two seconds. Devices attached to downstream port
1933 * which can't process the following IDENTIFY after this will
1934 * have to be reset again. For most cases, this should
1935 * suffice while making probing snappish enough.
1936 */
Tejun Heo9dadd452008-04-07 22:47:19 +09001937 if (online) {
1938 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
1939 ahci_check_ready);
1940 if (rc)
Shane Huang78d5ae32009-08-07 15:05:52 +08001941 ahci_kick_engine(ap);
Tejun Heo9dadd452008-04-07 22:47:19 +09001942 }
Tejun Heo9dadd452008-04-07 22:47:19 +09001943 return rc;
Tejun Heoedc93052007-10-25 14:59:16 +09001944}
1945
Tejun Heocc0680a2007-08-06 18:36:23 +09001946static void ahci_postreset(struct ata_link *link, unsigned int *class)
Tejun Heo4bd00f62006-02-11 16:26:02 +09001947{
Tejun Heocc0680a2007-08-06 18:36:23 +09001948 struct ata_port *ap = link->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09001949 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001950 u32 new_tmp, tmp;
1951
Tejun Heo203c75b2008-04-07 22:47:18 +09001952 ata_std_postreset(link, class);
Jeff Garzik02eaa662005-11-12 01:32:19 -05001953
1954 /* Make sure port's ATAPI bit is set appropriately */
1955 new_tmp = tmp = readl(port_mmio + PORT_CMD);
Tejun Heo4bd00f62006-02-11 16:26:02 +09001956 if (*class == ATA_DEV_ATAPI)
Jeff Garzik02eaa662005-11-12 01:32:19 -05001957 new_tmp |= PORT_CMD_ATAPI;
1958 else
1959 new_tmp &= ~PORT_CMD_ATAPI;
1960 if (new_tmp != tmp) {
1961 writel(new_tmp, port_mmio + PORT_CMD);
1962 readl(port_mmio + PORT_CMD); /* flush */
1963 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001964}
1965
Tejun Heo12fad3f2006-05-15 21:03:55 +09001966static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001967{
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001968 struct scatterlist *sg;
Tejun Heoff2aeb12007-12-05 16:43:11 +09001969 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1970 unsigned int si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001971
1972 VPRINTK("ENTER\n");
1973
1974 /*
1975 * Next, the S/G list.
1976 */
Tejun Heoff2aeb12007-12-05 16:43:11 +09001977 for_each_sg(qc->sg, sg, qc->n_elem, si) {
Jeff Garzikcedc9a42005-10-05 07:13:30 -04001978 dma_addr_t addr = sg_dma_address(sg);
1979 u32 sg_len = sg_dma_len(sg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001980
Tejun Heoff2aeb12007-12-05 16:43:11 +09001981 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1982 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1983 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001984 }
Jeff Garzik828d09d2005-11-12 01:27:07 -05001985
Tejun Heoff2aeb12007-12-05 16:43:11 +09001986 return si;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001987}
1988
1989static void ahci_qc_prep(struct ata_queued_cmd *qc)
1990{
Jeff Garzika0ea7322005-06-04 01:13:15 -04001991 struct ata_port *ap = qc->ap;
1992 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo405e66b2007-11-27 19:28:53 +09001993 int is_atapi = ata_is_atapi(qc->tf.protocol);
Tejun Heo12fad3f2006-05-15 21:03:55 +09001994 void *cmd_tbl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001995 u32 opts;
1996 const u32 cmd_fis_len = 5; /* five dwords */
Jeff Garzik828d09d2005-11-12 01:27:07 -05001997 unsigned int n_elem;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001998
1999 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002000 * Fill in command table information. First, the header,
2001 * a SATA Register - Host to Device command FIS.
2002 */
Tejun Heo12fad3f2006-05-15 21:03:55 +09002003 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
2004
Tejun Heo7d50b602007-09-23 13:19:54 +09002005 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
Tejun Heocc9278e2006-02-10 17:25:47 +09002006 if (is_atapi) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09002007 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
2008 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
Jeff Garzika0ea7322005-06-04 01:13:15 -04002009 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002010
Tejun Heocc9278e2006-02-10 17:25:47 +09002011 n_elem = 0;
2012 if (qc->flags & ATA_QCFLAG_DMAMAP)
Tejun Heo12fad3f2006-05-15 21:03:55 +09002013 n_elem = ahci_fill_sg(qc, cmd_tbl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002014
Tejun Heocc9278e2006-02-10 17:25:47 +09002015 /*
2016 * Fill in command slot information.
2017 */
Tejun Heo7d50b602007-09-23 13:19:54 +09002018 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
Tejun Heocc9278e2006-02-10 17:25:47 +09002019 if (qc->tf.flags & ATA_TFLAG_WRITE)
2020 opts |= AHCI_CMD_WRITE;
2021 if (is_atapi)
Tejun Heo4b10e552006-03-12 11:25:27 +09002022 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
Jeff Garzik828d09d2005-11-12 01:27:07 -05002023
Tejun Heo12fad3f2006-05-15 21:03:55 +09002024 ahci_fill_cmd_slot(pp, qc->tag, opts);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002025}
2026
Tejun Heo78cd52d2006-05-15 20:58:29 +09002027static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002028{
Tejun Heo417a1a62007-09-23 13:19:55 +09002029 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09002030 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09002031 struct ata_eh_info *host_ehi = &ap->link.eh_info;
2032 struct ata_link *link = NULL;
2033 struct ata_queued_cmd *active_qc;
2034 struct ata_eh_info *active_ehi;
Tejun Heo78cd52d2006-05-15 20:58:29 +09002035 u32 serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002036
Tejun Heo7d50b602007-09-23 13:19:54 +09002037 /* determine active link */
Tejun Heo1eca4362008-11-03 20:03:17 +09002038 ata_for_each_link(link, ap, EDGE)
Tejun Heo7d50b602007-09-23 13:19:54 +09002039 if (ata_link_active(link))
2040 break;
2041 if (!link)
2042 link = &ap->link;
2043
2044 active_qc = ata_qc_from_tag(ap, link->active_tag);
2045 active_ehi = &link->eh_info;
2046
2047 /* record irq stat */
2048 ata_ehi_clear_desc(host_ehi);
2049 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
Jeff Garzik9f68a242005-11-15 14:03:47 -05002050
Tejun Heo78cd52d2006-05-15 20:58:29 +09002051 /* AHCI needs SError cleared; otherwise, it might lock up */
Tejun Heo82ef04f2008-07-31 17:02:40 +09002052 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
2053 ahci_scr_write(&ap->link, SCR_ERROR, serror);
Tejun Heo7d50b602007-09-23 13:19:54 +09002054 host_ehi->serror |= serror;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002055
Tejun Heo41669552006-11-29 11:33:14 +09002056 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
Tejun Heo417a1a62007-09-23 13:19:55 +09002057 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
Tejun Heo41669552006-11-29 11:33:14 +09002058 irq_stat &= ~PORT_IRQ_IF_ERR;
2059
Conke Hu55a61602007-03-27 18:33:05 +08002060 if (irq_stat & PORT_IRQ_TF_ERR) {
Tejun Heo7d50b602007-09-23 13:19:54 +09002061 /* If qc is active, charge it; otherwise, the active
2062 * link. There's no active qc on NCQ errors. It will
2063 * be determined by EH by reading log page 10h.
2064 */
2065 if (active_qc)
2066 active_qc->err_mask |= AC_ERR_DEV;
2067 else
2068 active_ehi->err_mask |= AC_ERR_DEV;
2069
Tejun Heo417a1a62007-09-23 13:19:55 +09002070 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
Tejun Heo7d50b602007-09-23 13:19:54 +09002071 host_ehi->serror &= ~SERR_INTERNAL;
Tejun Heo78cd52d2006-05-15 20:58:29 +09002072 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002073
Tejun Heo78cd52d2006-05-15 20:58:29 +09002074 if (irq_stat & PORT_IRQ_UNK_FIS) {
2075 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002076
Tejun Heo7d50b602007-09-23 13:19:54 +09002077 active_ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002078 active_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002079 ata_ehi_push_desc(active_ehi,
2080 "unknown FIS %08x %08x %08x %08x" ,
Tejun Heo78cd52d2006-05-15 20:58:29 +09002081 unk[0], unk[1], unk[2], unk[3]);
2082 }
Jeff Garzikb8f61532005-08-25 22:01:20 -04002083
Tejun Heo071f44b2008-04-07 22:47:22 +09002084 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
Tejun Heo7d50b602007-09-23 13:19:54 +09002085 active_ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002086 active_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002087 ata_ehi_push_desc(active_ehi, "incorrect PMP");
2088 }
Tejun Heo78cd52d2006-05-15 20:58:29 +09002089
Tejun Heo7d50b602007-09-23 13:19:54 +09002090 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
2091 host_ehi->err_mask |= AC_ERR_HOST_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002092 host_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002093 ata_ehi_push_desc(host_ehi, "host bus error");
2094 }
2095
2096 if (irq_stat & PORT_IRQ_IF_ERR) {
2097 host_ehi->err_mask |= AC_ERR_ATA_BUS;
Tejun Heocf480622008-01-24 00:05:14 +09002098 host_ehi->action |= ATA_EH_RESET;
Tejun Heo7d50b602007-09-23 13:19:54 +09002099 ata_ehi_push_desc(host_ehi, "interface fatal error");
2100 }
2101
2102 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
2103 ata_ehi_hotplugged(host_ehi);
2104 ata_ehi_push_desc(host_ehi, "%s",
2105 irq_stat & PORT_IRQ_CONNECT ?
2106 "connection status changed" : "PHY RDY changed");
2107 }
2108
2109 /* okay, let's hand over to EH */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002110
Tejun Heo78cd52d2006-05-15 20:58:29 +09002111 if (irq_stat & PORT_IRQ_FREEZE)
2112 ata_port_freeze(ap);
2113 else
2114 ata_port_abort(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002115}
2116
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002117static void ahci_port_intr(struct ata_port *ap)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002118{
Tejun Heo350756f2008-04-07 22:47:21 +09002119 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo9af5c9c2007-08-06 18:36:22 +09002120 struct ata_eh_info *ehi = &ap->link.eh_info;
Tejun Heo0291f952007-01-25 19:16:28 +09002121 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo5f226c62007-10-09 15:02:23 +09002122 struct ahci_host_priv *hpriv = ap->host->private_data;
Tejun Heob06ce3e2007-10-09 15:06:48 +09002123 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
Tejun Heo12fad3f2006-05-15 21:03:55 +09002124 u32 status, qc_active;
Tejun Heo459ad682007-12-07 12:46:23 +09002125 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002126
2127 status = readl(port_mmio + PORT_IRQ_STAT);
2128 writel(status, port_mmio + PORT_IRQ_STAT);
2129
Tejun Heob06ce3e2007-10-09 15:06:48 +09002130 /* ignore BAD_PMP while resetting */
2131 if (unlikely(resetting))
2132 status &= ~PORT_IRQ_BAD_PMP;
2133
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002134 /* If we are getting PhyRdy, this is
2135 * just a power state change, we should
2136 * clear out this, plus the PhyRdy/Comm
2137 * Wake bits from Serror
2138 */
2139 if ((hpriv->flags & AHCI_HFLAG_NO_HOTPLUG) &&
2140 (status & PORT_IRQ_PHYRDY)) {
2141 status &= ~PORT_IRQ_PHYRDY;
Tejun Heo82ef04f2008-07-31 17:02:40 +09002142 ahci_scr_write(&ap->link, SCR_ERROR, ((1 << 16) | (1 << 18)));
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04002143 }
2144
Tejun Heo78cd52d2006-05-15 20:58:29 +09002145 if (unlikely(status & PORT_IRQ_ERROR)) {
2146 ahci_error_intr(ap, status);
2147 return;
2148 }
2149
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002150 if (status & PORT_IRQ_SDB_FIS) {
Tejun Heo5f226c62007-10-09 15:02:23 +09002151 /* If SNotification is available, leave notification
2152 * handling to sata_async_notification(). If not,
2153 * emulate it by snooping SDB FIS RX area.
2154 *
2155 * Snooping FIS RX area is probably cheaper than
2156 * poking SNotification but some constrollers which
2157 * implement SNotification, ICH9 for example, don't
2158 * store AN SDB FIS into receive area.
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002159 */
Tejun Heo5f226c62007-10-09 15:02:23 +09002160 if (hpriv->cap & HOST_CAP_SNTF)
Tejun Heo7d77b242007-09-23 13:14:13 +09002161 sata_async_notification(ap);
Tejun Heo5f226c62007-10-09 15:02:23 +09002162 else {
2163 /* If the 'N' bit in word 0 of the FIS is set,
2164 * we just received asynchronous notification.
2165 * Tell libata about it.
2166 */
2167 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
2168 u32 f0 = le32_to_cpu(f[0]);
2169
2170 if (f0 & (1 << 15))
2171 sata_async_notification(ap);
2172 }
Kristen Carlson Accardi2f294962007-08-15 04:11:25 -04002173 }
2174
Tejun Heo7d50b602007-09-23 13:19:54 +09002175 /* pp->active_link is valid iff any command is in flight */
2176 if (ap->qc_active && pp->active_link->sactive)
Tejun Heo12fad3f2006-05-15 21:03:55 +09002177 qc_active = readl(port_mmio + PORT_SCR_ACT);
2178 else
2179 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
2180
Tejun Heo79f97da2008-04-07 22:47:20 +09002181 rc = ata_qc_complete_multiple(ap, qc_active);
Tejun Heob06ce3e2007-10-09 15:06:48 +09002182
Tejun Heo459ad682007-12-07 12:46:23 +09002183 /* while resetting, invalid completions are expected */
2184 if (unlikely(rc < 0 && !resetting)) {
Tejun Heo12fad3f2006-05-15 21:03:55 +09002185 ehi->err_mask |= AC_ERR_HSM;
Tejun Heocf480622008-01-24 00:05:14 +09002186 ehi->action |= ATA_EH_RESET;
Tejun Heo12fad3f2006-05-15 21:03:55 +09002187 ata_port_freeze(ap);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002188 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002189}
2190
David Howells7d12e782006-10-05 14:55:46 +01002191static irqreturn_t ahci_interrupt(int irq, void *dev_instance)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002192{
Jeff Garzikcca39742006-08-24 03:19:22 -04002193 struct ata_host *host = dev_instance;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002194 struct ahci_host_priv *hpriv;
2195 unsigned int i, handled = 0;
Jeff Garzikea6ba102005-08-30 05:18:18 -04002196 void __iomem *mmio;
Tejun Heod28f87a2008-07-05 13:10:50 +09002197 u32 irq_stat, irq_masked;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002198
2199 VPRINTK("ENTER\n");
2200
Jeff Garzikcca39742006-08-24 03:19:22 -04002201 hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09002202 mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002203
2204 /* sigh. 0xffffffff is a valid return from h/w */
2205 irq_stat = readl(mmio + HOST_IRQ_STAT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002206 if (!irq_stat)
2207 return IRQ_NONE;
2208
Tejun Heod28f87a2008-07-05 13:10:50 +09002209 irq_masked = irq_stat & hpriv->port_map;
2210
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002211 spin_lock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002212
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002213 for (i = 0; i < host->n_ports; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002214 struct ata_port *ap;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002215
Tejun Heod28f87a2008-07-05 13:10:50 +09002216 if (!(irq_masked & (1 << i)))
Jeff Garzik67846b32005-10-05 02:58:32 -04002217 continue;
2218
Jeff Garzikcca39742006-08-24 03:19:22 -04002219 ap = host->ports[i];
Jeff Garzik67846b32005-10-05 02:58:32 -04002220 if (ap) {
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002221 ahci_port_intr(ap);
Jeff Garzik67846b32005-10-05 02:58:32 -04002222 VPRINTK("port %u\n", i);
2223 } else {
2224 VPRINTK("port %u (no irq)\n", i);
Tejun Heo6971ed12006-03-11 12:47:54 +09002225 if (ata_ratelimit())
Jeff Garzikcca39742006-08-24 03:19:22 -04002226 dev_printk(KERN_WARNING, host->dev,
Jeff Garzika9524a72005-10-30 14:39:11 -05002227 "interrupt on disabled port %u\n", i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002228 }
Jeff Garzik67846b32005-10-05 02:58:32 -04002229
Linus Torvalds1da177e2005-04-16 15:20:36 -07002230 handled = 1;
2231 }
2232
Tejun Heod28f87a2008-07-05 13:10:50 +09002233 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
2234 * it should be cleared after all the port events are cleared;
2235 * otherwise, it will raise a spurious interrupt after each
2236 * valid one. Please read section 10.6.2 of ahci 1.1 for more
2237 * information.
2238 *
2239 * Also, use the unmasked value to clear interrupt as spurious
2240 * pending event on a dummy port might cause screaming IRQ.
2241 */
Tejun Heoea0c62f2008-06-28 01:49:02 +09002242 writel(irq_stat, mmio + HOST_IRQ_STAT);
2243
Jeff Garzikcca39742006-08-24 03:19:22 -04002244 spin_unlock(&host->lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002245
2246 VPRINTK("EXIT\n");
2247
2248 return IRQ_RETVAL(handled);
2249}
2250
Tejun Heo9a3d9eb2006-01-23 13:09:36 +09002251static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002252{
2253 struct ata_port *ap = qc->ap;
Tejun Heo4447d352007-04-17 23:44:08 +09002254 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo7d50b602007-09-23 13:19:54 +09002255 struct ahci_port_priv *pp = ap->private_data;
2256
2257 /* Keep track of the currently active link. It will be used
2258 * in completion path to determine whether NCQ phase is in
2259 * progress.
2260 */
2261 pp->active_link = qc->dev->link;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002262
Tejun Heo12fad3f2006-05-15 21:03:55 +09002263 if (qc->tf.protocol == ATA_PROT_NCQ)
2264 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
2265 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002266
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002267 ahci_sw_activity(qc->dev->link);
2268
Linus Torvalds1da177e2005-04-16 15:20:36 -07002269 return 0;
2270}
2271
Tejun Heo4c9bf4e2008-04-07 22:47:20 +09002272static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
2273{
2274 struct ahci_port_priv *pp = qc->ap->private_data;
2275 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
2276
2277 ata_tf_from_fis(d2h_fis, &qc->result_tf);
2278 return true;
2279}
2280
Tejun Heo78cd52d2006-05-15 20:58:29 +09002281static void ahci_freeze(struct ata_port *ap)
2282{
Tejun Heo4447d352007-04-17 23:44:08 +09002283 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002284
2285 /* turn IRQ off */
2286 writel(0, port_mmio + PORT_IRQ_MASK);
2287}
2288
2289static void ahci_thaw(struct ata_port *ap)
2290{
Tejun Heo0d5ff562007-02-01 15:06:36 +09002291 void __iomem *mmio = ap->host->iomap[AHCI_PCI_BAR];
Tejun Heo4447d352007-04-17 23:44:08 +09002292 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002293 u32 tmp;
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002294 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo78cd52d2006-05-15 20:58:29 +09002295
2296 /* clear IRQ */
2297 tmp = readl(port_mmio + PORT_IRQ_STAT);
2298 writel(tmp, port_mmio + PORT_IRQ_STAT);
Tejun Heoa7187282007-01-27 11:04:26 +09002299 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002300
Tejun Heo1c954a42007-10-09 15:01:37 +09002301 /* turn IRQ back on */
2302 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002303}
2304
2305static void ahci_error_handler(struct ata_port *ap)
2306{
Tejun Heob51e9e52006-06-29 01:29:30 +09002307 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
Tejun Heo78cd52d2006-05-15 20:58:29 +09002308 /* restart engine */
Tejun Heo4447d352007-04-17 23:44:08 +09002309 ahci_stop_engine(ap);
2310 ahci_start_engine(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002311 }
2312
Tejun Heoa1efdab2008-03-25 12:22:50 +09002313 sata_pmp_error_handler(ap);
Tejun Heoedc93052007-10-25 14:59:16 +09002314}
2315
Tejun Heo78cd52d2006-05-15 20:58:29 +09002316static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2317{
2318 struct ata_port *ap = qc->ap;
2319
Tejun Heod2e75df2007-07-16 14:29:39 +09002320 /* make DMA engine forget about the failed command */
2321 if (qc->flags & ATA_QCFLAG_FAILED)
Shane Huang78d5ae32009-08-07 15:05:52 +08002322 ahci_kick_engine(ap);
Tejun Heo78cd52d2006-05-15 20:58:29 +09002323}
2324
Tejun Heo7d50b602007-09-23 13:19:54 +09002325static void ahci_pmp_attach(struct ata_port *ap)
2326{
2327 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09002328 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09002329 u32 cmd;
2330
2331 cmd = readl(port_mmio + PORT_CMD);
2332 cmd |= PORT_CMD_PMP;
2333 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09002334
2335 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2336 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09002337}
2338
2339static void ahci_pmp_detach(struct ata_port *ap)
2340{
2341 void __iomem *port_mmio = ahci_port_base(ap);
Tejun Heo1c954a42007-10-09 15:01:37 +09002342 struct ahci_port_priv *pp = ap->private_data;
Tejun Heo7d50b602007-09-23 13:19:54 +09002343 u32 cmd;
2344
2345 cmd = readl(port_mmio + PORT_CMD);
2346 cmd &= ~PORT_CMD_PMP;
2347 writel(cmd, port_mmio + PORT_CMD);
Tejun Heo1c954a42007-10-09 15:01:37 +09002348
2349 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2350 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
Tejun Heo7d50b602007-09-23 13:19:54 +09002351}
2352
Alexey Dobriyan028a2592007-07-17 23:48:48 +04002353static int ahci_port_resume(struct ata_port *ap)
2354{
2355 ahci_power_up(ap);
2356 ahci_start_port(ap);
2357
Tejun Heo071f44b2008-04-07 22:47:22 +09002358 if (sata_pmp_attached(ap))
Tejun Heo7d50b602007-09-23 13:19:54 +09002359 ahci_pmp_attach(ap);
2360 else
2361 ahci_pmp_detach(ap);
2362
Alexey Dobriyan028a2592007-07-17 23:48:48 +04002363 return 0;
2364}
2365
Tejun Heo438ac6d2007-03-02 17:31:26 +09002366#ifdef CONFIG_PM
Tejun Heoc1332872006-07-26 15:59:26 +09002367static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2368{
Tejun Heoc1332872006-07-26 15:59:26 +09002369 const char *emsg = NULL;
2370 int rc;
2371
Tejun Heo4447d352007-04-17 23:44:08 +09002372 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo8e16f942006-11-20 15:42:36 +09002373 if (rc == 0)
Tejun Heo4447d352007-04-17 23:44:08 +09002374 ahci_power_down(ap);
Tejun Heo8e16f942006-11-20 15:42:36 +09002375 else {
Tejun Heoc1332872006-07-26 15:59:26 +09002376 ata_port_printk(ap, KERN_ERR, "%s (%d)\n", emsg, rc);
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002377 ahci_start_port(ap);
Tejun Heoc1332872006-07-26 15:59:26 +09002378 }
2379
2380 return rc;
2381}
2382
Tejun Heoc1332872006-07-26 15:59:26 +09002383static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
2384{
Jeff Garzikcca39742006-08-24 03:19:22 -04002385 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heo9b10ae82009-05-30 20:50:12 +09002386 struct ahci_host_priv *hpriv = host->private_data;
Tejun Heo0d5ff562007-02-01 15:06:36 +09002387 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Tejun Heoc1332872006-07-26 15:59:26 +09002388 u32 ctl;
2389
Tejun Heo9b10ae82009-05-30 20:50:12 +09002390 if (mesg.event & PM_EVENT_SUSPEND &&
2391 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
2392 dev_printk(KERN_ERR, &pdev->dev,
2393 "BIOS update required for suspend/resume\n");
2394 return -EIO;
2395 }
2396
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +01002397 if (mesg.event & PM_EVENT_SLEEP) {
Tejun Heoc1332872006-07-26 15:59:26 +09002398 /* AHCI spec rev1.1 section 8.3.3:
2399 * Software must disable interrupts prior to requesting a
2400 * transition of the HBA to D3 state.
2401 */
2402 ctl = readl(mmio + HOST_CTL);
2403 ctl &= ~HOST_IRQ_EN;
2404 writel(ctl, mmio + HOST_CTL);
2405 readl(mmio + HOST_CTL); /* flush */
2406 }
2407
2408 return ata_pci_device_suspend(pdev, mesg);
2409}
2410
2411static int ahci_pci_device_resume(struct pci_dev *pdev)
2412{
Jeff Garzikcca39742006-08-24 03:19:22 -04002413 struct ata_host *host = dev_get_drvdata(&pdev->dev);
Tejun Heoc1332872006-07-26 15:59:26 +09002414 int rc;
2415
Tejun Heo553c4aa2006-12-26 19:39:50 +09002416 rc = ata_pci_device_do_resume(pdev);
2417 if (rc)
2418 return rc;
Tejun Heoc1332872006-07-26 15:59:26 +09002419
2420 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
Tejun Heo4447d352007-04-17 23:44:08 +09002421 rc = ahci_reset_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002422 if (rc)
2423 return rc;
2424
Tejun Heo4447d352007-04-17 23:44:08 +09002425 ahci_init_controller(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002426 }
2427
Jeff Garzikcca39742006-08-24 03:19:22 -04002428 ata_host_resume(host);
Tejun Heoc1332872006-07-26 15:59:26 +09002429
2430 return 0;
2431}
Tejun Heo438ac6d2007-03-02 17:31:26 +09002432#endif
Tejun Heoc1332872006-07-26 15:59:26 +09002433
Tejun Heo254950c2006-07-26 15:59:25 +09002434static int ahci_port_start(struct ata_port *ap)
2435{
Jeff Garzikcca39742006-08-24 03:19:22 -04002436 struct device *dev = ap->host->dev;
Tejun Heo254950c2006-07-26 15:59:25 +09002437 struct ahci_port_priv *pp;
Tejun Heo254950c2006-07-26 15:59:25 +09002438 void *mem;
2439 dma_addr_t mem_dma;
Tejun Heo254950c2006-07-26 15:59:25 +09002440
Tejun Heo24dc5f32007-01-20 16:00:28 +09002441 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
Tejun Heo254950c2006-07-26 15:59:25 +09002442 if (!pp)
2443 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09002444
Tejun Heo24dc5f32007-01-20 16:00:28 +09002445 mem = dmam_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma,
2446 GFP_KERNEL);
2447 if (!mem)
Tejun Heo254950c2006-07-26 15:59:25 +09002448 return -ENOMEM;
Tejun Heo254950c2006-07-26 15:59:25 +09002449 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
2450
2451 /*
2452 * First item in chunk of DMA memory: 32-slot command table,
2453 * 32 bytes each in size
2454 */
2455 pp->cmd_slot = mem;
2456 pp->cmd_slot_dma = mem_dma;
2457
2458 mem += AHCI_CMD_SLOT_SZ;
2459 mem_dma += AHCI_CMD_SLOT_SZ;
2460
2461 /*
2462 * Second item: Received-FIS area
2463 */
2464 pp->rx_fis = mem;
2465 pp->rx_fis_dma = mem_dma;
2466
2467 mem += AHCI_RX_FIS_SZ;
2468 mem_dma += AHCI_RX_FIS_SZ;
2469
2470 /*
2471 * Third item: data area for storing a single command
2472 * and its scatter-gather table
2473 */
2474 pp->cmd_tbl = mem;
2475 pp->cmd_tbl_dma = mem_dma;
2476
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002477 /*
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002478 * Save off initial list of interrupts to be enabled.
2479 * This could be changed later
2480 */
Kristen Carlson Accardia7384922007-08-09 14:23:41 -07002481 pp->intr_mask = DEF_PORT_IRQ;
2482
Tejun Heo254950c2006-07-26 15:59:25 +09002483 ap->private_data = pp;
2484
Jeff Garzikdf69c9c2007-05-26 20:46:51 -04002485 /* engage engines, captain */
2486 return ahci_port_resume(ap);
Tejun Heo254950c2006-07-26 15:59:25 +09002487}
2488
2489static void ahci_port_stop(struct ata_port *ap)
2490{
Tejun Heo0be0aa92006-07-26 15:59:26 +09002491 const char *emsg = NULL;
2492 int rc;
Tejun Heo254950c2006-07-26 15:59:25 +09002493
Tejun Heo0be0aa92006-07-26 15:59:26 +09002494 /* de-initialize port */
Tejun Heo4447d352007-04-17 23:44:08 +09002495 rc = ahci_deinit_port(ap, &emsg);
Tejun Heo0be0aa92006-07-26 15:59:26 +09002496 if (rc)
2497 ata_port_printk(ap, KERN_WARNING, "%s (%d)\n", emsg, rc);
Tejun Heo254950c2006-07-26 15:59:25 +09002498}
2499
Tejun Heo4447d352007-04-17 23:44:08 +09002500static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002501{
Linus Torvalds1da177e2005-04-16 15:20:36 -07002502 int rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002503
Linus Torvalds1da177e2005-04-16 15:20:36 -07002504 if (using_dac &&
Yang Hongyang6a355282009-04-06 19:01:13 -07002505 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2506 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002507 if (rc) {
Yang Hongyang284901a2009-04-06 19:01:15 -07002508 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002509 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002510 dev_printk(KERN_ERR, &pdev->dev,
2511 "64-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002512 return rc;
2513 }
2514 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002515 } else {
Yang Hongyang284901a2009-04-06 19:01:15 -07002516 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002517 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002518 dev_printk(KERN_ERR, &pdev->dev,
2519 "32-bit DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002520 return rc;
2521 }
Yang Hongyang284901a2009-04-06 19:01:15 -07002522 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002523 if (rc) {
Jeff Garzika9524a72005-10-30 14:39:11 -05002524 dev_printk(KERN_ERR, &pdev->dev,
2525 "32-bit consistent DMA enable failed\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002526 return rc;
2527 }
2528 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002529 return 0;
2530}
2531
Tejun Heo4447d352007-04-17 23:44:08 +09002532static void ahci_print_info(struct ata_host *host)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002533{
Tejun Heo4447d352007-04-17 23:44:08 +09002534 struct ahci_host_priv *hpriv = host->private_data;
2535 struct pci_dev *pdev = to_pci_dev(host->dev);
2536 void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07002537 u32 vers, cap, impl, speed;
2538 const char *speed_s;
2539 u16 cc;
2540 const char *scc_s;
2541
2542 vers = readl(mmio + HOST_VERSION);
2543 cap = hpriv->cap;
2544 impl = hpriv->port_map;
2545
2546 speed = (cap >> 20) & 0xf;
2547 if (speed == 1)
2548 speed_s = "1.5";
2549 else if (speed == 2)
2550 speed_s = "3";
Shane Huang8522ee22008-12-30 11:00:37 +08002551 else if (speed == 3)
2552 speed_s = "6";
Linus Torvalds1da177e2005-04-16 15:20:36 -07002553 else
2554 speed_s = "?";
2555
2556 pci_read_config_word(pdev, 0x0a, &cc);
Conke Huc9f89472007-01-09 05:32:51 -05002557 if (cc == PCI_CLASS_STORAGE_IDE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002558 scc_s = "IDE";
Conke Huc9f89472007-01-09 05:32:51 -05002559 else if (cc == PCI_CLASS_STORAGE_SATA)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002560 scc_s = "SATA";
Conke Huc9f89472007-01-09 05:32:51 -05002561 else if (cc == PCI_CLASS_STORAGE_RAID)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002562 scc_s = "RAID";
2563 else
2564 scc_s = "unknown";
2565
Jeff Garzika9524a72005-10-30 14:39:11 -05002566 dev_printk(KERN_INFO, &pdev->dev,
2567 "AHCI %02x%02x.%02x%02x "
Linus Torvalds1da177e2005-04-16 15:20:36 -07002568 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002569 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002570
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002571 (vers >> 24) & 0xff,
2572 (vers >> 16) & 0xff,
2573 (vers >> 8) & 0xff,
2574 vers & 0xff,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002575
2576 ((cap >> 8) & 0x1f) + 1,
2577 (cap & 0x1f) + 1,
2578 speed_s,
2579 impl,
2580 scc_s);
2581
Jeff Garzika9524a72005-10-30 14:39:11 -05002582 dev_printk(KERN_INFO, &pdev->dev,
2583 "flags: "
Tejun Heo203ef6c2007-07-16 14:29:40 +09002584 "%s%s%s%s%s%s%s"
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002585 "%s%s%s%s%s%s%s"
2586 "%s\n"
Jeff Garzik2dcb4072007-10-19 06:42:56 -04002587 ,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002588
2589 cap & (1 << 31) ? "64bit " : "",
2590 cap & (1 << 30) ? "ncq " : "",
Tejun Heo203ef6c2007-07-16 14:29:40 +09002591 cap & (1 << 29) ? "sntf " : "",
Linus Torvalds1da177e2005-04-16 15:20:36 -07002592 cap & (1 << 28) ? "ilck " : "",
2593 cap & (1 << 27) ? "stag " : "",
2594 cap & (1 << 26) ? "pm " : "",
2595 cap & (1 << 25) ? "led " : "",
2596
2597 cap & (1 << 24) ? "clo " : "",
2598 cap & (1 << 19) ? "nz " : "",
2599 cap & (1 << 18) ? "only " : "",
2600 cap & (1 << 17) ? "pmp " : "",
2601 cap & (1 << 15) ? "pio " : "",
2602 cap & (1 << 14) ? "slum " : "",
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002603 cap & (1 << 13) ? "part " : "",
2604 cap & (1 << 6) ? "ems ": ""
Linus Torvalds1da177e2005-04-16 15:20:36 -07002605 );
2606}
2607
Tejun Heoedc93052007-10-25 14:59:16 +09002608/* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
2609 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
2610 * support PMP and the 4726 either directly exports the device
2611 * attached to the first downstream port or acts as a hardware storage
2612 * controller and emulate a single ATA device (can be RAID 0/1 or some
2613 * other configuration).
2614 *
2615 * When there's no device attached to the first downstream port of the
2616 * 4726, "Config Disk" appears, which is a pseudo ATA device to
2617 * configure the 4726. However, ATA emulation of the device is very
2618 * lame. It doesn't send signature D2H Reg FIS after the initial
2619 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
2620 *
2621 * The following function works around the problem by always using
2622 * hardreset on the port and not depending on receiving signature FIS
2623 * afterward. If signature FIS isn't received soon, ATA class is
2624 * assumed without follow-up softreset.
2625 */
2626static void ahci_p5wdh_workaround(struct ata_host *host)
2627{
2628 static struct dmi_system_id sysids[] = {
2629 {
2630 .ident = "P5W DH Deluxe",
2631 .matches = {
2632 DMI_MATCH(DMI_SYS_VENDOR,
2633 "ASUSTEK COMPUTER INC"),
2634 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
2635 },
2636 },
2637 { }
2638 };
2639 struct pci_dev *pdev = to_pci_dev(host->dev);
2640
2641 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
2642 dmi_check_system(sysids)) {
2643 struct ata_port *ap = host->ports[1];
2644
2645 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
2646 "Deluxe on-board SIMG4726 workaround\n");
2647
2648 ap->ops = &ahci_p5wdh_ops;
2649 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
2650 }
2651}
2652
Shane Huang58a09b32009-05-27 15:04:43 +08002653/*
Tejun Heo03d783b2009-08-16 21:04:02 +09002654 * SB600 ahci controller on certain boards can't do 64bit DMA with
2655 * older BIOS.
Shane Huang58a09b32009-05-27 15:04:43 +08002656 */
Tejun Heo03d783b2009-08-16 21:04:02 +09002657static bool ahci_sb600_32bit_only(struct pci_dev *pdev)
Shane Huang58a09b32009-05-27 15:04:43 +08002658{
2659 static const struct dmi_system_id sysids[] = {
Tejun Heo03d783b2009-08-16 21:04:02 +09002660 /*
2661 * The oldest version known to be broken is 0901 and
2662 * working is 1501 which was released on 2007-10-26.
2663 * Force 32bit DMA on anything older than 1501.
2664 * Please read bko#9412 for more info.
2665 */
Shane Huang58a09b32009-05-27 15:04:43 +08002666 {
2667 .ident = "ASUS M2A-VM",
2668 .matches = {
2669 DMI_MATCH(DMI_BOARD_VENDOR,
2670 "ASUSTeK Computer INC."),
2671 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
2672 },
Tejun Heo03d783b2009-08-16 21:04:02 +09002673 .driver_data = "20071026", /* yyyymmdd */
Shane Huang58a09b32009-05-27 15:04:43 +08002674 },
Tejun Heo1b549dc2009-08-16 21:06:57 +09002675 /*
2676 * It's yet unknown whether more recent BIOS fixes the
2677 * problem. Blacklist the whole board for the time
2678 * being. Please read the following thread for more
2679 * info.
2680 *
2681 * http://thread.gmane.org/gmane.linux.ide/42326
2682 */
2683 {
2684 .ident = "Gigabyte GA-MA69VM-S2",
2685 .matches = {
2686 DMI_MATCH(DMI_BOARD_VENDOR,
2687 "Gigabyte Technology Co., Ltd."),
2688 DMI_MATCH(DMI_BOARD_NAME, "GA-MA69VM-S2"),
2689 },
2690 },
Shane Huang58a09b32009-05-27 15:04:43 +08002691 { }
2692 };
Tejun Heo03d783b2009-08-16 21:04:02 +09002693 const struct dmi_system_id *match;
Shane Huang58a09b32009-05-27 15:04:43 +08002694
Tejun Heo03d783b2009-08-16 21:04:02 +09002695 match = dmi_first_match(sysids);
Shane Huang58a09b32009-05-27 15:04:43 +08002696 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
Tejun Heo03d783b2009-08-16 21:04:02 +09002697 !match)
Shane Huang58a09b32009-05-27 15:04:43 +08002698 return false;
2699
Tejun Heo03d783b2009-08-16 21:04:02 +09002700 if (match->driver_data) {
2701 int year, month, date;
2702 char buf[9];
Shane Huang58a09b32009-05-27 15:04:43 +08002703
Tejun Heo03d783b2009-08-16 21:04:02 +09002704 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
2705 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
2706
2707 if (strcmp(buf, match->driver_data) >= 0)
2708 return false;
2709
2710 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
2711 "forcing 32bit DMA, update BIOS\n", match->ident);
2712 } else
2713 dev_printk(KERN_WARNING, &pdev->dev, "%s: this board can't "
2714 "do 64bit DMA, forcing 32bit\n", match->ident);
Shane Huang58a09b32009-05-27 15:04:43 +08002715
2716 return true;
2717}
2718
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01002719static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
2720{
2721 static const struct dmi_system_id broken_systems[] = {
2722 {
2723 .ident = "HP Compaq nx6310",
2724 .matches = {
2725 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2726 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
2727 },
2728 /* PCI slot number of the controller */
2729 .driver_data = (void *)0x1FUL,
2730 },
Maciej Ruteckid2f9c062009-03-20 00:06:46 +01002731 {
2732 .ident = "HP Compaq 6720s",
2733 .matches = {
2734 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2735 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
2736 },
2737 /* PCI slot number of the controller */
2738 .driver_data = (void *)0x1FUL,
2739 },
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01002740
2741 { } /* terminate list */
2742 };
2743 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
2744
2745 if (dmi) {
2746 unsigned long slot = (unsigned long)dmi->driver_data;
2747 /* apply the quirk only to on-board controllers */
2748 return slot == PCI_SLOT(pdev->devfn);
2749 }
2750
2751 return false;
2752}
2753
Tejun Heo9b10ae82009-05-30 20:50:12 +09002754static bool ahci_broken_suspend(struct pci_dev *pdev)
2755{
2756 static const struct dmi_system_id sysids[] = {
2757 /*
2758 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
2759 * to the harddisk doesn't become online after
2760 * resuming from STR. Warn and fail suspend.
2761 */
2762 {
2763 .ident = "dv4",
2764 .matches = {
2765 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2766 DMI_MATCH(DMI_PRODUCT_NAME,
2767 "HP Pavilion dv4 Notebook PC"),
2768 },
2769 .driver_data = "F.30", /* cutoff BIOS version */
2770 },
2771 {
2772 .ident = "dv5",
2773 .matches = {
2774 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2775 DMI_MATCH(DMI_PRODUCT_NAME,
2776 "HP Pavilion dv5 Notebook PC"),
2777 },
2778 .driver_data = "F.16", /* cutoff BIOS version */
2779 },
2780 {
2781 .ident = "dv6",
2782 .matches = {
2783 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2784 DMI_MATCH(DMI_PRODUCT_NAME,
2785 "HP Pavilion dv6 Notebook PC"),
2786 },
2787 .driver_data = "F.21", /* cutoff BIOS version */
2788 },
2789 {
2790 .ident = "HDX18",
2791 .matches = {
2792 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
2793 DMI_MATCH(DMI_PRODUCT_NAME,
2794 "HP HDX18 Notebook PC"),
2795 },
2796 .driver_data = "F.23", /* cutoff BIOS version */
2797 },
2798 { } /* terminate list */
2799 };
2800 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2801 const char *ver;
2802
2803 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
2804 return false;
2805
2806 ver = dmi_get_system_info(DMI_BIOS_VERSION);
2807
2808 return !ver || strcmp(ver, dmi->driver_data) < 0;
2809}
2810
Tejun Heo55946392009-08-04 14:30:08 +09002811static bool ahci_broken_online(struct pci_dev *pdev)
2812{
2813#define ENCODE_BUSDEVFN(bus, slot, func) \
2814 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
2815 static const struct dmi_system_id sysids[] = {
2816 /*
2817 * There are several gigabyte boards which use
2818 * SIMG5723s configured as hardware RAID. Certain
2819 * 5723 firmware revisions shipped there keep the link
2820 * online but fail to answer properly to SRST or
2821 * IDENTIFY when no device is attached downstream
2822 * causing libata to retry quite a few times leading
2823 * to excessive detection delay.
2824 *
2825 * As these firmwares respond to the second reset try
2826 * with invalid device signature, considering unknown
2827 * sig as offline works around the problem acceptably.
2828 */
2829 {
2830 .ident = "EP45-DQ6",
2831 .matches = {
2832 DMI_MATCH(DMI_BOARD_VENDOR,
2833 "Gigabyte Technology Co., Ltd."),
2834 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
2835 },
2836 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
2837 },
2838 {
2839 .ident = "EP45-DS5",
2840 .matches = {
2841 DMI_MATCH(DMI_BOARD_VENDOR,
2842 "Gigabyte Technology Co., Ltd."),
2843 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
2844 },
2845 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
2846 },
2847 { } /* terminate list */
2848 };
2849#undef ENCODE_BUSDEVFN
2850 const struct dmi_system_id *dmi = dmi_first_match(sysids);
2851 unsigned int val;
2852
2853 if (!dmi)
2854 return false;
2855
2856 val = (unsigned long)dmi->driver_data;
2857
2858 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
2859}
2860
Tejun Heo24dc5f32007-01-20 16:00:28 +09002861static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002862{
2863 static int printed_version;
Tejun Heoe297d992008-06-10 00:13:04 +09002864 unsigned int board_id = ent->driver_data;
2865 struct ata_port_info pi = ahci_port_info[board_id];
Tejun Heo4447d352007-04-17 23:44:08 +09002866 const struct ata_port_info *ppi[] = { &pi, NULL };
Tejun Heo24dc5f32007-01-20 16:00:28 +09002867 struct device *dev = &pdev->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002868 struct ahci_host_priv *hpriv;
Tejun Heo4447d352007-04-17 23:44:08 +09002869 struct ata_host *host;
Tejun Heo837f5f82008-02-06 15:13:51 +09002870 int n_ports, i, rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002871
2872 VPRINTK("ENTER\n");
2873
Tejun Heo12fad3f2006-05-15 21:03:55 +09002874 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
2875
Linus Torvalds1da177e2005-04-16 15:20:36 -07002876 if (!printed_version++)
Jeff Garzika9524a72005-10-30 14:39:11 -05002877 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07002878
Alan Cox5b66c822008-09-03 14:48:34 +01002879 /* The AHCI driver can only drive the SATA ports, the PATA driver
2880 can drive them all so if both drivers are selected make sure
2881 AHCI stays out of the way */
2882 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
2883 return -ENODEV;
2884
Tejun Heo4447d352007-04-17 23:44:08 +09002885 /* acquire resources */
Tejun Heo24dc5f32007-01-20 16:00:28 +09002886 rc = pcim_enable_device(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002887 if (rc)
2888 return rc;
2889
Tejun Heodea55132008-03-11 19:52:31 +09002890 /* AHCI controllers often implement SFF compatible interface.
2891 * Grab all PCI BARs just in case.
2892 */
2893 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002894 if (rc == -EBUSY)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002895 pcim_pin_device(pdev);
Tejun Heo0d5ff562007-02-01 15:06:36 +09002896 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09002897 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002898
Tejun Heoc4f77922007-12-06 15:09:43 +09002899 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
2900 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
2901 u8 map;
2902
2903 /* ICH6s share the same PCI ID for both piix and ahci
2904 * modes. Enabling ahci mode while MAP indicates
2905 * combined mode is a bad idea. Yield to ata_piix.
2906 */
2907 pci_read_config_byte(pdev, ICH_MAP, &map);
2908 if (map & 0x3) {
2909 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
2910 "combined mode, can't enable AHCI mode\n");
2911 return -ENODEV;
2912 }
2913 }
2914
Tejun Heo24dc5f32007-01-20 16:00:28 +09002915 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
2916 if (!hpriv)
2917 return -ENOMEM;
Tejun Heo417a1a62007-09-23 13:19:55 +09002918 hpriv->flags |= (unsigned long)pi.private_data;
2919
Tejun Heoe297d992008-06-10 00:13:04 +09002920 /* MCP65 revision A1 and A2 can't do MSI */
2921 if (board_id == board_ahci_mcp65 &&
2922 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
2923 hpriv->flags |= AHCI_HFLAG_NO_MSI;
2924
Shane Huange427fe02008-12-30 10:53:41 +08002925 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
2926 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
2927 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
2928
Tejun Heo03d783b2009-08-16 21:04:02 +09002929 /* apply sb600 32bit only quirk */
2930 if (ahci_sb600_32bit_only(pdev))
Shane Huang58a09b32009-05-27 15:04:43 +08002931 hpriv->flags |= AHCI_HFLAG_32BIT_ONLY;
2932
Tejun Heoa5bfc472009-01-23 11:31:39 +09002933 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI))
2934 pci_enable_msi(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002935
Tejun Heo4447d352007-04-17 23:44:08 +09002936 /* save initial config */
Tejun Heo417a1a62007-09-23 13:19:55 +09002937 ahci_save_initial_config(pdev, hpriv);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002938
Tejun Heo4447d352007-04-17 23:44:08 +09002939 /* prepare host */
Tejun Heo274c1fd2007-07-16 14:29:40 +09002940 if (hpriv->cap & HOST_CAP_NCQ)
Shaohua Li388539f2009-07-27 09:24:35 +08002941 pi.flags |= ATA_FLAG_NCQ | ATA_FLAG_FPDMA_AA;
Tejun Heo4447d352007-04-17 23:44:08 +09002942
Tejun Heo7d50b602007-09-23 13:19:54 +09002943 if (hpriv->cap & HOST_CAP_PMP)
2944 pi.flags |= ATA_FLAG_PMP;
2945
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002946 if (ahci_em_messages && (hpriv->cap & HOST_CAP_EMS)) {
2947 u8 messages;
2948 void __iomem *mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
2949 u32 em_loc = readl(mmio + HOST_EM_LOC);
2950 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2951
David Milburn87943ac2008-10-13 14:38:36 -05002952 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07002953
2954 /* we only support LED message type right now */
2955 if ((messages & 0x01) && (ahci_em_messages == 1)) {
2956 /* store em_loc */
2957 hpriv->em_loc = ((em_loc >> 16) * 4);
2958 pi.flags |= ATA_FLAG_EM;
2959 if (!(em_ctl & EM_CTL_ALHD))
2960 pi.flags |= ATA_FLAG_SW_ACTIVITY;
2961 }
2962 }
2963
Rafael J. Wysocki1fd68432009-01-19 20:57:36 +01002964 if (ahci_broken_system_poweroff(pdev)) {
2965 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
2966 dev_info(&pdev->dev,
2967 "quirky BIOS, skipping spindown on poweroff\n");
2968 }
2969
Tejun Heo9b10ae82009-05-30 20:50:12 +09002970 if (ahci_broken_suspend(pdev)) {
2971 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
2972 dev_printk(KERN_WARNING, &pdev->dev,
2973 "BIOS update required for suspend/resume\n");
2974 }
2975
Tejun Heo55946392009-08-04 14:30:08 +09002976 if (ahci_broken_online(pdev)) {
2977 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
2978 dev_info(&pdev->dev,
2979 "online status unreliable, applying workaround\n");
2980 }
2981
Tejun Heo837f5f82008-02-06 15:13:51 +09002982 /* CAP.NP sometimes indicate the index of the last enabled
2983 * port, at other times, that of the last possible port, so
2984 * determining the maximum port number requires looking at
2985 * both CAP.NP and port_map.
2986 */
2987 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
2988
2989 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
Tejun Heo4447d352007-04-17 23:44:08 +09002990 if (!host)
2991 return -ENOMEM;
2992 host->iomap = pcim_iomap_table(pdev);
2993 host->private_data = hpriv;
2994
Arjan van de Venf3d7f232009-01-26 02:05:44 -08002995 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
Arjan van de Ven886ad092009-01-09 15:54:07 -08002996 host->flags |= ATA_HOST_PARALLEL_SCAN;
Arjan van de Venf3d7f232009-01-26 02:05:44 -08002997 else
2998 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
Arjan van de Ven886ad092009-01-09 15:54:07 -08002999
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07003000 if (pi.flags & ATA_FLAG_EM)
3001 ahci_reset_em(host);
3002
Tejun Heo4447d352007-04-17 23:44:08 +09003003 for (i = 0; i < host->n_ports; i++) {
Jeff Garzikdab632e2007-05-28 08:33:01 -04003004 struct ata_port *ap = host->ports[i];
Tejun Heo4447d352007-04-17 23:44:08 +09003005
Tejun Heocbcdd872007-08-18 13:14:55 +09003006 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
3007 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
3008 0x100 + ap->port_no * 0x80, "port");
3009
Kristen Carlson Accardi31556592007-10-25 01:33:26 -04003010 /* set initial link pm policy */
3011 ap->pm_policy = NOT_AVAILABLE;
3012
Kristen Carlson Accardi18f7ba42008-06-03 10:33:55 -07003013 /* set enclosure management message type */
3014 if (ap->flags & ATA_FLAG_EM)
3015 ap->em_message_type = ahci_em_messages;
3016
3017
Jeff Garzikdab632e2007-05-28 08:33:01 -04003018 /* disabled/not-implemented port */
Tejun Heo350756f2008-04-07 22:47:21 +09003019 if (!(hpriv->port_map & (1 << i)))
Jeff Garzikdab632e2007-05-28 08:33:01 -04003020 ap->ops = &ata_dummy_port_ops;
Tejun Heo4447d352007-04-17 23:44:08 +09003021 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003022
Tejun Heoedc93052007-10-25 14:59:16 +09003023 /* apply workaround for ASUS P5W DH Deluxe mainboard */
3024 ahci_p5wdh_workaround(host);
3025
Linus Torvalds1da177e2005-04-16 15:20:36 -07003026 /* initialize adapter */
Tejun Heo4447d352007-04-17 23:44:08 +09003027 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003028 if (rc)
Tejun Heo24dc5f32007-01-20 16:00:28 +09003029 return rc;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003030
Tejun Heo4447d352007-04-17 23:44:08 +09003031 rc = ahci_reset_controller(host);
3032 if (rc)
3033 return rc;
Tejun Heo12fad3f2006-05-15 21:03:55 +09003034
Tejun Heo4447d352007-04-17 23:44:08 +09003035 ahci_init_controller(host);
3036 ahci_print_info(host);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003037
Tejun Heo4447d352007-04-17 23:44:08 +09003038 pci_set_master(pdev);
3039 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
3040 &ahci_sht);
Jeff Garzik907f4672005-05-12 15:03:42 -04003041}
Linus Torvalds1da177e2005-04-16 15:20:36 -07003042
3043static int __init ahci_init(void)
3044{
Pavel Roskinb7887192006-08-10 18:13:18 +09003045 return pci_register_driver(&ahci_pci_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003046}
3047
Linus Torvalds1da177e2005-04-16 15:20:36 -07003048static void __exit ahci_exit(void)
3049{
3050 pci_unregister_driver(&ahci_pci_driver);
3051}
3052
3053
3054MODULE_AUTHOR("Jeff Garzik");
3055MODULE_DESCRIPTION("AHCI SATA low-level driver");
3056MODULE_LICENSE("GPL");
3057MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
Jeff Garzik68854332005-08-23 02:53:51 -04003058MODULE_VERSION(DRV_VERSION);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003059
3060module_init(ahci_init);
3061module_exit(ahci_exit);