sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 3 | /*--- Begin main_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 4 | /*---------------------------------------------------------------*/ |
| 5 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 6 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 7 | This file is part of Valgrind, a dynamic binary instrumentation |
| 8 | framework. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | |
sewardj | 89ae847 | 2013-10-18 14:12:58 +0000 | [diff] [blame] | 10 | Copyright (C) 2004-2013 OpenWorks LLP |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 11 | info@open-works.net |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 12 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 13 | This program is free software; you can redistribute it and/or |
| 14 | modify it under the terms of the GNU General Public License as |
| 15 | published by the Free Software Foundation; either version 2 of the |
| 16 | License, or (at your option) any later version. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 17 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 18 | This program is distributed in the hope that it will be useful, but |
| 19 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 21 | General Public License for more details. |
| 22 | |
| 23 | You should have received a copy of the GNU General Public License |
| 24 | along with this program; if not, write to the Free Software |
| 25 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 26 | 02110-1301, USA. |
| 27 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 28 | The GNU General Public License is contained in the file COPYING. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 29 | |
| 30 | Neither the names of the U.S. Department of Energy nor the |
| 31 | University of California nor the names of its contributors may be |
| 32 | used to endorse or promote products derived from this software |
| 33 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 34 | */ |
| 35 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 36 | #include "libvex.h" |
florian | 33b0243 | 2012-08-25 21:48:04 +0000 | [diff] [blame] | 37 | #include "libvex_emnote.h" |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 38 | #include "libvex_guest_x86.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 39 | #include "libvex_guest_amd64.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 40 | #include "libvex_guest_arm.h" |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 41 | #include "libvex_guest_arm64.h" |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 42 | #include "libvex_guest_ppc32.h" |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 43 | #include "libvex_guest_ppc64.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 44 | #include "libvex_guest_s390x.h" |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 45 | #include "libvex_guest_mips32.h" |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 46 | #include "libvex_guest_mips64.h" |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 47 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 48 | #include "main_globals.h" |
| 49 | #include "main_util.h" |
| 50 | #include "host_generic_regs.h" |
| 51 | #include "ir_opt.h" |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 52 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 53 | #include "host_x86_defs.h" |
| 54 | #include "host_amd64_defs.h" |
| 55 | #include "host_ppc_defs.h" |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 56 | #include "host_arm_defs.h" |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 57 | #include "host_arm64_defs.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 58 | #include "host_s390_defs.h" |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 59 | #include "host_mips_defs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 60 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 61 | #include "guest_generic_bb_to_IR.h" |
| 62 | #include "guest_x86_defs.h" |
| 63 | #include "guest_amd64_defs.h" |
| 64 | #include "guest_arm_defs.h" |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 65 | #include "guest_arm64_defs.h" |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 66 | #include "guest_ppc_defs.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 67 | #include "guest_s390_defs.h" |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 68 | #include "guest_mips_defs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 69 | |
sewardj | 69d98e3 | 2010-06-18 08:17:41 +0000 | [diff] [blame] | 70 | #include "host_generic_simd128.h" |
| 71 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 72 | |
| 73 | /* This file contains the top level interface to the library. */ |
| 74 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 75 | /* --------- fwds ... --------- */ |
| 76 | |
| 77 | static Bool are_valid_hwcaps ( VexArch arch, UInt hwcaps ); |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 78 | static const HChar* show_hwcaps ( VexArch arch, UInt hwcaps ); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 79 | |
| 80 | |
sewardj | 8bde7f1 | 2013-04-11 13:57:43 +0000 | [diff] [blame] | 81 | /* --------- helpers --------- */ |
| 82 | |
| 83 | __attribute__((noinline)) |
| 84 | static UInt udiv32 ( UInt x, UInt y ) { return x/y; } |
| 85 | __attribute__((noinline)) |
| 86 | static Int sdiv32 ( Int x, Int y ) { return x/y; } |
| 87 | |
| 88 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 89 | /* --------- Initialise the library. --------- */ |
| 90 | |
| 91 | /* Exported to library client. */ |
| 92 | |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 93 | void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon ) |
| 94 | { |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 95 | vex_bzero(vcon, sizeof(*vcon)); |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 96 | vcon->iropt_verbosity = 0; |
| 97 | vcon->iropt_level = 2; |
philippe | c8e2f98 | 2012-08-01 22:04:13 +0000 | [diff] [blame] | 98 | vcon->iropt_register_updates = VexRegUpdUnwindregsAtMemAccess; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 99 | vcon->iropt_unroll_thresh = 120; |
sewardj | 18b4bb7 | 2005-03-29 21:32:41 +0000 | [diff] [blame] | 100 | vcon->guest_max_insns = 60; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 101 | vcon->guest_chase_thresh = 10; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 102 | vcon->guest_chase_cond = False; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 103 | } |
| 104 | |
| 105 | |
| 106 | /* Exported to library client. */ |
| 107 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 108 | void LibVEX_Init ( |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 109 | /* failure exit function */ |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 110 | __attribute__ ((noreturn)) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 111 | void (*failure_exit) ( void ), |
| 112 | /* logging output function */ |
sewardj | d976362 | 2005-02-07 03:12:19 +0000 | [diff] [blame] | 113 | void (*log_bytes) ( HChar*, Int nbytes ), |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 114 | /* debug paranoia level */ |
| 115 | Int debuglevel, |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 116 | /* Control ... */ |
florian | f72c2c1 | 2014-09-05 21:52:29 +0000 | [diff] [blame] | 117 | const VexControl* vcon |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 118 | ) |
| 119 | { |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 120 | /* First off, do enough minimal setup so that the following |
| 121 | assertions can fail in a sane fashion, if need be. */ |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 122 | vex_failure_exit = failure_exit; |
| 123 | vex_log_bytes = log_bytes; |
| 124 | |
| 125 | /* Now it's safe to check parameters for sanity. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 126 | vassert(!vex_initdone); |
| 127 | vassert(failure_exit); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 128 | vassert(log_bytes); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 129 | vassert(debuglevel >= 0); |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 130 | |
| 131 | vassert(vcon->iropt_verbosity >= 0); |
| 132 | vassert(vcon->iropt_level >= 0); |
| 133 | vassert(vcon->iropt_level <= 2); |
| 134 | vassert(vcon->iropt_unroll_thresh >= 0); |
| 135 | vassert(vcon->iropt_unroll_thresh <= 400); |
| 136 | vassert(vcon->guest_max_insns >= 1); |
| 137 | vassert(vcon->guest_max_insns <= 100); |
| 138 | vassert(vcon->guest_chase_thresh >= 0); |
| 139 | vassert(vcon->guest_chase_thresh < vcon->guest_max_insns); |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 140 | vassert(vcon->guest_chase_cond == True |
| 141 | || vcon->guest_chase_cond == False); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 142 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 143 | /* Check that Vex has been built with sizes of basic types as |
| 144 | stated in priv/libvex_basictypes.h. Failure of any of these is |
| 145 | a serious configuration error and should be corrected |
| 146 | immediately. If any of these assertions fail you can fully |
| 147 | expect Vex not to work properly, if at all. */ |
| 148 | |
| 149 | vassert(1 == sizeof(UChar)); |
| 150 | vassert(1 == sizeof(Char)); |
| 151 | vassert(2 == sizeof(UShort)); |
| 152 | vassert(2 == sizeof(Short)); |
| 153 | vassert(4 == sizeof(UInt)); |
| 154 | vassert(4 == sizeof(Int)); |
| 155 | vassert(8 == sizeof(ULong)); |
| 156 | vassert(8 == sizeof(Long)); |
| 157 | vassert(4 == sizeof(Float)); |
| 158 | vassert(8 == sizeof(Double)); |
| 159 | vassert(1 == sizeof(Bool)); |
| 160 | vassert(4 == sizeof(Addr32)); |
| 161 | vassert(8 == sizeof(Addr64)); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 162 | vassert(16 == sizeof(U128)); |
sewardj | 69d98e3 | 2010-06-18 08:17:41 +0000 | [diff] [blame] | 163 | vassert(16 == sizeof(V128)); |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 164 | vassert(32 == sizeof(U256)); |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 165 | |
| 166 | vassert(sizeof(void*) == 4 || sizeof(void*) == 8); |
| 167 | vassert(sizeof(void*) == sizeof(int*)); |
| 168 | vassert(sizeof(void*) == sizeof(HWord)); |
| 169 | |
sewardj | 97e8793 | 2005-02-07 00:00:50 +0000 | [diff] [blame] | 170 | vassert(VEX_HOST_WORDSIZE == sizeof(void*)); |
| 171 | vassert(VEX_HOST_WORDSIZE == sizeof(HWord)); |
| 172 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 173 | /* These take a lot of space, so make sure we don't have |
| 174 | any unnoticed size regressions. */ |
| 175 | if (VEX_HOST_WORDSIZE == 4) { |
florian | 420bfa9 | 2012-06-02 20:29:22 +0000 | [diff] [blame] | 176 | vassert(sizeof(IRExpr) == 16); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 177 | vassert(sizeof(IRStmt) == 20 /* x86 */ |
| 178 | || sizeof(IRStmt) == 24 /* arm */); |
| 179 | } else { |
florian | 420bfa9 | 2012-06-02 20:29:22 +0000 | [diff] [blame] | 180 | vassert(sizeof(IRExpr) == 32); |
florian | d6f38b3 | 2012-05-31 15:46:18 +0000 | [diff] [blame] | 181 | vassert(sizeof(IRStmt) == 32); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 182 | } |
| 183 | |
sewardj | 8bde7f1 | 2013-04-11 13:57:43 +0000 | [diff] [blame] | 184 | /* Check that signed integer division on the host rounds towards |
| 185 | zero. If not, h_calc_sdiv32_w_arm_semantics() won't work |
| 186 | correctly. */ |
| 187 | /* 100.0 / 7.0 == 14.2857 */ |
| 188 | vassert(udiv32(100, 7) == 14); |
| 189 | vassert(sdiv32(100, 7) == 14); |
| 190 | vassert(sdiv32(-100, 7) == -14); /* and not -15 */ |
| 191 | vassert(sdiv32(100, -7) == -14); /* ditto */ |
| 192 | vassert(sdiv32(-100, -7) == 14); /* not sure what this proves */ |
| 193 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 194 | /* Really start up .. */ |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 195 | vex_debuglevel = debuglevel; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 196 | vex_control = *vcon; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 197 | vex_initdone = True; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 198 | vexSetAllocMode ( VexAllocModeTEMP ); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 199 | } |
| 200 | |
| 201 | |
| 202 | /* --------- Make a translation. --------- */ |
| 203 | |
| 204 | /* Exported to library client. */ |
| 205 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 206 | VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 207 | { |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 208 | /* This the bundle of functions we need to do the back-end stuff |
| 209 | (insn selection, reg-alloc, assembly) whilst being insulated |
| 210 | from the target instruction set. */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 211 | HReg* available_real_regs; |
| 212 | Int n_available_real_regs; |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 213 | Bool (*isMove) ( const HInstr*, HReg*, HReg* ); |
| 214 | void (*getRegUsage) ( HRegUsage*, const HInstr*, Bool ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 215 | void (*mapRegs) ( HRegRemap*, HInstr*, Bool ); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 216 | void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool ); |
| 217 | void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 218 | HInstr* (*directReload) ( HInstr*, HReg, Short ); |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 219 | void (*ppInstr) ( const HInstr*, Bool ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 220 | void (*ppReg) ( HReg ); |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 221 | HInstrArray* (*iselSB) ( IRSB*, VexArch, const VexArchInfo*, |
| 222 | const VexAbiInfo*, Int, Int, Bool, Bool, |
| 223 | Addr64 ); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 224 | Int (*emit) ( /*MB_MOD*/Bool*, |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 225 | UChar*, Int, const HInstr*, Bool, VexEndness, |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 226 | const void*, const void*, const void*, |
| 227 | const void* ); |
florian | 1ff4756 | 2012-10-21 02:09:51 +0000 | [diff] [blame] | 228 | IRExpr* (*specHelper) ( const HChar*, IRExpr**, IRStmt**, Int ); |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 229 | Bool (*preciseMemExnsFn) ( Int, Int ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 230 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 231 | DisOneInstrFn disInstrFn; |
| 232 | |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 233 | VexGuestLayout* guest_layout; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 234 | IRSB* irsb; |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 235 | HInstrArray* vcode; |
| 236 | HInstrArray* rcode; |
| 237 | Int i, j, k, out_used, guest_sizeB; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 238 | Int offB_CMSTART, offB_CMLEN, offB_GUEST_IP, szB_GUEST_IP; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 239 | Int offB_HOST_EvC_COUNTER, offB_HOST_EvC_FAILADDR; |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 240 | UChar insn_bytes[128]; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 241 | IRType guest_word_type; |
| 242 | IRType host_word_type; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 243 | Bool mode64, chainingAllowed; |
| 244 | Addr64 max_ga; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 245 | |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 246 | guest_layout = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 247 | available_real_regs = NULL; |
| 248 | n_available_real_regs = 0; |
| 249 | isMove = NULL; |
| 250 | getRegUsage = NULL; |
| 251 | mapRegs = NULL; |
| 252 | genSpill = NULL; |
| 253 | genReload = NULL; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 254 | directReload = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 255 | ppInstr = NULL; |
| 256 | ppReg = NULL; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 257 | iselSB = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 258 | emit = NULL; |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 259 | specHelper = NULL; |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 260 | preciseMemExnsFn = NULL; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 261 | disInstrFn = NULL; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 262 | guest_word_type = Ity_INVALID; |
| 263 | host_word_type = Ity_INVALID; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 264 | offB_CMSTART = 0; |
| 265 | offB_CMLEN = 0; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 266 | offB_GUEST_IP = 0; |
| 267 | szB_GUEST_IP = 0; |
| 268 | offB_HOST_EvC_COUNTER = 0; |
| 269 | offB_HOST_EvC_FAILADDR = 0; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 270 | mode64 = False; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 271 | chainingAllowed = False; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 272 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 273 | vex_traceflags = vta->traceflags; |
sewardj | 58800ff | 2004-07-28 01:51:10 +0000 | [diff] [blame] | 274 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 275 | vassert(vex_initdone); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 276 | vassert(vta->needs_self_check != NULL); |
| 277 | vassert(vta->disp_cp_xassisted != NULL); |
| 278 | /* Both the chainers and the indir are either NULL or non-NULL. */ |
| 279 | if (vta->disp_cp_chain_me_to_slowEP != NULL) { |
| 280 | vassert(vta->disp_cp_chain_me_to_fastEP != NULL); |
| 281 | vassert(vta->disp_cp_xindir != NULL); |
| 282 | chainingAllowed = True; |
| 283 | } else { |
| 284 | vassert(vta->disp_cp_chain_me_to_fastEP == NULL); |
| 285 | vassert(vta->disp_cp_xindir == NULL); |
| 286 | } |
florian | 2eeeb9b | 2011-09-23 18:03:21 +0000 | [diff] [blame] | 287 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 288 | vexSetAllocModeTEMP_and_clear(); |
| 289 | vexAllocSanityCheck(); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 290 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 291 | /* First off, check that the guest and host insn sets |
| 292 | are supported. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 293 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 294 | switch (vta->arch_host) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 295 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 296 | case VexArchX86: |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 297 | mode64 = False; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 298 | getAllocableRegs_X86 ( &n_available_real_regs, |
| 299 | &available_real_regs ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 300 | isMove = (__typeof__(isMove)) isMove_X86Instr; |
| 301 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_X86Instr; |
| 302 | mapRegs = (__typeof__(mapRegs)) mapRegs_X86Instr; |
| 303 | genSpill = (__typeof__(genSpill)) genSpill_X86; |
| 304 | genReload = (__typeof__(genReload)) genReload_X86; |
| 305 | directReload = (__typeof__(directReload)) directReload_X86; |
| 306 | ppInstr = (__typeof__(ppInstr)) ppX86Instr; |
| 307 | ppReg = (__typeof__(ppReg)) ppHRegX86; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 308 | iselSB = iselSB_X86; |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 309 | emit = (__typeof__(emit)) emit_X86Instr; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 310 | host_word_type = Ity_I32; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 311 | vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 312 | vassert(vta->archinfo_host.endness == VexEndnessLE); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 313 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 314 | |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 315 | case VexArchAMD64: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 316 | mode64 = True; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 317 | getAllocableRegs_AMD64 ( &n_available_real_regs, |
| 318 | &available_real_regs ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 319 | isMove = (__typeof__(isMove)) isMove_AMD64Instr; |
| 320 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_AMD64Instr; |
| 321 | mapRegs = (__typeof__(mapRegs)) mapRegs_AMD64Instr; |
| 322 | genSpill = (__typeof__(genSpill)) genSpill_AMD64; |
| 323 | genReload = (__typeof__(genReload)) genReload_AMD64; |
| 324 | ppInstr = (__typeof__(ppInstr)) ppAMD64Instr; |
| 325 | ppReg = (__typeof__(ppReg)) ppHRegAMD64; |
| 326 | iselSB = iselSB_AMD64; |
| 327 | emit = (__typeof__(emit)) emit_AMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 328 | host_word_type = Ity_I64; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 329 | vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 330 | vassert(vta->archinfo_host.endness == VexEndnessLE); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 331 | break; |
| 332 | |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 333 | case VexArchPPC32: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 334 | mode64 = False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 335 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 336 | &available_real_regs, mode64 ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 337 | isMove = (__typeof__(isMove)) isMove_PPCInstr; |
| 338 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_PPCInstr; |
| 339 | mapRegs = (__typeof__(mapRegs)) mapRegs_PPCInstr; |
| 340 | genSpill = (__typeof__(genSpill)) genSpill_PPC; |
| 341 | genReload = (__typeof__(genReload)) genReload_PPC; |
| 342 | ppInstr = (__typeof__(ppInstr)) ppPPCInstr; |
| 343 | ppReg = (__typeof__(ppReg)) ppHRegPPC; |
| 344 | iselSB = iselSB_PPC; |
| 345 | emit = (__typeof__(emit)) emit_PPCInstr; |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 346 | host_word_type = Ity_I32; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 347 | vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 348 | vassert(vta->archinfo_host.endness == VexEndnessBE); |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 349 | break; |
| 350 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 351 | case VexArchPPC64: |
| 352 | mode64 = True; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 353 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 354 | &available_real_regs, mode64 ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 355 | isMove = (__typeof__(isMove)) isMove_PPCInstr; |
| 356 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_PPCInstr; |
| 357 | mapRegs = (__typeof__(mapRegs)) mapRegs_PPCInstr; |
| 358 | genSpill = (__typeof__(genSpill)) genSpill_PPC; |
| 359 | genReload = (__typeof__(genReload)) genReload_PPC; |
| 360 | ppInstr = (__typeof__(ppInstr)) ppPPCInstr; |
| 361 | ppReg = (__typeof__(ppReg)) ppHRegPPC; |
| 362 | iselSB = iselSB_PPC; |
| 363 | emit = (__typeof__(emit)) emit_PPCInstr; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 364 | host_word_type = Ity_I64; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 365 | vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_host.hwcaps)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 366 | vassert(vta->archinfo_host.endness == VexEndnessBE || |
| 367 | vta->archinfo_host.endness == VexEndnessLE ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 368 | break; |
| 369 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 370 | case VexArchS390X: |
| 371 | mode64 = True; |
| 372 | getAllocableRegs_S390 ( &n_available_real_regs, |
| 373 | &available_real_regs, mode64 ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 374 | isMove = (__typeof__(isMove)) isMove_S390Instr; |
| 375 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_S390Instr; |
| 376 | mapRegs = (__typeof__(mapRegs)) mapRegs_S390Instr; |
| 377 | genSpill = (__typeof__(genSpill)) genSpill_S390; |
| 378 | genReload = (__typeof__(genReload)) genReload_S390; |
florian | 017c0d5 | 2014-10-07 21:57:05 +0000 | [diff] [blame] | 379 | // fixs390: consider implementing directReload_S390 |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 380 | ppInstr = (__typeof__(ppInstr)) ppS390Instr; |
| 381 | ppReg = (__typeof__(ppReg)) ppHRegS390; |
| 382 | iselSB = iselSB_S390; |
| 383 | emit = (__typeof__(emit)) emit_S390Instr; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 384 | host_word_type = Ity_I64; |
| 385 | vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 386 | vassert(vta->archinfo_host.endness == VexEndnessBE); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 387 | break; |
| 388 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 389 | case VexArchARM: |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 390 | mode64 = False; |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 391 | getAllocableRegs_ARM ( &n_available_real_regs, |
| 392 | &available_real_regs ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 393 | isMove = (__typeof__(isMove)) isMove_ARMInstr; |
| 394 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_ARMInstr; |
| 395 | mapRegs = (__typeof__(mapRegs)) mapRegs_ARMInstr; |
| 396 | genSpill = (__typeof__(genSpill)) genSpill_ARM; |
| 397 | genReload = (__typeof__(genReload)) genReload_ARM; |
| 398 | ppInstr = (__typeof__(ppInstr)) ppARMInstr; |
| 399 | ppReg = (__typeof__(ppReg)) ppHRegARM; |
| 400 | iselSB = iselSB_ARM; |
| 401 | emit = (__typeof__(emit)) emit_ARMInstr; |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 402 | host_word_type = Ity_I32; |
| 403 | vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 404 | vassert(vta->archinfo_host.endness == VexEndnessLE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 405 | break; |
| 406 | |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 407 | case VexArchARM64: |
| 408 | mode64 = True; |
| 409 | getAllocableRegs_ARM64 ( &n_available_real_regs, |
| 410 | &available_real_regs ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 411 | isMove = (__typeof__(isMove)) isMove_ARM64Instr; |
| 412 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_ARM64Instr; |
| 413 | mapRegs = (__typeof__(mapRegs)) mapRegs_ARM64Instr; |
| 414 | genSpill = (__typeof__(genSpill)) genSpill_ARM64; |
| 415 | genReload = (__typeof__(genReload)) genReload_ARM64; |
| 416 | ppInstr = (__typeof__(ppInstr)) ppARM64Instr; |
| 417 | ppReg = (__typeof__(ppReg)) ppHRegARM64; |
| 418 | iselSB = iselSB_ARM64; |
| 419 | emit = (__typeof__(emit)) emit_ARM64Instr; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 420 | host_word_type = Ity_I64; |
| 421 | vassert(are_valid_hwcaps(VexArchARM64, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 422 | vassert(vta->archinfo_host.endness == VexEndnessLE); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 423 | break; |
| 424 | |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 425 | case VexArchMIPS32: |
| 426 | mode64 = False; |
| 427 | getAllocableRegs_MIPS ( &n_available_real_regs, |
| 428 | &available_real_regs, mode64 ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 429 | isMove = (__typeof__(isMove)) isMove_MIPSInstr; |
| 430 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_MIPSInstr; |
| 431 | mapRegs = (__typeof__(mapRegs)) mapRegs_MIPSInstr; |
| 432 | genSpill = (__typeof__(genSpill)) genSpill_MIPS; |
| 433 | genReload = (__typeof__(genReload)) genReload_MIPS; |
| 434 | ppInstr = (__typeof__(ppInstr)) ppMIPSInstr; |
| 435 | ppReg = (__typeof__(ppReg)) ppHRegMIPS; |
| 436 | iselSB = iselSB_MIPS; |
| 437 | emit = (__typeof__(emit)) emit_MIPSInstr; |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 438 | host_word_type = Ity_I32; |
| 439 | vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 440 | vassert(vta->archinfo_host.endness == VexEndnessLE |
| 441 | || vta->archinfo_host.endness == VexEndnessBE); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 442 | break; |
| 443 | |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 444 | case VexArchMIPS64: |
| 445 | mode64 = True; |
| 446 | getAllocableRegs_MIPS ( &n_available_real_regs, |
| 447 | &available_real_regs, mode64 ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 448 | isMove = (__typeof__(isMove)) isMove_MIPSInstr; |
| 449 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_MIPSInstr; |
| 450 | mapRegs = (__typeof__(mapRegs)) mapRegs_MIPSInstr; |
| 451 | genSpill = (__typeof__(genSpill)) genSpill_MIPS; |
| 452 | genReload = (__typeof__(genReload)) genReload_MIPS; |
| 453 | ppInstr = (__typeof__(ppInstr)) ppMIPSInstr; |
| 454 | ppReg = (__typeof__(ppReg)) ppHRegMIPS; |
| 455 | iselSB = iselSB_MIPS; |
| 456 | emit = (__typeof__(emit)) emit_MIPSInstr; |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 457 | host_word_type = Ity_I64; |
| 458 | vassert(are_valid_hwcaps(VexArchMIPS64, vta->archinfo_host.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 459 | vassert(vta->archinfo_host.endness == VexEndnessLE |
| 460 | || vta->archinfo_host.endness == VexEndnessBE); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 461 | break; |
| 462 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 463 | default: |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 464 | vpanic("LibVEX_Translate: unsupported host insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 465 | } |
| 466 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 467 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 468 | switch (vta->arch_guest) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 469 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 470 | case VexArchX86: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 471 | preciseMemExnsFn = guest_x86_state_requires_precise_mem_exns; |
| 472 | disInstrFn = disInstr_X86; |
| 473 | specHelper = guest_x86_spechelper; |
| 474 | guest_sizeB = sizeof(VexGuestX86State); |
| 475 | guest_word_type = Ity_I32; |
| 476 | guest_layout = &x86guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 477 | offB_CMSTART = offsetof(VexGuestX86State,guest_CMSTART); |
| 478 | offB_CMLEN = offsetof(VexGuestX86State,guest_CMLEN); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 479 | offB_GUEST_IP = offsetof(VexGuestX86State,guest_EIP); |
| 480 | szB_GUEST_IP = sizeof( ((VexGuestX86State*)0)->guest_EIP ); |
| 481 | offB_HOST_EvC_COUNTER = offsetof(VexGuestX86State,host_EvC_COUNTER); |
| 482 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestX86State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 483 | vassert(are_valid_hwcaps(VexArchX86, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 484 | vassert(vta->archinfo_guest.endness == VexEndnessLE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 485 | vassert(0 == sizeof(VexGuestX86State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 486 | vassert(sizeof( ((VexGuestX86State*)0)->guest_CMSTART) == 4); |
| 487 | vassert(sizeof( ((VexGuestX86State*)0)->guest_CMLEN ) == 4); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 488 | vassert(sizeof( ((VexGuestX86State*)0)->guest_NRADDR ) == 4); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 489 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 490 | |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 491 | case VexArchAMD64: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 492 | preciseMemExnsFn = guest_amd64_state_requires_precise_mem_exns; |
| 493 | disInstrFn = disInstr_AMD64; |
| 494 | specHelper = guest_amd64_spechelper; |
| 495 | guest_sizeB = sizeof(VexGuestAMD64State); |
| 496 | guest_word_type = Ity_I64; |
| 497 | guest_layout = &amd64guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 498 | offB_CMSTART = offsetof(VexGuestAMD64State,guest_CMSTART); |
| 499 | offB_CMLEN = offsetof(VexGuestAMD64State,guest_CMLEN); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 500 | offB_GUEST_IP = offsetof(VexGuestAMD64State,guest_RIP); |
| 501 | szB_GUEST_IP = sizeof( ((VexGuestAMD64State*)0)->guest_RIP ); |
| 502 | offB_HOST_EvC_COUNTER = offsetof(VexGuestAMD64State,host_EvC_COUNTER); |
| 503 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestAMD64State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 504 | vassert(are_valid_hwcaps(VexArchAMD64, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 505 | vassert(vta->archinfo_guest.endness == VexEndnessLE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 506 | vassert(0 == sizeof(VexGuestAMD64State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 507 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_CMSTART ) == 8); |
| 508 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_CMLEN ) == 8); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 509 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_NRADDR ) == 8); |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 510 | break; |
| 511 | |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 512 | case VexArchPPC32: |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 513 | preciseMemExnsFn = guest_ppc32_state_requires_precise_mem_exns; |
| 514 | disInstrFn = disInstr_PPC; |
| 515 | specHelper = guest_ppc32_spechelper; |
| 516 | guest_sizeB = sizeof(VexGuestPPC32State); |
| 517 | guest_word_type = Ity_I32; |
| 518 | guest_layout = &ppc32Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 519 | offB_CMSTART = offsetof(VexGuestPPC32State,guest_CMSTART); |
| 520 | offB_CMLEN = offsetof(VexGuestPPC32State,guest_CMLEN); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 521 | offB_GUEST_IP = offsetof(VexGuestPPC32State,guest_CIA); |
| 522 | szB_GUEST_IP = sizeof( ((VexGuestPPC32State*)0)->guest_CIA ); |
| 523 | offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC32State,host_EvC_COUNTER); |
| 524 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC32State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 525 | vassert(are_valid_hwcaps(VexArchPPC32, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 526 | vassert(vta->archinfo_guest.endness == VexEndnessBE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 527 | vassert(0 == sizeof(VexGuestPPC32State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 528 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_CMSTART ) == 4); |
| 529 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_CMLEN ) == 4); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 530 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_NRADDR ) == 4); |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 531 | break; |
| 532 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 533 | case VexArchPPC64: |
sewardj | 9e1cf15 | 2012-04-20 02:18:31 +0000 | [diff] [blame] | 534 | preciseMemExnsFn = guest_ppc64_state_requires_precise_mem_exns; |
| 535 | disInstrFn = disInstr_PPC; |
| 536 | specHelper = guest_ppc64_spechelper; |
| 537 | guest_sizeB = sizeof(VexGuestPPC64State); |
| 538 | guest_word_type = Ity_I64; |
| 539 | guest_layout = &ppc64Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 540 | offB_CMSTART = offsetof(VexGuestPPC64State,guest_CMSTART); |
| 541 | offB_CMLEN = offsetof(VexGuestPPC64State,guest_CMLEN); |
sewardj | 9e1cf15 | 2012-04-20 02:18:31 +0000 | [diff] [blame] | 542 | offB_GUEST_IP = offsetof(VexGuestPPC64State,guest_CIA); |
| 543 | szB_GUEST_IP = sizeof( ((VexGuestPPC64State*)0)->guest_CIA ); |
| 544 | offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC64State,host_EvC_COUNTER); |
| 545 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC64State,host_EvC_FAILADDR); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 546 | vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_guest.hwcaps)); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 547 | vassert(vta->archinfo_guest.endness == VexEndnessBE || |
| 548 | vta->archinfo_guest.endness == VexEndnessLE ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 549 | vassert(0 == sizeof(VexGuestPPC64State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 550 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_CMSTART ) == 8); |
| 551 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_CMLEN ) == 8); |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 552 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR ) == 8); |
| 553 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR_GPR2) == 8); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 554 | break; |
| 555 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 556 | case VexArchS390X: |
| 557 | preciseMemExnsFn = guest_s390x_state_requires_precise_mem_exns; |
| 558 | disInstrFn = disInstr_S390; |
| 559 | specHelper = guest_s390x_spechelper; |
| 560 | guest_sizeB = sizeof(VexGuestS390XState); |
| 561 | guest_word_type = Ity_I64; |
| 562 | guest_layout = &s390xGuest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 563 | offB_CMSTART = offsetof(VexGuestS390XState,guest_CMSTART); |
| 564 | offB_CMLEN = offsetof(VexGuestS390XState,guest_CMLEN); |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 565 | offB_GUEST_IP = offsetof(VexGuestS390XState,guest_IA); |
| 566 | szB_GUEST_IP = sizeof( ((VexGuestS390XState*)0)->guest_IA); |
| 567 | offB_HOST_EvC_COUNTER = offsetof(VexGuestS390XState,host_EvC_COUNTER); |
| 568 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestS390XState,host_EvC_FAILADDR); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 569 | vassert(are_valid_hwcaps(VexArchS390X, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 570 | vassert(vta->archinfo_guest.endness == VexEndnessBE); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 571 | vassert(0 == sizeof(VexGuestS390XState) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 572 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_CMSTART ) == 8); |
| 573 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_CMLEN ) == 8); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 574 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_NRADDR ) == 8); |
| 575 | break; |
| 576 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 577 | case VexArchARM: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 578 | preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns; |
| 579 | disInstrFn = disInstr_ARM; |
| 580 | specHelper = guest_arm_spechelper; |
| 581 | guest_sizeB = sizeof(VexGuestARMState); |
| 582 | guest_word_type = Ity_I32; |
| 583 | guest_layout = &armGuest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 584 | offB_CMSTART = offsetof(VexGuestARMState,guest_CMSTART); |
| 585 | offB_CMLEN = offsetof(VexGuestARMState,guest_CMLEN); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 586 | offB_GUEST_IP = offsetof(VexGuestARMState,guest_R15T); |
| 587 | szB_GUEST_IP = sizeof( ((VexGuestARMState*)0)->guest_R15T ); |
| 588 | offB_HOST_EvC_COUNTER = offsetof(VexGuestARMState,host_EvC_COUNTER); |
| 589 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestARMState,host_EvC_FAILADDR); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 590 | vassert(are_valid_hwcaps(VexArchARM, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 591 | vassert(vta->archinfo_guest.endness == VexEndnessLE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 592 | vassert(0 == sizeof(VexGuestARMState) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 593 | vassert(sizeof( ((VexGuestARMState*)0)->guest_CMSTART) == 4); |
| 594 | vassert(sizeof( ((VexGuestARMState*)0)->guest_CMLEN ) == 4); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 595 | vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4); |
| 596 | break; |
| 597 | |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 598 | case VexArchARM64: |
| 599 | preciseMemExnsFn = guest_arm64_state_requires_precise_mem_exns; |
| 600 | disInstrFn = disInstr_ARM64; |
| 601 | specHelper = guest_arm64_spechelper; |
| 602 | guest_sizeB = sizeof(VexGuestARM64State); |
| 603 | guest_word_type = Ity_I64; |
| 604 | guest_layout = &arm64Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 605 | offB_CMSTART = offsetof(VexGuestARM64State,guest_CMSTART); |
| 606 | offB_CMLEN = offsetof(VexGuestARM64State,guest_CMLEN); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 607 | offB_GUEST_IP = offsetof(VexGuestARM64State,guest_PC); |
| 608 | szB_GUEST_IP = sizeof( ((VexGuestARM64State*)0)->guest_PC ); |
| 609 | offB_HOST_EvC_COUNTER = offsetof(VexGuestARM64State,host_EvC_COUNTER); |
| 610 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestARM64State,host_EvC_FAILADDR); |
| 611 | vassert(are_valid_hwcaps(VexArchARM64, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 612 | vassert(vta->archinfo_guest.endness == VexEndnessLE); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 613 | vassert(0 == sizeof(VexGuestARM64State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 614 | vassert(sizeof( ((VexGuestARM64State*)0)->guest_CMSTART) == 8); |
| 615 | vassert(sizeof( ((VexGuestARM64State*)0)->guest_CMLEN ) == 8); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 616 | vassert(sizeof( ((VexGuestARM64State*)0)->guest_NRADDR ) == 8); |
| 617 | break; |
| 618 | |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 619 | case VexArchMIPS32: |
| 620 | preciseMemExnsFn = guest_mips32_state_requires_precise_mem_exns; |
| 621 | disInstrFn = disInstr_MIPS; |
| 622 | specHelper = guest_mips32_spechelper; |
| 623 | guest_sizeB = sizeof(VexGuestMIPS32State); |
| 624 | guest_word_type = Ity_I32; |
| 625 | guest_layout = &mips32Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 626 | offB_CMSTART = offsetof(VexGuestMIPS32State,guest_CMSTART); |
| 627 | offB_CMLEN = offsetof(VexGuestMIPS32State,guest_CMLEN); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 628 | offB_GUEST_IP = offsetof(VexGuestMIPS32State,guest_PC); |
| 629 | szB_GUEST_IP = sizeof( ((VexGuestMIPS32State*)0)->guest_PC ); |
| 630 | offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS32State,host_EvC_COUNTER); |
| 631 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR); |
| 632 | vassert(are_valid_hwcaps(VexArchMIPS32, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 633 | vassert(vta->archinfo_guest.endness == VexEndnessLE |
| 634 | || vta->archinfo_guest.endness == VexEndnessBE); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 635 | vassert(0 == sizeof(VexGuestMIPS32State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 636 | vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_CMSTART) == 4); |
| 637 | vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_CMLEN ) == 4); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 638 | vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_NRADDR ) == 4); |
| 639 | break; |
| 640 | |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 641 | case VexArchMIPS64: |
| 642 | preciseMemExnsFn = guest_mips64_state_requires_precise_mem_exns; |
| 643 | disInstrFn = disInstr_MIPS; |
| 644 | specHelper = guest_mips64_spechelper; |
| 645 | guest_sizeB = sizeof(VexGuestMIPS64State); |
| 646 | guest_word_type = Ity_I64; |
| 647 | guest_layout = &mips64Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 648 | offB_CMSTART = offsetof(VexGuestMIPS64State,guest_CMSTART); |
| 649 | offB_CMLEN = offsetof(VexGuestMIPS64State,guest_CMLEN); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 650 | offB_GUEST_IP = offsetof(VexGuestMIPS64State,guest_PC); |
| 651 | szB_GUEST_IP = sizeof( ((VexGuestMIPS64State*)0)->guest_PC ); |
| 652 | offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS64State,host_EvC_COUNTER); |
| 653 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS64State,host_EvC_FAILADDR); |
| 654 | vassert(are_valid_hwcaps(VexArchMIPS64, vta->archinfo_guest.hwcaps)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 655 | vassert(vta->archinfo_guest.endness == VexEndnessLE |
| 656 | || vta->archinfo_guest.endness == VexEndnessBE); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 657 | vassert(0 == sizeof(VexGuestMIPS64State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 658 | vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_CMSTART) == 8); |
| 659 | vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_CMLEN ) == 8); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 660 | vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_NRADDR ) == 8); |
| 661 | break; |
| 662 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 663 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 664 | vpanic("LibVEX_Translate: unsupported guest insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 665 | } |
| 666 | |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 667 | /* Set up result struct. */ |
| 668 | VexTranslateResult res; |
sewardj | fadbbe2 | 2012-04-24 11:49:03 +0000 | [diff] [blame] | 669 | res.status = VexTransOK; |
| 670 | res.n_sc_extents = 0; |
| 671 | res.offs_profInc = -1; |
| 672 | res.n_guest_instrs = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 673 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 674 | /* yet more sanity checks ... */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 675 | if (vta->arch_guest == vta->arch_host) { |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 676 | /* doesn't necessarily have to be true, but if it isn't it means |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 677 | we are simulating one flavour of an architecture a different |
| 678 | flavour of the same architecture, which is pretty strange. */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 679 | vassert(vta->archinfo_guest.hwcaps == vta->archinfo_host.hwcaps); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 680 | /* ditto */ |
| 681 | vassert(vta->archinfo_guest.endness == vta->archinfo_host.endness); |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 682 | } |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 683 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 684 | vexAllocSanityCheck(); |
| 685 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 686 | if (vex_traceflags & VEX_TRACE_FE) |
| 687 | vex_printf("\n------------------------" |
| 688 | " Front end " |
| 689 | "------------------------\n\n"); |
| 690 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 691 | irsb = bb_to_IR ( vta->guest_extents, |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 692 | &res.n_sc_extents, |
sewardj | fadbbe2 | 2012-04-24 11:49:03 +0000 | [diff] [blame] | 693 | &res.n_guest_instrs, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 694 | vta->callback_opaque, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 695 | disInstrFn, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 696 | vta->guest_bytes, |
| 697 | vta->guest_bytes_addr, |
| 698 | vta->chase_into_ok, |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 699 | vta->archinfo_host.endness, |
sewardj | 442e51a | 2012-12-06 18:08:04 +0000 | [diff] [blame] | 700 | vta->sigill_diag, |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 701 | vta->arch_guest, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 702 | &vta->archinfo_guest, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 703 | &vta->abiinfo_both, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 704 | guest_word_type, |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 705 | vta->needs_self_check, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 706 | vta->preamble_function, |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 707 | offB_CMSTART, |
| 708 | offB_CMLEN, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 709 | offB_GUEST_IP, |
| 710 | szB_GUEST_IP ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 711 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 712 | vexAllocSanityCheck(); |
| 713 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 714 | if (irsb == NULL) { |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 715 | /* Access failure. */ |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 716 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 717 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 718 | res.status = VexTransAccessFail; return res; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 719 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 720 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 721 | vassert(vta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3); |
| 722 | vassert(vta->guest_extents->base[0] == vta->guest_bytes_addr); |
| 723 | for (i = 0; i < vta->guest_extents->n_used; i++) { |
| 724 | vassert(vta->guest_extents->len[i] < 10000); /* sanity */ |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 725 | } |
| 726 | |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 727 | /* If debugging, show the raw guest bytes for this bb. */ |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 728 | if (0 || (vex_traceflags & VEX_TRACE_FE)) { |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 729 | if (vta->guest_extents->n_used > 1) { |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 730 | vex_printf("can't show code due to extents > 1\n"); |
| 731 | } else { |
| 732 | /* HACK */ |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 733 | const UChar* p = vta->guest_bytes; |
sewardj | 01f8cce | 2009-08-31 08:50:02 +0000 | [diff] [blame] | 734 | UInt sum = 0; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 735 | UInt guest_bytes_read = (UInt)vta->guest_extents->len[0]; |
sewardj | 01f8cce | 2009-08-31 08:50:02 +0000 | [diff] [blame] | 736 | vex_printf("GuestBytes %llx %u ", vta->guest_bytes_addr, |
| 737 | guest_bytes_read ); |
| 738 | for (i = 0; i < guest_bytes_read; i++) { |
| 739 | UInt b = (UInt)p[i]; |
| 740 | vex_printf(" %02x", b ); |
| 741 | sum = (sum << 1) ^ b; |
| 742 | } |
| 743 | vex_printf(" %08x\n\n", sum); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 744 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 745 | } |
| 746 | |
| 747 | /* Sanity check the initial IR. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 748 | sanityCheckIRSB( irsb, "initial IR", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 749 | False/*can be non-flat*/, guest_word_type ); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 750 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 751 | vexAllocSanityCheck(); |
| 752 | |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 753 | /* Clean it up, hopefully a lot. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 754 | irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn, |
sewardj | ec0d9a0 | 2010-08-22 12:54:56 +0000 | [diff] [blame] | 755 | vta->guest_bytes_addr, |
| 756 | vta->arch_guest ); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 757 | sanityCheckIRSB( irsb, "after initial iropt", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 758 | True/*must be flat*/, guest_word_type ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 759 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 760 | if (vex_traceflags & VEX_TRACE_OPT1) { |
| 761 | vex_printf("\n------------------------" |
| 762 | " After pre-instr IR optimisation " |
| 763 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 764 | ppIRSB ( irsb ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 765 | vex_printf("\n"); |
| 766 | } |
| 767 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 768 | vexAllocSanityCheck(); |
| 769 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 770 | /* Get the thing instrumented. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 771 | if (vta->instrument1) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 772 | irsb = vta->instrument1(vta->callback_opaque, |
| 773 | irsb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 774 | vta->guest_extents, |
florian | 5048192 | 2012-10-07 21:58:07 +0000 | [diff] [blame] | 775 | &vta->archinfo_host, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 776 | guest_word_type, host_word_type); |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 777 | vexAllocSanityCheck(); |
| 778 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 779 | if (vta->instrument2) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 780 | irsb = vta->instrument2(vta->callback_opaque, |
| 781 | irsb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 782 | vta->guest_extents, |
florian | 5048192 | 2012-10-07 21:58:07 +0000 | [diff] [blame] | 783 | &vta->archinfo_host, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 784 | guest_word_type, host_word_type); |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 785 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 786 | if (vex_traceflags & VEX_TRACE_INST) { |
| 787 | vex_printf("\n------------------------" |
| 788 | " After instrumentation " |
| 789 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 790 | ppIRSB ( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 791 | vex_printf("\n"); |
| 792 | } |
| 793 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 794 | if (vta->instrument1 || vta->instrument2) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 795 | sanityCheckIRSB( irsb, "after instrumentation", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 796 | True/*must be flat*/, guest_word_type ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 797 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 798 | /* Do a post-instrumentation cleanup pass. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 799 | if (vta->instrument1 || vta->instrument2) { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 800 | do_deadcode_BB( irsb ); |
| 801 | irsb = cprop_BB( irsb ); |
| 802 | do_deadcode_BB( irsb ); |
| 803 | sanityCheckIRSB( irsb, "after post-instrumentation cleanup", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 804 | True/*must be flat*/, guest_word_type ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 805 | } |
| 806 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 807 | vexAllocSanityCheck(); |
| 808 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 809 | if (vex_traceflags & VEX_TRACE_OPT2) { |
| 810 | vex_printf("\n------------------------" |
| 811 | " After post-instr IR optimisation " |
| 812 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 813 | ppIRSB ( irsb ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 814 | vex_printf("\n"); |
| 815 | } |
| 816 | |
sewardj | f9517d0 | 2005-11-28 13:39:37 +0000 | [diff] [blame] | 817 | /* Turn it into virtual-registerised code. Build trees -- this |
| 818 | also throws away any dead bindings. */ |
florian | 62140c1 | 2013-01-20 03:51:04 +0000 | [diff] [blame] | 819 | max_ga = ado_treebuild_BB( irsb, preciseMemExnsFn ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 820 | |
sewardj | be1b6ff | 2007-08-28 06:06:27 +0000 | [diff] [blame] | 821 | if (vta->finaltidy) { |
| 822 | irsb = vta->finaltidy(irsb); |
| 823 | } |
| 824 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 825 | vexAllocSanityCheck(); |
| 826 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 827 | if (vex_traceflags & VEX_TRACE_TREES) { |
| 828 | vex_printf("\n------------------------" |
| 829 | " After tree-building " |
| 830 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 831 | ppIRSB ( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 832 | vex_printf("\n"); |
| 833 | } |
| 834 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 835 | /* HACK */ |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 836 | if (0) { |
| 837 | *(vta->host_bytes_used) = 0; |
| 838 | res.status = VexTransOK; return res; |
| 839 | } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 840 | /* end HACK */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 841 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 842 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 843 | vex_printf("\n------------------------" |
| 844 | " Instruction selection " |
| 845 | "------------------------\n"); |
| 846 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 847 | /* No guest has its IP field at offset zero. If this fails it |
| 848 | means some transformation pass somewhere failed to update/copy |
| 849 | irsb->offsIP properly. */ |
| 850 | vassert(irsb->offsIP >= 16); |
| 851 | |
| 852 | vcode = iselSB ( irsb, vta->arch_host, |
| 853 | &vta->archinfo_host, |
| 854 | &vta->abiinfo_both, |
| 855 | offB_HOST_EvC_COUNTER, |
| 856 | offB_HOST_EvC_FAILADDR, |
| 857 | chainingAllowed, |
| 858 | vta->addProfInc, |
| 859 | max_ga ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 860 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 861 | vexAllocSanityCheck(); |
| 862 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 863 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 864 | vex_printf("\n"); |
| 865 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 866 | if (vex_traceflags & VEX_TRACE_VCODE) { |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 867 | for (i = 0; i < vcode->arr_used; i++) { |
| 868 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 869 | ppInstr(vcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 870 | vex_printf("\n"); |
| 871 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 872 | vex_printf("\n"); |
| 873 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 874 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 875 | /* Register allocate. */ |
| 876 | rcode = doRegisterAllocation ( vcode, available_real_regs, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 877 | n_available_real_regs, |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 878 | isMove, getRegUsage, mapRegs, |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 879 | genSpill, genReload, directReload, |
| 880 | guest_sizeB, |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 881 | ppInstr, ppReg, mode64 ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 882 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 883 | vexAllocSanityCheck(); |
| 884 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 885 | if (vex_traceflags & VEX_TRACE_RCODE) { |
| 886 | vex_printf("\n------------------------" |
| 887 | " Register-allocated code " |
| 888 | "------------------------\n\n"); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 889 | for (i = 0; i < rcode->arr_used; i++) { |
| 890 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 891 | ppInstr(rcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 892 | vex_printf("\n"); |
| 893 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 894 | vex_printf("\n"); |
| 895 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 896 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 897 | /* HACK */ |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 898 | if (0) { |
| 899 | *(vta->host_bytes_used) = 0; |
| 900 | res.status = VexTransOK; return res; |
| 901 | } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 902 | /* end HACK */ |
| 903 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 904 | /* Assemble */ |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 905 | if (vex_traceflags & VEX_TRACE_ASM) { |
| 906 | vex_printf("\n------------------------" |
| 907 | " Assembly " |
| 908 | "------------------------\n\n"); |
| 909 | } |
| 910 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 911 | out_used = 0; /* tracks along the host_bytes array */ |
| 912 | for (i = 0; i < rcode->arr_used; i++) { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 913 | HInstr* hi = rcode->arr[i]; |
| 914 | Bool hi_isProfInc = False; |
| 915 | if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) { |
| 916 | ppInstr(hi, mode64); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 917 | vex_printf("\n"); |
| 918 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 919 | j = emit( &hi_isProfInc, |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 920 | insn_bytes, sizeof insn_bytes, hi, |
| 921 | mode64, vta->archinfo_host.endness, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 922 | vta->disp_cp_chain_me_to_slowEP, |
| 923 | vta->disp_cp_chain_me_to_fastEP, |
| 924 | vta->disp_cp_xindir, |
| 925 | vta->disp_cp_xassisted ); |
| 926 | if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 927 | for (k = 0; k < j; k++) |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 928 | if (insn_bytes[k] < 16) |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 929 | vex_printf("0%x ", (UInt)insn_bytes[k]); |
| 930 | else |
| 931 | vex_printf("%x ", (UInt)insn_bytes[k]); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 932 | vex_printf("\n\n"); |
| 933 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 934 | if (UNLIKELY(out_used + j > vta->host_bytes_size)) { |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 935 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 936 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 937 | res.status = VexTransOutputFull; |
| 938 | return res; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 939 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 940 | if (UNLIKELY(hi_isProfInc)) { |
| 941 | vassert(vta->addProfInc); /* else where did it come from? */ |
| 942 | vassert(res.offs_profInc == -1); /* there can be only one (tm) */ |
| 943 | vassert(out_used >= 0); |
| 944 | res.offs_profInc = out_used; |
| 945 | } |
| 946 | { UChar* dst = &vta->host_bytes[out_used]; |
| 947 | for (k = 0; k < j; k++) { |
| 948 | dst[k] = insn_bytes[k]; |
| 949 | } |
| 950 | out_used += j; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 951 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 952 | vassert(out_used <= vta->host_bytes_size); |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 953 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 954 | *(vta->host_bytes_used) = out_used; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 955 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 956 | vexAllocSanityCheck(); |
| 957 | |
| 958 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 959 | |
sewardj | 65ea17e | 2012-12-28 09:01:59 +0000 | [diff] [blame] | 960 | if (vex_traceflags) { |
| 961 | /* Print the expansion ratio for this SB. */ |
| 962 | j = 0; /* total guest bytes */ |
| 963 | for (i = 0; i < vta->guest_extents->n_used; i++) { |
| 964 | j += vta->guest_extents->len[i]; |
| 965 | } |
| 966 | if (1) vex_printf("VexExpansionRatio %d %d %d :10\n\n", |
| 967 | j, out_used, (10 * out_used) / (j == 0 ? 1 : j)); |
| 968 | } |
| 969 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 970 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 971 | res.status = VexTransOK; |
| 972 | return res; |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 973 | } |
| 974 | |
| 975 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 976 | /* --------- Chain/Unchain XDirects. --------- */ |
| 977 | |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 978 | VexInvalRange LibVEX_Chain ( VexArch arch_host, |
| 979 | VexEndness endness_host, |
| 980 | void* place_to_chain, |
| 981 | const void* disp_cp_chain_me_EXPECTED, |
| 982 | const void* place_to_jump_to ) |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 983 | { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 984 | switch (arch_host) { |
| 985 | case VexArchX86: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 986 | return chainXDirect_X86(endness_host, |
| 987 | place_to_chain, |
| 988 | disp_cp_chain_me_EXPECTED, |
| 989 | place_to_jump_to); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 990 | case VexArchAMD64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 991 | return chainXDirect_AMD64(endness_host, |
| 992 | place_to_chain, |
| 993 | disp_cp_chain_me_EXPECTED, |
| 994 | place_to_jump_to); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 995 | case VexArchARM: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 996 | return chainXDirect_ARM(endness_host, |
| 997 | place_to_chain, |
| 998 | disp_cp_chain_me_EXPECTED, |
| 999 | place_to_jump_to); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1000 | case VexArchARM64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1001 | return chainXDirect_ARM64(endness_host, |
| 1002 | place_to_chain, |
| 1003 | disp_cp_chain_me_EXPECTED, |
| 1004 | place_to_jump_to); |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 1005 | case VexArchS390X: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1006 | return chainXDirect_S390(endness_host, |
| 1007 | place_to_chain, |
| 1008 | disp_cp_chain_me_EXPECTED, |
| 1009 | place_to_jump_to); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1010 | case VexArchPPC32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1011 | return chainXDirect_PPC(endness_host, |
| 1012 | place_to_chain, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1013 | disp_cp_chain_me_EXPECTED, |
| 1014 | place_to_jump_to, False/*!mode64*/); |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1015 | case VexArchPPC64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1016 | return chainXDirect_PPC(endness_host, |
| 1017 | place_to_chain, |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1018 | disp_cp_chain_me_EXPECTED, |
| 1019 | place_to_jump_to, True/*mode64*/); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1020 | case VexArchMIPS32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1021 | return chainXDirect_MIPS(endness_host, |
| 1022 | place_to_chain, |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1023 | disp_cp_chain_me_EXPECTED, |
| 1024 | place_to_jump_to, False/*!mode64*/); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1025 | case VexArchMIPS64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1026 | return chainXDirect_MIPS(endness_host, |
| 1027 | place_to_chain, |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1028 | disp_cp_chain_me_EXPECTED, |
| 1029 | place_to_jump_to, True/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1030 | default: |
| 1031 | vassert(0); |
| 1032 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1033 | } |
| 1034 | |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1035 | VexInvalRange LibVEX_UnChain ( VexArch arch_host, |
| 1036 | VexEndness endness_host, |
| 1037 | void* place_to_unchain, |
| 1038 | const void* place_to_jump_to_EXPECTED, |
| 1039 | const void* disp_cp_chain_me ) |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1040 | { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1041 | switch (arch_host) { |
| 1042 | case VexArchX86: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1043 | return unchainXDirect_X86(endness_host, |
| 1044 | place_to_unchain, |
| 1045 | place_to_jump_to_EXPECTED, |
| 1046 | disp_cp_chain_me); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1047 | case VexArchAMD64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1048 | return unchainXDirect_AMD64(endness_host, |
| 1049 | place_to_unchain, |
| 1050 | place_to_jump_to_EXPECTED, |
| 1051 | disp_cp_chain_me); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1052 | case VexArchARM: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1053 | return unchainXDirect_ARM(endness_host, |
| 1054 | place_to_unchain, |
| 1055 | place_to_jump_to_EXPECTED, |
| 1056 | disp_cp_chain_me); |
sewardj | c6acaa4 | 2014-02-19 17:42:59 +0000 | [diff] [blame] | 1057 | case VexArchARM64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1058 | return unchainXDirect_ARM64(endness_host, |
| 1059 | place_to_unchain, |
| 1060 | place_to_jump_to_EXPECTED, |
| 1061 | disp_cp_chain_me); |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 1062 | case VexArchS390X: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1063 | return unchainXDirect_S390(endness_host, |
| 1064 | place_to_unchain, |
| 1065 | place_to_jump_to_EXPECTED, |
| 1066 | disp_cp_chain_me); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1067 | case VexArchPPC32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1068 | return unchainXDirect_PPC(endness_host, |
| 1069 | place_to_unchain, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1070 | place_to_jump_to_EXPECTED, |
| 1071 | disp_cp_chain_me, False/*!mode64*/); |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1072 | case VexArchPPC64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1073 | return unchainXDirect_PPC(endness_host, |
| 1074 | place_to_unchain, |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1075 | place_to_jump_to_EXPECTED, |
| 1076 | disp_cp_chain_me, True/*mode64*/); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1077 | case VexArchMIPS32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1078 | return unchainXDirect_MIPS(endness_host, |
| 1079 | place_to_unchain, |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1080 | place_to_jump_to_EXPECTED, |
| 1081 | disp_cp_chain_me, False/*!mode64*/); |
| 1082 | case VexArchMIPS64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1083 | return unchainXDirect_MIPS(endness_host, |
| 1084 | place_to_unchain, |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1085 | place_to_jump_to_EXPECTED, |
| 1086 | disp_cp_chain_me, True/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1087 | default: |
| 1088 | vassert(0); |
| 1089 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1090 | } |
| 1091 | |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1092 | Int LibVEX_evCheckSzB ( VexArch arch_host, |
| 1093 | VexEndness endness_host ) |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1094 | { |
| 1095 | static Int cached = 0; /* DO NOT MAKE NON-STATIC */ |
| 1096 | if (UNLIKELY(cached == 0)) { |
| 1097 | switch (arch_host) { |
| 1098 | case VexArchX86: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1099 | cached = evCheckSzB_X86(endness_host); break; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1100 | case VexArchAMD64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1101 | cached = evCheckSzB_AMD64(endness_host); break; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1102 | case VexArchARM: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1103 | cached = evCheckSzB_ARM(endness_host); break; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1104 | case VexArchARM64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1105 | cached = evCheckSzB_ARM64(endness_host); break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 1106 | case VexArchS390X: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1107 | cached = evCheckSzB_S390(endness_host); break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1108 | case VexArchPPC32: |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1109 | case VexArchPPC64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1110 | cached = evCheckSzB_PPC(endness_host); break; |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1111 | case VexArchMIPS32: |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1112 | case VexArchMIPS64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1113 | cached = evCheckSzB_MIPS(endness_host); break; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1114 | default: |
| 1115 | vassert(0); |
| 1116 | } |
| 1117 | } |
| 1118 | return cached; |
| 1119 | } |
| 1120 | |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1121 | VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host, |
| 1122 | VexEndness endness_host, |
| 1123 | void* place_to_patch, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1124 | const ULong* location_of_counter ) |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1125 | { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1126 | switch (arch_host) { |
| 1127 | case VexArchX86: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1128 | return patchProfInc_X86(endness_host, place_to_patch, |
| 1129 | location_of_counter); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1130 | case VexArchAMD64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1131 | return patchProfInc_AMD64(endness_host, place_to_patch, |
| 1132 | location_of_counter); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1133 | case VexArchARM: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1134 | return patchProfInc_ARM(endness_host, place_to_patch, |
| 1135 | location_of_counter); |
sewardj | 0ad37a9 | 2014-08-29 21:58:03 +0000 | [diff] [blame] | 1136 | case VexArchARM64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1137 | return patchProfInc_ARM64(endness_host, place_to_patch, |
| 1138 | location_of_counter); |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 1139 | case VexArchS390X: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1140 | return patchProfInc_S390(endness_host, place_to_patch, |
| 1141 | location_of_counter); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1142 | case VexArchPPC32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1143 | return patchProfInc_PPC(endness_host, place_to_patch, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1144 | location_of_counter, False/*!mode64*/); |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1145 | case VexArchPPC64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1146 | return patchProfInc_PPC(endness_host, place_to_patch, |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1147 | location_of_counter, True/*mode64*/); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1148 | case VexArchMIPS32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1149 | return patchProfInc_MIPS(endness_host, place_to_patch, |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1150 | location_of_counter, False/*!mode64*/); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1151 | case VexArchMIPS64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1152 | return patchProfInc_MIPS(endness_host, place_to_patch, |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1153 | location_of_counter, True/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1154 | default: |
| 1155 | vassert(0); |
| 1156 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1157 | } |
| 1158 | |
| 1159 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1160 | /* --------- Emulation warnings. --------- */ |
| 1161 | |
florian | 1ff4756 | 2012-10-21 02:09:51 +0000 | [diff] [blame] | 1162 | const HChar* LibVEX_EmNote_string ( VexEmNote ew ) |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1163 | { |
| 1164 | switch (ew) { |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 1165 | case EmNote_NONE: |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1166 | return "none"; |
| 1167 | case EmWarn_X86_x87exns: |
| 1168 | return "Unmasking x87 FP exceptions"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1169 | case EmWarn_X86_x87precision: |
| 1170 | return "Selection of non-80-bit x87 FP precision"; |
| 1171 | case EmWarn_X86_sseExns: |
sewardj | 5edfc26 | 2004-12-15 12:13:52 +0000 | [diff] [blame] | 1172 | return "Unmasking SSE FP exceptions"; |
| 1173 | case EmWarn_X86_fz: |
| 1174 | return "Setting %mxcsr.fz (SSE flush-underflows-to-zero mode)"; |
| 1175 | case EmWarn_X86_daz: |
| 1176 | return "Setting %mxcsr.daz (SSE treat-denormals-as-zero mode)"; |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 1177 | case EmWarn_X86_acFlag: |
| 1178 | return "Setting %eflags.ac (setting noted but ignored)"; |
sewardj | 9dd9cf1 | 2006-01-20 14:13:55 +0000 | [diff] [blame] | 1179 | case EmWarn_PPCexns: |
| 1180 | return "Unmasking PPC32/64 FP exceptions"; |
| 1181 | case EmWarn_PPC64_redir_overflow: |
| 1182 | return "PPC64 function redirection stack overflow"; |
| 1183 | case EmWarn_PPC64_redir_underflow: |
| 1184 | return "PPC64 function redirection stack underflow"; |
florian | 4b8efad | 2012-09-02 18:07:08 +0000 | [diff] [blame] | 1185 | case EmWarn_S390X_fpext_rounding: |
| 1186 | return "The specified rounding mode cannot be supported. That\n" |
florian | 2a4de0b | 2014-12-05 18:28:29 +0000 | [diff] [blame] | 1187 | " feature requires the floating point extension facility\n" |
florian | 4b8efad | 2012-09-02 18:07:08 +0000 | [diff] [blame] | 1188 | " which is not available on this host. Continuing using\n" |
| 1189 | " the rounding mode from FPC. Results may differ!"; |
florian | f0fa1be | 2012-09-18 20:24:38 +0000 | [diff] [blame] | 1190 | case EmWarn_S390X_invalid_rounding: |
| 1191 | return "The specified rounding mode is invalid.\n" |
| 1192 | " Continuing using 'round to nearest'. Results may differ!"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1193 | case EmFail_S390X_stfle: |
florian | 4e0083e | 2012-08-26 03:41:56 +0000 | [diff] [blame] | 1194 | return "Instruction stfle is not supported on this host"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1195 | case EmFail_S390X_stckf: |
florian | c5c669b | 2012-08-26 14:32:28 +0000 | [diff] [blame] | 1196 | return "Instruction stckf is not supported on this host"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1197 | case EmFail_S390X_ecag: |
florian | 8c88cb6 | 2012-08-26 18:58:13 +0000 | [diff] [blame] | 1198 | return "Instruction ecag is not supported on this host"; |
florian | ad00ea9 | 2014-12-05 18:55:39 +0000 | [diff] [blame^] | 1199 | case EmFail_S390X_pfpo: |
| 1200 | return "Instruction pfpo is not supported on this host"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1201 | case EmFail_S390X_fpext: |
| 1202 | return "Encountered an instruction that requires the floating " |
| 1203 | "point extension facility.\n" |
| 1204 | " That facility is not available on this host"; |
florian | 78d5ef7 | 2013-05-11 15:02:58 +0000 | [diff] [blame] | 1205 | case EmFail_S390X_invalid_PFPO_rounding_mode: |
florian | 2a4de0b | 2014-12-05 18:28:29 +0000 | [diff] [blame] | 1206 | return "The rounding mode in GPR 0 for the PFPO instruction" |
florian | 78d5ef7 | 2013-05-11 15:02:58 +0000 | [diff] [blame] | 1207 | " is invalid"; |
| 1208 | case EmFail_S390X_invalid_PFPO_function: |
florian | 2a4de0b | 2014-12-05 18:28:29 +0000 | [diff] [blame] | 1209 | return "The function code in GPR 0 for the PFPO instruction" |
florian | 78d5ef7 | 2013-05-11 15:02:58 +0000 | [diff] [blame] | 1210 | " is invalid"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1211 | default: |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 1212 | vpanic("LibVEX_EmNote_string: unknown warning"); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1213 | } |
| 1214 | } |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1215 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1216 | /* ------------------ Arch/HwCaps stuff. ------------------ */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1217 | |
| 1218 | const HChar* LibVEX_ppVexArch ( VexArch arch ) |
| 1219 | { |
| 1220 | switch (arch) { |
| 1221 | case VexArch_INVALID: return "INVALID"; |
| 1222 | case VexArchX86: return "X86"; |
| 1223 | case VexArchAMD64: return "AMD64"; |
| 1224 | case VexArchARM: return "ARM"; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1225 | case VexArchARM64: return "ARM64"; |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 1226 | case VexArchPPC32: return "PPC32"; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1227 | case VexArchPPC64: return "PPC64"; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1228 | case VexArchS390X: return "S390X"; |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1229 | case VexArchMIPS32: return "MIPS32"; |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1230 | case VexArchMIPS64: return "MIPS64"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1231 | default: return "VexArch???"; |
| 1232 | } |
| 1233 | } |
| 1234 | |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1235 | const HChar* LibVEX_ppVexEndness ( VexEndness endness ) |
| 1236 | { |
| 1237 | switch (endness) { |
| 1238 | case VexEndness_INVALID: return "INVALID"; |
| 1239 | case VexEndnessLE: return "LittleEndian"; |
| 1240 | case VexEndnessBE: return "BigEndian"; |
| 1241 | default: return "VexEndness???"; |
| 1242 | } |
| 1243 | } |
| 1244 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1245 | const HChar* LibVEX_ppVexHwCaps ( VexArch arch, UInt hwcaps ) |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1246 | { |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1247 | const HChar* str = show_hwcaps(arch,hwcaps); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1248 | return str ? str : "INVALID"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1249 | } |
| 1250 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1251 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 1252 | /* Write default settings info *vai. */ |
| 1253 | void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ) |
| 1254 | { |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 1255 | vex_bzero(vai, sizeof(*vai)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1256 | vai->hwcaps = 0; |
| 1257 | vai->endness = VexEndness_INVALID; |
| 1258 | vai->ppc_icache_line_szB = 0; |
| 1259 | vai->ppc_dcbz_szB = 0; |
| 1260 | vai->ppc_dcbzl_szB = 0; |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 1261 | vai->arm64_dMinLine_lg2_szB = 0; |
| 1262 | vai->arm64_iMinLine_lg2_szB = 0; |
florian | f192a39 | 2012-10-07 19:44:40 +0000 | [diff] [blame] | 1263 | vai->hwcache_info.num_levels = 0; |
| 1264 | vai->hwcache_info.num_caches = 0; |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 1265 | vai->hwcache_info.caches = NULL; |
florian | f192a39 | 2012-10-07 19:44:40 +0000 | [diff] [blame] | 1266 | vai->hwcache_info.icaches_maintain_coherence = True; // whatever |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 1267 | } |
| 1268 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1269 | /* Write default settings info *vbi. */ |
| 1270 | void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi ) |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1271 | { |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 1272 | vex_bzero(vbi, sizeof(*vbi)); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1273 | vbi->guest_stack_redzone_size = 0; |
sewardj | 2e28ac4 | 2008-12-04 00:05:12 +0000 | [diff] [blame] | 1274 | vbi->guest_amd64_assume_fs_is_zero = False; |
| 1275 | vbi->guest_amd64_assume_gs_is_0x60 = False; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1276 | vbi->guest_ppc_zap_RZ_at_blr = False; |
| 1277 | vbi->guest_ppc_zap_RZ_at_bl = NULL; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1278 | vbi->host_ppc_calls_use_fndescrs = False; |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1279 | } |
| 1280 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 1281 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1282 | /* Return a string showing the hwcaps in a nice way. The string will |
| 1283 | be NULL for invalid combinations of flags, so these functions also |
| 1284 | serve as a way to validate hwcaps values. */ |
| 1285 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1286 | static const HChar* show_hwcaps_x86 ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1287 | { |
mjw | 6c65c12 | 2013-08-27 10:19:03 +0000 | [diff] [blame] | 1288 | /* Monotonic, LZCNT > SSE3 > SSE2 > SSE1 > MMXEXT > baseline. */ |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1289 | switch (hwcaps) { |
| 1290 | case 0: |
| 1291 | return "x86-sse0"; |
mjw | 6c65c12 | 2013-08-27 10:19:03 +0000 | [diff] [blame] | 1292 | case VEX_HWCAPS_X86_MMXEXT: |
| 1293 | return "x86-mmxext"; |
| 1294 | case VEX_HWCAPS_X86_MMXEXT | VEX_HWCAPS_X86_SSE1: |
| 1295 | return "x86-mmxext-sse1"; |
| 1296 | case VEX_HWCAPS_X86_MMXEXT | VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2: |
| 1297 | return "x86-mmxext-sse1-sse2"; |
| 1298 | case VEX_HWCAPS_X86_MMXEXT | VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1299 | | VEX_HWCAPS_X86_LZCNT: |
mjw | 6c65c12 | 2013-08-27 10:19:03 +0000 | [diff] [blame] | 1300 | return "x86-mmxext-sse1-sse2-lzcnt"; |
| 1301 | case VEX_HWCAPS_X86_MMXEXT | VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1302 | | VEX_HWCAPS_X86_SSE3: |
mjw | 6c65c12 | 2013-08-27 10:19:03 +0000 | [diff] [blame] | 1303 | return "x86-mmxext-sse1-sse2-sse3"; |
| 1304 | case VEX_HWCAPS_X86_MMXEXT | VEX_HWCAPS_X86_SSE1 | VEX_HWCAPS_X86_SSE2 |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1305 | | VEX_HWCAPS_X86_SSE3 | VEX_HWCAPS_X86_LZCNT: |
mjw | 6c65c12 | 2013-08-27 10:19:03 +0000 | [diff] [blame] | 1306 | return "x86-mmxext-sse1-sse2-sse3-lzcnt"; |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1307 | default: |
| 1308 | return NULL; |
| 1309 | } |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1310 | } |
| 1311 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1312 | static const HChar* show_hwcaps_amd64 ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1313 | { |
sewardj | e9d8a26 | 2009-07-01 08:06:34 +0000 | [diff] [blame] | 1314 | /* SSE3 and CX16 are orthogonal and > baseline, although we really |
| 1315 | don't expect to come across anything which can do SSE3 but can't |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1316 | do CX16. Still, we can handle that case. LZCNT is similarly |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1317 | orthogonal. */ |
| 1318 | |
| 1319 | /* Throw out obviously stupid cases: */ |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1320 | Bool have_sse3 = (hwcaps & VEX_HWCAPS_AMD64_SSE3) != 0; |
| 1321 | Bool have_avx = (hwcaps & VEX_HWCAPS_AMD64_AVX) != 0; |
sewardj | cc3d219 | 2013-03-27 11:37:33 +0000 | [diff] [blame] | 1322 | Bool have_bmi = (hwcaps & VEX_HWCAPS_AMD64_BMI) != 0; |
| 1323 | Bool have_avx2 = (hwcaps & VEX_HWCAPS_AMD64_AVX2) != 0; |
| 1324 | /* AVX without SSE3 */ |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1325 | if (have_avx && !have_sse3) |
| 1326 | return NULL; |
sewardj | cc3d219 | 2013-03-27 11:37:33 +0000 | [diff] [blame] | 1327 | /* AVX2 or BMI without AVX */ |
| 1328 | if ((have_avx2 || have_bmi) && !have_avx) |
| 1329 | return NULL; |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1330 | |
| 1331 | /* This isn't threadsafe. We might need to fix it at some point. */ |
| 1332 | static HChar buf[100] = { 0 }; |
| 1333 | if (buf[0] != 0) return buf; /* already constructed */ |
| 1334 | |
| 1335 | vex_bzero(buf, sizeof(buf)); |
| 1336 | |
| 1337 | HChar* p = &buf[0]; |
| 1338 | |
| 1339 | p = p + vex_sprintf(p, "%s", "amd64"); |
| 1340 | if (hwcaps == 0) { |
| 1341 | /* special-case the baseline case */ |
| 1342 | p = p + vex_sprintf(p, "%s", "-sse2"); |
| 1343 | goto out; |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1344 | } |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1345 | if (hwcaps & VEX_HWCAPS_AMD64_CX16) { |
| 1346 | p = p + vex_sprintf(p, "%s", "-cx16"); |
| 1347 | } |
| 1348 | if (hwcaps & VEX_HWCAPS_AMD64_LZCNT) { |
| 1349 | p = p + vex_sprintf(p, "%s", "-lzcnt"); |
| 1350 | } |
| 1351 | if (hwcaps & VEX_HWCAPS_AMD64_RDTSCP) { |
| 1352 | p = p + vex_sprintf(p, "%s", "-rdtscp"); |
| 1353 | } |
| 1354 | if (hwcaps & VEX_HWCAPS_AMD64_SSE3) { |
| 1355 | p = p + vex_sprintf(p, "%s", "-sse3"); |
| 1356 | } |
| 1357 | if (hwcaps & VEX_HWCAPS_AMD64_AVX) { |
| 1358 | p = p + vex_sprintf(p, "%s", "-avx"); |
| 1359 | } |
sewardj | cc3d219 | 2013-03-27 11:37:33 +0000 | [diff] [blame] | 1360 | if (hwcaps & VEX_HWCAPS_AMD64_AVX2) { |
| 1361 | p = p + vex_sprintf(p, "%s", "-avx2"); |
| 1362 | } |
| 1363 | if (hwcaps & VEX_HWCAPS_AMD64_BMI) { |
| 1364 | p = p + vex_sprintf(p, "%s", "-bmi"); |
| 1365 | } |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1366 | |
| 1367 | out: |
| 1368 | vassert(buf[sizeof(buf)-1] == 0); |
| 1369 | return buf; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1370 | } |
| 1371 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1372 | static const HChar* show_hwcaps_ppc32 ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1373 | { |
| 1374 | /* Monotonic with complications. Basically V > F > baseline, |
| 1375 | but once you have F then you can have FX or GX too. */ |
| 1376 | const UInt F = VEX_HWCAPS_PPC32_F; |
| 1377 | const UInt V = VEX_HWCAPS_PPC32_V; |
| 1378 | const UInt FX = VEX_HWCAPS_PPC32_FX; |
| 1379 | const UInt GX = VEX_HWCAPS_PPC32_GX; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1380 | const UInt VX = VEX_HWCAPS_PPC32_VX; |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 1381 | const UInt DFP = VEX_HWCAPS_PPC32_DFP; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 1382 | const UInt ISA2_07 = VEX_HWCAPS_PPC32_ISA2_07; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1383 | UInt c = hwcaps; |
| 1384 | if (c == 0) return "ppc32-int"; |
| 1385 | if (c == F) return "ppc32-int-flt"; |
| 1386 | if (c == (F|FX)) return "ppc32-int-flt-FX"; |
| 1387 | if (c == (F|GX)) return "ppc32-int-flt-GX"; |
| 1388 | if (c == (F|FX|GX)) return "ppc32-int-flt-FX-GX"; |
| 1389 | if (c == (F|V)) return "ppc32-int-flt-vmx"; |
| 1390 | if (c == (F|V|FX)) return "ppc32-int-flt-vmx-FX"; |
| 1391 | if (c == (F|V|GX)) return "ppc32-int-flt-vmx-GX"; |
| 1392 | if (c == (F|V|FX|GX)) return "ppc32-int-flt-vmx-FX-GX"; |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 1393 | if (c == (F|V|FX|GX|DFP)) return "ppc32-int-flt-vmx-FX-GX-DFP"; |
| 1394 | if (c == (F|V|FX|GX|VX|DFP)) return "ppc32-int-flt-vmx-FX-GX-VX-DFP"; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 1395 | if (c == (F|V|FX|GX|VX|DFP|ISA2_07)) |
| 1396 | return "ppc32-int-flt-vmx-FX-GX-VX-DFP-ISA2_07"; |
| 1397 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1398 | return NULL; |
| 1399 | } |
| 1400 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1401 | static const HChar* show_hwcaps_ppc64 ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1402 | { |
| 1403 | /* Monotonic with complications. Basically V > baseline(==F), |
| 1404 | but once you have F then you can have FX or GX too. */ |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 1405 | const UInt V = VEX_HWCAPS_PPC64_V; |
| 1406 | const UInt FX = VEX_HWCAPS_PPC64_FX; |
| 1407 | const UInt GX = VEX_HWCAPS_PPC64_GX; |
sewardj | 66d5ef2 | 2011-04-15 11:55:00 +0000 | [diff] [blame] | 1408 | const UInt VX = VEX_HWCAPS_PPC64_VX; |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 1409 | const UInt DFP = VEX_HWCAPS_PPC64_DFP; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 1410 | const UInt ISA2_07 = VEX_HWCAPS_PPC64_ISA2_07; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1411 | UInt c = hwcaps; |
| 1412 | if (c == 0) return "ppc64-int-flt"; |
| 1413 | if (c == FX) return "ppc64-int-flt-FX"; |
| 1414 | if (c == GX) return "ppc64-int-flt-GX"; |
| 1415 | if (c == (FX|GX)) return "ppc64-int-flt-FX-GX"; |
| 1416 | if (c == V) return "ppc64-int-flt-vmx"; |
| 1417 | if (c == (V|FX)) return "ppc64-int-flt-vmx-FX"; |
| 1418 | if (c == (V|GX)) return "ppc64-int-flt-vmx-GX"; |
| 1419 | if (c == (V|FX|GX)) return "ppc64-int-flt-vmx-FX-GX"; |
sewardj | c66d6fa | 2012-04-02 21:24:12 +0000 | [diff] [blame] | 1420 | if (c == (V|FX|GX|DFP)) return "ppc64-int-flt-vmx-FX-GX-DFP"; |
| 1421 | if (c == (V|FX|GX|VX|DFP)) return "ppc64-int-flt-vmx-FX-GX-VX-DFP"; |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 1422 | if (c == (V|FX|GX|VX|DFP|ISA2_07)) |
| 1423 | return "ppc64-int-flt-vmx-FX-GX-VX-DFP-ISA2_07"; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1424 | return NULL; |
| 1425 | } |
| 1426 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1427 | static const HChar* show_hwcaps_arm ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1428 | { |
sewardj | ec0d9a0 | 2010-08-22 12:54:56 +0000 | [diff] [blame] | 1429 | Bool N = ((hwcaps & VEX_HWCAPS_ARM_NEON) != 0); |
| 1430 | Bool vfp = ((hwcaps & (VEX_HWCAPS_ARM_VFP | |
| 1431 | VEX_HWCAPS_ARM_VFP2 | VEX_HWCAPS_ARM_VFP3)) != 0); |
| 1432 | switch (VEX_ARM_ARCHLEVEL(hwcaps)) { |
| 1433 | case 5: |
| 1434 | if (N) |
| 1435 | return NULL; |
| 1436 | if (vfp) |
| 1437 | return "ARMv5-vfp"; |
| 1438 | else |
| 1439 | return "ARMv5"; |
| 1440 | return NULL; |
| 1441 | case 6: |
| 1442 | if (N) |
| 1443 | return NULL; |
| 1444 | if (vfp) |
| 1445 | return "ARMv6-vfp"; |
| 1446 | else |
| 1447 | return "ARMv6"; |
| 1448 | return NULL; |
| 1449 | case 7: |
| 1450 | if (vfp) { |
| 1451 | if (N) |
| 1452 | return "ARMv7-vfp-neon"; |
| 1453 | else |
| 1454 | return "ARMv7-vfp"; |
| 1455 | } else { |
| 1456 | if (N) |
| 1457 | return "ARMv7-neon"; |
| 1458 | else |
| 1459 | return "ARMv7"; |
| 1460 | } |
| 1461 | default: |
| 1462 | return NULL; |
| 1463 | } |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1464 | return NULL; |
| 1465 | } |
| 1466 | |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1467 | static const HChar* show_hwcaps_arm64 ( UInt hwcaps ) |
| 1468 | { |
| 1469 | /* Since there are no variants, just insist that hwcaps is zero, |
| 1470 | and declare it invalid otherwise. */ |
| 1471 | if (hwcaps == 0) |
| 1472 | return "baseline"; |
| 1473 | return NULL; |
| 1474 | } |
| 1475 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1476 | static const HChar* show_hwcaps_s390x ( UInt hwcaps ) |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1477 | { |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1478 | static const HChar prefix[] = "s390x"; |
florian | 9061eb3 | 2012-12-09 17:53:45 +0000 | [diff] [blame] | 1479 | static const struct { |
| 1480 | UInt hwcaps_bit; |
| 1481 | HChar name[6]; |
| 1482 | } hwcaps_list[] = { |
| 1483 | { VEX_HWCAPS_S390X_LDISP, "ldisp" }, |
| 1484 | { VEX_HWCAPS_S390X_EIMM, "eimm" }, |
| 1485 | { VEX_HWCAPS_S390X_GIE, "gie" }, |
| 1486 | { VEX_HWCAPS_S390X_DFP, "dfp" }, |
| 1487 | { VEX_HWCAPS_S390X_FGX, "fgx" }, |
| 1488 | { VEX_HWCAPS_S390X_STFLE, "stfle" }, |
| 1489 | { VEX_HWCAPS_S390X_ETF2, "etf2" }, |
| 1490 | { VEX_HWCAPS_S390X_ETF3, "etf3" }, |
| 1491 | { VEX_HWCAPS_S390X_STCKF, "stckf" }, |
| 1492 | { VEX_HWCAPS_S390X_FPEXT, "fpext" }, |
| 1493 | { VEX_HWCAPS_S390X_LSC, "lsc" }, |
florian | 78d5ef7 | 2013-05-11 15:02:58 +0000 | [diff] [blame] | 1494 | { VEX_HWCAPS_S390X_PFPO, "pfpo" }, |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1495 | }; |
florian | 9061eb3 | 2012-12-09 17:53:45 +0000 | [diff] [blame] | 1496 | #define NUM_HWCAPS (sizeof hwcaps_list / sizeof hwcaps_list[0]) |
| 1497 | static HChar buf[sizeof prefix + |
| 1498 | NUM_HWCAPS * (sizeof hwcaps_list[0].name + 1) + |
| 1499 | 1]; // '\0' |
| 1500 | HChar *p; |
| 1501 | UInt i; |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1502 | |
| 1503 | if (buf[0] != '\0') return buf; /* already constructed */ |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1504 | |
sewardj | 652b56a | 2011-04-13 15:38:17 +0000 | [diff] [blame] | 1505 | hwcaps = VEX_HWCAPS_S390X(hwcaps); |
| 1506 | |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1507 | p = buf + vex_sprintf(buf, "%s", prefix); |
florian | 9061eb3 | 2012-12-09 17:53:45 +0000 | [diff] [blame] | 1508 | for (i = 0 ; i < NUM_HWCAPS; ++i) { |
| 1509 | if (hwcaps & hwcaps_list[i].hwcaps_bit) |
| 1510 | p = p + vex_sprintf(p, "-%s", hwcaps_list[i].name); |
| 1511 | } |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1512 | |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1513 | /* If there are no facilities, add "zarch" */ |
| 1514 | if (hwcaps == 0) |
| 1515 | vex_sprintf(p, "-%s", "zarch"); |
| 1516 | |
| 1517 | return buf; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1518 | } |
| 1519 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1520 | static const HChar* show_hwcaps_mips32 ( UInt hwcaps ) |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1521 | { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1522 | /* MIPS baseline. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1523 | if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_MIPS) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1524 | /* MIPS baseline with dspr2. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1525 | if (VEX_MIPS_PROC_DSP2(hwcaps)) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1526 | return "MIPS-baseline-dspr2"; |
| 1527 | } |
| 1528 | /* MIPS baseline with dsp. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1529 | if (VEX_MIPS_PROC_DSP(hwcaps)) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1530 | return "MIPS-baseline-dsp"; |
| 1531 | } |
| 1532 | return "MIPS-baseline"; |
| 1533 | } |
| 1534 | |
| 1535 | /* Broadcom baseline. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1536 | if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_BROADCOM) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1537 | return "Broadcom-baseline"; |
| 1538 | } |
| 1539 | |
| 1540 | /* Netlogic baseline. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1541 | if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_NETLOGIC) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1542 | return "Netlogic-baseline"; |
| 1543 | } |
| 1544 | |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1545 | /* Cavium baseline. */ |
| 1546 | if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_CAVIUM) { |
| 1547 | return "Cavium-baseline"; |
| 1548 | } |
| 1549 | |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1550 | return NULL; |
| 1551 | } |
| 1552 | |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1553 | static const HChar* show_hwcaps_mips64 ( UInt hwcaps ) |
| 1554 | { |
| 1555 | return "mips64-baseline"; |
| 1556 | } |
| 1557 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1558 | /* ---- */ |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1559 | static const HChar* show_hwcaps ( VexArch arch, UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1560 | { |
| 1561 | switch (arch) { |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1562 | case VexArchX86: return show_hwcaps_x86(hwcaps); |
| 1563 | case VexArchAMD64: return show_hwcaps_amd64(hwcaps); |
| 1564 | case VexArchPPC32: return show_hwcaps_ppc32(hwcaps); |
| 1565 | case VexArchPPC64: return show_hwcaps_ppc64(hwcaps); |
| 1566 | case VexArchARM: return show_hwcaps_arm(hwcaps); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1567 | case VexArchARM64: return show_hwcaps_arm64(hwcaps); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1568 | case VexArchS390X: return show_hwcaps_s390x(hwcaps); |
| 1569 | case VexArchMIPS32: return show_hwcaps_mips32(hwcaps); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1570 | case VexArchMIPS64: return show_hwcaps_mips64(hwcaps); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1571 | default: return NULL; |
| 1572 | } |
| 1573 | } |
| 1574 | |
| 1575 | static Bool are_valid_hwcaps ( VexArch arch, UInt hwcaps ) |
| 1576 | { |
| 1577 | return show_hwcaps(arch,hwcaps) != NULL; |
| 1578 | } |
| 1579 | |
| 1580 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1581 | /*---------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 1582 | /*--- end main_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1583 | /*---------------------------------------------------------------*/ |