florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1 | /* -*- mode: C; c-basic-offset: 3; -*- */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 2 | |
| 3 | /*---------------------------------------------------------------*/ |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 4 | /*--- Begin main_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 5 | /*---------------------------------------------------------------*/ |
| 6 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 7 | /* |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 8 | This file is part of Valgrind, a dynamic binary instrumentation |
| 9 | framework. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 10 | |
sewardj | 89ae847 | 2013-10-18 14:12:58 +0000 | [diff] [blame] | 11 | Copyright (C) 2004-2013 OpenWorks LLP |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 12 | info@open-works.net |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 13 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 14 | This program is free software; you can redistribute it and/or |
| 15 | modify it under the terms of the GNU General Public License as |
| 16 | published by the Free Software Foundation; either version 2 of the |
| 17 | License, or (at your option) any later version. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 18 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 19 | This program is distributed in the hope that it will be useful, but |
| 20 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 22 | General Public License for more details. |
| 23 | |
| 24 | You should have received a copy of the GNU General Public License |
| 25 | along with this program; if not, write to the Free Software |
| 26 | Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 27 | 02110-1301, USA. |
| 28 | |
sewardj | 752f906 | 2010-05-03 21:38:49 +0000 | [diff] [blame] | 29 | The GNU General Public License is contained in the file COPYING. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 30 | |
| 31 | Neither the names of the U.S. Department of Energy nor the |
| 32 | University of California nor the names of its contributors may be |
| 33 | used to endorse or promote products derived from this software |
| 34 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 35 | */ |
| 36 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 37 | #include "libvex.h" |
florian | 33b0243 | 2012-08-25 21:48:04 +0000 | [diff] [blame] | 38 | #include "libvex_emnote.h" |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 39 | #include "libvex_guest_x86.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 40 | #include "libvex_guest_amd64.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 41 | #include "libvex_guest_arm.h" |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 42 | #include "libvex_guest_arm64.h" |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 43 | #include "libvex_guest_ppc32.h" |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 44 | #include "libvex_guest_ppc64.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 45 | #include "libvex_guest_s390x.h" |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 46 | #include "libvex_guest_mips32.h" |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 47 | #include "libvex_guest_mips64.h" |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 48 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 49 | #include "main_globals.h" |
| 50 | #include "main_util.h" |
| 51 | #include "host_generic_regs.h" |
| 52 | #include "ir_opt.h" |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 53 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 54 | #include "host_x86_defs.h" |
| 55 | #include "host_amd64_defs.h" |
| 56 | #include "host_ppc_defs.h" |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 57 | #include "host_arm_defs.h" |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 58 | #include "host_arm64_defs.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 59 | #include "host_s390_defs.h" |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 60 | #include "host_mips_defs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 61 | |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 62 | #include "guest_generic_bb_to_IR.h" |
| 63 | #include "guest_x86_defs.h" |
| 64 | #include "guest_amd64_defs.h" |
| 65 | #include "guest_arm_defs.h" |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 66 | #include "guest_arm64_defs.h" |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 67 | #include "guest_ppc_defs.h" |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 68 | #include "guest_s390_defs.h" |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 69 | #include "guest_mips_defs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 70 | |
sewardj | 69d98e3 | 2010-06-18 08:17:41 +0000 | [diff] [blame] | 71 | #include "host_generic_simd128.h" |
| 72 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 73 | |
| 74 | /* This file contains the top level interface to the library. */ |
| 75 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 76 | /* --------- fwds ... --------- */ |
| 77 | |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 78 | static void check_hwcaps ( VexArch arch, UInt hwcaps ); |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 79 | static const HChar* show_hwcaps ( VexArch arch, UInt hwcaps ); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 80 | |
| 81 | |
sewardj | 8bde7f1 | 2013-04-11 13:57:43 +0000 | [diff] [blame] | 82 | /* --------- helpers --------- */ |
| 83 | |
| 84 | __attribute__((noinline)) |
| 85 | static UInt udiv32 ( UInt x, UInt y ) { return x/y; } |
| 86 | __attribute__((noinline)) |
| 87 | static Int sdiv32 ( Int x, Int y ) { return x/y; } |
| 88 | |
| 89 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 90 | /* --------- Initialise the library. --------- */ |
| 91 | |
| 92 | /* Exported to library client. */ |
| 93 | |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 94 | void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon ) |
| 95 | { |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 96 | vex_bzero(vcon, sizeof(*vcon)); |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 97 | vcon->iropt_verbosity = 0; |
| 98 | vcon->iropt_level = 2; |
philippe | c8e2f98 | 2012-08-01 22:04:13 +0000 | [diff] [blame] | 99 | vcon->iropt_register_updates = VexRegUpdUnwindregsAtMemAccess; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 100 | vcon->iropt_unroll_thresh = 120; |
sewardj | 18b4bb7 | 2005-03-29 21:32:41 +0000 | [diff] [blame] | 101 | vcon->guest_max_insns = 60; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 102 | vcon->guest_chase_thresh = 10; |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 103 | vcon->guest_chase_cond = False; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | |
| 107 | /* Exported to library client. */ |
| 108 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 109 | void LibVEX_Init ( |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 110 | /* failure exit function */ |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 111 | __attribute__ ((noreturn)) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 112 | void (*failure_exit) ( void ), |
| 113 | /* logging output function */ |
florian | 04fc6b1 | 2014-12-29 20:22:26 +0000 | [diff] [blame] | 114 | void (*log_bytes) ( const HChar*, SizeT nbytes ), |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 115 | /* debug paranoia level */ |
| 116 | Int debuglevel, |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 117 | /* Control ... */ |
florian | f72c2c1 | 2014-09-05 21:52:29 +0000 | [diff] [blame] | 118 | const VexControl* vcon |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 119 | ) |
| 120 | { |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 121 | /* First off, do enough minimal setup so that the following |
| 122 | assertions can fail in a sane fashion, if need be. */ |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 123 | vex_failure_exit = failure_exit; |
| 124 | vex_log_bytes = log_bytes; |
| 125 | |
| 126 | /* Now it's safe to check parameters for sanity. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 127 | vassert(!vex_initdone); |
| 128 | vassert(failure_exit); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 129 | vassert(log_bytes); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 130 | vassert(debuglevel >= 0); |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 131 | |
| 132 | vassert(vcon->iropt_verbosity >= 0); |
| 133 | vassert(vcon->iropt_level >= 0); |
| 134 | vassert(vcon->iropt_level <= 2); |
| 135 | vassert(vcon->iropt_unroll_thresh >= 0); |
| 136 | vassert(vcon->iropt_unroll_thresh <= 400); |
| 137 | vassert(vcon->guest_max_insns >= 1); |
| 138 | vassert(vcon->guest_max_insns <= 100); |
| 139 | vassert(vcon->guest_chase_thresh >= 0); |
| 140 | vassert(vcon->guest_chase_thresh < vcon->guest_max_insns); |
sewardj | 984d9b1 | 2010-01-15 10:53:21 +0000 | [diff] [blame] | 141 | vassert(vcon->guest_chase_cond == True |
| 142 | || vcon->guest_chase_cond == False); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 143 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 144 | /* Check that Vex has been built with sizes of basic types as |
| 145 | stated in priv/libvex_basictypes.h. Failure of any of these is |
| 146 | a serious configuration error and should be corrected |
| 147 | immediately. If any of these assertions fail you can fully |
| 148 | expect Vex not to work properly, if at all. */ |
| 149 | |
| 150 | vassert(1 == sizeof(UChar)); |
| 151 | vassert(1 == sizeof(Char)); |
| 152 | vassert(2 == sizeof(UShort)); |
| 153 | vassert(2 == sizeof(Short)); |
| 154 | vassert(4 == sizeof(UInt)); |
| 155 | vassert(4 == sizeof(Int)); |
| 156 | vassert(8 == sizeof(ULong)); |
| 157 | vassert(8 == sizeof(Long)); |
| 158 | vassert(4 == sizeof(Float)); |
| 159 | vassert(8 == sizeof(Double)); |
| 160 | vassert(1 == sizeof(Bool)); |
| 161 | vassert(4 == sizeof(Addr32)); |
| 162 | vassert(8 == sizeof(Addr64)); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 163 | vassert(16 == sizeof(U128)); |
sewardj | 69d98e3 | 2010-06-18 08:17:41 +0000 | [diff] [blame] | 164 | vassert(16 == sizeof(V128)); |
sewardj | c9069f2 | 2012-06-01 16:09:50 +0000 | [diff] [blame] | 165 | vassert(32 == sizeof(U256)); |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 166 | |
| 167 | vassert(sizeof(void*) == 4 || sizeof(void*) == 8); |
| 168 | vassert(sizeof(void*) == sizeof(int*)); |
| 169 | vassert(sizeof(void*) == sizeof(HWord)); |
florian | beac530 | 2014-12-31 12:09:38 +0000 | [diff] [blame] | 170 | vassert(sizeof(void*) == sizeof(Addr)); |
| 171 | vassert(sizeof(unsigned long) == sizeof(SizeT)); |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 172 | |
sewardj | 97e8793 | 2005-02-07 00:00:50 +0000 | [diff] [blame] | 173 | vassert(VEX_HOST_WORDSIZE == sizeof(void*)); |
| 174 | vassert(VEX_HOST_WORDSIZE == sizeof(HWord)); |
| 175 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 176 | /* These take a lot of space, so make sure we don't have |
| 177 | any unnoticed size regressions. */ |
| 178 | if (VEX_HOST_WORDSIZE == 4) { |
florian | 420bfa9 | 2012-06-02 20:29:22 +0000 | [diff] [blame] | 179 | vassert(sizeof(IRExpr) == 16); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 180 | vassert(sizeof(IRStmt) == 20 /* x86 */ |
| 181 | || sizeof(IRStmt) == 24 /* arm */); |
| 182 | } else { |
florian | 420bfa9 | 2012-06-02 20:29:22 +0000 | [diff] [blame] | 183 | vassert(sizeof(IRExpr) == 32); |
florian | d6f38b3 | 2012-05-31 15:46:18 +0000 | [diff] [blame] | 184 | vassert(sizeof(IRStmt) == 32); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 185 | } |
| 186 | |
sewardj | 8bde7f1 | 2013-04-11 13:57:43 +0000 | [diff] [blame] | 187 | /* Check that signed integer division on the host rounds towards |
| 188 | zero. If not, h_calc_sdiv32_w_arm_semantics() won't work |
| 189 | correctly. */ |
| 190 | /* 100.0 / 7.0 == 14.2857 */ |
| 191 | vassert(udiv32(100, 7) == 14); |
| 192 | vassert(sdiv32(100, 7) == 14); |
| 193 | vassert(sdiv32(-100, 7) == -14); /* and not -15 */ |
| 194 | vassert(sdiv32(100, -7) == -14); /* ditto */ |
| 195 | vassert(sdiv32(-100, -7) == 14); /* not sure what this proves */ |
| 196 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 197 | /* Really start up .. */ |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 198 | vex_debuglevel = debuglevel; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 199 | vex_control = *vcon; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 200 | vex_initdone = True; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 201 | vexSetAllocMode ( VexAllocModeTEMP ); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 202 | } |
| 203 | |
| 204 | |
| 205 | /* --------- Make a translation. --------- */ |
| 206 | |
| 207 | /* Exported to library client. */ |
| 208 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 209 | VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 210 | { |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 211 | /* This the bundle of functions we need to do the back-end stuff |
| 212 | (insn selection, reg-alloc, assembly) whilst being insulated |
| 213 | from the target instruction set. */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 214 | HReg* available_real_regs; |
| 215 | Int n_available_real_regs; |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 216 | Bool (*isMove) ( const HInstr*, HReg*, HReg* ); |
| 217 | void (*getRegUsage) ( HRegUsage*, const HInstr*, Bool ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 218 | void (*mapRegs) ( HRegRemap*, HInstr*, Bool ); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 219 | void (*genSpill) ( HInstr**, HInstr**, HReg, Int, Bool ); |
| 220 | void (*genReload) ( HInstr**, HInstr**, HReg, Int, Bool ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 221 | HInstr* (*directReload) ( HInstr*, HReg, Short ); |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 222 | void (*ppInstr) ( const HInstr*, Bool ); |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 223 | void (*ppReg) ( HReg ); |
florian | cacba8e | 2014-12-15 18:58:07 +0000 | [diff] [blame] | 224 | HInstrArray* (*iselSB) ( const IRSB*, VexArch, const VexArchInfo*, |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 225 | const VexAbiInfo*, Int, Int, Bool, Bool, |
florian | dcd6d23 | 2015-01-02 17:32:21 +0000 | [diff] [blame] | 226 | Addr ); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 227 | Int (*emit) ( /*MB_MOD*/Bool*, |
florian | d8c64e0 | 2014-10-08 08:54:44 +0000 | [diff] [blame] | 228 | UChar*, Int, const HInstr*, Bool, VexEndness, |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 229 | const void*, const void*, const void*, |
| 230 | const void* ); |
florian | 1ff4756 | 2012-10-21 02:09:51 +0000 | [diff] [blame] | 231 | IRExpr* (*specHelper) ( const HChar*, IRExpr**, IRStmt**, Int ); |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 232 | Bool (*preciseMemExnsFn) ( Int, Int ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 233 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 234 | DisOneInstrFn disInstrFn; |
| 235 | |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 236 | VexGuestLayout* guest_layout; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 237 | IRSB* irsb; |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 238 | HInstrArray* vcode; |
| 239 | HInstrArray* rcode; |
| 240 | Int i, j, k, out_used, guest_sizeB; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 241 | Int offB_CMSTART, offB_CMLEN, offB_GUEST_IP, szB_GUEST_IP; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 242 | Int offB_HOST_EvC_COUNTER, offB_HOST_EvC_FAILADDR; |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 243 | UChar insn_bytes[128]; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 244 | IRType guest_word_type; |
| 245 | IRType host_word_type; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 246 | Bool mode64, chainingAllowed; |
florian | dcd6d23 | 2015-01-02 17:32:21 +0000 | [diff] [blame] | 247 | Addr max_ga; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 248 | |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 249 | guest_layout = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 250 | available_real_regs = NULL; |
| 251 | n_available_real_regs = 0; |
| 252 | isMove = NULL; |
| 253 | getRegUsage = NULL; |
| 254 | mapRegs = NULL; |
| 255 | genSpill = NULL; |
| 256 | genReload = NULL; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 257 | directReload = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 258 | ppInstr = NULL; |
| 259 | ppReg = NULL; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 260 | iselSB = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 261 | emit = NULL; |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 262 | specHelper = NULL; |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 263 | preciseMemExnsFn = NULL; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 264 | disInstrFn = NULL; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 265 | guest_word_type = Ity_INVALID; |
| 266 | host_word_type = Ity_INVALID; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 267 | offB_CMSTART = 0; |
| 268 | offB_CMLEN = 0; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 269 | offB_GUEST_IP = 0; |
| 270 | szB_GUEST_IP = 0; |
| 271 | offB_HOST_EvC_COUNTER = 0; |
| 272 | offB_HOST_EvC_FAILADDR = 0; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 273 | mode64 = False; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 274 | chainingAllowed = False; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 275 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 276 | vex_traceflags = vta->traceflags; |
sewardj | 58800ff | 2004-07-28 01:51:10 +0000 | [diff] [blame] | 277 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 278 | vassert(vex_initdone); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 279 | vassert(vta->needs_self_check != NULL); |
| 280 | vassert(vta->disp_cp_xassisted != NULL); |
| 281 | /* Both the chainers and the indir are either NULL or non-NULL. */ |
| 282 | if (vta->disp_cp_chain_me_to_slowEP != NULL) { |
| 283 | vassert(vta->disp_cp_chain_me_to_fastEP != NULL); |
| 284 | vassert(vta->disp_cp_xindir != NULL); |
| 285 | chainingAllowed = True; |
| 286 | } else { |
| 287 | vassert(vta->disp_cp_chain_me_to_fastEP == NULL); |
| 288 | vassert(vta->disp_cp_xindir == NULL); |
| 289 | } |
florian | 2eeeb9b | 2011-09-23 18:03:21 +0000 | [diff] [blame] | 290 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 291 | vexSetAllocModeTEMP_and_clear(); |
| 292 | vexAllocSanityCheck(); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 293 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 294 | /* First off, check that the guest and host insn sets |
| 295 | are supported. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 296 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 297 | switch (vta->arch_host) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 298 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 299 | case VexArchX86: |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 300 | mode64 = False; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 301 | getAllocableRegs_X86 ( &n_available_real_regs, |
| 302 | &available_real_regs ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 303 | isMove = (__typeof__(isMove)) isMove_X86Instr; |
| 304 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_X86Instr; |
| 305 | mapRegs = (__typeof__(mapRegs)) mapRegs_X86Instr; |
| 306 | genSpill = (__typeof__(genSpill)) genSpill_X86; |
| 307 | genReload = (__typeof__(genReload)) genReload_X86; |
| 308 | directReload = (__typeof__(directReload)) directReload_X86; |
| 309 | ppInstr = (__typeof__(ppInstr)) ppX86Instr; |
| 310 | ppReg = (__typeof__(ppReg)) ppHRegX86; |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 311 | iselSB = iselSB_X86; |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 312 | emit = (__typeof__(emit)) emit_X86Instr; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 313 | host_word_type = Ity_I32; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 314 | vassert(vta->archinfo_host.endness == VexEndnessLE); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 315 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 316 | |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 317 | case VexArchAMD64: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 318 | mode64 = True; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 319 | getAllocableRegs_AMD64 ( &n_available_real_regs, |
| 320 | &available_real_regs ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 321 | isMove = (__typeof__(isMove)) isMove_AMD64Instr; |
| 322 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_AMD64Instr; |
| 323 | mapRegs = (__typeof__(mapRegs)) mapRegs_AMD64Instr; |
| 324 | genSpill = (__typeof__(genSpill)) genSpill_AMD64; |
| 325 | genReload = (__typeof__(genReload)) genReload_AMD64; |
| 326 | ppInstr = (__typeof__(ppInstr)) ppAMD64Instr; |
| 327 | ppReg = (__typeof__(ppReg)) ppHRegAMD64; |
| 328 | iselSB = iselSB_AMD64; |
| 329 | emit = (__typeof__(emit)) emit_AMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 330 | host_word_type = Ity_I64; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 331 | vassert(vta->archinfo_host.endness == VexEndnessLE); |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 332 | break; |
| 333 | |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 334 | case VexArchPPC32: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 335 | mode64 = False; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 336 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 337 | &available_real_regs, mode64 ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 338 | isMove = (__typeof__(isMove)) isMove_PPCInstr; |
| 339 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_PPCInstr; |
| 340 | mapRegs = (__typeof__(mapRegs)) mapRegs_PPCInstr; |
| 341 | genSpill = (__typeof__(genSpill)) genSpill_PPC; |
| 342 | genReload = (__typeof__(genReload)) genReload_PPC; |
| 343 | ppInstr = (__typeof__(ppInstr)) ppPPCInstr; |
| 344 | ppReg = (__typeof__(ppReg)) ppHRegPPC; |
| 345 | iselSB = iselSB_PPC; |
| 346 | emit = (__typeof__(emit)) emit_PPCInstr; |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 347 | host_word_type = Ity_I32; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 348 | vassert(vta->archinfo_host.endness == VexEndnessBE); |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 349 | break; |
| 350 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 351 | case VexArchPPC64: |
| 352 | mode64 = True; |
cerion | 5b2325f | 2005-12-23 00:55:09 +0000 | [diff] [blame] | 353 | getAllocableRegs_PPC ( &n_available_real_regs, |
| 354 | &available_real_regs, mode64 ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 355 | isMove = (__typeof__(isMove)) isMove_PPCInstr; |
| 356 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_PPCInstr; |
| 357 | mapRegs = (__typeof__(mapRegs)) mapRegs_PPCInstr; |
| 358 | genSpill = (__typeof__(genSpill)) genSpill_PPC; |
| 359 | genReload = (__typeof__(genReload)) genReload_PPC; |
| 360 | ppInstr = (__typeof__(ppInstr)) ppPPCInstr; |
| 361 | ppReg = (__typeof__(ppReg)) ppHRegPPC; |
| 362 | iselSB = iselSB_PPC; |
| 363 | emit = (__typeof__(emit)) emit_PPCInstr; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 364 | host_word_type = Ity_I64; |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 365 | vassert(vta->archinfo_host.endness == VexEndnessBE || |
| 366 | vta->archinfo_host.endness == VexEndnessLE ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 367 | break; |
| 368 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 369 | case VexArchS390X: |
| 370 | mode64 = True; |
florian | 3eb7bab | 2014-12-08 12:42:26 +0000 | [diff] [blame] | 371 | /* KLUDGE: export hwcaps. */ |
| 372 | s390_host_hwcaps = vta->archinfo_host.hwcaps; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 373 | getAllocableRegs_S390 ( &n_available_real_regs, |
| 374 | &available_real_regs, mode64 ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 375 | isMove = (__typeof__(isMove)) isMove_S390Instr; |
| 376 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_S390Instr; |
| 377 | mapRegs = (__typeof__(mapRegs)) mapRegs_S390Instr; |
| 378 | genSpill = (__typeof__(genSpill)) genSpill_S390; |
| 379 | genReload = (__typeof__(genReload)) genReload_S390; |
florian | 017c0d5 | 2014-10-07 21:57:05 +0000 | [diff] [blame] | 380 | // fixs390: consider implementing directReload_S390 |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 381 | ppInstr = (__typeof__(ppInstr)) ppS390Instr; |
| 382 | ppReg = (__typeof__(ppReg)) ppHRegS390; |
| 383 | iselSB = iselSB_S390; |
| 384 | emit = (__typeof__(emit)) emit_S390Instr; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 385 | host_word_type = Ity_I64; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 386 | vassert(vta->archinfo_host.endness == VexEndnessBE); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 387 | break; |
| 388 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 389 | case VexArchARM: |
sewardj | 2a1ed8e | 2009-12-31 19:26:03 +0000 | [diff] [blame] | 390 | mode64 = False; |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 391 | getAllocableRegs_ARM ( &n_available_real_regs, |
| 392 | &available_real_regs ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 393 | isMove = (__typeof__(isMove)) isMove_ARMInstr; |
| 394 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_ARMInstr; |
| 395 | mapRegs = (__typeof__(mapRegs)) mapRegs_ARMInstr; |
| 396 | genSpill = (__typeof__(genSpill)) genSpill_ARM; |
| 397 | genReload = (__typeof__(genReload)) genReload_ARM; |
| 398 | ppInstr = (__typeof__(ppInstr)) ppARMInstr; |
| 399 | ppReg = (__typeof__(ppReg)) ppHRegARM; |
| 400 | iselSB = iselSB_ARM; |
| 401 | emit = (__typeof__(emit)) emit_ARMInstr; |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 402 | host_word_type = Ity_I32; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 403 | vassert(vta->archinfo_host.endness == VexEndnessLE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 404 | break; |
| 405 | |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 406 | case VexArchARM64: |
| 407 | mode64 = True; |
| 408 | getAllocableRegs_ARM64 ( &n_available_real_regs, |
| 409 | &available_real_regs ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 410 | isMove = (__typeof__(isMove)) isMove_ARM64Instr; |
| 411 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_ARM64Instr; |
| 412 | mapRegs = (__typeof__(mapRegs)) mapRegs_ARM64Instr; |
| 413 | genSpill = (__typeof__(genSpill)) genSpill_ARM64; |
| 414 | genReload = (__typeof__(genReload)) genReload_ARM64; |
| 415 | ppInstr = (__typeof__(ppInstr)) ppARM64Instr; |
| 416 | ppReg = (__typeof__(ppReg)) ppHRegARM64; |
| 417 | iselSB = iselSB_ARM64; |
| 418 | emit = (__typeof__(emit)) emit_ARM64Instr; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 419 | host_word_type = Ity_I64; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 420 | vassert(vta->archinfo_host.endness == VexEndnessLE); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 421 | break; |
| 422 | |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 423 | case VexArchMIPS32: |
| 424 | mode64 = False; |
| 425 | getAllocableRegs_MIPS ( &n_available_real_regs, |
| 426 | &available_real_regs, mode64 ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 427 | isMove = (__typeof__(isMove)) isMove_MIPSInstr; |
| 428 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_MIPSInstr; |
| 429 | mapRegs = (__typeof__(mapRegs)) mapRegs_MIPSInstr; |
| 430 | genSpill = (__typeof__(genSpill)) genSpill_MIPS; |
| 431 | genReload = (__typeof__(genReload)) genReload_MIPS; |
| 432 | ppInstr = (__typeof__(ppInstr)) ppMIPSInstr; |
| 433 | ppReg = (__typeof__(ppReg)) ppHRegMIPS; |
| 434 | iselSB = iselSB_MIPS; |
| 435 | emit = (__typeof__(emit)) emit_MIPSInstr; |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 436 | host_word_type = Ity_I32; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 437 | vassert(vta->archinfo_host.endness == VexEndnessLE |
| 438 | || vta->archinfo_host.endness == VexEndnessBE); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 439 | break; |
| 440 | |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 441 | case VexArchMIPS64: |
| 442 | mode64 = True; |
| 443 | getAllocableRegs_MIPS ( &n_available_real_regs, |
| 444 | &available_real_regs, mode64 ); |
florian | b66ad46 | 2014-10-07 22:13:47 +0000 | [diff] [blame] | 445 | isMove = (__typeof__(isMove)) isMove_MIPSInstr; |
| 446 | getRegUsage = (__typeof__(getRegUsage)) getRegUsage_MIPSInstr; |
| 447 | mapRegs = (__typeof__(mapRegs)) mapRegs_MIPSInstr; |
| 448 | genSpill = (__typeof__(genSpill)) genSpill_MIPS; |
| 449 | genReload = (__typeof__(genReload)) genReload_MIPS; |
| 450 | ppInstr = (__typeof__(ppInstr)) ppMIPSInstr; |
| 451 | ppReg = (__typeof__(ppReg)) ppHRegMIPS; |
| 452 | iselSB = iselSB_MIPS; |
| 453 | emit = (__typeof__(emit)) emit_MIPSInstr; |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 454 | host_word_type = Ity_I64; |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 455 | vassert(vta->archinfo_host.endness == VexEndnessLE |
| 456 | || vta->archinfo_host.endness == VexEndnessBE); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 457 | break; |
| 458 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 459 | default: |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 460 | vpanic("LibVEX_Translate: unsupported host insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 461 | } |
| 462 | |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 463 | // Are the host's hardware capabilities feasible. The function will |
| 464 | // not return if hwcaps are infeasible in some sense. |
| 465 | check_hwcaps(vta->arch_host, vta->archinfo_host.hwcaps); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 466 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 467 | switch (vta->arch_guest) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 468 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 469 | case VexArchX86: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 470 | preciseMemExnsFn = guest_x86_state_requires_precise_mem_exns; |
| 471 | disInstrFn = disInstr_X86; |
| 472 | specHelper = guest_x86_spechelper; |
| 473 | guest_sizeB = sizeof(VexGuestX86State); |
| 474 | guest_word_type = Ity_I32; |
| 475 | guest_layout = &x86guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 476 | offB_CMSTART = offsetof(VexGuestX86State,guest_CMSTART); |
| 477 | offB_CMLEN = offsetof(VexGuestX86State,guest_CMLEN); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 478 | offB_GUEST_IP = offsetof(VexGuestX86State,guest_EIP); |
| 479 | szB_GUEST_IP = sizeof( ((VexGuestX86State*)0)->guest_EIP ); |
| 480 | offB_HOST_EvC_COUNTER = offsetof(VexGuestX86State,host_EvC_COUNTER); |
| 481 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestX86State,host_EvC_FAILADDR); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 482 | vassert(vta->archinfo_guest.endness == VexEndnessLE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 483 | vassert(0 == sizeof(VexGuestX86State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 484 | vassert(sizeof( ((VexGuestX86State*)0)->guest_CMSTART) == 4); |
| 485 | vassert(sizeof( ((VexGuestX86State*)0)->guest_CMLEN ) == 4); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 486 | vassert(sizeof( ((VexGuestX86State*)0)->guest_NRADDR ) == 4); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 487 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 488 | |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 489 | case VexArchAMD64: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 490 | preciseMemExnsFn = guest_amd64_state_requires_precise_mem_exns; |
| 491 | disInstrFn = disInstr_AMD64; |
| 492 | specHelper = guest_amd64_spechelper; |
| 493 | guest_sizeB = sizeof(VexGuestAMD64State); |
| 494 | guest_word_type = Ity_I64; |
| 495 | guest_layout = &amd64guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 496 | offB_CMSTART = offsetof(VexGuestAMD64State,guest_CMSTART); |
| 497 | offB_CMLEN = offsetof(VexGuestAMD64State,guest_CMLEN); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 498 | offB_GUEST_IP = offsetof(VexGuestAMD64State,guest_RIP); |
| 499 | szB_GUEST_IP = sizeof( ((VexGuestAMD64State*)0)->guest_RIP ); |
| 500 | offB_HOST_EvC_COUNTER = offsetof(VexGuestAMD64State,host_EvC_COUNTER); |
| 501 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestAMD64State,host_EvC_FAILADDR); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 502 | vassert(vta->archinfo_guest.endness == VexEndnessLE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 503 | vassert(0 == sizeof(VexGuestAMD64State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 504 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_CMSTART ) == 8); |
| 505 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_CMLEN ) == 8); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 506 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_NRADDR ) == 8); |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 507 | break; |
| 508 | |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 509 | case VexArchPPC32: |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 510 | preciseMemExnsFn = guest_ppc32_state_requires_precise_mem_exns; |
| 511 | disInstrFn = disInstr_PPC; |
| 512 | specHelper = guest_ppc32_spechelper; |
| 513 | guest_sizeB = sizeof(VexGuestPPC32State); |
| 514 | guest_word_type = Ity_I32; |
| 515 | guest_layout = &ppc32Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 516 | offB_CMSTART = offsetof(VexGuestPPC32State,guest_CMSTART); |
| 517 | offB_CMLEN = offsetof(VexGuestPPC32State,guest_CMLEN); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 518 | offB_GUEST_IP = offsetof(VexGuestPPC32State,guest_CIA); |
| 519 | szB_GUEST_IP = sizeof( ((VexGuestPPC32State*)0)->guest_CIA ); |
| 520 | offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC32State,host_EvC_COUNTER); |
| 521 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC32State,host_EvC_FAILADDR); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 522 | vassert(vta->archinfo_guest.endness == VexEndnessBE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 523 | vassert(0 == sizeof(VexGuestPPC32State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 524 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_CMSTART ) == 4); |
| 525 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_CMLEN ) == 4); |
sewardj | ce02aa7 | 2006-01-12 12:27:58 +0000 | [diff] [blame] | 526 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_NRADDR ) == 4); |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 527 | break; |
| 528 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 529 | case VexArchPPC64: |
sewardj | 9e1cf15 | 2012-04-20 02:18:31 +0000 | [diff] [blame] | 530 | preciseMemExnsFn = guest_ppc64_state_requires_precise_mem_exns; |
| 531 | disInstrFn = disInstr_PPC; |
| 532 | specHelper = guest_ppc64_spechelper; |
| 533 | guest_sizeB = sizeof(VexGuestPPC64State); |
| 534 | guest_word_type = Ity_I64; |
| 535 | guest_layout = &ppc64Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 536 | offB_CMSTART = offsetof(VexGuestPPC64State,guest_CMSTART); |
| 537 | offB_CMLEN = offsetof(VexGuestPPC64State,guest_CMLEN); |
sewardj | 9e1cf15 | 2012-04-20 02:18:31 +0000 | [diff] [blame] | 538 | offB_GUEST_IP = offsetof(VexGuestPPC64State,guest_CIA); |
| 539 | szB_GUEST_IP = sizeof( ((VexGuestPPC64State*)0)->guest_CIA ); |
| 540 | offB_HOST_EvC_COUNTER = offsetof(VexGuestPPC64State,host_EvC_COUNTER); |
| 541 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestPPC64State,host_EvC_FAILADDR); |
carll | 1f5fe1f | 2014-08-07 23:25:23 +0000 | [diff] [blame] | 542 | vassert(vta->archinfo_guest.endness == VexEndnessBE || |
| 543 | vta->archinfo_guest.endness == VexEndnessLE ); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 544 | vassert(0 == sizeof(VexGuestPPC64State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 545 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_CMSTART ) == 8); |
| 546 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_CMLEN ) == 8); |
sewardj | 3fd3967 | 2006-01-27 22:05:55 +0000 | [diff] [blame] | 547 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR ) == 8); |
| 548 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_NRADDR_GPR2) == 8); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 549 | break; |
| 550 | |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 551 | case VexArchS390X: |
| 552 | preciseMemExnsFn = guest_s390x_state_requires_precise_mem_exns; |
| 553 | disInstrFn = disInstr_S390; |
| 554 | specHelper = guest_s390x_spechelper; |
| 555 | guest_sizeB = sizeof(VexGuestS390XState); |
| 556 | guest_word_type = Ity_I64; |
| 557 | guest_layout = &s390xGuest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 558 | offB_CMSTART = offsetof(VexGuestS390XState,guest_CMSTART); |
| 559 | offB_CMLEN = offsetof(VexGuestS390XState,guest_CMLEN); |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 560 | offB_GUEST_IP = offsetof(VexGuestS390XState,guest_IA); |
| 561 | szB_GUEST_IP = sizeof( ((VexGuestS390XState*)0)->guest_IA); |
| 562 | offB_HOST_EvC_COUNTER = offsetof(VexGuestS390XState,host_EvC_COUNTER); |
| 563 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestS390XState,host_EvC_FAILADDR); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 564 | vassert(vta->archinfo_guest.endness == VexEndnessBE); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 565 | vassert(0 == sizeof(VexGuestS390XState) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 566 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_CMSTART ) == 8); |
| 567 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_CMLEN ) == 8); |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 568 | vassert(sizeof( ((VexGuestS390XState*)0)->guest_NRADDR ) == 8); |
| 569 | break; |
| 570 | |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 571 | case VexArchARM: |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 572 | preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns; |
| 573 | disInstrFn = disInstr_ARM; |
| 574 | specHelper = guest_arm_spechelper; |
| 575 | guest_sizeB = sizeof(VexGuestARMState); |
| 576 | guest_word_type = Ity_I32; |
| 577 | guest_layout = &armGuest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 578 | offB_CMSTART = offsetof(VexGuestARMState,guest_CMSTART); |
| 579 | offB_CMLEN = offsetof(VexGuestARMState,guest_CMLEN); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 580 | offB_GUEST_IP = offsetof(VexGuestARMState,guest_R15T); |
| 581 | szB_GUEST_IP = sizeof( ((VexGuestARMState*)0)->guest_R15T ); |
| 582 | offB_HOST_EvC_COUNTER = offsetof(VexGuestARMState,host_EvC_COUNTER); |
| 583 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestARMState,host_EvC_FAILADDR); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 584 | vassert(vta->archinfo_guest.endness == VexEndnessLE); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 585 | vassert(0 == sizeof(VexGuestARMState) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 586 | vassert(sizeof( ((VexGuestARMState*)0)->guest_CMSTART) == 4); |
| 587 | vassert(sizeof( ((VexGuestARMState*)0)->guest_CMLEN ) == 4); |
sewardj | 6c299f3 | 2009-12-31 18:00:12 +0000 | [diff] [blame] | 588 | vassert(sizeof( ((VexGuestARMState*)0)->guest_NRADDR ) == 4); |
| 589 | break; |
| 590 | |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 591 | case VexArchARM64: |
| 592 | preciseMemExnsFn = guest_arm64_state_requires_precise_mem_exns; |
| 593 | disInstrFn = disInstr_ARM64; |
| 594 | specHelper = guest_arm64_spechelper; |
| 595 | guest_sizeB = sizeof(VexGuestARM64State); |
| 596 | guest_word_type = Ity_I64; |
| 597 | guest_layout = &arm64Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 598 | offB_CMSTART = offsetof(VexGuestARM64State,guest_CMSTART); |
| 599 | offB_CMLEN = offsetof(VexGuestARM64State,guest_CMLEN); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 600 | offB_GUEST_IP = offsetof(VexGuestARM64State,guest_PC); |
| 601 | szB_GUEST_IP = sizeof( ((VexGuestARM64State*)0)->guest_PC ); |
| 602 | offB_HOST_EvC_COUNTER = offsetof(VexGuestARM64State,host_EvC_COUNTER); |
| 603 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestARM64State,host_EvC_FAILADDR); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 604 | vassert(vta->archinfo_guest.endness == VexEndnessLE); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 605 | vassert(0 == sizeof(VexGuestARM64State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 606 | vassert(sizeof( ((VexGuestARM64State*)0)->guest_CMSTART) == 8); |
| 607 | vassert(sizeof( ((VexGuestARM64State*)0)->guest_CMLEN ) == 8); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 608 | vassert(sizeof( ((VexGuestARM64State*)0)->guest_NRADDR ) == 8); |
| 609 | break; |
| 610 | |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 611 | case VexArchMIPS32: |
| 612 | preciseMemExnsFn = guest_mips32_state_requires_precise_mem_exns; |
| 613 | disInstrFn = disInstr_MIPS; |
| 614 | specHelper = guest_mips32_spechelper; |
| 615 | guest_sizeB = sizeof(VexGuestMIPS32State); |
| 616 | guest_word_type = Ity_I32; |
| 617 | guest_layout = &mips32Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 618 | offB_CMSTART = offsetof(VexGuestMIPS32State,guest_CMSTART); |
| 619 | offB_CMLEN = offsetof(VexGuestMIPS32State,guest_CMLEN); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 620 | offB_GUEST_IP = offsetof(VexGuestMIPS32State,guest_PC); |
| 621 | szB_GUEST_IP = sizeof( ((VexGuestMIPS32State*)0)->guest_PC ); |
| 622 | offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS32State,host_EvC_COUNTER); |
| 623 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS32State,host_EvC_FAILADDR); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 624 | vassert(vta->archinfo_guest.endness == VexEndnessLE |
| 625 | || vta->archinfo_guest.endness == VexEndnessBE); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 626 | vassert(0 == sizeof(VexGuestMIPS32State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 627 | vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_CMSTART) == 4); |
| 628 | vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_CMLEN ) == 4); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 629 | vassert(sizeof( ((VexGuestMIPS32State*)0)->guest_NRADDR ) == 4); |
| 630 | break; |
| 631 | |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 632 | case VexArchMIPS64: |
| 633 | preciseMemExnsFn = guest_mips64_state_requires_precise_mem_exns; |
| 634 | disInstrFn = disInstr_MIPS; |
| 635 | specHelper = guest_mips64_spechelper; |
| 636 | guest_sizeB = sizeof(VexGuestMIPS64State); |
| 637 | guest_word_type = Ity_I64; |
| 638 | guest_layout = &mips64Guest_layout; |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 639 | offB_CMSTART = offsetof(VexGuestMIPS64State,guest_CMSTART); |
| 640 | offB_CMLEN = offsetof(VexGuestMIPS64State,guest_CMLEN); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 641 | offB_GUEST_IP = offsetof(VexGuestMIPS64State,guest_PC); |
| 642 | szB_GUEST_IP = sizeof( ((VexGuestMIPS64State*)0)->guest_PC ); |
| 643 | offB_HOST_EvC_COUNTER = offsetof(VexGuestMIPS64State,host_EvC_COUNTER); |
| 644 | offB_HOST_EvC_FAILADDR = offsetof(VexGuestMIPS64State,host_EvC_FAILADDR); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 645 | vassert(vta->archinfo_guest.endness == VexEndnessLE |
| 646 | || vta->archinfo_guest.endness == VexEndnessBE); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 647 | vassert(0 == sizeof(VexGuestMIPS64State) % 16); |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 648 | vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_CMSTART) == 8); |
| 649 | vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_CMLEN ) == 8); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 650 | vassert(sizeof( ((VexGuestMIPS64State*)0)->guest_NRADDR ) == 8); |
| 651 | break; |
| 652 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 653 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 654 | vpanic("LibVEX_Translate: unsupported guest insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 655 | } |
| 656 | |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 657 | // Are the guest's hardware capabilities feasible. The function will |
| 658 | // not return if hwcaps are infeasible in some sense. |
| 659 | // FIXME: how can we know the guest's hardware capabilities? |
| 660 | check_hwcaps(vta->arch_guest, vta->archinfo_guest.hwcaps); |
| 661 | |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 662 | /* Set up result struct. */ |
| 663 | VexTranslateResult res; |
sewardj | fadbbe2 | 2012-04-24 11:49:03 +0000 | [diff] [blame] | 664 | res.status = VexTransOK; |
| 665 | res.n_sc_extents = 0; |
| 666 | res.offs_profInc = -1; |
| 667 | res.n_guest_instrs = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 668 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 669 | /* yet more sanity checks ... */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 670 | if (vta->arch_guest == vta->arch_host) { |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 671 | /* doesn't necessarily have to be true, but if it isn't it means |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 672 | we are simulating one flavour of an architecture a different |
| 673 | flavour of the same architecture, which is pretty strange. */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 674 | vassert(vta->archinfo_guest.hwcaps == vta->archinfo_host.hwcaps); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 675 | /* ditto */ |
| 676 | vassert(vta->archinfo_guest.endness == vta->archinfo_host.endness); |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 677 | } |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 678 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 679 | vexAllocSanityCheck(); |
| 680 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 681 | if (vex_traceflags & VEX_TRACE_FE) |
| 682 | vex_printf("\n------------------------" |
| 683 | " Front end " |
| 684 | "------------------------\n\n"); |
| 685 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 686 | irsb = bb_to_IR ( vta->guest_extents, |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 687 | &res.n_sc_extents, |
sewardj | fadbbe2 | 2012-04-24 11:49:03 +0000 | [diff] [blame] | 688 | &res.n_guest_instrs, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 689 | vta->callback_opaque, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 690 | disInstrFn, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 691 | vta->guest_bytes, |
| 692 | vta->guest_bytes_addr, |
| 693 | vta->chase_into_ok, |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 694 | vta->archinfo_host.endness, |
sewardj | 442e51a | 2012-12-06 18:08:04 +0000 | [diff] [blame] | 695 | vta->sigill_diag, |
sewardj | a5f55da | 2006-04-30 23:37:32 +0000 | [diff] [blame] | 696 | vta->arch_guest, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 697 | &vta->archinfo_guest, |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 698 | &vta->abiinfo_both, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 699 | guest_word_type, |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 700 | vta->needs_self_check, |
sewardj | c716aea | 2006-01-17 01:48:46 +0000 | [diff] [blame] | 701 | vta->preamble_function, |
sewardj | 05f5e01 | 2014-05-04 10:52:11 +0000 | [diff] [blame] | 702 | offB_CMSTART, |
| 703 | offB_CMLEN, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 704 | offB_GUEST_IP, |
| 705 | szB_GUEST_IP ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 706 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 707 | vexAllocSanityCheck(); |
| 708 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 709 | if (irsb == NULL) { |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 710 | /* Access failure. */ |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 711 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 712 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 713 | res.status = VexTransAccessFail; return res; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 714 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 715 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 716 | vassert(vta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3); |
| 717 | vassert(vta->guest_extents->base[0] == vta->guest_bytes_addr); |
| 718 | for (i = 0; i < vta->guest_extents->n_used; i++) { |
| 719 | vassert(vta->guest_extents->len[i] < 10000); /* sanity */ |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 720 | } |
| 721 | |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 722 | /* If debugging, show the raw guest bytes for this bb. */ |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 723 | if (0 || (vex_traceflags & VEX_TRACE_FE)) { |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 724 | if (vta->guest_extents->n_used > 1) { |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 725 | vex_printf("can't show code due to extents > 1\n"); |
| 726 | } else { |
| 727 | /* HACK */ |
florian | 8462d11 | 2014-09-24 15:18:09 +0000 | [diff] [blame] | 728 | const UChar* p = vta->guest_bytes; |
sewardj | 01f8cce | 2009-08-31 08:50:02 +0000 | [diff] [blame] | 729 | UInt sum = 0; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 730 | UInt guest_bytes_read = (UInt)vta->guest_extents->len[0]; |
florian | d4cc0de | 2015-01-02 11:44:12 +0000 | [diff] [blame] | 731 | vex_printf("GuestBytes %lx %u ", vta->guest_bytes_addr, |
| 732 | guest_bytes_read ); |
sewardj | 01f8cce | 2009-08-31 08:50:02 +0000 | [diff] [blame] | 733 | for (i = 0; i < guest_bytes_read; i++) { |
| 734 | UInt b = (UInt)p[i]; |
| 735 | vex_printf(" %02x", b ); |
| 736 | sum = (sum << 1) ^ b; |
| 737 | } |
| 738 | vex_printf(" %08x\n\n", sum); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 739 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 740 | } |
| 741 | |
| 742 | /* Sanity check the initial IR. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 743 | sanityCheckIRSB( irsb, "initial IR", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 744 | False/*can be non-flat*/, guest_word_type ); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 745 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 746 | vexAllocSanityCheck(); |
| 747 | |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 748 | /* Clean it up, hopefully a lot. */ |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 749 | irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn, |
sewardj | ec0d9a0 | 2010-08-22 12:54:56 +0000 | [diff] [blame] | 750 | vta->guest_bytes_addr, |
| 751 | vta->arch_guest ); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 752 | sanityCheckIRSB( irsb, "after initial iropt", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 753 | True/*must be flat*/, guest_word_type ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 754 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 755 | if (vex_traceflags & VEX_TRACE_OPT1) { |
| 756 | vex_printf("\n------------------------" |
| 757 | " After pre-instr IR optimisation " |
| 758 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 759 | ppIRSB ( irsb ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 760 | vex_printf("\n"); |
| 761 | } |
| 762 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 763 | vexAllocSanityCheck(); |
| 764 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 765 | /* Get the thing instrumented. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 766 | if (vta->instrument1) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 767 | irsb = vta->instrument1(vta->callback_opaque, |
| 768 | irsb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 769 | vta->guest_extents, |
florian | 5048192 | 2012-10-07 21:58:07 +0000 | [diff] [blame] | 770 | &vta->archinfo_host, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 771 | guest_word_type, host_word_type); |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 772 | vexAllocSanityCheck(); |
| 773 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 774 | if (vta->instrument2) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 775 | irsb = vta->instrument2(vta->callback_opaque, |
| 776 | irsb, guest_layout, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 777 | vta->guest_extents, |
florian | 5048192 | 2012-10-07 21:58:07 +0000 | [diff] [blame] | 778 | &vta->archinfo_host, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 779 | guest_word_type, host_word_type); |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 780 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 781 | if (vex_traceflags & VEX_TRACE_INST) { |
| 782 | vex_printf("\n------------------------" |
| 783 | " After instrumentation " |
| 784 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 785 | ppIRSB ( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 786 | vex_printf("\n"); |
| 787 | } |
| 788 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 789 | if (vta->instrument1 || vta->instrument2) |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 790 | sanityCheckIRSB( irsb, "after instrumentation", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 791 | True/*must be flat*/, guest_word_type ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 792 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 793 | /* Do a post-instrumentation cleanup pass. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 794 | if (vta->instrument1 || vta->instrument2) { |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 795 | do_deadcode_BB( irsb ); |
| 796 | irsb = cprop_BB( irsb ); |
| 797 | do_deadcode_BB( irsb ); |
| 798 | sanityCheckIRSB( irsb, "after post-instrumentation cleanup", |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 799 | True/*must be flat*/, guest_word_type ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 800 | } |
| 801 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 802 | vexAllocSanityCheck(); |
| 803 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 804 | if (vex_traceflags & VEX_TRACE_OPT2) { |
| 805 | vex_printf("\n------------------------" |
| 806 | " After post-instr IR optimisation " |
| 807 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 808 | ppIRSB ( irsb ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 809 | vex_printf("\n"); |
| 810 | } |
| 811 | |
sewardj | f9517d0 | 2005-11-28 13:39:37 +0000 | [diff] [blame] | 812 | /* Turn it into virtual-registerised code. Build trees -- this |
| 813 | also throws away any dead bindings. */ |
florian | 62140c1 | 2013-01-20 03:51:04 +0000 | [diff] [blame] | 814 | max_ga = ado_treebuild_BB( irsb, preciseMemExnsFn ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 815 | |
sewardj | be1b6ff | 2007-08-28 06:06:27 +0000 | [diff] [blame] | 816 | if (vta->finaltidy) { |
| 817 | irsb = vta->finaltidy(irsb); |
| 818 | } |
| 819 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 820 | vexAllocSanityCheck(); |
| 821 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 822 | if (vex_traceflags & VEX_TRACE_TREES) { |
| 823 | vex_printf("\n------------------------" |
| 824 | " After tree-building " |
| 825 | "------------------------\n\n"); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 826 | ppIRSB ( irsb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 827 | vex_printf("\n"); |
| 828 | } |
| 829 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 830 | /* HACK */ |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 831 | if (0) { |
| 832 | *(vta->host_bytes_used) = 0; |
| 833 | res.status = VexTransOK; return res; |
| 834 | } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 835 | /* end HACK */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 836 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 837 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 838 | vex_printf("\n------------------------" |
| 839 | " Instruction selection " |
| 840 | "------------------------\n"); |
| 841 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 842 | /* No guest has its IP field at offset zero. If this fails it |
| 843 | means some transformation pass somewhere failed to update/copy |
| 844 | irsb->offsIP properly. */ |
| 845 | vassert(irsb->offsIP >= 16); |
| 846 | |
| 847 | vcode = iselSB ( irsb, vta->arch_host, |
| 848 | &vta->archinfo_host, |
| 849 | &vta->abiinfo_both, |
| 850 | offB_HOST_EvC_COUNTER, |
| 851 | offB_HOST_EvC_FAILADDR, |
| 852 | chainingAllowed, |
| 853 | vta->addProfInc, |
| 854 | max_ga ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 855 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 856 | vexAllocSanityCheck(); |
| 857 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 858 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 859 | vex_printf("\n"); |
| 860 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 861 | if (vex_traceflags & VEX_TRACE_VCODE) { |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 862 | for (i = 0; i < vcode->arr_used; i++) { |
| 863 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 864 | ppInstr(vcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 865 | vex_printf("\n"); |
| 866 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 867 | vex_printf("\n"); |
| 868 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 869 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 870 | /* Register allocate. */ |
| 871 | rcode = doRegisterAllocation ( vcode, available_real_regs, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 872 | n_available_real_regs, |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 873 | isMove, getRegUsage, mapRegs, |
sewardj | fb7373a | 2007-08-25 21:29:03 +0000 | [diff] [blame] | 874 | genSpill, genReload, directReload, |
| 875 | guest_sizeB, |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 876 | ppInstr, ppReg, mode64 ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 877 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 878 | vexAllocSanityCheck(); |
| 879 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 880 | if (vex_traceflags & VEX_TRACE_RCODE) { |
| 881 | vex_printf("\n------------------------" |
| 882 | " Register-allocated code " |
| 883 | "------------------------\n\n"); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 884 | for (i = 0; i < rcode->arr_used; i++) { |
| 885 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 886 | ppInstr(rcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 887 | vex_printf("\n"); |
| 888 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 889 | vex_printf("\n"); |
| 890 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 891 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 892 | /* HACK */ |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 893 | if (0) { |
| 894 | *(vta->host_bytes_used) = 0; |
| 895 | res.status = VexTransOK; return res; |
| 896 | } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 897 | /* end HACK */ |
| 898 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 899 | /* Assemble */ |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 900 | if (vex_traceflags & VEX_TRACE_ASM) { |
| 901 | vex_printf("\n------------------------" |
| 902 | " Assembly " |
| 903 | "------------------------\n\n"); |
| 904 | } |
| 905 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 906 | out_used = 0; /* tracks along the host_bytes array */ |
| 907 | for (i = 0; i < rcode->arr_used; i++) { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 908 | HInstr* hi = rcode->arr[i]; |
| 909 | Bool hi_isProfInc = False; |
| 910 | if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) { |
| 911 | ppInstr(hi, mode64); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 912 | vex_printf("\n"); |
| 913 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 914 | j = emit( &hi_isProfInc, |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 915 | insn_bytes, sizeof insn_bytes, hi, |
| 916 | mode64, vta->archinfo_host.endness, |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 917 | vta->disp_cp_chain_me_to_slowEP, |
| 918 | vta->disp_cp_chain_me_to_fastEP, |
| 919 | vta->disp_cp_xindir, |
| 920 | vta->disp_cp_xassisted ); |
| 921 | if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 922 | for (k = 0; k < j; k++) |
florian | e554042 | 2014-12-15 21:07:37 +0000 | [diff] [blame] | 923 | vex_printf("%02x ", (UInt)insn_bytes[k]); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 924 | vex_printf("\n\n"); |
| 925 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 926 | if (UNLIKELY(out_used + j > vta->host_bytes_size)) { |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 927 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 928 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 929 | res.status = VexTransOutputFull; |
| 930 | return res; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 931 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 932 | if (UNLIKELY(hi_isProfInc)) { |
| 933 | vassert(vta->addProfInc); /* else where did it come from? */ |
| 934 | vassert(res.offs_profInc == -1); /* there can be only one (tm) */ |
| 935 | vassert(out_used >= 0); |
| 936 | res.offs_profInc = out_used; |
| 937 | } |
| 938 | { UChar* dst = &vta->host_bytes[out_used]; |
| 939 | for (k = 0; k < j; k++) { |
| 940 | dst[k] = insn_bytes[k]; |
| 941 | } |
| 942 | out_used += j; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 943 | } |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 944 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame] | 945 | *(vta->host_bytes_used) = out_used; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 946 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 947 | vexAllocSanityCheck(); |
| 948 | |
| 949 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 950 | |
sewardj | 65ea17e | 2012-12-28 09:01:59 +0000 | [diff] [blame] | 951 | if (vex_traceflags) { |
| 952 | /* Print the expansion ratio for this SB. */ |
| 953 | j = 0; /* total guest bytes */ |
| 954 | for (i = 0; i < vta->guest_extents->n_used; i++) { |
| 955 | j += vta->guest_extents->len[i]; |
| 956 | } |
| 957 | if (1) vex_printf("VexExpansionRatio %d %d %d :10\n\n", |
| 958 | j, out_used, (10 * out_used) / (j == 0 ? 1 : j)); |
| 959 | } |
| 960 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 961 | vex_traceflags = 0; |
sewardj | bc161a4 | 2011-06-07 21:28:38 +0000 | [diff] [blame] | 962 | res.status = VexTransOK; |
| 963 | return res; |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 964 | } |
| 965 | |
| 966 | |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 967 | /* --------- Chain/Unchain XDirects. --------- */ |
| 968 | |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 969 | VexInvalRange LibVEX_Chain ( VexArch arch_host, |
| 970 | VexEndness endness_host, |
| 971 | void* place_to_chain, |
| 972 | const void* disp_cp_chain_me_EXPECTED, |
| 973 | const void* place_to_jump_to ) |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 974 | { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 975 | switch (arch_host) { |
| 976 | case VexArchX86: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 977 | return chainXDirect_X86(endness_host, |
| 978 | place_to_chain, |
| 979 | disp_cp_chain_me_EXPECTED, |
| 980 | place_to_jump_to); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 981 | case VexArchAMD64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 982 | return chainXDirect_AMD64(endness_host, |
| 983 | place_to_chain, |
| 984 | disp_cp_chain_me_EXPECTED, |
| 985 | place_to_jump_to); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 986 | case VexArchARM: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 987 | return chainXDirect_ARM(endness_host, |
| 988 | place_to_chain, |
| 989 | disp_cp_chain_me_EXPECTED, |
| 990 | place_to_jump_to); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 991 | case VexArchARM64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 992 | return chainXDirect_ARM64(endness_host, |
| 993 | place_to_chain, |
| 994 | disp_cp_chain_me_EXPECTED, |
| 995 | place_to_jump_to); |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 996 | case VexArchS390X: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 997 | return chainXDirect_S390(endness_host, |
| 998 | place_to_chain, |
| 999 | disp_cp_chain_me_EXPECTED, |
| 1000 | place_to_jump_to); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1001 | case VexArchPPC32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1002 | return chainXDirect_PPC(endness_host, |
| 1003 | place_to_chain, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1004 | disp_cp_chain_me_EXPECTED, |
| 1005 | place_to_jump_to, False/*!mode64*/); |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1006 | case VexArchPPC64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1007 | return chainXDirect_PPC(endness_host, |
| 1008 | place_to_chain, |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1009 | disp_cp_chain_me_EXPECTED, |
| 1010 | place_to_jump_to, True/*mode64*/); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1011 | case VexArchMIPS32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1012 | return chainXDirect_MIPS(endness_host, |
| 1013 | place_to_chain, |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1014 | disp_cp_chain_me_EXPECTED, |
| 1015 | place_to_jump_to, False/*!mode64*/); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1016 | case VexArchMIPS64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1017 | return chainXDirect_MIPS(endness_host, |
| 1018 | place_to_chain, |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1019 | disp_cp_chain_me_EXPECTED, |
| 1020 | place_to_jump_to, True/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1021 | default: |
| 1022 | vassert(0); |
| 1023 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1024 | } |
| 1025 | |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1026 | VexInvalRange LibVEX_UnChain ( VexArch arch_host, |
| 1027 | VexEndness endness_host, |
| 1028 | void* place_to_unchain, |
| 1029 | const void* place_to_jump_to_EXPECTED, |
| 1030 | const void* disp_cp_chain_me ) |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1031 | { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1032 | switch (arch_host) { |
| 1033 | case VexArchX86: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1034 | return unchainXDirect_X86(endness_host, |
| 1035 | place_to_unchain, |
| 1036 | place_to_jump_to_EXPECTED, |
| 1037 | disp_cp_chain_me); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1038 | case VexArchAMD64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1039 | return unchainXDirect_AMD64(endness_host, |
| 1040 | place_to_unchain, |
| 1041 | place_to_jump_to_EXPECTED, |
| 1042 | disp_cp_chain_me); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1043 | case VexArchARM: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1044 | return unchainXDirect_ARM(endness_host, |
| 1045 | place_to_unchain, |
| 1046 | place_to_jump_to_EXPECTED, |
| 1047 | disp_cp_chain_me); |
sewardj | c6acaa4 | 2014-02-19 17:42:59 +0000 | [diff] [blame] | 1048 | case VexArchARM64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1049 | return unchainXDirect_ARM64(endness_host, |
| 1050 | place_to_unchain, |
| 1051 | place_to_jump_to_EXPECTED, |
| 1052 | disp_cp_chain_me); |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 1053 | case VexArchS390X: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1054 | return unchainXDirect_S390(endness_host, |
| 1055 | place_to_unchain, |
| 1056 | place_to_jump_to_EXPECTED, |
| 1057 | disp_cp_chain_me); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1058 | case VexArchPPC32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1059 | return unchainXDirect_PPC(endness_host, |
| 1060 | place_to_unchain, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1061 | place_to_jump_to_EXPECTED, |
| 1062 | disp_cp_chain_me, False/*!mode64*/); |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1063 | case VexArchPPC64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1064 | return unchainXDirect_PPC(endness_host, |
| 1065 | place_to_unchain, |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1066 | place_to_jump_to_EXPECTED, |
| 1067 | disp_cp_chain_me, True/*mode64*/); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1068 | case VexArchMIPS32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1069 | return unchainXDirect_MIPS(endness_host, |
| 1070 | place_to_unchain, |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1071 | place_to_jump_to_EXPECTED, |
| 1072 | disp_cp_chain_me, False/*!mode64*/); |
| 1073 | case VexArchMIPS64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1074 | return unchainXDirect_MIPS(endness_host, |
| 1075 | place_to_unchain, |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1076 | place_to_jump_to_EXPECTED, |
| 1077 | disp_cp_chain_me, True/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1078 | default: |
| 1079 | vassert(0); |
| 1080 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1081 | } |
| 1082 | |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1083 | Int LibVEX_evCheckSzB ( VexArch arch_host, |
| 1084 | VexEndness endness_host ) |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1085 | { |
| 1086 | static Int cached = 0; /* DO NOT MAKE NON-STATIC */ |
| 1087 | if (UNLIKELY(cached == 0)) { |
| 1088 | switch (arch_host) { |
| 1089 | case VexArchX86: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1090 | cached = evCheckSzB_X86(endness_host); break; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1091 | case VexArchAMD64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1092 | cached = evCheckSzB_AMD64(endness_host); break; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1093 | case VexArchARM: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1094 | cached = evCheckSzB_ARM(endness_host); break; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1095 | case VexArchARM64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1096 | cached = evCheckSzB_ARM64(endness_host); break; |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 1097 | case VexArchS390X: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1098 | cached = evCheckSzB_S390(endness_host); break; |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1099 | case VexArchPPC32: |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1100 | case VexArchPPC64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1101 | cached = evCheckSzB_PPC(endness_host); break; |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1102 | case VexArchMIPS32: |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1103 | case VexArchMIPS64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1104 | cached = evCheckSzB_MIPS(endness_host); break; |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1105 | default: |
| 1106 | vassert(0); |
| 1107 | } |
| 1108 | } |
| 1109 | return cached; |
| 1110 | } |
| 1111 | |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1112 | VexInvalRange LibVEX_PatchProfInc ( VexArch arch_host, |
| 1113 | VexEndness endness_host, |
| 1114 | void* place_to_patch, |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1115 | const ULong* location_of_counter ) |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1116 | { |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1117 | switch (arch_host) { |
| 1118 | case VexArchX86: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1119 | return patchProfInc_X86(endness_host, place_to_patch, |
| 1120 | location_of_counter); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1121 | case VexArchAMD64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1122 | return patchProfInc_AMD64(endness_host, place_to_patch, |
| 1123 | location_of_counter); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1124 | case VexArchARM: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1125 | return patchProfInc_ARM(endness_host, place_to_patch, |
| 1126 | location_of_counter); |
sewardj | 0ad37a9 | 2014-08-29 21:58:03 +0000 | [diff] [blame] | 1127 | case VexArchARM64: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1128 | return patchProfInc_ARM64(endness_host, place_to_patch, |
| 1129 | location_of_counter); |
florian | 8844a63 | 2012-04-13 04:04:06 +0000 | [diff] [blame] | 1130 | case VexArchS390X: |
florian | 7d6f81d | 2014-09-22 21:43:37 +0000 | [diff] [blame] | 1131 | return patchProfInc_S390(endness_host, place_to_patch, |
| 1132 | location_of_counter); |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1133 | case VexArchPPC32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1134 | return patchProfInc_PPC(endness_host, place_to_patch, |
sewardj | 3dee849 | 2012-04-20 00:13:28 +0000 | [diff] [blame] | 1135 | location_of_counter, False/*!mode64*/); |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1136 | case VexArchPPC64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1137 | return patchProfInc_PPC(endness_host, place_to_patch, |
sewardj | f252de5 | 2012-04-20 10:42:24 +0000 | [diff] [blame] | 1138 | location_of_counter, True/*mode64*/); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1139 | case VexArchMIPS32: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1140 | return patchProfInc_MIPS(endness_host, place_to_patch, |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1141 | location_of_counter, False/*!mode64*/); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1142 | case VexArchMIPS64: |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1143 | return patchProfInc_MIPS(endness_host, place_to_patch, |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1144 | location_of_counter, True/*!mode64*/); |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1145 | default: |
| 1146 | vassert(0); |
| 1147 | } |
sewardj | c6f970f | 2012-04-02 21:54:49 +0000 | [diff] [blame] | 1148 | } |
| 1149 | |
| 1150 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1151 | /* --------- Emulation warnings. --------- */ |
| 1152 | |
florian | 1ff4756 | 2012-10-21 02:09:51 +0000 | [diff] [blame] | 1153 | const HChar* LibVEX_EmNote_string ( VexEmNote ew ) |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1154 | { |
| 1155 | switch (ew) { |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 1156 | case EmNote_NONE: |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1157 | return "none"; |
| 1158 | case EmWarn_X86_x87exns: |
| 1159 | return "Unmasking x87 FP exceptions"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1160 | case EmWarn_X86_x87precision: |
| 1161 | return "Selection of non-80-bit x87 FP precision"; |
| 1162 | case EmWarn_X86_sseExns: |
sewardj | 5edfc26 | 2004-12-15 12:13:52 +0000 | [diff] [blame] | 1163 | return "Unmasking SSE FP exceptions"; |
| 1164 | case EmWarn_X86_fz: |
| 1165 | return "Setting %mxcsr.fz (SSE flush-underflows-to-zero mode)"; |
| 1166 | case EmWarn_X86_daz: |
| 1167 | return "Setting %mxcsr.daz (SSE treat-denormals-as-zero mode)"; |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 1168 | case EmWarn_X86_acFlag: |
| 1169 | return "Setting %eflags.ac (setting noted but ignored)"; |
sewardj | 9dd9cf1 | 2006-01-20 14:13:55 +0000 | [diff] [blame] | 1170 | case EmWarn_PPCexns: |
| 1171 | return "Unmasking PPC32/64 FP exceptions"; |
| 1172 | case EmWarn_PPC64_redir_overflow: |
| 1173 | return "PPC64 function redirection stack overflow"; |
| 1174 | case EmWarn_PPC64_redir_underflow: |
| 1175 | return "PPC64 function redirection stack underflow"; |
florian | 4b8efad | 2012-09-02 18:07:08 +0000 | [diff] [blame] | 1176 | case EmWarn_S390X_fpext_rounding: |
| 1177 | return "The specified rounding mode cannot be supported. That\n" |
florian | 2a4de0b | 2014-12-05 18:28:29 +0000 | [diff] [blame] | 1178 | " feature requires the floating point extension facility\n" |
florian | 4b8efad | 2012-09-02 18:07:08 +0000 | [diff] [blame] | 1179 | " which is not available on this host. Continuing using\n" |
| 1180 | " the rounding mode from FPC. Results may differ!"; |
florian | f0fa1be | 2012-09-18 20:24:38 +0000 | [diff] [blame] | 1181 | case EmWarn_S390X_invalid_rounding: |
| 1182 | return "The specified rounding mode is invalid.\n" |
| 1183 | " Continuing using 'round to nearest'. Results may differ!"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1184 | case EmFail_S390X_stfle: |
florian | 4e0083e | 2012-08-26 03:41:56 +0000 | [diff] [blame] | 1185 | return "Instruction stfle is not supported on this host"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1186 | case EmFail_S390X_stckf: |
florian | c5c669b | 2012-08-26 14:32:28 +0000 | [diff] [blame] | 1187 | return "Instruction stckf is not supported on this host"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1188 | case EmFail_S390X_ecag: |
florian | 8c88cb6 | 2012-08-26 18:58:13 +0000 | [diff] [blame] | 1189 | return "Instruction ecag is not supported on this host"; |
florian | ad00ea9 | 2014-12-05 18:55:39 +0000 | [diff] [blame] | 1190 | case EmFail_S390X_pfpo: |
| 1191 | return "Instruction pfpo is not supported on this host"; |
florian | fb59660 | 2014-12-06 16:34:48 +0000 | [diff] [blame] | 1192 | case EmFail_S390X_DFP_insn: |
| 1193 | return "DFP instructions are not supported on this host"; |
florian | e75dafa | 2012-09-01 17:54:09 +0000 | [diff] [blame] | 1194 | case EmFail_S390X_fpext: |
| 1195 | return "Encountered an instruction that requires the floating " |
| 1196 | "point extension facility.\n" |
| 1197 | " That facility is not available on this host"; |
florian | 78d5ef7 | 2013-05-11 15:02:58 +0000 | [diff] [blame] | 1198 | case EmFail_S390X_invalid_PFPO_rounding_mode: |
florian | 2a4de0b | 2014-12-05 18:28:29 +0000 | [diff] [blame] | 1199 | return "The rounding mode in GPR 0 for the PFPO instruction" |
florian | 78d5ef7 | 2013-05-11 15:02:58 +0000 | [diff] [blame] | 1200 | " is invalid"; |
| 1201 | case EmFail_S390X_invalid_PFPO_function: |
florian | 2a4de0b | 2014-12-05 18:28:29 +0000 | [diff] [blame] | 1202 | return "The function code in GPR 0 for the PFPO instruction" |
florian | 78d5ef7 | 2013-05-11 15:02:58 +0000 | [diff] [blame] | 1203 | " is invalid"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1204 | default: |
florian | 6ef84be | 2012-08-26 03:20:07 +0000 | [diff] [blame] | 1205 | vpanic("LibVEX_EmNote_string: unknown warning"); |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 1206 | } |
| 1207 | } |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1208 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1209 | /* ------------------ Arch/HwCaps stuff. ------------------ */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1210 | |
| 1211 | const HChar* LibVEX_ppVexArch ( VexArch arch ) |
| 1212 | { |
| 1213 | switch (arch) { |
| 1214 | case VexArch_INVALID: return "INVALID"; |
| 1215 | case VexArchX86: return "X86"; |
| 1216 | case VexArchAMD64: return "AMD64"; |
| 1217 | case VexArchARM: return "ARM"; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1218 | case VexArchARM64: return "ARM64"; |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 1219 | case VexArchPPC32: return "PPC32"; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 1220 | case VexArchPPC64: return "PPC64"; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1221 | case VexArchS390X: return "S390X"; |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1222 | case VexArchMIPS32: return "MIPS32"; |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1223 | case VexArchMIPS64: return "MIPS64"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1224 | default: return "VexArch???"; |
| 1225 | } |
| 1226 | } |
| 1227 | |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1228 | const HChar* LibVEX_ppVexEndness ( VexEndness endness ) |
| 1229 | { |
| 1230 | switch (endness) { |
| 1231 | case VexEndness_INVALID: return "INVALID"; |
| 1232 | case VexEndnessLE: return "LittleEndian"; |
| 1233 | case VexEndnessBE: return "BigEndian"; |
| 1234 | default: return "VexEndness???"; |
| 1235 | } |
| 1236 | } |
| 1237 | |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1238 | /* Return a string with the hardware capabilities to the extent as |
| 1239 | they pertain to the translation process. No attempt is made, to |
| 1240 | detect *all* capabilities an architecture may have. */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1241 | const HChar* LibVEX_ppVexHwCaps ( VexArch arch, UInt hwcaps ) |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1242 | { |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1243 | return show_hwcaps(arch, hwcaps); |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 1244 | } |
| 1245 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1246 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 1247 | /* Write default settings info *vai. */ |
| 1248 | void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ) |
| 1249 | { |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 1250 | vex_bzero(vai, sizeof(*vai)); |
sewardj | 9b76916 | 2014-07-24 12:42:03 +0000 | [diff] [blame] | 1251 | vai->hwcaps = 0; |
| 1252 | vai->endness = VexEndness_INVALID; |
| 1253 | vai->ppc_icache_line_szB = 0; |
| 1254 | vai->ppc_dcbz_szB = 0; |
| 1255 | vai->ppc_dcbzl_szB = 0; |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 1256 | vai->arm64_dMinLine_lg2_szB = 0; |
| 1257 | vai->arm64_iMinLine_lg2_szB = 0; |
florian | f192a39 | 2012-10-07 19:44:40 +0000 | [diff] [blame] | 1258 | vai->hwcache_info.num_levels = 0; |
| 1259 | vai->hwcache_info.num_caches = 0; |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 1260 | vai->hwcache_info.caches = NULL; |
florian | f192a39 | 2012-10-07 19:44:40 +0000 | [diff] [blame] | 1261 | vai->hwcache_info.icaches_maintain_coherence = True; // whatever |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 1262 | } |
| 1263 | |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1264 | /* Write default settings info *vbi. */ |
| 1265 | void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi ) |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1266 | { |
sewardj | 6590299 | 2014-05-03 21:20:56 +0000 | [diff] [blame] | 1267 | vex_bzero(vbi, sizeof(*vbi)); |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1268 | vbi->guest_stack_redzone_size = 0; |
philippe | e2cc4de | 2014-12-16 23:57:51 +0000 | [diff] [blame] | 1269 | vbi->guest_amd64_assume_fs_is_const = False; |
| 1270 | vbi->guest_amd64_assume_gs_is_const = False; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1271 | vbi->guest_ppc_zap_RZ_at_blr = False; |
| 1272 | vbi->guest_ppc_zap_RZ_at_bl = NULL; |
sewardj | dd40fdf | 2006-12-24 02:20:24 +0000 | [diff] [blame] | 1273 | vbi->host_ppc_calls_use_fndescrs = False; |
sewardj | aca070a | 2006-10-17 00:28:22 +0000 | [diff] [blame] | 1274 | } |
| 1275 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 1276 | |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1277 | /* Convenience macro to be used in show_hwcaps_ARCH functions */ |
| 1278 | #define NUM_HWCAPS (sizeof hwcaps_list / sizeof hwcaps_list[0]) |
| 1279 | |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1280 | /* Return a string showing the hwcaps in a nice way. The string will |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1281 | be NULL for unrecognised hardware capabilities. */ |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1282 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1283 | static const HChar* show_hwcaps_x86 ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1284 | { |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1285 | static const HChar prefix[] = "x86"; |
| 1286 | static const struct { |
| 1287 | UInt hwcaps_bit; |
| 1288 | HChar name[7]; |
| 1289 | } hwcaps_list[] = { |
| 1290 | { VEX_HWCAPS_X86_MMXEXT, "mmxext" }, |
| 1291 | { VEX_HWCAPS_X86_SSE1, "sse1" }, |
| 1292 | { VEX_HWCAPS_X86_SSE2, "sse2" }, |
| 1293 | { VEX_HWCAPS_X86_SSE3, "sse3" }, |
| 1294 | { VEX_HWCAPS_X86_LZCNT, "lzcnt" }, |
| 1295 | }; |
| 1296 | /* Allocate a large enough buffer */ |
| 1297 | static HChar buf[sizeof prefix + |
| 1298 | NUM_HWCAPS * (sizeof hwcaps_list[0].name + 1) + 1]; // '\0' |
| 1299 | if (buf[0] != '\0') return buf; /* already constructed */ |
| 1300 | |
| 1301 | HChar *p = buf + vex_sprintf(buf, "%s", prefix); |
| 1302 | |
| 1303 | if (hwcaps == 0) { |
| 1304 | vex_sprintf(p, "-%s", "sse0"); |
| 1305 | } else { |
| 1306 | UInt i; |
| 1307 | for (i = 0 ; i < NUM_HWCAPS; ++i) { |
| 1308 | if (hwcaps & hwcaps_list[i].hwcaps_bit) |
| 1309 | p = p + vex_sprintf(p, "-%s", hwcaps_list[i].name); |
| 1310 | } |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1311 | } |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1312 | return buf; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1313 | } |
| 1314 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1315 | static const HChar* show_hwcaps_amd64 ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1316 | { |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1317 | static const HChar prefix[] = "amd64"; |
| 1318 | static const struct { |
| 1319 | UInt hwcaps_bit; |
| 1320 | HChar name[7]; |
| 1321 | } hwcaps_list[] = { |
| 1322 | { VEX_HWCAPS_AMD64_CX16, "cx16" }, |
| 1323 | { VEX_HWCAPS_AMD64_LZCNT, "lzcnt" }, |
| 1324 | { VEX_HWCAPS_AMD64_RDTSCP, "rdtscp" }, |
| 1325 | { VEX_HWCAPS_AMD64_SSE3, "sse3" }, |
| 1326 | { VEX_HWCAPS_AMD64_AVX, "avx" }, |
| 1327 | { VEX_HWCAPS_AMD64_AVX2, "avx2" }, |
| 1328 | { VEX_HWCAPS_AMD64_BMI, "bmi" }, |
| 1329 | }; |
| 1330 | /* Allocate a large enough buffer */ |
| 1331 | static HChar buf[sizeof prefix + |
| 1332 | NUM_HWCAPS * (sizeof hwcaps_list[0].name + 1) + 1]; // '\0' |
| 1333 | if (buf[0] != '\0') return buf; /* already constructed */ |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1334 | |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1335 | HChar *p = buf + vex_sprintf(buf, "%s", prefix); |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1336 | |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1337 | if (hwcaps == 0) { |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1338 | vex_sprintf(p, "-%s", "sse2"); |
| 1339 | } else { |
| 1340 | UInt i; |
| 1341 | for (i = 0 ; i < NUM_HWCAPS; ++i) { |
| 1342 | if (hwcaps & hwcaps_list[i].hwcaps_bit) |
| 1343 | p = p + vex_sprintf(p, "-%s", hwcaps_list[i].name); |
| 1344 | } |
sewardj | 536fbab | 2010-07-29 15:39:05 +0000 | [diff] [blame] | 1345 | } |
sewardj | 818c730 | 2013-03-26 13:53:18 +0000 | [diff] [blame] | 1346 | return buf; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1347 | } |
| 1348 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1349 | static const HChar* show_hwcaps_ppc32 ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1350 | { |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1351 | static const HChar prefix[] = "ppc32-int"; |
| 1352 | static const struct { |
| 1353 | UInt hwcaps_bit; |
| 1354 | HChar name[8]; |
| 1355 | } hwcaps_list[] = { |
| 1356 | { VEX_HWCAPS_PPC32_F, "flt" }, |
| 1357 | { VEX_HWCAPS_PPC32_V, "vmx" }, |
| 1358 | { VEX_HWCAPS_PPC32_FX, "FX" }, |
| 1359 | { VEX_HWCAPS_PPC32_GX, "GX" }, |
| 1360 | { VEX_HWCAPS_PPC32_VX, "VX" }, |
| 1361 | { VEX_HWCAPS_PPC32_DFP, "DFP" }, |
| 1362 | { VEX_HWCAPS_PPC32_ISA2_07, "ISA2_07" }, |
| 1363 | }; |
| 1364 | /* Allocate a large enough buffer */ |
| 1365 | static HChar buf[sizeof prefix + |
| 1366 | NUM_HWCAPS * (sizeof hwcaps_list[0].name + 1) + 1]; // '\0' |
| 1367 | if (buf[0] != '\0') return buf; /* already constructed */ |
carll | 0c74bb5 | 2013-08-12 18:01:40 +0000 | [diff] [blame] | 1368 | |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1369 | HChar *p = buf + vex_sprintf(buf, "%s", prefix); |
| 1370 | |
| 1371 | if (hwcaps == 0) return buf; |
| 1372 | |
| 1373 | UInt i; |
| 1374 | for (i = 0 ; i < NUM_HWCAPS; ++i) { |
| 1375 | if (hwcaps & hwcaps_list[i].hwcaps_bit) |
| 1376 | p = p + vex_sprintf(p, "-%s", hwcaps_list[i].name); |
| 1377 | } |
| 1378 | return buf; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1379 | } |
| 1380 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1381 | static const HChar* show_hwcaps_ppc64 ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1382 | { |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1383 | static const HChar prefix[] = "ppc64-int-flt"; |
| 1384 | static const struct { |
| 1385 | UInt hwcaps_bit; |
| 1386 | HChar name[8]; |
| 1387 | } hwcaps_list[] = { |
| 1388 | { VEX_HWCAPS_PPC64_FX, "FX" }, |
| 1389 | { VEX_HWCAPS_PPC64_GX, "GX" }, |
| 1390 | { VEX_HWCAPS_PPC64_V, "vmx" }, |
| 1391 | { VEX_HWCAPS_PPC64_DFP, "DFP" }, |
| 1392 | { VEX_HWCAPS_PPC64_ISA2_07, "ISA2_07" }, |
| 1393 | }; |
| 1394 | /* Allocate a large enough buffer */ |
| 1395 | static HChar buf[sizeof prefix + |
| 1396 | NUM_HWCAPS * (sizeof hwcaps_list[0].name + 1) + 1]; // '\0' |
| 1397 | if (buf[0] != '\0') return buf; /* already constructed */ |
| 1398 | |
| 1399 | HChar *p = buf + vex_sprintf(buf, "%s", prefix); |
| 1400 | |
| 1401 | if (hwcaps == 0) return buf; |
| 1402 | |
| 1403 | UInt i; |
| 1404 | for (i = 0 ; i < NUM_HWCAPS; ++i) { |
| 1405 | if (hwcaps & hwcaps_list[i].hwcaps_bit) |
| 1406 | p = p + vex_sprintf(p, "-%s", hwcaps_list[i].name); |
| 1407 | } |
| 1408 | return buf; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1409 | } |
| 1410 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1411 | static const HChar* show_hwcaps_arm ( UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1412 | { |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1413 | static const HChar prefix[] = "ARM"; |
| 1414 | static const struct { |
| 1415 | UInt hwcaps_bit; |
| 1416 | HChar name[6]; |
| 1417 | } hwcaps_list[] = { |
| 1418 | { VEX_HWCAPS_ARM_NEON, "neon" }, |
| 1419 | { VEX_HWCAPS_ARM_VFP | VEX_HWCAPS_ARM_VFP2 | VEX_HWCAPS_ARM_VFP3, "vfp" }, |
| 1420 | }; |
| 1421 | /* Allocate a large enough buffer */ |
| 1422 | static HChar buf[sizeof prefix + 12 + // level |
| 1423 | NUM_HWCAPS * (sizeof hwcaps_list[0].name + 1) + 1]; // '\0' |
| 1424 | if (buf[0] != '\0') return buf; /* already constructed */ |
| 1425 | |
| 1426 | HChar *p; |
| 1427 | UInt i, level; |
| 1428 | |
| 1429 | level = VEX_ARM_ARCHLEVEL(hwcaps); |
| 1430 | |
| 1431 | p = buf + vex_sprintf(buf, "%sv%u", prefix, level); |
| 1432 | for (i = 0 ; i < NUM_HWCAPS; ++i) { |
| 1433 | if (hwcaps & hwcaps_list[i].hwcaps_bit) |
| 1434 | p = p + vex_sprintf(p, "-%s", hwcaps_list[i].name); |
sewardj | ec0d9a0 | 2010-08-22 12:54:56 +0000 | [diff] [blame] | 1435 | } |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1436 | return buf; |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1437 | } |
| 1438 | |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1439 | static const HChar* show_hwcaps_arm64 ( UInt hwcaps ) |
| 1440 | { |
| 1441 | /* Since there are no variants, just insist that hwcaps is zero, |
| 1442 | and declare it invalid otherwise. */ |
| 1443 | if (hwcaps == 0) |
| 1444 | return "baseline"; |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1445 | return "Unsupported"; |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1446 | } |
| 1447 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1448 | static const HChar* show_hwcaps_s390x ( UInt hwcaps ) |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1449 | { |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1450 | static const HChar prefix[] = "s390x"; |
florian | 9061eb3 | 2012-12-09 17:53:45 +0000 | [diff] [blame] | 1451 | static const struct { |
| 1452 | UInt hwcaps_bit; |
| 1453 | HChar name[6]; |
| 1454 | } hwcaps_list[] = { |
| 1455 | { VEX_HWCAPS_S390X_LDISP, "ldisp" }, |
| 1456 | { VEX_HWCAPS_S390X_EIMM, "eimm" }, |
| 1457 | { VEX_HWCAPS_S390X_GIE, "gie" }, |
| 1458 | { VEX_HWCAPS_S390X_DFP, "dfp" }, |
| 1459 | { VEX_HWCAPS_S390X_FGX, "fgx" }, |
| 1460 | { VEX_HWCAPS_S390X_STFLE, "stfle" }, |
| 1461 | { VEX_HWCAPS_S390X_ETF2, "etf2" }, |
| 1462 | { VEX_HWCAPS_S390X_ETF3, "etf3" }, |
| 1463 | { VEX_HWCAPS_S390X_STCKF, "stckf" }, |
| 1464 | { VEX_HWCAPS_S390X_FPEXT, "fpext" }, |
| 1465 | { VEX_HWCAPS_S390X_LSC, "lsc" }, |
florian | 78d5ef7 | 2013-05-11 15:02:58 +0000 | [diff] [blame] | 1466 | { VEX_HWCAPS_S390X_PFPO, "pfpo" }, |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1467 | }; |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1468 | /* Allocate a large enough buffer */ |
florian | 9061eb3 | 2012-12-09 17:53:45 +0000 | [diff] [blame] | 1469 | static HChar buf[sizeof prefix + |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1470 | NUM_HWCAPS * (sizeof hwcaps_list[0].name + 1) + 1]; // '\0' |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1471 | |
| 1472 | if (buf[0] != '\0') return buf; /* already constructed */ |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1473 | |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1474 | HChar *p; |
| 1475 | UInt i; |
| 1476 | |
sewardj | 652b56a | 2011-04-13 15:38:17 +0000 | [diff] [blame] | 1477 | hwcaps = VEX_HWCAPS_S390X(hwcaps); |
| 1478 | |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1479 | p = buf + vex_sprintf(buf, "%s", prefix); |
florian | 9061eb3 | 2012-12-09 17:53:45 +0000 | [diff] [blame] | 1480 | for (i = 0 ; i < NUM_HWCAPS; ++i) { |
| 1481 | if (hwcaps & hwcaps_list[i].hwcaps_bit) |
| 1482 | p = p + vex_sprintf(p, "-%s", hwcaps_list[i].name); |
| 1483 | } |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1484 | |
sewardj | d07b856 | 2011-04-27 11:58:22 +0000 | [diff] [blame] | 1485 | /* If there are no facilities, add "zarch" */ |
| 1486 | if (hwcaps == 0) |
| 1487 | vex_sprintf(p, "-%s", "zarch"); |
| 1488 | |
| 1489 | return buf; |
sewardj | 2019a97 | 2011-03-07 16:04:07 +0000 | [diff] [blame] | 1490 | } |
| 1491 | |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1492 | static const HChar* show_hwcaps_mips32 ( UInt hwcaps ) |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1493 | { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1494 | /* MIPS baseline. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1495 | if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_MIPS) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1496 | /* MIPS baseline with dspr2. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1497 | if (VEX_MIPS_PROC_DSP2(hwcaps)) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1498 | return "MIPS-baseline-dspr2"; |
| 1499 | } |
| 1500 | /* MIPS baseline with dsp. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1501 | if (VEX_MIPS_PROC_DSP(hwcaps)) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1502 | return "MIPS-baseline-dsp"; |
| 1503 | } |
| 1504 | return "MIPS-baseline"; |
| 1505 | } |
| 1506 | |
| 1507 | /* Broadcom baseline. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1508 | if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_BROADCOM) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1509 | return "Broadcom-baseline"; |
| 1510 | } |
| 1511 | |
| 1512 | /* Netlogic baseline. */ |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1513 | if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_NETLOGIC) { |
dejanj | c3fee0d | 2013-07-25 09:08:03 +0000 | [diff] [blame] | 1514 | return "Netlogic-baseline"; |
| 1515 | } |
| 1516 | |
petarj | bc7d6f4 | 2013-09-16 18:11:59 +0000 | [diff] [blame] | 1517 | /* Cavium baseline. */ |
| 1518 | if (VEX_MIPS_COMP_ID(hwcaps) == VEX_PRID_COMP_CAVIUM) { |
| 1519 | return "Cavium-baseline"; |
| 1520 | } |
| 1521 | |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1522 | return "Unsupported baseline"; |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1523 | } |
| 1524 | |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1525 | static const HChar* show_hwcaps_mips64 ( UInt hwcaps ) |
| 1526 | { |
| 1527 | return "mips64-baseline"; |
| 1528 | } |
| 1529 | |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1530 | #undef NUM_HWCAPS |
| 1531 | |
| 1532 | /* Thie function must not return NULL. */ |
florian | 55085f8 | 2012-11-21 00:36:55 +0000 | [diff] [blame] | 1533 | static const HChar* show_hwcaps ( VexArch arch, UInt hwcaps ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1534 | { |
| 1535 | switch (arch) { |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1536 | case VexArchX86: return show_hwcaps_x86(hwcaps); |
| 1537 | case VexArchAMD64: return show_hwcaps_amd64(hwcaps); |
| 1538 | case VexArchPPC32: return show_hwcaps_ppc32(hwcaps); |
| 1539 | case VexArchPPC64: return show_hwcaps_ppc64(hwcaps); |
| 1540 | case VexArchARM: return show_hwcaps_arm(hwcaps); |
sewardj | bbcf188 | 2014-01-12 12:49:10 +0000 | [diff] [blame] | 1541 | case VexArchARM64: return show_hwcaps_arm64(hwcaps); |
sewardj | d0e5fe7 | 2012-06-07 08:51:02 +0000 | [diff] [blame] | 1542 | case VexArchS390X: return show_hwcaps_s390x(hwcaps); |
| 1543 | case VexArchMIPS32: return show_hwcaps_mips32(hwcaps); |
petarj | b92a954 | 2013-02-27 22:57:17 +0000 | [diff] [blame] | 1544 | case VexArchMIPS64: return show_hwcaps_mips64(hwcaps); |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1545 | default: return NULL; |
| 1546 | } |
| 1547 | } |
| 1548 | |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1549 | /* To be used to complain about hwcaps we cannot handle */ |
| 1550 | __attribute__((noreturn)) |
| 1551 | static void invalid_hwcaps ( VexArch arch, UInt hwcaps, const HChar *message ) |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1552 | { |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1553 | vfatal("\nVEX: %s" |
| 1554 | " Found: %s\n", message, show_hwcaps(arch, hwcaps)); |
| 1555 | } |
| 1556 | |
| 1557 | /* This function will not return iff the hwcaps don't pass the test. */ |
| 1558 | static void check_hwcaps ( VexArch arch, UInt hwcaps ) |
| 1559 | { |
| 1560 | switch (arch) { |
| 1561 | case VexArchX86: { |
| 1562 | if (hwcaps == 0) return; // baseline |
| 1563 | |
| 1564 | /* Monotonic: SSE3 > SSE2 > SSE1 > MMXEXT > baseline. */ |
| 1565 | static const UInt extras[] = { |
| 1566 | VEX_HWCAPS_X86_MMXEXT, VEX_HWCAPS_X86_SSE1, VEX_HWCAPS_X86_SSE2, |
| 1567 | VEX_HWCAPS_X86_SSE3 |
| 1568 | }; |
| 1569 | |
| 1570 | UInt i, caps = 0; |
| 1571 | for (i = 0; i < sizeof extras / sizeof extras[0]; ++i) { |
| 1572 | caps |= extras[i]; |
| 1573 | if (caps == hwcaps) return; |
| 1574 | if ((caps & VEX_HWCAPS_X86_SSE2) != 0) { |
| 1575 | if ((caps & VEX_HWCAPS_X86_LZCNT) != 0) return; |
| 1576 | } |
| 1577 | } |
| 1578 | invalid_hwcaps(arch, hwcaps, "Cannot handle capabilities\n"); |
| 1579 | } |
| 1580 | |
| 1581 | case VexArchAMD64: { |
florian | f3652c9 | 2014-12-10 16:10:24 +0000 | [diff] [blame] | 1582 | /* SSE3 and CX16 are orthogonal and > baseline, although we really |
| 1583 | don't expect to come across anything which can do SSE3 but can't |
| 1584 | do CX16. Still, we can handle that case. LZCNT is similarly |
| 1585 | orthogonal. */ |
| 1586 | |
| 1587 | /* Throw out obviously stupid cases: */ |
| 1588 | Bool have_sse3 = (hwcaps & VEX_HWCAPS_AMD64_SSE3) != 0; |
| 1589 | Bool have_avx = (hwcaps & VEX_HWCAPS_AMD64_AVX) != 0; |
| 1590 | Bool have_bmi = (hwcaps & VEX_HWCAPS_AMD64_BMI) != 0; |
| 1591 | Bool have_avx2 = (hwcaps & VEX_HWCAPS_AMD64_AVX2) != 0; |
| 1592 | |
| 1593 | /* AVX without SSE3 */ |
| 1594 | if (have_avx && !have_sse3) |
| 1595 | invalid_hwcaps(arch, hwcaps, |
| 1596 | "Support for AVX requires SSE3 capabilities\n"); |
| 1597 | /* AVX2 or BMI without AVX */ |
| 1598 | if (have_avx2 && !have_avx) |
| 1599 | invalid_hwcaps(arch, hwcaps, |
| 1600 | "Support for AVX2 requires AVX capabilities\n"); |
| 1601 | if (have_bmi && !have_avx) |
| 1602 | invalid_hwcaps(arch, hwcaps, |
| 1603 | "Support for BMI requires AVX capabilities\n"); |
| 1604 | return; |
| 1605 | } |
| 1606 | |
| 1607 | case VexArchPPC32: { |
| 1608 | /* Monotonic with complications. Basically V > F > baseline, |
| 1609 | but once you have F then you can have FX or GX too. */ |
| 1610 | if (hwcaps == 0) return; // baseline |
| 1611 | |
| 1612 | if ((hwcaps & VEX_HWCAPS_PPC32_F) == 0) |
| 1613 | invalid_hwcaps(arch, hwcaps, |
| 1614 | "Missing floating point capability\n"); |
| 1615 | /* V, FX, and GX can appear in any combination */ |
| 1616 | |
| 1617 | /* DFP requires V and FX and GX */ |
| 1618 | UInt v_fx_gx = VEX_HWCAPS_PPC32_V | VEX_HWCAPS_PPC32_FX | |
| 1619 | VEX_HWCAPS_PPC32_GX; |
| 1620 | Bool has_v_fx_gx = (hwcaps & v_fx_gx) == v_fx_gx; |
| 1621 | |
| 1622 | if ((hwcaps & VEX_HWCAPS_PPC32_DFP) && ! has_v_fx_gx) |
| 1623 | invalid_hwcaps(arch, hwcaps, |
| 1624 | "DFP requires VMX and FX and GX capabilities\n"); |
| 1625 | |
| 1626 | /* VX requires V and FX and GX */ |
| 1627 | if ((hwcaps & VEX_HWCAPS_PPC32_VX) && ! has_v_fx_gx) |
| 1628 | invalid_hwcaps(arch, hwcaps, |
| 1629 | "VX requires VMX and FX and GX capabilities\n"); |
| 1630 | |
| 1631 | /* ISA2_07 requires everything else */ |
| 1632 | if ((hwcaps & VEX_HWCAPS_PPC32_ISA2_07) != 0) { |
| 1633 | if (! has_v_fx_gx) |
| 1634 | invalid_hwcaps(arch, hwcaps, |
| 1635 | "ISA2_07 requires VMX and FX and GX capabilities\n"); |
| 1636 | if (! (hwcaps & VEX_HWCAPS_PPC32_VX)) |
| 1637 | invalid_hwcaps(arch, hwcaps, |
| 1638 | "ISA2_07 requires VX capabilities\n"); |
| 1639 | if (! (hwcaps & VEX_HWCAPS_PPC32_DFP)) |
| 1640 | invalid_hwcaps(arch, hwcaps, |
| 1641 | "ISA2_07 requires DFP capabilities\n"); |
| 1642 | } |
| 1643 | return; |
| 1644 | } |
| 1645 | |
| 1646 | case VexArchPPC64: { |
| 1647 | /* Monotonic with complications. Basically V > baseline(==F), |
| 1648 | but once you have F then you can have FX or GX too. */ |
| 1649 | if (hwcaps == 0) return; // baseline |
| 1650 | |
| 1651 | /* V, FX, and GX can appear in any combination */ |
| 1652 | |
| 1653 | /* DFP requires V and FX and GX */ |
| 1654 | UInt v_fx_gx = VEX_HWCAPS_PPC64_V | VEX_HWCAPS_PPC64_FX | |
| 1655 | VEX_HWCAPS_PPC64_GX; |
| 1656 | Bool has_v_fx_gx = (hwcaps & v_fx_gx) == v_fx_gx; |
| 1657 | |
| 1658 | if ((hwcaps & VEX_HWCAPS_PPC64_DFP) && ! has_v_fx_gx) |
| 1659 | invalid_hwcaps(arch, hwcaps, |
| 1660 | "DFP requires VMX and FX and GX capabilities\n"); |
| 1661 | |
| 1662 | /* VX requires V and FX and GX */ |
| 1663 | if ((hwcaps & VEX_HWCAPS_PPC32_VX) && ! has_v_fx_gx) |
| 1664 | invalid_hwcaps(arch, hwcaps, |
| 1665 | "VX requires VMX and FX and GX capabilities\n"); |
| 1666 | |
| 1667 | /* ISA2_07 requires everything else */ |
| 1668 | if ((hwcaps & VEX_HWCAPS_PPC64_ISA2_07) != 0) { |
| 1669 | if (! has_v_fx_gx) |
| 1670 | invalid_hwcaps(arch, hwcaps, |
| 1671 | "ISA2_07 requires VMX and FX and GX capabilities\n"); |
| 1672 | if (! (hwcaps & VEX_HWCAPS_PPC64_VX)) |
| 1673 | invalid_hwcaps(arch, hwcaps, |
| 1674 | "ISA2_07 requires VX capabilities\n"); |
| 1675 | if (! (hwcaps & VEX_HWCAPS_PPC64_DFP)) |
| 1676 | invalid_hwcaps(arch, hwcaps, |
| 1677 | "ISA2_07 requires DFP capabilities\n"); |
| 1678 | } |
| 1679 | return; |
| 1680 | } |
| 1681 | |
| 1682 | case VexArchARM: { |
| 1683 | Bool NEON = ((hwcaps & VEX_HWCAPS_ARM_NEON) != 0); |
| 1684 | UInt level = VEX_ARM_ARCHLEVEL(hwcaps); |
| 1685 | |
| 1686 | switch (level) { |
| 1687 | case 5: |
| 1688 | if (NEON) |
| 1689 | invalid_hwcaps(arch, hwcaps, |
| 1690 | "NEON instructions are not supported for ARMv5.\n"); |
| 1691 | return; |
| 1692 | case 6: |
| 1693 | if (NEON) |
| 1694 | invalid_hwcaps(arch, hwcaps, |
| 1695 | "NEON instructions are not supported for ARMv6.\n"); |
| 1696 | return; |
| 1697 | case 7: |
| 1698 | return; |
| 1699 | default: |
| 1700 | invalid_hwcaps(arch, hwcaps, |
| 1701 | "ARM architecture level is not supported.\n"); |
| 1702 | } |
| 1703 | } |
| 1704 | |
| 1705 | case VexArchARM64: |
| 1706 | if (hwcaps != 0) |
| 1707 | invalid_hwcaps(arch, hwcaps, |
| 1708 | "Unsupported hardware capabilities.\n"); |
| 1709 | return; |
| 1710 | |
| 1711 | case VexArchS390X: |
| 1712 | if (! s390_host_has_ldisp) |
| 1713 | invalid_hwcaps(arch, hwcaps, |
| 1714 | "Host does not have long displacement facility.\n"); |
| 1715 | return; |
| 1716 | |
| 1717 | case VexArchMIPS32: |
| 1718 | switch (VEX_MIPS_COMP_ID(hwcaps)) { |
| 1719 | case VEX_PRID_COMP_MIPS: |
| 1720 | case VEX_PRID_COMP_BROADCOM: |
| 1721 | case VEX_PRID_COMP_NETLOGIC: |
| 1722 | return; |
| 1723 | default: |
| 1724 | invalid_hwcaps(arch, hwcaps, "Unsupported baseline\n"); |
| 1725 | } |
| 1726 | |
| 1727 | case VexArchMIPS64: |
| 1728 | return; |
| 1729 | |
| 1730 | default: |
| 1731 | vpanic("unknown architecture"); |
florian | dc6e747 | 2014-12-08 14:01:33 +0000 | [diff] [blame] | 1732 | } |
sewardj | 5117ce1 | 2006-01-27 21:20:15 +0000 | [diff] [blame] | 1733 | } |
| 1734 | |
| 1735 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1736 | /*---------------------------------------------------------------*/ |
sewardj | cef7d3e | 2009-07-02 12:21:59 +0000 | [diff] [blame] | 1737 | /*--- end main_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1738 | /*---------------------------------------------------------------*/ |