Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / b190e1b74b422b1488c1735ac3557e0e89377dcf / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: 61e6bc502c17d4cab81849e6a922e2caba467dca [file] [log] [blame]
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]1// Group template arguments that can be derived from the vector type (EltNum x
2// EltVT). These are things like the register class for the writemask, etc.
3// The idea is to pass one of these as the template argument rather than the
4// individual arguments.
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]5class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]6 string suffix = ""> {
7 RegisterClass RC = rc;
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]8 int NumElts = numelts;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]9
10 // Corresponding mask register class.
11 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
12
13 // Corresponding write-mask register class.
14 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
15
16 // The GPR register class that can hold the write mask. Use GR8 for fewer
17 // than 8 elements. Use shift-right and equal to work around the lack of
18 // !lt in tablegen.
19 RegisterClass MRC =
20 !cast<RegisterClass>("GR" #
21 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
22
23 // Suffix used in the instruction mnemonic.
24 string Suffix = suffix;
25
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]26 string VTName = "v" # NumElts # EltVT;
27
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]28 // The vector VT.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]29 ValueType VT = !cast<ValueType>(VTName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]30
31 string EltTypeName = !cast<string>(EltVT);
32 // Size of the element type in bits, e.g. 32 for v16i32.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]33 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
34 int EltSize = EltVT.Size;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]35
36 // "i" for integer types and "f" for floating-point types
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]37 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]38
39 // Size of RC in bits, e.g. 512 for VR512.
40 int Size = VT.Size;
41
42 // The corresponding memory operand, e.g. i512mem for VR512.
43 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]44 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
45
46 // Load patterns
47 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
48 // due to load promotion during legalization
49 PatFrag LdFrag = !cast<PatFrag>("load" #
50 !if (!eq (TypeVariantName, "i"),
51 !if (!eq (Size, 128), "v2i64",
52 !if (!eq (Size, 256), "v4i64",
53 VTName)), VTName));
54 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]55
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]56 // Load patterns used for memory operands. We only have this defined in
57 // case of i64 element types for sub-512 integer vectors. For now, keep
58 // MemOpFrag undefined in these cases.
59 PatFrag MemOpFrag =
60 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
62 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
63
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]64 // The corresponding float type, e.g. v16f32 for v16i32
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]65 // Note: For EltSize < 32, FloatVT is illegal and TableGen
66 // fails to compile, so we choose FloatVT = VT
67 ValueType FloatVT = !cast<ValueType>(
68 !if (!eq (!srl(EltSize,5),0),
69 VTName,
70 !if (!eq(TypeVariantName, "i"),
71 "v" # NumElts # "f" # EltSize,
72 VTName)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]73
74 // The string to specify embedded broadcast in assembly.
75 string BroadcastStr = "{1to" # NumElts # "}";
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]76
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]77 // 8-bit compressed displacement tuple/subvector format. This is only
78 // defined for NumElts <= 8.
79 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
80 !cast<CD8VForm>("CD8VT" # NumElts), ?);
81
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]82 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
83 !if (!eq (Size, 256), sub_ymm, ?));
84
85 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
86 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
87 SSEPackedInt));
Adam Nemet09377232014-10-08 23:25:31 +0000[diff] [blame]88
89 // A vector type of the same width with element type i32. This is used to
90 // create the canonical constant zero node ImmAllZerosV.
91 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
92 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]93}
94
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]95def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
96def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]97def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
98def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]99def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
100def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]101
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]102// "x" in v32i8x_info means RC = VR256X
103def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
104def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
105def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
106def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
Robert Khasanov3e534c92014-10-28 16:37:13 +0000[diff] [blame]107def v8f32x_info : X86VectorVTInfo<8, f32, VR256X, "ps">;
108def v4f64x_info : X86VectorVTInfo<4, f64, VR256X, "pd">;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]109
110def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
111def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
112def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
113def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
Robert Khasanov3e534c92014-10-28 16:37:13 +0000[diff] [blame]114def v4f32x_info : X86VectorVTInfo<4, f32, VR128X, "ps">;
115def v2f64x_info : X86VectorVTInfo<2, f64, VR128X, "pd">;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]116
117class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
118 X86VectorVTInfo i128> {
119 X86VectorVTInfo info512 = i512;
120 X86VectorVTInfo info256 = i256;
121 X86VectorVTInfo info128 = i128;
122}
123
124def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
125 v16i8x_info>;
126def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
127 v8i16x_info>;
128def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
129 v4i32x_info>;
130def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
131 v2i64x_info>;
132
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame]133// This multiclass generates the masking variants from the non-masking
134// variant. It only provides the assembly pieces for the masking variants.
135// It assumes custom ISel patterns for masking which can be provided as
136// template arguments.
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]137multiclass AVX512_maskable_custom<bits<8> O, Format F,
138 dag Outs,
139 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
140 string OpcodeStr,
141 string AttSrcAsm, string IntelSrcAsm,
142 list<dag> Pattern,
143 list<dag> MaskingPattern,
144 list<dag> ZeroMaskingPattern,
145 string MaskingConstraint = "",
146 InstrItinClass itin = NoItinerary,
147 bit IsCommutable = 0> {
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame]148 let isCommutable = IsCommutable in
149 def NAME: AVX512<O, F, Outs, Ins,
150 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
151 "$dst, "#IntelSrcAsm#"}",
152 Pattern, itin>;
153
154 // Prefer over VMOV*rrk Pat<>
155 let AddedComplexity = 20 in
156 def NAME#k: AVX512<O, F, Outs, MaskingIns,
157 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
158 "$dst {${mask}}, "#IntelSrcAsm#"}",
159 MaskingPattern, itin>,
160 EVEX_K {
161 // In case of the 3src subclass this is overridden with a let.
162 string Constraints = MaskingConstraint;
163 }
164 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
165 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
166 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
167 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
168 ZeroMaskingPattern,
169 itin>,
170 EVEX_KZ;
171}
172
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]173
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]174// Common base class of AVX512_maskable and AVX512_maskable_3src.
175multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
176 dag Outs,
177 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
178 string OpcodeStr,
179 string AttSrcAsm, string IntelSrcAsm,
180 dag RHS, dag MaskingRHS,
181 string MaskingConstraint = "",
182 InstrItinClass itin = NoItinerary,
183 bit IsCommutable = 0> :
184 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
185 AttSrcAsm, IntelSrcAsm,
186 [(set _.RC:$dst, RHS)],
187 [(set _.RC:$dst, MaskingRHS)],
188 [(set _.RC:$dst,
189 (vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
190 MaskingConstraint, NoItinerary, IsCommutable>;
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]191
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]192// This multiclass generates the unconditional/non-masking, the masking and
193// the zero-masking variant of the instruction. In the masking case, the
194// perserved vector elements come from a new dummy input operand tied to $dst.
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]195multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
196 dag Outs, dag Ins, string OpcodeStr,
197 string AttSrcAsm, string IntelSrcAsm,
198 dag RHS, InstrItinClass itin = NoItinerary,
199 bit IsCommutable = 0> :
200 AVX512_maskable_common<O, F, _, Outs, Ins,
201 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
202 !con((ins _.KRCWM:$mask), Ins),
203 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
204 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
205 "$src0 = $dst", itin, IsCommutable>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]206
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]207// Similar to AVX512_maskable but in this case one of the source operands
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]208// ($src1) is already tied to $dst so we just use that for the preserved
209// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
210// $src1.
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]211multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
212 dag Outs, dag NonTiedIns, string OpcodeStr,
213 string AttSrcAsm, string IntelSrcAsm,
214 dag RHS> :
215 AVX512_maskable_common<O, F, _, Outs,
216 !con((ins _.RC:$src1), NonTiedIns),
217 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
218 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
219 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
220 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]221
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000[diff] [blame]222
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]223multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
224 dag Outs, dag Ins,
225 string OpcodeStr,
226 string AttSrcAsm, string IntelSrcAsm,
227 list<dag> Pattern> :
228 AVX512_maskable_custom<O, F, Outs, Ins,
229 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
230 !con((ins _.KRCWM:$mask), Ins),
231 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
232 "$src0 = $dst">;
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000[diff] [blame]233
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]234// Bitcasts between 512-bit vector types. Return the original type since
235// no instruction is needed for the conversion
236let Predicates = [HasAVX512] in {
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]237 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]238 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]239 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
240 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
241 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]242 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]243 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
244 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
245 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]246 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]247 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]248 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
249 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]250 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]251 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
252 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovsky40a77142014-08-11 09:59:08 +0000[diff] [blame]253 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]254 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
255 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]256 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]257 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
258 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
259 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
260 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
261 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
262 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
263 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
264 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
265 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
266 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
267 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]268
269 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
270 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
271 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
272 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
273 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
274 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
275 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
276 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
277 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
278 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
279 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
280 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
281 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
282 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
283 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
284 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
285 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
286 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
287 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
288 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
289 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
290 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
291 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
292 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
293 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
294 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
295 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
296 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
297 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
298 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
299
300// Bitcasts between 256-bit vector types. Return the original type since
301// no instruction is needed for the conversion
302 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
303 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
304 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
305 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
306 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
307 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
308 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
309 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
310 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
311 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
312 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
313 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
314 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
315 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
316 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
317 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
318 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
319 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
320 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
321 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
322 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
323 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
324 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
325 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
326 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
327 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
328 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
329 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
330 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
331 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
332}
333
334//
335// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
336//
337
338let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
339 isPseudo = 1, Predicates = [HasAVX512] in {
340def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
341 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
342}
343
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]344let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]345def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
346def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
347def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]348}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]349
350//===----------------------------------------------------------------------===//
351// AVX-512 - VECTOR INSERT
352//
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]353
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]354multiclass vinsert_for_size_no_alt<int Opcode,
355 X86VectorVTInfo From, X86VectorVTInfo To,
356 PatFrag vinsert_insert,
357 SDNodeXForm INSERT_get_vinsert_imm> {
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]358 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
359 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
360 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]361 "vinsert" # From.EltTypeName # "x" # From.NumElts #
362 "\t{$src3, $src2, $src1, $dst|"
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]363 "$dst, $src1, $src2, $src3}",
Adam Nemet4dca3ce2014-10-02 23:18:30 +0000[diff] [blame]364 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
365 (From.VT From.RC:$src2),
366 (iPTR imm)))]>,
367 EVEX_4V, EVEX_V512;
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]368
369 let mayLoad = 1 in
370 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
371 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]372 "vinsert" # From.EltTypeName # "x" # From.NumElts #
373 "\t{$src3, $src2, $src1, $dst|"
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]374 "$dst, $src1, $src2, $src3}",
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]375 []>,
376 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]377 }
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]378}
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]379
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]380multiclass vinsert_for_size<int Opcode,
381 X86VectorVTInfo From, X86VectorVTInfo To,
382 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
383 PatFrag vinsert_insert,
384 SDNodeXForm INSERT_get_vinsert_imm> :
385 vinsert_for_size_no_alt<Opcode, From, To,
386 vinsert_insert, INSERT_get_vinsert_imm> {
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]387 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]388 // vinserti32x4. Only add this if 64x2 and friends are not supported
389 // natively via AVX512DQ.
390 let Predicates = [NoDQI] in
391 def : Pat<(vinsert_insert:$ins
392 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
393 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
394 VR512:$src1, From.RC:$src2,
395 (INSERT_get_vinsert_imm VR512:$ins)))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]396}
397
Adam Nemetb1c3ef42014-10-15 23:42:04 +0000[diff] [blame]398multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
399 ValueType EltVT64, int Opcode256> {
400 defm NAME # "32x4" : vinsert_for_size<Opcode128,
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]401 X86VectorVTInfo< 4, EltVT32, VR128X>,
402 X86VectorVTInfo<16, EltVT32, VR512>,
403 X86VectorVTInfo< 2, EltVT64, VR128X>,
404 X86VectorVTInfo< 8, EltVT64, VR512>,
405 vinsert128_insert,
406 INSERT_get_vinsert128_imm>;
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]407 let Predicates = [HasDQI] in
408 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
409 X86VectorVTInfo< 2, EltVT64, VR128X>,
410 X86VectorVTInfo< 8, EltVT64, VR512>,
411 vinsert128_insert,
412 INSERT_get_vinsert128_imm>, VEX_W;
Adam Nemetb1c3ef42014-10-15 23:42:04 +0000[diff] [blame]413 defm NAME # "64x4" : vinsert_for_size<Opcode256,
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]414 X86VectorVTInfo< 4, EltVT64, VR256X>,
415 X86VectorVTInfo< 8, EltVT64, VR512>,
416 X86VectorVTInfo< 8, EltVT32, VR256>,
417 X86VectorVTInfo<16, EltVT32, VR512>,
418 vinsert256_insert,
419 INSERT_get_vinsert256_imm>, VEX_W;
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]420 let Predicates = [HasDQI] in
421 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
422 X86VectorVTInfo< 8, EltVT32, VR256X>,
423 X86VectorVTInfo<16, EltVT32, VR512>,
424 vinsert256_insert,
425 INSERT_get_vinsert256_imm>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]426}
427
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]428defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
429defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]430
431// vinsertps - insert f32 to XMM
432def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]433 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]434 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]435 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]436 EVEX_4V;
437def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]438 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]439 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]440 [(set VR128X:$dst, (X86insertps VR128X:$src1,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]441 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
442 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
443
444//===----------------------------------------------------------------------===//
445// AVX-512 VECTOR EXTRACT
446//---
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]447
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]448multiclass vextract_for_size<int Opcode,
449 X86VectorVTInfo From, X86VectorVTInfo To,
450 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
451 PatFrag vextract_extract,
452 SDNodeXForm EXTRACT_get_vextract_imm> {
453 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]454 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000[diff] [blame]455 (ins VR512:$src1, i8imm:$idx),
456 "vextract" # To.EltTypeName # "x4",
457 "$idx, $src1", "$src1, $idx",
458 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
459 (iPTR imm)))]>,
460 AVX512AIi8Base, EVEX, EVEX_V512;
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]461 let mayStore = 1 in
462 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
463 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
464 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
465 "$dst, $src1, $src2}",
466 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
467 }
468
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]469 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
470 // vextracti32x4
471 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
472 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
473 VR512:$src1,
474 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
475
476 // A 128/256-bit subvector extract from the first 512-bit vector position is
477 // a subregister copy that needs no instruction.
478 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
479 (To.VT
480 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
481
482 // And for the alternative types.
483 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
484 (AltTo.VT
485 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
Adam Nemet47b2d5f2014-10-08 23:25:37 +0000[diff] [blame]486
487 // Intrinsic call with masking.
488 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
489 "x4_512")
490 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
491 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
492 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
493 VR512:$src1, imm:$idx)>;
494
495 // Intrinsic call with zero-masking.
496 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
497 "x4_512")
498 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
499 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
500 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
501 VR512:$src1, imm:$idx)>;
502
503 // Intrinsic call without masking.
504 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
505 "x4_512")
506 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
507 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
508 VR512:$src1, imm:$idx)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]509}
510
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]511multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
512 ValueType EltVT64, int Opcode64> {
513 defm NAME # "32x4" : vextract_for_size<Opcode32,
514 X86VectorVTInfo<16, EltVT32, VR512>,
515 X86VectorVTInfo< 4, EltVT32, VR128X>,
516 X86VectorVTInfo< 8, EltVT64, VR512>,
517 X86VectorVTInfo< 2, EltVT64, VR128X>,
518 vextract128_extract,
519 EXTRACT_get_vextract128_imm>;
520 defm NAME # "64x4" : vextract_for_size<Opcode64,
521 X86VectorVTInfo< 8, EltVT64, VR512>,
522 X86VectorVTInfo< 4, EltVT64, VR256X>,
523 X86VectorVTInfo<16, EltVT32, VR512>,
524 X86VectorVTInfo< 8, EltVT32, VR256>,
525 vextract256_extract,
526 EXTRACT_get_vextract256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]527}
528
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]529defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
530defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]531
532// A 128-bit subvector insert to the first 512-bit vector position
533// is a subregister copy that needs no instruction.
534def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
535 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
536 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
537 sub_ymm)>;
538def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
539 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
540 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
541 sub_ymm)>;
542def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
543 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
544 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
545 sub_ymm)>;
546def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
547 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
548 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
549 sub_ymm)>;
550
551def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
552 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
553def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
554 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
555def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
556 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
557def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
558 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
559
560// vextractps - extract 32 bits from XMM
561def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]562 (ins VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]563 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]564 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
565 EVEX;
566
567def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]568 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]569 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]570 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
Elena Demikhovsky2aafc222014-02-11 07:25:59 +0000[diff] [blame]571 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]572
573//===---------------------------------------------------------------------===//
574// AVX-512 BROADCAST
575//---
576multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
577 RegisterClass DestRC,
578 RegisterClass SrcRC, X86MemOperand x86memop> {
579 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]580 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]581 []>, EVEX;
582 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]583 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]584}
585let ExeDomain = SSEPackedSingle in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]586 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]587 VR128X, f32mem>,
588 EVEX_V512, EVEX_CD8<32, CD8VT1>;
589}
590
591let ExeDomain = SSEPackedDouble in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]592 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]593 VR128X, f64mem>,
594 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
595}
596
597def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
598 (VBROADCASTSSZrm addr:$src)>;
599def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
600 (VBROADCASTSDZrm addr:$src)>;
601
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]602def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
603 (VBROADCASTSSZrm addr:$src)>;
604def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
605 (VBROADCASTSDZrm addr:$src)>;
606
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]607multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
608 RegisterClass SrcRC, RegisterClass KRC> {
609 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]610 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]611 []>, EVEX, EVEX_V512;
612 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
613 (ins KRC:$mask, SrcRC:$src),
614 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]615 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]616 []>, EVEX, EVEX_V512, EVEX_KZ;
617}
618
619defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
620defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
621 VEX_W;
622
623def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
624 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
625
626def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
627 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
628
629def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
630 (VPBROADCASTDrZrr GR32:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]631def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
632 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]633def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
634 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]635def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
636 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]637
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]638def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
639 (VPBROADCASTDrZrr GR32:$src)>;
640def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
641 (VPBROADCASTQrZrr GR64:$src)>;
642
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]643def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
644 (v16i32 immAllZerosV), (i16 GR16:$mask))),
645 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
646def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
647 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
648 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
649
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]650multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
651 X86MemOperand x86memop, PatFrag ld_frag,
652 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
653 RegisterClass KRC> {
654 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]655 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]656 [(set DstRC:$dst,
657 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
658 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
659 VR128X:$src),
660 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]661 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]662 [(set DstRC:$dst,
663 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
664 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]665 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]666 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]667 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]668 [(set DstRC:$dst,
669 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
670 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
671 x86memop:$src),
672 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]673 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]674 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
675 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]676 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]677}
678
679defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
680 loadi32, VR512, v16i32, v4i32, VK16WM>,
681 EVEX_V512, EVEX_CD8<32, CD8VT1>;
682defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
683 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
684 EVEX_CD8<64, CD8VT1>;
685
Adam Nemet73f72e12014-06-27 00:43:38 +0000[diff] [blame]686multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
687 X86MemOperand x86memop, PatFrag ld_frag,
688 RegisterClass KRC> {
689 let mayLoad = 1 in {
690 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
691 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
692 []>, EVEX;
693 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
694 x86memop:$src),
695 !strconcat(OpcodeStr,
696 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
697 []>, EVEX, EVEX_KZ;
698 }
699}
700
701defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
702 i128mem, loadv2i64, VK16WM>,
703 EVEX_V512, EVEX_CD8<32, CD8VT4>;
704defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
705 i256mem, loadv4i64, VK16WM>, VEX_W,
706 EVEX_V512, EVEX_CD8<64, CD8VT4>;
707
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]708def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
709 (VPBROADCASTDZrr VR128X:$src)>;
710def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
711 (VPBROADCASTQZrr VR128X:$src)>;
712
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]713def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
714 (VBROADCASTSSZrr VR128X:$src)>;
715def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
716 (VBROADCASTSDZrr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]717
Robert Khasanovdd09a8f2014-10-28 12:28:51 +0000[diff] [blame]718def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
719 (VBROADCASTSSZrr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
720def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
721 (VBROADCASTSDZrr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
722
723def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
724 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
725def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
726 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
727
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]728def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
729 (VBROADCASTSSZrr VR128X:$src)>;
730def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
731 (VBROADCASTSDZrr VR128X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]732
733// Provide fallback in case the load node that is used in the patterns above
734// is used by additional users, which prevents the pattern selection.
735def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
736 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
737def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
738 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
739
740
741let Predicates = [HasAVX512] in {
742def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
743 (EXTRACT_SUBREG
744 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
745 addr:$src)), sub_ymm)>;
746}
747//===----------------------------------------------------------------------===//
748// AVX-512 BROADCAST MASK TO VECTOR REGISTER
749//---
750
751multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000[diff] [blame]752 RegisterClass KRC> {
753let Predicates = [HasCDI] in
754def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]755 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000[diff] [blame]756 []>, EVEX, EVEX_V512;
757
758let Predicates = [HasCDI, HasVLX] in {
759def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
760 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
761 []>, EVEX, EVEX_V128;
762def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
763 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
764 []>, EVEX, EVEX_V256;
765}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]766}
767
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]768let Predicates = [HasCDI] in {
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000[diff] [blame]769defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
770 VK16>;
771defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
772 VK8>, VEX_W;
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]773}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]774
775//===----------------------------------------------------------------------===//
776// AVX-512 - VPERM
777//
778// -- immediate form --
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]779multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
780 X86VectorVTInfo _> {
781 let ExeDomain = _.ExeDomain in {
782 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
783 (ins _.RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]784 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]785 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]786 [(set _.RC:$dst,
787 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]788 EVEX;
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]789 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
790 (ins _.MemOp:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]791 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]792 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]793 [(set _.RC:$dst,
794 (_.VT (OpNode (_.MemOpFrag addr:$src1),
795 (i8 imm:$src2))))]>,
796 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
797}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]798}
799
Adam Nemetcf7a4a22014-10-27 23:08:40 +0000[diff] [blame]800multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
801 X86VectorVTInfo Ctrl> :
802 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
803 let ExeDomain = _.ExeDomain in {
804 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
805 (ins _.RC:$src1, _.RC:$src2),
806 !strconcat("vpermil" # _.Suffix,
807 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
808 [(set _.RC:$dst,
809 (_.VT (X86VPermilpv _.RC:$src1,
810 (Ctrl.VT Ctrl.RC:$src2))))]>,
811 EVEX_4V;
812 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
813 (ins _.RC:$src1, Ctrl.MemOp:$src2),
814 !strconcat("vpermil" # _.Suffix,
815 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
816 [(set _.RC:$dst,
817 (_.VT (X86VPermilpv _.RC:$src1,
818 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
819 EVEX_4V;
820 }
821}
822
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]823defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
824 EVEX_V512, VEX_W;
825defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
826 EVEX_V512, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]827
Adam Nemetcf7a4a22014-10-27 23:08:40 +0000[diff] [blame]828defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]829 EVEX_V512;
Adam Nemetcf7a4a22014-10-27 23:08:40 +0000[diff] [blame]830defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]831 EVEX_V512, VEX_W;
Adam Nemet9aad1312014-10-27 23:08:34 +0000[diff] [blame]832
833def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
834 (VPERMILPSZri VR512:$src1, imm:$imm)>;
835def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
836 (VPERMILPDZri VR512:$src1, imm:$imm)>;
837
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]838// -- VPERM - register form --
839multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
840 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
841
842 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
843 (ins RC:$src1, RC:$src2),
844 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]845 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]846 [(set RC:$dst,
847 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
848
849 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
850 (ins RC:$src1, x86memop:$src2),
851 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]852 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]853 [(set RC:$dst,
854 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
855 EVEX_4V;
856}
857
858defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
859 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
860defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
861 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
862let ExeDomain = SSEPackedSingle in
863defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
864 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
865let ExeDomain = SSEPackedDouble in
866defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
867 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
868
869// -- VPERM2I - 3 source operands form --
870multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
871 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]872 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]873let Constraints = "$src1 = $dst" in {
874 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
875 (ins RC:$src1, RC:$src2, RC:$src3),
876 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]877 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]878 [(set RC:$dst,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]879 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]880 EVEX_4V;
881
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]882 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
883 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
884 !strconcat(OpcodeStr,
885 " \t{$src3, $src2, $dst {${mask}}|"
886 "$dst {${mask}}, $src2, $src3}"),
887 [(set RC:$dst, (OpVT (vselect KRC:$mask,
888 (OpNode RC:$src1, RC:$src2,
889 RC:$src3),
890 RC:$src1)))]>,
891 EVEX_4V, EVEX_K;
892
893 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
894 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
895 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
896 !strconcat(OpcodeStr,
897 " \t{$src3, $src2, $dst {${mask}} {z} |",
898 "$dst {${mask}} {z}, $src2, $src3}"),
899 [(set RC:$dst, (OpVT (vselect KRC:$mask,
900 (OpNode RC:$src1, RC:$src2,
901 RC:$src3),
902 (OpVT (bitconvert
903 (v16i32 immAllZerosV))))))]>,
904 EVEX_4V, EVEX_KZ;
905
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]906 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
907 (ins RC:$src1, RC:$src2, x86memop:$src3),
908 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]909 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]910 [(set RC:$dst,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]911 (OpVT (OpNode RC:$src1, RC:$src2,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]912 (mem_frag addr:$src3))))]>, EVEX_4V;
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]913
914 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
915 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
916 !strconcat(OpcodeStr,
917 " \t{$src3, $src2, $dst {${mask}}|"
918 "$dst {${mask}}, $src2, $src3}"),
919 [(set RC:$dst,
920 (OpVT (vselect KRC:$mask,
921 (OpNode RC:$src1, RC:$src2,
922 (mem_frag addr:$src3)),
923 RC:$src1)))]>,
924 EVEX_4V, EVEX_K;
925
926 let AddedComplexity = 10 in // Prefer over the rrkz variant
927 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
928 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
929 !strconcat(OpcodeStr,
930 " \t{$src3, $src2, $dst {${mask}} {z}|"
931 "$dst {${mask}} {z}, $src2, $src3}"),
932 [(set RC:$dst,
933 (OpVT (vselect KRC:$mask,
934 (OpNode RC:$src1, RC:$src2,
935 (mem_frag addr:$src3)),
936 (OpVT (bitconvert
937 (v16i32 immAllZerosV))))))]>,
938 EVEX_4V, EVEX_KZ;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]939 }
940}
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]941defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
942 i512mem, X86VPermiv3, v16i32, VK16WM>,
943 EVEX_V512, EVEX_CD8<32, CD8VF>;
944defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
945 i512mem, X86VPermiv3, v8i64, VK8WM>,
946 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
947defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
948 i512mem, X86VPermiv3, v16f32, VK16WM>,
949 EVEX_V512, EVEX_CD8<32, CD8VF>;
950defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
951 i512mem, X86VPermiv3, v8f64, VK8WM>,
952 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]953
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]954multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
955 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]956 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
957 ValueType MaskVT, RegisterClass MRC> :
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]958 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
959 OpVT, KRC> {
960 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
961 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
962 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]963
964 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
965 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
966 (!cast<Instruction>(NAME#rrk) VR512:$src1,
967 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]968}
969
970defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]971 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
972 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]973defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]974 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
975 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]976defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]977 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
978 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]979defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]980 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
981 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky299cf5112014-04-29 09:09:15 +0000[diff] [blame]982
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]983//===----------------------------------------------------------------------===//
984// AVX-512 - BLEND using mask
985//
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]986multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]987 RegisterClass KRC, RegisterClass RC,
988 X86MemOperand x86memop, PatFrag mem_frag,
989 SDNode OpNode, ValueType vt> {
990 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]991 (ins KRC:$mask, RC:$src1, RC:$src2),
992 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]993 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]994 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]995 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]996 let mayLoad = 1 in
997 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
998 (ins KRC:$mask, RC:$src1, x86memop:$src2),
999 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1000 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1001 []>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1002}
1003
1004let ExeDomain = SSEPackedSingle in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1005defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1006 VK16WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1007 memopv16f32, vselect, v16f32>,
1008 EVEX_CD8<32, CD8VF>, EVEX_V512;
1009let ExeDomain = SSEPackedDouble in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1010defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1011 VK8WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1012 memopv8f64, vselect, v8f64>,
1013 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1014
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1015def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1016 (v16f32 VR512:$src2), (i16 GR16:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1017 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1018 VR512:$src1, VR512:$src2)>;
1019
1020def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1021 (v8f64 VR512:$src2), (i8 GR8:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1022 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1023 VR512:$src1, VR512:$src2)>;
1024
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1025defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1026 VK16WM, VR512, f512mem,
1027 memopv16i32, vselect, v16i32>,
1028 EVEX_CD8<32, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1029
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1030defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1031 VK8WM, VR512, f512mem,
1032 memopv8i64, vselect, v8i64>,
1033 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1034
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1035def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1036 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1037 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1038 VR512:$src1, VR512:$src2)>;
1039
1040def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1041 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1042 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1043 VR512:$src1, VR512:$src2)>;
1044
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1045let Predicates = [HasAVX512] in {
1046def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1047 (v8f32 VR256X:$src2))),
1048 (EXTRACT_SUBREG
1049 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1050 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1051 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1052
1053def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1054 (v8i32 VR256X:$src2))),
1055 (EXTRACT_SUBREG
1056 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1057 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1058 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1059}
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1060//===----------------------------------------------------------------------===//
1061// Compare Instructions
1062//===----------------------------------------------------------------------===//
1063
1064// avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1065multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1066 Operand CC, SDNode OpNode, ValueType VT,
1067 PatFrag ld_frag, string asm, string asm_alt> {
1068 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1069 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1070 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1071 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1072 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1073 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1074 [(set VK1:$dst, (OpNode (VT RC:$src1),
1075 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1076 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1077 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1078 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1079 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1080 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1081 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1082 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1083 }
1084}
1085
1086let Predicates = [HasAVX512] in {
1087defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1088 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1089 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1090 XS;
1091defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1092 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1093 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1094 XD, VEX_W;
1095}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1096
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1097multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1098 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1099 def rr : AVX512BI<opc, MRMSrcReg,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1100 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1101 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1102 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1103 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1104 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1105 def rm : AVX512BI<opc, MRMSrcMem,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1106 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1107 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1108 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1109 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1110 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1111 def rrk : AVX512BI<opc, MRMSrcReg,
1112 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1113 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1114 "$dst {${mask}}, $src1, $src2}"),
1115 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1116 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1117 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1118 let mayLoad = 1 in
1119 def rmk : AVX512BI<opc, MRMSrcMem,
1120 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1121 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1122 "$dst {${mask}}, $src1, $src2}"),
1123 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1124 (OpNode (_.VT _.RC:$src1),
1125 (_.VT (bitconvert
1126 (_.LdFrag addr:$src2))))))],
1127 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1128}
1129
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1130multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1131 X86VectorVTInfo _> :
1132 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1133 let mayLoad = 1 in {
1134 def rmb : AVX512BI<opc, MRMSrcMem,
1135 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1136 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1137 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1138 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1139 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1140 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1141 def rmbk : AVX512BI<opc, MRMSrcMem,
1142 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1143 _.ScalarMemOp:$src2),
1144 !strconcat(OpcodeStr,
1145 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1146 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1147 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1148 (OpNode (_.VT _.RC:$src1),
1149 (X86VBroadcast
1150 (_.ScalarLdFrag addr:$src2)))))],
1151 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1152 }
1153}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1154
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1155multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1156 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1157 let Predicates = [prd] in
1158 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1159 EVEX_V512;
1160
1161 let Predicates = [prd, HasVLX] in {
1162 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1163 EVEX_V256;
1164 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1165 EVEX_V128;
1166 }
1167}
1168
1169multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1170 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1171 Predicate prd> {
1172 let Predicates = [prd] in
1173 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1174 EVEX_V512;
1175
1176 let Predicates = [prd, HasVLX] in {
1177 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1178 EVEX_V256;
1179 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1180 EVEX_V128;
1181 }
1182}
1183
1184defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1185 avx512vl_i8_info, HasBWI>,
1186 EVEX_CD8<8, CD8VF>;
1187
1188defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1189 avx512vl_i16_info, HasBWI>,
1190 EVEX_CD8<16, CD8VF>;
1191
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1192defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1193 avx512vl_i32_info, HasAVX512>,
1194 EVEX_CD8<32, CD8VF>;
1195
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1196defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1197 avx512vl_i64_info, HasAVX512>,
1198 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1199
1200defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1201 avx512vl_i8_info, HasBWI>,
1202 EVEX_CD8<8, CD8VF>;
1203
1204defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1205 avx512vl_i16_info, HasBWI>,
1206 EVEX_CD8<16, CD8VF>;
1207
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1208defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1209 avx512vl_i32_info, HasAVX512>,
1210 EVEX_CD8<32, CD8VF>;
1211
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1212defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1213 avx512vl_i64_info, HasAVX512>,
1214 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1215
1216def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1217 (COPY_TO_REGCLASS (VPCMPGTDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1218 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1219 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1220
1221def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1222 (COPY_TO_REGCLASS (VPCMPEQDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1223 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1224 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1225
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1226multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1227 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1228 def rri : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1229 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1230 !strconcat("vpcmp${cc}", Suffix,
1231 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1232 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1233 imm:$cc))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1234 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1235 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1236 def rmi : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1237 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1238 !strconcat("vpcmp${cc}", Suffix,
1239 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1240 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1241 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1242 imm:$cc))],
1243 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1244 def rrik : AVX512AIi8<opc, MRMSrcReg,
1245 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1246 AVXCC:$cc),
1247 !strconcat("vpcmp${cc}", Suffix,
1248 "\t{$src2, $src1, $dst {${mask}}|",
1249 "$dst {${mask}}, $src1, $src2}"),
1250 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1251 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1252 imm:$cc)))],
1253 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1254 let mayLoad = 1 in
1255 def rmik : AVX512AIi8<opc, MRMSrcMem,
1256 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1257 AVXCC:$cc),
1258 !strconcat("vpcmp${cc}", Suffix,
1259 "\t{$src2, $src1, $dst {${mask}}|",
1260 "$dst {${mask}}, $src1, $src2}"),
1261 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1262 (OpNode (_.VT _.RC:$src1),
1263 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1264 imm:$cc)))],
1265 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1266
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1267 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1268 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1269 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1270 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1271 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1272 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1273 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1274 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1275 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1276 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1277 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1278 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1279 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1280 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1281 i8imm:$cc),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1282 !strconcat("vpcmp", Suffix,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1283 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1284 "$dst {${mask}}, $src1, $src2, $cc}"),
1285 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1286 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1287 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1288 i8imm:$cc),
1289 !strconcat("vpcmp", Suffix,
1290 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1291 "$dst {${mask}}, $src1, $src2, $cc}"),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1292 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1293 }
1294}
1295
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1296multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1297 X86VectorVTInfo _> :
1298 avx512_icmp_cc<opc, Suffix, OpNode, _> {
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1299 let mayLoad = 1 in {
1300 def rmib : AVX512AIi8<opc, MRMSrcMem,
1301 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1302 AVXCC:$cc),
1303 !strconcat("vpcmp${cc}", Suffix,
1304 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1305 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1306 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1307 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1308 imm:$cc))],
1309 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1310 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1311 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1312 _.ScalarMemOp:$src2, AVXCC:$cc),
1313 !strconcat("vpcmp${cc}", Suffix,
1314 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1315 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1316 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1317 (OpNode (_.VT _.RC:$src1),
1318 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1319 imm:$cc)))],
1320 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1321 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1322
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1323 // Accept explicit immediate argument form instead of comparison code.
1324 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1325 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1326 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1327 i8imm:$cc),
1328 !strconcat("vpcmp", Suffix,
1329 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1330 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1331 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1332 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1333 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1334 _.ScalarMemOp:$src2, i8imm:$cc),
1335 !strconcat("vpcmp", Suffix,
1336 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1337 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1338 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1339 }
1340}
1341
1342multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1343 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1344 let Predicates = [prd] in
1345 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1346
1347 let Predicates = [prd, HasVLX] in {
1348 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1349 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1350 }
1351}
1352
1353multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1354 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1355 let Predicates = [prd] in
1356 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1357 EVEX_V512;
1358
1359 let Predicates = [prd, HasVLX] in {
1360 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1361 EVEX_V256;
1362 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1363 EVEX_V128;
1364 }
1365}
1366
1367defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1368 HasBWI>, EVEX_CD8<8, CD8VF>;
1369defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1370 HasBWI>, EVEX_CD8<8, CD8VF>;
1371
1372defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1373 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1374defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1375 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1376
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1377defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1378 HasAVX512>, EVEX_CD8<32, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1379defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1380 HasAVX512>, EVEX_CD8<32, CD8VF>;
1381
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1382defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1383 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1384defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1385 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1386
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1387// avx512_cmp_packed - compare packed instructions
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1388multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1389 X86MemOperand x86memop, ValueType vt,
1390 string suffix, Domain d> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1391 def rri : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1392 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1393 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1394 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1395 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1396 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1397 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1398 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1399 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1400 [], d>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1401 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1402 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1403 !strconcat("vcmp${cc}", suffix,
1404 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1405 [(set KRC:$dst,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1406 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1407
1408 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1409 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1410 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1411 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1412 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1413 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1414 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1415 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1416 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1417 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1418 }
1419}
1420
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1421defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1422 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]1423 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1424defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1425 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1426 EVEX_CD8<64, CD8VF>;
1427
1428def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1429 (COPY_TO_REGCLASS (VCMPPSZrri
1430 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1431 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1432 imm:$cc), VK8)>;
1433def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1434 (COPY_TO_REGCLASS (VPCMPDZrri
1435 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1436 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1437 imm:$cc), VK8)>;
1438def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1439 (COPY_TO_REGCLASS (VPCMPUDZrri
1440 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1441 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1442 imm:$cc), VK8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1443
1444def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1445 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1446 FROUND_NO_EXC)),
1447 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1448 (I8Imm imm:$cc)), GR16)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1449
1450def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1451 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1452 FROUND_NO_EXC)),
1453 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1454 (I8Imm imm:$cc)), GR8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1455
1456def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1457 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1458 FROUND_CURRENT)),
1459 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1460 (I8Imm imm:$cc)), GR16)>;
1461
1462def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1463 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1464 FROUND_CURRENT)),
1465 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1466 (I8Imm imm:$cc)), GR8)>;
1467
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1468// Mask register copy, including
1469// - copy between mask registers
1470// - load/store mask registers
1471// - copy from GPR to mask register and vice versa
1472//
1473multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1474 string OpcodeStr, RegisterClass KRC,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1475 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1476 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1477 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1478 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1479 let mayLoad = 1 in
1480 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1481 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1482 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1483 let mayStore = 1 in
1484 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1485 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1486 }
1487}
1488
1489multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1490 string OpcodeStr,
1491 RegisterClass KRC, RegisterClass GRC> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1492 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1493 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1494 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1495 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1496 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1497 }
1498}
1499
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1500let Predicates = [HasDQI] in
1501 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1502 i8mem>,
1503 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1504 VEX, PD;
1505
1506let Predicates = [HasAVX512] in
1507 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1508 i16mem>,
1509 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1510 VEX, PS;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1511
1512let Predicates = [HasBWI] in {
1513 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1514 i32mem>, VEX, PD, VEX_W;
1515 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1516 VEX, XD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1517}
1518
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1519let Predicates = [HasBWI] in {
1520 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1521 i64mem>, VEX, PS, VEX_W;
1522 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1523 VEX, XD, VEX_W;
1524}
1525
1526// GR from/to mask register
1527let Predicates = [HasDQI] in {
1528 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1529 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1530 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1531 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1532}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1533let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1534 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1535 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1536 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1537 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1538}
1539let Predicates = [HasBWI] in {
1540 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1541 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1542}
1543let Predicates = [HasBWI] in {
1544 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1545 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1546}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1547
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1548// Load/store kreg
1549let Predicates = [HasDQI] in {
1550 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1551 (KMOVBmk addr:$dst, VK8:$src)>;
1552}
1553let Predicates = [HasAVX512] in {
1554 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1555 (KMOVWmk addr:$dst, VK16:$src)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1556 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1557 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1558 def : Pat<(i1 (load addr:$src)),
1559 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1560 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1561 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1562}
1563let Predicates = [HasBWI] in {
1564 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1565 (KMOVDmk addr:$dst, VK32:$src)>;
1566}
1567let Predicates = [HasBWI] in {
1568 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1569 (KMOVQmk addr:$dst, VK64:$src)>;
1570}
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1571
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1572let Predicates = [HasAVX512] in {
Elena Demikhovsky34d2d762014-08-18 11:59:06 +0000[diff] [blame]1573 def : Pat<(i1 (trunc (i64 GR64:$src))),
1574 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1575 (i32 1))), VK1)>;
1576
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1577 def : Pat<(i1 (trunc (i32 GR32:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1578 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1579
1580 def : Pat<(i1 (trunc (i8 GR8:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1581 (COPY_TO_REGCLASS
1582 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1583 VK1)>;
1584 def : Pat<(i1 (trunc (i16 GR16:$src))),
1585 (COPY_TO_REGCLASS
1586 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1587 VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1588
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1589 def : Pat<(i32 (zext VK1:$src)),
1590 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1591 def : Pat<(i8 (zext VK1:$src)),
1592 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1593 (AND32ri (KMOVWrk
1594 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1595 def : Pat<(i64 (zext VK1:$src)),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1596 (AND64ri8 (SUBREG_TO_REG (i64 0),
1597 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
Elena Demikhovsky750498c2014-02-17 07:29:33 +0000[diff] [blame]1598 def : Pat<(i16 (zext VK1:$src)),
1599 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1600 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1601 sub_16bit)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1602 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1603 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1604 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1605 (COPY_TO_REGCLASS VK1:$src, VK8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1606}
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1607let Predicates = [HasBWI] in {
1608 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1609 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1610 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1611 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1612}
1613
1614
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1615// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1616let Predicates = [HasAVX512] in {
1617 // GR from/to 8-bit mask without native support
1618 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1619 (COPY_TO_REGCLASS
1620 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1621 VK8)>;
1622 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1623 (EXTRACT_SUBREG
1624 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1625 sub_8bit)>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1626
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1627 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1628 (COPY_TO_REGCLASS VK16:$src, VK1)>;
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1629 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1630 (COPY_TO_REGCLASS VK8:$src, VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1631}
1632let Predicates = [HasBWI] in {
1633 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1634 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1635 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1636 (COPY_TO_REGCLASS VK64:$src, VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1637}
1638
1639// Mask unary operation
1640// - KNOT
1641multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1642 RegisterClass KRC, SDPatternOperator OpNode,
1643 Predicate prd> {
1644 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1645 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1646 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1647 [(set KRC:$dst, (OpNode KRC:$src))]>;
1648}
1649
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1650multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1651 SDPatternOperator OpNode> {
1652 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1653 HasDQI>, VEX, PD;
1654 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1655 HasAVX512>, VEX, PS;
1656 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1657 HasBWI>, VEX, PD, VEX_W;
1658 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1659 HasBWI>, VEX, PS, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1660}
1661
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1662defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1663
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1664multiclass avx512_mask_unop_int<string IntName, string InstName> {
1665 let Predicates = [HasAVX512] in
1666 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1667 (i16 GR16:$src)),
1668 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1669 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1670}
1671defm : avx512_mask_unop_int<"knot", "KNOT">;
1672
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1673let Predicates = [HasDQI] in
1674def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1675let Predicates = [HasAVX512] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1676def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1677let Predicates = [HasBWI] in
1678def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1679let Predicates = [HasBWI] in
1680def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1681
1682// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1683let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1684def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1685 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1686
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1687def : Pat<(not VK8:$src),
1688 (COPY_TO_REGCLASS
1689 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1690}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1691
1692// Mask binary operation
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1693// - KAND, KANDN, KOR, KXNOR, KXOR
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1694multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1695 RegisterClass KRC, SDPatternOperator OpNode,
1696 Predicate prd> {
1697 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1698 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1699 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1700 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1701 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1702}
1703
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1704multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1705 SDPatternOperator OpNode> {
1706 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1707 HasDQI>, VEX_4V, VEX_L, PD;
1708 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1709 HasAVX512>, VEX_4V, VEX_L, PS;
1710 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1711 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1712 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1713 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1714}
1715
1716def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1717def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1718
1719let isCommutable = 1 in {
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1720 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1721 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1722 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1723 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1724}
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1725let isCommutable = 0 in
1726 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1727
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1728def : Pat<(xor VK1:$src1, VK1:$src2),
1729 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1730 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1731
1732def : Pat<(or VK1:$src1, VK1:$src2),
1733 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1734 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1735
Elena Demikhovskyb64d7e82013-12-25 10:06:40 +0000[diff] [blame]1736def : Pat<(and VK1:$src1, VK1:$src2),
1737 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1738 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1739
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1740multiclass avx512_mask_binop_int<string IntName, string InstName> {
1741 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1742 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1743 (i16 GR16:$src1), (i16 GR16:$src2)),
1744 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1745 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1746 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1747}
1748
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1749defm : avx512_mask_binop_int<"kand", "KAND">;
1750defm : avx512_mask_binop_int<"kandn", "KANDN">;
1751defm : avx512_mask_binop_int<"kor", "KOR">;
1752defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1753defm : avx512_mask_binop_int<"kxor", "KXOR">;
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1754
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1755// With AVX-512, 8-bit mask is promoted to 16-bit mask.
1756multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1757 let Predicates = [HasAVX512] in
1758 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1759 (COPY_TO_REGCLASS
1760 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1761 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1762}
1763
1764defm : avx512_binop_pat<and, KANDWrr>;
1765defm : avx512_binop_pat<andn, KANDNWrr>;
1766defm : avx512_binop_pat<or, KORWrr>;
1767defm : avx512_binop_pat<xnor, KXNORWrr>;
1768defm : avx512_binop_pat<xor, KXORWrr>;
1769
1770// Mask unpacking
1771multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1772 RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1773 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1774 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1775 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1776 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1777}
1778
1779multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1780 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1781 VEX_4V, VEX_L, PD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1782}
1783
1784defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1785def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1786 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1787 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1788
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1789
1790multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1791 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1792 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1793 (i16 GR16:$src1), (i16 GR16:$src2)),
1794 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1795 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1796 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1797}
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1798defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1799
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1800// Mask bit testing
1801multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1802 SDNode OpNode> {
1803 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1804 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1805 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1806 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1807}
1808
1809multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1810 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1811 VEX, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1812}
1813
1814defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1815
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1816def : Pat<(X86cmp VK1:$src1, (i1 0)),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1817 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1818 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1819
1820// Mask shift
1821multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1822 SDNode OpNode> {
1823 let Predicates = [HasAVX512] in
1824 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1825 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1826 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1827 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1828}
1829
1830multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1831 SDNode OpNode> {
1832 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1833 VEX, TAPD, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1834}
1835
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1836defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1837defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1838
1839// Mask setting all 0s or 1s
1840multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1841 let Predicates = [HasAVX512] in
1842 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1843 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1844 [(set KRC:$dst, (VT Val))]>;
1845}
1846
1847multiclass avx512_mask_setop_w<PatFrag Val> {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1848 defm B : avx512_mask_setop<VK8, v8i1, Val>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1849 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1850}
1851
1852defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1853defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1854
1855// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1856let Predicates = [HasAVX512] in {
1857 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1858 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1859 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1860 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1861 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1862}
1863def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1864 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1865
1866def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1867 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1868
1869def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1870 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1871
Robert Khasanov5aa44452014-09-30 11:41:54 +0000[diff] [blame]1872let Predicates = [HasVLX] in {
1873 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1874 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1875 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1876 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1877 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1878 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1879 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1880 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1881}
1882
Elena Demikhovsky9737e382014-03-02 09:19:44 +0000[diff] [blame]1883def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1884 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1885
1886def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1887 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1888//===----------------------------------------------------------------------===//
1889// AVX-512 - Aligned and unaligned load and store
1890//
1891
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1892multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1893 RegisterClass KRC, RegisterClass RC,
1894 ValueType vt, ValueType zvt, X86MemOperand memop,
1895 Domain d, bit IsReMaterializable = 1> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1896let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1897 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1898 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1899 d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1900 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1901 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1902 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1903 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1904 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1905 SchedRW = [WriteLoad] in
1906 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1907 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1908 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1909 d>, EVEX;
1910
1911 let AddedComplexity = 20 in {
1912 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1913 let hasSideEffects = 0 in
1914 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1915 (ins RC:$src0, KRC:$mask, RC:$src1),
1916 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1917 "${dst} {${mask}}, $src1}"),
1918 [(set RC:$dst, (vt (vselect KRC:$mask,
1919 (vt RC:$src1),
1920 (vt RC:$src0))))],
1921 d>, EVEX, EVEX_K;
1922 let mayLoad = 1, SchedRW = [WriteLoad] in
1923 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1924 (ins RC:$src0, KRC:$mask, memop:$src1),
1925 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1926 "${dst} {${mask}}, $src1}"),
1927 [(set RC:$dst, (vt
1928 (vselect KRC:$mask,
1929 (vt (bitconvert (ld_frag addr:$src1))),
1930 (vt RC:$src0))))],
1931 d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1932 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1933 let mayLoad = 1, SchedRW = [WriteLoad] in
1934 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1935 (ins KRC:$mask, memop:$src),
1936 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1937 "${dst} {${mask}} {z}, $src}"),
1938 [(set RC:$dst, (vt
1939 (vselect KRC:$mask,
1940 (vt (bitconvert (ld_frag addr:$src))),
1941 (vt (bitconvert (zvt immAllZerosV))))))],
1942 d>, EVEX, EVEX_KZ;
1943 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1944}
1945
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1946multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1947 string elty, string elsz, string vsz512,
1948 string vsz256, string vsz128, Domain d,
1949 Predicate prd, bit IsReMaterializable = 1> {
1950 let Predicates = [prd] in
1951 defm Z : avx512_load<opc, OpcodeStr,
1952 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1953 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1954 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1955 !cast<X86MemOperand>(elty##"512mem"), d,
1956 IsReMaterializable>, EVEX_V512;
1957
1958 let Predicates = [prd, HasVLX] in {
1959 defm Z256 : avx512_load<opc, OpcodeStr,
1960 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1961 "v"##vsz256##elty##elsz, "v4i64")),
1962 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1963 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1964 !cast<X86MemOperand>(elty##"256mem"), d,
1965 IsReMaterializable>, EVEX_V256;
1966
1967 defm Z128 : avx512_load<opc, OpcodeStr,
1968 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1969 "v"##vsz128##elty##elsz, "v2i64")),
1970 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1971 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1972 !cast<X86MemOperand>(elty##"128mem"), d,
1973 IsReMaterializable>, EVEX_V128;
1974 }
1975}
1976
1977
1978multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1979 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1980 X86MemOperand memop, Domain d> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1981 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1982 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1983 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1984 EVEX;
1985 let Constraints = "$src1 = $dst" in
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1986 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1987 (ins RC:$src1, KRC:$mask, RC:$src2),
1988 !strconcat(OpcodeStr,
1989 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1990 EVEX, EVEX_K;
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1991 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1992 (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1993 !strconcat(OpcodeStr,
1994 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1995 [], d>, EVEX, EVEX_KZ;
1996 }
1997 let mayStore = 1 in {
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1998 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1999 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2000 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2001 def mrk : AVX512PI<opc, MRMDestMem, (outs),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2002 (ins memop:$dst, KRC:$mask, RC:$src),
2003 !strconcat(OpcodeStr,
2004 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2005 [], d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2006 }
2007}
2008
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2009
2010multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2011 string st_suff_512, string st_suff_256,
2012 string st_suff_128, string elty, string elsz,
2013 string vsz512, string vsz256, string vsz128,
2014 Domain d, Predicate prd> {
2015 let Predicates = [prd] in
2016 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2017 !cast<ValueType>("v"##vsz512##elty##elsz),
2018 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2019 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2020
2021 let Predicates = [prd, HasVLX] in {
2022 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2023 !cast<ValueType>("v"##vsz256##elty##elsz),
2024 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2025 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2026
2027 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2028 !cast<ValueType>("v"##vsz128##elty##elsz),
2029 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2030 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2031 }
2032}
2033
2034defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2035 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2036 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2037 "512", "256", "", "f", "32", "16", "8", "4",
2038 SSEPackedSingle, HasAVX512>,
2039 PS, EVEX_CD8<32, CD8VF>;
2040
2041defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2042 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2043 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2044 "512", "256", "", "f", "64", "8", "4", "2",
2045 SSEPackedDouble, HasAVX512>,
2046 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2047
2048defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2049 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2050 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2051 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2052 PS, EVEX_CD8<32, CD8VF>;
2053
2054defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2055 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2056 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2057 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2058 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2059
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2060def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2061 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2062 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2063
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2064def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2065 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2066 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2067
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2068def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2069 GR16:$mask),
2070 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2071 VR512:$src)>;
2072def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2073 GR8:$mask),
2074 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2075 VR512:$src)>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]2076
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2077defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2078 "16", "8", "4", SSEPackedInt, HasAVX512>,
2079 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2080 "512", "256", "", "i", "32", "16", "8", "4",
2081 SSEPackedInt, HasAVX512>,
2082 PD, EVEX_CD8<32, CD8VF>;
2083
2084defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2085 "8", "4", "2", SSEPackedInt, HasAVX512>,
2086 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2087 "512", "256", "", "i", "64", "8", "4", "2",
2088 SSEPackedInt, HasAVX512>,
2089 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2090
2091defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2092 "64", "32", "16", SSEPackedInt, HasBWI>,
2093 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2094 "i", "8", "64", "32", "16", SSEPackedInt,
2095 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2096
2097defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2098 "32", "16", "8", SSEPackedInt, HasBWI>,
2099 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2100 "i", "16", "32", "16", "8", SSEPackedInt,
2101 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2102
2103defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2104 "16", "8", "4", SSEPackedInt, HasAVX512>,
2105 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2106 "i", "32", "16", "8", "4", SSEPackedInt,
2107 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2108
2109defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2110 "8", "4", "2", SSEPackedInt, HasAVX512>,
2111 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2112 "i", "64", "8", "4", "2", SSEPackedInt,
2113 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]2114
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2115def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2116 (v16i32 immAllZerosV), GR16:$mask)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2117 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2118
2119def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2120 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2121 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2122
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2123def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2124 GR16:$mask),
2125 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2126 VR512:$src)>;
2127def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2128 GR8:$mask),
2129 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2130 VR512:$src)>;
2131
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2132let AddedComplexity = 20 in {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2133def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2134 (bc_v8i64 (v16i32 immAllZerosV)))),
2135 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2136
2137def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2138 (v8i64 VR512:$src))),
2139 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2140 VK8), VR512:$src)>;
2141
2142def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2143 (v16i32 immAllZerosV))),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2144 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2145
2146def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2147 (v16i32 VR512:$src))),
2148 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2149}
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2150
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2151// Move Int Doubleword to Packed Double Int
2152//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2153def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2154 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2155 [(set VR128X:$dst,
2156 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2157 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2158def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2159 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2160 [(set VR128X:$dst,
2161 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2162 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2163def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2164 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2165 [(set VR128X:$dst,
2166 (v2i64 (scalar_to_vector GR64:$src)))],
2167 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2168let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2169def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2170 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2171 [(set FR64:$dst, (bitconvert GR64:$src))],
2172 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2173def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2174 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2175 [(set GR64:$dst, (bitconvert FR64:$src))],
2176 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2177}
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2178def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2179 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2180 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2181 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2182 EVEX_CD8<64, CD8VT1>;
2183
2184// Move Int Doubleword to Single Scalar
2185//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2186let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2187def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2188 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2189 [(set FR32X:$dst, (bitconvert GR32:$src))],
2190 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2191
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2192def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2193 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2194 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2195 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2196}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2197
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2198// Move doubleword from xmm register to r/m32
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2199//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2200def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2201 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2202 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2203 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2204 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2205def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2206 (ins i32mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2207 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2208 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2209 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2210 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2211
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2212// Move quadword from xmm1 register to r/m64
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2213//
2214def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2215 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2216 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2217 (iPTR 0)))],
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2218 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2219 Requires<[HasAVX512, In64BitMode]>;
2220
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]2221def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2222 (ins i64mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2223 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2224 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2225 addr:$dst)], IIC_SSE_MOVDQ>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2226 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2227 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2228
2229// Move Scalar Single to Double Int
2230//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2231let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2232def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2233 (ins FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2234 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2235 [(set GR32:$dst, (bitconvert FR32X:$src))],
2236 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2237def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2238 (ins i32mem:$dst, FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2239 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2240 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2241 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2242}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2243
2244// Move Quadword Int to Packed Quadword Int
2245//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2246def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2247 (ins i64mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2248 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2249 [(set VR128X:$dst,
2250 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2251 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2252
2253//===----------------------------------------------------------------------===//
2254// AVX-512 MOVSS, MOVSD
2255//===----------------------------------------------------------------------===//
2256
2257multiclass avx512_move_scalar <string asm, RegisterClass RC,
2258 SDNode OpNode, ValueType vt,
2259 X86MemOperand x86memop, PatFrag mem_pat> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2260 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2261 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2262 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2263 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2264 (scalar_to_vector RC:$src2))))],
2265 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2266 let Constraints = "$src1 = $dst" in
2267 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2268 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2269 !strconcat(asm,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2270 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2271 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2272 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2273 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2274 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2275 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2276 let mayStore = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2277 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2278 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2279 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2280 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2281 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2282 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2283 [], IIC_SSE_MOV_S_MR>,
2284 EVEX, VEX_LIG, EVEX_K;
2285 } // mayStore
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2286 } //hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2287}
2288
2289let ExeDomain = SSEPackedSingle in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2290defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2291 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2292
2293let ExeDomain = SSEPackedDouble in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2294defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2295 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2296
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2297def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2298 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2299 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2300
2301def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2302 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2303 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2304
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2305def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2306 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2307 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2308
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2309// For the disassembler
Craig Topper3484fc22014-01-05 04:17:28 +0000[diff] [blame]2310let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2311 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2312 (ins VR128X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2313 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2314 IIC_SSE_MOV_S_RR>,
2315 XS, EVEX_4V, VEX_LIG;
2316 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2317 (ins VR128X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2318 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2319 IIC_SSE_MOV_S_RR>,
2320 XD, EVEX_4V, VEX_LIG, VEX_W;
2321}
2322
2323let Predicates = [HasAVX512] in {
2324 let AddedComplexity = 15 in {
2325 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2326 // MOVS{S,D} to the lower bits.
2327 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2328 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2329 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2330 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2331 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2332 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2333 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2334 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2335
2336 // Move low f32 and clear high bits.
2337 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2338 (SUBREG_TO_REG (i32 0),
2339 (VMOVSSZrr (v4f32 (V_SET0)),
2340 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2341 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2342 (SUBREG_TO_REG (i32 0),
2343 (VMOVSSZrr (v4i32 (V_SET0)),
2344 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2345 }
2346
2347 let AddedComplexity = 20 in {
2348 // MOVSSrm zeros the high parts of the register; represent this
2349 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2350 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2351 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2352 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2353 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2354 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2355 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2356
2357 // MOVSDrm zeros the high parts of the register; represent this
2358 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2359 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2360 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2361 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2362 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2363 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2364 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2365 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2366 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2367 def : Pat<(v2f64 (X86vzload addr:$src)),
2368 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2369
2370 // Represent the same patterns above but in the form they appear for
2371 // 256-bit types
2372 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2373 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2374 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2375 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2376 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2377 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2378 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2379 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2380 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2381 }
2382 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2383 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2384 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2385 FR32X:$src)), sub_xmm)>;
2386 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2387 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2388 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2389 FR64X:$src)), sub_xmm)>;
2390 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2391 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2392 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2393
2394 // Move low f64 and clear high bits.
2395 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2396 (SUBREG_TO_REG (i32 0),
2397 (VMOVSDZrr (v2f64 (V_SET0)),
2398 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2399
2400 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2401 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2402 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2403
2404 // Extract and store.
2405 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2406 addr:$dst),
2407 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2408 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2409 addr:$dst),
2410 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2411
2412 // Shuffle with VMOVSS
2413 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2414 (VMOVSSZrr (v4i32 VR128X:$src1),
2415 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2416 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2417 (VMOVSSZrr (v4f32 VR128X:$src1),
2418 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2419
2420 // 256-bit variants
2421 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2422 (SUBREG_TO_REG (i32 0),
2423 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2424 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2425 sub_xmm)>;
2426 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2427 (SUBREG_TO_REG (i32 0),
2428 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2429 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2430 sub_xmm)>;
2431
2432 // Shuffle with VMOVSD
2433 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2434 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2435 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2436 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2437 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2438 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2439 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2440 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2441
2442 // 256-bit variants
2443 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2444 (SUBREG_TO_REG (i32 0),
2445 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2446 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2447 sub_xmm)>;
2448 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2449 (SUBREG_TO_REG (i32 0),
2450 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2451 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2452 sub_xmm)>;
2453
2454 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2455 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2456 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2457 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2458 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2459 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2460 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2461 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2462}
2463
2464let AddedComplexity = 15 in
2465def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2466 (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2467 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2468 [(set VR128X:$dst, (v2i64 (X86vzmovl
2469 (v2i64 VR128X:$src))))],
2470 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2471
2472let AddedComplexity = 20 in
2473def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2474 (ins i128mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2475 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2476 [(set VR128X:$dst, (v2i64 (X86vzmovl
2477 (loadv2i64 addr:$src))))],
2478 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2479 EVEX_CD8<8, CD8VT8>;
2480
2481let Predicates = [HasAVX512] in {
2482 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2483 let AddedComplexity = 20 in {
2484 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2485 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2486 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2487 (VMOV64toPQIZrr GR64:$src)>;
2488 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2489 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2490
2491 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2492 (VMOVDI2PDIZrm addr:$src)>;
2493 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2494 (VMOVDI2PDIZrm addr:$src)>;
2495 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2496 (VMOVZPQILo2PQIZrm addr:$src)>;
2497 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2498 (VMOVZPQILo2PQIZrr VR128X:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]2499 def : Pat<(v2i64 (X86vzload addr:$src)),
2500 (VMOVZPQILo2PQIZrm addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2501 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2502
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2503 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2504 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2505 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2506 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2507 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2508 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2509 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2510}
2511
2512def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2513 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2514
2515def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2516 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2517
2518def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2519 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2520
2521def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2522 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2523
2524//===----------------------------------------------------------------------===//
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2525// AVX-512 - Non-temporals
2526//===----------------------------------------------------------------------===//
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2527let SchedRW = [WriteLoad] in {
2528 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2529 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2530 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2531 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2532 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2533
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2534 let Predicates = [HasAVX512, HasVLX] in {
2535 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2536 (ins i256mem:$src),
2537 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2538 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2539 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2540
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2541 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2542 (ins i128mem:$src),
2543 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2544 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2545 EVEX_CD8<64, CD8VF>;
2546 }
Adam Nemetefd07852014-06-18 16:51:10 +0000[diff] [blame]2547}
2548
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2549multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2550 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2551 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2552 let SchedRW = [WriteStore], mayStore = 1,
2553 AddedComplexity = 400 in
2554 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2555 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2556 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2557}
2558
2559multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2560 string elty, string elsz, string vsz512,
2561 string vsz256, string vsz128, Domain d,
2562 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2563 let Predicates = [prd] in
2564 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2565 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2566 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2567 EVEX_V512;
2568
2569 let Predicates = [prd, HasVLX] in {
2570 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2571 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2572 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2573 EVEX_V256;
2574
2575 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2576 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2577 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2578 EVEX_V128;
2579 }
2580}
2581
2582defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2583 "i", "64", "8", "4", "2", SSEPackedInt,
2584 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2585
2586defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2587 "f", "64", "8", "4", "2", SSEPackedDouble,
2588 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2589
2590defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2591 "f", "32", "16", "8", "4", SSEPackedSingle,
2592 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2593
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2594//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2595// AVX-512 - Integer arithmetic
2596//
2597multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2598 X86VectorVTInfo _, OpndItins itins,
2599 bit IsCommutable = 0> {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]2600 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2601 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2602 "$src2, $src1", "$src1, $src2",
2603 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2604 itins.rr, IsCommutable>,
2605 AVX512BIBase, EVEX_4V;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2606
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2607 let mayLoad = 1 in
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]2608 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2609 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2610 "$src2, $src1", "$src1, $src2",
2611 (_.VT (OpNode _.RC:$src1,
2612 (bitconvert (_.LdFrag addr:$src2)))),
2613 itins.rm>,
2614 AVX512BIBase, EVEX_4V;
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2615}
2616
2617multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2618 X86VectorVTInfo _, OpndItins itins,
2619 bit IsCommutable = 0> :
2620 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2621 let mayLoad = 1 in
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]2622 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2623 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2624 "${src2}"##_.BroadcastStr##", $src1",
2625 "$src1, ${src2}"##_.BroadcastStr,
2626 (_.VT (OpNode _.RC:$src1,
2627 (X86VBroadcast
2628 (_.ScalarLdFrag addr:$src2)))),
2629 itins.rm>,
2630 AVX512BIBase, EVEX_4V, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2631}
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2632
Robert Khasanovd5b14f72014-10-09 08:38:48 +0000[diff] [blame]2633multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2634 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2635 Predicate prd, bit IsCommutable = 0> {
2636 let Predicates = [prd] in
2637 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2638 IsCommutable>, EVEX_V512;
2639
2640 let Predicates = [prd, HasVLX] in {
2641 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2642 IsCommutable>, EVEX_V256;
2643 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2644 IsCommutable>, EVEX_V128;
2645 }
2646}
2647
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2648multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2649 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2650 Predicate prd, bit IsCommutable = 0> {
2651 let Predicates = [prd] in
2652 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2653 IsCommutable>, EVEX_V512;
2654
2655 let Predicates = [prd, HasVLX] in {
2656 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2657 IsCommutable>, EVEX_V256;
2658 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2659 IsCommutable>, EVEX_V128;
2660 }
2661}
2662
2663multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2664 OpndItins itins, Predicate prd,
2665 bit IsCommutable = 0> {
2666 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2667 itins, prd, IsCommutable>,
2668 VEX_W, EVEX_CD8<64, CD8VF>;
2669}
2670
2671multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2672 OpndItins itins, Predicate prd,
2673 bit IsCommutable = 0> {
2674 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2675 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2676}
2677
2678multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2679 OpndItins itins, Predicate prd,
2680 bit IsCommutable = 0> {
2681 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2682 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2683}
2684
2685multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2686 OpndItins itins, Predicate prd,
2687 bit IsCommutable = 0> {
2688 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2689 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2690}
2691
2692multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2693 SDNode OpNode, OpndItins itins, Predicate prd,
2694 bit IsCommutable = 0> {
2695 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2696 IsCommutable>;
2697
2698 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2699 IsCommutable>;
2700}
2701
2702multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2703 SDNode OpNode, OpndItins itins, Predicate prd,
2704 bit IsCommutable = 0> {
2705 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2706 IsCommutable>;
2707
2708 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2709 IsCommutable>;
2710}
2711
2712multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2713 bits<8> opc_d, bits<8> opc_q,
2714 string OpcodeStr, SDNode OpNode,
2715 OpndItins itins, bit IsCommutable = 0> {
2716 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2717 itins, HasAVX512, IsCommutable>,
2718 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2719 itins, HasBWI, IsCommutable>;
2720}
2721
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2722multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2723 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2724 PatFrag memop_frag, X86MemOperand x86memop,
2725 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2726 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2727 let isCommutable = IsCommutable in
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2728 {
2729 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2730 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2731 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2732 []>, EVEX_4V;
2733 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2734 (ins KRC:$mask, RC:$src1, RC:$src2),
2735 !strconcat(OpcodeStr,
2736 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2737 [], itins.rr>, EVEX_4V, EVEX_K;
2738 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2739 (ins KRC:$mask, RC:$src1, RC:$src2),
2740 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2741 "|$dst {${mask}} {z}, $src1, $src2}"),
2742 [], itins.rr>, EVEX_4V, EVEX_KZ;
2743 }
2744 let mayLoad = 1 in {
2745 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2746 (ins RC:$src1, x86memop:$src2),
2747 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2748 []>, EVEX_4V;
2749 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2750 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2751 !strconcat(OpcodeStr,
2752 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2753 [], itins.rm>, EVEX_4V, EVEX_K;
2754 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2755 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2756 !strconcat(OpcodeStr,
2757 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2758 [], itins.rm>, EVEX_4V, EVEX_KZ;
2759 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2760 (ins RC:$src1, x86scalar_mop:$src2),
2761 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2762 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2763 [], itins.rm>, EVEX_4V, EVEX_B;
2764 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2765 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2766 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2767 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2768 BrdcstStr, "}"),
2769 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2770 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2771 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2772 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2773 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2774 BrdcstStr, "}"),
2775 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2776 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2777}
2778
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2779defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2780 SSE_INTALU_ITINS_P, 1>;
2781defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2782 SSE_INTALU_ITINS_P, 0>;
2783defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2784 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2785defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2786 SSE_INTALU_ITINS_P, HasBWI, 1>;
Robert Khasanov1a77f662014-10-14 15:13:56 +0000[diff] [blame]2787defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2788 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2789
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2790defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2791 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2792 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2793 EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2794
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2795defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2796 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2797 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2798
2799def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2800 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2801
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2802def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2803 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2804 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2805def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2806 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2807 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2808
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2809defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2810 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2811defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2812 SSE_INTALU_ITINS_P, HasBWI, 1>;
2813defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2814 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2815
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2816defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2817 SSE_INTALU_ITINS_P, HasBWI, 1>;
2818defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2819 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2820defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2821 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2822
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2823defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2824 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2825defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
2826 SSE_INTALU_ITINS_P, HasBWI, 1>;
2827defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
2828 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2829
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2830defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
2831 SSE_INTALU_ITINS_P, HasBWI, 1>;
2832defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
2833 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2834defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
2835 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2836
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2837def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2838 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2839 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2840def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2841 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2842 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2843def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2844 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2845 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2846def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2847 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2848 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2849def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2850 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2851 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2852def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2853 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2854 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2855def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2856 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2857 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2858def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2859 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2860 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2861//===----------------------------------------------------------------------===//
2862// AVX-512 - Unpack Instructions
2863//===----------------------------------------------------------------------===//
2864
2865multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2866 PatFrag mem_frag, RegisterClass RC,
2867 X86MemOperand x86memop, string asm,
2868 Domain d> {
2869 def rr : AVX512PI<opc, MRMSrcReg,
2870 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2871 asm, [(set RC:$dst,
2872 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2873 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2874 def rm : AVX512PI<opc, MRMSrcMem,
2875 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2876 asm, [(set RC:$dst,
2877 (vt (OpNode RC:$src1,
2878 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2879 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2880}
2881
2882defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2883 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2884 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2885defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2886 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2887 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2888defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2889 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2890 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2891defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2892 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2893 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2894
2895multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2896 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2897 X86MemOperand x86memop> {
2898 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2899 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2900 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2901 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2902 IIC_SSE_UNPCK>, EVEX_4V;
2903 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2904 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2905 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2906 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2907 (bitconvert (memop_frag addr:$src2)))))],
2908 IIC_SSE_UNPCK>, EVEX_4V;
2909}
2910defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2911 VR512, memopv16i32, i512mem>, EVEX_V512,
2912 EVEX_CD8<32, CD8VF>;
2913defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2914 VR512, memopv8i64, i512mem>, EVEX_V512,
2915 VEX_W, EVEX_CD8<64, CD8VF>;
2916defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2917 VR512, memopv16i32, i512mem>, EVEX_V512,
2918 EVEX_CD8<32, CD8VF>;
2919defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2920 VR512, memopv8i64, i512mem>, EVEX_V512,
2921 VEX_W, EVEX_CD8<64, CD8VF>;
2922//===----------------------------------------------------------------------===//
2923// AVX-512 - PSHUFD
2924//
2925
2926multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2927 SDNode OpNode, PatFrag mem_frag,
2928 X86MemOperand x86memop, ValueType OpVT> {
2929 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2930 (ins RC:$src1, i8imm:$src2),
2931 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2932 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2933 [(set RC:$dst,
2934 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2935 EVEX;
2936 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2937 (ins x86memop:$src1, i8imm:$src2),
2938 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2939 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2940 [(set RC:$dst,
2941 (OpVT (OpNode (mem_frag addr:$src1),
2942 (i8 imm:$src2))))]>, EVEX;
2943}
2944
2945defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2946 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2947
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2948//===----------------------------------------------------------------------===//
2949// AVX-512 Logical Instructions
2950//===----------------------------------------------------------------------===//
2951
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2952defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
2953 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2954defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
2955 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2956defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
2957 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2958defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
2959 SSE_INTALU_ITINS_P, HasAVX512, 1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2960
2961//===----------------------------------------------------------------------===//
2962// AVX-512 FP arithmetic
2963//===----------------------------------------------------------------------===//
2964
2965multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2966 SizeItins itins> {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2967 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2968 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2969 EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2970 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2971 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2972 EVEX_CD8<64, CD8VT1>;
2973}
2974
2975let isCommutable = 1 in {
2976defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2977defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2978defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2979defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2980}
2981let isCommutable = 0 in {
2982defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2983defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2984}
2985
2986multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanov595e5982014-10-29 15:43:02 +0000[diff] [blame]2987 X86VectorVTInfo _, bit IsCommutable> {
2988 defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
2989 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2990 "$src2, $src1", "$src1, $src2",
2991 (_.VT (OpNode _.RC:$src1, _.RC:$src2))>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2992 let mayLoad = 1 in {
Robert Khasanov595e5982014-10-29 15:43:02 +0000[diff] [blame]2993 defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2994 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2995 "$src2, $src1", "$src1, $src2",
2996 (OpNode _.RC:$src1, (_.LdFrag addr:$src2))>, EVEX_4V;
2997 defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
2998 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2999 "${src2}"##_.BroadcastStr##", $src1",
3000 "$src1, ${src2}"##_.BroadcastStr,
3001 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3002 (_.ScalarLdFrag addr:$src2))))>,
3003 EVEX_4V, EVEX_B;
3004 }//let mayLoad = 1
3005}
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3006
Robert Khasanov595e5982014-10-29 15:43:02 +0000[diff] [blame]3007multiclass avx512_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3008 bit IsCommutable = 0> {
3009 defm PSZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v16f32_info,
3010 IsCommutable>, EVEX_V512, PS,
3011 EVEX_CD8<32, CD8VF>;
3012 defm PDZ : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f64_info,
3013 IsCommutable>, EVEX_V512, PD, VEX_W,
3014 EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3015
Robert Khasanov595e5982014-10-29 15:43:02 +0000[diff] [blame]3016 // Define only if AVX512VL feature is present.
3017 let Predicates = [HasVLX] in {
3018 defm PSZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f32x_info,
3019 IsCommutable>, EVEX_V128, PS,
3020 EVEX_CD8<32, CD8VF>;
3021 defm PSZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v8f32x_info,
3022 IsCommutable>, EVEX_V256, PS,
3023 EVEX_CD8<32, CD8VF>;
3024 defm PDZ128 : avx512_fp_packed<opc, OpcodeStr, OpNode, v2f64x_info,
3025 IsCommutable>, EVEX_V128, PD, VEX_W,
3026 EVEX_CD8<64, CD8VF>;
3027 defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
3028 IsCommutable>, EVEX_V256, PD, VEX_W,
3029 EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3030 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3031}
3032
Robert Khasanov595e5982014-10-29 15:43:02 +0000[diff] [blame]3033defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, 1>;
3034defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, 1>;
3035defm VMIN : avx512_fp_binop_p<0x5D, "vmin", X86fmin, 1>;
3036defm VMAX : avx512_fp_binop_p<0x5F, "vmax", X86fmax, 1>;
3037defm VSUB : avx512_fp_binop_p<0x5C, "vsub", fsub>;
3038defm VDIV : avx512_fp_binop_p<0x5E, "vdiv", fdiv>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3039
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3040def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3041 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3042 (i16 -1), FROUND_CURRENT)),
3043 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3044
3045def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3046 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3047 (i8 -1), FROUND_CURRENT)),
3048 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3049
3050def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3051 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3052 (i16 -1), FROUND_CURRENT)),
3053 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3054
3055def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3056 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3057 (i8 -1), FROUND_CURRENT)),
3058 (VMINPDZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3059//===----------------------------------------------------------------------===//
3060// AVX-512 VPTESTM instructions
3061//===----------------------------------------------------------------------===//
3062
3063multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3064 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3065 SDNode OpNode, ValueType vt> {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3066 def rr : AVX512PI<opc, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3067 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3068 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3069 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3070 SSEPackedInt>, EVEX_4V;
3071 def rm : AVX512PI<opc, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3072 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3073 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3074 [(set KRC:$dst, (OpNode (vt RC:$src1),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3075 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3076}
3077
3078defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3079 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3080 EVEX_CD8<32, CD8VF>;
3081defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3082 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3083 EVEX_CD8<64, CD8VF>;
3084
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3085let Predicates = [HasCDI] in {
3086defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3087 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3088 EVEX_CD8<32, CD8VF>;
3089defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3090 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3091 EVEX_CD8<64, CD8VF>;
3092}
3093
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3094def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3095 (v16i32 VR512:$src2), (i16 -1))),
3096 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3097
3098def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3099 (v8i64 VR512:$src2), (i8 -1))),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3100 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3101//===----------------------------------------------------------------------===//
3102// AVX-512 Shift instructions
3103//===----------------------------------------------------------------------===//
3104multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3105 string OpcodeStr, SDNode OpNode, RegisterClass RC,
3106 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
3107 RegisterClass KRC> {
3108 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3109 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3110 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3111 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3112 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3113 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3114 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3115 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3116 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3117 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3118 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3119 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3120 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3121 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3122 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3123 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3124 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3125 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3126 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3127 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3128}
3129
3130multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3131 RegisterClass RC, ValueType vt, ValueType SrcVT,
3132 PatFrag bc_frag, RegisterClass KRC> {
3133 // src2 is always 128-bit
3134 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3135 (ins RC:$src1, VR128X:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3136 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3137 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3138 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3139 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3140 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3141 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3142 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3143 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3144 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3145 (ins RC:$src1, i128mem:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3146 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3147 [(set RC:$dst, (vt (OpNode RC:$src1,
3148 (bc_frag (memopv2i64 addr:$src2)))))],
3149 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3150 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3151 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3152 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3153 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3154 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3155}
3156
3157defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3158 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3159 EVEX_V512, EVEX_CD8<32, CD8VF>;
3160defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3161 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3162 EVEX_CD8<32, CD8VQ>;
3163
3164defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3165 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3166 EVEX_CD8<64, CD8VF>, VEX_W;
3167defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3168 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3169 EVEX_CD8<64, CD8VQ>, VEX_W;
3170
3171defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3172 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3173 EVEX_CD8<32, CD8VF>;
3174defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3175 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3176 EVEX_CD8<32, CD8VQ>;
3177
3178defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3179 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3180 EVEX_CD8<64, CD8VF>, VEX_W;
3181defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3182 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3183 EVEX_CD8<64, CD8VQ>, VEX_W;
3184
3185defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3186 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3187 EVEX_V512, EVEX_CD8<32, CD8VF>;
3188defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3189 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3190 EVEX_CD8<32, CD8VQ>;
3191
3192defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3193 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3194 EVEX_CD8<64, CD8VF>, VEX_W;
3195defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3196 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3197 EVEX_CD8<64, CD8VQ>, VEX_W;
3198
3199//===-------------------------------------------------------------------===//
3200// Variable Bit Shifts
3201//===-------------------------------------------------------------------===//
3202multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3203 RegisterClass RC, ValueType vt,
3204 X86MemOperand x86memop, PatFrag mem_frag> {
3205 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3206 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3207 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3208 [(set RC:$dst,
3209 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3210 EVEX_4V;
3211 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3212 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3213 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3214 [(set RC:$dst,
3215 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3216 EVEX_4V;
3217}
3218
3219defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3220 i512mem, memopv16i32>, EVEX_V512,
3221 EVEX_CD8<32, CD8VF>;
3222defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3223 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3224 EVEX_CD8<64, CD8VF>;
3225defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3226 i512mem, memopv16i32>, EVEX_V512,
3227 EVEX_CD8<32, CD8VF>;
3228defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3229 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3230 EVEX_CD8<64, CD8VF>;
3231defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3232 i512mem, memopv16i32>, EVEX_V512,
3233 EVEX_CD8<32, CD8VF>;
3234defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3235 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3236 EVEX_CD8<64, CD8VF>;
3237
3238//===----------------------------------------------------------------------===//
3239// AVX-512 - MOVDDUP
3240//===----------------------------------------------------------------------===//
3241
3242multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3243 X86MemOperand x86memop, PatFrag memop_frag> {
3244def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3245 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3246 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3247def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3248 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3249 [(set RC:$dst,
3250 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3251}
3252
3253defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3254 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3255def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3256 (VMOVDDUPZrm addr:$src)>;
3257
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3258//===---------------------------------------------------------------------===//
3259// Replicate Single FP - MOVSHDUP and MOVSLDUP
3260//===---------------------------------------------------------------------===//
3261multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3262 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3263 X86MemOperand x86memop> {
3264 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3265 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3266 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3267 let mayLoad = 1 in
3268 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3269 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3270 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3271}
3272
3273defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3274 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3275 EVEX_CD8<32, CD8VF>;
3276defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3277 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3278 EVEX_CD8<32, CD8VF>;
3279
3280def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3281def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3282 (VMOVSHDUPZrm addr:$src)>;
3283def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3284def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3285 (VMOVSLDUPZrm addr:$src)>;
3286
3287//===----------------------------------------------------------------------===//
3288// Move Low to High and High to Low packed FP Instructions
3289//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3290def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3291 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3292 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3293 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3294 IIC_SSE_MOV_LH>, EVEX_4V;
3295def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3296 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3297 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3298 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3299 IIC_SSE_MOV_LH>, EVEX_4V;
3300
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3301let Predicates = [HasAVX512] in {
3302 // MOVLHPS patterns
3303 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3304 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3305 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3306 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3307
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3308 // MOVHLPS patterns
3309 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3310 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3311}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3312
3313//===----------------------------------------------------------------------===//
3314// FMA - Fused Multiply Operations
3315//
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3316
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3317let Constraints = "$src1 = $dst" in {
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3318// Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3319multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3320 SDPatternOperator OpNode = null_frag> {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]3321 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3322 (ins _.RC:$src2, _.RC:$src3),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3323 OpcodeStr, "$src3, $src2", "$src2, $src3",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3324 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3325 AVX512FMA3Base;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3326
3327 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3328 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3329 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3330 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3331 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3332 (_.MemOpFrag addr:$src3))))]>;
3333 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3334 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3335 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3336 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3337 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3338 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3339}
3340} // Constraints = "$src1 = $dst"
3341
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3342multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3343 string OpcodeStr, X86VectorVTInfo VTI,
3344 SDPatternOperator OpNode> {
3345 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3346 VTI, OpNode>,
3347 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3348
3349 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3350 VTI>,
3351 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3352}
3353
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3354let ExeDomain = SSEPackedSingle in {
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3355 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3356 v16f32_info, X86Fmadd>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3357 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3358 v16f32_info, X86Fmsub>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3359 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3360 v16f32_info, X86Fmaddsub>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3361 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3362 v16f32_info, X86Fmsubadd>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3363 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3364 v16f32_info, X86Fnmadd>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3365 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3366 v16f32_info, X86Fnmsub>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3367}
3368let ExeDomain = SSEPackedDouble in {
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3369 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3370 v8f64_info, X86Fmadd>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3371 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3372 v8f64_info, X86Fmsub>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3373 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3374 v8f64_info, X86Fmaddsub>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3375 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3376 v8f64_info, X86Fmsubadd>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3377 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3378 v8f64_info, X86Fnmadd>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3379 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3380 v8f64_info, X86Fnmsub>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3381}
3382
3383let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3384multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3385 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3386 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3387 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3388 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3389 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3390 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3391 _.RC:$src3)))]>;
3392 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3393 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3394 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3395 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3396 [(set _.RC:$dst,
3397 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3398 (_.ScalarLdFrag addr:$src2))),
3399 _.RC:$src3))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3400}
3401} // Constraints = "$src1 = $dst"
3402
3403
3404let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3405 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3406 v16f32_info>,
3407 EVEX_V512, EVEX_CD8<32, CD8VF>;
3408 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3409 v16f32_info>,
3410 EVEX_V512, EVEX_CD8<32, CD8VF>;
3411 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3412 v16f32_info>,
3413 EVEX_V512, EVEX_CD8<32, CD8VF>;
3414 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3415 v16f32_info>,
3416 EVEX_V512, EVEX_CD8<32, CD8VF>;
3417 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3418 v16f32_info>,
3419 EVEX_V512, EVEX_CD8<32, CD8VF>;
3420 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3421 v16f32_info>,
3422 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3423}
3424let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3425 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3426 v8f64_info>,
3427 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3428 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3429 v8f64_info>,
3430 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3431 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3432 v8f64_info>,
3433 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3434 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3435 v8f64_info>,
3436 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3437 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3438 v8f64_info>,
3439 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3440 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3441 v8f64_info>,
3442 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3443}
3444
3445// Scalar FMA
3446let Constraints = "$src1 = $dst" in {
3447multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3448 RegisterClass RC, ValueType OpVT,
3449 X86MemOperand x86memop, Operand memop,
3450 PatFrag mem_frag> {
3451 let isCommutable = 1 in
3452 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3453 (ins RC:$src1, RC:$src2, RC:$src3),
3454 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3455 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3456 [(set RC:$dst,
3457 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3458 let mayLoad = 1 in
3459 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3460 (ins RC:$src1, RC:$src2, f128mem:$src3),
3461 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3462 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3463 [(set RC:$dst,
3464 (OpVT (OpNode RC:$src2, RC:$src1,
3465 (mem_frag addr:$src3))))]>;
3466}
3467
3468} // Constraints = "$src1 = $dst"
3469
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3470defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3471 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3472defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3473 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3474defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3475 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3476defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3477 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3478defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3479 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3480defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3481 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3482defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3483 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3484defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3485 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3486
3487//===----------------------------------------------------------------------===//
3488// AVX-512 Scalar convert from sign integer to float/double
3489//===----------------------------------------------------------------------===//
3490
3491multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3492 X86MemOperand x86memop, string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3493let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3494 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3495 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3496 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3497 let mayLoad = 1 in
3498 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3499 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3500 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3501 EVEX_4V;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3502} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3503}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3504let Predicates = [HasAVX512] in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3505defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3506 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3507defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3508 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3509defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3510 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3511defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3512 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3513
3514def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3515 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3516def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3517 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3518def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3519 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3520def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3521 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3522
3523def : Pat<(f32 (sint_to_fp GR32:$src)),
3524 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3525def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3526 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3527def : Pat<(f64 (sint_to_fp GR32:$src)),
3528 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3529def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3530 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3531
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3532defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3533 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3534defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3535 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3536defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3537 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3538defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3539 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3540
3541def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3542 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3543def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3544 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3545def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3546 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3547def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3548 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3549
3550def : Pat<(f32 (uint_to_fp GR32:$src)),
3551 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3552def : Pat<(f32 (uint_to_fp GR64:$src)),
3553 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3554def : Pat<(f64 (uint_to_fp GR32:$src)),
3555 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3556def : Pat<(f64 (uint_to_fp GR64:$src)),
3557 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3558}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3559
3560//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3561// AVX-512 Scalar convert from float/double to integer
3562//===----------------------------------------------------------------------===//
3563multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3564 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3565 string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3566let hasSideEffects = 0 in {
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3567 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3568 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3569 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3570 Requires<[HasAVX512]>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3571 let mayLoad = 1 in
3572 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3573 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3574 Requires<[HasAVX512]>;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3575} // hasSideEffects = 0
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3576}
3577let Predicates = [HasAVX512] in {
3578// Convert float/double to signed/unsigned int 32/64
3579defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3580 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3581 XS, EVEX_CD8<32, CD8VT1>;
3582defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3583 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3584 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3585defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3586 ssmem, sse_load_f32, "cvtss2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3587 XS, EVEX_CD8<32, CD8VT1>;
3588defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3589 int_x86_avx512_cvtss2usi64, ssmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3590 sse_load_f32, "cvtss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3591 EVEX_CD8<32, CD8VT1>;
3592defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3593 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3594 XD, EVEX_CD8<64, CD8VT1>;
3595defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3596 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3597 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3598defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3599 sdmem, sse_load_f64, "cvtsd2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3600 XD, EVEX_CD8<64, CD8VT1>;
3601defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3602 int_x86_avx512_cvtsd2usi64, sdmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3603 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3604 EVEX_CD8<64, CD8VT1>;
3605
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3606let isCodeGenOnly = 1 in {
3607 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3608 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3609 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3610 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3611 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3612 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3613 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3614 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3615 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3616 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3617 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3618 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3619
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3620 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3621 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3622 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3623 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3624 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3625 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3626 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3627 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3628 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3629 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3630 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3631 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3632} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3633
3634// Convert float/double to signed/unsigned int 32/64 with truncation
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3635let isCodeGenOnly = 1 in {
3636 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3637 ssmem, sse_load_f32, "cvttss2si">,
3638 XS, EVEX_CD8<32, CD8VT1>;
3639 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3640 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3641 "cvttss2si">, XS, VEX_W,
3642 EVEX_CD8<32, CD8VT1>;
3643 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3644 sdmem, sse_load_f64, "cvttsd2si">, XD,
3645 EVEX_CD8<64, CD8VT1>;
3646 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3647 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3648 "cvttsd2si">, XD, VEX_W,
3649 EVEX_CD8<64, CD8VT1>;
3650 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3651 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3652 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3653 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3654 int_x86_avx512_cvttss2usi64, ssmem,
3655 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3656 EVEX_CD8<32, CD8VT1>;
3657 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3658 int_x86_avx512_cvttsd2usi,
3659 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3660 EVEX_CD8<64, CD8VT1>;
3661 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3662 int_x86_avx512_cvttsd2usi64, sdmem,
3663 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3664 EVEX_CD8<64, CD8VT1>;
3665} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3666
3667multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3668 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3669 string asm> {
3670 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3671 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3672 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3673 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3674 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3675 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3676}
3677
3678defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3679 loadf32, "cvttss2si">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3680 EVEX_CD8<32, CD8VT1>;
3681defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3682 loadf32, "cvttss2usi">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3683 EVEX_CD8<32, CD8VT1>;
3684defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3685 loadf32, "cvttss2si">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3686 EVEX_CD8<32, CD8VT1>;
3687defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3688 loadf32, "cvttss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3689 EVEX_CD8<32, CD8VT1>;
3690defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3691 loadf64, "cvttsd2si">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3692 EVEX_CD8<64, CD8VT1>;
3693defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3694 loadf64, "cvttsd2usi">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3695 EVEX_CD8<64, CD8VT1>;
3696defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3697 loadf64, "cvttsd2si">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3698 EVEX_CD8<64, CD8VT1>;
3699defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3700 loadf64, "cvttsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3701 EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3702} // HasAVX512
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3703//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3704// AVX-512 Convert form float to double and back
3705//===----------------------------------------------------------------------===//
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3706let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3707def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3708 (ins FR32X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3709 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3710 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3711let mayLoad = 1 in
3712def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3713 (ins FR32X:$src1, f32mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3714 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3715 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3716 EVEX_CD8<32, CD8VT1>;
3717
3718// Convert scalar double to scalar single
3719def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3720 (ins FR64X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3721 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3722 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3723let mayLoad = 1 in
3724def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3725 (ins FR64X:$src1, f64mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3726 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3727 []>, EVEX_4V, VEX_LIG, VEX_W,
3728 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3729}
3730
3731def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3732 Requires<[HasAVX512]>;
3733def : Pat<(fextend (loadf32 addr:$src)),
3734 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3735
3736def : Pat<(extloadf32 addr:$src),
3737 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3738 Requires<[HasAVX512, OptForSize]>;
3739
3740def : Pat<(extloadf32 addr:$src),
3741 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3742 Requires<[HasAVX512, OptForSpeed]>;
3743
3744def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3745 Requires<[HasAVX512]>;
3746
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3747multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3748 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3749 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3750 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3751let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3752 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3753 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3754 [(set DstRC:$dst,
3755 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3756 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3757 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3758 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3759 let mayLoad = 1 in
3760 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3761 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3762 [(set DstRC:$dst,
3763 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3764} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3765}
3766
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3767multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3768 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3769 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3770 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3771let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3772 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3773 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3774 [(set DstRC:$dst,
3775 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3776 let mayLoad = 1 in
3777 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3778 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3779 [(set DstRC:$dst,
3780 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3781} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3782}
3783
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3784defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3785 memopv8f64, f512mem, v8f32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3786 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3787 EVEX_CD8<64, CD8VF>;
3788
3789defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3790 memopv4f64, f256mem, v8f64, v8f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3791 SSEPackedDouble>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3792 EVEX_CD8<32, CD8VH>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3793def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3794 (VCVTPS2PDZrm addr:$src)>;
Elena Demikhovsky3629b4a2014-01-06 08:45:54 +0000[diff] [blame]3795
3796def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3797 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3798 (VCVTPD2PSZrr VR512:$src)>;
3799
3800def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3801 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3802 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3803
3804//===----------------------------------------------------------------------===//
3805// AVX-512 Vector convert from sign integer to float/double
3806//===----------------------------------------------------------------------===//
3807
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3808defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3809 memopv8i64, i512mem, v16f32, v16i32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3810 SSEPackedSingle>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3811 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3812
3813defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3814 memopv4i64, i256mem, v8f64, v8i32,
3815 SSEPackedDouble>, EVEX_V512, XS,
3816 EVEX_CD8<32, CD8VH>;
3817
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3818defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3819 memopv16f32, f512mem, v16i32, v16f32,
3820 SSEPackedSingle>, EVEX_V512, XS,
3821 EVEX_CD8<32, CD8VF>;
3822
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3823defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3824 memopv8f64, f512mem, v8i32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3825 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3826 EVEX_CD8<64, CD8VF>;
3827
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3828defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3829 memopv16f32, f512mem, v16i32, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3830 SSEPackedSingle>, EVEX_V512, PS,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3831 EVEX_CD8<32, CD8VF>;
3832
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3833// cvttps2udq (src, 0, mask-all-ones, sae-current)
3834def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3835 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3836 (VCVTTPS2UDQZrr VR512:$src)>;
3837
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3838defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3839 memopv8f64, f512mem, v8i32, v8f64,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3840 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3841 EVEX_CD8<64, CD8VF>;
3842
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3843// cvttpd2udq (src, 0, mask-all-ones, sae-current)
3844def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3845 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3846 (VCVTTPD2UDQZrr VR512:$src)>;
3847
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3848defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3849 memopv4i64, f256mem, v8f64, v8i32,
3850 SSEPackedDouble>, EVEX_V512, XS,
3851 EVEX_CD8<32, CD8VH>;
3852
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3853defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3854 memopv16i32, f512mem, v16f32, v16i32,
3855 SSEPackedSingle>, EVEX_V512, XD,
3856 EVEX_CD8<32, CD8VF>;
3857
3858def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3859 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3860 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3861
Elena Demikhovsky3dcfbdf2014-04-08 07:24:02 +0000[diff] [blame]3862def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3863 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3864 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3865
3866def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3867 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3868 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3869
3870def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3871 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3872 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3873
Cameron McInallyf10a7c92014-06-18 14:04:37 +0000[diff] [blame]3874def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3875 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3876 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3877
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3878def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3879 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3880 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3881def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3882 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3883 (VCVTDQ2PDZrr VR256X:$src)>;
3884def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3885 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3886 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3887def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3888 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3889 (VCVTUDQ2PDZrr VR256X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3890
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3891multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3892 RegisterClass DstRC, PatFrag mem_frag,
3893 X86MemOperand x86memop, Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3894let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3895 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3896 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3897 [], d>, EVEX;
3898 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3899 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3900 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3901 let mayLoad = 1 in
3902 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3903 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3904 [], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3905} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3906}
3907
3908defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3909 memopv16f32, f512mem, SSEPackedSingle>, PD,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3910 EVEX_V512, EVEX_CD8<32, CD8VF>;
3911defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3912 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3913 EVEX_V512, EVEX_CD8<64, CD8VF>;
3914
3915def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3916 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3917 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3918
3919def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3920 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3921 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3922
3923defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3924 memopv16f32, f512mem, SSEPackedSingle>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3925 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3926defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3927 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3928 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3929
3930def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3931 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3932 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3933
3934def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3935 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3936 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3937
3938let Predicates = [HasAVX512] in {
3939 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3940 (VCVTPD2PSZrm addr:$src)>;
3941 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3942 (VCVTPS2PDZrm addr:$src)>;
3943}
3944
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3945//===----------------------------------------------------------------------===//
3946// Half precision conversion instructions
3947//===----------------------------------------------------------------------===//
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3948multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3949 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3950 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3951 "vcvtph2ps\t{$src, $dst|$dst, $src}",
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3952 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3953 let hasSideEffects = 0, mayLoad = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3954 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3955 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3956}
3957
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3958multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3959 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3960 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3961 (ins srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3962 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3963 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3964 let hasSideEffects = 0, mayStore = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3965 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3966 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3967 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3968}
3969
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3970defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3971 EVEX_CD8<32, CD8VH>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3972defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3973 EVEX_CD8<32, CD8VH>;
3974
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3975def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3976 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3977 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3978
3979def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3980 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3981 (VCVTPH2PSZrr VR256X:$src)>;
3982
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3983let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3984 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3985 "ucomiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3986 EVEX_CD8<32, CD8VT1>;
3987 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3988 "ucomisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3989 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3990 let Pattern = []<dag> in {
3991 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3992 "comiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3993 EVEX_CD8<32, CD8VT1>;
3994 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3995 "comisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3996 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3997 }
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3998 let isCodeGenOnly = 1 in {
3999 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4000 load, "ucomiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4001 EVEX_CD8<32, CD8VT1>;
4002 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4003 load, "ucomisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4004 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4005
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4006 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4007 load, "comiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4008 EVEX_CD8<32, CD8VT1>;
4009 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4010 load, "comisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4011 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4012 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4013}
4014
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4015/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4016multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4017 X86MemOperand x86memop> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4018 let hasSideEffects = 0 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4019 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4020 (ins RC:$src1, RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4021 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4022 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4023 let mayLoad = 1 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4024 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4025 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4026 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4027 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4028 }
4029}
4030}
4031
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4032defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4033 EVEX_CD8<32, CD8VT1>;
4034defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4035 VEX_W, EVEX_CD8<64, CD8VT1>;
4036defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4037 EVEX_CD8<32, CD8VT1>;
4038defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4039 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4040
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4041def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4042 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4043 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4044 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4045
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4046def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4047 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4048 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4049 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4050
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4051def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4052 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4053 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4054 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4055
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4056def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4057 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4058 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4059 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4060
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4061/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4062multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanov3e534c92014-10-28 16:37:13 +0000[diff] [blame]4063 X86VectorVTInfo _> {
4064 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
4065 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4066 (_.FloatVT (OpNode _.RC:$src))>, EVEX, T8PD;
4067 let mayLoad = 1 in {
4068 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4069 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4070 (OpNode (_.FloatVT
4071 (bitconvert (_.LdFrag addr:$src))))>, EVEX, T8PD;
4072 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
4073 (ins _.ScalarMemOp:$src), OpcodeStr,
4074 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4075 (OpNode (_.FloatVT
4076 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4077 EVEX, T8PD, EVEX_B;
4078 }
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4079}
Robert Khasanov3e534c92014-10-28 16:37:13 +0000[diff] [blame]4080
4081multiclass avx512_fp14_p_vl_all<bits<8> opc, string OpcodeStr, SDNode OpNode> {
4082 defm PSZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"), OpNode, v16f32_info>,
4083 EVEX_V512, EVEX_CD8<32, CD8VF>;
4084 defm PDZ : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"), OpNode, v8f64_info>,
4085 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4086
4087 // Define only if AVX512VL feature is present.
4088 let Predicates = [HasVLX] in {
4089 defm PSZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4090 OpNode, v4f32x_info>,
4091 EVEX_V128, EVEX_CD8<32, CD8VF>;
4092 defm PSZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "ps"),
4093 OpNode, v8f32x_info>,
4094 EVEX_V256, EVEX_CD8<32, CD8VF>;
4095 defm PDZ128 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4096 OpNode, v2f64x_info>,
4097 EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
4098 defm PDZ256 : avx512_fp14_p<opc, !strconcat(OpcodeStr, "pd"),
4099 OpNode, v4f64x_info>,
4100 EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
4101 }
4102}
4103
4104defm VRSQRT14 : avx512_fp14_p_vl_all<0x4E, "vrsqrt14", X86frsqrt>;
4105defm VRCP14 : avx512_fp14_p_vl_all<0x4C, "vrcp14", X86frcp>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4106
4107def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4108 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4109 (VRSQRT14PSZr VR512:$src)>;
4110def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4111 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4112 (VRSQRT14PDZr VR512:$src)>;
4113
4114def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4115 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4116 (VRCP14PSZr VR512:$src)>;
4117def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4118 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4119 (VRCP14PDZr VR512:$src)>;
4120
4121/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4122multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4123 X86MemOperand x86memop> {
4124 let hasSideEffects = 0, Predicates = [HasERI] in {
4125 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4126 (ins RC:$src1, RC:$src2),
4127 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4128 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4129 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4130 (ins RC:$src1, RC:$src2),
4131 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4132 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4133 []>, EVEX_4V, EVEX_B;
4134 let mayLoad = 1 in {
4135 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4136 (ins RC:$src1, x86memop:$src2),
4137 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4138 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4139 }
4140}
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4141}
4142
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4143defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4144 EVEX_CD8<32, CD8VT1>;
4145defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4146 VEX_W, EVEX_CD8<64, CD8VT1>;
4147defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4148 EVEX_CD8<32, CD8VT1>;
4149defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4150 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4151
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4152def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4153 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4154 FROUND_NO_EXC)),
4155 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4156 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4157
4158def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4159 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4160 FROUND_NO_EXC)),
4161 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4162 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4163
4164def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4165 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4166 FROUND_NO_EXC)),
4167 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4168 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4169
4170def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4171 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4172 FROUND_NO_EXC)),
4173 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4174 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4175
4176/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4177multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4178 RegisterClass RC, X86MemOperand x86memop> {
4179 let hasSideEffects = 0, Predicates = [HasERI] in {
4180 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4181 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4182 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4183 []>, EVEX;
4184 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4185 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4186 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4187 []>, EVEX, EVEX_B;
4188 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4189 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4190 []>, EVEX;
4191 }
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4192}
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4193defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4194 EVEX_V512, EVEX_CD8<32, CD8VF>;
4195defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4196 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4197defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4198 EVEX_V512, EVEX_CD8<32, CD8VF>;
4199defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4200 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4201
4202def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4203 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4204 (VRSQRT28PSZrb VR512:$src)>;
4205def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4206 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4207 (VRSQRT28PDZrb VR512:$src)>;
4208
4209def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4210 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4211 (VRCP28PSZrb VR512:$src)>;
4212def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4213 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4214 (VRCP28PDZrb VR512:$src)>;
4215
Robert Khasanoveb126392014-10-28 18:15:20 +0000[diff] [blame]4216multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
4217 SDNode OpNode, X86VectorVTInfo _>{
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]4218 defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
Robert Khasanoveb126392014-10-28 18:15:20 +0000[diff] [blame]4219 (ins _.RC:$src), OpcodeStr, "$src", "$src",
4220 (_.FloatVT (OpNode _.RC:$src))>, EVEX;
4221 let mayLoad = 1 in {
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]4222 defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanoveb126392014-10-28 18:15:20 +0000[diff] [blame]4223 (ins _.MemOp:$src), OpcodeStr, "$src", "$src",
4224 (OpNode (_.FloatVT
4225 (bitconvert (_.LdFrag addr:$src))))>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4226
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]4227 defm mb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanoveb126392014-10-28 18:15:20 +0000[diff] [blame]4228 (ins _.ScalarMemOp:$src), OpcodeStr,
4229 "${src}"##_.BroadcastStr, "${src}"##_.BroadcastStr,
4230 (OpNode (_.FloatVT
4231 (X86VBroadcast (_.ScalarLdFrag addr:$src))))>,
4232 EVEX, EVEX_B;
4233 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4234}
4235
4236multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4237 Intrinsic F32Int, Intrinsic F64Int,
4238 OpndItins itins_s, OpndItins itins_d> {
4239 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4240 (ins FR32X:$src1, FR32X:$src2),
4241 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4242 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4243 [], itins_s.rr>, XS, EVEX_4V;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4244 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4245 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4246 (ins VR128X:$src1, VR128X:$src2),
4247 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4248 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4249 [(set VR128X:$dst,
4250 (F32Int VR128X:$src1, VR128X:$src2))],
4251 itins_s.rr>, XS, EVEX_4V;
4252 let mayLoad = 1 in {
4253 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4254 (ins FR32X:$src1, f32mem:$src2),
4255 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4256 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4257 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4258 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4259 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4260 (ins VR128X:$src1, ssmem:$src2),
4261 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4262 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4263 [(set VR128X:$dst,
4264 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4265 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4266 }
4267 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4268 (ins FR64X:$src1, FR64X:$src2),
4269 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4270 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4271 XD, EVEX_4V, VEX_W;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4272 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4273 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4274 (ins VR128X:$src1, VR128X:$src2),
4275 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4276 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4277 [(set VR128X:$dst,
4278 (F64Int VR128X:$src1, VR128X:$src2))],
4279 itins_s.rr>, XD, EVEX_4V, VEX_W;
4280 let mayLoad = 1 in {
4281 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4282 (ins FR64X:$src1, f64mem:$src2),
4283 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4284 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4285 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4286 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4287 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4288 (ins VR128X:$src1, sdmem:$src2),
4289 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4290 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4291 [(set VR128X:$dst,
4292 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4293 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4294 }
4295}
4296
Robert Khasanoveb126392014-10-28 18:15:20 +0000[diff] [blame]4297multiclass avx512_sqrt_packed_all<bits<8> opc, string OpcodeStr,
4298 SDNode OpNode> {
4299 defm PSZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
4300 v16f32_info>,
4301 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
4302 defm PDZ : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
4303 v8f64_info>,
4304 EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4305 // Define only if AVX512VL feature is present.
4306 let Predicates = [HasVLX] in {
4307 defm PSZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4308 OpNode, v4f32x_info>,
4309 EVEX_V128, PS, EVEX_CD8<32, CD8VF>;
4310 defm PSZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "ps"),
4311 OpNode, v8f32x_info>,
4312 EVEX_V256, PS, EVEX_CD8<32, CD8VF>;
4313 defm PDZ128 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4314 OpNode, v2f64x_info>,
4315 EVEX_V128, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4316 defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
4317 OpNode, v4f64x_info>,
4318 EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
4319 }
4320}
4321
4322defm VSQRT : avx512_sqrt_packed_all<0x51, "vsqrt", fsqrt>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4323
4324defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4325 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
Robert Khasanoveb126392014-10-28 18:15:20 +0000[diff] [blame]4326 SSE_SQRTSS, SSE_SQRTSD>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4327
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4328let Predicates = [HasAVX512] in {
Elena Demikhovskyf1648592014-07-22 11:07:31 +0000[diff] [blame]4329 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4330 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]4331 (VSQRTPSZr VR512:$src1)>;
Elena Demikhovskyf1648592014-07-22 11:07:31 +0000[diff] [blame]4332 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4333 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]4334 (VSQRTPDZr VR512:$src1)>;
Elena Demikhovskyf1648592014-07-22 11:07:31 +0000[diff] [blame]4335
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4336 def : Pat<(f32 (fsqrt FR32X:$src)),
4337 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4338 def : Pat<(f32 (fsqrt (load addr:$src))),
4339 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4340 Requires<[OptForSize]>;
4341 def : Pat<(f64 (fsqrt FR64X:$src)),
4342 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4343 def : Pat<(f64 (fsqrt (load addr:$src))),
4344 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4345 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4346
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4347 def : Pat<(f32 (X86frsqrt FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4348 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4349 def : Pat<(f32 (X86frsqrt (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4350 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4351 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4352
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4353 def : Pat<(f32 (X86frcp FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4354 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4355 def : Pat<(f32 (X86frcp (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4356 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4357 Requires<[OptForSize]>;
4358
4359 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4360 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4361 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4362 VR128X)>;
4363 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4364 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4365
4366 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4367 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4368 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4369 VR128X)>;
4370 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4371 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4372}
4373
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4374
4375multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4376 X86MemOperand x86memop, RegisterClass RC,
4377 PatFrag mem_frag32, PatFrag mem_frag64,
4378 Intrinsic V4F32Int, Intrinsic V2F64Int,
4379 CD8VForm VForm> {
4380let ExeDomain = SSEPackedSingle in {
4381 // Intrinsic operation, reg.
4382 // Vector intrinsic operation, reg
4383 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4384 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4385 !strconcat(OpcodeStr,
4386 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4387 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4388
4389 // Vector intrinsic operation, mem
4390 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4391 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4392 !strconcat(OpcodeStr,
4393 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4394 [(set RC:$dst,
4395 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4396 EVEX_CD8<32, VForm>;
4397} // ExeDomain = SSEPackedSingle
4398
4399let ExeDomain = SSEPackedDouble in {
4400 // Vector intrinsic operation, reg
4401 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4402 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4403 !strconcat(OpcodeStr,
4404 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4405 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4406
4407 // Vector intrinsic operation, mem
4408 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4409 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4410 !strconcat(OpcodeStr,
4411 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4412 [(set RC:$dst,
4413 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4414 EVEX_CD8<64, VForm>;
4415} // ExeDomain = SSEPackedDouble
4416}
4417
4418multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4419 string OpcodeStr,
4420 Intrinsic F32Int,
4421 Intrinsic F64Int> {
4422let ExeDomain = GenericDomain in {
4423 // Operation, reg.
4424 let hasSideEffects = 0 in
4425 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4426 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4427 !strconcat(OpcodeStr,
4428 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4429 []>;
4430
4431 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4432 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4433 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4434 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4435 !strconcat(OpcodeStr,
4436 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4437 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4438
4439 // Intrinsic operation, mem.
4440 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4441 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4442 !strconcat(OpcodeStr,
4443 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4444 [(set VR128X:$dst, (F32Int VR128X:$src1,
4445 sse_load_f32:$src2, imm:$src3))]>,
4446 EVEX_CD8<32, CD8VT1>;
4447
4448 // Operation, reg.
4449 let hasSideEffects = 0 in
4450 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4451 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4452 !strconcat(OpcodeStr,
4453 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4454 []>, VEX_W;
4455
4456 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4457 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4458 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4459 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4460 !strconcat(OpcodeStr,
4461 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4462 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4463 VEX_W;
4464
4465 // Intrinsic operation, mem.
4466 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4467 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4468 !strconcat(OpcodeStr,
4469 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4470 [(set VR128X:$dst,
4471 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4472 VEX_W, EVEX_CD8<64, CD8VT1>;
4473} // ExeDomain = GenericDomain
4474}
4475
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4476multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4477 X86MemOperand x86memop, RegisterClass RC,
4478 PatFrag mem_frag, Domain d> {
4479let ExeDomain = d in {
4480 // Intrinsic operation, reg.
4481 // Vector intrinsic operation, reg
4482 def r : AVX512AIi8<opc, MRMSrcReg,
4483 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4484 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4485 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4486 []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4487
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4488 // Vector intrinsic operation, mem
4489 def m : AVX512AIi8<opc, MRMSrcMem,
4490 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4491 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4492 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4493 []>, EVEX;
4494} // ExeDomain
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4495}
4496
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4497
4498defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4499 memopv16f32, SSEPackedSingle>, EVEX_V512,
4500 EVEX_CD8<32, CD8VF>;
4501
4502def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4503 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4504 FROUND_CURRENT)),
4505 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4506
4507
4508defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4509 memopv8f64, SSEPackedDouble>, EVEX_V512,
4510 VEX_W, EVEX_CD8<64, CD8VF>;
4511
4512def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4513 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4514 FROUND_CURRENT)),
4515 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4516
4517multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4518 Operand x86memop, RegisterClass RC, Domain d> {
4519let ExeDomain = d in {
4520 def r : AVX512AIi8<opc, MRMSrcReg,
4521 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4522 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4523 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4524 []>, EVEX_4V;
4525
4526 def m : AVX512AIi8<opc, MRMSrcMem,
4527 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4528 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4529 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4530 []>, EVEX_4V;
4531} // ExeDomain
4532}
4533
4534defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4535 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4536
4537defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4538 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4539
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4540def : Pat<(ffloor FR32X:$src),
4541 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4542def : Pat<(f64 (ffloor FR64X:$src)),
4543 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4544def : Pat<(f32 (fnearbyint FR32X:$src)),
4545 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4546def : Pat<(f64 (fnearbyint FR64X:$src)),
4547 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4548def : Pat<(f32 (fceil FR32X:$src)),
4549 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4550def : Pat<(f64 (fceil FR64X:$src)),
4551 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4552def : Pat<(f32 (frint FR32X:$src)),
4553 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4554def : Pat<(f64 (frint FR64X:$src)),
4555 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4556def : Pat<(f32 (ftrunc FR32X:$src)),
4557 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4558def : Pat<(f64 (ftrunc FR64X:$src)),
4559 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4560
4561def : Pat<(v16f32 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4562 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4563def : Pat<(v16f32 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4564 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4565def : Pat<(v16f32 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4566 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4567def : Pat<(v16f32 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4568 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4569def : Pat<(v16f32 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4570 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4571
4572def : Pat<(v8f64 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4573 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4574def : Pat<(v8f64 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4575 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4576def : Pat<(v8f64 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4577 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4578def : Pat<(v8f64 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4579 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4580def : Pat<(v8f64 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4581 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4582
4583//-------------------------------------------------
4584// Integer truncate and extend operations
4585//-------------------------------------------------
4586
4587multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4588 RegisterClass dstRC, RegisterClass srcRC,
4589 RegisterClass KRC, X86MemOperand x86memop> {
4590 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4591 (ins srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4592 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4593 []>, EVEX;
4594
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4595 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4596 (ins KRC:$mask, srcRC:$src),
4597 !strconcat(OpcodeStr,
4598 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4599 []>, EVEX, EVEX_K;
4600
4601 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4602 (ins KRC:$mask, srcRC:$src),
4603 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4604 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4605 []>, EVEX, EVEX_KZ;
4606
4607 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4608 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4609 []>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4610
4611 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4612 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4613 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4614 []>, EVEX, EVEX_K;
4615
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4616}
4617defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4618 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4619defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4620 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4621defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4622 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4623defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4624 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4625defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4626 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4627defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4628 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4629defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4630 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4631defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4632 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4633defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4634 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4635defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4636 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4637defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4638 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4639defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4640 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4641defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4642 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4643defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4644 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4645defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4646 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4647
4648def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4649def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4650def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4651def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4652def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4653
4654def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4655 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4656def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4657 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4658def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4659 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4660def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4661 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4662
4663
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4664multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4665 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4666 PatFrag mem_frag, X86MemOperand x86memop,
4667 ValueType OpVT, ValueType InVT> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4668
4669 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4670 (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4671 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4672 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4673
4674 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4675 (ins KRC:$mask, SrcRC:$src),
4676 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4677 []>, EVEX, EVEX_K;
4678
4679 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4680 (ins KRC:$mask, SrcRC:$src),
4681 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4682 []>, EVEX, EVEX_KZ;
4683
4684 let mayLoad = 1 in {
4685 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4686 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4687 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4688 [(set DstRC:$dst,
4689 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4690 EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4691
4692 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4693 (ins KRC:$mask, x86memop:$src),
4694 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4695 []>,
4696 EVEX, EVEX_K;
4697
4698 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4699 (ins KRC:$mask, x86memop:$src),
4700 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4701 []>,
4702 EVEX, EVEX_KZ;
4703 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4704}
4705
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4706defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4707 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4708 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4709defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4710 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4711 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4712defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4713 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4714 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4715defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4716 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4717 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4718defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4719 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4720 EVEX_CD8<32, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4721
4722defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4723 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4724 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4725defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4726 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4727 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4728defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4729 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4730 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4731defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4732 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4733 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4734defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4735 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4736 EVEX_CD8<32, CD8VH>;
4737
4738//===----------------------------------------------------------------------===//
4739// GATHER - SCATTER Operations
4740
4741multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4742 RegisterClass RC, X86MemOperand memop> {
4743let mayLoad = 1,
4744 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4745 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4746 (ins RC:$src1, KRC:$mask, memop:$src2),
4747 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4748 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4749 []>, EVEX, EVEX_K;
4750}
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4751
4752let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4753defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4754 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4755defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4756 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4757}
4758
4759let ExeDomain = SSEPackedSingle in {
4760defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4761 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4762defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4763 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4764}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4765
4766defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4767 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4768defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4769 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4770
4771defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4772 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4773defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4774 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4775
4776multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4777 RegisterClass RC, X86MemOperand memop> {
4778let mayStore = 1, Constraints = "$mask = $mask_wb" in
4779 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4780 (ins memop:$dst, KRC:$mask, RC:$src2),
4781 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4782 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4783 []>, EVEX, EVEX_K;
4784}
4785
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4786let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4787defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4788 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4789defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4790 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4791}
4792
4793let ExeDomain = SSEPackedSingle in {
4794defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4795 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4796defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4797 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4798}
4799
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4800defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4801 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4802defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4803 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4804
4805defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4806 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4807defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4808 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4809
Elena Demikhovsky8e8fde82014-05-12 07:18:51 +0000[diff] [blame]4810// prefetch
4811multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4812 RegisterClass KRC, X86MemOperand memop> {
4813 let Predicates = [HasPFI], hasSideEffects = 1 in
4814 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4815 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4816 []>, EVEX, EVEX_K;
4817}
4818
4819defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4820 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4821
4822defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4823 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4824
4825defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4826 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4827
4828defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4829 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4830
4831defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4832 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4833
4834defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4835 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4836
4837defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4838 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4839
4840defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4841 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4842
4843defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4844 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4845
4846defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4847 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4848
4849defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4850 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4851
4852defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4853 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4854
4855defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4856 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4857
4858defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4859 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4860
4861defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4862 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4863
4864defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4865 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4866//===----------------------------------------------------------------------===//
4867// VSHUFPS - VSHUFPD Operations
4868
4869multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4870 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4871 Domain d> {
4872 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4873 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4874 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4875 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4876 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4877 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4878 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4879 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4880 (ins RC:$src1, RC:$src2, i8imm:$src3),
4881 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4882 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4883 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4884 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4885 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4886}
4887
4888defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4889 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4890defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4891 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4892
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]4893def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4894 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4895def : Pat<(v16i32 (X86Shufp VR512:$src1,
4896 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4897 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4898
4899def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4900 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4901def : Pat<(v8i64 (X86Shufp VR512:$src1,
4902 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4903 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4904
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4905multiclass avx512_valign<X86VectorVTInfo _> {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]4906 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4907 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4908 "valign"##_.Suffix,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4909 "$src3, $src2, $src1", "$src1, $src2, $src3",
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4910 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]4911 (i8 imm:$src3)))>,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4912 AVX512AIi8Base, EVEX_4V;
Adam Nemetfd2161b2014-08-05 17:23:04 +0000[diff] [blame]4913
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4914 // Also match valign of packed floats.
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4915 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4916 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4917
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4918 let mayLoad = 1 in
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4919 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4920 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4921 !strconcat("valign"##_.Suffix,
Adam Nemet1c752d82014-08-05 17:22:47 +0000[diff] [blame]4922 " \t{$src3, $src2, $src1, $dst|"
4923 "$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4924 []>, EVEX_4V;
4925}
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4926defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4927defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4928
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4929// Helper fragments to match sext vXi1 to vXiY.
4930def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4931def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4932
4933multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4934 RegisterClass KRC, RegisterClass RC,
4935 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4936 string BrdcstStr> {
4937 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4938 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4939 []>, EVEX;
4940 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4941 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4942 []>, EVEX, EVEX_K;
4943 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4944 !strconcat(OpcodeStr,
4945 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4946 []>, EVEX, EVEX_KZ;
4947 let mayLoad = 1 in {
4948 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4949 (ins x86memop:$src),
4950 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4951 []>, EVEX;
4952 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4953 (ins KRC:$mask, x86memop:$src),
4954 !strconcat(OpcodeStr,
4955 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4956 []>, EVEX, EVEX_K;
4957 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4958 (ins KRC:$mask, x86memop:$src),
4959 !strconcat(OpcodeStr,
4960 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4961 []>, EVEX, EVEX_KZ;
4962 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4963 (ins x86scalar_mop:$src),
4964 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4965 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4966 []>, EVEX, EVEX_B;
4967 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4968 (ins KRC:$mask, x86scalar_mop:$src),
4969 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4970 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4971 []>, EVEX, EVEX_B, EVEX_K;
4972 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4973 (ins KRC:$mask, x86scalar_mop:$src),
4974 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4975 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4976 BrdcstStr, "}"),
4977 []>, EVEX, EVEX_B, EVEX_KZ;
4978 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4979}
4980
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4981defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4982 i512mem, i32mem, "{1to16}">, EVEX_V512,
4983 EVEX_CD8<32, CD8VF>;
4984defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4985 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4986 EVEX_CD8<64, CD8VF>;
4987
4988def : Pat<(xor
4989 (bc_v16i32 (v16i1sextv16i32)),
4990 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4991 (VPABSDZrr VR512:$src)>;
4992def : Pat<(xor
4993 (bc_v8i64 (v8i1sextv8i64)),
4994 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4995 (VPABSQZrr VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4996
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4997def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4998 (v16i32 immAllZerosV), (i16 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4999 (VPABSDZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]5000def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5001 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]5002 (VPABSQZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]5003
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5004multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5005 RegisterClass RC, RegisterClass KRC,
5006 X86MemOperand x86memop,
5007 X86MemOperand x86scalar_mop, string BrdcstStr> {
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5008 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5009 (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5010 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5011 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5012 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5013 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5014 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5015 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5016 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5017 (ins x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5018 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5019 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5020 []>, EVEX, EVEX_B;
5021 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5022 (ins KRC:$mask, RC:$src),
5023 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5024 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5025 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5026 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5027 (ins KRC:$mask, x86memop:$src),
5028 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5029 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5030 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5031 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5032 (ins KRC:$mask, x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5033 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5034 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5035 BrdcstStr, "}"),
5036 []>, EVEX, EVEX_KZ, EVEX_B;
5037
5038 let Constraints = "$src1 = $dst" in {
5039 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5040 (ins RC:$src1, KRC:$mask, RC:$src2),
5041 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5042 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5043 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5044 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5045 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5046 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5047 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5048 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5049 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5050 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5051 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5052 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5053 []>, EVEX, EVEX_K, EVEX_B;
5054 }
5055}
5056
5057let Predicates = [HasCDI] in {
5058defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5059 i512mem, i32mem, "{1to16}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5060 EVEX_V512, EVEX_CD8<32, CD8VF>;
5061
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5062
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5063defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5064 i512mem, i64mem, "{1to8}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5065 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5066
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5067}
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5068
5069def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5070 GR16:$mask),
5071 (VPCONFLICTDrrk VR512:$src1,
5072 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5073
5074def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5075 GR8:$mask),
5076 (VPCONFLICTQrrk VR512:$src1,
5077 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]5078
Cameron McInally5d1b7b92014-06-11 12:54:45 +0000[diff] [blame]5079let Predicates = [HasCDI] in {
5080defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5081 i512mem, i32mem, "{1to16}">,
5082 EVEX_V512, EVEX_CD8<32, CD8VF>;
5083
5084
5085defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5086 i512mem, i64mem, "{1to8}">,
5087 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5088
5089}
5090
5091def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5092 GR16:$mask),
5093 (VPLZCNTDrrk VR512:$src1,
5094 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5095
5096def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5097 GR8:$mask),
5098 (VPLZCNTQrrk VR512:$src1,
5099 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5100
Cameron McInally0d0489c2014-06-16 14:12:28 +0000[diff] [blame]5101def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5102 (VPLZCNTDrm addr:$src)>;
5103def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5104 (VPLZCNTDrr VR512:$src)>;
5105def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5106 (VPLZCNTQrm addr:$src)>;
5107def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5108 (VPLZCNTQrr VR512:$src)>;
5109
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]5110def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5111def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5112def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
Elena Demikhovskyacc5c9e2014-04-22 14:13:10 +0000[diff] [blame]5113
5114def : Pat<(store VK1:$src, addr:$dst),
5115 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5116
5117def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5118 (truncstore node:$val, node:$ptr), [{
5119 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5120}]>;
5121
5122def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5123 (MOV8mr addr:$dst, GR8:$src)>;
5124
Elena Demikhovsky44bf0632014-10-05 14:11:08 +0000[diff] [blame]5125multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5126def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5127 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
5128 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5129}
5130
5131multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5132 string OpcodeStr, Predicate prd> {
5133let Predicates = [prd] in
5134 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5135
5136 let Predicates = [prd, HasVLX] in {
5137 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5138 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5139 }
5140}
5141
5142multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5143 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5144 HasBWI>;
5145 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5146 HasBWI>, VEX_W;
5147 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5148 HasDQI>;
5149 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5150 HasDQI>, VEX_W;
5151}
5152
5153defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;