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gerrit-public.fairphone.software / toolchain / llvm-project / dd09a8f320d8dc0e5e57e68cc4e3d6dbb15ed4a3 / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: 3dbc3d2abd8fdd62775ee5af007321afb70f48bb [file] [log] [blame]
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]1// Group template arguments that can be derived from the vector type (EltNum x
2// EltVT). These are things like the register class for the writemask, etc.
3// The idea is to pass one of these as the template argument rather than the
4// individual arguments.
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]5class X86VectorVTInfo<int numelts, ValueType EltVT, RegisterClass rc,
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]6 string suffix = ""> {
7 RegisterClass RC = rc;
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]8 int NumElts = numelts;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]9
10 // Corresponding mask register class.
11 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
12
13 // Corresponding write-mask register class.
14 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
15
16 // The GPR register class that can hold the write mask. Use GR8 for fewer
17 // than 8 elements. Use shift-right and equal to work around the lack of
18 // !lt in tablegen.
19 RegisterClass MRC =
20 !cast<RegisterClass>("GR" #
21 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
22
23 // Suffix used in the instruction mnemonic.
24 string Suffix = suffix;
25
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]26 string VTName = "v" # NumElts # EltVT;
27
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]28 // The vector VT.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]29 ValueType VT = !cast<ValueType>(VTName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]30
31 string EltTypeName = !cast<string>(EltVT);
32 // Size of the element type in bits, e.g. 32 for v16i32.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]33 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
34 int EltSize = EltVT.Size;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]35
36 // "i" for integer types and "f" for floating-point types
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]37 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]38
39 // Size of RC in bits, e.g. 512 for VR512.
40 int Size = VT.Size;
41
42 // The corresponding memory operand, e.g. i512mem for VR512.
43 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]44 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
45
46 // Load patterns
47 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
48 // due to load promotion during legalization
49 PatFrag LdFrag = !cast<PatFrag>("load" #
50 !if (!eq (TypeVariantName, "i"),
51 !if (!eq (Size, 128), "v2i64",
52 !if (!eq (Size, 256), "v4i64",
53 VTName)), VTName));
54 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]55
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]56 // Load patterns used for memory operands. We only have this defined in
57 // case of i64 element types for sub-512 integer vectors. For now, keep
58 // MemOpFrag undefined in these cases.
59 PatFrag MemOpFrag =
60 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
62 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
63
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]64 // The corresponding float type, e.g. v16f32 for v16i32
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]65 // Note: For EltSize < 32, FloatVT is illegal and TableGen
66 // fails to compile, so we choose FloatVT = VT
67 ValueType FloatVT = !cast<ValueType>(
68 !if (!eq (!srl(EltSize,5),0),
69 VTName,
70 !if (!eq(TypeVariantName, "i"),
71 "v" # NumElts # "f" # EltSize,
72 VTName)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]73
74 // The string to specify embedded broadcast in assembly.
75 string BroadcastStr = "{1to" # NumElts # "}";
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]76
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]77 // 8-bit compressed displacement tuple/subvector format. This is only
78 // defined for NumElts <= 8.
79 CD8VForm CD8TupleForm = !if (!eq (!srl(NumElts, 4), 0),
80 !cast<CD8VForm>("CD8VT" # NumElts), ?);
81
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]82 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
83 !if (!eq (Size, 256), sub_ymm, ?));
84
85 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
86 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
87 SSEPackedInt));
Adam Nemet09377232014-10-08 23:25:31 +0000[diff] [blame]88
89 // A vector type of the same width with element type i32. This is used to
90 // create the canonical constant zero node ImmAllZerosV.
91 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
92 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]93}
94
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]95def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
96def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]97def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
98def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]99def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
100def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]101
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]102// "x" in v32i8x_info means RC = VR256X
103def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
104def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
105def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
106def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
107
108def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
109def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
110def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
111def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
112
113class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
114 X86VectorVTInfo i128> {
115 X86VectorVTInfo info512 = i512;
116 X86VectorVTInfo info256 = i256;
117 X86VectorVTInfo info128 = i128;
118}
119
120def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
121 v16i8x_info>;
122def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
123 v8i16x_info>;
124def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
125 v4i32x_info>;
126def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
127 v2i64x_info>;
128
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame]129// This multiclass generates the masking variants from the non-masking
130// variant. It only provides the assembly pieces for the masking variants.
131// It assumes custom ISel patterns for masking which can be provided as
132// template arguments.
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]133multiclass AVX512_maskable_custom<bits<8> O, Format F,
134 dag Outs,
135 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
136 string OpcodeStr,
137 string AttSrcAsm, string IntelSrcAsm,
138 list<dag> Pattern,
139 list<dag> MaskingPattern,
140 list<dag> ZeroMaskingPattern,
141 string MaskingConstraint = "",
142 InstrItinClass itin = NoItinerary,
143 bit IsCommutable = 0> {
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame]144 let isCommutable = IsCommutable in
145 def NAME: AVX512<O, F, Outs, Ins,
146 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
147 "$dst, "#IntelSrcAsm#"}",
148 Pattern, itin>;
149
150 // Prefer over VMOV*rrk Pat<>
151 let AddedComplexity = 20 in
152 def NAME#k: AVX512<O, F, Outs, MaskingIns,
153 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
154 "$dst {${mask}}, "#IntelSrcAsm#"}",
155 MaskingPattern, itin>,
156 EVEX_K {
157 // In case of the 3src subclass this is overridden with a let.
158 string Constraints = MaskingConstraint;
159 }
160 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
161 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
162 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
163 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
164 ZeroMaskingPattern,
165 itin>,
166 EVEX_KZ;
167}
168
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]169
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]170// Common base class of AVX512_maskable and AVX512_maskable_3src.
171multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
172 dag Outs,
173 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
174 string OpcodeStr,
175 string AttSrcAsm, string IntelSrcAsm,
176 dag RHS, dag MaskingRHS,
177 string MaskingConstraint = "",
178 InstrItinClass itin = NoItinerary,
179 bit IsCommutable = 0> :
180 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
181 AttSrcAsm, IntelSrcAsm,
182 [(set _.RC:$dst, RHS)],
183 [(set _.RC:$dst, MaskingRHS)],
184 [(set _.RC:$dst,
185 (vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
186 MaskingConstraint, NoItinerary, IsCommutable>;
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]187
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]188// This multiclass generates the unconditional/non-masking, the masking and
189// the zero-masking variant of the instruction. In the masking case, the
190// perserved vector elements come from a new dummy input operand tied to $dst.
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]191multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
192 dag Outs, dag Ins, string OpcodeStr,
193 string AttSrcAsm, string IntelSrcAsm,
194 dag RHS, InstrItinClass itin = NoItinerary,
195 bit IsCommutable = 0> :
196 AVX512_maskable_common<O, F, _, Outs, Ins,
197 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
198 !con((ins _.KRCWM:$mask), Ins),
199 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
200 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
201 "$src0 = $dst", itin, IsCommutable>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]202
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]203// Similar to AVX512_maskable but in this case one of the source operands
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]204// ($src1) is already tied to $dst so we just use that for the preserved
205// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
206// $src1.
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]207multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
208 dag Outs, dag NonTiedIns, string OpcodeStr,
209 string AttSrcAsm, string IntelSrcAsm,
210 dag RHS> :
211 AVX512_maskable_common<O, F, _, Outs,
212 !con((ins _.RC:$src1), NonTiedIns),
213 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
214 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
215 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
216 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]217
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000[diff] [blame]218
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]219multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
220 dag Outs, dag Ins,
221 string OpcodeStr,
222 string AttSrcAsm, string IntelSrcAsm,
223 list<dag> Pattern> :
224 AVX512_maskable_custom<O, F, Outs, Ins,
225 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
226 !con((ins _.KRCWM:$mask), Ins),
227 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
228 "$src0 = $dst">;
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000[diff] [blame]229
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]230// Bitcasts between 512-bit vector types. Return the original type since
231// no instruction is needed for the conversion
232let Predicates = [HasAVX512] in {
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]233 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]234 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]235 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
236 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
237 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]238 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]239 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
240 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
241 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]242 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]243 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]244 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
245 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]246 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]247 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
248 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovsky40a77142014-08-11 09:59:08 +0000[diff] [blame]249 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]250 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
251 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]252 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]253 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
254 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
255 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
256 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
257 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
258 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
259 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
260 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
261 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
262 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
263 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]264
265 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
266 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
267 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
268 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
269 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
270 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
271 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
272 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
273 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
274 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
275 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
276 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
277 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
278 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
279 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
280 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
281 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
282 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
283 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
284 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
285 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
286 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
287 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
288 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
289 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
290 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
291 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
292 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
293 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
294 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
295
296// Bitcasts between 256-bit vector types. Return the original type since
297// no instruction is needed for the conversion
298 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
299 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
300 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
301 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
302 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
303 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
304 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
305 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
306 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
307 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
308 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
309 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
310 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
311 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
312 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
313 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
314 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
315 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
316 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
317 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
318 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
319 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
320 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
321 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
322 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
323 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
324 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
325 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
326 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
327 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
328}
329
330//
331// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
332//
333
334let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
335 isPseudo = 1, Predicates = [HasAVX512] in {
336def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
337 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
338}
339
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]340let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]341def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
342def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
343def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]344}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]345
346//===----------------------------------------------------------------------===//
347// AVX-512 - VECTOR INSERT
348//
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]349
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]350multiclass vinsert_for_size_no_alt<int Opcode,
351 X86VectorVTInfo From, X86VectorVTInfo To,
352 PatFrag vinsert_insert,
353 SDNodeXForm INSERT_get_vinsert_imm> {
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]354 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
355 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
356 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]357 "vinsert" # From.EltTypeName # "x" # From.NumElts #
358 "\t{$src3, $src2, $src1, $dst|"
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]359 "$dst, $src1, $src2, $src3}",
Adam Nemet4dca3ce2014-10-02 23:18:30 +0000[diff] [blame]360 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
361 (From.VT From.RC:$src2),
362 (iPTR imm)))]>,
363 EVEX_4V, EVEX_V512;
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]364
365 let mayLoad = 1 in
366 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
367 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]368 "vinsert" # From.EltTypeName # "x" # From.NumElts #
369 "\t{$src3, $src2, $src1, $dst|"
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]370 "$dst, $src1, $src2, $src3}",
Adam Nemet449b3f02014-10-15 23:42:09 +0000[diff] [blame]371 []>,
372 EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, From.CD8TupleForm>;
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]373 }
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]374}
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]375
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]376multiclass vinsert_for_size<int Opcode,
377 X86VectorVTInfo From, X86VectorVTInfo To,
378 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
379 PatFrag vinsert_insert,
380 SDNodeXForm INSERT_get_vinsert_imm> :
381 vinsert_for_size_no_alt<Opcode, From, To,
382 vinsert_insert, INSERT_get_vinsert_imm> {
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]383 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]384 // vinserti32x4. Only add this if 64x2 and friends are not supported
385 // natively via AVX512DQ.
386 let Predicates = [NoDQI] in
387 def : Pat<(vinsert_insert:$ins
388 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
389 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
390 VR512:$src1, From.RC:$src2,
391 (INSERT_get_vinsert_imm VR512:$ins)))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]392}
393
Adam Nemetb1c3ef42014-10-15 23:42:04 +0000[diff] [blame]394multiclass vinsert_for_type<ValueType EltVT32, int Opcode128,
395 ValueType EltVT64, int Opcode256> {
396 defm NAME # "32x4" : vinsert_for_size<Opcode128,
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]397 X86VectorVTInfo< 4, EltVT32, VR128X>,
398 X86VectorVTInfo<16, EltVT32, VR512>,
399 X86VectorVTInfo< 2, EltVT64, VR128X>,
400 X86VectorVTInfo< 8, EltVT64, VR512>,
401 vinsert128_insert,
402 INSERT_get_vinsert128_imm>;
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]403 let Predicates = [HasDQI] in
404 defm NAME # "64x2" : vinsert_for_size_no_alt<Opcode128,
405 X86VectorVTInfo< 2, EltVT64, VR128X>,
406 X86VectorVTInfo< 8, EltVT64, VR512>,
407 vinsert128_insert,
408 INSERT_get_vinsert128_imm>, VEX_W;
Adam Nemetb1c3ef42014-10-15 23:42:04 +0000[diff] [blame]409 defm NAME # "64x4" : vinsert_for_size<Opcode256,
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]410 X86VectorVTInfo< 4, EltVT64, VR256X>,
411 X86VectorVTInfo< 8, EltVT64, VR512>,
412 X86VectorVTInfo< 8, EltVT32, VR256>,
413 X86VectorVTInfo<16, EltVT32, VR512>,
414 vinsert256_insert,
415 INSERT_get_vinsert256_imm>, VEX_W;
Adam Nemet4285c1f2014-10-15 23:42:17 +0000[diff] [blame]416 let Predicates = [HasDQI] in
417 defm NAME # "32x8" : vinsert_for_size_no_alt<Opcode256,
418 X86VectorVTInfo< 8, EltVT32, VR256X>,
419 X86VectorVTInfo<16, EltVT32, VR512>,
420 vinsert256_insert,
421 INSERT_get_vinsert256_imm>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]422}
423
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]424defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
425defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]426
427// vinsertps - insert f32 to XMM
428def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]429 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]430 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]431 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]432 EVEX_4V;
433def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]434 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]435 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]436 [(set VR128X:$dst, (X86insertps VR128X:$src1,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]437 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
438 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
439
440//===----------------------------------------------------------------------===//
441// AVX-512 VECTOR EXTRACT
442//---
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]443
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]444multiclass vextract_for_size<int Opcode,
445 X86VectorVTInfo From, X86VectorVTInfo To,
446 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
447 PatFrag vextract_extract,
448 SDNodeXForm EXTRACT_get_vextract_imm> {
449 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]450 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000[diff] [blame]451 (ins VR512:$src1, i8imm:$idx),
452 "vextract" # To.EltTypeName # "x4",
453 "$idx, $src1", "$src1, $idx",
454 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
455 (iPTR imm)))]>,
456 AVX512AIi8Base, EVEX, EVEX_V512;
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]457 let mayStore = 1 in
458 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
459 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
460 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
461 "$dst, $src1, $src2}",
462 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
463 }
464
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]465 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
466 // vextracti32x4
467 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
468 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
469 VR512:$src1,
470 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
471
472 // A 128/256-bit subvector extract from the first 512-bit vector position is
473 // a subregister copy that needs no instruction.
474 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
475 (To.VT
476 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
477
478 // And for the alternative types.
479 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
480 (AltTo.VT
481 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
Adam Nemet47b2d5f2014-10-08 23:25:37 +0000[diff] [blame]482
483 // Intrinsic call with masking.
484 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
485 "x4_512")
486 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
487 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
488 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
489 VR512:$src1, imm:$idx)>;
490
491 // Intrinsic call with zero-masking.
492 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
493 "x4_512")
494 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
495 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
496 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
497 VR512:$src1, imm:$idx)>;
498
499 // Intrinsic call without masking.
500 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
501 "x4_512")
502 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
503 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
504 VR512:$src1, imm:$idx)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]505}
506
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]507multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
508 ValueType EltVT64, int Opcode64> {
509 defm NAME # "32x4" : vextract_for_size<Opcode32,
510 X86VectorVTInfo<16, EltVT32, VR512>,
511 X86VectorVTInfo< 4, EltVT32, VR128X>,
512 X86VectorVTInfo< 8, EltVT64, VR512>,
513 X86VectorVTInfo< 2, EltVT64, VR128X>,
514 vextract128_extract,
515 EXTRACT_get_vextract128_imm>;
516 defm NAME # "64x4" : vextract_for_size<Opcode64,
517 X86VectorVTInfo< 8, EltVT64, VR512>,
518 X86VectorVTInfo< 4, EltVT64, VR256X>,
519 X86VectorVTInfo<16, EltVT32, VR512>,
520 X86VectorVTInfo< 8, EltVT32, VR256>,
521 vextract256_extract,
522 EXTRACT_get_vextract256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]523}
524
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]525defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
526defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]527
528// A 128-bit subvector insert to the first 512-bit vector position
529// is a subregister copy that needs no instruction.
530def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
531 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
532 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
533 sub_ymm)>;
534def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
535 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
536 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
537 sub_ymm)>;
538def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
539 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
540 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
541 sub_ymm)>;
542def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
543 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
544 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
545 sub_ymm)>;
546
547def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
548 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
549def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
550 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
551def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
552 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
553def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
554 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
555
556// vextractps - extract 32 bits from XMM
557def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]558 (ins VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]559 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]560 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
561 EVEX;
562
563def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]564 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]565 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]566 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
Elena Demikhovsky2aafc222014-02-11 07:25:59 +0000[diff] [blame]567 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]568
569//===---------------------------------------------------------------------===//
570// AVX-512 BROADCAST
571//---
572multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
573 RegisterClass DestRC,
574 RegisterClass SrcRC, X86MemOperand x86memop> {
575 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]576 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]577 []>, EVEX;
578 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]579 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]580}
581let ExeDomain = SSEPackedSingle in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]582 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]583 VR128X, f32mem>,
584 EVEX_V512, EVEX_CD8<32, CD8VT1>;
585}
586
587let ExeDomain = SSEPackedDouble in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]588 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]589 VR128X, f64mem>,
590 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
591}
592
593def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
594 (VBROADCASTSSZrm addr:$src)>;
595def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
596 (VBROADCASTSDZrm addr:$src)>;
597
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]598def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
599 (VBROADCASTSSZrm addr:$src)>;
600def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
601 (VBROADCASTSDZrm addr:$src)>;
602
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]603multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
604 RegisterClass SrcRC, RegisterClass KRC> {
605 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]606 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]607 []>, EVEX, EVEX_V512;
608 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
609 (ins KRC:$mask, SrcRC:$src),
610 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]611 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]612 []>, EVEX, EVEX_V512, EVEX_KZ;
613}
614
615defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
616defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
617 VEX_W;
618
619def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
620 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
621
622def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
623 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
624
625def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
626 (VPBROADCASTDrZrr GR32:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]627def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
628 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]629def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
630 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]631def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
632 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]633
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]634def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
635 (VPBROADCASTDrZrr GR32:$src)>;
636def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
637 (VPBROADCASTQrZrr GR64:$src)>;
638
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]639def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
640 (v16i32 immAllZerosV), (i16 GR16:$mask))),
641 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
642def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
643 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
644 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
645
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]646multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
647 X86MemOperand x86memop, PatFrag ld_frag,
648 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
649 RegisterClass KRC> {
650 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]651 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]652 [(set DstRC:$dst,
653 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
654 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
655 VR128X:$src),
656 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]657 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]658 [(set DstRC:$dst,
659 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
660 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]661 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]662 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]663 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]664 [(set DstRC:$dst,
665 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
666 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
667 x86memop:$src),
668 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]669 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]670 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
671 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]672 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]673}
674
675defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
676 loadi32, VR512, v16i32, v4i32, VK16WM>,
677 EVEX_V512, EVEX_CD8<32, CD8VT1>;
678defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
679 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
680 EVEX_CD8<64, CD8VT1>;
681
Adam Nemet73f72e12014-06-27 00:43:38 +0000[diff] [blame]682multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
683 X86MemOperand x86memop, PatFrag ld_frag,
684 RegisterClass KRC> {
685 let mayLoad = 1 in {
686 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
687 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
688 []>, EVEX;
689 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
690 x86memop:$src),
691 !strconcat(OpcodeStr,
692 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
693 []>, EVEX, EVEX_KZ;
694 }
695}
696
697defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
698 i128mem, loadv2i64, VK16WM>,
699 EVEX_V512, EVEX_CD8<32, CD8VT4>;
700defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
701 i256mem, loadv4i64, VK16WM>, VEX_W,
702 EVEX_V512, EVEX_CD8<64, CD8VT4>;
703
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]704def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
705 (VPBROADCASTDZrr VR128X:$src)>;
706def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
707 (VPBROADCASTQZrr VR128X:$src)>;
708
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]709def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
710 (VBROADCASTSSZrr VR128X:$src)>;
711def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
712 (VBROADCASTSDZrr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]713
Robert Khasanovdd09a8f2014-10-28 12:28:51 +0000[diff] [blame^]714def : Pat<(v16f32 (X86VBroadcast (v16f32 VR512:$src))),
715 (VBROADCASTSSZrr (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
716def : Pat<(v8f64 (X86VBroadcast (v8f64 VR512:$src))),
717 (VBROADCASTSDZrr (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
718
719def : Pat<(v16i32 (X86VBroadcast (v16i32 VR512:$src))),
720 (VPBROADCASTDZrr (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
721def : Pat<(v8i64 (X86VBroadcast (v8i64 VR512:$src))),
722 (VPBROADCASTQZrr (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
723
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]724def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
725 (VBROADCASTSSZrr VR128X:$src)>;
726def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
727 (VBROADCASTSDZrr VR128X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]728
729// Provide fallback in case the load node that is used in the patterns above
730// is used by additional users, which prevents the pattern selection.
731def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
732 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
733def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
734 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
735
736
737let Predicates = [HasAVX512] in {
738def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
739 (EXTRACT_SUBREG
740 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
741 addr:$src)), sub_ymm)>;
742}
743//===----------------------------------------------------------------------===//
744// AVX-512 BROADCAST MASK TO VECTOR REGISTER
745//---
746
747multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000[diff] [blame]748 RegisterClass KRC> {
749let Predicates = [HasCDI] in
750def Zrr : AVX512XS8I<opc, MRMSrcReg, (outs VR512:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]751 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000[diff] [blame]752 []>, EVEX, EVEX_V512;
753
754let Predicates = [HasCDI, HasVLX] in {
755def Z128rr : AVX512XS8I<opc, MRMSrcReg, (outs VR128:$dst), (ins KRC:$src),
756 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
757 []>, EVEX, EVEX_V128;
758def Z256rr : AVX512XS8I<opc, MRMSrcReg, (outs VR256:$dst), (ins KRC:$src),
759 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
760 []>, EVEX, EVEX_V256;
761}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]762}
763
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]764let Predicates = [HasCDI] in {
Elena Demikhovsky4b01b732014-10-26 09:52:24 +0000[diff] [blame]765defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d",
766 VK16>;
767defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q",
768 VK8>, VEX_W;
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]769}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]770
771//===----------------------------------------------------------------------===//
772// AVX-512 - VPERM
773//
774// -- immediate form --
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]775multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, SDNode OpNode,
776 X86VectorVTInfo _> {
777 let ExeDomain = _.ExeDomain in {
778 def ri : AVX512AIi8<opc, MRMSrcReg, (outs _.RC:$dst),
779 (ins _.RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]780 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]781 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]782 [(set _.RC:$dst,
783 (_.VT (OpNode _.RC:$src1, (i8 imm:$src2))))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]784 EVEX;
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]785 def mi : AVX512AIi8<opc, MRMSrcMem, (outs _.RC:$dst),
786 (ins _.MemOp:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]787 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]788 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]789 [(set _.RC:$dst,
790 (_.VT (OpNode (_.MemOpFrag addr:$src1),
791 (i8 imm:$src2))))]>,
792 EVEX, EVEX_CD8<_.EltSize, CD8VF>;
793}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]794}
795
Adam Nemetcf7a4a22014-10-27 23:08:40 +0000[diff] [blame]796multiclass avx512_permil<bits<8> OpcImm, bits<8> OpcVar, X86VectorVTInfo _,
797 X86VectorVTInfo Ctrl> :
798 avx512_perm_imm<OpcImm, "vpermil" # _.Suffix, X86VPermilpi, _> {
799 let ExeDomain = _.ExeDomain in {
800 def rr : AVX5128I<OpcVar, MRMSrcReg, (outs _.RC:$dst),
801 (ins _.RC:$src1, _.RC:$src2),
802 !strconcat("vpermil" # _.Suffix,
803 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
804 [(set _.RC:$dst,
805 (_.VT (X86VPermilpv _.RC:$src1,
806 (Ctrl.VT Ctrl.RC:$src2))))]>,
807 EVEX_4V;
808 def rm : AVX5128I<OpcVar, MRMSrcMem, (outs _.RC:$dst),
809 (ins _.RC:$src1, Ctrl.MemOp:$src2),
810 !strconcat("vpermil" # _.Suffix,
811 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
812 [(set _.RC:$dst,
813 (_.VT (X86VPermilpv _.RC:$src1,
814 (Ctrl.VT (Ctrl.MemOpFrag addr:$src2)))))]>,
815 EVEX_4V;
816 }
817}
818
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]819defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", X86VPermi, v8i64_info>,
820 EVEX_V512, VEX_W;
821defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", X86VPermi, v8f64_info>,
822 EVEX_V512, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]823
Adam Nemetcf7a4a22014-10-27 23:08:40 +0000[diff] [blame]824defm VPERMILPSZ : avx512_permil<0x04, 0x0C, v16f32_info, v16i32_info>,
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]825 EVEX_V512;
Adam Nemetcf7a4a22014-10-27 23:08:40 +0000[diff] [blame]826defm VPERMILPDZ : avx512_permil<0x05, 0x0D, v8f64_info, v8i64_info>,
Adam Nemet8d85b0c2014-10-27 23:08:37 +0000[diff] [blame]827 EVEX_V512, VEX_W;
Adam Nemet9aad1312014-10-27 23:08:34 +0000[diff] [blame]828
829def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
830 (VPERMILPSZri VR512:$src1, imm:$imm)>;
831def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
832 (VPERMILPDZri VR512:$src1, imm:$imm)>;
833
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]834// -- VPERM - register form --
835multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
836 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
837
838 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
839 (ins RC:$src1, RC:$src2),
840 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]841 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]842 [(set RC:$dst,
843 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
844
845 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
846 (ins RC:$src1, x86memop:$src2),
847 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]848 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]849 [(set RC:$dst,
850 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
851 EVEX_4V;
852}
853
854defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
855 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
856defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
857 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
858let ExeDomain = SSEPackedSingle in
859defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
860 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
861let ExeDomain = SSEPackedDouble in
862defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
863 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
864
865// -- VPERM2I - 3 source operands form --
866multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
867 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]868 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]869let Constraints = "$src1 = $dst" in {
870 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
871 (ins RC:$src1, RC:$src2, RC:$src3),
872 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]873 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]874 [(set RC:$dst,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]875 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]876 EVEX_4V;
877
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]878 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
879 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
880 !strconcat(OpcodeStr,
881 " \t{$src3, $src2, $dst {${mask}}|"
882 "$dst {${mask}}, $src2, $src3}"),
883 [(set RC:$dst, (OpVT (vselect KRC:$mask,
884 (OpNode RC:$src1, RC:$src2,
885 RC:$src3),
886 RC:$src1)))]>,
887 EVEX_4V, EVEX_K;
888
889 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
890 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
891 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
892 !strconcat(OpcodeStr,
893 " \t{$src3, $src2, $dst {${mask}} {z} |",
894 "$dst {${mask}} {z}, $src2, $src3}"),
895 [(set RC:$dst, (OpVT (vselect KRC:$mask,
896 (OpNode RC:$src1, RC:$src2,
897 RC:$src3),
898 (OpVT (bitconvert
899 (v16i32 immAllZerosV))))))]>,
900 EVEX_4V, EVEX_KZ;
901
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]902 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
903 (ins RC:$src1, RC:$src2, x86memop:$src3),
904 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]905 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]906 [(set RC:$dst,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]907 (OpVT (OpNode RC:$src1, RC:$src2,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]908 (mem_frag addr:$src3))))]>, EVEX_4V;
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]909
910 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
911 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
912 !strconcat(OpcodeStr,
913 " \t{$src3, $src2, $dst {${mask}}|"
914 "$dst {${mask}}, $src2, $src3}"),
915 [(set RC:$dst,
916 (OpVT (vselect KRC:$mask,
917 (OpNode RC:$src1, RC:$src2,
918 (mem_frag addr:$src3)),
919 RC:$src1)))]>,
920 EVEX_4V, EVEX_K;
921
922 let AddedComplexity = 10 in // Prefer over the rrkz variant
923 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
924 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
925 !strconcat(OpcodeStr,
926 " \t{$src3, $src2, $dst {${mask}} {z}|"
927 "$dst {${mask}} {z}, $src2, $src3}"),
928 [(set RC:$dst,
929 (OpVT (vselect KRC:$mask,
930 (OpNode RC:$src1, RC:$src2,
931 (mem_frag addr:$src3)),
932 (OpVT (bitconvert
933 (v16i32 immAllZerosV))))))]>,
934 EVEX_4V, EVEX_KZ;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]935 }
936}
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]937defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
938 i512mem, X86VPermiv3, v16i32, VK16WM>,
939 EVEX_V512, EVEX_CD8<32, CD8VF>;
940defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
941 i512mem, X86VPermiv3, v8i64, VK8WM>,
942 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
943defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
944 i512mem, X86VPermiv3, v16f32, VK16WM>,
945 EVEX_V512, EVEX_CD8<32, CD8VF>;
946defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
947 i512mem, X86VPermiv3, v8f64, VK8WM>,
948 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]949
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]950multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
951 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]952 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
953 ValueType MaskVT, RegisterClass MRC> :
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]954 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
955 OpVT, KRC> {
956 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
957 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
958 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]959
960 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
961 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
962 (!cast<Instruction>(NAME#rrk) VR512:$src1,
963 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]964}
965
966defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]967 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
968 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]969defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]970 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
971 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]972defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]973 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
974 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]975defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]976 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
977 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky299cf5112014-04-29 09:09:15 +0000[diff] [blame]978
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]979//===----------------------------------------------------------------------===//
980// AVX-512 - BLEND using mask
981//
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]982multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]983 RegisterClass KRC, RegisterClass RC,
984 X86MemOperand x86memop, PatFrag mem_frag,
985 SDNode OpNode, ValueType vt> {
986 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]987 (ins KRC:$mask, RC:$src1, RC:$src2),
988 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]989 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]990 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]991 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]992 let mayLoad = 1 in
993 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
994 (ins KRC:$mask, RC:$src1, x86memop:$src2),
995 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]996 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]997 []>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]998}
999
1000let ExeDomain = SSEPackedSingle in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1001defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1002 VK16WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1003 memopv16f32, vselect, v16f32>,
1004 EVEX_CD8<32, CD8VF>, EVEX_V512;
1005let ExeDomain = SSEPackedDouble in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1006defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1007 VK8WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1008 memopv8f64, vselect, v8f64>,
1009 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
1010
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1011def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
1012 (v16f32 VR512:$src2), (i16 GR16:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1013 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1014 VR512:$src1, VR512:$src2)>;
1015
1016def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
1017 (v8f64 VR512:$src2), (i8 GR8:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1018 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1019 VR512:$src1, VR512:$src2)>;
1020
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1021defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1022 VK16WM, VR512, f512mem,
1023 memopv16i32, vselect, v16i32>,
1024 EVEX_CD8<32, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1025
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1026defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]1027 VK8WM, VR512, f512mem,
1028 memopv8i64, vselect, v8i64>,
1029 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1030
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1031def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
1032 (v16i32 VR512:$src2), (i16 GR16:$mask))),
1033 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
1034 VR512:$src1, VR512:$src2)>;
1035
1036def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
1037 (v8i64 VR512:$src2), (i8 GR8:$mask))),
1038 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
1039 VR512:$src1, VR512:$src2)>;
1040
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1041let Predicates = [HasAVX512] in {
1042def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
1043 (v8f32 VR256X:$src2))),
1044 (EXTRACT_SUBREG
1045 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1046 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1047 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1048
1049def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
1050 (v8i32 VR256X:$src2))),
1051 (EXTRACT_SUBREG
1052 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
1053 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1054 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
1055}
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1056//===----------------------------------------------------------------------===//
1057// Compare Instructions
1058//===----------------------------------------------------------------------===//
1059
1060// avx512_cmp_scalar - AVX512 CMPSS and CMPSD
1061multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1062 Operand CC, SDNode OpNode, ValueType VT,
1063 PatFrag ld_frag, string asm, string asm_alt> {
1064 def rr : AVX512Ii8<0xC2, MRMSrcReg,
1065 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
1066 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
1067 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1068 def rm : AVX512Ii8<0xC2, MRMSrcMem,
1069 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
1070 [(set VK1:$dst, (OpNode (VT RC:$src1),
1071 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1072 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1073 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
1074 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
1075 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
1076 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
1077 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
1078 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1079 }
1080}
1081
1082let Predicates = [HasAVX512] in {
1083defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1084 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1085 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1086 XS;
1087defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1088 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1089 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1090 XD, VEX_W;
1091}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1092
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1093multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1094 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1095 def rr : AVX512BI<opc, MRMSrcReg,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1096 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1097 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1098 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1099 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1100 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1101 def rm : AVX512BI<opc, MRMSrcMem,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1102 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1103 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1104 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1105 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1106 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1107 def rrk : AVX512BI<opc, MRMSrcReg,
1108 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1109 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1110 "$dst {${mask}}, $src1, $src2}"),
1111 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1112 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1113 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1114 let mayLoad = 1 in
1115 def rmk : AVX512BI<opc, MRMSrcMem,
1116 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1117 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1118 "$dst {${mask}}, $src1, $src2}"),
1119 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1120 (OpNode (_.VT _.RC:$src1),
1121 (_.VT (bitconvert
1122 (_.LdFrag addr:$src2))))))],
1123 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1124}
1125
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1126multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1127 X86VectorVTInfo _> :
1128 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1129 let mayLoad = 1 in {
1130 def rmb : AVX512BI<opc, MRMSrcMem,
1131 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1132 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1133 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1134 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1135 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1136 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1137 def rmbk : AVX512BI<opc, MRMSrcMem,
1138 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1139 _.ScalarMemOp:$src2),
1140 !strconcat(OpcodeStr,
1141 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1142 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1143 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1144 (OpNode (_.VT _.RC:$src1),
1145 (X86VBroadcast
1146 (_.ScalarLdFrag addr:$src2)))))],
1147 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1148 }
1149}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1150
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1151multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1152 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1153 let Predicates = [prd] in
1154 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1155 EVEX_V512;
1156
1157 let Predicates = [prd, HasVLX] in {
1158 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1159 EVEX_V256;
1160 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1161 EVEX_V128;
1162 }
1163}
1164
1165multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1166 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1167 Predicate prd> {
1168 let Predicates = [prd] in
1169 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1170 EVEX_V512;
1171
1172 let Predicates = [prd, HasVLX] in {
1173 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1174 EVEX_V256;
1175 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1176 EVEX_V128;
1177 }
1178}
1179
1180defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1181 avx512vl_i8_info, HasBWI>,
1182 EVEX_CD8<8, CD8VF>;
1183
1184defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1185 avx512vl_i16_info, HasBWI>,
1186 EVEX_CD8<16, CD8VF>;
1187
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1188defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1189 avx512vl_i32_info, HasAVX512>,
1190 EVEX_CD8<32, CD8VF>;
1191
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1192defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1193 avx512vl_i64_info, HasAVX512>,
1194 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1195
1196defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1197 avx512vl_i8_info, HasBWI>,
1198 EVEX_CD8<8, CD8VF>;
1199
1200defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1201 avx512vl_i16_info, HasBWI>,
1202 EVEX_CD8<16, CD8VF>;
1203
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1204defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1205 avx512vl_i32_info, HasAVX512>,
1206 EVEX_CD8<32, CD8VF>;
1207
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1208defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1209 avx512vl_i64_info, HasAVX512>,
1210 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1211
1212def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1213 (COPY_TO_REGCLASS (VPCMPGTDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1214 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1215 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1216
1217def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1218 (COPY_TO_REGCLASS (VPCMPEQDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1219 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1220 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1221
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1222multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1223 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1224 def rri : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1225 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1226 !strconcat("vpcmp${cc}", Suffix,
1227 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1228 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1229 imm:$cc))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1230 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1231 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1232 def rmi : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1233 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1234 !strconcat("vpcmp${cc}", Suffix,
1235 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1236 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1237 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1238 imm:$cc))],
1239 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1240 def rrik : AVX512AIi8<opc, MRMSrcReg,
1241 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1242 AVXCC:$cc),
1243 !strconcat("vpcmp${cc}", Suffix,
1244 "\t{$src2, $src1, $dst {${mask}}|",
1245 "$dst {${mask}}, $src1, $src2}"),
1246 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1247 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1248 imm:$cc)))],
1249 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1250 let mayLoad = 1 in
1251 def rmik : AVX512AIi8<opc, MRMSrcMem,
1252 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1253 AVXCC:$cc),
1254 !strconcat("vpcmp${cc}", Suffix,
1255 "\t{$src2, $src1, $dst {${mask}}|",
1256 "$dst {${mask}}, $src1, $src2}"),
1257 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1258 (OpNode (_.VT _.RC:$src1),
1259 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1260 imm:$cc)))],
1261 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1262
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1263 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1264 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1265 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1266 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1267 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1268 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1269 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1270 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1271 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1272 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1273 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1274 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1275 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1276 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1277 i8imm:$cc),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1278 !strconcat("vpcmp", Suffix,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1279 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1280 "$dst {${mask}}, $src1, $src2, $cc}"),
1281 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1282 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1283 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1284 i8imm:$cc),
1285 !strconcat("vpcmp", Suffix,
1286 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1287 "$dst {${mask}}, $src1, $src2, $cc}"),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1288 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1289 }
1290}
1291
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1292multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1293 X86VectorVTInfo _> :
1294 avx512_icmp_cc<opc, Suffix, OpNode, _> {
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1295 let mayLoad = 1 in {
1296 def rmib : AVX512AIi8<opc, MRMSrcMem,
1297 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1298 AVXCC:$cc),
1299 !strconcat("vpcmp${cc}", Suffix,
1300 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1301 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1302 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1303 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1304 imm:$cc))],
1305 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1306 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1307 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1308 _.ScalarMemOp:$src2, AVXCC:$cc),
1309 !strconcat("vpcmp${cc}", Suffix,
1310 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1311 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1312 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1313 (OpNode (_.VT _.RC:$src1),
1314 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1315 imm:$cc)))],
1316 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1317 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1318
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1319 // Accept explicit immediate argument form instead of comparison code.
1320 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1321 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1322 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1323 i8imm:$cc),
1324 !strconcat("vpcmp", Suffix,
1325 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1326 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1327 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1328 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1329 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1330 _.ScalarMemOp:$src2, i8imm:$cc),
1331 !strconcat("vpcmp", Suffix,
1332 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1333 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1334 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1335 }
1336}
1337
1338multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1339 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1340 let Predicates = [prd] in
1341 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1342
1343 let Predicates = [prd, HasVLX] in {
1344 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1345 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1346 }
1347}
1348
1349multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1350 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1351 let Predicates = [prd] in
1352 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1353 EVEX_V512;
1354
1355 let Predicates = [prd, HasVLX] in {
1356 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1357 EVEX_V256;
1358 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1359 EVEX_V128;
1360 }
1361}
1362
1363defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1364 HasBWI>, EVEX_CD8<8, CD8VF>;
1365defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1366 HasBWI>, EVEX_CD8<8, CD8VF>;
1367
1368defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1369 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1370defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1371 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1372
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1373defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1374 HasAVX512>, EVEX_CD8<32, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1375defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1376 HasAVX512>, EVEX_CD8<32, CD8VF>;
1377
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1378defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1379 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1380defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1381 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1382
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1383// avx512_cmp_packed - compare packed instructions
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1384multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1385 X86MemOperand x86memop, ValueType vt,
1386 string suffix, Domain d> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1387 def rri : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1388 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1389 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1390 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1391 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1392 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1393 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1394 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1395 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1396 [], d>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1397 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1398 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1399 !strconcat("vcmp${cc}", suffix,
1400 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1401 [(set KRC:$dst,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1402 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1403
1404 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1405 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1406 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1407 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1408 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1409 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1410 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1411 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1412 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1413 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1414 }
1415}
1416
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1417defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1418 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]1419 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1420defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1421 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1422 EVEX_CD8<64, CD8VF>;
1423
1424def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1425 (COPY_TO_REGCLASS (VCMPPSZrri
1426 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1427 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1428 imm:$cc), VK8)>;
1429def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1430 (COPY_TO_REGCLASS (VPCMPDZrri
1431 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1432 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1433 imm:$cc), VK8)>;
1434def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1435 (COPY_TO_REGCLASS (VPCMPUDZrri
1436 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1437 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1438 imm:$cc), VK8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1439
1440def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1441 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1442 FROUND_NO_EXC)),
1443 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1444 (I8Imm imm:$cc)), GR16)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1445
1446def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1447 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1448 FROUND_NO_EXC)),
1449 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1450 (I8Imm imm:$cc)), GR8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1451
1452def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1453 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1454 FROUND_CURRENT)),
1455 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1456 (I8Imm imm:$cc)), GR16)>;
1457
1458def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1459 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1460 FROUND_CURRENT)),
1461 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1462 (I8Imm imm:$cc)), GR8)>;
1463
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1464// Mask register copy, including
1465// - copy between mask registers
1466// - load/store mask registers
1467// - copy from GPR to mask register and vice versa
1468//
1469multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1470 string OpcodeStr, RegisterClass KRC,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1471 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1472 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1473 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1474 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1475 let mayLoad = 1 in
1476 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1477 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1478 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1479 let mayStore = 1 in
1480 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1481 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1482 }
1483}
1484
1485multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1486 string OpcodeStr,
1487 RegisterClass KRC, RegisterClass GRC> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1488 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1489 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1490 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1491 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1492 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1493 }
1494}
1495
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1496let Predicates = [HasDQI] in
1497 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1498 i8mem>,
1499 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1500 VEX, PD;
1501
1502let Predicates = [HasAVX512] in
1503 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1504 i16mem>,
1505 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1506 VEX, PS;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1507
1508let Predicates = [HasBWI] in {
1509 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1510 i32mem>, VEX, PD, VEX_W;
1511 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1512 VEX, XD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1513}
1514
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1515let Predicates = [HasBWI] in {
1516 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1517 i64mem>, VEX, PS, VEX_W;
1518 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1519 VEX, XD, VEX_W;
1520}
1521
1522// GR from/to mask register
1523let Predicates = [HasDQI] in {
1524 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1525 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1526 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1527 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1528}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1529let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1530 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1531 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1532 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1533 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1534}
1535let Predicates = [HasBWI] in {
1536 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1537 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1538}
1539let Predicates = [HasBWI] in {
1540 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1541 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1542}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1543
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1544// Load/store kreg
1545let Predicates = [HasDQI] in {
1546 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1547 (KMOVBmk addr:$dst, VK8:$src)>;
1548}
1549let Predicates = [HasAVX512] in {
1550 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1551 (KMOVWmk addr:$dst, VK16:$src)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1552 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1553 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1554 def : Pat<(i1 (load addr:$src)),
1555 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1556 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1557 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1558}
1559let Predicates = [HasBWI] in {
1560 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1561 (KMOVDmk addr:$dst, VK32:$src)>;
1562}
1563let Predicates = [HasBWI] in {
1564 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1565 (KMOVQmk addr:$dst, VK64:$src)>;
1566}
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1567
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1568let Predicates = [HasAVX512] in {
Elena Demikhovsky34d2d762014-08-18 11:59:06 +0000[diff] [blame]1569 def : Pat<(i1 (trunc (i64 GR64:$src))),
1570 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1571 (i32 1))), VK1)>;
1572
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1573 def : Pat<(i1 (trunc (i32 GR32:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1574 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1575
1576 def : Pat<(i1 (trunc (i8 GR8:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1577 (COPY_TO_REGCLASS
1578 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1579 VK1)>;
1580 def : Pat<(i1 (trunc (i16 GR16:$src))),
1581 (COPY_TO_REGCLASS
1582 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1583 VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1584
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1585 def : Pat<(i32 (zext VK1:$src)),
1586 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1587 def : Pat<(i8 (zext VK1:$src)),
1588 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1589 (AND32ri (KMOVWrk
1590 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1591 def : Pat<(i64 (zext VK1:$src)),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1592 (AND64ri8 (SUBREG_TO_REG (i64 0),
1593 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
Elena Demikhovsky750498c2014-02-17 07:29:33 +0000[diff] [blame]1594 def : Pat<(i16 (zext VK1:$src)),
1595 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1596 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1597 sub_16bit)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1598 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1599 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1600 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1601 (COPY_TO_REGCLASS VK1:$src, VK8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1602}
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1603let Predicates = [HasBWI] in {
1604 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1605 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1606 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1607 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1608}
1609
1610
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1611// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1612let Predicates = [HasAVX512] in {
1613 // GR from/to 8-bit mask without native support
1614 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1615 (COPY_TO_REGCLASS
1616 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1617 VK8)>;
1618 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1619 (EXTRACT_SUBREG
1620 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1621 sub_8bit)>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1622
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1623 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1624 (COPY_TO_REGCLASS VK16:$src, VK1)>;
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1625 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1626 (COPY_TO_REGCLASS VK8:$src, VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1627}
1628let Predicates = [HasBWI] in {
1629 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1630 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1631 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1632 (COPY_TO_REGCLASS VK64:$src, VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1633}
1634
1635// Mask unary operation
1636// - KNOT
1637multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1638 RegisterClass KRC, SDPatternOperator OpNode,
1639 Predicate prd> {
1640 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1641 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1642 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1643 [(set KRC:$dst, (OpNode KRC:$src))]>;
1644}
1645
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1646multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1647 SDPatternOperator OpNode> {
1648 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1649 HasDQI>, VEX, PD;
1650 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1651 HasAVX512>, VEX, PS;
1652 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1653 HasBWI>, VEX, PD, VEX_W;
1654 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1655 HasBWI>, VEX, PS, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1656}
1657
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1658defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1659
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1660multiclass avx512_mask_unop_int<string IntName, string InstName> {
1661 let Predicates = [HasAVX512] in
1662 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1663 (i16 GR16:$src)),
1664 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1665 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1666}
1667defm : avx512_mask_unop_int<"knot", "KNOT">;
1668
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1669let Predicates = [HasDQI] in
1670def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1671let Predicates = [HasAVX512] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1672def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1673let Predicates = [HasBWI] in
1674def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1675let Predicates = [HasBWI] in
1676def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1677
1678// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1679let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1680def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1681 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1682
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1683def : Pat<(not VK8:$src),
1684 (COPY_TO_REGCLASS
1685 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1686}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1687
1688// Mask binary operation
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1689// - KAND, KANDN, KOR, KXNOR, KXOR
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1690multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1691 RegisterClass KRC, SDPatternOperator OpNode,
1692 Predicate prd> {
1693 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1694 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1695 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1696 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1697 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1698}
1699
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1700multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1701 SDPatternOperator OpNode> {
1702 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1703 HasDQI>, VEX_4V, VEX_L, PD;
1704 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1705 HasAVX512>, VEX_4V, VEX_L, PS;
1706 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1707 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1708 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1709 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1710}
1711
1712def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1713def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1714
1715let isCommutable = 1 in {
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1716 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1717 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1718 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1719 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1720}
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1721let isCommutable = 0 in
1722 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1723
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1724def : Pat<(xor VK1:$src1, VK1:$src2),
1725 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1726 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1727
1728def : Pat<(or VK1:$src1, VK1:$src2),
1729 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1730 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1731
Elena Demikhovskyb64d7e82013-12-25 10:06:40 +0000[diff] [blame]1732def : Pat<(and VK1:$src1, VK1:$src2),
1733 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1734 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1735
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1736multiclass avx512_mask_binop_int<string IntName, string InstName> {
1737 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1738 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1739 (i16 GR16:$src1), (i16 GR16:$src2)),
1740 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1741 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1742 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1743}
1744
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1745defm : avx512_mask_binop_int<"kand", "KAND">;
1746defm : avx512_mask_binop_int<"kandn", "KANDN">;
1747defm : avx512_mask_binop_int<"kor", "KOR">;
1748defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1749defm : avx512_mask_binop_int<"kxor", "KXOR">;
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1750
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1751// With AVX-512, 8-bit mask is promoted to 16-bit mask.
1752multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1753 let Predicates = [HasAVX512] in
1754 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1755 (COPY_TO_REGCLASS
1756 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1757 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1758}
1759
1760defm : avx512_binop_pat<and, KANDWrr>;
1761defm : avx512_binop_pat<andn, KANDNWrr>;
1762defm : avx512_binop_pat<or, KORWrr>;
1763defm : avx512_binop_pat<xnor, KXNORWrr>;
1764defm : avx512_binop_pat<xor, KXORWrr>;
1765
1766// Mask unpacking
1767multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1768 RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1769 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1770 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1771 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1772 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1773}
1774
1775multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1776 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1777 VEX_4V, VEX_L, PD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1778}
1779
1780defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1781def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1782 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1783 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1784
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1785
1786multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1787 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1788 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1789 (i16 GR16:$src1), (i16 GR16:$src2)),
1790 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1791 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1792 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1793}
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1794defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1795
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1796// Mask bit testing
1797multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1798 SDNode OpNode> {
1799 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1800 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1801 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1802 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1803}
1804
1805multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1806 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1807 VEX, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1808}
1809
1810defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1811
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1812def : Pat<(X86cmp VK1:$src1, (i1 0)),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1813 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1814 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1815
1816// Mask shift
1817multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1818 SDNode OpNode> {
1819 let Predicates = [HasAVX512] in
1820 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1821 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1822 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1823 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1824}
1825
1826multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1827 SDNode OpNode> {
1828 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1829 VEX, TAPD, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1830}
1831
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1832defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1833defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1834
1835// Mask setting all 0s or 1s
1836multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1837 let Predicates = [HasAVX512] in
1838 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1839 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1840 [(set KRC:$dst, (VT Val))]>;
1841}
1842
1843multiclass avx512_mask_setop_w<PatFrag Val> {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1844 defm B : avx512_mask_setop<VK8, v8i1, Val>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1845 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1846}
1847
1848defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1849defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1850
1851// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1852let Predicates = [HasAVX512] in {
1853 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1854 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1855 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1856 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1857 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1858}
1859def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1860 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1861
1862def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1863 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1864
1865def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1866 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1867
Robert Khasanov5aa44452014-09-30 11:41:54 +0000[diff] [blame]1868let Predicates = [HasVLX] in {
1869 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1870 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1871 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1872 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1873 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1874 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1875 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1876 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1877}
1878
Elena Demikhovsky9737e382014-03-02 09:19:44 +0000[diff] [blame]1879def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1880 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1881
1882def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1883 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1884//===----------------------------------------------------------------------===//
1885// AVX-512 - Aligned and unaligned load and store
1886//
1887
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1888multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1889 RegisterClass KRC, RegisterClass RC,
1890 ValueType vt, ValueType zvt, X86MemOperand memop,
1891 Domain d, bit IsReMaterializable = 1> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1892let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1893 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1894 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1895 d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1896 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1897 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1898 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1899 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1900 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1901 SchedRW = [WriteLoad] in
1902 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1903 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1904 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1905 d>, EVEX;
1906
1907 let AddedComplexity = 20 in {
1908 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1909 let hasSideEffects = 0 in
1910 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1911 (ins RC:$src0, KRC:$mask, RC:$src1),
1912 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1913 "${dst} {${mask}}, $src1}"),
1914 [(set RC:$dst, (vt (vselect KRC:$mask,
1915 (vt RC:$src1),
1916 (vt RC:$src0))))],
1917 d>, EVEX, EVEX_K;
1918 let mayLoad = 1, SchedRW = [WriteLoad] in
1919 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1920 (ins RC:$src0, KRC:$mask, memop:$src1),
1921 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1922 "${dst} {${mask}}, $src1}"),
1923 [(set RC:$dst, (vt
1924 (vselect KRC:$mask,
1925 (vt (bitconvert (ld_frag addr:$src1))),
1926 (vt RC:$src0))))],
1927 d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1928 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1929 let mayLoad = 1, SchedRW = [WriteLoad] in
1930 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1931 (ins KRC:$mask, memop:$src),
1932 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1933 "${dst} {${mask}} {z}, $src}"),
1934 [(set RC:$dst, (vt
1935 (vselect KRC:$mask,
1936 (vt (bitconvert (ld_frag addr:$src))),
1937 (vt (bitconvert (zvt immAllZerosV))))))],
1938 d>, EVEX, EVEX_KZ;
1939 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1940}
1941
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1942multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1943 string elty, string elsz, string vsz512,
1944 string vsz256, string vsz128, Domain d,
1945 Predicate prd, bit IsReMaterializable = 1> {
1946 let Predicates = [prd] in
1947 defm Z : avx512_load<opc, OpcodeStr,
1948 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1949 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1950 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1951 !cast<X86MemOperand>(elty##"512mem"), d,
1952 IsReMaterializable>, EVEX_V512;
1953
1954 let Predicates = [prd, HasVLX] in {
1955 defm Z256 : avx512_load<opc, OpcodeStr,
1956 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1957 "v"##vsz256##elty##elsz, "v4i64")),
1958 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1959 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1960 !cast<X86MemOperand>(elty##"256mem"), d,
1961 IsReMaterializable>, EVEX_V256;
1962
1963 defm Z128 : avx512_load<opc, OpcodeStr,
1964 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1965 "v"##vsz128##elty##elsz, "v2i64")),
1966 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1967 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1968 !cast<X86MemOperand>(elty##"128mem"), d,
1969 IsReMaterializable>, EVEX_V128;
1970 }
1971}
1972
1973
1974multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1975 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1976 X86MemOperand memop, Domain d> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1977 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1978 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1979 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1980 EVEX;
1981 let Constraints = "$src1 = $dst" in
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1982 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1983 (ins RC:$src1, KRC:$mask, RC:$src2),
1984 !strconcat(OpcodeStr,
1985 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1986 EVEX, EVEX_K;
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1987 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1988 (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1989 !strconcat(OpcodeStr,
1990 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1991 [], d>, EVEX, EVEX_KZ;
1992 }
1993 let mayStore = 1 in {
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1994 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1995 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1996 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1997 def mrk : AVX512PI<opc, MRMDestMem, (outs),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1998 (ins memop:$dst, KRC:$mask, RC:$src),
1999 !strconcat(OpcodeStr,
2000 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2001 [], d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2002 }
2003}
2004
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2005
2006multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
2007 string st_suff_512, string st_suff_256,
2008 string st_suff_128, string elty, string elsz,
2009 string vsz512, string vsz256, string vsz128,
2010 Domain d, Predicate prd> {
2011 let Predicates = [prd] in
2012 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
2013 !cast<ValueType>("v"##vsz512##elty##elsz),
2014 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
2015 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
2016
2017 let Predicates = [prd, HasVLX] in {
2018 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
2019 !cast<ValueType>("v"##vsz256##elty##elsz),
2020 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
2021 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
2022
2023 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
2024 !cast<ValueType>("v"##vsz128##elty##elsz),
2025 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
2026 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
2027 }
2028}
2029
2030defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
2031 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2032 avx512_store_vl<0x29, "vmovaps", "alignedstore",
2033 "512", "256", "", "f", "32", "16", "8", "4",
2034 SSEPackedSingle, HasAVX512>,
2035 PS, EVEX_CD8<32, CD8VF>;
2036
2037defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
2038 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2039 avx512_store_vl<0x29, "vmovapd", "alignedstore",
2040 "512", "256", "", "f", "64", "8", "4", "2",
2041 SSEPackedDouble, HasAVX512>,
2042 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2043
2044defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
2045 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2046 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
2047 "16", "8", "4", SSEPackedSingle, HasAVX512>,
2048 PS, EVEX_CD8<32, CD8VF>;
2049
2050defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
2051 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
2052 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
2053 "8", "4", "2", SSEPackedDouble, HasAVX512>,
2054 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2055
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2056def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2057 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2058 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2059
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2060def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
2061 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
2062 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2063
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]2064def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
2065 GR16:$mask),
2066 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
2067 VR512:$src)>;
2068def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
2069 GR8:$mask),
2070 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
2071 VR512:$src)>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]2072
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2073defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
2074 "16", "8", "4", SSEPackedInt, HasAVX512>,
2075 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
2076 "512", "256", "", "i", "32", "16", "8", "4",
2077 SSEPackedInt, HasAVX512>,
2078 PD, EVEX_CD8<32, CD8VF>;
2079
2080defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
2081 "8", "4", "2", SSEPackedInt, HasAVX512>,
2082 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2083 "512", "256", "", "i", "64", "8", "4", "2",
2084 SSEPackedInt, HasAVX512>,
2085 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2086
2087defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2088 "64", "32", "16", SSEPackedInt, HasBWI>,
2089 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2090 "i", "8", "64", "32", "16", SSEPackedInt,
2091 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2092
2093defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2094 "32", "16", "8", SSEPackedInt, HasBWI>,
2095 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2096 "i", "16", "32", "16", "8", SSEPackedInt,
2097 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2098
2099defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2100 "16", "8", "4", SSEPackedInt, HasAVX512>,
2101 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2102 "i", "32", "16", "8", "4", SSEPackedInt,
2103 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2104
2105defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2106 "8", "4", "2", SSEPackedInt, HasAVX512>,
2107 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2108 "i", "64", "8", "4", "2", SSEPackedInt,
2109 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]2110
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2111def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2112 (v16i32 immAllZerosV), GR16:$mask)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2113 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2114
2115def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2116 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2117 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2118
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2119def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2120 GR16:$mask),
2121 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2122 VR512:$src)>;
2123def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2124 GR8:$mask),
2125 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2126 VR512:$src)>;
2127
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2128let AddedComplexity = 20 in {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2129def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2130 (bc_v8i64 (v16i32 immAllZerosV)))),
2131 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2132
2133def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2134 (v8i64 VR512:$src))),
2135 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2136 VK8), VR512:$src)>;
2137
2138def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2139 (v16i32 immAllZerosV))),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2140 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2141
2142def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2143 (v16i32 VR512:$src))),
2144 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2145}
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2146
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2147// Move Int Doubleword to Packed Double Int
2148//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2149def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2150 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2151 [(set VR128X:$dst,
2152 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2153 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2154def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2155 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2156 [(set VR128X:$dst,
2157 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2158 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2159def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2160 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2161 [(set VR128X:$dst,
2162 (v2i64 (scalar_to_vector GR64:$src)))],
2163 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2164let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2165def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2166 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2167 [(set FR64:$dst, (bitconvert GR64:$src))],
2168 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2169def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2170 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2171 [(set GR64:$dst, (bitconvert FR64:$src))],
2172 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2173}
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2174def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2175 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2176 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2177 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2178 EVEX_CD8<64, CD8VT1>;
2179
2180// Move Int Doubleword to Single Scalar
2181//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2182let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2183def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2184 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2185 [(set FR32X:$dst, (bitconvert GR32:$src))],
2186 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2187
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2188def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2189 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2190 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2191 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2192}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2193
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2194// Move doubleword from xmm register to r/m32
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2195//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2196def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2197 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2198 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2199 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2200 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2201def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2202 (ins i32mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2203 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2204 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2205 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2206 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2207
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2208// Move quadword from xmm1 register to r/m64
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2209//
2210def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2211 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2212 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2213 (iPTR 0)))],
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2214 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2215 Requires<[HasAVX512, In64BitMode]>;
2216
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]2217def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2218 (ins i64mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2219 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2220 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2221 addr:$dst)], IIC_SSE_MOVDQ>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2222 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2223 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2224
2225// Move Scalar Single to Double Int
2226//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2227let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2228def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2229 (ins FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2230 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2231 [(set GR32:$dst, (bitconvert FR32X:$src))],
2232 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2233def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2234 (ins i32mem:$dst, FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2235 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2236 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2237 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2238}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2239
2240// Move Quadword Int to Packed Quadword Int
2241//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2242def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2243 (ins i64mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2244 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2245 [(set VR128X:$dst,
2246 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2247 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2248
2249//===----------------------------------------------------------------------===//
2250// AVX-512 MOVSS, MOVSD
2251//===----------------------------------------------------------------------===//
2252
2253multiclass avx512_move_scalar <string asm, RegisterClass RC,
2254 SDNode OpNode, ValueType vt,
2255 X86MemOperand x86memop, PatFrag mem_pat> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2256 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2257 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2258 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2259 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2260 (scalar_to_vector RC:$src2))))],
2261 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2262 let Constraints = "$src1 = $dst" in
2263 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2264 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2265 !strconcat(asm,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2266 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2267 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2268 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2269 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2270 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2271 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2272 let mayStore = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2273 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2274 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2275 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2276 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2277 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2278 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2279 [], IIC_SSE_MOV_S_MR>,
2280 EVEX, VEX_LIG, EVEX_K;
2281 } // mayStore
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2282 } //hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2283}
2284
2285let ExeDomain = SSEPackedSingle in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2286defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2287 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2288
2289let ExeDomain = SSEPackedDouble in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2290defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2291 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2292
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2293def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2294 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2295 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2296
2297def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2298 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2299 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2300
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2301def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2302 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2303 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2304
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2305// For the disassembler
Craig Topper3484fc22014-01-05 04:17:28 +0000[diff] [blame]2306let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2307 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2308 (ins VR128X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2309 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2310 IIC_SSE_MOV_S_RR>,
2311 XS, EVEX_4V, VEX_LIG;
2312 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2313 (ins VR128X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2314 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2315 IIC_SSE_MOV_S_RR>,
2316 XD, EVEX_4V, VEX_LIG, VEX_W;
2317}
2318
2319let Predicates = [HasAVX512] in {
2320 let AddedComplexity = 15 in {
2321 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2322 // MOVS{S,D} to the lower bits.
2323 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2324 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2325 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2326 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2327 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2328 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2329 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2330 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2331
2332 // Move low f32 and clear high bits.
2333 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2334 (SUBREG_TO_REG (i32 0),
2335 (VMOVSSZrr (v4f32 (V_SET0)),
2336 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2337 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2338 (SUBREG_TO_REG (i32 0),
2339 (VMOVSSZrr (v4i32 (V_SET0)),
2340 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2341 }
2342
2343 let AddedComplexity = 20 in {
2344 // MOVSSrm zeros the high parts of the register; represent this
2345 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2346 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2347 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2348 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2349 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2350 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2351 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2352
2353 // MOVSDrm zeros the high parts of the register; represent this
2354 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2355 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2356 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2357 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2358 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2359 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2360 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2361 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2362 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2363 def : Pat<(v2f64 (X86vzload addr:$src)),
2364 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2365
2366 // Represent the same patterns above but in the form they appear for
2367 // 256-bit types
2368 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2369 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2370 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2371 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2372 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2373 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2374 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2375 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2376 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2377 }
2378 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2379 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2380 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2381 FR32X:$src)), sub_xmm)>;
2382 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2383 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2384 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2385 FR64X:$src)), sub_xmm)>;
2386 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2387 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2388 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2389
2390 // Move low f64 and clear high bits.
2391 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2392 (SUBREG_TO_REG (i32 0),
2393 (VMOVSDZrr (v2f64 (V_SET0)),
2394 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2395
2396 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2397 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2398 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2399
2400 // Extract and store.
2401 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2402 addr:$dst),
2403 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2404 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2405 addr:$dst),
2406 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2407
2408 // Shuffle with VMOVSS
2409 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2410 (VMOVSSZrr (v4i32 VR128X:$src1),
2411 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2412 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2413 (VMOVSSZrr (v4f32 VR128X:$src1),
2414 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2415
2416 // 256-bit variants
2417 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2418 (SUBREG_TO_REG (i32 0),
2419 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2420 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2421 sub_xmm)>;
2422 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2423 (SUBREG_TO_REG (i32 0),
2424 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2425 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2426 sub_xmm)>;
2427
2428 // Shuffle with VMOVSD
2429 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2430 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2431 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2432 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2433 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2434 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2435 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2436 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2437
2438 // 256-bit variants
2439 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2440 (SUBREG_TO_REG (i32 0),
2441 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2442 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2443 sub_xmm)>;
2444 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2445 (SUBREG_TO_REG (i32 0),
2446 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2447 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2448 sub_xmm)>;
2449
2450 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2451 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2452 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2453 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2454 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2455 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2456 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2457 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2458}
2459
2460let AddedComplexity = 15 in
2461def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2462 (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2463 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2464 [(set VR128X:$dst, (v2i64 (X86vzmovl
2465 (v2i64 VR128X:$src))))],
2466 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2467
2468let AddedComplexity = 20 in
2469def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2470 (ins i128mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2471 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2472 [(set VR128X:$dst, (v2i64 (X86vzmovl
2473 (loadv2i64 addr:$src))))],
2474 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2475 EVEX_CD8<8, CD8VT8>;
2476
2477let Predicates = [HasAVX512] in {
2478 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2479 let AddedComplexity = 20 in {
2480 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2481 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2482 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2483 (VMOV64toPQIZrr GR64:$src)>;
2484 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2485 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2486
2487 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2488 (VMOVDI2PDIZrm addr:$src)>;
2489 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2490 (VMOVDI2PDIZrm addr:$src)>;
2491 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2492 (VMOVZPQILo2PQIZrm addr:$src)>;
2493 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2494 (VMOVZPQILo2PQIZrr VR128X:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]2495 def : Pat<(v2i64 (X86vzload addr:$src)),
2496 (VMOVZPQILo2PQIZrm addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2497 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2498
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2499 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2500 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2501 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2502 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2503 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2504 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2505 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2506}
2507
2508def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2509 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2510
2511def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2512 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2513
2514def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2515 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2516
2517def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2518 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2519
2520//===----------------------------------------------------------------------===//
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2521// AVX-512 - Non-temporals
2522//===----------------------------------------------------------------------===//
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2523let SchedRW = [WriteLoad] in {
2524 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2525 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2526 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2527 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2528 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2529
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2530 let Predicates = [HasAVX512, HasVLX] in {
2531 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2532 (ins i256mem:$src),
2533 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2534 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2535 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2536
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2537 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2538 (ins i128mem:$src),
2539 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2540 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2541 EVEX_CD8<64, CD8VF>;
2542 }
Adam Nemetefd07852014-06-18 16:51:10 +0000[diff] [blame]2543}
2544
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2545multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2546 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2547 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2548 let SchedRW = [WriteStore], mayStore = 1,
2549 AddedComplexity = 400 in
2550 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2551 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2552 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2553}
2554
2555multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2556 string elty, string elsz, string vsz512,
2557 string vsz256, string vsz128, Domain d,
2558 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2559 let Predicates = [prd] in
2560 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2561 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2562 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2563 EVEX_V512;
2564
2565 let Predicates = [prd, HasVLX] in {
2566 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2567 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2568 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2569 EVEX_V256;
2570
2571 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2572 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2573 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2574 EVEX_V128;
2575 }
2576}
2577
2578defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2579 "i", "64", "8", "4", "2", SSEPackedInt,
2580 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2581
2582defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2583 "f", "64", "8", "4", "2", SSEPackedDouble,
2584 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2585
2586defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2587 "f", "32", "16", "8", "4", SSEPackedSingle,
2588 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2589
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2590//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2591// AVX-512 - Integer arithmetic
2592//
2593multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2594 X86VectorVTInfo _, OpndItins itins,
2595 bit IsCommutable = 0> {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]2596 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2597 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2598 "$src2, $src1", "$src1, $src2",
2599 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2600 itins.rr, IsCommutable>,
2601 AVX512BIBase, EVEX_4V;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2602
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2603 let mayLoad = 1 in
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]2604 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2605 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2606 "$src2, $src1", "$src1, $src2",
2607 (_.VT (OpNode _.RC:$src1,
2608 (bitconvert (_.LdFrag addr:$src2)))),
2609 itins.rm>,
2610 AVX512BIBase, EVEX_4V;
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2611}
2612
2613multiclass avx512_binop_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
2614 X86VectorVTInfo _, OpndItins itins,
2615 bit IsCommutable = 0> :
2616 avx512_binop_rm<opc, OpcodeStr, OpNode, _, itins, IsCommutable> {
2617 let mayLoad = 1 in
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]2618 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2619 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2620 "${src2}"##_.BroadcastStr##", $src1",
2621 "$src1, ${src2}"##_.BroadcastStr,
2622 (_.VT (OpNode _.RC:$src1,
2623 (X86VBroadcast
2624 (_.ScalarLdFrag addr:$src2)))),
2625 itins.rm>,
2626 AVX512BIBase, EVEX_4V, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2627}
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2628
Robert Khasanovd5b14f72014-10-09 08:38:48 +0000[diff] [blame]2629multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2630 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2631 Predicate prd, bit IsCommutable = 0> {
2632 let Predicates = [prd] in
2633 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2634 IsCommutable>, EVEX_V512;
2635
2636 let Predicates = [prd, HasVLX] in {
2637 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2638 IsCommutable>, EVEX_V256;
2639 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2640 IsCommutable>, EVEX_V128;
2641 }
2642}
2643
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2644multiclass avx512_binop_rmb_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2645 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2646 Predicate prd, bit IsCommutable = 0> {
2647 let Predicates = [prd] in
2648 defm Z : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2649 IsCommutable>, EVEX_V512;
2650
2651 let Predicates = [prd, HasVLX] in {
2652 defm Z256 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2653 IsCommutable>, EVEX_V256;
2654 defm Z128 : avx512_binop_rmb<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2655 IsCommutable>, EVEX_V128;
2656 }
2657}
2658
2659multiclass avx512_binop_rm_vl_q<bits<8> opc, string OpcodeStr, SDNode OpNode,
2660 OpndItins itins, Predicate prd,
2661 bit IsCommutable = 0> {
2662 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i64_info,
2663 itins, prd, IsCommutable>,
2664 VEX_W, EVEX_CD8<64, CD8VF>;
2665}
2666
2667multiclass avx512_binop_rm_vl_d<bits<8> opc, string OpcodeStr, SDNode OpNode,
2668 OpndItins itins, Predicate prd,
2669 bit IsCommutable = 0> {
2670 defm NAME : avx512_binop_rmb_vl<opc, OpcodeStr, OpNode, avx512vl_i32_info,
2671 itins, prd, IsCommutable>, EVEX_CD8<32, CD8VF>;
2672}
2673
2674multiclass avx512_binop_rm_vl_w<bits<8> opc, string OpcodeStr, SDNode OpNode,
2675 OpndItins itins, Predicate prd,
2676 bit IsCommutable = 0> {
2677 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i16_info,
2678 itins, prd, IsCommutable>, EVEX_CD8<16, CD8VF>;
2679}
2680
2681multiclass avx512_binop_rm_vl_b<bits<8> opc, string OpcodeStr, SDNode OpNode,
2682 OpndItins itins, Predicate prd,
2683 bit IsCommutable = 0> {
2684 defm NAME : avx512_binop_rm_vl<opc, OpcodeStr, OpNode, avx512vl_i8_info,
2685 itins, prd, IsCommutable>, EVEX_CD8<8, CD8VF>;
2686}
2687
2688multiclass avx512_binop_rm_vl_dq<bits<8> opc_d, bits<8> opc_q, string OpcodeStr,
2689 SDNode OpNode, OpndItins itins, Predicate prd,
2690 bit IsCommutable = 0> {
2691 defm Q : avx512_binop_rm_vl_q<opc_q, OpcodeStr, OpNode, itins, prd,
2692 IsCommutable>;
2693
2694 defm D : avx512_binop_rm_vl_d<opc_d, OpcodeStr, OpNode, itins, prd,
2695 IsCommutable>;
2696}
2697
2698multiclass avx512_binop_rm_vl_bw<bits<8> opc_b, bits<8> opc_w, string OpcodeStr,
2699 SDNode OpNode, OpndItins itins, Predicate prd,
2700 bit IsCommutable = 0> {
2701 defm W : avx512_binop_rm_vl_w<opc_w, OpcodeStr, OpNode, itins, prd,
2702 IsCommutable>;
2703
2704 defm B : avx512_binop_rm_vl_b<opc_b, OpcodeStr, OpNode, itins, prd,
2705 IsCommutable>;
2706}
2707
2708multiclass avx512_binop_rm_vl_all<bits<8> opc_b, bits<8> opc_w,
2709 bits<8> opc_d, bits<8> opc_q,
2710 string OpcodeStr, SDNode OpNode,
2711 OpndItins itins, bit IsCommutable = 0> {
2712 defm NAME : avx512_binop_rm_vl_dq<opc_d, opc_q, OpcodeStr, OpNode,
2713 itins, HasAVX512, IsCommutable>,
2714 avx512_binop_rm_vl_bw<opc_b, opc_w, OpcodeStr, OpNode,
2715 itins, HasBWI, IsCommutable>;
2716}
2717
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2718multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2719 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2720 PatFrag memop_frag, X86MemOperand x86memop,
2721 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2722 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2723 let isCommutable = IsCommutable in
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2724 {
2725 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2726 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2727 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2728 []>, EVEX_4V;
2729 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2730 (ins KRC:$mask, RC:$src1, RC:$src2),
2731 !strconcat(OpcodeStr,
2732 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2733 [], itins.rr>, EVEX_4V, EVEX_K;
2734 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2735 (ins KRC:$mask, RC:$src1, RC:$src2),
2736 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2737 "|$dst {${mask}} {z}, $src1, $src2}"),
2738 [], itins.rr>, EVEX_4V, EVEX_KZ;
2739 }
2740 let mayLoad = 1 in {
2741 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2742 (ins RC:$src1, x86memop:$src2),
2743 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2744 []>, EVEX_4V;
2745 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2746 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2747 !strconcat(OpcodeStr,
2748 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2749 [], itins.rm>, EVEX_4V, EVEX_K;
2750 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2751 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2752 !strconcat(OpcodeStr,
2753 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2754 [], itins.rm>, EVEX_4V, EVEX_KZ;
2755 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2756 (ins RC:$src1, x86scalar_mop:$src2),
2757 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2758 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2759 [], itins.rm>, EVEX_4V, EVEX_B;
2760 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2761 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2762 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2763 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2764 BrdcstStr, "}"),
2765 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2766 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2767 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2768 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2769 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2770 BrdcstStr, "}"),
2771 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2772 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2773}
2774
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2775defm VPADD : avx512_binop_rm_vl_all<0xFC, 0xFD, 0xFE, 0xD4, "vpadd", add,
2776 SSE_INTALU_ITINS_P, 1>;
2777defm VPSUB : avx512_binop_rm_vl_all<0xF8, 0xF9, 0xFA, 0xFB, "vpsub", sub,
2778 SSE_INTALU_ITINS_P, 0>;
2779defm VPMULLD : avx512_binop_rm_vl_d<0x40, "vpmull", mul,
2780 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
2781defm VPMULLW : avx512_binop_rm_vl_w<0xD5, "vpmull", mul,
2782 SSE_INTALU_ITINS_P, HasBWI, 1>;
Robert Khasanov1a77f662014-10-14 15:13:56 +0000[diff] [blame]2783defm VPMULLQ : avx512_binop_rm_vl_q<0x40, "vpmull", mul,
2784 SSE_INTALU_ITINS_P, HasDQI, 1>, T8PD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2785
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2786defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2787 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2788 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2789 EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2790
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2791defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2792 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2793 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2794
2795def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2796 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2797
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2798def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2799 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2800 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2801def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2802 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2803 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2804
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2805defm VPMAXSB : avx512_binop_rm_vl_b<0x3C, "vpmaxs", X86smax,
2806 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2807defm VPMAXSW : avx512_binop_rm_vl_w<0xEE, "vpmaxs", X86smax,
2808 SSE_INTALU_ITINS_P, HasBWI, 1>;
2809defm VPMAXS : avx512_binop_rm_vl_dq<0x3D, 0x3D, "vpmaxs", X86smax,
2810 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2811
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2812defm VPMAXUB : avx512_binop_rm_vl_b<0xDE, "vpmaxu", X86umax,
2813 SSE_INTALU_ITINS_P, HasBWI, 1>;
2814defm VPMAXUW : avx512_binop_rm_vl_w<0x3E, "vpmaxu", X86umax,
2815 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2816defm VPMAXU : avx512_binop_rm_vl_dq<0x3F, 0x3F, "vpmaxu", X86umax,
2817 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2818
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2819defm VPMINSB : avx512_binop_rm_vl_b<0x38, "vpmins", X86smin,
2820 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2821defm VPMINSW : avx512_binop_rm_vl_w<0xEA, "vpmins", X86smin,
2822 SSE_INTALU_ITINS_P, HasBWI, 1>;
2823defm VPMINS : avx512_binop_rm_vl_dq<0x39, 0x39, "vpmins", X86smin,
2824 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2825
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2826defm VPMINUB : avx512_binop_rm_vl_b<0xDA, "vpminu", X86umin,
2827 SSE_INTALU_ITINS_P, HasBWI, 1>;
2828defm VPMINUW : avx512_binop_rm_vl_w<0x3A, "vpminu", X86umin,
2829 SSE_INTALU_ITINS_P, HasBWI, 1>, T8PD;
2830defm VPMINU : avx512_binop_rm_vl_dq<0x3B, 0x3B, "vpminu", X86umin,
2831 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2832
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2833def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2834 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2835 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2836def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2837 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2838 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2839def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2840 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2841 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2842def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2843 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2844 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2845def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2846 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2847 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2848def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2849 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2850 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2851def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2852 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2853 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2854def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2855 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2856 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2857//===----------------------------------------------------------------------===//
2858// AVX-512 - Unpack Instructions
2859//===----------------------------------------------------------------------===//
2860
2861multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2862 PatFrag mem_frag, RegisterClass RC,
2863 X86MemOperand x86memop, string asm,
2864 Domain d> {
2865 def rr : AVX512PI<opc, MRMSrcReg,
2866 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2867 asm, [(set RC:$dst,
2868 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2869 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2870 def rm : AVX512PI<opc, MRMSrcMem,
2871 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2872 asm, [(set RC:$dst,
2873 (vt (OpNode RC:$src1,
2874 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2875 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2876}
2877
2878defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2879 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2880 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2881defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2882 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2883 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2884defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2885 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2886 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2887defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2888 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2889 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2890
2891multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2892 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2893 X86MemOperand x86memop> {
2894 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2895 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2896 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2897 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2898 IIC_SSE_UNPCK>, EVEX_4V;
2899 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2900 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2901 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2902 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2903 (bitconvert (memop_frag addr:$src2)))))],
2904 IIC_SSE_UNPCK>, EVEX_4V;
2905}
2906defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2907 VR512, memopv16i32, i512mem>, EVEX_V512,
2908 EVEX_CD8<32, CD8VF>;
2909defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2910 VR512, memopv8i64, i512mem>, EVEX_V512,
2911 VEX_W, EVEX_CD8<64, CD8VF>;
2912defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2913 VR512, memopv16i32, i512mem>, EVEX_V512,
2914 EVEX_CD8<32, CD8VF>;
2915defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2916 VR512, memopv8i64, i512mem>, EVEX_V512,
2917 VEX_W, EVEX_CD8<64, CD8VF>;
2918//===----------------------------------------------------------------------===//
2919// AVX-512 - PSHUFD
2920//
2921
2922multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2923 SDNode OpNode, PatFrag mem_frag,
2924 X86MemOperand x86memop, ValueType OpVT> {
2925 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2926 (ins RC:$src1, i8imm:$src2),
2927 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2928 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2929 [(set RC:$dst,
2930 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2931 EVEX;
2932 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2933 (ins x86memop:$src1, i8imm:$src2),
2934 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2935 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2936 [(set RC:$dst,
2937 (OpVT (OpNode (mem_frag addr:$src1),
2938 (i8 imm:$src2))))]>, EVEX;
2939}
2940
2941defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2942 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2943
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2944//===----------------------------------------------------------------------===//
2945// AVX-512 Logical Instructions
2946//===----------------------------------------------------------------------===//
2947
Robert Khasanov545d1b72014-10-14 14:36:19 +0000[diff] [blame]2948defm VPAND : avx512_binop_rm_vl_dq<0xDB, 0xDB, "vpand", and,
2949 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2950defm VPOR : avx512_binop_rm_vl_dq<0xEB, 0xEB, "vpor", or,
2951 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2952defm VPXOR : avx512_binop_rm_vl_dq<0xEF, 0xEF, "vpxor", xor,
2953 SSE_INTALU_ITINS_P, HasAVX512, 1>;
2954defm VPANDN : avx512_binop_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
2955 SSE_INTALU_ITINS_P, HasAVX512, 1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2956
2957//===----------------------------------------------------------------------===//
2958// AVX-512 FP arithmetic
2959//===----------------------------------------------------------------------===//
2960
2961multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2962 SizeItins itins> {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2963 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2964 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2965 EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2966 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2967 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2968 EVEX_CD8<64, CD8VT1>;
2969}
2970
2971let isCommutable = 1 in {
2972defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2973defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2974defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2975defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2976}
2977let isCommutable = 0 in {
2978defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2979defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2980}
2981
2982multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2983 RegisterClass KRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2984 RegisterClass RC, ValueType vt,
2985 X86MemOperand x86memop, PatFrag mem_frag,
2986 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2987 string BrdcstStr,
2988 Domain d, OpndItins itins, bit commutable> {
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2989 let isCommutable = commutable in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2990 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2991 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2992 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2993 EVEX_4V;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2994
2995 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2996 !strconcat(OpcodeStr,
2997 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2998 [], itins.rr, d>, EVEX_4V, EVEX_K;
2999
3000 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
3001 !strconcat(OpcodeStr,
3002 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
3003 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
3004 }
3005
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3006 let mayLoad = 1 in {
3007 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3008 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3009 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3010 itins.rm, d>, EVEX_4V;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3011
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3012 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
3013 (ins RC:$src1, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3014 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3015 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3016 [(set RC:$dst, (OpNode RC:$src1,
3017 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3018 itins.rm, d>, EVEX_4V, EVEX_B;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3019
3020 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
3021 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
3022 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
3023 [], itins.rm, d>, EVEX_4V, EVEX_K;
3024
3025 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
3026 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
3027 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
3028 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
3029
3030 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
3031 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
3032 " \t{${src2}", BrdcstStr,
3033 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
3034 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
3035
3036 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
3037 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
3038 " \t{${src2}", BrdcstStr,
3039 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
3040 BrdcstStr, "}"),
3041 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
3042 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3043}
3044
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3045defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3046 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3047 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3048
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3049defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3050 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3051 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3052 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3053
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3054defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3055 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3056 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3057defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3058 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3059 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3060 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3061
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3062defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3063 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3064 SSE_ALU_ITINS_P.s, 1>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3065 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3066defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3067 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
3068 SSE_ALU_ITINS_P.s, 1>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3069 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3070
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3071defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3072 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3073 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3074 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3075defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3076 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3077 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3078 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3079
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3080defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3081 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3082 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3083defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3084 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3085 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3086
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3087defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3088 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3089 SSE_ALU_ITINS_P.d, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3090 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]3091defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3092 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
3093 SSE_ALU_ITINS_P.d, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3094 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3095
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3096def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3097 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3098 (i16 -1), FROUND_CURRENT)),
3099 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3100
3101def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3102 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3103 (i8 -1), FROUND_CURRENT)),
3104 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3105
3106def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3107 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3108 (i16 -1), FROUND_CURRENT)),
3109 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3110
3111def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3112 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3113 (i8 -1), FROUND_CURRENT)),
3114 (VMINPDZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3115//===----------------------------------------------------------------------===//
3116// AVX-512 VPTESTM instructions
3117//===----------------------------------------------------------------------===//
3118
3119multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3120 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3121 SDNode OpNode, ValueType vt> {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3122 def rr : AVX512PI<opc, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3123 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3124 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3125 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3126 SSEPackedInt>, EVEX_4V;
3127 def rm : AVX512PI<opc, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3128 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3129 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3130 [(set KRC:$dst, (OpNode (vt RC:$src1),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3131 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3132}
3133
3134defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3135 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3136 EVEX_CD8<32, CD8VF>;
3137defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3138 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3139 EVEX_CD8<64, CD8VF>;
3140
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3141let Predicates = [HasCDI] in {
3142defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3143 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3144 EVEX_CD8<32, CD8VF>;
3145defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3146 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3147 EVEX_CD8<64, CD8VF>;
3148}
3149
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3150def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3151 (v16i32 VR512:$src2), (i16 -1))),
3152 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3153
3154def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3155 (v8i64 VR512:$src2), (i8 -1))),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3156 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3157//===----------------------------------------------------------------------===//
3158// AVX-512 Shift instructions
3159//===----------------------------------------------------------------------===//
3160multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3161 string OpcodeStr, SDNode OpNode, RegisterClass RC,
3162 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
3163 RegisterClass KRC> {
3164 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3165 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3166 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3167 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3168 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3169 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3170 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3171 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3172 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3173 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3174 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3175 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3176 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3177 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3178 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3179 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3180 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3181 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3182 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3183 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3184}
3185
3186multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3187 RegisterClass RC, ValueType vt, ValueType SrcVT,
3188 PatFrag bc_frag, RegisterClass KRC> {
3189 // src2 is always 128-bit
3190 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3191 (ins RC:$src1, VR128X:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3192 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3193 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3194 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3195 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3196 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3197 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3198 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3199 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3200 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3201 (ins RC:$src1, i128mem:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3202 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3203 [(set RC:$dst, (vt (OpNode RC:$src1,
3204 (bc_frag (memopv2i64 addr:$src2)))))],
3205 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3206 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3207 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3208 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3209 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3210 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3211}
3212
3213defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3214 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3215 EVEX_V512, EVEX_CD8<32, CD8VF>;
3216defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3217 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3218 EVEX_CD8<32, CD8VQ>;
3219
3220defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3221 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3222 EVEX_CD8<64, CD8VF>, VEX_W;
3223defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3224 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3225 EVEX_CD8<64, CD8VQ>, VEX_W;
3226
3227defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3228 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3229 EVEX_CD8<32, CD8VF>;
3230defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3231 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3232 EVEX_CD8<32, CD8VQ>;
3233
3234defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3235 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3236 EVEX_CD8<64, CD8VF>, VEX_W;
3237defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3238 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3239 EVEX_CD8<64, CD8VQ>, VEX_W;
3240
3241defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3242 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3243 EVEX_V512, EVEX_CD8<32, CD8VF>;
3244defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3245 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3246 EVEX_CD8<32, CD8VQ>;
3247
3248defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3249 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3250 EVEX_CD8<64, CD8VF>, VEX_W;
3251defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3252 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3253 EVEX_CD8<64, CD8VQ>, VEX_W;
3254
3255//===-------------------------------------------------------------------===//
3256// Variable Bit Shifts
3257//===-------------------------------------------------------------------===//
3258multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3259 RegisterClass RC, ValueType vt,
3260 X86MemOperand x86memop, PatFrag mem_frag> {
3261 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3262 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3263 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3264 [(set RC:$dst,
3265 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3266 EVEX_4V;
3267 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3268 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3269 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3270 [(set RC:$dst,
3271 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3272 EVEX_4V;
3273}
3274
3275defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3276 i512mem, memopv16i32>, EVEX_V512,
3277 EVEX_CD8<32, CD8VF>;
3278defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3279 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3280 EVEX_CD8<64, CD8VF>;
3281defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3282 i512mem, memopv16i32>, EVEX_V512,
3283 EVEX_CD8<32, CD8VF>;
3284defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3285 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3286 EVEX_CD8<64, CD8VF>;
3287defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3288 i512mem, memopv16i32>, EVEX_V512,
3289 EVEX_CD8<32, CD8VF>;
3290defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3291 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3292 EVEX_CD8<64, CD8VF>;
3293
3294//===----------------------------------------------------------------------===//
3295// AVX-512 - MOVDDUP
3296//===----------------------------------------------------------------------===//
3297
3298multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3299 X86MemOperand x86memop, PatFrag memop_frag> {
3300def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3301 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3302 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3303def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3304 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3305 [(set RC:$dst,
3306 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3307}
3308
3309defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3310 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3311def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3312 (VMOVDDUPZrm addr:$src)>;
3313
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3314//===---------------------------------------------------------------------===//
3315// Replicate Single FP - MOVSHDUP and MOVSLDUP
3316//===---------------------------------------------------------------------===//
3317multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3318 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3319 X86MemOperand x86memop> {
3320 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3321 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3322 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3323 let mayLoad = 1 in
3324 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3325 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3326 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3327}
3328
3329defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3330 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3331 EVEX_CD8<32, CD8VF>;
3332defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3333 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3334 EVEX_CD8<32, CD8VF>;
3335
3336def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3337def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3338 (VMOVSHDUPZrm addr:$src)>;
3339def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3340def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3341 (VMOVSLDUPZrm addr:$src)>;
3342
3343//===----------------------------------------------------------------------===//
3344// Move Low to High and High to Low packed FP Instructions
3345//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3346def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3347 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3348 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3349 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3350 IIC_SSE_MOV_LH>, EVEX_4V;
3351def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3352 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3353 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3354 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3355 IIC_SSE_MOV_LH>, EVEX_4V;
3356
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3357let Predicates = [HasAVX512] in {
3358 // MOVLHPS patterns
3359 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3360 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3361 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3362 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3363
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3364 // MOVHLPS patterns
3365 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3366 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3367}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3368
3369//===----------------------------------------------------------------------===//
3370// FMA - Fused Multiply Operations
3371//
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3372
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3373let Constraints = "$src1 = $dst" in {
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3374// Omitting the parameter OpNode (= null_frag) disables ISel pattern matching.
3375multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
3376 SDPatternOperator OpNode = null_frag> {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]3377 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3378 (ins _.RC:$src2, _.RC:$src3),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3379 OpcodeStr, "$src3, $src2", "$src2, $src3",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3380 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3381 AVX512FMA3Base;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3382
3383 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3384 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3385 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3386 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3387 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3388 (_.MemOpFrag addr:$src3))))]>;
3389 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3390 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3391 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3392 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3393 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3394 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3395}
3396} // Constraints = "$src1 = $dst"
3397
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3398multiclass avx512_fma3p_forms<bits<8> opc213, bits<8> opc231,
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3399 string OpcodeStr, X86VectorVTInfo VTI,
3400 SDPatternOperator OpNode> {
3401 defm v213 : avx512_fma3p_rm<opc213, !strconcat(OpcodeStr, "213", VTI.Suffix),
3402 VTI, OpNode>,
3403 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3404
3405 defm v231 : avx512_fma3p_rm<opc231, !strconcat(OpcodeStr, "231", VTI.Suffix),
3406 VTI>,
3407 EVEX_V512, EVEX_CD8<VTI.EltSize, CD8VF>;
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3408}
3409
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3410let ExeDomain = SSEPackedSingle in {
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3411 defm VFMADDPSZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3412 v16f32_info, X86Fmadd>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3413 defm VFMSUBPSZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3414 v16f32_info, X86Fmsub>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3415 defm VFMADDSUBPSZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3416 v16f32_info, X86Fmaddsub>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3417 defm VFMSUBADDPSZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3418 v16f32_info, X86Fmsubadd>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3419 defm VFNMADDPSZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3420 v16f32_info, X86Fnmadd>;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3421 defm VFNMSUBPSZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3422 v16f32_info, X86Fnmsub>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3423}
3424let ExeDomain = SSEPackedDouble in {
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3425 defm VFMADDPDZ : avx512_fma3p_forms<0xA8, 0xB8, "vfmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3426 v8f64_info, X86Fmadd>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3427 defm VFMSUBPDZ : avx512_fma3p_forms<0xAA, 0xBA, "vfmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3428 v8f64_info, X86Fmsub>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3429 defm VFMADDSUBPDZ : avx512_fma3p_forms<0xA6, 0xB6, "vfmaddsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3430 v8f64_info, X86Fmaddsub>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3431 defm VFMSUBADDPDZ : avx512_fma3p_forms<0xA7, 0xB7, "vfmsubadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3432 v8f64_info, X86Fmsubadd>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3433 defm VFNMADDPDZ : avx512_fma3p_forms<0xAC, 0xBC, "vfnmadd",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3434 v8f64_info, X86Fnmadd>, VEX_W;
Adam Nemet832ec5e2014-10-24 00:03:00 +0000[diff] [blame]3435 defm VFNMSUBPDZ : avx512_fma3p_forms<0xAE, 0xBE, "vfnmsub",
Adam Nemet26371ce2014-10-24 00:02:55 +0000[diff] [blame]3436 v8f64_info, X86Fnmsub>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3437}
3438
3439let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3440multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3441 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3442 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3443 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3444 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3445 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3446 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3447 _.RC:$src3)))]>;
3448 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3449 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3450 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3451 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3452 [(set _.RC:$dst,
3453 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3454 (_.ScalarLdFrag addr:$src2))),
3455 _.RC:$src3))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3456}
3457} // Constraints = "$src1 = $dst"
3458
3459
3460let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3461 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3462 v16f32_info>,
3463 EVEX_V512, EVEX_CD8<32, CD8VF>;
3464 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3465 v16f32_info>,
3466 EVEX_V512, EVEX_CD8<32, CD8VF>;
3467 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3468 v16f32_info>,
3469 EVEX_V512, EVEX_CD8<32, CD8VF>;
3470 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3471 v16f32_info>,
3472 EVEX_V512, EVEX_CD8<32, CD8VF>;
3473 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3474 v16f32_info>,
3475 EVEX_V512, EVEX_CD8<32, CD8VF>;
3476 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3477 v16f32_info>,
3478 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3479}
3480let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3481 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3482 v8f64_info>,
3483 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3484 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3485 v8f64_info>,
3486 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3487 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3488 v8f64_info>,
3489 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3490 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3491 v8f64_info>,
3492 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3493 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3494 v8f64_info>,
3495 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3496 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3497 v8f64_info>,
3498 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3499}
3500
3501// Scalar FMA
3502let Constraints = "$src1 = $dst" in {
3503multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3504 RegisterClass RC, ValueType OpVT,
3505 X86MemOperand x86memop, Operand memop,
3506 PatFrag mem_frag> {
3507 let isCommutable = 1 in
3508 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3509 (ins RC:$src1, RC:$src2, RC:$src3),
3510 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3511 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3512 [(set RC:$dst,
3513 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3514 let mayLoad = 1 in
3515 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3516 (ins RC:$src1, RC:$src2, f128mem:$src3),
3517 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3518 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3519 [(set RC:$dst,
3520 (OpVT (OpNode RC:$src2, RC:$src1,
3521 (mem_frag addr:$src3))))]>;
3522}
3523
3524} // Constraints = "$src1 = $dst"
3525
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3526defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3527 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3528defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3529 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3530defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3531 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3532defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3533 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3534defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3535 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3536defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3537 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3538defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3539 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3540defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3541 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3542
3543//===----------------------------------------------------------------------===//
3544// AVX-512 Scalar convert from sign integer to float/double
3545//===----------------------------------------------------------------------===//
3546
3547multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3548 X86MemOperand x86memop, string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3549let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3550 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3551 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3552 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3553 let mayLoad = 1 in
3554 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3555 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3556 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3557 EVEX_4V;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3558} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3559}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3560let Predicates = [HasAVX512] in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3561defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3562 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3563defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3564 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3565defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3566 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3567defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3568 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3569
3570def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3571 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3572def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3573 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3574def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3575 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3576def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3577 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3578
3579def : Pat<(f32 (sint_to_fp GR32:$src)),
3580 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3581def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3582 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3583def : Pat<(f64 (sint_to_fp GR32:$src)),
3584 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3585def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3586 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3587
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3588defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3589 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3590defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3591 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3592defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3593 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3594defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3595 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3596
3597def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3598 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3599def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3600 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3601def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3602 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3603def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3604 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3605
3606def : Pat<(f32 (uint_to_fp GR32:$src)),
3607 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3608def : Pat<(f32 (uint_to_fp GR64:$src)),
3609 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3610def : Pat<(f64 (uint_to_fp GR32:$src)),
3611 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3612def : Pat<(f64 (uint_to_fp GR64:$src)),
3613 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3614}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3615
3616//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3617// AVX-512 Scalar convert from float/double to integer
3618//===----------------------------------------------------------------------===//
3619multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3620 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3621 string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3622let hasSideEffects = 0 in {
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3623 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3624 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3625 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3626 Requires<[HasAVX512]>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3627 let mayLoad = 1 in
3628 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3629 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3630 Requires<[HasAVX512]>;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3631} // hasSideEffects = 0
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3632}
3633let Predicates = [HasAVX512] in {
3634// Convert float/double to signed/unsigned int 32/64
3635defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3636 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3637 XS, EVEX_CD8<32, CD8VT1>;
3638defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3639 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3640 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3641defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3642 ssmem, sse_load_f32, "cvtss2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3643 XS, EVEX_CD8<32, CD8VT1>;
3644defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3645 int_x86_avx512_cvtss2usi64, ssmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3646 sse_load_f32, "cvtss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3647 EVEX_CD8<32, CD8VT1>;
3648defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3649 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3650 XD, EVEX_CD8<64, CD8VT1>;
3651defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3652 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3653 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3654defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3655 sdmem, sse_load_f64, "cvtsd2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3656 XD, EVEX_CD8<64, CD8VT1>;
3657defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3658 int_x86_avx512_cvtsd2usi64, sdmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3659 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3660 EVEX_CD8<64, CD8VT1>;
3661
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3662let isCodeGenOnly = 1 in {
3663 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3664 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3665 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3666 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3667 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3668 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3669 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3670 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3671 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3672 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3673 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3674 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3675
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3676 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3677 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3678 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3679 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3680 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3681 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3682 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3683 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3684 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3685 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3686 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3687 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3688} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3689
3690// Convert float/double to signed/unsigned int 32/64 with truncation
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3691let isCodeGenOnly = 1 in {
3692 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3693 ssmem, sse_load_f32, "cvttss2si">,
3694 XS, EVEX_CD8<32, CD8VT1>;
3695 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3696 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3697 "cvttss2si">, XS, VEX_W,
3698 EVEX_CD8<32, CD8VT1>;
3699 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3700 sdmem, sse_load_f64, "cvttsd2si">, XD,
3701 EVEX_CD8<64, CD8VT1>;
3702 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3703 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3704 "cvttsd2si">, XD, VEX_W,
3705 EVEX_CD8<64, CD8VT1>;
3706 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3707 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3708 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3709 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3710 int_x86_avx512_cvttss2usi64, ssmem,
3711 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3712 EVEX_CD8<32, CD8VT1>;
3713 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3714 int_x86_avx512_cvttsd2usi,
3715 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3716 EVEX_CD8<64, CD8VT1>;
3717 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3718 int_x86_avx512_cvttsd2usi64, sdmem,
3719 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3720 EVEX_CD8<64, CD8VT1>;
3721} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3722
3723multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3724 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3725 string asm> {
3726 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3727 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3728 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3729 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3730 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3731 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3732}
3733
3734defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3735 loadf32, "cvttss2si">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3736 EVEX_CD8<32, CD8VT1>;
3737defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3738 loadf32, "cvttss2usi">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3739 EVEX_CD8<32, CD8VT1>;
3740defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3741 loadf32, "cvttss2si">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3742 EVEX_CD8<32, CD8VT1>;
3743defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3744 loadf32, "cvttss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3745 EVEX_CD8<32, CD8VT1>;
3746defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3747 loadf64, "cvttsd2si">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3748 EVEX_CD8<64, CD8VT1>;
3749defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3750 loadf64, "cvttsd2usi">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3751 EVEX_CD8<64, CD8VT1>;
3752defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3753 loadf64, "cvttsd2si">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3754 EVEX_CD8<64, CD8VT1>;
3755defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3756 loadf64, "cvttsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3757 EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3758} // HasAVX512
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3759//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3760// AVX-512 Convert form float to double and back
3761//===----------------------------------------------------------------------===//
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3762let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3763def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3764 (ins FR32X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3765 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3766 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3767let mayLoad = 1 in
3768def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3769 (ins FR32X:$src1, f32mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3770 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3771 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3772 EVEX_CD8<32, CD8VT1>;
3773
3774// Convert scalar double to scalar single
3775def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3776 (ins FR64X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3777 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3778 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3779let mayLoad = 1 in
3780def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3781 (ins FR64X:$src1, f64mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3782 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3783 []>, EVEX_4V, VEX_LIG, VEX_W,
3784 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3785}
3786
3787def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3788 Requires<[HasAVX512]>;
3789def : Pat<(fextend (loadf32 addr:$src)),
3790 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3791
3792def : Pat<(extloadf32 addr:$src),
3793 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3794 Requires<[HasAVX512, OptForSize]>;
3795
3796def : Pat<(extloadf32 addr:$src),
3797 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3798 Requires<[HasAVX512, OptForSpeed]>;
3799
3800def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3801 Requires<[HasAVX512]>;
3802
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3803multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3804 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3805 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3806 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3807let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3808 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3809 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3810 [(set DstRC:$dst,
3811 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3812 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3813 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3814 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3815 let mayLoad = 1 in
3816 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3817 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3818 [(set DstRC:$dst,
3819 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3820} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3821}
3822
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3823multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3824 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3825 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3826 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3827let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3828 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3829 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3830 [(set DstRC:$dst,
3831 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3832 let mayLoad = 1 in
3833 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3834 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3835 [(set DstRC:$dst,
3836 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3837} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3838}
3839
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3840defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3841 memopv8f64, f512mem, v8f32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3842 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3843 EVEX_CD8<64, CD8VF>;
3844
3845defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3846 memopv4f64, f256mem, v8f64, v8f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3847 SSEPackedDouble>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3848 EVEX_CD8<32, CD8VH>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3849def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3850 (VCVTPS2PDZrm addr:$src)>;
Elena Demikhovsky3629b4a2014-01-06 08:45:54 +0000[diff] [blame]3851
3852def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3853 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3854 (VCVTPD2PSZrr VR512:$src)>;
3855
3856def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3857 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3858 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3859
3860//===----------------------------------------------------------------------===//
3861// AVX-512 Vector convert from sign integer to float/double
3862//===----------------------------------------------------------------------===//
3863
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3864defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3865 memopv8i64, i512mem, v16f32, v16i32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3866 SSEPackedSingle>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3867 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3868
3869defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3870 memopv4i64, i256mem, v8f64, v8i32,
3871 SSEPackedDouble>, EVEX_V512, XS,
3872 EVEX_CD8<32, CD8VH>;
3873
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3874defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3875 memopv16f32, f512mem, v16i32, v16f32,
3876 SSEPackedSingle>, EVEX_V512, XS,
3877 EVEX_CD8<32, CD8VF>;
3878
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3879defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3880 memopv8f64, f512mem, v8i32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3881 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3882 EVEX_CD8<64, CD8VF>;
3883
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3884defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3885 memopv16f32, f512mem, v16i32, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3886 SSEPackedSingle>, EVEX_V512, PS,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3887 EVEX_CD8<32, CD8VF>;
3888
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3889// cvttps2udq (src, 0, mask-all-ones, sae-current)
3890def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3891 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3892 (VCVTTPS2UDQZrr VR512:$src)>;
3893
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3894defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3895 memopv8f64, f512mem, v8i32, v8f64,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3896 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3897 EVEX_CD8<64, CD8VF>;
3898
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3899// cvttpd2udq (src, 0, mask-all-ones, sae-current)
3900def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3901 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3902 (VCVTTPD2UDQZrr VR512:$src)>;
3903
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3904defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3905 memopv4i64, f256mem, v8f64, v8i32,
3906 SSEPackedDouble>, EVEX_V512, XS,
3907 EVEX_CD8<32, CD8VH>;
3908
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3909defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3910 memopv16i32, f512mem, v16f32, v16i32,
3911 SSEPackedSingle>, EVEX_V512, XD,
3912 EVEX_CD8<32, CD8VF>;
3913
3914def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3915 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3916 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3917
Elena Demikhovsky3dcfbdf2014-04-08 07:24:02 +0000[diff] [blame]3918def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3919 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3920 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3921
3922def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3923 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3924 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3925
3926def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3927 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3928 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3929
Cameron McInallyf10a7c92014-06-18 14:04:37 +0000[diff] [blame]3930def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3931 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3932 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3933
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3934def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3935 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3936 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3937def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3938 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3939 (VCVTDQ2PDZrr VR256X:$src)>;
3940def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3941 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3942 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3943def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3944 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3945 (VCVTUDQ2PDZrr VR256X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3946
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3947multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3948 RegisterClass DstRC, PatFrag mem_frag,
3949 X86MemOperand x86memop, Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3950let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3951 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3952 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3953 [], d>, EVEX;
3954 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3955 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3956 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3957 let mayLoad = 1 in
3958 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3959 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3960 [], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3961} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3962}
3963
3964defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3965 memopv16f32, f512mem, SSEPackedSingle>, PD,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3966 EVEX_V512, EVEX_CD8<32, CD8VF>;
3967defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3968 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3969 EVEX_V512, EVEX_CD8<64, CD8VF>;
3970
3971def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3972 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3973 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3974
3975def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3976 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3977 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3978
3979defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3980 memopv16f32, f512mem, SSEPackedSingle>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3981 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3982defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3983 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3984 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3985
3986def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3987 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3988 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3989
3990def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3991 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3992 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3993
3994let Predicates = [HasAVX512] in {
3995 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3996 (VCVTPD2PSZrm addr:$src)>;
3997 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3998 (VCVTPS2PDZrm addr:$src)>;
3999}
4000
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]4001//===----------------------------------------------------------------------===//
4002// Half precision conversion instructions
4003//===----------------------------------------------------------------------===//
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]4004multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
4005 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]4006 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
4007 "vcvtph2ps\t{$src, $dst|$dst, $src}",
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]4008 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]4009 let hasSideEffects = 0, mayLoad = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]4010 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
4011 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
4012}
4013
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]4014multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
4015 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]4016 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
4017 (ins srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]4018 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4019 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]4020 let hasSideEffects = 0, mayStore = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]4021 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
4022 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]4023 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]4024}
4025
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]4026defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]4027 EVEX_CD8<32, CD8VH>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]4028defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]4029 EVEX_CD8<32, CD8VH>;
4030
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]4031def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
4032 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
4033 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
4034
4035def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
4036 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
4037 (VCVTPH2PSZrr VR256X:$src)>;
4038
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4039let Defs = [EFLAGS], Predicates = [HasAVX512] in {
4040 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4041 "ucomiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4042 EVEX_CD8<32, CD8VT1>;
4043 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4044 "ucomisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4045 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4046 let Pattern = []<dag> in {
4047 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4048 "comiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4049 EVEX_CD8<32, CD8VT1>;
4050 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4051 "comisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4052 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4053 }
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4054 let isCodeGenOnly = 1 in {
4055 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4056 load, "ucomiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4057 EVEX_CD8<32, CD8VT1>;
4058 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4059 load, "ucomisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4060 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4061
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4062 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4063 load, "comiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4064 EVEX_CD8<32, CD8VT1>;
4065 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4066 load, "comisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4067 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
4068 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4069}
4070
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4071/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
4072multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4073 X86MemOperand x86memop> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4074 let hasSideEffects = 0 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4075 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4076 (ins RC:$src1, RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4077 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4078 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4079 let mayLoad = 1 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4080 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4081 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4082 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4083 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4084 }
4085}
4086}
4087
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4088defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
4089 EVEX_CD8<32, CD8VT1>;
4090defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
4091 VEX_W, EVEX_CD8<64, CD8VT1>;
4092defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
4093 EVEX_CD8<32, CD8VT1>;
4094defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
4095 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4096
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4097def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4098 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4099 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4100 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4101
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4102def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4103 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4104 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4105 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4106
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4107def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4108 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4109 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4110 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4111
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4112def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4113 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4114 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4115 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4116
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4117/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4118multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4119 RegisterClass RC, X86MemOperand x86memop,
4120 PatFrag mem_frag, ValueType OpVt> {
4121 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4122 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4123 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4124 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
4125 EVEX;
4126 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4127 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4128 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
4129 EVEX;
4130}
4131defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
4132 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4133defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
4134 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4135defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
4136 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4137defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
4138 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4139
4140def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4141 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4142 (VRSQRT14PSZr VR512:$src)>;
4143def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4144 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4145 (VRSQRT14PDZr VR512:$src)>;
4146
4147def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4148 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4149 (VRCP14PSZr VR512:$src)>;
4150def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4151 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4152 (VRCP14PDZr VR512:$src)>;
4153
4154/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4155multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4156 X86MemOperand x86memop> {
4157 let hasSideEffects = 0, Predicates = [HasERI] in {
4158 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4159 (ins RC:$src1, RC:$src2),
4160 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4161 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4162 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4163 (ins RC:$src1, RC:$src2),
4164 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4165 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4166 []>, EVEX_4V, EVEX_B;
4167 let mayLoad = 1 in {
4168 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4169 (ins RC:$src1, x86memop:$src2),
4170 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4171 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4172 }
4173}
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4174}
4175
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4176defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4177 EVEX_CD8<32, CD8VT1>;
4178defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4179 VEX_W, EVEX_CD8<64, CD8VT1>;
4180defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4181 EVEX_CD8<32, CD8VT1>;
4182defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4183 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4184
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4185def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4186 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4187 FROUND_NO_EXC)),
4188 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4189 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4190
4191def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4192 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4193 FROUND_NO_EXC)),
4194 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4195 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4196
4197def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4198 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4199 FROUND_NO_EXC)),
4200 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4201 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4202
4203def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4204 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4205 FROUND_NO_EXC)),
4206 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4207 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4208
4209/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4210multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4211 RegisterClass RC, X86MemOperand x86memop> {
4212 let hasSideEffects = 0, Predicates = [HasERI] in {
4213 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4214 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4215 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4216 []>, EVEX;
4217 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4218 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4219 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4220 []>, EVEX, EVEX_B;
4221 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4222 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4223 []>, EVEX;
4224 }
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4225}
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4226defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4227 EVEX_V512, EVEX_CD8<32, CD8VF>;
4228defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4229 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4230defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4231 EVEX_V512, EVEX_CD8<32, CD8VF>;
4232defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4233 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4234
4235def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4236 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4237 (VRSQRT28PSZrb VR512:$src)>;
4238def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4239 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4240 (VRSQRT28PDZrb VR512:$src)>;
4241
4242def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4243 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4244 (VRCP28PSZrb VR512:$src)>;
4245def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4246 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4247 (VRCP28PDZrb VR512:$src)>;
4248
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4249multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4250 OpndItins itins_s, OpndItins itins_d> {
4251 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4252 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4253 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
4254 EVEX, EVEX_V512;
4255
4256 let mayLoad = 1 in
4257 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4258 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4259 [(set VR512:$dst,
4260 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
4261 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
4262
4263 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4264 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4265 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
4266 EVEX, EVEX_V512;
4267
4268 let mayLoad = 1 in
4269 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4270 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4271 [(set VR512:$dst, (OpNode
4272 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
4273 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
4274
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4275}
4276
4277multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4278 Intrinsic F32Int, Intrinsic F64Int,
4279 OpndItins itins_s, OpndItins itins_d> {
4280 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4281 (ins FR32X:$src1, FR32X:$src2),
4282 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4283 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4284 [], itins_s.rr>, XS, EVEX_4V;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4285 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4286 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4287 (ins VR128X:$src1, VR128X:$src2),
4288 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4289 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4290 [(set VR128X:$dst,
4291 (F32Int VR128X:$src1, VR128X:$src2))],
4292 itins_s.rr>, XS, EVEX_4V;
4293 let mayLoad = 1 in {
4294 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4295 (ins FR32X:$src1, f32mem:$src2),
4296 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4297 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4298 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4299 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4300 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4301 (ins VR128X:$src1, ssmem:$src2),
4302 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4303 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4304 [(set VR128X:$dst,
4305 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4306 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4307 }
4308 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4309 (ins FR64X:$src1, FR64X:$src2),
4310 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4311 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4312 XD, EVEX_4V, VEX_W;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4313 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4314 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4315 (ins VR128X:$src1, VR128X:$src2),
4316 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4317 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4318 [(set VR128X:$dst,
4319 (F64Int VR128X:$src1, VR128X:$src2))],
4320 itins_s.rr>, XD, EVEX_4V, VEX_W;
4321 let mayLoad = 1 in {
4322 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4323 (ins FR64X:$src1, f64mem:$src2),
4324 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4325 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4326 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4327 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4328 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4329 (ins VR128X:$src1, sdmem:$src2),
4330 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4331 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4332 [(set VR128X:$dst,
4333 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4334 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4335 }
4336}
4337
4338
4339defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4340 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4341 SSE_SQRTSS, SSE_SQRTSD>,
4342 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4343 SSE_SQRTPS, SSE_SQRTPD>;
4344
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4345let Predicates = [HasAVX512] in {
Elena Demikhovskyf1648592014-07-22 11:07:31 +0000[diff] [blame]4346 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4347 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4348 (VSQRTPSZrr VR512:$src1)>;
4349 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4350 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4351 (VSQRTPDZrr VR512:$src1)>;
4352
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4353 def : Pat<(f32 (fsqrt FR32X:$src)),
4354 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4355 def : Pat<(f32 (fsqrt (load addr:$src))),
4356 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4357 Requires<[OptForSize]>;
4358 def : Pat<(f64 (fsqrt FR64X:$src)),
4359 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4360 def : Pat<(f64 (fsqrt (load addr:$src))),
4361 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4362 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4363
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4364 def : Pat<(f32 (X86frsqrt FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4365 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4366 def : Pat<(f32 (X86frsqrt (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4367 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4368 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4369
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4370 def : Pat<(f32 (X86frcp FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4371 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4372 def : Pat<(f32 (X86frcp (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4373 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4374 Requires<[OptForSize]>;
4375
4376 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4377 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4378 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4379 VR128X)>;
4380 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4381 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4382
4383 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4384 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4385 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4386 VR128X)>;
4387 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4388 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4389}
4390
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4391
4392multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4393 X86MemOperand x86memop, RegisterClass RC,
4394 PatFrag mem_frag32, PatFrag mem_frag64,
4395 Intrinsic V4F32Int, Intrinsic V2F64Int,
4396 CD8VForm VForm> {
4397let ExeDomain = SSEPackedSingle in {
4398 // Intrinsic operation, reg.
4399 // Vector intrinsic operation, reg
4400 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4401 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4402 !strconcat(OpcodeStr,
4403 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4404 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4405
4406 // Vector intrinsic operation, mem
4407 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4408 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4409 !strconcat(OpcodeStr,
4410 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4411 [(set RC:$dst,
4412 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4413 EVEX_CD8<32, VForm>;
4414} // ExeDomain = SSEPackedSingle
4415
4416let ExeDomain = SSEPackedDouble in {
4417 // Vector intrinsic operation, reg
4418 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4419 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4420 !strconcat(OpcodeStr,
4421 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4422 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4423
4424 // Vector intrinsic operation, mem
4425 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4426 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4427 !strconcat(OpcodeStr,
4428 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4429 [(set RC:$dst,
4430 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4431 EVEX_CD8<64, VForm>;
4432} // ExeDomain = SSEPackedDouble
4433}
4434
4435multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4436 string OpcodeStr,
4437 Intrinsic F32Int,
4438 Intrinsic F64Int> {
4439let ExeDomain = GenericDomain in {
4440 // Operation, reg.
4441 let hasSideEffects = 0 in
4442 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4443 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4444 !strconcat(OpcodeStr,
4445 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4446 []>;
4447
4448 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4449 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4450 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4451 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4452 !strconcat(OpcodeStr,
4453 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4454 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4455
4456 // Intrinsic operation, mem.
4457 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4458 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4459 !strconcat(OpcodeStr,
4460 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4461 [(set VR128X:$dst, (F32Int VR128X:$src1,
4462 sse_load_f32:$src2, imm:$src3))]>,
4463 EVEX_CD8<32, CD8VT1>;
4464
4465 // Operation, reg.
4466 let hasSideEffects = 0 in
4467 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4468 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4469 !strconcat(OpcodeStr,
4470 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4471 []>, VEX_W;
4472
4473 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4474 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4475 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4476 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4477 !strconcat(OpcodeStr,
4478 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4479 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4480 VEX_W;
4481
4482 // Intrinsic operation, mem.
4483 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4484 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4485 !strconcat(OpcodeStr,
4486 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4487 [(set VR128X:$dst,
4488 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4489 VEX_W, EVEX_CD8<64, CD8VT1>;
4490} // ExeDomain = GenericDomain
4491}
4492
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4493multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4494 X86MemOperand x86memop, RegisterClass RC,
4495 PatFrag mem_frag, Domain d> {
4496let ExeDomain = d in {
4497 // Intrinsic operation, reg.
4498 // Vector intrinsic operation, reg
4499 def r : AVX512AIi8<opc, MRMSrcReg,
4500 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4501 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4502 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4503 []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4504
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4505 // Vector intrinsic operation, mem
4506 def m : AVX512AIi8<opc, MRMSrcMem,
4507 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4508 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4509 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4510 []>, EVEX;
4511} // ExeDomain
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4512}
4513
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4514
4515defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4516 memopv16f32, SSEPackedSingle>, EVEX_V512,
4517 EVEX_CD8<32, CD8VF>;
4518
4519def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4520 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4521 FROUND_CURRENT)),
4522 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4523
4524
4525defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4526 memopv8f64, SSEPackedDouble>, EVEX_V512,
4527 VEX_W, EVEX_CD8<64, CD8VF>;
4528
4529def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4530 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4531 FROUND_CURRENT)),
4532 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4533
4534multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4535 Operand x86memop, RegisterClass RC, Domain d> {
4536let ExeDomain = d in {
4537 def r : AVX512AIi8<opc, MRMSrcReg,
4538 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4539 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4540 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4541 []>, EVEX_4V;
4542
4543 def m : AVX512AIi8<opc, MRMSrcMem,
4544 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4545 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4546 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4547 []>, EVEX_4V;
4548} // ExeDomain
4549}
4550
4551defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4552 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4553
4554defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4555 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4556
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4557def : Pat<(ffloor FR32X:$src),
4558 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4559def : Pat<(f64 (ffloor FR64X:$src)),
4560 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4561def : Pat<(f32 (fnearbyint FR32X:$src)),
4562 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4563def : Pat<(f64 (fnearbyint FR64X:$src)),
4564 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4565def : Pat<(f32 (fceil FR32X:$src)),
4566 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4567def : Pat<(f64 (fceil FR64X:$src)),
4568 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4569def : Pat<(f32 (frint FR32X:$src)),
4570 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4571def : Pat<(f64 (frint FR64X:$src)),
4572 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4573def : Pat<(f32 (ftrunc FR32X:$src)),
4574 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4575def : Pat<(f64 (ftrunc FR64X:$src)),
4576 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4577
4578def : Pat<(v16f32 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4579 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4580def : Pat<(v16f32 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4581 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4582def : Pat<(v16f32 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4583 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4584def : Pat<(v16f32 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4585 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4586def : Pat<(v16f32 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4587 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4588
4589def : Pat<(v8f64 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4590 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4591def : Pat<(v8f64 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4592 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4593def : Pat<(v8f64 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4594 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4595def : Pat<(v8f64 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4596 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4597def : Pat<(v8f64 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4598 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4599
4600//-------------------------------------------------
4601// Integer truncate and extend operations
4602//-------------------------------------------------
4603
4604multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4605 RegisterClass dstRC, RegisterClass srcRC,
4606 RegisterClass KRC, X86MemOperand x86memop> {
4607 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4608 (ins srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4609 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4610 []>, EVEX;
4611
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4612 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4613 (ins KRC:$mask, srcRC:$src),
4614 !strconcat(OpcodeStr,
4615 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4616 []>, EVEX, EVEX_K;
4617
4618 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4619 (ins KRC:$mask, srcRC:$src),
4620 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4621 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4622 []>, EVEX, EVEX_KZ;
4623
4624 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4625 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4626 []>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4627
4628 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4629 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4630 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4631 []>, EVEX, EVEX_K;
4632
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4633}
4634defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4635 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4636defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4637 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4638defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4639 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4640defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4641 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4642defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4643 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4644defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4645 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4646defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4647 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4648defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4649 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4650defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4651 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4652defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4653 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4654defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4655 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4656defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4657 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4658defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4659 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4660defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4661 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4662defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4663 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4664
4665def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4666def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4667def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4668def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4669def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4670
4671def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4672 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4673def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4674 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4675def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4676 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4677def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4678 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4679
4680
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4681multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4682 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4683 PatFrag mem_frag, X86MemOperand x86memop,
4684 ValueType OpVT, ValueType InVT> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4685
4686 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4687 (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4688 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4689 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4690
4691 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4692 (ins KRC:$mask, SrcRC:$src),
4693 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4694 []>, EVEX, EVEX_K;
4695
4696 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4697 (ins KRC:$mask, SrcRC:$src),
4698 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4699 []>, EVEX, EVEX_KZ;
4700
4701 let mayLoad = 1 in {
4702 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4703 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4704 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4705 [(set DstRC:$dst,
4706 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4707 EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4708
4709 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4710 (ins KRC:$mask, x86memop:$src),
4711 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4712 []>,
4713 EVEX, EVEX_K;
4714
4715 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4716 (ins KRC:$mask, x86memop:$src),
4717 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4718 []>,
4719 EVEX, EVEX_KZ;
4720 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4721}
4722
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4723defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4724 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4725 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4726defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4727 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4728 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4729defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4730 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4731 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4732defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4733 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4734 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4735defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4736 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4737 EVEX_CD8<32, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4738
4739defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4740 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4741 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4742defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4743 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4744 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4745defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4746 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4747 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4748defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4749 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4750 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4751defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4752 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4753 EVEX_CD8<32, CD8VH>;
4754
4755//===----------------------------------------------------------------------===//
4756// GATHER - SCATTER Operations
4757
4758multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4759 RegisterClass RC, X86MemOperand memop> {
4760let mayLoad = 1,
4761 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4762 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4763 (ins RC:$src1, KRC:$mask, memop:$src2),
4764 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4765 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4766 []>, EVEX, EVEX_K;
4767}
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4768
4769let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4770defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4771 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4772defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4773 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4774}
4775
4776let ExeDomain = SSEPackedSingle in {
4777defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4778 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4779defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4780 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4781}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4782
4783defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4784 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4785defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4786 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4787
4788defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4789 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4790defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4791 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4792
4793multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4794 RegisterClass RC, X86MemOperand memop> {
4795let mayStore = 1, Constraints = "$mask = $mask_wb" in
4796 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4797 (ins memop:$dst, KRC:$mask, RC:$src2),
4798 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4799 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4800 []>, EVEX, EVEX_K;
4801}
4802
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4803let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4804defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4805 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4806defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4807 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4808}
4809
4810let ExeDomain = SSEPackedSingle in {
4811defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4812 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4813defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4814 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4815}
4816
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4817defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4818 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4819defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4820 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4821
4822defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4823 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4824defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4825 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4826
Elena Demikhovsky8e8fde82014-05-12 07:18:51 +0000[diff] [blame]4827// prefetch
4828multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4829 RegisterClass KRC, X86MemOperand memop> {
4830 let Predicates = [HasPFI], hasSideEffects = 1 in
4831 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4832 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4833 []>, EVEX, EVEX_K;
4834}
4835
4836defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4837 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4838
4839defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4840 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4841
4842defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4843 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4844
4845defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4846 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4847
4848defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4849 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4850
4851defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4852 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4853
4854defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4855 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4856
4857defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4858 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4859
4860defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4861 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4862
4863defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4864 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4865
4866defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4867 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4868
4869defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4870 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4871
4872defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4873 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4874
4875defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4876 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4877
4878defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4879 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4880
4881defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4882 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4883//===----------------------------------------------------------------------===//
4884// VSHUFPS - VSHUFPD Operations
4885
4886multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4887 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4888 Domain d> {
4889 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4890 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4891 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4892 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4893 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4894 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4895 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4896 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4897 (ins RC:$src1, RC:$src2, i8imm:$src3),
4898 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4899 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4900 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4901 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4902 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4903}
4904
4905defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4906 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4907defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4908 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4909
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]4910def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4911 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4912def : Pat<(v16i32 (X86Shufp VR512:$src1,
4913 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4914 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4915
4916def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4917 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4918def : Pat<(v8i64 (X86Shufp VR512:$src1,
4919 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4920 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4921
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4922multiclass avx512_valign<X86VectorVTInfo _> {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]4923 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4924 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4925 "valign"##_.Suffix,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4926 "$src3, $src2, $src1", "$src1, $src2, $src3",
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4927 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]4928 (i8 imm:$src3)))>,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4929 AVX512AIi8Base, EVEX_4V;
Adam Nemetfd2161b2014-08-05 17:23:04 +0000[diff] [blame]4930
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4931 // Also match valign of packed floats.
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4932 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4933 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4934
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4935 let mayLoad = 1 in
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4936 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4937 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4938 !strconcat("valign"##_.Suffix,
Adam Nemet1c752d82014-08-05 17:22:47 +0000[diff] [blame]4939 " \t{$src3, $src2, $src1, $dst|"
4940 "$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4941 []>, EVEX_4V;
4942}
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4943defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4944defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4945
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4946// Helper fragments to match sext vXi1 to vXiY.
4947def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4948def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4949
4950multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4951 RegisterClass KRC, RegisterClass RC,
4952 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4953 string BrdcstStr> {
4954 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4955 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4956 []>, EVEX;
4957 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4958 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4959 []>, EVEX, EVEX_K;
4960 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4961 !strconcat(OpcodeStr,
4962 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4963 []>, EVEX, EVEX_KZ;
4964 let mayLoad = 1 in {
4965 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4966 (ins x86memop:$src),
4967 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4968 []>, EVEX;
4969 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4970 (ins KRC:$mask, x86memop:$src),
4971 !strconcat(OpcodeStr,
4972 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4973 []>, EVEX, EVEX_K;
4974 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4975 (ins KRC:$mask, x86memop:$src),
4976 !strconcat(OpcodeStr,
4977 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4978 []>, EVEX, EVEX_KZ;
4979 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4980 (ins x86scalar_mop:$src),
4981 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4982 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4983 []>, EVEX, EVEX_B;
4984 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4985 (ins KRC:$mask, x86scalar_mop:$src),
4986 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4987 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4988 []>, EVEX, EVEX_B, EVEX_K;
4989 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4990 (ins KRC:$mask, x86scalar_mop:$src),
4991 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4992 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4993 BrdcstStr, "}"),
4994 []>, EVEX, EVEX_B, EVEX_KZ;
4995 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4996}
4997
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4998defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4999 i512mem, i32mem, "{1to16}">, EVEX_V512,
5000 EVEX_CD8<32, CD8VF>;
5001defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
5002 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
5003 EVEX_CD8<64, CD8VF>;
5004
5005def : Pat<(xor
5006 (bc_v16i32 (v16i1sextv16i32)),
5007 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
5008 (VPABSDZrr VR512:$src)>;
5009def : Pat<(xor
5010 (bc_v8i64 (v8i1sextv8i64)),
5011 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
5012 (VPABSQZrr VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]5013
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]5014def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
5015 (v16i32 immAllZerosV), (i16 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]5016 (VPABSDZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]5017def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
5018 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]5019 (VPABSQZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]5020
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5021multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5022 RegisterClass RC, RegisterClass KRC,
5023 X86MemOperand x86memop,
5024 X86MemOperand x86scalar_mop, string BrdcstStr> {
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5025 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5026 (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5027 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5028 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5029 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5030 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5031 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5032 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5033 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5034 (ins x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5035 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5036 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
5037 []>, EVEX, EVEX_B;
5038 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5039 (ins KRC:$mask, RC:$src),
5040 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5041 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5042 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5043 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5044 (ins KRC:$mask, x86memop:$src),
5045 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5046 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5047 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5048 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5049 (ins KRC:$mask, x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5050 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5051 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
5052 BrdcstStr, "}"),
5053 []>, EVEX, EVEX_KZ, EVEX_B;
5054
5055 let Constraints = "$src1 = $dst" in {
5056 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
5057 (ins RC:$src1, KRC:$mask, RC:$src2),
5058 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5059 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5060 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5061 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5062 (ins RC:$src1, KRC:$mask, x86memop:$src2),
5063 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5064 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5065 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5066 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
5067 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]5068 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5069 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
5070 []>, EVEX, EVEX_K, EVEX_B;
5071 }
5072}
5073
5074let Predicates = [HasCDI] in {
5075defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5076 i512mem, i32mem, "{1to16}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5077 EVEX_V512, EVEX_CD8<32, CD8VF>;
5078
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5079
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5080defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5081 i512mem, i64mem, "{1to8}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5082 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5083
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]5084}
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]5085
5086def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
5087 GR16:$mask),
5088 (VPCONFLICTDrrk VR512:$src1,
5089 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5090
5091def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
5092 GR8:$mask),
5093 (VPCONFLICTQrrk VR512:$src1,
5094 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]5095
Cameron McInally5d1b7b92014-06-11 12:54:45 +0000[diff] [blame]5096let Predicates = [HasCDI] in {
5097defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5098 i512mem, i32mem, "{1to16}">,
5099 EVEX_V512, EVEX_CD8<32, CD8VF>;
5100
5101
5102defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5103 i512mem, i64mem, "{1to8}">,
5104 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5105
5106}
5107
5108def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5109 GR16:$mask),
5110 (VPLZCNTDrrk VR512:$src1,
5111 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5112
5113def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5114 GR8:$mask),
5115 (VPLZCNTQrrk VR512:$src1,
5116 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5117
Cameron McInally0d0489c2014-06-16 14:12:28 +0000[diff] [blame]5118def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5119 (VPLZCNTDrm addr:$src)>;
5120def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5121 (VPLZCNTDrr VR512:$src)>;
5122def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5123 (VPLZCNTQrm addr:$src)>;
5124def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5125 (VPLZCNTQrr VR512:$src)>;
5126
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]5127def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5128def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5129def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
Elena Demikhovskyacc5c9e2014-04-22 14:13:10 +0000[diff] [blame]5130
5131def : Pat<(store VK1:$src, addr:$dst),
5132 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5133
5134def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5135 (truncstore node:$val, node:$ptr), [{
5136 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5137}]>;
5138
5139def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5140 (MOV8mr addr:$dst, GR8:$src)>;
5141
Elena Demikhovsky44bf0632014-10-05 14:11:08 +0000[diff] [blame]5142multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5143def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5144 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
5145 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5146}
5147
5148multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5149 string OpcodeStr, Predicate prd> {
5150let Predicates = [prd] in
5151 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5152
5153 let Predicates = [prd, HasVLX] in {
5154 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5155 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5156 }
5157}
5158
5159multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5160 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5161 HasBWI>;
5162 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5163 HasBWI>, VEX_W;
5164 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5165 HasDQI>;
5166 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5167 HasDQI>, VEX_W;
5168}
5169
5170defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;