blob: a90d31c786437b246890298a8b14f2ace9dec302 [file] [log] [blame]
Ben Gamari20172632009-02-17 20:08:50 -05001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 *
27 */
28
29#include <linux/seq_file.h>
Damien Lespiaub2c88f52013-10-15 18:55:29 +010030#include <linux/circ_buf.h>
Daniel Vetter926321d2013-10-16 13:30:34 +020031#include <linux/ctype.h>
Chris Wilsonf3cd4742009-10-13 22:20:20 +010032#include <linux/debugfs.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090033#include <linux/slab.h>
Paul Gortmaker2d1a8a42011-08-30 18:16:33 -040034#include <linux/export.h>
Chris Wilson6d2b8882013-08-07 18:30:54 +010035#include <linux/list_sort.h>
Jesse Barnesec013e72013-08-20 10:29:23 +010036#include <asm/msr-index.h>
David Howells760285e2012-10-02 18:01:07 +010037#include <drm/drmP.h>
Simon Farnsworth4e5359c2010-09-01 17:47:52 +010038#include "intel_drv.h"
Chris Wilsone5c65262010-11-01 11:35:28 +000039#include "intel_ringbuffer.h"
David Howells760285e2012-10-02 18:01:07 +010040#include <drm/i915_drm.h>
Ben Gamari20172632009-02-17 20:08:50 -050041#include "i915_drv.h"
42
Chris Wilsonf13d3f72010-09-20 17:36:15 +010043enum {
Chris Wilson69dc4982010-10-19 10:36:51 +010044 ACTIVE_LIST,
Chris Wilsonf13d3f72010-09-20 17:36:15 +010045 INACTIVE_LIST,
Chris Wilsond21d5972010-09-26 11:19:33 +010046 PINNED_LIST,
Chris Wilsonf13d3f72010-09-20 17:36:15 +010047};
Ben Gamari433e12f2009-02-17 20:08:51 -050048
Chris Wilson70d39fe2010-08-25 16:03:34 +010049static const char *yesno(int v)
50{
51 return v ? "yes" : "no";
52}
53
Damien Lespiau497666d2013-10-15 18:55:39 +010054/* As the drm_debugfs_init() routines are called before dev->dev_private is
55 * allocated we need to hook into the minor for release. */
56static int
57drm_add_fake_info_node(struct drm_minor *minor,
58 struct dentry *ent,
59 const void *key)
60{
61 struct drm_info_node *node;
62
63 node = kmalloc(sizeof(*node), GFP_KERNEL);
64 if (node == NULL) {
65 debugfs_remove(ent);
66 return -ENOMEM;
67 }
68
69 node->minor = minor;
70 node->dent = ent;
71 node->info_ent = (void *) key;
72
73 mutex_lock(&minor->debugfs_lock);
74 list_add(&node->list, &minor->debugfs_list);
75 mutex_unlock(&minor->debugfs_lock);
76
77 return 0;
78}
79
Chris Wilson70d39fe2010-08-25 16:03:34 +010080static int i915_capabilities(struct seq_file *m, void *data)
81{
82 struct drm_info_node *node = (struct drm_info_node *) m->private;
83 struct drm_device *dev = node->minor->dev;
84 const struct intel_device_info *info = INTEL_INFO(dev);
85
86 seq_printf(m, "gen: %d\n", info->gen);
Paulo Zanoni03d00ac2011-10-14 18:17:41 -030087 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
Damien Lespiau79fc46d2013-04-23 16:37:17 +010088#define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
89#define SEP_SEMICOLON ;
90 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
91#undef PRINT_FLAG
92#undef SEP_SEMICOLON
Chris Wilson70d39fe2010-08-25 16:03:34 +010093
94 return 0;
95}
Ben Gamari433e12f2009-02-17 20:08:51 -050096
Chris Wilson05394f32010-11-08 19:18:58 +000097static const char *get_pin_flag(struct drm_i915_gem_object *obj)
Chris Wilsona6172a82009-02-11 14:26:38 +000098{
Chris Wilson05394f32010-11-08 19:18:58 +000099 if (obj->user_pin_count > 0)
Chris Wilsona6172a82009-02-11 14:26:38 +0000100 return "P";
Ben Widawskyd7f46fc2013-12-06 14:10:55 -0800101 else if (i915_gem_obj_is_pinned(obj))
Chris Wilsona6172a82009-02-11 14:26:38 +0000102 return "p";
103 else
104 return " ";
105}
106
Chris Wilson05394f32010-11-08 19:18:58 +0000107static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
Chris Wilsona6172a82009-02-11 14:26:38 +0000108{
Akshay Joshi0206e352011-08-16 15:34:10 -0400109 switch (obj->tiling_mode) {
110 default:
111 case I915_TILING_NONE: return " ";
112 case I915_TILING_X: return "X";
113 case I915_TILING_Y: return "Y";
114 }
Chris Wilsona6172a82009-02-11 14:26:38 +0000115}
116
Ben Widawsky1d693bc2013-07-31 17:00:00 -0700117static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
118{
119 return obj->has_global_gtt_mapping ? "g" : " ";
120}
121
Chris Wilson37811fc2010-08-25 22:45:57 +0100122static void
123describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
124{
Ben Widawsky1d693bc2013-07-31 17:00:00 -0700125 struct i915_vma *vma;
Ben Widawskyd7f46fc2013-12-06 14:10:55 -0800126 int pin_count = 0;
127
Ville Syrjäläfb1ae912013-08-22 19:21:30 +0300128 seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
Chris Wilson37811fc2010-08-25 22:45:57 +0100129 &obj->base,
130 get_pin_flag(obj),
131 get_tiling_flag(obj),
Ben Widawsky1d693bc2013-07-31 17:00:00 -0700132 get_global_flag(obj),
Eric Anholta05a5862011-12-20 08:54:15 -0800133 obj->base.size / 1024,
Chris Wilson37811fc2010-08-25 22:45:57 +0100134 obj->base.read_domains,
135 obj->base.write_domain,
Chris Wilson0201f1e2012-07-20 12:41:01 +0100136 obj->last_read_seqno,
137 obj->last_write_seqno,
Chris Wilsoncaea7472010-11-12 13:53:37 +0000138 obj->last_fenced_seqno,
Mika Kuoppala84734a02013-07-12 16:50:57 +0300139 i915_cache_level_str(obj->cache_level),
Chris Wilson37811fc2010-08-25 22:45:57 +0100140 obj->dirty ? " dirty" : "",
141 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
142 if (obj->base.name)
143 seq_printf(m, " (name: %d)", obj->base.name);
Ben Widawskyd7f46fc2013-12-06 14:10:55 -0800144 list_for_each_entry(vma, &obj->vma_list, vma_link)
145 if (vma->pin_count > 0)
146 pin_count++;
147 seq_printf(m, " (pinned x %d)", pin_count);
Chris Wilsoncc98b412013-08-09 12:25:09 +0100148 if (obj->pin_display)
149 seq_printf(m, " (display)");
Chris Wilson37811fc2010-08-25 22:45:57 +0100150 if (obj->fence_reg != I915_FENCE_REG_NONE)
151 seq_printf(m, " (fence: %d)", obj->fence_reg);
Ben Widawsky1d693bc2013-07-31 17:00:00 -0700152 list_for_each_entry(vma, &obj->vma_list, vma_link) {
153 if (!i915_is_ggtt(vma->vm))
154 seq_puts(m, " (pp");
155 else
156 seq_puts(m, " (g");
157 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
158 vma->node.start, vma->node.size);
159 }
Chris Wilsonc1ad11f2012-11-15 11:32:21 +0000160 if (obj->stolen)
161 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
Chris Wilson6299f992010-11-24 12:23:44 +0000162 if (obj->pin_mappable || obj->fault_mappable) {
163 char s[3], *t = s;
164 if (obj->pin_mappable)
165 *t++ = 'p';
166 if (obj->fault_mappable)
167 *t++ = 'f';
168 *t = '\0';
169 seq_printf(m, " (%s mappable)", s);
170 }
Chris Wilson69dc4982010-10-19 10:36:51 +0100171 if (obj->ring != NULL)
172 seq_printf(m, " (%s)", obj->ring->name);
Chris Wilson37811fc2010-08-25 22:45:57 +0100173}
174
Ben Widawsky3ccfd192013-09-18 19:03:18 -0700175static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
176{
177 seq_putc(m, ctx->is_initialized ? 'I' : 'i');
178 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
179 seq_putc(m, ' ');
180}
181
Ben Gamari433e12f2009-02-17 20:08:51 -0500182static int i915_gem_object_list_info(struct seq_file *m, void *data)
Ben Gamari20172632009-02-17 20:08:50 -0500183{
184 struct drm_info_node *node = (struct drm_info_node *) m->private;
Ben Gamari433e12f2009-02-17 20:08:51 -0500185 uintptr_t list = (uintptr_t) node->info_ent->data;
186 struct list_head *head;
Ben Gamari20172632009-02-17 20:08:50 -0500187 struct drm_device *dev = node->minor->dev;
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700188 struct drm_i915_private *dev_priv = dev->dev_private;
189 struct i915_address_space *vm = &dev_priv->gtt.base;
Ben Widawskyca191b12013-07-31 17:00:14 -0700190 struct i915_vma *vma;
Chris Wilson8f2480f2010-09-26 11:44:19 +0100191 size_t total_obj_size, total_gtt_size;
192 int count, ret;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100193
194 ret = mutex_lock_interruptible(&dev->struct_mutex);
195 if (ret)
196 return ret;
Ben Gamari20172632009-02-17 20:08:50 -0500197
Ben Widawskyca191b12013-07-31 17:00:14 -0700198 /* FIXME: the user of this interface might want more than just GGTT */
Ben Gamari433e12f2009-02-17 20:08:51 -0500199 switch (list) {
200 case ACTIVE_LIST:
Damien Lespiau267f0c92013-06-24 22:59:48 +0100201 seq_puts(m, "Active:\n");
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700202 head = &vm->active_list;
Ben Gamari433e12f2009-02-17 20:08:51 -0500203 break;
204 case INACTIVE_LIST:
Damien Lespiau267f0c92013-06-24 22:59:48 +0100205 seq_puts(m, "Inactive:\n");
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700206 head = &vm->inactive_list;
Ben Gamari433e12f2009-02-17 20:08:51 -0500207 break;
Ben Gamari433e12f2009-02-17 20:08:51 -0500208 default:
Chris Wilsonde227ef2010-07-03 07:58:38 +0100209 mutex_unlock(&dev->struct_mutex);
210 return -EINVAL;
Ben Gamari433e12f2009-02-17 20:08:51 -0500211 }
212
Chris Wilson8f2480f2010-09-26 11:44:19 +0100213 total_obj_size = total_gtt_size = count = 0;
Ben Widawskyca191b12013-07-31 17:00:14 -0700214 list_for_each_entry(vma, head, mm_list) {
215 seq_printf(m, " ");
216 describe_obj(m, vma->obj);
217 seq_printf(m, "\n");
218 total_obj_size += vma->obj->base.size;
219 total_gtt_size += vma->node.size;
Chris Wilson8f2480f2010-09-26 11:44:19 +0100220 count++;
Ben Gamari20172632009-02-17 20:08:50 -0500221 }
Chris Wilsonde227ef2010-07-03 07:58:38 +0100222 mutex_unlock(&dev->struct_mutex);
Carl Worth5e118f42009-03-20 11:54:25 -0700223
Chris Wilson8f2480f2010-09-26 11:44:19 +0100224 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
225 count, total_obj_size, total_gtt_size);
Ben Gamari20172632009-02-17 20:08:50 -0500226 return 0;
227}
228
Chris Wilson6d2b8882013-08-07 18:30:54 +0100229static int obj_rank_by_stolen(void *priv,
230 struct list_head *A, struct list_head *B)
231{
232 struct drm_i915_gem_object *a =
Ben Widawskyb25cb2f2013-08-14 11:38:33 +0200233 container_of(A, struct drm_i915_gem_object, obj_exec_link);
Chris Wilson6d2b8882013-08-07 18:30:54 +0100234 struct drm_i915_gem_object *b =
Ben Widawskyb25cb2f2013-08-14 11:38:33 +0200235 container_of(B, struct drm_i915_gem_object, obj_exec_link);
Chris Wilson6d2b8882013-08-07 18:30:54 +0100236
237 return a->stolen->start - b->stolen->start;
238}
239
240static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
241{
242 struct drm_info_node *node = (struct drm_info_node *) m->private;
243 struct drm_device *dev = node->minor->dev;
244 struct drm_i915_private *dev_priv = dev->dev_private;
245 struct drm_i915_gem_object *obj;
246 size_t total_obj_size, total_gtt_size;
247 LIST_HEAD(stolen);
248 int count, ret;
249
250 ret = mutex_lock_interruptible(&dev->struct_mutex);
251 if (ret)
252 return ret;
253
254 total_obj_size = total_gtt_size = count = 0;
255 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
256 if (obj->stolen == NULL)
257 continue;
258
Ben Widawskyb25cb2f2013-08-14 11:38:33 +0200259 list_add(&obj->obj_exec_link, &stolen);
Chris Wilson6d2b8882013-08-07 18:30:54 +0100260
261 total_obj_size += obj->base.size;
262 total_gtt_size += i915_gem_obj_ggtt_size(obj);
263 count++;
264 }
265 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
266 if (obj->stolen == NULL)
267 continue;
268
Ben Widawskyb25cb2f2013-08-14 11:38:33 +0200269 list_add(&obj->obj_exec_link, &stolen);
Chris Wilson6d2b8882013-08-07 18:30:54 +0100270
271 total_obj_size += obj->base.size;
272 count++;
273 }
274 list_sort(NULL, &stolen, obj_rank_by_stolen);
275 seq_puts(m, "Stolen:\n");
276 while (!list_empty(&stolen)) {
Ben Widawskyb25cb2f2013-08-14 11:38:33 +0200277 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
Chris Wilson6d2b8882013-08-07 18:30:54 +0100278 seq_puts(m, " ");
279 describe_obj(m, obj);
280 seq_putc(m, '\n');
Ben Widawskyb25cb2f2013-08-14 11:38:33 +0200281 list_del_init(&obj->obj_exec_link);
Chris Wilson6d2b8882013-08-07 18:30:54 +0100282 }
283 mutex_unlock(&dev->struct_mutex);
284
285 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
286 count, total_obj_size, total_gtt_size);
287 return 0;
288}
289
Chris Wilson6299f992010-11-24 12:23:44 +0000290#define count_objects(list, member) do { \
291 list_for_each_entry(obj, list, member) { \
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700292 size += i915_gem_obj_ggtt_size(obj); \
Chris Wilson6299f992010-11-24 12:23:44 +0000293 ++count; \
294 if (obj->map_and_fenceable) { \
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700295 mappable_size += i915_gem_obj_ggtt_size(obj); \
Chris Wilson6299f992010-11-24 12:23:44 +0000296 ++mappable_count; \
297 } \
298 } \
Akshay Joshi0206e352011-08-16 15:34:10 -0400299} while (0)
Chris Wilson6299f992010-11-24 12:23:44 +0000300
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100301struct file_stats {
302 int count;
303 size_t total, active, inactive, unbound;
304};
305
306static int per_file_stats(int id, void *ptr, void *data)
307{
308 struct drm_i915_gem_object *obj = ptr;
309 struct file_stats *stats = data;
310
311 stats->count++;
312 stats->total += obj->base.size;
313
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700314 if (i915_gem_obj_ggtt_bound(obj)) {
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100315 if (!list_empty(&obj->ring_list))
316 stats->active += obj->base.size;
317 else
318 stats->inactive += obj->base.size;
319 } else {
320 if (!list_empty(&obj->global_list))
321 stats->unbound += obj->base.size;
322 }
323
324 return 0;
325}
326
Ben Widawskyca191b12013-07-31 17:00:14 -0700327#define count_vmas(list, member) do { \
328 list_for_each_entry(vma, list, member) { \
329 size += i915_gem_obj_ggtt_size(vma->obj); \
330 ++count; \
331 if (vma->obj->map_and_fenceable) { \
332 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
333 ++mappable_count; \
334 } \
335 } \
336} while (0)
337
338static int i915_gem_object_info(struct seq_file *m, void* data)
Chris Wilson73aa8082010-09-30 11:46:12 +0100339{
340 struct drm_info_node *node = (struct drm_info_node *) m->private;
341 struct drm_device *dev = node->minor->dev;
342 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonb7abb712012-08-20 11:33:30 +0200343 u32 count, mappable_count, purgeable_count;
344 size_t size, mappable_size, purgeable_size;
Chris Wilson6299f992010-11-24 12:23:44 +0000345 struct drm_i915_gem_object *obj;
Ben Widawsky5cef07e2013-07-16 16:50:08 -0700346 struct i915_address_space *vm = &dev_priv->gtt.base;
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100347 struct drm_file *file;
Ben Widawskyca191b12013-07-31 17:00:14 -0700348 struct i915_vma *vma;
Chris Wilson73aa8082010-09-30 11:46:12 +0100349 int ret;
350
351 ret = mutex_lock_interruptible(&dev->struct_mutex);
352 if (ret)
353 return ret;
354
Chris Wilson6299f992010-11-24 12:23:44 +0000355 seq_printf(m, "%u objects, %zu bytes\n",
356 dev_priv->mm.object_count,
357 dev_priv->mm.object_memory);
358
359 size = count = mappable_size = mappable_count = 0;
Ben Widawsky35c20a62013-05-31 11:28:48 -0700360 count_objects(&dev_priv->mm.bound_list, global_list);
Chris Wilson6299f992010-11-24 12:23:44 +0000361 seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
362 count, mappable_count, size, mappable_size);
363
364 size = count = mappable_size = mappable_count = 0;
Ben Widawskyca191b12013-07-31 17:00:14 -0700365 count_vmas(&vm->active_list, mm_list);
Chris Wilson6299f992010-11-24 12:23:44 +0000366 seq_printf(m, " %u [%u] active objects, %zu [%zu] bytes\n",
367 count, mappable_count, size, mappable_size);
368
369 size = count = mappable_size = mappable_count = 0;
Ben Widawskyca191b12013-07-31 17:00:14 -0700370 count_vmas(&vm->inactive_list, mm_list);
Chris Wilson6299f992010-11-24 12:23:44 +0000371 seq_printf(m, " %u [%u] inactive objects, %zu [%zu] bytes\n",
372 count, mappable_count, size, mappable_size);
373
Chris Wilsonb7abb712012-08-20 11:33:30 +0200374 size = count = purgeable_size = purgeable_count = 0;
Ben Widawsky35c20a62013-05-31 11:28:48 -0700375 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
Chris Wilson6c085a72012-08-20 11:40:46 +0200376 size += obj->base.size, ++count;
Chris Wilsonb7abb712012-08-20 11:33:30 +0200377 if (obj->madv == I915_MADV_DONTNEED)
378 purgeable_size += obj->base.size, ++purgeable_count;
379 }
Chris Wilson6c085a72012-08-20 11:40:46 +0200380 seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
381
Chris Wilson6299f992010-11-24 12:23:44 +0000382 size = count = mappable_size = mappable_count = 0;
Ben Widawsky35c20a62013-05-31 11:28:48 -0700383 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
Chris Wilson6299f992010-11-24 12:23:44 +0000384 if (obj->fault_mappable) {
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700385 size += i915_gem_obj_ggtt_size(obj);
Chris Wilson6299f992010-11-24 12:23:44 +0000386 ++count;
387 }
388 if (obj->pin_mappable) {
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700389 mappable_size += i915_gem_obj_ggtt_size(obj);
Chris Wilson6299f992010-11-24 12:23:44 +0000390 ++mappable_count;
391 }
Chris Wilsonb7abb712012-08-20 11:33:30 +0200392 if (obj->madv == I915_MADV_DONTNEED) {
393 purgeable_size += obj->base.size;
394 ++purgeable_count;
395 }
Chris Wilson6299f992010-11-24 12:23:44 +0000396 }
Chris Wilsonb7abb712012-08-20 11:33:30 +0200397 seq_printf(m, "%u purgeable objects, %zu bytes\n",
398 purgeable_count, purgeable_size);
Chris Wilson6299f992010-11-24 12:23:44 +0000399 seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
400 mappable_count, mappable_size);
401 seq_printf(m, "%u fault mappable objects, %zu bytes\n",
402 count, size);
403
Ben Widawsky93d18792013-01-17 12:45:17 -0800404 seq_printf(m, "%zu [%lu] gtt total\n",
Ben Widawsky853ba5d2013-07-16 16:50:05 -0700405 dev_priv->gtt.base.total,
406 dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
Chris Wilson73aa8082010-09-30 11:46:12 +0100407
Damien Lespiau267f0c92013-06-24 22:59:48 +0100408 seq_putc(m, '\n');
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100409 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
410 struct file_stats stats;
Tetsuo Handa3ec2f422014-01-03 20:42:18 +0900411 struct task_struct *task;
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100412
413 memset(&stats, 0, sizeof(stats));
414 idr_for_each(&file->object_idr, per_file_stats, &stats);
Tetsuo Handa3ec2f422014-01-03 20:42:18 +0900415 /*
416 * Although we have a valid reference on file->pid, that does
417 * not guarantee that the task_struct who called get_pid() is
418 * still alive (e.g. get_pid(current) => fork() => exit()).
419 * Therefore, we need to protect this ->comm access using RCU.
420 */
421 rcu_read_lock();
422 task = pid_task(file->pid, PIDTYPE_PID);
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100423 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
Tetsuo Handa3ec2f422014-01-03 20:42:18 +0900424 task ? task->comm : "<unknown>",
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100425 stats.count,
426 stats.total,
427 stats.active,
428 stats.inactive,
429 stats.unbound);
Tetsuo Handa3ec2f422014-01-03 20:42:18 +0900430 rcu_read_unlock();
Chris Wilson2db8e9d2013-06-04 23:49:08 +0100431 }
432
Chris Wilson73aa8082010-09-30 11:46:12 +0100433 mutex_unlock(&dev->struct_mutex);
434
435 return 0;
436}
437
Damien Lespiauaee56cf2013-06-24 22:59:49 +0100438static int i915_gem_gtt_info(struct seq_file *m, void *data)
Chris Wilson08c18322011-01-10 00:00:24 +0000439{
440 struct drm_info_node *node = (struct drm_info_node *) m->private;
441 struct drm_device *dev = node->minor->dev;
Chris Wilson1b502472012-04-24 15:47:30 +0100442 uintptr_t list = (uintptr_t) node->info_ent->data;
Chris Wilson08c18322011-01-10 00:00:24 +0000443 struct drm_i915_private *dev_priv = dev->dev_private;
444 struct drm_i915_gem_object *obj;
445 size_t total_obj_size, total_gtt_size;
446 int count, ret;
447
448 ret = mutex_lock_interruptible(&dev->struct_mutex);
449 if (ret)
450 return ret;
451
452 total_obj_size = total_gtt_size = count = 0;
Ben Widawsky35c20a62013-05-31 11:28:48 -0700453 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
Ben Widawskyd7f46fc2013-12-06 14:10:55 -0800454 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
Chris Wilson1b502472012-04-24 15:47:30 +0100455 continue;
456
Damien Lespiau267f0c92013-06-24 22:59:48 +0100457 seq_puts(m, " ");
Chris Wilson08c18322011-01-10 00:00:24 +0000458 describe_obj(m, obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +0100459 seq_putc(m, '\n');
Chris Wilson08c18322011-01-10 00:00:24 +0000460 total_obj_size += obj->base.size;
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700461 total_gtt_size += i915_gem_obj_ggtt_size(obj);
Chris Wilson08c18322011-01-10 00:00:24 +0000462 count++;
463 }
464
465 mutex_unlock(&dev->struct_mutex);
466
467 seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
468 count, total_obj_size, total_gtt_size);
469
470 return 0;
471}
472
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100473static int i915_gem_pageflip_info(struct seq_file *m, void *data)
474{
475 struct drm_info_node *node = (struct drm_info_node *) m->private;
476 struct drm_device *dev = node->minor->dev;
477 unsigned long flags;
478 struct intel_crtc *crtc;
479
480 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800481 const char pipe = pipe_name(crtc->pipe);
482 const char plane = plane_name(crtc->plane);
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100483 struct intel_unpin_work *work;
484
485 spin_lock_irqsave(&dev->event_lock, flags);
486 work = crtc->unpin_work;
487 if (work == NULL) {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800488 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100489 pipe, plane);
490 } else {
Chris Wilsone7d841c2012-12-03 11:36:30 +0000491 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800492 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100493 pipe, plane);
494 } else {
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800495 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100496 pipe, plane);
497 }
498 if (work->enable_stall_check)
Damien Lespiau267f0c92013-06-24 22:59:48 +0100499 seq_puts(m, "Stall check enabled, ");
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100500 else
Damien Lespiau267f0c92013-06-24 22:59:48 +0100501 seq_puts(m, "Stall check waiting for page flip ioctl, ");
Chris Wilsone7d841c2012-12-03 11:36:30 +0000502 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100503
504 if (work->old_fb_obj) {
Chris Wilson05394f32010-11-08 19:18:58 +0000505 struct drm_i915_gem_object *obj = work->old_fb_obj;
506 if (obj)
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700507 seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
508 i915_gem_obj_ggtt_offset(obj));
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100509 }
510 if (work->pending_flip_obj) {
Chris Wilson05394f32010-11-08 19:18:58 +0000511 struct drm_i915_gem_object *obj = work->pending_flip_obj;
512 if (obj)
Ben Widawskyf343c5f2013-07-05 14:41:04 -0700513 seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
514 i915_gem_obj_ggtt_offset(obj));
Simon Farnsworth4e5359c2010-09-01 17:47:52 +0100515 }
516 }
517 spin_unlock_irqrestore(&dev->event_lock, flags);
518 }
519
520 return 0;
521}
522
Ben Gamari20172632009-02-17 20:08:50 -0500523static int i915_gem_request_info(struct seq_file *m, void *data)
524{
525 struct drm_info_node *node = (struct drm_info_node *) m->private;
526 struct drm_device *dev = node->minor->dev;
527 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100528 struct intel_ring_buffer *ring;
Ben Gamari20172632009-02-17 20:08:50 -0500529 struct drm_i915_gem_request *gem_request;
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100530 int ret, count, i;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100531
532 ret = mutex_lock_interruptible(&dev->struct_mutex);
533 if (ret)
534 return ret;
Ben Gamari20172632009-02-17 20:08:50 -0500535
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100536 count = 0;
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100537 for_each_ring(ring, dev_priv, i) {
538 if (list_empty(&ring->request_list))
539 continue;
540
541 seq_printf(m, "%s requests:\n", ring->name);
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100542 list_for_each_entry(gem_request,
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100543 &ring->request_list,
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100544 list) {
545 seq_printf(m, " %d @ %d\n",
546 gem_request->seqno,
547 (int) (jiffies - gem_request->emitted_jiffies));
548 }
549 count++;
Ben Gamari20172632009-02-17 20:08:50 -0500550 }
Chris Wilsonde227ef2010-07-03 07:58:38 +0100551 mutex_unlock(&dev->struct_mutex);
552
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100553 if (count == 0)
Damien Lespiau267f0c92013-06-24 22:59:48 +0100554 seq_puts(m, "No requests\n");
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100555
Ben Gamari20172632009-02-17 20:08:50 -0500556 return 0;
557}
558
Chris Wilsonb2223492010-10-27 15:27:33 +0100559static void i915_ring_seqno_info(struct seq_file *m,
560 struct intel_ring_buffer *ring)
561{
562 if (ring->get_seqno) {
Mika Kuoppala43a7b922012-12-04 15:12:01 +0200563 seq_printf(m, "Current sequence (%s): %u\n",
Chris Wilsonb2eadbc2012-08-09 10:58:30 +0100564 ring->name, ring->get_seqno(ring, false));
Chris Wilsonb2223492010-10-27 15:27:33 +0100565 }
566}
567
Ben Gamari20172632009-02-17 20:08:50 -0500568static int i915_gem_seqno_info(struct seq_file *m, void *data)
569{
570 struct drm_info_node *node = (struct drm_info_node *) m->private;
571 struct drm_device *dev = node->minor->dev;
572 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100573 struct intel_ring_buffer *ring;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000574 int ret, i;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100575
576 ret = mutex_lock_interruptible(&dev->struct_mutex);
577 if (ret)
578 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -0200579 intel_runtime_pm_get(dev_priv);
Ben Gamari20172632009-02-17 20:08:50 -0500580
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100581 for_each_ring(ring, dev_priv, i)
582 i915_ring_seqno_info(m, ring);
Chris Wilsonde227ef2010-07-03 07:58:38 +0100583
Paulo Zanonic8c8fb32013-11-27 18:21:54 -0200584 intel_runtime_pm_put(dev_priv);
Chris Wilsonde227ef2010-07-03 07:58:38 +0100585 mutex_unlock(&dev->struct_mutex);
586
Ben Gamari20172632009-02-17 20:08:50 -0500587 return 0;
588}
589
590
591static int i915_interrupt_info(struct seq_file *m, void *data)
592{
593 struct drm_info_node *node = (struct drm_info_node *) m->private;
594 struct drm_device *dev = node->minor->dev;
595 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100596 struct intel_ring_buffer *ring;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800597 int ret, i, pipe;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100598
599 ret = mutex_lock_interruptible(&dev->struct_mutex);
600 if (ret)
601 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -0200602 intel_runtime_pm_get(dev_priv);
Ben Gamari20172632009-02-17 20:08:50 -0500603
Ben Widawskya123f152013-11-02 21:07:10 -0700604 if (INTEL_INFO(dev)->gen >= 8) {
Ben Widawskya123f152013-11-02 21:07:10 -0700605 seq_printf(m, "Master Interrupt Control:\t%08x\n",
606 I915_READ(GEN8_MASTER_IRQ));
607
608 for (i = 0; i < 4; i++) {
609 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
610 i, I915_READ(GEN8_GT_IMR(i)));
611 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
612 i, I915_READ(GEN8_GT_IIR(i)));
613 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
614 i, I915_READ(GEN8_GT_IER(i)));
615 }
616
Damien Lespiau07d27e22014-03-03 17:31:46 +0000617 for_each_pipe(pipe) {
Ben Widawskya123f152013-11-02 21:07:10 -0700618 seq_printf(m, "Pipe %c IMR:\t%08x\n",
Damien Lespiau07d27e22014-03-03 17:31:46 +0000619 pipe_name(pipe),
620 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
Ben Widawskya123f152013-11-02 21:07:10 -0700621 seq_printf(m, "Pipe %c IIR:\t%08x\n",
Damien Lespiau07d27e22014-03-03 17:31:46 +0000622 pipe_name(pipe),
623 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
Ben Widawskya123f152013-11-02 21:07:10 -0700624 seq_printf(m, "Pipe %c IER:\t%08x\n",
Damien Lespiau07d27e22014-03-03 17:31:46 +0000625 pipe_name(pipe),
626 I915_READ(GEN8_DE_PIPE_IER(pipe)));
Ben Widawskya123f152013-11-02 21:07:10 -0700627 }
628
629 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
630 I915_READ(GEN8_DE_PORT_IMR));
631 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
632 I915_READ(GEN8_DE_PORT_IIR));
633 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
634 I915_READ(GEN8_DE_PORT_IER));
635
636 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
637 I915_READ(GEN8_DE_MISC_IMR));
638 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
639 I915_READ(GEN8_DE_MISC_IIR));
640 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
641 I915_READ(GEN8_DE_MISC_IER));
642
643 seq_printf(m, "PCU interrupt mask:\t%08x\n",
644 I915_READ(GEN8_PCU_IMR));
645 seq_printf(m, "PCU interrupt identity:\t%08x\n",
646 I915_READ(GEN8_PCU_IIR));
647 seq_printf(m, "PCU interrupt enable:\t%08x\n",
648 I915_READ(GEN8_PCU_IER));
649 } else if (IS_VALLEYVIEW(dev)) {
Jesse Barnes7e231dbe2012-03-28 13:39:38 -0700650 seq_printf(m, "Display IER:\t%08x\n",
651 I915_READ(VLV_IER));
652 seq_printf(m, "Display IIR:\t%08x\n",
653 I915_READ(VLV_IIR));
654 seq_printf(m, "Display IIR_RW:\t%08x\n",
655 I915_READ(VLV_IIR_RW));
656 seq_printf(m, "Display IMR:\t%08x\n",
657 I915_READ(VLV_IMR));
658 for_each_pipe(pipe)
659 seq_printf(m, "Pipe %c stat:\t%08x\n",
660 pipe_name(pipe),
661 I915_READ(PIPESTAT(pipe)));
662
663 seq_printf(m, "Master IER:\t%08x\n",
664 I915_READ(VLV_MASTER_IER));
665
666 seq_printf(m, "Render IER:\t%08x\n",
667 I915_READ(GTIER));
668 seq_printf(m, "Render IIR:\t%08x\n",
669 I915_READ(GTIIR));
670 seq_printf(m, "Render IMR:\t%08x\n",
671 I915_READ(GTIMR));
672
673 seq_printf(m, "PM IER:\t\t%08x\n",
674 I915_READ(GEN6_PMIER));
675 seq_printf(m, "PM IIR:\t\t%08x\n",
676 I915_READ(GEN6_PMIIR));
677 seq_printf(m, "PM IMR:\t\t%08x\n",
678 I915_READ(GEN6_PMIMR));
679
680 seq_printf(m, "Port hotplug:\t%08x\n",
681 I915_READ(PORT_HOTPLUG_EN));
682 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
683 I915_READ(VLV_DPFLIPSTAT));
684 seq_printf(m, "DPINVGTT:\t%08x\n",
685 I915_READ(DPINVGTT));
686
687 } else if (!HAS_PCH_SPLIT(dev)) {
Zhenyu Wang5f6a1692009-08-10 21:37:24 +0800688 seq_printf(m, "Interrupt enable: %08x\n",
689 I915_READ(IER));
690 seq_printf(m, "Interrupt identity: %08x\n",
691 I915_READ(IIR));
692 seq_printf(m, "Interrupt mask: %08x\n",
693 I915_READ(IMR));
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800694 for_each_pipe(pipe)
695 seq_printf(m, "Pipe %c stat: %08x\n",
696 pipe_name(pipe),
697 I915_READ(PIPESTAT(pipe)));
Zhenyu Wang5f6a1692009-08-10 21:37:24 +0800698 } else {
699 seq_printf(m, "North Display Interrupt enable: %08x\n",
700 I915_READ(DEIER));
701 seq_printf(m, "North Display Interrupt identity: %08x\n",
702 I915_READ(DEIIR));
703 seq_printf(m, "North Display Interrupt mask: %08x\n",
704 I915_READ(DEIMR));
705 seq_printf(m, "South Display Interrupt enable: %08x\n",
706 I915_READ(SDEIER));
707 seq_printf(m, "South Display Interrupt identity: %08x\n",
708 I915_READ(SDEIIR));
709 seq_printf(m, "South Display Interrupt mask: %08x\n",
710 I915_READ(SDEIMR));
711 seq_printf(m, "Graphics Interrupt enable: %08x\n",
712 I915_READ(GTIER));
713 seq_printf(m, "Graphics Interrupt identity: %08x\n",
714 I915_READ(GTIIR));
715 seq_printf(m, "Graphics Interrupt mask: %08x\n",
716 I915_READ(GTIMR));
717 }
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100718 for_each_ring(ring, dev_priv, i) {
Ben Widawskya123f152013-11-02 21:07:10 -0700719 if (INTEL_INFO(dev)->gen >= 6) {
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100720 seq_printf(m,
721 "Graphics Interrupt mask (%s): %08x\n",
722 ring->name, I915_READ_IMR(ring));
Chris Wilson9862e602011-01-04 22:22:17 +0000723 }
Chris Wilsona2c7f6f2012-09-01 20:51:22 +0100724 i915_ring_seqno_info(m, ring);
Chris Wilson9862e602011-01-04 22:22:17 +0000725 }
Paulo Zanonic8c8fb32013-11-27 18:21:54 -0200726 intel_runtime_pm_put(dev_priv);
Chris Wilsonde227ef2010-07-03 07:58:38 +0100727 mutex_unlock(&dev->struct_mutex);
728
Ben Gamari20172632009-02-17 20:08:50 -0500729 return 0;
730}
731
Chris Wilsona6172a82009-02-11 14:26:38 +0000732static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
733{
734 struct drm_info_node *node = (struct drm_info_node *) m->private;
735 struct drm_device *dev = node->minor->dev;
736 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonde227ef2010-07-03 07:58:38 +0100737 int i, ret;
738
739 ret = mutex_lock_interruptible(&dev->struct_mutex);
740 if (ret)
741 return ret;
Chris Wilsona6172a82009-02-11 14:26:38 +0000742
743 seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
744 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
745 for (i = 0; i < dev_priv->num_fence_regs; i++) {
Chris Wilson05394f32010-11-08 19:18:58 +0000746 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
Chris Wilsona6172a82009-02-11 14:26:38 +0000747
Chris Wilson6c085a72012-08-20 11:40:46 +0200748 seq_printf(m, "Fence %d, pin count = %d, object = ",
749 i, dev_priv->fence_regs[i].pin_count);
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100750 if (obj == NULL)
Damien Lespiau267f0c92013-06-24 22:59:48 +0100751 seq_puts(m, "unused");
Chris Wilsonc2c347a92010-10-27 15:11:53 +0100752 else
Chris Wilson05394f32010-11-08 19:18:58 +0000753 describe_obj(m, obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +0100754 seq_putc(m, '\n');
Chris Wilsona6172a82009-02-11 14:26:38 +0000755 }
756
Chris Wilson05394f32010-11-08 19:18:58 +0000757 mutex_unlock(&dev->struct_mutex);
Chris Wilsona6172a82009-02-11 14:26:38 +0000758 return 0;
759}
760
Ben Gamari20172632009-02-17 20:08:50 -0500761static int i915_hws_info(struct seq_file *m, void *data)
762{
763 struct drm_info_node *node = (struct drm_info_node *) m->private;
764 struct drm_device *dev = node->minor->dev;
765 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilson4066c0a2010-10-29 21:00:54 +0100766 struct intel_ring_buffer *ring;
Daniel Vetter1a240d42012-11-29 22:18:51 +0100767 const u32 *hws;
Chris Wilson4066c0a2010-10-29 21:00:54 +0100768 int i;
Ben Gamari20172632009-02-17 20:08:50 -0500769
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000770 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
Daniel Vetter1a240d42012-11-29 22:18:51 +0100771 hws = ring->status_page.page_addr;
Ben Gamari20172632009-02-17 20:08:50 -0500772 if (hws == NULL)
773 return 0;
774
775 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
776 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
777 i * 4,
778 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
779 }
780 return 0;
781}
782
Daniel Vetterd5442302012-04-27 15:17:40 +0200783static ssize_t
784i915_error_state_write(struct file *filp,
785 const char __user *ubuf,
786 size_t cnt,
787 loff_t *ppos)
788{
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300789 struct i915_error_state_file_priv *error_priv = filp->private_data;
Daniel Vetterd5442302012-04-27 15:17:40 +0200790 struct drm_device *dev = error_priv->dev;
Daniel Vetter22bcfc62012-08-09 15:07:02 +0200791 int ret;
Daniel Vetterd5442302012-04-27 15:17:40 +0200792
793 DRM_DEBUG_DRIVER("Resetting error state\n");
794
Daniel Vetter22bcfc62012-08-09 15:07:02 +0200795 ret = mutex_lock_interruptible(&dev->struct_mutex);
796 if (ret)
797 return ret;
798
Daniel Vetterd5442302012-04-27 15:17:40 +0200799 i915_destroy_error_state(dev);
800 mutex_unlock(&dev->struct_mutex);
801
802 return cnt;
803}
804
805static int i915_error_state_open(struct inode *inode, struct file *file)
806{
807 struct drm_device *dev = inode->i_private;
Daniel Vetterd5442302012-04-27 15:17:40 +0200808 struct i915_error_state_file_priv *error_priv;
Daniel Vetterd5442302012-04-27 15:17:40 +0200809
810 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
811 if (!error_priv)
812 return -ENOMEM;
813
814 error_priv->dev = dev;
815
Mika Kuoppala95d5bfb2013-06-06 15:18:40 +0300816 i915_error_state_get(dev, error_priv);
Daniel Vetterd5442302012-04-27 15:17:40 +0200817
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300818 file->private_data = error_priv;
819
820 return 0;
Daniel Vetterd5442302012-04-27 15:17:40 +0200821}
822
823static int i915_error_state_release(struct inode *inode, struct file *file)
824{
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300825 struct i915_error_state_file_priv *error_priv = file->private_data;
Daniel Vetterd5442302012-04-27 15:17:40 +0200826
Mika Kuoppala95d5bfb2013-06-06 15:18:40 +0300827 i915_error_state_put(error_priv);
Daniel Vetterd5442302012-04-27 15:17:40 +0200828 kfree(error_priv);
829
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300830 return 0;
831}
832
833static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
834 size_t count, loff_t *pos)
835{
836 struct i915_error_state_file_priv *error_priv = file->private_data;
837 struct drm_i915_error_state_buf error_str;
838 loff_t tmp_pos = 0;
839 ssize_t ret_count = 0;
Mika Kuoppala4dc955f2013-06-06 15:18:41 +0300840 int ret;
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300841
Mika Kuoppala4dc955f2013-06-06 15:18:41 +0300842 ret = i915_error_state_buf_init(&error_str, count, *pos);
843 if (ret)
844 return ret;
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300845
Mika Kuoppalafc16b482013-06-06 15:18:39 +0300846 ret = i915_error_state_to_str(&error_str, error_priv);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300847 if (ret)
848 goto out;
849
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300850 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
851 error_str.buf,
852 error_str.bytes);
853
854 if (ret_count < 0)
855 ret = ret_count;
856 else
857 *pos = error_str.start + ret_count;
858out:
Mika Kuoppala4dc955f2013-06-06 15:18:41 +0300859 i915_error_state_buf_release(&error_str);
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300860 return ret ?: ret_count;
Daniel Vetterd5442302012-04-27 15:17:40 +0200861}
862
863static const struct file_operations i915_error_state_fops = {
864 .owner = THIS_MODULE,
865 .open = i915_error_state_open,
Mika Kuoppalaedc3d882013-05-23 13:55:35 +0300866 .read = i915_error_state_read,
Daniel Vetterd5442302012-04-27 15:17:40 +0200867 .write = i915_error_state_write,
868 .llseek = default_llseek,
869 .release = i915_error_state_release,
870};
871
Kees Cook647416f2013-03-10 14:10:06 -0700872static int
873i915_next_seqno_get(void *data, u64 *val)
Mika Kuoppala40633212012-12-04 15:12:00 +0200874{
Kees Cook647416f2013-03-10 14:10:06 -0700875 struct drm_device *dev = data;
Mika Kuoppala40633212012-12-04 15:12:00 +0200876 drm_i915_private_t *dev_priv = dev->dev_private;
Mika Kuoppala40633212012-12-04 15:12:00 +0200877 int ret;
878
879 ret = mutex_lock_interruptible(&dev->struct_mutex);
880 if (ret)
881 return ret;
882
Kees Cook647416f2013-03-10 14:10:06 -0700883 *val = dev_priv->next_seqno;
Mika Kuoppala40633212012-12-04 15:12:00 +0200884 mutex_unlock(&dev->struct_mutex);
885
Kees Cook647416f2013-03-10 14:10:06 -0700886 return 0;
Mika Kuoppala40633212012-12-04 15:12:00 +0200887}
888
Kees Cook647416f2013-03-10 14:10:06 -0700889static int
890i915_next_seqno_set(void *data, u64 val)
Mika Kuoppala40633212012-12-04 15:12:00 +0200891{
Kees Cook647416f2013-03-10 14:10:06 -0700892 struct drm_device *dev = data;
Mika Kuoppala40633212012-12-04 15:12:00 +0200893 int ret;
894
Mika Kuoppala40633212012-12-04 15:12:00 +0200895 ret = mutex_lock_interruptible(&dev->struct_mutex);
896 if (ret)
897 return ret;
898
Mika Kuoppalae94fbaa2012-12-19 11:13:09 +0200899 ret = i915_gem_set_seqno(dev, val);
Mika Kuoppala40633212012-12-04 15:12:00 +0200900 mutex_unlock(&dev->struct_mutex);
901
Kees Cook647416f2013-03-10 14:10:06 -0700902 return ret;
Mika Kuoppala40633212012-12-04 15:12:00 +0200903}
904
Kees Cook647416f2013-03-10 14:10:06 -0700905DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
906 i915_next_seqno_get, i915_next_seqno_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +0300907 "0x%llx\n");
Mika Kuoppala40633212012-12-04 15:12:00 +0200908
Jesse Barnesf97108d2010-01-29 11:27:07 -0800909static int i915_rstdby_delays(struct seq_file *m, void *unused)
910{
911 struct drm_info_node *node = (struct drm_info_node *) m->private;
912 struct drm_device *dev = node->minor->dev;
913 drm_i915_private_t *dev_priv = dev->dev_private;
Ben Widawsky616fdb52011-10-05 11:44:54 -0700914 u16 crstanddelay;
915 int ret;
916
917 ret = mutex_lock_interruptible(&dev->struct_mutex);
918 if (ret)
919 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -0200920 intel_runtime_pm_get(dev_priv);
Ben Widawsky616fdb52011-10-05 11:44:54 -0700921
922 crstanddelay = I915_READ16(CRSTANDVID);
923
Paulo Zanonic8c8fb32013-11-27 18:21:54 -0200924 intel_runtime_pm_put(dev_priv);
Ben Widawsky616fdb52011-10-05 11:44:54 -0700925 mutex_unlock(&dev->struct_mutex);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800926
927 seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
928
929 return 0;
930}
931
932static int i915_cur_delayinfo(struct seq_file *m, void *unused)
933{
934 struct drm_info_node *node = (struct drm_info_node *) m->private;
935 struct drm_device *dev = node->minor->dev;
936 drm_i915_private_t *dev_priv = dev->dev_private;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -0200937 int ret = 0;
938
939 intel_runtime_pm_get(dev_priv);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800940
Tom O'Rourke5c9669c2013-09-16 14:56:43 -0700941 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
942
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800943 if (IS_GEN5(dev)) {
944 u16 rgvswctl = I915_READ16(MEMSWCTL);
945 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
946
947 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
948 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
949 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
950 MEMSTAT_VID_SHIFT);
951 seq_printf(m, "Current P-state: %d\n",
952 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
Jesse Barnes0a073b82013-04-17 15:54:58 -0700953 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800954 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
955 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
956 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
Chris Wilson8e8c06c2013-08-26 19:51:01 -0300957 u32 rpstat, cagf, reqf;
Jesse Barnesccab5c82011-01-18 15:49:25 -0800958 u32 rpupei, rpcurup, rpprevup;
959 u32 rpdownei, rpcurdown, rpprevdown;
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800960 int max_freq;
961
962 /* RPSTAT1 is in the GT power well */
Ben Widawskyd1ebd8162011-04-25 20:11:50 +0100963 ret = mutex_lock_interruptible(&dev->struct_mutex);
964 if (ret)
Paulo Zanonic8c8fb32013-11-27 18:21:54 -0200965 goto out;
Ben Widawskyd1ebd8162011-04-25 20:11:50 +0100966
Deepak Sc8d9a592013-11-23 14:55:42 +0530967 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800968
Chris Wilson8e8c06c2013-08-26 19:51:01 -0300969 reqf = I915_READ(GEN6_RPNSWREQ);
970 reqf &= ~GEN6_TURBO_DISABLE;
971 if (IS_HASWELL(dev))
972 reqf >>= 24;
973 else
974 reqf >>= 25;
975 reqf *= GT_FREQUENCY_MULTIPLIER;
976
Jesse Barnesccab5c82011-01-18 15:49:25 -0800977 rpstat = I915_READ(GEN6_RPSTAT1);
978 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
979 rpcurup = I915_READ(GEN6_RP_CUR_UP);
980 rpprevup = I915_READ(GEN6_RP_PREV_UP);
981 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
982 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
983 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
Ben Widawskyf82855d2013-01-29 12:00:15 -0800984 if (IS_HASWELL(dev))
985 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
986 else
987 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
988 cagf *= GT_FREQUENCY_MULTIPLIER;
Jesse Barnesccab5c82011-01-18 15:49:25 -0800989
Deepak Sc8d9a592013-11-23 14:55:42 +0530990 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
Ben Widawskyd1ebd8162011-04-25 20:11:50 +0100991 mutex_unlock(&dev->struct_mutex);
992
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800993 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
Jesse Barnesccab5c82011-01-18 15:49:25 -0800994 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -0800995 seq_printf(m, "Render p-state ratio: %d\n",
996 (gt_perf_status & 0xff00) >> 8);
997 seq_printf(m, "Render p-state VID: %d\n",
998 gt_perf_status & 0xff);
999 seq_printf(m, "Render p-state limit: %d\n",
1000 rp_state_limits & 0xff);
Chris Wilson8e8c06c2013-08-26 19:51:01 -03001001 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
Ben Widawskyf82855d2013-01-29 12:00:15 -08001002 seq_printf(m, "CAGF: %dMHz\n", cagf);
Jesse Barnesccab5c82011-01-18 15:49:25 -08001003 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1004 GEN6_CURICONT_MASK);
1005 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1006 GEN6_CURBSYTAVG_MASK);
1007 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1008 GEN6_CURBSYTAVG_MASK);
1009 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1010 GEN6_CURIAVG_MASK);
1011 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1012 GEN6_CURBSYTAVG_MASK);
1013 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1014 GEN6_CURBSYTAVG_MASK);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001015
1016 max_freq = (rp_state_cap & 0xff0000) >> 16;
1017 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
Ben Widawskyc8735b02012-09-07 19:43:39 -07001018 max_freq * GT_FREQUENCY_MULTIPLIER);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001019
1020 max_freq = (rp_state_cap & 0xff00) >> 8;
1021 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
Ben Widawskyc8735b02012-09-07 19:43:39 -07001022 max_freq * GT_FREQUENCY_MULTIPLIER);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001023
1024 max_freq = rp_state_cap & 0xff;
1025 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
Ben Widawskyc8735b02012-09-07 19:43:39 -07001026 max_freq * GT_FREQUENCY_MULTIPLIER);
Ben Widawsky31c77382013-04-05 14:29:22 -07001027
1028 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1029 dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
Jesse Barnes0a073b82013-04-17 15:54:58 -07001030 } else if (IS_VALLEYVIEW(dev)) {
1031 u32 freq_sts, val;
1032
Jesse Barnes259bd5d2013-04-22 15:59:30 -07001033 mutex_lock(&dev_priv->rps.hw_lock);
Jani Nikula64936252013-05-22 15:36:20 +03001034 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
Jesse Barnes0a073b82013-04-17 15:54:58 -07001035 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1036 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1037
Chon Ming Leec5bd2bf2013-11-07 15:23:27 +08001038 val = valleyview_rps_max_freq(dev_priv);
Jesse Barnes0a073b82013-04-17 15:54:58 -07001039 seq_printf(m, "max GPU freq: %d MHz\n",
Ville Syrjälä2ec38152013-11-05 22:42:29 +02001040 vlv_gpu_freq(dev_priv, val));
Jesse Barnes0a073b82013-04-17 15:54:58 -07001041
Chon Ming Leec5bd2bf2013-11-07 15:23:27 +08001042 val = valleyview_rps_min_freq(dev_priv);
Jesse Barnes0a073b82013-04-17 15:54:58 -07001043 seq_printf(m, "min GPU freq: %d MHz\n",
Ville Syrjälä2ec38152013-11-05 22:42:29 +02001044 vlv_gpu_freq(dev_priv, val));
Jesse Barnes0a073b82013-04-17 15:54:58 -07001045
1046 seq_printf(m, "current GPU freq: %d MHz\n",
Ville Syrjälä2ec38152013-11-05 22:42:29 +02001047 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
Jesse Barnes259bd5d2013-04-22 15:59:30 -07001048 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001049 } else {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001050 seq_puts(m, "no P-state info available\n");
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001051 }
Jesse Barnesf97108d2010-01-29 11:27:07 -08001052
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001053out:
1054 intel_runtime_pm_put(dev_priv);
1055 return ret;
Jesse Barnesf97108d2010-01-29 11:27:07 -08001056}
1057
1058static int i915_delayfreq_table(struct seq_file *m, void *unused)
1059{
1060 struct drm_info_node *node = (struct drm_info_node *) m->private;
1061 struct drm_device *dev = node->minor->dev;
1062 drm_i915_private_t *dev_priv = dev->dev_private;
1063 u32 delayfreq;
Ben Widawsky616fdb52011-10-05 11:44:54 -07001064 int ret, i;
1065
1066 ret = mutex_lock_interruptible(&dev->struct_mutex);
1067 if (ret)
1068 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001069 intel_runtime_pm_get(dev_priv);
Jesse Barnesf97108d2010-01-29 11:27:07 -08001070
1071 for (i = 0; i < 16; i++) {
1072 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001073 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1074 (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
Jesse Barnesf97108d2010-01-29 11:27:07 -08001075 }
1076
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001077 intel_runtime_pm_put(dev_priv);
1078
Ben Widawsky616fdb52011-10-05 11:44:54 -07001079 mutex_unlock(&dev->struct_mutex);
1080
Jesse Barnesf97108d2010-01-29 11:27:07 -08001081 return 0;
1082}
1083
1084static inline int MAP_TO_MV(int map)
1085{
1086 return 1250 - (map * 25);
1087}
1088
1089static int i915_inttoext_table(struct seq_file *m, void *unused)
1090{
1091 struct drm_info_node *node = (struct drm_info_node *) m->private;
1092 struct drm_device *dev = node->minor->dev;
1093 drm_i915_private_t *dev_priv = dev->dev_private;
1094 u32 inttoext;
Ben Widawsky616fdb52011-10-05 11:44:54 -07001095 int ret, i;
1096
1097 ret = mutex_lock_interruptible(&dev->struct_mutex);
1098 if (ret)
1099 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001100 intel_runtime_pm_get(dev_priv);
Jesse Barnesf97108d2010-01-29 11:27:07 -08001101
1102 for (i = 1; i <= 32; i++) {
1103 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1104 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1105 }
1106
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001107 intel_runtime_pm_put(dev_priv);
Ben Widawsky616fdb52011-10-05 11:44:54 -07001108 mutex_unlock(&dev->struct_mutex);
1109
Jesse Barnesf97108d2010-01-29 11:27:07 -08001110 return 0;
1111}
1112
Ben Widawsky4d855292011-12-12 19:34:16 -08001113static int ironlake_drpc_info(struct seq_file *m)
Jesse Barnesf97108d2010-01-29 11:27:07 -08001114{
1115 struct drm_info_node *node = (struct drm_info_node *) m->private;
1116 struct drm_device *dev = node->minor->dev;
1117 drm_i915_private_t *dev_priv = dev->dev_private;
Ben Widawsky616fdb52011-10-05 11:44:54 -07001118 u32 rgvmodectl, rstdbyctl;
1119 u16 crstandvid;
1120 int ret;
1121
1122 ret = mutex_lock_interruptible(&dev->struct_mutex);
1123 if (ret)
1124 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001125 intel_runtime_pm_get(dev_priv);
Ben Widawsky616fdb52011-10-05 11:44:54 -07001126
1127 rgvmodectl = I915_READ(MEMMODECTL);
1128 rstdbyctl = I915_READ(RSTDBYCTL);
1129 crstandvid = I915_READ16(CRSTANDVID);
1130
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001131 intel_runtime_pm_put(dev_priv);
Ben Widawsky616fdb52011-10-05 11:44:54 -07001132 mutex_unlock(&dev->struct_mutex);
Jesse Barnesf97108d2010-01-29 11:27:07 -08001133
1134 seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1135 "yes" : "no");
1136 seq_printf(m, "Boost freq: %d\n",
1137 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1138 MEMMODE_BOOST_FREQ_SHIFT);
1139 seq_printf(m, "HW control enabled: %s\n",
1140 rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1141 seq_printf(m, "SW control enabled: %s\n",
1142 rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1143 seq_printf(m, "Gated voltage change: %s\n",
1144 rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1145 seq_printf(m, "Starting frequency: P%d\n",
1146 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001147 seq_printf(m, "Max P-state: P%d\n",
Jesse Barnesf97108d2010-01-29 11:27:07 -08001148 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001149 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1150 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1151 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1152 seq_printf(m, "Render standby enabled: %s\n",
1153 (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
Damien Lespiau267f0c92013-06-24 22:59:48 +01001154 seq_puts(m, "Current RS state: ");
Jesse Barnes88271da2011-01-05 12:01:24 -08001155 switch (rstdbyctl & RSX_STATUS_MASK) {
1156 case RSX_STATUS_ON:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001157 seq_puts(m, "on\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001158 break;
1159 case RSX_STATUS_RC1:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001160 seq_puts(m, "RC1\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001161 break;
1162 case RSX_STATUS_RC1E:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001163 seq_puts(m, "RC1E\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001164 break;
1165 case RSX_STATUS_RS1:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001166 seq_puts(m, "RS1\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001167 break;
1168 case RSX_STATUS_RS2:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001169 seq_puts(m, "RS2 (RC6)\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001170 break;
1171 case RSX_STATUS_RS3:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001172 seq_puts(m, "RC3 (RC6+)\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001173 break;
1174 default:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001175 seq_puts(m, "unknown\n");
Jesse Barnes88271da2011-01-05 12:01:24 -08001176 break;
1177 }
Jesse Barnesf97108d2010-01-29 11:27:07 -08001178
1179 return 0;
1180}
1181
Deepak S669ab5a2014-01-10 15:18:26 +05301182static int vlv_drpc_info(struct seq_file *m)
1183{
1184
1185 struct drm_info_node *node = (struct drm_info_node *) m->private;
1186 struct drm_device *dev = node->minor->dev;
1187 struct drm_i915_private *dev_priv = dev->dev_private;
1188 u32 rpmodectl1, rcctl1;
1189 unsigned fw_rendercount = 0, fw_mediacount = 0;
1190
1191 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1192 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1193
1194 seq_printf(m, "Video Turbo Mode: %s\n",
1195 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1196 seq_printf(m, "Turbo enabled: %s\n",
1197 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1198 seq_printf(m, "HW control enabled: %s\n",
1199 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1200 seq_printf(m, "SW control enabled: %s\n",
1201 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1202 GEN6_RP_MEDIA_SW_MODE));
1203 seq_printf(m, "RC6 Enabled: %s\n",
1204 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1205 GEN6_RC_CTL_EI_MODE(1))));
1206 seq_printf(m, "Render Power Well: %s\n",
1207 (I915_READ(VLV_GTLC_PW_STATUS) &
1208 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1209 seq_printf(m, "Media Power Well: %s\n",
1210 (I915_READ(VLV_GTLC_PW_STATUS) &
1211 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1212
1213 spin_lock_irq(&dev_priv->uncore.lock);
1214 fw_rendercount = dev_priv->uncore.fw_rendercount;
1215 fw_mediacount = dev_priv->uncore.fw_mediacount;
1216 spin_unlock_irq(&dev_priv->uncore.lock);
1217
1218 seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1219 seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1220
1221
1222 return 0;
1223}
1224
1225
Ben Widawsky4d855292011-12-12 19:34:16 -08001226static int gen6_drpc_info(struct seq_file *m)
1227{
1228
1229 struct drm_info_node *node = (struct drm_info_node *) m->private;
1230 struct drm_device *dev = node->minor->dev;
1231 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskyecd8fae2012-09-26 10:34:02 -07001232 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
Daniel Vetter93b525d2012-01-25 13:52:43 +01001233 unsigned forcewake_count;
Damien Lespiauaee56cf2013-06-24 22:59:49 +01001234 int count = 0, ret;
Ben Widawsky4d855292011-12-12 19:34:16 -08001235
1236 ret = mutex_lock_interruptible(&dev->struct_mutex);
1237 if (ret)
1238 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001239 intel_runtime_pm_get(dev_priv);
Ben Widawsky4d855292011-12-12 19:34:16 -08001240
Chris Wilson907b28c2013-07-19 20:36:52 +01001241 spin_lock_irq(&dev_priv->uncore.lock);
1242 forcewake_count = dev_priv->uncore.forcewake_count;
1243 spin_unlock_irq(&dev_priv->uncore.lock);
Daniel Vetter93b525d2012-01-25 13:52:43 +01001244
1245 if (forcewake_count) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001246 seq_puts(m, "RC information inaccurate because somebody "
1247 "holds a forcewake reference \n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001248 } else {
1249 /* NB: we cannot use forcewake, else we read the wrong values */
1250 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1251 udelay(10);
1252 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1253 }
1254
1255 gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
Chris Wilsoned71f1b2013-07-19 20:36:56 +01001256 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
Ben Widawsky4d855292011-12-12 19:34:16 -08001257
1258 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1259 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1260 mutex_unlock(&dev->struct_mutex);
Ben Widawsky44cbd332012-11-06 14:36:36 +00001261 mutex_lock(&dev_priv->rps.hw_lock);
1262 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1263 mutex_unlock(&dev_priv->rps.hw_lock);
Ben Widawsky4d855292011-12-12 19:34:16 -08001264
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001265 intel_runtime_pm_put(dev_priv);
1266
Ben Widawsky4d855292011-12-12 19:34:16 -08001267 seq_printf(m, "Video Turbo Mode: %s\n",
1268 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1269 seq_printf(m, "HW control enabled: %s\n",
1270 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1271 seq_printf(m, "SW control enabled: %s\n",
1272 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1273 GEN6_RP_MEDIA_SW_MODE));
Eric Anholtfff24e22012-01-23 16:14:05 -08001274 seq_printf(m, "RC1e Enabled: %s\n",
Ben Widawsky4d855292011-12-12 19:34:16 -08001275 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1276 seq_printf(m, "RC6 Enabled: %s\n",
1277 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1278 seq_printf(m, "Deep RC6 Enabled: %s\n",
1279 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1280 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1281 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
Damien Lespiau267f0c92013-06-24 22:59:48 +01001282 seq_puts(m, "Current RC state: ");
Ben Widawsky4d855292011-12-12 19:34:16 -08001283 switch (gt_core_status & GEN6_RCn_MASK) {
1284 case GEN6_RC0:
1285 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
Damien Lespiau267f0c92013-06-24 22:59:48 +01001286 seq_puts(m, "Core Power Down\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001287 else
Damien Lespiau267f0c92013-06-24 22:59:48 +01001288 seq_puts(m, "on\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001289 break;
1290 case GEN6_RC3:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001291 seq_puts(m, "RC3\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001292 break;
1293 case GEN6_RC6:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001294 seq_puts(m, "RC6\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001295 break;
1296 case GEN6_RC7:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001297 seq_puts(m, "RC7\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001298 break;
1299 default:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001300 seq_puts(m, "Unknown\n");
Ben Widawsky4d855292011-12-12 19:34:16 -08001301 break;
1302 }
1303
1304 seq_printf(m, "Core Power Down: %s\n",
1305 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
Ben Widawskycce66a22012-03-27 18:59:38 -07001306
1307 /* Not exactly sure what this is */
1308 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1309 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1310 seq_printf(m, "RC6 residency since boot: %u\n",
1311 I915_READ(GEN6_GT_GFX_RC6));
1312 seq_printf(m, "RC6+ residency since boot: %u\n",
1313 I915_READ(GEN6_GT_GFX_RC6p));
1314 seq_printf(m, "RC6++ residency since boot: %u\n",
1315 I915_READ(GEN6_GT_GFX_RC6pp));
1316
Ben Widawskyecd8fae2012-09-26 10:34:02 -07001317 seq_printf(m, "RC6 voltage: %dmV\n",
1318 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1319 seq_printf(m, "RC6+ voltage: %dmV\n",
1320 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1321 seq_printf(m, "RC6++ voltage: %dmV\n",
1322 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
Ben Widawsky4d855292011-12-12 19:34:16 -08001323 return 0;
1324}
1325
1326static int i915_drpc_info(struct seq_file *m, void *unused)
1327{
1328 struct drm_info_node *node = (struct drm_info_node *) m->private;
1329 struct drm_device *dev = node->minor->dev;
1330
Deepak S669ab5a2014-01-10 15:18:26 +05301331 if (IS_VALLEYVIEW(dev))
1332 return vlv_drpc_info(m);
1333 else if (IS_GEN6(dev) || IS_GEN7(dev))
Ben Widawsky4d855292011-12-12 19:34:16 -08001334 return gen6_drpc_info(m);
1335 else
1336 return ironlake_drpc_info(m);
1337}
1338
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001339static int i915_fbc_status(struct seq_file *m, void *unused)
1340{
1341 struct drm_info_node *node = (struct drm_info_node *) m->private;
1342 struct drm_device *dev = node->minor->dev;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001343 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001344
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01001345 if (!HAS_FBC(dev)) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001346 seq_puts(m, "FBC unsupported on this chipset\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001347 return 0;
1348 }
1349
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001350 intel_runtime_pm_get(dev_priv);
1351
Adam Jacksonee5382a2010-04-23 11:17:39 -04001352 if (intel_fbc_enabled(dev)) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001353 seq_puts(m, "FBC enabled\n");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001354 } else {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001355 seq_puts(m, "FBC disabled: ");
Ben Widawsky5c3fe8b2013-06-27 16:30:21 -07001356 switch (dev_priv->fbc.no_fbc_reason) {
Chris Wilson29ebf902013-07-27 17:23:55 +01001357 case FBC_OK:
1358 seq_puts(m, "FBC actived, but currently disabled in hardware");
1359 break;
1360 case FBC_UNSUPPORTED:
1361 seq_puts(m, "unsupported by this chipset");
1362 break;
Chris Wilsonbed4a672010-09-11 10:47:47 +01001363 case FBC_NO_OUTPUT:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001364 seq_puts(m, "no outputs");
Chris Wilsonbed4a672010-09-11 10:47:47 +01001365 break;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001366 case FBC_STOLEN_TOO_SMALL:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001367 seq_puts(m, "not enough stolen memory");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001368 break;
1369 case FBC_UNSUPPORTED_MODE:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001370 seq_puts(m, "mode not supported");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001371 break;
1372 case FBC_MODE_TOO_LARGE:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001373 seq_puts(m, "mode too large");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001374 break;
1375 case FBC_BAD_PLANE:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001376 seq_puts(m, "FBC unsupported on plane");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001377 break;
1378 case FBC_NOT_TILED:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001379 seq_puts(m, "scanout buffer not tiled");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001380 break;
Jesse Barnes9c928d12010-07-23 15:20:00 -07001381 case FBC_MULTIPLE_PIPES:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001382 seq_puts(m, "multiple pipes are enabled");
Jesse Barnes9c928d12010-07-23 15:20:00 -07001383 break;
Jesse Barnesc1a9f042011-05-05 15:24:21 -07001384 case FBC_MODULE_PARAM:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001385 seq_puts(m, "disabled per module param (default off)");
Jesse Barnesc1a9f042011-05-05 15:24:21 -07001386 break;
Damien Lespiau8a5729a2013-06-24 16:22:02 +01001387 case FBC_CHIP_DEFAULT:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001388 seq_puts(m, "disabled per chip default");
Damien Lespiau8a5729a2013-06-24 16:22:02 +01001389 break;
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001390 default:
Damien Lespiau267f0c92013-06-24 22:59:48 +01001391 seq_puts(m, "unknown reason");
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001392 }
Damien Lespiau267f0c92013-06-24 22:59:48 +01001393 seq_putc(m, '\n');
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001394 }
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001395
1396 intel_runtime_pm_put(dev_priv);
1397
Jesse Barnesb5e50c32010-02-05 12:42:41 -08001398 return 0;
1399}
1400
Paulo Zanoni92d44622013-05-31 16:33:24 -03001401static int i915_ips_status(struct seq_file *m, void *unused)
1402{
1403 struct drm_info_node *node = (struct drm_info_node *) m->private;
1404 struct drm_device *dev = node->minor->dev;
1405 struct drm_i915_private *dev_priv = dev->dev_private;
1406
Damien Lespiauf5adf942013-06-24 18:29:34 +01001407 if (!HAS_IPS(dev)) {
Paulo Zanoni92d44622013-05-31 16:33:24 -03001408 seq_puts(m, "not supported\n");
1409 return 0;
1410 }
1411
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001412 intel_runtime_pm_get(dev_priv);
1413
Jesse Barnese59150d2014-01-07 13:30:45 -08001414 if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
Paulo Zanoni92d44622013-05-31 16:33:24 -03001415 seq_puts(m, "enabled\n");
1416 else
1417 seq_puts(m, "disabled\n");
1418
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001419 intel_runtime_pm_put(dev_priv);
1420
Paulo Zanoni92d44622013-05-31 16:33:24 -03001421 return 0;
1422}
1423
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001424static int i915_sr_status(struct seq_file *m, void *unused)
1425{
1426 struct drm_info_node *node = (struct drm_info_node *) m->private;
1427 struct drm_device *dev = node->minor->dev;
1428 drm_i915_private_t *dev_priv = dev->dev_private;
1429 bool sr_enabled = false;
1430
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001431 intel_runtime_pm_get(dev_priv);
1432
Yuanhan Liu13982612010-12-15 15:42:31 +08001433 if (HAS_PCH_SPLIT(dev))
Chris Wilson5ba2aaa2010-08-19 18:04:08 +01001434 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
Chris Wilsona6c45cf2010-09-17 00:32:17 +01001435 else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001436 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1437 else if (IS_I915GM(dev))
1438 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1439 else if (IS_PINEVIEW(dev))
1440 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1441
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001442 intel_runtime_pm_put(dev_priv);
1443
Chris Wilson5ba2aaa2010-08-19 18:04:08 +01001444 seq_printf(m, "self-refresh: %s\n",
1445 sr_enabled ? "enabled" : "disabled");
Jesse Barnes4a9bef32010-02-05 12:47:35 -08001446
1447 return 0;
1448}
1449
Jesse Barnes7648fa92010-05-20 14:28:11 -07001450static int i915_emon_status(struct seq_file *m, void *unused)
1451{
1452 struct drm_info_node *node = (struct drm_info_node *) m->private;
1453 struct drm_device *dev = node->minor->dev;
1454 drm_i915_private_t *dev_priv = dev->dev_private;
1455 unsigned long temp, chipset, gfx;
Chris Wilsonde227ef2010-07-03 07:58:38 +01001456 int ret;
1457
Chris Wilson582be6b2012-04-30 19:35:02 +01001458 if (!IS_GEN5(dev))
1459 return -ENODEV;
1460
Chris Wilsonde227ef2010-07-03 07:58:38 +01001461 ret = mutex_lock_interruptible(&dev->struct_mutex);
1462 if (ret)
1463 return ret;
Jesse Barnes7648fa92010-05-20 14:28:11 -07001464
1465 temp = i915_mch_val(dev_priv);
1466 chipset = i915_chipset_val(dev_priv);
1467 gfx = i915_gfx_val(dev_priv);
Chris Wilsonde227ef2010-07-03 07:58:38 +01001468 mutex_unlock(&dev->struct_mutex);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001469
1470 seq_printf(m, "GMCH temp: %ld\n", temp);
1471 seq_printf(m, "Chipset power: %ld\n", chipset);
1472 seq_printf(m, "GFX power: %ld\n", gfx);
1473 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1474
1475 return 0;
1476}
1477
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001478static int i915_ring_freq_table(struct seq_file *m, void *unused)
1479{
1480 struct drm_info_node *node = (struct drm_info_node *) m->private;
1481 struct drm_device *dev = node->minor->dev;
1482 drm_i915_private_t *dev_priv = dev->dev_private;
Paulo Zanoni5bfa0192013-12-19 11:54:52 -02001483 int ret = 0;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001484 int gpu_freq, ia_freq;
1485
Jesse Barnes1c70c0c2011-06-29 13:34:36 -07001486 if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001487 seq_puts(m, "unsupported on this chipset\n");
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001488 return 0;
1489 }
1490
Paulo Zanoni5bfa0192013-12-19 11:54:52 -02001491 intel_runtime_pm_get(dev_priv);
1492
Tom O'Rourke5c9669c2013-09-16 14:56:43 -07001493 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1494
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001495 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001496 if (ret)
Paulo Zanoni5bfa0192013-12-19 11:54:52 -02001497 goto out;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001498
Damien Lespiau267f0c92013-06-24 22:59:48 +01001499 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001500
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001501 for (gpu_freq = dev_priv->rps.min_delay;
1502 gpu_freq <= dev_priv->rps.max_delay;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001503 gpu_freq++) {
Ben Widawsky42c05262012-09-26 10:34:00 -07001504 ia_freq = gpu_freq;
1505 sandybridge_pcode_read(dev_priv,
1506 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1507 &ia_freq);
Chris Wilson3ebecd02013-04-12 19:10:13 +01001508 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1509 gpu_freq * GT_FREQUENCY_MULTIPLIER,
1510 ((ia_freq >> 0) & 0xff) * 100,
1511 ((ia_freq >> 8) & 0xff) * 100);
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001512 }
1513
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001514 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001515
Paulo Zanoni5bfa0192013-12-19 11:54:52 -02001516out:
1517 intel_runtime_pm_put(dev_priv);
1518 return ret;
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07001519}
1520
Jesse Barnes7648fa92010-05-20 14:28:11 -07001521static int i915_gfxec(struct seq_file *m, void *unused)
1522{
1523 struct drm_info_node *node = (struct drm_info_node *) m->private;
1524 struct drm_device *dev = node->minor->dev;
1525 drm_i915_private_t *dev_priv = dev->dev_private;
Ben Widawsky616fdb52011-10-05 11:44:54 -07001526 int ret;
1527
1528 ret = mutex_lock_interruptible(&dev->struct_mutex);
1529 if (ret)
1530 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001531 intel_runtime_pm_get(dev_priv);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001532
1533 seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001534 intel_runtime_pm_put(dev_priv);
Jesse Barnes7648fa92010-05-20 14:28:11 -07001535
Ben Widawsky616fdb52011-10-05 11:44:54 -07001536 mutex_unlock(&dev->struct_mutex);
1537
Jesse Barnes7648fa92010-05-20 14:28:11 -07001538 return 0;
1539}
1540
Chris Wilson44834a62010-08-19 16:09:23 +01001541static int i915_opregion(struct seq_file *m, void *unused)
1542{
1543 struct drm_info_node *node = (struct drm_info_node *) m->private;
1544 struct drm_device *dev = node->minor->dev;
1545 drm_i915_private_t *dev_priv = dev->dev_private;
1546 struct intel_opregion *opregion = &dev_priv->opregion;
Daniel Vetter0d38f002012-04-21 22:49:10 +02001547 void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
Chris Wilson44834a62010-08-19 16:09:23 +01001548 int ret;
1549
Daniel Vetter0d38f002012-04-21 22:49:10 +02001550 if (data == NULL)
1551 return -ENOMEM;
1552
Chris Wilson44834a62010-08-19 16:09:23 +01001553 ret = mutex_lock_interruptible(&dev->struct_mutex);
1554 if (ret)
Daniel Vetter0d38f002012-04-21 22:49:10 +02001555 goto out;
Chris Wilson44834a62010-08-19 16:09:23 +01001556
Daniel Vetter0d38f002012-04-21 22:49:10 +02001557 if (opregion->header) {
1558 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1559 seq_write(m, data, OPREGION_SIZE);
1560 }
Chris Wilson44834a62010-08-19 16:09:23 +01001561
1562 mutex_unlock(&dev->struct_mutex);
1563
Daniel Vetter0d38f002012-04-21 22:49:10 +02001564out:
1565 kfree(data);
Chris Wilson44834a62010-08-19 16:09:23 +01001566 return 0;
1567}
1568
Chris Wilson37811fc2010-08-25 22:45:57 +01001569static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1570{
1571 struct drm_info_node *node = (struct drm_info_node *) m->private;
1572 struct drm_device *dev = node->minor->dev;
Daniel Vetter4520f532013-10-09 09:18:51 +02001573 struct intel_fbdev *ifbdev = NULL;
Chris Wilson37811fc2010-08-25 22:45:57 +01001574 struct intel_framebuffer *fb;
Chris Wilson37811fc2010-08-25 22:45:57 +01001575
Daniel Vetter4520f532013-10-09 09:18:51 +02001576#ifdef CONFIG_DRM_I915_FBDEV
1577 struct drm_i915_private *dev_priv = dev->dev_private;
1578 int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
Chris Wilson37811fc2010-08-25 22:45:57 +01001579 if (ret)
1580 return ret;
1581
1582 ifbdev = dev_priv->fbdev;
1583 fb = to_intel_framebuffer(ifbdev->helper.fb);
1584
Daniel Vetter623f9782012-12-11 16:21:38 +01001585 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
Chris Wilson37811fc2010-08-25 22:45:57 +01001586 fb->base.width,
1587 fb->base.height,
1588 fb->base.depth,
Daniel Vetter623f9782012-12-11 16:21:38 +01001589 fb->base.bits_per_pixel,
1590 atomic_read(&fb->base.refcount.refcount));
Chris Wilson05394f32010-11-08 19:18:58 +00001591 describe_obj(m, fb->obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +01001592 seq_putc(m, '\n');
Daniel Vetter4b096ac2012-12-10 21:19:18 +01001593 mutex_unlock(&dev->mode_config.mutex);
Daniel Vetter4520f532013-10-09 09:18:51 +02001594#endif
Chris Wilson37811fc2010-08-25 22:45:57 +01001595
Daniel Vetter4b096ac2012-12-10 21:19:18 +01001596 mutex_lock(&dev->mode_config.fb_lock);
Chris Wilson37811fc2010-08-25 22:45:57 +01001597 list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
Daniel Vetter131a56d2013-10-17 14:35:31 +02001598 if (ifbdev && &fb->base == ifbdev->helper.fb)
Chris Wilson37811fc2010-08-25 22:45:57 +01001599 continue;
1600
Daniel Vetter623f9782012-12-11 16:21:38 +01001601 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
Chris Wilson37811fc2010-08-25 22:45:57 +01001602 fb->base.width,
1603 fb->base.height,
1604 fb->base.depth,
Daniel Vetter623f9782012-12-11 16:21:38 +01001605 fb->base.bits_per_pixel,
1606 atomic_read(&fb->base.refcount.refcount));
Chris Wilson05394f32010-11-08 19:18:58 +00001607 describe_obj(m, fb->obj);
Damien Lespiau267f0c92013-06-24 22:59:48 +01001608 seq_putc(m, '\n');
Chris Wilson37811fc2010-08-25 22:45:57 +01001609 }
Daniel Vetter4b096ac2012-12-10 21:19:18 +01001610 mutex_unlock(&dev->mode_config.fb_lock);
Chris Wilson37811fc2010-08-25 22:45:57 +01001611
1612 return 0;
1613}
1614
Ben Widawskye76d3632011-03-19 18:14:29 -07001615static int i915_context_status(struct seq_file *m, void *unused)
1616{
1617 struct drm_info_node *node = (struct drm_info_node *) m->private;
1618 struct drm_device *dev = node->minor->dev;
1619 drm_i915_private_t *dev_priv = dev->dev_private;
Ben Widawskya168c292013-02-14 15:05:12 -08001620 struct intel_ring_buffer *ring;
Ben Widawskya33afea2013-09-17 21:12:45 -07001621 struct i915_hw_context *ctx;
Ben Widawskya168c292013-02-14 15:05:12 -08001622 int ret, i;
Ben Widawskye76d3632011-03-19 18:14:29 -07001623
1624 ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1625 if (ret)
1626 return ret;
1627
Daniel Vetter3e373942012-11-02 19:55:04 +01001628 if (dev_priv->ips.pwrctx) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001629 seq_puts(m, "power context ");
Daniel Vetter3e373942012-11-02 19:55:04 +01001630 describe_obj(m, dev_priv->ips.pwrctx);
Damien Lespiau267f0c92013-06-24 22:59:48 +01001631 seq_putc(m, '\n');
Ben Widawskydc501fb2011-06-29 11:41:51 -07001632 }
Ben Widawskye76d3632011-03-19 18:14:29 -07001633
Daniel Vetter3e373942012-11-02 19:55:04 +01001634 if (dev_priv->ips.renderctx) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001635 seq_puts(m, "render context ");
Daniel Vetter3e373942012-11-02 19:55:04 +01001636 describe_obj(m, dev_priv->ips.renderctx);
Damien Lespiau267f0c92013-06-24 22:59:48 +01001637 seq_putc(m, '\n');
Ben Widawskydc501fb2011-06-29 11:41:51 -07001638 }
Ben Widawskye76d3632011-03-19 18:14:29 -07001639
Ben Widawskya33afea2013-09-17 21:12:45 -07001640 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1641 seq_puts(m, "HW context ");
Ben Widawsky3ccfd192013-09-18 19:03:18 -07001642 describe_ctx(m, ctx);
Ben Widawskya33afea2013-09-17 21:12:45 -07001643 for_each_ring(ring, dev_priv, i)
1644 if (ring->default_context == ctx)
1645 seq_printf(m, "(default context %s) ", ring->name);
1646
1647 describe_obj(m, ctx->obj);
1648 seq_putc(m, '\n');
Ben Widawskya168c292013-02-14 15:05:12 -08001649 }
1650
Ben Widawskye76d3632011-03-19 18:14:29 -07001651 mutex_unlock(&dev->mode_config.mutex);
1652
1653 return 0;
1654}
1655
Ben Widawsky6d794d42011-04-25 11:25:56 -07001656static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1657{
1658 struct drm_info_node *node = (struct drm_info_node *) m->private;
1659 struct drm_device *dev = node->minor->dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
Deepak S43709ba2013-11-23 14:55:44 +05301661 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
Ben Widawsky6d794d42011-04-25 11:25:56 -07001662
Chris Wilson907b28c2013-07-19 20:36:52 +01001663 spin_lock_irq(&dev_priv->uncore.lock);
Deepak S43709ba2013-11-23 14:55:44 +05301664 if (IS_VALLEYVIEW(dev)) {
1665 fw_rendercount = dev_priv->uncore.fw_rendercount;
1666 fw_mediacount = dev_priv->uncore.fw_mediacount;
1667 } else
1668 forcewake_count = dev_priv->uncore.forcewake_count;
Chris Wilson907b28c2013-07-19 20:36:52 +01001669 spin_unlock_irq(&dev_priv->uncore.lock);
Daniel Vetter9f1f46a2011-12-14 13:57:03 +01001670
Deepak S43709ba2013-11-23 14:55:44 +05301671 if (IS_VALLEYVIEW(dev)) {
1672 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1673 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1674 } else
1675 seq_printf(m, "forcewake count = %u\n", forcewake_count);
Ben Widawsky6d794d42011-04-25 11:25:56 -07001676
1677 return 0;
1678}
1679
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001680static const char *swizzle_string(unsigned swizzle)
1681{
Damien Lespiauaee56cf2013-06-24 22:59:49 +01001682 switch (swizzle) {
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001683 case I915_BIT_6_SWIZZLE_NONE:
1684 return "none";
1685 case I915_BIT_6_SWIZZLE_9:
1686 return "bit9";
1687 case I915_BIT_6_SWIZZLE_9_10:
1688 return "bit9/bit10";
1689 case I915_BIT_6_SWIZZLE_9_11:
1690 return "bit9/bit11";
1691 case I915_BIT_6_SWIZZLE_9_10_11:
1692 return "bit9/bit10/bit11";
1693 case I915_BIT_6_SWIZZLE_9_17:
1694 return "bit9/bit17";
1695 case I915_BIT_6_SWIZZLE_9_10_17:
1696 return "bit9/bit10/bit17";
1697 case I915_BIT_6_SWIZZLE_UNKNOWN:
Masanari Iida8a168ca2012-12-29 02:00:09 +09001698 return "unknown";
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001699 }
1700
1701 return "bug";
1702}
1703
1704static int i915_swizzle_info(struct seq_file *m, void *data)
1705{
1706 struct drm_info_node *node = (struct drm_info_node *) m->private;
1707 struct drm_device *dev = node->minor->dev;
1708 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter22bcfc62012-08-09 15:07:02 +02001709 int ret;
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001710
Daniel Vetter22bcfc62012-08-09 15:07:02 +02001711 ret = mutex_lock_interruptible(&dev->struct_mutex);
1712 if (ret)
1713 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001714 intel_runtime_pm_get(dev_priv);
Daniel Vetter22bcfc62012-08-09 15:07:02 +02001715
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001716 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1717 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1718 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1719 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1720
1721 if (IS_GEN3(dev) || IS_GEN4(dev)) {
1722 seq_printf(m, "DDC = 0x%08x\n",
1723 I915_READ(DCC));
1724 seq_printf(m, "C0DRB3 = 0x%04x\n",
1725 I915_READ16(C0DRB3));
1726 seq_printf(m, "C1DRB3 = 0x%04x\n",
1727 I915_READ16(C1DRB3));
Ben Widawsky9d3203e2013-11-02 21:07:14 -07001728 } else if (INTEL_INFO(dev)->gen >= 6) {
Daniel Vetter3fa7d232012-01-31 16:47:56 +01001729 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1730 I915_READ(MAD_DIMM_C0));
1731 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1732 I915_READ(MAD_DIMM_C1));
1733 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1734 I915_READ(MAD_DIMM_C2));
1735 seq_printf(m, "TILECTL = 0x%08x\n",
1736 I915_READ(TILECTL));
Ben Widawsky9d3203e2013-11-02 21:07:14 -07001737 if (IS_GEN8(dev))
1738 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1739 I915_READ(GAMTARBMODE));
1740 else
1741 seq_printf(m, "ARB_MODE = 0x%08x\n",
1742 I915_READ(ARB_MODE));
Daniel Vetter3fa7d232012-01-31 16:47:56 +01001743 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1744 I915_READ(DISP_ARB_CTL));
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001745 }
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001746 intel_runtime_pm_put(dev_priv);
Daniel Vetterea16a3c2011-12-14 13:57:16 +01001747 mutex_unlock(&dev->struct_mutex);
1748
1749 return 0;
1750}
1751
Ben Widawsky1c60fef2013-12-06 14:11:30 -08001752static int per_file_ctx(int id, void *ptr, void *data)
1753{
1754 struct i915_hw_context *ctx = ptr;
1755 struct seq_file *m = data;
1756 struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1757
1758 ppgtt->debug_dump(ppgtt, m);
1759
1760 return 0;
1761}
1762
Ben Widawsky77df6772013-11-02 21:07:30 -07001763static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01001764{
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01001765 struct drm_i915_private *dev_priv = dev->dev_private;
1766 struct intel_ring_buffer *ring;
Ben Widawsky77df6772013-11-02 21:07:30 -07001767 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1768 int unused, i;
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01001769
Ben Widawsky77df6772013-11-02 21:07:30 -07001770 if (!ppgtt)
1771 return;
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01001772
Ben Widawsky77df6772013-11-02 21:07:30 -07001773 seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
Ben Widawsky5abbcca2014-02-21 13:06:34 -08001774 seq_printf(m, "Page tables: %d\n", ppgtt->num_pd_entries);
Ben Widawsky77df6772013-11-02 21:07:30 -07001775 for_each_ring(ring, dev_priv, unused) {
1776 seq_printf(m, "%s\n", ring->name);
1777 for (i = 0; i < 4; i++) {
1778 u32 offset = 0x270 + i * 8;
1779 u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1780 pdp <<= 32;
1781 pdp |= I915_READ(ring->mmio_base + offset);
1782 for (i = 0; i < 4; i++)
1783 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1784 }
1785 }
1786}
1787
1788static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1789{
1790 struct drm_i915_private *dev_priv = dev->dev_private;
1791 struct intel_ring_buffer *ring;
Ben Widawsky1c60fef2013-12-06 14:11:30 -08001792 struct drm_file *file;
Ben Widawsky77df6772013-11-02 21:07:30 -07001793 int i;
1794
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01001795 if (INTEL_INFO(dev)->gen == 6)
1796 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1797
Chris Wilsona2c7f6f2012-09-01 20:51:22 +01001798 for_each_ring(ring, dev_priv, i) {
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01001799 seq_printf(m, "%s\n", ring->name);
1800 if (INTEL_INFO(dev)->gen == 7)
1801 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1802 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1803 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1804 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1805 }
1806 if (dev_priv->mm.aliasing_ppgtt) {
1807 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1808
Damien Lespiau267f0c92013-06-24 22:59:48 +01001809 seq_puts(m, "aliasing PPGTT:\n");
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01001810 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
Ben Widawsky1c60fef2013-12-06 14:11:30 -08001811
Ben Widawsky87d60b62013-12-06 14:11:29 -08001812 ppgtt->debug_dump(ppgtt, m);
Ben Widawsky1c60fef2013-12-06 14:11:30 -08001813 } else
1814 return;
1815
1816 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1817 struct drm_i915_file_private *file_priv = file->driver_priv;
1818 struct i915_hw_ppgtt *pvt_ppgtt;
1819
1820 pvt_ppgtt = ctx_to_ppgtt(file_priv->private_default_ctx);
1821 seq_printf(m, "proc: %s\n",
1822 get_pid_task(file->pid, PIDTYPE_PID)->comm);
1823 seq_puts(m, " default context:\n");
1824 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01001825 }
1826 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
Ben Widawsky77df6772013-11-02 21:07:30 -07001827}
1828
1829static int i915_ppgtt_info(struct seq_file *m, void *data)
1830{
1831 struct drm_info_node *node = (struct drm_info_node *) m->private;
1832 struct drm_device *dev = node->minor->dev;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001833 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky77df6772013-11-02 21:07:30 -07001834
1835 int ret = mutex_lock_interruptible(&dev->struct_mutex);
1836 if (ret)
1837 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001838 intel_runtime_pm_get(dev_priv);
Ben Widawsky77df6772013-11-02 21:07:30 -07001839
1840 if (INTEL_INFO(dev)->gen >= 8)
1841 gen8_ppgtt_info(m, dev);
1842 else if (INTEL_INFO(dev)->gen >= 6)
1843 gen6_ppgtt_info(m, dev);
1844
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001845 intel_runtime_pm_put(dev_priv);
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01001846 mutex_unlock(&dev->struct_mutex);
1847
1848 return 0;
1849}
1850
Jesse Barnes57f350b2012-03-28 13:39:25 -07001851static int i915_dpio_info(struct seq_file *m, void *data)
1852{
1853 struct drm_info_node *node = (struct drm_info_node *) m->private;
1854 struct drm_device *dev = node->minor->dev;
1855 struct drm_i915_private *dev_priv = dev->dev_private;
1856 int ret;
1857
1858
1859 if (!IS_VALLEYVIEW(dev)) {
Damien Lespiau267f0c92013-06-24 22:59:48 +01001860 seq_puts(m, "unsupported\n");
Jesse Barnes57f350b2012-03-28 13:39:25 -07001861 return 0;
1862 }
1863
Daniel Vetter09153002012-12-12 14:06:44 +01001864 ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
Jesse Barnes57f350b2012-03-28 13:39:25 -07001865 if (ret)
1866 return ret;
1867
1868 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1869
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001870 seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1871 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1872 seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1873 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
Jesse Barnes57f350b2012-03-28 13:39:25 -07001874
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001875 seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1876 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1877 seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1878 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
Jesse Barnes57f350b2012-03-28 13:39:25 -07001879
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001880 seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1881 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1882 seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1883 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
Jesse Barnes57f350b2012-03-28 13:39:25 -07001884
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001885 seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1886 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1887 seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1888 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
Jesse Barnes57f350b2012-03-28 13:39:25 -07001889
1890 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001891 vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
Jesse Barnes57f350b2012-03-28 13:39:25 -07001892
Daniel Vetter09153002012-12-12 14:06:44 +01001893 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes57f350b2012-03-28 13:39:25 -07001894
1895 return 0;
1896}
1897
Ben Widawsky63573eb2013-07-04 11:02:07 -07001898static int i915_llc(struct seq_file *m, void *data)
1899{
1900 struct drm_info_node *node = (struct drm_info_node *) m->private;
1901 struct drm_device *dev = node->minor->dev;
1902 struct drm_i915_private *dev_priv = dev->dev_private;
1903
1904 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1905 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1906 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1907
1908 return 0;
1909}
1910
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03001911static int i915_edp_psr_status(struct seq_file *m, void *data)
1912{
1913 struct drm_info_node *node = m->private;
1914 struct drm_device *dev = node->minor->dev;
1915 struct drm_i915_private *dev_priv = dev->dev_private;
Rodrigo Vivia031d702013-10-03 16:15:06 -03001916 u32 psrperf = 0;
1917 bool enabled = false;
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03001918
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001919 intel_runtime_pm_get(dev_priv);
1920
Rodrigo Vivia031d702013-10-03 16:15:06 -03001921 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1922 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03001923
Rodrigo Vivia031d702013-10-03 16:15:06 -03001924 enabled = HAS_PSR(dev) &&
1925 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1926 seq_printf(m, "Enabled: %s\n", yesno(enabled));
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03001927
Rodrigo Vivia031d702013-10-03 16:15:06 -03001928 if (HAS_PSR(dev))
1929 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1930 EDP_PSR_PERF_CNT_MASK;
1931 seq_printf(m, "Performance_Counter: %u\n", psrperf);
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03001932
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02001933 intel_runtime_pm_put(dev_priv);
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03001934 return 0;
1935}
1936
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02001937static int i915_sink_crc(struct seq_file *m, void *data)
1938{
1939 struct drm_info_node *node = m->private;
1940 struct drm_device *dev = node->minor->dev;
1941 struct intel_encoder *encoder;
1942 struct intel_connector *connector;
1943 struct intel_dp *intel_dp = NULL;
1944 int ret;
1945 u8 crc[6];
1946
1947 drm_modeset_lock_all(dev);
1948 list_for_each_entry(connector, &dev->mode_config.connector_list,
1949 base.head) {
1950
1951 if (connector->base.dpms != DRM_MODE_DPMS_ON)
1952 continue;
1953
Paulo Zanonib6ae3c72014-02-13 17:51:33 -02001954 if (!connector->base.encoder)
1955 continue;
1956
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02001957 encoder = to_intel_encoder(connector->base.encoder);
1958 if (encoder->type != INTEL_OUTPUT_EDP)
1959 continue;
1960
1961 intel_dp = enc_to_intel_dp(&encoder->base);
1962
1963 ret = intel_dp_sink_crc(intel_dp, crc);
1964 if (ret)
1965 goto out;
1966
1967 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
1968 crc[0], crc[1], crc[2],
1969 crc[3], crc[4], crc[5]);
1970 goto out;
1971 }
1972 ret = -ENODEV;
1973out:
1974 drm_modeset_unlock_all(dev);
1975 return ret;
1976}
1977
Jesse Barnesec013e72013-08-20 10:29:23 +01001978static int i915_energy_uJ(struct seq_file *m, void *data)
1979{
1980 struct drm_info_node *node = m->private;
1981 struct drm_device *dev = node->minor->dev;
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 u64 power;
1984 u32 units;
1985
1986 if (INTEL_INFO(dev)->gen < 6)
1987 return -ENODEV;
1988
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001989 intel_runtime_pm_get(dev_priv);
1990
Jesse Barnesec013e72013-08-20 10:29:23 +01001991 rdmsrl(MSR_RAPL_POWER_UNIT, power);
1992 power = (power & 0x1f00) >> 8;
1993 units = 1000000 / (1 << power); /* convert to uJ */
1994 power = I915_READ(MCH_SECP_NRG_STTS);
1995 power *= units;
1996
Paulo Zanoni36623ef2014-02-21 13:52:23 -03001997 intel_runtime_pm_put(dev_priv);
1998
Jesse Barnesec013e72013-08-20 10:29:23 +01001999 seq_printf(m, "%llu", (long long unsigned)power);
Paulo Zanoni371db662013-08-19 13:18:10 -03002000
2001 return 0;
2002}
2003
2004static int i915_pc8_status(struct seq_file *m, void *unused)
2005{
2006 struct drm_info_node *node = (struct drm_info_node *) m->private;
2007 struct drm_device *dev = node->minor->dev;
2008 struct drm_i915_private *dev_priv = dev->dev_private;
2009
2010 if (!IS_HASWELL(dev)) {
2011 seq_puts(m, "not supported\n");
2012 return 0;
2013 }
2014
2015 mutex_lock(&dev_priv->pc8.lock);
2016 seq_printf(m, "Requirements met: %s\n",
2017 yesno(dev_priv->pc8.requirements_met));
Paulo Zanoni86c4ec02014-02-21 13:52:24 -03002018 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
Paulo Zanoni371db662013-08-19 13:18:10 -03002019 seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
2020 seq_printf(m, "IRQs disabled: %s\n",
2021 yesno(dev_priv->pc8.irqs_disabled));
2022 seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
2023 mutex_unlock(&dev_priv->pc8.lock);
2024
Jesse Barnesec013e72013-08-20 10:29:23 +01002025 return 0;
2026}
2027
Imre Deak1da51582013-11-25 17:15:35 +02002028static const char *power_domain_str(enum intel_display_power_domain domain)
2029{
2030 switch (domain) {
2031 case POWER_DOMAIN_PIPE_A:
2032 return "PIPE_A";
2033 case POWER_DOMAIN_PIPE_B:
2034 return "PIPE_B";
2035 case POWER_DOMAIN_PIPE_C:
2036 return "PIPE_C";
2037 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2038 return "PIPE_A_PANEL_FITTER";
2039 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2040 return "PIPE_B_PANEL_FITTER";
2041 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2042 return "PIPE_C_PANEL_FITTER";
2043 case POWER_DOMAIN_TRANSCODER_A:
2044 return "TRANSCODER_A";
2045 case POWER_DOMAIN_TRANSCODER_B:
2046 return "TRANSCODER_B";
2047 case POWER_DOMAIN_TRANSCODER_C:
2048 return "TRANSCODER_C";
2049 case POWER_DOMAIN_TRANSCODER_EDP:
2050 return "TRANSCODER_EDP";
Imre Deak319be8a2014-03-04 19:22:57 +02002051 case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2052 return "PORT_DDI_A_2_LANES";
2053 case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2054 return "PORT_DDI_A_4_LANES";
2055 case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2056 return "PORT_DDI_B_2_LANES";
2057 case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2058 return "PORT_DDI_B_4_LANES";
2059 case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2060 return "PORT_DDI_C_2_LANES";
2061 case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2062 return "PORT_DDI_C_4_LANES";
2063 case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2064 return "PORT_DDI_D_2_LANES";
2065 case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2066 return "PORT_DDI_D_4_LANES";
2067 case POWER_DOMAIN_PORT_DSI:
2068 return "PORT_DSI";
2069 case POWER_DOMAIN_PORT_CRT:
2070 return "PORT_CRT";
2071 case POWER_DOMAIN_PORT_OTHER:
2072 return "PORT_OTHER";
Imre Deak1da51582013-11-25 17:15:35 +02002073 case POWER_DOMAIN_VGA:
2074 return "VGA";
2075 case POWER_DOMAIN_AUDIO:
2076 return "AUDIO";
2077 case POWER_DOMAIN_INIT:
2078 return "INIT";
2079 default:
2080 WARN_ON(1);
2081 return "?";
2082 }
2083}
2084
2085static int i915_power_domain_info(struct seq_file *m, void *unused)
2086{
2087 struct drm_info_node *node = (struct drm_info_node *) m->private;
2088 struct drm_device *dev = node->minor->dev;
2089 struct drm_i915_private *dev_priv = dev->dev_private;
2090 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2091 int i;
2092
2093 mutex_lock(&power_domains->lock);
2094
2095 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2096 for (i = 0; i < power_domains->power_well_count; i++) {
2097 struct i915_power_well *power_well;
2098 enum intel_display_power_domain power_domain;
2099
2100 power_well = &power_domains->power_wells[i];
2101 seq_printf(m, "%-25s %d\n", power_well->name,
2102 power_well->count);
2103
2104 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2105 power_domain++) {
2106 if (!(BIT(power_domain) & power_well->domains))
2107 continue;
2108
2109 seq_printf(m, " %-23s %d\n",
2110 power_domain_str(power_domain),
2111 power_domains->domain_use_count[power_domain]);
2112 }
2113 }
2114
2115 mutex_unlock(&power_domains->lock);
2116
2117 return 0;
2118}
2119
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002120static void intel_seq_print_mode(struct seq_file *m, int tabs,
2121 struct drm_display_mode *mode)
2122{
2123 int i;
2124
2125 for (i = 0; i < tabs; i++)
2126 seq_putc(m, '\t');
2127
2128 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2129 mode->base.id, mode->name,
2130 mode->vrefresh, mode->clock,
2131 mode->hdisplay, mode->hsync_start,
2132 mode->hsync_end, mode->htotal,
2133 mode->vdisplay, mode->vsync_start,
2134 mode->vsync_end, mode->vtotal,
2135 mode->type, mode->flags);
2136}
2137
2138static void intel_encoder_info(struct seq_file *m,
2139 struct intel_crtc *intel_crtc,
2140 struct intel_encoder *intel_encoder)
2141{
2142 struct drm_info_node *node = (struct drm_info_node *) m->private;
2143 struct drm_device *dev = node->minor->dev;
2144 struct drm_crtc *crtc = &intel_crtc->base;
2145 struct intel_connector *intel_connector;
2146 struct drm_encoder *encoder;
2147
2148 encoder = &intel_encoder->base;
2149 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2150 encoder->base.id, drm_get_encoder_name(encoder));
2151 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2152 struct drm_connector *connector = &intel_connector->base;
2153 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2154 connector->base.id,
2155 drm_get_connector_name(connector),
2156 drm_get_connector_status_name(connector->status));
2157 if (connector->status == connector_status_connected) {
2158 struct drm_display_mode *mode = &crtc->mode;
2159 seq_printf(m, ", mode:\n");
2160 intel_seq_print_mode(m, 2, mode);
2161 } else {
2162 seq_putc(m, '\n');
2163 }
2164 }
2165}
2166
2167static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2168{
2169 struct drm_info_node *node = (struct drm_info_node *) m->private;
2170 struct drm_device *dev = node->minor->dev;
2171 struct drm_crtc *crtc = &intel_crtc->base;
2172 struct intel_encoder *intel_encoder;
2173
2174 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2175 crtc->fb->base.id, crtc->x, crtc->y,
2176 crtc->fb->width, crtc->fb->height);
2177 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2178 intel_encoder_info(m, intel_crtc, intel_encoder);
2179}
2180
2181static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2182{
2183 struct drm_display_mode *mode = panel->fixed_mode;
2184
2185 seq_printf(m, "\tfixed mode:\n");
2186 intel_seq_print_mode(m, 2, mode);
2187}
2188
2189static void intel_dp_info(struct seq_file *m,
2190 struct intel_connector *intel_connector)
2191{
2192 struct intel_encoder *intel_encoder = intel_connector->encoder;
2193 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2194
2195 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2196 seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2197 "no");
2198 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2199 intel_panel_info(m, &intel_connector->panel);
2200}
2201
2202static void intel_hdmi_info(struct seq_file *m,
2203 struct intel_connector *intel_connector)
2204{
2205 struct intel_encoder *intel_encoder = intel_connector->encoder;
2206 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2207
2208 seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2209 "no");
2210}
2211
2212static void intel_lvds_info(struct seq_file *m,
2213 struct intel_connector *intel_connector)
2214{
2215 intel_panel_info(m, &intel_connector->panel);
2216}
2217
2218static void intel_connector_info(struct seq_file *m,
2219 struct drm_connector *connector)
2220{
2221 struct intel_connector *intel_connector = to_intel_connector(connector);
2222 struct intel_encoder *intel_encoder = intel_connector->encoder;
Jesse Barnesf103fc72014-02-20 12:39:57 -08002223 struct drm_display_mode *mode;
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002224
2225 seq_printf(m, "connector %d: type %s, status: %s\n",
2226 connector->base.id, drm_get_connector_name(connector),
2227 drm_get_connector_status_name(connector->status));
2228 if (connector->status == connector_status_connected) {
2229 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2230 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2231 connector->display_info.width_mm,
2232 connector->display_info.height_mm);
2233 seq_printf(m, "\tsubpixel order: %s\n",
2234 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2235 seq_printf(m, "\tCEA rev: %d\n",
2236 connector->display_info.cea_rev);
2237 }
2238 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2239 intel_encoder->type == INTEL_OUTPUT_EDP)
2240 intel_dp_info(m, intel_connector);
2241 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2242 intel_hdmi_info(m, intel_connector);
2243 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2244 intel_lvds_info(m, intel_connector);
2245
Jesse Barnesf103fc72014-02-20 12:39:57 -08002246 seq_printf(m, "\tmodes:\n");
2247 list_for_each_entry(mode, &connector->modes, head)
2248 intel_seq_print_mode(m, 2, mode);
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08002249}
2250
2251static int i915_display_info(struct seq_file *m, void *unused)
2252{
2253 struct drm_info_node *node = (struct drm_info_node *) m->private;
2254 struct drm_device *dev = node->minor->dev;
2255 struct drm_crtc *crtc;
2256 struct drm_connector *connector;
2257
2258 drm_modeset_lock_all(dev);
2259 seq_printf(m, "CRTC info\n");
2260 seq_printf(m, "---------\n");
2261 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2263
2264 seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",
2265 crtc->base.id, pipe_name(intel_crtc->pipe),
2266 intel_crtc->active ? "yes" : "no");
2267 if (intel_crtc->active)
2268 intel_crtc_info(m, intel_crtc);
2269 }
2270
2271 seq_printf(m, "\n");
2272 seq_printf(m, "Connector info\n");
2273 seq_printf(m, "--------------\n");
2274 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2275 intel_connector_info(m, connector);
2276 }
2277 drm_modeset_unlock_all(dev);
2278
2279 return 0;
2280}
2281
Damien Lespiau07144422013-10-15 18:55:40 +01002282struct pipe_crc_info {
2283 const char *name;
2284 struct drm_device *dev;
2285 enum pipe pipe;
2286};
2287
2288static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
Shuang He8bf1e9f2013-10-15 18:55:27 +01002289{
Damien Lespiaube5c7a92013-10-15 18:55:41 +01002290 struct pipe_crc_info *info = inode->i_private;
2291 struct drm_i915_private *dev_priv = info->dev->dev_private;
2292 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2293
Daniel Vetter7eb1c492013-11-14 11:30:43 +01002294 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2295 return -ENODEV;
2296
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002297 spin_lock_irq(&pipe_crc->lock);
2298
2299 if (pipe_crc->opened) {
2300 spin_unlock_irq(&pipe_crc->lock);
Damien Lespiaube5c7a92013-10-15 18:55:41 +01002301 return -EBUSY; /* already open */
2302 }
2303
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002304 pipe_crc->opened = true;
Damien Lespiau07144422013-10-15 18:55:40 +01002305 filep->private_data = inode->i_private;
2306
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002307 spin_unlock_irq(&pipe_crc->lock);
2308
Damien Lespiau07144422013-10-15 18:55:40 +01002309 return 0;
2310}
2311
2312static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2313{
Damien Lespiaube5c7a92013-10-15 18:55:41 +01002314 struct pipe_crc_info *info = inode->i_private;
2315 struct drm_i915_private *dev_priv = info->dev->dev_private;
2316 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2317
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002318 spin_lock_irq(&pipe_crc->lock);
2319 pipe_crc->opened = false;
2320 spin_unlock_irq(&pipe_crc->lock);
Damien Lespiaube5c7a92013-10-15 18:55:41 +01002321
Damien Lespiau07144422013-10-15 18:55:40 +01002322 return 0;
2323}
2324
2325/* (6 fields, 8 chars each, space separated (5) + '\n') */
2326#define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
2327/* account for \'0' */
2328#define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
2329
2330static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2331{
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002332 assert_spin_locked(&pipe_crc->lock);
2333 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2334 INTEL_PIPE_CRC_ENTRIES_NR);
Damien Lespiau07144422013-10-15 18:55:40 +01002335}
Shuang He8bf1e9f2013-10-15 18:55:27 +01002336
Damien Lespiau07144422013-10-15 18:55:40 +01002337static ssize_t
2338i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2339 loff_t *pos)
2340{
2341 struct pipe_crc_info *info = filep->private_data;
2342 struct drm_device *dev = info->dev;
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2344 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2345 char buf[PIPE_CRC_BUFFER_LEN];
2346 int head, tail, n_entries, n;
2347 ssize_t bytes_read;
2348
2349 /*
2350 * Don't allow user space to provide buffers not big enough to hold
2351 * a line of data.
2352 */
2353 if (count < PIPE_CRC_LINE_LEN)
2354 return -EINVAL;
2355
2356 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2357 return 0;
2358
2359 /* nothing to read */
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002360 spin_lock_irq(&pipe_crc->lock);
Damien Lespiau07144422013-10-15 18:55:40 +01002361 while (pipe_crc_data_count(pipe_crc) == 0) {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002362 int ret;
Damien Lespiau07144422013-10-15 18:55:40 +01002363
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002364 if (filep->f_flags & O_NONBLOCK) {
2365 spin_unlock_irq(&pipe_crc->lock);
2366 return -EAGAIN;
2367 }
2368
2369 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2370 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2371 if (ret) {
2372 spin_unlock_irq(&pipe_crc->lock);
2373 return ret;
2374 }
Damien Lespiau07144422013-10-15 18:55:40 +01002375 }
2376
2377 /* We now have one or more entries to read */
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002378 head = pipe_crc->head;
2379 tail = pipe_crc->tail;
Damien Lespiau07144422013-10-15 18:55:40 +01002380 n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2381 count / PIPE_CRC_LINE_LEN);
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002382 spin_unlock_irq(&pipe_crc->lock);
2383
Damien Lespiau07144422013-10-15 18:55:40 +01002384 bytes_read = 0;
2385 n = 0;
2386 do {
2387 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2388 int ret;
2389
2390 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2391 "%8u %8x %8x %8x %8x %8x\n",
2392 entry->frame, entry->crc[0],
2393 entry->crc[1], entry->crc[2],
2394 entry->crc[3], entry->crc[4]);
2395
2396 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2397 buf, PIPE_CRC_LINE_LEN);
2398 if (ret == PIPE_CRC_LINE_LEN)
2399 return -EFAULT;
Damien Lespiaub2c88f52013-10-15 18:55:29 +01002400
2401 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2402 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
Damien Lespiau07144422013-10-15 18:55:40 +01002403 n++;
2404 } while (--n_entries);
Shuang He8bf1e9f2013-10-15 18:55:27 +01002405
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002406 spin_lock_irq(&pipe_crc->lock);
2407 pipe_crc->tail = tail;
2408 spin_unlock_irq(&pipe_crc->lock);
2409
Damien Lespiau07144422013-10-15 18:55:40 +01002410 return bytes_read;
2411}
2412
2413static const struct file_operations i915_pipe_crc_fops = {
2414 .owner = THIS_MODULE,
2415 .open = i915_pipe_crc_open,
2416 .read = i915_pipe_crc_read,
2417 .release = i915_pipe_crc_release,
2418};
2419
2420static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2421 {
2422 .name = "i915_pipe_A_crc",
2423 .pipe = PIPE_A,
2424 },
2425 {
2426 .name = "i915_pipe_B_crc",
2427 .pipe = PIPE_B,
2428 },
2429 {
2430 .name = "i915_pipe_C_crc",
2431 .pipe = PIPE_C,
2432 },
2433};
2434
2435static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2436 enum pipe pipe)
2437{
2438 struct drm_device *dev = minor->dev;
2439 struct dentry *ent;
2440 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2441
2442 info->dev = dev;
2443 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2444 &i915_pipe_crc_fops);
Wei Yongjunf3c5fe92013-12-16 14:13:25 +08002445 if (!ent)
2446 return -ENOMEM;
Damien Lespiau07144422013-10-15 18:55:40 +01002447
2448 return drm_add_fake_info_node(minor, ent, info);
Shuang He8bf1e9f2013-10-15 18:55:27 +01002449}
2450
Daniel Vettere8dfcf72013-10-16 11:51:54 +02002451static const char * const pipe_crc_sources[] = {
Daniel Vetter926321d2013-10-16 13:30:34 +02002452 "none",
2453 "plane1",
2454 "plane2",
2455 "pf",
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002456 "pipe",
Daniel Vetter3d099a02013-10-16 22:55:58 +02002457 "TV",
2458 "DP-B",
2459 "DP-C",
2460 "DP-D",
Daniel Vetter46a19182013-11-01 10:50:20 +01002461 "auto",
Daniel Vetter926321d2013-10-16 13:30:34 +02002462};
2463
2464static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2465{
2466 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2467 return pipe_crc_sources[source];
2468}
2469
Damien Lespiaubd9db022013-10-15 18:55:36 +01002470static int display_crc_ctl_show(struct seq_file *m, void *data)
Daniel Vetter926321d2013-10-16 13:30:34 +02002471{
2472 struct drm_device *dev = m->private;
2473 struct drm_i915_private *dev_priv = dev->dev_private;
2474 int i;
2475
2476 for (i = 0; i < I915_MAX_PIPES; i++)
2477 seq_printf(m, "%c %s\n", pipe_name(i),
2478 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2479
2480 return 0;
2481}
2482
Damien Lespiaubd9db022013-10-15 18:55:36 +01002483static int display_crc_ctl_open(struct inode *inode, struct file *file)
Daniel Vetter926321d2013-10-16 13:30:34 +02002484{
2485 struct drm_device *dev = inode->i_private;
2486
Damien Lespiaubd9db022013-10-15 18:55:36 +01002487 return single_open(file, display_crc_ctl_show, dev);
Daniel Vetter926321d2013-10-16 13:30:34 +02002488}
2489
Daniel Vetter46a19182013-11-01 10:50:20 +01002490static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
Daniel Vetter52f843f2013-10-21 17:26:38 +02002491 uint32_t *val)
2492{
Daniel Vetter46a19182013-11-01 10:50:20 +01002493 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2494 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2495
2496 switch (*source) {
Daniel Vetter52f843f2013-10-21 17:26:38 +02002497 case INTEL_PIPE_CRC_SOURCE_PIPE:
2498 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2499 break;
2500 case INTEL_PIPE_CRC_SOURCE_NONE:
2501 *val = 0;
2502 break;
2503 default:
2504 return -EINVAL;
2505 }
2506
2507 return 0;
2508}
2509
Daniel Vetter46a19182013-11-01 10:50:20 +01002510static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2511 enum intel_pipe_crc_source *source)
2512{
2513 struct intel_encoder *encoder;
2514 struct intel_crtc *crtc;
Daniel Vetter26756802013-11-01 10:50:23 +01002515 struct intel_digital_port *dig_port;
Daniel Vetter46a19182013-11-01 10:50:20 +01002516 int ret = 0;
2517
2518 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2519
2520 mutex_lock(&dev->mode_config.mutex);
2521 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2522 base.head) {
2523 if (!encoder->base.crtc)
2524 continue;
2525
2526 crtc = to_intel_crtc(encoder->base.crtc);
2527
2528 if (crtc->pipe != pipe)
2529 continue;
2530
2531 switch (encoder->type) {
2532 case INTEL_OUTPUT_TVOUT:
2533 *source = INTEL_PIPE_CRC_SOURCE_TV;
2534 break;
2535 case INTEL_OUTPUT_DISPLAYPORT:
2536 case INTEL_OUTPUT_EDP:
Daniel Vetter26756802013-11-01 10:50:23 +01002537 dig_port = enc_to_dig_port(&encoder->base);
2538 switch (dig_port->port) {
2539 case PORT_B:
2540 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2541 break;
2542 case PORT_C:
2543 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2544 break;
2545 case PORT_D:
2546 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2547 break;
2548 default:
2549 WARN(1, "nonexisting DP port %c\n",
2550 port_name(dig_port->port));
2551 break;
2552 }
Daniel Vetter46a19182013-11-01 10:50:20 +01002553 break;
2554 }
2555 }
2556 mutex_unlock(&dev->mode_config.mutex);
2557
2558 return ret;
2559}
2560
2561static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2562 enum pipe pipe,
2563 enum intel_pipe_crc_source *source,
Daniel Vetter7ac01292013-10-18 16:37:06 +02002564 uint32_t *val)
2565{
Daniel Vetter8d2f24c2013-11-01 10:50:22 +01002566 struct drm_i915_private *dev_priv = dev->dev_private;
2567 bool need_stable_symbols = false;
2568
Daniel Vetter46a19182013-11-01 10:50:20 +01002569 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2570 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2571 if (ret)
2572 return ret;
2573 }
2574
2575 switch (*source) {
Daniel Vetter7ac01292013-10-18 16:37:06 +02002576 case INTEL_PIPE_CRC_SOURCE_PIPE:
2577 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2578 break;
2579 case INTEL_PIPE_CRC_SOURCE_DP_B:
2580 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
Daniel Vetter8d2f24c2013-11-01 10:50:22 +01002581 need_stable_symbols = true;
Daniel Vetter7ac01292013-10-18 16:37:06 +02002582 break;
2583 case INTEL_PIPE_CRC_SOURCE_DP_C:
2584 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
Daniel Vetter8d2f24c2013-11-01 10:50:22 +01002585 need_stable_symbols = true;
Daniel Vetter7ac01292013-10-18 16:37:06 +02002586 break;
2587 case INTEL_PIPE_CRC_SOURCE_NONE:
2588 *val = 0;
2589 break;
2590 default:
2591 return -EINVAL;
2592 }
2593
Daniel Vetter8d2f24c2013-11-01 10:50:22 +01002594 /*
2595 * When the pipe CRC tap point is after the transcoders we need
2596 * to tweak symbol-level features to produce a deterministic series of
2597 * symbols for a given frame. We need to reset those features only once
2598 * a frame (instead of every nth symbol):
2599 * - DC-balance: used to ensure a better clock recovery from the data
2600 * link (SDVO)
2601 * - DisplayPort scrambling: used for EMI reduction
2602 */
2603 if (need_stable_symbols) {
2604 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2605
2606 WARN_ON(!IS_G4X(dev));
2607
2608 tmp |= DC_BALANCE_RESET_VLV;
2609 if (pipe == PIPE_A)
2610 tmp |= PIPE_A_SCRAMBLE_RESET;
2611 else
2612 tmp |= PIPE_B_SCRAMBLE_RESET;
2613
2614 I915_WRITE(PORT_DFT2_G4X, tmp);
2615 }
2616
Daniel Vetter7ac01292013-10-18 16:37:06 +02002617 return 0;
2618}
2619
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02002620static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
Daniel Vetter46a19182013-11-01 10:50:20 +01002621 enum pipe pipe,
2622 enum intel_pipe_crc_source *source,
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02002623 uint32_t *val)
2624{
Daniel Vetter84093602013-11-01 10:50:21 +01002625 struct drm_i915_private *dev_priv = dev->dev_private;
2626 bool need_stable_symbols = false;
2627
Daniel Vetter46a19182013-11-01 10:50:20 +01002628 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2629 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2630 if (ret)
2631 return ret;
2632 }
2633
2634 switch (*source) {
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02002635 case INTEL_PIPE_CRC_SOURCE_PIPE:
2636 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2637 break;
2638 case INTEL_PIPE_CRC_SOURCE_TV:
2639 if (!SUPPORTS_TV(dev))
2640 return -EINVAL;
2641 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2642 break;
2643 case INTEL_PIPE_CRC_SOURCE_DP_B:
2644 if (!IS_G4X(dev))
2645 return -EINVAL;
2646 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
Daniel Vetter84093602013-11-01 10:50:21 +01002647 need_stable_symbols = true;
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02002648 break;
2649 case INTEL_PIPE_CRC_SOURCE_DP_C:
2650 if (!IS_G4X(dev))
2651 return -EINVAL;
2652 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
Daniel Vetter84093602013-11-01 10:50:21 +01002653 need_stable_symbols = true;
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02002654 break;
2655 case INTEL_PIPE_CRC_SOURCE_DP_D:
2656 if (!IS_G4X(dev))
2657 return -EINVAL;
2658 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
Daniel Vetter84093602013-11-01 10:50:21 +01002659 need_stable_symbols = true;
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02002660 break;
2661 case INTEL_PIPE_CRC_SOURCE_NONE:
2662 *val = 0;
2663 break;
2664 default:
2665 return -EINVAL;
2666 }
2667
Daniel Vetter84093602013-11-01 10:50:21 +01002668 /*
2669 * When the pipe CRC tap point is after the transcoders we need
2670 * to tweak symbol-level features to produce a deterministic series of
2671 * symbols for a given frame. We need to reset those features only once
2672 * a frame (instead of every nth symbol):
2673 * - DC-balance: used to ensure a better clock recovery from the data
2674 * link (SDVO)
2675 * - DisplayPort scrambling: used for EMI reduction
2676 */
2677 if (need_stable_symbols) {
2678 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2679
2680 WARN_ON(!IS_G4X(dev));
2681
2682 I915_WRITE(PORT_DFT_I9XX,
2683 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2684
2685 if (pipe == PIPE_A)
2686 tmp |= PIPE_A_SCRAMBLE_RESET;
2687 else
2688 tmp |= PIPE_B_SCRAMBLE_RESET;
2689
2690 I915_WRITE(PORT_DFT2_G4X, tmp);
2691 }
2692
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02002693 return 0;
2694}
2695
Daniel Vetter8d2f24c2013-11-01 10:50:22 +01002696static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2697 enum pipe pipe)
2698{
2699 struct drm_i915_private *dev_priv = dev->dev_private;
2700 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2701
2702 if (pipe == PIPE_A)
2703 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2704 else
2705 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2706 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2707 tmp &= ~DC_BALANCE_RESET_VLV;
2708 I915_WRITE(PORT_DFT2_G4X, tmp);
2709
2710}
2711
Daniel Vetter84093602013-11-01 10:50:21 +01002712static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2713 enum pipe pipe)
2714{
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2717
2718 if (pipe == PIPE_A)
2719 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2720 else
2721 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2722 I915_WRITE(PORT_DFT2_G4X, tmp);
2723
2724 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2725 I915_WRITE(PORT_DFT_I9XX,
2726 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2727 }
2728}
2729
Daniel Vetter46a19182013-11-01 10:50:20 +01002730static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002731 uint32_t *val)
2732{
Daniel Vetter46a19182013-11-01 10:50:20 +01002733 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2734 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2735
2736 switch (*source) {
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002737 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2738 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2739 break;
2740 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2741 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2742 break;
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002743 case INTEL_PIPE_CRC_SOURCE_PIPE:
2744 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2745 break;
Daniel Vetter3d099a02013-10-16 22:55:58 +02002746 case INTEL_PIPE_CRC_SOURCE_NONE:
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002747 *val = 0;
2748 break;
Daniel Vetter3d099a02013-10-16 22:55:58 +02002749 default:
2750 return -EINVAL;
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002751 }
2752
2753 return 0;
2754}
2755
Daniel Vetter46a19182013-11-01 10:50:20 +01002756static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002757 uint32_t *val)
2758{
Daniel Vetter46a19182013-11-01 10:50:20 +01002759 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2760 *source = INTEL_PIPE_CRC_SOURCE_PF;
2761
2762 switch (*source) {
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002763 case INTEL_PIPE_CRC_SOURCE_PLANE1:
2764 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2765 break;
2766 case INTEL_PIPE_CRC_SOURCE_PLANE2:
2767 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2768 break;
2769 case INTEL_PIPE_CRC_SOURCE_PF:
2770 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2771 break;
Daniel Vetter3d099a02013-10-16 22:55:58 +02002772 case INTEL_PIPE_CRC_SOURCE_NONE:
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002773 *val = 0;
2774 break;
Daniel Vetter3d099a02013-10-16 22:55:58 +02002775 default:
2776 return -EINVAL;
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002777 }
2778
2779 return 0;
2780}
2781
Daniel Vetter926321d2013-10-16 13:30:34 +02002782static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2783 enum intel_pipe_crc_source source)
2784{
2785 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiaucc3da172013-10-15 18:55:31 +01002786 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
Borislav Petkov432f3342013-11-21 16:49:46 +01002787 u32 val = 0; /* shut up gcc */
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002788 int ret;
Daniel Vetter926321d2013-10-16 13:30:34 +02002789
Damien Lespiaucc3da172013-10-15 18:55:31 +01002790 if (pipe_crc->source == source)
2791 return 0;
2792
Damien Lespiauae676fc2013-10-15 18:55:32 +01002793 /* forbid changing the source without going back to 'none' */
2794 if (pipe_crc->source && source)
2795 return -EINVAL;
2796
Daniel Vetter52f843f2013-10-21 17:26:38 +02002797 if (IS_GEN2(dev))
Daniel Vetter46a19182013-11-01 10:50:20 +01002798 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
Daniel Vetter52f843f2013-10-21 17:26:38 +02002799 else if (INTEL_INFO(dev)->gen < 5)
Daniel Vetter46a19182013-11-01 10:50:20 +01002800 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
Daniel Vetter7ac01292013-10-18 16:37:06 +02002801 else if (IS_VALLEYVIEW(dev))
Daniel Vetter46a19182013-11-01 10:50:20 +01002802 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
Daniel Vetter4b79ebf2013-10-16 22:55:59 +02002803 else if (IS_GEN5(dev) || IS_GEN6(dev))
Daniel Vetter46a19182013-11-01 10:50:20 +01002804 ret = ilk_pipe_crc_ctl_reg(&source, &val);
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002805 else
Daniel Vetter46a19182013-11-01 10:50:20 +01002806 ret = ivb_pipe_crc_ctl_reg(&source, &val);
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002807
2808 if (ret != 0)
2809 return ret;
2810
Damien Lespiau4b584362013-10-15 18:55:33 +01002811 /* none -> real source transition */
2812 if (source) {
Damien Lespiau7cd6ccf2013-10-15 18:55:38 +01002813 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2814 pipe_name(pipe), pipe_crc_source_name(source));
2815
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01002816 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2817 INTEL_PIPE_CRC_ENTRIES_NR,
2818 GFP_KERNEL);
2819 if (!pipe_crc->entries)
2820 return -ENOMEM;
2821
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002822 spin_lock_irq(&pipe_crc->lock);
2823 pipe_crc->head = 0;
2824 pipe_crc->tail = 0;
2825 spin_unlock_irq(&pipe_crc->lock);
Damien Lespiau4b584362013-10-15 18:55:33 +01002826 }
2827
Damien Lespiaucc3da172013-10-15 18:55:31 +01002828 pipe_crc->source = source;
Daniel Vetter926321d2013-10-16 13:30:34 +02002829
Daniel Vetter926321d2013-10-16 13:30:34 +02002830 I915_WRITE(PIPE_CRC_CTL(pipe), val);
2831 POSTING_READ(PIPE_CRC_CTL(pipe));
2832
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01002833 /* real source -> none transition */
2834 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002835 struct intel_pipe_crc_entry *entries;
2836
Damien Lespiau7cd6ccf2013-10-15 18:55:38 +01002837 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2838 pipe_name(pipe));
2839
Daniel Vetterbcf17ab2013-10-16 22:55:50 +02002840 intel_wait_for_vblank(dev, pipe);
2841
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002842 spin_lock_irq(&pipe_crc->lock);
2843 entries = pipe_crc->entries;
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01002844 pipe_crc->entries = NULL;
Damien Lespiaud538bbd2013-10-21 14:29:30 +01002845 spin_unlock_irq(&pipe_crc->lock);
2846
2847 kfree(entries);
Daniel Vetter84093602013-11-01 10:50:21 +01002848
2849 if (IS_G4X(dev))
2850 g4x_undo_pipe_scramble_reset(dev, pipe);
Daniel Vetter8d2f24c2013-11-01 10:50:22 +01002851 else if (IS_VALLEYVIEW(dev))
2852 vlv_undo_pipe_scramble_reset(dev, pipe);
Damien Lespiaue5f75ac2013-10-15 18:55:34 +01002853 }
2854
Daniel Vetter926321d2013-10-16 13:30:34 +02002855 return 0;
2856}
2857
2858/*
2859 * Parse pipe CRC command strings:
Damien Lespiaub94dec82013-10-15 18:55:35 +01002860 * command: wsp* object wsp+ name wsp+ source wsp*
2861 * object: 'pipe'
2862 * name: (A | B | C)
Daniel Vetter926321d2013-10-16 13:30:34 +02002863 * source: (none | plane1 | plane2 | pf)
2864 * wsp: (#0x20 | #0x9 | #0xA)+
2865 *
2866 * eg.:
Damien Lespiaub94dec82013-10-15 18:55:35 +01002867 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
2868 * "pipe A none" -> Stop CRC
Daniel Vetter926321d2013-10-16 13:30:34 +02002869 */
Damien Lespiaubd9db022013-10-15 18:55:36 +01002870static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
Daniel Vetter926321d2013-10-16 13:30:34 +02002871{
2872 int n_words = 0;
2873
2874 while (*buf) {
2875 char *end;
2876
2877 /* skip leading white space */
2878 buf = skip_spaces(buf);
2879 if (!*buf)
2880 break; /* end of buffer */
2881
2882 /* find end of word */
2883 for (end = buf; *end && !isspace(*end); end++)
2884 ;
2885
2886 if (n_words == max_words) {
2887 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2888 max_words);
2889 return -EINVAL; /* ran out of words[] before bytes */
2890 }
2891
2892 if (*end)
2893 *end++ = '\0';
2894 words[n_words++] = buf;
2895 buf = end;
2896 }
2897
2898 return n_words;
2899}
2900
Damien Lespiaub94dec82013-10-15 18:55:35 +01002901enum intel_pipe_crc_object {
2902 PIPE_CRC_OBJECT_PIPE,
2903};
2904
Daniel Vettere8dfcf72013-10-16 11:51:54 +02002905static const char * const pipe_crc_objects[] = {
Damien Lespiaub94dec82013-10-15 18:55:35 +01002906 "pipe",
2907};
2908
2909static int
Damien Lespiaubd9db022013-10-15 18:55:36 +01002910display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
Damien Lespiaub94dec82013-10-15 18:55:35 +01002911{
2912 int i;
2913
2914 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2915 if (!strcmp(buf, pipe_crc_objects[i])) {
Damien Lespiaubd9db022013-10-15 18:55:36 +01002916 *o = i;
Damien Lespiaub94dec82013-10-15 18:55:35 +01002917 return 0;
2918 }
2919
2920 return -EINVAL;
2921}
2922
Damien Lespiaubd9db022013-10-15 18:55:36 +01002923static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
Daniel Vetter926321d2013-10-16 13:30:34 +02002924{
2925 const char name = buf[0];
2926
2927 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2928 return -EINVAL;
2929
2930 *pipe = name - 'A';
2931
2932 return 0;
2933}
2934
2935static int
Damien Lespiaubd9db022013-10-15 18:55:36 +01002936display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
Daniel Vetter926321d2013-10-16 13:30:34 +02002937{
2938 int i;
2939
2940 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2941 if (!strcmp(buf, pipe_crc_sources[i])) {
Damien Lespiaubd9db022013-10-15 18:55:36 +01002942 *s = i;
Daniel Vetter926321d2013-10-16 13:30:34 +02002943 return 0;
2944 }
2945
2946 return -EINVAL;
2947}
2948
Damien Lespiaubd9db022013-10-15 18:55:36 +01002949static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
Daniel Vetter926321d2013-10-16 13:30:34 +02002950{
Damien Lespiaub94dec82013-10-15 18:55:35 +01002951#define N_WORDS 3
Daniel Vetter926321d2013-10-16 13:30:34 +02002952 int n_words;
Damien Lespiaub94dec82013-10-15 18:55:35 +01002953 char *words[N_WORDS];
Daniel Vetter926321d2013-10-16 13:30:34 +02002954 enum pipe pipe;
Damien Lespiaub94dec82013-10-15 18:55:35 +01002955 enum intel_pipe_crc_object object;
Daniel Vetter926321d2013-10-16 13:30:34 +02002956 enum intel_pipe_crc_source source;
2957
Damien Lespiaubd9db022013-10-15 18:55:36 +01002958 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
Damien Lespiaub94dec82013-10-15 18:55:35 +01002959 if (n_words != N_WORDS) {
2960 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2961 N_WORDS);
Daniel Vetter926321d2013-10-16 13:30:34 +02002962 return -EINVAL;
2963 }
2964
Damien Lespiaubd9db022013-10-15 18:55:36 +01002965 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
Damien Lespiaub94dec82013-10-15 18:55:35 +01002966 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
Daniel Vetter926321d2013-10-16 13:30:34 +02002967 return -EINVAL;
2968 }
2969
Damien Lespiaubd9db022013-10-15 18:55:36 +01002970 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
Damien Lespiaub94dec82013-10-15 18:55:35 +01002971 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
2972 return -EINVAL;
2973 }
2974
Damien Lespiaubd9db022013-10-15 18:55:36 +01002975 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
Damien Lespiaub94dec82013-10-15 18:55:35 +01002976 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
Daniel Vetter926321d2013-10-16 13:30:34 +02002977 return -EINVAL;
2978 }
2979
2980 return pipe_crc_set_source(dev, pipe, source);
2981}
2982
Damien Lespiaubd9db022013-10-15 18:55:36 +01002983static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
2984 size_t len, loff_t *offp)
Daniel Vetter926321d2013-10-16 13:30:34 +02002985{
2986 struct seq_file *m = file->private_data;
2987 struct drm_device *dev = m->private;
2988 char *tmpbuf;
2989 int ret;
2990
2991 if (len == 0)
2992 return 0;
2993
2994 if (len > PAGE_SIZE - 1) {
2995 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2996 PAGE_SIZE);
2997 return -E2BIG;
2998 }
2999
3000 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3001 if (!tmpbuf)
3002 return -ENOMEM;
3003
3004 if (copy_from_user(tmpbuf, ubuf, len)) {
3005 ret = -EFAULT;
3006 goto out;
3007 }
3008 tmpbuf[len] = '\0';
3009
Damien Lespiaubd9db022013-10-15 18:55:36 +01003010 ret = display_crc_ctl_parse(dev, tmpbuf, len);
Daniel Vetter926321d2013-10-16 13:30:34 +02003011
3012out:
3013 kfree(tmpbuf);
3014 if (ret < 0)
3015 return ret;
3016
3017 *offp += len;
3018 return len;
3019}
3020
Damien Lespiaubd9db022013-10-15 18:55:36 +01003021static const struct file_operations i915_display_crc_ctl_fops = {
Daniel Vetter926321d2013-10-16 13:30:34 +02003022 .owner = THIS_MODULE,
Damien Lespiaubd9db022013-10-15 18:55:36 +01003023 .open = display_crc_ctl_open,
Daniel Vetter926321d2013-10-16 13:30:34 +02003024 .read = seq_read,
3025 .llseek = seq_lseek,
3026 .release = single_release,
Damien Lespiaubd9db022013-10-15 18:55:36 +01003027 .write = display_crc_ctl_write
Daniel Vetter926321d2013-10-16 13:30:34 +02003028};
3029
Ville Syrjälä369a1342014-01-22 14:36:08 +02003030static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
3031{
3032 struct drm_device *dev = m->private;
3033 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3034 int level;
3035
3036 drm_modeset_lock_all(dev);
3037
3038 for (level = 0; level < num_levels; level++) {
3039 unsigned int latency = wm[level];
3040
3041 /* WM1+ latency values in 0.5us units */
3042 if (level > 0)
3043 latency *= 5;
3044
3045 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3046 level, wm[level],
3047 latency / 10, latency % 10);
3048 }
3049
3050 drm_modeset_unlock_all(dev);
3051}
3052
3053static int pri_wm_latency_show(struct seq_file *m, void *data)
3054{
3055 struct drm_device *dev = m->private;
3056
3057 wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3058
3059 return 0;
3060}
3061
3062static int spr_wm_latency_show(struct seq_file *m, void *data)
3063{
3064 struct drm_device *dev = m->private;
3065
3066 wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3067
3068 return 0;
3069}
3070
3071static int cur_wm_latency_show(struct seq_file *m, void *data)
3072{
3073 struct drm_device *dev = m->private;
3074
3075 wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3076
3077 return 0;
3078}
3079
3080static int pri_wm_latency_open(struct inode *inode, struct file *file)
3081{
3082 struct drm_device *dev = inode->i_private;
3083
3084 if (!HAS_PCH_SPLIT(dev))
3085 return -ENODEV;
3086
3087 return single_open(file, pri_wm_latency_show, dev);
3088}
3089
3090static int spr_wm_latency_open(struct inode *inode, struct file *file)
3091{
3092 struct drm_device *dev = inode->i_private;
3093
3094 if (!HAS_PCH_SPLIT(dev))
3095 return -ENODEV;
3096
3097 return single_open(file, spr_wm_latency_show, dev);
3098}
3099
3100static int cur_wm_latency_open(struct inode *inode, struct file *file)
3101{
3102 struct drm_device *dev = inode->i_private;
3103
3104 if (!HAS_PCH_SPLIT(dev))
3105 return -ENODEV;
3106
3107 return single_open(file, cur_wm_latency_show, dev);
3108}
3109
3110static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3111 size_t len, loff_t *offp, uint16_t wm[5])
3112{
3113 struct seq_file *m = file->private_data;
3114 struct drm_device *dev = m->private;
3115 uint16_t new[5] = { 0 };
3116 int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3117 int level;
3118 int ret;
3119 char tmp[32];
3120
3121 if (len >= sizeof(tmp))
3122 return -EINVAL;
3123
3124 if (copy_from_user(tmp, ubuf, len))
3125 return -EFAULT;
3126
3127 tmp[len] = '\0';
3128
3129 ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3130 if (ret != num_levels)
3131 return -EINVAL;
3132
3133 drm_modeset_lock_all(dev);
3134
3135 for (level = 0; level < num_levels; level++)
3136 wm[level] = new[level];
3137
3138 drm_modeset_unlock_all(dev);
3139
3140 return len;
3141}
3142
3143
3144static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3145 size_t len, loff_t *offp)
3146{
3147 struct seq_file *m = file->private_data;
3148 struct drm_device *dev = m->private;
3149
3150 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3151}
3152
3153static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3154 size_t len, loff_t *offp)
3155{
3156 struct seq_file *m = file->private_data;
3157 struct drm_device *dev = m->private;
3158
3159 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3160}
3161
3162static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3163 size_t len, loff_t *offp)
3164{
3165 struct seq_file *m = file->private_data;
3166 struct drm_device *dev = m->private;
3167
3168 return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3169}
3170
3171static const struct file_operations i915_pri_wm_latency_fops = {
3172 .owner = THIS_MODULE,
3173 .open = pri_wm_latency_open,
3174 .read = seq_read,
3175 .llseek = seq_lseek,
3176 .release = single_release,
3177 .write = pri_wm_latency_write
3178};
3179
3180static const struct file_operations i915_spr_wm_latency_fops = {
3181 .owner = THIS_MODULE,
3182 .open = spr_wm_latency_open,
3183 .read = seq_read,
3184 .llseek = seq_lseek,
3185 .release = single_release,
3186 .write = spr_wm_latency_write
3187};
3188
3189static const struct file_operations i915_cur_wm_latency_fops = {
3190 .owner = THIS_MODULE,
3191 .open = cur_wm_latency_open,
3192 .read = seq_read,
3193 .llseek = seq_lseek,
3194 .release = single_release,
3195 .write = cur_wm_latency_write
3196};
3197
Kees Cook647416f2013-03-10 14:10:06 -07003198static int
3199i915_wedged_get(void *data, u64 *val)
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003200{
Kees Cook647416f2013-03-10 14:10:06 -07003201 struct drm_device *dev = data;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003202 drm_i915_private_t *dev_priv = dev->dev_private;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003203
Kees Cook647416f2013-03-10 14:10:06 -07003204 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003205
Kees Cook647416f2013-03-10 14:10:06 -07003206 return 0;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003207}
3208
Kees Cook647416f2013-03-10 14:10:06 -07003209static int
3210i915_wedged_set(void *data, u64 val)
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003211{
Kees Cook647416f2013-03-10 14:10:06 -07003212 struct drm_device *dev = data;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003213
Mika Kuoppala58174462014-02-25 17:11:26 +02003214 i915_handle_error(dev, val,
3215 "Manually setting wedged to %llu", val);
Kees Cook647416f2013-03-10 14:10:06 -07003216 return 0;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003217}
3218
Kees Cook647416f2013-03-10 14:10:06 -07003219DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3220 i915_wedged_get, i915_wedged_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +03003221 "%llu\n");
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003222
Kees Cook647416f2013-03-10 14:10:06 -07003223static int
3224i915_ring_stop_get(void *data, u64 *val)
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003225{
Kees Cook647416f2013-03-10 14:10:06 -07003226 struct drm_device *dev = data;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003227 drm_i915_private_t *dev_priv = dev->dev_private;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003228
Kees Cook647416f2013-03-10 14:10:06 -07003229 *val = dev_priv->gpu_error.stop_rings;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003230
Kees Cook647416f2013-03-10 14:10:06 -07003231 return 0;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003232}
3233
Kees Cook647416f2013-03-10 14:10:06 -07003234static int
3235i915_ring_stop_set(void *data, u64 val)
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003236{
Kees Cook647416f2013-03-10 14:10:06 -07003237 struct drm_device *dev = data;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003238 struct drm_i915_private *dev_priv = dev->dev_private;
Kees Cook647416f2013-03-10 14:10:06 -07003239 int ret;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003240
Kees Cook647416f2013-03-10 14:10:06 -07003241 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003242
Daniel Vetter22bcfc62012-08-09 15:07:02 +02003243 ret = mutex_lock_interruptible(&dev->struct_mutex);
3244 if (ret)
3245 return ret;
3246
Daniel Vetter99584db2012-11-14 17:14:04 +01003247 dev_priv->gpu_error.stop_rings = val;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003248 mutex_unlock(&dev->struct_mutex);
3249
Kees Cook647416f2013-03-10 14:10:06 -07003250 return 0;
Daniel Vettere5eb3d62012-05-03 14:48:16 +02003251}
3252
Kees Cook647416f2013-03-10 14:10:06 -07003253DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3254 i915_ring_stop_get, i915_ring_stop_set,
3255 "0x%08llx\n");
Daniel Vetterd5442302012-04-27 15:17:40 +02003256
Chris Wilson094f9a52013-09-25 17:34:55 +01003257static int
3258i915_ring_missed_irq_get(void *data, u64 *val)
3259{
3260 struct drm_device *dev = data;
3261 struct drm_i915_private *dev_priv = dev->dev_private;
3262
3263 *val = dev_priv->gpu_error.missed_irq_rings;
3264 return 0;
3265}
3266
3267static int
3268i915_ring_missed_irq_set(void *data, u64 val)
3269{
3270 struct drm_device *dev = data;
3271 struct drm_i915_private *dev_priv = dev->dev_private;
3272 int ret;
3273
3274 /* Lock against concurrent debugfs callers */
3275 ret = mutex_lock_interruptible(&dev->struct_mutex);
3276 if (ret)
3277 return ret;
3278 dev_priv->gpu_error.missed_irq_rings = val;
3279 mutex_unlock(&dev->struct_mutex);
3280
3281 return 0;
3282}
3283
3284DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3285 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3286 "0x%08llx\n");
3287
3288static int
3289i915_ring_test_irq_get(void *data, u64 *val)
3290{
3291 struct drm_device *dev = data;
3292 struct drm_i915_private *dev_priv = dev->dev_private;
3293
3294 *val = dev_priv->gpu_error.test_irq_rings;
3295
3296 return 0;
3297}
3298
3299static int
3300i915_ring_test_irq_set(void *data, u64 val)
3301{
3302 struct drm_device *dev = data;
3303 struct drm_i915_private *dev_priv = dev->dev_private;
3304 int ret;
3305
3306 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3307
3308 /* Lock against concurrent debugfs callers */
3309 ret = mutex_lock_interruptible(&dev->struct_mutex);
3310 if (ret)
3311 return ret;
3312
3313 dev_priv->gpu_error.test_irq_rings = val;
3314 mutex_unlock(&dev->struct_mutex);
3315
3316 return 0;
3317}
3318
3319DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3320 i915_ring_test_irq_get, i915_ring_test_irq_set,
3321 "0x%08llx\n");
3322
Chris Wilsondd624af2013-01-15 12:39:35 +00003323#define DROP_UNBOUND 0x1
3324#define DROP_BOUND 0x2
3325#define DROP_RETIRE 0x4
3326#define DROP_ACTIVE 0x8
3327#define DROP_ALL (DROP_UNBOUND | \
3328 DROP_BOUND | \
3329 DROP_RETIRE | \
3330 DROP_ACTIVE)
Kees Cook647416f2013-03-10 14:10:06 -07003331static int
3332i915_drop_caches_get(void *data, u64 *val)
Chris Wilsondd624af2013-01-15 12:39:35 +00003333{
Kees Cook647416f2013-03-10 14:10:06 -07003334 *val = DROP_ALL;
Chris Wilsondd624af2013-01-15 12:39:35 +00003335
Kees Cook647416f2013-03-10 14:10:06 -07003336 return 0;
Chris Wilsondd624af2013-01-15 12:39:35 +00003337}
3338
Kees Cook647416f2013-03-10 14:10:06 -07003339static int
3340i915_drop_caches_set(void *data, u64 val)
Chris Wilsondd624af2013-01-15 12:39:35 +00003341{
Kees Cook647416f2013-03-10 14:10:06 -07003342 struct drm_device *dev = data;
Chris Wilsondd624af2013-01-15 12:39:35 +00003343 struct drm_i915_private *dev_priv = dev->dev_private;
3344 struct drm_i915_gem_object *obj, *next;
Ben Widawskyca191b12013-07-31 17:00:14 -07003345 struct i915_address_space *vm;
3346 struct i915_vma *vma, *x;
Kees Cook647416f2013-03-10 14:10:06 -07003347 int ret;
Chris Wilsondd624af2013-01-15 12:39:35 +00003348
Ben Widawsky2f9fe5f2013-11-25 09:54:37 -08003349 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
Chris Wilsondd624af2013-01-15 12:39:35 +00003350
3351 /* No need to check and wait for gpu resets, only libdrm auto-restarts
3352 * on ioctls on -EAGAIN. */
3353 ret = mutex_lock_interruptible(&dev->struct_mutex);
3354 if (ret)
3355 return ret;
3356
3357 if (val & DROP_ACTIVE) {
3358 ret = i915_gpu_idle(dev);
3359 if (ret)
3360 goto unlock;
3361 }
3362
3363 if (val & (DROP_RETIRE | DROP_ACTIVE))
3364 i915_gem_retire_requests(dev);
3365
3366 if (val & DROP_BOUND) {
Ben Widawskyca191b12013-07-31 17:00:14 -07003367 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3368 list_for_each_entry_safe(vma, x, &vm->inactive_list,
3369 mm_list) {
Ben Widawskyd7f46fc2013-12-06 14:10:55 -08003370 if (vma->pin_count)
Ben Widawskyca191b12013-07-31 17:00:14 -07003371 continue;
Ben Widawsky31a46c92013-07-31 16:59:55 -07003372
Ben Widawskyca191b12013-07-31 17:00:14 -07003373 ret = i915_vma_unbind(vma);
3374 if (ret)
3375 goto unlock;
3376 }
Ben Widawsky31a46c92013-07-31 16:59:55 -07003377 }
Chris Wilsondd624af2013-01-15 12:39:35 +00003378 }
3379
3380 if (val & DROP_UNBOUND) {
Ben Widawsky35c20a62013-05-31 11:28:48 -07003381 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3382 global_list)
Chris Wilsondd624af2013-01-15 12:39:35 +00003383 if (obj->pages_pin_count == 0) {
3384 ret = i915_gem_object_put_pages(obj);
3385 if (ret)
3386 goto unlock;
3387 }
3388 }
3389
3390unlock:
3391 mutex_unlock(&dev->struct_mutex);
3392
Kees Cook647416f2013-03-10 14:10:06 -07003393 return ret;
Chris Wilsondd624af2013-01-15 12:39:35 +00003394}
3395
Kees Cook647416f2013-03-10 14:10:06 -07003396DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3397 i915_drop_caches_get, i915_drop_caches_set,
3398 "0x%08llx\n");
Chris Wilsondd624af2013-01-15 12:39:35 +00003399
Kees Cook647416f2013-03-10 14:10:06 -07003400static int
3401i915_max_freq_get(void *data, u64 *val)
Jesse Barnes358733e2011-07-27 11:53:01 -07003402{
Kees Cook647416f2013-03-10 14:10:06 -07003403 struct drm_device *dev = data;
Jesse Barnes358733e2011-07-27 11:53:01 -07003404 drm_i915_private_t *dev_priv = dev->dev_private;
Kees Cook647416f2013-03-10 14:10:06 -07003405 int ret;
Daniel Vetter004777c2012-08-09 15:07:01 +02003406
3407 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3408 return -ENODEV;
3409
Tom O'Rourke5c9669c2013-09-16 14:56:43 -07003410 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3411
Jesse Barnes4fc688c2012-11-02 11:14:01 -07003412 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Daniel Vetter004777c2012-08-09 15:07:01 +02003413 if (ret)
3414 return ret;
Jesse Barnes358733e2011-07-27 11:53:01 -07003415
Jesse Barnes0a073b82013-04-17 15:54:58 -07003416 if (IS_VALLEYVIEW(dev))
Ville Syrjälä2ec38152013-11-05 22:42:29 +02003417 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
Jesse Barnes0a073b82013-04-17 15:54:58 -07003418 else
3419 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07003420 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes358733e2011-07-27 11:53:01 -07003421
Kees Cook647416f2013-03-10 14:10:06 -07003422 return 0;
Jesse Barnes358733e2011-07-27 11:53:01 -07003423}
3424
Kees Cook647416f2013-03-10 14:10:06 -07003425static int
3426i915_max_freq_set(void *data, u64 val)
Jesse Barnes358733e2011-07-27 11:53:01 -07003427{
Kees Cook647416f2013-03-10 14:10:06 -07003428 struct drm_device *dev = data;
Jesse Barnes358733e2011-07-27 11:53:01 -07003429 struct drm_i915_private *dev_priv = dev->dev_private;
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06003430 u32 rp_state_cap, hw_max, hw_min;
Kees Cook647416f2013-03-10 14:10:06 -07003431 int ret;
Daniel Vetter004777c2012-08-09 15:07:01 +02003432
3433 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3434 return -ENODEV;
Jesse Barnes358733e2011-07-27 11:53:01 -07003435
Tom O'Rourke5c9669c2013-09-16 14:56:43 -07003436 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3437
Kees Cook647416f2013-03-10 14:10:06 -07003438 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
Jesse Barnes358733e2011-07-27 11:53:01 -07003439
Jesse Barnes4fc688c2012-11-02 11:14:01 -07003440 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Daniel Vetter004777c2012-08-09 15:07:01 +02003441 if (ret)
3442 return ret;
3443
Jesse Barnes358733e2011-07-27 11:53:01 -07003444 /*
3445 * Turbo will still be enabled, but won't go above the set value.
3446 */
Jesse Barnes0a073b82013-04-17 15:54:58 -07003447 if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä2ec38152013-11-05 22:42:29 +02003448 val = vlv_freq_opcode(dev_priv, val);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06003449
3450 hw_max = valleyview_rps_max_freq(dev_priv);
3451 hw_min = valleyview_rps_min_freq(dev_priv);
Jesse Barnes0a073b82013-04-17 15:54:58 -07003452 } else {
3453 do_div(val, GT_FREQUENCY_MULTIPLIER);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06003454
3455 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3456 hw_max = dev_priv->rps.hw_max;
3457 hw_min = (rp_state_cap >> 16) & 0xff;
Jesse Barnes0a073b82013-04-17 15:54:58 -07003458 }
3459
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06003460 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_delay) {
3461 mutex_unlock(&dev_priv->rps.hw_lock);
3462 return -EINVAL;
3463 }
3464
3465 dev_priv->rps.max_delay = val;
3466
3467 if (IS_VALLEYVIEW(dev))
3468 valleyview_set_rps(dev, val);
3469 else
3470 gen6_set_rps(dev, val);
3471
Jesse Barnes4fc688c2012-11-02 11:14:01 -07003472 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes358733e2011-07-27 11:53:01 -07003473
Kees Cook647416f2013-03-10 14:10:06 -07003474 return 0;
Jesse Barnes358733e2011-07-27 11:53:01 -07003475}
3476
Kees Cook647416f2013-03-10 14:10:06 -07003477DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3478 i915_max_freq_get, i915_max_freq_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +03003479 "%llu\n");
Jesse Barnes358733e2011-07-27 11:53:01 -07003480
Kees Cook647416f2013-03-10 14:10:06 -07003481static int
3482i915_min_freq_get(void *data, u64 *val)
Jesse Barnes1523c312012-05-25 12:34:54 -07003483{
Kees Cook647416f2013-03-10 14:10:06 -07003484 struct drm_device *dev = data;
Jesse Barnes1523c312012-05-25 12:34:54 -07003485 drm_i915_private_t *dev_priv = dev->dev_private;
Kees Cook647416f2013-03-10 14:10:06 -07003486 int ret;
Daniel Vetter004777c2012-08-09 15:07:01 +02003487
3488 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3489 return -ENODEV;
3490
Tom O'Rourke5c9669c2013-09-16 14:56:43 -07003491 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3492
Jesse Barnes4fc688c2012-11-02 11:14:01 -07003493 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Daniel Vetter004777c2012-08-09 15:07:01 +02003494 if (ret)
3495 return ret;
Jesse Barnes1523c312012-05-25 12:34:54 -07003496
Jesse Barnes0a073b82013-04-17 15:54:58 -07003497 if (IS_VALLEYVIEW(dev))
Ville Syrjälä2ec38152013-11-05 22:42:29 +02003498 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
Jesse Barnes0a073b82013-04-17 15:54:58 -07003499 else
3500 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
Jesse Barnes4fc688c2012-11-02 11:14:01 -07003501 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes1523c312012-05-25 12:34:54 -07003502
Kees Cook647416f2013-03-10 14:10:06 -07003503 return 0;
Jesse Barnes1523c312012-05-25 12:34:54 -07003504}
3505
Kees Cook647416f2013-03-10 14:10:06 -07003506static int
3507i915_min_freq_set(void *data, u64 val)
Jesse Barnes1523c312012-05-25 12:34:54 -07003508{
Kees Cook647416f2013-03-10 14:10:06 -07003509 struct drm_device *dev = data;
Jesse Barnes1523c312012-05-25 12:34:54 -07003510 struct drm_i915_private *dev_priv = dev->dev_private;
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06003511 u32 rp_state_cap, hw_max, hw_min;
Kees Cook647416f2013-03-10 14:10:06 -07003512 int ret;
Daniel Vetter004777c2012-08-09 15:07:01 +02003513
3514 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3515 return -ENODEV;
Jesse Barnes1523c312012-05-25 12:34:54 -07003516
Tom O'Rourke5c9669c2013-09-16 14:56:43 -07003517 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3518
Kees Cook647416f2013-03-10 14:10:06 -07003519 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
Jesse Barnes1523c312012-05-25 12:34:54 -07003520
Jesse Barnes4fc688c2012-11-02 11:14:01 -07003521 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
Daniel Vetter004777c2012-08-09 15:07:01 +02003522 if (ret)
3523 return ret;
3524
Jesse Barnes1523c312012-05-25 12:34:54 -07003525 /*
3526 * Turbo will still be enabled, but won't go below the set value.
3527 */
Jesse Barnes0a073b82013-04-17 15:54:58 -07003528 if (IS_VALLEYVIEW(dev)) {
Ville Syrjälä2ec38152013-11-05 22:42:29 +02003529 val = vlv_freq_opcode(dev_priv, val);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06003530
3531 hw_max = valleyview_rps_max_freq(dev_priv);
3532 hw_min = valleyview_rps_min_freq(dev_priv);
Jesse Barnes0a073b82013-04-17 15:54:58 -07003533 } else {
3534 do_div(val, GT_FREQUENCY_MULTIPLIER);
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06003535
3536 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3537 hw_max = dev_priv->rps.hw_max;
3538 hw_min = (rp_state_cap >> 16) & 0xff;
Jesse Barnes0a073b82013-04-17 15:54:58 -07003539 }
Jeff McGeedd0a1aa2014-02-04 11:32:31 -06003540
3541 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
3542 mutex_unlock(&dev_priv->rps.hw_lock);
3543 return -EINVAL;
3544 }
3545
3546 dev_priv->rps.min_delay = val;
3547
3548 if (IS_VALLEYVIEW(dev))
3549 valleyview_set_rps(dev, val);
3550 else
3551 gen6_set_rps(dev, val);
3552
Jesse Barnes4fc688c2012-11-02 11:14:01 -07003553 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes1523c312012-05-25 12:34:54 -07003554
Kees Cook647416f2013-03-10 14:10:06 -07003555 return 0;
Jesse Barnes1523c312012-05-25 12:34:54 -07003556}
3557
Kees Cook647416f2013-03-10 14:10:06 -07003558DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3559 i915_min_freq_get, i915_min_freq_set,
Mika Kuoppala3a3b4f92013-04-12 12:10:05 +03003560 "%llu\n");
Jesse Barnes1523c312012-05-25 12:34:54 -07003561
Kees Cook647416f2013-03-10 14:10:06 -07003562static int
3563i915_cache_sharing_get(void *data, u64 *val)
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003564{
Kees Cook647416f2013-03-10 14:10:06 -07003565 struct drm_device *dev = data;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003566 drm_i915_private_t *dev_priv = dev->dev_private;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003567 u32 snpcr;
Kees Cook647416f2013-03-10 14:10:06 -07003568 int ret;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003569
Daniel Vetter004777c2012-08-09 15:07:01 +02003570 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3571 return -ENODEV;
3572
Daniel Vetter22bcfc62012-08-09 15:07:02 +02003573 ret = mutex_lock_interruptible(&dev->struct_mutex);
3574 if (ret)
3575 return ret;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003576 intel_runtime_pm_get(dev_priv);
Daniel Vetter22bcfc62012-08-09 15:07:02 +02003577
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003578 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003579
3580 intel_runtime_pm_put(dev_priv);
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003581 mutex_unlock(&dev_priv->dev->struct_mutex);
3582
Kees Cook647416f2013-03-10 14:10:06 -07003583 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003584
Kees Cook647416f2013-03-10 14:10:06 -07003585 return 0;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003586}
3587
Kees Cook647416f2013-03-10 14:10:06 -07003588static int
3589i915_cache_sharing_set(void *data, u64 val)
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003590{
Kees Cook647416f2013-03-10 14:10:06 -07003591 struct drm_device *dev = data;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003592 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003593 u32 snpcr;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003594
Daniel Vetter004777c2012-08-09 15:07:01 +02003595 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3596 return -ENODEV;
3597
Kees Cook647416f2013-03-10 14:10:06 -07003598 if (val > 3)
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003599 return -EINVAL;
3600
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003601 intel_runtime_pm_get(dev_priv);
Kees Cook647416f2013-03-10 14:10:06 -07003602 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003603
3604 /* Update the cache sharing policy here as well */
3605 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3606 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3607 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3608 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3609
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003610 intel_runtime_pm_put(dev_priv);
Kees Cook647416f2013-03-10 14:10:06 -07003611 return 0;
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003612}
3613
Kees Cook647416f2013-03-10 14:10:06 -07003614DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3615 i915_cache_sharing_get, i915_cache_sharing_set,
3616 "%llu\n");
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003617
Ben Widawsky6d794d42011-04-25 11:25:56 -07003618static int i915_forcewake_open(struct inode *inode, struct file *file)
3619{
3620 struct drm_device *dev = inode->i_private;
3621 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky6d794d42011-04-25 11:25:56 -07003622
Daniel Vetter075edca2012-01-24 09:44:28 +01003623 if (INTEL_INFO(dev)->gen < 6)
Ben Widawsky6d794d42011-04-25 11:25:56 -07003624 return 0;
3625
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003626 intel_runtime_pm_get(dev_priv);
Deepak Sc8d9a592013-11-23 14:55:42 +05303627 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
Ben Widawsky6d794d42011-04-25 11:25:56 -07003628
3629 return 0;
3630}
3631
Ben Widawskyc43b5632012-04-16 14:07:40 -07003632static int i915_forcewake_release(struct inode *inode, struct file *file)
Ben Widawsky6d794d42011-04-25 11:25:56 -07003633{
3634 struct drm_device *dev = inode->i_private;
3635 struct drm_i915_private *dev_priv = dev->dev_private;
3636
Daniel Vetter075edca2012-01-24 09:44:28 +01003637 if (INTEL_INFO(dev)->gen < 6)
Ben Widawsky6d794d42011-04-25 11:25:56 -07003638 return 0;
3639
Deepak Sc8d9a592013-11-23 14:55:42 +05303640 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003641 intel_runtime_pm_put(dev_priv);
Ben Widawsky6d794d42011-04-25 11:25:56 -07003642
3643 return 0;
3644}
3645
3646static const struct file_operations i915_forcewake_fops = {
3647 .owner = THIS_MODULE,
3648 .open = i915_forcewake_open,
3649 .release = i915_forcewake_release,
3650};
3651
3652static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3653{
3654 struct drm_device *dev = minor->dev;
3655 struct dentry *ent;
3656
3657 ent = debugfs_create_file("i915_forcewake_user",
Ben Widawsky8eb57292011-05-11 15:10:58 -07003658 S_IRUSR,
Ben Widawsky6d794d42011-04-25 11:25:56 -07003659 root, dev,
3660 &i915_forcewake_fops);
Wei Yongjunf3c5fe92013-12-16 14:13:25 +08003661 if (!ent)
3662 return -ENOMEM;
Ben Widawsky6d794d42011-04-25 11:25:56 -07003663
Ben Widawsky8eb57292011-05-11 15:10:58 -07003664 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
Ben Widawsky6d794d42011-04-25 11:25:56 -07003665}
3666
Daniel Vetter6a9c3082011-12-14 13:57:11 +01003667static int i915_debugfs_create(struct dentry *root,
3668 struct drm_minor *minor,
3669 const char *name,
3670 const struct file_operations *fops)
Jesse Barnes358733e2011-07-27 11:53:01 -07003671{
3672 struct drm_device *dev = minor->dev;
3673 struct dentry *ent;
3674
Daniel Vetter6a9c3082011-12-14 13:57:11 +01003675 ent = debugfs_create_file(name,
Jesse Barnes358733e2011-07-27 11:53:01 -07003676 S_IRUGO | S_IWUSR,
3677 root, dev,
Daniel Vetter6a9c3082011-12-14 13:57:11 +01003678 fops);
Wei Yongjunf3c5fe92013-12-16 14:13:25 +08003679 if (!ent)
3680 return -ENOMEM;
Jesse Barnes358733e2011-07-27 11:53:01 -07003681
Daniel Vetter6a9c3082011-12-14 13:57:11 +01003682 return drm_add_fake_info_node(minor, ent, fops);
Jesse Barnes07b7ddd2011-08-03 11:28:44 -07003683}
3684
Lespiau, Damien06c5bf82013-10-17 19:09:56 +01003685static const struct drm_info_list i915_debugfs_list[] = {
Chris Wilson311bd682011-01-13 19:06:50 +00003686 {"i915_capabilities", i915_capabilities, 0},
Chris Wilson73aa8082010-09-30 11:46:12 +01003687 {"i915_gem_objects", i915_gem_object_info, 0},
Chris Wilson08c18322011-01-10 00:00:24 +00003688 {"i915_gem_gtt", i915_gem_gtt_info, 0},
Chris Wilson1b502472012-04-24 15:47:30 +01003689 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
Ben Gamari433e12f2009-02-17 20:08:51 -05003690 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
Ben Gamari433e12f2009-02-17 20:08:51 -05003691 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
Chris Wilson6d2b8882013-08-07 18:30:54 +01003692 {"i915_gem_stolen", i915_gem_stolen_list_info },
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01003693 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
Ben Gamari20172632009-02-17 20:08:50 -05003694 {"i915_gem_request", i915_gem_request_info, 0},
3695 {"i915_gem_seqno", i915_gem_seqno_info, 0},
Chris Wilsona6172a82009-02-11 14:26:38 +00003696 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
Ben Gamari20172632009-02-17 20:08:50 -05003697 {"i915_gem_interrupt", i915_interrupt_info, 0},
Chris Wilson1ec14ad2010-12-04 11:30:53 +00003698 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3699 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3700 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
Xiang, Haihao9010ebf2013-05-29 09:22:36 -07003701 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
Jesse Barnesf97108d2010-01-29 11:27:07 -08003702 {"i915_rstdby_delays", i915_rstdby_delays, 0},
3703 {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
3704 {"i915_delayfreq_table", i915_delayfreq_table, 0},
3705 {"i915_inttoext_table", i915_inttoext_table, 0},
3706 {"i915_drpc_info", i915_drpc_info, 0},
Jesse Barnes7648fa92010-05-20 14:28:11 -07003707 {"i915_emon_status", i915_emon_status, 0},
Jesse Barnes23b2f8b2011-06-28 13:04:16 -07003708 {"i915_ring_freq_table", i915_ring_freq_table, 0},
Jesse Barnes7648fa92010-05-20 14:28:11 -07003709 {"i915_gfxec", i915_gfxec, 0},
Jesse Barnesb5e50c32010-02-05 12:42:41 -08003710 {"i915_fbc_status", i915_fbc_status, 0},
Paulo Zanoni92d44622013-05-31 16:33:24 -03003711 {"i915_ips_status", i915_ips_status, 0},
Jesse Barnes4a9bef32010-02-05 12:47:35 -08003712 {"i915_sr_status", i915_sr_status, 0},
Chris Wilson44834a62010-08-19 16:09:23 +01003713 {"i915_opregion", i915_opregion, 0},
Chris Wilson37811fc2010-08-25 22:45:57 +01003714 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
Ben Widawskye76d3632011-03-19 18:14:29 -07003715 {"i915_context_status", i915_context_status, 0},
Ben Widawsky6d794d42011-04-25 11:25:56 -07003716 {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
Daniel Vetterea16a3c2011-12-14 13:57:16 +01003717 {"i915_swizzle_info", i915_swizzle_info, 0},
Daniel Vetter3cf17fc2012-02-09 17:15:49 +01003718 {"i915_ppgtt_info", i915_ppgtt_info, 0},
Jesse Barnes57f350b2012-03-28 13:39:25 -07003719 {"i915_dpio", i915_dpio_info, 0},
Ben Widawsky63573eb2013-07-04 11:02:07 -07003720 {"i915_llc", i915_llc, 0},
Rodrigo Vivie91fd8c2013-07-11 18:44:59 -03003721 {"i915_edp_psr_status", i915_edp_psr_status, 0},
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02003722 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
Jesse Barnesec013e72013-08-20 10:29:23 +01003723 {"i915_energy_uJ", i915_energy_uJ, 0},
Paulo Zanoni371db662013-08-19 13:18:10 -03003724 {"i915_pc8_status", i915_pc8_status, 0},
Imre Deak1da51582013-11-25 17:15:35 +02003725 {"i915_power_domain_info", i915_power_domain_info, 0},
Jesse Barnes53f5e3c2014-02-07 12:48:15 -08003726 {"i915_display_info", i915_display_info, 0},
Ben Gamari20172632009-02-17 20:08:50 -05003727};
Ben Gamari27c202a2009-07-01 22:26:52 -04003728#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
Ben Gamari20172632009-02-17 20:08:50 -05003729
Lespiau, Damien06c5bf82013-10-17 19:09:56 +01003730static const struct i915_debugfs_files {
Daniel Vetter34b96742013-07-04 20:49:44 +02003731 const char *name;
3732 const struct file_operations *fops;
3733} i915_debugfs_files[] = {
3734 {"i915_wedged", &i915_wedged_fops},
3735 {"i915_max_freq", &i915_max_freq_fops},
3736 {"i915_min_freq", &i915_min_freq_fops},
3737 {"i915_cache_sharing", &i915_cache_sharing_fops},
3738 {"i915_ring_stop", &i915_ring_stop_fops},
Chris Wilson094f9a52013-09-25 17:34:55 +01003739 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3740 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
Daniel Vetter34b96742013-07-04 20:49:44 +02003741 {"i915_gem_drop_caches", &i915_drop_caches_fops},
3742 {"i915_error_state", &i915_error_state_fops},
3743 {"i915_next_seqno", &i915_next_seqno_fops},
Damien Lespiaubd9db022013-10-15 18:55:36 +01003744 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
Ville Syrjälä369a1342014-01-22 14:36:08 +02003745 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3746 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3747 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
Daniel Vetter34b96742013-07-04 20:49:44 +02003748};
3749
Damien Lespiau07144422013-10-15 18:55:40 +01003750void intel_display_crc_init(struct drm_device *dev)
3751{
3752 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterb3783602013-11-14 11:30:42 +01003753 enum pipe pipe;
Damien Lespiau07144422013-10-15 18:55:40 +01003754
Daniel Vetterb3783602013-11-14 11:30:42 +01003755 for_each_pipe(pipe) {
3756 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
Damien Lespiau07144422013-10-15 18:55:40 +01003757
Damien Lespiaud538bbd2013-10-21 14:29:30 +01003758 pipe_crc->opened = false;
3759 spin_lock_init(&pipe_crc->lock);
Damien Lespiau07144422013-10-15 18:55:40 +01003760 init_waitqueue_head(&pipe_crc->wq);
3761 }
3762}
3763
Ben Gamari27c202a2009-07-01 22:26:52 -04003764int i915_debugfs_init(struct drm_minor *minor)
Ben Gamari20172632009-02-17 20:08:50 -05003765{
Daniel Vetter34b96742013-07-04 20:49:44 +02003766 int ret, i;
Chris Wilsonf3cd4742009-10-13 22:20:20 +01003767
Ben Widawsky6d794d42011-04-25 11:25:56 -07003768 ret = i915_forcewake_create(minor->debugfs_root, minor);
3769 if (ret)
3770 return ret;
Daniel Vetter6a9c3082011-12-14 13:57:11 +01003771
Damien Lespiau07144422013-10-15 18:55:40 +01003772 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3773 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3774 if (ret)
3775 return ret;
3776 }
3777
Daniel Vetter34b96742013-07-04 20:49:44 +02003778 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3779 ret = i915_debugfs_create(minor->debugfs_root, minor,
3780 i915_debugfs_files[i].name,
3781 i915_debugfs_files[i].fops);
3782 if (ret)
3783 return ret;
3784 }
Mika Kuoppala40633212012-12-04 15:12:00 +02003785
Ben Gamari27c202a2009-07-01 22:26:52 -04003786 return drm_debugfs_create_files(i915_debugfs_list,
3787 I915_DEBUGFS_ENTRIES,
Ben Gamari20172632009-02-17 20:08:50 -05003788 minor->debugfs_root, minor);
3789}
3790
Ben Gamari27c202a2009-07-01 22:26:52 -04003791void i915_debugfs_cleanup(struct drm_minor *minor)
Ben Gamari20172632009-02-17 20:08:50 -05003792{
Daniel Vetter34b96742013-07-04 20:49:44 +02003793 int i;
3794
Ben Gamari27c202a2009-07-01 22:26:52 -04003795 drm_debugfs_remove_files(i915_debugfs_list,
3796 I915_DEBUGFS_ENTRIES, minor);
Damien Lespiau07144422013-10-15 18:55:40 +01003797
Ben Widawsky6d794d42011-04-25 11:25:56 -07003798 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3799 1, minor);
Damien Lespiau07144422013-10-15 18:55:40 +01003800
Daniel Vettere309a992013-10-16 22:55:51 +02003801 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
Damien Lespiau07144422013-10-15 18:55:40 +01003802 struct drm_info_list *info_list =
3803 (struct drm_info_list *)&i915_pipe_crc_data[i];
3804
3805 drm_debugfs_remove_files(info_list, 1, minor);
3806 }
3807
Daniel Vetter34b96742013-07-04 20:49:44 +02003808 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3809 struct drm_info_list *info_list =
3810 (struct drm_info_list *) i915_debugfs_files[i].fops;
3811
3812 drm_debugfs_remove_files(info_list, 1, minor);
3813 }
Ben Gamari20172632009-02-17 20:08:50 -05003814}