blob: 72f4777f06feb7d58032650d29b621813d0ac947 [file] [log] [blame]
Daniel Vetter76aaf222010-11-05 22:23:30 +01001/*
2 * Copyright © 2010 Daniel Vetter
Ben Widawskyc4ac5242014-02-19 22:05:47 -08003 * Copyright © 2011-2014 Intel Corporation
Daniel Vetter76aaf222010-11-05 22:23:30 +01004 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 *
24 */
25
Daniel Vetter0e46ce22014-01-08 16:10:27 +010026#include <linux/seq_file.h>
David Howells760285e2012-10-02 18:01:07 +010027#include <drm/drmP.h>
28#include <drm/i915_drm.h>
Daniel Vetter76aaf222010-11-05 22:23:30 +010029#include "i915_drv.h"
Yu Zhang5dda8fa2015-02-10 19:05:48 +080030#include "i915_vgpu.h"
Daniel Vetter76aaf222010-11-05 22:23:30 +010031#include "i915_trace.h"
32#include "intel_drv.h"
33
Tvrtko Ursulin45f8f692014-12-10 17:27:59 +000034/**
35 * DOC: Global GTT views
36 *
37 * Background and previous state
38 *
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
42 *
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
46 *
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
49 * (2x2 pages):
50 *
51 * 12
52 * 34
53 *
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
57 *
58 * 1212
59 * 3434
60 *
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
63 *
64 * Implementation and usage
65 *
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
68 *
69 * A new flavour of core GEM functions which work with GGTT bound objects were
Joonas Lahtinenec7adb62015-03-16 14:11:13 +020070 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
Tvrtko Ursulin45f8f692014-12-10 17:27:59 +000073 *
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
78 *
79 * Code wanting to add or use a new GGTT view needs to:
80 *
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
84 *
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
88 *
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
92 *
93 */
94
Daniel Vetter70b9f6f2015-04-14 17:35:27 +020095static int
96i915_get_ggtt_vma_pages(struct i915_vma *vma);
97
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +000098const struct i915_ggtt_view i915_ggtt_view_normal;
Joonas Lahtinen9abc4642015-03-27 13:09:22 +020099const struct i915_ggtt_view i915_ggtt_view_rotated = {
100 .type = I915_GGTT_VIEW_ROTATED
101};
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +0000102
Daniel Vettercfa7c862014-04-29 11:53:58 +0200103static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
104{
Chris Wilson1893a712014-09-19 11:56:27 +0100105 bool has_aliasing_ppgtt;
106 bool has_full_ppgtt;
107
108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
Chris Wilson1893a712014-09-19 11:56:27 +0100110
Yu Zhang71ba2d62015-02-10 19:05:54 +0800111 if (intel_vgpu_active(dev))
112 has_full_ppgtt = false; /* emulation is too hard */
113
Damien Lespiau70ee45e2014-11-14 15:05:59 +0000114 /*
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
117 */
118 if (INTEL_INFO(dev)->gen < 9 &&
119 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
Daniel Vettercfa7c862014-04-29 11:53:58 +0200120 return 0;
121
122 if (enable_ppgtt == 1)
123 return 1;
124
Chris Wilson1893a712014-09-19 11:56:27 +0100125 if (enable_ppgtt == 2 && has_full_ppgtt)
Daniel Vettercfa7c862014-04-29 11:53:58 +0200126 return 2;
127
Daniel Vetter93a25a92014-03-06 09:40:43 +0100128#ifdef CONFIG_INTEL_IOMMU
129 /* Disable ppgtt on SNB if VT-d is on. */
130 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
131 DRM_INFO("Disabling PPGTT because VT-d is on\n");
Daniel Vettercfa7c862014-04-29 11:53:58 +0200132 return 0;
Daniel Vetter93a25a92014-03-06 09:40:43 +0100133 }
134#endif
135
Jesse Barnes62942ed2014-06-13 09:28:33 -0700136 /* Early VLV doesn't have this */
Ville Syrjäläca2aed6c2014-06-28 02:03:56 +0300137 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
138 dev->pdev->revision < 0xb) {
Jesse Barnes62942ed2014-06-13 09:28:33 -0700139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
140 return 0;
141 }
142
Michel Thierry2f82bbd2014-12-15 14:58:00 +0000143 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
144 return 2;
145 else
146 return has_aliasing_ppgtt ? 1 : 0;
Daniel Vetter93a25a92014-03-06 09:40:43 +0100147}
148
Daniel Vetter70b9f6f2015-04-14 17:35:27 +0200149static int ppgtt_bind_vma(struct i915_vma *vma,
150 enum i915_cache_level cache_level,
151 u32 unused)
Daniel Vetter47552652015-04-14 17:35:24 +0200152{
153 u32 pte_flags = 0;
154
155 /* Currently applicable only to VLV */
156 if (vma->obj->gt_ro)
157 pte_flags |= PTE_READ_ONLY;
158
159 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
160 cache_level, pte_flags);
Daniel Vetter70b9f6f2015-04-14 17:35:27 +0200161
162 return 0;
Daniel Vetter47552652015-04-14 17:35:24 +0200163}
164
165static void ppgtt_unbind_vma(struct i915_vma *vma)
166{
167 vma->vm->clear_range(vma->vm,
168 vma->node.start,
169 vma->obj->base.size,
170 true);
171}
Ben Widawsky6f65e292013-12-06 14:10:56 -0800172
Daniel Vetter2c642b02015-04-14 17:35:26 +0200173static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
174 enum i915_cache_level level,
175 bool valid)
Ben Widawsky94ec8f62013-11-02 21:07:18 -0700176{
Michel Thierry07749ef2015-03-16 16:00:54 +0000177 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
Ben Widawsky94ec8f62013-11-02 21:07:18 -0700178 pte |= addr;
Ben Widawsky63c42e52014-04-18 18:04:27 -0300179
180 switch (level) {
181 case I915_CACHE_NONE:
Ben Widawskyfbe5d362013-11-04 19:56:49 -0800182 pte |= PPAT_UNCACHED_INDEX;
Ben Widawsky63c42e52014-04-18 18:04:27 -0300183 break;
184 case I915_CACHE_WT:
185 pte |= PPAT_DISPLAY_ELLC_INDEX;
186 break;
187 default:
188 pte |= PPAT_CACHED_INDEX;
189 break;
190 }
191
Ben Widawsky94ec8f62013-11-02 21:07:18 -0700192 return pte;
193}
194
Mika Kuoppalafe36f552015-06-25 18:35:16 +0300195static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
196 const enum i915_cache_level level)
Ben Widawskyb1fe6672013-11-04 21:20:14 -0800197{
Michel Thierry07749ef2015-03-16 16:00:54 +0000198 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
Ben Widawskyb1fe6672013-11-04 21:20:14 -0800199 pde |= addr;
200 if (level != I915_CACHE_NONE)
201 pde |= PPAT_CACHED_PDE_INDEX;
202 else
203 pde |= PPAT_UNCACHED_INDEX;
204 return pde;
205}
206
Michel Thierry07749ef2015-03-16 16:00:54 +0000207static gen6_pte_t snb_pte_encode(dma_addr_t addr,
208 enum i915_cache_level level,
209 bool valid, u32 unused)
Ben Widawsky54d12522012-09-24 16:44:32 -0700210{
Michel Thierry07749ef2015-03-16 16:00:54 +0000211 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Ben Widawsky54d12522012-09-24 16:44:32 -0700212 pte |= GEN6_PTE_ADDR_ENCODE(addr);
Ben Widawskye7210c32012-10-19 09:33:22 -0700213
214 switch (level) {
Chris Wilson350ec882013-08-06 13:17:02 +0100215 case I915_CACHE_L3_LLC:
216 case I915_CACHE_LLC:
217 pte |= GEN6_PTE_CACHE_LLC;
218 break;
219 case I915_CACHE_NONE:
220 pte |= GEN6_PTE_UNCACHED;
221 break;
222 default:
Daniel Vetter5f77eeb2014-12-08 16:40:10 +0100223 MISSING_CASE(level);
Chris Wilson350ec882013-08-06 13:17:02 +0100224 }
225
226 return pte;
227}
228
Michel Thierry07749ef2015-03-16 16:00:54 +0000229static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
230 enum i915_cache_level level,
231 bool valid, u32 unused)
Chris Wilson350ec882013-08-06 13:17:02 +0100232{
Michel Thierry07749ef2015-03-16 16:00:54 +0000233 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Chris Wilson350ec882013-08-06 13:17:02 +0100234 pte |= GEN6_PTE_ADDR_ENCODE(addr);
235
236 switch (level) {
237 case I915_CACHE_L3_LLC:
238 pte |= GEN7_PTE_CACHE_L3_LLC;
Ben Widawskye7210c32012-10-19 09:33:22 -0700239 break;
240 case I915_CACHE_LLC:
241 pte |= GEN6_PTE_CACHE_LLC;
242 break;
243 case I915_CACHE_NONE:
Kenneth Graunke91197082013-04-22 00:53:51 -0700244 pte |= GEN6_PTE_UNCACHED;
Ben Widawskye7210c32012-10-19 09:33:22 -0700245 break;
246 default:
Daniel Vetter5f77eeb2014-12-08 16:40:10 +0100247 MISSING_CASE(level);
Ben Widawskye7210c32012-10-19 09:33:22 -0700248 }
249
Ben Widawsky54d12522012-09-24 16:44:32 -0700250 return pte;
251}
252
Michel Thierry07749ef2015-03-16 16:00:54 +0000253static gen6_pte_t byt_pte_encode(dma_addr_t addr,
254 enum i915_cache_level level,
255 bool valid, u32 flags)
Kenneth Graunke93c34e72013-04-22 00:53:50 -0700256{
Michel Thierry07749ef2015-03-16 16:00:54 +0000257 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Kenneth Graunke93c34e72013-04-22 00:53:50 -0700258 pte |= GEN6_PTE_ADDR_ENCODE(addr);
259
Akash Goel24f3a8c2014-06-17 10:59:42 +0530260 if (!(flags & PTE_READ_ONLY))
261 pte |= BYT_PTE_WRITEABLE;
Kenneth Graunke93c34e72013-04-22 00:53:50 -0700262
263 if (level != I915_CACHE_NONE)
264 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
265
266 return pte;
267}
268
Michel Thierry07749ef2015-03-16 16:00:54 +0000269static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
270 enum i915_cache_level level,
271 bool valid, u32 unused)
Kenneth Graunke91197082013-04-22 00:53:51 -0700272{
Michel Thierry07749ef2015-03-16 16:00:54 +0000273 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Ben Widawsky0d8ff152013-07-04 11:02:03 -0700274 pte |= HSW_PTE_ADDR_ENCODE(addr);
Kenneth Graunke91197082013-04-22 00:53:51 -0700275
276 if (level != I915_CACHE_NONE)
Ben Widawsky87a6b682013-08-04 23:47:29 -0700277 pte |= HSW_WB_LLC_AGE3;
Kenneth Graunke91197082013-04-22 00:53:51 -0700278
279 return pte;
280}
281
Michel Thierry07749ef2015-03-16 16:00:54 +0000282static gen6_pte_t iris_pte_encode(dma_addr_t addr,
283 enum i915_cache_level level,
284 bool valid, u32 unused)
Ben Widawsky4d15c142013-07-04 11:02:06 -0700285{
Michel Thierry07749ef2015-03-16 16:00:54 +0000286 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
Ben Widawsky4d15c142013-07-04 11:02:06 -0700287 pte |= HSW_PTE_ADDR_ENCODE(addr);
288
Chris Wilson651d7942013-08-08 14:41:10 +0100289 switch (level) {
290 case I915_CACHE_NONE:
291 break;
292 case I915_CACHE_WT:
Chris Wilsonc51e9702013-11-22 10:37:53 +0000293 pte |= HSW_WT_ELLC_LLC_AGE3;
Chris Wilson651d7942013-08-08 14:41:10 +0100294 break;
295 default:
Chris Wilsonc51e9702013-11-22 10:37:53 +0000296 pte |= HSW_WB_ELLC_LLC_AGE3;
Chris Wilson651d7942013-08-08 14:41:10 +0100297 break;
298 }
Ben Widawsky4d15c142013-07-04 11:02:06 -0700299
300 return pte;
301}
302
Mika Kuoppalac114f762015-06-25 18:35:13 +0300303static int __setup_page_dma(struct drm_device *dev,
304 struct i915_page_dma *p, gfp_t flags)
Ben Widawsky678d96f2015-03-16 16:00:56 +0000305{
306 struct device *device = &dev->pdev->dev;
307
Mika Kuoppalac114f762015-06-25 18:35:13 +0300308 p->page = alloc_page(flags);
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300309 if (!p->page)
Michel Thierry1266cdb2015-03-24 17:06:33 +0000310 return -ENOMEM;
311
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300312 p->daddr = dma_map_page(device,
313 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
314
315 if (dma_mapping_error(device, p->daddr)) {
316 __free_page(p->page);
317 return -EINVAL;
318 }
319
Michel Thierry1266cdb2015-03-24 17:06:33 +0000320 return 0;
Ben Widawsky678d96f2015-03-16 16:00:56 +0000321}
322
Mika Kuoppalac114f762015-06-25 18:35:13 +0300323static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
324{
325 return __setup_page_dma(dev, p, GFP_KERNEL);
326}
327
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300328static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
329{
330 if (WARN_ON(!p->page))
331 return;
332
333 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
334 __free_page(p->page);
335 memset(p, 0, sizeof(*p));
336}
337
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300338static void *kmap_page_dma(struct i915_page_dma *p)
Mika Kuoppala73eeea52015-06-25 18:35:10 +0300339{
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300340 return kmap_atomic(p->page);
341}
Mika Kuoppala73eeea52015-06-25 18:35:10 +0300342
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300343/* We use the flushing unmap only with ppgtt structures:
344 * page directories, page tables and scratch pages.
345 */
346static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
347{
Mika Kuoppala73eeea52015-06-25 18:35:10 +0300348 /* There are only few exceptions for gen >=6. chv and bxt.
349 * And we are not sure about the latter so play safe for now.
350 */
351 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
352 drm_clflush_virt_range(vaddr, PAGE_SIZE);
353
354 kunmap_atomic(vaddr);
355}
356
Mika Kuoppala567047b2015-06-25 18:35:12 +0300357#define kmap_px(px) kmap_page_dma(px_base(px))
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300358#define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
359
Mika Kuoppala567047b2015-06-25 18:35:12 +0300360#define setup_px(dev, px) setup_page_dma((dev), px_base(px))
361#define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
362#define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
363#define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
364
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300365static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
366 const uint64_t val)
367{
368 int i;
369 uint64_t * const vaddr = kmap_page_dma(p);
370
371 for (i = 0; i < 512; i++)
372 vaddr[i] = val;
373
374 kunmap_page_dma(dev, vaddr);
375}
376
Mika Kuoppala73eeea52015-06-25 18:35:10 +0300377static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
378 const uint32_t val32)
379{
380 uint64_t v = val32;
381
382 v = v << 32 | val32;
383
384 fill_page_dma(dev, p, v);
385}
386
Mika Kuoppala4ad2af12015-06-30 18:16:39 +0300387static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
388{
389 struct i915_page_scratch *sp;
390 int ret;
391
392 sp = kzalloc(sizeof(*sp), GFP_KERNEL);
393 if (sp == NULL)
394 return ERR_PTR(-ENOMEM);
395
396 ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
397 if (ret) {
398 kfree(sp);
399 return ERR_PTR(ret);
400 }
401
402 set_pages_uc(px_page(sp), 1);
403
404 return sp;
405}
406
407static void free_scratch_page(struct drm_device *dev,
408 struct i915_page_scratch *sp)
409{
410 set_pages_wb(px_page(sp), 1);
411
412 cleanup_px(dev, sp);
413 kfree(sp);
414}
415
Mika Kuoppala8a1ebd72015-05-22 20:04:59 +0300416static struct i915_page_table *alloc_pt(struct drm_device *dev)
Ben Widawsky06fda602015-02-24 16:22:36 +0000417{
Michel Thierryec565b32015-04-08 12:13:23 +0100418 struct i915_page_table *pt;
Ben Widawsky678d96f2015-03-16 16:00:56 +0000419 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
420 GEN8_PTES : GEN6_PTES;
421 int ret = -ENOMEM;
Ben Widawsky06fda602015-02-24 16:22:36 +0000422
423 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
424 if (!pt)
425 return ERR_PTR(-ENOMEM);
426
Ben Widawsky678d96f2015-03-16 16:00:56 +0000427 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
428 GFP_KERNEL);
429
430 if (!pt->used_ptes)
431 goto fail_bitmap;
432
Mika Kuoppala567047b2015-06-25 18:35:12 +0300433 ret = setup_px(dev, pt);
Ben Widawsky678d96f2015-03-16 16:00:56 +0000434 if (ret)
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300435 goto fail_page_m;
Ben Widawsky06fda602015-02-24 16:22:36 +0000436
437 return pt;
Ben Widawsky678d96f2015-03-16 16:00:56 +0000438
Mika Kuoppala44159dd2015-06-25 18:35:07 +0300439fail_page_m:
Ben Widawsky678d96f2015-03-16 16:00:56 +0000440 kfree(pt->used_ptes);
441fail_bitmap:
442 kfree(pt);
443
444 return ERR_PTR(ret);
Ben Widawsky06fda602015-02-24 16:22:36 +0000445}
446
Mika Kuoppala2e906be2015-06-30 18:16:37 +0300447static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
Ben Widawsky06fda602015-02-24 16:22:36 +0000448{
Mika Kuoppala2e906be2015-06-30 18:16:37 +0300449 cleanup_px(dev, pt);
450 kfree(pt->used_ptes);
451 kfree(pt);
452}
453
454static void gen8_initialize_pt(struct i915_address_space *vm,
455 struct i915_page_table *pt)
456{
457 gen8_pte_t scratch_pte;
458
459 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
460 I915_CACHE_LLC, true);
461
462 fill_px(vm->dev, pt, scratch_pte);
463}
464
465static void gen6_initialize_pt(struct i915_address_space *vm,
466 struct i915_page_table *pt)
467{
468 gen6_pte_t scratch_pte;
469
470 WARN_ON(px_dma(vm->scratch_page) == 0);
471
472 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
473 I915_CACHE_LLC, true, 0);
474
475 fill32_px(vm->dev, pt, scratch_pte);
Ben Widawsky06fda602015-02-24 16:22:36 +0000476}
477
Mika Kuoppala8a1ebd72015-05-22 20:04:59 +0300478static struct i915_page_directory *alloc_pd(struct drm_device *dev)
Ben Widawsky06fda602015-02-24 16:22:36 +0000479{
Michel Thierryec565b32015-04-08 12:13:23 +0100480 struct i915_page_directory *pd;
Michel Thierry33c88192015-04-08 12:13:33 +0100481 int ret = -ENOMEM;
Ben Widawsky06fda602015-02-24 16:22:36 +0000482
483 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
484 if (!pd)
485 return ERR_PTR(-ENOMEM);
486
Michel Thierry33c88192015-04-08 12:13:33 +0100487 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
488 sizeof(*pd->used_pdes), GFP_KERNEL);
489 if (!pd->used_pdes)
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300490 goto fail_bitmap;
Michel Thierry33c88192015-04-08 12:13:33 +0100491
Mika Kuoppala567047b2015-06-25 18:35:12 +0300492 ret = setup_px(dev, pd);
Michel Thierry33c88192015-04-08 12:13:33 +0100493 if (ret)
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300494 goto fail_page_m;
Michel Thierrye5815a22015-04-08 12:13:32 +0100495
Ben Widawsky06fda602015-02-24 16:22:36 +0000496 return pd;
Michel Thierry33c88192015-04-08 12:13:33 +0100497
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300498fail_page_m:
Michel Thierry33c88192015-04-08 12:13:33 +0100499 kfree(pd->used_pdes);
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300500fail_bitmap:
Michel Thierry33c88192015-04-08 12:13:33 +0100501 kfree(pd);
502
503 return ERR_PTR(ret);
Ben Widawsky06fda602015-02-24 16:22:36 +0000504}
505
Mika Kuoppala2e906be2015-06-30 18:16:37 +0300506static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
507{
508 if (px_page(pd)) {
509 cleanup_px(dev, pd);
510 kfree(pd->used_pdes);
511 kfree(pd);
512 }
513}
514
515static void gen8_initialize_pd(struct i915_address_space *vm,
516 struct i915_page_directory *pd)
517{
518 gen8_pde_t scratch_pde;
519
520 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
521
522 fill_px(vm->dev, pd, scratch_pde);
523}
524
Michel Thierry6ac18502015-07-29 17:23:46 +0100525static int __pdp_init(struct drm_device *dev,
526 struct i915_page_directory_pointer *pdp)
527{
528 size_t pdpes = I915_PDPES_PER_PDP(dev);
529
530 pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
531 sizeof(unsigned long),
532 GFP_KERNEL);
533 if (!pdp->used_pdpes)
534 return -ENOMEM;
535
536 pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
537 GFP_KERNEL);
538 if (!pdp->page_directory) {
539 kfree(pdp->used_pdpes);
540 /* the PDP might be the statically allocated top level. Keep it
541 * as clean as possible */
542 pdp->used_pdpes = NULL;
543 return -ENOMEM;
544 }
545
546 return 0;
547}
548
549static void __pdp_fini(struct i915_page_directory_pointer *pdp)
550{
551 kfree(pdp->used_pdpes);
552 kfree(pdp->page_directory);
553 pdp->page_directory = NULL;
554}
555
556static void free_pdp(struct drm_device *dev,
557 struct i915_page_directory_pointer *pdp)
558{
559 __pdp_fini(pdp);
560}
561
Ben Widawsky94e409c2013-11-04 22:29:36 -0800562/* Broadwell Page Directory Pointer Descriptors */
John Harrisone85b26d2015-05-29 17:43:56 +0100563static int gen8_write_pdp(struct drm_i915_gem_request *req,
Michel Thierry7cb6d7a2015-04-08 12:13:29 +0100564 unsigned entry,
565 dma_addr_t addr)
Ben Widawsky94e409c2013-11-04 22:29:36 -0800566{
John Harrisone85b26d2015-05-29 17:43:56 +0100567 struct intel_engine_cs *ring = req->ring;
Ben Widawsky94e409c2013-11-04 22:29:36 -0800568 int ret;
569
570 BUG_ON(entry >= 4);
571
John Harrison5fb9de12015-05-29 17:44:07 +0100572 ret = intel_ring_begin(req, 6);
Ben Widawsky94e409c2013-11-04 22:29:36 -0800573 if (ret)
574 return ret;
575
576 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
577 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
Michel Thierry7cb6d7a2015-04-08 12:13:29 +0100578 intel_ring_emit(ring, upper_32_bits(addr));
Ben Widawsky94e409c2013-11-04 22:29:36 -0800579 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
580 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
Michel Thierry7cb6d7a2015-04-08 12:13:29 +0100581 intel_ring_emit(ring, lower_32_bits(addr));
Ben Widawsky94e409c2013-11-04 22:29:36 -0800582 intel_ring_advance(ring);
583
584 return 0;
585}
586
Ben Widawskyeeb94882013-12-06 14:11:10 -0800587static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
John Harrisone85b26d2015-05-29 17:43:56 +0100588 struct drm_i915_gem_request *req)
Ben Widawsky94e409c2013-11-04 22:29:36 -0800589{
Ben Widawskyeeb94882013-12-06 14:11:10 -0800590 int i, ret;
Ben Widawsky94e409c2013-11-04 22:29:36 -0800591
Michel Thierry7cb6d7a2015-04-08 12:13:29 +0100592 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
Mika Kuoppalad852c7b2015-06-25 18:35:06 +0300593 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
594
John Harrisone85b26d2015-05-29 17:43:56 +0100595 ret = gen8_write_pdp(req, i, pd_daddr);
Ben Widawskyeeb94882013-12-06 14:11:10 -0800596 if (ret)
597 return ret;
Ben Widawsky94e409c2013-11-04 22:29:36 -0800598 }
Ben Widawskyd595bd42013-11-25 09:54:32 -0800599
Ben Widawskyeeb94882013-12-06 14:11:10 -0800600 return 0;
Ben Widawsky94e409c2013-11-04 22:29:36 -0800601}
602
Michel Thierryf9b5b782015-07-30 11:02:49 +0100603static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
604 struct i915_page_directory_pointer *pdp,
605 uint64_t start,
606 uint64_t length,
607 gen8_pte_t scratch_pte)
Ben Widawsky459108b2013-11-02 21:07:23 -0700608{
609 struct i915_hw_ppgtt *ppgtt =
610 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierryf9b5b782015-07-30 11:02:49 +0100611 gen8_pte_t *pt_vaddr;
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800612 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
613 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
614 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
Ben Widawsky782f1492014-02-20 11:50:33 -0800615 unsigned num_entries = length >> PAGE_SHIFT;
Ben Widawsky459108b2013-11-02 21:07:23 -0700616 unsigned last_pte, i;
617
Michel Thierryf9b5b782015-07-30 11:02:49 +0100618 if (WARN_ON(!pdp))
619 return;
Ben Widawsky459108b2013-11-02 21:07:23 -0700620
621 while (num_entries) {
Michel Thierryec565b32015-04-08 12:13:23 +0100622 struct i915_page_directory *pd;
623 struct i915_page_table *pt;
Ben Widawsky06fda602015-02-24 16:22:36 +0000624
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100625 if (WARN_ON(!pdp->page_directory[pdpe]))
Michel Thierry00245262015-06-25 12:59:38 +0100626 break;
Ben Widawsky06fda602015-02-24 16:22:36 +0000627
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100628 pd = pdp->page_directory[pdpe];
Ben Widawsky06fda602015-02-24 16:22:36 +0000629
630 if (WARN_ON(!pd->page_table[pde]))
Michel Thierry00245262015-06-25 12:59:38 +0100631 break;
Ben Widawsky06fda602015-02-24 16:22:36 +0000632
633 pt = pd->page_table[pde];
634
Mika Kuoppala567047b2015-06-25 18:35:12 +0300635 if (WARN_ON(!px_page(pt)))
Michel Thierry00245262015-06-25 12:59:38 +0100636 break;
Ben Widawsky06fda602015-02-24 16:22:36 +0000637
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800638 last_pte = pte + num_entries;
Michel Thierry07749ef2015-03-16 16:00:54 +0000639 if (last_pte > GEN8_PTES)
640 last_pte = GEN8_PTES;
Ben Widawsky459108b2013-11-02 21:07:23 -0700641
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300642 pt_vaddr = kmap_px(pt);
Ben Widawsky459108b2013-11-02 21:07:23 -0700643
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800644 for (i = pte; i < last_pte; i++) {
Ben Widawsky459108b2013-11-02 21:07:23 -0700645 pt_vaddr[i] = scratch_pte;
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800646 num_entries--;
647 }
Ben Widawsky459108b2013-11-02 21:07:23 -0700648
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300649 kunmap_px(ppgtt, pt);
Ben Widawsky459108b2013-11-02 21:07:23 -0700650
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800651 pte = 0;
Michel Thierry07749ef2015-03-16 16:00:54 +0000652 if (++pde == I915_PDES) {
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800653 pdpe++;
654 pde = 0;
655 }
Ben Widawsky459108b2013-11-02 21:07:23 -0700656 }
657}
658
Michel Thierryf9b5b782015-07-30 11:02:49 +0100659static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
660 uint64_t start,
661 uint64_t length,
662 bool use_scratch)
Ben Widawsky9df15b42013-11-02 21:07:24 -0700663{
664 struct i915_hw_ppgtt *ppgtt =
665 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100666 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
Michel Thierryf9b5b782015-07-30 11:02:49 +0100667
668 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
669 I915_CACHE_LLC, use_scratch);
670
671 gen8_ppgtt_clear_pte_range(vm, pdp, start, length, scratch_pte);
672}
673
674static void
675gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
676 struct i915_page_directory_pointer *pdp,
677 struct sg_table *pages,
678 uint64_t start,
679 enum i915_cache_level cache_level)
680{
681 struct i915_hw_ppgtt *ppgtt =
682 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierry07749ef2015-03-16 16:00:54 +0000683 gen8_pte_t *pt_vaddr;
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800684 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
685 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
686 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
Ben Widawsky9df15b42013-11-02 21:07:24 -0700687 struct sg_page_iter sg_iter;
688
Chris Wilson6f1cc992013-12-31 15:50:31 +0000689 pt_vaddr = NULL;
Ben Widawsky9df15b42013-11-02 21:07:24 -0700690
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800691 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
Ben Widawsky76643602015-01-22 17:01:24 +0000692 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800693 break;
694
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000695 if (pt_vaddr == NULL) {
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100696 struct i915_page_directory *pd = pdp->page_directory[pdpe];
Michel Thierryec565b32015-04-08 12:13:23 +0100697 struct i915_page_table *pt = pd->page_table[pde];
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300698 pt_vaddr = kmap_px(pt);
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000699 }
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800700
701 pt_vaddr[pte] =
Chris Wilson6f1cc992013-12-31 15:50:31 +0000702 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
703 cache_level, true);
Michel Thierry07749ef2015-03-16 16:00:54 +0000704 if (++pte == GEN8_PTES) {
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300705 kunmap_px(ppgtt, pt_vaddr);
Chris Wilson6f1cc992013-12-31 15:50:31 +0000706 pt_vaddr = NULL;
Michel Thierry07749ef2015-03-16 16:00:54 +0000707 if (++pde == I915_PDES) {
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800708 pdpe++;
709 pde = 0;
710 }
711 pte = 0;
Ben Widawsky9df15b42013-11-02 21:07:24 -0700712 }
713 }
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +0300714
715 if (pt_vaddr)
716 kunmap_px(ppgtt, pt_vaddr);
Ben Widawsky9df15b42013-11-02 21:07:24 -0700717}
718
Michel Thierryf9b5b782015-07-30 11:02:49 +0100719static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
720 struct sg_table *pages,
721 uint64_t start,
722 enum i915_cache_level cache_level,
723 u32 unused)
724{
725 struct i915_hw_ppgtt *ppgtt =
726 container_of(vm, struct i915_hw_ppgtt, base);
727 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
728
729 gen8_ppgtt_insert_pte_entries(vm, pdp, pages, start, cache_level);
730}
731
Michel Thierryf37c0502015-06-10 17:46:39 +0100732static void gen8_free_page_tables(struct drm_device *dev,
733 struct i915_page_directory *pd)
Ben Widawskyb45a6712014-02-12 14:28:44 -0800734{
735 int i;
736
Mika Kuoppala567047b2015-06-25 18:35:12 +0300737 if (!px_page(pd))
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800738 return;
Ben Widawskyb45a6712014-02-12 14:28:44 -0800739
Michel Thierry33c88192015-04-08 12:13:33 +0100740 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
Ben Widawsky06fda602015-02-24 16:22:36 +0000741 if (WARN_ON(!pd->page_table[i]))
742 continue;
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800743
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300744 free_pt(dev, pd->page_table[i]);
Ben Widawsky06fda602015-02-24 16:22:36 +0000745 pd->page_table[i] = NULL;
746 }
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000747}
748
Mika Kuoppala8776f022015-06-30 18:16:40 +0300749static int gen8_init_scratch(struct i915_address_space *vm)
750{
751 struct drm_device *dev = vm->dev;
752
753 vm->scratch_page = alloc_scratch_page(dev);
754 if (IS_ERR(vm->scratch_page))
755 return PTR_ERR(vm->scratch_page);
756
757 vm->scratch_pt = alloc_pt(dev);
758 if (IS_ERR(vm->scratch_pt)) {
759 free_scratch_page(dev, vm->scratch_page);
760 return PTR_ERR(vm->scratch_pt);
761 }
762
763 vm->scratch_pd = alloc_pd(dev);
764 if (IS_ERR(vm->scratch_pd)) {
765 free_pt(dev, vm->scratch_pt);
766 free_scratch_page(dev, vm->scratch_page);
767 return PTR_ERR(vm->scratch_pd);
768 }
769
770 gen8_initialize_pt(vm, vm->scratch_pt);
771 gen8_initialize_pd(vm, vm->scratch_pd);
772
773 return 0;
774}
775
776static void gen8_free_scratch(struct i915_address_space *vm)
777{
778 struct drm_device *dev = vm->dev;
779
780 free_pd(dev, vm->scratch_pd);
781 free_pt(dev, vm->scratch_pt);
782 free_scratch_page(dev, vm->scratch_page);
783}
784
Daniel Vetter061dd492015-04-14 17:35:13 +0200785static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800786{
Daniel Vetter061dd492015-04-14 17:35:13 +0200787 struct i915_hw_ppgtt *ppgtt =
788 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100789 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
790 struct drm_device *dev = ppgtt->base.dev;
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800791 int i;
792
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100793 for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
794 if (WARN_ON(!pdp->page_directory[i]))
Ben Widawsky06fda602015-02-24 16:22:36 +0000795 continue;
796
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100797 gen8_free_page_tables(dev, pdp->page_directory[i]);
798 free_pd(dev, pdp->page_directory[i]);
Ben Widawsky7ad47cf2014-02-20 11:51:21 -0800799 }
Michel Thierry69876be2015-04-08 12:13:27 +0100800
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100801 free_pdp(dev, pdp);
802
Mika Kuoppala8776f022015-06-30 18:16:40 +0300803 gen8_free_scratch(vm);
Ben Widawskyb45a6712014-02-12 14:28:44 -0800804}
805
Michel Thierryd7b26332015-04-08 12:13:34 +0100806/**
807 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100808 * @vm: Master vm structure.
809 * @pd: Page directory for this address range.
Michel Thierryd7b26332015-04-08 12:13:34 +0100810 * @start: Starting virtual address to begin allocations.
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100811 * @length: Size of the allocations.
Michel Thierryd7b26332015-04-08 12:13:34 +0100812 * @new_pts: Bitmap set by function with new allocations. Likely used by the
813 * caller to free on error.
814 *
815 * Allocate the required number of page tables. Extremely similar to
816 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
817 * the page directory boundary (instead of the page directory pointer). That
818 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
819 * possible, and likely that the caller will need to use multiple calls of this
820 * function to achieve the appropriate allocation.
821 *
822 * Return: 0 if success; negative error code otherwise.
823 */
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100824static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
Michel Thierrye5815a22015-04-08 12:13:32 +0100825 struct i915_page_directory *pd,
Michel Thierry5441f0c2015-04-08 12:13:28 +0100826 uint64_t start,
Michel Thierryd7b26332015-04-08 12:13:34 +0100827 uint64_t length,
828 unsigned long *new_pts)
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000829{
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100830 struct drm_device *dev = vm->dev;
Michel Thierryd7b26332015-04-08 12:13:34 +0100831 struct i915_page_table *pt;
Michel Thierry5441f0c2015-04-08 12:13:28 +0100832 uint64_t temp;
833 uint32_t pde;
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000834
Michel Thierryd7b26332015-04-08 12:13:34 +0100835 gen8_for_each_pde(pt, pd, start, length, temp, pde) {
836 /* Don't reallocate page tables */
Michel Thierry6ac18502015-07-29 17:23:46 +0100837 if (test_bit(pde, pd->used_pdes)) {
Michel Thierryd7b26332015-04-08 12:13:34 +0100838 /* Scratch is never allocated this way */
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100839 WARN_ON(pt == vm->scratch_pt);
Michel Thierryd7b26332015-04-08 12:13:34 +0100840 continue;
841 }
842
Mika Kuoppala8a1ebd72015-05-22 20:04:59 +0300843 pt = alloc_pt(dev);
Michel Thierryd7b26332015-04-08 12:13:34 +0100844 if (IS_ERR(pt))
Ben Widawsky06fda602015-02-24 16:22:36 +0000845 goto unwind_out;
Michel Thierry5441f0c2015-04-08 12:13:28 +0100846
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100847 gen8_initialize_pt(vm, pt);
Michel Thierryd7b26332015-04-08 12:13:34 +0100848 pd->page_table[pde] = pt;
Mika Kuoppala966082c2015-06-25 18:35:19 +0300849 __set_bit(pde, new_pts);
Michel Thierry4c06ec82015-07-29 17:23:49 +0100850 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000851 }
852
853 return 0;
854
855unwind_out:
Michel Thierryd7b26332015-04-08 12:13:34 +0100856 for_each_set_bit(pde, new_pts, I915_PDES)
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300857 free_pt(dev, pd->page_table[pde]);
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000858
859 return -ENOMEM;
860}
861
Michel Thierryd7b26332015-04-08 12:13:34 +0100862/**
863 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100864 * @vm: Master vm structure.
Michel Thierryd7b26332015-04-08 12:13:34 +0100865 * @pdp: Page directory pointer for this address range.
866 * @start: Starting virtual address to begin allocations.
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100867 * @length: Size of the allocations.
868 * @new_pds: Bitmap set by function with new allocations. Likely used by the
Michel Thierryd7b26332015-04-08 12:13:34 +0100869 * caller to free on error.
870 *
871 * Allocate the required number of page directories starting at the pde index of
872 * @start, and ending at the pde index @start + @length. This function will skip
873 * over already allocated page directories within the range, and only allocate
874 * new ones, setting the appropriate pointer within the pdp as well as the
875 * correct position in the bitmap @new_pds.
876 *
877 * The function will only allocate the pages within the range for a give page
878 * directory pointer. In other words, if @start + @length straddles a virtually
879 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
880 * required by the caller, This is not currently possible, and the BUG in the
881 * code will prevent it.
882 *
883 * Return: 0 if success; negative error code otherwise.
884 */
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100885static int
886gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
887 struct i915_page_directory_pointer *pdp,
888 uint64_t start,
889 uint64_t length,
890 unsigned long *new_pds)
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800891{
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100892 struct drm_device *dev = vm->dev;
Michel Thierryd7b26332015-04-08 12:13:34 +0100893 struct i915_page_directory *pd;
Michel Thierry69876be2015-04-08 12:13:27 +0100894 uint64_t temp;
895 uint32_t pdpe;
Michel Thierry6ac18502015-07-29 17:23:46 +0100896 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800897
Michel Thierry6ac18502015-07-29 17:23:46 +0100898 WARN_ON(!bitmap_empty(new_pds, pdpes));
Michel Thierryd7b26332015-04-08 12:13:34 +0100899
Michel Thierryd7b26332015-04-08 12:13:34 +0100900 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
Michel Thierry6ac18502015-07-29 17:23:46 +0100901 if (test_bit(pdpe, pdp->used_pdpes))
Michel Thierryd7b26332015-04-08 12:13:34 +0100902 continue;
Michel Thierry33c88192015-04-08 12:13:33 +0100903
Mika Kuoppala8a1ebd72015-05-22 20:04:59 +0300904 pd = alloc_pd(dev);
Michel Thierryd7b26332015-04-08 12:13:34 +0100905 if (IS_ERR(pd))
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000906 goto unwind_out;
Michel Thierry69876be2015-04-08 12:13:27 +0100907
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100908 gen8_initialize_pd(vm, pd);
Michel Thierryd7b26332015-04-08 12:13:34 +0100909 pdp->page_directory[pdpe] = pd;
Mika Kuoppala966082c2015-06-25 18:35:19 +0300910 __set_bit(pdpe, new_pds);
Michel Thierry4c06ec82015-07-29 17:23:49 +0100911 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000912 }
913
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800914 return 0;
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000915
916unwind_out:
Michel Thierry6ac18502015-07-29 17:23:46 +0100917 for_each_set_bit(pdpe, new_pds, pdpes)
Mika Kuoppalaa08e1112015-06-25 18:35:08 +0300918 free_pd(dev, pdp->page_directory[pdpe]);
Ben Widawskyd7b3de92015-02-24 16:22:34 +0000919
920 return -ENOMEM;
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800921}
922
Michel Thierryd7b26332015-04-08 12:13:34 +0100923static void
Michel Thierry6ac18502015-07-29 17:23:46 +0100924free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts,
925 uint32_t pdpes)
Michel Thierryd7b26332015-04-08 12:13:34 +0100926{
927 int i;
928
Michel Thierry6ac18502015-07-29 17:23:46 +0100929 for (i = 0; i < pdpes; i++)
Michel Thierryd7b26332015-04-08 12:13:34 +0100930 kfree(new_pts[i]);
931 kfree(new_pts);
932 kfree(new_pds);
933}
934
935/* Fills in the page directory bitmap, and the array of page tables bitmap. Both
936 * of these are based on the number of PDPEs in the system.
937 */
938static
939int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
Michel Thierry6ac18502015-07-29 17:23:46 +0100940 unsigned long ***new_pts,
941 uint32_t pdpes)
Michel Thierryd7b26332015-04-08 12:13:34 +0100942{
943 int i;
944 unsigned long *pds;
945 unsigned long **pts;
946
Michel Thierry6ac18502015-07-29 17:23:46 +0100947 pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_KERNEL);
Michel Thierryd7b26332015-04-08 12:13:34 +0100948 if (!pds)
949 return -ENOMEM;
950
Michel Thierry6ac18502015-07-29 17:23:46 +0100951 pts = kcalloc(pdpes, sizeof(unsigned long *), GFP_KERNEL);
Michel Thierryd7b26332015-04-08 12:13:34 +0100952 if (!pts) {
953 kfree(pds);
954 return -ENOMEM;
955 }
956
Michel Thierry6ac18502015-07-29 17:23:46 +0100957 for (i = 0; i < pdpes; i++) {
Michel Thierryd7b26332015-04-08 12:13:34 +0100958 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
959 sizeof(unsigned long), GFP_KERNEL);
960 if (!pts[i])
961 goto err_out;
962 }
963
964 *new_pds = pds;
965 *new_pts = pts;
966
967 return 0;
968
969err_out:
Michel Thierry6ac18502015-07-29 17:23:46 +0100970 free_gen8_temp_bitmaps(pds, pts, pdpes);
Michel Thierryd7b26332015-04-08 12:13:34 +0100971 return -ENOMEM;
972}
973
Mika Kuoppala5b7e4c92015-06-25 18:35:03 +0300974/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
975 * the page table structures, we mark them dirty so that
976 * context switching/execlist queuing code takes extra steps
977 * to ensure that tlbs are flushed.
978 */
979static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
980{
981 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
982}
983
Michel Thierrye5815a22015-04-08 12:13:32 +0100984static int gen8_alloc_va_range(struct i915_address_space *vm,
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100985 uint64_t start, uint64_t length)
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800986{
Michel Thierrye5815a22015-04-08 12:13:32 +0100987 struct i915_hw_ppgtt *ppgtt =
988 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierryd7b26332015-04-08 12:13:34 +0100989 unsigned long *new_page_dirs, **new_page_tables;
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100990 struct drm_device *dev = vm->dev;
991 struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
Michel Thierry5441f0c2015-04-08 12:13:28 +0100992 struct i915_page_directory *pd;
Michel Thierry33c88192015-04-08 12:13:33 +0100993 const uint64_t orig_start = start;
994 const uint64_t orig_length = length;
Michel Thierry5441f0c2015-04-08 12:13:28 +0100995 uint64_t temp;
996 uint32_t pdpe;
Michel Thierryd4ec9da2015-07-30 11:02:03 +0100997 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
Ben Widawskybf2b4ed2014-02-19 22:05:43 -0800998 int ret;
999
Michel Thierryd7b26332015-04-08 12:13:34 +01001000 /* Wrap is never okay since we can only represent 48b, and we don't
1001 * actually use the other side of the canonical address space.
1002 */
1003 if (WARN_ON(start + length < start))
Mika Kuoppalaa05d80e2015-06-25 18:35:04 +03001004 return -ENODEV;
1005
Michel Thierryd4ec9da2015-07-30 11:02:03 +01001006 if (WARN_ON(start + length > vm->total))
Mika Kuoppalaa05d80e2015-06-25 18:35:04 +03001007 return -ENODEV;
Michel Thierryd7b26332015-04-08 12:13:34 +01001008
Michel Thierry6ac18502015-07-29 17:23:46 +01001009 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
Ben Widawskybf2b4ed2014-02-19 22:05:43 -08001010 if (ret)
1011 return ret;
1012
Michel Thierryd7b26332015-04-08 12:13:34 +01001013 /* Do the allocations first so we can easily bail out */
Michel Thierryd4ec9da2015-07-30 11:02:03 +01001014 ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1015 new_page_dirs);
Michel Thierryd7b26332015-04-08 12:13:34 +01001016 if (ret) {
Michel Thierry6ac18502015-07-29 17:23:46 +01001017 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
Michel Thierryd7b26332015-04-08 12:13:34 +01001018 return ret;
1019 }
1020
1021 /* For every page directory referenced, allocate page tables */
Michel Thierryd4ec9da2015-07-30 11:02:03 +01001022 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1023 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
Michel Thierryd7b26332015-04-08 12:13:34 +01001024 new_page_tables[pdpe]);
Michel Thierry5441f0c2015-04-08 12:13:28 +01001025 if (ret)
1026 goto err_out;
Michel Thierry5441f0c2015-04-08 12:13:28 +01001027 }
1028
Michel Thierry33c88192015-04-08 12:13:33 +01001029 start = orig_start;
1030 length = orig_length;
1031
Michel Thierryd7b26332015-04-08 12:13:34 +01001032 /* Allocations have completed successfully, so set the bitmaps, and do
1033 * the mappings. */
Michel Thierryd4ec9da2015-07-30 11:02:03 +01001034 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001035 gen8_pde_t *const page_directory = kmap_px(pd);
Michel Thierry33c88192015-04-08 12:13:33 +01001036 struct i915_page_table *pt;
Michel Thierry09120d42015-07-29 17:23:45 +01001037 uint64_t pd_len = length;
Michel Thierry33c88192015-04-08 12:13:33 +01001038 uint64_t pd_start = start;
1039 uint32_t pde;
1040
Michel Thierryd7b26332015-04-08 12:13:34 +01001041 /* Every pd should be allocated, we just did that above. */
1042 WARN_ON(!pd);
1043
1044 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1045 /* Same reasoning as pd */
1046 WARN_ON(!pt);
1047 WARN_ON(!pd_len);
1048 WARN_ON(!gen8_pte_count(pd_start, pd_len));
1049
1050 /* Set our used ptes within the page table */
1051 bitmap_set(pt->used_ptes,
1052 gen8_pte_index(pd_start),
1053 gen8_pte_count(pd_start, pd_len));
1054
1055 /* Our pde is now pointing to the pagetable, pt */
Mika Kuoppala966082c2015-06-25 18:35:19 +03001056 __set_bit(pde, pd->used_pdes);
Michel Thierryd7b26332015-04-08 12:13:34 +01001057
1058 /* Map the PDE to the page table */
Mika Kuoppalafe36f552015-06-25 18:35:16 +03001059 page_directory[pde] = gen8_pde_encode(px_dma(pt),
1060 I915_CACHE_LLC);
Michel Thierry4c06ec82015-07-29 17:23:49 +01001061 trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1062 gen8_pte_index(start),
1063 gen8_pte_count(start, length),
1064 GEN8_PTES);
Michel Thierryd7b26332015-04-08 12:13:34 +01001065
1066 /* NB: We haven't yet mapped ptes to pages. At this
1067 * point we're still relying on insert_entries() */
Michel Thierry33c88192015-04-08 12:13:33 +01001068 }
Michel Thierryd7b26332015-04-08 12:13:34 +01001069
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001070 kunmap_px(ppgtt, page_directory);
Michel Thierryd4ec9da2015-07-30 11:02:03 +01001071 __set_bit(pdpe, pdp->used_pdpes);
Michel Thierry33c88192015-04-08 12:13:33 +01001072 }
1073
Michel Thierry6ac18502015-07-29 17:23:46 +01001074 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
Mika Kuoppala5b7e4c92015-06-25 18:35:03 +03001075 mark_tlbs_dirty(ppgtt);
Ben Widawskyd7b3de92015-02-24 16:22:34 +00001076 return 0;
1077
1078err_out:
Michel Thierryd7b26332015-04-08 12:13:34 +01001079 while (pdpe--) {
1080 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
Michel Thierryd4ec9da2015-07-30 11:02:03 +01001081 free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
Michel Thierryd7b26332015-04-08 12:13:34 +01001082 }
1083
Michel Thierry6ac18502015-07-29 17:23:46 +01001084 for_each_set_bit(pdpe, new_page_dirs, pdpes)
Michel Thierryd4ec9da2015-07-30 11:02:03 +01001085 free_pd(dev, pdp->page_directory[pdpe]);
Michel Thierryd7b26332015-04-08 12:13:34 +01001086
Michel Thierry6ac18502015-07-29 17:23:46 +01001087 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables, pdpes);
Mika Kuoppala5b7e4c92015-06-25 18:35:03 +03001088 mark_tlbs_dirty(ppgtt);
Ben Widawskybf2b4ed2014-02-19 22:05:43 -08001089 return ret;
1090}
1091
Daniel Vettereb0b44a2015-03-18 14:47:59 +01001092/*
Ben Widawskyf3a964b2014-02-19 22:05:42 -08001093 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1094 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1095 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1096 * space.
Ben Widawsky37aca442013-11-04 20:47:32 -08001097 *
Ben Widawskyf3a964b2014-02-19 22:05:42 -08001098 */
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001099static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
Ben Widawsky37aca442013-11-04 20:47:32 -08001100{
Mika Kuoppala8776f022015-06-30 18:16:40 +03001101 int ret;
Michel Thierry69876be2015-04-08 12:13:27 +01001102
Mika Kuoppala8776f022015-06-30 18:16:40 +03001103 ret = gen8_init_scratch(&ppgtt->base);
1104 if (ret)
1105 return ret;
Michel Thierry69876be2015-04-08 12:13:27 +01001106
Michel Thierryd7b26332015-04-08 12:13:34 +01001107 ppgtt->base.start = 0;
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001108 ppgtt->base.total = 1ULL << 32;
Michel Thierry501fd702015-05-29 14:15:05 +01001109 if (IS_ENABLED(CONFIG_X86_32))
1110 /* While we have a proliferation of size_t variables
1111 * we cannot represent the full ppgtt size on 32bit,
1112 * so limit it to the same size as the GGTT (currently
1113 * 2GiB).
1114 */
1115 ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
Michel Thierryd7b26332015-04-08 12:13:34 +01001116 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001117 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
Michel Thierryd7b26332015-04-08 12:13:34 +01001118 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
Daniel Vetterc7e16f22015-04-14 17:35:11 +02001119 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
Daniel Vetter777dc5b2015-04-14 17:35:12 +02001120 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1121 ppgtt->base.bind_vma = ppgtt_bind_vma;
Michel Thierryd7b26332015-04-08 12:13:34 +01001122
1123 ppgtt->switch_mm = gen8_mm_switch;
1124
Michel Thierry6ac18502015-07-29 17:23:46 +01001125 ret = __pdp_init(false, &ppgtt->pdp);
1126
1127 if (ret)
1128 goto free_scratch;
1129
Michel Thierryd7b26332015-04-08 12:13:34 +01001130 return 0;
Michel Thierry6ac18502015-07-29 17:23:46 +01001131
1132free_scratch:
1133 gen8_free_scratch(&ppgtt->base);
1134 return ret;
Michel Thierryd7b26332015-04-08 12:13:34 +01001135}
1136
Ben Widawsky87d60b62013-12-06 14:11:29 -08001137static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1138{
Ben Widawsky87d60b62013-12-06 14:11:29 -08001139 struct i915_address_space *vm = &ppgtt->base;
Michel Thierry09942c62015-04-08 12:13:30 +01001140 struct i915_page_table *unused;
Michel Thierry07749ef2015-03-16 16:00:54 +00001141 gen6_pte_t scratch_pte;
Ben Widawsky87d60b62013-12-06 14:11:29 -08001142 uint32_t pd_entry;
Michel Thierry09942c62015-04-08 12:13:30 +01001143 uint32_t pte, pde, temp;
1144 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
Ben Widawsky87d60b62013-12-06 14:11:29 -08001145
Mika Kuoppala79ab9372015-06-25 18:35:17 +03001146 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1147 I915_CACHE_LLC, true, 0);
Ben Widawsky87d60b62013-12-06 14:11:29 -08001148
Michel Thierry09942c62015-04-08 12:13:30 +01001149 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
Ben Widawsky87d60b62013-12-06 14:11:29 -08001150 u32 expected;
Michel Thierry07749ef2015-03-16 16:00:54 +00001151 gen6_pte_t *pt_vaddr;
Mika Kuoppala567047b2015-06-25 18:35:12 +03001152 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
Michel Thierry09942c62015-04-08 12:13:30 +01001153 pd_entry = readl(ppgtt->pd_addr + pde);
Ben Widawsky87d60b62013-12-06 14:11:29 -08001154 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1155
1156 if (pd_entry != expected)
1157 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1158 pde,
1159 pd_entry,
1160 expected);
1161 seq_printf(m, "\tPDE: %x\n", pd_entry);
1162
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001163 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1164
Michel Thierry07749ef2015-03-16 16:00:54 +00001165 for (pte = 0; pte < GEN6_PTES; pte+=4) {
Ben Widawsky87d60b62013-12-06 14:11:29 -08001166 unsigned long va =
Michel Thierry07749ef2015-03-16 16:00:54 +00001167 (pde * PAGE_SIZE * GEN6_PTES) +
Ben Widawsky87d60b62013-12-06 14:11:29 -08001168 (pte * PAGE_SIZE);
1169 int i;
1170 bool found = false;
1171 for (i = 0; i < 4; i++)
1172 if (pt_vaddr[pte + i] != scratch_pte)
1173 found = true;
1174 if (!found)
1175 continue;
1176
1177 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1178 for (i = 0; i < 4; i++) {
1179 if (pt_vaddr[pte + i] != scratch_pte)
1180 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1181 else
1182 seq_puts(m, " SCRATCH ");
1183 }
1184 seq_puts(m, "\n");
1185 }
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001186 kunmap_px(ppgtt, pt_vaddr);
Ben Widawsky87d60b62013-12-06 14:11:29 -08001187 }
1188}
1189
Ben Widawsky678d96f2015-03-16 16:00:56 +00001190/* Write pde (index) from the page directory @pd to the page table @pt */
Michel Thierryec565b32015-04-08 12:13:23 +01001191static void gen6_write_pde(struct i915_page_directory *pd,
1192 const int pde, struct i915_page_table *pt)
Ben Widawsky61973492013-04-08 18:43:54 -07001193{
Ben Widawsky678d96f2015-03-16 16:00:56 +00001194 /* Caller needs to make sure the write completes if necessary */
1195 struct i915_hw_ppgtt *ppgtt =
1196 container_of(pd, struct i915_hw_ppgtt, pd);
1197 u32 pd_entry;
Ben Widawsky61973492013-04-08 18:43:54 -07001198
Mika Kuoppala567047b2015-06-25 18:35:12 +03001199 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
Ben Widawsky678d96f2015-03-16 16:00:56 +00001200 pd_entry |= GEN6_PDE_VALID;
Ben Widawsky61973492013-04-08 18:43:54 -07001201
Ben Widawsky678d96f2015-03-16 16:00:56 +00001202 writel(pd_entry, ppgtt->pd_addr + pde);
1203}
Ben Widawsky61973492013-04-08 18:43:54 -07001204
Ben Widawsky678d96f2015-03-16 16:00:56 +00001205/* Write all the page tables found in the ppgtt structure to incrementing page
1206 * directories. */
1207static void gen6_write_page_range(struct drm_i915_private *dev_priv,
Michel Thierryec565b32015-04-08 12:13:23 +01001208 struct i915_page_directory *pd,
Ben Widawsky678d96f2015-03-16 16:00:56 +00001209 uint32_t start, uint32_t length)
1210{
Michel Thierryec565b32015-04-08 12:13:23 +01001211 struct i915_page_table *pt;
Ben Widawsky678d96f2015-03-16 16:00:56 +00001212 uint32_t pde, temp;
1213
1214 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1215 gen6_write_pde(pd, pde, pt);
1216
1217 /* Make sure write is complete before other code can use this page
1218 * table. Also require for WC mapped PTEs */
1219 readl(dev_priv->gtt.gsm);
Ben Widawsky3e302542013-04-23 23:15:32 -07001220}
1221
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001222static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
Ben Widawsky3e302542013-04-23 23:15:32 -07001223{
Mika Kuoppala44159dd2015-06-25 18:35:07 +03001224 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
Ben Widawsky3e302542013-04-23 23:15:32 -07001225
Mika Kuoppala44159dd2015-06-25 18:35:07 +03001226 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001227}
Ben Widawsky61973492013-04-08 18:43:54 -07001228
Ben Widawsky90252e52013-12-06 14:11:12 -08001229static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
John Harrisone85b26d2015-05-29 17:43:56 +01001230 struct drm_i915_gem_request *req)
Ben Widawsky90252e52013-12-06 14:11:12 -08001231{
John Harrisone85b26d2015-05-29 17:43:56 +01001232 struct intel_engine_cs *ring = req->ring;
Ben Widawsky90252e52013-12-06 14:11:12 -08001233 int ret;
Ben Widawsky61973492013-04-08 18:43:54 -07001234
Ben Widawsky90252e52013-12-06 14:11:12 -08001235 /* NB: TLBs must be flushed and invalidated before a switch */
John Harrisona84c3ae2015-05-29 17:43:57 +01001236 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
Ben Widawsky90252e52013-12-06 14:11:12 -08001237 if (ret)
1238 return ret;
1239
John Harrison5fb9de12015-05-29 17:44:07 +01001240 ret = intel_ring_begin(req, 6);
Ben Widawsky90252e52013-12-06 14:11:12 -08001241 if (ret)
1242 return ret;
1243
1244 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1245 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1246 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1247 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1248 intel_ring_emit(ring, get_pd_offset(ppgtt));
1249 intel_ring_emit(ring, MI_NOOP);
1250 intel_ring_advance(ring);
1251
1252 return 0;
1253}
1254
Yu Zhang71ba2d62015-02-10 19:05:54 +08001255static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
John Harrisone85b26d2015-05-29 17:43:56 +01001256 struct drm_i915_gem_request *req)
Yu Zhang71ba2d62015-02-10 19:05:54 +08001257{
John Harrisone85b26d2015-05-29 17:43:56 +01001258 struct intel_engine_cs *ring = req->ring;
Yu Zhang71ba2d62015-02-10 19:05:54 +08001259 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1260
1261 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1262 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1263 return 0;
1264}
1265
Ben Widawsky48a10382013-12-06 14:11:11 -08001266static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
John Harrisone85b26d2015-05-29 17:43:56 +01001267 struct drm_i915_gem_request *req)
Ben Widawsky48a10382013-12-06 14:11:11 -08001268{
John Harrisone85b26d2015-05-29 17:43:56 +01001269 struct intel_engine_cs *ring = req->ring;
Ben Widawsky48a10382013-12-06 14:11:11 -08001270 int ret;
1271
Ben Widawsky48a10382013-12-06 14:11:11 -08001272 /* NB: TLBs must be flushed and invalidated before a switch */
John Harrisona84c3ae2015-05-29 17:43:57 +01001273 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
Ben Widawsky48a10382013-12-06 14:11:11 -08001274 if (ret)
1275 return ret;
1276
John Harrison5fb9de12015-05-29 17:44:07 +01001277 ret = intel_ring_begin(req, 6);
Ben Widawsky48a10382013-12-06 14:11:11 -08001278 if (ret)
1279 return ret;
1280
1281 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1282 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1283 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1284 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1285 intel_ring_emit(ring, get_pd_offset(ppgtt));
1286 intel_ring_emit(ring, MI_NOOP);
1287 intel_ring_advance(ring);
1288
Ben Widawsky90252e52013-12-06 14:11:12 -08001289 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1290 if (ring->id != RCS) {
John Harrisona84c3ae2015-05-29 17:43:57 +01001291 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
Ben Widawsky90252e52013-12-06 14:11:12 -08001292 if (ret)
1293 return ret;
1294 }
1295
Ben Widawsky48a10382013-12-06 14:11:11 -08001296 return 0;
1297}
1298
Ben Widawskyeeb94882013-12-06 14:11:10 -08001299static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
John Harrisone85b26d2015-05-29 17:43:56 +01001300 struct drm_i915_gem_request *req)
Ben Widawskyeeb94882013-12-06 14:11:10 -08001301{
John Harrisone85b26d2015-05-29 17:43:56 +01001302 struct intel_engine_cs *ring = req->ring;
Ben Widawskyeeb94882013-12-06 14:11:10 -08001303 struct drm_device *dev = ppgtt->base.dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305
Ben Widawsky48a10382013-12-06 14:11:11 -08001306
Ben Widawskyeeb94882013-12-06 14:11:10 -08001307 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1308 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1309
1310 POSTING_READ(RING_PP_DIR_DCLV(ring));
1311
1312 return 0;
1313}
1314
Daniel Vetter82460d92014-08-06 20:19:53 +02001315static void gen8_ppgtt_enable(struct drm_device *dev)
Ben Widawskyeeb94882013-12-06 14:11:10 -08001316{
Ben Widawskyeeb94882013-12-06 14:11:10 -08001317 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001318 struct intel_engine_cs *ring;
Daniel Vetter82460d92014-08-06 20:19:53 +02001319 int j;
Ben Widawskyeeb94882013-12-06 14:11:10 -08001320
1321 for_each_ring(ring, dev_priv, j) {
1322 I915_WRITE(RING_MODE_GEN7(ring),
1323 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
Ben Widawskyeeb94882013-12-06 14:11:10 -08001324 }
Ben Widawskyeeb94882013-12-06 14:11:10 -08001325}
1326
Daniel Vetter82460d92014-08-06 20:19:53 +02001327static void gen7_ppgtt_enable(struct drm_device *dev)
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001328{
Jani Nikula50227e12014-03-31 14:27:21 +03001329 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001330 struct intel_engine_cs *ring;
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001331 uint32_t ecochk, ecobits;
1332 int i;
1333
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001334 ecobits = I915_READ(GAC_ECO_BITS);
1335 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1336
1337 ecochk = I915_READ(GAM_ECOCHK);
1338 if (IS_HASWELL(dev)) {
1339 ecochk |= ECOCHK_PPGTT_WB_HSW;
1340 } else {
1341 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1342 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1343 }
1344 I915_WRITE(GAM_ECOCHK, ecochk);
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001345
Ben Widawsky61973492013-04-08 18:43:54 -07001346 for_each_ring(ring, dev_priv, i) {
Ben Widawskyeeb94882013-12-06 14:11:10 -08001347 /* GFX_MODE is per-ring on gen7+ */
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001348 I915_WRITE(RING_MODE_GEN7(ring),
1349 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
Ben Widawsky61973492013-04-08 18:43:54 -07001350 }
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001351}
1352
Daniel Vetter82460d92014-08-06 20:19:53 +02001353static void gen6_ppgtt_enable(struct drm_device *dev)
Ben Widawsky61973492013-04-08 18:43:54 -07001354{
Jani Nikula50227e12014-03-31 14:27:21 +03001355 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001356 uint32_t ecochk, gab_ctl, ecobits;
Ben Widawsky61973492013-04-08 18:43:54 -07001357
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001358 ecobits = I915_READ(GAC_ECO_BITS);
1359 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1360 ECOBITS_PPGTT_CACHE64B);
Ben Widawsky61973492013-04-08 18:43:54 -07001361
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001362 gab_ctl = I915_READ(GAB_CTL);
1363 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
Ben Widawsky61973492013-04-08 18:43:54 -07001364
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001365 ecochk = I915_READ(GAM_ECOCHK);
1366 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
Ben Widawsky61973492013-04-08 18:43:54 -07001367
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001368 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
Ben Widawsky61973492013-04-08 18:43:54 -07001369}
1370
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001371/* PPGTT support for Sandybdrige/Gen6 and later */
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001372static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
Ben Widawsky782f1492014-02-20 11:50:33 -08001373 uint64_t start,
1374 uint64_t length,
Ben Widawsky828c7902013-10-16 09:21:30 -07001375 bool use_scratch)
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001376{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001377 struct i915_hw_ppgtt *ppgtt =
1378 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierry07749ef2015-03-16 16:00:54 +00001379 gen6_pte_t *pt_vaddr, scratch_pte;
Ben Widawsky782f1492014-02-20 11:50:33 -08001380 unsigned first_entry = start >> PAGE_SHIFT;
1381 unsigned num_entries = length >> PAGE_SHIFT;
Michel Thierry07749ef2015-03-16 16:00:54 +00001382 unsigned act_pt = first_entry / GEN6_PTES;
1383 unsigned first_pte = first_entry % GEN6_PTES;
Daniel Vetter7bddb012012-02-09 17:15:47 +01001384 unsigned last_pte, i;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001385
Mika Kuoppalac114f762015-06-25 18:35:13 +03001386 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1387 I915_CACHE_LLC, true, 0);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001388
Daniel Vetter7bddb012012-02-09 17:15:47 +01001389 while (num_entries) {
1390 last_pte = first_pte + num_entries;
Michel Thierry07749ef2015-03-16 16:00:54 +00001391 if (last_pte > GEN6_PTES)
1392 last_pte = GEN6_PTES;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001393
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001394 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
Daniel Vetter7bddb012012-02-09 17:15:47 +01001395
1396 for (i = first_pte; i < last_pte; i++)
1397 pt_vaddr[i] = scratch_pte;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001398
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001399 kunmap_px(ppgtt, pt_vaddr);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001400
Daniel Vetter7bddb012012-02-09 17:15:47 +01001401 num_entries -= last_pte - first_pte;
1402 first_pte = 0;
Daniel Vettera15326a2013-03-19 23:48:39 +01001403 act_pt++;
Daniel Vetter7bddb012012-02-09 17:15:47 +01001404 }
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001405}
1406
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001407static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
Daniel Vetterdef886c2013-01-24 14:44:56 -08001408 struct sg_table *pages,
Ben Widawsky782f1492014-02-20 11:50:33 -08001409 uint64_t start,
Akash Goel24f3a8c2014-06-17 10:59:42 +05301410 enum i915_cache_level cache_level, u32 flags)
Daniel Vetterdef886c2013-01-24 14:44:56 -08001411{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001412 struct i915_hw_ppgtt *ppgtt =
1413 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierry07749ef2015-03-16 16:00:54 +00001414 gen6_pte_t *pt_vaddr;
Ben Widawsky782f1492014-02-20 11:50:33 -08001415 unsigned first_entry = start >> PAGE_SHIFT;
Michel Thierry07749ef2015-03-16 16:00:54 +00001416 unsigned act_pt = first_entry / GEN6_PTES;
1417 unsigned act_pte = first_entry % GEN6_PTES;
Imre Deak6e995e22013-02-18 19:28:04 +02001418 struct sg_page_iter sg_iter;
Daniel Vetterdef886c2013-01-24 14:44:56 -08001419
Chris Wilsoncc797142013-12-31 15:50:30 +00001420 pt_vaddr = NULL;
Imre Deak6e995e22013-02-18 19:28:04 +02001421 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
Chris Wilsoncc797142013-12-31 15:50:30 +00001422 if (pt_vaddr == NULL)
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001423 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
Daniel Vetterdef886c2013-01-24 14:44:56 -08001424
Chris Wilsoncc797142013-12-31 15:50:30 +00001425 pt_vaddr[act_pte] =
1426 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
Akash Goel24f3a8c2014-06-17 10:59:42 +05301427 cache_level, true, flags);
1428
Michel Thierry07749ef2015-03-16 16:00:54 +00001429 if (++act_pte == GEN6_PTES) {
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001430 kunmap_px(ppgtt, pt_vaddr);
Chris Wilsoncc797142013-12-31 15:50:30 +00001431 pt_vaddr = NULL;
Daniel Vettera15326a2013-03-19 23:48:39 +01001432 act_pt++;
Imre Deak6e995e22013-02-18 19:28:04 +02001433 act_pte = 0;
Daniel Vetterdef886c2013-01-24 14:44:56 -08001434 }
Daniel Vetterdef886c2013-01-24 14:44:56 -08001435 }
Chris Wilsoncc797142013-12-31 15:50:30 +00001436 if (pt_vaddr)
Mika Kuoppalad1c54ac2015-06-25 18:35:11 +03001437 kunmap_px(ppgtt, pt_vaddr);
Daniel Vetterdef886c2013-01-24 14:44:56 -08001438}
1439
Ben Widawsky678d96f2015-03-16 16:00:56 +00001440static int gen6_alloc_va_range(struct i915_address_space *vm,
Mika Kuoppalaa05d80e2015-06-25 18:35:04 +03001441 uint64_t start_in, uint64_t length_in)
Ben Widawsky678d96f2015-03-16 16:00:56 +00001442{
Michel Thierry4933d512015-03-24 15:46:22 +00001443 DECLARE_BITMAP(new_page_tables, I915_PDES);
1444 struct drm_device *dev = vm->dev;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky678d96f2015-03-16 16:00:56 +00001446 struct i915_hw_ppgtt *ppgtt =
1447 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierryec565b32015-04-08 12:13:23 +01001448 struct i915_page_table *pt;
Mika Kuoppalaa05d80e2015-06-25 18:35:04 +03001449 uint32_t start, length, start_save, length_save;
Ben Widawsky678d96f2015-03-16 16:00:56 +00001450 uint32_t pde, temp;
Michel Thierry4933d512015-03-24 15:46:22 +00001451 int ret;
1452
Mika Kuoppalaa05d80e2015-06-25 18:35:04 +03001453 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1454 return -ENODEV;
1455
1456 start = start_save = start_in;
1457 length = length_save = length_in;
Michel Thierry4933d512015-03-24 15:46:22 +00001458
1459 bitmap_zero(new_page_tables, I915_PDES);
1460
1461 /* The allocation is done in two stages so that we can bail out with
1462 * minimal amount of pain. The first stage finds new page tables that
1463 * need allocation. The second stage marks use ptes within the page
1464 * tables.
1465 */
1466 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
Mika Kuoppala79ab9372015-06-25 18:35:17 +03001467 if (pt != vm->scratch_pt) {
Michel Thierry4933d512015-03-24 15:46:22 +00001468 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1469 continue;
1470 }
1471
1472 /* We've already allocated a page table */
1473 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1474
Mika Kuoppala8a1ebd72015-05-22 20:04:59 +03001475 pt = alloc_pt(dev);
Michel Thierry4933d512015-03-24 15:46:22 +00001476 if (IS_ERR(pt)) {
1477 ret = PTR_ERR(pt);
1478 goto unwind_out;
1479 }
1480
1481 gen6_initialize_pt(vm, pt);
1482
1483 ppgtt->pd.page_table[pde] = pt;
Mika Kuoppala966082c2015-06-25 18:35:19 +03001484 __set_bit(pde, new_page_tables);
Michel Thierry72744cb2015-03-24 15:46:23 +00001485 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
Michel Thierry4933d512015-03-24 15:46:22 +00001486 }
1487
1488 start = start_save;
1489 length = length_save;
Ben Widawsky678d96f2015-03-16 16:00:56 +00001490
1491 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1492 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1493
1494 bitmap_zero(tmp_bitmap, GEN6_PTES);
1495 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1496 gen6_pte_count(start, length));
1497
Mika Kuoppala966082c2015-06-25 18:35:19 +03001498 if (__test_and_clear_bit(pde, new_page_tables))
Michel Thierry4933d512015-03-24 15:46:22 +00001499 gen6_write_pde(&ppgtt->pd, pde, pt);
1500
Michel Thierry72744cb2015-03-24 15:46:23 +00001501 trace_i915_page_table_entry_map(vm, pde, pt,
1502 gen6_pte_index(start),
1503 gen6_pte_count(start, length),
1504 GEN6_PTES);
Michel Thierry4933d512015-03-24 15:46:22 +00001505 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
Ben Widawsky678d96f2015-03-16 16:00:56 +00001506 GEN6_PTES);
1507 }
1508
Michel Thierry4933d512015-03-24 15:46:22 +00001509 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1510
1511 /* Make sure write is complete before other code can use this page
1512 * table. Also require for WC mapped PTEs */
1513 readl(dev_priv->gtt.gsm);
1514
Ben Widawsky563222a2015-03-19 12:53:28 +00001515 mark_tlbs_dirty(ppgtt);
Ben Widawsky678d96f2015-03-16 16:00:56 +00001516 return 0;
Michel Thierry4933d512015-03-24 15:46:22 +00001517
1518unwind_out:
1519 for_each_set_bit(pde, new_page_tables, I915_PDES) {
Michel Thierryec565b32015-04-08 12:13:23 +01001520 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
Michel Thierry4933d512015-03-24 15:46:22 +00001521
Mika Kuoppala79ab9372015-06-25 18:35:17 +03001522 ppgtt->pd.page_table[pde] = vm->scratch_pt;
Mika Kuoppalaa08e1112015-06-25 18:35:08 +03001523 free_pt(vm->dev, pt);
Michel Thierry4933d512015-03-24 15:46:22 +00001524 }
1525
1526 mark_tlbs_dirty(ppgtt);
1527 return ret;
Ben Widawsky678d96f2015-03-16 16:00:56 +00001528}
1529
Mika Kuoppala8776f022015-06-30 18:16:40 +03001530static int gen6_init_scratch(struct i915_address_space *vm)
1531{
1532 struct drm_device *dev = vm->dev;
1533
1534 vm->scratch_page = alloc_scratch_page(dev);
1535 if (IS_ERR(vm->scratch_page))
1536 return PTR_ERR(vm->scratch_page);
1537
1538 vm->scratch_pt = alloc_pt(dev);
1539 if (IS_ERR(vm->scratch_pt)) {
1540 free_scratch_page(dev, vm->scratch_page);
1541 return PTR_ERR(vm->scratch_pt);
1542 }
1543
1544 gen6_initialize_pt(vm, vm->scratch_pt);
1545
1546 return 0;
1547}
1548
1549static void gen6_free_scratch(struct i915_address_space *vm)
1550{
1551 struct drm_device *dev = vm->dev;
1552
1553 free_pt(dev, vm->scratch_pt);
1554 free_scratch_page(dev, vm->scratch_page);
1555}
1556
Daniel Vetter061dd492015-04-14 17:35:13 +02001557static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
Ben Widawskya00d8252014-02-19 22:05:48 -08001558{
Daniel Vetter061dd492015-04-14 17:35:13 +02001559 struct i915_hw_ppgtt *ppgtt =
1560 container_of(vm, struct i915_hw_ppgtt, base);
Michel Thierry09942c62015-04-08 12:13:30 +01001561 struct i915_page_table *pt;
1562 uint32_t pde;
Daniel Vetter3440d262013-01-24 13:49:56 -08001563
Daniel Vetter061dd492015-04-14 17:35:13 +02001564 drm_mm_remove_node(&ppgtt->node);
1565
Michel Thierry09942c62015-04-08 12:13:30 +01001566 gen6_for_all_pdes(pt, ppgtt, pde) {
Mika Kuoppala79ab9372015-06-25 18:35:17 +03001567 if (pt != vm->scratch_pt)
Mika Kuoppalaa08e1112015-06-25 18:35:08 +03001568 free_pt(ppgtt->base.dev, pt);
Michel Thierry4933d512015-03-24 15:46:22 +00001569 }
1570
Mika Kuoppala8776f022015-06-30 18:16:40 +03001571 gen6_free_scratch(vm);
Daniel Vetter3440d262013-01-24 13:49:56 -08001572}
1573
Ben Widawskyb1465202014-02-19 22:05:49 -08001574static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
Daniel Vetter3440d262013-01-24 13:49:56 -08001575{
Mika Kuoppala8776f022015-06-30 18:16:40 +03001576 struct i915_address_space *vm = &ppgtt->base;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001577 struct drm_device *dev = ppgtt->base.dev;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001578 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskye3cc1992013-12-06 14:11:08 -08001579 bool retried = false;
Ben Widawskyb1465202014-02-19 22:05:49 -08001580 int ret;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001581
Ben Widawskyc8d4c0d2013-12-06 14:11:07 -08001582 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1583 * allocator works in address space sizes, so it's multiplied by page
1584 * size. We allocate at the top of the GTT to avoid fragmentation.
1585 */
1586 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
Michel Thierry4933d512015-03-24 15:46:22 +00001587
Mika Kuoppala8776f022015-06-30 18:16:40 +03001588 ret = gen6_init_scratch(vm);
1589 if (ret)
1590 return ret;
Michel Thierry4933d512015-03-24 15:46:22 +00001591
Ben Widawskye3cc1992013-12-06 14:11:08 -08001592alloc:
Ben Widawskyc8d4c0d2013-12-06 14:11:07 -08001593 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1594 &ppgtt->node, GEN6_PD_SIZE,
1595 GEN6_PD_ALIGN, 0,
1596 0, dev_priv->gtt.base.total,
Ben Widawsky3e8b5ae2014-05-06 22:21:30 -07001597 DRM_MM_TOPDOWN);
Ben Widawskye3cc1992013-12-06 14:11:08 -08001598 if (ret == -ENOSPC && !retried) {
1599 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1600 GEN6_PD_SIZE, GEN6_PD_ALIGN,
Chris Wilsond23db882014-05-23 08:48:08 +02001601 I915_CACHE_NONE,
1602 0, dev_priv->gtt.base.total,
1603 0);
Ben Widawskye3cc1992013-12-06 14:11:08 -08001604 if (ret)
Ben Widawsky678d96f2015-03-16 16:00:56 +00001605 goto err_out;
Ben Widawskye3cc1992013-12-06 14:11:08 -08001606
1607 retried = true;
1608 goto alloc;
1609 }
Ben Widawskyc8d4c0d2013-12-06 14:11:07 -08001610
Ben Widawskyc8c26622015-01-22 17:01:25 +00001611 if (ret)
Ben Widawsky678d96f2015-03-16 16:00:56 +00001612 goto err_out;
1613
Ben Widawskyc8c26622015-01-22 17:01:25 +00001614
Ben Widawskyc8d4c0d2013-12-06 14:11:07 -08001615 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1616 DRM_DEBUG("Forced to use aperture for PDEs\n");
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001617
Ben Widawskyc8c26622015-01-22 17:01:25 +00001618 return 0;
Ben Widawsky678d96f2015-03-16 16:00:56 +00001619
1620err_out:
Mika Kuoppala8776f022015-06-30 18:16:40 +03001621 gen6_free_scratch(vm);
Ben Widawsky678d96f2015-03-16 16:00:56 +00001622 return ret;
Ben Widawskyb1465202014-02-19 22:05:49 -08001623}
1624
Ben Widawskyb1465202014-02-19 22:05:49 -08001625static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1626{
kbuild test robot2f2cf682015-03-27 19:26:35 +08001627 return gen6_ppgtt_allocate_page_directories(ppgtt);
Ben Widawskyb1465202014-02-19 22:05:49 -08001628}
1629
Michel Thierry4933d512015-03-24 15:46:22 +00001630static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1631 uint64_t start, uint64_t length)
1632{
Michel Thierryec565b32015-04-08 12:13:23 +01001633 struct i915_page_table *unused;
Michel Thierry4933d512015-03-24 15:46:22 +00001634 uint32_t pde, temp;
1635
1636 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
Mika Kuoppala79ab9372015-06-25 18:35:17 +03001637 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
Michel Thierry4933d512015-03-24 15:46:22 +00001638}
1639
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001640static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
Ben Widawskyb1465202014-02-19 22:05:49 -08001641{
1642 struct drm_device *dev = ppgtt->base.dev;
1643 struct drm_i915_private *dev_priv = dev->dev_private;
1644 int ret;
1645
1646 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
Ben Widawsky48a10382013-12-06 14:11:11 -08001647 if (IS_GEN6(dev)) {
Ben Widawsky48a10382013-12-06 14:11:11 -08001648 ppgtt->switch_mm = gen6_mm_switch;
Ben Widawsky90252e52013-12-06 14:11:12 -08001649 } else if (IS_HASWELL(dev)) {
Ben Widawsky90252e52013-12-06 14:11:12 -08001650 ppgtt->switch_mm = hsw_mm_switch;
Ben Widawsky48a10382013-12-06 14:11:11 -08001651 } else if (IS_GEN7(dev)) {
Ben Widawsky48a10382013-12-06 14:11:11 -08001652 ppgtt->switch_mm = gen7_mm_switch;
1653 } else
Ben Widawskyb4a74e32013-12-06 14:11:09 -08001654 BUG();
Ben Widawskyb1465202014-02-19 22:05:49 -08001655
Yu Zhang71ba2d62015-02-10 19:05:54 +08001656 if (intel_vgpu_active(dev))
1657 ppgtt->switch_mm = vgpu_mm_switch;
1658
Ben Widawskyb1465202014-02-19 22:05:49 -08001659 ret = gen6_ppgtt_alloc(ppgtt);
1660 if (ret)
1661 return ret;
1662
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001663 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001664 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1665 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
Daniel Vetter777dc5b2015-04-14 17:35:12 +02001666 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1667 ppgtt->base.bind_vma = ppgtt_bind_vma;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001668 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
Ben Widawsky686e1f62013-11-25 09:54:34 -08001669 ppgtt->base.start = 0;
Michel Thierry09942c62015-04-08 12:13:30 +01001670 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
Ben Widawskyb1465202014-02-19 22:05:49 -08001671 ppgtt->debug_dump = gen6_dump_ppgtt;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001672
Mika Kuoppala44159dd2015-06-25 18:35:07 +03001673 ppgtt->pd.base.ggtt_offset =
Michel Thierry07749ef2015-03-16 16:00:54 +00001674 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001675
Ben Widawsky678d96f2015-03-16 16:00:56 +00001676 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
Mika Kuoppala44159dd2015-06-25 18:35:07 +03001677 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
Ben Widawsky678d96f2015-03-16 16:00:56 +00001678
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001679 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001680
Ben Widawsky678d96f2015-03-16 16:00:56 +00001681 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1682
Thierry Reding440fd522015-01-23 09:05:06 +01001683 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
Ben Widawskyc8d4c0d2013-12-06 14:11:07 -08001684 ppgtt->node.size >> 20,
1685 ppgtt->node.start / PAGE_SIZE);
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001686
Daniel Vetterfa76da32014-08-06 20:19:54 +02001687 DRM_DEBUG("Adding PPGTT at offset %x\n",
Mika Kuoppala44159dd2015-06-25 18:35:07 +03001688 ppgtt->pd.base.ggtt_offset << 10);
Daniel Vetterfa76da32014-08-06 20:19:54 +02001689
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001690 return 0;
Daniel Vetter3440d262013-01-24 13:49:56 -08001691}
1692
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001693static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
Daniel Vetter3440d262013-01-24 13:49:56 -08001694{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001695 ppgtt->base.dev = dev;
Daniel Vetter3440d262013-01-24 13:49:56 -08001696
Ben Widawsky3ed124b2013-04-08 18:43:53 -07001697 if (INTEL_INFO(dev)->gen < 8)
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001698 return gen6_ppgtt_init(ppgtt);
Ben Widawsky3ed124b2013-04-08 18:43:53 -07001699 else
Michel Thierryd7b26332015-04-08 12:13:34 +01001700 return gen8_ppgtt_init(ppgtt);
Daniel Vetterfa76da32014-08-06 20:19:54 +02001701}
Mika Kuoppalac114f762015-06-25 18:35:13 +03001702
Daniel Vetterfa76da32014-08-06 20:19:54 +02001703int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1704{
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int ret = 0;
Ben Widawsky3ed124b2013-04-08 18:43:53 -07001707
Daniel Vetter5c5f6452015-04-14 17:35:14 +02001708 ret = __hw_ppgtt_init(dev, ppgtt);
Daniel Vetterfa76da32014-08-06 20:19:54 +02001709 if (ret == 0) {
Ben Widawskyc7c48df2013-12-06 14:11:15 -08001710 kref_init(&ppgtt->ref);
Ben Widawsky93bd8642013-07-16 16:50:06 -07001711 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1712 ppgtt->base.total);
Ben Widawsky7e0d96b2013-12-06 14:11:26 -08001713 i915_init_vm(dev_priv, &ppgtt->base);
Ben Widawsky93bd8642013-07-16 16:50:06 -07001714 }
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001715
1716 return ret;
1717}
1718
Daniel Vetter82460d92014-08-06 20:19:53 +02001719int i915_ppgtt_init_hw(struct drm_device *dev)
1720{
Thomas Daniel671b50132014-08-20 16:24:50 +01001721 /* In the case of execlists, PPGTT is enabled by the context descriptor
1722 * and the PDPs are contained within the context itself. We don't
1723 * need to do anything here. */
1724 if (i915.enable_execlists)
1725 return 0;
1726
Daniel Vetter82460d92014-08-06 20:19:53 +02001727 if (!USES_PPGTT(dev))
1728 return 0;
1729
1730 if (IS_GEN6(dev))
1731 gen6_ppgtt_enable(dev);
1732 else if (IS_GEN7(dev))
1733 gen7_ppgtt_enable(dev);
1734 else if (INTEL_INFO(dev)->gen >= 8)
1735 gen8_ppgtt_enable(dev);
1736 else
Daniel Vetter5f77eeb2014-12-08 16:40:10 +01001737 MISSING_CASE(INTEL_INFO(dev)->gen);
Daniel Vetter82460d92014-08-06 20:19:53 +02001738
John Harrison4ad2fd82015-06-18 13:11:20 +01001739 return 0;
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001740}
John Harrison4ad2fd82015-06-18 13:11:20 +01001741
John Harrisonb3dd6b92015-05-29 17:43:40 +01001742int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
John Harrison4ad2fd82015-06-18 13:11:20 +01001743{
John Harrisonb3dd6b92015-05-29 17:43:40 +01001744 struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
John Harrison4ad2fd82015-06-18 13:11:20 +01001745 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1746
1747 if (i915.enable_execlists)
1748 return 0;
1749
1750 if (!ppgtt)
1751 return 0;
1752
John Harrisone85b26d2015-05-29 17:43:56 +01001753 return ppgtt->switch_mm(ppgtt, req);
John Harrison4ad2fd82015-06-18 13:11:20 +01001754}
1755
Daniel Vetter4d884702014-08-06 15:04:47 +02001756struct i915_hw_ppgtt *
1757i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1758{
1759 struct i915_hw_ppgtt *ppgtt;
1760 int ret;
1761
1762 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1763 if (!ppgtt)
1764 return ERR_PTR(-ENOMEM);
1765
1766 ret = i915_ppgtt_init(dev, ppgtt);
1767 if (ret) {
1768 kfree(ppgtt);
1769 return ERR_PTR(ret);
1770 }
1771
1772 ppgtt->file_priv = fpriv;
1773
Daniele Ceraolo Spurio198c9742014-11-10 13:44:31 +00001774 trace_i915_ppgtt_create(&ppgtt->base);
1775
Daniel Vetter4d884702014-08-06 15:04:47 +02001776 return ppgtt;
1777}
1778
Daniel Vetteree960be2014-08-06 15:04:45 +02001779void i915_ppgtt_release(struct kref *kref)
1780{
1781 struct i915_hw_ppgtt *ppgtt =
1782 container_of(kref, struct i915_hw_ppgtt, ref);
1783
Daniele Ceraolo Spurio198c9742014-11-10 13:44:31 +00001784 trace_i915_ppgtt_release(&ppgtt->base);
1785
Daniel Vetteree960be2014-08-06 15:04:45 +02001786 /* vmas should already be unbound */
1787 WARN_ON(!list_empty(&ppgtt->base.active_list));
1788 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1789
Daniel Vetter19dd1202014-08-06 15:04:55 +02001790 list_del(&ppgtt->base.global_link);
1791 drm_mm_takedown(&ppgtt->base.mm);
1792
Daniel Vetteree960be2014-08-06 15:04:45 +02001793 ppgtt->base.cleanup(&ppgtt->base);
1794 kfree(ppgtt);
1795}
Daniel Vetter1d2a3142012-02-09 17:15:46 +01001796
Ben Widawskya81cc002013-01-18 12:30:31 -08001797extern int intel_iommu_gfx_mapped;
1798/* Certain Gen5 chipsets require require idling the GPU before
1799 * unmapping anything from the GTT when VT-d is enabled.
1800 */
Daniel Vetter2c642b02015-04-14 17:35:26 +02001801static bool needs_idle_maps(struct drm_device *dev)
Ben Widawskya81cc002013-01-18 12:30:31 -08001802{
1803#ifdef CONFIG_INTEL_IOMMU
1804 /* Query intel_iommu to see if we need the workaround. Presumably that
1805 * was loaded first.
1806 */
1807 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1808 return true;
1809#endif
1810 return false;
1811}
1812
Ben Widawsky5c042282011-10-17 15:51:55 -07001813static bool do_idling(struct drm_i915_private *dev_priv)
1814{
1815 bool ret = dev_priv->mm.interruptible;
1816
Ben Widawskya81cc002013-01-18 12:30:31 -08001817 if (unlikely(dev_priv->gtt.do_idle_maps)) {
Ben Widawsky5c042282011-10-17 15:51:55 -07001818 dev_priv->mm.interruptible = false;
Ben Widawskyb2da9fe2012-04-26 16:02:58 -07001819 if (i915_gpu_idle(dev_priv->dev)) {
Ben Widawsky5c042282011-10-17 15:51:55 -07001820 DRM_ERROR("Couldn't idle GPU\n");
1821 /* Wait a bit, in hopes it avoids the hang */
1822 udelay(10);
1823 }
1824 }
1825
1826 return ret;
1827}
1828
1829static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1830{
Ben Widawskya81cc002013-01-18 12:30:31 -08001831 if (unlikely(dev_priv->gtt.do_idle_maps))
Ben Widawsky5c042282011-10-17 15:51:55 -07001832 dev_priv->mm.interruptible = interruptible;
1833}
1834
Ben Widawsky828c7902013-10-16 09:21:30 -07001835void i915_check_and_clear_faults(struct drm_device *dev)
1836{
1837 struct drm_i915_private *dev_priv = dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01001838 struct intel_engine_cs *ring;
Ben Widawsky828c7902013-10-16 09:21:30 -07001839 int i;
1840
1841 if (INTEL_INFO(dev)->gen < 6)
1842 return;
1843
1844 for_each_ring(ring, dev_priv, i) {
1845 u32 fault_reg;
1846 fault_reg = I915_READ(RING_FAULT_REG(ring));
1847 if (fault_reg & RING_FAULT_VALID) {
1848 DRM_DEBUG_DRIVER("Unexpected fault\n"
Paulo Zanoni59a5d292014-10-30 15:52:45 -02001849 "\tAddr: 0x%08lx\n"
Ben Widawsky828c7902013-10-16 09:21:30 -07001850 "\tAddress space: %s\n"
1851 "\tSource ID: %d\n"
1852 "\tType: %d\n",
1853 fault_reg & PAGE_MASK,
1854 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1855 RING_FAULT_SRCID(fault_reg),
1856 RING_FAULT_FAULT_TYPE(fault_reg));
1857 I915_WRITE(RING_FAULT_REG(ring),
1858 fault_reg & ~RING_FAULT_VALID);
1859 }
1860 }
1861 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1862}
1863
Chris Wilson91e56492014-09-25 10:13:12 +01001864static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1865{
1866 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1867 intel_gtt_chipset_flush();
1868 } else {
1869 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1870 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1871 }
1872}
1873
Ben Widawsky828c7902013-10-16 09:21:30 -07001874void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1875{
1876 struct drm_i915_private *dev_priv = dev->dev_private;
1877
1878 /* Don't bother messing with faults pre GEN6 as we have little
1879 * documentation supporting that it's a good idea.
1880 */
1881 if (INTEL_INFO(dev)->gen < 6)
1882 return;
1883
1884 i915_check_and_clear_faults(dev);
1885
1886 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
Ben Widawsky782f1492014-02-20 11:50:33 -08001887 dev_priv->gtt.base.start,
1888 dev_priv->gtt.base.total,
Daniel Vettere568af12014-03-26 20:08:20 +01001889 true);
Chris Wilson91e56492014-09-25 10:13:12 +01001890
1891 i915_ggtt_flush(dev_priv);
Ben Widawsky828c7902013-10-16 09:21:30 -07001892}
1893
Daniel Vetter74163902012-02-15 23:50:21 +01001894int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +01001895{
Chris Wilson9da3da62012-06-01 15:20:22 +01001896 if (!dma_map_sg(&obj->base.dev->pdev->dev,
1897 obj->pages->sgl, obj->pages->nents,
1898 PCI_DMA_BIDIRECTIONAL))
1899 return -ENOSPC;
1900
1901 return 0;
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +01001902}
1903
Daniel Vetter2c642b02015-04-14 17:35:26 +02001904static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001905{
1906#ifdef writeq
1907 writeq(pte, addr);
1908#else
1909 iowrite32((u32)pte, addr);
1910 iowrite32(pte >> 32, addr + 4);
1911#endif
1912}
1913
1914static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1915 struct sg_table *st,
Ben Widawsky782f1492014-02-20 11:50:33 -08001916 uint64_t start,
Akash Goel24f3a8c2014-06-17 10:59:42 +05301917 enum i915_cache_level level, u32 unused)
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001918{
1919 struct drm_i915_private *dev_priv = vm->dev->dev_private;
Ben Widawsky782f1492014-02-20 11:50:33 -08001920 unsigned first_entry = start >> PAGE_SHIFT;
Michel Thierry07749ef2015-03-16 16:00:54 +00001921 gen8_pte_t __iomem *gtt_entries =
1922 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001923 int i = 0;
1924 struct sg_page_iter sg_iter;
Pavel Machek57007df2014-07-28 13:20:58 +02001925 dma_addr_t addr = 0; /* shut up gcc */
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001926
1927 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1928 addr = sg_dma_address(sg_iter.sg) +
1929 (sg_iter.sg_pgoffset << PAGE_SHIFT);
1930 gen8_set_pte(&gtt_entries[i],
1931 gen8_pte_encode(addr, level, true));
1932 i++;
1933 }
1934
1935 /*
1936 * XXX: This serves as a posting read to make sure that the PTE has
1937 * actually been updated. There is some concern that even though
1938 * registers and PTEs are within the same BAR that they are potentially
1939 * of NUMA access patterns. Therefore, even with the way we assume
1940 * hardware should work, we must keep this posting read for paranoia.
1941 */
1942 if (i != 0)
1943 WARN_ON(readq(&gtt_entries[i-1])
1944 != gen8_pte_encode(addr, level, true));
1945
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001946 /* This next bit makes the above posting read even more important. We
1947 * want to flush the TLBs only after we're certain all the PTE updates
1948 * have finished.
1949 */
1950 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1951 POSTING_READ(GFX_FLSH_CNTL_GEN6);
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001952}
1953
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001954/*
1955 * Binds an object into the global gtt with the specified cache level. The object
1956 * will be accessible to the GPU via commands whose operands reference offsets
1957 * within the global GTT as well as accessible by the GPU through the GMADR
1958 * mapped BAR (dev_priv->mm.gtt->gtt).
1959 */
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001960static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08001961 struct sg_table *st,
Ben Widawsky782f1492014-02-20 11:50:33 -08001962 uint64_t start,
Akash Goel24f3a8c2014-06-17 10:59:42 +05301963 enum i915_cache_level level, u32 flags)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001964{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07001965 struct drm_i915_private *dev_priv = vm->dev->dev_private;
Ben Widawsky782f1492014-02-20 11:50:33 -08001966 unsigned first_entry = start >> PAGE_SHIFT;
Michel Thierry07749ef2015-03-16 16:00:54 +00001967 gen6_pte_t __iomem *gtt_entries =
1968 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
Imre Deak6e995e22013-02-18 19:28:04 +02001969 int i = 0;
1970 struct sg_page_iter sg_iter;
Pavel Machek57007df2014-07-28 13:20:58 +02001971 dma_addr_t addr = 0;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001972
Imre Deak6e995e22013-02-18 19:28:04 +02001973 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
Imre Deak2db76d72013-03-26 15:14:18 +02001974 addr = sg_page_iter_dma_address(&sg_iter);
Akash Goel24f3a8c2014-06-17 10:59:42 +05301975 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
Imre Deak6e995e22013-02-18 19:28:04 +02001976 i++;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001977 }
1978
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001979 /* XXX: This serves as a posting read to make sure that the PTE has
1980 * actually been updated. There is some concern that even though
1981 * registers and PTEs are within the same BAR that they are potentially
1982 * of NUMA access patterns. Therefore, even with the way we assume
1983 * hardware should work, we must keep this posting read for paranoia.
1984 */
Pavel Machek57007df2014-07-28 13:20:58 +02001985 if (i != 0) {
1986 unsigned long gtt = readl(&gtt_entries[i-1]);
1987 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1988 }
Ben Widawsky0f9b91c2012-11-04 09:21:30 -08001989
1990 /* This next bit makes the above posting read even more important. We
1991 * want to flush the TLBs only after we're certain all the PTE updates
1992 * have finished.
1993 */
1994 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1995 POSTING_READ(GFX_FLSH_CNTL_GEN6);
Ben Widawskye76e9ae2012-11-04 09:21:27 -08001996}
1997
Ben Widawsky94ec8f62013-11-02 21:07:18 -07001998static void gen8_ggtt_clear_range(struct i915_address_space *vm,
Ben Widawsky782f1492014-02-20 11:50:33 -08001999 uint64_t start,
2000 uint64_t length,
Ben Widawsky94ec8f62013-11-02 21:07:18 -07002001 bool use_scratch)
2002{
2003 struct drm_i915_private *dev_priv = vm->dev->dev_private;
Ben Widawsky782f1492014-02-20 11:50:33 -08002004 unsigned first_entry = start >> PAGE_SHIFT;
2005 unsigned num_entries = length >> PAGE_SHIFT;
Michel Thierry07749ef2015-03-16 16:00:54 +00002006 gen8_pte_t scratch_pte, __iomem *gtt_base =
2007 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
Ben Widawsky94ec8f62013-11-02 21:07:18 -07002008 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2009 int i;
2010
2011 if (WARN(num_entries > max_entries,
2012 "First entry = %d; Num entries = %d (max=%d)\n",
2013 first_entry, num_entries, max_entries))
2014 num_entries = max_entries;
2015
Mika Kuoppalac114f762015-06-25 18:35:13 +03002016 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
Ben Widawsky94ec8f62013-11-02 21:07:18 -07002017 I915_CACHE_LLC,
2018 use_scratch);
2019 for (i = 0; i < num_entries; i++)
2020 gen8_set_pte(&gtt_base[i], scratch_pte);
2021 readl(gtt_base);
2022}
2023
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002024static void gen6_ggtt_clear_range(struct i915_address_space *vm,
Ben Widawsky782f1492014-02-20 11:50:33 -08002025 uint64_t start,
2026 uint64_t length,
Ben Widawsky828c7902013-10-16 09:21:30 -07002027 bool use_scratch)
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08002028{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002029 struct drm_i915_private *dev_priv = vm->dev->dev_private;
Ben Widawsky782f1492014-02-20 11:50:33 -08002030 unsigned first_entry = start >> PAGE_SHIFT;
2031 unsigned num_entries = length >> PAGE_SHIFT;
Michel Thierry07749ef2015-03-16 16:00:54 +00002032 gen6_pte_t scratch_pte, __iomem *gtt_base =
2033 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
Ben Widawskya54c0c22013-01-24 14:45:00 -08002034 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08002035 int i;
2036
2037 if (WARN(num_entries > max_entries,
2038 "First entry = %d; Num entries = %d (max=%d)\n",
2039 first_entry, num_entries, max_entries))
2040 num_entries = max_entries;
2041
Mika Kuoppalac114f762015-06-25 18:35:13 +03002042 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2043 I915_CACHE_LLC, use_scratch, 0);
Ben Widawsky828c7902013-10-16 09:21:30 -07002044
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08002045 for (i = 0; i < num_entries; i++)
2046 iowrite32(scratch_pte, &gtt_base[i]);
2047 readl(gtt_base);
2048}
2049
Daniel Vetterd369d2d2015-04-14 17:35:25 +02002050static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2051 struct sg_table *pages,
2052 uint64_t start,
2053 enum i915_cache_level cache_level, u32 unused)
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08002054{
2055 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2056 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2057
Daniel Vetterd369d2d2015-04-14 17:35:25 +02002058 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
Daniel Vetter08755462015-04-20 09:04:05 -07002059
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08002060}
2061
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002062static void i915_ggtt_clear_range(struct i915_address_space *vm,
Ben Widawsky782f1492014-02-20 11:50:33 -08002063 uint64_t start,
2064 uint64_t length,
Ben Widawsky828c7902013-10-16 09:21:30 -07002065 bool unused)
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08002066{
Ben Widawsky782f1492014-02-20 11:50:33 -08002067 unsigned first_entry = start >> PAGE_SHIFT;
2068 unsigned num_entries = length >> PAGE_SHIFT;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08002069 intel_gtt_clear_range(first_entry, num_entries);
2070}
2071
Daniel Vetter70b9f6f2015-04-14 17:35:27 +02002072static int ggtt_bind_vma(struct i915_vma *vma,
2073 enum i915_cache_level cache_level,
2074 u32 flags)
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +01002075{
Ben Widawsky6f65e292013-12-06 14:10:56 -08002076 struct drm_device *dev = vma->vm->dev;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08002077 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawsky6f65e292013-12-06 14:10:56 -08002078 struct drm_i915_gem_object *obj = vma->obj;
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002079 struct sg_table *pages = obj->pages;
Daniel Vetterf329f5f2015-04-14 17:35:15 +02002080 u32 pte_flags = 0;
Daniel Vetter70b9f6f2015-04-14 17:35:27 +02002081 int ret;
2082
2083 ret = i915_get_ggtt_vma_pages(vma);
2084 if (ret)
2085 return ret;
2086 pages = vma->ggtt_view.pages;
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08002087
Akash Goel24f3a8c2014-06-17 10:59:42 +05302088 /* Currently applicable only to VLV */
2089 if (obj->gt_ro)
Daniel Vetterf329f5f2015-04-14 17:35:15 +02002090 pte_flags |= PTE_READ_ONLY;
Akash Goel24f3a8c2014-06-17 10:59:42 +05302091
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002092
Ben Widawsky6f65e292013-12-06 14:10:56 -08002093 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
Daniel Vetter08755462015-04-20 09:04:05 -07002094 vma->vm->insert_entries(vma->vm, pages,
2095 vma->node.start,
2096 cache_level, pte_flags);
Chris Wilsond0e30ad2015-07-29 20:02:48 +01002097
2098 /* Note the inconsistency here is due to absence of the
2099 * aliasing ppgtt on gen4 and earlier. Though we always
2100 * request PIN_USER for execbuffer (translated to LOCAL_BIND),
2101 * without the appgtt, we cannot honour that request and so
2102 * must substitute it with a global binding. Since we do this
2103 * behind the upper layers back, we need to explicitly set
2104 * the bound flag ourselves.
2105 */
2106 vma->bound |= GLOBAL_BIND;
2107
Ben Widawsky6f65e292013-12-06 14:10:56 -08002108 }
Daniel Vetter74898d72012-02-15 23:50:22 +01002109
Daniel Vetter08755462015-04-20 09:04:05 -07002110 if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
Ben Widawsky6f65e292013-12-06 14:10:56 -08002111 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002112 appgtt->base.insert_entries(&appgtt->base, pages,
Ben Widawsky782f1492014-02-20 11:50:33 -08002113 vma->node.start,
Daniel Vetterf329f5f2015-04-14 17:35:15 +02002114 cache_level, pte_flags);
Ben Widawsky6f65e292013-12-06 14:10:56 -08002115 }
Daniel Vetter70b9f6f2015-04-14 17:35:27 +02002116
2117 return 0;
Ben Widawsky6f65e292013-12-06 14:10:56 -08002118}
2119
2120static void ggtt_unbind_vma(struct i915_vma *vma)
2121{
2122 struct drm_device *dev = vma->vm->dev;
2123 struct drm_i915_private *dev_priv = dev->dev_private;
2124 struct drm_i915_gem_object *obj = vma->obj;
Joonas Lahtinen06615ee2015-04-24 15:09:03 +03002125 const uint64_t size = min_t(uint64_t,
2126 obj->base.size,
2127 vma->node.size);
Ben Widawsky6f65e292013-12-06 14:10:56 -08002128
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01002129 if (vma->bound & GLOBAL_BIND) {
Ben Widawsky782f1492014-02-20 11:50:33 -08002130 vma->vm->clear_range(vma->vm,
2131 vma->node.start,
Joonas Lahtinen06615ee2015-04-24 15:09:03 +03002132 size,
Ben Widawsky6f65e292013-12-06 14:10:56 -08002133 true);
Ben Widawsky6f65e292013-12-06 14:10:56 -08002134 }
2135
Daniel Vetter08755462015-04-20 09:04:05 -07002136 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
Ben Widawsky6f65e292013-12-06 14:10:56 -08002137 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
Joonas Lahtinen06615ee2015-04-24 15:09:03 +03002138
Ben Widawsky6f65e292013-12-06 14:10:56 -08002139 appgtt->base.clear_range(&appgtt->base,
Ben Widawsky782f1492014-02-20 11:50:33 -08002140 vma->node.start,
Joonas Lahtinen06615ee2015-04-24 15:09:03 +03002141 size,
Ben Widawsky6f65e292013-12-06 14:10:56 -08002142 true);
Ben Widawsky6f65e292013-12-06 14:10:56 -08002143 }
Daniel Vetter74163902012-02-15 23:50:21 +01002144}
2145
2146void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
2147{
Ben Widawsky5c042282011-10-17 15:51:55 -07002148 struct drm_device *dev = obj->base.dev;
2149 struct drm_i915_private *dev_priv = dev->dev_private;
2150 bool interruptible;
2151
2152 interruptible = do_idling(dev_priv);
2153
Imre Deak5ec5b512015-07-08 19:18:59 +03002154 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2155 PCI_DMA_BIDIRECTIONAL);
Ben Widawsky5c042282011-10-17 15:51:55 -07002156
2157 undo_idling(dev_priv, interruptible);
Daniel Vetter7c2e6fd2010-11-06 10:10:47 +01002158}
Daniel Vetter644ec022012-03-26 09:45:40 +02002159
Chris Wilson42d6ab42012-07-26 11:49:32 +01002160static void i915_gtt_color_adjust(struct drm_mm_node *node,
2161 unsigned long color,
Thierry Reding440fd522015-01-23 09:05:06 +01002162 u64 *start,
2163 u64 *end)
Chris Wilson42d6ab42012-07-26 11:49:32 +01002164{
2165 if (node->color != color)
2166 *start += 4096;
2167
2168 if (!list_empty(&node->node_list)) {
2169 node = list_entry(node->node_list.next,
2170 struct drm_mm_node,
2171 node_list);
2172 if (node->allocated && node->color != color)
2173 *end -= 4096;
2174 }
2175}
Ben Widawskyfbe5d362013-11-04 19:56:49 -08002176
Daniel Vetterf548c0e2014-11-19 21:40:13 +01002177static int i915_gem_setup_global_gtt(struct drm_device *dev,
2178 unsigned long start,
2179 unsigned long mappable_end,
2180 unsigned long end)
Daniel Vetter644ec022012-03-26 09:45:40 +02002181{
Ben Widawskye78891c2013-01-25 16:41:04 -08002182 /* Let GEM Manage all of the aperture.
2183 *
2184 * However, leave one page at the end still bound to the scratch page.
2185 * There are a number of places where the hardware apparently prefetches
2186 * past the end of the object, and we've seen multiple hangs with the
2187 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2188 * aperture. One page should be enough to keep any prefetching inside
2189 * of the aperture.
2190 */
Ben Widawsky40d749802013-07-31 16:59:59 -07002191 struct drm_i915_private *dev_priv = dev->dev_private;
2192 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
Chris Wilsoned2f3452012-11-15 11:32:19 +00002193 struct drm_mm_node *entry;
2194 struct drm_i915_gem_object *obj;
2195 unsigned long hole_start, hole_end;
Daniel Vetterfa76da32014-08-06 20:19:54 +02002196 int ret;
Daniel Vetter644ec022012-03-26 09:45:40 +02002197
Ben Widawsky35451cb2013-01-17 12:45:13 -08002198 BUG_ON(mappable_end > end);
2199
Chris Wilsoned2f3452012-11-15 11:32:19 +00002200 /* Subtract the guard page ... */
Ben Widawsky40d749802013-07-31 16:59:59 -07002201 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
Yu Zhang5dda8fa2015-02-10 19:05:48 +08002202
2203 dev_priv->gtt.base.start = start;
2204 dev_priv->gtt.base.total = end - start;
2205
2206 if (intel_vgpu_active(dev)) {
2207 ret = intel_vgt_balloon(dev);
2208 if (ret)
2209 return ret;
2210 }
2211
Chris Wilson42d6ab42012-07-26 11:49:32 +01002212 if (!HAS_LLC(dev))
Ben Widawsky93bd8642013-07-16 16:50:06 -07002213 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
Daniel Vetter644ec022012-03-26 09:45:40 +02002214
Chris Wilsoned2f3452012-11-15 11:32:19 +00002215 /* Mark any preallocated objects as occupied */
Ben Widawsky35c20a62013-05-31 11:28:48 -07002216 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
Ben Widawsky40d749802013-07-31 16:59:59 -07002217 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
Daniel Vetterfa76da32014-08-06 20:19:54 +02002218
Ben Widawskyedd41a82013-07-05 14:41:05 -07002219 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
Ben Widawskyc6cfb322013-07-05 14:41:06 -07002220 i915_gem_obj_ggtt_offset(obj), obj->base.size);
Chris Wilsoned2f3452012-11-15 11:32:19 +00002221
Ben Widawskyc6cfb322013-07-05 14:41:06 -07002222 WARN_ON(i915_gem_obj_ggtt_bound(obj));
Ben Widawsky40d749802013-07-31 16:59:59 -07002223 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
Daniel Vetter6c5566a2014-08-06 15:04:50 +02002224 if (ret) {
2225 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2226 return ret;
2227 }
Tvrtko Ursulinaff43762014-10-24 12:42:33 +01002228 vma->bound |= GLOBAL_BIND;
Chris Wilsoned2f3452012-11-15 11:32:19 +00002229 }
2230
Chris Wilsoned2f3452012-11-15 11:32:19 +00002231 /* Clear any non-preallocated blocks */
Ben Widawsky40d749802013-07-31 16:59:59 -07002232 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
Chris Wilsoned2f3452012-11-15 11:32:19 +00002233 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2234 hole_start, hole_end);
Ben Widawsky782f1492014-02-20 11:50:33 -08002235 ggtt_vm->clear_range(ggtt_vm, hole_start,
2236 hole_end - hole_start, true);
Chris Wilsoned2f3452012-11-15 11:32:19 +00002237 }
2238
2239 /* And finally clear the reserved guard page */
Ben Widawsky782f1492014-02-20 11:50:33 -08002240 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
Daniel Vetter6c5566a2014-08-06 15:04:50 +02002241
Daniel Vetterfa76da32014-08-06 20:19:54 +02002242 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2243 struct i915_hw_ppgtt *ppgtt;
2244
2245 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2246 if (!ppgtt)
2247 return -ENOMEM;
2248
Daniel Vetter5c5f6452015-04-14 17:35:14 +02002249 ret = __hw_ppgtt_init(dev, ppgtt);
Michel Thierry4933d512015-03-24 15:46:22 +00002250 if (ret) {
Daniel Vetter061dd492015-04-14 17:35:13 +02002251 ppgtt->base.cleanup(&ppgtt->base);
Michel Thierry4933d512015-03-24 15:46:22 +00002252 kfree(ppgtt);
Daniel Vetterfa76da32014-08-06 20:19:54 +02002253 return ret;
Michel Thierry4933d512015-03-24 15:46:22 +00002254 }
Daniel Vetterfa76da32014-08-06 20:19:54 +02002255
Daniel Vetter5c5f6452015-04-14 17:35:14 +02002256 if (ppgtt->base.allocate_va_range)
2257 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2258 ppgtt->base.total);
2259 if (ret) {
2260 ppgtt->base.cleanup(&ppgtt->base);
2261 kfree(ppgtt);
2262 return ret;
2263 }
2264
2265 ppgtt->base.clear_range(&ppgtt->base,
2266 ppgtt->base.start,
2267 ppgtt->base.total,
2268 true);
2269
Daniel Vetterfa76da32014-08-06 20:19:54 +02002270 dev_priv->mm.aliasing_ppgtt = ppgtt;
2271 }
2272
Daniel Vetter6c5566a2014-08-06 15:04:50 +02002273 return 0;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002274}
2275
Ben Widawskyd7e50082012-12-18 10:31:25 -08002276void i915_gem_init_global_gtt(struct drm_device *dev)
2277{
2278 struct drm_i915_private *dev_priv = dev->dev_private;
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002279 u64 gtt_size, mappable_size;
Ben Widawskyd7e50082012-12-18 10:31:25 -08002280
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002281 gtt_size = dev_priv->gtt.base.total;
Ben Widawsky93d18792013-01-17 12:45:17 -08002282 mappable_size = dev_priv->gtt.mappable_end;
Ben Widawskyd7e50082012-12-18 10:31:25 -08002283
Ben Widawskye78891c2013-01-25 16:41:04 -08002284 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002285}
2286
Daniel Vetter90d0a0e2014-08-06 15:04:56 +02002287void i915_global_gtt_cleanup(struct drm_device *dev)
2288{
2289 struct drm_i915_private *dev_priv = dev->dev_private;
2290 struct i915_address_space *vm = &dev_priv->gtt.base;
2291
Daniel Vetter70e32542014-08-06 15:04:57 +02002292 if (dev_priv->mm.aliasing_ppgtt) {
2293 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2294
2295 ppgtt->base.cleanup(&ppgtt->base);
2296 }
2297
Daniel Vetter90d0a0e2014-08-06 15:04:56 +02002298 if (drm_mm_initialized(&vm->mm)) {
Yu Zhang5dda8fa2015-02-10 19:05:48 +08002299 if (intel_vgpu_active(dev))
2300 intel_vgt_deballoon();
2301
Daniel Vetter90d0a0e2014-08-06 15:04:56 +02002302 drm_mm_takedown(&vm->mm);
2303 list_del(&vm->global_link);
2304 }
2305
2306 vm->cleanup(vm);
2307}
Daniel Vetter70e32542014-08-06 15:04:57 +02002308
Daniel Vetter2c642b02015-04-14 17:35:26 +02002309static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002310{
2311 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2312 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2313 return snb_gmch_ctl << 20;
2314}
2315
Daniel Vetter2c642b02015-04-14 17:35:26 +02002316static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
Ben Widawsky9459d252013-11-03 16:53:55 -08002317{
2318 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2319 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2320 if (bdw_gmch_ctl)
2321 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
Ben Widawsky562d55d2014-05-27 16:53:08 -07002322
2323#ifdef CONFIG_X86_32
2324 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2325 if (bdw_gmch_ctl > 4)
2326 bdw_gmch_ctl = 4;
2327#endif
2328
Ben Widawsky9459d252013-11-03 16:53:55 -08002329 return bdw_gmch_ctl << 20;
2330}
2331
Daniel Vetter2c642b02015-04-14 17:35:26 +02002332static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
Damien Lespiaud7f25f22014-05-08 22:19:40 +03002333{
2334 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2335 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2336
2337 if (gmch_ctrl)
2338 return 1 << (20 + gmch_ctrl);
2339
2340 return 0;
2341}
2342
Daniel Vetter2c642b02015-04-14 17:35:26 +02002343static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002344{
2345 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2346 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2347 return snb_gmch_ctl << 25; /* 32 MB units */
2348}
2349
Daniel Vetter2c642b02015-04-14 17:35:26 +02002350static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
Ben Widawsky9459d252013-11-03 16:53:55 -08002351{
2352 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2353 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2354 return bdw_gmch_ctl << 25; /* 32 MB units */
2355}
2356
Damien Lespiaud7f25f22014-05-08 22:19:40 +03002357static size_t chv_get_stolen_size(u16 gmch_ctrl)
2358{
2359 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2360 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2361
2362 /*
2363 * 0x0 to 0x10: 32MB increments starting at 0MB
2364 * 0x11 to 0x16: 4MB increments starting at 8MB
2365 * 0x17 to 0x1d: 4MB increments start at 36MB
2366 */
2367 if (gmch_ctrl < 0x11)
2368 return gmch_ctrl << 25;
2369 else if (gmch_ctrl < 0x17)
2370 return (gmch_ctrl - 0x11 + 2) << 22;
2371 else
2372 return (gmch_ctrl - 0x17 + 9) << 22;
2373}
2374
Damien Lespiau66375012014-01-09 18:02:46 +00002375static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2376{
2377 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2378 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2379
2380 if (gen9_gmch_ctl < 0xf0)
2381 return gen9_gmch_ctl << 25; /* 32 MB units */
2382 else
2383 /* 4MB increments starting at 0xf0 for 4MB */
2384 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2385}
2386
Ben Widawsky63340132013-11-04 19:32:22 -08002387static int ggtt_probe_common(struct drm_device *dev,
2388 size_t gtt_size)
2389{
2390 struct drm_i915_private *dev_priv = dev->dev_private;
Mika Kuoppala4ad2af12015-06-30 18:16:39 +03002391 struct i915_page_scratch *scratch_page;
Bjorn Helgaas21c34602013-12-21 10:52:52 -07002392 phys_addr_t gtt_phys_addr;
Ben Widawsky63340132013-11-04 19:32:22 -08002393
2394 /* For Modern GENs the PTEs and register space are split in the BAR */
Bjorn Helgaas21c34602013-12-21 10:52:52 -07002395 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
Ben Widawsky63340132013-11-04 19:32:22 -08002396 (pci_resource_len(dev->pdev, 0) / 2);
2397
Imre Deak2a073f892015-03-27 13:07:33 +02002398 /*
2399 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2400 * dropped. For WC mappings in general we have 64 byte burst writes
2401 * when the WC buffer is flushed, so we can't use it, but have to
2402 * resort to an uncached mapping. The WC issue is easily caught by the
2403 * readback check when writing GTT PTE entries.
2404 */
2405 if (IS_BROXTON(dev))
2406 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2407 else
2408 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
Ben Widawsky63340132013-11-04 19:32:22 -08002409 if (!dev_priv->gtt.gsm) {
2410 DRM_ERROR("Failed to map the gtt page table\n");
2411 return -ENOMEM;
2412 }
2413
Mika Kuoppala4ad2af12015-06-30 18:16:39 +03002414 scratch_page = alloc_scratch_page(dev);
2415 if (IS_ERR(scratch_page)) {
Ben Widawsky63340132013-11-04 19:32:22 -08002416 DRM_ERROR("Scratch setup failed\n");
2417 /* iounmap will also get called at remove, but meh */
2418 iounmap(dev_priv->gtt.gsm);
Mika Kuoppala4ad2af12015-06-30 18:16:39 +03002419 return PTR_ERR(scratch_page);
Ben Widawsky63340132013-11-04 19:32:22 -08002420 }
2421
Mika Kuoppala4ad2af12015-06-30 18:16:39 +03002422 dev_priv->gtt.base.scratch_page = scratch_page;
2423
2424 return 0;
Ben Widawsky63340132013-11-04 19:32:22 -08002425}
2426
Ben Widawskyfbe5d362013-11-04 19:56:49 -08002427/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2428 * bits. When using advanced contexts each context stores its own PAT, but
2429 * writing this data shouldn't be harmful even in those cases. */
Ville Syrjäläee0ce472014-04-09 13:28:01 +03002430static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
Ben Widawskyfbe5d362013-11-04 19:56:49 -08002431{
Ben Widawskyfbe5d362013-11-04 19:56:49 -08002432 uint64_t pat;
2433
2434 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2435 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2436 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2437 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2438 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2439 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2440 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2441 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2442
Rodrigo Vivid6a8b722014-11-05 16:56:36 -08002443 if (!USES_PPGTT(dev_priv->dev))
2444 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2445 * so RTL will always use the value corresponding to
2446 * pat_sel = 000".
2447 * So let's disable cache for GGTT to avoid screen corruptions.
2448 * MOCS still can be used though.
2449 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2450 * before this patch, i.e. the same uncached + snooping access
2451 * like on gen6/7 seems to be in effect.
2452 * - So this just fixes blitter/render access. Again it looks
2453 * like it's not just uncached access, but uncached + snooping.
2454 * So we can still hold onto all our assumptions wrt cpu
2455 * clflushing on LLC machines.
2456 */
2457 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2458
Ben Widawskyfbe5d362013-11-04 19:56:49 -08002459 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2460 * write would work. */
2461 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2462 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2463}
2464
Ville Syrjäläee0ce472014-04-09 13:28:01 +03002465static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2466{
2467 uint64_t pat;
2468
2469 /*
2470 * Map WB on BDW to snooped on CHV.
2471 *
2472 * Only the snoop bit has meaning for CHV, the rest is
2473 * ignored.
2474 *
Ville Syrjäläcf3d2622014-11-14 21:02:44 +02002475 * The hardware will never snoop for certain types of accesses:
2476 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2477 * - PPGTT page tables
2478 * - some other special cycles
2479 *
2480 * As with BDW, we also need to consider the following for GT accesses:
2481 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2482 * so RTL will always use the value corresponding to
2483 * pat_sel = 000".
2484 * Which means we must set the snoop bit in PAT entry 0
2485 * in order to keep the global status page working.
Ville Syrjäläee0ce472014-04-09 13:28:01 +03002486 */
2487 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2488 GEN8_PPAT(1, 0) |
2489 GEN8_PPAT(2, 0) |
2490 GEN8_PPAT(3, 0) |
2491 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2492 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2493 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2494 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2495
2496 I915_WRITE(GEN8_PRIVATE_PAT, pat);
2497 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2498}
2499
Ben Widawsky63340132013-11-04 19:32:22 -08002500static int gen8_gmch_probe(struct drm_device *dev,
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002501 u64 *gtt_total,
Ben Widawsky63340132013-11-04 19:32:22 -08002502 size_t *stolen,
2503 phys_addr_t *mappable_base,
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002504 u64 *mappable_end)
Ben Widawsky63340132013-11-04 19:32:22 -08002505{
2506 struct drm_i915_private *dev_priv = dev->dev_private;
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002507 u64 gtt_size;
Ben Widawsky63340132013-11-04 19:32:22 -08002508 u16 snb_gmch_ctl;
2509 int ret;
2510
2511 /* TODO: We're not aware of mappable constraints on gen8 yet */
2512 *mappable_base = pci_resource_start(dev->pdev, 2);
2513 *mappable_end = pci_resource_len(dev->pdev, 2);
2514
2515 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2516 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2517
2518 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2519
Damien Lespiau66375012014-01-09 18:02:46 +00002520 if (INTEL_INFO(dev)->gen >= 9) {
2521 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2522 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2523 } else if (IS_CHERRYVIEW(dev)) {
Damien Lespiaud7f25f22014-05-08 22:19:40 +03002524 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2525 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2526 } else {
2527 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2528 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2529 }
Ben Widawsky63340132013-11-04 19:32:22 -08002530
Michel Thierry07749ef2015-03-16 16:00:54 +00002531 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
Ben Widawsky63340132013-11-04 19:32:22 -08002532
Sumit Singh5a4e33a2015-03-17 11:39:31 +02002533 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
Ville Syrjäläee0ce472014-04-09 13:28:01 +03002534 chv_setup_private_ppat(dev_priv);
2535 else
2536 bdw_setup_private_ppat(dev_priv);
Ben Widawskyfbe5d362013-11-04 19:56:49 -08002537
Ben Widawsky63340132013-11-04 19:32:22 -08002538 ret = ggtt_probe_common(dev, gtt_size);
2539
Ben Widawsky94ec8f62013-11-02 21:07:18 -07002540 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2541 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
Daniel Vetter777dc5b2015-04-14 17:35:12 +02002542 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2543 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
Ben Widawsky63340132013-11-04 19:32:22 -08002544
2545 return ret;
2546}
2547
Ben Widawskybaa09f52013-01-24 13:49:57 -08002548static int gen6_gmch_probe(struct drm_device *dev,
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002549 u64 *gtt_total,
Ben Widawsky41907dd2013-02-08 11:32:47 -08002550 size_t *stolen,
2551 phys_addr_t *mappable_base,
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002552 u64 *mappable_end)
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002553{
2554 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskybaa09f52013-01-24 13:49:57 -08002555 unsigned int gtt_size;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002556 u16 snb_gmch_ctl;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002557 int ret;
2558
Ben Widawsky41907dd2013-02-08 11:32:47 -08002559 *mappable_base = pci_resource_start(dev->pdev, 2);
2560 *mappable_end = pci_resource_len(dev->pdev, 2);
2561
Ben Widawskybaa09f52013-01-24 13:49:57 -08002562 /* 64/512MB is the current min/max we actually know of, but this is just
2563 * a coarse sanity check.
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002564 */
Ben Widawsky41907dd2013-02-08 11:32:47 -08002565 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002566 DRM_ERROR("Unknown GMADR size (%llx)\n",
Ben Widawskybaa09f52013-01-24 13:49:57 -08002567 dev_priv->gtt.mappable_end);
2568 return -ENXIO;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002569 }
2570
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002571 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2572 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
Ben Widawskybaa09f52013-01-24 13:49:57 -08002573 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002574
Ben Widawskyc4ae25e2013-05-01 11:00:34 -07002575 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002576
Ben Widawsky63340132013-11-04 19:32:22 -08002577 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
Michel Thierry07749ef2015-03-16 16:00:54 +00002578 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
Ben Widawskybaa09f52013-01-24 13:49:57 -08002579
Ben Widawsky63340132013-11-04 19:32:22 -08002580 ret = ggtt_probe_common(dev, gtt_size);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002581
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002582 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2583 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
Daniel Vetter777dc5b2015-04-14 17:35:12 +02002584 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2585 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
Ben Widawskybaa09f52013-01-24 13:49:57 -08002586
2587 return ret;
2588}
2589
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002590static void gen6_gmch_remove(struct i915_address_space *vm)
Ben Widawskybaa09f52013-01-24 13:49:57 -08002591{
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002592
2593 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
Ben Widawsky5ed16782013-11-25 09:54:43 -08002594
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002595 iounmap(gtt->gsm);
Mika Kuoppala4ad2af12015-06-30 18:16:39 +03002596 free_scratch_page(vm->dev, vm->scratch_page);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002597}
2598
2599static int i915_gmch_probe(struct drm_device *dev,
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002600 u64 *gtt_total,
Ben Widawsky41907dd2013-02-08 11:32:47 -08002601 size_t *stolen,
2602 phys_addr_t *mappable_base,
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002603 u64 *mappable_end)
Ben Widawskybaa09f52013-01-24 13:49:57 -08002604{
2605 struct drm_i915_private *dev_priv = dev->dev_private;
2606 int ret;
2607
Ben Widawskybaa09f52013-01-24 13:49:57 -08002608 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2609 if (!ret) {
2610 DRM_ERROR("failed to set up gmch\n");
2611 return -EIO;
2612 }
2613
Ben Widawsky41907dd2013-02-08 11:32:47 -08002614 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
Ben Widawskybaa09f52013-01-24 13:49:57 -08002615
2616 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
Daniel Vetterd369d2d2015-04-14 17:35:25 +02002617 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002618 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
Daniel Vetterd369d2d2015-04-14 17:35:25 +02002619 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2620 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
Ben Widawskybaa09f52013-01-24 13:49:57 -08002621
Chris Wilsonc0a7f812013-12-30 12:16:15 +00002622 if (unlikely(dev_priv->gtt.do_idle_maps))
2623 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2624
Ben Widawskybaa09f52013-01-24 13:49:57 -08002625 return 0;
2626}
2627
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002628static void i915_gmch_remove(struct i915_address_space *vm)
Ben Widawskybaa09f52013-01-24 13:49:57 -08002629{
2630 intel_gmch_remove();
2631}
2632
2633int i915_gem_gtt_init(struct drm_device *dev)
2634{
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636 struct i915_gtt *gtt = &dev_priv->gtt;
Ben Widawskybaa09f52013-01-24 13:49:57 -08002637 int ret;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002638
Ben Widawskybaa09f52013-01-24 13:49:57 -08002639 if (INTEL_INFO(dev)->gen <= 5) {
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002640 gtt->gtt_probe = i915_gmch_probe;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002641 gtt->base.cleanup = i915_gmch_remove;
Ben Widawsky63340132013-11-04 19:32:22 -08002642 } else if (INTEL_INFO(dev)->gen < 8) {
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002643 gtt->gtt_probe = gen6_gmch_probe;
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002644 gtt->base.cleanup = gen6_gmch_remove;
Ben Widawsky4d15c142013-07-04 11:02:06 -07002645 if (IS_HASWELL(dev) && dev_priv->ellc_size)
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002646 gtt->base.pte_encode = iris_pte_encode;
Ben Widawsky4d15c142013-07-04 11:02:06 -07002647 else if (IS_HASWELL(dev))
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002648 gtt->base.pte_encode = hsw_pte_encode;
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002649 else if (IS_VALLEYVIEW(dev))
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002650 gtt->base.pte_encode = byt_pte_encode;
Chris Wilson350ec882013-08-06 13:17:02 +01002651 else if (INTEL_INFO(dev)->gen >= 7)
2652 gtt->base.pte_encode = ivb_pte_encode;
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002653 else
Chris Wilson350ec882013-08-06 13:17:02 +01002654 gtt->base.pte_encode = snb_pte_encode;
Ben Widawsky63340132013-11-04 19:32:22 -08002655 } else {
2656 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2657 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002658 }
2659
Mika Kuoppalac114f762015-06-25 18:35:13 +03002660 gtt->base.dev = dev;
2661
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002662 ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002663 &gtt->mappable_base, &gtt->mappable_end);
Ben Widawskya54c0c22013-01-24 14:45:00 -08002664 if (ret)
Ben Widawskybaa09f52013-01-24 13:49:57 -08002665 return ret;
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002666
Ben Widawskybaa09f52013-01-24 13:49:57 -08002667 /* GMADR is the PCI mmio aperture into the global GTT. */
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002668 DRM_INFO("Memory usable by graphics device = %lluM\n",
Ben Widawsky853ba5d2013-07-16 16:50:05 -07002669 gtt->base.total >> 20);
Mika Kuoppalac44ef602015-06-25 18:35:05 +03002670 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
Ben Widawskyb2f21b42013-06-27 16:30:20 -07002671 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
Daniel Vetter5db6c732014-03-31 16:23:04 +02002672#ifdef CONFIG_INTEL_IOMMU
2673 if (intel_iommu_gfx_mapped)
2674 DRM_INFO("VT-d active for gfx access\n");
2675#endif
Daniel Vettercfa7c862014-04-29 11:53:58 +02002676 /*
2677 * i915.enable_ppgtt is read-only, so do an early pass to validate the
2678 * user's requested state against the hardware/driver capabilities. We
2679 * do this now so that we can print out any log messages once rather
2680 * than every time we check intel_enable_ppgtt().
2681 */
2682 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2683 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
Daniel Vetter7faf1ab2013-01-24 14:44:55 -08002684
Ben Widawskye76e9ae2012-11-04 09:21:27 -08002685 return 0;
Daniel Vetter644ec022012-03-26 09:45:40 +02002686}
Ben Widawsky6f65e292013-12-06 14:10:56 -08002687
Daniel Vetterfa423312015-04-14 17:35:23 +02002688void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2689{
2690 struct drm_i915_private *dev_priv = dev->dev_private;
2691 struct drm_i915_gem_object *obj;
2692 struct i915_address_space *vm;
Tvrtko Ursulin2c3d9982015-07-06 15:15:01 +01002693 struct i915_vma *vma;
2694 bool flush;
Daniel Vetterfa423312015-04-14 17:35:23 +02002695
2696 i915_check_and_clear_faults(dev);
2697
2698 /* First fill our portion of the GTT with scratch pages */
2699 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2700 dev_priv->gtt.base.start,
2701 dev_priv->gtt.base.total,
2702 true);
2703
Tvrtko Ursulin2c3d9982015-07-06 15:15:01 +01002704 /* Cache flush objects bound into GGTT and rebind them. */
2705 vm = &dev_priv->gtt.base;
Daniel Vetterfa423312015-04-14 17:35:23 +02002706 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
Tvrtko Ursulin2c3d9982015-07-06 15:15:01 +01002707 flush = false;
2708 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2709 if (vma->vm != vm)
2710 continue;
Daniel Vetterfa423312015-04-14 17:35:23 +02002711
Tvrtko Ursulin2c3d9982015-07-06 15:15:01 +01002712 WARN_ON(i915_vma_bind(vma, obj->cache_level,
2713 PIN_UPDATE));
2714
2715 flush = true;
2716 }
2717
2718 if (flush)
2719 i915_gem_clflush_object(obj, obj->pin_display);
Daniel Vetterfa423312015-04-14 17:35:23 +02002720 }
2721
Daniel Vetterfa423312015-04-14 17:35:23 +02002722 if (INTEL_INFO(dev)->gen >= 8) {
2723 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2724 chv_setup_private_ppat(dev_priv);
2725 else
2726 bdw_setup_private_ppat(dev_priv);
2727
2728 return;
2729 }
2730
2731 if (USES_PPGTT(dev)) {
2732 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2733 /* TODO: Perhaps it shouldn't be gen6 specific */
2734
2735 struct i915_hw_ppgtt *ppgtt =
2736 container_of(vm, struct i915_hw_ppgtt,
2737 base);
2738
2739 if (i915_is_ggtt(vm))
2740 ppgtt = dev_priv->mm.aliasing_ppgtt;
2741
2742 gen6_write_page_range(dev_priv, &ppgtt->pd,
2743 0, ppgtt->base.total);
2744 }
2745 }
2746
2747 i915_ggtt_flush(dev_priv);
2748}
2749
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002750static struct i915_vma *
2751__i915_gem_vma_create(struct drm_i915_gem_object *obj,
2752 struct i915_address_space *vm,
2753 const struct i915_ggtt_view *ggtt_view)
Ben Widawsky6f65e292013-12-06 14:10:56 -08002754{
Dan Carpenterdabde5c2015-03-18 11:21:58 +03002755 struct i915_vma *vma;
Ben Widawsky6f65e292013-12-06 14:10:56 -08002756
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002757 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2758 return ERR_PTR(-EINVAL);
Chris Wilsone20d2ab2015-04-07 16:20:58 +01002759
2760 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
Dan Carpenterdabde5c2015-03-18 11:21:58 +03002761 if (vma == NULL)
2762 return ERR_PTR(-ENOMEM);
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002763
Ben Widawsky6f65e292013-12-06 14:10:56 -08002764 INIT_LIST_HEAD(&vma->vma_link);
2765 INIT_LIST_HEAD(&vma->mm_list);
2766 INIT_LIST_HEAD(&vma->exec_list);
2767 vma->vm = vm;
2768 vma->obj = obj;
2769
Daniel Vetter777dc5b2015-04-14 17:35:12 +02002770 if (i915_is_ggtt(vm))
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002771 vma->ggtt_view = *ggtt_view;
Ben Widawsky6f65e292013-12-06 14:10:56 -08002772
Tvrtko Ursulinf7635662014-12-03 14:59:24 +00002773 list_add_tail(&vma->vma_link, &obj->vma_list);
2774 if (!i915_is_ggtt(vm))
Michel Thierrye07f0552014-08-19 15:49:41 +01002775 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
Ben Widawsky6f65e292013-12-06 14:10:56 -08002776
2777 return vma;
2778}
2779
2780struct i915_vma *
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002781i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2782 struct i915_address_space *vm)
Ben Widawsky6f65e292013-12-06 14:10:56 -08002783{
2784 struct i915_vma *vma;
2785
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002786 vma = i915_gem_obj_to_vma(obj, vm);
Ben Widawsky6f65e292013-12-06 14:10:56 -08002787 if (!vma)
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002788 vma = __i915_gem_vma_create(obj, vm,
2789 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
Ben Widawsky6f65e292013-12-06 14:10:56 -08002790
2791 return vma;
2792}
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002793
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002794struct i915_vma *
2795i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2796 const struct i915_ggtt_view *view)
2797{
2798 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
2799 struct i915_vma *vma;
2800
2801 if (WARN_ON(!view))
2802 return ERR_PTR(-EINVAL);
2803
2804 vma = i915_gem_obj_to_ggtt_view(obj, view);
2805
2806 if (IS_ERR(vma))
2807 return vma;
2808
2809 if (!vma)
2810 vma = __i915_gem_vma_create(obj, ggtt, view);
2811
2812 return vma;
2813
2814}
2815
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002816static void
2817rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2818 struct sg_table *st)
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002819{
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002820 unsigned int column, row;
2821 unsigned int src_idx;
2822 struct scatterlist *sg = st->sgl;
2823
2824 st->nents = 0;
2825
2826 for (column = 0; column < width; column++) {
2827 src_idx = width * (height - 1) + column;
2828 for (row = 0; row < height; row++) {
2829 st->nents++;
2830 /* We don't need the pages, but need to initialize
2831 * the entries so the sg list can be happily traversed.
2832 * The only thing we need are DMA addresses.
2833 */
2834 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2835 sg_dma_address(sg) = in[src_idx];
2836 sg_dma_len(sg) = PAGE_SIZE;
2837 sg = sg_next(sg);
2838 src_idx -= width;
2839 }
2840 }
2841}
2842
2843static struct sg_table *
2844intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2845 struct drm_i915_gem_object *obj)
2846{
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002847 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002848 unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002849 struct sg_page_iter sg_iter;
2850 unsigned long i;
2851 dma_addr_t *page_addr_list;
2852 struct sg_table *st;
Tvrtko Ursulin1d00dad2015-03-25 10:15:26 +00002853 int ret = -ENOMEM;
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002854
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002855 /* Allocate a temporary list of source pages for random access. */
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002856 page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
2857 sizeof(dma_addr_t));
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002858 if (!page_addr_list)
2859 return ERR_PTR(ret);
2860
2861 /* Allocate target SG list. */
2862 st = kmalloc(sizeof(*st), GFP_KERNEL);
2863 if (!st)
2864 goto err_st_alloc;
2865
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002866 ret = sg_alloc_table(st, size_pages, GFP_KERNEL);
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002867 if (ret)
2868 goto err_sg_alloc;
2869
2870 /* Populate source page list from the object. */
2871 i = 0;
2872 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2873 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2874 i++;
2875 }
2876
2877 /* Rotate the pages. */
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002878 rotate_pages(page_addr_list,
2879 rot_info->width_pages, rot_info->height_pages,
2880 st);
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002881
2882 DRM_DEBUG_KMS(
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002883 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
Tvrtko Ursulinc9f8fd22015-06-24 09:55:20 +01002884 obj->base.size, rot_info->pitch, rot_info->height,
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002885 rot_info->pixel_format, rot_info->width_pages,
2886 rot_info->height_pages, size_pages);
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002887
2888 drm_free_large(page_addr_list);
2889
2890 return st;
2891
2892err_sg_alloc:
2893 kfree(st);
2894err_st_alloc:
2895 drm_free_large(page_addr_list);
2896
2897 DRM_DEBUG_KMS(
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002898 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
Tvrtko Ursulinc9f8fd22015-06-24 09:55:20 +01002899 obj->base.size, ret, rot_info->pitch, rot_info->height,
Tvrtko Ursulin84fe03f2015-06-23 14:26:46 +01002900 rot_info->pixel_format, rot_info->width_pages,
2901 rot_info->height_pages, size_pages);
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002902 return ERR_PTR(ret);
2903}
2904
Joonas Lahtinen8bd7ef12015-05-06 14:35:38 +03002905static struct sg_table *
2906intel_partial_pages(const struct i915_ggtt_view *view,
2907 struct drm_i915_gem_object *obj)
2908{
2909 struct sg_table *st;
2910 struct scatterlist *sg;
2911 struct sg_page_iter obj_sg_iter;
2912 int ret = -ENOMEM;
2913
2914 st = kmalloc(sizeof(*st), GFP_KERNEL);
2915 if (!st)
2916 goto err_st_alloc;
2917
2918 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
2919 if (ret)
2920 goto err_sg_alloc;
2921
2922 sg = st->sgl;
2923 st->nents = 0;
2924 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
2925 view->params.partial.offset)
2926 {
2927 if (st->nents >= view->params.partial.size)
2928 break;
2929
2930 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2931 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
2932 sg_dma_len(sg) = PAGE_SIZE;
2933
2934 sg = sg_next(sg);
2935 st->nents++;
2936 }
2937
2938 return st;
2939
2940err_sg_alloc:
2941 kfree(st);
2942err_st_alloc:
2943 return ERR_PTR(ret);
2944}
2945
Daniel Vetter70b9f6f2015-04-14 17:35:27 +02002946static int
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002947i915_get_ggtt_vma_pages(struct i915_vma *vma)
2948{
2949 int ret = 0;
2950
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002951 if (vma->ggtt_view.pages)
2952 return 0;
2953
2954 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2955 vma->ggtt_view.pages = vma->obj->pages;
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002956 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2957 vma->ggtt_view.pages =
2958 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
Joonas Lahtinen8bd7ef12015-05-06 14:35:38 +03002959 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
2960 vma->ggtt_view.pages =
2961 intel_partial_pages(&vma->ggtt_view, vma->obj);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002962 else
2963 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2964 vma->ggtt_view.type);
2965
2966 if (!vma->ggtt_view.pages) {
Joonas Lahtinenec7adb62015-03-16 14:11:13 +02002967 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002968 vma->ggtt_view.type);
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002969 ret = -EINVAL;
2970 } else if (IS_ERR(vma->ggtt_view.pages)) {
2971 ret = PTR_ERR(vma->ggtt_view.pages);
2972 vma->ggtt_view.pages = NULL;
2973 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2974 vma->ggtt_view.type, ret);
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002975 }
2976
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00002977 return ret;
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00002978}
2979
2980/**
2981 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2982 * @vma: VMA to map
2983 * @cache_level: mapping cache level
2984 * @flags: flags like global or local mapping
2985 *
2986 * DMA addresses are taken from the scatter-gather table of this object (or of
2987 * this VMA in case of non-default GGTT views) and PTE entries set up.
2988 * Note that DMA addresses are also the only part of the SG table we care about.
2989 */
2990int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2991 u32 flags)
2992{
Mika Kuoppala75d04a32015-04-28 17:56:17 +03002993 int ret;
2994 u32 bind_flags;
Mika Kuoppala1d335d12015-04-10 15:54:58 +03002995
Mika Kuoppala75d04a32015-04-28 17:56:17 +03002996 if (WARN_ON(flags == 0))
2997 return -EINVAL;
Mika Kuoppala1d335d12015-04-10 15:54:58 +03002998
Mika Kuoppala75d04a32015-04-28 17:56:17 +03002999 bind_flags = 0;
Daniel Vetter08755462015-04-20 09:04:05 -07003000 if (flags & PIN_GLOBAL)
3001 bind_flags |= GLOBAL_BIND;
3002 if (flags & PIN_USER)
3003 bind_flags |= LOCAL_BIND;
3004
3005 if (flags & PIN_UPDATE)
3006 bind_flags |= vma->bound;
3007 else
3008 bind_flags &= ~vma->bound;
3009
Mika Kuoppala75d04a32015-04-28 17:56:17 +03003010 if (bind_flags == 0)
3011 return 0;
3012
3013 if (vma->bound == 0 && vma->vm->allocate_va_range) {
3014 trace_i915_va_alloc(vma->vm,
3015 vma->node.start,
3016 vma->node.size,
3017 VM_TO_TRACE_NAME(vma->vm));
3018
Mika Kuoppalab2dd4512015-06-25 18:35:15 +03003019 /* XXX: i915_vma_pin() will fix this +- hack */
3020 vma->pin_count++;
Mika Kuoppala75d04a32015-04-28 17:56:17 +03003021 ret = vma->vm->allocate_va_range(vma->vm,
3022 vma->node.start,
3023 vma->node.size);
Mika Kuoppalab2dd4512015-06-25 18:35:15 +03003024 vma->pin_count--;
Mika Kuoppala75d04a32015-04-28 17:56:17 +03003025 if (ret)
3026 return ret;
3027 }
3028
3029 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
Daniel Vetter70b9f6f2015-04-14 17:35:27 +02003030 if (ret)
3031 return ret;
Daniel Vetter08755462015-04-20 09:04:05 -07003032
3033 vma->bound |= bind_flags;
Tvrtko Ursulinfe14d5f2014-12-10 17:27:58 +00003034
3035 return 0;
3036}
Joonas Lahtinen91e67112015-05-06 14:33:58 +03003037
3038/**
3039 * i915_ggtt_view_size - Get the size of a GGTT view.
3040 * @obj: Object the view is of.
3041 * @view: The view in question.
3042 *
3043 * @return The size of the GGTT view in bytes.
3044 */
3045size_t
3046i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3047 const struct i915_ggtt_view *view)
3048{
Tvrtko Ursulin9e759ff2015-06-23 12:57:43 +01003049 if (view->type == I915_GGTT_VIEW_NORMAL) {
Joonas Lahtinen91e67112015-05-06 14:33:58 +03003050 return obj->base.size;
Tvrtko Ursulin9e759ff2015-06-23 12:57:43 +01003051 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3052 return view->rotation_info.size;
Joonas Lahtinen8bd7ef12015-05-06 14:35:38 +03003053 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3054 return view->params.partial.size << PAGE_SHIFT;
Joonas Lahtinen91e67112015-05-06 14:33:58 +03003055 } else {
3056 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3057 return obj->base.size;
3058 }
3059}