blob: 11e791b965f6a772588ac7dff64437b3ec836e70 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 *
Takashi Iwaid01ce992007-07-27 16:52:19 +02003 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
Linus Torvalds1da177e2005-04-16 15:20:36 -07005 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
Linus Torvalds1da177e2005-04-16 15:20:36 -070037#include <asm/io.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
Randy Dunlap362775e2005-11-07 14:43:23 +010040#include <linux/kernel.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070041#include <linux/module.h>
Andrew Morton24982c52008-03-04 10:08:58 +010042#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070043#include <linux/moduleparam.h>
44#include <linux/init.h>
45#include <linux/slab.h>
46#include <linux/pci.h>
Ingo Molnar62932df2006-01-16 16:34:20 +010047#include <linux/mutex.h>
Takashi Iwai0cbf0092008-10-29 16:18:25 +010048#include <linux/reboot.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070049#include <sound/core.h>
50#include <sound/initval.h>
51#include "hda_codec.h"
52
53
Takashi Iwai5aba4f82008-01-07 15:16:37 +010054static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57static char *model[SNDRV_CARDS];
58static int position_fix[SNDRV_CARDS];
Takashi Iwai5c0d7bc2008-06-10 17:53:35 +020059static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
Takashi Iwai5aba4f82008-01-07 15:16:37 +010060static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
Takashi Iwaid4d9cd032008-12-19 15:19:11 +010061static int probe_only[SNDRV_CARDS];
Takashi Iwai27346162006-01-12 18:28:44 +010062static int single_cmd;
Takashi Iwai134a11f2006-11-10 12:08:37 +010063static int enable_msi;
Linus Torvalds1da177e2005-04-16 15:20:36 -070064
Takashi Iwai5aba4f82008-01-07 15:16:37 +010065module_param_array(index, int, NULL, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070066MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010067module_param_array(id, charp, NULL, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070068MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010069module_param_array(enable, bool, NULL, 0444);
70MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
71module_param_array(model, charp, NULL, 0444);
Linus Torvalds1da177e2005-04-16 15:20:36 -070072MODULE_PARM_DESC(model, "Use the given board model.");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010073module_param_array(position_fix, int, NULL, 0444);
Takashi Iwaid01ce992007-07-27 16:52:19 +020074MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
Takashi Iwaid2e1c972008-06-10 17:53:34 +020075 "(0 = auto, 1 = none, 2 = POSBUF).");
Takashi Iwai555e2192008-06-10 17:53:34 +020076module_param_array(bdl_pos_adj, int, NULL, 0644);
77MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010078module_param_array(probe_mask, int, NULL, 0444);
Takashi Iwai606ad752005-11-24 16:03:40 +010079MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
Takashi Iwaid4d9cd032008-12-19 15:19:11 +010080module_param_array(probe_only, bool, NULL, 0444);
81MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
Takashi Iwai27346162006-01-12 18:28:44 +010082module_param(single_cmd, bool, 0444);
Takashi Iwaid01ce992007-07-27 16:52:19 +020083MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
84 "(for debugging only).");
Takashi Iwai5aba4f82008-01-07 15:16:37 +010085module_param(enable_msi, int, 0444);
Takashi Iwai134a11f2006-11-10 12:08:37 +010086MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
Takashi Iwai606ad752005-11-24 16:03:40 +010087
Takashi Iwaidee1b662007-08-13 16:10:30 +020088#ifdef CONFIG_SND_HDA_POWER_SAVE
Takashi Iwaifee2fba2008-11-27 12:43:28 +010089static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
90module_param(power_save, int, 0644);
91MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
92 "(in second, 0 = disable).");
Linus Torvalds1da177e2005-04-16 15:20:36 -070093
Takashi Iwaidee1b662007-08-13 16:10:30 +020094/* reset the HD-audio controller in power save mode.
95 * this may give more power-saving, but will take longer time to
96 * wake up.
97 */
98static int power_save_controller = 1;
99module_param(power_save_controller, bool, 0644);
100MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
101#endif
102
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103MODULE_LICENSE("GPL");
104MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
105 "{Intel, ICH6M},"
Jason Gaston2f1b3812005-05-01 08:58:50 -0700106 "{Intel, ICH7},"
Frederick Lif5d40b32005-05-12 14:55:20 +0200107 "{Intel, ESB2},"
Jason Gastond2981392006-01-10 11:07:37 +0100108 "{Intel, ICH8},"
Jason Gastonf9cc8a82006-11-22 11:53:52 +0100109 "{Intel, ICH9},"
Jason Gastonc34f5a02008-01-29 12:38:49 +0100110 "{Intel, ICH10},"
Seth Heasleyb29c2362008-08-08 15:56:39 -0700111 "{Intel, PCH},"
Tobin Davis4979bca2008-01-30 08:13:55 +0100112 "{Intel, SCH},"
Takashi Iwaifc20a562005-05-12 15:00:41 +0200113 "{ATI, SB450},"
Felix Kuehling89be83f2006-03-31 12:33:59 +0200114 "{ATI, SB600},"
Felix Kuehling778b6e12006-05-17 11:22:21 +0200115 "{ATI, RS600},"
Felix Kuehling5b15c952006-10-16 12:49:47 +0200116 "{ATI, RS690},"
Wolke Liue6db1112007-04-27 12:20:57 +0200117 "{ATI, RS780},"
118 "{ATI, R600},"
Herton Ronaldo Krzesinski2797f722007-11-05 18:21:56 +0100119 "{ATI, RV630},"
120 "{ATI, RV610},"
Wolke Liu27da1832007-11-16 11:06:30 +0100121 "{ATI, RV670},"
122 "{ATI, RV635},"
123 "{ATI, RV620},"
124 "{ATI, RV770},"
Takashi Iwaifc20a562005-05-12 15:00:41 +0200125 "{VIA, VT8251},"
Takashi Iwai47672312005-08-12 16:44:04 +0200126 "{VIA, VT8237A},"
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200127 "{SiS, SIS966},"
128 "{ULI, M5461}}");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129MODULE_DESCRIPTION("Intel HDA driver");
130
131#define SFX "hda-intel: "
132
Takashi Iwaicb53c622007-08-10 17:21:45 +0200133
134/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700135 * registers
136 */
137#define ICH6_REG_GCAP 0x00
138#define ICH6_REG_VMIN 0x02
139#define ICH6_REG_VMAJ 0x03
140#define ICH6_REG_OUTPAY 0x04
141#define ICH6_REG_INPAY 0x06
142#define ICH6_REG_GCTL 0x08
143#define ICH6_REG_WAKEEN 0x0c
144#define ICH6_REG_STATESTS 0x0e
145#define ICH6_REG_GSTS 0x10
146#define ICH6_REG_INTCTL 0x20
147#define ICH6_REG_INTSTS 0x24
148#define ICH6_REG_WALCLK 0x30
149#define ICH6_REG_SYNC 0x34
150#define ICH6_REG_CORBLBASE 0x40
151#define ICH6_REG_CORBUBASE 0x44
152#define ICH6_REG_CORBWP 0x48
153#define ICH6_REG_CORBRP 0x4A
154#define ICH6_REG_CORBCTL 0x4c
155#define ICH6_REG_CORBSTS 0x4d
156#define ICH6_REG_CORBSIZE 0x4e
157
158#define ICH6_REG_RIRBLBASE 0x50
159#define ICH6_REG_RIRBUBASE 0x54
160#define ICH6_REG_RIRBWP 0x58
161#define ICH6_REG_RINTCNT 0x5a
162#define ICH6_REG_RIRBCTL 0x5c
163#define ICH6_REG_RIRBSTS 0x5d
164#define ICH6_REG_RIRBSIZE 0x5e
165
166#define ICH6_REG_IC 0x60
167#define ICH6_REG_IR 0x64
168#define ICH6_REG_IRS 0x68
169#define ICH6_IRS_VALID (1<<1)
170#define ICH6_IRS_BUSY (1<<0)
171
172#define ICH6_REG_DPLBASE 0x70
173#define ICH6_REG_DPUBASE 0x74
174#define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
175
176/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
177enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
178
179/* stream register offsets from stream base */
180#define ICH6_REG_SD_CTL 0x00
181#define ICH6_REG_SD_STS 0x03
182#define ICH6_REG_SD_LPIB 0x04
183#define ICH6_REG_SD_CBL 0x08
184#define ICH6_REG_SD_LVI 0x0c
185#define ICH6_REG_SD_FIFOW 0x0e
186#define ICH6_REG_SD_FIFOSIZE 0x10
187#define ICH6_REG_SD_FORMAT 0x12
188#define ICH6_REG_SD_BDLPL 0x18
189#define ICH6_REG_SD_BDLPU 0x1c
190
191/* PCI space */
192#define ICH6_PCIREG_TCSEL 0x44
193
194/*
195 * other constants
196 */
197
198/* max number of SDs */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200199/* ICH, ATI and VIA have 4 playback and 4 capture */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200200#define ICH6_NUM_CAPTURE 4
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200201#define ICH6_NUM_PLAYBACK 4
202
203/* ULI has 6 playback and 5 capture */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200204#define ULI_NUM_CAPTURE 5
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200205#define ULI_NUM_PLAYBACK 6
206
Felix Kuehling778b6e12006-05-17 11:22:21 +0200207/* ATI HDMI has 1 playback and 0 capture */
Felix Kuehling778b6e12006-05-17 11:22:21 +0200208#define ATIHDMI_NUM_CAPTURE 0
Felix Kuehling778b6e12006-05-17 11:22:21 +0200209#define ATIHDMI_NUM_PLAYBACK 1
210
Kailang Yangf2690022008-05-27 11:44:55 +0200211/* TERA has 4 playback and 3 capture */
212#define TERA_NUM_CAPTURE 3
213#define TERA_NUM_PLAYBACK 4
214
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200215/* this number is statically defined for simplicity */
216#define MAX_AZX_DEV 16
217
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218/* max number of fragments - we may use more if allocating more pages for BDL */
Takashi Iwai4ce107b2008-02-06 14:50:19 +0100219#define BDL_SIZE 4096
220#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
221#define AZX_MAX_FRAG 32
Linus Torvalds1da177e2005-04-16 15:20:36 -0700222/* max buffer size - no h/w limit, you can increase as you like */
223#define AZX_MAX_BUF_SIZE (1024*1024*1024)
224/* max number of PCM devics per card */
Takashi Iwai7ba72ba2008-02-06 14:03:20 +0100225#define AZX_MAX_PCMS 8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226
227/* RIRB int mask: overrun[2], response[0] */
228#define RIRB_INT_RESPONSE 0x01
229#define RIRB_INT_OVERRUN 0x04
230#define RIRB_INT_MASK 0x05
231
Takashi Iwai2f5983f2008-09-03 16:00:44 +0200232/* STATESTS int mask: S3,SD2,SD1,SD0 */
233#define AZX_MAX_CODECS 4
234#define STATESTS_INT_MASK 0x0f
Linus Torvalds1da177e2005-04-16 15:20:36 -0700235
236/* SD_CTL bits */
237#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
238#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
Takashi Iwai850f0e52008-03-18 17:11:05 +0100239#define SD_CTL_STRIPE (3 << 16) /* stripe control */
240#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
241#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700242#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
243#define SD_CTL_STREAM_TAG_SHIFT 20
244
245/* SD_CTL and SD_STS */
246#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
247#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
248#define SD_INT_COMPLETE 0x04 /* completion interrupt */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200249#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
250 SD_INT_COMPLETE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700251
252/* SD_STS */
253#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
254
255/* INTCTL and INTSTS */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200256#define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
257#define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
258#define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700259
Matt41e2fce2005-07-04 17:49:55 +0200260/* GCTL unsolicited response enable bit */
261#define ICH6_GCTL_UREN (1<<8)
262
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263/* GCTL reset bit */
264#define ICH6_GCTL_RESET (1<<0)
265
266/* CORB/RIRB control, read/write pointer */
267#define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
268#define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
269#define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
270/* below are so far hardcoded - should read registers in future */
271#define ICH6_MAX_CORB_ENTRIES 256
272#define ICH6_MAX_RIRB_ENTRIES 256
273
Takashi Iwaic74db862005-05-12 14:26:27 +0200274/* position fix mode */
275enum {
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200276 POS_FIX_AUTO,
Takashi Iwaid2e1c972008-06-10 17:53:34 +0200277 POS_FIX_LPIB,
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200278 POS_FIX_POSBUF,
Takashi Iwaic74db862005-05-12 14:26:27 +0200279};
Linus Torvalds1da177e2005-04-16 15:20:36 -0700280
Frederick Lif5d40b32005-05-12 14:55:20 +0200281/* Defines for ATI HD Audio support in SB450 south bridge */
Frederick Lif5d40b32005-05-12 14:55:20 +0200282#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
283#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
284
Vinod Gda3fca22005-09-13 18:49:12 +0200285/* Defines for Nvidia HDA support */
286#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
287#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
Peer Chen320dcc32008-08-20 16:43:24 -0700288#define NVIDIA_HDA_ISTRM_COH 0x4d
289#define NVIDIA_HDA_OSTRM_COH 0x4c
290#define NVIDIA_HDA_ENABLE_COHBIT 0x01
Frederick Lif5d40b32005-05-12 14:55:20 +0200291
Takashi Iwai90a5ad52008-02-22 18:36:22 +0100292/* Defines for Intel SCH HDA snoop control */
293#define INTEL_SCH_HDA_DEVC 0x78
294#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
295
Joseph Chan0e153472008-08-26 14:38:03 +0200296/* Define IN stream 0 FIFO size offset in VIA controller */
297#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
298/* Define VIA HD Audio Device ID*/
299#define VIA_HDAC_DEVICE_ID 0x3288
300
Yang, Libinc4da29c2008-11-13 11:07:07 +0100301/* HD Audio class code */
302#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
Takashi Iwai90a5ad52008-02-22 18:36:22 +0100303
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305 */
306
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100307struct azx_dev {
Takashi Iwai4ce107b2008-02-06 14:50:19 +0100308 struct snd_dma_buffer bdl; /* BDL buffer */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200309 u32 *posbuf; /* position buffer pointer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310
Takashi Iwaid01ce992007-07-27 16:52:19 +0200311 unsigned int bufsize; /* size of the play buffer in bytes */
Takashi Iwai9ad593f2008-05-16 12:34:47 +0200312 unsigned int period_bytes; /* size of the period in bytes */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200313 unsigned int frags; /* number for period in the play buffer */
314 unsigned int fifo_size; /* FIFO size */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315
Takashi Iwaid01ce992007-07-27 16:52:19 +0200316 void __iomem *sd_addr; /* stream descriptor pointer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317
Takashi Iwaid01ce992007-07-27 16:52:19 +0200318 u32 sd_int_sta_mask; /* stream int status mask */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700319
320 /* pcm support */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200321 struct snd_pcm_substream *substream; /* assigned substream,
322 * set in PCM open
323 */
324 unsigned int format_val; /* format value to be set in the
325 * controller and the codec
326 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327 unsigned char stream_tag; /* assigned stream */
328 unsigned char index; /* stream index */
329
Pavel Machek927fc862006-08-31 17:03:43 +0200330 unsigned int opened :1;
331 unsigned int running :1;
Takashi Iwai675f25d2008-06-10 17:53:20 +0200332 unsigned int irq_pending :1;
333 unsigned int irq_ignore :1;
Joseph Chan0e153472008-08-26 14:38:03 +0200334 /*
335 * For VIA:
336 * A flag to ensure DMA position is 0
337 * when link position is not greater than FIFO size
338 */
339 unsigned int insufficient :1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340};
341
342/* CORB/RIRB */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100343struct azx_rb {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344 u32 *buf; /* CORB/RIRB buffer
345 * Each CORB entry is 4byte, RIRB is 8byte
346 */
347 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
348 /* for RIRB */
349 unsigned short rp, wp; /* read/write pointers */
350 int cmds; /* number of pending requests */
351 u32 res; /* last read value */
352};
353
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100354struct azx {
355 struct snd_card *card;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356 struct pci_dev *pci;
Takashi Iwai555e2192008-06-10 17:53:34 +0200357 int dev_index;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700358
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200359 /* chip type specific */
360 int driver_type;
361 int playback_streams;
362 int playback_index_offset;
363 int capture_streams;
364 int capture_index_offset;
365 int num_streams;
366
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367 /* pci resources */
368 unsigned long addr;
369 void __iomem *remap_addr;
370 int irq;
371
372 /* locks */
373 spinlock_t reg_lock;
Ingo Molnar62932df2006-01-16 16:34:20 +0100374 struct mutex open_mutex;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200376 /* streams (x num_streams) */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100377 struct azx_dev *azx_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700378
379 /* PCM */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100380 struct snd_pcm *pcm[AZX_MAX_PCMS];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381
382 /* HD codec */
383 unsigned short codec_mask;
384 struct hda_bus *bus;
385
386 /* CORB/RIRB */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100387 struct azx_rb corb;
388 struct azx_rb rirb;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389
Takashi Iwai4ce107b2008-02-06 14:50:19 +0100390 /* CORB/RIRB and position buffers */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700391 struct snd_dma_buffer rb;
392 struct snd_dma_buffer posbuf;
Takashi Iwaic74db862005-05-12 14:26:27 +0200393
394 /* flags */
395 int position_fix;
Takashi Iwaicb53c622007-08-10 17:21:45 +0200396 unsigned int running :1;
Pavel Machek927fc862006-08-31 17:03:43 +0200397 unsigned int initialized :1;
398 unsigned int single_cmd :1;
399 unsigned int polling_mode :1;
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200400 unsigned int msi :1;
Takashi Iwaia6a950a2008-06-10 17:53:35 +0200401 unsigned int irq_pending_warned :1;
Joseph Chan0e153472008-08-26 14:38:03 +0200402 unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +0100403 unsigned int probing :1; /* codec probing phase */
Takashi Iwai43bbb6c2007-07-06 20:22:05 +0200404
405 /* for debugging */
406 unsigned int last_cmd; /* last issued command (to sync) */
Takashi Iwai9ad593f2008-05-16 12:34:47 +0200407
408 /* for pending irqs */
409 struct work_struct irq_pending_work;
Takashi Iwai0cbf0092008-10-29 16:18:25 +0100410
411 /* reboot notifier (for mysterious hangup problem at power-down) */
412 struct notifier_block reboot_notifier;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413};
414
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200415/* driver types */
416enum {
417 AZX_DRIVER_ICH,
Tobin Davis4979bca2008-01-30 08:13:55 +0100418 AZX_DRIVER_SCH,
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200419 AZX_DRIVER_ATI,
Felix Kuehling778b6e12006-05-17 11:22:21 +0200420 AZX_DRIVER_ATIHDMI,
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200421 AZX_DRIVER_VIA,
422 AZX_DRIVER_SIS,
423 AZX_DRIVER_ULI,
Vinod Gda3fca22005-09-13 18:49:12 +0200424 AZX_DRIVER_NVIDIA,
Kailang Yangf2690022008-05-27 11:44:55 +0200425 AZX_DRIVER_TERA,
Yang, Libinc4da29c2008-11-13 11:07:07 +0100426 AZX_DRIVER_GENERIC,
Takashi Iwai2f5983f2008-09-03 16:00:44 +0200427 AZX_NUM_DRIVERS, /* keep this as last entry */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200428};
429
430static char *driver_short_names[] __devinitdata = {
431 [AZX_DRIVER_ICH] = "HDA Intel",
Tobin Davis4979bca2008-01-30 08:13:55 +0100432 [AZX_DRIVER_SCH] = "HDA Intel MID",
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200433 [AZX_DRIVER_ATI] = "HDA ATI SB",
Felix Kuehling778b6e12006-05-17 11:22:21 +0200434 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200435 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
436 [AZX_DRIVER_SIS] = "HDA SIS966",
Vinod Gda3fca22005-09-13 18:49:12 +0200437 [AZX_DRIVER_ULI] = "HDA ULI M5461",
438 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
Kailang Yangf2690022008-05-27 11:44:55 +0200439 [AZX_DRIVER_TERA] = "HDA Teradici",
Yang, Libinc4da29c2008-11-13 11:07:07 +0100440 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200441};
442
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443/*
444 * macros for easy use
445 */
446#define azx_writel(chip,reg,value) \
447 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
448#define azx_readl(chip,reg) \
449 readl((chip)->remap_addr + ICH6_REG_##reg)
450#define azx_writew(chip,reg,value) \
451 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
452#define azx_readw(chip,reg) \
453 readw((chip)->remap_addr + ICH6_REG_##reg)
454#define azx_writeb(chip,reg,value) \
455 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
456#define azx_readb(chip,reg) \
457 readb((chip)->remap_addr + ICH6_REG_##reg)
458
459#define azx_sd_writel(dev,reg,value) \
460 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
461#define azx_sd_readl(dev,reg) \
462 readl((dev)->sd_addr + ICH6_REG_##reg)
463#define azx_sd_writew(dev,reg,value) \
464 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
465#define azx_sd_readw(dev,reg) \
466 readw((dev)->sd_addr + ICH6_REG_##reg)
467#define azx_sd_writeb(dev,reg,value) \
468 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
469#define azx_sd_readb(dev,reg) \
470 readb((dev)->sd_addr + ICH6_REG_##reg)
471
472/* for pcm support */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100473#define get_azx_dev(substream) (substream->runtime->private_data)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700474
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200475static int azx_acquire_irq(struct azx *chip, int do_disconnect);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700476
477/*
478 * Interface for HD codec
479 */
480
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481/*
482 * CORB / RIRB interface
483 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100484static int azx_alloc_cmd_io(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700485{
486 int err;
487
488 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200489 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
490 snd_dma_pci_data(chip->pci),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491 PAGE_SIZE, &chip->rb);
492 if (err < 0) {
493 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
494 return err;
495 }
496 return 0;
497}
498
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100499static void azx_init_cmd_io(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700500{
501 /* CORB set up */
502 chip->corb.addr = chip->rb.addr;
503 chip->corb.buf = (u32 *)chip->rb.area;
504 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
Takashi Iwai766979e2008-06-13 20:53:56 +0200505 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200507 /* set the corb size to 256 entries (ULI requires explicitly) */
508 azx_writeb(chip, CORBSIZE, 0x02);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700509 /* set the corb write pointer to 0 */
510 azx_writew(chip, CORBWP, 0);
511 /* reset the corb hw read pointer */
512 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
513 /* enable corb dma */
514 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
515
516 /* RIRB set up */
517 chip->rirb.addr = chip->rb.addr + 2048;
518 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
519 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
Takashi Iwai766979e2008-06-13 20:53:56 +0200520 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700521
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200522 /* set the rirb size to 256 entries (ULI requires explicitly) */
523 azx_writeb(chip, RIRBSIZE, 0x02);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524 /* reset the rirb hw write pointer */
525 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
526 /* set N=1, get RIRB response interrupt for new entry */
527 azx_writew(chip, RINTCNT, 1);
528 /* enable rirb dma and response irq */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700529 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700530 chip->rirb.rp = chip->rirb.cmds = 0;
531}
532
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100533static void azx_free_cmd_io(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700534{
535 /* disable ringbuffer DMAs */
536 azx_writeb(chip, RIRBCTL, 0);
537 azx_writeb(chip, CORBCTL, 0);
538}
539
540/* send a command */
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100541static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100543 struct azx *chip = bus->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700544 unsigned int wp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700545
546 /* add command to corb */
547 wp = azx_readb(chip, CORBWP);
548 wp++;
549 wp %= ICH6_MAX_CORB_ENTRIES;
550
551 spin_lock_irq(&chip->reg_lock);
552 chip->rirb.cmds++;
553 chip->corb.buf[wp] = cpu_to_le32(val);
554 azx_writel(chip, CORBWP, wp);
555 spin_unlock_irq(&chip->reg_lock);
556
557 return 0;
558}
559
560#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
561
562/* retrieve RIRB entry - called from interrupt handler */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100563static void azx_update_rirb(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700564{
565 unsigned int rp, wp;
566 u32 res, res_ex;
567
568 wp = azx_readb(chip, RIRBWP);
569 if (wp == chip->rirb.wp)
570 return;
571 chip->rirb.wp = wp;
572
573 while (chip->rirb.rp != wp) {
574 chip->rirb.rp++;
575 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
576
577 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
578 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
579 res = le32_to_cpu(chip->rirb.buf[rp]);
580 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
581 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
582 else if (chip->rirb.cmds) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583 chip->rirb.res = res;
Takashi Iwai2add9b92008-03-18 09:47:06 +0100584 smp_wmb();
585 chip->rirb.cmds--;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700586 }
587 }
588}
589
590/* receive a response */
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100591static unsigned int azx_rirb_get_response(struct hda_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100593 struct azx *chip = bus->private_data;
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200594 unsigned long timeout;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700595
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200596 again:
597 timeout = jiffies + msecs_to_jiffies(1000);
Takashi Iwai28a0d9d2008-01-18 15:32:32 +0100598 for (;;) {
Takashi Iwaie96224a2006-08-21 17:57:44 +0200599 if (chip->polling_mode) {
600 spin_lock_irq(&chip->reg_lock);
601 azx_update_rirb(chip);
602 spin_unlock_irq(&chip->reg_lock);
603 }
Takashi Iwai2add9b92008-03-18 09:47:06 +0100604 if (!chip->rirb.cmds) {
605 smp_rmb();
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200606 return chip->rirb.res; /* the last value */
Takashi Iwai2add9b92008-03-18 09:47:06 +0100607 }
Takashi Iwai28a0d9d2008-01-18 15:32:32 +0100608 if (time_after(jiffies, timeout))
609 break;
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100610 if (bus->needs_damn_long_delay)
Takashi Iwai52987652008-01-16 16:09:47 +0100611 msleep(2); /* temporary workaround */
612 else {
613 udelay(10);
614 cond_resched();
615 }
Takashi Iwai28a0d9d2008-01-18 15:32:32 +0100616 }
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200617
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200618 if (chip->msi) {
619 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
Takashi Iwai43bbb6c2007-07-06 20:22:05 +0200620 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
Takashi Iwai68e7fff2006-10-23 13:40:59 +0200621 free_irq(chip->irq, chip);
622 chip->irq = -1;
623 pci_disable_msi(chip->pci);
624 chip->msi = 0;
625 if (azx_acquire_irq(chip, 1) < 0)
626 return -1;
627 goto again;
628 }
629
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200630 if (!chip->polling_mode) {
631 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
Takashi Iwai43bbb6c2007-07-06 20:22:05 +0200632 "switching to polling mode: last cmd=0x%08x\n",
633 chip->last_cmd);
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200634 chip->polling_mode = 1;
635 goto again;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636 }
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200637
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +0100638 if (chip->probing) {
639 /* If this critical timeout happens during the codec probing
640 * phase, this is likely an access to a non-existing codec
641 * slot. Better to return an error and reset the system.
642 */
643 return -1;
644 }
645
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200646 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
Takashi Iwai43bbb6c2007-07-06 20:22:05 +0200647 "switching to single_cmd mode: last cmd=0x%08x\n",
648 chip->last_cmd);
Takashi Iwai5c79b1f2006-09-21 13:34:13 +0200649 chip->rirb.rp = azx_readb(chip, RIRBWP);
650 chip->rirb.cmds = 0;
651 /* switch to single_cmd mode */
652 chip->single_cmd = 1;
653 azx_free_cmd_io(chip);
654 return -1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700655}
656
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657/*
658 * Use the single immediate command instead of CORB/RIRB for simplicity
659 *
660 * Note: according to Intel, this is not preferred use. The command was
661 * intended for the BIOS only, and may get confused with unsolicited
662 * responses. So, we shouldn't use it for normal operation from the
663 * driver.
664 * I left the codes, however, for debugging/testing purposes.
665 */
666
Linus Torvalds1da177e2005-04-16 15:20:36 -0700667/* send a command */
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100668static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100670 struct azx *chip = bus->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700671 int timeout = 50;
672
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673 while (timeout--) {
674 /* check ICB busy bit */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200675 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700676 /* Clear IRV valid bit */
Takashi Iwaid01ce992007-07-27 16:52:19 +0200677 azx_writew(chip, IRS, azx_readw(chip, IRS) |
678 ICH6_IRS_VALID);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700679 azx_writel(chip, IC, val);
Takashi Iwaid01ce992007-07-27 16:52:19 +0200680 azx_writew(chip, IRS, azx_readw(chip, IRS) |
681 ICH6_IRS_BUSY);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700682 return 0;
683 }
684 udelay(1);
685 }
Marc Boucher1cfd52b2008-01-22 15:29:26 +0100686 if (printk_ratelimit())
687 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
688 azx_readw(chip, IRS), val);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700689 return -EIO;
690}
691
692/* receive a response */
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100693static unsigned int azx_single_get_response(struct hda_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700694{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100695 struct azx *chip = bus->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700696 int timeout = 50;
697
698 while (timeout--) {
699 /* check IRV busy bit */
700 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
701 return azx_readl(chip, IR);
702 udelay(1);
703 }
Marc Boucher1cfd52b2008-01-22 15:29:26 +0100704 if (printk_ratelimit())
705 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
706 azx_readw(chip, IRS));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700707 return (unsigned int)-1;
708}
709
Takashi Iwai111d3af2006-02-16 18:17:58 +0100710/*
711 * The below are the main callbacks from hda_codec.
712 *
713 * They are just the skeleton to call sub-callbacks according to the
714 * current setting of chip->single_cmd.
715 */
716
717/* send a command */
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100718static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
Takashi Iwai111d3af2006-02-16 18:17:58 +0100719{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100720 struct azx *chip = bus->private_data;
Takashi Iwai43bbb6c2007-07-06 20:22:05 +0200721
Takashi Iwai43bbb6c2007-07-06 20:22:05 +0200722 chip->last_cmd = val;
Takashi Iwai111d3af2006-02-16 18:17:58 +0100723 if (chip->single_cmd)
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100724 return azx_single_send_cmd(bus, val);
Takashi Iwai111d3af2006-02-16 18:17:58 +0100725 else
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100726 return azx_corb_send_cmd(bus, val);
Takashi Iwai111d3af2006-02-16 18:17:58 +0100727}
728
729/* get a response */
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100730static unsigned int azx_get_response(struct hda_bus *bus)
Takashi Iwai111d3af2006-02-16 18:17:58 +0100731{
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100732 struct azx *chip = bus->private_data;
Takashi Iwai111d3af2006-02-16 18:17:58 +0100733 if (chip->single_cmd)
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100734 return azx_single_get_response(bus);
Takashi Iwai111d3af2006-02-16 18:17:58 +0100735 else
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100736 return azx_rirb_get_response(bus);
Takashi Iwai111d3af2006-02-16 18:17:58 +0100737}
738
Takashi Iwaicb53c622007-08-10 17:21:45 +0200739#ifdef CONFIG_SND_HDA_POWER_SAVE
Takashi Iwai33fa35e2008-11-06 16:50:40 +0100740static void azx_power_notify(struct hda_bus *bus);
Takashi Iwaicb53c622007-08-10 17:21:45 +0200741#endif
Takashi Iwai111d3af2006-02-16 18:17:58 +0100742
Linus Torvalds1da177e2005-04-16 15:20:36 -0700743/* reset codec link */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100744static int azx_reset(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700745{
746 int count;
747
Danny Tholene8a7f132007-09-11 21:41:56 +0200748 /* clear STATESTS */
749 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
750
Linus Torvalds1da177e2005-04-16 15:20:36 -0700751 /* reset controller */
752 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
753
754 count = 50;
755 while (azx_readb(chip, GCTL) && --count)
756 msleep(1);
757
758 /* delay for >= 100us for codec PLL to settle per spec
759 * Rev 0.9 section 5.5.1
760 */
761 msleep(1);
762
763 /* Bring controller out of reset */
764 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
765
766 count = 50;
Pavel Machek927fc862006-08-31 17:03:43 +0200767 while (!azx_readb(chip, GCTL) && --count)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700768 msleep(1);
769
Pavel Machek927fc862006-08-31 17:03:43 +0200770 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700771 msleep(1);
772
773 /* check to see if controller is ready */
Pavel Machek927fc862006-08-31 17:03:43 +0200774 if (!azx_readb(chip, GCTL)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700775 snd_printd("azx_reset: controller not ready!\n");
776 return -EBUSY;
777 }
778
Matt41e2fce2005-07-04 17:49:55 +0200779 /* Accept unsolicited responses */
780 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
781
Linus Torvalds1da177e2005-04-16 15:20:36 -0700782 /* detect codecs */
Pavel Machek927fc862006-08-31 17:03:43 +0200783 if (!chip->codec_mask) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700784 chip->codec_mask = azx_readw(chip, STATESTS);
785 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
786 }
787
788 return 0;
789}
790
791
792/*
793 * Lowlevel interface
794 */
795
796/* enable interrupts */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100797static void azx_int_enable(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798{
799 /* enable controller CIE and GIE */
800 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
801 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
802}
803
804/* disable interrupts */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100805static void azx_int_disable(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700806{
807 int i;
808
809 /* disable interrupts in stream descriptor */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200810 for (i = 0; i < chip->num_streams; i++) {
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100811 struct azx_dev *azx_dev = &chip->azx_dev[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700812 azx_sd_writeb(azx_dev, SD_CTL,
813 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
814 }
815
816 /* disable SIE for all streams */
817 azx_writeb(chip, INTCTL, 0);
818
819 /* disable controller CIE and GIE */
820 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
821 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
822}
823
824/* clear interrupts */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100825static void azx_int_clear(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700826{
827 int i;
828
829 /* clear stream status */
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200830 for (i = 0; i < chip->num_streams; i++) {
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100831 struct azx_dev *azx_dev = &chip->azx_dev[i];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
833 }
834
835 /* clear STATESTS */
836 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
837
838 /* clear rirb status */
839 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
840
841 /* clear int status */
842 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
843}
844
845/* start a stream */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100846static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700847{
Joseph Chan0e153472008-08-26 14:38:03 +0200848 /*
849 * Before stream start, initialize parameter
850 */
851 azx_dev->insufficient = 1;
852
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853 /* enable SIE */
854 azx_writeb(chip, INTCTL,
855 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
856 /* set DMA start and interrupt mask */
857 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
858 SD_CTL_DMA_START | SD_INT_MASK);
859}
860
861/* stop a stream */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100862static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863{
864 /* stop DMA */
865 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
866 ~(SD_CTL_DMA_START | SD_INT_MASK));
867 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
868 /* disable SIE */
869 azx_writeb(chip, INTCTL,
870 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
871}
872
873
874/*
Takashi Iwaicb53c622007-08-10 17:21:45 +0200875 * reset and start the controller registers
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100877static void azx_init_chip(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700878{
Takashi Iwaicb53c622007-08-10 17:21:45 +0200879 if (chip->initialized)
880 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700881
882 /* reset controller */
883 azx_reset(chip);
884
885 /* initialize interrupts */
886 azx_int_clear(chip);
887 azx_int_enable(chip);
888
889 /* initialize the codec command I/O */
Pavel Machek927fc862006-08-31 17:03:43 +0200890 if (!chip->single_cmd)
Takashi Iwai27346162006-01-12 18:28:44 +0100891 azx_init_cmd_io(chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892
Takashi Iwai0be3b5d2005-09-05 17:11:40 +0200893 /* program the position buffer */
894 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
Takashi Iwai766979e2008-06-13 20:53:56 +0200895 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
Frederick Lif5d40b32005-05-12 14:55:20 +0200896
Takashi Iwaicb53c622007-08-10 17:21:45 +0200897 chip->initialized = 1;
898}
899
900/*
901 * initialize the PCI registers
902 */
903/* update bits in a PCI register byte */
904static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
905 unsigned char mask, unsigned char val)
906{
907 unsigned char data;
908
909 pci_read_config_byte(pci, reg, &data);
910 data &= ~mask;
911 data |= (val & mask);
912 pci_write_config_byte(pci, reg, data);
913}
914
915static void azx_init_pci(struct azx *chip)
916{
Takashi Iwai90a5ad52008-02-22 18:36:22 +0100917 unsigned short snoop;
918
Takashi Iwaicb53c622007-08-10 17:21:45 +0200919 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
920 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
921 * Ensuring these bits are 0 clears playback static on some HD Audio
922 * codecs
923 */
924 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
925
Vinod Gda3fca22005-09-13 18:49:12 +0200926 switch (chip->driver_type) {
927 case AZX_DRIVER_ATI:
928 /* For ATI SB450 azalia HD audio, we need to enable snoop */
Takashi Iwaicb53c622007-08-10 17:21:45 +0200929 update_pci_byte(chip->pci,
930 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
931 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
Vinod Gda3fca22005-09-13 18:49:12 +0200932 break;
933 case AZX_DRIVER_NVIDIA:
934 /* For NVIDIA HDA, enable snoop */
Takashi Iwaicb53c622007-08-10 17:21:45 +0200935 update_pci_byte(chip->pci,
936 NVIDIA_HDA_TRANSREG_ADDR,
937 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
Peer Chen320dcc32008-08-20 16:43:24 -0700938 update_pci_byte(chip->pci,
939 NVIDIA_HDA_ISTRM_COH,
940 0x01, NVIDIA_HDA_ENABLE_COHBIT);
941 update_pci_byte(chip->pci,
942 NVIDIA_HDA_OSTRM_COH,
943 0x01, NVIDIA_HDA_ENABLE_COHBIT);
Vinod Gda3fca22005-09-13 18:49:12 +0200944 break;
Takashi Iwai90a5ad52008-02-22 18:36:22 +0100945 case AZX_DRIVER_SCH:
946 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
947 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
948 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
949 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
950 pci_read_config_word(chip->pci,
951 INTEL_SCH_HDA_DEVC, &snoop);
952 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
953 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
954 ? "Failed" : "OK");
955 }
956 break;
957
Vinod Gda3fca22005-09-13 18:49:12 +0200958 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700959}
960
961
Takashi Iwai9ad593f2008-05-16 12:34:47 +0200962static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
963
Linus Torvalds1da177e2005-04-16 15:20:36 -0700964/*
965 * interrupt handler
966 */
David Howells7d12e782006-10-05 14:55:46 +0100967static irqreturn_t azx_interrupt(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700968{
Takashi Iwaia98f90f2005-11-17 14:59:02 +0100969 struct azx *chip = dev_id;
970 struct azx_dev *azx_dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971 u32 status;
972 int i;
973
974 spin_lock(&chip->reg_lock);
975
976 status = azx_readl(chip, INTSTS);
977 if (status == 0) {
978 spin_unlock(&chip->reg_lock);
979 return IRQ_NONE;
980 }
981
Takashi Iwai07e4ca52005-08-24 14:14:57 +0200982 for (i = 0; i < chip->num_streams; i++) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700983 azx_dev = &chip->azx_dev[i];
984 if (status & azx_dev->sd_int_sta_mask) {
985 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
Takashi Iwai9ad593f2008-05-16 12:34:47 +0200986 if (!azx_dev->substream || !azx_dev->running)
987 continue;
Takashi Iwai675f25d2008-06-10 17:53:20 +0200988 /* ignore the first dummy IRQ (due to pos_adj) */
989 if (azx_dev->irq_ignore) {
990 azx_dev->irq_ignore = 0;
991 continue;
992 }
Takashi Iwai9ad593f2008-05-16 12:34:47 +0200993 /* check whether this IRQ is really acceptable */
994 if (azx_position_ok(chip, azx_dev)) {
995 azx_dev->irq_pending = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700996 spin_unlock(&chip->reg_lock);
997 snd_pcm_period_elapsed(azx_dev->substream);
998 spin_lock(&chip->reg_lock);
Takashi Iwai6acaed32009-01-12 10:09:24 +0100999 } else if (chip->bus && chip->bus->workq) {
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001000 /* bogus IRQ, process it later */
1001 azx_dev->irq_pending = 1;
Takashi Iwai6acaed32009-01-12 10:09:24 +01001002 queue_work(chip->bus->workq,
1003 &chip->irq_pending_work);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004 }
1005 }
1006 }
1007
1008 /* clear rirb int */
1009 status = azx_readb(chip, RIRBSTS);
1010 if (status & RIRB_INT_MASK) {
Takashi Iwaid01ce992007-07-27 16:52:19 +02001011 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001012 azx_update_rirb(chip);
1013 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1014 }
1015
1016#if 0
1017 /* clear state status int */
1018 if (azx_readb(chip, STATESTS) & 0x04)
1019 azx_writeb(chip, STATESTS, 0x04);
1020#endif
1021 spin_unlock(&chip->reg_lock);
1022
1023 return IRQ_HANDLED;
1024}
1025
1026
1027/*
Takashi Iwai675f25d2008-06-10 17:53:20 +02001028 * set up a BDL entry
1029 */
1030static int setup_bdle(struct snd_pcm_substream *substream,
1031 struct azx_dev *azx_dev, u32 **bdlp,
1032 int ofs, int size, int with_ioc)
1033{
Takashi Iwai675f25d2008-06-10 17:53:20 +02001034 u32 *bdl = *bdlp;
1035
1036 while (size > 0) {
1037 dma_addr_t addr;
1038 int chunk;
1039
1040 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1041 return -EINVAL;
1042
Takashi Iwai77a23f22008-08-21 13:00:13 +02001043 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
Takashi Iwai675f25d2008-06-10 17:53:20 +02001044 /* program the address field of the BDL entry */
1045 bdl[0] = cpu_to_le32((u32)addr);
Takashi Iwai766979e2008-06-13 20:53:56 +02001046 bdl[1] = cpu_to_le32(upper_32_bits(addr));
Takashi Iwai675f25d2008-06-10 17:53:20 +02001047 /* program the size field of the BDL entry */
Takashi Iwaifc4abee2008-07-30 15:13:34 +02001048 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
Takashi Iwai675f25d2008-06-10 17:53:20 +02001049 bdl[2] = cpu_to_le32(chunk);
1050 /* program the IOC to enable interrupt
1051 * only when the whole fragment is processed
1052 */
1053 size -= chunk;
1054 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1055 bdl += 4;
1056 azx_dev->frags++;
1057 ofs += chunk;
1058 }
1059 *bdlp = bdl;
1060 return ofs;
1061}
1062
1063/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001064 * set up BDL entries
1065 */
Takashi Iwai555e2192008-06-10 17:53:34 +02001066static int azx_setup_periods(struct azx *chip,
1067 struct snd_pcm_substream *substream,
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001068 struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001069{
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001070 u32 *bdl;
1071 int i, ofs, periods, period_bytes;
Takashi Iwai555e2192008-06-10 17:53:34 +02001072 int pos_adj;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001073
1074 /* reset BDL address */
1075 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1076 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1077
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001078 period_bytes = snd_pcm_lib_period_bytes(substream);
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001079 azx_dev->period_bytes = period_bytes;
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001080 periods = azx_dev->bufsize / period_bytes;
1081
Linus Torvalds1da177e2005-04-16 15:20:36 -07001082 /* program the initial BDL entries */
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001083 bdl = (u32 *)azx_dev->bdl.area;
1084 ofs = 0;
1085 azx_dev->frags = 0;
Takashi Iwai675f25d2008-06-10 17:53:20 +02001086 azx_dev->irq_ignore = 0;
Takashi Iwai555e2192008-06-10 17:53:34 +02001087 pos_adj = bdl_pos_adj[chip->dev_index];
1088 if (pos_adj > 0) {
Takashi Iwai675f25d2008-06-10 17:53:20 +02001089 struct snd_pcm_runtime *runtime = substream->runtime;
Takashi Iwaie785d3d2008-07-15 16:28:43 +02001090 int pos_align = pos_adj;
Takashi Iwai555e2192008-06-10 17:53:34 +02001091 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
Takashi Iwai675f25d2008-06-10 17:53:20 +02001092 if (!pos_adj)
Takashi Iwaie785d3d2008-07-15 16:28:43 +02001093 pos_adj = pos_align;
1094 else
1095 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1096 pos_align;
Takashi Iwai675f25d2008-06-10 17:53:20 +02001097 pos_adj = frames_to_bytes(runtime, pos_adj);
1098 if (pos_adj >= period_bytes) {
1099 snd_printk(KERN_WARNING "Too big adjustment %d\n",
Takashi Iwai555e2192008-06-10 17:53:34 +02001100 bdl_pos_adj[chip->dev_index]);
Takashi Iwai675f25d2008-06-10 17:53:20 +02001101 pos_adj = 0;
1102 } else {
1103 ofs = setup_bdle(substream, azx_dev,
1104 &bdl, ofs, pos_adj, 1);
1105 if (ofs < 0)
1106 goto error;
1107 azx_dev->irq_ignore = 1;
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001108 }
Takashi Iwai555e2192008-06-10 17:53:34 +02001109 } else
1110 pos_adj = 0;
Takashi Iwai675f25d2008-06-10 17:53:20 +02001111 for (i = 0; i < periods; i++) {
1112 if (i == periods - 1 && pos_adj)
1113 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1114 period_bytes - pos_adj, 0);
1115 else
1116 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1117 period_bytes, 1);
1118 if (ofs < 0)
1119 goto error;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120 }
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001121 return 0;
Takashi Iwai675f25d2008-06-10 17:53:20 +02001122
1123 error:
1124 snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
1125 azx_dev->bufsize, period_bytes);
1126 /* reset */
1127 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1128 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1129 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001130}
1131
1132/*
1133 * set up the SD for streaming
1134 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001135static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001136{
1137 unsigned char val;
1138 int timeout;
1139
1140 /* make sure the run bit is zero for SD */
Takashi Iwaid01ce992007-07-27 16:52:19 +02001141 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1142 ~SD_CTL_DMA_START);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001143 /* reset stream */
Takashi Iwaid01ce992007-07-27 16:52:19 +02001144 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1145 SD_CTL_STREAM_RESET);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001146 udelay(3);
1147 timeout = 300;
1148 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1149 --timeout)
1150 ;
1151 val &= ~SD_CTL_STREAM_RESET;
1152 azx_sd_writeb(azx_dev, SD_CTL, val);
1153 udelay(3);
1154
1155 timeout = 300;
1156 /* waiting for hardware to report that the stream is out of reset */
1157 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1158 --timeout)
1159 ;
1160
1161 /* program the stream_tag */
1162 azx_sd_writel(azx_dev, SD_CTL,
Takashi Iwaid01ce992007-07-27 16:52:19 +02001163 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
Linus Torvalds1da177e2005-04-16 15:20:36 -07001164 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1165
1166 /* program the length of samples in cyclic buffer */
1167 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1168
1169 /* program the stream format */
1170 /* this value needs to be the same as the one programmed */
1171 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1172
1173 /* program the stream LVI (last valid index) of the BDL */
1174 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1175
1176 /* program the BDL address */
1177 /* lower BDL address */
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001178 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179 /* upper BDL address */
Takashi Iwai766979e2008-06-13 20:53:56 +02001180 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001181
Takashi Iwai0be3b5d2005-09-05 17:11:40 +02001182 /* enable the position buffer */
Takashi Iwaiee9d6b92008-03-14 15:52:20 +01001183 if (chip->position_fix == POS_FIX_POSBUF ||
Joseph Chan0e153472008-08-26 14:38:03 +02001184 chip->position_fix == POS_FIX_AUTO ||
1185 chip->via_dmapos_patch) {
Takashi Iwaiee9d6b92008-03-14 15:52:20 +01001186 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1187 azx_writel(chip, DPLBASE,
1188 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1189 }
Takashi Iwaic74db862005-05-12 14:26:27 +02001190
Linus Torvalds1da177e2005-04-16 15:20:36 -07001191 /* set the interrupt enable bits in the descriptor control register */
Takashi Iwaid01ce992007-07-27 16:52:19 +02001192 azx_sd_writel(azx_dev, SD_CTL,
1193 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001194
1195 return 0;
1196}
1197
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001198/*
1199 * Probe the given codec address
1200 */
1201static int probe_codec(struct azx *chip, int addr)
1202{
1203 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1204 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1205 unsigned int res;
1206
1207 chip->probing = 1;
1208 azx_send_cmd(chip->bus, cmd);
1209 res = azx_get_response(chip->bus);
1210 chip->probing = 0;
1211 if (res == -1)
1212 return -EIO;
1213 snd_printdd("hda_intel: codec #%d probed OK\n", addr);
1214 return 0;
1215}
1216
Takashi Iwai33fa35e2008-11-06 16:50:40 +01001217static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1218 struct hda_pcm *cpcm);
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001219static void azx_stop_chip(struct azx *chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001220
1221/*
1222 * Codec initialization
1223 */
1224
Takashi Iwai2f5983f2008-09-03 16:00:44 +02001225/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1226static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
Kailang Yangf2690022008-05-27 11:44:55 +02001227 [AZX_DRIVER_TERA] = 1,
Takashi Iwaia9995a32007-03-12 21:30:46 +01001228};
1229
Takashi Iwai5aba4f82008-01-07 15:16:37 +01001230static int __devinit azx_codec_create(struct azx *chip, const char *model,
Takashi Iwaid4d9cd032008-12-19 15:19:11 +01001231 unsigned int codec_probe_mask,
1232 int no_init)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001233{
1234 struct hda_bus_template bus_temp;
Takashi Iwai34c25352008-10-28 11:38:58 +01001235 int c, codecs, err;
1236 int max_slots;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001237
1238 memset(&bus_temp, 0, sizeof(bus_temp));
1239 bus_temp.private_data = chip;
1240 bus_temp.modelname = model;
1241 bus_temp.pci = chip->pci;
Takashi Iwai111d3af2006-02-16 18:17:58 +01001242 bus_temp.ops.command = azx_send_cmd;
1243 bus_temp.ops.get_response = azx_get_response;
Takashi Iwai176d5332008-07-30 15:01:44 +02001244 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
Takashi Iwaicb53c622007-08-10 17:21:45 +02001245#ifdef CONFIG_SND_HDA_POWER_SAVE
Takashi Iwai11cd41b2008-11-28 07:22:18 +01001246 bus_temp.power_save = &power_save;
Takashi Iwaicb53c622007-08-10 17:21:45 +02001247 bus_temp.ops.pm_notify = azx_power_notify;
1248#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001249
Takashi Iwaid01ce992007-07-27 16:52:19 +02001250 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1251 if (err < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001252 return err;
1253
Wei Nidc9c8e22008-09-26 13:55:56 +08001254 if (chip->driver_type == AZX_DRIVER_NVIDIA)
1255 chip->bus->needs_damn_long_delay = 1;
1256
Takashi Iwai34c25352008-10-28 11:38:58 +01001257 codecs = 0;
Takashi Iwai2f5983f2008-09-03 16:00:44 +02001258 max_slots = azx_max_codecs[chip->driver_type];
1259 if (!max_slots)
1260 max_slots = AZX_MAX_CODECS;
Takashi Iwai6ce4a3b2008-11-06 17:11:10 +01001261
1262 /* First try to probe all given codec slots */
1263 for (c = 0; c < max_slots; c++) {
1264 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1265 if (probe_codec(chip, c) < 0) {
1266 /* Some BIOSen give you wrong codec addresses
1267 * that don't exist
1268 */
1269 snd_printk(KERN_WARNING
1270 "hda_intel: Codec #%d probe error; "
1271 "disabling it...\n", c);
1272 chip->codec_mask &= ~(1 << c);
1273 /* More badly, accessing to a non-existing
1274 * codec often screws up the controller chip,
1275 * and distrubs the further communications.
1276 * Thus if an error occurs during probing,
1277 * better to reset the controller chip to
1278 * get back to the sanity state.
1279 */
1280 azx_stop_chip(chip);
1281 azx_init_chip(chip);
1282 }
1283 }
1284 }
1285
1286 /* Then create codec instances */
Takashi Iwai34c25352008-10-28 11:38:58 +01001287 for (c = 0; c < max_slots; c++) {
Takashi Iwai5aba4f82008-01-07 15:16:37 +01001288 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
Takashi Iwaibccad142007-04-24 12:23:53 +02001289 struct hda_codec *codec;
Takashi Iwaid4d9cd032008-12-19 15:19:11 +01001290 err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001291 if (err < 0)
1292 continue;
1293 codecs++;
Takashi Iwai19a982b2007-03-21 15:14:35 +01001294 }
1295 }
1296 if (!codecs) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001297 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1298 return -ENXIO;
1299 }
1300
1301 return 0;
1302}
1303
1304
1305/*
1306 * PCM support
1307 */
1308
1309/* assign a stream for the PCM */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001310static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001311{
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001312 int dev, i, nums;
1313 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1314 dev = chip->playback_index_offset;
1315 nums = chip->playback_streams;
1316 } else {
1317 dev = chip->capture_index_offset;
1318 nums = chip->capture_streams;
1319 }
1320 for (i = 0; i < nums; i++, dev++)
Takashi Iwaid01ce992007-07-27 16:52:19 +02001321 if (!chip->azx_dev[dev].opened) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001322 chip->azx_dev[dev].opened = 1;
1323 return &chip->azx_dev[dev];
1324 }
1325 return NULL;
1326}
1327
1328/* release the assigned stream */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001329static inline void azx_release_device(struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001330{
1331 azx_dev->opened = 0;
1332}
1333
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001334static struct snd_pcm_hardware azx_pcm_hw = {
Takashi Iwaid01ce992007-07-27 16:52:19 +02001335 .info = (SNDRV_PCM_INFO_MMAP |
1336 SNDRV_PCM_INFO_INTERLEAVED |
Linus Torvalds1da177e2005-04-16 15:20:36 -07001337 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1338 SNDRV_PCM_INFO_MMAP_VALID |
Pavel Machek927fc862006-08-31 17:03:43 +02001339 /* No full-resume yet implemented */
1340 /* SNDRV_PCM_INFO_RESUME |*/
Takashi Iwai850f0e52008-03-18 17:11:05 +01001341 SNDRV_PCM_INFO_PAUSE |
1342 SNDRV_PCM_INFO_SYNC_START),
Linus Torvalds1da177e2005-04-16 15:20:36 -07001343 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1344 .rates = SNDRV_PCM_RATE_48000,
1345 .rate_min = 48000,
1346 .rate_max = 48000,
1347 .channels_min = 2,
1348 .channels_max = 2,
1349 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1350 .period_bytes_min = 128,
1351 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1352 .periods_min = 2,
1353 .periods_max = AZX_MAX_FRAG,
1354 .fifo_size = 0,
1355};
1356
1357struct azx_pcm {
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001358 struct azx *chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001359 struct hda_codec *codec;
1360 struct hda_pcm_stream *hinfo[2];
1361};
1362
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001363static int azx_pcm_open(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001364{
1365 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1366 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001367 struct azx *chip = apcm->chip;
1368 struct azx_dev *azx_dev;
1369 struct snd_pcm_runtime *runtime = substream->runtime;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370 unsigned long flags;
1371 int err;
1372
Ingo Molnar62932df2006-01-16 16:34:20 +01001373 mutex_lock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001374 azx_dev = azx_assign_device(chip, substream->stream);
1375 if (azx_dev == NULL) {
Ingo Molnar62932df2006-01-16 16:34:20 +01001376 mutex_unlock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001377 return -EBUSY;
1378 }
1379 runtime->hw = azx_pcm_hw;
1380 runtime->hw.channels_min = hinfo->channels_min;
1381 runtime->hw.channels_max = hinfo->channels_max;
1382 runtime->hw.formats = hinfo->formats;
1383 runtime->hw.rates = hinfo->rates;
1384 snd_pcm_limit_hw_rates(runtime);
1385 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
Joachim Deguara5f1545b2007-03-16 15:01:36 +01001386 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1387 128);
1388 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1389 128);
Takashi Iwaicb53c622007-08-10 17:21:45 +02001390 snd_hda_power_up(apcm->codec);
Takashi Iwaid01ce992007-07-27 16:52:19 +02001391 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1392 if (err < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001393 azx_release_device(azx_dev);
Takashi Iwaicb53c622007-08-10 17:21:45 +02001394 snd_hda_power_down(apcm->codec);
Ingo Molnar62932df2006-01-16 16:34:20 +01001395 mutex_unlock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001396 return err;
1397 }
1398 spin_lock_irqsave(&chip->reg_lock, flags);
1399 azx_dev->substream = substream;
1400 azx_dev->running = 0;
1401 spin_unlock_irqrestore(&chip->reg_lock, flags);
1402
1403 runtime->private_data = azx_dev;
Takashi Iwai850f0e52008-03-18 17:11:05 +01001404 snd_pcm_set_sync(substream);
Ingo Molnar62932df2006-01-16 16:34:20 +01001405 mutex_unlock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001406 return 0;
1407}
1408
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001409static int azx_pcm_close(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001410{
1411 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1412 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001413 struct azx *chip = apcm->chip;
1414 struct azx_dev *azx_dev = get_azx_dev(substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001415 unsigned long flags;
1416
Ingo Molnar62932df2006-01-16 16:34:20 +01001417 mutex_lock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001418 spin_lock_irqsave(&chip->reg_lock, flags);
1419 azx_dev->substream = NULL;
1420 azx_dev->running = 0;
1421 spin_unlock_irqrestore(&chip->reg_lock, flags);
1422 azx_release_device(azx_dev);
1423 hinfo->ops.close(hinfo, apcm->codec, substream);
Takashi Iwaicb53c622007-08-10 17:21:45 +02001424 snd_hda_power_down(apcm->codec);
Ingo Molnar62932df2006-01-16 16:34:20 +01001425 mutex_unlock(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001426 return 0;
1427}
1428
Takashi Iwaid01ce992007-07-27 16:52:19 +02001429static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1430 struct snd_pcm_hw_params *hw_params)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001431{
Takashi Iwaid01ce992007-07-27 16:52:19 +02001432 return snd_pcm_lib_malloc_pages(substream,
1433 params_buffer_bytes(hw_params));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001434}
1435
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001436static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001437{
1438 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001439 struct azx_dev *azx_dev = get_azx_dev(substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001440 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1441
1442 /* reset BDL address */
1443 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1444 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1445 azx_sd_writel(azx_dev, SD_CTL, 0);
1446
1447 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1448
1449 return snd_pcm_lib_free_pages(substream);
1450}
1451
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001452static int azx_pcm_prepare(struct snd_pcm_substream *substream)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001453{
1454 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001455 struct azx *chip = apcm->chip;
1456 struct azx_dev *azx_dev = get_azx_dev(substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001457 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001458 struct snd_pcm_runtime *runtime = substream->runtime;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001459
1460 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001461 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1462 runtime->channels,
1463 runtime->format,
1464 hinfo->maxbps);
Takashi Iwaid01ce992007-07-27 16:52:19 +02001465 if (!azx_dev->format_val) {
1466 snd_printk(KERN_ERR SFX
1467 "invalid format_val, rate=%d, ch=%d, format=%d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001468 runtime->rate, runtime->channels, runtime->format);
1469 return -EINVAL;
1470 }
1471
Takashi Iwai21c7b082008-02-07 12:06:32 +01001472 snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1473 azx_dev->bufsize, azx_dev->format_val);
Takashi Iwai555e2192008-06-10 17:53:34 +02001474 if (azx_setup_periods(chip, substream, azx_dev) < 0)
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001475 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001476 azx_setup_controller(chip, azx_dev);
1477 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1478 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1479 else
1480 azx_dev->fifo_size = 0;
1481
1482 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1483 azx_dev->format_val, substream);
1484}
1485
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001486static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001487{
1488 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001489 struct azx *chip = apcm->chip;
Takashi Iwai850f0e52008-03-18 17:11:05 +01001490 struct azx_dev *azx_dev;
1491 struct snd_pcm_substream *s;
1492 int start, nsync = 0, sbits = 0;
1493 int nwait, timeout;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001494
Linus Torvalds1da177e2005-04-16 15:20:36 -07001495 switch (cmd) {
1496 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1497 case SNDRV_PCM_TRIGGER_RESUME:
1498 case SNDRV_PCM_TRIGGER_START:
Takashi Iwai850f0e52008-03-18 17:11:05 +01001499 start = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001500 break;
1501 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Jaroslav Kysela47123192005-08-15 20:53:07 +02001502 case SNDRV_PCM_TRIGGER_SUSPEND:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001503 case SNDRV_PCM_TRIGGER_STOP:
Takashi Iwai850f0e52008-03-18 17:11:05 +01001504 start = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001505 break;
1506 default:
Takashi Iwai850f0e52008-03-18 17:11:05 +01001507 return -EINVAL;
1508 }
1509
1510 snd_pcm_group_for_each_entry(s, substream) {
1511 if (s->pcm->card != substream->pcm->card)
1512 continue;
1513 azx_dev = get_azx_dev(s);
1514 sbits |= 1 << azx_dev->index;
1515 nsync++;
1516 snd_pcm_trigger_done(s, substream);
1517 }
1518
1519 spin_lock(&chip->reg_lock);
1520 if (nsync > 1) {
1521 /* first, set SYNC bits of corresponding streams */
1522 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1523 }
1524 snd_pcm_group_for_each_entry(s, substream) {
1525 if (s->pcm->card != substream->pcm->card)
1526 continue;
1527 azx_dev = get_azx_dev(s);
1528 if (start)
1529 azx_stream_start(chip, azx_dev);
1530 else
1531 azx_stream_stop(chip, azx_dev);
1532 azx_dev->running = start;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001533 }
1534 spin_unlock(&chip->reg_lock);
Takashi Iwai850f0e52008-03-18 17:11:05 +01001535 if (start) {
1536 if (nsync == 1)
1537 return 0;
1538 /* wait until all FIFOs get ready */
1539 for (timeout = 5000; timeout; timeout--) {
1540 nwait = 0;
1541 snd_pcm_group_for_each_entry(s, substream) {
1542 if (s->pcm->card != substream->pcm->card)
1543 continue;
1544 azx_dev = get_azx_dev(s);
1545 if (!(azx_sd_readb(azx_dev, SD_STS) &
1546 SD_STS_FIFO_READY))
1547 nwait++;
1548 }
1549 if (!nwait)
1550 break;
1551 cpu_relax();
1552 }
1553 } else {
1554 /* wait until all RUN bits are cleared */
1555 for (timeout = 5000; timeout; timeout--) {
1556 nwait = 0;
1557 snd_pcm_group_for_each_entry(s, substream) {
1558 if (s->pcm->card != substream->pcm->card)
1559 continue;
1560 azx_dev = get_azx_dev(s);
1561 if (azx_sd_readb(azx_dev, SD_CTL) &
1562 SD_CTL_DMA_START)
1563 nwait++;
1564 }
1565 if (!nwait)
1566 break;
1567 cpu_relax();
1568 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001569 }
Takashi Iwai850f0e52008-03-18 17:11:05 +01001570 if (nsync > 1) {
1571 spin_lock(&chip->reg_lock);
1572 /* reset SYNC bits */
1573 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1574 spin_unlock(&chip->reg_lock);
1575 }
1576 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001577}
1578
Joseph Chan0e153472008-08-26 14:38:03 +02001579/* get the current DMA position with correction on VIA chips */
1580static unsigned int azx_via_get_position(struct azx *chip,
1581 struct azx_dev *azx_dev)
1582{
1583 unsigned int link_pos, mini_pos, bound_pos;
1584 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1585 unsigned int fifo_size;
1586
1587 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1588 if (azx_dev->index >= 4) {
1589 /* Playback, no problem using link position */
1590 return link_pos;
1591 }
1592
1593 /* Capture */
1594 /* For new chipset,
1595 * use mod to get the DMA position just like old chipset
1596 */
1597 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1598 mod_dma_pos %= azx_dev->period_bytes;
1599
1600 /* azx_dev->fifo_size can't get FIFO size of in stream.
1601 * Get from base address + offset.
1602 */
1603 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1604
1605 if (azx_dev->insufficient) {
1606 /* Link position never gather than FIFO size */
1607 if (link_pos <= fifo_size)
1608 return 0;
1609
1610 azx_dev->insufficient = 0;
1611 }
1612
1613 if (link_pos <= fifo_size)
1614 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1615 else
1616 mini_pos = link_pos - fifo_size;
1617
1618 /* Find nearest previous boudary */
1619 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1620 mod_link_pos = link_pos % azx_dev->period_bytes;
1621 if (mod_link_pos >= fifo_size)
1622 bound_pos = link_pos - mod_link_pos;
1623 else if (mod_dma_pos >= mod_mini_pos)
1624 bound_pos = mini_pos - mod_mini_pos;
1625 else {
1626 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1627 if (bound_pos >= azx_dev->bufsize)
1628 bound_pos = 0;
1629 }
1630
1631 /* Calculate real DMA position we want */
1632 return bound_pos + mod_dma_pos;
1633}
1634
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001635static unsigned int azx_get_position(struct azx *chip,
1636 struct azx_dev *azx_dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001637{
Linus Torvalds1da177e2005-04-16 15:20:36 -07001638 unsigned int pos;
1639
Joseph Chan0e153472008-08-26 14:38:03 +02001640 if (chip->via_dmapos_patch)
1641 pos = azx_via_get_position(chip, azx_dev);
1642 else if (chip->position_fix == POS_FIX_POSBUF ||
1643 chip->position_fix == POS_FIX_AUTO) {
Takashi Iwaic74db862005-05-12 14:26:27 +02001644 /* use the position buffer */
Takashi Iwai929861c2006-08-31 16:55:40 +02001645 pos = le32_to_cpu(*azx_dev->posbuf);
Takashi Iwaic74db862005-05-12 14:26:27 +02001646 } else {
1647 /* read LPIB */
1648 pos = azx_sd_readl(azx_dev, SD_LPIB);
Takashi Iwaic74db862005-05-12 14:26:27 +02001649 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001650 if (pos >= azx_dev->bufsize)
1651 pos = 0;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001652 return pos;
1653}
1654
1655static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1656{
1657 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1658 struct azx *chip = apcm->chip;
1659 struct azx_dev *azx_dev = get_azx_dev(substream);
1660 return bytes_to_frames(substream->runtime,
1661 azx_get_position(chip, azx_dev));
1662}
1663
1664/*
1665 * Check whether the current DMA position is acceptable for updating
1666 * periods. Returns non-zero if it's OK.
1667 *
1668 * Many HD-audio controllers appear pretty inaccurate about
1669 * the update-IRQ timing. The IRQ is issued before actually the
1670 * data is processed. So, we need to process it afterwords in a
1671 * workqueue.
1672 */
1673static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1674{
1675 unsigned int pos;
1676
1677 pos = azx_get_position(chip, azx_dev);
1678 if (chip->position_fix == POS_FIX_AUTO) {
1679 if (!pos) {
1680 printk(KERN_WARNING
1681 "hda-intel: Invalid position buffer, "
1682 "using LPIB read method instead.\n");
Takashi Iwaid2e1c972008-06-10 17:53:34 +02001683 chip->position_fix = POS_FIX_LPIB;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001684 pos = azx_get_position(chip, azx_dev);
1685 } else
1686 chip->position_fix = POS_FIX_POSBUF;
1687 }
1688
Takashi Iwaia62741c2008-08-18 17:11:09 +02001689 if (!bdl_pos_adj[chip->dev_index])
1690 return 1; /* no delayed ack */
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001691 if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1692 return 0; /* NG - it's below the period boundary */
1693 return 1; /* OK, it's fine */
1694}
1695
1696/*
1697 * The work for pending PCM period updates.
1698 */
1699static void azx_irq_pending_work(struct work_struct *work)
1700{
1701 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1702 int i, pending;
1703
Takashi Iwaia6a950a2008-06-10 17:53:35 +02001704 if (!chip->irq_pending_warned) {
1705 printk(KERN_WARNING
1706 "hda-intel: IRQ timing workaround is activated "
1707 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1708 chip->card->number);
1709 chip->irq_pending_warned = 1;
1710 }
1711
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001712 for (;;) {
1713 pending = 0;
1714 spin_lock_irq(&chip->reg_lock);
1715 for (i = 0; i < chip->num_streams; i++) {
1716 struct azx_dev *azx_dev = &chip->azx_dev[i];
1717 if (!azx_dev->irq_pending ||
1718 !azx_dev->substream ||
1719 !azx_dev->running)
1720 continue;
1721 if (azx_position_ok(chip, azx_dev)) {
1722 azx_dev->irq_pending = 0;
1723 spin_unlock(&chip->reg_lock);
1724 snd_pcm_period_elapsed(azx_dev->substream);
1725 spin_lock(&chip->reg_lock);
1726 } else
1727 pending++;
1728 }
1729 spin_unlock_irq(&chip->reg_lock);
1730 if (!pending)
1731 return;
1732 cond_resched();
1733 }
1734}
1735
1736/* clear irq_pending flags and assure no on-going workq */
1737static void azx_clear_irq_pending(struct azx *chip)
1738{
1739 int i;
1740
1741 spin_lock_irq(&chip->reg_lock);
1742 for (i = 0; i < chip->num_streams; i++)
1743 chip->azx_dev[i].irq_pending = 0;
1744 spin_unlock_irq(&chip->reg_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001745}
1746
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001747static struct snd_pcm_ops azx_pcm_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001748 .open = azx_pcm_open,
1749 .close = azx_pcm_close,
1750 .ioctl = snd_pcm_lib_ioctl,
1751 .hw_params = azx_pcm_hw_params,
1752 .hw_free = azx_pcm_hw_free,
1753 .prepare = azx_pcm_prepare,
1754 .trigger = azx_pcm_trigger,
1755 .pointer = azx_pcm_pointer,
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001756 .page = snd_pcm_sgbuf_ops_page,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001757};
1758
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001759static void azx_pcm_free(struct snd_pcm *pcm)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001760{
Takashi Iwai176d5332008-07-30 15:01:44 +02001761 struct azx_pcm *apcm = pcm->private_data;
1762 if (apcm) {
1763 apcm->chip->pcm[pcm->device] = NULL;
1764 kfree(apcm);
1765 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001766}
1767
Takashi Iwai176d5332008-07-30 15:01:44 +02001768static int
Takashi Iwai33fa35e2008-11-06 16:50:40 +01001769azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1770 struct hda_pcm *cpcm)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001771{
Takashi Iwai33fa35e2008-11-06 16:50:40 +01001772 struct azx *chip = bus->private_data;
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001773 struct snd_pcm *pcm;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001774 struct azx_pcm *apcm;
Takashi Iwai176d5332008-07-30 15:01:44 +02001775 int pcm_dev = cpcm->device;
1776 int s, err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001777
Takashi Iwai176d5332008-07-30 15:01:44 +02001778 if (pcm_dev >= AZX_MAX_PCMS) {
1779 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1780 pcm_dev);
Takashi Iwaida3cec32008-08-08 17:12:14 +02001781 return -EINVAL;
Takashi Iwai176d5332008-07-30 15:01:44 +02001782 }
1783 if (chip->pcm[pcm_dev]) {
1784 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1785 return -EBUSY;
1786 }
1787 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1788 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1789 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001790 &pcm);
1791 if (err < 0)
1792 return err;
1793 strcpy(pcm->name, cpcm->name);
Takashi Iwai176d5332008-07-30 15:01:44 +02001794 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001795 if (apcm == NULL)
1796 return -ENOMEM;
1797 apcm->chip = chip;
1798 apcm->codec = codec;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001799 pcm->private_data = apcm;
1800 pcm->private_free = azx_pcm_free;
Takashi Iwai176d5332008-07-30 15:01:44 +02001801 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1802 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1803 chip->pcm[pcm_dev] = pcm;
1804 cpcm->pcm = pcm;
1805 for (s = 0; s < 2; s++) {
1806 apcm->hinfo[s] = &cpcm->stream[s];
1807 if (cpcm->stream[s].substreams)
1808 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1809 }
1810 /* buffer pre-allocation */
Takashi Iwai4ce107b2008-02-06 14:50:19 +01001811 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001812 snd_dma_pci_data(chip->pci),
Takashi Iwaifc4abee2008-07-30 15:13:34 +02001813 1024 * 64, 32 * 1024 * 1024);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001814 return 0;
1815}
1816
1817/*
1818 * mixer creation - all stuff is implemented in hda module
1819 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001820static int __devinit azx_mixer_create(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001821{
1822 return snd_hda_build_controls(chip->bus);
1823}
1824
1825
1826/*
1827 * initialize SD streams
1828 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001829static int __devinit azx_init_stream(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001830{
1831 int i;
1832
1833 /* initialize each stream (aka device)
Takashi Iwaid01ce992007-07-27 16:52:19 +02001834 * assign the starting bdl address to each stream (device)
1835 * and initialize
Linus Torvalds1da177e2005-04-16 15:20:36 -07001836 */
Takashi Iwai07e4ca52005-08-24 14:14:57 +02001837 for (i = 0; i < chip->num_streams; i++) {
Takashi Iwaia98f90f2005-11-17 14:59:02 +01001838 struct azx_dev *azx_dev = &chip->azx_dev[i];
Takashi Iwai929861c2006-08-31 16:55:40 +02001839 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001840 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1841 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1842 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1843 azx_dev->sd_int_sta_mask = 1 << i;
1844 /* stream tag: must be non-zero and unique */
1845 azx_dev->index = i;
1846 azx_dev->stream_tag = i + 1;
1847 }
1848
1849 return 0;
1850}
1851
Takashi Iwai68e7fff2006-10-23 13:40:59 +02001852static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1853{
Takashi Iwai437a5a42006-11-21 12:14:23 +01001854 if (request_irq(chip->pci->irq, azx_interrupt,
1855 chip->msi ? 0 : IRQF_SHARED,
Takashi Iwai68e7fff2006-10-23 13:40:59 +02001856 "HDA Intel", chip)) {
1857 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1858 "disabling device\n", chip->pci->irq);
1859 if (do_disconnect)
1860 snd_card_disconnect(chip->card);
1861 return -1;
1862 }
1863 chip->irq = chip->pci->irq;
Takashi Iwai69e13412006-11-21 12:10:55 +01001864 pci_intx(chip->pci, !chip->msi);
Takashi Iwai68e7fff2006-10-23 13:40:59 +02001865 return 0;
1866}
1867
Linus Torvalds1da177e2005-04-16 15:20:36 -07001868
Takashi Iwaicb53c622007-08-10 17:21:45 +02001869static void azx_stop_chip(struct azx *chip)
1870{
Takashi Iwai95e99fd2007-08-13 15:29:04 +02001871 if (!chip->initialized)
Takashi Iwaicb53c622007-08-10 17:21:45 +02001872 return;
1873
1874 /* disable interrupts */
1875 azx_int_disable(chip);
1876 azx_int_clear(chip);
1877
1878 /* disable CORB/RIRB */
1879 azx_free_cmd_io(chip);
1880
1881 /* disable position buffer */
1882 azx_writel(chip, DPLBASE, 0);
1883 azx_writel(chip, DPUBASE, 0);
1884
1885 chip->initialized = 0;
1886}
1887
1888#ifdef CONFIG_SND_HDA_POWER_SAVE
1889/* power-up/down the controller */
Takashi Iwai33fa35e2008-11-06 16:50:40 +01001890static void azx_power_notify(struct hda_bus *bus)
Takashi Iwaicb53c622007-08-10 17:21:45 +02001891{
Takashi Iwai33fa35e2008-11-06 16:50:40 +01001892 struct azx *chip = bus->private_data;
Takashi Iwaicb53c622007-08-10 17:21:45 +02001893 struct hda_codec *c;
1894 int power_on = 0;
1895
Takashi Iwai33fa35e2008-11-06 16:50:40 +01001896 list_for_each_entry(c, &bus->codec_list, list) {
Takashi Iwaicb53c622007-08-10 17:21:45 +02001897 if (c->power_on) {
1898 power_on = 1;
1899 break;
1900 }
1901 }
1902 if (power_on)
1903 azx_init_chip(chip);
Takashi Iwaidee1b662007-08-13 16:10:30 +02001904 else if (chip->running && power_save_controller)
Takashi Iwaicb53c622007-08-10 17:21:45 +02001905 azx_stop_chip(chip);
Takashi Iwaicb53c622007-08-10 17:21:45 +02001906}
Takashi Iwai5c0b9be2008-12-11 11:47:17 +01001907#endif /* CONFIG_SND_HDA_POWER_SAVE */
1908
1909#ifdef CONFIG_PM
1910/*
1911 * power management
1912 */
Takashi Iwai986862bd2008-11-27 12:40:13 +01001913
1914static int snd_hda_codecs_inuse(struct hda_bus *bus)
1915{
1916 struct hda_codec *codec;
1917
1918 list_for_each_entry(codec, &bus->codec_list, list) {
1919 if (snd_hda_codec_needs_resume(codec))
1920 return 1;
1921 }
1922 return 0;
1923}
Takashi Iwaicb53c622007-08-10 17:21:45 +02001924
Takashi Iwai421a1252005-11-17 16:11:09 +01001925static int azx_suspend(struct pci_dev *pci, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001926{
Takashi Iwai421a1252005-11-17 16:11:09 +01001927 struct snd_card *card = pci_get_drvdata(pci);
1928 struct azx *chip = card->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001929 int i;
1930
Takashi Iwai421a1252005-11-17 16:11:09 +01001931 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
Takashi Iwai9ad593f2008-05-16 12:34:47 +02001932 azx_clear_irq_pending(chip);
Takashi Iwai7ba72ba2008-02-06 14:03:20 +01001933 for (i = 0; i < AZX_MAX_PCMS; i++)
Takashi Iwai421a1252005-11-17 16:11:09 +01001934 snd_pcm_suspend_all(chip->pcm[i]);
Takashi Iwai0b7a2e92007-08-14 15:18:26 +02001935 if (chip->initialized)
1936 snd_hda_suspend(chip->bus, state);
Takashi Iwaicb53c622007-08-10 17:21:45 +02001937 azx_stop_chip(chip);
Takashi Iwai30b35392006-10-11 18:52:53 +02001938 if (chip->irq >= 0) {
Takashi Iwai43001c92006-09-08 12:30:03 +02001939 free_irq(chip->irq, chip);
Takashi Iwai30b35392006-10-11 18:52:53 +02001940 chip->irq = -1;
1941 }
Takashi Iwai68e7fff2006-10-23 13:40:59 +02001942 if (chip->msi)
Takashi Iwai43001c92006-09-08 12:30:03 +02001943 pci_disable_msi(chip->pci);
Takashi Iwai421a1252005-11-17 16:11:09 +01001944 pci_disable_device(pci);
1945 pci_save_state(pci);
Takashi Iwai30b35392006-10-11 18:52:53 +02001946 pci_set_power_state(pci, pci_choose_state(pci, state));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001947 return 0;
1948}
1949
Rafael J. Wysocki32e176c2008-12-06 15:09:08 +01001950static int azx_resume_early(struct pci_dev *pci)
1951{
1952 return pci_restore_state(pci);
1953}
1954
Takashi Iwai421a1252005-11-17 16:11:09 +01001955static int azx_resume(struct pci_dev *pci)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001956{
Takashi Iwai421a1252005-11-17 16:11:09 +01001957 struct snd_card *card = pci_get_drvdata(pci);
1958 struct azx *chip = card->private_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001959
Takashi Iwai30b35392006-10-11 18:52:53 +02001960 if (pci_enable_device(pci) < 0) {
1961 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1962 "disabling device\n");
1963 snd_card_disconnect(card);
1964 return -EIO;
1965 }
1966 pci_set_master(pci);
Takashi Iwai68e7fff2006-10-23 13:40:59 +02001967 if (chip->msi)
1968 if (pci_enable_msi(pci) < 0)
1969 chip->msi = 0;
1970 if (azx_acquire_irq(chip, 1) < 0)
Takashi Iwai30b35392006-10-11 18:52:53 +02001971 return -EIO;
Takashi Iwaicb53c622007-08-10 17:21:45 +02001972 azx_init_pci(chip);
Maxim Levitskyd804ad92007-09-03 15:28:04 +02001973
1974 if (snd_hda_codecs_inuse(chip->bus))
1975 azx_init_chip(chip);
1976
Linus Torvalds1da177e2005-04-16 15:20:36 -07001977 snd_hda_resume(chip->bus);
Takashi Iwai421a1252005-11-17 16:11:09 +01001978 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001979 return 0;
1980}
1981#endif /* CONFIG_PM */
1982
1983
1984/*
Takashi Iwai0cbf0092008-10-29 16:18:25 +01001985 * reboot notifier for hang-up problem at power-down
1986 */
1987static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
1988{
1989 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
1990 azx_stop_chip(chip);
1991 return NOTIFY_OK;
1992}
1993
1994static void azx_notifier_register(struct azx *chip)
1995{
1996 chip->reboot_notifier.notifier_call = azx_halt;
1997 register_reboot_notifier(&chip->reboot_notifier);
1998}
1999
2000static void azx_notifier_unregister(struct azx *chip)
2001{
2002 if (chip->reboot_notifier.notifier_call)
2003 unregister_reboot_notifier(&chip->reboot_notifier);
2004}
2005
2006/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002007 * destructor
2008 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002009static int azx_free(struct azx *chip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002010{
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002011 int i;
2012
Takashi Iwai0cbf0092008-10-29 16:18:25 +01002013 azx_notifier_unregister(chip);
2014
Takashi Iwaice43fba2005-05-30 20:33:44 +02002015 if (chip->initialized) {
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002016 azx_clear_irq_pending(chip);
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002017 for (i = 0; i < chip->num_streams; i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002018 azx_stream_stop(chip, &chip->azx_dev[i]);
Takashi Iwaicb53c622007-08-10 17:21:45 +02002019 azx_stop_chip(chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002020 }
2021
Jeff Garzikf000fd82008-04-22 13:50:34 +02002022 if (chip->irq >= 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002023 free_irq(chip->irq, (void*)chip);
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002024 if (chip->msi)
Takashi Iwai30b35392006-10-11 18:52:53 +02002025 pci_disable_msi(chip->pci);
Takashi Iwaif079c252006-06-01 11:42:14 +02002026 if (chip->remap_addr)
2027 iounmap(chip->remap_addr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002028
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002029 if (chip->azx_dev) {
2030 for (i = 0; i < chip->num_streams; i++)
2031 if (chip->azx_dev[i].bdl.area)
2032 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2033 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002034 if (chip->rb.area)
2035 snd_dma_free_pages(&chip->rb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002036 if (chip->posbuf.area)
2037 snd_dma_free_pages(&chip->posbuf);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002038 pci_release_regions(chip->pci);
2039 pci_disable_device(chip->pci);
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002040 kfree(chip->azx_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002041 kfree(chip);
2042
2043 return 0;
2044}
2045
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002046static int azx_dev_free(struct snd_device *device)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002047{
2048 return azx_free(device->device_data);
2049}
2050
2051/*
Takashi Iwai3372a152007-02-01 15:46:50 +01002052 * white/black-listing for position_fix
2053 */
Ralf Baechle623ec042007-03-13 15:29:47 +01002054static struct snd_pci_quirk position_fix_list[] __devinitdata = {
Takashi Iwaid2e1c972008-06-10 17:53:34 +02002055 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2056 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2057 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
Takashi Iwai3372a152007-02-01 15:46:50 +01002058 {}
2059};
2060
2061static int __devinit check_position_fix(struct azx *chip, int fix)
2062{
2063 const struct snd_pci_quirk *q;
2064
Joseph Chan0e153472008-08-26 14:38:03 +02002065 /* Check VIA HD Audio Controller exist */
2066 if (chip->pci->vendor == PCI_VENDOR_ID_VIA &&
2067 chip->pci->device == VIA_HDAC_DEVICE_ID) {
2068 chip->via_dmapos_patch = 1;
2069 /* Use link position directly, avoid any transfer problem. */
2070 return POS_FIX_LPIB;
2071 }
2072 chip->via_dmapos_patch = 0;
2073
Takashi Iwai3372a152007-02-01 15:46:50 +01002074 if (fix == POS_FIX_AUTO) {
2075 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2076 if (q) {
Takashi Iwai669ba272007-08-17 09:17:36 +02002077 printk(KERN_INFO
Takashi Iwai3372a152007-02-01 15:46:50 +01002078 "hda_intel: position_fix set to %d "
2079 "for device %04x:%04x\n",
2080 q->value, q->subvendor, q->subdevice);
2081 return q->value;
2082 }
2083 }
2084 return fix;
2085}
2086
2087/*
Takashi Iwai669ba272007-08-17 09:17:36 +02002088 * black-lists for probe_mask
2089 */
2090static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2091 /* Thinkpad often breaks the controller communication when accessing
2092 * to the non-working (or non-existing) modem codec slot.
2093 */
2094 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2095 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2096 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
Takashi Iwai0edb9452008-11-07 14:53:09 +01002097 /* broken BIOS */
2098 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
Takashi Iwaief1681d2008-11-24 17:29:28 +01002099 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2100 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
Takashi Iwai669ba272007-08-17 09:17:36 +02002101 {}
2102};
2103
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002104static void __devinit check_probe_mask(struct azx *chip, int dev)
Takashi Iwai669ba272007-08-17 09:17:36 +02002105{
2106 const struct snd_pci_quirk *q;
2107
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002108 if (probe_mask[dev] == -1) {
Takashi Iwai669ba272007-08-17 09:17:36 +02002109 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2110 if (q) {
2111 printk(KERN_INFO
2112 "hda_intel: probe_mask set to 0x%x "
2113 "for device %04x:%04x\n",
2114 q->value, q->subvendor, q->subdevice);
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002115 probe_mask[dev] = q->value;
Takashi Iwai669ba272007-08-17 09:17:36 +02002116 }
2117 }
2118}
2119
2120
2121/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002122 * constructor
2123 */
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002124static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002125 int dev, int driver_type,
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002126 struct azx **rchip)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002127{
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002128 struct azx *chip;
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002129 int i, err;
Tobin Davisbcd72002008-01-15 11:23:55 +01002130 unsigned short gcap;
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002131 static struct snd_device_ops ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002132 .dev_free = azx_dev_free,
2133 };
2134
2135 *rchip = NULL;
Tobin Davisbcd72002008-01-15 11:23:55 +01002136
Pavel Machek927fc862006-08-31 17:03:43 +02002137 err = pci_enable_device(pci);
2138 if (err < 0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002139 return err;
2140
Takashi Iwaie560d8d2005-09-09 14:21:46 +02002141 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
Pavel Machek927fc862006-08-31 17:03:43 +02002142 if (!chip) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002143 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2144 pci_disable_device(pci);
2145 return -ENOMEM;
2146 }
2147
2148 spin_lock_init(&chip->reg_lock);
Ingo Molnar62932df2006-01-16 16:34:20 +01002149 mutex_init(&chip->open_mutex);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002150 chip->card = card;
2151 chip->pci = pci;
2152 chip->irq = -1;
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002153 chip->driver_type = driver_type;
Takashi Iwai134a11f2006-11-10 12:08:37 +01002154 chip->msi = enable_msi;
Takashi Iwai555e2192008-06-10 17:53:34 +02002155 chip->dev_index = dev;
Takashi Iwai9ad593f2008-05-16 12:34:47 +02002156 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002157
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002158 chip->position_fix = check_position_fix(chip, position_fix[dev]);
2159 check_probe_mask(chip, dev);
Takashi Iwai3372a152007-02-01 15:46:50 +01002160
Takashi Iwai27346162006-01-12 18:28:44 +01002161 chip->single_cmd = single_cmd;
Takashi Iwaic74db862005-05-12 14:26:27 +02002162
Takashi Iwai5c0d7bc2008-06-10 17:53:35 +02002163 if (bdl_pos_adj[dev] < 0) {
2164 switch (chip->driver_type) {
Takashi Iwai0c6341a2008-06-13 20:50:27 +02002165 case AZX_DRIVER_ICH:
2166 bdl_pos_adj[dev] = 1;
Takashi Iwai5c0d7bc2008-06-10 17:53:35 +02002167 break;
2168 default:
Takashi Iwai0c6341a2008-06-13 20:50:27 +02002169 bdl_pos_adj[dev] = 32;
Takashi Iwai5c0d7bc2008-06-10 17:53:35 +02002170 break;
2171 }
2172 }
2173
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002174#if BITS_PER_LONG != 64
2175 /* Fix up base address on ULI M5461 */
2176 if (chip->driver_type == AZX_DRIVER_ULI) {
2177 u16 tmp3;
2178 pci_read_config_word(pci, 0x40, &tmp3);
2179 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2180 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2181 }
2182#endif
2183
Pavel Machek927fc862006-08-31 17:03:43 +02002184 err = pci_request_regions(pci, "ICH HD audio");
2185 if (err < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002186 kfree(chip);
2187 pci_disable_device(pci);
2188 return err;
2189 }
2190
Pavel Machek927fc862006-08-31 17:03:43 +02002191 chip->addr = pci_resource_start(pci, 0);
Arjan van de Ven2f5ad542008-09-28 16:20:09 -07002192 chip->remap_addr = pci_ioremap_bar(pci, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002193 if (chip->remap_addr == NULL) {
2194 snd_printk(KERN_ERR SFX "ioremap error\n");
2195 err = -ENXIO;
2196 goto errout;
2197 }
2198
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002199 if (chip->msi)
2200 if (pci_enable_msi(pci) < 0)
2201 chip->msi = 0;
Stephen Hemminger7376d012006-08-21 19:17:46 +02002202
Takashi Iwai68e7fff2006-10-23 13:40:59 +02002203 if (azx_acquire_irq(chip, 0) < 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002204 err = -EBUSY;
2205 goto errout;
2206 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002207
2208 pci_set_master(pci);
2209 synchronize_irq(chip->irq);
2210
Tobin Davisbcd72002008-01-15 11:23:55 +01002211 gcap = azx_readw(chip, GCAP);
2212 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
2213
Takashi Iwaicf7aaca2008-02-06 15:05:57 +01002214 /* allow 64bit DMA address if supported by H/W */
2215 if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
2216 pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2217
Takashi Iwai8b6ed8e2008-02-19 11:36:35 +01002218 /* read number of streams from GCAP register instead of using
2219 * hardcoded value
2220 */
2221 chip->capture_streams = (gcap >> 8) & 0x0f;
2222 chip->playback_streams = (gcap >> 12) & 0x0f;
2223 if (!chip->playback_streams && !chip->capture_streams) {
Tobin Davisbcd72002008-01-15 11:23:55 +01002224 /* gcap didn't give any info, switching to old method */
2225
2226 switch (chip->driver_type) {
2227 case AZX_DRIVER_ULI:
2228 chip->playback_streams = ULI_NUM_PLAYBACK;
2229 chip->capture_streams = ULI_NUM_CAPTURE;
Tobin Davisbcd72002008-01-15 11:23:55 +01002230 break;
2231 case AZX_DRIVER_ATIHDMI:
2232 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2233 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
Tobin Davisbcd72002008-01-15 11:23:55 +01002234 break;
Yang, Libinc4da29c2008-11-13 11:07:07 +01002235 case AZX_DRIVER_GENERIC:
Tobin Davisbcd72002008-01-15 11:23:55 +01002236 default:
2237 chip->playback_streams = ICH6_NUM_PLAYBACK;
2238 chip->capture_streams = ICH6_NUM_CAPTURE;
Tobin Davisbcd72002008-01-15 11:23:55 +01002239 break;
2240 }
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002241 }
Takashi Iwai8b6ed8e2008-02-19 11:36:35 +01002242 chip->capture_index_offset = 0;
2243 chip->playback_index_offset = chip->capture_streams;
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002244 chip->num_streams = chip->playback_streams + chip->capture_streams;
Takashi Iwaid01ce992007-07-27 16:52:19 +02002245 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2246 GFP_KERNEL);
Pavel Machek927fc862006-08-31 17:03:43 +02002247 if (!chip->azx_dev) {
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002248 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
2249 goto errout;
2250 }
2251
Takashi Iwai4ce107b2008-02-06 14:50:19 +01002252 for (i = 0; i < chip->num_streams; i++) {
2253 /* allocate memory for the BDL for each stream */
2254 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2255 snd_dma_pci_data(chip->pci),
2256 BDL_SIZE, &chip->azx_dev[i].bdl);
2257 if (err < 0) {
2258 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2259 goto errout;
2260 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002261 }
Takashi Iwai0be3b5d2005-09-05 17:11:40 +02002262 /* allocate memory for the position buffer */
Takashi Iwaid01ce992007-07-27 16:52:19 +02002263 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2264 snd_dma_pci_data(chip->pci),
2265 chip->num_streams * 8, &chip->posbuf);
2266 if (err < 0) {
Takashi Iwai0be3b5d2005-09-05 17:11:40 +02002267 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2268 goto errout;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002269 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002270 /* allocate CORB/RIRB */
Takashi Iwaid01ce992007-07-27 16:52:19 +02002271 if (!chip->single_cmd) {
2272 err = azx_alloc_cmd_io(chip);
2273 if (err < 0)
Takashi Iwai27346162006-01-12 18:28:44 +01002274 goto errout;
Takashi Iwaid01ce992007-07-27 16:52:19 +02002275 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002276
2277 /* initialize streams */
2278 azx_init_stream(chip);
2279
2280 /* initialize chip */
Takashi Iwaicb53c622007-08-10 17:21:45 +02002281 azx_init_pci(chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002282 azx_init_chip(chip);
2283
2284 /* codec detection */
Pavel Machek927fc862006-08-31 17:03:43 +02002285 if (!chip->codec_mask) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002286 snd_printk(KERN_ERR SFX "no codecs found!\n");
2287 err = -ENODEV;
2288 goto errout;
2289 }
2290
Takashi Iwaid01ce992007-07-27 16:52:19 +02002291 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2292 if (err <0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002293 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2294 goto errout;
2295 }
2296
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002297 strcpy(card->driver, "HDA-Intel");
2298 strcpy(card->shortname, driver_short_names[chip->driver_type]);
Takashi Iwaid01ce992007-07-27 16:52:19 +02002299 sprintf(card->longname, "%s at 0x%lx irq %i",
2300 card->shortname, chip->addr, chip->irq);
Takashi Iwai07e4ca52005-08-24 14:14:57 +02002301
Linus Torvalds1da177e2005-04-16 15:20:36 -07002302 *rchip = chip;
2303 return 0;
2304
2305 errout:
2306 azx_free(chip);
2307 return err;
2308}
2309
Takashi Iwaicb53c622007-08-10 17:21:45 +02002310static void power_down_all_codecs(struct azx *chip)
2311{
2312#ifdef CONFIG_SND_HDA_POWER_SAVE
2313 /* The codecs were powered up in snd_hda_codec_new().
2314 * Now all initialization done, so turn them down if possible
2315 */
2316 struct hda_codec *codec;
2317 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2318 snd_hda_power_down(codec);
2319 }
2320#endif
2321}
2322
Takashi Iwaid01ce992007-07-27 16:52:19 +02002323static int __devinit azx_probe(struct pci_dev *pci,
2324 const struct pci_device_id *pci_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002325{
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002326 static int dev;
Takashi Iwaia98f90f2005-11-17 14:59:02 +01002327 struct snd_card *card;
2328 struct azx *chip;
Pavel Machek927fc862006-08-31 17:03:43 +02002329 int err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002330
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002331 if (dev >= SNDRV_CARDS)
2332 return -ENODEV;
2333 if (!enable[dev]) {
2334 dev++;
2335 return -ENOENT;
2336 }
2337
2338 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
Pavel Machek927fc862006-08-31 17:03:43 +02002339 if (!card) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002340 snd_printk(KERN_ERR SFX "Error creating card!\n");
2341 return -ENOMEM;
2342 }
2343
Takashi Iwai5aba4f82008-01-07 15:16:37 +01002344 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002345 if (err < 0)
2346 goto out_free;
Takashi Iwai421a1252005-11-17 16:11:09 +01002347 card->private_data = chip;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002348
Linus Torvalds1da177e2005-04-16 15:20:36 -07002349 /* create codec instances */
Takashi Iwaid4d9cd032008-12-19 15:19:11 +01002350 err = azx_codec_create(chip, model[dev], probe_mask[dev],
2351 probe_only[dev]);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002352 if (err < 0)
2353 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002354
2355 /* create PCM streams */
Takashi Iwai176d5332008-07-30 15:01:44 +02002356 err = snd_hda_build_pcms(chip->bus);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002357 if (err < 0)
2358 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002359
2360 /* create mixer controls */
Takashi Iwaid01ce992007-07-27 16:52:19 +02002361 err = azx_mixer_create(chip);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002362 if (err < 0)
2363 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002364
Linus Torvalds1da177e2005-04-16 15:20:36 -07002365 snd_card_set_dev(card, &pci->dev);
2366
Takashi Iwaid01ce992007-07-27 16:52:19 +02002367 err = snd_card_register(card);
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002368 if (err < 0)
2369 goto out_free;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002370
2371 pci_set_drvdata(pci, card);
Takashi Iwaicb53c622007-08-10 17:21:45 +02002372 chip->running = 1;
2373 power_down_all_codecs(chip);
Takashi Iwai0cbf0092008-10-29 16:18:25 +01002374 azx_notifier_register(chip);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002375
Andrew Paprockie25bcdb2008-01-13 11:57:17 +01002376 dev++;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002377 return err;
Wu Fengguang41dda0f2008-11-20 09:24:52 +08002378out_free:
2379 snd_card_free(card);
2380 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002381}
2382
2383static void __devexit azx_remove(struct pci_dev *pci)
2384{
2385 snd_card_free(pci_get_drvdata(pci));
2386 pci_set_drvdata(pci, NULL);
2387}
2388
2389/* PCI IDs */
Takashi Iwaif40b6892006-07-05 16:51:05 +02002390static struct pci_device_id azx_ids[] = {
Takashi Iwai87218e92008-02-21 08:13:11 +01002391 /* ICH 6..10 */
2392 { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2393 { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2394 { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2395 { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
Kailang Yangabbc9d12008-05-27 11:48:01 +02002396 { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
Takashi Iwai87218e92008-02-21 08:13:11 +01002397 { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2398 { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2399 { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2400 { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
Seth Heasleyb29c2362008-08-08 15:56:39 -07002401 /* PCH */
2402 { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
Takashi Iwai87218e92008-02-21 08:13:11 +01002403 /* SCH */
2404 { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2405 /* ATI SB 450/600 */
2406 { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2407 { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2408 /* ATI HDMI */
2409 { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2410 { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2411 { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
Libin Yang9e6dd472008-08-12 12:25:46 +02002412 { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
Takashi Iwai87218e92008-02-21 08:13:11 +01002413 { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2414 { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2415 { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2416 { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2417 { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2418 { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2419 { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2420 { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2421 { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2422 { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2423 /* VIA VT8251/VT8237A */
2424 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2425 /* SIS966 */
2426 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2427 /* ULI M5461 */
2428 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2429 /* NVIDIA MCP */
2430 { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2431 { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2432 { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2433 { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2434 { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2435 { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2436 { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2437 { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2438 { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2439 { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2440 { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2441 { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2442 { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2443 { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2444 { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2445 { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2446 { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2447 { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
Peer Chen487145a2008-03-06 15:15:11 +01002448 { PCI_DEVICE(0x10de, 0x0bd4), .driver_data = AZX_DRIVER_NVIDIA },
2449 { PCI_DEVICE(0x10de, 0x0bd5), .driver_data = AZX_DRIVER_NVIDIA },
2450 { PCI_DEVICE(0x10de, 0x0bd6), .driver_data = AZX_DRIVER_NVIDIA },
2451 { PCI_DEVICE(0x10de, 0x0bd7), .driver_data = AZX_DRIVER_NVIDIA },
Kailang Yangf2690022008-05-27 11:44:55 +02002452 /* Teradici */
2453 { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
Yang, Libinc4da29c2008-11-13 11:07:07 +01002454 /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2455 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2456 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2457 .class_mask = 0xffffff,
2458 .driver_data = AZX_DRIVER_GENERIC },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002459 { 0, }
2460};
2461MODULE_DEVICE_TABLE(pci, azx_ids);
2462
2463/* pci_driver definition */
2464static struct pci_driver driver = {
2465 .name = "HDA Intel",
2466 .id_table = azx_ids,
2467 .probe = azx_probe,
2468 .remove = __devexit_p(azx_remove),
Takashi Iwai421a1252005-11-17 16:11:09 +01002469#ifdef CONFIG_PM
2470 .suspend = azx_suspend,
Rafael J. Wysocki32e176c2008-12-06 15:09:08 +01002471 .resume_early = azx_resume_early,
Takashi Iwai421a1252005-11-17 16:11:09 +01002472 .resume = azx_resume,
2473#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002474};
2475
2476static int __init alsa_card_azx_init(void)
2477{
Takashi Iwai01d25d42005-04-11 16:58:24 +02002478 return pci_register_driver(&driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002479}
2480
2481static void __exit alsa_card_azx_exit(void)
2482{
2483 pci_unregister_driver(&driver);
2484}
2485
2486module_init(alsa_card_azx_init)
2487module_exit(alsa_card_azx_exit)