blob: f60e2ba515d030b283047dc3ba49408816dd6444 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020056#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020057#include <net/pkt_cls.h>
58#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020059#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010060#include <net/tc_act/tc_sample.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020061
62#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020063#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020064#include "core.h"
65#include "reg.h"
66#include "port.h"
67#include "trap.h"
68#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010069#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020070#include "spectrum_dpipe.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020071#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020072
Yotam Gigi6b742192017-05-23 21:56:29 +020073#define MLXSW_FWREV_MAJOR 13
74#define MLXSW_FWREV_MINOR 1420
75#define MLXSW_FWREV_SUBMINOR 122
76
77static const struct mlxsw_fw_rev mlxsw_sp_supported_fw_rev = {
78 .major = MLXSW_FWREV_MAJOR,
79 .minor = MLXSW_FWREV_MINOR,
80 .subminor = MLXSW_FWREV_SUBMINOR
81};
82
83#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020084 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020085 "." __stringify(MLXSW_FWREV_MINOR) \
86 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
87
Jiri Pirko56ade8f2015-10-16 14:01:37 +020088static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
89static const char mlxsw_sp_driver_version[] = "1.0";
90
91/* tx_hdr_version
92 * Tx header version.
93 * Must be set to 1.
94 */
95MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
96
97/* tx_hdr_ctl
98 * Packet control type.
99 * 0 - Ethernet control (e.g. EMADs, LACP)
100 * 1 - Ethernet data
101 */
102MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
103
104/* tx_hdr_proto
105 * Packet protocol type. Must be set to 1 (Ethernet).
106 */
107MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
108
109/* tx_hdr_rx_is_router
110 * Packet is sent from the router. Valid for data packets only.
111 */
112MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
113
114/* tx_hdr_fid_valid
115 * Indicates if the 'fid' field is valid and should be used for
116 * forwarding lookup. Valid for data packets only.
117 */
118MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
119
120/* tx_hdr_swid
121 * Switch partition ID. Must be set to 0.
122 */
123MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
124
125/* tx_hdr_control_tclass
126 * Indicates if the packet should use the control TClass and not one
127 * of the data TClasses.
128 */
129MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
130
131/* tx_hdr_etclass
132 * Egress TClass to be used on the egress device on the egress port.
133 */
134MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
135
136/* tx_hdr_port_mid
137 * Destination local port for unicast packets.
138 * Destination multicast ID for multicast packets.
139 *
140 * Control packets are directed to a specific egress port, while data
141 * packets are transmitted through the CPU port (0) into the switch partition,
142 * where forwarding rules are applied.
143 */
144MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
145
146/* tx_hdr_fid
147 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
148 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
149 * Valid for data packets only.
150 */
151MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
152
153/* tx_hdr_type
154 * 0 - Data packets
155 * 6 - Control packets
156 */
157MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
158
Yotam Gigie5e5c882017-05-23 21:56:27 +0200159struct mlxsw_sp_mlxfw_dev {
160 struct mlxfw_dev mlxfw_dev;
161 struct mlxsw_sp *mlxsw_sp;
162};
163
164static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
165 u16 component_index, u32 *p_max_size,
166 u8 *p_align_bits, u16 *p_max_write_size)
167{
168 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
169 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
170 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
171 char mcqi_pl[MLXSW_REG_MCQI_LEN];
172 int err;
173
174 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
175 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
176 if (err)
177 return err;
178 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
179 p_max_write_size);
180
181 *p_align_bits = max_t(u8, *p_align_bits, 2);
182 *p_max_write_size = min_t(u16, *p_max_write_size,
183 MLXSW_REG_MCDA_MAX_DATA_LEN);
184 return 0;
185}
186
187static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
188{
189 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
190 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
191 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
192 char mcc_pl[MLXSW_REG_MCC_LEN];
193 u8 control_state;
194 int err;
195
196 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
197 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
198 if (err)
199 return err;
200
201 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
202 if (control_state != MLXFW_FSM_STATE_IDLE)
203 return -EBUSY;
204
205 mlxsw_reg_mcc_pack(mcc_pl,
206 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
207 0, *fwhandle, 0);
208 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
209}
210
211static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
212 u32 fwhandle, u16 component_index,
213 u32 component_size)
214{
215 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
216 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
217 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
218 char mcc_pl[MLXSW_REG_MCC_LEN];
219
220 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
221 component_index, fwhandle, component_size);
222 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
223}
224
225static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
226 u32 fwhandle, u8 *data, u16 size,
227 u32 offset)
228{
229 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
230 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
231 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
232 char mcda_pl[MLXSW_REG_MCDA_LEN];
233
234 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
235 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
236}
237
238static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
239 u32 fwhandle, u16 component_index)
240{
241 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
242 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
243 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
244 char mcc_pl[MLXSW_REG_MCC_LEN];
245
246 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
247 component_index, fwhandle, 0);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
249}
250
251static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
252{
253 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
254 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
255 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
256 char mcc_pl[MLXSW_REG_MCC_LEN];
257
258 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
259 fwhandle, 0);
260 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
261}
262
263static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
264 enum mlxfw_fsm_state *fsm_state,
265 enum mlxfw_fsm_state_err *fsm_state_err)
266{
267 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
268 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
269 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
270 char mcc_pl[MLXSW_REG_MCC_LEN];
271 u8 control_state;
272 u8 error_code;
273 int err;
274
275 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
276 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
277 if (err)
278 return err;
279
280 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
281 *fsm_state = control_state;
282 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
283 MLXFW_FSM_STATE_ERR_MAX);
284 return 0;
285}
286
287static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
288{
289 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
290 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
291 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
292 char mcc_pl[MLXSW_REG_MCC_LEN];
293
294 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
295 fwhandle, 0);
296 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
297}
298
299static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
300{
301 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
302 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
303 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
304 char mcc_pl[MLXSW_REG_MCC_LEN];
305
306 mlxsw_reg_mcc_pack(mcc_pl,
307 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
308 fwhandle, 0);
309 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
310}
311
312static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
313 .component_query = mlxsw_sp_component_query,
314 .fsm_lock = mlxsw_sp_fsm_lock,
315 .fsm_component_update = mlxsw_sp_fsm_component_update,
316 .fsm_block_download = mlxsw_sp_fsm_block_download,
317 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
318 .fsm_activate = mlxsw_sp_fsm_activate,
319 .fsm_query_state = mlxsw_sp_fsm_query_state,
320 .fsm_cancel = mlxsw_sp_fsm_cancel,
321 .fsm_release = mlxsw_sp_fsm_release
322};
323
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300324static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
325 const struct firmware *firmware)
326{
327 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
328 .mlxfw_dev = {
329 .ops = &mlxsw_sp_mlxfw_dev_ops,
330 .psid = mlxsw_sp->bus_info->psid,
331 .psid_size = strlen(mlxsw_sp->bus_info->psid),
332 },
333 .mlxsw_sp = mlxsw_sp
334 };
335
336 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
337}
338
Yotam Gigi6b742192017-05-23 21:56:29 +0200339static bool mlxsw_sp_fw_rev_ge(const struct mlxsw_fw_rev *a,
340 const struct mlxsw_fw_rev *b)
341{
342 if (a->major != b->major)
343 return a->major > b->major;
344 if (a->minor != b->minor)
345 return a->minor > b->minor;
346 return a->subminor >= b->subminor;
347}
348
349static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
350{
351 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200352 const struct firmware *firmware;
353 int err;
354
355 if (mlxsw_sp_fw_rev_ge(rev, &mlxsw_sp_supported_fw_rev))
356 return 0;
357
358 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d out of data\n",
359 rev->major, rev->minor, rev->subminor);
360 dev_info(mlxsw_sp->bus_info->dev, "Upgrading firmware using file %s\n",
361 MLXSW_SP_FW_FILENAME);
362
363 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
364 mlxsw_sp->bus_info->dev);
365 if (err) {
366 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
367 MLXSW_SP_FW_FILENAME);
368 return err;
369 }
370
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300371 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200372 release_firmware(firmware);
373 return err;
374}
375
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100376int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
377 unsigned int counter_index, u64 *packets,
378 u64 *bytes)
379{
380 char mgpc_pl[MLXSW_REG_MGPC_LEN];
381 int err;
382
383 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
384 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
385 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
386 if (err)
387 return err;
388 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
389 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
390 return 0;
391}
392
393static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
394 unsigned int counter_index)
395{
396 char mgpc_pl[MLXSW_REG_MGPC_LEN];
397
398 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
399 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
400 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
401}
402
403int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
404 unsigned int *p_counter_index)
405{
406 int err;
407
408 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
409 p_counter_index);
410 if (err)
411 return err;
412 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
413 if (err)
414 goto err_counter_clear;
415 return 0;
416
417err_counter_clear:
418 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
419 *p_counter_index);
420 return err;
421}
422
423void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
424 unsigned int counter_index)
425{
426 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
427 counter_index);
428}
429
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200430static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
431 const struct mlxsw_tx_info *tx_info)
432{
433 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
434
435 memset(txhdr, 0, MLXSW_TXHDR_LEN);
436
437 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
438 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
439 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
440 mlxsw_tx_hdr_swid_set(txhdr, 0);
441 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
442 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
443 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
444}
445
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200446int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
447 u8 state)
448{
449 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
450 enum mlxsw_reg_spms_state spms_state;
451 char *spms_pl;
452 int err;
453
454 switch (state) {
455 case BR_STATE_FORWARDING:
456 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
457 break;
458 case BR_STATE_LEARNING:
459 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
460 break;
461 case BR_STATE_LISTENING: /* fall-through */
462 case BR_STATE_DISABLED: /* fall-through */
463 case BR_STATE_BLOCKING:
464 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
465 break;
466 default:
467 BUG();
468 }
469
470 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
471 if (!spms_pl)
472 return -ENOMEM;
473 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
474 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
475
476 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
477 kfree(spms_pl);
478 return err;
479}
480
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200481static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
482{
Elad Raz5b090742016-10-28 21:35:46 +0200483 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200484 int err;
485
486 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
487 if (err)
488 return err;
489 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
490 return 0;
491}
492
Yotam Gigi763b4b72016-07-21 12:03:17 +0200493static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
494{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200495 int i;
496
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200497 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200498 return -EIO;
499
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200500 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
501 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200502 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
503 sizeof(struct mlxsw_sp_span_entry),
504 GFP_KERNEL);
505 if (!mlxsw_sp->span.entries)
506 return -ENOMEM;
507
508 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
509 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
510
511 return 0;
512}
513
514static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
515{
516 int i;
517
518 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
519 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
520
521 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
522 }
523 kfree(mlxsw_sp->span.entries);
524}
525
526static struct mlxsw_sp_span_entry *
527mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
528{
529 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
530 struct mlxsw_sp_span_entry *span_entry;
531 char mpat_pl[MLXSW_REG_MPAT_LEN];
532 u8 local_port = port->local_port;
533 int index;
534 int i;
535 int err;
536
537 /* find a free entry to use */
538 index = -1;
539 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
540 if (!mlxsw_sp->span.entries[i].used) {
541 index = i;
542 span_entry = &mlxsw_sp->span.entries[i];
543 break;
544 }
545 }
546 if (index < 0)
547 return NULL;
548
549 /* create a new port analayzer entry for local_port */
550 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
551 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
552 if (err)
553 return NULL;
554
555 span_entry->used = true;
556 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100557 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200558 span_entry->local_port = local_port;
559 return span_entry;
560}
561
562static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
563 struct mlxsw_sp_span_entry *span_entry)
564{
565 u8 local_port = span_entry->local_port;
566 char mpat_pl[MLXSW_REG_MPAT_LEN];
567 int pa_id = span_entry->id;
568
569 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
570 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
571 span_entry->used = false;
572}
573
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200574static struct mlxsw_sp_span_entry *
575mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200576{
577 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
578 int i;
579
580 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
581 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
582
583 if (curr->used && curr->local_port == port->local_port)
584 return curr;
585 }
586 return NULL;
587}
588
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200589static struct mlxsw_sp_span_entry
590*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200591{
592 struct mlxsw_sp_span_entry *span_entry;
593
594 span_entry = mlxsw_sp_span_entry_find(port);
595 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100596 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200597 span_entry->ref_count++;
598 return span_entry;
599 }
600
601 return mlxsw_sp_span_entry_create(port);
602}
603
604static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
605 struct mlxsw_sp_span_entry *span_entry)
606{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100607 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200608 if (--span_entry->ref_count == 0)
609 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
610 return 0;
611}
612
613static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
614{
615 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
616 struct mlxsw_sp_span_inspected_port *p;
617 int i;
618
619 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
620 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
621
622 list_for_each_entry(p, &curr->bound_ports_list, list)
623 if (p->local_port == port->local_port &&
624 p->type == MLXSW_SP_SPAN_EGRESS)
625 return true;
626 }
627
628 return false;
629}
630
Ido Schimmel18281f22017-03-24 08:02:51 +0100631static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
632 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200633{
Ido Schimmel18281f22017-03-24 08:02:51 +0100634 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200635}
636
637static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
638{
639 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
640 char sbib_pl[MLXSW_REG_SBIB_LEN];
641 int err;
642
643 /* If port is egress mirrored, the shared buffer size should be
644 * updated according to the mtu value
645 */
646 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100647 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
648
649 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200650 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
651 if (err) {
652 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
653 return err;
654 }
655 }
656
657 return 0;
658}
659
660static struct mlxsw_sp_span_inspected_port *
661mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
662 struct mlxsw_sp_span_entry *span_entry)
663{
664 struct mlxsw_sp_span_inspected_port *p;
665
666 list_for_each_entry(p, &span_entry->bound_ports_list, list)
667 if (port->local_port == p->local_port)
668 return p;
669 return NULL;
670}
671
672static int
673mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
674 struct mlxsw_sp_span_entry *span_entry,
675 enum mlxsw_sp_span_type type)
676{
677 struct mlxsw_sp_span_inspected_port *inspected_port;
678 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
679 char mpar_pl[MLXSW_REG_MPAR_LEN];
680 char sbib_pl[MLXSW_REG_SBIB_LEN];
681 int pa_id = span_entry->id;
682 int err;
683
684 /* if it is an egress SPAN, bind a shared buffer to it */
685 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100686 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
687 port->dev->mtu);
688
689 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200690 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
691 if (err) {
692 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
693 return err;
694 }
695 }
696
697 /* bind the port to the SPAN entry */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200698 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
699 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200700 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
701 if (err)
702 goto err_mpar_reg_write;
703
704 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
705 if (!inspected_port) {
706 err = -ENOMEM;
707 goto err_inspected_port_alloc;
708 }
709 inspected_port->local_port = port->local_port;
710 inspected_port->type = type;
711 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
712
713 return 0;
714
715err_mpar_reg_write:
716err_inspected_port_alloc:
717 if (type == MLXSW_SP_SPAN_EGRESS) {
718 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
719 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
720 }
721 return err;
722}
723
724static void
725mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
726 struct mlxsw_sp_span_entry *span_entry,
727 enum mlxsw_sp_span_type type)
728{
729 struct mlxsw_sp_span_inspected_port *inspected_port;
730 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
731 char mpar_pl[MLXSW_REG_MPAR_LEN];
732 char sbib_pl[MLXSW_REG_SBIB_LEN];
733 int pa_id = span_entry->id;
734
735 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
736 if (!inspected_port)
737 return;
738
739 /* remove the inspected port */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200740 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
741 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200742 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
743
744 /* remove the SBIB buffer if it was egress SPAN */
745 if (type == MLXSW_SP_SPAN_EGRESS) {
746 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
747 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
748 }
749
750 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
751
752 list_del(&inspected_port->list);
753 kfree(inspected_port);
754}
755
756static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
757 struct mlxsw_sp_port *to,
758 enum mlxsw_sp_span_type type)
759{
760 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
761 struct mlxsw_sp_span_entry *span_entry;
762 int err;
763
764 span_entry = mlxsw_sp_span_entry_get(to);
765 if (!span_entry)
766 return -ENOENT;
767
768 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
769 span_entry->id);
770
771 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
772 if (err)
773 goto err_port_bind;
774
775 return 0;
776
777err_port_bind:
778 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
779 return err;
780}
781
782static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
783 struct mlxsw_sp_port *to,
784 enum mlxsw_sp_span_type type)
785{
786 struct mlxsw_sp_span_entry *span_entry;
787
788 span_entry = mlxsw_sp_span_entry_find(to);
789 if (!span_entry) {
790 netdev_err(from->dev, "no span entry found\n");
791 return;
792 }
793
794 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
795 span_entry->id);
796 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
797}
798
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100799static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
800 bool enable, u32 rate)
801{
802 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
803 char mpsc_pl[MLXSW_REG_MPSC_LEN];
804
805 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
806 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
807}
808
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200809static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
810 bool is_up)
811{
812 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
813 char paos_pl[MLXSW_REG_PAOS_LEN];
814
815 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
816 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
817 MLXSW_PORT_ADMIN_STATUS_DOWN);
818 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
819}
820
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200821static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
822 unsigned char *addr)
823{
824 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
825 char ppad_pl[MLXSW_REG_PPAD_LEN];
826
827 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
828 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
829 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
830}
831
832static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
833{
834 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
835 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
836
837 ether_addr_copy(addr, mlxsw_sp->base_mac);
838 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
839 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
840}
841
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200842static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
843{
844 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
845 char pmtu_pl[MLXSW_REG_PMTU_LEN];
846 int max_mtu;
847 int err;
848
849 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
850 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
851 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
852 if (err)
853 return err;
854 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
855
856 if (mtu > max_mtu)
857 return -EINVAL;
858
859 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
860 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
861}
862
Ido Schimmelbe945352016-06-09 09:51:39 +0200863static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
864 u8 swid)
865{
866 char pspa_pl[MLXSW_REG_PSPA_LEN];
867
868 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
869 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
870}
871
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200872static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
873{
874 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200875
Ido Schimmelbe945352016-06-09 09:51:39 +0200876 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
877 swid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200878}
879
Ido Schimmela1107482017-05-26 08:37:39 +0200880int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200881{
882 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
883 char svpe_pl[MLXSW_REG_SVPE_LEN];
884
885 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
886 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
887}
888
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200889int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
890 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200891{
892 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
893 char *spvmlr_pl;
894 int err;
895
896 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
897 if (!spvmlr_pl)
898 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200899 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
900 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200901 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
902 kfree(spvmlr_pl);
903 return err;
904}
905
Ido Schimmelb02eae92017-05-16 19:38:34 +0200906static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
907 u16 vid)
908{
909 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
910 char spvid_pl[MLXSW_REG_SPVID_LEN];
911
912 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
913 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
914}
915
916static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
917 bool allow)
918{
919 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
920 char spaft_pl[MLXSW_REG_SPAFT_LEN];
921
922 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
923 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
924}
925
926int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
927{
928 int err;
929
930 if (!vid) {
931 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
932 if (err)
933 return err;
934 } else {
935 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
936 if (err)
937 return err;
938 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
939 if (err)
940 goto err_port_allow_untagged_set;
941 }
942
943 mlxsw_sp_port->pvid = vid;
944 return 0;
945
946err_port_allow_untagged_set:
947 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
948 return err;
949}
950
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200951static int
952mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
953{
954 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
955 char sspr_pl[MLXSW_REG_SSPR_LEN];
956
957 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
958 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
959}
960
Ido Schimmeld664b412016-06-09 09:51:40 +0200961static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
962 u8 local_port, u8 *p_module,
963 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200964{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200965 char pmlp_pl[MLXSW_REG_PMLP_LEN];
966 int err;
967
Ido Schimmel558c2d52016-02-26 17:32:29 +0100968 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200969 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
970 if (err)
971 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100972 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
973 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200974 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200975 return 0;
976}
977
Ido Schimmel18f1e702016-02-26 17:32:31 +0100978static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
979 u8 module, u8 width, u8 lane)
980{
981 char pmlp_pl[MLXSW_REG_PMLP_LEN];
982 int i;
983
984 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
985 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
986 for (i = 0; i < width; i++) {
987 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
988 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
989 }
990
991 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
992}
993
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100994static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
995{
996 char pmlp_pl[MLXSW_REG_PMLP_LEN];
997
998 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
999 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
1000 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1001}
1002
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001003static int mlxsw_sp_port_open(struct net_device *dev)
1004{
1005 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1006 int err;
1007
1008 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1009 if (err)
1010 return err;
1011 netif_start_queue(dev);
1012 return 0;
1013}
1014
1015static int mlxsw_sp_port_stop(struct net_device *dev)
1016{
1017 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1018
1019 netif_stop_queue(dev);
1020 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1021}
1022
1023static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1024 struct net_device *dev)
1025{
1026 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1027 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1028 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1029 const struct mlxsw_tx_info tx_info = {
1030 .local_port = mlxsw_sp_port->local_port,
1031 .is_emad = false,
1032 };
1033 u64 len;
1034 int err;
1035
Jiri Pirko307c2432016-04-08 19:11:22 +02001036 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001037 return NETDEV_TX_BUSY;
1038
1039 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1040 struct sk_buff *skb_orig = skb;
1041
1042 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1043 if (!skb) {
1044 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1045 dev_kfree_skb_any(skb_orig);
1046 return NETDEV_TX_OK;
1047 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +01001048 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001049 }
1050
1051 if (eth_skb_pad(skb)) {
1052 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1053 return NETDEV_TX_OK;
1054 }
1055
1056 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +02001057 /* TX header is consumed by HW on the way so we shouldn't count its
1058 * bytes as being sent.
1059 */
1060 len = skb->len - MLXSW_TXHDR_LEN;
1061
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001062 /* Due to a race we might fail here because of a full queue. In that
1063 * unlikely case we simply drop the packet.
1064 */
Jiri Pirko307c2432016-04-08 19:11:22 +02001065 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001066
1067 if (!err) {
1068 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1069 u64_stats_update_begin(&pcpu_stats->syncp);
1070 pcpu_stats->tx_packets++;
1071 pcpu_stats->tx_bytes += len;
1072 u64_stats_update_end(&pcpu_stats->syncp);
1073 } else {
1074 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1075 dev_kfree_skb_any(skb);
1076 }
1077 return NETDEV_TX_OK;
1078}
1079
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001080static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1081{
1082}
1083
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001084static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1085{
1086 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1087 struct sockaddr *addr = p;
1088 int err;
1089
1090 if (!is_valid_ether_addr(addr->sa_data))
1091 return -EADDRNOTAVAIL;
1092
1093 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1094 if (err)
1095 return err;
1096 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1097 return 0;
1098}
1099
Ido Schimmel18281f22017-03-24 08:02:51 +01001100static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1101 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001102{
Ido Schimmel18281f22017-03-24 08:02:51 +01001103 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001104}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001105
Ido Schimmelf417f042017-03-24 08:02:50 +01001106#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +01001107
1108static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1109 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +01001110{
Ido Schimmel18281f22017-03-24 08:02:51 +01001111 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1112 BITS_PER_BYTE));
1113 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1114 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001115}
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001116
Ido Schimmel18281f22017-03-24 08:02:51 +01001117/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +01001118 * Assumes 100m cable and maximum MTU.
1119 */
Ido Schimmel18281f22017-03-24 08:02:51 +01001120#define MLXSW_SP_PAUSE_DELAY 58752
1121
1122static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1123 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +01001124{
1125 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +01001126 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +01001127 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +01001128 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001129 else
Ido Schimmelf417f042017-03-24 08:02:50 +01001130 return 0;
1131}
1132
1133static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1134 bool lossy)
1135{
1136 if (lossy)
1137 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
1138 else
1139 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1140 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001141}
1142
1143int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001144 u8 *prio_tc, bool pause_en,
1145 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +02001146{
1147 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001148 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1149 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001150 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001151 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001152
1153 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1154 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1155 if (err)
1156 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001157
1158 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1159 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001160 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +01001161 bool lossy;
1162 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001163
1164 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1165 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001166 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001167 configure = true;
1168 break;
1169 }
1170 }
1171
1172 if (!configure)
1173 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +01001174
1175 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +01001176 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1177 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1178 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +01001179 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001180 }
1181
Ido Schimmelff6551e2016-04-06 17:10:03 +02001182 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1183}
1184
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001185static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001186 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001187{
1188 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1189 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001190 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001191 u8 *prio_tc;
1192
1193 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001194 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001195
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001196 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001197 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001198}
1199
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001200static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1201{
1202 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001203 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001204 int err;
1205
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001206 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001207 if (err)
1208 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001209 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1210 if (err)
1211 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001212 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1213 if (err)
1214 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001215 dev->mtu = mtu;
1216 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001217
1218err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001219 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1220err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001221 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +02001222 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001223}
1224
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001225static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001226mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1227 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001228{
1229 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1230 struct mlxsw_sp_port_pcpu_stats *p;
1231 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1232 u32 tx_dropped = 0;
1233 unsigned int start;
1234 int i;
1235
1236 for_each_possible_cpu(i) {
1237 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1238 do {
1239 start = u64_stats_fetch_begin_irq(&p->syncp);
1240 rx_packets = p->rx_packets;
1241 rx_bytes = p->rx_bytes;
1242 tx_packets = p->tx_packets;
1243 tx_bytes = p->tx_bytes;
1244 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1245
1246 stats->rx_packets += rx_packets;
1247 stats->rx_bytes += rx_bytes;
1248 stats->tx_packets += tx_packets;
1249 stats->tx_bytes += tx_bytes;
1250 /* tx_dropped is u32, updated without syncp protection. */
1251 tx_dropped += p->tx_dropped;
1252 }
1253 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001254 return 0;
1255}
1256
Or Gerlitz3df5b3c2016-11-22 23:09:54 +02001257static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001258{
1259 switch (attr_id) {
1260 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1261 return true;
1262 }
1263
1264 return false;
1265}
1266
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001267static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1268 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001269{
1270 switch (attr_id) {
1271 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1272 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1273 }
1274
1275 return -EINVAL;
1276}
1277
1278static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1279 int prio, char *ppcnt_pl)
1280{
1281 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1283
1284 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1285 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1286}
1287
1288static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1289 struct rtnl_link_stats64 *stats)
1290{
1291 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1292 int err;
1293
1294 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1295 0, ppcnt_pl);
1296 if (err)
1297 goto out;
1298
1299 stats->tx_packets =
1300 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1301 stats->rx_packets =
1302 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1303 stats->tx_bytes =
1304 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1305 stats->rx_bytes =
1306 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1307 stats->multicast =
1308 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1309
1310 stats->rx_crc_errors =
1311 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1312 stats->rx_frame_errors =
1313 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1314
1315 stats->rx_length_errors = (
1316 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1317 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1318 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1319
1320 stats->rx_errors = (stats->rx_crc_errors +
1321 stats->rx_frame_errors + stats->rx_length_errors);
1322
1323out:
1324 return err;
1325}
1326
1327static void update_stats_cache(struct work_struct *work)
1328{
1329 struct mlxsw_sp_port *mlxsw_sp_port =
1330 container_of(work, struct mlxsw_sp_port,
1331 hw_stats.update_dw.work);
1332
1333 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1334 goto out;
1335
1336 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1337 mlxsw_sp_port->hw_stats.cache);
1338
1339out:
1340 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
1341 MLXSW_HW_STATS_UPDATE_TIME);
1342}
1343
1344/* Return the stats from a cache that is updated periodically,
1345 * as this function might get called in an atomic context.
1346 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001347static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001348mlxsw_sp_port_get_stats64(struct net_device *dev,
1349 struct rtnl_link_stats64 *stats)
1350{
1351 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1352
1353 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001354}
1355
Jiri Pirko93cd0812017-04-18 16:55:35 +02001356static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1357 u16 vid_begin, u16 vid_end,
1358 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001359{
1360 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1361 char *spvm_pl;
1362 int err;
1363
1364 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1365 if (!spvm_pl)
1366 return -ENOMEM;
1367
1368 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1369 vid_end, is_member, untagged);
1370 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1371 kfree(spvm_pl);
1372 return err;
1373}
1374
Jiri Pirko93cd0812017-04-18 16:55:35 +02001375int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1376 u16 vid_end, bool is_member, bool untagged)
1377{
1378 u16 vid, vid_e;
1379 int err;
1380
1381 for (vid = vid_begin; vid <= vid_end;
1382 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1383 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1384 vid_end);
1385
1386 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1387 is_member, untagged);
1388 if (err)
1389 return err;
1390 }
1391
1392 return 0;
1393}
1394
Ido Schimmelc57529e2017-05-26 08:37:31 +02001395static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001396{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001397 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001398
Ido Schimmelc57529e2017-05-26 08:37:31 +02001399 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1400 &mlxsw_sp_port->vlans_list, list)
1401 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001402}
1403
Ido Schimmel31a08a52017-05-26 08:37:26 +02001404static struct mlxsw_sp_port_vlan *
1405mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1406{
1407 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001408 bool untagged = vid == 1;
1409 int err;
1410
1411 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1412 if (err)
1413 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001414
1415 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001416 if (!mlxsw_sp_port_vlan) {
1417 err = -ENOMEM;
1418 goto err_port_vlan_alloc;
1419 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001420
1421 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1422 mlxsw_sp_port_vlan->vid = vid;
1423 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1424
1425 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001426
1427err_port_vlan_alloc:
1428 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1429 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001430}
1431
1432static void
1433mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1434{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001435 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1436 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001437
Ido Schimmel31a08a52017-05-26 08:37:26 +02001438 list_del(&mlxsw_sp_port_vlan->list);
1439 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001440 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1441}
1442
1443struct mlxsw_sp_port_vlan *
1444mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1445{
1446 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1447
1448 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1449 if (mlxsw_sp_port_vlan)
1450 return mlxsw_sp_port_vlan;
1451
1452 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1453}
1454
1455void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1456{
Ido Schimmela1107482017-05-26 08:37:39 +02001457 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1458
Ido Schimmelc57529e2017-05-26 08:37:31 +02001459 if (mlxsw_sp_port_vlan->bridge_port)
1460 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001461 else if (fid)
1462 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001463
1464 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001465}
1466
Ido Schimmel05978482016-08-17 16:39:30 +02001467static int mlxsw_sp_port_add_vid(struct net_device *dev,
1468 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001469{
1470 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001471
1472 /* VLAN 0 is added to HW filter when device goes up, but it is
1473 * reserved in our case, so simply return.
1474 */
1475 if (!vid)
1476 return 0;
1477
Ido Schimmelc57529e2017-05-26 08:37:31 +02001478 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001479}
1480
Ido Schimmel32d863f2016-07-02 11:00:10 +02001481static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1482 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001483{
1484 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001485 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001486
1487 /* VLAN 0 is removed from HW filter when device goes down, but
1488 * it is reserved in our case, so simply return.
1489 */
1490 if (!vid)
1491 return 0;
1492
Ido Schimmel31a08a52017-05-26 08:37:26 +02001493 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001494 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001495 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001496 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001497
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001498 return 0;
1499}
1500
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001501static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1502 size_t len)
1503{
1504 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001505 u8 module = mlxsw_sp_port->mapping.module;
1506 u8 width = mlxsw_sp_port->mapping.width;
1507 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001508 int err;
1509
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001510 if (!mlxsw_sp_port->split)
1511 err = snprintf(name, len, "p%d", module + 1);
1512 else
1513 err = snprintf(name, len, "p%ds%d", module + 1,
1514 lane / width);
1515
1516 if (err >= len)
1517 return -EINVAL;
1518
1519 return 0;
1520}
1521
Yotam Gigi763b4b72016-07-21 12:03:17 +02001522static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001523mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1524 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001525 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1526
1527 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1528 if (mall_tc_entry->cookie == cookie)
1529 return mall_tc_entry;
1530
1531 return NULL;
1532}
1533
1534static int
1535mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001536 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001537 const struct tc_action *a,
1538 bool ingress)
1539{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001540 struct net *net = dev_net(mlxsw_sp_port->dev);
1541 enum mlxsw_sp_span_type span_type;
1542 struct mlxsw_sp_port *to_port;
1543 struct net_device *to_dev;
1544 int ifindex;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001545
1546 ifindex = tcf_mirred_ifindex(a);
1547 to_dev = __dev_get_by_index(net, ifindex);
1548 if (!to_dev) {
1549 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1550 return -EINVAL;
1551 }
1552
1553 if (!mlxsw_sp_port_dev_check(to_dev)) {
1554 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001555 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001556 }
1557 to_port = netdev_priv(to_dev);
1558
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001559 mirror->to_local_port = to_port->local_port;
1560 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001561 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001562 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1563}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001564
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001565static void
1566mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1567 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1568{
1569 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1570 enum mlxsw_sp_span_type span_type;
1571 struct mlxsw_sp_port *to_port;
1572
1573 to_port = mlxsw_sp->ports[mirror->to_local_port];
1574 span_type = mirror->ingress ?
1575 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1576 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001577}
1578
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001579static int
1580mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1581 struct tc_cls_matchall_offload *cls,
1582 const struct tc_action *a,
1583 bool ingress)
1584{
1585 int err;
1586
1587 if (!mlxsw_sp_port->sample)
1588 return -EOPNOTSUPP;
1589 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1590 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1591 return -EEXIST;
1592 }
1593 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1594 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1595 return -EOPNOTSUPP;
1596 }
1597
1598 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1599 tcf_sample_psample_group(a));
1600 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1601 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1602 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1603
1604 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1605 if (err)
1606 goto err_port_sample_set;
1607 return 0;
1608
1609err_port_sample_set:
1610 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1611 return err;
1612}
1613
1614static void
1615mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1616{
1617 if (!mlxsw_sp_port->sample)
1618 return;
1619
1620 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1621 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1622}
1623
Yotam Gigi763b4b72016-07-21 12:03:17 +02001624static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1625 __be16 protocol,
1626 struct tc_cls_matchall_offload *cls,
1627 bool ingress)
1628{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001629 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001630 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001631 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001632 int err;
1633
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001634 if (!tc_single_action(cls->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001635 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001636 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001637 }
1638
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001639 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1640 if (!mall_tc_entry)
1641 return -ENOMEM;
1642 mall_tc_entry->cookie = cls->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001643
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001644 tcf_exts_to_list(cls->exts, &actions);
1645 a = list_first_entry(&actions, struct tc_action, list);
1646
1647 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1648 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1649
1650 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1651 mirror = &mall_tc_entry->mirror;
1652 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1653 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001654 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1655 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1656 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, cls,
1657 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001658 } else {
1659 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001660 }
1661
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001662 if (err)
1663 goto err_add_action;
1664
1665 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001666 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001667
1668err_add_action:
1669 kfree(mall_tc_entry);
1670 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001671}
1672
1673static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1674 struct tc_cls_matchall_offload *cls)
1675{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001676 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001677
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001678 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1679 cls->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001680 if (!mall_tc_entry) {
1681 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1682 return;
1683 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001684 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001685
1686 switch (mall_tc_entry->type) {
1687 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001688 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1689 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001690 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001691 case MLXSW_SP_PORT_MALL_SAMPLE:
1692 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1693 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001694 default:
1695 WARN_ON(1);
1696 }
1697
Yotam Gigi763b4b72016-07-21 12:03:17 +02001698 kfree(mall_tc_entry);
1699}
1700
1701static int mlxsw_sp_setup_tc(struct net_device *dev, u32 handle,
1702 __be16 proto, struct tc_to_netdev *tc)
1703{
1704 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1705 bool ingress = TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS);
1706
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001707 switch (tc->type) {
1708 case TC_SETUP_MATCHALL:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001709 switch (tc->cls_mall->command) {
1710 case TC_CLSMATCHALL_REPLACE:
1711 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port,
1712 proto,
1713 tc->cls_mall,
1714 ingress);
1715 case TC_CLSMATCHALL_DESTROY:
1716 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port,
1717 tc->cls_mall);
1718 return 0;
1719 default:
Or Gerlitzabbdf4b2017-03-17 09:38:01 +01001720 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001721 }
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001722 case TC_SETUP_CLSFLOWER:
1723 switch (tc->cls_flower->command) {
1724 case TC_CLSFLOWER_REPLACE:
1725 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress,
1726 proto, tc->cls_flower);
1727 case TC_CLSFLOWER_DESTROY:
1728 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress,
1729 tc->cls_flower);
1730 return 0;
Arkadi Sharshevsky7c1b8eb2017-03-11 09:42:59 +01001731 case TC_CLSFLOWER_STATS:
1732 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress,
1733 tc->cls_flower);
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001734 default:
1735 return -EOPNOTSUPP;
1736 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001737 }
1738
Yotam Gigie915ac62017-01-09 11:25:48 +01001739 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001740}
1741
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001742static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1743 .ndo_open = mlxsw_sp_port_open,
1744 .ndo_stop = mlxsw_sp_port_stop,
1745 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001746 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001747 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001748 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1749 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1750 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001751 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1752 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001753 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1754 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1755 .ndo_fdb_add = switchdev_port_fdb_add,
1756 .ndo_fdb_del = switchdev_port_fdb_del,
1757 .ndo_fdb_dump = switchdev_port_fdb_dump,
1758 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
1759 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
1760 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001761 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001762};
1763
1764static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1765 struct ethtool_drvinfo *drvinfo)
1766{
1767 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1768 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1769
1770 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1771 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1772 sizeof(drvinfo->version));
1773 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1774 "%d.%d.%d",
1775 mlxsw_sp->bus_info->fw_rev.major,
1776 mlxsw_sp->bus_info->fw_rev.minor,
1777 mlxsw_sp->bus_info->fw_rev.subminor);
1778 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1779 sizeof(drvinfo->bus_info));
1780}
1781
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001782static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1783 struct ethtool_pauseparam *pause)
1784{
1785 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1786
1787 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1788 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1789}
1790
1791static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1792 struct ethtool_pauseparam *pause)
1793{
1794 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1795
1796 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1797 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1798 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1799
1800 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1801 pfcc_pl);
1802}
1803
1804static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1805 struct ethtool_pauseparam *pause)
1806{
1807 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1808 bool pause_en = pause->tx_pause || pause->rx_pause;
1809 int err;
1810
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001811 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1812 netdev_err(dev, "PFC already enabled on port\n");
1813 return -EINVAL;
1814 }
1815
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001816 if (pause->autoneg) {
1817 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1818 return -EINVAL;
1819 }
1820
1821 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1822 if (err) {
1823 netdev_err(dev, "Failed to configure port's headroom\n");
1824 return err;
1825 }
1826
1827 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1828 if (err) {
1829 netdev_err(dev, "Failed to set PAUSE parameters\n");
1830 goto err_port_pause_configure;
1831 }
1832
1833 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1834 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1835
1836 return 0;
1837
1838err_port_pause_configure:
1839 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1840 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1841 return err;
1842}
1843
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001844struct mlxsw_sp_port_hw_stats {
1845 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001846 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001847 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001848};
1849
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001850static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001851 {
1852 .str = "a_frames_transmitted_ok",
1853 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1854 },
1855 {
1856 .str = "a_frames_received_ok",
1857 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1858 },
1859 {
1860 .str = "a_frame_check_sequence_errors",
1861 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1862 },
1863 {
1864 .str = "a_alignment_errors",
1865 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1866 },
1867 {
1868 .str = "a_octets_transmitted_ok",
1869 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1870 },
1871 {
1872 .str = "a_octets_received_ok",
1873 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1874 },
1875 {
1876 .str = "a_multicast_frames_xmitted_ok",
1877 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1878 },
1879 {
1880 .str = "a_broadcast_frames_xmitted_ok",
1881 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1882 },
1883 {
1884 .str = "a_multicast_frames_received_ok",
1885 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1886 },
1887 {
1888 .str = "a_broadcast_frames_received_ok",
1889 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1890 },
1891 {
1892 .str = "a_in_range_length_errors",
1893 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1894 },
1895 {
1896 .str = "a_out_of_range_length_field",
1897 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1898 },
1899 {
1900 .str = "a_frame_too_long_errors",
1901 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1902 },
1903 {
1904 .str = "a_symbol_error_during_carrier",
1905 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1906 },
1907 {
1908 .str = "a_mac_control_frames_transmitted",
1909 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1910 },
1911 {
1912 .str = "a_mac_control_frames_received",
1913 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1914 },
1915 {
1916 .str = "a_unsupported_opcodes_received",
1917 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1918 },
1919 {
1920 .str = "a_pause_mac_ctrl_frames_received",
1921 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1922 },
1923 {
1924 .str = "a_pause_mac_ctrl_frames_xmitted",
1925 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1926 },
1927};
1928
1929#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1930
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001931static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1932 {
1933 .str = "rx_octets_prio",
1934 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1935 },
1936 {
1937 .str = "rx_frames_prio",
1938 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1939 },
1940 {
1941 .str = "tx_octets_prio",
1942 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1943 },
1944 {
1945 .str = "tx_frames_prio",
1946 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1947 },
1948 {
1949 .str = "rx_pause_prio",
1950 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1951 },
1952 {
1953 .str = "rx_pause_duration_prio",
1954 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1955 },
1956 {
1957 .str = "tx_pause_prio",
1958 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1959 },
1960 {
1961 .str = "tx_pause_duration_prio",
1962 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1963 },
1964};
1965
1966#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1967
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001968static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1969 {
1970 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01001971 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1972 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001973 },
1974 {
1975 .str = "tc_no_buffer_discard_uc_tc",
1976 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1977 },
1978};
1979
1980#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1981
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001982#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001983 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1984 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001985 IEEE_8021QAZ_MAX_TCS)
1986
1987static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1988{
1989 int i;
1990
1991 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1992 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1993 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1994 *p += ETH_GSTRING_LEN;
1995 }
1996}
1997
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001998static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1999{
2000 int i;
2001
2002 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2003 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2004 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2005 *p += ETH_GSTRING_LEN;
2006 }
2007}
2008
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002009static void mlxsw_sp_port_get_strings(struct net_device *dev,
2010 u32 stringset, u8 *data)
2011{
2012 u8 *p = data;
2013 int i;
2014
2015 switch (stringset) {
2016 case ETH_SS_STATS:
2017 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2018 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2019 ETH_GSTRING_LEN);
2020 p += ETH_GSTRING_LEN;
2021 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002022
2023 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2024 mlxsw_sp_port_get_prio_strings(&p, i);
2025
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002026 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2027 mlxsw_sp_port_get_tc_strings(&p, i);
2028
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002029 break;
2030 }
2031}
2032
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002033static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2034 enum ethtool_phys_id_state state)
2035{
2036 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2037 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2038 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2039 bool active;
2040
2041 switch (state) {
2042 case ETHTOOL_ID_ACTIVE:
2043 active = true;
2044 break;
2045 case ETHTOOL_ID_INACTIVE:
2046 active = false;
2047 break;
2048 default:
2049 return -EOPNOTSUPP;
2050 }
2051
2052 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2053 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2054}
2055
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002056static int
2057mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2058 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2059{
2060 switch (grp) {
2061 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2062 *p_hw_stats = mlxsw_sp_port_hw_stats;
2063 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2064 break;
2065 case MLXSW_REG_PPCNT_PRIO_CNT:
2066 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2067 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2068 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002069 case MLXSW_REG_PPCNT_TC_CNT:
2070 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2071 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2072 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002073 default:
2074 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002075 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002076 }
2077 return 0;
2078}
2079
2080static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2081 enum mlxsw_reg_ppcnt_grp grp, int prio,
2082 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002083{
Ido Schimmel18281f22017-03-24 08:02:51 +01002084 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2085 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002086 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002087 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002088 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002089 int err;
2090
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002091 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2092 if (err)
2093 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002094 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002095 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002096 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002097 if (!hw_stats[i].cells_bytes)
2098 continue;
2099 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2100 data[data_index + i]);
2101 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002102}
2103
2104static void mlxsw_sp_port_get_stats(struct net_device *dev,
2105 struct ethtool_stats *stats, u64 *data)
2106{
2107 int i, data_index = 0;
2108
2109 /* IEEE 802.3 Counters */
2110 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2111 data, data_index);
2112 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2113
2114 /* Per-Priority Counters */
2115 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2116 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2117 data, data_index);
2118 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2119 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002120
2121 /* Per-TC Counters */
2122 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2123 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2124 data, data_index);
2125 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2126 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002127}
2128
2129static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2130{
2131 switch (sset) {
2132 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002133 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002134 default:
2135 return -EOPNOTSUPP;
2136 }
2137}
2138
2139struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002140 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002141 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002142 u32 speed;
2143};
2144
2145static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2146 {
2147 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002148 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2149 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002150 },
2151 {
2152 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2153 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002154 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2155 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002156 },
2157 {
2158 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002159 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2160 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002161 },
2162 {
2163 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2164 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002165 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2166 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002167 },
2168 {
2169 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2170 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2171 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2172 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002173 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2174 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002175 },
2176 {
2177 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002178 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2179 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002180 },
2181 {
2182 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002183 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2184 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002185 },
2186 {
2187 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002188 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2189 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002190 },
2191 {
2192 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002193 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2194 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002195 },
2196 {
2197 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002198 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2199 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002200 },
2201 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002202 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2203 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2204 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002205 },
2206 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002207 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2208 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2209 .speed = SPEED_25000,
2210 },
2211 {
2212 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2213 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2214 .speed = SPEED_25000,
2215 },
2216 {
2217 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2218 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2219 .speed = SPEED_25000,
2220 },
2221 {
2222 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2223 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2224 .speed = SPEED_50000,
2225 },
2226 {
2227 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2228 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2229 .speed = SPEED_50000,
2230 },
2231 {
2232 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2233 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2234 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002235 },
2236 {
2237 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002238 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2239 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002240 },
2241 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002242 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2243 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2244 .speed = SPEED_56000,
2245 },
2246 {
2247 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2248 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2249 .speed = SPEED_56000,
2250 },
2251 {
2252 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2253 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2254 .speed = SPEED_56000,
2255 },
2256 {
2257 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2258 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2259 .speed = SPEED_100000,
2260 },
2261 {
2262 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2263 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2264 .speed = SPEED_100000,
2265 },
2266 {
2267 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2268 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2269 .speed = SPEED_100000,
2270 },
2271 {
2272 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2273 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2274 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002275 },
2276};
2277
2278#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2279
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002280static void
2281mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2282 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002283{
2284 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2285 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2286 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2287 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2288 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2289 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002290 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002291
2292 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2293 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2294 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2295 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2296 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002297 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002298}
2299
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002300static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002301{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002302 int i;
2303
2304 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2305 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002306 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2307 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002308 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002309}
2310
2311static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002312 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002313{
2314 u32 speed = SPEED_UNKNOWN;
2315 u8 duplex = DUPLEX_UNKNOWN;
2316 int i;
2317
2318 if (!carrier_ok)
2319 goto out;
2320
2321 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2322 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2323 speed = mlxsw_sp_port_link_mode[i].speed;
2324 duplex = DUPLEX_FULL;
2325 break;
2326 }
2327 }
2328out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002329 cmd->base.speed = speed;
2330 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002331}
2332
2333static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2334{
2335 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2336 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2337 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2338 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2339 return PORT_FIBRE;
2340
2341 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2342 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2343 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2344 return PORT_DA;
2345
2346 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2347 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2348 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2349 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2350 return PORT_NONE;
2351
2352 return PORT_OTHER;
2353}
2354
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002355static u32
2356mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002357{
2358 u32 ptys_proto = 0;
2359 int i;
2360
2361 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002362 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2363 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002364 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2365 }
2366 return ptys_proto;
2367}
2368
2369static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2370{
2371 u32 ptys_proto = 0;
2372 int i;
2373
2374 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2375 if (speed == mlxsw_sp_port_link_mode[i].speed)
2376 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2377 }
2378 return ptys_proto;
2379}
2380
Ido Schimmel18f1e702016-02-26 17:32:31 +01002381static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2382{
2383 u32 ptys_proto = 0;
2384 int i;
2385
2386 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2387 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2388 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2389 }
2390 return ptys_proto;
2391}
2392
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002393static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2394 struct ethtool_link_ksettings *cmd)
2395{
2396 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2397 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2398 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2399
2400 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2401 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2402}
2403
2404static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2405 struct ethtool_link_ksettings *cmd)
2406{
2407 if (!autoneg)
2408 return;
2409
2410 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2411 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2412}
2413
2414static void
2415mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2416 struct ethtool_link_ksettings *cmd)
2417{
2418 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2419 return;
2420
2421 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2422 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2423}
2424
2425static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2426 struct ethtool_link_ksettings *cmd)
2427{
2428 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2429 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2430 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2431 char ptys_pl[MLXSW_REG_PTYS_LEN];
2432 u8 autoneg_status;
2433 bool autoneg;
2434 int err;
2435
2436 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002437 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002438 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2439 if (err)
2440 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002441 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2442 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002443
2444 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2445
2446 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2447
2448 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2449 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2450 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2451
2452 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2453 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2454 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2455 cmd);
2456
2457 return 0;
2458}
2459
2460static int
2461mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2462 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002463{
2464 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2465 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2466 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002467 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002468 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002469 int err;
2470
Elad Raz401c8b42016-10-28 21:35:52 +02002471 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002472 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002473 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002474 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002475 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002476
2477 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2478 eth_proto_new = autoneg ?
2479 mlxsw_sp_to_ptys_advert_link(cmd) :
2480 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002481
2482 eth_proto_new = eth_proto_new & eth_proto_cap;
2483 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002484 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002485 return -EINVAL;
2486 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002487
Elad Raz401c8b42016-10-28 21:35:52 +02002488 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2489 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002490 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002491 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002492 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002493
Ido Schimmel6277d462016-07-15 11:14:58 +02002494 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002495 return 0;
2496
Ido Schimmel0c83f882016-09-12 13:26:23 +02002497 mlxsw_sp_port->link.autoneg = autoneg;
2498
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002499 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2500 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002501
2502 return 0;
2503}
2504
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002505static int mlxsw_sp_flash_device(struct net_device *dev,
2506 struct ethtool_flash *flash)
2507{
2508 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2509 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2510 const struct firmware *firmware;
2511 int err;
2512
2513 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2514 return -EOPNOTSUPP;
2515
2516 dev_hold(dev);
2517 rtnl_unlock();
2518
2519 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2520 if (err)
2521 goto out;
2522 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2523 release_firmware(firmware);
2524out:
2525 rtnl_lock();
2526 dev_put(dev);
2527 return err;
2528}
2529
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002530static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2531 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2532 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002533 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2534 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002535 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002536 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002537 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2538 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002539 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2540 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002541 .flash_device = mlxsw_sp_flash_device,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002542};
2543
Ido Schimmel18f1e702016-02-26 17:32:31 +01002544static int
2545mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2546{
2547 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2548 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2549 char ptys_pl[MLXSW_REG_PTYS_LEN];
2550 u32 eth_proto_admin;
2551
2552 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002553 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2554 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002555 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2556}
2557
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002558int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2559 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2560 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002561{
2562 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2563 char qeec_pl[MLXSW_REG_QEEC_LEN];
2564
2565 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2566 next_index);
2567 mlxsw_reg_qeec_de_set(qeec_pl, true);
2568 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2569 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2570 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2571}
2572
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002573int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2574 enum mlxsw_reg_qeec_hr hr, u8 index,
2575 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002576{
2577 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2578 char qeec_pl[MLXSW_REG_QEEC_LEN];
2579
2580 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2581 next_index);
2582 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2583 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2584 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2585}
2586
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002587int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2588 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002589{
2590 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2591 char qtct_pl[MLXSW_REG_QTCT_LEN];
2592
2593 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2594 tclass);
2595 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2596}
2597
2598static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2599{
2600 int err, i;
2601
2602 /* Setup the elements hierarcy, so that each TC is linked to
2603 * one subgroup, which are all member in the same group.
2604 */
2605 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2606 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2607 0);
2608 if (err)
2609 return err;
2610 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2611 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2612 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2613 0, false, 0);
2614 if (err)
2615 return err;
2616 }
2617 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2618 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2619 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2620 false, 0);
2621 if (err)
2622 return err;
2623 }
2624
2625 /* Make sure the max shaper is disabled in all hierarcies that
2626 * support it.
2627 */
2628 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2629 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2630 MLXSW_REG_QEEC_MAS_DIS);
2631 if (err)
2632 return err;
2633 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2634 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2635 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2636 i, 0,
2637 MLXSW_REG_QEEC_MAS_DIS);
2638 if (err)
2639 return err;
2640 }
2641 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2642 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2643 MLXSW_REG_QEEC_HIERARCY_TC,
2644 i, i,
2645 MLXSW_REG_QEEC_MAS_DIS);
2646 if (err)
2647 return err;
2648 }
2649
2650 /* Map all priorities to traffic class 0. */
2651 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2652 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2653 if (err)
2654 return err;
2655 }
2656
2657 return 0;
2658}
2659
Jiri Pirko67963a32016-10-28 21:35:55 +02002660static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2661 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002662{
Ido Schimmelc57529e2017-05-26 08:37:31 +02002663 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002664 struct mlxsw_sp_port *mlxsw_sp_port;
2665 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002666 int err;
2667
2668 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2669 if (!dev)
2670 return -ENOMEM;
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002671 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002672 mlxsw_sp_port = netdev_priv(dev);
2673 mlxsw_sp_port->dev = dev;
2674 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2675 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02002676 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002677 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002678 mlxsw_sp_port->mapping.module = module;
2679 mlxsw_sp_port->mapping.width = width;
2680 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002681 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02002682 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002683 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002684
2685 mlxsw_sp_port->pcpu_stats =
2686 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2687 if (!mlxsw_sp_port->pcpu_stats) {
2688 err = -ENOMEM;
2689 goto err_alloc_stats;
2690 }
2691
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002692 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2693 GFP_KERNEL);
2694 if (!mlxsw_sp_port->sample) {
2695 err = -ENOMEM;
2696 goto err_alloc_sample;
2697 }
2698
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002699 mlxsw_sp_port->hw_stats.cache =
2700 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2701
2702 if (!mlxsw_sp_port->hw_stats.cache) {
2703 err = -ENOMEM;
2704 goto err_alloc_hw_stats;
2705 }
2706 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2707 &update_stats_cache);
2708
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002709 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2710 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2711
Ido Schimmel3247ff22016-09-08 08:16:02 +02002712 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2713 if (err) {
2714 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2715 mlxsw_sp_port->local_port);
2716 goto err_port_swid_set;
2717 }
2718
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002719 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2720 if (err) {
2721 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2722 mlxsw_sp_port->local_port);
2723 goto err_dev_addr_init;
2724 }
2725
2726 netif_carrier_off(dev);
2727
2728 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002729 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2730 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002731
Jarod Wilsond894be52016-10-20 13:55:16 -04002732 dev->min_mtu = 0;
2733 dev->max_mtu = ETH_MAX_MTU;
2734
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002735 /* Each packet needs to have a Tx header (metadata) on top all other
2736 * headers.
2737 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002738 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002739
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002740 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2741 if (err) {
2742 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2743 mlxsw_sp_port->local_port);
2744 goto err_port_system_port_mapping_set;
2745 }
2746
Ido Schimmel18f1e702016-02-26 17:32:31 +01002747 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2748 if (err) {
2749 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2750 mlxsw_sp_port->local_port);
2751 goto err_port_speed_by_width_set;
2752 }
2753
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002754 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2755 if (err) {
2756 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2757 mlxsw_sp_port->local_port);
2758 goto err_port_mtu_set;
2759 }
2760
2761 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2762 if (err)
2763 goto err_port_admin_status_set;
2764
2765 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2766 if (err) {
2767 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2768 mlxsw_sp_port->local_port);
2769 goto err_port_buffers_init;
2770 }
2771
Ido Schimmel90183b92016-04-06 17:10:08 +02002772 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2773 if (err) {
2774 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2775 mlxsw_sp_port->local_port);
2776 goto err_port_ets_init;
2777 }
2778
Ido Schimmelf00817d2016-04-06 17:10:09 +02002779 /* ETS and buffers must be initialized before DCB. */
2780 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2781 if (err) {
2782 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2783 mlxsw_sp_port->local_port);
2784 goto err_port_dcb_init;
2785 }
2786
Ido Schimmela1107482017-05-26 08:37:39 +02002787 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02002788 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02002789 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02002790 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002791 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02002792 }
2793
Ido Schimmelc57529e2017-05-26 08:37:31 +02002794 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
2795 if (IS_ERR(mlxsw_sp_port_vlan)) {
2796 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02002797 mlxsw_sp_port->local_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002798 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02002799 }
2800
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002801 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002802 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002803 err = register_netdev(dev);
2804 if (err) {
2805 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2806 mlxsw_sp_port->local_port);
2807 goto err_register_netdev;
2808 }
2809
Elad Razd808c7e2016-10-28 21:35:57 +02002810 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2811 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2812 module);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002813 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002814 return 0;
2815
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002816err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002817 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002818 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002819 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
2820err_port_vlan_get:
Ido Schimmela1107482017-05-26 08:37:39 +02002821 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
2822err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002823 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002824err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002825err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002826err_port_buffers_init:
2827err_port_admin_status_set:
2828err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002829err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002830err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002831err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002832 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2833err_port_swid_set:
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002834 kfree(mlxsw_sp_port->hw_stats.cache);
2835err_alloc_hw_stats:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002836 kfree(mlxsw_sp_port->sample);
2837err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002838 free_percpu(mlxsw_sp_port->pcpu_stats);
2839err_alloc_stats:
2840 free_netdev(dev);
2841 return err;
2842}
2843
Jiri Pirko67963a32016-10-28 21:35:55 +02002844static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2845 bool split, u8 module, u8 width, u8 lane)
2846{
2847 int err;
2848
2849 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2850 if (err) {
2851 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2852 local_port);
2853 return err;
2854 }
Ido Schimmel9a60c902016-12-16 19:29:03 +01002855 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, split,
Jiri Pirko67963a32016-10-28 21:35:55 +02002856 module, width, lane);
2857 if (err)
2858 goto err_port_create;
2859 return 0;
2860
2861err_port_create:
2862 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2863 return err;
2864}
2865
2866static void __mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002867{
2868 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2869
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002870 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002871 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002872 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002873 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002874 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002875 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002876 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002877 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002878 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2879 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002880 kfree(mlxsw_sp_port->hw_stats.cache);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002881 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002882 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02002883 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002884 free_netdev(mlxsw_sp_port->dev);
2885}
2886
Jiri Pirko67963a32016-10-28 21:35:55 +02002887static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2888{
2889 __mlxsw_sp_port_remove(mlxsw_sp, local_port);
2890 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2891}
2892
Jiri Pirkof83e2102016-10-28 21:35:49 +02002893static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2894{
2895 return mlxsw_sp->ports[local_port] != NULL;
2896}
2897
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002898static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2899{
2900 int i;
2901
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002902 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002903 if (mlxsw_sp_port_created(mlxsw_sp, i))
2904 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002905 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002906 kfree(mlxsw_sp->ports);
2907}
2908
2909static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2910{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002911 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02002912 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002913 size_t alloc_size;
2914 int i;
2915 int err;
2916
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002917 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002918 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2919 if (!mlxsw_sp->ports)
2920 return -ENOMEM;
2921
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002922 mlxsw_sp->port_to_module = kcalloc(max_ports, sizeof(u8), GFP_KERNEL);
2923 if (!mlxsw_sp->port_to_module) {
2924 err = -ENOMEM;
2925 goto err_port_to_module_alloc;
2926 }
2927
2928 for (i = 1; i < max_ports; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01002929 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02002930 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01002931 if (err)
2932 goto err_port_module_info_get;
2933 if (!width)
2934 continue;
2935 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02002936 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
2937 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002938 if (err)
2939 goto err_port_create;
2940 }
2941 return 0;
2942
2943err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01002944err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002945 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002946 if (mlxsw_sp_port_created(mlxsw_sp, i))
2947 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002948 kfree(mlxsw_sp->port_to_module);
2949err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002950 kfree(mlxsw_sp->ports);
2951 return err;
2952}
2953
Ido Schimmel18f1e702016-02-26 17:32:31 +01002954static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
2955{
2956 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
2957
2958 return local_port - offset;
2959}
2960
Ido Schimmelbe945352016-06-09 09:51:39 +02002961static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
2962 u8 module, unsigned int count)
2963{
2964 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
2965 int err, i;
2966
2967 for (i = 0; i < count; i++) {
2968 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
2969 width, i * width);
2970 if (err)
2971 goto err_port_module_map;
2972 }
2973
2974 for (i = 0; i < count; i++) {
2975 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
2976 if (err)
2977 goto err_port_swid_set;
2978 }
2979
2980 for (i = 0; i < count; i++) {
2981 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02002982 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02002983 if (err)
2984 goto err_port_create;
2985 }
2986
2987 return 0;
2988
2989err_port_create:
2990 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002991 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2992 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02002993 i = count;
2994err_port_swid_set:
2995 for (i--; i >= 0; i--)
2996 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
2997 MLXSW_PORT_SWID_DISABLED_PORT);
2998 i = count;
2999err_port_module_map:
3000 for (i--; i >= 0; i--)
3001 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
3002 return err;
3003}
3004
3005static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3006 u8 base_port, unsigned int count)
3007{
3008 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3009 int i;
3010
3011 /* Split by four means we need to re-create two ports, otherwise
3012 * only one.
3013 */
3014 count = count / 2;
3015
3016 for (i = 0; i < count; i++) {
3017 local_port = base_port + i * 2;
3018 module = mlxsw_sp->port_to_module[local_port];
3019
3020 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
3021 0);
3022 }
3023
3024 for (i = 0; i < count; i++)
3025 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
3026
3027 for (i = 0; i < count; i++) {
3028 local_port = base_port + i * 2;
3029 module = mlxsw_sp->port_to_module[local_port];
3030
3031 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003032 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003033 }
3034}
3035
Jiri Pirkob2f10572016-04-08 19:11:23 +02003036static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3037 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003038{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003039 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003040 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003041 u8 module, cur_width, base_port;
3042 int i;
3043 int err;
3044
3045 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3046 if (!mlxsw_sp_port) {
3047 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3048 local_port);
3049 return -EINVAL;
3050 }
3051
Ido Schimmeld664b412016-06-09 09:51:40 +02003052 module = mlxsw_sp_port->mapping.module;
3053 cur_width = mlxsw_sp_port->mapping.width;
3054
Ido Schimmel18f1e702016-02-26 17:32:31 +01003055 if (count != 2 && count != 4) {
3056 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3057 return -EINVAL;
3058 }
3059
Ido Schimmel18f1e702016-02-26 17:32:31 +01003060 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3061 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3062 return -EINVAL;
3063 }
3064
3065 /* Make sure we have enough slave (even) ports for the split. */
3066 if (count == 2) {
3067 base_port = local_port;
3068 if (mlxsw_sp->ports[base_port + 1]) {
3069 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3070 return -EINVAL;
3071 }
3072 } else {
3073 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3074 if (mlxsw_sp->ports[base_port + 1] ||
3075 mlxsw_sp->ports[base_port + 3]) {
3076 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3077 return -EINVAL;
3078 }
3079 }
3080
3081 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003082 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3083 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003084
Ido Schimmelbe945352016-06-09 09:51:39 +02003085 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3086 if (err) {
3087 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3088 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003089 }
3090
3091 return 0;
3092
Ido Schimmelbe945352016-06-09 09:51:39 +02003093err_port_split_create:
3094 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003095 return err;
3096}
3097
Jiri Pirkob2f10572016-04-08 19:11:23 +02003098static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003099{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003100 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003101 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003102 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003103 unsigned int count;
3104 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003105
3106 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3107 if (!mlxsw_sp_port) {
3108 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3109 local_port);
3110 return -EINVAL;
3111 }
3112
3113 if (!mlxsw_sp_port->split) {
3114 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3115 return -EINVAL;
3116 }
3117
Ido Schimmeld664b412016-06-09 09:51:40 +02003118 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003119 count = cur_width == 1 ? 4 : 2;
3120
3121 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3122
3123 /* Determine which ports to remove. */
3124 if (count == 2 && local_port >= base_port + 2)
3125 base_port = base_port + 2;
3126
3127 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003128 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3129 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003130
Ido Schimmelbe945352016-06-09 09:51:39 +02003131 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003132
3133 return 0;
3134}
3135
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003136static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3137 char *pude_pl, void *priv)
3138{
3139 struct mlxsw_sp *mlxsw_sp = priv;
3140 struct mlxsw_sp_port *mlxsw_sp_port;
3141 enum mlxsw_reg_pude_oper_status status;
3142 u8 local_port;
3143
3144 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3145 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003146 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003147 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003148
3149 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3150 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3151 netdev_info(mlxsw_sp_port->dev, "link up\n");
3152 netif_carrier_on(mlxsw_sp_port->dev);
3153 } else {
3154 netdev_info(mlxsw_sp_port->dev, "link down\n");
3155 netif_carrier_off(mlxsw_sp_port->dev);
3156 }
3157}
3158
Nogah Frankel14eeda92016-11-25 10:33:32 +01003159static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3160 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003161{
3162 struct mlxsw_sp *mlxsw_sp = priv;
3163 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3164 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3165
3166 if (unlikely(!mlxsw_sp_port)) {
3167 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3168 local_port);
3169 return;
3170 }
3171
3172 skb->dev = mlxsw_sp_port->dev;
3173
3174 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3175 u64_stats_update_begin(&pcpu_stats->syncp);
3176 pcpu_stats->rx_packets++;
3177 pcpu_stats->rx_bytes += skb->len;
3178 u64_stats_update_end(&pcpu_stats->syncp);
3179
3180 skb->protocol = eth_type_trans(skb, skb->dev);
3181 netif_receive_skb(skb);
3182}
3183
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003184static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3185 void *priv)
3186{
3187 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003188 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003189}
3190
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003191static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3192 void *priv)
3193{
3194 struct mlxsw_sp *mlxsw_sp = priv;
3195 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3196 struct psample_group *psample_group;
3197 u32 size;
3198
3199 if (unlikely(!mlxsw_sp_port)) {
3200 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3201 local_port);
3202 goto out;
3203 }
3204 if (unlikely(!mlxsw_sp_port->sample)) {
3205 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3206 local_port);
3207 goto out;
3208 }
3209
3210 size = mlxsw_sp_port->sample->truncate ?
3211 mlxsw_sp_port->sample->trunc_size : skb->len;
3212
3213 rcu_read_lock();
3214 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3215 if (!psample_group)
3216 goto out_unlock;
3217 psample_sample_packet(psample_group, skb, size,
3218 mlxsw_sp_port->dev->ifindex, 0,
3219 mlxsw_sp_port->sample->rate);
3220out_unlock:
3221 rcu_read_unlock();
3222out:
3223 consume_skb(skb);
3224}
3225
Nogah Frankel117b0da2016-11-25 10:33:44 +01003226#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003227 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003228 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003229
Nogah Frankel117b0da2016-11-25 10:33:44 +01003230#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003231 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003232 _is_ctrl, SP_##_trap_group, DISCARD)
3233
3234#define MLXSW_SP_EVENTL(_func, _trap_id) \
3235 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003236
Nogah Frankel45449132016-11-25 10:33:35 +01003237static const struct mlxsw_listener mlxsw_sp_listener[] = {
3238 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003239 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003240 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003241 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3242 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3243 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3244 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3245 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3246 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3247 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3248 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3249 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3250 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3251 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003252 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003253 /* L3 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003254 MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3255 MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3256 MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3257 MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, OSPF, false),
3258 MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
3259 MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
3260 MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, ARP_MISS, false),
3261 MLXSW_SP_RXL_NO_MARK(BGP_IPV4, TRAP_TO_CPU, BGP_IPV4, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003262 /* PKT Sample trap */
3263 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003264 false, SP_IP2ME, DISCARD),
3265 /* ACL trap */
3266 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003267};
3268
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003269static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3270{
3271 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3272 enum mlxsw_reg_qpcr_ir_units ir_units;
3273 int max_cpu_policers;
3274 bool is_bytes;
3275 u8 burst_size;
3276 u32 rate;
3277 int i, err;
3278
3279 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3280 return -EIO;
3281
3282 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3283
3284 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3285 for (i = 0; i < max_cpu_policers; i++) {
3286 is_bytes = false;
3287 switch (i) {
3288 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3289 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3290 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3291 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3292 rate = 128;
3293 burst_size = 7;
3294 break;
3295 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3296 rate = 16 * 1024;
3297 burst_size = 10;
3298 break;
3299 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3300 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3301 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3302 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3303 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3304 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3305 rate = 1024;
3306 burst_size = 7;
3307 break;
3308 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3309 is_bytes = true;
3310 rate = 4 * 1024;
3311 burst_size = 4;
3312 break;
3313 default:
3314 continue;
3315 }
3316
3317 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3318 burst_size);
3319 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3320 if (err)
3321 return err;
3322 }
3323
3324 return 0;
3325}
3326
Nogah Frankel579c82e2016-11-25 10:33:42 +01003327static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003328{
3329 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003330 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003331 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003332 int max_trap_groups;
3333 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003334 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003335 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003336
3337 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3338 return -EIO;
3339
3340 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003341 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003342
3343 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003344 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003345 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003346 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3347 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3348 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3349 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3350 priority = 5;
3351 tc = 5;
3352 break;
3353 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3354 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3355 priority = 4;
3356 tc = 4;
3357 break;
3358 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3359 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3360 priority = 3;
3361 tc = 3;
3362 break;
3363 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3364 priority = 2;
3365 tc = 2;
3366 break;
3367 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3368 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3369 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3370 priority = 1;
3371 tc = 1;
3372 break;
3373 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003374 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3375 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003376 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003377 break;
3378 default:
3379 continue;
3380 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003381
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003382 if (max_cpu_policers <= policer_id &&
3383 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3384 return -EIO;
3385
3386 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003387 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3388 if (err)
3389 return err;
3390 }
3391
3392 return 0;
3393}
3394
3395static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3396{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003397 int i;
3398 int err;
3399
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003400 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3401 if (err)
3402 return err;
3403
Nogah Frankel579c82e2016-11-25 10:33:42 +01003404 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003405 if (err)
3406 return err;
3407
Nogah Frankel45449132016-11-25 10:33:35 +01003408 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003409 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003410 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003411 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003412 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003413 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003414
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003415 }
3416 return 0;
3417
Nogah Frankel45449132016-11-25 10:33:35 +01003418err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003419 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003420 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003421 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003422 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003423 }
3424 return err;
3425}
3426
3427static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3428{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003429 int i;
3430
Nogah Frankel45449132016-11-25 10:33:35 +01003431 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003432 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003433 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003434 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003435 }
3436}
3437
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003438static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3439{
3440 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003441 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003442
3443 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3444 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3445 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3446 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3447 MLXSW_REG_SLCR_LAG_HASH_SIP |
3448 MLXSW_REG_SLCR_LAG_HASH_DIP |
3449 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3450 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3451 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003452 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3453 if (err)
3454 return err;
3455
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003456 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3457 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003458 return -EIO;
3459
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003460 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003461 sizeof(struct mlxsw_sp_upper),
3462 GFP_KERNEL);
3463 if (!mlxsw_sp->lags)
3464 return -ENOMEM;
3465
3466 return 0;
3467}
3468
3469static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3470{
3471 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003472}
3473
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003474static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3475{
3476 char htgt_pl[MLXSW_REG_HTGT_LEN];
3477
Nogah Frankel579c82e2016-11-25 10:33:42 +01003478 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3479 MLXSW_REG_HTGT_INVALID_POLICER,
3480 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3481 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003482 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3483}
3484
Jiri Pirkob2f10572016-04-08 19:11:23 +02003485static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003486 const struct mlxsw_bus_info *mlxsw_bus_info)
3487{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003488 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003489 int err;
3490
3491 mlxsw_sp->core = mlxsw_core;
3492 mlxsw_sp->bus_info = mlxsw_bus_info;
3493
Yotam Gigi6b742192017-05-23 21:56:29 +02003494 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3495 if (err) {
3496 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3497 return err;
3498 }
3499
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003500 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3501 if (err) {
3502 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3503 return err;
3504 }
3505
Ido Schimmela1107482017-05-26 08:37:39 +02003506 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003507 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003508 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Nogah Frankel45449132016-11-25 10:33:35 +01003509 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003510 }
3511
Ido Schimmela1107482017-05-26 08:37:39 +02003512 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003513 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003514 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3515 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003516 }
3517
3518 err = mlxsw_sp_buffers_init(mlxsw_sp);
3519 if (err) {
3520 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3521 goto err_buffers_init;
3522 }
3523
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003524 err = mlxsw_sp_lag_init(mlxsw_sp);
3525 if (err) {
3526 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3527 goto err_lag_init;
3528 }
3529
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003530 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3531 if (err) {
3532 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3533 goto err_switchdev_init;
3534 }
3535
Ido Schimmel464dce12016-07-02 11:00:15 +02003536 err = mlxsw_sp_router_init(mlxsw_sp);
3537 if (err) {
3538 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3539 goto err_router_init;
3540 }
3541
Yotam Gigi763b4b72016-07-21 12:03:17 +02003542 err = mlxsw_sp_span_init(mlxsw_sp);
3543 if (err) {
3544 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3545 goto err_span_init;
3546 }
3547
Jiri Pirko22a67762017-02-03 10:29:07 +01003548 err = mlxsw_sp_acl_init(mlxsw_sp);
3549 if (err) {
3550 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3551 goto err_acl_init;
3552 }
3553
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003554 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3555 if (err) {
3556 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3557 goto err_counter_pool_init;
3558 }
3559
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003560 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3561 if (err) {
3562 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3563 goto err_dpipe_init;
3564 }
3565
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003566 err = mlxsw_sp_ports_create(mlxsw_sp);
3567 if (err) {
3568 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3569 goto err_ports_create;
3570 }
3571
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003572 return 0;
3573
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003574err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003575 mlxsw_sp_dpipe_fini(mlxsw_sp);
3576err_dpipe_init:
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003577 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3578err_counter_pool_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003579 mlxsw_sp_acl_fini(mlxsw_sp);
3580err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02003581 mlxsw_sp_span_fini(mlxsw_sp);
3582err_span_init:
Ido Schimmel464dce12016-07-02 11:00:15 +02003583 mlxsw_sp_router_fini(mlxsw_sp);
3584err_router_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003585 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003586err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003587 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003588err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003589 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003590err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003591 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003592err_traps_init:
3593 mlxsw_sp_fids_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003594 return err;
3595}
3596
Jiri Pirkob2f10572016-04-08 19:11:23 +02003597static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003598{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003599 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003600
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003601 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003602 mlxsw_sp_dpipe_fini(mlxsw_sp);
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003603 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003604 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003605 mlxsw_sp_span_fini(mlxsw_sp);
Ido Schimmel464dce12016-07-02 11:00:15 +02003606 mlxsw_sp_router_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003607 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003608 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003609 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003610 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003611 mlxsw_sp_fids_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003612}
3613
3614static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3615 .used_max_vepa_channels = 1,
3616 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003617 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003618 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003619 .used_max_pgt = 1,
3620 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003621 .used_flood_tables = 1,
3622 .used_flood_mode = 1,
3623 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003624 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003625 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003626 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02003627 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003628 .used_max_ib_mc = 1,
3629 .max_ib_mc = 0,
3630 .used_max_pkey = 1,
3631 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003632 .used_kvd_split_data = 1,
3633 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3634 .kvd_hash_single_parts = 2,
3635 .kvd_hash_double_parts = 1,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003636 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003637 .swid_config = {
3638 {
3639 .used_type = 1,
3640 .type = MLXSW_PORT_SWID_TYPE_ETH,
3641 }
3642 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003643 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003644};
3645
3646static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003647 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003648 .priv_size = sizeof(struct mlxsw_sp),
3649 .init = mlxsw_sp_init,
3650 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003651 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003652 .port_split = mlxsw_sp_port_split,
3653 .port_unsplit = mlxsw_sp_port_unsplit,
3654 .sb_pool_get = mlxsw_sp_sb_pool_get,
3655 .sb_pool_set = mlxsw_sp_sb_pool_set,
3656 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3657 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3658 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3659 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3660 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3661 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3662 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3663 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3664 .txhdr_construct = mlxsw_sp_txhdr_construct,
3665 .txhdr_len = MLXSW_TXHDR_LEN,
3666 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003667};
3668
Jiri Pirko22a67762017-02-03 10:29:07 +01003669bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003670{
3671 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3672}
3673
Jiri Pirko1182e532017-03-06 21:25:20 +01003674static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07003675{
Jiri Pirko1182e532017-03-06 21:25:20 +01003676 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07003677 int ret = 0;
3678
3679 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01003680 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07003681 ret = 1;
3682 }
3683
3684 return ret;
3685}
3686
Ido Schimmelc57529e2017-05-26 08:37:31 +02003687struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003688{
Jiri Pirko1182e532017-03-06 21:25:20 +01003689 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003690
3691 if (mlxsw_sp_port_dev_check(dev))
3692 return netdev_priv(dev);
3693
Jiri Pirko1182e532017-03-06 21:25:20 +01003694 mlxsw_sp_port = NULL;
3695 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003696
Jiri Pirko1182e532017-03-06 21:25:20 +01003697 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003698}
3699
Ido Schimmel4724ba562017-03-10 08:53:39 +01003700struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003701{
3702 struct mlxsw_sp_port *mlxsw_sp_port;
3703
3704 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3705 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3706}
3707
3708static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
3709{
Jiri Pirko1182e532017-03-06 21:25:20 +01003710 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003711
3712 if (mlxsw_sp_port_dev_check(dev))
3713 return netdev_priv(dev);
3714
Jiri Pirko1182e532017-03-06 21:25:20 +01003715 mlxsw_sp_port = NULL;
3716 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
3717 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003718
Jiri Pirko1182e532017-03-06 21:25:20 +01003719 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003720}
3721
3722struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3723{
3724 struct mlxsw_sp_port *mlxsw_sp_port;
3725
3726 rcu_read_lock();
3727 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3728 if (mlxsw_sp_port)
3729 dev_hold(mlxsw_sp_port->dev);
3730 rcu_read_unlock();
3731 return mlxsw_sp_port;
3732}
3733
3734void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3735{
3736 dev_put(mlxsw_sp_port->dev);
3737}
3738
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003739static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003740{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003741 char sldr_pl[MLXSW_REG_SLDR_LEN];
3742
3743 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3744 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3745}
3746
3747static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3748{
3749 char sldr_pl[MLXSW_REG_SLDR_LEN];
3750
3751 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3752 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3753}
3754
3755static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3756 u16 lag_id, u8 port_index)
3757{
3758 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3759 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3760
3761 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
3762 lag_id, port_index);
3763 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3764}
3765
3766static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3767 u16 lag_id)
3768{
3769 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3770 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3771
3772 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
3773 lag_id);
3774 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3775}
3776
3777static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
3778 u16 lag_id)
3779{
3780 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3781 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3782
3783 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
3784 lag_id);
3785 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3786}
3787
3788static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
3789 u16 lag_id)
3790{
3791 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3792 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3793
3794 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
3795 lag_id);
3796 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3797}
3798
3799static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3800 struct net_device *lag_dev,
3801 u16 *p_lag_id)
3802{
3803 struct mlxsw_sp_upper *lag;
3804 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003805 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003806 int i;
3807
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003808 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
3809 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003810 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
3811 if (lag->ref_count) {
3812 if (lag->dev == lag_dev) {
3813 *p_lag_id = i;
3814 return 0;
3815 }
3816 } else if (free_lag_id < 0) {
3817 free_lag_id = i;
3818 }
3819 }
3820 if (free_lag_id < 0)
3821 return -EBUSY;
3822 *p_lag_id = free_lag_id;
3823 return 0;
3824}
3825
3826static bool
3827mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
3828 struct net_device *lag_dev,
3829 struct netdev_lag_upper_info *lag_upper_info)
3830{
3831 u16 lag_id;
3832
3833 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
3834 return false;
3835 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
3836 return false;
3837 return true;
3838}
3839
3840static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3841 u16 lag_id, u8 *p_port_index)
3842{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003843 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003844 int i;
3845
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003846 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3847 MAX_LAG_MEMBERS);
3848 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003849 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
3850 *p_port_index = i;
3851 return 0;
3852 }
3853 }
3854 return -EBUSY;
3855}
3856
3857static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
3858 struct net_device *lag_dev)
3859{
3860 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02003861 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003862 struct mlxsw_sp_upper *lag;
3863 u16 lag_id;
3864 u8 port_index;
3865 int err;
3866
3867 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
3868 if (err)
3869 return err;
3870 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3871 if (!lag->ref_count) {
3872 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
3873 if (err)
3874 return err;
3875 lag->dev = lag_dev;
3876 }
3877
3878 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
3879 if (err)
3880 return err;
3881 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
3882 if (err)
3883 goto err_col_port_add;
3884 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
3885 if (err)
3886 goto err_col_port_enable;
3887
3888 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
3889 mlxsw_sp_port->local_port);
3890 mlxsw_sp_port->lag_id = lag_id;
3891 mlxsw_sp_port->lagged = 1;
3892 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003893
Ido Schimmelc57529e2017-05-26 08:37:31 +02003894 /* Port is no longer usable as a router interface */
3895 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
3896 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02003897 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003898
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003899 return 0;
3900
Ido Schimmel51554db2016-05-06 22:18:39 +02003901err_col_port_enable:
3902 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003903err_col_port_add:
3904 if (!lag->ref_count)
3905 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003906 return err;
3907}
3908
Ido Schimmel82e6db02016-06-20 23:04:04 +02003909static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
3910 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003911{
3912 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003913 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02003914 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003915
3916 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02003917 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003918 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3919 WARN_ON(lag->ref_count == 0);
3920
Ido Schimmel82e6db02016-06-20 23:04:04 +02003921 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
3922 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003923
Ido Schimmelc57529e2017-05-26 08:37:31 +02003924 /* Any VLANs configured on the port are no longer valid */
3925 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01003926
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003927 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02003928 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003929
3930 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
3931 mlxsw_sp_port->local_port);
3932 mlxsw_sp_port->lagged = 0;
3933 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003934
Ido Schimmelc57529e2017-05-26 08:37:31 +02003935 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3936 /* Make sure untagged frames are allowed to ingress */
3937 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003938}
3939
Jiri Pirko74581202015-12-03 12:12:30 +01003940static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3941 u16 lag_id)
3942{
3943 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3944 char sldr_pl[MLXSW_REG_SLDR_LEN];
3945
3946 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
3947 mlxsw_sp_port->local_port);
3948 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3949}
3950
3951static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3952 u16 lag_id)
3953{
3954 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3955 char sldr_pl[MLXSW_REG_SLDR_LEN];
3956
3957 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
3958 mlxsw_sp_port->local_port);
3959 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3960}
3961
3962static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
3963 bool lag_tx_enabled)
3964{
3965 if (lag_tx_enabled)
3966 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
3967 mlxsw_sp_port->lag_id);
3968 else
3969 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
3970 mlxsw_sp_port->lag_id);
3971}
3972
3973static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
3974 struct netdev_lag_lower_state_info *info)
3975{
3976 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
3977}
3978
Jiri Pirko2b94e582017-04-18 16:55:37 +02003979static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
3980 bool enable)
3981{
3982 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3983 enum mlxsw_reg_spms_state spms_state;
3984 char *spms_pl;
3985 u16 vid;
3986 int err;
3987
3988 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
3989 MLXSW_REG_SPMS_STATE_DISCARDING;
3990
3991 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
3992 if (!spms_pl)
3993 return -ENOMEM;
3994 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
3995
3996 for (vid = 0; vid < VLAN_N_VID; vid++)
3997 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
3998
3999 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4000 kfree(spms_pl);
4001 return err;
4002}
4003
4004static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4005{
4006 int err;
4007
Ido Schimmel4aafc362017-05-26 08:37:25 +02004008 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004009 if (err)
4010 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004011 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4012 if (err)
4013 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004014 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4015 true, false);
4016 if (err)
4017 goto err_port_vlan_set;
4018 return 0;
4019
4020err_port_vlan_set:
4021 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004022err_port_stp_set:
4023 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004024 return err;
4025}
4026
4027static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4028{
4029 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4030 false, false);
4031 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004032 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004033}
4034
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004035static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4036 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004037 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004038{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004039 struct netdev_notifier_changeupper_info *info;
4040 struct mlxsw_sp_port *mlxsw_sp_port;
4041 struct net_device *upper_dev;
4042 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004043 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004044
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004045 mlxsw_sp_port = netdev_priv(dev);
4046 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4047 info = ptr;
4048
4049 switch (event) {
4050 case NETDEV_PRECHANGEUPPER:
4051 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004052 if (!is_vlan_dev(upper_dev) &&
4053 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004054 !netif_is_bridge_master(upper_dev) &&
Jiri Pirko2b94e582017-04-18 16:55:37 +02004055 !netif_is_ovs_master(upper_dev))
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004056 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004057 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004058 break;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004059 if (netif_is_lag_master(upper_dev) &&
4060 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4061 info->upper_info))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004062 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004063 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4064 return -EINVAL;
4065 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4066 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4067 return -EINVAL;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004068 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev))
4069 return -EINVAL;
4070 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev))
4071 return -EINVAL;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004072 break;
4073 case NETDEV_CHANGEUPPER:
4074 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004075 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004076 if (info->linking)
4077 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004078 lower_dev,
Ido Schimmel7117a572016-06-20 23:04:06 +02004079 upper_dev);
4080 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004081 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4082 lower_dev,
4083 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004084 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004085 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004086 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4087 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004088 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004089 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4090 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004091 } else if (netif_is_ovs_master(upper_dev)) {
4092 if (info->linking)
4093 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4094 else
4095 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004096 }
4097 break;
4098 }
4099
Ido Schimmel80bedf12016-06-20 23:03:59 +02004100 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004101}
4102
Jiri Pirko74581202015-12-03 12:12:30 +01004103static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4104 unsigned long event, void *ptr)
4105{
4106 struct netdev_notifier_changelowerstate_info *info;
4107 struct mlxsw_sp_port *mlxsw_sp_port;
4108 int err;
4109
4110 mlxsw_sp_port = netdev_priv(dev);
4111 info = ptr;
4112
4113 switch (event) {
4114 case NETDEV_CHANGELOWERSTATE:
4115 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4116 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4117 info->lower_state_info);
4118 if (err)
4119 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4120 }
4121 break;
4122 }
4123
Ido Schimmel80bedf12016-06-20 23:03:59 +02004124 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004125}
4126
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004127static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4128 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004129 unsigned long event, void *ptr)
4130{
4131 switch (event) {
4132 case NETDEV_PRECHANGEUPPER:
4133 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004134 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4135 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004136 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004137 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4138 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004139 }
4140
Ido Schimmel80bedf12016-06-20 23:03:59 +02004141 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004142}
4143
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004144static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4145 unsigned long event, void *ptr)
4146{
4147 struct net_device *dev;
4148 struct list_head *iter;
4149 int ret;
4150
4151 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4152 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004153 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4154 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004155 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004156 return ret;
4157 }
4158 }
4159
Ido Schimmel80bedf12016-06-20 23:03:59 +02004160 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004161}
4162
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004163static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4164 struct net_device *dev,
4165 unsigned long event, void *ptr,
4166 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004167{
4168 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4169 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004170 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004171 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004172
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004173 switch (event) {
4174 case NETDEV_PRECHANGEUPPER:
4175 upper_dev = info->upper_dev;
Ido Schimmelb1e45522017-04-30 19:47:14 +03004176 if (!netif_is_bridge_master(upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004177 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004178 break;
4179 case NETDEV_CHANGEUPPER:
4180 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004181 if (netif_is_bridge_master(upper_dev)) {
4182 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004183 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4184 vlan_dev,
4185 upper_dev);
Ido Schimmel1f880612017-03-10 08:53:35 +01004186 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004187 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4188 vlan_dev,
4189 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004190 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004191 err = -EINVAL;
4192 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004193 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004194 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004195 }
4196
Ido Schimmel80bedf12016-06-20 23:03:59 +02004197 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004198}
4199
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004200static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4201 struct net_device *lag_dev,
4202 unsigned long event,
4203 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004204{
4205 struct net_device *dev;
4206 struct list_head *iter;
4207 int ret;
4208
4209 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4210 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004211 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4212 event, ptr,
4213 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004214 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004215 return ret;
4216 }
4217 }
4218
Ido Schimmel80bedf12016-06-20 23:03:59 +02004219 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004220}
4221
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004222static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4223 unsigned long event, void *ptr)
4224{
4225 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4226 u16 vid = vlan_dev_vlan_id(vlan_dev);
4227
Ido Schimmel272c4472015-12-15 16:03:47 +01004228 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004229 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4230 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01004231 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004232 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4233 real_dev, event,
4234 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004235
Ido Schimmel80bedf12016-06-20 23:03:59 +02004236 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004237}
4238
Ido Schimmelb1e45522017-04-30 19:47:14 +03004239static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4240{
4241 struct netdev_notifier_changeupper_info *info = ptr;
4242
4243 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4244 return false;
4245 return netif_is_l3_master(info->upper_dev);
4246}
4247
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004248static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4249 unsigned long event, void *ptr)
4250{
4251 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004252 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004253
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004254 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4255 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004256 else if (mlxsw_sp_is_vrf_event(event, ptr))
4257 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004258 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004259 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004260 else if (netif_is_lag_master(dev))
4261 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4262 else if (is_vlan_dev(dev))
4263 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004264
Ido Schimmel80bedf12016-06-20 23:03:59 +02004265 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004266}
4267
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004268static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4269 .notifier_call = mlxsw_sp_netdevice_event,
4270};
4271
Ido Schimmel99724c12016-07-04 08:23:14 +02004272static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4273 .notifier_call = mlxsw_sp_inetaddr_event,
4274 .priority = 10, /* Must be called before FIB notifier block */
4275};
4276
Jiri Pirkoe7322632016-09-01 10:37:43 +02004277static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4278 .notifier_call = mlxsw_sp_router_netevent_event,
4279};
4280
Jiri Pirko1d20d232016-10-27 15:12:59 +02004281static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4282 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4283 {0, },
4284};
4285
4286static struct pci_driver mlxsw_sp_pci_driver = {
4287 .name = mlxsw_sp_driver_name,
4288 .id_table = mlxsw_sp_pci_id_table,
4289};
4290
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004291static int __init mlxsw_sp_module_init(void)
4292{
4293 int err;
4294
4295 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004296 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004297 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4298
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004299 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4300 if (err)
4301 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004302
4303 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4304 if (err)
4305 goto err_pci_driver_register;
4306
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004307 return 0;
4308
Jiri Pirko1d20d232016-10-27 15:12:59 +02004309err_pci_driver_register:
4310 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004311err_core_driver_register:
Jiri Pirkoe7322632016-09-01 10:37:43 +02004312 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004313 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004314 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4315 return err;
4316}
4317
4318static void __exit mlxsw_sp_module_exit(void)
4319{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004320 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004321 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004322 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004323 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004324 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4325}
4326
4327module_init(mlxsw_sp_module_init);
4328module_exit(mlxsw_sp_module_exit);
4329
4330MODULE_LICENSE("Dual BSD/GPL");
4331MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4332MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004333MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02004334MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);