blob: 6f5f01151c4948936e371a734ffd181efa500ea9 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020056#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020057#include <net/pkt_cls.h>
58#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020059#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010060#include <net/tc_act/tc_sample.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020061
62#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020063#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020064#include "core.h"
65#include "reg.h"
66#include "port.h"
67#include "trap.h"
68#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010069#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020070#include "spectrum_dpipe.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020071#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020072
Yotam Gigi6b742192017-05-23 21:56:29 +020073#define MLXSW_FWREV_MAJOR 13
74#define MLXSW_FWREV_MINOR 1420
75#define MLXSW_FWREV_SUBMINOR 122
76
77static const struct mlxsw_fw_rev mlxsw_sp_supported_fw_rev = {
78 .major = MLXSW_FWREV_MAJOR,
79 .minor = MLXSW_FWREV_MINOR,
80 .subminor = MLXSW_FWREV_SUBMINOR
81};
82
83#define MLXSW_SP_FW_FILENAME \
84 "mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
85 "." __stringify(MLXSW_FWREV_MINOR) \
86 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
87
Jiri Pirko56ade8f2015-10-16 14:01:37 +020088static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
89static const char mlxsw_sp_driver_version[] = "1.0";
90
91/* tx_hdr_version
92 * Tx header version.
93 * Must be set to 1.
94 */
95MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
96
97/* tx_hdr_ctl
98 * Packet control type.
99 * 0 - Ethernet control (e.g. EMADs, LACP)
100 * 1 - Ethernet data
101 */
102MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
103
104/* tx_hdr_proto
105 * Packet protocol type. Must be set to 1 (Ethernet).
106 */
107MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
108
109/* tx_hdr_rx_is_router
110 * Packet is sent from the router. Valid for data packets only.
111 */
112MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
113
114/* tx_hdr_fid_valid
115 * Indicates if the 'fid' field is valid and should be used for
116 * forwarding lookup. Valid for data packets only.
117 */
118MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
119
120/* tx_hdr_swid
121 * Switch partition ID. Must be set to 0.
122 */
123MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
124
125/* tx_hdr_control_tclass
126 * Indicates if the packet should use the control TClass and not one
127 * of the data TClasses.
128 */
129MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
130
131/* tx_hdr_etclass
132 * Egress TClass to be used on the egress device on the egress port.
133 */
134MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
135
136/* tx_hdr_port_mid
137 * Destination local port for unicast packets.
138 * Destination multicast ID for multicast packets.
139 *
140 * Control packets are directed to a specific egress port, while data
141 * packets are transmitted through the CPU port (0) into the switch partition,
142 * where forwarding rules are applied.
143 */
144MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
145
146/* tx_hdr_fid
147 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
148 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
149 * Valid for data packets only.
150 */
151MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
152
153/* tx_hdr_type
154 * 0 - Data packets
155 * 6 - Control packets
156 */
157MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
158
Yotam Gigie5e5c882017-05-23 21:56:27 +0200159struct mlxsw_sp_mlxfw_dev {
160 struct mlxfw_dev mlxfw_dev;
161 struct mlxsw_sp *mlxsw_sp;
162};
163
164static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
165 u16 component_index, u32 *p_max_size,
166 u8 *p_align_bits, u16 *p_max_write_size)
167{
168 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
169 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
170 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
171 char mcqi_pl[MLXSW_REG_MCQI_LEN];
172 int err;
173
174 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
175 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
176 if (err)
177 return err;
178 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
179 p_max_write_size);
180
181 *p_align_bits = max_t(u8, *p_align_bits, 2);
182 *p_max_write_size = min_t(u16, *p_max_write_size,
183 MLXSW_REG_MCDA_MAX_DATA_LEN);
184 return 0;
185}
186
187static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
188{
189 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
190 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
191 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
192 char mcc_pl[MLXSW_REG_MCC_LEN];
193 u8 control_state;
194 int err;
195
196 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
197 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
198 if (err)
199 return err;
200
201 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
202 if (control_state != MLXFW_FSM_STATE_IDLE)
203 return -EBUSY;
204
205 mlxsw_reg_mcc_pack(mcc_pl,
206 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
207 0, *fwhandle, 0);
208 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
209}
210
211static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
212 u32 fwhandle, u16 component_index,
213 u32 component_size)
214{
215 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
216 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
217 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
218 char mcc_pl[MLXSW_REG_MCC_LEN];
219
220 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
221 component_index, fwhandle, component_size);
222 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
223}
224
225static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
226 u32 fwhandle, u8 *data, u16 size,
227 u32 offset)
228{
229 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
230 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
231 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
232 char mcda_pl[MLXSW_REG_MCDA_LEN];
233
234 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
235 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
236}
237
238static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
239 u32 fwhandle, u16 component_index)
240{
241 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
242 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
243 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
244 char mcc_pl[MLXSW_REG_MCC_LEN];
245
246 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
247 component_index, fwhandle, 0);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
249}
250
251static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
252{
253 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
254 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
255 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
256 char mcc_pl[MLXSW_REG_MCC_LEN];
257
258 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
259 fwhandle, 0);
260 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
261}
262
263static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
264 enum mlxfw_fsm_state *fsm_state,
265 enum mlxfw_fsm_state_err *fsm_state_err)
266{
267 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
268 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
269 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
270 char mcc_pl[MLXSW_REG_MCC_LEN];
271 u8 control_state;
272 u8 error_code;
273 int err;
274
275 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
276 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
277 if (err)
278 return err;
279
280 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
281 *fsm_state = control_state;
282 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
283 MLXFW_FSM_STATE_ERR_MAX);
284 return 0;
285}
286
287static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
288{
289 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
290 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
291 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
292 char mcc_pl[MLXSW_REG_MCC_LEN];
293
294 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
295 fwhandle, 0);
296 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
297}
298
299static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
300{
301 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
302 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
303 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
304 char mcc_pl[MLXSW_REG_MCC_LEN];
305
306 mlxsw_reg_mcc_pack(mcc_pl,
307 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
308 fwhandle, 0);
309 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
310}
311
312static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
313 .component_query = mlxsw_sp_component_query,
314 .fsm_lock = mlxsw_sp_fsm_lock,
315 .fsm_component_update = mlxsw_sp_fsm_component_update,
316 .fsm_block_download = mlxsw_sp_fsm_block_download,
317 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
318 .fsm_activate = mlxsw_sp_fsm_activate,
319 .fsm_query_state = mlxsw_sp_fsm_query_state,
320 .fsm_cancel = mlxsw_sp_fsm_cancel,
321 .fsm_release = mlxsw_sp_fsm_release
322};
323
Yotam Gigi6b742192017-05-23 21:56:29 +0200324static bool mlxsw_sp_fw_rev_ge(const struct mlxsw_fw_rev *a,
325 const struct mlxsw_fw_rev *b)
326{
327 if (a->major != b->major)
328 return a->major > b->major;
329 if (a->minor != b->minor)
330 return a->minor > b->minor;
331 return a->subminor >= b->subminor;
332}
333
334static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
335{
336 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
337 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
338 .mlxfw_dev = {
339 .ops = &mlxsw_sp_mlxfw_dev_ops,
340 .psid = mlxsw_sp->bus_info->psid,
341 .psid_size = strlen(mlxsw_sp->bus_info->psid),
342 },
343 .mlxsw_sp = mlxsw_sp
344 };
345 const struct firmware *firmware;
346 int err;
347
348 if (mlxsw_sp_fw_rev_ge(rev, &mlxsw_sp_supported_fw_rev))
349 return 0;
350
351 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d out of data\n",
352 rev->major, rev->minor, rev->subminor);
353 dev_info(mlxsw_sp->bus_info->dev, "Upgrading firmware using file %s\n",
354 MLXSW_SP_FW_FILENAME);
355
356 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
357 mlxsw_sp->bus_info->dev);
358 if (err) {
359 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
360 MLXSW_SP_FW_FILENAME);
361 return err;
362 }
363
364 err = mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
365 release_firmware(firmware);
366 return err;
367}
368
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100369int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
370 unsigned int counter_index, u64 *packets,
371 u64 *bytes)
372{
373 char mgpc_pl[MLXSW_REG_MGPC_LEN];
374 int err;
375
376 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
377 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
378 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
379 if (err)
380 return err;
381 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
382 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
383 return 0;
384}
385
386static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
387 unsigned int counter_index)
388{
389 char mgpc_pl[MLXSW_REG_MGPC_LEN];
390
391 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
392 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
393 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
394}
395
396int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
397 unsigned int *p_counter_index)
398{
399 int err;
400
401 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
402 p_counter_index);
403 if (err)
404 return err;
405 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
406 if (err)
407 goto err_counter_clear;
408 return 0;
409
410err_counter_clear:
411 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
412 *p_counter_index);
413 return err;
414}
415
416void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
417 unsigned int counter_index)
418{
419 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
420 counter_index);
421}
422
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200423static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
424 const struct mlxsw_tx_info *tx_info)
425{
426 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
427
428 memset(txhdr, 0, MLXSW_TXHDR_LEN);
429
430 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
431 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
432 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
433 mlxsw_tx_hdr_swid_set(txhdr, 0);
434 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
435 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
436 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
437}
438
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200439int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
440 u8 state)
441{
442 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
443 enum mlxsw_reg_spms_state spms_state;
444 char *spms_pl;
445 int err;
446
447 switch (state) {
448 case BR_STATE_FORWARDING:
449 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
450 break;
451 case BR_STATE_LEARNING:
452 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
453 break;
454 case BR_STATE_LISTENING: /* fall-through */
455 case BR_STATE_DISABLED: /* fall-through */
456 case BR_STATE_BLOCKING:
457 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
458 break;
459 default:
460 BUG();
461 }
462
463 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
464 if (!spms_pl)
465 return -ENOMEM;
466 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
467 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
468
469 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
470 kfree(spms_pl);
471 return err;
472}
473
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200474static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
475{
Elad Raz5b090742016-10-28 21:35:46 +0200476 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200477 int err;
478
479 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
480 if (err)
481 return err;
482 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
483 return 0;
484}
485
Yotam Gigi763b4b72016-07-21 12:03:17 +0200486static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
487{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200488 int i;
489
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200490 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200491 return -EIO;
492
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200493 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
494 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200495 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
496 sizeof(struct mlxsw_sp_span_entry),
497 GFP_KERNEL);
498 if (!mlxsw_sp->span.entries)
499 return -ENOMEM;
500
501 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
502 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
503
504 return 0;
505}
506
507static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
508{
509 int i;
510
511 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
512 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
513
514 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
515 }
516 kfree(mlxsw_sp->span.entries);
517}
518
519static struct mlxsw_sp_span_entry *
520mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
521{
522 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
523 struct mlxsw_sp_span_entry *span_entry;
524 char mpat_pl[MLXSW_REG_MPAT_LEN];
525 u8 local_port = port->local_port;
526 int index;
527 int i;
528 int err;
529
530 /* find a free entry to use */
531 index = -1;
532 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
533 if (!mlxsw_sp->span.entries[i].used) {
534 index = i;
535 span_entry = &mlxsw_sp->span.entries[i];
536 break;
537 }
538 }
539 if (index < 0)
540 return NULL;
541
542 /* create a new port analayzer entry for local_port */
543 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
544 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
545 if (err)
546 return NULL;
547
548 span_entry->used = true;
549 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100550 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200551 span_entry->local_port = local_port;
552 return span_entry;
553}
554
555static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
556 struct mlxsw_sp_span_entry *span_entry)
557{
558 u8 local_port = span_entry->local_port;
559 char mpat_pl[MLXSW_REG_MPAT_LEN];
560 int pa_id = span_entry->id;
561
562 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
563 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
564 span_entry->used = false;
565}
566
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200567static struct mlxsw_sp_span_entry *
568mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200569{
570 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
571 int i;
572
573 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
574 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
575
576 if (curr->used && curr->local_port == port->local_port)
577 return curr;
578 }
579 return NULL;
580}
581
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200582static struct mlxsw_sp_span_entry
583*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200584{
585 struct mlxsw_sp_span_entry *span_entry;
586
587 span_entry = mlxsw_sp_span_entry_find(port);
588 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100589 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200590 span_entry->ref_count++;
591 return span_entry;
592 }
593
594 return mlxsw_sp_span_entry_create(port);
595}
596
597static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
598 struct mlxsw_sp_span_entry *span_entry)
599{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100600 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200601 if (--span_entry->ref_count == 0)
602 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
603 return 0;
604}
605
606static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
607{
608 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
609 struct mlxsw_sp_span_inspected_port *p;
610 int i;
611
612 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
613 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
614
615 list_for_each_entry(p, &curr->bound_ports_list, list)
616 if (p->local_port == port->local_port &&
617 p->type == MLXSW_SP_SPAN_EGRESS)
618 return true;
619 }
620
621 return false;
622}
623
Ido Schimmel18281f22017-03-24 08:02:51 +0100624static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
625 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200626{
Ido Schimmel18281f22017-03-24 08:02:51 +0100627 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200628}
629
630static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
631{
632 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
633 char sbib_pl[MLXSW_REG_SBIB_LEN];
634 int err;
635
636 /* If port is egress mirrored, the shared buffer size should be
637 * updated according to the mtu value
638 */
639 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100640 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
641
642 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200643 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
644 if (err) {
645 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
646 return err;
647 }
648 }
649
650 return 0;
651}
652
653static struct mlxsw_sp_span_inspected_port *
654mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
655 struct mlxsw_sp_span_entry *span_entry)
656{
657 struct mlxsw_sp_span_inspected_port *p;
658
659 list_for_each_entry(p, &span_entry->bound_ports_list, list)
660 if (port->local_port == p->local_port)
661 return p;
662 return NULL;
663}
664
665static int
666mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
667 struct mlxsw_sp_span_entry *span_entry,
668 enum mlxsw_sp_span_type type)
669{
670 struct mlxsw_sp_span_inspected_port *inspected_port;
671 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
672 char mpar_pl[MLXSW_REG_MPAR_LEN];
673 char sbib_pl[MLXSW_REG_SBIB_LEN];
674 int pa_id = span_entry->id;
675 int err;
676
677 /* if it is an egress SPAN, bind a shared buffer to it */
678 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100679 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
680 port->dev->mtu);
681
682 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200683 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
684 if (err) {
685 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
686 return err;
687 }
688 }
689
690 /* bind the port to the SPAN entry */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200691 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
692 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200693 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
694 if (err)
695 goto err_mpar_reg_write;
696
697 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
698 if (!inspected_port) {
699 err = -ENOMEM;
700 goto err_inspected_port_alloc;
701 }
702 inspected_port->local_port = port->local_port;
703 inspected_port->type = type;
704 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
705
706 return 0;
707
708err_mpar_reg_write:
709err_inspected_port_alloc:
710 if (type == MLXSW_SP_SPAN_EGRESS) {
711 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
712 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
713 }
714 return err;
715}
716
717static void
718mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
719 struct mlxsw_sp_span_entry *span_entry,
720 enum mlxsw_sp_span_type type)
721{
722 struct mlxsw_sp_span_inspected_port *inspected_port;
723 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
724 char mpar_pl[MLXSW_REG_MPAR_LEN];
725 char sbib_pl[MLXSW_REG_SBIB_LEN];
726 int pa_id = span_entry->id;
727
728 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
729 if (!inspected_port)
730 return;
731
732 /* remove the inspected port */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200733 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
734 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200735 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
736
737 /* remove the SBIB buffer if it was egress SPAN */
738 if (type == MLXSW_SP_SPAN_EGRESS) {
739 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
740 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
741 }
742
743 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
744
745 list_del(&inspected_port->list);
746 kfree(inspected_port);
747}
748
749static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
750 struct mlxsw_sp_port *to,
751 enum mlxsw_sp_span_type type)
752{
753 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
754 struct mlxsw_sp_span_entry *span_entry;
755 int err;
756
757 span_entry = mlxsw_sp_span_entry_get(to);
758 if (!span_entry)
759 return -ENOENT;
760
761 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
762 span_entry->id);
763
764 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
765 if (err)
766 goto err_port_bind;
767
768 return 0;
769
770err_port_bind:
771 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
772 return err;
773}
774
775static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
776 struct mlxsw_sp_port *to,
777 enum mlxsw_sp_span_type type)
778{
779 struct mlxsw_sp_span_entry *span_entry;
780
781 span_entry = mlxsw_sp_span_entry_find(to);
782 if (!span_entry) {
783 netdev_err(from->dev, "no span entry found\n");
784 return;
785 }
786
787 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
788 span_entry->id);
789 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
790}
791
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100792static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
793 bool enable, u32 rate)
794{
795 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
796 char mpsc_pl[MLXSW_REG_MPSC_LEN];
797
798 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
799 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
800}
801
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200802static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
803 bool is_up)
804{
805 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
806 char paos_pl[MLXSW_REG_PAOS_LEN];
807
808 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
809 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
810 MLXSW_PORT_ADMIN_STATUS_DOWN);
811 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
812}
813
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200814static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
815 unsigned char *addr)
816{
817 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
818 char ppad_pl[MLXSW_REG_PPAD_LEN];
819
820 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
821 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
822 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
823}
824
825static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
826{
827 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
828 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
829
830 ether_addr_copy(addr, mlxsw_sp->base_mac);
831 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
832 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
833}
834
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200835static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
836{
837 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
838 char pmtu_pl[MLXSW_REG_PMTU_LEN];
839 int max_mtu;
840 int err;
841
842 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
843 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
844 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
845 if (err)
846 return err;
847 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
848
849 if (mtu > max_mtu)
850 return -EINVAL;
851
852 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
853 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
854}
855
Ido Schimmelbe945352016-06-09 09:51:39 +0200856static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
857 u8 swid)
858{
859 char pspa_pl[MLXSW_REG_PSPA_LEN];
860
861 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
862 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
863}
864
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200865static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
866{
867 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200868
Ido Schimmelbe945352016-06-09 09:51:39 +0200869 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
870 swid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200871}
872
873static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
874 bool enable)
875{
876 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
877 char svpe_pl[MLXSW_REG_SVPE_LEN];
878
879 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
880 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
881}
882
883int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
884 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
885 u16 vid)
886{
887 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
888 char svfa_pl[MLXSW_REG_SVFA_LEN];
889
890 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
891 fid, vid);
892 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
893}
894
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200895int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
896 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200897{
898 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
899 char *spvmlr_pl;
900 int err;
901
902 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
903 if (!spvmlr_pl)
904 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200905 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
906 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200907 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
908 kfree(spvmlr_pl);
909 return err;
910}
911
Ido Schimmelb02eae92017-05-16 19:38:34 +0200912static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
913 u16 vid)
914{
915 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
916 char spvid_pl[MLXSW_REG_SPVID_LEN];
917
918 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
919 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
920}
921
922static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
923 bool allow)
924{
925 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
926 char spaft_pl[MLXSW_REG_SPAFT_LEN];
927
928 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
929 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
930}
931
932int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
933{
934 int err;
935
936 if (!vid) {
937 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
938 if (err)
939 return err;
940 } else {
941 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
942 if (err)
943 return err;
944 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
945 if (err)
946 goto err_port_allow_untagged_set;
947 }
948
949 mlxsw_sp_port->pvid = vid;
950 return 0;
951
952err_port_allow_untagged_set:
953 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
954 return err;
955}
956
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200957static int
958mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
959{
960 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
961 char sspr_pl[MLXSW_REG_SSPR_LEN];
962
963 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
964 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
965}
966
Ido Schimmeld664b412016-06-09 09:51:40 +0200967static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
968 u8 local_port, u8 *p_module,
969 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200970{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200971 char pmlp_pl[MLXSW_REG_PMLP_LEN];
972 int err;
973
Ido Schimmel558c2d52016-02-26 17:32:29 +0100974 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200975 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
976 if (err)
977 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100978 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
979 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200980 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200981 return 0;
982}
983
Ido Schimmel18f1e702016-02-26 17:32:31 +0100984static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
985 u8 module, u8 width, u8 lane)
986{
987 char pmlp_pl[MLXSW_REG_PMLP_LEN];
988 int i;
989
990 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
991 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
992 for (i = 0; i < width; i++) {
993 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
994 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
995 }
996
997 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
998}
999
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001000static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1001{
1002 char pmlp_pl[MLXSW_REG_PMLP_LEN];
1003
1004 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
1005 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
1006 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1007}
1008
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001009static int mlxsw_sp_port_open(struct net_device *dev)
1010{
1011 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1012 int err;
1013
1014 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1015 if (err)
1016 return err;
1017 netif_start_queue(dev);
1018 return 0;
1019}
1020
1021static int mlxsw_sp_port_stop(struct net_device *dev)
1022{
1023 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1024
1025 netif_stop_queue(dev);
1026 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1027}
1028
1029static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1030 struct net_device *dev)
1031{
1032 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1033 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1034 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1035 const struct mlxsw_tx_info tx_info = {
1036 .local_port = mlxsw_sp_port->local_port,
1037 .is_emad = false,
1038 };
1039 u64 len;
1040 int err;
1041
Jiri Pirko307c2432016-04-08 19:11:22 +02001042 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001043 return NETDEV_TX_BUSY;
1044
1045 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1046 struct sk_buff *skb_orig = skb;
1047
1048 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1049 if (!skb) {
1050 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1051 dev_kfree_skb_any(skb_orig);
1052 return NETDEV_TX_OK;
1053 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +01001054 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001055 }
1056
1057 if (eth_skb_pad(skb)) {
1058 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1059 return NETDEV_TX_OK;
1060 }
1061
1062 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +02001063 /* TX header is consumed by HW on the way so we shouldn't count its
1064 * bytes as being sent.
1065 */
1066 len = skb->len - MLXSW_TXHDR_LEN;
1067
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001068 /* Due to a race we might fail here because of a full queue. In that
1069 * unlikely case we simply drop the packet.
1070 */
Jiri Pirko307c2432016-04-08 19:11:22 +02001071 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001072
1073 if (!err) {
1074 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1075 u64_stats_update_begin(&pcpu_stats->syncp);
1076 pcpu_stats->tx_packets++;
1077 pcpu_stats->tx_bytes += len;
1078 u64_stats_update_end(&pcpu_stats->syncp);
1079 } else {
1080 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1081 dev_kfree_skb_any(skb);
1082 }
1083 return NETDEV_TX_OK;
1084}
1085
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001086static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1087{
1088}
1089
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001090static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1091{
1092 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1093 struct sockaddr *addr = p;
1094 int err;
1095
1096 if (!is_valid_ether_addr(addr->sa_data))
1097 return -EADDRNOTAVAIL;
1098
1099 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1100 if (err)
1101 return err;
1102 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1103 return 0;
1104}
1105
Ido Schimmel18281f22017-03-24 08:02:51 +01001106static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1107 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001108{
Ido Schimmel18281f22017-03-24 08:02:51 +01001109 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001110}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001111
Ido Schimmelf417f042017-03-24 08:02:50 +01001112#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +01001113
1114static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1115 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +01001116{
Ido Schimmel18281f22017-03-24 08:02:51 +01001117 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1118 BITS_PER_BYTE));
1119 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1120 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001121}
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001122
Ido Schimmel18281f22017-03-24 08:02:51 +01001123/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +01001124 * Assumes 100m cable and maximum MTU.
1125 */
Ido Schimmel18281f22017-03-24 08:02:51 +01001126#define MLXSW_SP_PAUSE_DELAY 58752
1127
1128static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1129 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +01001130{
1131 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +01001132 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +01001133 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +01001134 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001135 else
Ido Schimmelf417f042017-03-24 08:02:50 +01001136 return 0;
1137}
1138
1139static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1140 bool lossy)
1141{
1142 if (lossy)
1143 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
1144 else
1145 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1146 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001147}
1148
1149int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001150 u8 *prio_tc, bool pause_en,
1151 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +02001152{
1153 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001154 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1155 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001156 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001157 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001158
1159 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1160 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1161 if (err)
1162 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001163
1164 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1165 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001166 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +01001167 bool lossy;
1168 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001169
1170 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1171 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001172 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001173 configure = true;
1174 break;
1175 }
1176 }
1177
1178 if (!configure)
1179 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +01001180
1181 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +01001182 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1183 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1184 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +01001185 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001186 }
1187
Ido Schimmelff6551e2016-04-06 17:10:03 +02001188 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1189}
1190
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001191static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001192 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001193{
1194 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1195 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001196 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001197 u8 *prio_tc;
1198
1199 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001200 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001201
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001202 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001203 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001204}
1205
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001206static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1207{
1208 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001209 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001210 int err;
1211
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001212 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001213 if (err)
1214 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001215 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1216 if (err)
1217 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001218 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1219 if (err)
1220 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001221 dev->mtu = mtu;
1222 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001223
1224err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001225 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1226err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001227 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +02001228 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001229}
1230
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001231static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001232mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1233 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001234{
1235 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1236 struct mlxsw_sp_port_pcpu_stats *p;
1237 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1238 u32 tx_dropped = 0;
1239 unsigned int start;
1240 int i;
1241
1242 for_each_possible_cpu(i) {
1243 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1244 do {
1245 start = u64_stats_fetch_begin_irq(&p->syncp);
1246 rx_packets = p->rx_packets;
1247 rx_bytes = p->rx_bytes;
1248 tx_packets = p->tx_packets;
1249 tx_bytes = p->tx_bytes;
1250 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1251
1252 stats->rx_packets += rx_packets;
1253 stats->rx_bytes += rx_bytes;
1254 stats->tx_packets += tx_packets;
1255 stats->tx_bytes += tx_bytes;
1256 /* tx_dropped is u32, updated without syncp protection. */
1257 tx_dropped += p->tx_dropped;
1258 }
1259 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001260 return 0;
1261}
1262
Or Gerlitz3df5b3c2016-11-22 23:09:54 +02001263static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001264{
1265 switch (attr_id) {
1266 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1267 return true;
1268 }
1269
1270 return false;
1271}
1272
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001273static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1274 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001275{
1276 switch (attr_id) {
1277 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1278 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1279 }
1280
1281 return -EINVAL;
1282}
1283
1284static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1285 int prio, char *ppcnt_pl)
1286{
1287 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1288 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1289
1290 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1291 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1292}
1293
1294static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1295 struct rtnl_link_stats64 *stats)
1296{
1297 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1298 int err;
1299
1300 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1301 0, ppcnt_pl);
1302 if (err)
1303 goto out;
1304
1305 stats->tx_packets =
1306 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1307 stats->rx_packets =
1308 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1309 stats->tx_bytes =
1310 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1311 stats->rx_bytes =
1312 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1313 stats->multicast =
1314 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1315
1316 stats->rx_crc_errors =
1317 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1318 stats->rx_frame_errors =
1319 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1320
1321 stats->rx_length_errors = (
1322 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1323 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1324 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1325
1326 stats->rx_errors = (stats->rx_crc_errors +
1327 stats->rx_frame_errors + stats->rx_length_errors);
1328
1329out:
1330 return err;
1331}
1332
1333static void update_stats_cache(struct work_struct *work)
1334{
1335 struct mlxsw_sp_port *mlxsw_sp_port =
1336 container_of(work, struct mlxsw_sp_port,
1337 hw_stats.update_dw.work);
1338
1339 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1340 goto out;
1341
1342 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1343 mlxsw_sp_port->hw_stats.cache);
1344
1345out:
1346 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
1347 MLXSW_HW_STATS_UPDATE_TIME);
1348}
1349
1350/* Return the stats from a cache that is updated periodically,
1351 * as this function might get called in an atomic context.
1352 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001353static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001354mlxsw_sp_port_get_stats64(struct net_device *dev,
1355 struct rtnl_link_stats64 *stats)
1356{
1357 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1358
1359 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001360}
1361
Jiri Pirko93cd0812017-04-18 16:55:35 +02001362static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1363 u16 vid_begin, u16 vid_end,
1364 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001365{
1366 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1367 char *spvm_pl;
1368 int err;
1369
1370 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1371 if (!spvm_pl)
1372 return -ENOMEM;
1373
1374 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1375 vid_end, is_member, untagged);
1376 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1377 kfree(spvm_pl);
1378 return err;
1379}
1380
Jiri Pirko93cd0812017-04-18 16:55:35 +02001381int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1382 u16 vid_end, bool is_member, bool untagged)
1383{
1384 u16 vid, vid_e;
1385 int err;
1386
1387 for (vid = vid_begin; vid <= vid_end;
1388 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1389 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1390 vid_end);
1391
1392 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1393 is_member, untagged);
1394 if (err)
1395 return err;
1396 }
1397
1398 return 0;
1399}
1400
Ido Schimmel4aafc362017-05-26 08:37:25 +02001401int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001402{
1403 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1404 u16 vid, last_visited_vid;
1405 int err;
1406
1407 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1408 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
1409 vid);
1410 if (err) {
1411 last_visited_vid = vid;
1412 goto err_port_vid_to_fid_set;
1413 }
1414 }
1415
1416 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
1417 if (err) {
1418 last_visited_vid = VLAN_N_VID;
1419 goto err_port_vid_to_fid_set;
1420 }
1421
1422 return 0;
1423
1424err_port_vid_to_fid_set:
1425 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
1426 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
1427 vid);
1428 return err;
1429}
1430
Ido Schimmel4aafc362017-05-26 08:37:25 +02001431int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001432{
1433 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1434 u16 vid;
1435 int err;
1436
1437 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
1438 if (err)
1439 return err;
1440
1441 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1442 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
1443 vid, vid);
1444 if (err)
1445 return err;
1446 }
1447
1448 return 0;
1449}
1450
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001451static struct mlxsw_sp_port *
Ido Schimmel0355b592016-06-20 23:04:13 +02001452mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001453{
1454 struct mlxsw_sp_port *mlxsw_sp_vport;
1455
1456 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
1457 if (!mlxsw_sp_vport)
1458 return NULL;
1459
1460 /* dev will be set correctly after the VLAN device is linked
1461 * with the real device. In case of bridge SELF invocation, dev
1462 * will remain as is.
1463 */
1464 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
1465 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1466 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
1467 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
Ido Schimmel272c4472015-12-15 16:03:47 +01001468 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
1469 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel0355b592016-06-20 23:04:13 +02001470 mlxsw_sp_vport->vport.vid = vid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001471
1472 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
1473
1474 return mlxsw_sp_vport;
1475}
1476
1477static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
1478{
1479 list_del(&mlxsw_sp_vport->vport.list);
1480 kfree(mlxsw_sp_vport);
1481}
1482
Ido Schimmel31a08a52017-05-26 08:37:26 +02001483static struct mlxsw_sp_port_vlan *
1484mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1485{
1486 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1487
1488 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1489 if (!mlxsw_sp_port_vlan)
1490 return ERR_PTR(-ENOMEM);
1491
1492 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1493 mlxsw_sp_port_vlan->vid = vid;
1494 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1495
1496 return mlxsw_sp_port_vlan;
1497}
1498
1499static void
1500mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1501{
1502 list_del(&mlxsw_sp_port_vlan->list);
1503 kfree(mlxsw_sp_port_vlan);
1504}
1505
Ido Schimmel05978482016-08-17 16:39:30 +02001506static int mlxsw_sp_port_add_vid(struct net_device *dev,
1507 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001508{
1509 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001510 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001511 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel52697a92016-07-02 11:00:09 +02001512 bool untagged = vid == 1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001513 int err;
1514
1515 /* VLAN 0 is added to HW filter when device goes up, but it is
1516 * reserved in our case, so simply return.
1517 */
1518 if (!vid)
1519 return 0;
1520
Ido Schimmel31a08a52017-05-26 08:37:26 +02001521 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1522 if (mlxsw_sp_port_vlan)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001523 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001524
Ido Schimmel31a08a52017-05-26 08:37:26 +02001525 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1526 if (IS_ERR(mlxsw_sp_port_vlan))
1527 return PTR_ERR(mlxsw_sp_port_vlan);
1528
Ido Schimmel0355b592016-06-20 23:04:13 +02001529 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001530 if (!mlxsw_sp_vport) {
1531 err = -ENOMEM;
1532 goto err_port_vport_create;
1533 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001534
Ido Schimmel52697a92016-07-02 11:00:09 +02001535 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
Ido Schimmelfa66d7e2016-08-17 16:39:29 +02001536 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001537 goto err_port_add_vid;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001538
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001539 return 0;
1540
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001541err_port_add_vid:
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001542 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001543err_port_vport_create:
1544 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001545 return err;
1546}
1547
Ido Schimmel32d863f2016-07-02 11:00:10 +02001548static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1549 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001550{
1551 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001552 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001553 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel1c800752016-06-20 23:04:20 +02001554 struct mlxsw_sp_fid *f;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001555
1556 /* VLAN 0 is removed from HW filter when device goes down, but
1557 * it is reserved in our case, so simply return.
1558 */
1559 if (!vid)
1560 return 0;
1561
Ido Schimmel31a08a52017-05-26 08:37:26 +02001562 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1563 if (WARN_ON(!mlxsw_sp_port_vlan))
1564 return 0;
1565
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001566 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel7a355832016-08-17 16:39:28 +02001567 if (WARN_ON(!mlxsw_sp_vport))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001568 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001569
Ido Schimmel7a355832016-08-17 16:39:28 +02001570 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001571
Ido Schimmel1c800752016-06-20 23:04:20 +02001572 /* Drop FID reference. If this was the last reference the
1573 * resources will be freed.
1574 */
1575 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
1576 if (f && !WARN_ON(!f->leave))
1577 f->leave(mlxsw_sp_vport);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001578
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001579 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
1580
Ido Schimmel31a08a52017-05-26 08:37:26 +02001581 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1582
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001583 return 0;
1584}
1585
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001586static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1587 size_t len)
1588{
1589 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001590 u8 module = mlxsw_sp_port->mapping.module;
1591 u8 width = mlxsw_sp_port->mapping.width;
1592 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001593 int err;
1594
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001595 if (!mlxsw_sp_port->split)
1596 err = snprintf(name, len, "p%d", module + 1);
1597 else
1598 err = snprintf(name, len, "p%ds%d", module + 1,
1599 lane / width);
1600
1601 if (err >= len)
1602 return -EINVAL;
1603
1604 return 0;
1605}
1606
Yotam Gigi763b4b72016-07-21 12:03:17 +02001607static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001608mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1609 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001610 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1611
1612 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1613 if (mall_tc_entry->cookie == cookie)
1614 return mall_tc_entry;
1615
1616 return NULL;
1617}
1618
1619static int
1620mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001621 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001622 const struct tc_action *a,
1623 bool ingress)
1624{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001625 struct net *net = dev_net(mlxsw_sp_port->dev);
1626 enum mlxsw_sp_span_type span_type;
1627 struct mlxsw_sp_port *to_port;
1628 struct net_device *to_dev;
1629 int ifindex;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001630
1631 ifindex = tcf_mirred_ifindex(a);
1632 to_dev = __dev_get_by_index(net, ifindex);
1633 if (!to_dev) {
1634 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1635 return -EINVAL;
1636 }
1637
1638 if (!mlxsw_sp_port_dev_check(to_dev)) {
1639 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001640 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001641 }
1642 to_port = netdev_priv(to_dev);
1643
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001644 mirror->to_local_port = to_port->local_port;
1645 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001646 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001647 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1648}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001649
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001650static void
1651mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1652 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1653{
1654 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1655 enum mlxsw_sp_span_type span_type;
1656 struct mlxsw_sp_port *to_port;
1657
1658 to_port = mlxsw_sp->ports[mirror->to_local_port];
1659 span_type = mirror->ingress ?
1660 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1661 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001662}
1663
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001664static int
1665mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1666 struct tc_cls_matchall_offload *cls,
1667 const struct tc_action *a,
1668 bool ingress)
1669{
1670 int err;
1671
1672 if (!mlxsw_sp_port->sample)
1673 return -EOPNOTSUPP;
1674 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1675 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1676 return -EEXIST;
1677 }
1678 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1679 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1680 return -EOPNOTSUPP;
1681 }
1682
1683 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1684 tcf_sample_psample_group(a));
1685 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1686 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1687 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1688
1689 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1690 if (err)
1691 goto err_port_sample_set;
1692 return 0;
1693
1694err_port_sample_set:
1695 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1696 return err;
1697}
1698
1699static void
1700mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1701{
1702 if (!mlxsw_sp_port->sample)
1703 return;
1704
1705 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1706 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1707}
1708
Yotam Gigi763b4b72016-07-21 12:03:17 +02001709static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1710 __be16 protocol,
1711 struct tc_cls_matchall_offload *cls,
1712 bool ingress)
1713{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001714 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001715 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001716 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001717 int err;
1718
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001719 if (!tc_single_action(cls->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001720 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001721 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001722 }
1723
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001724 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1725 if (!mall_tc_entry)
1726 return -ENOMEM;
1727 mall_tc_entry->cookie = cls->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001728
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001729 tcf_exts_to_list(cls->exts, &actions);
1730 a = list_first_entry(&actions, struct tc_action, list);
1731
1732 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1733 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1734
1735 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1736 mirror = &mall_tc_entry->mirror;
1737 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1738 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001739 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1740 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1741 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, cls,
1742 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001743 } else {
1744 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001745 }
1746
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001747 if (err)
1748 goto err_add_action;
1749
1750 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001751 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001752
1753err_add_action:
1754 kfree(mall_tc_entry);
1755 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001756}
1757
1758static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1759 struct tc_cls_matchall_offload *cls)
1760{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001761 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001762
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001763 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1764 cls->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001765 if (!mall_tc_entry) {
1766 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1767 return;
1768 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001769 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001770
1771 switch (mall_tc_entry->type) {
1772 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001773 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1774 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001775 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001776 case MLXSW_SP_PORT_MALL_SAMPLE:
1777 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1778 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001779 default:
1780 WARN_ON(1);
1781 }
1782
Yotam Gigi763b4b72016-07-21 12:03:17 +02001783 kfree(mall_tc_entry);
1784}
1785
1786static int mlxsw_sp_setup_tc(struct net_device *dev, u32 handle,
1787 __be16 proto, struct tc_to_netdev *tc)
1788{
1789 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1790 bool ingress = TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS);
1791
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001792 switch (tc->type) {
1793 case TC_SETUP_MATCHALL:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001794 switch (tc->cls_mall->command) {
1795 case TC_CLSMATCHALL_REPLACE:
1796 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port,
1797 proto,
1798 tc->cls_mall,
1799 ingress);
1800 case TC_CLSMATCHALL_DESTROY:
1801 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port,
1802 tc->cls_mall);
1803 return 0;
1804 default:
Or Gerlitzabbdf4b2017-03-17 09:38:01 +01001805 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001806 }
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001807 case TC_SETUP_CLSFLOWER:
1808 switch (tc->cls_flower->command) {
1809 case TC_CLSFLOWER_REPLACE:
1810 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress,
1811 proto, tc->cls_flower);
1812 case TC_CLSFLOWER_DESTROY:
1813 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress,
1814 tc->cls_flower);
1815 return 0;
Arkadi Sharshevsky7c1b8eb2017-03-11 09:42:59 +01001816 case TC_CLSFLOWER_STATS:
1817 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress,
1818 tc->cls_flower);
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001819 default:
1820 return -EOPNOTSUPP;
1821 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001822 }
1823
Yotam Gigie915ac62017-01-09 11:25:48 +01001824 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001825}
1826
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001827static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1828 .ndo_open = mlxsw_sp_port_open,
1829 .ndo_stop = mlxsw_sp_port_stop,
1830 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001831 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001832 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001833 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1834 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1835 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001836 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1837 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001838 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1839 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1840 .ndo_fdb_add = switchdev_port_fdb_add,
1841 .ndo_fdb_del = switchdev_port_fdb_del,
1842 .ndo_fdb_dump = switchdev_port_fdb_dump,
1843 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
1844 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
1845 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001846 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001847};
1848
1849static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1850 struct ethtool_drvinfo *drvinfo)
1851{
1852 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1853 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1854
1855 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1856 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1857 sizeof(drvinfo->version));
1858 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1859 "%d.%d.%d",
1860 mlxsw_sp->bus_info->fw_rev.major,
1861 mlxsw_sp->bus_info->fw_rev.minor,
1862 mlxsw_sp->bus_info->fw_rev.subminor);
1863 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1864 sizeof(drvinfo->bus_info));
1865}
1866
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001867static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1868 struct ethtool_pauseparam *pause)
1869{
1870 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1871
1872 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1873 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1874}
1875
1876static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1877 struct ethtool_pauseparam *pause)
1878{
1879 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1880
1881 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1882 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1883 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1884
1885 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1886 pfcc_pl);
1887}
1888
1889static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1890 struct ethtool_pauseparam *pause)
1891{
1892 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1893 bool pause_en = pause->tx_pause || pause->rx_pause;
1894 int err;
1895
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001896 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1897 netdev_err(dev, "PFC already enabled on port\n");
1898 return -EINVAL;
1899 }
1900
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001901 if (pause->autoneg) {
1902 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1903 return -EINVAL;
1904 }
1905
1906 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1907 if (err) {
1908 netdev_err(dev, "Failed to configure port's headroom\n");
1909 return err;
1910 }
1911
1912 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1913 if (err) {
1914 netdev_err(dev, "Failed to set PAUSE parameters\n");
1915 goto err_port_pause_configure;
1916 }
1917
1918 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1919 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1920
1921 return 0;
1922
1923err_port_pause_configure:
1924 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1925 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1926 return err;
1927}
1928
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001929struct mlxsw_sp_port_hw_stats {
1930 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001931 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001932 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001933};
1934
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001935static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001936 {
1937 .str = "a_frames_transmitted_ok",
1938 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1939 },
1940 {
1941 .str = "a_frames_received_ok",
1942 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1943 },
1944 {
1945 .str = "a_frame_check_sequence_errors",
1946 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1947 },
1948 {
1949 .str = "a_alignment_errors",
1950 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1951 },
1952 {
1953 .str = "a_octets_transmitted_ok",
1954 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1955 },
1956 {
1957 .str = "a_octets_received_ok",
1958 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1959 },
1960 {
1961 .str = "a_multicast_frames_xmitted_ok",
1962 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1963 },
1964 {
1965 .str = "a_broadcast_frames_xmitted_ok",
1966 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1967 },
1968 {
1969 .str = "a_multicast_frames_received_ok",
1970 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1971 },
1972 {
1973 .str = "a_broadcast_frames_received_ok",
1974 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1975 },
1976 {
1977 .str = "a_in_range_length_errors",
1978 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1979 },
1980 {
1981 .str = "a_out_of_range_length_field",
1982 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1983 },
1984 {
1985 .str = "a_frame_too_long_errors",
1986 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1987 },
1988 {
1989 .str = "a_symbol_error_during_carrier",
1990 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1991 },
1992 {
1993 .str = "a_mac_control_frames_transmitted",
1994 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1995 },
1996 {
1997 .str = "a_mac_control_frames_received",
1998 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1999 },
2000 {
2001 .str = "a_unsupported_opcodes_received",
2002 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2003 },
2004 {
2005 .str = "a_pause_mac_ctrl_frames_received",
2006 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2007 },
2008 {
2009 .str = "a_pause_mac_ctrl_frames_xmitted",
2010 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2011 },
2012};
2013
2014#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2015
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002016static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2017 {
2018 .str = "rx_octets_prio",
2019 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2020 },
2021 {
2022 .str = "rx_frames_prio",
2023 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2024 },
2025 {
2026 .str = "tx_octets_prio",
2027 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2028 },
2029 {
2030 .str = "tx_frames_prio",
2031 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2032 },
2033 {
2034 .str = "rx_pause_prio",
2035 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2036 },
2037 {
2038 .str = "rx_pause_duration_prio",
2039 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2040 },
2041 {
2042 .str = "tx_pause_prio",
2043 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2044 },
2045 {
2046 .str = "tx_pause_duration_prio",
2047 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2048 },
2049};
2050
2051#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2052
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002053static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2054 {
2055 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01002056 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2057 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002058 },
2059 {
2060 .str = "tc_no_buffer_discard_uc_tc",
2061 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2062 },
2063};
2064
2065#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2066
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002067#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002068 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
2069 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002070 IEEE_8021QAZ_MAX_TCS)
2071
2072static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2073{
2074 int i;
2075
2076 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2077 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2078 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2079 *p += ETH_GSTRING_LEN;
2080 }
2081}
2082
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002083static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2084{
2085 int i;
2086
2087 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2088 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2089 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2090 *p += ETH_GSTRING_LEN;
2091 }
2092}
2093
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002094static void mlxsw_sp_port_get_strings(struct net_device *dev,
2095 u32 stringset, u8 *data)
2096{
2097 u8 *p = data;
2098 int i;
2099
2100 switch (stringset) {
2101 case ETH_SS_STATS:
2102 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2103 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2104 ETH_GSTRING_LEN);
2105 p += ETH_GSTRING_LEN;
2106 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002107
2108 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2109 mlxsw_sp_port_get_prio_strings(&p, i);
2110
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002111 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2112 mlxsw_sp_port_get_tc_strings(&p, i);
2113
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002114 break;
2115 }
2116}
2117
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002118static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2119 enum ethtool_phys_id_state state)
2120{
2121 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2122 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2123 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2124 bool active;
2125
2126 switch (state) {
2127 case ETHTOOL_ID_ACTIVE:
2128 active = true;
2129 break;
2130 case ETHTOOL_ID_INACTIVE:
2131 active = false;
2132 break;
2133 default:
2134 return -EOPNOTSUPP;
2135 }
2136
2137 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2138 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2139}
2140
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002141static int
2142mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2143 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2144{
2145 switch (grp) {
2146 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2147 *p_hw_stats = mlxsw_sp_port_hw_stats;
2148 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2149 break;
2150 case MLXSW_REG_PPCNT_PRIO_CNT:
2151 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2152 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2153 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002154 case MLXSW_REG_PPCNT_TC_CNT:
2155 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2156 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2157 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002158 default:
2159 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002160 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002161 }
2162 return 0;
2163}
2164
2165static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2166 enum mlxsw_reg_ppcnt_grp grp, int prio,
2167 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002168{
Ido Schimmel18281f22017-03-24 08:02:51 +01002169 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2170 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002171 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002172 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002173 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002174 int err;
2175
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002176 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2177 if (err)
2178 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002179 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002180 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002181 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002182 if (!hw_stats[i].cells_bytes)
2183 continue;
2184 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2185 data[data_index + i]);
2186 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002187}
2188
2189static void mlxsw_sp_port_get_stats(struct net_device *dev,
2190 struct ethtool_stats *stats, u64 *data)
2191{
2192 int i, data_index = 0;
2193
2194 /* IEEE 802.3 Counters */
2195 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2196 data, data_index);
2197 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2198
2199 /* Per-Priority Counters */
2200 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2201 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2202 data, data_index);
2203 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2204 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002205
2206 /* Per-TC Counters */
2207 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2208 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2209 data, data_index);
2210 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2211 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002212}
2213
2214static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2215{
2216 switch (sset) {
2217 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002218 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002219 default:
2220 return -EOPNOTSUPP;
2221 }
2222}
2223
2224struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002225 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002226 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002227 u32 speed;
2228};
2229
2230static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2231 {
2232 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002233 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2234 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002235 },
2236 {
2237 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2238 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002239 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2240 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002241 },
2242 {
2243 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002244 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2245 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002246 },
2247 {
2248 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2249 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002250 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2251 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002252 },
2253 {
2254 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2255 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2256 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2257 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002258 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2259 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002260 },
2261 {
2262 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002263 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2264 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002265 },
2266 {
2267 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002268 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2269 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002270 },
2271 {
2272 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002273 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2274 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002275 },
2276 {
2277 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002278 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2279 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002280 },
2281 {
2282 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002283 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2284 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002285 },
2286 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002287 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2288 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2289 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002290 },
2291 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002292 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2293 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2294 .speed = SPEED_25000,
2295 },
2296 {
2297 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2298 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2299 .speed = SPEED_25000,
2300 },
2301 {
2302 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2303 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2304 .speed = SPEED_25000,
2305 },
2306 {
2307 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2308 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2309 .speed = SPEED_50000,
2310 },
2311 {
2312 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2313 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2314 .speed = SPEED_50000,
2315 },
2316 {
2317 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2318 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2319 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002320 },
2321 {
2322 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002323 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2324 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002325 },
2326 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002327 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2328 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2329 .speed = SPEED_56000,
2330 },
2331 {
2332 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2333 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2334 .speed = SPEED_56000,
2335 },
2336 {
2337 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2338 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2339 .speed = SPEED_56000,
2340 },
2341 {
2342 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2343 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2344 .speed = SPEED_100000,
2345 },
2346 {
2347 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2348 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2349 .speed = SPEED_100000,
2350 },
2351 {
2352 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2353 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2354 .speed = SPEED_100000,
2355 },
2356 {
2357 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2358 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2359 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002360 },
2361};
2362
2363#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2364
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002365static void
2366mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2367 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002368{
2369 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2370 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2371 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2372 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2373 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2374 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002375 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002376
2377 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2378 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2379 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2380 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2381 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002382 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002383}
2384
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002385static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002386{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002387 int i;
2388
2389 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2390 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002391 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2392 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002393 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002394}
2395
2396static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002397 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002398{
2399 u32 speed = SPEED_UNKNOWN;
2400 u8 duplex = DUPLEX_UNKNOWN;
2401 int i;
2402
2403 if (!carrier_ok)
2404 goto out;
2405
2406 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2407 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2408 speed = mlxsw_sp_port_link_mode[i].speed;
2409 duplex = DUPLEX_FULL;
2410 break;
2411 }
2412 }
2413out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002414 cmd->base.speed = speed;
2415 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002416}
2417
2418static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2419{
2420 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2421 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2422 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2423 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2424 return PORT_FIBRE;
2425
2426 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2427 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2428 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2429 return PORT_DA;
2430
2431 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2432 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2433 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2434 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2435 return PORT_NONE;
2436
2437 return PORT_OTHER;
2438}
2439
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002440static u32
2441mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002442{
2443 u32 ptys_proto = 0;
2444 int i;
2445
2446 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002447 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2448 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002449 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2450 }
2451 return ptys_proto;
2452}
2453
2454static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2455{
2456 u32 ptys_proto = 0;
2457 int i;
2458
2459 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2460 if (speed == mlxsw_sp_port_link_mode[i].speed)
2461 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2462 }
2463 return ptys_proto;
2464}
2465
Ido Schimmel18f1e702016-02-26 17:32:31 +01002466static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2467{
2468 u32 ptys_proto = 0;
2469 int i;
2470
2471 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2472 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2473 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2474 }
2475 return ptys_proto;
2476}
2477
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002478static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2479 struct ethtool_link_ksettings *cmd)
2480{
2481 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2482 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2483 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2484
2485 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2486 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2487}
2488
2489static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2490 struct ethtool_link_ksettings *cmd)
2491{
2492 if (!autoneg)
2493 return;
2494
2495 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2496 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2497}
2498
2499static void
2500mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2501 struct ethtool_link_ksettings *cmd)
2502{
2503 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2504 return;
2505
2506 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2507 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2508}
2509
2510static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2511 struct ethtool_link_ksettings *cmd)
2512{
2513 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2514 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2515 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2516 char ptys_pl[MLXSW_REG_PTYS_LEN];
2517 u8 autoneg_status;
2518 bool autoneg;
2519 int err;
2520
2521 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002522 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002523 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2524 if (err)
2525 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002526 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2527 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002528
2529 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2530
2531 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2532
2533 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2534 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2535 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2536
2537 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2538 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2539 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2540 cmd);
2541
2542 return 0;
2543}
2544
2545static int
2546mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2547 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002548{
2549 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2550 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2551 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002552 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002553 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002554 int err;
2555
Elad Raz401c8b42016-10-28 21:35:52 +02002556 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002557 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002558 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002559 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002560 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002561
2562 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2563 eth_proto_new = autoneg ?
2564 mlxsw_sp_to_ptys_advert_link(cmd) :
2565 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002566
2567 eth_proto_new = eth_proto_new & eth_proto_cap;
2568 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002569 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002570 return -EINVAL;
2571 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002572
Elad Raz401c8b42016-10-28 21:35:52 +02002573 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2574 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002575 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002576 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002577 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002578
Ido Schimmel6277d462016-07-15 11:14:58 +02002579 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002580 return 0;
2581
Ido Schimmel0c83f882016-09-12 13:26:23 +02002582 mlxsw_sp_port->link.autoneg = autoneg;
2583
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002584 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2585 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002586
2587 return 0;
2588}
2589
2590static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2591 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2592 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002593 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2594 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002595 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002596 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002597 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2598 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002599 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2600 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002601};
2602
Ido Schimmel18f1e702016-02-26 17:32:31 +01002603static int
2604mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2605{
2606 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2607 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2608 char ptys_pl[MLXSW_REG_PTYS_LEN];
2609 u32 eth_proto_admin;
2610
2611 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002612 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2613 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002614 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2615}
2616
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002617int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2618 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2619 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002620{
2621 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2622 char qeec_pl[MLXSW_REG_QEEC_LEN];
2623
2624 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2625 next_index);
2626 mlxsw_reg_qeec_de_set(qeec_pl, true);
2627 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2628 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2629 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2630}
2631
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002632int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2633 enum mlxsw_reg_qeec_hr hr, u8 index,
2634 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002635{
2636 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2637 char qeec_pl[MLXSW_REG_QEEC_LEN];
2638
2639 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2640 next_index);
2641 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2642 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2643 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2644}
2645
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002646int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2647 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002648{
2649 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2650 char qtct_pl[MLXSW_REG_QTCT_LEN];
2651
2652 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2653 tclass);
2654 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2655}
2656
2657static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2658{
2659 int err, i;
2660
2661 /* Setup the elements hierarcy, so that each TC is linked to
2662 * one subgroup, which are all member in the same group.
2663 */
2664 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2665 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2666 0);
2667 if (err)
2668 return err;
2669 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2670 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2671 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2672 0, false, 0);
2673 if (err)
2674 return err;
2675 }
2676 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2677 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2678 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2679 false, 0);
2680 if (err)
2681 return err;
2682 }
2683
2684 /* Make sure the max shaper is disabled in all hierarcies that
2685 * support it.
2686 */
2687 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2688 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2689 MLXSW_REG_QEEC_MAS_DIS);
2690 if (err)
2691 return err;
2692 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2693 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2694 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2695 i, 0,
2696 MLXSW_REG_QEEC_MAS_DIS);
2697 if (err)
2698 return err;
2699 }
2700 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2701 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2702 MLXSW_REG_QEEC_HIERARCY_TC,
2703 i, i,
2704 MLXSW_REG_QEEC_MAS_DIS);
2705 if (err)
2706 return err;
2707 }
2708
2709 /* Map all priorities to traffic class 0. */
2710 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2711 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2712 if (err)
2713 return err;
2714 }
2715
2716 return 0;
2717}
2718
Ido Schimmel05978482016-08-17 16:39:30 +02002719static int mlxsw_sp_port_pvid_vport_create(struct mlxsw_sp_port *mlxsw_sp_port)
2720{
2721 mlxsw_sp_port->pvid = 1;
2722
2723 return mlxsw_sp_port_add_vid(mlxsw_sp_port->dev, 0, 1);
2724}
2725
2726static int mlxsw_sp_port_pvid_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_port)
2727{
2728 return mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
2729}
2730
Jiri Pirko67963a32016-10-28 21:35:55 +02002731static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2732 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002733{
2734 struct mlxsw_sp_port *mlxsw_sp_port;
2735 struct net_device *dev;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002736 size_t bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002737 int err;
2738
2739 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2740 if (!dev)
2741 return -ENOMEM;
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002742 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002743 mlxsw_sp_port = netdev_priv(dev);
2744 mlxsw_sp_port->dev = dev;
2745 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2746 mlxsw_sp_port->local_port = local_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002747 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002748 mlxsw_sp_port->mapping.module = module;
2749 mlxsw_sp_port->mapping.width = width;
2750 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002751 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002752 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
2753 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
2754 if (!mlxsw_sp_port->active_vlans) {
2755 err = -ENOMEM;
2756 goto err_port_active_vlans_alloc;
2757 }
Elad Razfc1273a2016-01-06 13:01:11 +01002758 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
2759 if (!mlxsw_sp_port->untagged_vlans) {
2760 err = -ENOMEM;
2761 goto err_port_untagged_vlans_alloc;
2762 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02002763 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002764 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002765 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002766
2767 mlxsw_sp_port->pcpu_stats =
2768 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2769 if (!mlxsw_sp_port->pcpu_stats) {
2770 err = -ENOMEM;
2771 goto err_alloc_stats;
2772 }
2773
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002774 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2775 GFP_KERNEL);
2776 if (!mlxsw_sp_port->sample) {
2777 err = -ENOMEM;
2778 goto err_alloc_sample;
2779 }
2780
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002781 mlxsw_sp_port->hw_stats.cache =
2782 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2783
2784 if (!mlxsw_sp_port->hw_stats.cache) {
2785 err = -ENOMEM;
2786 goto err_alloc_hw_stats;
2787 }
2788 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2789 &update_stats_cache);
2790
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002791 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2792 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2793
Ido Schimmel3247ff22016-09-08 08:16:02 +02002794 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2795 if (err) {
2796 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2797 mlxsw_sp_port->local_port);
2798 goto err_port_swid_set;
2799 }
2800
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002801 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2802 if (err) {
2803 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2804 mlxsw_sp_port->local_port);
2805 goto err_dev_addr_init;
2806 }
2807
2808 netif_carrier_off(dev);
2809
2810 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002811 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2812 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002813
Jarod Wilsond894be52016-10-20 13:55:16 -04002814 dev->min_mtu = 0;
2815 dev->max_mtu = ETH_MAX_MTU;
2816
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002817 /* Each packet needs to have a Tx header (metadata) on top all other
2818 * headers.
2819 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002820 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002821
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002822 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2823 if (err) {
2824 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2825 mlxsw_sp_port->local_port);
2826 goto err_port_system_port_mapping_set;
2827 }
2828
Ido Schimmel18f1e702016-02-26 17:32:31 +01002829 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2830 if (err) {
2831 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2832 mlxsw_sp_port->local_port);
2833 goto err_port_speed_by_width_set;
2834 }
2835
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002836 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2837 if (err) {
2838 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2839 mlxsw_sp_port->local_port);
2840 goto err_port_mtu_set;
2841 }
2842
2843 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2844 if (err)
2845 goto err_port_admin_status_set;
2846
2847 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2848 if (err) {
2849 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2850 mlxsw_sp_port->local_port);
2851 goto err_port_buffers_init;
2852 }
2853
Ido Schimmel90183b92016-04-06 17:10:08 +02002854 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2855 if (err) {
2856 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2857 mlxsw_sp_port->local_port);
2858 goto err_port_ets_init;
2859 }
2860
Ido Schimmelf00817d2016-04-06 17:10:09 +02002861 /* ETS and buffers must be initialized before DCB. */
2862 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2863 if (err) {
2864 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2865 mlxsw_sp_port->local_port);
2866 goto err_port_dcb_init;
2867 }
2868
Ido Schimmel45a4a162017-05-16 19:38:35 +02002869 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2870 if (err) {
2871 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set non-virtual mode\n",
2872 mlxsw_sp_port->local_port);
2873 goto err_port_vp_mode_set;
2874 }
2875
Ido Schimmel05978482016-08-17 16:39:30 +02002876 err = mlxsw_sp_port_pvid_vport_create(mlxsw_sp_port);
2877 if (err) {
2878 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create PVID vPort\n",
2879 mlxsw_sp_port->local_port);
2880 goto err_port_pvid_vport_create;
2881 }
2882
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002883 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002884 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002885 err = register_netdev(dev);
2886 if (err) {
2887 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2888 mlxsw_sp_port->local_port);
2889 goto err_register_netdev;
2890 }
2891
Elad Razd808c7e2016-10-28 21:35:57 +02002892 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2893 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2894 module);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002895 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002896 return 0;
2897
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002898err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002899 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002900 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel05978482016-08-17 16:39:30 +02002901 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
2902err_port_pvid_vport_create:
Ido Schimmel45a4a162017-05-16 19:38:35 +02002903err_port_vp_mode_set:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002904 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002905err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002906err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002907err_port_buffers_init:
2908err_port_admin_status_set:
2909err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002910err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002911err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002912err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002913 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2914err_port_swid_set:
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002915 kfree(mlxsw_sp_port->hw_stats.cache);
2916err_alloc_hw_stats:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002917 kfree(mlxsw_sp_port->sample);
2918err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002919 free_percpu(mlxsw_sp_port->pcpu_stats);
2920err_alloc_stats:
Elad Razfc1273a2016-01-06 13:01:11 +01002921 kfree(mlxsw_sp_port->untagged_vlans);
2922err_port_untagged_vlans_alloc:
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002923 kfree(mlxsw_sp_port->active_vlans);
2924err_port_active_vlans_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002925 free_netdev(dev);
2926 return err;
2927}
2928
Jiri Pirko67963a32016-10-28 21:35:55 +02002929static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2930 bool split, u8 module, u8 width, u8 lane)
2931{
2932 int err;
2933
2934 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2935 if (err) {
2936 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2937 local_port);
2938 return err;
2939 }
Ido Schimmel9a60c902016-12-16 19:29:03 +01002940 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, split,
Jiri Pirko67963a32016-10-28 21:35:55 +02002941 module, width, lane);
2942 if (err)
2943 goto err_port_create;
2944 return 0;
2945
2946err_port_create:
2947 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2948 return err;
2949}
2950
2951static void __mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002952{
2953 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2954
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002955 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002956 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002957 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002958 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002959 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel05978482016-08-17 16:39:30 +02002960 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002961 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002962 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2963 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002964 kfree(mlxsw_sp_port->hw_stats.cache);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002965 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002966 free_percpu(mlxsw_sp_port->pcpu_stats);
Elad Razfc1273a2016-01-06 13:01:11 +01002967 kfree(mlxsw_sp_port->untagged_vlans);
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002968 kfree(mlxsw_sp_port->active_vlans);
Ido Schimmel32d863f2016-07-02 11:00:10 +02002969 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
Ido Schimmel31a08a52017-05-26 08:37:26 +02002970 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002971 free_netdev(mlxsw_sp_port->dev);
2972}
2973
Jiri Pirko67963a32016-10-28 21:35:55 +02002974static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2975{
2976 __mlxsw_sp_port_remove(mlxsw_sp, local_port);
2977 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2978}
2979
Jiri Pirkof83e2102016-10-28 21:35:49 +02002980static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2981{
2982 return mlxsw_sp->ports[local_port] != NULL;
2983}
2984
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002985static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2986{
2987 int i;
2988
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002989 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002990 if (mlxsw_sp_port_created(mlxsw_sp, i))
2991 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002992 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002993 kfree(mlxsw_sp->ports);
2994}
2995
2996static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2997{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002998 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02002999 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003000 size_t alloc_size;
3001 int i;
3002 int err;
3003
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003004 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003005 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3006 if (!mlxsw_sp->ports)
3007 return -ENOMEM;
3008
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003009 mlxsw_sp->port_to_module = kcalloc(max_ports, sizeof(u8), GFP_KERNEL);
3010 if (!mlxsw_sp->port_to_module) {
3011 err = -ENOMEM;
3012 goto err_port_to_module_alloc;
3013 }
3014
3015 for (i = 1; i < max_ports; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01003016 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003017 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003018 if (err)
3019 goto err_port_module_info_get;
3020 if (!width)
3021 continue;
3022 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003023 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3024 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003025 if (err)
3026 goto err_port_create;
3027 }
3028 return 0;
3029
3030err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003031err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003032 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003033 if (mlxsw_sp_port_created(mlxsw_sp, i))
3034 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003035 kfree(mlxsw_sp->port_to_module);
3036err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003037 kfree(mlxsw_sp->ports);
3038 return err;
3039}
3040
Ido Schimmel18f1e702016-02-26 17:32:31 +01003041static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3042{
3043 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3044
3045 return local_port - offset;
3046}
3047
Ido Schimmelbe945352016-06-09 09:51:39 +02003048static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3049 u8 module, unsigned int count)
3050{
3051 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3052 int err, i;
3053
3054 for (i = 0; i < count; i++) {
3055 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
3056 width, i * width);
3057 if (err)
3058 goto err_port_module_map;
3059 }
3060
3061 for (i = 0; i < count; i++) {
3062 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
3063 if (err)
3064 goto err_port_swid_set;
3065 }
3066
3067 for (i = 0; i < count; i++) {
3068 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003069 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003070 if (err)
3071 goto err_port_create;
3072 }
3073
3074 return 0;
3075
3076err_port_create:
3077 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003078 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3079 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003080 i = count;
3081err_port_swid_set:
3082 for (i--; i >= 0; i--)
3083 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
3084 MLXSW_PORT_SWID_DISABLED_PORT);
3085 i = count;
3086err_port_module_map:
3087 for (i--; i >= 0; i--)
3088 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
3089 return err;
3090}
3091
3092static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3093 u8 base_port, unsigned int count)
3094{
3095 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3096 int i;
3097
3098 /* Split by four means we need to re-create two ports, otherwise
3099 * only one.
3100 */
3101 count = count / 2;
3102
3103 for (i = 0; i < count; i++) {
3104 local_port = base_port + i * 2;
3105 module = mlxsw_sp->port_to_module[local_port];
3106
3107 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
3108 0);
3109 }
3110
3111 for (i = 0; i < count; i++)
3112 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
3113
3114 for (i = 0; i < count; i++) {
3115 local_port = base_port + i * 2;
3116 module = mlxsw_sp->port_to_module[local_port];
3117
3118 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003119 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003120 }
3121}
3122
Jiri Pirkob2f10572016-04-08 19:11:23 +02003123static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3124 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003125{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003126 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003127 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003128 u8 module, cur_width, base_port;
3129 int i;
3130 int err;
3131
3132 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3133 if (!mlxsw_sp_port) {
3134 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3135 local_port);
3136 return -EINVAL;
3137 }
3138
Ido Schimmeld664b412016-06-09 09:51:40 +02003139 module = mlxsw_sp_port->mapping.module;
3140 cur_width = mlxsw_sp_port->mapping.width;
3141
Ido Schimmel18f1e702016-02-26 17:32:31 +01003142 if (count != 2 && count != 4) {
3143 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3144 return -EINVAL;
3145 }
3146
Ido Schimmel18f1e702016-02-26 17:32:31 +01003147 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3148 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3149 return -EINVAL;
3150 }
3151
3152 /* Make sure we have enough slave (even) ports for the split. */
3153 if (count == 2) {
3154 base_port = local_port;
3155 if (mlxsw_sp->ports[base_port + 1]) {
3156 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3157 return -EINVAL;
3158 }
3159 } else {
3160 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3161 if (mlxsw_sp->ports[base_port + 1] ||
3162 mlxsw_sp->ports[base_port + 3]) {
3163 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3164 return -EINVAL;
3165 }
3166 }
3167
3168 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003169 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3170 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003171
Ido Schimmelbe945352016-06-09 09:51:39 +02003172 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3173 if (err) {
3174 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3175 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003176 }
3177
3178 return 0;
3179
Ido Schimmelbe945352016-06-09 09:51:39 +02003180err_port_split_create:
3181 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003182 return err;
3183}
3184
Jiri Pirkob2f10572016-04-08 19:11:23 +02003185static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003186{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003187 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003188 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003189 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003190 unsigned int count;
3191 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003192
3193 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3194 if (!mlxsw_sp_port) {
3195 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3196 local_port);
3197 return -EINVAL;
3198 }
3199
3200 if (!mlxsw_sp_port->split) {
3201 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3202 return -EINVAL;
3203 }
3204
Ido Schimmeld664b412016-06-09 09:51:40 +02003205 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003206 count = cur_width == 1 ? 4 : 2;
3207
3208 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3209
3210 /* Determine which ports to remove. */
3211 if (count == 2 && local_port >= base_port + 2)
3212 base_port = base_port + 2;
3213
3214 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003215 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3216 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003217
Ido Schimmelbe945352016-06-09 09:51:39 +02003218 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003219
3220 return 0;
3221}
3222
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003223static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3224 char *pude_pl, void *priv)
3225{
3226 struct mlxsw_sp *mlxsw_sp = priv;
3227 struct mlxsw_sp_port *mlxsw_sp_port;
3228 enum mlxsw_reg_pude_oper_status status;
3229 u8 local_port;
3230
3231 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3232 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003233 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003234 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003235
3236 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3237 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3238 netdev_info(mlxsw_sp_port->dev, "link up\n");
3239 netif_carrier_on(mlxsw_sp_port->dev);
3240 } else {
3241 netdev_info(mlxsw_sp_port->dev, "link down\n");
3242 netif_carrier_off(mlxsw_sp_port->dev);
3243 }
3244}
3245
Nogah Frankel14eeda92016-11-25 10:33:32 +01003246static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3247 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003248{
3249 struct mlxsw_sp *mlxsw_sp = priv;
3250 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3251 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3252
3253 if (unlikely(!mlxsw_sp_port)) {
3254 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3255 local_port);
3256 return;
3257 }
3258
3259 skb->dev = mlxsw_sp_port->dev;
3260
3261 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3262 u64_stats_update_begin(&pcpu_stats->syncp);
3263 pcpu_stats->rx_packets++;
3264 pcpu_stats->rx_bytes += skb->len;
3265 u64_stats_update_end(&pcpu_stats->syncp);
3266
3267 skb->protocol = eth_type_trans(skb, skb->dev);
3268 netif_receive_skb(skb);
3269}
3270
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003271static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3272 void *priv)
3273{
3274 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003275 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003276}
3277
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003278static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3279 void *priv)
3280{
3281 struct mlxsw_sp *mlxsw_sp = priv;
3282 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3283 struct psample_group *psample_group;
3284 u32 size;
3285
3286 if (unlikely(!mlxsw_sp_port)) {
3287 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3288 local_port);
3289 goto out;
3290 }
3291 if (unlikely(!mlxsw_sp_port->sample)) {
3292 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3293 local_port);
3294 goto out;
3295 }
3296
3297 size = mlxsw_sp_port->sample->truncate ?
3298 mlxsw_sp_port->sample->trunc_size : skb->len;
3299
3300 rcu_read_lock();
3301 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3302 if (!psample_group)
3303 goto out_unlock;
3304 psample_sample_packet(psample_group, skb, size,
3305 mlxsw_sp_port->dev->ifindex, 0,
3306 mlxsw_sp_port->sample->rate);
3307out_unlock:
3308 rcu_read_unlock();
3309out:
3310 consume_skb(skb);
3311}
3312
Nogah Frankel117b0da2016-11-25 10:33:44 +01003313#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003314 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003315 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003316
Nogah Frankel117b0da2016-11-25 10:33:44 +01003317#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003318 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003319 _is_ctrl, SP_##_trap_group, DISCARD)
3320
3321#define MLXSW_SP_EVENTL(_func, _trap_id) \
3322 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003323
Nogah Frankel45449132016-11-25 10:33:35 +01003324static const struct mlxsw_listener mlxsw_sp_listener[] = {
3325 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003326 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003327 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003328 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3329 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3330 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3331 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3332 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3333 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3334 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3335 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3336 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3337 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3338 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003339 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003340 /* L3 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003341 MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3342 MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3343 MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3344 MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, OSPF, false),
3345 MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
3346 MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
3347 MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, ARP_MISS, false),
3348 MLXSW_SP_RXL_NO_MARK(BGP_IPV4, TRAP_TO_CPU, BGP_IPV4, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003349 /* PKT Sample trap */
3350 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
3351 false, SP_IP2ME, DISCARD)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003352};
3353
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003354static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3355{
3356 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3357 enum mlxsw_reg_qpcr_ir_units ir_units;
3358 int max_cpu_policers;
3359 bool is_bytes;
3360 u8 burst_size;
3361 u32 rate;
3362 int i, err;
3363
3364 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3365 return -EIO;
3366
3367 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3368
3369 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3370 for (i = 0; i < max_cpu_policers; i++) {
3371 is_bytes = false;
3372 switch (i) {
3373 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3374 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3375 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3376 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3377 rate = 128;
3378 burst_size = 7;
3379 break;
3380 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3381 rate = 16 * 1024;
3382 burst_size = 10;
3383 break;
3384 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3385 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3386 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3387 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3388 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3389 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3390 rate = 1024;
3391 burst_size = 7;
3392 break;
3393 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3394 is_bytes = true;
3395 rate = 4 * 1024;
3396 burst_size = 4;
3397 break;
3398 default:
3399 continue;
3400 }
3401
3402 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3403 burst_size);
3404 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3405 if (err)
3406 return err;
3407 }
3408
3409 return 0;
3410}
3411
Nogah Frankel579c82e2016-11-25 10:33:42 +01003412static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003413{
3414 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003415 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003416 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003417 int max_trap_groups;
3418 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003419 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003420 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003421
3422 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3423 return -EIO;
3424
3425 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003426 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003427
3428 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003429 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003430 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003431 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3432 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3433 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3434 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3435 priority = 5;
3436 tc = 5;
3437 break;
3438 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3439 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3440 priority = 4;
3441 tc = 4;
3442 break;
3443 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3444 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3445 priority = 3;
3446 tc = 3;
3447 break;
3448 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3449 priority = 2;
3450 tc = 2;
3451 break;
3452 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3453 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3454 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3455 priority = 1;
3456 tc = 1;
3457 break;
3458 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003459 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3460 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003461 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003462 break;
3463 default:
3464 continue;
3465 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003466
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003467 if (max_cpu_policers <= policer_id &&
3468 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3469 return -EIO;
3470
3471 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003472 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3473 if (err)
3474 return err;
3475 }
3476
3477 return 0;
3478}
3479
3480static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3481{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003482 int i;
3483 int err;
3484
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003485 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3486 if (err)
3487 return err;
3488
Nogah Frankel579c82e2016-11-25 10:33:42 +01003489 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003490 if (err)
3491 return err;
3492
Nogah Frankel45449132016-11-25 10:33:35 +01003493 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003494 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003495 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003496 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003497 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003498 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003499
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003500 }
3501 return 0;
3502
Nogah Frankel45449132016-11-25 10:33:35 +01003503err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003504 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003505 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003506 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003507 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003508 }
3509 return err;
3510}
3511
3512static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3513{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003514 int i;
3515
Nogah Frankel45449132016-11-25 10:33:35 +01003516 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003517 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003518 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003519 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003520 }
3521}
3522
3523static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
3524 enum mlxsw_reg_sfgc_type type,
3525 enum mlxsw_reg_sfgc_bridge_type bridge_type)
3526{
3527 enum mlxsw_flood_table_type table_type;
3528 enum mlxsw_sp_flood_table flood_table;
3529 char sfgc_pl[MLXSW_REG_SFGC_LEN];
3530
Ido Schimmel19ae6122015-12-15 16:03:39 +01003531 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003532 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
Ido Schimmel19ae6122015-12-15 16:03:39 +01003533 else
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003534 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
Ido Schimmel19ae6122015-12-15 16:03:39 +01003535
Nogah Frankel71c365b2017-02-09 14:54:46 +01003536 switch (type) {
3537 case MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST:
Ido Schimmel19ae6122015-12-15 16:03:39 +01003538 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
Nogah Frankel71c365b2017-02-09 14:54:46 +01003539 break;
3540 case MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4:
Nogah Frankel71c365b2017-02-09 14:54:46 +01003541 flood_table = MLXSW_SP_FLOOD_TABLE_MC;
3542 break;
3543 default:
3544 flood_table = MLXSW_SP_FLOOD_TABLE_BC;
3545 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003546
3547 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
3548 flood_table);
3549 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
3550}
3551
3552static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
3553{
3554 int type, err;
3555
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003556 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
3557 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
3558 continue;
3559
3560 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3561 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
3562 if (err)
3563 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003564
3565 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3566 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
3567 if (err)
3568 return err;
3569 }
3570
3571 return 0;
3572}
3573
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003574static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3575{
3576 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003577 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003578
3579 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3580 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3581 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3582 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3583 MLXSW_REG_SLCR_LAG_HASH_SIP |
3584 MLXSW_REG_SLCR_LAG_HASH_DIP |
3585 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3586 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3587 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003588 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3589 if (err)
3590 return err;
3591
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003592 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3593 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003594 return -EIO;
3595
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003596 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003597 sizeof(struct mlxsw_sp_upper),
3598 GFP_KERNEL);
3599 if (!mlxsw_sp->lags)
3600 return -ENOMEM;
3601
3602 return 0;
3603}
3604
3605static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3606{
3607 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003608}
3609
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003610static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3611{
3612 char htgt_pl[MLXSW_REG_HTGT_LEN];
3613
Nogah Frankel579c82e2016-11-25 10:33:42 +01003614 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3615 MLXSW_REG_HTGT_INVALID_POLICER,
3616 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3617 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003618 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3619}
3620
Jiri Pirko202d6f42017-04-18 16:55:33 +02003621static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create);
3622
3623static int mlxsw_sp_dummy_fid_init(struct mlxsw_sp *mlxsw_sp)
3624{
3625 return mlxsw_sp_vfid_op(mlxsw_sp, MLXSW_SP_DUMMY_FID, true);
3626}
3627
3628static void mlxsw_sp_dummy_fid_fini(struct mlxsw_sp *mlxsw_sp)
3629{
3630 mlxsw_sp_vfid_op(mlxsw_sp, MLXSW_SP_DUMMY_FID, false);
3631}
3632
Jiri Pirkob2f10572016-04-08 19:11:23 +02003633static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003634 const struct mlxsw_bus_info *mlxsw_bus_info)
3635{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003636 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003637 int err;
3638
3639 mlxsw_sp->core = mlxsw_core;
3640 mlxsw_sp->bus_info = mlxsw_bus_info;
Ido Schimmel14d39462016-06-20 23:04:15 +02003641 INIT_LIST_HEAD(&mlxsw_sp->fids);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003642 INIT_LIST_HEAD(&mlxsw_sp->vfids.list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003643
Yotam Gigi6b742192017-05-23 21:56:29 +02003644 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3645 if (err) {
3646 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3647 return err;
3648 }
3649
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003650 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3651 if (err) {
3652 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3653 return err;
3654 }
3655
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003656 err = mlxsw_sp_traps_init(mlxsw_sp);
3657 if (err) {
Nogah Frankel45449132016-11-25 10:33:35 +01003658 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3659 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003660 }
3661
3662 err = mlxsw_sp_flood_init(mlxsw_sp);
3663 if (err) {
3664 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
3665 goto err_flood_init;
3666 }
3667
3668 err = mlxsw_sp_buffers_init(mlxsw_sp);
3669 if (err) {
3670 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3671 goto err_buffers_init;
3672 }
3673
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003674 err = mlxsw_sp_lag_init(mlxsw_sp);
3675 if (err) {
3676 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3677 goto err_lag_init;
3678 }
3679
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003680 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3681 if (err) {
3682 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3683 goto err_switchdev_init;
3684 }
3685
Ido Schimmel464dce12016-07-02 11:00:15 +02003686 err = mlxsw_sp_router_init(mlxsw_sp);
3687 if (err) {
3688 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3689 goto err_router_init;
3690 }
3691
Yotam Gigi763b4b72016-07-21 12:03:17 +02003692 err = mlxsw_sp_span_init(mlxsw_sp);
3693 if (err) {
3694 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3695 goto err_span_init;
3696 }
3697
Jiri Pirko22a67762017-02-03 10:29:07 +01003698 err = mlxsw_sp_acl_init(mlxsw_sp);
3699 if (err) {
3700 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3701 goto err_acl_init;
3702 }
3703
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003704 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3705 if (err) {
3706 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3707 goto err_counter_pool_init;
3708 }
3709
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003710 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3711 if (err) {
3712 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3713 goto err_dpipe_init;
3714 }
3715
Jiri Pirko202d6f42017-04-18 16:55:33 +02003716 err = mlxsw_sp_dummy_fid_init(mlxsw_sp);
3717 if (err) {
3718 dev_err(mlxsw_sp->bus_info->dev, "Failed to init dummy FID\n");
3719 goto err_dummy_fid_init;
3720 }
3721
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003722 err = mlxsw_sp_ports_create(mlxsw_sp);
3723 if (err) {
3724 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3725 goto err_ports_create;
3726 }
3727
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003728 return 0;
3729
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003730err_ports_create:
Jiri Pirko202d6f42017-04-18 16:55:33 +02003731 mlxsw_sp_dummy_fid_fini(mlxsw_sp);
3732err_dummy_fid_init:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003733 mlxsw_sp_dpipe_fini(mlxsw_sp);
3734err_dpipe_init:
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003735 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3736err_counter_pool_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003737 mlxsw_sp_acl_fini(mlxsw_sp);
3738err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02003739 mlxsw_sp_span_fini(mlxsw_sp);
3740err_span_init:
Ido Schimmel464dce12016-07-02 11:00:15 +02003741 mlxsw_sp_router_fini(mlxsw_sp);
3742err_router_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003743 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003744err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003745 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003746err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003747 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003748err_buffers_init:
3749err_flood_init:
3750 mlxsw_sp_traps_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003751 return err;
3752}
3753
Jiri Pirkob2f10572016-04-08 19:11:23 +02003754static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003755{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003756 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003757
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003758 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko202d6f42017-04-18 16:55:33 +02003759 mlxsw_sp_dummy_fid_fini(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003760 mlxsw_sp_dpipe_fini(mlxsw_sp);
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003761 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003762 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003763 mlxsw_sp_span_fini(mlxsw_sp);
Ido Schimmel464dce12016-07-02 11:00:15 +02003764 mlxsw_sp_router_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003765 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003766 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003767 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003768 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003769 WARN_ON(!list_empty(&mlxsw_sp->vfids.list));
Ido Schimmel14d39462016-06-20 23:04:15 +02003770 WARN_ON(!list_empty(&mlxsw_sp->fids));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003771}
3772
3773static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3774 .used_max_vepa_channels = 1,
3775 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003776 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003777 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003778 .used_max_pgt = 1,
3779 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003780 .used_flood_tables = 1,
3781 .used_flood_mode = 1,
3782 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003783 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003784 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003785 .max_fid_flood_tables = 3,
Ido Schimmel19ae6122015-12-15 16:03:39 +01003786 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003787 .used_max_ib_mc = 1,
3788 .max_ib_mc = 0,
3789 .used_max_pkey = 1,
3790 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003791 .used_kvd_split_data = 1,
3792 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3793 .kvd_hash_single_parts = 2,
3794 .kvd_hash_double_parts = 1,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003795 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003796 .swid_config = {
3797 {
3798 .used_type = 1,
3799 .type = MLXSW_PORT_SWID_TYPE_ETH,
3800 }
3801 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003802 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003803};
3804
3805static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003806 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003807 .priv_size = sizeof(struct mlxsw_sp),
3808 .init = mlxsw_sp_init,
3809 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003810 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003811 .port_split = mlxsw_sp_port_split,
3812 .port_unsplit = mlxsw_sp_port_unsplit,
3813 .sb_pool_get = mlxsw_sp_sb_pool_get,
3814 .sb_pool_set = mlxsw_sp_sb_pool_set,
3815 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3816 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3817 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3818 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3819 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3820 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3821 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3822 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3823 .txhdr_construct = mlxsw_sp_txhdr_construct,
3824 .txhdr_len = MLXSW_TXHDR_LEN,
3825 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003826};
3827
Jiri Pirko22a67762017-02-03 10:29:07 +01003828bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003829{
3830 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3831}
3832
Jiri Pirko1182e532017-03-06 21:25:20 +01003833static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07003834{
Jiri Pirko1182e532017-03-06 21:25:20 +01003835 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07003836 int ret = 0;
3837
3838 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01003839 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07003840 ret = 1;
3841 }
3842
3843 return ret;
3844}
3845
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003846static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
3847{
Jiri Pirko1182e532017-03-06 21:25:20 +01003848 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003849
3850 if (mlxsw_sp_port_dev_check(dev))
3851 return netdev_priv(dev);
3852
Jiri Pirko1182e532017-03-06 21:25:20 +01003853 mlxsw_sp_port = NULL;
3854 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003855
Jiri Pirko1182e532017-03-06 21:25:20 +01003856 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003857}
3858
Ido Schimmel4724ba562017-03-10 08:53:39 +01003859struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003860{
3861 struct mlxsw_sp_port *mlxsw_sp_port;
3862
3863 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3864 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3865}
3866
3867static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
3868{
Jiri Pirko1182e532017-03-06 21:25:20 +01003869 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003870
3871 if (mlxsw_sp_port_dev_check(dev))
3872 return netdev_priv(dev);
3873
Jiri Pirko1182e532017-03-06 21:25:20 +01003874 mlxsw_sp_port = NULL;
3875 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
3876 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003877
Jiri Pirko1182e532017-03-06 21:25:20 +01003878 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003879}
3880
3881struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3882{
3883 struct mlxsw_sp_port *mlxsw_sp_port;
3884
3885 rcu_read_lock();
3886 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3887 if (mlxsw_sp_port)
3888 dev_hold(mlxsw_sp_port->dev);
3889 rcu_read_unlock();
3890 return mlxsw_sp_port;
3891}
3892
3893void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3894{
3895 dev_put(mlxsw_sp_port->dev);
3896}
3897
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003898static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
3899 u16 fid)
3900{
3901 if (mlxsw_sp_fid_is_vfid(fid))
3902 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
3903 else
3904 return test_bit(fid, lag_port->active_vlans);
3905}
3906
3907static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
3908 u16 fid)
Ido Schimmel039c49a2016-01-27 15:20:18 +01003909{
3910 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003911 u8 local_port = mlxsw_sp_port->local_port;
3912 u16 lag_id = mlxsw_sp_port->lag_id;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003913 u64 max_lag_members;
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003914 int i, count = 0;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003915
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003916 if (!mlxsw_sp_port->lagged)
3917 return true;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003918
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003919 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3920 MAX_LAG_MEMBERS);
3921 for (i = 0; i < max_lag_members; i++) {
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003922 struct mlxsw_sp_port *lag_port;
3923
3924 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
3925 if (!lag_port || lag_port->local_port == local_port)
3926 continue;
3927 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
3928 count++;
3929 }
3930
3931 return !count;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003932}
3933
3934static int
3935mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3936 u16 fid)
3937{
3938 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3939 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3940
3941 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
3942 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3943 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
3944 mlxsw_sp_port->local_port);
3945
Ido Schimmel22305372016-06-20 23:04:21 +02003946 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
3947 mlxsw_sp_port->local_port, fid);
3948
Ido Schimmel039c49a2016-01-27 15:20:18 +01003949 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3950}
3951
3952static int
Ido Schimmel039c49a2016-01-27 15:20:18 +01003953mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3954 u16 fid)
3955{
3956 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3957 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3958
3959 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
3960 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3961 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
3962
Ido Schimmel22305372016-06-20 23:04:21 +02003963 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
3964 mlxsw_sp_port->lag_id, fid);
3965
Ido Schimmel039c49a2016-01-27 15:20:18 +01003966 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3967}
3968
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003969int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
Ido Schimmel039c49a2016-01-27 15:20:18 +01003970{
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003971 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
3972 return 0;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003973
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003974 if (mlxsw_sp_port->lagged)
3975 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
Ido Schimmel039c49a2016-01-27 15:20:18 +01003976 fid);
3977 else
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003978 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
Ido Schimmel039c49a2016-01-27 15:20:18 +01003979}
3980
Ido Schimmel701b1862016-07-04 08:23:16 +02003981static void mlxsw_sp_master_bridge_gone_sync(struct mlxsw_sp *mlxsw_sp)
3982{
3983 struct mlxsw_sp_fid *f, *tmp;
3984
3985 list_for_each_entry_safe(f, tmp, &mlxsw_sp->fids, list)
3986 if (--f->ref_count == 0)
3987 mlxsw_sp_fid_destroy(mlxsw_sp, f);
3988 else
3989 WARN_ON_ONCE(1);
3990}
3991
Ido Schimmel7117a572016-06-20 23:04:06 +02003992static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
3993 struct net_device *br_dev)
3994{
Ido Schimmel5f6935c2017-05-16 19:38:26 +02003995 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
3996
3997 return !master_bridge->dev || master_bridge->dev == br_dev;
Ido Schimmel7117a572016-06-20 23:04:06 +02003998}
3999
4000static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
4001 struct net_device *br_dev)
4002{
Ido Schimmel5f6935c2017-05-16 19:38:26 +02004003 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
4004
4005 master_bridge->dev = br_dev;
4006 master_bridge->ref_count++;
Ido Schimmel7117a572016-06-20 23:04:06 +02004007}
4008
4009static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
4010{
Ido Schimmel5f6935c2017-05-16 19:38:26 +02004011 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
4012
4013 if (--master_bridge->ref_count == 0) {
4014 master_bridge->dev = NULL;
Ido Schimmel701b1862016-07-04 08:23:16 +02004015 /* It's possible upper VLAN devices are still holding
4016 * references to underlying FIDs. Drop the reference
4017 * and release the resources if it was the last one.
4018 * If it wasn't, then something bad happened.
4019 */
4020 mlxsw_sp_master_bridge_gone_sync(mlxsw_sp);
4021 }
Ido Schimmel7117a572016-06-20 23:04:06 +02004022}
4023
4024static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
4025 struct net_device *br_dev)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004026{
4027 struct net_device *dev = mlxsw_sp_port->dev;
4028 int err;
4029
4030 /* When port is not bridged untagged packets are tagged with
4031 * PVID=VID=1, thereby creating an implicit VLAN interface in
4032 * the device. Remove it and let bridge code take care of its
4033 * own VLANs.
4034 */
4035 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01004036 if (err)
4037 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004038
Ido Schimmel7117a572016-06-20 23:04:06 +02004039 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
4040
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01004041 mlxsw_sp_port->learning = 1;
4042 mlxsw_sp_port->learning_sync = 1;
4043 mlxsw_sp_port->uc_flood = 1;
Nogah Frankel71c365b2017-02-09 14:54:46 +01004044 mlxsw_sp_port->mc_flood = 1;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01004045 mlxsw_sp_port->mc_router = 0;
4046 mlxsw_sp_port->mc_disabled = 1;
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01004047 mlxsw_sp_port->bridged = 1;
4048
4049 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004050}
4051
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004052static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004053{
4054 struct net_device *dev = mlxsw_sp_port->dev;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01004055
Ido Schimmel28a01d22016-02-18 11:30:02 +01004056 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
4057
Ido Schimmel7117a572016-06-20 23:04:06 +02004058 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
4059
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01004060 mlxsw_sp_port->learning = 0;
4061 mlxsw_sp_port->learning_sync = 0;
4062 mlxsw_sp_port->uc_flood = 0;
Nogah Frankel71c365b2017-02-09 14:54:46 +01004063 mlxsw_sp_port->mc_flood = 0;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01004064 mlxsw_sp_port->mc_router = 0;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01004065 mlxsw_sp_port->bridged = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004066
4067 /* Add implicit VLAN interface in the device, so that untagged
4068 * packets will be classified to the default vFID.
4069 */
Ido Schimmel82e6db02016-06-20 23:04:04 +02004070 mlxsw_sp_port_add_vid(dev, 0, 1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004071}
4072
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004073static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004074{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004075 char sldr_pl[MLXSW_REG_SLDR_LEN];
4076
4077 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4078 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4079}
4080
4081static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4082{
4083 char sldr_pl[MLXSW_REG_SLDR_LEN];
4084
4085 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4086 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4087}
4088
4089static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4090 u16 lag_id, u8 port_index)
4091{
4092 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4093 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4094
4095 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4096 lag_id, port_index);
4097 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4098}
4099
4100static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4101 u16 lag_id)
4102{
4103 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4104 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4105
4106 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4107 lag_id);
4108 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4109}
4110
4111static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4112 u16 lag_id)
4113{
4114 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4115 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4116
4117 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4118 lag_id);
4119 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4120}
4121
4122static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4123 u16 lag_id)
4124{
4125 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4126 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4127
4128 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4129 lag_id);
4130 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4131}
4132
4133static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4134 struct net_device *lag_dev,
4135 u16 *p_lag_id)
4136{
4137 struct mlxsw_sp_upper *lag;
4138 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004139 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004140 int i;
4141
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004142 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4143 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004144 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4145 if (lag->ref_count) {
4146 if (lag->dev == lag_dev) {
4147 *p_lag_id = i;
4148 return 0;
4149 }
4150 } else if (free_lag_id < 0) {
4151 free_lag_id = i;
4152 }
4153 }
4154 if (free_lag_id < 0)
4155 return -EBUSY;
4156 *p_lag_id = free_lag_id;
4157 return 0;
4158}
4159
4160static bool
4161mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4162 struct net_device *lag_dev,
4163 struct netdev_lag_upper_info *lag_upper_info)
4164{
4165 u16 lag_id;
4166
4167 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
4168 return false;
4169 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
4170 return false;
4171 return true;
4172}
4173
4174static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4175 u16 lag_id, u8 *p_port_index)
4176{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004177 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004178 int i;
4179
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004180 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4181 MAX_LAG_MEMBERS);
4182 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004183 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4184 *p_port_index = i;
4185 return 0;
4186 }
4187 }
4188 return -EBUSY;
4189}
4190
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004191static void
4192mlxsw_sp_port_pvid_vport_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel186962e2017-03-10 08:53:36 +01004193 struct net_device *lag_dev, u16 lag_id)
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004194{
4195 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel11943ff2016-07-02 11:00:12 +02004196 struct mlxsw_sp_fid *f;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004197
4198 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
4199 if (WARN_ON(!mlxsw_sp_vport))
4200 return;
4201
Ido Schimmel11943ff2016-07-02 11:00:12 +02004202 /* If vPort is assigned a RIF, then leave it since it's no
4203 * longer valid.
4204 */
4205 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4206 if (f)
4207 f->leave(mlxsw_sp_vport);
4208
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004209 mlxsw_sp_vport->lag_id = lag_id;
4210 mlxsw_sp_vport->lagged = 1;
Ido Schimmel186962e2017-03-10 08:53:36 +01004211 mlxsw_sp_vport->dev = lag_dev;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004212}
4213
4214static void
4215mlxsw_sp_port_pvid_vport_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4216{
4217 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel11943ff2016-07-02 11:00:12 +02004218 struct mlxsw_sp_fid *f;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004219
4220 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
4221 if (WARN_ON(!mlxsw_sp_vport))
4222 return;
4223
Ido Schimmel11943ff2016-07-02 11:00:12 +02004224 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4225 if (f)
4226 f->leave(mlxsw_sp_vport);
4227
Ido Schimmel186962e2017-03-10 08:53:36 +01004228 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004229 mlxsw_sp_vport->lagged = 0;
4230}
4231
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004232static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4233 struct net_device *lag_dev)
4234{
4235 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4236 struct mlxsw_sp_upper *lag;
4237 u16 lag_id;
4238 u8 port_index;
4239 int err;
4240
4241 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4242 if (err)
4243 return err;
4244 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4245 if (!lag->ref_count) {
4246 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4247 if (err)
4248 return err;
4249 lag->dev = lag_dev;
4250 }
4251
4252 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4253 if (err)
4254 return err;
4255 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4256 if (err)
4257 goto err_col_port_add;
4258 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4259 if (err)
4260 goto err_col_port_enable;
4261
4262 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4263 mlxsw_sp_port->local_port);
4264 mlxsw_sp_port->lag_id = lag_id;
4265 mlxsw_sp_port->lagged = 1;
4266 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004267
Ido Schimmel186962e2017-03-10 08:53:36 +01004268 mlxsw_sp_port_pvid_vport_lag_join(mlxsw_sp_port, lag_dev, lag_id);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004269
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004270 return 0;
4271
Ido Schimmel51554db2016-05-06 22:18:39 +02004272err_col_port_enable:
4273 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004274err_col_port_add:
4275 if (!lag->ref_count)
4276 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004277 return err;
4278}
4279
Ido Schimmel82e6db02016-06-20 23:04:04 +02004280static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4281 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004282{
4283 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004284 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004285 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004286
4287 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004288 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004289 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4290 WARN_ON(lag->ref_count == 0);
4291
Ido Schimmel82e6db02016-06-20 23:04:04 +02004292 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4293 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004294
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004295 if (mlxsw_sp_port->bridged) {
4296 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004297 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004298 }
4299
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004300 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004301 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004302
4303 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4304 mlxsw_sp_port->local_port);
4305 mlxsw_sp_port->lagged = 0;
4306 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004307
4308 mlxsw_sp_port_pvid_vport_lag_leave(mlxsw_sp_port);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004309}
4310
Jiri Pirko74581202015-12-03 12:12:30 +01004311static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4312 u16 lag_id)
4313{
4314 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4315 char sldr_pl[MLXSW_REG_SLDR_LEN];
4316
4317 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4318 mlxsw_sp_port->local_port);
4319 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4320}
4321
4322static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4323 u16 lag_id)
4324{
4325 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4326 char sldr_pl[MLXSW_REG_SLDR_LEN];
4327
4328 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4329 mlxsw_sp_port->local_port);
4330 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4331}
4332
4333static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4334 bool lag_tx_enabled)
4335{
4336 if (lag_tx_enabled)
4337 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4338 mlxsw_sp_port->lag_id);
4339 else
4340 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4341 mlxsw_sp_port->lag_id);
4342}
4343
4344static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4345 struct netdev_lag_lower_state_info *info)
4346{
4347 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4348}
4349
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004350static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
4351 struct net_device *vlan_dev)
4352{
4353 struct mlxsw_sp_port *mlxsw_sp_vport;
4354 u16 vid = vlan_dev_vlan_id(vlan_dev);
4355
4356 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02004357 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004358 return -EINVAL;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004359
4360 mlxsw_sp_vport->dev = vlan_dev;
4361
4362 return 0;
4363}
4364
Ido Schimmel82e6db02016-06-20 23:04:04 +02004365static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
4366 struct net_device *vlan_dev)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004367{
4368 struct mlxsw_sp_port *mlxsw_sp_vport;
4369 u16 vid = vlan_dev_vlan_id(vlan_dev);
4370
4371 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02004372 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel82e6db02016-06-20 23:04:04 +02004373 return;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004374
4375 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004376}
4377
Jiri Pirko2b94e582017-04-18 16:55:37 +02004378static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4379 bool enable)
4380{
4381 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4382 enum mlxsw_reg_spms_state spms_state;
4383 char *spms_pl;
4384 u16 vid;
4385 int err;
4386
4387 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4388 MLXSW_REG_SPMS_STATE_DISCARDING;
4389
4390 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4391 if (!spms_pl)
4392 return -ENOMEM;
4393 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4394
4395 for (vid = 0; vid < VLAN_N_VID; vid++)
4396 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4397
4398 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4399 kfree(spms_pl);
4400 return err;
4401}
4402
4403static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4404{
4405 int err;
4406
Ido Schimmel4aafc362017-05-26 08:37:25 +02004407 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004408 if (err)
4409 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004410 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4411 if (err)
4412 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004413 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4414 true, false);
4415 if (err)
4416 goto err_port_vlan_set;
4417 return 0;
4418
4419err_port_vlan_set:
4420 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004421err_port_stp_set:
4422 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004423 return err;
4424}
4425
4426static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4427{
4428 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4429 false, false);
4430 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004431 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004432}
4433
Jiri Pirko74581202015-12-03 12:12:30 +01004434static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
4435 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004436{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004437 struct netdev_notifier_changeupper_info *info;
4438 struct mlxsw_sp_port *mlxsw_sp_port;
4439 struct net_device *upper_dev;
4440 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004441 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004442
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004443 mlxsw_sp_port = netdev_priv(dev);
4444 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4445 info = ptr;
4446
4447 switch (event) {
4448 case NETDEV_PRECHANGEUPPER:
4449 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004450 if (!is_vlan_dev(upper_dev) &&
4451 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004452 !netif_is_bridge_master(upper_dev) &&
Jiri Pirko2b94e582017-04-18 16:55:37 +02004453 !netif_is_ovs_master(upper_dev))
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004454 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004455 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004456 break;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004457 /* HW limitation forbids to put ports to multiple bridges. */
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004458 if (netif_is_bridge_master(upper_dev) &&
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004459 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004460 return -EINVAL;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004461 if (netif_is_lag_master(upper_dev) &&
4462 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4463 info->upper_info))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004464 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004465 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4466 return -EINVAL;
4467 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4468 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4469 return -EINVAL;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004470 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev))
4471 return -EINVAL;
4472 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev))
4473 return -EINVAL;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004474 break;
4475 case NETDEV_CHANGEUPPER:
4476 upper_dev = info->upper_dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004477 if (is_vlan_dev(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004478 if (info->linking)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004479 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
4480 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004481 else
Jiri Pirkob51df792017-04-18 16:55:31 +02004482 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
4483 upper_dev);
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004484 } else if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004485 if (info->linking)
4486 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4487 upper_dev);
4488 else
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004489 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004490 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004491 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004492 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4493 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004494 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004495 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4496 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004497 } else if (netif_is_ovs_master(upper_dev)) {
4498 if (info->linking)
4499 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4500 else
4501 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004502 } else {
4503 err = -EINVAL;
4504 WARN_ON(1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004505 }
4506 break;
4507 }
4508
Ido Schimmel80bedf12016-06-20 23:03:59 +02004509 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004510}
4511
Jiri Pirko74581202015-12-03 12:12:30 +01004512static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4513 unsigned long event, void *ptr)
4514{
4515 struct netdev_notifier_changelowerstate_info *info;
4516 struct mlxsw_sp_port *mlxsw_sp_port;
4517 int err;
4518
4519 mlxsw_sp_port = netdev_priv(dev);
4520 info = ptr;
4521
4522 switch (event) {
4523 case NETDEV_CHANGELOWERSTATE:
4524 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4525 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4526 info->lower_state_info);
4527 if (err)
4528 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4529 }
4530 break;
4531 }
4532
Ido Schimmel80bedf12016-06-20 23:03:59 +02004533 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004534}
4535
4536static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
4537 unsigned long event, void *ptr)
4538{
4539 switch (event) {
4540 case NETDEV_PRECHANGEUPPER:
4541 case NETDEV_CHANGEUPPER:
4542 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
4543 case NETDEV_CHANGELOWERSTATE:
4544 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
4545 }
4546
Ido Schimmel80bedf12016-06-20 23:03:59 +02004547 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004548}
4549
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004550static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4551 unsigned long event, void *ptr)
4552{
4553 struct net_device *dev;
4554 struct list_head *iter;
4555 int ret;
4556
4557 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4558 if (mlxsw_sp_port_dev_check(dev)) {
4559 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004560 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004561 return ret;
4562 }
4563 }
4564
Ido Schimmel80bedf12016-06-20 23:03:59 +02004565 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004566}
4567
Ido Schimmel701b1862016-07-04 08:23:16 +02004568static int mlxsw_sp_master_bridge_vlan_link(struct mlxsw_sp *mlxsw_sp,
4569 struct net_device *vlan_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004570{
Ido Schimmel701b1862016-07-04 08:23:16 +02004571 u16 fid = vlan_dev_vlan_id(vlan_dev);
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004572 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004573
Ido Schimmel701b1862016-07-04 08:23:16 +02004574 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
4575 if (!f) {
4576 f = mlxsw_sp_fid_create(mlxsw_sp, fid);
4577 if (IS_ERR(f))
4578 return PTR_ERR(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004579 }
4580
Ido Schimmel701b1862016-07-04 08:23:16 +02004581 f->ref_count++;
4582
4583 return 0;
4584}
4585
4586static void mlxsw_sp_master_bridge_vlan_unlink(struct mlxsw_sp *mlxsw_sp,
4587 struct net_device *vlan_dev)
4588{
4589 u16 fid = vlan_dev_vlan_id(vlan_dev);
4590 struct mlxsw_sp_fid *f;
4591
4592 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
Arkadi Sharshevskybf952332017-03-17 09:38:00 +01004593 if (f && f->rif)
4594 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->rif);
Ido Schimmel701b1862016-07-04 08:23:16 +02004595 if (f && --f->ref_count == 0)
4596 mlxsw_sp_fid_destroy(mlxsw_sp, f);
4597}
4598
4599static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4600 unsigned long event, void *ptr)
4601{
4602 struct netdev_notifier_changeupper_info *info;
4603 struct net_device *upper_dev;
4604 struct mlxsw_sp *mlxsw_sp;
Ido Schimmelb4149702017-03-10 08:53:34 +01004605 int err = 0;
Ido Schimmel701b1862016-07-04 08:23:16 +02004606
4607 mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4608 if (!mlxsw_sp)
4609 return 0;
Ido Schimmel701b1862016-07-04 08:23:16 +02004610
4611 info = ptr;
4612
4613 switch (event) {
Ido Schimmelb4149702017-03-10 08:53:34 +01004614 case NETDEV_PRECHANGEUPPER:
Ido Schimmel701b1862016-07-04 08:23:16 +02004615 upper_dev = info->upper_dev;
Ido Schimmelb1e45522017-04-30 19:47:14 +03004616 if (!is_vlan_dev(upper_dev))
Ido Schimmelb4149702017-03-10 08:53:34 +01004617 return -EINVAL;
4618 if (is_vlan_dev(upper_dev) &&
Ido Schimmel5f6935c2017-05-16 19:38:26 +02004619 br_dev != mlxsw_sp_master_bridge(mlxsw_sp)->dev)
Ido Schimmelb4149702017-03-10 08:53:34 +01004620 return -EINVAL;
4621 break;
4622 case NETDEV_CHANGEUPPER:
4623 upper_dev = info->upper_dev;
4624 if (is_vlan_dev(upper_dev)) {
4625 if (info->linking)
4626 err = mlxsw_sp_master_bridge_vlan_link(mlxsw_sp,
4627 upper_dev);
4628 else
4629 mlxsw_sp_master_bridge_vlan_unlink(mlxsw_sp,
4630 upper_dev);
Ido Schimmel701b1862016-07-04 08:23:16 +02004631 } else {
Ido Schimmelb4149702017-03-10 08:53:34 +01004632 err = -EINVAL;
4633 WARN_ON(1);
Ido Schimmel701b1862016-07-04 08:23:16 +02004634 }
4635 break;
4636 }
4637
Ido Schimmelb4149702017-03-10 08:53:34 +01004638 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004639}
4640
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004641static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004642{
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004643 return find_first_zero_bit(mlxsw_sp->vfids.mapped,
Ido Schimmel99724c12016-07-04 08:23:14 +02004644 MLXSW_SP_VFID_MAX);
4645}
4646
4647static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
4648{
4649 char sfmr_pl[MLXSW_REG_SFMR_LEN];
4650
4651 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
4652 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004653}
4654
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004655static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport);
Ido Schimmel1c800752016-06-20 23:04:20 +02004656
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004657static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
4658 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004659{
4660 struct device *dev = mlxsw_sp->bus_info->dev;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004661 struct mlxsw_sp_fid *f;
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004662 u16 vfid, fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004663 int err;
4664
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004665 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004666 if (vfid == MLXSW_SP_VFID_MAX) {
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004667 dev_err(dev, "No available vFIDs\n");
4668 return ERR_PTR(-ERANGE);
4669 }
4670
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004671 fid = mlxsw_sp_vfid_to_fid(vfid);
4672 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004673 if (err) {
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004674 dev_err(dev, "Failed to create FID=%d\n", fid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004675 return ERR_PTR(err);
4676 }
4677
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004678 f = kzalloc(sizeof(*f), GFP_KERNEL);
4679 if (!f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004680 goto err_allocate_vfid;
4681
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004682 f->leave = mlxsw_sp_vport_vfid_leave;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004683 f->fid = fid;
4684 f->dev = br_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004685
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004686 list_add(&f->list, &mlxsw_sp->vfids.list);
4687 set_bit(vfid, mlxsw_sp->vfids.mapped);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004688
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004689 return f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004690
4691err_allocate_vfid:
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004692 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004693 return ERR_PTR(-ENOMEM);
4694}
4695
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004696static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
4697 struct mlxsw_sp_fid *f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004698{
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004699 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02004700 u16 fid = f->fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004701
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004702 clear_bit(vfid, mlxsw_sp->vfids.mapped);
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004703 list_del(&f->list);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004704
Arkadi Sharshevskybf952332017-03-17 09:38:00 +01004705 if (f->rif)
4706 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->rif);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004707
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004708 kfree(f);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02004709
4710 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004711}
4712
Ido Schimmel99724c12016-07-04 08:23:14 +02004713static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
4714 bool valid)
4715{
4716 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
4717 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4718
4719 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
4720 vid);
4721}
4722
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004723static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4724 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004725{
Ido Schimmel4aafc362017-05-26 08:37:25 +02004726 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel0355b592016-06-20 23:04:13 +02004727 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004728 int err;
4729
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004730 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
Ido Schimmel0355b592016-06-20 23:04:13 +02004731 if (!f) {
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004732 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
Ido Schimmel0355b592016-06-20 23:04:13 +02004733 if (IS_ERR(f))
4734 return PTR_ERR(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004735 }
4736
Ido Schimmel0355b592016-06-20 23:04:13 +02004737 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
4738 if (err)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004739 goto err_vport_flood_set;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004740
Ido Schimmel0355b592016-06-20 23:04:13 +02004741 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
4742 if (err)
4743 goto err_vport_fid_map;
Ido Schimmel6a9863a2016-02-15 13:19:54 +01004744
Ido Schimmel4aafc362017-05-26 08:37:25 +02004745 mlxsw_sp_port = mlxsw_sp_vport_port(mlxsw_sp_vport);
4746 if (mlxsw_sp_port->nr_port_vid_map++ == 0) {
4747 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
4748 if (err)
4749 goto err_port_vp_mode_trans;
4750 }
4751
Ido Schimmel41b996c2016-06-20 23:04:17 +02004752 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
Ido Schimmel0355b592016-06-20 23:04:13 +02004753 f->ref_count++;
Ido Schimmel039c49a2016-01-27 15:20:18 +01004754
Ido Schimmel22305372016-06-20 23:04:21 +02004755 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
4756
Ido Schimmel0355b592016-06-20 23:04:13 +02004757 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004758
Ido Schimmel4aafc362017-05-26 08:37:25 +02004759err_port_vp_mode_trans:
4760 mlxsw_sp_port->nr_port_vid_map--;
4761 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
Ido Schimmel9c4d4422016-06-20 23:04:10 +02004762err_vport_fid_map:
Ido Schimmel0355b592016-06-20 23:04:13 +02004763 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4764err_vport_flood_set:
4765 if (!f->ref_count)
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004766 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
Ido Schimmel0355b592016-06-20 23:04:13 +02004767 return err;
4768}
4769
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004770static void mlxsw_sp_vport_vfid_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02004771{
Ido Schimmel41b996c2016-06-20 23:04:17 +02004772 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004773 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel0355b592016-06-20 23:04:13 +02004774
Ido Schimmel22305372016-06-20 23:04:21 +02004775 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
4776
Ido Schimmel4aafc362017-05-26 08:37:25 +02004777 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
4778 f->ref_count--;
4779
4780 mlxsw_sp_port = mlxsw_sp_vport_port(mlxsw_sp_vport);
4781 if (mlxsw_sp_port->nr_port_vid_map == 1)
4782 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
4783 mlxsw_sp_port->nr_port_vid_map--;
4784
Ido Schimmel0355b592016-06-20 23:04:13 +02004785 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
4786
4787 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4788
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004789 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
4790
Ido Schimmel4aafc362017-05-26 08:37:25 +02004791 if (f->ref_count == 0)
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004792 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004793}
4794
4795static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4796 struct net_device *br_dev)
4797{
Ido Schimmel99724c12016-07-04 08:23:14 +02004798 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004799 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4800 struct net_device *dev = mlxsw_sp_vport->dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004801 int err;
4802
Ido Schimmel99724c12016-07-04 08:23:14 +02004803 if (f && !WARN_ON(!f->leave))
4804 f->leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004805
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004806 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport, br_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004807 if (err) {
Ido Schimmel0355b592016-06-20 23:04:13 +02004808 netdev_err(dev, "Failed to join vFID\n");
Ido Schimmel99724c12016-07-04 08:23:14 +02004809 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004810 }
4811
4812 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
4813 if (err) {
4814 netdev_err(dev, "Failed to enable learning\n");
4815 goto err_port_vid_learning_set;
4816 }
4817
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004818 mlxsw_sp_vport->learning = 1;
4819 mlxsw_sp_vport->learning_sync = 1;
4820 mlxsw_sp_vport->uc_flood = 1;
Nogah Frankel71c365b2017-02-09 14:54:46 +01004821 mlxsw_sp_vport->mc_flood = 1;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01004822 mlxsw_sp_vport->mc_router = 0;
4823 mlxsw_sp_vport->mc_disabled = 1;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004824 mlxsw_sp_vport->bridged = 1;
4825
4826 return 0;
4827
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004828err_port_vid_learning_set:
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004829 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004830 return err;
4831}
4832
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004833static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02004834{
4835 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02004836
4837 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
4838
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004839 mlxsw_sp_vport_vfid_leave(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02004840
Ido Schimmel0355b592016-06-20 23:04:13 +02004841 mlxsw_sp_vport->learning = 0;
4842 mlxsw_sp_vport->learning_sync = 0;
4843 mlxsw_sp_vport->uc_flood = 0;
Nogah Frankel71c365b2017-02-09 14:54:46 +01004844 mlxsw_sp_vport->mc_flood = 0;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01004845 mlxsw_sp_vport->mc_router = 0;
Ido Schimmel0355b592016-06-20 23:04:13 +02004846 mlxsw_sp_vport->bridged = 0;
4847}
4848
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004849static bool
4850mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
4851 const struct net_device *br_dev)
4852{
4853 struct mlxsw_sp_port *mlxsw_sp_vport;
4854
4855 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
4856 vport.list) {
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004857 struct net_device *dev = mlxsw_sp_vport_dev_get(mlxsw_sp_vport);
Ido Schimmel56918b62016-06-20 23:04:18 +02004858
4859 if (dev && dev == br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004860 return false;
4861 }
4862
4863 return true;
4864}
4865
4866static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
4867 unsigned long event, void *ptr,
4868 u16 vid)
4869{
4870 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4871 struct netdev_notifier_changeupper_info *info = ptr;
4872 struct mlxsw_sp_port *mlxsw_sp_vport;
4873 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004874 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004875
4876 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel1f880612017-03-10 08:53:35 +01004877 if (!mlxsw_sp_vport)
4878 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004879
4880 switch (event) {
4881 case NETDEV_PRECHANGEUPPER:
4882 upper_dev = info->upper_dev;
Ido Schimmelb1e45522017-04-30 19:47:14 +03004883 if (!netif_is_bridge_master(upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004884 return -EINVAL;
Ido Schimmelddbe9932016-06-20 23:04:02 +02004885 if (!info->linking)
4886 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004887 /* We can't have multiple VLAN interfaces configured on
4888 * the same port and being members in the same bridge.
4889 */
Ido Schimmel7179eb52017-03-16 09:08:18 +01004890 if (netif_is_bridge_master(upper_dev) &&
4891 !mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004892 upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004893 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004894 break;
4895 case NETDEV_CHANGEUPPER:
4896 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004897 if (netif_is_bridge_master(upper_dev)) {
4898 if (info->linking)
4899 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
4900 upper_dev);
4901 else
4902 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004903 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004904 err = -EINVAL;
4905 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004906 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004907 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004908 }
4909
Ido Schimmel80bedf12016-06-20 23:03:59 +02004910 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004911}
4912
Ido Schimmel272c4472015-12-15 16:03:47 +01004913static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
4914 unsigned long event, void *ptr,
4915 u16 vid)
4916{
4917 struct net_device *dev;
4918 struct list_head *iter;
4919 int ret;
4920
4921 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4922 if (mlxsw_sp_port_dev_check(dev)) {
4923 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
4924 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004925 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004926 return ret;
4927 }
4928 }
4929
Ido Schimmel80bedf12016-06-20 23:03:59 +02004930 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004931}
4932
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004933static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4934 unsigned long event, void *ptr)
4935{
4936 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4937 u16 vid = vlan_dev_vlan_id(vlan_dev);
4938
Ido Schimmel272c4472015-12-15 16:03:47 +01004939 if (mlxsw_sp_port_dev_check(real_dev))
4940 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
4941 vid);
4942 else if (netif_is_lag_master(real_dev))
4943 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
4944 vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004945
Ido Schimmel80bedf12016-06-20 23:03:59 +02004946 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004947}
4948
Ido Schimmelb1e45522017-04-30 19:47:14 +03004949static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4950{
4951 struct netdev_notifier_changeupper_info *info = ptr;
4952
4953 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4954 return false;
4955 return netif_is_l3_master(info->upper_dev);
4956}
4957
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004958static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4959 unsigned long event, void *ptr)
4960{
4961 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004962 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004963
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004964 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4965 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004966 else if (mlxsw_sp_is_vrf_event(event, ptr))
4967 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004968 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004969 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4970 else if (netif_is_lag_master(dev))
4971 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
Ido Schimmel701b1862016-07-04 08:23:16 +02004972 else if (netif_is_bridge_master(dev))
4973 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004974 else if (is_vlan_dev(dev))
4975 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004976
Ido Schimmel80bedf12016-06-20 23:03:59 +02004977 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004978}
4979
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004980static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4981 .notifier_call = mlxsw_sp_netdevice_event,
4982};
4983
Ido Schimmel99724c12016-07-04 08:23:14 +02004984static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4985 .notifier_call = mlxsw_sp_inetaddr_event,
4986 .priority = 10, /* Must be called before FIB notifier block */
4987};
4988
Jiri Pirkoe7322632016-09-01 10:37:43 +02004989static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4990 .notifier_call = mlxsw_sp_router_netevent_event,
4991};
4992
Jiri Pirko1d20d232016-10-27 15:12:59 +02004993static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4994 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4995 {0, },
4996};
4997
4998static struct pci_driver mlxsw_sp_pci_driver = {
4999 .name = mlxsw_sp_driver_name,
5000 .id_table = mlxsw_sp_pci_id_table,
5001};
5002
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005003static int __init mlxsw_sp_module_init(void)
5004{
5005 int err;
5006
5007 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02005008 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02005009 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
5010
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005011 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
5012 if (err)
5013 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02005014
5015 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
5016 if (err)
5017 goto err_pci_driver_register;
5018
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005019 return 0;
5020
Jiri Pirko1d20d232016-10-27 15:12:59 +02005021err_pci_driver_register:
5022 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005023err_core_driver_register:
Jiri Pirkoe7322632016-09-01 10:37:43 +02005024 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02005025 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005026 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
5027 return err;
5028}
5029
5030static void __exit mlxsw_sp_module_exit(void)
5031{
Jiri Pirko1d20d232016-10-27 15:12:59 +02005032 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005033 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirkoe7322632016-09-01 10:37:43 +02005034 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02005035 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005036 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
5037}
5038
5039module_init(mlxsw_sp_module_init);
5040module_exit(mlxsw_sp_module_exit);
5041
5042MODULE_LICENSE("Dual BSD/GPL");
5043MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5044MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02005045MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02005046MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);