blob: 0e51c3693243539de1b7bf973db78a036e0bbf99 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020056#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020057#include <net/pkt_cls.h>
58#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020059#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010060#include <net/tc_act/tc_sample.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020061
62#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020063#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020064#include "core.h"
65#include "reg.h"
66#include "port.h"
67#include "trap.h"
68#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010069#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020070#include "spectrum_dpipe.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020071#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020072
Yotam Gigi6b742192017-05-23 21:56:29 +020073#define MLXSW_FWREV_MAJOR 13
74#define MLXSW_FWREV_MINOR 1420
75#define MLXSW_FWREV_SUBMINOR 122
76
77static const struct mlxsw_fw_rev mlxsw_sp_supported_fw_rev = {
78 .major = MLXSW_FWREV_MAJOR,
79 .minor = MLXSW_FWREV_MINOR,
80 .subminor = MLXSW_FWREV_SUBMINOR
81};
82
83#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020084 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020085 "." __stringify(MLXSW_FWREV_MINOR) \
86 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
87
Jiri Pirko56ade8f2015-10-16 14:01:37 +020088static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
89static const char mlxsw_sp_driver_version[] = "1.0";
90
91/* tx_hdr_version
92 * Tx header version.
93 * Must be set to 1.
94 */
95MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
96
97/* tx_hdr_ctl
98 * Packet control type.
99 * 0 - Ethernet control (e.g. EMADs, LACP)
100 * 1 - Ethernet data
101 */
102MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
103
104/* tx_hdr_proto
105 * Packet protocol type. Must be set to 1 (Ethernet).
106 */
107MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
108
109/* tx_hdr_rx_is_router
110 * Packet is sent from the router. Valid for data packets only.
111 */
112MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
113
114/* tx_hdr_fid_valid
115 * Indicates if the 'fid' field is valid and should be used for
116 * forwarding lookup. Valid for data packets only.
117 */
118MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
119
120/* tx_hdr_swid
121 * Switch partition ID. Must be set to 0.
122 */
123MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
124
125/* tx_hdr_control_tclass
126 * Indicates if the packet should use the control TClass and not one
127 * of the data TClasses.
128 */
129MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
130
131/* tx_hdr_etclass
132 * Egress TClass to be used on the egress device on the egress port.
133 */
134MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
135
136/* tx_hdr_port_mid
137 * Destination local port for unicast packets.
138 * Destination multicast ID for multicast packets.
139 *
140 * Control packets are directed to a specific egress port, while data
141 * packets are transmitted through the CPU port (0) into the switch partition,
142 * where forwarding rules are applied.
143 */
144MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
145
146/* tx_hdr_fid
147 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
148 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
149 * Valid for data packets only.
150 */
151MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
152
153/* tx_hdr_type
154 * 0 - Data packets
155 * 6 - Control packets
156 */
157MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
158
Yotam Gigie5e5c882017-05-23 21:56:27 +0200159struct mlxsw_sp_mlxfw_dev {
160 struct mlxfw_dev mlxfw_dev;
161 struct mlxsw_sp *mlxsw_sp;
162};
163
164static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
165 u16 component_index, u32 *p_max_size,
166 u8 *p_align_bits, u16 *p_max_write_size)
167{
168 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
169 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
170 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
171 char mcqi_pl[MLXSW_REG_MCQI_LEN];
172 int err;
173
174 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
175 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
176 if (err)
177 return err;
178 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
179 p_max_write_size);
180
181 *p_align_bits = max_t(u8, *p_align_bits, 2);
182 *p_max_write_size = min_t(u16, *p_max_write_size,
183 MLXSW_REG_MCDA_MAX_DATA_LEN);
184 return 0;
185}
186
187static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
188{
189 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
190 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
191 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
192 char mcc_pl[MLXSW_REG_MCC_LEN];
193 u8 control_state;
194 int err;
195
196 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
197 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
198 if (err)
199 return err;
200
201 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
202 if (control_state != MLXFW_FSM_STATE_IDLE)
203 return -EBUSY;
204
205 mlxsw_reg_mcc_pack(mcc_pl,
206 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
207 0, *fwhandle, 0);
208 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
209}
210
211static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
212 u32 fwhandle, u16 component_index,
213 u32 component_size)
214{
215 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
216 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
217 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
218 char mcc_pl[MLXSW_REG_MCC_LEN];
219
220 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
221 component_index, fwhandle, component_size);
222 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
223}
224
225static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
226 u32 fwhandle, u8 *data, u16 size,
227 u32 offset)
228{
229 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
230 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
231 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
232 char mcda_pl[MLXSW_REG_MCDA_LEN];
233
234 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
235 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
236}
237
238static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
239 u32 fwhandle, u16 component_index)
240{
241 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
242 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
243 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
244 char mcc_pl[MLXSW_REG_MCC_LEN];
245
246 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
247 component_index, fwhandle, 0);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
249}
250
251static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
252{
253 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
254 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
255 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
256 char mcc_pl[MLXSW_REG_MCC_LEN];
257
258 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
259 fwhandle, 0);
260 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
261}
262
263static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
264 enum mlxfw_fsm_state *fsm_state,
265 enum mlxfw_fsm_state_err *fsm_state_err)
266{
267 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
268 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
269 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
270 char mcc_pl[MLXSW_REG_MCC_LEN];
271 u8 control_state;
272 u8 error_code;
273 int err;
274
275 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
276 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
277 if (err)
278 return err;
279
280 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
281 *fsm_state = control_state;
282 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
283 MLXFW_FSM_STATE_ERR_MAX);
284 return 0;
285}
286
287static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
288{
289 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
290 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
291 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
292 char mcc_pl[MLXSW_REG_MCC_LEN];
293
294 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
295 fwhandle, 0);
296 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
297}
298
299static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
300{
301 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
302 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
303 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
304 char mcc_pl[MLXSW_REG_MCC_LEN];
305
306 mlxsw_reg_mcc_pack(mcc_pl,
307 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
308 fwhandle, 0);
309 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
310}
311
312static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
313 .component_query = mlxsw_sp_component_query,
314 .fsm_lock = mlxsw_sp_fsm_lock,
315 .fsm_component_update = mlxsw_sp_fsm_component_update,
316 .fsm_block_download = mlxsw_sp_fsm_block_download,
317 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
318 .fsm_activate = mlxsw_sp_fsm_activate,
319 .fsm_query_state = mlxsw_sp_fsm_query_state,
320 .fsm_cancel = mlxsw_sp_fsm_cancel,
321 .fsm_release = mlxsw_sp_fsm_release
322};
323
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300324static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
325 const struct firmware *firmware)
326{
327 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
328 .mlxfw_dev = {
329 .ops = &mlxsw_sp_mlxfw_dev_ops,
330 .psid = mlxsw_sp->bus_info->psid,
331 .psid_size = strlen(mlxsw_sp->bus_info->psid),
332 },
333 .mlxsw_sp = mlxsw_sp
334 };
335
336 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
337}
338
Yotam Gigi6b742192017-05-23 21:56:29 +0200339static bool mlxsw_sp_fw_rev_ge(const struct mlxsw_fw_rev *a,
340 const struct mlxsw_fw_rev *b)
341{
342 if (a->major != b->major)
343 return a->major > b->major;
344 if (a->minor != b->minor)
345 return a->minor > b->minor;
346 return a->subminor >= b->subminor;
347}
348
349static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
350{
351 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200352 const struct firmware *firmware;
353 int err;
354
355 if (mlxsw_sp_fw_rev_ge(rev, &mlxsw_sp_supported_fw_rev))
356 return 0;
357
358 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d out of data\n",
359 rev->major, rev->minor, rev->subminor);
360 dev_info(mlxsw_sp->bus_info->dev, "Upgrading firmware using file %s\n",
361 MLXSW_SP_FW_FILENAME);
362
363 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
364 mlxsw_sp->bus_info->dev);
365 if (err) {
366 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
367 MLXSW_SP_FW_FILENAME);
368 return err;
369 }
370
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300371 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200372 release_firmware(firmware);
373 return err;
374}
375
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100376int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
377 unsigned int counter_index, u64 *packets,
378 u64 *bytes)
379{
380 char mgpc_pl[MLXSW_REG_MGPC_LEN];
381 int err;
382
383 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
384 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
385 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
386 if (err)
387 return err;
388 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
389 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
390 return 0;
391}
392
393static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
394 unsigned int counter_index)
395{
396 char mgpc_pl[MLXSW_REG_MGPC_LEN];
397
398 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
399 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
400 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
401}
402
403int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
404 unsigned int *p_counter_index)
405{
406 int err;
407
408 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
409 p_counter_index);
410 if (err)
411 return err;
412 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
413 if (err)
414 goto err_counter_clear;
415 return 0;
416
417err_counter_clear:
418 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
419 *p_counter_index);
420 return err;
421}
422
423void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
424 unsigned int counter_index)
425{
426 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
427 counter_index);
428}
429
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200430static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
431 const struct mlxsw_tx_info *tx_info)
432{
433 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
434
435 memset(txhdr, 0, MLXSW_TXHDR_LEN);
436
437 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
438 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
439 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
440 mlxsw_tx_hdr_swid_set(txhdr, 0);
441 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
442 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
443 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
444}
445
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200446int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
447 u8 state)
448{
449 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
450 enum mlxsw_reg_spms_state spms_state;
451 char *spms_pl;
452 int err;
453
454 switch (state) {
455 case BR_STATE_FORWARDING:
456 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
457 break;
458 case BR_STATE_LEARNING:
459 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
460 break;
461 case BR_STATE_LISTENING: /* fall-through */
462 case BR_STATE_DISABLED: /* fall-through */
463 case BR_STATE_BLOCKING:
464 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
465 break;
466 default:
467 BUG();
468 }
469
470 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
471 if (!spms_pl)
472 return -ENOMEM;
473 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
474 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
475
476 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
477 kfree(spms_pl);
478 return err;
479}
480
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200481static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
482{
Elad Raz5b090742016-10-28 21:35:46 +0200483 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200484 int err;
485
486 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
487 if (err)
488 return err;
489 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
490 return 0;
491}
492
Yotam Gigi763b4b72016-07-21 12:03:17 +0200493static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
494{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200495 int i;
496
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200497 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200498 return -EIO;
499
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200500 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
501 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200502 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
503 sizeof(struct mlxsw_sp_span_entry),
504 GFP_KERNEL);
505 if (!mlxsw_sp->span.entries)
506 return -ENOMEM;
507
508 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
509 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
510
511 return 0;
512}
513
514static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
515{
516 int i;
517
518 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
519 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
520
521 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
522 }
523 kfree(mlxsw_sp->span.entries);
524}
525
526static struct mlxsw_sp_span_entry *
527mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
528{
529 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
530 struct mlxsw_sp_span_entry *span_entry;
531 char mpat_pl[MLXSW_REG_MPAT_LEN];
532 u8 local_port = port->local_port;
533 int index;
534 int i;
535 int err;
536
537 /* find a free entry to use */
538 index = -1;
539 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
540 if (!mlxsw_sp->span.entries[i].used) {
541 index = i;
542 span_entry = &mlxsw_sp->span.entries[i];
543 break;
544 }
545 }
546 if (index < 0)
547 return NULL;
548
549 /* create a new port analayzer entry for local_port */
550 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
551 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
552 if (err)
553 return NULL;
554
555 span_entry->used = true;
556 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100557 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200558 span_entry->local_port = local_port;
559 return span_entry;
560}
561
562static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
563 struct mlxsw_sp_span_entry *span_entry)
564{
565 u8 local_port = span_entry->local_port;
566 char mpat_pl[MLXSW_REG_MPAT_LEN];
567 int pa_id = span_entry->id;
568
569 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
570 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
571 span_entry->used = false;
572}
573
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200574static struct mlxsw_sp_span_entry *
575mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200576{
577 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
578 int i;
579
580 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
581 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
582
583 if (curr->used && curr->local_port == port->local_port)
584 return curr;
585 }
586 return NULL;
587}
588
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200589static struct mlxsw_sp_span_entry
590*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200591{
592 struct mlxsw_sp_span_entry *span_entry;
593
594 span_entry = mlxsw_sp_span_entry_find(port);
595 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100596 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200597 span_entry->ref_count++;
598 return span_entry;
599 }
600
601 return mlxsw_sp_span_entry_create(port);
602}
603
604static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
605 struct mlxsw_sp_span_entry *span_entry)
606{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100607 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200608 if (--span_entry->ref_count == 0)
609 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
610 return 0;
611}
612
613static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
614{
615 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
616 struct mlxsw_sp_span_inspected_port *p;
617 int i;
618
619 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
620 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
621
622 list_for_each_entry(p, &curr->bound_ports_list, list)
623 if (p->local_port == port->local_port &&
624 p->type == MLXSW_SP_SPAN_EGRESS)
625 return true;
626 }
627
628 return false;
629}
630
Ido Schimmel18281f22017-03-24 08:02:51 +0100631static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
632 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200633{
Ido Schimmel18281f22017-03-24 08:02:51 +0100634 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200635}
636
637static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
638{
639 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
640 char sbib_pl[MLXSW_REG_SBIB_LEN];
641 int err;
642
643 /* If port is egress mirrored, the shared buffer size should be
644 * updated according to the mtu value
645 */
646 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100647 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
648
649 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200650 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
651 if (err) {
652 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
653 return err;
654 }
655 }
656
657 return 0;
658}
659
660static struct mlxsw_sp_span_inspected_port *
661mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
662 struct mlxsw_sp_span_entry *span_entry)
663{
664 struct mlxsw_sp_span_inspected_port *p;
665
666 list_for_each_entry(p, &span_entry->bound_ports_list, list)
667 if (port->local_port == p->local_port)
668 return p;
669 return NULL;
670}
671
672static int
673mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
674 struct mlxsw_sp_span_entry *span_entry,
675 enum mlxsw_sp_span_type type)
676{
677 struct mlxsw_sp_span_inspected_port *inspected_port;
678 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
679 char mpar_pl[MLXSW_REG_MPAR_LEN];
680 char sbib_pl[MLXSW_REG_SBIB_LEN];
681 int pa_id = span_entry->id;
682 int err;
683
684 /* if it is an egress SPAN, bind a shared buffer to it */
685 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100686 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
687 port->dev->mtu);
688
689 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200690 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
691 if (err) {
692 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
693 return err;
694 }
695 }
696
697 /* bind the port to the SPAN entry */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200698 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
699 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200700 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
701 if (err)
702 goto err_mpar_reg_write;
703
704 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
705 if (!inspected_port) {
706 err = -ENOMEM;
707 goto err_inspected_port_alloc;
708 }
709 inspected_port->local_port = port->local_port;
710 inspected_port->type = type;
711 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
712
713 return 0;
714
715err_mpar_reg_write:
716err_inspected_port_alloc:
717 if (type == MLXSW_SP_SPAN_EGRESS) {
718 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
719 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
720 }
721 return err;
722}
723
724static void
725mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
726 struct mlxsw_sp_span_entry *span_entry,
727 enum mlxsw_sp_span_type type)
728{
729 struct mlxsw_sp_span_inspected_port *inspected_port;
730 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
731 char mpar_pl[MLXSW_REG_MPAR_LEN];
732 char sbib_pl[MLXSW_REG_SBIB_LEN];
733 int pa_id = span_entry->id;
734
735 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
736 if (!inspected_port)
737 return;
738
739 /* remove the inspected port */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200740 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
741 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200742 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
743
744 /* remove the SBIB buffer if it was egress SPAN */
745 if (type == MLXSW_SP_SPAN_EGRESS) {
746 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
747 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
748 }
749
750 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
751
752 list_del(&inspected_port->list);
753 kfree(inspected_port);
754}
755
756static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
757 struct mlxsw_sp_port *to,
758 enum mlxsw_sp_span_type type)
759{
760 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
761 struct mlxsw_sp_span_entry *span_entry;
762 int err;
763
764 span_entry = mlxsw_sp_span_entry_get(to);
765 if (!span_entry)
766 return -ENOENT;
767
768 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
769 span_entry->id);
770
771 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
772 if (err)
773 goto err_port_bind;
774
775 return 0;
776
777err_port_bind:
778 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
779 return err;
780}
781
782static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
783 struct mlxsw_sp_port *to,
784 enum mlxsw_sp_span_type type)
785{
786 struct mlxsw_sp_span_entry *span_entry;
787
788 span_entry = mlxsw_sp_span_entry_find(to);
789 if (!span_entry) {
790 netdev_err(from->dev, "no span entry found\n");
791 return;
792 }
793
794 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
795 span_entry->id);
796 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
797}
798
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100799static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
800 bool enable, u32 rate)
801{
802 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
803 char mpsc_pl[MLXSW_REG_MPSC_LEN];
804
805 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
806 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
807}
808
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200809static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
810 bool is_up)
811{
812 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
813 char paos_pl[MLXSW_REG_PAOS_LEN];
814
815 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
816 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
817 MLXSW_PORT_ADMIN_STATUS_DOWN);
818 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
819}
820
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200821static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
822 unsigned char *addr)
823{
824 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
825 char ppad_pl[MLXSW_REG_PPAD_LEN];
826
827 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
828 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
829 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
830}
831
832static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
833{
834 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
835 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
836
837 ether_addr_copy(addr, mlxsw_sp->base_mac);
838 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
839 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
840}
841
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200842static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
843{
844 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
845 char pmtu_pl[MLXSW_REG_PMTU_LEN];
846 int max_mtu;
847 int err;
848
849 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
850 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
851 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
852 if (err)
853 return err;
854 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
855
856 if (mtu > max_mtu)
857 return -EINVAL;
858
859 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
860 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
861}
862
863static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
864{
865 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200866 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200867
Ido Schimmel5b153852017-06-08 08:47:44 +0200868 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
869 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200870}
871
Ido Schimmela1107482017-05-26 08:37:39 +0200872int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200873{
874 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
875 char svpe_pl[MLXSW_REG_SVPE_LEN];
876
877 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
878 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
879}
880
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200881int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
882 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200883{
884 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
885 char *spvmlr_pl;
886 int err;
887
888 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
889 if (!spvmlr_pl)
890 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200891 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
892 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200893 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
894 kfree(spvmlr_pl);
895 return err;
896}
897
Ido Schimmelb02eae92017-05-16 19:38:34 +0200898static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
899 u16 vid)
900{
901 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
902 char spvid_pl[MLXSW_REG_SPVID_LEN];
903
904 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
905 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
906}
907
908static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
909 bool allow)
910{
911 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
912 char spaft_pl[MLXSW_REG_SPAFT_LEN];
913
914 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
915 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
916}
917
918int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
919{
920 int err;
921
922 if (!vid) {
923 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
924 if (err)
925 return err;
926 } else {
927 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
928 if (err)
929 return err;
930 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
931 if (err)
932 goto err_port_allow_untagged_set;
933 }
934
935 mlxsw_sp_port->pvid = vid;
936 return 0;
937
938err_port_allow_untagged_set:
939 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
940 return err;
941}
942
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200943static int
944mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
945{
946 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
947 char sspr_pl[MLXSW_REG_SSPR_LEN];
948
949 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
950 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
951}
952
Ido Schimmeld664b412016-06-09 09:51:40 +0200953static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
954 u8 local_port, u8 *p_module,
955 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200956{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200957 char pmlp_pl[MLXSW_REG_PMLP_LEN];
958 int err;
959
Ido Schimmel558c2d52016-02-26 17:32:29 +0100960 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200961 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
962 if (err)
963 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100964 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
965 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200966 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200967 return 0;
968}
969
Ido Schimmel2e915e02017-06-08 08:47:45 +0200970static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100971 u8 module, u8 width, u8 lane)
972{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200973 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100974 char pmlp_pl[MLXSW_REG_PMLP_LEN];
975 int i;
976
Ido Schimmel2e915e02017-06-08 08:47:45 +0200977 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100978 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
979 for (i = 0; i < width; i++) {
980 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
981 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
982 }
983
984 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
985}
986
Ido Schimmel2e915e02017-06-08 08:47:45 +0200987static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100988{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200989 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100990 char pmlp_pl[MLXSW_REG_PMLP_LEN];
991
Ido Schimmel2e915e02017-06-08 08:47:45 +0200992 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100993 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
994 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
995}
996
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200997static int mlxsw_sp_port_open(struct net_device *dev)
998{
999 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1000 int err;
1001
1002 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1003 if (err)
1004 return err;
1005 netif_start_queue(dev);
1006 return 0;
1007}
1008
1009static int mlxsw_sp_port_stop(struct net_device *dev)
1010{
1011 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1012
1013 netif_stop_queue(dev);
1014 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1015}
1016
1017static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1018 struct net_device *dev)
1019{
1020 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1021 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1022 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1023 const struct mlxsw_tx_info tx_info = {
1024 .local_port = mlxsw_sp_port->local_port,
1025 .is_emad = false,
1026 };
1027 u64 len;
1028 int err;
1029
Jiri Pirko307c2432016-04-08 19:11:22 +02001030 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001031 return NETDEV_TX_BUSY;
1032
1033 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1034 struct sk_buff *skb_orig = skb;
1035
1036 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1037 if (!skb) {
1038 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1039 dev_kfree_skb_any(skb_orig);
1040 return NETDEV_TX_OK;
1041 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +01001042 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001043 }
1044
1045 if (eth_skb_pad(skb)) {
1046 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1047 return NETDEV_TX_OK;
1048 }
1049
1050 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +02001051 /* TX header is consumed by HW on the way so we shouldn't count its
1052 * bytes as being sent.
1053 */
1054 len = skb->len - MLXSW_TXHDR_LEN;
1055
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001056 /* Due to a race we might fail here because of a full queue. In that
1057 * unlikely case we simply drop the packet.
1058 */
Jiri Pirko307c2432016-04-08 19:11:22 +02001059 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001060
1061 if (!err) {
1062 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1063 u64_stats_update_begin(&pcpu_stats->syncp);
1064 pcpu_stats->tx_packets++;
1065 pcpu_stats->tx_bytes += len;
1066 u64_stats_update_end(&pcpu_stats->syncp);
1067 } else {
1068 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1069 dev_kfree_skb_any(skb);
1070 }
1071 return NETDEV_TX_OK;
1072}
1073
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001074static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1075{
1076}
1077
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001078static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1079{
1080 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1081 struct sockaddr *addr = p;
1082 int err;
1083
1084 if (!is_valid_ether_addr(addr->sa_data))
1085 return -EADDRNOTAVAIL;
1086
1087 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1088 if (err)
1089 return err;
1090 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1091 return 0;
1092}
1093
Ido Schimmel18281f22017-03-24 08:02:51 +01001094static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1095 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001096{
Ido Schimmel18281f22017-03-24 08:02:51 +01001097 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001098}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001099
Ido Schimmelf417f042017-03-24 08:02:50 +01001100#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +01001101
1102static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1103 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +01001104{
Ido Schimmel18281f22017-03-24 08:02:51 +01001105 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1106 BITS_PER_BYTE));
1107 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1108 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001109}
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001110
Ido Schimmel18281f22017-03-24 08:02:51 +01001111/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +01001112 * Assumes 100m cable and maximum MTU.
1113 */
Ido Schimmel18281f22017-03-24 08:02:51 +01001114#define MLXSW_SP_PAUSE_DELAY 58752
1115
1116static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1117 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +01001118{
1119 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +01001120 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +01001121 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +01001122 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001123 else
Ido Schimmelf417f042017-03-24 08:02:50 +01001124 return 0;
1125}
1126
1127static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1128 bool lossy)
1129{
1130 if (lossy)
1131 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
1132 else
1133 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1134 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001135}
1136
1137int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001138 u8 *prio_tc, bool pause_en,
1139 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +02001140{
1141 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001142 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1143 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001144 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001145 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001146
1147 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1148 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1149 if (err)
1150 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001151
1152 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1153 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001154 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +01001155 bool lossy;
1156 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001157
1158 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1159 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001160 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001161 configure = true;
1162 break;
1163 }
1164 }
1165
1166 if (!configure)
1167 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +01001168
1169 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +01001170 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1171 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1172 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +01001173 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001174 }
1175
Ido Schimmelff6551e2016-04-06 17:10:03 +02001176 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1177}
1178
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001179static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001180 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001181{
1182 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1183 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001184 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001185 u8 *prio_tc;
1186
1187 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001188 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001189
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001190 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001191 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001192}
1193
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001194static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1195{
1196 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001197 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001198 int err;
1199
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001200 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001201 if (err)
1202 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001203 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1204 if (err)
1205 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001206 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1207 if (err)
1208 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001209 dev->mtu = mtu;
1210 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001211
1212err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001213 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1214err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001215 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +02001216 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001217}
1218
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001219static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001220mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1221 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001222{
1223 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1224 struct mlxsw_sp_port_pcpu_stats *p;
1225 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1226 u32 tx_dropped = 0;
1227 unsigned int start;
1228 int i;
1229
1230 for_each_possible_cpu(i) {
1231 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1232 do {
1233 start = u64_stats_fetch_begin_irq(&p->syncp);
1234 rx_packets = p->rx_packets;
1235 rx_bytes = p->rx_bytes;
1236 tx_packets = p->tx_packets;
1237 tx_bytes = p->tx_bytes;
1238 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1239
1240 stats->rx_packets += rx_packets;
1241 stats->rx_bytes += rx_bytes;
1242 stats->tx_packets += tx_packets;
1243 stats->tx_bytes += tx_bytes;
1244 /* tx_dropped is u32, updated without syncp protection. */
1245 tx_dropped += p->tx_dropped;
1246 }
1247 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001248 return 0;
1249}
1250
Or Gerlitz3df5b3c2016-11-22 23:09:54 +02001251static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001252{
1253 switch (attr_id) {
1254 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1255 return true;
1256 }
1257
1258 return false;
1259}
1260
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001261static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1262 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001263{
1264 switch (attr_id) {
1265 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1266 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1267 }
1268
1269 return -EINVAL;
1270}
1271
1272static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1273 int prio, char *ppcnt_pl)
1274{
1275 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1276 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1277
1278 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1279 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1280}
1281
1282static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1283 struct rtnl_link_stats64 *stats)
1284{
1285 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1286 int err;
1287
1288 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1289 0, ppcnt_pl);
1290 if (err)
1291 goto out;
1292
1293 stats->tx_packets =
1294 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1295 stats->rx_packets =
1296 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1297 stats->tx_bytes =
1298 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1299 stats->rx_bytes =
1300 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1301 stats->multicast =
1302 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1303
1304 stats->rx_crc_errors =
1305 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1306 stats->rx_frame_errors =
1307 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1308
1309 stats->rx_length_errors = (
1310 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1311 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1312 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1313
1314 stats->rx_errors = (stats->rx_crc_errors +
1315 stats->rx_frame_errors + stats->rx_length_errors);
1316
1317out:
1318 return err;
1319}
1320
1321static void update_stats_cache(struct work_struct *work)
1322{
1323 struct mlxsw_sp_port *mlxsw_sp_port =
1324 container_of(work, struct mlxsw_sp_port,
1325 hw_stats.update_dw.work);
1326
1327 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1328 goto out;
1329
1330 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1331 mlxsw_sp_port->hw_stats.cache);
1332
1333out:
1334 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
1335 MLXSW_HW_STATS_UPDATE_TIME);
1336}
1337
1338/* Return the stats from a cache that is updated periodically,
1339 * as this function might get called in an atomic context.
1340 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001341static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001342mlxsw_sp_port_get_stats64(struct net_device *dev,
1343 struct rtnl_link_stats64 *stats)
1344{
1345 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1346
1347 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001348}
1349
Jiri Pirko93cd0812017-04-18 16:55:35 +02001350static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1351 u16 vid_begin, u16 vid_end,
1352 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001353{
1354 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1355 char *spvm_pl;
1356 int err;
1357
1358 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1359 if (!spvm_pl)
1360 return -ENOMEM;
1361
1362 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1363 vid_end, is_member, untagged);
1364 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1365 kfree(spvm_pl);
1366 return err;
1367}
1368
Jiri Pirko93cd0812017-04-18 16:55:35 +02001369int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1370 u16 vid_end, bool is_member, bool untagged)
1371{
1372 u16 vid, vid_e;
1373 int err;
1374
1375 for (vid = vid_begin; vid <= vid_end;
1376 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1377 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1378 vid_end);
1379
1380 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1381 is_member, untagged);
1382 if (err)
1383 return err;
1384 }
1385
1386 return 0;
1387}
1388
Ido Schimmelc57529e2017-05-26 08:37:31 +02001389static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001390{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001391 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001392
Ido Schimmelc57529e2017-05-26 08:37:31 +02001393 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1394 &mlxsw_sp_port->vlans_list, list)
1395 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001396}
1397
Ido Schimmel31a08a52017-05-26 08:37:26 +02001398static struct mlxsw_sp_port_vlan *
1399mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1400{
1401 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001402 bool untagged = vid == 1;
1403 int err;
1404
1405 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1406 if (err)
1407 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001408
1409 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001410 if (!mlxsw_sp_port_vlan) {
1411 err = -ENOMEM;
1412 goto err_port_vlan_alloc;
1413 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001414
1415 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1416 mlxsw_sp_port_vlan->vid = vid;
1417 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1418
1419 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001420
1421err_port_vlan_alloc:
1422 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1423 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001424}
1425
1426static void
1427mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1428{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001429 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1430 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001431
Ido Schimmel31a08a52017-05-26 08:37:26 +02001432 list_del(&mlxsw_sp_port_vlan->list);
1433 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001434 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1435}
1436
1437struct mlxsw_sp_port_vlan *
1438mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1439{
1440 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1441
1442 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1443 if (mlxsw_sp_port_vlan)
1444 return mlxsw_sp_port_vlan;
1445
1446 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1447}
1448
1449void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1450{
Ido Schimmela1107482017-05-26 08:37:39 +02001451 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1452
Ido Schimmelc57529e2017-05-26 08:37:31 +02001453 if (mlxsw_sp_port_vlan->bridge_port)
1454 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001455 else if (fid)
1456 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001457
1458 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001459}
1460
Ido Schimmel05978482016-08-17 16:39:30 +02001461static int mlxsw_sp_port_add_vid(struct net_device *dev,
1462 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001463{
1464 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001465
1466 /* VLAN 0 is added to HW filter when device goes up, but it is
1467 * reserved in our case, so simply return.
1468 */
1469 if (!vid)
1470 return 0;
1471
Ido Schimmelc57529e2017-05-26 08:37:31 +02001472 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001473}
1474
Ido Schimmel32d863f2016-07-02 11:00:10 +02001475static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1476 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001477{
1478 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001479 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001480
1481 /* VLAN 0 is removed from HW filter when device goes down, but
1482 * it is reserved in our case, so simply return.
1483 */
1484 if (!vid)
1485 return 0;
1486
Ido Schimmel31a08a52017-05-26 08:37:26 +02001487 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001488 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001489 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001490 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001491
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001492 return 0;
1493}
1494
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001495static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1496 size_t len)
1497{
1498 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001499 u8 module = mlxsw_sp_port->mapping.module;
1500 u8 width = mlxsw_sp_port->mapping.width;
1501 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001502 int err;
1503
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001504 if (!mlxsw_sp_port->split)
1505 err = snprintf(name, len, "p%d", module + 1);
1506 else
1507 err = snprintf(name, len, "p%ds%d", module + 1,
1508 lane / width);
1509
1510 if (err >= len)
1511 return -EINVAL;
1512
1513 return 0;
1514}
1515
Yotam Gigi763b4b72016-07-21 12:03:17 +02001516static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001517mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1518 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001519 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1520
1521 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1522 if (mall_tc_entry->cookie == cookie)
1523 return mall_tc_entry;
1524
1525 return NULL;
1526}
1527
1528static int
1529mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001530 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001531 const struct tc_action *a,
1532 bool ingress)
1533{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001534 struct net *net = dev_net(mlxsw_sp_port->dev);
1535 enum mlxsw_sp_span_type span_type;
1536 struct mlxsw_sp_port *to_port;
1537 struct net_device *to_dev;
1538 int ifindex;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001539
1540 ifindex = tcf_mirred_ifindex(a);
1541 to_dev = __dev_get_by_index(net, ifindex);
1542 if (!to_dev) {
1543 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1544 return -EINVAL;
1545 }
1546
1547 if (!mlxsw_sp_port_dev_check(to_dev)) {
1548 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001549 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001550 }
1551 to_port = netdev_priv(to_dev);
1552
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001553 mirror->to_local_port = to_port->local_port;
1554 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001555 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001556 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1557}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001558
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001559static void
1560mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1561 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1562{
1563 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1564 enum mlxsw_sp_span_type span_type;
1565 struct mlxsw_sp_port *to_port;
1566
1567 to_port = mlxsw_sp->ports[mirror->to_local_port];
1568 span_type = mirror->ingress ?
1569 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1570 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001571}
1572
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001573static int
1574mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1575 struct tc_cls_matchall_offload *cls,
1576 const struct tc_action *a,
1577 bool ingress)
1578{
1579 int err;
1580
1581 if (!mlxsw_sp_port->sample)
1582 return -EOPNOTSUPP;
1583 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1584 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1585 return -EEXIST;
1586 }
1587 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1588 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1589 return -EOPNOTSUPP;
1590 }
1591
1592 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1593 tcf_sample_psample_group(a));
1594 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1595 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1596 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1597
1598 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1599 if (err)
1600 goto err_port_sample_set;
1601 return 0;
1602
1603err_port_sample_set:
1604 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1605 return err;
1606}
1607
1608static void
1609mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1610{
1611 if (!mlxsw_sp_port->sample)
1612 return;
1613
1614 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1615 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1616}
1617
Yotam Gigi763b4b72016-07-21 12:03:17 +02001618static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1619 __be16 protocol,
1620 struct tc_cls_matchall_offload *cls,
1621 bool ingress)
1622{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001623 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001624 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001625 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001626 int err;
1627
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001628 if (!tc_single_action(cls->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001629 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001630 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001631 }
1632
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001633 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1634 if (!mall_tc_entry)
1635 return -ENOMEM;
1636 mall_tc_entry->cookie = cls->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001637
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001638 tcf_exts_to_list(cls->exts, &actions);
1639 a = list_first_entry(&actions, struct tc_action, list);
1640
1641 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1642 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1643
1644 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1645 mirror = &mall_tc_entry->mirror;
1646 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1647 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001648 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1649 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1650 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, cls,
1651 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001652 } else {
1653 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001654 }
1655
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001656 if (err)
1657 goto err_add_action;
1658
1659 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001660 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001661
1662err_add_action:
1663 kfree(mall_tc_entry);
1664 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001665}
1666
1667static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1668 struct tc_cls_matchall_offload *cls)
1669{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001670 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001671
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001672 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1673 cls->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001674 if (!mall_tc_entry) {
1675 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1676 return;
1677 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001678 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001679
1680 switch (mall_tc_entry->type) {
1681 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001682 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1683 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001684 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001685 case MLXSW_SP_PORT_MALL_SAMPLE:
1686 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1687 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001688 default:
1689 WARN_ON(1);
1690 }
1691
Yotam Gigi763b4b72016-07-21 12:03:17 +02001692 kfree(mall_tc_entry);
1693}
1694
1695static int mlxsw_sp_setup_tc(struct net_device *dev, u32 handle,
Jiri Pirkoa5fcf8a2017-06-06 17:00:16 +02001696 u32 chain_index, __be16 proto,
1697 struct tc_to_netdev *tc)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001698{
1699 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1700 bool ingress = TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS);
1701
Jiri Pirkoa5fcf8a2017-06-06 17:00:16 +02001702 if (chain_index)
1703 return -EOPNOTSUPP;
1704
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001705 switch (tc->type) {
1706 case TC_SETUP_MATCHALL:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001707 switch (tc->cls_mall->command) {
1708 case TC_CLSMATCHALL_REPLACE:
1709 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port,
1710 proto,
1711 tc->cls_mall,
1712 ingress);
1713 case TC_CLSMATCHALL_DESTROY:
1714 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port,
1715 tc->cls_mall);
1716 return 0;
1717 default:
Or Gerlitzabbdf4b2017-03-17 09:38:01 +01001718 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001719 }
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001720 case TC_SETUP_CLSFLOWER:
1721 switch (tc->cls_flower->command) {
1722 case TC_CLSFLOWER_REPLACE:
1723 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress,
1724 proto, tc->cls_flower);
1725 case TC_CLSFLOWER_DESTROY:
1726 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress,
1727 tc->cls_flower);
1728 return 0;
Arkadi Sharshevsky7c1b8eb2017-03-11 09:42:59 +01001729 case TC_CLSFLOWER_STATS:
1730 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress,
1731 tc->cls_flower);
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001732 default:
1733 return -EOPNOTSUPP;
1734 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001735 }
1736
Yotam Gigie915ac62017-01-09 11:25:48 +01001737 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001738}
1739
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001740static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1741 .ndo_open = mlxsw_sp_port_open,
1742 .ndo_stop = mlxsw_sp_port_stop,
1743 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001744 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001745 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001746 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1747 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1748 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001749 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1750 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001751 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1752 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001753 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001754};
1755
1756static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1757 struct ethtool_drvinfo *drvinfo)
1758{
1759 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1760 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1761
1762 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1763 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1764 sizeof(drvinfo->version));
1765 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1766 "%d.%d.%d",
1767 mlxsw_sp->bus_info->fw_rev.major,
1768 mlxsw_sp->bus_info->fw_rev.minor,
1769 mlxsw_sp->bus_info->fw_rev.subminor);
1770 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1771 sizeof(drvinfo->bus_info));
1772}
1773
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001774static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1775 struct ethtool_pauseparam *pause)
1776{
1777 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1778
1779 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1780 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1781}
1782
1783static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1784 struct ethtool_pauseparam *pause)
1785{
1786 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1787
1788 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1789 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1790 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1791
1792 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1793 pfcc_pl);
1794}
1795
1796static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1797 struct ethtool_pauseparam *pause)
1798{
1799 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1800 bool pause_en = pause->tx_pause || pause->rx_pause;
1801 int err;
1802
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001803 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1804 netdev_err(dev, "PFC already enabled on port\n");
1805 return -EINVAL;
1806 }
1807
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001808 if (pause->autoneg) {
1809 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1810 return -EINVAL;
1811 }
1812
1813 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1814 if (err) {
1815 netdev_err(dev, "Failed to configure port's headroom\n");
1816 return err;
1817 }
1818
1819 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1820 if (err) {
1821 netdev_err(dev, "Failed to set PAUSE parameters\n");
1822 goto err_port_pause_configure;
1823 }
1824
1825 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1826 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1827
1828 return 0;
1829
1830err_port_pause_configure:
1831 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1832 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1833 return err;
1834}
1835
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001836struct mlxsw_sp_port_hw_stats {
1837 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001838 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001839 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001840};
1841
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001842static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001843 {
1844 .str = "a_frames_transmitted_ok",
1845 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1846 },
1847 {
1848 .str = "a_frames_received_ok",
1849 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1850 },
1851 {
1852 .str = "a_frame_check_sequence_errors",
1853 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1854 },
1855 {
1856 .str = "a_alignment_errors",
1857 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1858 },
1859 {
1860 .str = "a_octets_transmitted_ok",
1861 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1862 },
1863 {
1864 .str = "a_octets_received_ok",
1865 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1866 },
1867 {
1868 .str = "a_multicast_frames_xmitted_ok",
1869 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1870 },
1871 {
1872 .str = "a_broadcast_frames_xmitted_ok",
1873 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1874 },
1875 {
1876 .str = "a_multicast_frames_received_ok",
1877 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1878 },
1879 {
1880 .str = "a_broadcast_frames_received_ok",
1881 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1882 },
1883 {
1884 .str = "a_in_range_length_errors",
1885 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1886 },
1887 {
1888 .str = "a_out_of_range_length_field",
1889 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1890 },
1891 {
1892 .str = "a_frame_too_long_errors",
1893 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1894 },
1895 {
1896 .str = "a_symbol_error_during_carrier",
1897 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1898 },
1899 {
1900 .str = "a_mac_control_frames_transmitted",
1901 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1902 },
1903 {
1904 .str = "a_mac_control_frames_received",
1905 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1906 },
1907 {
1908 .str = "a_unsupported_opcodes_received",
1909 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1910 },
1911 {
1912 .str = "a_pause_mac_ctrl_frames_received",
1913 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1914 },
1915 {
1916 .str = "a_pause_mac_ctrl_frames_xmitted",
1917 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1918 },
1919};
1920
1921#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1922
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001923static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1924 {
1925 .str = "rx_octets_prio",
1926 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1927 },
1928 {
1929 .str = "rx_frames_prio",
1930 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1931 },
1932 {
1933 .str = "tx_octets_prio",
1934 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1935 },
1936 {
1937 .str = "tx_frames_prio",
1938 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1939 },
1940 {
1941 .str = "rx_pause_prio",
1942 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1943 },
1944 {
1945 .str = "rx_pause_duration_prio",
1946 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1947 },
1948 {
1949 .str = "tx_pause_prio",
1950 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1951 },
1952 {
1953 .str = "tx_pause_duration_prio",
1954 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1955 },
1956};
1957
1958#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1959
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001960static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1961 {
1962 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01001963 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1964 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001965 },
1966 {
1967 .str = "tc_no_buffer_discard_uc_tc",
1968 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1969 },
1970};
1971
1972#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1973
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001974#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001975 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
1976 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001977 IEEE_8021QAZ_MAX_TCS)
1978
1979static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
1980{
1981 int i;
1982
1983 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
1984 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1985 mlxsw_sp_port_hw_prio_stats[i].str, prio);
1986 *p += ETH_GSTRING_LEN;
1987 }
1988}
1989
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001990static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
1991{
1992 int i;
1993
1994 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
1995 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
1996 mlxsw_sp_port_hw_tc_stats[i].str, tc);
1997 *p += ETH_GSTRING_LEN;
1998 }
1999}
2000
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002001static void mlxsw_sp_port_get_strings(struct net_device *dev,
2002 u32 stringset, u8 *data)
2003{
2004 u8 *p = data;
2005 int i;
2006
2007 switch (stringset) {
2008 case ETH_SS_STATS:
2009 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2010 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2011 ETH_GSTRING_LEN);
2012 p += ETH_GSTRING_LEN;
2013 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002014
2015 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2016 mlxsw_sp_port_get_prio_strings(&p, i);
2017
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002018 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2019 mlxsw_sp_port_get_tc_strings(&p, i);
2020
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002021 break;
2022 }
2023}
2024
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002025static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2026 enum ethtool_phys_id_state state)
2027{
2028 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2029 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2030 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2031 bool active;
2032
2033 switch (state) {
2034 case ETHTOOL_ID_ACTIVE:
2035 active = true;
2036 break;
2037 case ETHTOOL_ID_INACTIVE:
2038 active = false;
2039 break;
2040 default:
2041 return -EOPNOTSUPP;
2042 }
2043
2044 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2045 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2046}
2047
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002048static int
2049mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2050 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2051{
2052 switch (grp) {
2053 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2054 *p_hw_stats = mlxsw_sp_port_hw_stats;
2055 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2056 break;
2057 case MLXSW_REG_PPCNT_PRIO_CNT:
2058 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2059 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2060 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002061 case MLXSW_REG_PPCNT_TC_CNT:
2062 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2063 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2064 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002065 default:
2066 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002067 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002068 }
2069 return 0;
2070}
2071
2072static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2073 enum mlxsw_reg_ppcnt_grp grp, int prio,
2074 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002075{
Ido Schimmel18281f22017-03-24 08:02:51 +01002076 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2077 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002078 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002079 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002080 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002081 int err;
2082
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002083 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2084 if (err)
2085 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002086 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002087 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002088 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002089 if (!hw_stats[i].cells_bytes)
2090 continue;
2091 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2092 data[data_index + i]);
2093 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002094}
2095
2096static void mlxsw_sp_port_get_stats(struct net_device *dev,
2097 struct ethtool_stats *stats, u64 *data)
2098{
2099 int i, data_index = 0;
2100
2101 /* IEEE 802.3 Counters */
2102 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2103 data, data_index);
2104 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2105
2106 /* Per-Priority Counters */
2107 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2108 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2109 data, data_index);
2110 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2111 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002112
2113 /* Per-TC Counters */
2114 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2115 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2116 data, data_index);
2117 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2118 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002119}
2120
2121static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2122{
2123 switch (sset) {
2124 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002125 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002126 default:
2127 return -EOPNOTSUPP;
2128 }
2129}
2130
2131struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002132 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002133 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002134 u32 speed;
2135};
2136
2137static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2138 {
2139 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002140 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2141 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002142 },
2143 {
2144 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2145 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002146 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2147 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002148 },
2149 {
2150 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002151 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2152 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002153 },
2154 {
2155 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2156 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002157 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2158 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002159 },
2160 {
2161 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2162 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2163 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2164 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002165 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2166 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002167 },
2168 {
2169 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002170 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2171 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002172 },
2173 {
2174 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002175 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2176 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002177 },
2178 {
2179 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002180 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2181 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002182 },
2183 {
2184 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002185 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2186 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002187 },
2188 {
2189 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002190 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2191 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002192 },
2193 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002194 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2195 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2196 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002197 },
2198 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002199 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2200 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2201 .speed = SPEED_25000,
2202 },
2203 {
2204 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2205 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2206 .speed = SPEED_25000,
2207 },
2208 {
2209 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2210 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2211 .speed = SPEED_25000,
2212 },
2213 {
2214 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2215 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2216 .speed = SPEED_50000,
2217 },
2218 {
2219 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2220 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2221 .speed = SPEED_50000,
2222 },
2223 {
2224 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2225 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2226 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002227 },
2228 {
2229 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002230 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2231 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002232 },
2233 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002234 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2235 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2236 .speed = SPEED_56000,
2237 },
2238 {
2239 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2240 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2241 .speed = SPEED_56000,
2242 },
2243 {
2244 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2245 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2246 .speed = SPEED_56000,
2247 },
2248 {
2249 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2250 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2251 .speed = SPEED_100000,
2252 },
2253 {
2254 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2255 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2256 .speed = SPEED_100000,
2257 },
2258 {
2259 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2260 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2261 .speed = SPEED_100000,
2262 },
2263 {
2264 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2265 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2266 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002267 },
2268};
2269
2270#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2271
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002272static void
2273mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2274 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002275{
2276 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2277 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2278 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2279 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2280 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2281 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002282 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002283
2284 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2285 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2286 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2287 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2288 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002289 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002290}
2291
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002292static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002293{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002294 int i;
2295
2296 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2297 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002298 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2299 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002300 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002301}
2302
2303static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002304 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002305{
2306 u32 speed = SPEED_UNKNOWN;
2307 u8 duplex = DUPLEX_UNKNOWN;
2308 int i;
2309
2310 if (!carrier_ok)
2311 goto out;
2312
2313 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2314 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2315 speed = mlxsw_sp_port_link_mode[i].speed;
2316 duplex = DUPLEX_FULL;
2317 break;
2318 }
2319 }
2320out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002321 cmd->base.speed = speed;
2322 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002323}
2324
2325static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2326{
2327 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2328 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2329 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2330 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2331 return PORT_FIBRE;
2332
2333 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2334 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2335 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2336 return PORT_DA;
2337
2338 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2339 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2340 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2341 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2342 return PORT_NONE;
2343
2344 return PORT_OTHER;
2345}
2346
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002347static u32
2348mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002349{
2350 u32 ptys_proto = 0;
2351 int i;
2352
2353 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002354 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2355 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002356 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2357 }
2358 return ptys_proto;
2359}
2360
2361static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2362{
2363 u32 ptys_proto = 0;
2364 int i;
2365
2366 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2367 if (speed == mlxsw_sp_port_link_mode[i].speed)
2368 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2369 }
2370 return ptys_proto;
2371}
2372
Ido Schimmel18f1e702016-02-26 17:32:31 +01002373static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2374{
2375 u32 ptys_proto = 0;
2376 int i;
2377
2378 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2379 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2380 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2381 }
2382 return ptys_proto;
2383}
2384
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002385static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2386 struct ethtool_link_ksettings *cmd)
2387{
2388 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2389 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2390 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2391
2392 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2393 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2394}
2395
2396static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2397 struct ethtool_link_ksettings *cmd)
2398{
2399 if (!autoneg)
2400 return;
2401
2402 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2403 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2404}
2405
2406static void
2407mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2408 struct ethtool_link_ksettings *cmd)
2409{
2410 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2411 return;
2412
2413 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2414 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2415}
2416
2417static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2418 struct ethtool_link_ksettings *cmd)
2419{
2420 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2421 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2422 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2423 char ptys_pl[MLXSW_REG_PTYS_LEN];
2424 u8 autoneg_status;
2425 bool autoneg;
2426 int err;
2427
2428 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002429 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002430 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2431 if (err)
2432 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002433 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2434 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002435
2436 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2437
2438 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2439
2440 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2441 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2442 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2443
2444 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2445 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2446 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2447 cmd);
2448
2449 return 0;
2450}
2451
2452static int
2453mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2454 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002455{
2456 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2457 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2458 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002459 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002460 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002461 int err;
2462
Elad Raz401c8b42016-10-28 21:35:52 +02002463 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002464 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002465 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002466 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002467 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002468
2469 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2470 eth_proto_new = autoneg ?
2471 mlxsw_sp_to_ptys_advert_link(cmd) :
2472 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002473
2474 eth_proto_new = eth_proto_new & eth_proto_cap;
2475 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002476 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002477 return -EINVAL;
2478 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002479
Elad Raz401c8b42016-10-28 21:35:52 +02002480 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2481 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002482 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002483 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002484 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002485
Ido Schimmel6277d462016-07-15 11:14:58 +02002486 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002487 return 0;
2488
Ido Schimmel0c83f882016-09-12 13:26:23 +02002489 mlxsw_sp_port->link.autoneg = autoneg;
2490
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002491 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2492 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002493
2494 return 0;
2495}
2496
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002497static int mlxsw_sp_flash_device(struct net_device *dev,
2498 struct ethtool_flash *flash)
2499{
2500 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2501 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2502 const struct firmware *firmware;
2503 int err;
2504
2505 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2506 return -EOPNOTSUPP;
2507
2508 dev_hold(dev);
2509 rtnl_unlock();
2510
2511 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2512 if (err)
2513 goto out;
2514 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2515 release_firmware(firmware);
2516out:
2517 rtnl_lock();
2518 dev_put(dev);
2519 return err;
2520}
2521
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002522static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2523 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2524 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002525 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2526 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002527 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002528 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002529 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2530 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002531 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2532 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002533 .flash_device = mlxsw_sp_flash_device,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002534};
2535
Ido Schimmel18f1e702016-02-26 17:32:31 +01002536static int
2537mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2538{
2539 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2540 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2541 char ptys_pl[MLXSW_REG_PTYS_LEN];
2542 u32 eth_proto_admin;
2543
2544 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002545 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2546 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002547 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2548}
2549
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002550int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2551 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2552 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002553{
2554 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2555 char qeec_pl[MLXSW_REG_QEEC_LEN];
2556
2557 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2558 next_index);
2559 mlxsw_reg_qeec_de_set(qeec_pl, true);
2560 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2561 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2562 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2563}
2564
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002565int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2566 enum mlxsw_reg_qeec_hr hr, u8 index,
2567 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002568{
2569 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2570 char qeec_pl[MLXSW_REG_QEEC_LEN];
2571
2572 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2573 next_index);
2574 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2575 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2576 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2577}
2578
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002579int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2580 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002581{
2582 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2583 char qtct_pl[MLXSW_REG_QTCT_LEN];
2584
2585 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2586 tclass);
2587 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2588}
2589
2590static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2591{
2592 int err, i;
2593
2594 /* Setup the elements hierarcy, so that each TC is linked to
2595 * one subgroup, which are all member in the same group.
2596 */
2597 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2598 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2599 0);
2600 if (err)
2601 return err;
2602 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2603 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2604 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2605 0, false, 0);
2606 if (err)
2607 return err;
2608 }
2609 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2610 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2611 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2612 false, 0);
2613 if (err)
2614 return err;
2615 }
2616
2617 /* Make sure the max shaper is disabled in all hierarcies that
2618 * support it.
2619 */
2620 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2621 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2622 MLXSW_REG_QEEC_MAS_DIS);
2623 if (err)
2624 return err;
2625 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2626 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2627 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2628 i, 0,
2629 MLXSW_REG_QEEC_MAS_DIS);
2630 if (err)
2631 return err;
2632 }
2633 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2634 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2635 MLXSW_REG_QEEC_HIERARCY_TC,
2636 i, i,
2637 MLXSW_REG_QEEC_MAS_DIS);
2638 if (err)
2639 return err;
2640 }
2641
2642 /* Map all priorities to traffic class 0. */
2643 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2644 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2645 if (err)
2646 return err;
2647 }
2648
2649 return 0;
2650}
2651
Ido Schimmel5b153852017-06-08 08:47:44 +02002652static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2653 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002654{
Ido Schimmelc57529e2017-05-26 08:37:31 +02002655 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002656 struct mlxsw_sp_port *mlxsw_sp_port;
2657 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002658 int err;
2659
Ido Schimmel5b153852017-06-08 08:47:44 +02002660 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2661 if (err) {
2662 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2663 local_port);
2664 return err;
2665 }
2666
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002667 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02002668 if (!dev) {
2669 err = -ENOMEM;
2670 goto err_alloc_etherdev;
2671 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002672 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002673 mlxsw_sp_port = netdev_priv(dev);
2674 mlxsw_sp_port->dev = dev;
2675 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2676 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02002677 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002678 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002679 mlxsw_sp_port->mapping.module = module;
2680 mlxsw_sp_port->mapping.width = width;
2681 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002682 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02002683 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002684 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002685
2686 mlxsw_sp_port->pcpu_stats =
2687 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2688 if (!mlxsw_sp_port->pcpu_stats) {
2689 err = -ENOMEM;
2690 goto err_alloc_stats;
2691 }
2692
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002693 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2694 GFP_KERNEL);
2695 if (!mlxsw_sp_port->sample) {
2696 err = -ENOMEM;
2697 goto err_alloc_sample;
2698 }
2699
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002700 mlxsw_sp_port->hw_stats.cache =
2701 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2702
2703 if (!mlxsw_sp_port->hw_stats.cache) {
2704 err = -ENOMEM;
2705 goto err_alloc_hw_stats;
2706 }
2707 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2708 &update_stats_cache);
2709
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002710 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2711 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2712
Ido Schimmel2e915e02017-06-08 08:47:45 +02002713 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02002714 if (err) {
2715 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2716 mlxsw_sp_port->local_port);
2717 goto err_port_module_map;
2718 }
2719
Ido Schimmel3247ff22016-09-08 08:16:02 +02002720 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2721 if (err) {
2722 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2723 mlxsw_sp_port->local_port);
2724 goto err_port_swid_set;
2725 }
2726
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002727 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2728 if (err) {
2729 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2730 mlxsw_sp_port->local_port);
2731 goto err_dev_addr_init;
2732 }
2733
2734 netif_carrier_off(dev);
2735
2736 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002737 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2738 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002739
Jarod Wilsond894be52016-10-20 13:55:16 -04002740 dev->min_mtu = 0;
2741 dev->max_mtu = ETH_MAX_MTU;
2742
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002743 /* Each packet needs to have a Tx header (metadata) on top all other
2744 * headers.
2745 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002746 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002747
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002748 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2749 if (err) {
2750 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2751 mlxsw_sp_port->local_port);
2752 goto err_port_system_port_mapping_set;
2753 }
2754
Ido Schimmel18f1e702016-02-26 17:32:31 +01002755 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2756 if (err) {
2757 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2758 mlxsw_sp_port->local_port);
2759 goto err_port_speed_by_width_set;
2760 }
2761
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002762 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2763 if (err) {
2764 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2765 mlxsw_sp_port->local_port);
2766 goto err_port_mtu_set;
2767 }
2768
2769 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2770 if (err)
2771 goto err_port_admin_status_set;
2772
2773 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2774 if (err) {
2775 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2776 mlxsw_sp_port->local_port);
2777 goto err_port_buffers_init;
2778 }
2779
Ido Schimmel90183b92016-04-06 17:10:08 +02002780 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2781 if (err) {
2782 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2783 mlxsw_sp_port->local_port);
2784 goto err_port_ets_init;
2785 }
2786
Ido Schimmelf00817d2016-04-06 17:10:09 +02002787 /* ETS and buffers must be initialized before DCB. */
2788 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2789 if (err) {
2790 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2791 mlxsw_sp_port->local_port);
2792 goto err_port_dcb_init;
2793 }
2794
Ido Schimmela1107482017-05-26 08:37:39 +02002795 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02002796 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02002797 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02002798 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002799 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02002800 }
2801
Ido Schimmelc57529e2017-05-26 08:37:31 +02002802 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
2803 if (IS_ERR(mlxsw_sp_port_vlan)) {
2804 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02002805 mlxsw_sp_port->local_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002806 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02002807 }
2808
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002809 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002810 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002811 err = register_netdev(dev);
2812 if (err) {
2813 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2814 mlxsw_sp_port->local_port);
2815 goto err_register_netdev;
2816 }
2817
Elad Razd808c7e2016-10-28 21:35:57 +02002818 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2819 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2820 module);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002821 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002822 return 0;
2823
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002824err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002825 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002826 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002827 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
2828err_port_vlan_get:
Ido Schimmela1107482017-05-26 08:37:39 +02002829 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
2830err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002831 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002832err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002833err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002834err_port_buffers_init:
2835err_port_admin_status_set:
2836err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002837err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002838err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002839err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002840 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2841err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02002842 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02002843err_port_module_map:
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002844 kfree(mlxsw_sp_port->hw_stats.cache);
2845err_alloc_hw_stats:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002846 kfree(mlxsw_sp_port->sample);
2847err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002848 free_percpu(mlxsw_sp_port->pcpu_stats);
2849err_alloc_stats:
2850 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02002851err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02002852 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2853 return err;
2854}
2855
Ido Schimmel5b153852017-06-08 08:47:44 +02002856static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002857{
2858 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2859
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002860 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002861 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002862 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002863 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002864 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002865 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002866 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002867 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002868 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02002869 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002870 kfree(mlxsw_sp_port->hw_stats.cache);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002871 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002872 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02002873 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002874 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02002875 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2876}
2877
Jiri Pirkof83e2102016-10-28 21:35:49 +02002878static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2879{
2880 return mlxsw_sp->ports[local_port] != NULL;
2881}
2882
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002883static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2884{
2885 int i;
2886
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002887 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002888 if (mlxsw_sp_port_created(mlxsw_sp, i))
2889 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002890 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002891 kfree(mlxsw_sp->ports);
2892}
2893
2894static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
2895{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002896 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02002897 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002898 size_t alloc_size;
2899 int i;
2900 int err;
2901
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002902 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002903 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
2904 if (!mlxsw_sp->ports)
2905 return -ENOMEM;
2906
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002907 mlxsw_sp->port_to_module = kcalloc(max_ports, sizeof(u8), GFP_KERNEL);
2908 if (!mlxsw_sp->port_to_module) {
2909 err = -ENOMEM;
2910 goto err_port_to_module_alloc;
2911 }
2912
2913 for (i = 1; i < max_ports; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01002914 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02002915 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01002916 if (err)
2917 goto err_port_module_info_get;
2918 if (!width)
2919 continue;
2920 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02002921 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
2922 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002923 if (err)
2924 goto err_port_create;
2925 }
2926 return 0;
2927
2928err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01002929err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002930 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002931 if (mlxsw_sp_port_created(mlxsw_sp, i))
2932 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002933 kfree(mlxsw_sp->port_to_module);
2934err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002935 kfree(mlxsw_sp->ports);
2936 return err;
2937}
2938
Ido Schimmel18f1e702016-02-26 17:32:31 +01002939static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
2940{
2941 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
2942
2943 return local_port - offset;
2944}
2945
Ido Schimmelbe945352016-06-09 09:51:39 +02002946static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
2947 u8 module, unsigned int count)
2948{
2949 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
2950 int err, i;
2951
2952 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02002953 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02002954 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02002955 if (err)
2956 goto err_port_create;
2957 }
2958
2959 return 0;
2960
2961err_port_create:
2962 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002963 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
2964 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02002965 return err;
2966}
2967
2968static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
2969 u8 base_port, unsigned int count)
2970{
2971 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
2972 int i;
2973
2974 /* Split by four means we need to re-create two ports, otherwise
2975 * only one.
2976 */
2977 count = count / 2;
2978
2979 for (i = 0; i < count; i++) {
2980 local_port = base_port + i * 2;
2981 module = mlxsw_sp->port_to_module[local_port];
2982
Ido Schimmelbe945352016-06-09 09:51:39 +02002983 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02002984 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02002985 }
2986}
2987
Jiri Pirkob2f10572016-04-08 19:11:23 +02002988static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
2989 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01002990{
Jiri Pirkob2f10572016-04-08 19:11:23 +02002991 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002992 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002993 u8 module, cur_width, base_port;
2994 int i;
2995 int err;
2996
2997 mlxsw_sp_port = mlxsw_sp->ports[local_port];
2998 if (!mlxsw_sp_port) {
2999 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3000 local_port);
3001 return -EINVAL;
3002 }
3003
Ido Schimmeld664b412016-06-09 09:51:40 +02003004 module = mlxsw_sp_port->mapping.module;
3005 cur_width = mlxsw_sp_port->mapping.width;
3006
Ido Schimmel18f1e702016-02-26 17:32:31 +01003007 if (count != 2 && count != 4) {
3008 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3009 return -EINVAL;
3010 }
3011
Ido Schimmel18f1e702016-02-26 17:32:31 +01003012 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3013 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3014 return -EINVAL;
3015 }
3016
3017 /* Make sure we have enough slave (even) ports for the split. */
3018 if (count == 2) {
3019 base_port = local_port;
3020 if (mlxsw_sp->ports[base_port + 1]) {
3021 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3022 return -EINVAL;
3023 }
3024 } else {
3025 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3026 if (mlxsw_sp->ports[base_port + 1] ||
3027 mlxsw_sp->ports[base_port + 3]) {
3028 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3029 return -EINVAL;
3030 }
3031 }
3032
3033 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003034 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3035 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003036
Ido Schimmelbe945352016-06-09 09:51:39 +02003037 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3038 if (err) {
3039 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3040 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003041 }
3042
3043 return 0;
3044
Ido Schimmelbe945352016-06-09 09:51:39 +02003045err_port_split_create:
3046 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003047 return err;
3048}
3049
Jiri Pirkob2f10572016-04-08 19:11:23 +02003050static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003051{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003052 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003053 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003054 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003055 unsigned int count;
3056 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003057
3058 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3059 if (!mlxsw_sp_port) {
3060 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3061 local_port);
3062 return -EINVAL;
3063 }
3064
3065 if (!mlxsw_sp_port->split) {
3066 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3067 return -EINVAL;
3068 }
3069
Ido Schimmeld664b412016-06-09 09:51:40 +02003070 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003071 count = cur_width == 1 ? 4 : 2;
3072
3073 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3074
3075 /* Determine which ports to remove. */
3076 if (count == 2 && local_port >= base_port + 2)
3077 base_port = base_port + 2;
3078
3079 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003080 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3081 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003082
Ido Schimmelbe945352016-06-09 09:51:39 +02003083 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003084
3085 return 0;
3086}
3087
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003088static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3089 char *pude_pl, void *priv)
3090{
3091 struct mlxsw_sp *mlxsw_sp = priv;
3092 struct mlxsw_sp_port *mlxsw_sp_port;
3093 enum mlxsw_reg_pude_oper_status status;
3094 u8 local_port;
3095
3096 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3097 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003098 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003099 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003100
3101 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3102 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3103 netdev_info(mlxsw_sp_port->dev, "link up\n");
3104 netif_carrier_on(mlxsw_sp_port->dev);
3105 } else {
3106 netdev_info(mlxsw_sp_port->dev, "link down\n");
3107 netif_carrier_off(mlxsw_sp_port->dev);
3108 }
3109}
3110
Nogah Frankel14eeda92016-11-25 10:33:32 +01003111static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3112 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003113{
3114 struct mlxsw_sp *mlxsw_sp = priv;
3115 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3116 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3117
3118 if (unlikely(!mlxsw_sp_port)) {
3119 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3120 local_port);
3121 return;
3122 }
3123
3124 skb->dev = mlxsw_sp_port->dev;
3125
3126 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3127 u64_stats_update_begin(&pcpu_stats->syncp);
3128 pcpu_stats->rx_packets++;
3129 pcpu_stats->rx_bytes += skb->len;
3130 u64_stats_update_end(&pcpu_stats->syncp);
3131
3132 skb->protocol = eth_type_trans(skb, skb->dev);
3133 netif_receive_skb(skb);
3134}
3135
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003136static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3137 void *priv)
3138{
3139 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003140 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003141}
3142
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003143static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3144 void *priv)
3145{
3146 struct mlxsw_sp *mlxsw_sp = priv;
3147 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3148 struct psample_group *psample_group;
3149 u32 size;
3150
3151 if (unlikely(!mlxsw_sp_port)) {
3152 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3153 local_port);
3154 goto out;
3155 }
3156 if (unlikely(!mlxsw_sp_port->sample)) {
3157 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3158 local_port);
3159 goto out;
3160 }
3161
3162 size = mlxsw_sp_port->sample->truncate ?
3163 mlxsw_sp_port->sample->trunc_size : skb->len;
3164
3165 rcu_read_lock();
3166 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3167 if (!psample_group)
3168 goto out_unlock;
3169 psample_sample_packet(psample_group, skb, size,
3170 mlxsw_sp_port->dev->ifindex, 0,
3171 mlxsw_sp_port->sample->rate);
3172out_unlock:
3173 rcu_read_unlock();
3174out:
3175 consume_skb(skb);
3176}
3177
Nogah Frankel117b0da2016-11-25 10:33:44 +01003178#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003179 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003180 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003181
Nogah Frankel117b0da2016-11-25 10:33:44 +01003182#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003183 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003184 _is_ctrl, SP_##_trap_group, DISCARD)
3185
3186#define MLXSW_SP_EVENTL(_func, _trap_id) \
3187 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003188
Nogah Frankel45449132016-11-25 10:33:35 +01003189static const struct mlxsw_listener mlxsw_sp_listener[] = {
3190 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003191 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003192 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003193 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3194 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3195 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3196 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3197 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3198 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3199 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3200 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3201 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3202 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3203 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003204 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003205 /* L3 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003206 MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3207 MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3208 MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3209 MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, OSPF, false),
3210 MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
3211 MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
3212 MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, ARP_MISS, false),
3213 MLXSW_SP_RXL_NO_MARK(BGP_IPV4, TRAP_TO_CPU, BGP_IPV4, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003214 /* PKT Sample trap */
3215 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003216 false, SP_IP2ME, DISCARD),
3217 /* ACL trap */
3218 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003219};
3220
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003221static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3222{
3223 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3224 enum mlxsw_reg_qpcr_ir_units ir_units;
3225 int max_cpu_policers;
3226 bool is_bytes;
3227 u8 burst_size;
3228 u32 rate;
3229 int i, err;
3230
3231 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3232 return -EIO;
3233
3234 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3235
3236 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3237 for (i = 0; i < max_cpu_policers; i++) {
3238 is_bytes = false;
3239 switch (i) {
3240 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3241 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3242 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3243 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3244 rate = 128;
3245 burst_size = 7;
3246 break;
3247 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3248 rate = 16 * 1024;
3249 burst_size = 10;
3250 break;
3251 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3252 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3253 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3254 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3255 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3256 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3257 rate = 1024;
3258 burst_size = 7;
3259 break;
3260 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3261 is_bytes = true;
3262 rate = 4 * 1024;
3263 burst_size = 4;
3264 break;
3265 default:
3266 continue;
3267 }
3268
3269 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3270 burst_size);
3271 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3272 if (err)
3273 return err;
3274 }
3275
3276 return 0;
3277}
3278
Nogah Frankel579c82e2016-11-25 10:33:42 +01003279static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003280{
3281 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003282 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003283 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003284 int max_trap_groups;
3285 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003286 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003287 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003288
3289 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3290 return -EIO;
3291
3292 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003293 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003294
3295 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003296 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003297 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003298 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3299 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3300 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3301 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3302 priority = 5;
3303 tc = 5;
3304 break;
3305 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3306 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3307 priority = 4;
3308 tc = 4;
3309 break;
3310 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3311 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3312 priority = 3;
3313 tc = 3;
3314 break;
3315 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3316 priority = 2;
3317 tc = 2;
3318 break;
3319 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3320 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3321 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3322 priority = 1;
3323 tc = 1;
3324 break;
3325 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003326 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3327 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003328 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003329 break;
3330 default:
3331 continue;
3332 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003333
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003334 if (max_cpu_policers <= policer_id &&
3335 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3336 return -EIO;
3337
3338 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003339 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3340 if (err)
3341 return err;
3342 }
3343
3344 return 0;
3345}
3346
3347static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3348{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003349 int i;
3350 int err;
3351
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003352 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3353 if (err)
3354 return err;
3355
Nogah Frankel579c82e2016-11-25 10:33:42 +01003356 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003357 if (err)
3358 return err;
3359
Nogah Frankel45449132016-11-25 10:33:35 +01003360 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003361 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003362 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003363 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003364 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003365 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003366
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003367 }
3368 return 0;
3369
Nogah Frankel45449132016-11-25 10:33:35 +01003370err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003371 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003372 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003373 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003374 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003375 }
3376 return err;
3377}
3378
3379static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3380{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003381 int i;
3382
Nogah Frankel45449132016-11-25 10:33:35 +01003383 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003384 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003385 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003386 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003387 }
3388}
3389
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003390static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3391{
3392 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003393 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003394
3395 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3396 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3397 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3398 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3399 MLXSW_REG_SLCR_LAG_HASH_SIP |
3400 MLXSW_REG_SLCR_LAG_HASH_DIP |
3401 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3402 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3403 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003404 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3405 if (err)
3406 return err;
3407
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003408 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3409 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003410 return -EIO;
3411
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003412 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003413 sizeof(struct mlxsw_sp_upper),
3414 GFP_KERNEL);
3415 if (!mlxsw_sp->lags)
3416 return -ENOMEM;
3417
3418 return 0;
3419}
3420
3421static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3422{
3423 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003424}
3425
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003426static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3427{
3428 char htgt_pl[MLXSW_REG_HTGT_LEN];
3429
Nogah Frankel579c82e2016-11-25 10:33:42 +01003430 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3431 MLXSW_REG_HTGT_INVALID_POLICER,
3432 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3433 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003434 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3435}
3436
Jiri Pirkob2f10572016-04-08 19:11:23 +02003437static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003438 const struct mlxsw_bus_info *mlxsw_bus_info)
3439{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003440 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003441 int err;
3442
3443 mlxsw_sp->core = mlxsw_core;
3444 mlxsw_sp->bus_info = mlxsw_bus_info;
3445
Yotam Gigi6b742192017-05-23 21:56:29 +02003446 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3447 if (err) {
3448 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3449 return err;
3450 }
3451
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003452 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3453 if (err) {
3454 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3455 return err;
3456 }
3457
Ido Schimmela1107482017-05-26 08:37:39 +02003458 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003459 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003460 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Nogah Frankel45449132016-11-25 10:33:35 +01003461 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003462 }
3463
Ido Schimmela1107482017-05-26 08:37:39 +02003464 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003465 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003466 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3467 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003468 }
3469
3470 err = mlxsw_sp_buffers_init(mlxsw_sp);
3471 if (err) {
3472 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3473 goto err_buffers_init;
3474 }
3475
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003476 err = mlxsw_sp_lag_init(mlxsw_sp);
3477 if (err) {
3478 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3479 goto err_lag_init;
3480 }
3481
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003482 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3483 if (err) {
3484 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3485 goto err_switchdev_init;
3486 }
3487
Ido Schimmel464dce12016-07-02 11:00:15 +02003488 err = mlxsw_sp_router_init(mlxsw_sp);
3489 if (err) {
3490 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3491 goto err_router_init;
3492 }
3493
Yotam Gigi763b4b72016-07-21 12:03:17 +02003494 err = mlxsw_sp_span_init(mlxsw_sp);
3495 if (err) {
3496 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3497 goto err_span_init;
3498 }
3499
Jiri Pirko22a67762017-02-03 10:29:07 +01003500 err = mlxsw_sp_acl_init(mlxsw_sp);
3501 if (err) {
3502 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3503 goto err_acl_init;
3504 }
3505
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003506 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3507 if (err) {
3508 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3509 goto err_counter_pool_init;
3510 }
3511
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003512 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3513 if (err) {
3514 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3515 goto err_dpipe_init;
3516 }
3517
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003518 err = mlxsw_sp_ports_create(mlxsw_sp);
3519 if (err) {
3520 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3521 goto err_ports_create;
3522 }
3523
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003524 return 0;
3525
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003526err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003527 mlxsw_sp_dpipe_fini(mlxsw_sp);
3528err_dpipe_init:
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003529 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3530err_counter_pool_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003531 mlxsw_sp_acl_fini(mlxsw_sp);
3532err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02003533 mlxsw_sp_span_fini(mlxsw_sp);
3534err_span_init:
Ido Schimmel464dce12016-07-02 11:00:15 +02003535 mlxsw_sp_router_fini(mlxsw_sp);
3536err_router_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003537 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003538err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003539 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003540err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003541 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003542err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003543 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003544err_traps_init:
3545 mlxsw_sp_fids_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003546 return err;
3547}
3548
Jiri Pirkob2f10572016-04-08 19:11:23 +02003549static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003550{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003551 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003552
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003553 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003554 mlxsw_sp_dpipe_fini(mlxsw_sp);
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003555 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003556 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003557 mlxsw_sp_span_fini(mlxsw_sp);
Ido Schimmel464dce12016-07-02 11:00:15 +02003558 mlxsw_sp_router_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003559 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003560 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003561 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003562 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003563 mlxsw_sp_fids_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003564}
3565
3566static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3567 .used_max_vepa_channels = 1,
3568 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003569 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003570 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003571 .used_max_pgt = 1,
3572 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003573 .used_flood_tables = 1,
3574 .used_flood_mode = 1,
3575 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003576 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003577 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003578 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02003579 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003580 .used_max_ib_mc = 1,
3581 .max_ib_mc = 0,
3582 .used_max_pkey = 1,
3583 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003584 .used_kvd_split_data = 1,
3585 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3586 .kvd_hash_single_parts = 2,
3587 .kvd_hash_double_parts = 1,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003588 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003589 .swid_config = {
3590 {
3591 .used_type = 1,
3592 .type = MLXSW_PORT_SWID_TYPE_ETH,
3593 }
3594 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003595 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003596};
3597
3598static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003599 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003600 .priv_size = sizeof(struct mlxsw_sp),
3601 .init = mlxsw_sp_init,
3602 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003603 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003604 .port_split = mlxsw_sp_port_split,
3605 .port_unsplit = mlxsw_sp_port_unsplit,
3606 .sb_pool_get = mlxsw_sp_sb_pool_get,
3607 .sb_pool_set = mlxsw_sp_sb_pool_set,
3608 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3609 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3610 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3611 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3612 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3613 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3614 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3615 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3616 .txhdr_construct = mlxsw_sp_txhdr_construct,
3617 .txhdr_len = MLXSW_TXHDR_LEN,
3618 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003619};
3620
Jiri Pirko22a67762017-02-03 10:29:07 +01003621bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003622{
3623 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3624}
3625
Jiri Pirko1182e532017-03-06 21:25:20 +01003626static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07003627{
Jiri Pirko1182e532017-03-06 21:25:20 +01003628 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07003629 int ret = 0;
3630
3631 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01003632 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07003633 ret = 1;
3634 }
3635
3636 return ret;
3637}
3638
Ido Schimmelc57529e2017-05-26 08:37:31 +02003639struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003640{
Jiri Pirko1182e532017-03-06 21:25:20 +01003641 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003642
3643 if (mlxsw_sp_port_dev_check(dev))
3644 return netdev_priv(dev);
3645
Jiri Pirko1182e532017-03-06 21:25:20 +01003646 mlxsw_sp_port = NULL;
3647 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003648
Jiri Pirko1182e532017-03-06 21:25:20 +01003649 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003650}
3651
Ido Schimmel4724ba562017-03-10 08:53:39 +01003652struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003653{
3654 struct mlxsw_sp_port *mlxsw_sp_port;
3655
3656 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3657 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3658}
3659
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02003660struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003661{
Jiri Pirko1182e532017-03-06 21:25:20 +01003662 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003663
3664 if (mlxsw_sp_port_dev_check(dev))
3665 return netdev_priv(dev);
3666
Jiri Pirko1182e532017-03-06 21:25:20 +01003667 mlxsw_sp_port = NULL;
3668 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
3669 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003670
Jiri Pirko1182e532017-03-06 21:25:20 +01003671 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003672}
3673
3674struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3675{
3676 struct mlxsw_sp_port *mlxsw_sp_port;
3677
3678 rcu_read_lock();
3679 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3680 if (mlxsw_sp_port)
3681 dev_hold(mlxsw_sp_port->dev);
3682 rcu_read_unlock();
3683 return mlxsw_sp_port;
3684}
3685
3686void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3687{
3688 dev_put(mlxsw_sp_port->dev);
3689}
3690
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003691static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003692{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003693 char sldr_pl[MLXSW_REG_SLDR_LEN];
3694
3695 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3696 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3697}
3698
3699static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3700{
3701 char sldr_pl[MLXSW_REG_SLDR_LEN];
3702
3703 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3704 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3705}
3706
3707static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3708 u16 lag_id, u8 port_index)
3709{
3710 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3711 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3712
3713 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
3714 lag_id, port_index);
3715 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3716}
3717
3718static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3719 u16 lag_id)
3720{
3721 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3722 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3723
3724 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
3725 lag_id);
3726 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3727}
3728
3729static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
3730 u16 lag_id)
3731{
3732 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3733 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3734
3735 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
3736 lag_id);
3737 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3738}
3739
3740static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
3741 u16 lag_id)
3742{
3743 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3744 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3745
3746 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
3747 lag_id);
3748 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3749}
3750
3751static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3752 struct net_device *lag_dev,
3753 u16 *p_lag_id)
3754{
3755 struct mlxsw_sp_upper *lag;
3756 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003757 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003758 int i;
3759
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003760 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
3761 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003762 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
3763 if (lag->ref_count) {
3764 if (lag->dev == lag_dev) {
3765 *p_lag_id = i;
3766 return 0;
3767 }
3768 } else if (free_lag_id < 0) {
3769 free_lag_id = i;
3770 }
3771 }
3772 if (free_lag_id < 0)
3773 return -EBUSY;
3774 *p_lag_id = free_lag_id;
3775 return 0;
3776}
3777
3778static bool
3779mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
3780 struct net_device *lag_dev,
3781 struct netdev_lag_upper_info *lag_upper_info)
3782{
3783 u16 lag_id;
3784
3785 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
3786 return false;
3787 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
3788 return false;
3789 return true;
3790}
3791
3792static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3793 u16 lag_id, u8 *p_port_index)
3794{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003795 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003796 int i;
3797
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003798 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3799 MAX_LAG_MEMBERS);
3800 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003801 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
3802 *p_port_index = i;
3803 return 0;
3804 }
3805 }
3806 return -EBUSY;
3807}
3808
3809static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
3810 struct net_device *lag_dev)
3811{
3812 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02003813 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003814 struct mlxsw_sp_upper *lag;
3815 u16 lag_id;
3816 u8 port_index;
3817 int err;
3818
3819 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
3820 if (err)
3821 return err;
3822 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3823 if (!lag->ref_count) {
3824 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
3825 if (err)
3826 return err;
3827 lag->dev = lag_dev;
3828 }
3829
3830 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
3831 if (err)
3832 return err;
3833 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
3834 if (err)
3835 goto err_col_port_add;
3836 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
3837 if (err)
3838 goto err_col_port_enable;
3839
3840 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
3841 mlxsw_sp_port->local_port);
3842 mlxsw_sp_port->lag_id = lag_id;
3843 mlxsw_sp_port->lagged = 1;
3844 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003845
Ido Schimmelc57529e2017-05-26 08:37:31 +02003846 /* Port is no longer usable as a router interface */
3847 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
3848 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02003849 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003850
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003851 return 0;
3852
Ido Schimmel51554db2016-05-06 22:18:39 +02003853err_col_port_enable:
3854 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003855err_col_port_add:
3856 if (!lag->ref_count)
3857 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003858 return err;
3859}
3860
Ido Schimmel82e6db02016-06-20 23:04:04 +02003861static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
3862 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003863{
3864 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003865 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02003866 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003867
3868 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02003869 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003870 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
3871 WARN_ON(lag->ref_count == 0);
3872
Ido Schimmel82e6db02016-06-20 23:04:04 +02003873 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
3874 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003875
Ido Schimmelc57529e2017-05-26 08:37:31 +02003876 /* Any VLANs configured on the port are no longer valid */
3877 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01003878
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003879 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02003880 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003881
3882 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
3883 mlxsw_sp_port->local_port);
3884 mlxsw_sp_port->lagged = 0;
3885 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02003886
Ido Schimmelc57529e2017-05-26 08:37:31 +02003887 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3888 /* Make sure untagged frames are allowed to ingress */
3889 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003890}
3891
Jiri Pirko74581202015-12-03 12:12:30 +01003892static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3893 u16 lag_id)
3894{
3895 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3896 char sldr_pl[MLXSW_REG_SLDR_LEN];
3897
3898 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
3899 mlxsw_sp_port->local_port);
3900 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3901}
3902
3903static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3904 u16 lag_id)
3905{
3906 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3907 char sldr_pl[MLXSW_REG_SLDR_LEN];
3908
3909 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
3910 mlxsw_sp_port->local_port);
3911 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3912}
3913
3914static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
3915 bool lag_tx_enabled)
3916{
3917 if (lag_tx_enabled)
3918 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
3919 mlxsw_sp_port->lag_id);
3920 else
3921 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
3922 mlxsw_sp_port->lag_id);
3923}
3924
3925static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
3926 struct netdev_lag_lower_state_info *info)
3927{
3928 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
3929}
3930
Jiri Pirko2b94e582017-04-18 16:55:37 +02003931static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
3932 bool enable)
3933{
3934 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3935 enum mlxsw_reg_spms_state spms_state;
3936 char *spms_pl;
3937 u16 vid;
3938 int err;
3939
3940 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
3941 MLXSW_REG_SPMS_STATE_DISCARDING;
3942
3943 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
3944 if (!spms_pl)
3945 return -ENOMEM;
3946 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
3947
3948 for (vid = 0; vid < VLAN_N_VID; vid++)
3949 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
3950
3951 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
3952 kfree(spms_pl);
3953 return err;
3954}
3955
3956static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
3957{
3958 int err;
3959
Ido Schimmel4aafc362017-05-26 08:37:25 +02003960 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02003961 if (err)
3962 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02003963 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
3964 if (err)
3965 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02003966 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
3967 true, false);
3968 if (err)
3969 goto err_port_vlan_set;
3970 return 0;
3971
3972err_port_vlan_set:
3973 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02003974err_port_stp_set:
3975 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02003976 return err;
3977}
3978
3979static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
3980{
3981 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
3982 false, false);
3983 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02003984 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02003985}
3986
Ido Schimmelf0cebd82017-05-26 08:37:29 +02003987static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
3988 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01003989 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003990{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003991 struct netdev_notifier_changeupper_info *info;
3992 struct mlxsw_sp_port *mlxsw_sp_port;
3993 struct net_device *upper_dev;
3994 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02003995 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003996
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003997 mlxsw_sp_port = netdev_priv(dev);
3998 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3999 info = ptr;
4000
4001 switch (event) {
4002 case NETDEV_PRECHANGEUPPER:
4003 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004004 if (!is_vlan_dev(upper_dev) &&
4005 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004006 !netif_is_bridge_master(upper_dev) &&
Jiri Pirko2b94e582017-04-18 16:55:37 +02004007 !netif_is_ovs_master(upper_dev))
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004008 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004009 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004010 break;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004011 if (netif_is_lag_master(upper_dev) &&
4012 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4013 info->upper_info))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004014 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004015 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4016 return -EINVAL;
4017 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4018 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4019 return -EINVAL;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004020 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev))
4021 return -EINVAL;
4022 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev))
4023 return -EINVAL;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004024 break;
4025 case NETDEV_CHANGEUPPER:
4026 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004027 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004028 if (info->linking)
4029 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004030 lower_dev,
Ido Schimmel7117a572016-06-20 23:04:06 +02004031 upper_dev);
4032 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004033 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4034 lower_dev,
4035 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004036 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004037 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004038 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4039 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004040 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004041 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4042 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004043 } else if (netif_is_ovs_master(upper_dev)) {
4044 if (info->linking)
4045 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4046 else
4047 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004048 }
4049 break;
4050 }
4051
Ido Schimmel80bedf12016-06-20 23:03:59 +02004052 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004053}
4054
Jiri Pirko74581202015-12-03 12:12:30 +01004055static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4056 unsigned long event, void *ptr)
4057{
4058 struct netdev_notifier_changelowerstate_info *info;
4059 struct mlxsw_sp_port *mlxsw_sp_port;
4060 int err;
4061
4062 mlxsw_sp_port = netdev_priv(dev);
4063 info = ptr;
4064
4065 switch (event) {
4066 case NETDEV_CHANGELOWERSTATE:
4067 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4068 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4069 info->lower_state_info);
4070 if (err)
4071 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4072 }
4073 break;
4074 }
4075
Ido Schimmel80bedf12016-06-20 23:03:59 +02004076 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004077}
4078
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004079static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4080 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004081 unsigned long event, void *ptr)
4082{
4083 switch (event) {
4084 case NETDEV_PRECHANGEUPPER:
4085 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004086 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4087 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004088 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004089 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4090 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004091 }
4092
Ido Schimmel80bedf12016-06-20 23:03:59 +02004093 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004094}
4095
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004096static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4097 unsigned long event, void *ptr)
4098{
4099 struct net_device *dev;
4100 struct list_head *iter;
4101 int ret;
4102
4103 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4104 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004105 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4106 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004107 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004108 return ret;
4109 }
4110 }
4111
Ido Schimmel80bedf12016-06-20 23:03:59 +02004112 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004113}
4114
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004115static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4116 struct net_device *dev,
4117 unsigned long event, void *ptr,
4118 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004119{
4120 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4121 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004122 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004123 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004124
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004125 switch (event) {
4126 case NETDEV_PRECHANGEUPPER:
4127 upper_dev = info->upper_dev;
Ido Schimmelb1e45522017-04-30 19:47:14 +03004128 if (!netif_is_bridge_master(upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004129 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004130 break;
4131 case NETDEV_CHANGEUPPER:
4132 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004133 if (netif_is_bridge_master(upper_dev)) {
4134 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004135 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4136 vlan_dev,
4137 upper_dev);
Ido Schimmel1f880612017-03-10 08:53:35 +01004138 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004139 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4140 vlan_dev,
4141 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004142 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004143 err = -EINVAL;
4144 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004145 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004146 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004147 }
4148
Ido Schimmel80bedf12016-06-20 23:03:59 +02004149 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004150}
4151
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004152static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4153 struct net_device *lag_dev,
4154 unsigned long event,
4155 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004156{
4157 struct net_device *dev;
4158 struct list_head *iter;
4159 int ret;
4160
4161 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4162 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004163 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4164 event, ptr,
4165 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004166 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004167 return ret;
4168 }
4169 }
4170
Ido Schimmel80bedf12016-06-20 23:03:59 +02004171 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004172}
4173
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004174static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4175 unsigned long event, void *ptr)
4176{
4177 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4178 u16 vid = vlan_dev_vlan_id(vlan_dev);
4179
Ido Schimmel272c4472015-12-15 16:03:47 +01004180 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004181 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4182 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01004183 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004184 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4185 real_dev, event,
4186 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004187
Ido Schimmel80bedf12016-06-20 23:03:59 +02004188 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004189}
4190
Ido Schimmelb1e45522017-04-30 19:47:14 +03004191static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4192{
4193 struct netdev_notifier_changeupper_info *info = ptr;
4194
4195 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4196 return false;
4197 return netif_is_l3_master(info->upper_dev);
4198}
4199
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004200static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4201 unsigned long event, void *ptr)
4202{
4203 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004204 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004205
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004206 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4207 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004208 else if (mlxsw_sp_is_vrf_event(event, ptr))
4209 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004210 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004211 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004212 else if (netif_is_lag_master(dev))
4213 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4214 else if (is_vlan_dev(dev))
4215 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004216
Ido Schimmel80bedf12016-06-20 23:03:59 +02004217 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004218}
4219
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004220static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4221 .notifier_call = mlxsw_sp_netdevice_event,
4222};
4223
Ido Schimmel99724c12016-07-04 08:23:14 +02004224static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4225 .notifier_call = mlxsw_sp_inetaddr_event,
4226 .priority = 10, /* Must be called before FIB notifier block */
4227};
4228
Jiri Pirkoe7322632016-09-01 10:37:43 +02004229static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4230 .notifier_call = mlxsw_sp_router_netevent_event,
4231};
4232
Jiri Pirko1d20d232016-10-27 15:12:59 +02004233static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4234 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4235 {0, },
4236};
4237
4238static struct pci_driver mlxsw_sp_pci_driver = {
4239 .name = mlxsw_sp_driver_name,
4240 .id_table = mlxsw_sp_pci_id_table,
4241};
4242
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004243static int __init mlxsw_sp_module_init(void)
4244{
4245 int err;
4246
4247 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004248 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004249 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4250
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004251 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4252 if (err)
4253 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004254
4255 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4256 if (err)
4257 goto err_pci_driver_register;
4258
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004259 return 0;
4260
Jiri Pirko1d20d232016-10-27 15:12:59 +02004261err_pci_driver_register:
4262 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004263err_core_driver_register:
Jiri Pirkoe7322632016-09-01 10:37:43 +02004264 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004265 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004266 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4267 return err;
4268}
4269
4270static void __exit mlxsw_sp_module_exit(void)
4271{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004272 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004273 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004274 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004275 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004276 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4277}
4278
4279module_init(mlxsw_sp_module_init);
4280module_exit(mlxsw_sp_module_exit);
4281
4282MODULE_LICENSE("Dual BSD/GPL");
4283MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4284MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004285MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02004286MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);