blob: 63e50877796b1a6c835788892ef04881aaf0fe6e [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +020056#include <linux/netlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020057#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020058#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020060#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010061#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020062#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020063
64#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020065#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020066#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010071#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020072#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020073#include "spectrum_acl_flex_actions.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020074#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020075
Yotam Gigi6b742192017-05-23 21:56:29 +020076#define MLXSW_FWREV_MAJOR 13
77#define MLXSW_FWREV_MINOR 1420
78#define MLXSW_FWREV_SUBMINOR 122
79
80static const struct mlxsw_fw_rev mlxsw_sp_supported_fw_rev = {
81 .major = MLXSW_FWREV_MAJOR,
82 .minor = MLXSW_FWREV_MINOR,
83 .subminor = MLXSW_FWREV_SUBMINOR
84};
85
86#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020087 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020088 "." __stringify(MLXSW_FWREV_MINOR) \
89 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
90
Jiri Pirko56ade8f2015-10-16 14:01:37 +020091static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
92static const char mlxsw_sp_driver_version[] = "1.0";
93
94/* tx_hdr_version
95 * Tx header version.
96 * Must be set to 1.
97 */
98MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
99
100/* tx_hdr_ctl
101 * Packet control type.
102 * 0 - Ethernet control (e.g. EMADs, LACP)
103 * 1 - Ethernet data
104 */
105MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
106
107/* tx_hdr_proto
108 * Packet protocol type. Must be set to 1 (Ethernet).
109 */
110MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
111
112/* tx_hdr_rx_is_router
113 * Packet is sent from the router. Valid for data packets only.
114 */
115MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
116
117/* tx_hdr_fid_valid
118 * Indicates if the 'fid' field is valid and should be used for
119 * forwarding lookup. Valid for data packets only.
120 */
121MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
122
123/* tx_hdr_swid
124 * Switch partition ID. Must be set to 0.
125 */
126MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
127
128/* tx_hdr_control_tclass
129 * Indicates if the packet should use the control TClass and not one
130 * of the data TClasses.
131 */
132MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
133
134/* tx_hdr_etclass
135 * Egress TClass to be used on the egress device on the egress port.
136 */
137MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
138
139/* tx_hdr_port_mid
140 * Destination local port for unicast packets.
141 * Destination multicast ID for multicast packets.
142 *
143 * Control packets are directed to a specific egress port, while data
144 * packets are transmitted through the CPU port (0) into the switch partition,
145 * where forwarding rules are applied.
146 */
147MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
148
149/* tx_hdr_fid
150 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
151 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
152 * Valid for data packets only.
153 */
154MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
155
156/* tx_hdr_type
157 * 0 - Data packets
158 * 6 - Control packets
159 */
160MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
161
Yotam Gigie5e5c882017-05-23 21:56:27 +0200162struct mlxsw_sp_mlxfw_dev {
163 struct mlxfw_dev mlxfw_dev;
164 struct mlxsw_sp *mlxsw_sp;
165};
166
167static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
168 u16 component_index, u32 *p_max_size,
169 u8 *p_align_bits, u16 *p_max_write_size)
170{
171 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
172 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
173 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
174 char mcqi_pl[MLXSW_REG_MCQI_LEN];
175 int err;
176
177 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
178 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
179 if (err)
180 return err;
181 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
182 p_max_write_size);
183
184 *p_align_bits = max_t(u8, *p_align_bits, 2);
185 *p_max_write_size = min_t(u16, *p_max_write_size,
186 MLXSW_REG_MCDA_MAX_DATA_LEN);
187 return 0;
188}
189
190static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
191{
192 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
193 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
194 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
195 char mcc_pl[MLXSW_REG_MCC_LEN];
196 u8 control_state;
197 int err;
198
199 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
200 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
201 if (err)
202 return err;
203
204 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
205 if (control_state != MLXFW_FSM_STATE_IDLE)
206 return -EBUSY;
207
208 mlxsw_reg_mcc_pack(mcc_pl,
209 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
210 0, *fwhandle, 0);
211 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
212}
213
214static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
215 u32 fwhandle, u16 component_index,
216 u32 component_size)
217{
218 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
219 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
220 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
221 char mcc_pl[MLXSW_REG_MCC_LEN];
222
223 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
224 component_index, fwhandle, component_size);
225 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
226}
227
228static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
229 u32 fwhandle, u8 *data, u16 size,
230 u32 offset)
231{
232 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
233 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
234 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
235 char mcda_pl[MLXSW_REG_MCDA_LEN];
236
237 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
238 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
239}
240
241static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
242 u32 fwhandle, u16 component_index)
243{
244 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
245 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
246 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
247 char mcc_pl[MLXSW_REG_MCC_LEN];
248
249 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
250 component_index, fwhandle, 0);
251 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
252}
253
254static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
255{
256 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
257 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
258 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
259 char mcc_pl[MLXSW_REG_MCC_LEN];
260
261 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
262 fwhandle, 0);
263 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
264}
265
266static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
267 enum mlxfw_fsm_state *fsm_state,
268 enum mlxfw_fsm_state_err *fsm_state_err)
269{
270 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
271 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
272 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
273 char mcc_pl[MLXSW_REG_MCC_LEN];
274 u8 control_state;
275 u8 error_code;
276 int err;
277
278 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
279 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
280 if (err)
281 return err;
282
283 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
284 *fsm_state = control_state;
285 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
286 MLXFW_FSM_STATE_ERR_MAX);
287 return 0;
288}
289
290static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
291{
292 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
293 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
294 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
295 char mcc_pl[MLXSW_REG_MCC_LEN];
296
297 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
298 fwhandle, 0);
299 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
300}
301
302static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
303{
304 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
305 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
306 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
307 char mcc_pl[MLXSW_REG_MCC_LEN];
308
309 mlxsw_reg_mcc_pack(mcc_pl,
310 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
311 fwhandle, 0);
312 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
313}
314
315static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
316 .component_query = mlxsw_sp_component_query,
317 .fsm_lock = mlxsw_sp_fsm_lock,
318 .fsm_component_update = mlxsw_sp_fsm_component_update,
319 .fsm_block_download = mlxsw_sp_fsm_block_download,
320 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
321 .fsm_activate = mlxsw_sp_fsm_activate,
322 .fsm_query_state = mlxsw_sp_fsm_query_state,
323 .fsm_cancel = mlxsw_sp_fsm_cancel,
324 .fsm_release = mlxsw_sp_fsm_release
325};
326
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300327static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
328 const struct firmware *firmware)
329{
330 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
331 .mlxfw_dev = {
332 .ops = &mlxsw_sp_mlxfw_dev_ops,
333 .psid = mlxsw_sp->bus_info->psid,
334 .psid_size = strlen(mlxsw_sp->bus_info->psid),
335 },
336 .mlxsw_sp = mlxsw_sp
337 };
338
339 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
340}
341
Yotam Gigi6b742192017-05-23 21:56:29 +0200342static bool mlxsw_sp_fw_rev_ge(const struct mlxsw_fw_rev *a,
343 const struct mlxsw_fw_rev *b)
344{
345 if (a->major != b->major)
346 return a->major > b->major;
347 if (a->minor != b->minor)
348 return a->minor > b->minor;
349 return a->subminor >= b->subminor;
350}
351
352static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
353{
354 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200355 const struct firmware *firmware;
356 int err;
357
358 if (mlxsw_sp_fw_rev_ge(rev, &mlxsw_sp_supported_fw_rev))
359 return 0;
360
361 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d out of data\n",
362 rev->major, rev->minor, rev->subminor);
363 dev_info(mlxsw_sp->bus_info->dev, "Upgrading firmware using file %s\n",
364 MLXSW_SP_FW_FILENAME);
365
366 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
367 mlxsw_sp->bus_info->dev);
368 if (err) {
369 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
370 MLXSW_SP_FW_FILENAME);
371 return err;
372 }
373
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300374 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200375 release_firmware(firmware);
376 return err;
377}
378
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100379int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
380 unsigned int counter_index, u64 *packets,
381 u64 *bytes)
382{
383 char mgpc_pl[MLXSW_REG_MGPC_LEN];
384 int err;
385
386 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200387 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100388 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
389 if (err)
390 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200391 if (packets)
392 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
393 if (bytes)
394 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100395 return 0;
396}
397
398static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
399 unsigned int counter_index)
400{
401 char mgpc_pl[MLXSW_REG_MGPC_LEN];
402
403 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200404 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100405 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
406}
407
408int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
409 unsigned int *p_counter_index)
410{
411 int err;
412
413 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
414 p_counter_index);
415 if (err)
416 return err;
417 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
418 if (err)
419 goto err_counter_clear;
420 return 0;
421
422err_counter_clear:
423 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
424 *p_counter_index);
425 return err;
426}
427
428void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
429 unsigned int counter_index)
430{
431 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
432 counter_index);
433}
434
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200435static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
436 const struct mlxsw_tx_info *tx_info)
437{
438 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
439
440 memset(txhdr, 0, MLXSW_TXHDR_LEN);
441
442 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
443 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
444 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
445 mlxsw_tx_hdr_swid_set(txhdr, 0);
446 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
447 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
448 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
449}
450
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200451int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
452 u8 state)
453{
454 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
455 enum mlxsw_reg_spms_state spms_state;
456 char *spms_pl;
457 int err;
458
459 switch (state) {
460 case BR_STATE_FORWARDING:
461 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
462 break;
463 case BR_STATE_LEARNING:
464 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
465 break;
466 case BR_STATE_LISTENING: /* fall-through */
467 case BR_STATE_DISABLED: /* fall-through */
468 case BR_STATE_BLOCKING:
469 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
470 break;
471 default:
472 BUG();
473 }
474
475 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
476 if (!spms_pl)
477 return -ENOMEM;
478 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
479 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
480
481 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
482 kfree(spms_pl);
483 return err;
484}
485
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200486static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
487{
Elad Raz5b090742016-10-28 21:35:46 +0200488 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200489 int err;
490
491 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
492 if (err)
493 return err;
494 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
495 return 0;
496}
497
Yotam Gigi763b4b72016-07-21 12:03:17 +0200498static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
499{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200500 int i;
501
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200502 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200503 return -EIO;
504
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200505 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
506 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200507 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
508 sizeof(struct mlxsw_sp_span_entry),
509 GFP_KERNEL);
510 if (!mlxsw_sp->span.entries)
511 return -ENOMEM;
512
513 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
514 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
515
516 return 0;
517}
518
519static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
520{
521 int i;
522
523 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
524 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
525
526 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
527 }
528 kfree(mlxsw_sp->span.entries);
529}
530
531static struct mlxsw_sp_span_entry *
532mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
533{
534 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
535 struct mlxsw_sp_span_entry *span_entry;
536 char mpat_pl[MLXSW_REG_MPAT_LEN];
537 u8 local_port = port->local_port;
538 int index;
539 int i;
540 int err;
541
542 /* find a free entry to use */
543 index = -1;
544 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
545 if (!mlxsw_sp->span.entries[i].used) {
546 index = i;
547 span_entry = &mlxsw_sp->span.entries[i];
548 break;
549 }
550 }
551 if (index < 0)
552 return NULL;
553
554 /* create a new port analayzer entry for local_port */
555 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
556 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
557 if (err)
558 return NULL;
559
560 span_entry->used = true;
561 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100562 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200563 span_entry->local_port = local_port;
564 return span_entry;
565}
566
567static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
568 struct mlxsw_sp_span_entry *span_entry)
569{
570 u8 local_port = span_entry->local_port;
571 char mpat_pl[MLXSW_REG_MPAT_LEN];
572 int pa_id = span_entry->id;
573
574 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
575 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
576 span_entry->used = false;
577}
578
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200579static struct mlxsw_sp_span_entry *
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200580mlxsw_sp_span_entry_find(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200581{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200582 int i;
583
584 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
585 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
586
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200587 if (curr->used && curr->local_port == local_port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200588 return curr;
589 }
590 return NULL;
591}
592
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200593static struct mlxsw_sp_span_entry
594*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200595{
596 struct mlxsw_sp_span_entry *span_entry;
597
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200598 span_entry = mlxsw_sp_span_entry_find(port->mlxsw_sp,
599 port->local_port);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200600 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100601 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200602 span_entry->ref_count++;
603 return span_entry;
604 }
605
606 return mlxsw_sp_span_entry_create(port);
607}
608
609static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
610 struct mlxsw_sp_span_entry *span_entry)
611{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100612 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200613 if (--span_entry->ref_count == 0)
614 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
615 return 0;
616}
617
618static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
619{
620 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
621 struct mlxsw_sp_span_inspected_port *p;
622 int i;
623
624 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
625 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
626
627 list_for_each_entry(p, &curr->bound_ports_list, list)
628 if (p->local_port == port->local_port &&
629 p->type == MLXSW_SP_SPAN_EGRESS)
630 return true;
631 }
632
633 return false;
634}
635
Ido Schimmel18281f22017-03-24 08:02:51 +0100636static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
637 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200638{
Ido Schimmel18281f22017-03-24 08:02:51 +0100639 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200640}
641
642static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
643{
644 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
645 char sbib_pl[MLXSW_REG_SBIB_LEN];
646 int err;
647
648 /* If port is egress mirrored, the shared buffer size should be
649 * updated according to the mtu value
650 */
651 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100652 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
653
654 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200655 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
656 if (err) {
657 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
658 return err;
659 }
660 }
661
662 return 0;
663}
664
665static struct mlxsw_sp_span_inspected_port *
666mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
667 struct mlxsw_sp_span_entry *span_entry)
668{
669 struct mlxsw_sp_span_inspected_port *p;
670
671 list_for_each_entry(p, &span_entry->bound_ports_list, list)
672 if (port->local_port == p->local_port)
673 return p;
674 return NULL;
675}
676
677static int
678mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
679 struct mlxsw_sp_span_entry *span_entry,
680 enum mlxsw_sp_span_type type)
681{
682 struct mlxsw_sp_span_inspected_port *inspected_port;
683 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
684 char mpar_pl[MLXSW_REG_MPAR_LEN];
685 char sbib_pl[MLXSW_REG_SBIB_LEN];
686 int pa_id = span_entry->id;
687 int err;
688
689 /* if it is an egress SPAN, bind a shared buffer to it */
690 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100691 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
692 port->dev->mtu);
693
694 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200695 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
696 if (err) {
697 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
698 return err;
699 }
700 }
701
702 /* bind the port to the SPAN entry */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200703 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
704 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200705 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
706 if (err)
707 goto err_mpar_reg_write;
708
709 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
710 if (!inspected_port) {
711 err = -ENOMEM;
712 goto err_inspected_port_alloc;
713 }
714 inspected_port->local_port = port->local_port;
715 inspected_port->type = type;
716 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
717
718 return 0;
719
720err_mpar_reg_write:
721err_inspected_port_alloc:
722 if (type == MLXSW_SP_SPAN_EGRESS) {
723 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
724 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
725 }
726 return err;
727}
728
729static void
730mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
731 struct mlxsw_sp_span_entry *span_entry,
732 enum mlxsw_sp_span_type type)
733{
734 struct mlxsw_sp_span_inspected_port *inspected_port;
735 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
736 char mpar_pl[MLXSW_REG_MPAR_LEN];
737 char sbib_pl[MLXSW_REG_SBIB_LEN];
738 int pa_id = span_entry->id;
739
740 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
741 if (!inspected_port)
742 return;
743
744 /* remove the inspected port */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200745 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
746 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200747 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
748
749 /* remove the SBIB buffer if it was egress SPAN */
750 if (type == MLXSW_SP_SPAN_EGRESS) {
751 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
752 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
753 }
754
755 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
756
757 list_del(&inspected_port->list);
758 kfree(inspected_port);
759}
760
761static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
762 struct mlxsw_sp_port *to,
763 enum mlxsw_sp_span_type type)
764{
765 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
766 struct mlxsw_sp_span_entry *span_entry;
767 int err;
768
769 span_entry = mlxsw_sp_span_entry_get(to);
770 if (!span_entry)
771 return -ENOENT;
772
773 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
774 span_entry->id);
775
776 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
777 if (err)
778 goto err_port_bind;
779
780 return 0;
781
782err_port_bind:
783 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
784 return err;
785}
786
787static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200788 u8 destination_port,
Yotam Gigi763b4b72016-07-21 12:03:17 +0200789 enum mlxsw_sp_span_type type)
790{
791 struct mlxsw_sp_span_entry *span_entry;
792
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200793 span_entry = mlxsw_sp_span_entry_find(from->mlxsw_sp,
794 destination_port);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200795 if (!span_entry) {
796 netdev_err(from->dev, "no span entry found\n");
797 return;
798 }
799
800 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
801 span_entry->id);
802 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
803}
804
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100805static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
806 bool enable, u32 rate)
807{
808 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
809 char mpsc_pl[MLXSW_REG_MPSC_LEN];
810
811 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
812 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
813}
814
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200815static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
816 bool is_up)
817{
818 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
819 char paos_pl[MLXSW_REG_PAOS_LEN];
820
821 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
822 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
823 MLXSW_PORT_ADMIN_STATUS_DOWN);
824 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
825}
826
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200827static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
828 unsigned char *addr)
829{
830 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
831 char ppad_pl[MLXSW_REG_PPAD_LEN];
832
833 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
834 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
835 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
836}
837
838static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
839{
840 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
841 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
842
843 ether_addr_copy(addr, mlxsw_sp->base_mac);
844 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
845 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
846}
847
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200848static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
849{
850 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
851 char pmtu_pl[MLXSW_REG_PMTU_LEN];
852 int max_mtu;
853 int err;
854
855 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
856 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
857 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
858 if (err)
859 return err;
860 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
861
862 if (mtu > max_mtu)
863 return -EINVAL;
864
865 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
866 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
867}
868
869static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
870{
871 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200872 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200873
Ido Schimmel5b153852017-06-08 08:47:44 +0200874 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
875 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200876}
877
Ido Schimmela1107482017-05-26 08:37:39 +0200878int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200879{
880 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
881 char svpe_pl[MLXSW_REG_SVPE_LEN];
882
883 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
884 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
885}
886
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200887int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
888 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200889{
890 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
891 char *spvmlr_pl;
892 int err;
893
894 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
895 if (!spvmlr_pl)
896 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200897 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
898 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200899 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
900 kfree(spvmlr_pl);
901 return err;
902}
903
Ido Schimmelb02eae92017-05-16 19:38:34 +0200904static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
905 u16 vid)
906{
907 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
908 char spvid_pl[MLXSW_REG_SPVID_LEN];
909
910 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
911 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
912}
913
914static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
915 bool allow)
916{
917 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
918 char spaft_pl[MLXSW_REG_SPAFT_LEN];
919
920 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
921 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
922}
923
924int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
925{
926 int err;
927
928 if (!vid) {
929 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
930 if (err)
931 return err;
932 } else {
933 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
934 if (err)
935 return err;
936 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
937 if (err)
938 goto err_port_allow_untagged_set;
939 }
940
941 mlxsw_sp_port->pvid = vid;
942 return 0;
943
944err_port_allow_untagged_set:
945 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
946 return err;
947}
948
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200949static int
950mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
951{
952 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
953 char sspr_pl[MLXSW_REG_SSPR_LEN];
954
955 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
956 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
957}
958
Ido Schimmeld664b412016-06-09 09:51:40 +0200959static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
960 u8 local_port, u8 *p_module,
961 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200962{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200963 char pmlp_pl[MLXSW_REG_PMLP_LEN];
964 int err;
965
Ido Schimmel558c2d52016-02-26 17:32:29 +0100966 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200967 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
968 if (err)
969 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100970 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
971 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200972 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200973 return 0;
974}
975
Ido Schimmel2e915e02017-06-08 08:47:45 +0200976static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100977 u8 module, u8 width, u8 lane)
978{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200979 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100980 char pmlp_pl[MLXSW_REG_PMLP_LEN];
981 int i;
982
Ido Schimmel2e915e02017-06-08 08:47:45 +0200983 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100984 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
985 for (i = 0; i < width; i++) {
986 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
987 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
988 }
989
990 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
991}
992
Ido Schimmel2e915e02017-06-08 08:47:45 +0200993static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100994{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200995 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100996 char pmlp_pl[MLXSW_REG_PMLP_LEN];
997
Ido Schimmel2e915e02017-06-08 08:47:45 +0200998 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100999 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
1000 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1001}
1002
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001003static int mlxsw_sp_port_open(struct net_device *dev)
1004{
1005 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1006 int err;
1007
1008 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1009 if (err)
1010 return err;
1011 netif_start_queue(dev);
1012 return 0;
1013}
1014
1015static int mlxsw_sp_port_stop(struct net_device *dev)
1016{
1017 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1018
1019 netif_stop_queue(dev);
1020 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1021}
1022
1023static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1024 struct net_device *dev)
1025{
1026 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1027 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1028 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1029 const struct mlxsw_tx_info tx_info = {
1030 .local_port = mlxsw_sp_port->local_port,
1031 .is_emad = false,
1032 };
1033 u64 len;
1034 int err;
1035
Jiri Pirko307c2432016-04-08 19:11:22 +02001036 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001037 return NETDEV_TX_BUSY;
1038
1039 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1040 struct sk_buff *skb_orig = skb;
1041
1042 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1043 if (!skb) {
1044 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1045 dev_kfree_skb_any(skb_orig);
1046 return NETDEV_TX_OK;
1047 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +01001048 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001049 }
1050
1051 if (eth_skb_pad(skb)) {
1052 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1053 return NETDEV_TX_OK;
1054 }
1055
1056 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +02001057 /* TX header is consumed by HW on the way so we shouldn't count its
1058 * bytes as being sent.
1059 */
1060 len = skb->len - MLXSW_TXHDR_LEN;
1061
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001062 /* Due to a race we might fail here because of a full queue. In that
1063 * unlikely case we simply drop the packet.
1064 */
Jiri Pirko307c2432016-04-08 19:11:22 +02001065 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001066
1067 if (!err) {
1068 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1069 u64_stats_update_begin(&pcpu_stats->syncp);
1070 pcpu_stats->tx_packets++;
1071 pcpu_stats->tx_bytes += len;
1072 u64_stats_update_end(&pcpu_stats->syncp);
1073 } else {
1074 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1075 dev_kfree_skb_any(skb);
1076 }
1077 return NETDEV_TX_OK;
1078}
1079
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001080static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1081{
1082}
1083
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001084static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1085{
1086 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1087 struct sockaddr *addr = p;
1088 int err;
1089
1090 if (!is_valid_ether_addr(addr->sa_data))
1091 return -EADDRNOTAVAIL;
1092
1093 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1094 if (err)
1095 return err;
1096 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1097 return 0;
1098}
1099
Ido Schimmel18281f22017-03-24 08:02:51 +01001100static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1101 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001102{
Ido Schimmel18281f22017-03-24 08:02:51 +01001103 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001104}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001105
Ido Schimmelf417f042017-03-24 08:02:50 +01001106#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +01001107
1108static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1109 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +01001110{
Ido Schimmel18281f22017-03-24 08:02:51 +01001111 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1112 BITS_PER_BYTE));
1113 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1114 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001115}
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001116
Ido Schimmel18281f22017-03-24 08:02:51 +01001117/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +01001118 * Assumes 100m cable and maximum MTU.
1119 */
Ido Schimmel18281f22017-03-24 08:02:51 +01001120#define MLXSW_SP_PAUSE_DELAY 58752
1121
1122static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1123 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +01001124{
1125 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +01001126 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +01001127 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +01001128 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001129 else
Ido Schimmelf417f042017-03-24 08:02:50 +01001130 return 0;
1131}
1132
1133static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1134 bool lossy)
1135{
1136 if (lossy)
1137 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
1138 else
1139 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1140 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001141}
1142
1143int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001144 u8 *prio_tc, bool pause_en,
1145 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +02001146{
1147 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001148 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1149 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001150 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001151 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001152
1153 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1154 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1155 if (err)
1156 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001157
1158 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1159 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001160 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +01001161 bool lossy;
1162 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001163
1164 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1165 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001166 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001167 configure = true;
1168 break;
1169 }
1170 }
1171
1172 if (!configure)
1173 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +01001174
1175 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +01001176 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1177 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1178 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +01001179 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001180 }
1181
Ido Schimmelff6551e2016-04-06 17:10:03 +02001182 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1183}
1184
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001185static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001186 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001187{
1188 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1189 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001190 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001191 u8 *prio_tc;
1192
1193 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001194 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001195
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001196 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001197 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001198}
1199
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001200static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1201{
1202 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001203 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001204 int err;
1205
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001206 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001207 if (err)
1208 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001209 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1210 if (err)
1211 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001212 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1213 if (err)
1214 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001215 dev->mtu = mtu;
1216 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001217
1218err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001219 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1220err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001221 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +02001222 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001223}
1224
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001225static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001226mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1227 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001228{
1229 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1230 struct mlxsw_sp_port_pcpu_stats *p;
1231 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1232 u32 tx_dropped = 0;
1233 unsigned int start;
1234 int i;
1235
1236 for_each_possible_cpu(i) {
1237 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1238 do {
1239 start = u64_stats_fetch_begin_irq(&p->syncp);
1240 rx_packets = p->rx_packets;
1241 rx_bytes = p->rx_bytes;
1242 tx_packets = p->tx_packets;
1243 tx_bytes = p->tx_bytes;
1244 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1245
1246 stats->rx_packets += rx_packets;
1247 stats->rx_bytes += rx_bytes;
1248 stats->tx_packets += tx_packets;
1249 stats->tx_bytes += tx_bytes;
1250 /* tx_dropped is u32, updated without syncp protection. */
1251 tx_dropped += p->tx_dropped;
1252 }
1253 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001254 return 0;
1255}
1256
Or Gerlitz3df5b3c2016-11-22 23:09:54 +02001257static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001258{
1259 switch (attr_id) {
1260 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1261 return true;
1262 }
1263
1264 return false;
1265}
1266
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001267static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1268 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001269{
1270 switch (attr_id) {
1271 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1272 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1273 }
1274
1275 return -EINVAL;
1276}
1277
1278static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1279 int prio, char *ppcnt_pl)
1280{
1281 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1283
1284 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1285 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1286}
1287
1288static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1289 struct rtnl_link_stats64 *stats)
1290{
1291 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1292 int err;
1293
1294 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1295 0, ppcnt_pl);
1296 if (err)
1297 goto out;
1298
1299 stats->tx_packets =
1300 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1301 stats->rx_packets =
1302 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1303 stats->tx_bytes =
1304 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1305 stats->rx_bytes =
1306 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1307 stats->multicast =
1308 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1309
1310 stats->rx_crc_errors =
1311 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1312 stats->rx_frame_errors =
1313 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1314
1315 stats->rx_length_errors = (
1316 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1317 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1318 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1319
1320 stats->rx_errors = (stats->rx_crc_errors +
1321 stats->rx_frame_errors + stats->rx_length_errors);
1322
1323out:
1324 return err;
1325}
1326
1327static void update_stats_cache(struct work_struct *work)
1328{
1329 struct mlxsw_sp_port *mlxsw_sp_port =
1330 container_of(work, struct mlxsw_sp_port,
Nogah Frankel9deef432017-10-26 10:55:32 +02001331 periodic_hw_stats.update_dw.work);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001332
1333 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1334 goto out;
1335
1336 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
Nogah Frankel9deef432017-10-26 10:55:32 +02001337 &mlxsw_sp_port->periodic_hw_stats.stats);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001338
1339out:
Nogah Frankel9deef432017-10-26 10:55:32 +02001340 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001341 MLXSW_HW_STATS_UPDATE_TIME);
1342}
1343
1344/* Return the stats from a cache that is updated periodically,
1345 * as this function might get called in an atomic context.
1346 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001347static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001348mlxsw_sp_port_get_stats64(struct net_device *dev,
1349 struct rtnl_link_stats64 *stats)
1350{
1351 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1352
Nogah Frankel9deef432017-10-26 10:55:32 +02001353 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001354}
1355
Jiri Pirko93cd0812017-04-18 16:55:35 +02001356static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1357 u16 vid_begin, u16 vid_end,
1358 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001359{
1360 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1361 char *spvm_pl;
1362 int err;
1363
1364 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1365 if (!spvm_pl)
1366 return -ENOMEM;
1367
1368 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1369 vid_end, is_member, untagged);
1370 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1371 kfree(spvm_pl);
1372 return err;
1373}
1374
Jiri Pirko93cd0812017-04-18 16:55:35 +02001375int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1376 u16 vid_end, bool is_member, bool untagged)
1377{
1378 u16 vid, vid_e;
1379 int err;
1380
1381 for (vid = vid_begin; vid <= vid_end;
1382 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1383 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1384 vid_end);
1385
1386 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1387 is_member, untagged);
1388 if (err)
1389 return err;
1390 }
1391
1392 return 0;
1393}
1394
Ido Schimmelc57529e2017-05-26 08:37:31 +02001395static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001396{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001397 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001398
Ido Schimmelc57529e2017-05-26 08:37:31 +02001399 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1400 &mlxsw_sp_port->vlans_list, list)
1401 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001402}
1403
Ido Schimmel31a08a52017-05-26 08:37:26 +02001404static struct mlxsw_sp_port_vlan *
1405mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1406{
1407 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001408 bool untagged = vid == 1;
1409 int err;
1410
1411 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1412 if (err)
1413 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001414
1415 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001416 if (!mlxsw_sp_port_vlan) {
1417 err = -ENOMEM;
1418 goto err_port_vlan_alloc;
1419 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001420
1421 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1422 mlxsw_sp_port_vlan->vid = vid;
1423 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1424
1425 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001426
1427err_port_vlan_alloc:
1428 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1429 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001430}
1431
1432static void
1433mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1434{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001435 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1436 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001437
Ido Schimmel31a08a52017-05-26 08:37:26 +02001438 list_del(&mlxsw_sp_port_vlan->list);
1439 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001440 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1441}
1442
1443struct mlxsw_sp_port_vlan *
1444mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1445{
1446 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1447
1448 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1449 if (mlxsw_sp_port_vlan)
1450 return mlxsw_sp_port_vlan;
1451
1452 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1453}
1454
1455void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1456{
Ido Schimmela1107482017-05-26 08:37:39 +02001457 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1458
Ido Schimmelc57529e2017-05-26 08:37:31 +02001459 if (mlxsw_sp_port_vlan->bridge_port)
1460 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001461 else if (fid)
1462 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001463
1464 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001465}
1466
Ido Schimmel05978482016-08-17 16:39:30 +02001467static int mlxsw_sp_port_add_vid(struct net_device *dev,
1468 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001469{
1470 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001471
1472 /* VLAN 0 is added to HW filter when device goes up, but it is
1473 * reserved in our case, so simply return.
1474 */
1475 if (!vid)
1476 return 0;
1477
Ido Schimmelc57529e2017-05-26 08:37:31 +02001478 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001479}
1480
Ido Schimmel32d863f2016-07-02 11:00:10 +02001481static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1482 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001483{
1484 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001485 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001486
1487 /* VLAN 0 is removed from HW filter when device goes down, but
1488 * it is reserved in our case, so simply return.
1489 */
1490 if (!vid)
1491 return 0;
1492
Ido Schimmel31a08a52017-05-26 08:37:26 +02001493 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001494 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001495 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001496 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001497
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001498 return 0;
1499}
1500
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001501static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1502 size_t len)
1503{
1504 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001505 u8 module = mlxsw_sp_port->mapping.module;
1506 u8 width = mlxsw_sp_port->mapping.width;
1507 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001508 int err;
1509
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001510 if (!mlxsw_sp_port->split)
1511 err = snprintf(name, len, "p%d", module + 1);
1512 else
1513 err = snprintf(name, len, "p%ds%d", module + 1,
1514 lane / width);
1515
1516 if (err >= len)
1517 return -EINVAL;
1518
1519 return 0;
1520}
1521
Yotam Gigi763b4b72016-07-21 12:03:17 +02001522static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001523mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1524 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001525 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1526
1527 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1528 if (mall_tc_entry->cookie == cookie)
1529 return mall_tc_entry;
1530
1531 return NULL;
1532}
1533
1534static int
1535mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001536 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001537 const struct tc_action *a,
1538 bool ingress)
1539{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001540 struct net *net = dev_net(mlxsw_sp_port->dev);
1541 enum mlxsw_sp_span_type span_type;
1542 struct mlxsw_sp_port *to_port;
1543 struct net_device *to_dev;
1544 int ifindex;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001545
1546 ifindex = tcf_mirred_ifindex(a);
1547 to_dev = __dev_get_by_index(net, ifindex);
1548 if (!to_dev) {
1549 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1550 return -EINVAL;
1551 }
1552
1553 if (!mlxsw_sp_port_dev_check(to_dev)) {
1554 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001555 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001556 }
1557 to_port = netdev_priv(to_dev);
1558
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001559 mirror->to_local_port = to_port->local_port;
1560 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001561 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001562 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1563}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001564
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001565static void
1566mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1567 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1568{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001569 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001570
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001571 span_type = mirror->ingress ?
1572 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yuval Mintz6399ebc2017-09-12 08:50:53 +02001573 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, mirror->to_local_port,
1574 span_type);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001575}
1576
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001577static int
1578mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1579 struct tc_cls_matchall_offload *cls,
1580 const struct tc_action *a,
1581 bool ingress)
1582{
1583 int err;
1584
1585 if (!mlxsw_sp_port->sample)
1586 return -EOPNOTSUPP;
1587 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1588 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1589 return -EEXIST;
1590 }
1591 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1592 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1593 return -EOPNOTSUPP;
1594 }
1595
1596 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1597 tcf_sample_psample_group(a));
1598 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1599 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1600 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1601
1602 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1603 if (err)
1604 goto err_port_sample_set;
1605 return 0;
1606
1607err_port_sample_set:
1608 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1609 return err;
1610}
1611
1612static void
1613mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1614{
1615 if (!mlxsw_sp_port->sample)
1616 return;
1617
1618 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1619 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1620}
1621
Yotam Gigi763b4b72016-07-21 12:03:17 +02001622static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001623 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001624 bool ingress)
1625{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001626 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001627 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001628 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001629 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001630 int err;
1631
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001632 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001633 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001634 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001635 }
1636
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001637 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1638 if (!mall_tc_entry)
1639 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001640 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001641
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001642 tcf_exts_to_list(f->exts, &actions);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001643 a = list_first_entry(&actions, struct tc_action, list);
1644
1645 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1646 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1647
1648 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1649 mirror = &mall_tc_entry->mirror;
1650 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1651 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001652 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1653 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001654 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001655 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001656 } else {
1657 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001658 }
1659
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001660 if (err)
1661 goto err_add_action;
1662
1663 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001664 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001665
1666err_add_action:
1667 kfree(mall_tc_entry);
1668 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001669}
1670
1671static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001672 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001673{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001674 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001675
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001676 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001677 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001678 if (!mall_tc_entry) {
1679 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1680 return;
1681 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001682 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001683
1684 switch (mall_tc_entry->type) {
1685 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001686 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1687 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001688 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001689 case MLXSW_SP_PORT_MALL_SAMPLE:
1690 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1691 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001692 default:
1693 WARN_ON(1);
1694 }
1695
Yotam Gigi763b4b72016-07-21 12:03:17 +02001696 kfree(mall_tc_entry);
1697}
1698
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001699static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001700 struct tc_cls_matchall_offload *f,
1701 bool ingress)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001702{
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001703 if (f->common.chain_index)
Jiri Pirkoa5fcf8a2017-06-06 17:00:16 +02001704 return -EOPNOTSUPP;
1705
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001706 switch (f->command) {
1707 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001708 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001709 ingress);
1710 case TC_CLSMATCHALL_DESTROY:
1711 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1712 return 0;
1713 default:
1714 return -EOPNOTSUPP;
1715 }
1716}
1717
1718static int
1719mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001720 struct tc_cls_flower_offload *f,
1721 bool ingress)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001722{
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001723 switch (f->command) {
1724 case TC_CLSFLOWER_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001725 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001726 case TC_CLSFLOWER_DESTROY:
1727 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress, f);
1728 return 0;
1729 case TC_CLSFLOWER_STATS:
1730 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress, f);
1731 default:
1732 return -EOPNOTSUPP;
1733 }
1734}
1735
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001736static int mlxsw_sp_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
1737 void *cb_priv, bool ingress)
1738{
1739 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1740
Jiri Pirko44ae12a2017-11-01 11:47:39 +01001741 if (!tc_can_offload(mlxsw_sp_port->dev))
1742 return -EOPNOTSUPP;
1743
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001744 switch (type) {
1745 case TC_SETUP_CLSMATCHALL:
1746 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1747 ingress);
1748 case TC_SETUP_CLSFLOWER:
1749 return mlxsw_sp_setup_tc_cls_flower(mlxsw_sp_port, type_data,
1750 ingress);
1751 default:
1752 return -EOPNOTSUPP;
1753 }
1754}
1755
1756static int mlxsw_sp_setup_tc_block_cb_ig(enum tc_setup_type type,
1757 void *type_data, void *cb_priv)
1758{
1759 return mlxsw_sp_setup_tc_block_cb(type, type_data, cb_priv, true);
1760}
1761
1762static int mlxsw_sp_setup_tc_block_cb_eg(enum tc_setup_type type,
1763 void *type_data, void *cb_priv)
1764{
1765 return mlxsw_sp_setup_tc_block_cb(type, type_data, cb_priv, false);
1766}
1767
1768static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1769 struct tc_block_offload *f)
1770{
1771 tc_setup_cb_t *cb;
1772
1773 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
1774 cb = mlxsw_sp_setup_tc_block_cb_ig;
1775 else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS)
1776 cb = mlxsw_sp_setup_tc_block_cb_eg;
1777 else
1778 return -EOPNOTSUPP;
1779
1780 switch (f->command) {
1781 case TC_BLOCK_BIND:
1782 return tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1783 mlxsw_sp_port);
1784 case TC_BLOCK_UNBIND:
1785 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1786 return 0;
1787 default:
1788 return -EOPNOTSUPP;
1789 }
1790}
1791
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001792static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001793 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001794{
1795 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1796
Jiri Pirko2572ac52017-08-07 10:15:17 +02001797 switch (type) {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001798 case TC_SETUP_BLOCK:
1799 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001800 default:
1801 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001802 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001803}
1804
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001805static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1806 .ndo_open = mlxsw_sp_port_open,
1807 .ndo_stop = mlxsw_sp_port_stop,
1808 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001809 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001810 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001811 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1812 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1813 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001814 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1815 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001816 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1817 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001818 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001819};
1820
1821static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1822 struct ethtool_drvinfo *drvinfo)
1823{
1824 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1825 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1826
1827 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1828 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1829 sizeof(drvinfo->version));
1830 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1831 "%d.%d.%d",
1832 mlxsw_sp->bus_info->fw_rev.major,
1833 mlxsw_sp->bus_info->fw_rev.minor,
1834 mlxsw_sp->bus_info->fw_rev.subminor);
1835 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1836 sizeof(drvinfo->bus_info));
1837}
1838
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001839static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1840 struct ethtool_pauseparam *pause)
1841{
1842 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1843
1844 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1845 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1846}
1847
1848static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1849 struct ethtool_pauseparam *pause)
1850{
1851 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1852
1853 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1854 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1855 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1856
1857 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1858 pfcc_pl);
1859}
1860
1861static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1862 struct ethtool_pauseparam *pause)
1863{
1864 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1865 bool pause_en = pause->tx_pause || pause->rx_pause;
1866 int err;
1867
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001868 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1869 netdev_err(dev, "PFC already enabled on port\n");
1870 return -EINVAL;
1871 }
1872
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001873 if (pause->autoneg) {
1874 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1875 return -EINVAL;
1876 }
1877
1878 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1879 if (err) {
1880 netdev_err(dev, "Failed to configure port's headroom\n");
1881 return err;
1882 }
1883
1884 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1885 if (err) {
1886 netdev_err(dev, "Failed to set PAUSE parameters\n");
1887 goto err_port_pause_configure;
1888 }
1889
1890 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1891 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1892
1893 return 0;
1894
1895err_port_pause_configure:
1896 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1897 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1898 return err;
1899}
1900
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001901struct mlxsw_sp_port_hw_stats {
1902 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001903 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001904 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001905};
1906
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001907static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001908 {
1909 .str = "a_frames_transmitted_ok",
1910 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1911 },
1912 {
1913 .str = "a_frames_received_ok",
1914 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1915 },
1916 {
1917 .str = "a_frame_check_sequence_errors",
1918 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1919 },
1920 {
1921 .str = "a_alignment_errors",
1922 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1923 },
1924 {
1925 .str = "a_octets_transmitted_ok",
1926 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1927 },
1928 {
1929 .str = "a_octets_received_ok",
1930 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1931 },
1932 {
1933 .str = "a_multicast_frames_xmitted_ok",
1934 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1935 },
1936 {
1937 .str = "a_broadcast_frames_xmitted_ok",
1938 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1939 },
1940 {
1941 .str = "a_multicast_frames_received_ok",
1942 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1943 },
1944 {
1945 .str = "a_broadcast_frames_received_ok",
1946 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1947 },
1948 {
1949 .str = "a_in_range_length_errors",
1950 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1951 },
1952 {
1953 .str = "a_out_of_range_length_field",
1954 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1955 },
1956 {
1957 .str = "a_frame_too_long_errors",
1958 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1959 },
1960 {
1961 .str = "a_symbol_error_during_carrier",
1962 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1963 },
1964 {
1965 .str = "a_mac_control_frames_transmitted",
1966 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1967 },
1968 {
1969 .str = "a_mac_control_frames_received",
1970 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1971 },
1972 {
1973 .str = "a_unsupported_opcodes_received",
1974 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1975 },
1976 {
1977 .str = "a_pause_mac_ctrl_frames_received",
1978 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1979 },
1980 {
1981 .str = "a_pause_mac_ctrl_frames_xmitted",
1982 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1983 },
1984};
1985
1986#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1987
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001988static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1989 {
1990 .str = "rx_octets_prio",
1991 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1992 },
1993 {
1994 .str = "rx_frames_prio",
1995 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1996 },
1997 {
1998 .str = "tx_octets_prio",
1999 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2000 },
2001 {
2002 .str = "tx_frames_prio",
2003 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2004 },
2005 {
2006 .str = "rx_pause_prio",
2007 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2008 },
2009 {
2010 .str = "rx_pause_duration_prio",
2011 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2012 },
2013 {
2014 .str = "tx_pause_prio",
2015 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2016 },
2017 {
2018 .str = "tx_pause_duration_prio",
2019 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2020 },
2021};
2022
2023#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2024
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002025static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2026 {
2027 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01002028 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2029 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002030 },
2031 {
2032 .str = "tc_no_buffer_discard_uc_tc",
2033 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2034 },
2035};
2036
2037#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2038
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002039#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002040 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
2041 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002042 IEEE_8021QAZ_MAX_TCS)
2043
2044static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2045{
2046 int i;
2047
2048 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2049 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2050 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2051 *p += ETH_GSTRING_LEN;
2052 }
2053}
2054
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002055static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2056{
2057 int i;
2058
2059 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2060 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2061 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2062 *p += ETH_GSTRING_LEN;
2063 }
2064}
2065
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002066static void mlxsw_sp_port_get_strings(struct net_device *dev,
2067 u32 stringset, u8 *data)
2068{
2069 u8 *p = data;
2070 int i;
2071
2072 switch (stringset) {
2073 case ETH_SS_STATS:
2074 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2075 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2076 ETH_GSTRING_LEN);
2077 p += ETH_GSTRING_LEN;
2078 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002079
2080 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2081 mlxsw_sp_port_get_prio_strings(&p, i);
2082
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002083 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2084 mlxsw_sp_port_get_tc_strings(&p, i);
2085
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002086 break;
2087 }
2088}
2089
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002090static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2091 enum ethtool_phys_id_state state)
2092{
2093 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2094 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2095 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2096 bool active;
2097
2098 switch (state) {
2099 case ETHTOOL_ID_ACTIVE:
2100 active = true;
2101 break;
2102 case ETHTOOL_ID_INACTIVE:
2103 active = false;
2104 break;
2105 default:
2106 return -EOPNOTSUPP;
2107 }
2108
2109 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2110 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2111}
2112
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002113static int
2114mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2115 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2116{
2117 switch (grp) {
2118 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2119 *p_hw_stats = mlxsw_sp_port_hw_stats;
2120 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2121 break;
2122 case MLXSW_REG_PPCNT_PRIO_CNT:
2123 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2124 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2125 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002126 case MLXSW_REG_PPCNT_TC_CNT:
2127 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2128 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2129 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002130 default:
2131 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002132 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002133 }
2134 return 0;
2135}
2136
2137static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2138 enum mlxsw_reg_ppcnt_grp grp, int prio,
2139 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002140{
Ido Schimmel18281f22017-03-24 08:02:51 +01002141 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2142 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002143 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002144 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002145 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002146 int err;
2147
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002148 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2149 if (err)
2150 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002151 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002152 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002153 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002154 if (!hw_stats[i].cells_bytes)
2155 continue;
2156 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2157 data[data_index + i]);
2158 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002159}
2160
2161static void mlxsw_sp_port_get_stats(struct net_device *dev,
2162 struct ethtool_stats *stats, u64 *data)
2163{
2164 int i, data_index = 0;
2165
2166 /* IEEE 802.3 Counters */
2167 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2168 data, data_index);
2169 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2170
2171 /* Per-Priority Counters */
2172 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2173 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2174 data, data_index);
2175 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2176 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002177
2178 /* Per-TC Counters */
2179 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2180 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2181 data, data_index);
2182 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2183 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002184}
2185
2186static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2187{
2188 switch (sset) {
2189 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002190 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002191 default:
2192 return -EOPNOTSUPP;
2193 }
2194}
2195
2196struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002197 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002198 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002199 u32 speed;
2200};
2201
2202static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2203 {
2204 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002205 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2206 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002207 },
2208 {
2209 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2210 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002211 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2212 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002213 },
2214 {
2215 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002216 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2217 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002218 },
2219 {
2220 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2221 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002222 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2223 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002224 },
2225 {
2226 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2227 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2228 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2229 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002230 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2231 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002232 },
2233 {
2234 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002235 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2236 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002237 },
2238 {
2239 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002240 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2241 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002242 },
2243 {
2244 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002245 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2246 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002247 },
2248 {
2249 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002250 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2251 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002252 },
2253 {
2254 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002255 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2256 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002257 },
2258 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002259 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2260 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2261 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002262 },
2263 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002264 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2265 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2266 .speed = SPEED_25000,
2267 },
2268 {
2269 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2270 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2271 .speed = SPEED_25000,
2272 },
2273 {
2274 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2275 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2276 .speed = SPEED_25000,
2277 },
2278 {
2279 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2280 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2281 .speed = SPEED_50000,
2282 },
2283 {
2284 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2285 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2286 .speed = SPEED_50000,
2287 },
2288 {
2289 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2290 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2291 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002292 },
2293 {
2294 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002295 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2296 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002297 },
2298 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002299 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2300 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2301 .speed = SPEED_56000,
2302 },
2303 {
2304 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2305 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2306 .speed = SPEED_56000,
2307 },
2308 {
2309 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2310 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2311 .speed = SPEED_56000,
2312 },
2313 {
2314 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2315 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2316 .speed = SPEED_100000,
2317 },
2318 {
2319 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2320 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2321 .speed = SPEED_100000,
2322 },
2323 {
2324 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2325 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2326 .speed = SPEED_100000,
2327 },
2328 {
2329 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2330 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2331 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002332 },
2333};
2334
2335#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2336
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002337static void
2338mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2339 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002340{
2341 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2342 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2343 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2344 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2345 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2346 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002347 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002348
2349 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2350 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2351 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2352 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2353 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002354 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002355}
2356
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002357static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002358{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002359 int i;
2360
2361 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2362 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002363 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2364 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002365 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002366}
2367
2368static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002369 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002370{
2371 u32 speed = SPEED_UNKNOWN;
2372 u8 duplex = DUPLEX_UNKNOWN;
2373 int i;
2374
2375 if (!carrier_ok)
2376 goto out;
2377
2378 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2379 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2380 speed = mlxsw_sp_port_link_mode[i].speed;
2381 duplex = DUPLEX_FULL;
2382 break;
2383 }
2384 }
2385out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002386 cmd->base.speed = speed;
2387 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002388}
2389
2390static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2391{
2392 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2393 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2394 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2395 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2396 return PORT_FIBRE;
2397
2398 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2399 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2400 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2401 return PORT_DA;
2402
2403 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2404 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2405 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2406 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2407 return PORT_NONE;
2408
2409 return PORT_OTHER;
2410}
2411
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002412static u32
2413mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002414{
2415 u32 ptys_proto = 0;
2416 int i;
2417
2418 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002419 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2420 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002421 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2422 }
2423 return ptys_proto;
2424}
2425
2426static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2427{
2428 u32 ptys_proto = 0;
2429 int i;
2430
2431 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2432 if (speed == mlxsw_sp_port_link_mode[i].speed)
2433 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2434 }
2435 return ptys_proto;
2436}
2437
Ido Schimmel18f1e702016-02-26 17:32:31 +01002438static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2439{
2440 u32 ptys_proto = 0;
2441 int i;
2442
2443 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2444 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2445 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2446 }
2447 return ptys_proto;
2448}
2449
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002450static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2451 struct ethtool_link_ksettings *cmd)
2452{
2453 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2454 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2455 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2456
2457 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2458 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2459}
2460
2461static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2462 struct ethtool_link_ksettings *cmd)
2463{
2464 if (!autoneg)
2465 return;
2466
2467 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2468 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2469}
2470
2471static void
2472mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2473 struct ethtool_link_ksettings *cmd)
2474{
2475 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2476 return;
2477
2478 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2479 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2480}
2481
2482static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2483 struct ethtool_link_ksettings *cmd)
2484{
2485 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2486 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2487 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2488 char ptys_pl[MLXSW_REG_PTYS_LEN];
2489 u8 autoneg_status;
2490 bool autoneg;
2491 int err;
2492
2493 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002494 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002495 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2496 if (err)
2497 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002498 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2499 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002500
2501 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2502
2503 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2504
2505 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2506 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2507 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2508
2509 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2510 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2511 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2512 cmd);
2513
2514 return 0;
2515}
2516
2517static int
2518mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2519 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002520{
2521 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2522 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2523 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002524 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002525 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002526 int err;
2527
Elad Raz401c8b42016-10-28 21:35:52 +02002528 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002529 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002530 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002531 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002532 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002533
2534 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2535 eth_proto_new = autoneg ?
2536 mlxsw_sp_to_ptys_advert_link(cmd) :
2537 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002538
2539 eth_proto_new = eth_proto_new & eth_proto_cap;
2540 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002541 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002542 return -EINVAL;
2543 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002544
Elad Raz401c8b42016-10-28 21:35:52 +02002545 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2546 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002547 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002548 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002549 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002550
Ido Schimmel6277d462016-07-15 11:14:58 +02002551 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002552 return 0;
2553
Ido Schimmel0c83f882016-09-12 13:26:23 +02002554 mlxsw_sp_port->link.autoneg = autoneg;
2555
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002556 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2557 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002558
2559 return 0;
2560}
2561
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002562static int mlxsw_sp_flash_device(struct net_device *dev,
2563 struct ethtool_flash *flash)
2564{
2565 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2566 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2567 const struct firmware *firmware;
2568 int err;
2569
2570 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2571 return -EOPNOTSUPP;
2572
2573 dev_hold(dev);
2574 rtnl_unlock();
2575
2576 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2577 if (err)
2578 goto out;
2579 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2580 release_firmware(firmware);
2581out:
2582 rtnl_lock();
2583 dev_put(dev);
2584 return err;
2585}
2586
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002587#define MLXSW_SP_I2C_ADDR_LOW 0x50
2588#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2589#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002590
2591static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2592 u16 offset, u16 size, void *data,
2593 unsigned int *p_read_size)
2594{
2595 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2596 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2597 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002598 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002599 int status;
2600 int err;
2601
2602 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002603
2604 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2605 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2606 /* Cross pages read, read until offset 256 in low page */
2607 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2608
2609 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2610 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2611 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2612 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2613 }
2614
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002615 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002616 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002617
2618 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2619 if (err)
2620 return err;
2621
2622 status = mlxsw_reg_mcia_status_get(mcia_pl);
2623 if (status)
2624 return -EIO;
2625
2626 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2627 memcpy(data, eeprom_tmp, size);
2628 *p_read_size = size;
2629
2630 return 0;
2631}
2632
2633enum mlxsw_sp_eeprom_module_info_rev_id {
2634 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2635 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2636 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2637};
2638
2639enum mlxsw_sp_eeprom_module_info_id {
2640 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2641 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2642 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2643 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2644};
2645
2646enum mlxsw_sp_eeprom_module_info {
2647 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2648 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2649 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2650};
2651
2652static int mlxsw_sp_get_module_info(struct net_device *netdev,
2653 struct ethtool_modinfo *modinfo)
2654{
2655 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2656 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2657 u8 module_rev_id, module_id;
2658 unsigned int read_size;
2659 int err;
2660
2661 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2662 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2663 module_info, &read_size);
2664 if (err)
2665 return err;
2666
2667 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2668 return -EIO;
2669
2670 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2671 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2672
2673 switch (module_id) {
2674 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2675 modinfo->type = ETH_MODULE_SFF_8436;
2676 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2677 break;
2678 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2679 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2680 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2681 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2682 modinfo->type = ETH_MODULE_SFF_8636;
2683 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2684 } else {
2685 modinfo->type = ETH_MODULE_SFF_8436;
2686 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2687 }
2688 break;
2689 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2690 modinfo->type = ETH_MODULE_SFF_8472;
2691 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2692 break;
2693 default:
2694 return -EINVAL;
2695 }
2696
2697 return 0;
2698}
2699
2700static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2701 struct ethtool_eeprom *ee,
2702 u8 *data)
2703{
2704 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2705 int offset = ee->offset;
2706 unsigned int read_size;
2707 int i = 0;
2708 int err;
2709
2710 if (!ee->len)
2711 return -EINVAL;
2712
2713 memset(data, 0, ee->len);
2714
2715 while (i < ee->len) {
2716 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2717 ee->len - i, data + i,
2718 &read_size);
2719 if (err) {
2720 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2721 return err;
2722 }
2723
2724 i += read_size;
2725 offset += read_size;
2726 }
2727
2728 return 0;
2729}
2730
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002731static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2732 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2733 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002734 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2735 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002736 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002737 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002738 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2739 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002740 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2741 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002742 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002743 .get_module_info = mlxsw_sp_get_module_info,
2744 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002745};
2746
Ido Schimmel18f1e702016-02-26 17:32:31 +01002747static int
2748mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2749{
2750 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2751 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2752 char ptys_pl[MLXSW_REG_PTYS_LEN];
2753 u32 eth_proto_admin;
2754
2755 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002756 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2757 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002758 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2759}
2760
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002761int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2762 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2763 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002764{
2765 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2766 char qeec_pl[MLXSW_REG_QEEC_LEN];
2767
2768 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2769 next_index);
2770 mlxsw_reg_qeec_de_set(qeec_pl, true);
2771 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2772 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2773 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2774}
2775
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002776int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2777 enum mlxsw_reg_qeec_hr hr, u8 index,
2778 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002779{
2780 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2781 char qeec_pl[MLXSW_REG_QEEC_LEN];
2782
2783 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2784 next_index);
2785 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2786 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2787 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2788}
2789
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002790int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2791 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002792{
2793 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2794 char qtct_pl[MLXSW_REG_QTCT_LEN];
2795
2796 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2797 tclass);
2798 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2799}
2800
2801static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2802{
2803 int err, i;
2804
2805 /* Setup the elements hierarcy, so that each TC is linked to
2806 * one subgroup, which are all member in the same group.
2807 */
2808 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2809 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2810 0);
2811 if (err)
2812 return err;
2813 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2814 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2815 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2816 0, false, 0);
2817 if (err)
2818 return err;
2819 }
2820 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2821 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2822 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2823 false, 0);
2824 if (err)
2825 return err;
2826 }
2827
2828 /* Make sure the max shaper is disabled in all hierarcies that
2829 * support it.
2830 */
2831 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2832 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2833 MLXSW_REG_QEEC_MAS_DIS);
2834 if (err)
2835 return err;
2836 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2837 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2838 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2839 i, 0,
2840 MLXSW_REG_QEEC_MAS_DIS);
2841 if (err)
2842 return err;
2843 }
2844 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2845 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2846 MLXSW_REG_QEEC_HIERARCY_TC,
2847 i, i,
2848 MLXSW_REG_QEEC_MAS_DIS);
2849 if (err)
2850 return err;
2851 }
2852
2853 /* Map all priorities to traffic class 0. */
2854 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2855 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2856 if (err)
2857 return err;
2858 }
2859
2860 return 0;
2861}
2862
Ido Schimmel5b153852017-06-08 08:47:44 +02002863static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2864 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002865{
Ido Schimmelc57529e2017-05-26 08:37:31 +02002866 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002867 struct mlxsw_sp_port *mlxsw_sp_port;
2868 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002869 int err;
2870
Ido Schimmel5b153852017-06-08 08:47:44 +02002871 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2872 if (err) {
2873 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2874 local_port);
2875 return err;
2876 }
2877
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002878 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02002879 if (!dev) {
2880 err = -ENOMEM;
2881 goto err_alloc_etherdev;
2882 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002883 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002884 mlxsw_sp_port = netdev_priv(dev);
2885 mlxsw_sp_port->dev = dev;
2886 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2887 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02002888 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002889 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002890 mlxsw_sp_port->mapping.module = module;
2891 mlxsw_sp_port->mapping.width = width;
2892 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002893 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02002894 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002895 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002896
2897 mlxsw_sp_port->pcpu_stats =
2898 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2899 if (!mlxsw_sp_port->pcpu_stats) {
2900 err = -ENOMEM;
2901 goto err_alloc_stats;
2902 }
2903
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002904 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2905 GFP_KERNEL);
2906 if (!mlxsw_sp_port->sample) {
2907 err = -ENOMEM;
2908 goto err_alloc_sample;
2909 }
2910
Nogah Frankel9deef432017-10-26 10:55:32 +02002911 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002912 &update_stats_cache);
2913
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002914 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2915 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2916
Ido Schimmel2e915e02017-06-08 08:47:45 +02002917 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02002918 if (err) {
2919 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2920 mlxsw_sp_port->local_port);
2921 goto err_port_module_map;
2922 }
2923
Ido Schimmel3247ff22016-09-08 08:16:02 +02002924 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2925 if (err) {
2926 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2927 mlxsw_sp_port->local_port);
2928 goto err_port_swid_set;
2929 }
2930
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002931 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2932 if (err) {
2933 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2934 mlxsw_sp_port->local_port);
2935 goto err_dev_addr_init;
2936 }
2937
2938 netif_carrier_off(dev);
2939
2940 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002941 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2942 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002943
Jarod Wilsond894be52016-10-20 13:55:16 -04002944 dev->min_mtu = 0;
2945 dev->max_mtu = ETH_MAX_MTU;
2946
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002947 /* Each packet needs to have a Tx header (metadata) on top all other
2948 * headers.
2949 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002950 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002951
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002952 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2953 if (err) {
2954 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2955 mlxsw_sp_port->local_port);
2956 goto err_port_system_port_mapping_set;
2957 }
2958
Ido Schimmel18f1e702016-02-26 17:32:31 +01002959 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2960 if (err) {
2961 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2962 mlxsw_sp_port->local_port);
2963 goto err_port_speed_by_width_set;
2964 }
2965
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002966 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2967 if (err) {
2968 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2969 mlxsw_sp_port->local_port);
2970 goto err_port_mtu_set;
2971 }
2972
2973 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2974 if (err)
2975 goto err_port_admin_status_set;
2976
2977 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2978 if (err) {
2979 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2980 mlxsw_sp_port->local_port);
2981 goto err_port_buffers_init;
2982 }
2983
Ido Schimmel90183b92016-04-06 17:10:08 +02002984 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2985 if (err) {
2986 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2987 mlxsw_sp_port->local_port);
2988 goto err_port_ets_init;
2989 }
2990
Ido Schimmelf00817d2016-04-06 17:10:09 +02002991 /* ETS and buffers must be initialized before DCB. */
2992 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2993 if (err) {
2994 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2995 mlxsw_sp_port->local_port);
2996 goto err_port_dcb_init;
2997 }
2998
Ido Schimmela1107482017-05-26 08:37:39 +02002999 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02003000 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003001 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02003002 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003003 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02003004 }
3005
Ido Schimmelc57529e2017-05-26 08:37:31 +02003006 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3007 if (IS_ERR(mlxsw_sp_port_vlan)) {
3008 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02003009 mlxsw_sp_port->local_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003010 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02003011 }
3012
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003013 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02003014 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003015 err = register_netdev(dev);
3016 if (err) {
3017 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3018 mlxsw_sp_port->local_port);
3019 goto err_register_netdev;
3020 }
3021
Elad Razd808c7e2016-10-28 21:35:57 +02003022 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3023 mlxsw_sp_port, dev, mlxsw_sp_port->split,
3024 module);
Nogah Frankel9deef432017-10-26 10:55:32 +02003025 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003026 return 0;
3027
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003028err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02003029 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003030 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003031 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3032err_port_vlan_get:
Ido Schimmela1107482017-05-26 08:37:39 +02003033 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3034err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03003035 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003036err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02003037err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003038err_port_buffers_init:
3039err_port_admin_status_set:
3040err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01003041err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003042err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003043err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02003044 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3045err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02003046 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02003047err_port_module_map:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003048 kfree(mlxsw_sp_port->sample);
3049err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003050 free_percpu(mlxsw_sp_port->pcpu_stats);
3051err_alloc_stats:
3052 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02003053err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02003054 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3055 return err;
3056}
3057
Ido Schimmel5b153852017-06-08 08:47:44 +02003058static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003059{
3060 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3061
Nogah Frankel9deef432017-10-26 10:55:32 +02003062 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02003063 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003064 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02003065 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003066 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003067 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003068 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003069 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01003070 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02003071 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003072 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01003073 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02003074 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003075 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02003076 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3077}
3078
Jiri Pirkof83e2102016-10-28 21:35:49 +02003079static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3080{
3081 return mlxsw_sp->ports[local_port] != NULL;
3082}
3083
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003084static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3085{
3086 int i;
3087
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003088 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003089 if (mlxsw_sp_port_created(mlxsw_sp, i))
3090 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003091 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003092 kfree(mlxsw_sp->ports);
3093}
3094
3095static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3096{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003097 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02003098 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003099 size_t alloc_size;
3100 int i;
3101 int err;
3102
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003103 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003104 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3105 if (!mlxsw_sp->ports)
3106 return -ENOMEM;
3107
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003108 mlxsw_sp->port_to_module = kcalloc(max_ports, sizeof(u8), GFP_KERNEL);
3109 if (!mlxsw_sp->port_to_module) {
3110 err = -ENOMEM;
3111 goto err_port_to_module_alloc;
3112 }
3113
3114 for (i = 1; i < max_ports; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01003115 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003116 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003117 if (err)
3118 goto err_port_module_info_get;
3119 if (!width)
3120 continue;
3121 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003122 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3123 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003124 if (err)
3125 goto err_port_create;
3126 }
3127 return 0;
3128
3129err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003130err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003131 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003132 if (mlxsw_sp_port_created(mlxsw_sp, i))
3133 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003134 kfree(mlxsw_sp->port_to_module);
3135err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003136 kfree(mlxsw_sp->ports);
3137 return err;
3138}
3139
Ido Schimmel18f1e702016-02-26 17:32:31 +01003140static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3141{
3142 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3143
3144 return local_port - offset;
3145}
3146
Ido Schimmelbe945352016-06-09 09:51:39 +02003147static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3148 u8 module, unsigned int count)
3149{
3150 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3151 int err, i;
3152
3153 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003154 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003155 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003156 if (err)
3157 goto err_port_create;
3158 }
3159
3160 return 0;
3161
3162err_port_create:
3163 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003164 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3165 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003166 return err;
3167}
3168
3169static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3170 u8 base_port, unsigned int count)
3171{
3172 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3173 int i;
3174
3175 /* Split by four means we need to re-create two ports, otherwise
3176 * only one.
3177 */
3178 count = count / 2;
3179
3180 for (i = 0; i < count; i++) {
3181 local_port = base_port + i * 2;
3182 module = mlxsw_sp->port_to_module[local_port];
3183
Ido Schimmelbe945352016-06-09 09:51:39 +02003184 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003185 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003186 }
3187}
3188
Jiri Pirkob2f10572016-04-08 19:11:23 +02003189static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3190 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003191{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003192 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003193 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003194 u8 module, cur_width, base_port;
3195 int i;
3196 int err;
3197
3198 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3199 if (!mlxsw_sp_port) {
3200 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3201 local_port);
3202 return -EINVAL;
3203 }
3204
Ido Schimmeld664b412016-06-09 09:51:40 +02003205 module = mlxsw_sp_port->mapping.module;
3206 cur_width = mlxsw_sp_port->mapping.width;
3207
Ido Schimmel18f1e702016-02-26 17:32:31 +01003208 if (count != 2 && count != 4) {
3209 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3210 return -EINVAL;
3211 }
3212
Ido Schimmel18f1e702016-02-26 17:32:31 +01003213 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3214 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3215 return -EINVAL;
3216 }
3217
3218 /* Make sure we have enough slave (even) ports for the split. */
3219 if (count == 2) {
3220 base_port = local_port;
3221 if (mlxsw_sp->ports[base_port + 1]) {
3222 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3223 return -EINVAL;
3224 }
3225 } else {
3226 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3227 if (mlxsw_sp->ports[base_port + 1] ||
3228 mlxsw_sp->ports[base_port + 3]) {
3229 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3230 return -EINVAL;
3231 }
3232 }
3233
3234 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003235 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3236 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003237
Ido Schimmelbe945352016-06-09 09:51:39 +02003238 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3239 if (err) {
3240 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3241 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003242 }
3243
3244 return 0;
3245
Ido Schimmelbe945352016-06-09 09:51:39 +02003246err_port_split_create:
3247 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003248 return err;
3249}
3250
Jiri Pirkob2f10572016-04-08 19:11:23 +02003251static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003252{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003253 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003254 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003255 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003256 unsigned int count;
3257 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003258
3259 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3260 if (!mlxsw_sp_port) {
3261 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3262 local_port);
3263 return -EINVAL;
3264 }
3265
3266 if (!mlxsw_sp_port->split) {
3267 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3268 return -EINVAL;
3269 }
3270
Ido Schimmeld664b412016-06-09 09:51:40 +02003271 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003272 count = cur_width == 1 ? 4 : 2;
3273
3274 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3275
3276 /* Determine which ports to remove. */
3277 if (count == 2 && local_port >= base_port + 2)
3278 base_port = base_port + 2;
3279
3280 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003281 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3282 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003283
Ido Schimmelbe945352016-06-09 09:51:39 +02003284 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003285
3286 return 0;
3287}
3288
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003289static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3290 char *pude_pl, void *priv)
3291{
3292 struct mlxsw_sp *mlxsw_sp = priv;
3293 struct mlxsw_sp_port *mlxsw_sp_port;
3294 enum mlxsw_reg_pude_oper_status status;
3295 u8 local_port;
3296
3297 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3298 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003299 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003300 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003301
3302 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3303 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3304 netdev_info(mlxsw_sp_port->dev, "link up\n");
3305 netif_carrier_on(mlxsw_sp_port->dev);
3306 } else {
3307 netdev_info(mlxsw_sp_port->dev, "link down\n");
3308 netif_carrier_off(mlxsw_sp_port->dev);
3309 }
3310}
3311
Nogah Frankel14eeda92016-11-25 10:33:32 +01003312static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3313 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003314{
3315 struct mlxsw_sp *mlxsw_sp = priv;
3316 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3317 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3318
3319 if (unlikely(!mlxsw_sp_port)) {
3320 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3321 local_port);
3322 return;
3323 }
3324
3325 skb->dev = mlxsw_sp_port->dev;
3326
3327 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3328 u64_stats_update_begin(&pcpu_stats->syncp);
3329 pcpu_stats->rx_packets++;
3330 pcpu_stats->rx_bytes += skb->len;
3331 u64_stats_update_end(&pcpu_stats->syncp);
3332
3333 skb->protocol = eth_type_trans(skb, skb->dev);
3334 netif_receive_skb(skb);
3335}
3336
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003337static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3338 void *priv)
3339{
3340 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003341 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003342}
3343
Yotam Gigia0040c82017-10-03 09:58:10 +02003344static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3345 u8 local_port, void *priv)
3346{
3347 skb->offload_mr_fwd_mark = 1;
3348 skb->offload_fwd_mark = 1;
3349 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3350}
3351
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003352static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3353 void *priv)
3354{
3355 struct mlxsw_sp *mlxsw_sp = priv;
3356 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3357 struct psample_group *psample_group;
3358 u32 size;
3359
3360 if (unlikely(!mlxsw_sp_port)) {
3361 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3362 local_port);
3363 goto out;
3364 }
3365 if (unlikely(!mlxsw_sp_port->sample)) {
3366 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3367 local_port);
3368 goto out;
3369 }
3370
3371 size = mlxsw_sp_port->sample->truncate ?
3372 mlxsw_sp_port->sample->trunc_size : skb->len;
3373
3374 rcu_read_lock();
3375 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3376 if (!psample_group)
3377 goto out_unlock;
3378 psample_sample_packet(psample_group, skb, size,
3379 mlxsw_sp_port->dev->ifindex, 0,
3380 mlxsw_sp_port->sample->rate);
3381out_unlock:
3382 rcu_read_unlock();
3383out:
3384 consume_skb(skb);
3385}
3386
Nogah Frankel117b0da2016-11-25 10:33:44 +01003387#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003388 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003389 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003390
Nogah Frankel117b0da2016-11-25 10:33:44 +01003391#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003392 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003393 _is_ctrl, SP_##_trap_group, DISCARD)
3394
Yotam Gigia0040c82017-10-03 09:58:10 +02003395#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3396 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3397 _is_ctrl, SP_##_trap_group, DISCARD)
3398
Nogah Frankel117b0da2016-11-25 10:33:44 +01003399#define MLXSW_SP_EVENTL(_func, _trap_id) \
3400 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003401
Nogah Frankel45449132016-11-25 10:33:35 +01003402static const struct mlxsw_listener mlxsw_sp_listener[] = {
3403 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003404 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003405 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003406 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3407 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3408 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3409 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3410 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3411 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3412 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3413 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3414 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3415 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3416 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003417 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003418 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3419 false),
3420 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3421 false),
3422 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3423 false),
3424 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3425 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003426 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003427 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3428 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3429 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003430 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003431 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3432 false),
3433 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3434 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3435 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3436 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3437 false),
3438 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3439 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3440 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003441 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003442 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3443 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3444 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3445 false),
3446 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3447 false),
3448 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3449 false),
3450 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3451 false),
3452 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3453 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3454 false),
3455 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3456 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003457 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003458 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003459 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003460 /* PKT Sample trap */
3461 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003462 false, SP_IP2ME, DISCARD),
3463 /* ACL trap */
3464 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003465 /* Multicast Router Traps */
3466 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3467 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3468 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Yotam Gigia0040c82017-10-03 09:58:10 +02003469 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003470};
3471
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003472static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3473{
3474 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3475 enum mlxsw_reg_qpcr_ir_units ir_units;
3476 int max_cpu_policers;
3477 bool is_bytes;
3478 u8 burst_size;
3479 u32 rate;
3480 int i, err;
3481
3482 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3483 return -EIO;
3484
3485 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3486
3487 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3488 for (i = 0; i < max_cpu_policers; i++) {
3489 is_bytes = false;
3490 switch (i) {
3491 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3492 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3493 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3494 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003495 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3496 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003497 rate = 128;
3498 burst_size = 7;
3499 break;
3500 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003501 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003502 rate = 16 * 1024;
3503 burst_size = 10;
3504 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003505 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003506 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3507 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003508 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003509 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3510 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003511 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003512 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003513 rate = 1024;
3514 burst_size = 7;
3515 break;
3516 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3517 is_bytes = true;
3518 rate = 4 * 1024;
3519 burst_size = 4;
3520 break;
3521 default:
3522 continue;
3523 }
3524
3525 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3526 burst_size);
3527 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3528 if (err)
3529 return err;
3530 }
3531
3532 return 0;
3533}
3534
Nogah Frankel579c82e2016-11-25 10:33:42 +01003535static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003536{
3537 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003538 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003539 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003540 int max_trap_groups;
3541 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003542 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003543 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003544
3545 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3546 return -EIO;
3547
3548 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003549 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003550
3551 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003552 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003553 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003554 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3555 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3556 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3557 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003558 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003559 priority = 5;
3560 tc = 5;
3561 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003562 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003563 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3564 priority = 4;
3565 tc = 4;
3566 break;
3567 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3568 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003569 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003570 priority = 3;
3571 tc = 3;
3572 break;
3573 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003574 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003575 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003576 priority = 2;
3577 tc = 2;
3578 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003579 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003580 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3581 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003582 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003583 priority = 1;
3584 tc = 1;
3585 break;
3586 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003587 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3588 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003589 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003590 break;
3591 default:
3592 continue;
3593 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003594
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003595 if (max_cpu_policers <= policer_id &&
3596 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3597 return -EIO;
3598
3599 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003600 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3601 if (err)
3602 return err;
3603 }
3604
3605 return 0;
3606}
3607
3608static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3609{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003610 int i;
3611 int err;
3612
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003613 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3614 if (err)
3615 return err;
3616
Nogah Frankel579c82e2016-11-25 10:33:42 +01003617 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003618 if (err)
3619 return err;
3620
Nogah Frankel45449132016-11-25 10:33:35 +01003621 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003622 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003623 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003624 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003625 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003626 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003627
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003628 }
3629 return 0;
3630
Nogah Frankel45449132016-11-25 10:33:35 +01003631err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003632 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003633 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003634 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003635 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003636 }
3637 return err;
3638}
3639
3640static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3641{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003642 int i;
3643
Nogah Frankel45449132016-11-25 10:33:35 +01003644 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003645 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003646 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003647 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003648 }
3649}
3650
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003651static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3652{
3653 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003654 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003655
3656 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3657 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3658 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3659 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3660 MLXSW_REG_SLCR_LAG_HASH_SIP |
3661 MLXSW_REG_SLCR_LAG_HASH_DIP |
3662 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3663 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3664 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003665 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3666 if (err)
3667 return err;
3668
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003669 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3670 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003671 return -EIO;
3672
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003673 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003674 sizeof(struct mlxsw_sp_upper),
3675 GFP_KERNEL);
3676 if (!mlxsw_sp->lags)
3677 return -ENOMEM;
3678
3679 return 0;
3680}
3681
3682static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3683{
3684 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003685}
3686
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003687static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3688{
3689 char htgt_pl[MLXSW_REG_HTGT_LEN];
3690
Nogah Frankel579c82e2016-11-25 10:33:42 +01003691 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3692 MLXSW_REG_HTGT_INVALID_POLICER,
3693 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3694 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003695 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3696}
3697
Petr Machatac30f5d02017-10-16 16:26:35 +02003698static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3699 unsigned long event, void *ptr);
3700
Jiri Pirkob2f10572016-04-08 19:11:23 +02003701static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003702 const struct mlxsw_bus_info *mlxsw_bus_info)
3703{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003704 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003705 int err;
3706
3707 mlxsw_sp->core = mlxsw_core;
3708 mlxsw_sp->bus_info = mlxsw_bus_info;
3709
Yotam Gigi6b742192017-05-23 21:56:29 +02003710 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3711 if (err) {
3712 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3713 return err;
3714 }
3715
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003716 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3717 if (err) {
3718 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3719 return err;
3720 }
3721
Ido Schimmela875a2e2017-10-22 23:11:44 +02003722 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3723 if (err) {
3724 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3725 return err;
3726 }
3727
Ido Schimmela1107482017-05-26 08:37:39 +02003728 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003729 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003730 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Ido Schimmela875a2e2017-10-22 23:11:44 +02003731 goto err_fids_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003732 }
3733
Ido Schimmela1107482017-05-26 08:37:39 +02003734 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003735 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003736 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3737 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003738 }
3739
3740 err = mlxsw_sp_buffers_init(mlxsw_sp);
3741 if (err) {
3742 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3743 goto err_buffers_init;
3744 }
3745
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003746 err = mlxsw_sp_lag_init(mlxsw_sp);
3747 if (err) {
3748 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3749 goto err_lag_init;
3750 }
3751
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003752 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3753 if (err) {
3754 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3755 goto err_switchdev_init;
3756 }
3757
Yotam Gigie2b2d352017-09-19 10:00:08 +02003758 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3759 if (err) {
3760 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3761 goto err_counter_pool_init;
3762 }
3763
Yotam Gigid3b939b2017-09-19 10:00:09 +02003764 err = mlxsw_sp_afa_init(mlxsw_sp);
3765 if (err) {
3766 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3767 goto err_afa_init;
3768 }
3769
Ido Schimmel464dce12016-07-02 11:00:15 +02003770 err = mlxsw_sp_router_init(mlxsw_sp);
3771 if (err) {
3772 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3773 goto err_router_init;
3774 }
3775
Petr Machatac30f5d02017-10-16 16:26:35 +02003776 /* Initialize netdevice notifier after router is initialized, so that
3777 * the event handler can use router structures.
3778 */
3779 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3780 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3781 if (err) {
3782 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3783 goto err_netdev_notifier;
3784 }
3785
Yotam Gigi763b4b72016-07-21 12:03:17 +02003786 err = mlxsw_sp_span_init(mlxsw_sp);
3787 if (err) {
3788 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3789 goto err_span_init;
3790 }
3791
Jiri Pirko22a67762017-02-03 10:29:07 +01003792 err = mlxsw_sp_acl_init(mlxsw_sp);
3793 if (err) {
3794 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3795 goto err_acl_init;
3796 }
3797
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003798 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3799 if (err) {
3800 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3801 goto err_dpipe_init;
3802 }
3803
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003804 err = mlxsw_sp_ports_create(mlxsw_sp);
3805 if (err) {
3806 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3807 goto err_ports_create;
3808 }
3809
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003810 return 0;
3811
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003812err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003813 mlxsw_sp_dpipe_fini(mlxsw_sp);
3814err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003815 mlxsw_sp_acl_fini(mlxsw_sp);
3816err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02003817 mlxsw_sp_span_fini(mlxsw_sp);
3818err_span_init:
Petr Machatac30f5d02017-10-16 16:26:35 +02003819 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3820err_netdev_notifier:
Ido Schimmel464dce12016-07-02 11:00:15 +02003821 mlxsw_sp_router_fini(mlxsw_sp);
3822err_router_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02003823 mlxsw_sp_afa_fini(mlxsw_sp);
3824err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02003825 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3826err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003827 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003828err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003829 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003830err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003831 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003832err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003833 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003834err_traps_init:
3835 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003836err_fids_init:
3837 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003838 return err;
3839}
3840
Jiri Pirkob2f10572016-04-08 19:11:23 +02003841static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003842{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003843 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003844
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003845 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003846 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003847 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003848 mlxsw_sp_span_fini(mlxsw_sp);
Petr Machatac30f5d02017-10-16 16:26:35 +02003849 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
Ido Schimmel464dce12016-07-02 11:00:15 +02003850 mlxsw_sp_router_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02003851 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02003852 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003853 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003854 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003855 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003856 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003857 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003858 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003859}
3860
Bhumika Goyal159fe882017-08-11 19:10:42 +05303861static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003862 .used_max_vepa_channels = 1,
3863 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003864 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003865 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003866 .used_max_pgt = 1,
3867 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003868 .used_flood_tables = 1,
3869 .used_flood_mode = 1,
3870 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003871 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003872 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003873 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02003874 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003875 .used_max_ib_mc = 1,
3876 .max_ib_mc = 0,
3877 .used_max_pkey = 1,
3878 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003879 .used_kvd_split_data = 1,
3880 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
Ido Schimmelf11fbaf2017-10-22 23:11:49 +02003881 .kvd_hash_single_parts = 59,
3882 .kvd_hash_double_parts = 41,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003883 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003884 .swid_config = {
3885 {
3886 .used_type = 1,
3887 .type = MLXSW_PORT_SWID_TYPE_ETH,
3888 }
3889 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003890 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003891};
3892
3893static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003894 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003895 .priv_size = sizeof(struct mlxsw_sp),
3896 .init = mlxsw_sp_init,
3897 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003898 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003899 .port_split = mlxsw_sp_port_split,
3900 .port_unsplit = mlxsw_sp_port_unsplit,
3901 .sb_pool_get = mlxsw_sp_sb_pool_get,
3902 .sb_pool_set = mlxsw_sp_sb_pool_set,
3903 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3904 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3905 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3906 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3907 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3908 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3909 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3910 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3911 .txhdr_construct = mlxsw_sp_txhdr_construct,
3912 .txhdr_len = MLXSW_TXHDR_LEN,
3913 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003914};
3915
Jiri Pirko22a67762017-02-03 10:29:07 +01003916bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003917{
3918 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3919}
3920
Jiri Pirko1182e532017-03-06 21:25:20 +01003921static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07003922{
Jiri Pirko1182e532017-03-06 21:25:20 +01003923 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07003924 int ret = 0;
3925
3926 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01003927 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07003928 ret = 1;
3929 }
3930
3931 return ret;
3932}
3933
Ido Schimmelc57529e2017-05-26 08:37:31 +02003934struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003935{
Jiri Pirko1182e532017-03-06 21:25:20 +01003936 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003937
3938 if (mlxsw_sp_port_dev_check(dev))
3939 return netdev_priv(dev);
3940
Jiri Pirko1182e532017-03-06 21:25:20 +01003941 mlxsw_sp_port = NULL;
3942 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003943
Jiri Pirko1182e532017-03-06 21:25:20 +01003944 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003945}
3946
Ido Schimmel4724ba562017-03-10 08:53:39 +01003947struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003948{
3949 struct mlxsw_sp_port *mlxsw_sp_port;
3950
3951 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3952 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3953}
3954
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02003955struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003956{
Jiri Pirko1182e532017-03-06 21:25:20 +01003957 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003958
3959 if (mlxsw_sp_port_dev_check(dev))
3960 return netdev_priv(dev);
3961
Jiri Pirko1182e532017-03-06 21:25:20 +01003962 mlxsw_sp_port = NULL;
3963 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
3964 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003965
Jiri Pirko1182e532017-03-06 21:25:20 +01003966 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003967}
3968
3969struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3970{
3971 struct mlxsw_sp_port *mlxsw_sp_port;
3972
3973 rcu_read_lock();
3974 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3975 if (mlxsw_sp_port)
3976 dev_hold(mlxsw_sp_port->dev);
3977 rcu_read_unlock();
3978 return mlxsw_sp_port;
3979}
3980
3981void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3982{
3983 dev_put(mlxsw_sp_port->dev);
3984}
3985
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003986static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003987{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003988 char sldr_pl[MLXSW_REG_SLDR_LEN];
3989
3990 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3991 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3992}
3993
3994static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3995{
3996 char sldr_pl[MLXSW_REG_SLDR_LEN];
3997
3998 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3999 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4000}
4001
4002static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4003 u16 lag_id, u8 port_index)
4004{
4005 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4006 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4007
4008 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4009 lag_id, port_index);
4010 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4011}
4012
4013static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4014 u16 lag_id)
4015{
4016 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4017 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4018
4019 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4020 lag_id);
4021 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4022}
4023
4024static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4025 u16 lag_id)
4026{
4027 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4028 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4029
4030 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4031 lag_id);
4032 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4033}
4034
4035static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4036 u16 lag_id)
4037{
4038 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4039 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4040
4041 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4042 lag_id);
4043 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4044}
4045
4046static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4047 struct net_device *lag_dev,
4048 u16 *p_lag_id)
4049{
4050 struct mlxsw_sp_upper *lag;
4051 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004052 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004053 int i;
4054
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004055 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4056 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004057 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4058 if (lag->ref_count) {
4059 if (lag->dev == lag_dev) {
4060 *p_lag_id = i;
4061 return 0;
4062 }
4063 } else if (free_lag_id < 0) {
4064 free_lag_id = i;
4065 }
4066 }
4067 if (free_lag_id < 0)
4068 return -EBUSY;
4069 *p_lag_id = free_lag_id;
4070 return 0;
4071}
4072
4073static bool
4074mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4075 struct net_device *lag_dev,
David Aherne58376e2017-10-04 17:48:51 -07004076 struct netdev_lag_upper_info *lag_upper_info,
4077 struct netlink_ext_ack *extack)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004078{
4079 u16 lag_id;
4080
David Aherne58376e2017-10-04 17:48:51 -07004081 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4082 NL_SET_ERR_MSG(extack,
4083 "spectrum: Exceeded number of supported LAG devices");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004084 return false;
David Aherne58376e2017-10-04 17:48:51 -07004085 }
4086 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4087 NL_SET_ERR_MSG(extack,
4088 "spectrum: LAG device using unsupported Tx type");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004089 return false;
David Aherne58376e2017-10-04 17:48:51 -07004090 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004091 return true;
4092}
4093
4094static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4095 u16 lag_id, u8 *p_port_index)
4096{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004097 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004098 int i;
4099
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004100 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4101 MAX_LAG_MEMBERS);
4102 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004103 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4104 *p_port_index = i;
4105 return 0;
4106 }
4107 }
4108 return -EBUSY;
4109}
4110
4111static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4112 struct net_device *lag_dev)
4113{
4114 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004115 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004116 struct mlxsw_sp_upper *lag;
4117 u16 lag_id;
4118 u8 port_index;
4119 int err;
4120
4121 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4122 if (err)
4123 return err;
4124 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4125 if (!lag->ref_count) {
4126 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4127 if (err)
4128 return err;
4129 lag->dev = lag_dev;
4130 }
4131
4132 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4133 if (err)
4134 return err;
4135 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4136 if (err)
4137 goto err_col_port_add;
4138 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4139 if (err)
4140 goto err_col_port_enable;
4141
4142 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4143 mlxsw_sp_port->local_port);
4144 mlxsw_sp_port->lag_id = lag_id;
4145 mlxsw_sp_port->lagged = 1;
4146 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004147
Ido Schimmelc57529e2017-05-26 08:37:31 +02004148 /* Port is no longer usable as a router interface */
4149 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4150 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004151 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004152
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004153 return 0;
4154
Ido Schimmel51554db2016-05-06 22:18:39 +02004155err_col_port_enable:
4156 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004157err_col_port_add:
4158 if (!lag->ref_count)
4159 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004160 return err;
4161}
4162
Ido Schimmel82e6db02016-06-20 23:04:04 +02004163static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4164 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004165{
4166 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004167 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004168 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004169
4170 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004171 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004172 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4173 WARN_ON(lag->ref_count == 0);
4174
Ido Schimmel82e6db02016-06-20 23:04:04 +02004175 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4176 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004177
Ido Schimmelc57529e2017-05-26 08:37:31 +02004178 /* Any VLANs configured on the port are no longer valid */
4179 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004180
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004181 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004182 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004183
4184 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4185 mlxsw_sp_port->local_port);
4186 mlxsw_sp_port->lagged = 0;
4187 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004188
Ido Schimmelc57529e2017-05-26 08:37:31 +02004189 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4190 /* Make sure untagged frames are allowed to ingress */
4191 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004192}
4193
Jiri Pirko74581202015-12-03 12:12:30 +01004194static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4195 u16 lag_id)
4196{
4197 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4198 char sldr_pl[MLXSW_REG_SLDR_LEN];
4199
4200 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4201 mlxsw_sp_port->local_port);
4202 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4203}
4204
4205static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4206 u16 lag_id)
4207{
4208 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4209 char sldr_pl[MLXSW_REG_SLDR_LEN];
4210
4211 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4212 mlxsw_sp_port->local_port);
4213 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4214}
4215
4216static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4217 bool lag_tx_enabled)
4218{
4219 if (lag_tx_enabled)
4220 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4221 mlxsw_sp_port->lag_id);
4222 else
4223 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4224 mlxsw_sp_port->lag_id);
4225}
4226
4227static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4228 struct netdev_lag_lower_state_info *info)
4229{
4230 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4231}
4232
Jiri Pirko2b94e582017-04-18 16:55:37 +02004233static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4234 bool enable)
4235{
4236 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4237 enum mlxsw_reg_spms_state spms_state;
4238 char *spms_pl;
4239 u16 vid;
4240 int err;
4241
4242 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4243 MLXSW_REG_SPMS_STATE_DISCARDING;
4244
4245 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4246 if (!spms_pl)
4247 return -ENOMEM;
4248 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4249
4250 for (vid = 0; vid < VLAN_N_VID; vid++)
4251 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4252
4253 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4254 kfree(spms_pl);
4255 return err;
4256}
4257
4258static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4259{
4260 int err;
4261
Ido Schimmel4aafc362017-05-26 08:37:25 +02004262 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004263 if (err)
4264 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004265 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4266 if (err)
4267 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004268 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4269 true, false);
4270 if (err)
4271 goto err_port_vlan_set;
4272 return 0;
4273
4274err_port_vlan_set:
4275 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004276err_port_stp_set:
4277 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004278 return err;
4279}
4280
4281static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4282{
4283 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4284 false, false);
4285 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004286 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004287}
4288
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004289static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4290 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004291 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004292{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004293 struct netdev_notifier_changeupper_info *info;
4294 struct mlxsw_sp_port *mlxsw_sp_port;
David Aherne58376e2017-10-04 17:48:51 -07004295 struct netlink_ext_ack *extack;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004296 struct net_device *upper_dev;
4297 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004298 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004299
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004300 mlxsw_sp_port = netdev_priv(dev);
4301 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4302 info = ptr;
David Aherne58376e2017-10-04 17:48:51 -07004303 extack = netdev_notifier_info_to_extack(&info->info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004304
4305 switch (event) {
4306 case NETDEV_PRECHANGEUPPER:
4307 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004308 if (!is_vlan_dev(upper_dev) &&
4309 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004310 !netif_is_bridge_master(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004311 !netif_is_ovs_master(upper_dev)) {
4312 NL_SET_ERR_MSG(extack,
4313 "spectrum: Unknown upper device type");
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004314 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004315 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004316 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004317 break;
David Aherne58376e2017-10-04 17:48:51 -07004318 if (netdev_has_any_upper_dev(upper_dev)) {
4319 NL_SET_ERR_MSG(extack,
4320 "spectrum: Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004321 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004322 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004323 if (netif_is_lag_master(upper_dev) &&
4324 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
David Aherne58376e2017-10-04 17:48:51 -07004325 info->upper_info, extack))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004326 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004327 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4328 NL_SET_ERR_MSG(extack,
4329 "spectrum: Master device is a LAG master and this device has a VLAN");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004330 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004331 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004332 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004333 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4334 NL_SET_ERR_MSG(extack,
4335 "spectrum: Can not put a VLAN on a LAG port");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004336 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004337 }
4338 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4339 NL_SET_ERR_MSG(extack,
4340 "spectrum: Master device is an OVS master and this device has a VLAN");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004341 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004342 }
4343 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4344 NL_SET_ERR_MSG(extack,
4345 "spectrum: Can not put a VLAN on an OVS port");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004346 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004347 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004348 break;
4349 case NETDEV_CHANGEUPPER:
4350 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004351 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004352 if (info->linking)
4353 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004354 lower_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004355 upper_dev,
4356 extack);
Ido Schimmel7117a572016-06-20 23:04:06 +02004357 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004358 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4359 lower_dev,
4360 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004361 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004362 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004363 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4364 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004365 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004366 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4367 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004368 } else if (netif_is_ovs_master(upper_dev)) {
4369 if (info->linking)
4370 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4371 else
4372 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004373 }
4374 break;
4375 }
4376
Ido Schimmel80bedf12016-06-20 23:03:59 +02004377 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004378}
4379
Jiri Pirko74581202015-12-03 12:12:30 +01004380static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4381 unsigned long event, void *ptr)
4382{
4383 struct netdev_notifier_changelowerstate_info *info;
4384 struct mlxsw_sp_port *mlxsw_sp_port;
4385 int err;
4386
4387 mlxsw_sp_port = netdev_priv(dev);
4388 info = ptr;
4389
4390 switch (event) {
4391 case NETDEV_CHANGELOWERSTATE:
4392 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4393 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4394 info->lower_state_info);
4395 if (err)
4396 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4397 }
4398 break;
4399 }
4400
Ido Schimmel80bedf12016-06-20 23:03:59 +02004401 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004402}
4403
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004404static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4405 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004406 unsigned long event, void *ptr)
4407{
4408 switch (event) {
4409 case NETDEV_PRECHANGEUPPER:
4410 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004411 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4412 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004413 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004414 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4415 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004416 }
4417
Ido Schimmel80bedf12016-06-20 23:03:59 +02004418 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004419}
4420
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004421static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4422 unsigned long event, void *ptr)
4423{
4424 struct net_device *dev;
4425 struct list_head *iter;
4426 int ret;
4427
4428 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4429 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004430 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4431 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004432 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004433 return ret;
4434 }
4435 }
4436
Ido Schimmel80bedf12016-06-20 23:03:59 +02004437 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004438}
4439
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004440static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4441 struct net_device *dev,
4442 unsigned long event, void *ptr,
4443 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004444{
4445 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4446 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004447 struct netlink_ext_ack *extack;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004448 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004449 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004450
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004451 extack = netdev_notifier_info_to_extack(&info->info);
4452
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004453 switch (event) {
4454 case NETDEV_PRECHANGEUPPER:
4455 upper_dev = info->upper_dev;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004456 if (!netif_is_bridge_master(upper_dev)) {
4457 NL_SET_ERR_MSG(extack, "spectrum: VLAN devices only support bridge and VRF uppers");
Ido Schimmel80bedf12016-06-20 23:03:59 +02004458 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004459 }
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004460 if (!info->linking)
4461 break;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004462 if (netdev_has_any_upper_dev(upper_dev)) {
4463 NL_SET_ERR_MSG(extack, "spectrum: Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004464 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004465 }
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004466 break;
4467 case NETDEV_CHANGEUPPER:
4468 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004469 if (netif_is_bridge_master(upper_dev)) {
4470 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004471 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4472 vlan_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004473 upper_dev,
4474 extack);
Ido Schimmel1f880612017-03-10 08:53:35 +01004475 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004476 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4477 vlan_dev,
4478 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004479 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004480 err = -EINVAL;
4481 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004482 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004483 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004484 }
4485
Ido Schimmel80bedf12016-06-20 23:03:59 +02004486 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004487}
4488
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004489static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4490 struct net_device *lag_dev,
4491 unsigned long event,
4492 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004493{
4494 struct net_device *dev;
4495 struct list_head *iter;
4496 int ret;
4497
4498 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4499 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004500 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4501 event, ptr,
4502 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004503 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004504 return ret;
4505 }
4506 }
4507
Ido Schimmel80bedf12016-06-20 23:03:59 +02004508 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004509}
4510
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004511static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4512 unsigned long event, void *ptr)
4513{
4514 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4515 u16 vid = vlan_dev_vlan_id(vlan_dev);
4516
Ido Schimmel272c4472015-12-15 16:03:47 +01004517 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004518 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4519 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01004520 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004521 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4522 real_dev, event,
4523 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004524
Ido Schimmel80bedf12016-06-20 23:03:59 +02004525 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004526}
4527
Ido Schimmelb1e45522017-04-30 19:47:14 +03004528static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4529{
4530 struct netdev_notifier_changeupper_info *info = ptr;
4531
4532 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4533 return false;
4534 return netif_is_l3_master(info->upper_dev);
4535}
4536
Petr Machata00635872017-10-16 16:26:37 +02004537static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004538 unsigned long event, void *ptr)
4539{
4540 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Petr Machata00635872017-10-16 16:26:37 +02004541 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004542 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004543
Petr Machata00635872017-10-16 16:26:37 +02004544 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
Petr Machata796ec772017-11-03 10:03:29 +01004545 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4546 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4547 event, ptr);
Petr Machata61481f22017-11-03 10:03:41 +01004548 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4549 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4550 event, ptr);
Petr Machata00635872017-10-16 16:26:37 +02004551 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004552 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004553 else if (mlxsw_sp_is_vrf_event(event, ptr))
4554 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004555 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004556 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004557 else if (netif_is_lag_master(dev))
4558 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4559 else if (is_vlan_dev(dev))
4560 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004561
Ido Schimmel80bedf12016-06-20 23:03:59 +02004562 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004563}
4564
David Ahern89d5dd22017-10-18 09:56:55 -07004565static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
4566 .notifier_call = mlxsw_sp_inetaddr_valid_event,
4567};
4568
Ido Schimmel99724c12016-07-04 08:23:14 +02004569static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4570 .notifier_call = mlxsw_sp_inetaddr_event,
David Ahern89d5dd22017-10-18 09:56:55 -07004571};
4572
4573static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4574 .notifier_call = mlxsw_sp_inet6addr_valid_event,
Ido Schimmel99724c12016-07-04 08:23:14 +02004575};
4576
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004577static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4578 .notifier_call = mlxsw_sp_inet6addr_event,
4579};
4580
Jiri Pirko1d20d232016-10-27 15:12:59 +02004581static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4582 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4583 {0, },
4584};
4585
4586static struct pci_driver mlxsw_sp_pci_driver = {
4587 .name = mlxsw_sp_driver_name,
4588 .id_table = mlxsw_sp_pci_id_table,
4589};
4590
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004591static int __init mlxsw_sp_module_init(void)
4592{
4593 int err;
4594
David Ahern89d5dd22017-10-18 09:56:55 -07004595 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004596 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004597 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004598 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004599
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004600 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4601 if (err)
4602 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004603
4604 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4605 if (err)
4606 goto err_pci_driver_register;
4607
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004608 return 0;
4609
Jiri Pirko1d20d232016-10-27 15:12:59 +02004610err_pci_driver_register:
4611 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004612err_core_driver_register:
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004613 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004614 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004615 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004616 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004617 return err;
4618}
4619
4620static void __exit mlxsw_sp_module_exit(void)
4621{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004622 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004623 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004624 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004625 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004626 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004627 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004628}
4629
4630module_init(mlxsw_sp_module_init);
4631module_exit(mlxsw_sp_module_exit);
4632
4633MODULE_LICENSE("Dual BSD/GPL");
4634MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4635MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004636MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02004637MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);