blob: e9b94430afed6e541fe65172100a121cf1d0d729 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020056#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020057#include <net/pkt_cls.h>
58#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020059#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010060#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020061#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020062
63#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020064#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020065#include "core.h"
66#include "reg.h"
67#include "port.h"
68#include "trap.h"
69#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010070#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020071#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020072#include "spectrum_acl_flex_actions.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020073#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020074
Yotam Gigi6b742192017-05-23 21:56:29 +020075#define MLXSW_FWREV_MAJOR 13
76#define MLXSW_FWREV_MINOR 1420
77#define MLXSW_FWREV_SUBMINOR 122
78
79static const struct mlxsw_fw_rev mlxsw_sp_supported_fw_rev = {
80 .major = MLXSW_FWREV_MAJOR,
81 .minor = MLXSW_FWREV_MINOR,
82 .subminor = MLXSW_FWREV_SUBMINOR
83};
84
85#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020086 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020087 "." __stringify(MLXSW_FWREV_MINOR) \
88 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
89
Jiri Pirko56ade8f2015-10-16 14:01:37 +020090static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
91static const char mlxsw_sp_driver_version[] = "1.0";
92
93/* tx_hdr_version
94 * Tx header version.
95 * Must be set to 1.
96 */
97MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
98
99/* tx_hdr_ctl
100 * Packet control type.
101 * 0 - Ethernet control (e.g. EMADs, LACP)
102 * 1 - Ethernet data
103 */
104MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
105
106/* tx_hdr_proto
107 * Packet protocol type. Must be set to 1 (Ethernet).
108 */
109MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
110
111/* tx_hdr_rx_is_router
112 * Packet is sent from the router. Valid for data packets only.
113 */
114MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
115
116/* tx_hdr_fid_valid
117 * Indicates if the 'fid' field is valid and should be used for
118 * forwarding lookup. Valid for data packets only.
119 */
120MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
121
122/* tx_hdr_swid
123 * Switch partition ID. Must be set to 0.
124 */
125MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
126
127/* tx_hdr_control_tclass
128 * Indicates if the packet should use the control TClass and not one
129 * of the data TClasses.
130 */
131MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
132
133/* tx_hdr_etclass
134 * Egress TClass to be used on the egress device on the egress port.
135 */
136MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
137
138/* tx_hdr_port_mid
139 * Destination local port for unicast packets.
140 * Destination multicast ID for multicast packets.
141 *
142 * Control packets are directed to a specific egress port, while data
143 * packets are transmitted through the CPU port (0) into the switch partition,
144 * where forwarding rules are applied.
145 */
146MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
147
148/* tx_hdr_fid
149 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
150 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
151 * Valid for data packets only.
152 */
153MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
154
155/* tx_hdr_type
156 * 0 - Data packets
157 * 6 - Control packets
158 */
159MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
160
Yotam Gigie5e5c882017-05-23 21:56:27 +0200161struct mlxsw_sp_mlxfw_dev {
162 struct mlxfw_dev mlxfw_dev;
163 struct mlxsw_sp *mlxsw_sp;
164};
165
166static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
167 u16 component_index, u32 *p_max_size,
168 u8 *p_align_bits, u16 *p_max_write_size)
169{
170 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
171 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
172 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
173 char mcqi_pl[MLXSW_REG_MCQI_LEN];
174 int err;
175
176 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
177 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
178 if (err)
179 return err;
180 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
181 p_max_write_size);
182
183 *p_align_bits = max_t(u8, *p_align_bits, 2);
184 *p_max_write_size = min_t(u16, *p_max_write_size,
185 MLXSW_REG_MCDA_MAX_DATA_LEN);
186 return 0;
187}
188
189static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
190{
191 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
192 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
193 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
194 char mcc_pl[MLXSW_REG_MCC_LEN];
195 u8 control_state;
196 int err;
197
198 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
199 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
200 if (err)
201 return err;
202
203 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
204 if (control_state != MLXFW_FSM_STATE_IDLE)
205 return -EBUSY;
206
207 mlxsw_reg_mcc_pack(mcc_pl,
208 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
209 0, *fwhandle, 0);
210 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
211}
212
213static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
214 u32 fwhandle, u16 component_index,
215 u32 component_size)
216{
217 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
218 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
219 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
220 char mcc_pl[MLXSW_REG_MCC_LEN];
221
222 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
223 component_index, fwhandle, component_size);
224 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
225}
226
227static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
228 u32 fwhandle, u8 *data, u16 size,
229 u32 offset)
230{
231 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
232 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
233 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
234 char mcda_pl[MLXSW_REG_MCDA_LEN];
235
236 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
237 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
238}
239
240static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
241 u32 fwhandle, u16 component_index)
242{
243 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
244 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
245 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
246 char mcc_pl[MLXSW_REG_MCC_LEN];
247
248 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
249 component_index, fwhandle, 0);
250 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
251}
252
253static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
254{
255 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
256 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
257 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
258 char mcc_pl[MLXSW_REG_MCC_LEN];
259
260 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
261 fwhandle, 0);
262 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
263}
264
265static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
266 enum mlxfw_fsm_state *fsm_state,
267 enum mlxfw_fsm_state_err *fsm_state_err)
268{
269 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
270 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
271 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
272 char mcc_pl[MLXSW_REG_MCC_LEN];
273 u8 control_state;
274 u8 error_code;
275 int err;
276
277 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
278 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
279 if (err)
280 return err;
281
282 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
283 *fsm_state = control_state;
284 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
285 MLXFW_FSM_STATE_ERR_MAX);
286 return 0;
287}
288
289static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
290{
291 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
292 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
293 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
294 char mcc_pl[MLXSW_REG_MCC_LEN];
295
296 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
297 fwhandle, 0);
298 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
299}
300
301static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
302{
303 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
304 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
305 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
306 char mcc_pl[MLXSW_REG_MCC_LEN];
307
308 mlxsw_reg_mcc_pack(mcc_pl,
309 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
310 fwhandle, 0);
311 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
312}
313
314static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
315 .component_query = mlxsw_sp_component_query,
316 .fsm_lock = mlxsw_sp_fsm_lock,
317 .fsm_component_update = mlxsw_sp_fsm_component_update,
318 .fsm_block_download = mlxsw_sp_fsm_block_download,
319 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
320 .fsm_activate = mlxsw_sp_fsm_activate,
321 .fsm_query_state = mlxsw_sp_fsm_query_state,
322 .fsm_cancel = mlxsw_sp_fsm_cancel,
323 .fsm_release = mlxsw_sp_fsm_release
324};
325
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300326static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
327 const struct firmware *firmware)
328{
329 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
330 .mlxfw_dev = {
331 .ops = &mlxsw_sp_mlxfw_dev_ops,
332 .psid = mlxsw_sp->bus_info->psid,
333 .psid_size = strlen(mlxsw_sp->bus_info->psid),
334 },
335 .mlxsw_sp = mlxsw_sp
336 };
337
338 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
339}
340
Yotam Gigi6b742192017-05-23 21:56:29 +0200341static bool mlxsw_sp_fw_rev_ge(const struct mlxsw_fw_rev *a,
342 const struct mlxsw_fw_rev *b)
343{
344 if (a->major != b->major)
345 return a->major > b->major;
346 if (a->minor != b->minor)
347 return a->minor > b->minor;
348 return a->subminor >= b->subminor;
349}
350
351static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
352{
353 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200354 const struct firmware *firmware;
355 int err;
356
357 if (mlxsw_sp_fw_rev_ge(rev, &mlxsw_sp_supported_fw_rev))
358 return 0;
359
360 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d out of data\n",
361 rev->major, rev->minor, rev->subminor);
362 dev_info(mlxsw_sp->bus_info->dev, "Upgrading firmware using file %s\n",
363 MLXSW_SP_FW_FILENAME);
364
365 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
366 mlxsw_sp->bus_info->dev);
367 if (err) {
368 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
369 MLXSW_SP_FW_FILENAME);
370 return err;
371 }
372
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300373 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200374 release_firmware(firmware);
375 return err;
376}
377
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100378int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
379 unsigned int counter_index, u64 *packets,
380 u64 *bytes)
381{
382 char mgpc_pl[MLXSW_REG_MGPC_LEN];
383 int err;
384
385 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200386 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100387 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
388 if (err)
389 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200390 if (packets)
391 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
392 if (bytes)
393 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100394 return 0;
395}
396
397static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
398 unsigned int counter_index)
399{
400 char mgpc_pl[MLXSW_REG_MGPC_LEN];
401
402 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200403 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100404 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
405}
406
407int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
408 unsigned int *p_counter_index)
409{
410 int err;
411
412 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
413 p_counter_index);
414 if (err)
415 return err;
416 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
417 if (err)
418 goto err_counter_clear;
419 return 0;
420
421err_counter_clear:
422 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
423 *p_counter_index);
424 return err;
425}
426
427void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
428 unsigned int counter_index)
429{
430 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
431 counter_index);
432}
433
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200434static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
435 const struct mlxsw_tx_info *tx_info)
436{
437 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
438
439 memset(txhdr, 0, MLXSW_TXHDR_LEN);
440
441 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
442 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
443 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
444 mlxsw_tx_hdr_swid_set(txhdr, 0);
445 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
446 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
447 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
448}
449
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200450int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
451 u8 state)
452{
453 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
454 enum mlxsw_reg_spms_state spms_state;
455 char *spms_pl;
456 int err;
457
458 switch (state) {
459 case BR_STATE_FORWARDING:
460 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
461 break;
462 case BR_STATE_LEARNING:
463 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
464 break;
465 case BR_STATE_LISTENING: /* fall-through */
466 case BR_STATE_DISABLED: /* fall-through */
467 case BR_STATE_BLOCKING:
468 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
469 break;
470 default:
471 BUG();
472 }
473
474 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
475 if (!spms_pl)
476 return -ENOMEM;
477 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
478 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
479
480 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
481 kfree(spms_pl);
482 return err;
483}
484
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200485static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
486{
Elad Raz5b090742016-10-28 21:35:46 +0200487 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200488 int err;
489
490 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
491 if (err)
492 return err;
493 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
494 return 0;
495}
496
Yotam Gigi763b4b72016-07-21 12:03:17 +0200497static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
498{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200499 int i;
500
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200501 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200502 return -EIO;
503
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200504 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
505 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200506 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
507 sizeof(struct mlxsw_sp_span_entry),
508 GFP_KERNEL);
509 if (!mlxsw_sp->span.entries)
510 return -ENOMEM;
511
512 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
513 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
514
515 return 0;
516}
517
518static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
519{
520 int i;
521
522 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
523 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
524
525 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
526 }
527 kfree(mlxsw_sp->span.entries);
528}
529
530static struct mlxsw_sp_span_entry *
531mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
532{
533 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
534 struct mlxsw_sp_span_entry *span_entry;
535 char mpat_pl[MLXSW_REG_MPAT_LEN];
536 u8 local_port = port->local_port;
537 int index;
538 int i;
539 int err;
540
541 /* find a free entry to use */
542 index = -1;
543 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
544 if (!mlxsw_sp->span.entries[i].used) {
545 index = i;
546 span_entry = &mlxsw_sp->span.entries[i];
547 break;
548 }
549 }
550 if (index < 0)
551 return NULL;
552
553 /* create a new port analayzer entry for local_port */
554 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
555 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
556 if (err)
557 return NULL;
558
559 span_entry->used = true;
560 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100561 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200562 span_entry->local_port = local_port;
563 return span_entry;
564}
565
566static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
567 struct mlxsw_sp_span_entry *span_entry)
568{
569 u8 local_port = span_entry->local_port;
570 char mpat_pl[MLXSW_REG_MPAT_LEN];
571 int pa_id = span_entry->id;
572
573 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
574 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
575 span_entry->used = false;
576}
577
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200578static struct mlxsw_sp_span_entry *
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200579mlxsw_sp_span_entry_find(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200580{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200581 int i;
582
583 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
584 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
585
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200586 if (curr->used && curr->local_port == local_port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200587 return curr;
588 }
589 return NULL;
590}
591
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200592static struct mlxsw_sp_span_entry
593*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200594{
595 struct mlxsw_sp_span_entry *span_entry;
596
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200597 span_entry = mlxsw_sp_span_entry_find(port->mlxsw_sp,
598 port->local_port);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200599 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100600 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200601 span_entry->ref_count++;
602 return span_entry;
603 }
604
605 return mlxsw_sp_span_entry_create(port);
606}
607
608static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
609 struct mlxsw_sp_span_entry *span_entry)
610{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100611 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200612 if (--span_entry->ref_count == 0)
613 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
614 return 0;
615}
616
617static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
618{
619 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
620 struct mlxsw_sp_span_inspected_port *p;
621 int i;
622
623 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
624 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
625
626 list_for_each_entry(p, &curr->bound_ports_list, list)
627 if (p->local_port == port->local_port &&
628 p->type == MLXSW_SP_SPAN_EGRESS)
629 return true;
630 }
631
632 return false;
633}
634
Ido Schimmel18281f22017-03-24 08:02:51 +0100635static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
636 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200637{
Ido Schimmel18281f22017-03-24 08:02:51 +0100638 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200639}
640
641static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
642{
643 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
644 char sbib_pl[MLXSW_REG_SBIB_LEN];
645 int err;
646
647 /* If port is egress mirrored, the shared buffer size should be
648 * updated according to the mtu value
649 */
650 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100651 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
652
653 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200654 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
655 if (err) {
656 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
657 return err;
658 }
659 }
660
661 return 0;
662}
663
664static struct mlxsw_sp_span_inspected_port *
665mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
666 struct mlxsw_sp_span_entry *span_entry)
667{
668 struct mlxsw_sp_span_inspected_port *p;
669
670 list_for_each_entry(p, &span_entry->bound_ports_list, list)
671 if (port->local_port == p->local_port)
672 return p;
673 return NULL;
674}
675
676static int
677mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
678 struct mlxsw_sp_span_entry *span_entry,
679 enum mlxsw_sp_span_type type)
680{
681 struct mlxsw_sp_span_inspected_port *inspected_port;
682 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
683 char mpar_pl[MLXSW_REG_MPAR_LEN];
684 char sbib_pl[MLXSW_REG_SBIB_LEN];
685 int pa_id = span_entry->id;
686 int err;
687
688 /* if it is an egress SPAN, bind a shared buffer to it */
689 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100690 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
691 port->dev->mtu);
692
693 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200694 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
695 if (err) {
696 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
697 return err;
698 }
699 }
700
701 /* bind the port to the SPAN entry */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200702 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
703 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200704 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
705 if (err)
706 goto err_mpar_reg_write;
707
708 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
709 if (!inspected_port) {
710 err = -ENOMEM;
711 goto err_inspected_port_alloc;
712 }
713 inspected_port->local_port = port->local_port;
714 inspected_port->type = type;
715 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
716
717 return 0;
718
719err_mpar_reg_write:
720err_inspected_port_alloc:
721 if (type == MLXSW_SP_SPAN_EGRESS) {
722 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
723 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
724 }
725 return err;
726}
727
728static void
729mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
730 struct mlxsw_sp_span_entry *span_entry,
731 enum mlxsw_sp_span_type type)
732{
733 struct mlxsw_sp_span_inspected_port *inspected_port;
734 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
735 char mpar_pl[MLXSW_REG_MPAR_LEN];
736 char sbib_pl[MLXSW_REG_SBIB_LEN];
737 int pa_id = span_entry->id;
738
739 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
740 if (!inspected_port)
741 return;
742
743 /* remove the inspected port */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200744 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
745 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200746 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
747
748 /* remove the SBIB buffer if it was egress SPAN */
749 if (type == MLXSW_SP_SPAN_EGRESS) {
750 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
751 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
752 }
753
754 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
755
756 list_del(&inspected_port->list);
757 kfree(inspected_port);
758}
759
760static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
761 struct mlxsw_sp_port *to,
762 enum mlxsw_sp_span_type type)
763{
764 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
765 struct mlxsw_sp_span_entry *span_entry;
766 int err;
767
768 span_entry = mlxsw_sp_span_entry_get(to);
769 if (!span_entry)
770 return -ENOENT;
771
772 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
773 span_entry->id);
774
775 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
776 if (err)
777 goto err_port_bind;
778
779 return 0;
780
781err_port_bind:
782 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
783 return err;
784}
785
786static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200787 u8 destination_port,
Yotam Gigi763b4b72016-07-21 12:03:17 +0200788 enum mlxsw_sp_span_type type)
789{
790 struct mlxsw_sp_span_entry *span_entry;
791
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200792 span_entry = mlxsw_sp_span_entry_find(from->mlxsw_sp,
793 destination_port);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200794 if (!span_entry) {
795 netdev_err(from->dev, "no span entry found\n");
796 return;
797 }
798
799 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
800 span_entry->id);
801 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
802}
803
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100804static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
805 bool enable, u32 rate)
806{
807 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
808 char mpsc_pl[MLXSW_REG_MPSC_LEN];
809
810 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
811 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
812}
813
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200814static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
815 bool is_up)
816{
817 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
818 char paos_pl[MLXSW_REG_PAOS_LEN];
819
820 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
821 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
822 MLXSW_PORT_ADMIN_STATUS_DOWN);
823 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
824}
825
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200826static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
827 unsigned char *addr)
828{
829 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
830 char ppad_pl[MLXSW_REG_PPAD_LEN];
831
832 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
833 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
834 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
835}
836
837static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
838{
839 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
840 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
841
842 ether_addr_copy(addr, mlxsw_sp->base_mac);
843 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
844 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
845}
846
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200847static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
848{
849 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
850 char pmtu_pl[MLXSW_REG_PMTU_LEN];
851 int max_mtu;
852 int err;
853
854 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
855 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
856 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
857 if (err)
858 return err;
859 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
860
861 if (mtu > max_mtu)
862 return -EINVAL;
863
864 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
865 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
866}
867
868static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
869{
870 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200871 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200872
Ido Schimmel5b153852017-06-08 08:47:44 +0200873 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
874 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200875}
876
Ido Schimmela1107482017-05-26 08:37:39 +0200877int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200878{
879 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
880 char svpe_pl[MLXSW_REG_SVPE_LEN];
881
882 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
883 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
884}
885
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200886int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
887 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200888{
889 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
890 char *spvmlr_pl;
891 int err;
892
893 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
894 if (!spvmlr_pl)
895 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200896 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
897 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200898 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
899 kfree(spvmlr_pl);
900 return err;
901}
902
Ido Schimmelb02eae92017-05-16 19:38:34 +0200903static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
904 u16 vid)
905{
906 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
907 char spvid_pl[MLXSW_REG_SPVID_LEN];
908
909 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
910 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
911}
912
913static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
914 bool allow)
915{
916 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
917 char spaft_pl[MLXSW_REG_SPAFT_LEN];
918
919 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
920 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
921}
922
923int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
924{
925 int err;
926
927 if (!vid) {
928 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
929 if (err)
930 return err;
931 } else {
932 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
933 if (err)
934 return err;
935 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
936 if (err)
937 goto err_port_allow_untagged_set;
938 }
939
940 mlxsw_sp_port->pvid = vid;
941 return 0;
942
943err_port_allow_untagged_set:
944 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
945 return err;
946}
947
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200948static int
949mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
950{
951 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
952 char sspr_pl[MLXSW_REG_SSPR_LEN];
953
954 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
955 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
956}
957
Ido Schimmeld664b412016-06-09 09:51:40 +0200958static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
959 u8 local_port, u8 *p_module,
960 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200961{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200962 char pmlp_pl[MLXSW_REG_PMLP_LEN];
963 int err;
964
Ido Schimmel558c2d52016-02-26 17:32:29 +0100965 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200966 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
967 if (err)
968 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100969 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
970 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200971 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200972 return 0;
973}
974
Ido Schimmel2e915e02017-06-08 08:47:45 +0200975static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100976 u8 module, u8 width, u8 lane)
977{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200978 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100979 char pmlp_pl[MLXSW_REG_PMLP_LEN];
980 int i;
981
Ido Schimmel2e915e02017-06-08 08:47:45 +0200982 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100983 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
984 for (i = 0; i < width; i++) {
985 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
986 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
987 }
988
989 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
990}
991
Ido Schimmel2e915e02017-06-08 08:47:45 +0200992static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100993{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200994 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100995 char pmlp_pl[MLXSW_REG_PMLP_LEN];
996
Ido Schimmel2e915e02017-06-08 08:47:45 +0200997 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100998 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
999 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1000}
1001
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001002static int mlxsw_sp_port_open(struct net_device *dev)
1003{
1004 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1005 int err;
1006
1007 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1008 if (err)
1009 return err;
1010 netif_start_queue(dev);
1011 return 0;
1012}
1013
1014static int mlxsw_sp_port_stop(struct net_device *dev)
1015{
1016 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1017
1018 netif_stop_queue(dev);
1019 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1020}
1021
1022static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1023 struct net_device *dev)
1024{
1025 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1026 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1027 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1028 const struct mlxsw_tx_info tx_info = {
1029 .local_port = mlxsw_sp_port->local_port,
1030 .is_emad = false,
1031 };
1032 u64 len;
1033 int err;
1034
Jiri Pirko307c2432016-04-08 19:11:22 +02001035 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001036 return NETDEV_TX_BUSY;
1037
1038 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1039 struct sk_buff *skb_orig = skb;
1040
1041 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1042 if (!skb) {
1043 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1044 dev_kfree_skb_any(skb_orig);
1045 return NETDEV_TX_OK;
1046 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +01001047 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001048 }
1049
1050 if (eth_skb_pad(skb)) {
1051 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1052 return NETDEV_TX_OK;
1053 }
1054
1055 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +02001056 /* TX header is consumed by HW on the way so we shouldn't count its
1057 * bytes as being sent.
1058 */
1059 len = skb->len - MLXSW_TXHDR_LEN;
1060
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001061 /* Due to a race we might fail here because of a full queue. In that
1062 * unlikely case we simply drop the packet.
1063 */
Jiri Pirko307c2432016-04-08 19:11:22 +02001064 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001065
1066 if (!err) {
1067 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1068 u64_stats_update_begin(&pcpu_stats->syncp);
1069 pcpu_stats->tx_packets++;
1070 pcpu_stats->tx_bytes += len;
1071 u64_stats_update_end(&pcpu_stats->syncp);
1072 } else {
1073 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1074 dev_kfree_skb_any(skb);
1075 }
1076 return NETDEV_TX_OK;
1077}
1078
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001079static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1080{
1081}
1082
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001083static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1084{
1085 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1086 struct sockaddr *addr = p;
1087 int err;
1088
1089 if (!is_valid_ether_addr(addr->sa_data))
1090 return -EADDRNOTAVAIL;
1091
1092 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1093 if (err)
1094 return err;
1095 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1096 return 0;
1097}
1098
Ido Schimmel18281f22017-03-24 08:02:51 +01001099static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1100 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001101{
Ido Schimmel18281f22017-03-24 08:02:51 +01001102 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001103}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001104
Ido Schimmelf417f042017-03-24 08:02:50 +01001105#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +01001106
1107static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1108 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +01001109{
Ido Schimmel18281f22017-03-24 08:02:51 +01001110 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1111 BITS_PER_BYTE));
1112 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1113 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001114}
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001115
Ido Schimmel18281f22017-03-24 08:02:51 +01001116/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +01001117 * Assumes 100m cable and maximum MTU.
1118 */
Ido Schimmel18281f22017-03-24 08:02:51 +01001119#define MLXSW_SP_PAUSE_DELAY 58752
1120
1121static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1122 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +01001123{
1124 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +01001125 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +01001126 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +01001127 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001128 else
Ido Schimmelf417f042017-03-24 08:02:50 +01001129 return 0;
1130}
1131
1132static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1133 bool lossy)
1134{
1135 if (lossy)
1136 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
1137 else
1138 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1139 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001140}
1141
1142int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001143 u8 *prio_tc, bool pause_en,
1144 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +02001145{
1146 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001147 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1148 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001149 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001150 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001151
1152 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1153 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1154 if (err)
1155 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001156
1157 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1158 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001159 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +01001160 bool lossy;
1161 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001162
1163 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1164 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001165 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001166 configure = true;
1167 break;
1168 }
1169 }
1170
1171 if (!configure)
1172 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +01001173
1174 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +01001175 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1176 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1177 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +01001178 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001179 }
1180
Ido Schimmelff6551e2016-04-06 17:10:03 +02001181 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1182}
1183
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001184static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001185 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001186{
1187 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1188 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001189 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001190 u8 *prio_tc;
1191
1192 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001193 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001194
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001195 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001196 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001197}
1198
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001199static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1200{
1201 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001202 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001203 int err;
1204
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001205 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001206 if (err)
1207 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001208 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1209 if (err)
1210 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001211 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1212 if (err)
1213 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001214 dev->mtu = mtu;
1215 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001216
1217err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001218 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1219err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001220 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +02001221 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001222}
1223
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001224static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001225mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1226 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001227{
1228 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1229 struct mlxsw_sp_port_pcpu_stats *p;
1230 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1231 u32 tx_dropped = 0;
1232 unsigned int start;
1233 int i;
1234
1235 for_each_possible_cpu(i) {
1236 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1237 do {
1238 start = u64_stats_fetch_begin_irq(&p->syncp);
1239 rx_packets = p->rx_packets;
1240 rx_bytes = p->rx_bytes;
1241 tx_packets = p->tx_packets;
1242 tx_bytes = p->tx_bytes;
1243 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1244
1245 stats->rx_packets += rx_packets;
1246 stats->rx_bytes += rx_bytes;
1247 stats->tx_packets += tx_packets;
1248 stats->tx_bytes += tx_bytes;
1249 /* tx_dropped is u32, updated without syncp protection. */
1250 tx_dropped += p->tx_dropped;
1251 }
1252 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001253 return 0;
1254}
1255
Or Gerlitz3df5b3c2016-11-22 23:09:54 +02001256static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001257{
1258 switch (attr_id) {
1259 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1260 return true;
1261 }
1262
1263 return false;
1264}
1265
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001266static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1267 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001268{
1269 switch (attr_id) {
1270 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1271 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1272 }
1273
1274 return -EINVAL;
1275}
1276
1277static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1278 int prio, char *ppcnt_pl)
1279{
1280 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1281 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1282
1283 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1284 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1285}
1286
1287static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1288 struct rtnl_link_stats64 *stats)
1289{
1290 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1291 int err;
1292
1293 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1294 0, ppcnt_pl);
1295 if (err)
1296 goto out;
1297
1298 stats->tx_packets =
1299 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1300 stats->rx_packets =
1301 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1302 stats->tx_bytes =
1303 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1304 stats->rx_bytes =
1305 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1306 stats->multicast =
1307 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1308
1309 stats->rx_crc_errors =
1310 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1311 stats->rx_frame_errors =
1312 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1313
1314 stats->rx_length_errors = (
1315 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1316 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1317 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1318
1319 stats->rx_errors = (stats->rx_crc_errors +
1320 stats->rx_frame_errors + stats->rx_length_errors);
1321
1322out:
1323 return err;
1324}
1325
1326static void update_stats_cache(struct work_struct *work)
1327{
1328 struct mlxsw_sp_port *mlxsw_sp_port =
1329 container_of(work, struct mlxsw_sp_port,
1330 hw_stats.update_dw.work);
1331
1332 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1333 goto out;
1334
1335 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1336 mlxsw_sp_port->hw_stats.cache);
1337
1338out:
1339 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
1340 MLXSW_HW_STATS_UPDATE_TIME);
1341}
1342
1343/* Return the stats from a cache that is updated periodically,
1344 * as this function might get called in an atomic context.
1345 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001346static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001347mlxsw_sp_port_get_stats64(struct net_device *dev,
1348 struct rtnl_link_stats64 *stats)
1349{
1350 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1351
1352 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001353}
1354
Jiri Pirko93cd0812017-04-18 16:55:35 +02001355static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1356 u16 vid_begin, u16 vid_end,
1357 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001358{
1359 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1360 char *spvm_pl;
1361 int err;
1362
1363 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1364 if (!spvm_pl)
1365 return -ENOMEM;
1366
1367 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1368 vid_end, is_member, untagged);
1369 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1370 kfree(spvm_pl);
1371 return err;
1372}
1373
Jiri Pirko93cd0812017-04-18 16:55:35 +02001374int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1375 u16 vid_end, bool is_member, bool untagged)
1376{
1377 u16 vid, vid_e;
1378 int err;
1379
1380 for (vid = vid_begin; vid <= vid_end;
1381 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1382 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1383 vid_end);
1384
1385 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1386 is_member, untagged);
1387 if (err)
1388 return err;
1389 }
1390
1391 return 0;
1392}
1393
Ido Schimmelc57529e2017-05-26 08:37:31 +02001394static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001395{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001396 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001397
Ido Schimmelc57529e2017-05-26 08:37:31 +02001398 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1399 &mlxsw_sp_port->vlans_list, list)
1400 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001401}
1402
Ido Schimmel31a08a52017-05-26 08:37:26 +02001403static struct mlxsw_sp_port_vlan *
1404mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1405{
1406 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001407 bool untagged = vid == 1;
1408 int err;
1409
1410 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1411 if (err)
1412 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001413
1414 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001415 if (!mlxsw_sp_port_vlan) {
1416 err = -ENOMEM;
1417 goto err_port_vlan_alloc;
1418 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001419
1420 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1421 mlxsw_sp_port_vlan->vid = vid;
1422 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1423
1424 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001425
1426err_port_vlan_alloc:
1427 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1428 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001429}
1430
1431static void
1432mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1433{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001434 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1435 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001436
Ido Schimmel31a08a52017-05-26 08:37:26 +02001437 list_del(&mlxsw_sp_port_vlan->list);
1438 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001439 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1440}
1441
1442struct mlxsw_sp_port_vlan *
1443mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1444{
1445 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1446
1447 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1448 if (mlxsw_sp_port_vlan)
1449 return mlxsw_sp_port_vlan;
1450
1451 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1452}
1453
1454void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1455{
Ido Schimmela1107482017-05-26 08:37:39 +02001456 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1457
Ido Schimmelc57529e2017-05-26 08:37:31 +02001458 if (mlxsw_sp_port_vlan->bridge_port)
1459 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001460 else if (fid)
1461 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001462
1463 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001464}
1465
Ido Schimmel05978482016-08-17 16:39:30 +02001466static int mlxsw_sp_port_add_vid(struct net_device *dev,
1467 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001468{
1469 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001470
1471 /* VLAN 0 is added to HW filter when device goes up, but it is
1472 * reserved in our case, so simply return.
1473 */
1474 if (!vid)
1475 return 0;
1476
Ido Schimmelc57529e2017-05-26 08:37:31 +02001477 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001478}
1479
Ido Schimmel32d863f2016-07-02 11:00:10 +02001480static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1481 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001482{
1483 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001484 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001485
1486 /* VLAN 0 is removed from HW filter when device goes down, but
1487 * it is reserved in our case, so simply return.
1488 */
1489 if (!vid)
1490 return 0;
1491
Ido Schimmel31a08a52017-05-26 08:37:26 +02001492 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001493 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001494 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001495 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001496
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001497 return 0;
1498}
1499
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001500static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1501 size_t len)
1502{
1503 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001504 u8 module = mlxsw_sp_port->mapping.module;
1505 u8 width = mlxsw_sp_port->mapping.width;
1506 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001507 int err;
1508
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001509 if (!mlxsw_sp_port->split)
1510 err = snprintf(name, len, "p%d", module + 1);
1511 else
1512 err = snprintf(name, len, "p%ds%d", module + 1,
1513 lane / width);
1514
1515 if (err >= len)
1516 return -EINVAL;
1517
1518 return 0;
1519}
1520
Yotam Gigi763b4b72016-07-21 12:03:17 +02001521static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001522mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1523 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001524 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1525
1526 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1527 if (mall_tc_entry->cookie == cookie)
1528 return mall_tc_entry;
1529
1530 return NULL;
1531}
1532
1533static int
1534mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001535 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001536 const struct tc_action *a,
1537 bool ingress)
1538{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001539 struct net *net = dev_net(mlxsw_sp_port->dev);
1540 enum mlxsw_sp_span_type span_type;
1541 struct mlxsw_sp_port *to_port;
1542 struct net_device *to_dev;
1543 int ifindex;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001544
1545 ifindex = tcf_mirred_ifindex(a);
1546 to_dev = __dev_get_by_index(net, ifindex);
1547 if (!to_dev) {
1548 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1549 return -EINVAL;
1550 }
1551
1552 if (!mlxsw_sp_port_dev_check(to_dev)) {
1553 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001554 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001555 }
1556 to_port = netdev_priv(to_dev);
1557
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001558 mirror->to_local_port = to_port->local_port;
1559 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001560 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001561 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1562}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001563
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001564static void
1565mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1566 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1567{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001568 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001569
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001570 span_type = mirror->ingress ?
1571 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yuval Mintz6399ebc2017-09-12 08:50:53 +02001572 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, mirror->to_local_port,
1573 span_type);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001574}
1575
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001576static int
1577mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1578 struct tc_cls_matchall_offload *cls,
1579 const struct tc_action *a,
1580 bool ingress)
1581{
1582 int err;
1583
1584 if (!mlxsw_sp_port->sample)
1585 return -EOPNOTSUPP;
1586 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1587 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1588 return -EEXIST;
1589 }
1590 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1591 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1592 return -EOPNOTSUPP;
1593 }
1594
1595 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1596 tcf_sample_psample_group(a));
1597 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1598 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1599 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1600
1601 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1602 if (err)
1603 goto err_port_sample_set;
1604 return 0;
1605
1606err_port_sample_set:
1607 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1608 return err;
1609}
1610
1611static void
1612mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1613{
1614 if (!mlxsw_sp_port->sample)
1615 return;
1616
1617 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1618 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1619}
1620
Yotam Gigi763b4b72016-07-21 12:03:17 +02001621static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001622 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001623 bool ingress)
1624{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001625 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001626 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001627 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001628 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001629 int err;
1630
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001631 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001632 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001633 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001634 }
1635
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001636 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1637 if (!mall_tc_entry)
1638 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001639 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001640
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001641 tcf_exts_to_list(f->exts, &actions);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001642 a = list_first_entry(&actions, struct tc_action, list);
1643
1644 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1645 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1646
1647 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1648 mirror = &mall_tc_entry->mirror;
1649 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1650 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001651 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1652 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001653 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001654 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001655 } else {
1656 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001657 }
1658
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001659 if (err)
1660 goto err_add_action;
1661
1662 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001663 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001664
1665err_add_action:
1666 kfree(mall_tc_entry);
1667 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001668}
1669
1670static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001671 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001672{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001673 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001674
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001675 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001676 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001677 if (!mall_tc_entry) {
1678 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1679 return;
1680 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001681 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001682
1683 switch (mall_tc_entry->type) {
1684 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001685 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1686 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001687 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001688 case MLXSW_SP_PORT_MALL_SAMPLE:
1689 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1690 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001691 default:
1692 WARN_ON(1);
1693 }
1694
Yotam Gigi763b4b72016-07-21 12:03:17 +02001695 kfree(mall_tc_entry);
1696}
1697
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001698static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001699 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001700{
Jiri Pirkoa2e8da92017-08-09 14:30:33 +02001701 bool ingress;
1702
1703 if (is_classid_clsact_ingress(f->common.classid))
1704 ingress = true;
1705 else if (is_classid_clsact_egress(f->common.classid))
1706 ingress = false;
1707 else
1708 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001709
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001710 if (f->common.chain_index)
Jiri Pirkoa5fcf8a2017-06-06 17:00:16 +02001711 return -EOPNOTSUPP;
1712
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001713 switch (f->command) {
1714 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001715 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001716 ingress);
1717 case TC_CLSMATCHALL_DESTROY:
1718 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1719 return 0;
1720 default:
1721 return -EOPNOTSUPP;
1722 }
1723}
1724
1725static int
1726mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001727 struct tc_cls_flower_offload *f)
1728{
Jiri Pirkoa2e8da92017-08-09 14:30:33 +02001729 bool ingress;
1730
1731 if (is_classid_clsact_ingress(f->common.classid))
1732 ingress = true;
1733 else if (is_classid_clsact_egress(f->common.classid))
1734 ingress = false;
1735 else
1736 return -EOPNOTSUPP;
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001737
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001738 switch (f->command) {
1739 case TC_CLSFLOWER_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001740 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001741 case TC_CLSFLOWER_DESTROY:
1742 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress, f);
1743 return 0;
1744 case TC_CLSFLOWER_STATS:
1745 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress, f);
1746 default:
1747 return -EOPNOTSUPP;
1748 }
1749}
1750
1751static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001752 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001753{
1754 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1755
Jiri Pirko2572ac52017-08-07 10:15:17 +02001756 switch (type) {
Jiri Pirkoade9b652017-08-07 10:15:18 +02001757 case TC_SETUP_CLSMATCHALL:
Jiri Pirkode4784c2017-08-07 10:15:32 +02001758 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data);
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001759 case TC_SETUP_CLSFLOWER:
Jiri Pirkode4784c2017-08-07 10:15:32 +02001760 return mlxsw_sp_setup_tc_cls_flower(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001761 default:
1762 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001763 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001764}
1765
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001766static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1767 .ndo_open = mlxsw_sp_port_open,
1768 .ndo_stop = mlxsw_sp_port_stop,
1769 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001770 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001771 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001772 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1773 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1774 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001775 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1776 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001777 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1778 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001779 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001780};
1781
1782static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1783 struct ethtool_drvinfo *drvinfo)
1784{
1785 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1786 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1787
1788 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1789 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1790 sizeof(drvinfo->version));
1791 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1792 "%d.%d.%d",
1793 mlxsw_sp->bus_info->fw_rev.major,
1794 mlxsw_sp->bus_info->fw_rev.minor,
1795 mlxsw_sp->bus_info->fw_rev.subminor);
1796 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1797 sizeof(drvinfo->bus_info));
1798}
1799
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001800static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1801 struct ethtool_pauseparam *pause)
1802{
1803 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1804
1805 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1806 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1807}
1808
1809static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1810 struct ethtool_pauseparam *pause)
1811{
1812 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1813
1814 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1815 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1816 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1817
1818 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1819 pfcc_pl);
1820}
1821
1822static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1823 struct ethtool_pauseparam *pause)
1824{
1825 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1826 bool pause_en = pause->tx_pause || pause->rx_pause;
1827 int err;
1828
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001829 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1830 netdev_err(dev, "PFC already enabled on port\n");
1831 return -EINVAL;
1832 }
1833
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001834 if (pause->autoneg) {
1835 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1836 return -EINVAL;
1837 }
1838
1839 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1840 if (err) {
1841 netdev_err(dev, "Failed to configure port's headroom\n");
1842 return err;
1843 }
1844
1845 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1846 if (err) {
1847 netdev_err(dev, "Failed to set PAUSE parameters\n");
1848 goto err_port_pause_configure;
1849 }
1850
1851 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1852 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1853
1854 return 0;
1855
1856err_port_pause_configure:
1857 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1858 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1859 return err;
1860}
1861
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001862struct mlxsw_sp_port_hw_stats {
1863 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001864 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001865 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001866};
1867
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001868static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001869 {
1870 .str = "a_frames_transmitted_ok",
1871 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1872 },
1873 {
1874 .str = "a_frames_received_ok",
1875 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1876 },
1877 {
1878 .str = "a_frame_check_sequence_errors",
1879 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1880 },
1881 {
1882 .str = "a_alignment_errors",
1883 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1884 },
1885 {
1886 .str = "a_octets_transmitted_ok",
1887 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1888 },
1889 {
1890 .str = "a_octets_received_ok",
1891 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1892 },
1893 {
1894 .str = "a_multicast_frames_xmitted_ok",
1895 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1896 },
1897 {
1898 .str = "a_broadcast_frames_xmitted_ok",
1899 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1900 },
1901 {
1902 .str = "a_multicast_frames_received_ok",
1903 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1904 },
1905 {
1906 .str = "a_broadcast_frames_received_ok",
1907 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1908 },
1909 {
1910 .str = "a_in_range_length_errors",
1911 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1912 },
1913 {
1914 .str = "a_out_of_range_length_field",
1915 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1916 },
1917 {
1918 .str = "a_frame_too_long_errors",
1919 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1920 },
1921 {
1922 .str = "a_symbol_error_during_carrier",
1923 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1924 },
1925 {
1926 .str = "a_mac_control_frames_transmitted",
1927 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1928 },
1929 {
1930 .str = "a_mac_control_frames_received",
1931 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
1932 },
1933 {
1934 .str = "a_unsupported_opcodes_received",
1935 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
1936 },
1937 {
1938 .str = "a_pause_mac_ctrl_frames_received",
1939 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
1940 },
1941 {
1942 .str = "a_pause_mac_ctrl_frames_xmitted",
1943 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
1944 },
1945};
1946
1947#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
1948
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001949static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
1950 {
1951 .str = "rx_octets_prio",
1952 .getter = mlxsw_reg_ppcnt_rx_octets_get,
1953 },
1954 {
1955 .str = "rx_frames_prio",
1956 .getter = mlxsw_reg_ppcnt_rx_frames_get,
1957 },
1958 {
1959 .str = "tx_octets_prio",
1960 .getter = mlxsw_reg_ppcnt_tx_octets_get,
1961 },
1962 {
1963 .str = "tx_frames_prio",
1964 .getter = mlxsw_reg_ppcnt_tx_frames_get,
1965 },
1966 {
1967 .str = "rx_pause_prio",
1968 .getter = mlxsw_reg_ppcnt_rx_pause_get,
1969 },
1970 {
1971 .str = "rx_pause_duration_prio",
1972 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
1973 },
1974 {
1975 .str = "tx_pause_prio",
1976 .getter = mlxsw_reg_ppcnt_tx_pause_get,
1977 },
1978 {
1979 .str = "tx_pause_duration_prio",
1980 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
1981 },
1982};
1983
1984#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
1985
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001986static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
1987 {
1988 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01001989 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
1990 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02001991 },
1992 {
1993 .str = "tc_no_buffer_discard_uc_tc",
1994 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
1995 },
1996};
1997
1998#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
1999
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002000#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002001 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
2002 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002003 IEEE_8021QAZ_MAX_TCS)
2004
2005static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2006{
2007 int i;
2008
2009 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2010 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2011 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2012 *p += ETH_GSTRING_LEN;
2013 }
2014}
2015
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002016static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2017{
2018 int i;
2019
2020 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2021 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2022 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2023 *p += ETH_GSTRING_LEN;
2024 }
2025}
2026
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002027static void mlxsw_sp_port_get_strings(struct net_device *dev,
2028 u32 stringset, u8 *data)
2029{
2030 u8 *p = data;
2031 int i;
2032
2033 switch (stringset) {
2034 case ETH_SS_STATS:
2035 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2036 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2037 ETH_GSTRING_LEN);
2038 p += ETH_GSTRING_LEN;
2039 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002040
2041 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2042 mlxsw_sp_port_get_prio_strings(&p, i);
2043
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002044 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2045 mlxsw_sp_port_get_tc_strings(&p, i);
2046
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002047 break;
2048 }
2049}
2050
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002051static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2052 enum ethtool_phys_id_state state)
2053{
2054 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2055 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2056 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2057 bool active;
2058
2059 switch (state) {
2060 case ETHTOOL_ID_ACTIVE:
2061 active = true;
2062 break;
2063 case ETHTOOL_ID_INACTIVE:
2064 active = false;
2065 break;
2066 default:
2067 return -EOPNOTSUPP;
2068 }
2069
2070 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2071 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2072}
2073
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002074static int
2075mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2076 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2077{
2078 switch (grp) {
2079 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2080 *p_hw_stats = mlxsw_sp_port_hw_stats;
2081 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2082 break;
2083 case MLXSW_REG_PPCNT_PRIO_CNT:
2084 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2085 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2086 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002087 case MLXSW_REG_PPCNT_TC_CNT:
2088 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2089 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2090 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002091 default:
2092 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002093 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002094 }
2095 return 0;
2096}
2097
2098static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2099 enum mlxsw_reg_ppcnt_grp grp, int prio,
2100 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002101{
Ido Schimmel18281f22017-03-24 08:02:51 +01002102 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2103 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002104 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002105 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002106 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002107 int err;
2108
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002109 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2110 if (err)
2111 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002112 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002113 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002114 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002115 if (!hw_stats[i].cells_bytes)
2116 continue;
2117 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2118 data[data_index + i]);
2119 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002120}
2121
2122static void mlxsw_sp_port_get_stats(struct net_device *dev,
2123 struct ethtool_stats *stats, u64 *data)
2124{
2125 int i, data_index = 0;
2126
2127 /* IEEE 802.3 Counters */
2128 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2129 data, data_index);
2130 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2131
2132 /* Per-Priority Counters */
2133 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2134 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2135 data, data_index);
2136 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2137 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002138
2139 /* Per-TC Counters */
2140 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2141 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2142 data, data_index);
2143 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2144 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002145}
2146
2147static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2148{
2149 switch (sset) {
2150 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002151 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002152 default:
2153 return -EOPNOTSUPP;
2154 }
2155}
2156
2157struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002158 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002159 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002160 u32 speed;
2161};
2162
2163static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2164 {
2165 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002166 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2167 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002168 },
2169 {
2170 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2171 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002172 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2173 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002174 },
2175 {
2176 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002177 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2178 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002179 },
2180 {
2181 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2182 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002183 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2184 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002185 },
2186 {
2187 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2188 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2189 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2190 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002191 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2192 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002193 },
2194 {
2195 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002196 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2197 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002198 },
2199 {
2200 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002201 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2202 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002203 },
2204 {
2205 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002206 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2207 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002208 },
2209 {
2210 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002211 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2212 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002213 },
2214 {
2215 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002216 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2217 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002218 },
2219 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002220 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2221 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2222 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002223 },
2224 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002225 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2226 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2227 .speed = SPEED_25000,
2228 },
2229 {
2230 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2231 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2232 .speed = SPEED_25000,
2233 },
2234 {
2235 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2236 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2237 .speed = SPEED_25000,
2238 },
2239 {
2240 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2241 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2242 .speed = SPEED_50000,
2243 },
2244 {
2245 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2246 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2247 .speed = SPEED_50000,
2248 },
2249 {
2250 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2251 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2252 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002253 },
2254 {
2255 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002256 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2257 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002258 },
2259 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002260 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2261 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2262 .speed = SPEED_56000,
2263 },
2264 {
2265 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2266 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2267 .speed = SPEED_56000,
2268 },
2269 {
2270 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2271 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2272 .speed = SPEED_56000,
2273 },
2274 {
2275 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2276 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2277 .speed = SPEED_100000,
2278 },
2279 {
2280 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2281 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2282 .speed = SPEED_100000,
2283 },
2284 {
2285 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2286 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2287 .speed = SPEED_100000,
2288 },
2289 {
2290 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2291 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2292 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002293 },
2294};
2295
2296#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2297
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002298static void
2299mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2300 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002301{
2302 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2303 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2304 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2305 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2306 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2307 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002308 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002309
2310 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2311 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2312 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2313 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2314 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002315 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002316}
2317
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002318static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002319{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002320 int i;
2321
2322 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2323 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002324 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2325 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002326 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002327}
2328
2329static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002330 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002331{
2332 u32 speed = SPEED_UNKNOWN;
2333 u8 duplex = DUPLEX_UNKNOWN;
2334 int i;
2335
2336 if (!carrier_ok)
2337 goto out;
2338
2339 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2340 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2341 speed = mlxsw_sp_port_link_mode[i].speed;
2342 duplex = DUPLEX_FULL;
2343 break;
2344 }
2345 }
2346out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002347 cmd->base.speed = speed;
2348 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002349}
2350
2351static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2352{
2353 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2354 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2355 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2356 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2357 return PORT_FIBRE;
2358
2359 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2360 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2361 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2362 return PORT_DA;
2363
2364 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2365 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2366 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2367 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2368 return PORT_NONE;
2369
2370 return PORT_OTHER;
2371}
2372
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002373static u32
2374mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002375{
2376 u32 ptys_proto = 0;
2377 int i;
2378
2379 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002380 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2381 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002382 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2383 }
2384 return ptys_proto;
2385}
2386
2387static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2388{
2389 u32 ptys_proto = 0;
2390 int i;
2391
2392 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2393 if (speed == mlxsw_sp_port_link_mode[i].speed)
2394 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2395 }
2396 return ptys_proto;
2397}
2398
Ido Schimmel18f1e702016-02-26 17:32:31 +01002399static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2400{
2401 u32 ptys_proto = 0;
2402 int i;
2403
2404 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2405 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2406 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2407 }
2408 return ptys_proto;
2409}
2410
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002411static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2412 struct ethtool_link_ksettings *cmd)
2413{
2414 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2415 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2416 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2417
2418 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2419 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2420}
2421
2422static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2423 struct ethtool_link_ksettings *cmd)
2424{
2425 if (!autoneg)
2426 return;
2427
2428 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2429 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2430}
2431
2432static void
2433mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2434 struct ethtool_link_ksettings *cmd)
2435{
2436 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2437 return;
2438
2439 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2440 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2441}
2442
2443static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2444 struct ethtool_link_ksettings *cmd)
2445{
2446 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2447 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2448 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2449 char ptys_pl[MLXSW_REG_PTYS_LEN];
2450 u8 autoneg_status;
2451 bool autoneg;
2452 int err;
2453
2454 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002455 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002456 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2457 if (err)
2458 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002459 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2460 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002461
2462 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2463
2464 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2465
2466 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2467 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2468 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2469
2470 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2471 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2472 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2473 cmd);
2474
2475 return 0;
2476}
2477
2478static int
2479mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2480 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002481{
2482 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2483 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2484 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002485 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002486 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002487 int err;
2488
Elad Raz401c8b42016-10-28 21:35:52 +02002489 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002490 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002491 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002492 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002493 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002494
2495 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2496 eth_proto_new = autoneg ?
2497 mlxsw_sp_to_ptys_advert_link(cmd) :
2498 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002499
2500 eth_proto_new = eth_proto_new & eth_proto_cap;
2501 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002502 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002503 return -EINVAL;
2504 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002505
Elad Raz401c8b42016-10-28 21:35:52 +02002506 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2507 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002508 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002509 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002510 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002511
Ido Schimmel6277d462016-07-15 11:14:58 +02002512 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002513 return 0;
2514
Ido Schimmel0c83f882016-09-12 13:26:23 +02002515 mlxsw_sp_port->link.autoneg = autoneg;
2516
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002517 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2518 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002519
2520 return 0;
2521}
2522
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002523static int mlxsw_sp_flash_device(struct net_device *dev,
2524 struct ethtool_flash *flash)
2525{
2526 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2527 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2528 const struct firmware *firmware;
2529 int err;
2530
2531 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2532 return -EOPNOTSUPP;
2533
2534 dev_hold(dev);
2535 rtnl_unlock();
2536
2537 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2538 if (err)
2539 goto out;
2540 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2541 release_firmware(firmware);
2542out:
2543 rtnl_lock();
2544 dev_put(dev);
2545 return err;
2546}
2547
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002548#define MLXSW_SP_I2C_ADDR_LOW 0x50
2549#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2550#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002551
2552static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2553 u16 offset, u16 size, void *data,
2554 unsigned int *p_read_size)
2555{
2556 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2557 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2558 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002559 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002560 int status;
2561 int err;
2562
2563 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002564
2565 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2566 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2567 /* Cross pages read, read until offset 256 in low page */
2568 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2569
2570 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2571 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2572 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2573 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2574 }
2575
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002576 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002577 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002578
2579 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2580 if (err)
2581 return err;
2582
2583 status = mlxsw_reg_mcia_status_get(mcia_pl);
2584 if (status)
2585 return -EIO;
2586
2587 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2588 memcpy(data, eeprom_tmp, size);
2589 *p_read_size = size;
2590
2591 return 0;
2592}
2593
2594enum mlxsw_sp_eeprom_module_info_rev_id {
2595 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2596 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2597 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2598};
2599
2600enum mlxsw_sp_eeprom_module_info_id {
2601 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2602 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2603 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2604 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2605};
2606
2607enum mlxsw_sp_eeprom_module_info {
2608 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2609 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2610 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2611};
2612
2613static int mlxsw_sp_get_module_info(struct net_device *netdev,
2614 struct ethtool_modinfo *modinfo)
2615{
2616 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2617 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2618 u8 module_rev_id, module_id;
2619 unsigned int read_size;
2620 int err;
2621
2622 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2623 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2624 module_info, &read_size);
2625 if (err)
2626 return err;
2627
2628 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2629 return -EIO;
2630
2631 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2632 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2633
2634 switch (module_id) {
2635 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2636 modinfo->type = ETH_MODULE_SFF_8436;
2637 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2638 break;
2639 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2640 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2641 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2642 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2643 modinfo->type = ETH_MODULE_SFF_8636;
2644 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2645 } else {
2646 modinfo->type = ETH_MODULE_SFF_8436;
2647 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2648 }
2649 break;
2650 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2651 modinfo->type = ETH_MODULE_SFF_8472;
2652 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2653 break;
2654 default:
2655 return -EINVAL;
2656 }
2657
2658 return 0;
2659}
2660
2661static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2662 struct ethtool_eeprom *ee,
2663 u8 *data)
2664{
2665 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2666 int offset = ee->offset;
2667 unsigned int read_size;
2668 int i = 0;
2669 int err;
2670
2671 if (!ee->len)
2672 return -EINVAL;
2673
2674 memset(data, 0, ee->len);
2675
2676 while (i < ee->len) {
2677 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2678 ee->len - i, data + i,
2679 &read_size);
2680 if (err) {
2681 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2682 return err;
2683 }
2684
2685 i += read_size;
2686 offset += read_size;
2687 }
2688
2689 return 0;
2690}
2691
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002692static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2693 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2694 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002695 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2696 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002697 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002698 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002699 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2700 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002701 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2702 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002703 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002704 .get_module_info = mlxsw_sp_get_module_info,
2705 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002706};
2707
Ido Schimmel18f1e702016-02-26 17:32:31 +01002708static int
2709mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2710{
2711 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2712 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2713 char ptys_pl[MLXSW_REG_PTYS_LEN];
2714 u32 eth_proto_admin;
2715
2716 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002717 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2718 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002719 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2720}
2721
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002722int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2723 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2724 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002725{
2726 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2727 char qeec_pl[MLXSW_REG_QEEC_LEN];
2728
2729 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2730 next_index);
2731 mlxsw_reg_qeec_de_set(qeec_pl, true);
2732 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2733 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2734 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2735}
2736
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002737int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2738 enum mlxsw_reg_qeec_hr hr, u8 index,
2739 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002740{
2741 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2742 char qeec_pl[MLXSW_REG_QEEC_LEN];
2743
2744 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2745 next_index);
2746 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2747 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2748 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2749}
2750
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002751int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2752 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002753{
2754 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2755 char qtct_pl[MLXSW_REG_QTCT_LEN];
2756
2757 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2758 tclass);
2759 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2760}
2761
2762static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2763{
2764 int err, i;
2765
2766 /* Setup the elements hierarcy, so that each TC is linked to
2767 * one subgroup, which are all member in the same group.
2768 */
2769 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2770 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2771 0);
2772 if (err)
2773 return err;
2774 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2775 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2776 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2777 0, false, 0);
2778 if (err)
2779 return err;
2780 }
2781 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2782 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2783 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2784 false, 0);
2785 if (err)
2786 return err;
2787 }
2788
2789 /* Make sure the max shaper is disabled in all hierarcies that
2790 * support it.
2791 */
2792 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2793 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2794 MLXSW_REG_QEEC_MAS_DIS);
2795 if (err)
2796 return err;
2797 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2798 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2799 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2800 i, 0,
2801 MLXSW_REG_QEEC_MAS_DIS);
2802 if (err)
2803 return err;
2804 }
2805 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2806 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2807 MLXSW_REG_QEEC_HIERARCY_TC,
2808 i, i,
2809 MLXSW_REG_QEEC_MAS_DIS);
2810 if (err)
2811 return err;
2812 }
2813
2814 /* Map all priorities to traffic class 0. */
2815 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2816 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2817 if (err)
2818 return err;
2819 }
2820
2821 return 0;
2822}
2823
Ido Schimmel5b153852017-06-08 08:47:44 +02002824static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2825 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002826{
Ido Schimmelc57529e2017-05-26 08:37:31 +02002827 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002828 struct mlxsw_sp_port *mlxsw_sp_port;
2829 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002830 int err;
2831
Ido Schimmel5b153852017-06-08 08:47:44 +02002832 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2833 if (err) {
2834 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2835 local_port);
2836 return err;
2837 }
2838
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002839 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02002840 if (!dev) {
2841 err = -ENOMEM;
2842 goto err_alloc_etherdev;
2843 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002844 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002845 mlxsw_sp_port = netdev_priv(dev);
2846 mlxsw_sp_port->dev = dev;
2847 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2848 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02002849 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002850 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002851 mlxsw_sp_port->mapping.module = module;
2852 mlxsw_sp_port->mapping.width = width;
2853 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002854 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02002855 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002856 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002857
2858 mlxsw_sp_port->pcpu_stats =
2859 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2860 if (!mlxsw_sp_port->pcpu_stats) {
2861 err = -ENOMEM;
2862 goto err_alloc_stats;
2863 }
2864
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002865 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2866 GFP_KERNEL);
2867 if (!mlxsw_sp_port->sample) {
2868 err = -ENOMEM;
2869 goto err_alloc_sample;
2870 }
2871
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002872 mlxsw_sp_port->hw_stats.cache =
2873 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2874
2875 if (!mlxsw_sp_port->hw_stats.cache) {
2876 err = -ENOMEM;
2877 goto err_alloc_hw_stats;
2878 }
2879 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2880 &update_stats_cache);
2881
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002882 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2883 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2884
Ido Schimmel2e915e02017-06-08 08:47:45 +02002885 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02002886 if (err) {
2887 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
2888 mlxsw_sp_port->local_port);
2889 goto err_port_module_map;
2890 }
2891
Ido Schimmel3247ff22016-09-08 08:16:02 +02002892 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2893 if (err) {
2894 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2895 mlxsw_sp_port->local_port);
2896 goto err_port_swid_set;
2897 }
2898
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002899 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2900 if (err) {
2901 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2902 mlxsw_sp_port->local_port);
2903 goto err_dev_addr_init;
2904 }
2905
2906 netif_carrier_off(dev);
2907
2908 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002909 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2910 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002911
Jarod Wilsond894be52016-10-20 13:55:16 -04002912 dev->min_mtu = 0;
2913 dev->max_mtu = ETH_MAX_MTU;
2914
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002915 /* Each packet needs to have a Tx header (metadata) on top all other
2916 * headers.
2917 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002918 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002919
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002920 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2921 if (err) {
2922 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2923 mlxsw_sp_port->local_port);
2924 goto err_port_system_port_mapping_set;
2925 }
2926
Ido Schimmel18f1e702016-02-26 17:32:31 +01002927 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2928 if (err) {
2929 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2930 mlxsw_sp_port->local_port);
2931 goto err_port_speed_by_width_set;
2932 }
2933
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002934 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2935 if (err) {
2936 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2937 mlxsw_sp_port->local_port);
2938 goto err_port_mtu_set;
2939 }
2940
2941 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2942 if (err)
2943 goto err_port_admin_status_set;
2944
2945 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2946 if (err) {
2947 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2948 mlxsw_sp_port->local_port);
2949 goto err_port_buffers_init;
2950 }
2951
Ido Schimmel90183b92016-04-06 17:10:08 +02002952 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2953 if (err) {
2954 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2955 mlxsw_sp_port->local_port);
2956 goto err_port_ets_init;
2957 }
2958
Ido Schimmelf00817d2016-04-06 17:10:09 +02002959 /* ETS and buffers must be initialized before DCB. */
2960 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2961 if (err) {
2962 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2963 mlxsw_sp_port->local_port);
2964 goto err_port_dcb_init;
2965 }
2966
Ido Schimmela1107482017-05-26 08:37:39 +02002967 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02002968 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02002969 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02002970 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02002971 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02002972 }
2973
Ido Schimmelc57529e2017-05-26 08:37:31 +02002974 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
2975 if (IS_ERR(mlxsw_sp_port_vlan)) {
2976 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02002977 mlxsw_sp_port->local_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002978 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02002979 }
2980
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002981 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002982 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002983 err = register_netdev(dev);
2984 if (err) {
2985 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2986 mlxsw_sp_port->local_port);
2987 goto err_register_netdev;
2988 }
2989
Elad Razd808c7e2016-10-28 21:35:57 +02002990 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2991 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2992 module);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002993 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002994 return 0;
2995
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002996err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002997 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002998 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02002999 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3000err_port_vlan_get:
Ido Schimmela1107482017-05-26 08:37:39 +02003001 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3002err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03003003 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003004err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02003005err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003006err_port_buffers_init:
3007err_port_admin_status_set:
3008err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01003009err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003010err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003011err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02003012 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3013err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02003014 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02003015err_port_module_map:
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02003016 kfree(mlxsw_sp_port->hw_stats.cache);
3017err_alloc_hw_stats:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003018 kfree(mlxsw_sp_port->sample);
3019err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003020 free_percpu(mlxsw_sp_port->pcpu_stats);
3021err_alloc_stats:
3022 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02003023err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02003024 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3025 return err;
3026}
3027
Ido Schimmel5b153852017-06-08 08:47:44 +02003028static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003029{
3030 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3031
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02003032 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02003033 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003034 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02003035 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003036 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003037 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003038 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003039 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01003040 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02003041 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02003042 kfree(mlxsw_sp_port->hw_stats.cache);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003043 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01003044 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02003045 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003046 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02003047 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3048}
3049
Jiri Pirkof83e2102016-10-28 21:35:49 +02003050static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3051{
3052 return mlxsw_sp->ports[local_port] != NULL;
3053}
3054
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003055static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3056{
3057 int i;
3058
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003059 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003060 if (mlxsw_sp_port_created(mlxsw_sp, i))
3061 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003062 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003063 kfree(mlxsw_sp->ports);
3064}
3065
3066static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3067{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003068 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02003069 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003070 size_t alloc_size;
3071 int i;
3072 int err;
3073
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003074 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003075 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3076 if (!mlxsw_sp->ports)
3077 return -ENOMEM;
3078
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003079 mlxsw_sp->port_to_module = kcalloc(max_ports, sizeof(u8), GFP_KERNEL);
3080 if (!mlxsw_sp->port_to_module) {
3081 err = -ENOMEM;
3082 goto err_port_to_module_alloc;
3083 }
3084
3085 for (i = 1; i < max_ports; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01003086 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003087 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003088 if (err)
3089 goto err_port_module_info_get;
3090 if (!width)
3091 continue;
3092 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003093 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3094 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003095 if (err)
3096 goto err_port_create;
3097 }
3098 return 0;
3099
3100err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003101err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003102 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003103 if (mlxsw_sp_port_created(mlxsw_sp, i))
3104 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003105 kfree(mlxsw_sp->port_to_module);
3106err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003107 kfree(mlxsw_sp->ports);
3108 return err;
3109}
3110
Ido Schimmel18f1e702016-02-26 17:32:31 +01003111static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3112{
3113 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3114
3115 return local_port - offset;
3116}
3117
Ido Schimmelbe945352016-06-09 09:51:39 +02003118static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3119 u8 module, unsigned int count)
3120{
3121 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3122 int err, i;
3123
3124 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003125 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003126 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003127 if (err)
3128 goto err_port_create;
3129 }
3130
3131 return 0;
3132
3133err_port_create:
3134 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003135 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3136 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003137 return err;
3138}
3139
3140static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3141 u8 base_port, unsigned int count)
3142{
3143 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3144 int i;
3145
3146 /* Split by four means we need to re-create two ports, otherwise
3147 * only one.
3148 */
3149 count = count / 2;
3150
3151 for (i = 0; i < count; i++) {
3152 local_port = base_port + i * 2;
3153 module = mlxsw_sp->port_to_module[local_port];
3154
Ido Schimmelbe945352016-06-09 09:51:39 +02003155 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003156 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003157 }
3158}
3159
Jiri Pirkob2f10572016-04-08 19:11:23 +02003160static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3161 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003162{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003163 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003164 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003165 u8 module, cur_width, base_port;
3166 int i;
3167 int err;
3168
3169 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3170 if (!mlxsw_sp_port) {
3171 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3172 local_port);
3173 return -EINVAL;
3174 }
3175
Ido Schimmeld664b412016-06-09 09:51:40 +02003176 module = mlxsw_sp_port->mapping.module;
3177 cur_width = mlxsw_sp_port->mapping.width;
3178
Ido Schimmel18f1e702016-02-26 17:32:31 +01003179 if (count != 2 && count != 4) {
3180 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3181 return -EINVAL;
3182 }
3183
Ido Schimmel18f1e702016-02-26 17:32:31 +01003184 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3185 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3186 return -EINVAL;
3187 }
3188
3189 /* Make sure we have enough slave (even) ports for the split. */
3190 if (count == 2) {
3191 base_port = local_port;
3192 if (mlxsw_sp->ports[base_port + 1]) {
3193 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3194 return -EINVAL;
3195 }
3196 } else {
3197 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3198 if (mlxsw_sp->ports[base_port + 1] ||
3199 mlxsw_sp->ports[base_port + 3]) {
3200 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3201 return -EINVAL;
3202 }
3203 }
3204
3205 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003206 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3207 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003208
Ido Schimmelbe945352016-06-09 09:51:39 +02003209 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3210 if (err) {
3211 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3212 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003213 }
3214
3215 return 0;
3216
Ido Schimmelbe945352016-06-09 09:51:39 +02003217err_port_split_create:
3218 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003219 return err;
3220}
3221
Jiri Pirkob2f10572016-04-08 19:11:23 +02003222static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003223{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003224 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003225 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003226 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003227 unsigned int count;
3228 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003229
3230 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3231 if (!mlxsw_sp_port) {
3232 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3233 local_port);
3234 return -EINVAL;
3235 }
3236
3237 if (!mlxsw_sp_port->split) {
3238 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3239 return -EINVAL;
3240 }
3241
Ido Schimmeld664b412016-06-09 09:51:40 +02003242 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003243 count = cur_width == 1 ? 4 : 2;
3244
3245 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3246
3247 /* Determine which ports to remove. */
3248 if (count == 2 && local_port >= base_port + 2)
3249 base_port = base_port + 2;
3250
3251 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003252 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3253 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003254
Ido Schimmelbe945352016-06-09 09:51:39 +02003255 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003256
3257 return 0;
3258}
3259
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003260static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3261 char *pude_pl, void *priv)
3262{
3263 struct mlxsw_sp *mlxsw_sp = priv;
3264 struct mlxsw_sp_port *mlxsw_sp_port;
3265 enum mlxsw_reg_pude_oper_status status;
3266 u8 local_port;
3267
3268 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3269 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003270 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003271 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003272
3273 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3274 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3275 netdev_info(mlxsw_sp_port->dev, "link up\n");
3276 netif_carrier_on(mlxsw_sp_port->dev);
3277 } else {
3278 netdev_info(mlxsw_sp_port->dev, "link down\n");
3279 netif_carrier_off(mlxsw_sp_port->dev);
3280 }
3281}
3282
Nogah Frankel14eeda92016-11-25 10:33:32 +01003283static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3284 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003285{
3286 struct mlxsw_sp *mlxsw_sp = priv;
3287 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3288 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3289
3290 if (unlikely(!mlxsw_sp_port)) {
3291 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3292 local_port);
3293 return;
3294 }
3295
3296 skb->dev = mlxsw_sp_port->dev;
3297
3298 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3299 u64_stats_update_begin(&pcpu_stats->syncp);
3300 pcpu_stats->rx_packets++;
3301 pcpu_stats->rx_bytes += skb->len;
3302 u64_stats_update_end(&pcpu_stats->syncp);
3303
3304 skb->protocol = eth_type_trans(skb, skb->dev);
3305 netif_receive_skb(skb);
3306}
3307
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003308static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3309 void *priv)
3310{
3311 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003312 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003313}
3314
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003315static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3316 void *priv)
3317{
3318 struct mlxsw_sp *mlxsw_sp = priv;
3319 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3320 struct psample_group *psample_group;
3321 u32 size;
3322
3323 if (unlikely(!mlxsw_sp_port)) {
3324 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3325 local_port);
3326 goto out;
3327 }
3328 if (unlikely(!mlxsw_sp_port->sample)) {
3329 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3330 local_port);
3331 goto out;
3332 }
3333
3334 size = mlxsw_sp_port->sample->truncate ?
3335 mlxsw_sp_port->sample->trunc_size : skb->len;
3336
3337 rcu_read_lock();
3338 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3339 if (!psample_group)
3340 goto out_unlock;
3341 psample_sample_packet(psample_group, skb, size,
3342 mlxsw_sp_port->dev->ifindex, 0,
3343 mlxsw_sp_port->sample->rate);
3344out_unlock:
3345 rcu_read_unlock();
3346out:
3347 consume_skb(skb);
3348}
3349
Nogah Frankel117b0da2016-11-25 10:33:44 +01003350#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003351 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003352 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003353
Nogah Frankel117b0da2016-11-25 10:33:44 +01003354#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003355 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003356 _is_ctrl, SP_##_trap_group, DISCARD)
3357
3358#define MLXSW_SP_EVENTL(_func, _trap_id) \
3359 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003360
Nogah Frankel45449132016-11-25 10:33:35 +01003361static const struct mlxsw_listener mlxsw_sp_listener[] = {
3362 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003363 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003364 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003365 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3366 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3367 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3368 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3369 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3370 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3371 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3372 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3373 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3374 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3375 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003376 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003377 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3378 false),
3379 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3380 false),
3381 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3382 false),
3383 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3384 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003385 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003386 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3387 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3388 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003389 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003390 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3391 false),
3392 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3393 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3394 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3395 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3396 false),
3397 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3398 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3399 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003400 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003401 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3402 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3403 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3404 false),
3405 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3406 false),
3407 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3408 false),
3409 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3410 false),
3411 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3412 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3413 false),
3414 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3415 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003416 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003417 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003418 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003419 /* PKT Sample trap */
3420 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003421 false, SP_IP2ME, DISCARD),
3422 /* ACL trap */
3423 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003424 /* Multicast Router Traps */
3425 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3426 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3427 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003428};
3429
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003430static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3431{
3432 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3433 enum mlxsw_reg_qpcr_ir_units ir_units;
3434 int max_cpu_policers;
3435 bool is_bytes;
3436 u8 burst_size;
3437 u32 rate;
3438 int i, err;
3439
3440 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3441 return -EIO;
3442
3443 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3444
3445 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3446 for (i = 0; i < max_cpu_policers; i++) {
3447 is_bytes = false;
3448 switch (i) {
3449 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3450 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3451 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3452 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003453 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3454 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003455 rate = 128;
3456 burst_size = 7;
3457 break;
3458 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003459 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003460 rate = 16 * 1024;
3461 burst_size = 10;
3462 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003463 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003464 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3465 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003466 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003467 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3468 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003469 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003470 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003471 rate = 1024;
3472 burst_size = 7;
3473 break;
3474 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3475 is_bytes = true;
3476 rate = 4 * 1024;
3477 burst_size = 4;
3478 break;
3479 default:
3480 continue;
3481 }
3482
3483 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3484 burst_size);
3485 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3486 if (err)
3487 return err;
3488 }
3489
3490 return 0;
3491}
3492
Nogah Frankel579c82e2016-11-25 10:33:42 +01003493static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003494{
3495 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003496 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003497 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003498 int max_trap_groups;
3499 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003500 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003501 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003502
3503 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3504 return -EIO;
3505
3506 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003507 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003508
3509 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003510 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003511 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003512 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3513 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3514 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3515 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003516 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003517 priority = 5;
3518 tc = 5;
3519 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003520 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003521 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3522 priority = 4;
3523 tc = 4;
3524 break;
3525 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3526 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003527 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003528 priority = 3;
3529 tc = 3;
3530 break;
3531 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003532 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003533 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003534 priority = 2;
3535 tc = 2;
3536 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003537 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003538 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3539 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003540 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003541 priority = 1;
3542 tc = 1;
3543 break;
3544 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003545 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3546 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003547 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003548 break;
3549 default:
3550 continue;
3551 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003552
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003553 if (max_cpu_policers <= policer_id &&
3554 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3555 return -EIO;
3556
3557 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003558 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3559 if (err)
3560 return err;
3561 }
3562
3563 return 0;
3564}
3565
3566static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3567{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003568 int i;
3569 int err;
3570
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003571 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3572 if (err)
3573 return err;
3574
Nogah Frankel579c82e2016-11-25 10:33:42 +01003575 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003576 if (err)
3577 return err;
3578
Nogah Frankel45449132016-11-25 10:33:35 +01003579 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003580 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003581 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003582 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003583 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003584 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003585
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003586 }
3587 return 0;
3588
Nogah Frankel45449132016-11-25 10:33:35 +01003589err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003590 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003591 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003592 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003593 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003594 }
3595 return err;
3596}
3597
3598static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3599{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003600 int i;
3601
Nogah Frankel45449132016-11-25 10:33:35 +01003602 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003603 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003604 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003605 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003606 }
3607}
3608
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003609static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3610{
3611 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003612 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003613
3614 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3615 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3616 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3617 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3618 MLXSW_REG_SLCR_LAG_HASH_SIP |
3619 MLXSW_REG_SLCR_LAG_HASH_DIP |
3620 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3621 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3622 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003623 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3624 if (err)
3625 return err;
3626
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003627 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3628 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003629 return -EIO;
3630
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003631 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003632 sizeof(struct mlxsw_sp_upper),
3633 GFP_KERNEL);
3634 if (!mlxsw_sp->lags)
3635 return -ENOMEM;
3636
3637 return 0;
3638}
3639
3640static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3641{
3642 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003643}
3644
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003645static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3646{
3647 char htgt_pl[MLXSW_REG_HTGT_LEN];
3648
Nogah Frankel579c82e2016-11-25 10:33:42 +01003649 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3650 MLXSW_REG_HTGT_INVALID_POLICER,
3651 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3652 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003653 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3654}
3655
Jiri Pirkob2f10572016-04-08 19:11:23 +02003656static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003657 const struct mlxsw_bus_info *mlxsw_bus_info)
3658{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003659 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003660 int err;
3661
3662 mlxsw_sp->core = mlxsw_core;
3663 mlxsw_sp->bus_info = mlxsw_bus_info;
3664
Yotam Gigi6b742192017-05-23 21:56:29 +02003665 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3666 if (err) {
3667 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3668 return err;
3669 }
3670
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003671 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3672 if (err) {
3673 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3674 return err;
3675 }
3676
Ido Schimmela1107482017-05-26 08:37:39 +02003677 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003678 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003679 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Nogah Frankel45449132016-11-25 10:33:35 +01003680 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003681 }
3682
Ido Schimmela1107482017-05-26 08:37:39 +02003683 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003684 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003685 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3686 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003687 }
3688
3689 err = mlxsw_sp_buffers_init(mlxsw_sp);
3690 if (err) {
3691 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3692 goto err_buffers_init;
3693 }
3694
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003695 err = mlxsw_sp_lag_init(mlxsw_sp);
3696 if (err) {
3697 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3698 goto err_lag_init;
3699 }
3700
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003701 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3702 if (err) {
3703 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3704 goto err_switchdev_init;
3705 }
3706
Yotam Gigie2b2d352017-09-19 10:00:08 +02003707 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3708 if (err) {
3709 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3710 goto err_counter_pool_init;
3711 }
3712
Yotam Gigid3b939b2017-09-19 10:00:09 +02003713 err = mlxsw_sp_afa_init(mlxsw_sp);
3714 if (err) {
3715 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3716 goto err_afa_init;
3717 }
3718
Ido Schimmel464dce12016-07-02 11:00:15 +02003719 err = mlxsw_sp_router_init(mlxsw_sp);
3720 if (err) {
3721 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3722 goto err_router_init;
3723 }
3724
Yotam Gigi763b4b72016-07-21 12:03:17 +02003725 err = mlxsw_sp_span_init(mlxsw_sp);
3726 if (err) {
3727 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3728 goto err_span_init;
3729 }
3730
Jiri Pirko22a67762017-02-03 10:29:07 +01003731 err = mlxsw_sp_acl_init(mlxsw_sp);
3732 if (err) {
3733 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3734 goto err_acl_init;
3735 }
3736
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003737 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3738 if (err) {
3739 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3740 goto err_dpipe_init;
3741 }
3742
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003743 err = mlxsw_sp_ports_create(mlxsw_sp);
3744 if (err) {
3745 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3746 goto err_ports_create;
3747 }
3748
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003749 return 0;
3750
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003751err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003752 mlxsw_sp_dpipe_fini(mlxsw_sp);
3753err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003754 mlxsw_sp_acl_fini(mlxsw_sp);
3755err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02003756 mlxsw_sp_span_fini(mlxsw_sp);
3757err_span_init:
Ido Schimmel464dce12016-07-02 11:00:15 +02003758 mlxsw_sp_router_fini(mlxsw_sp);
3759err_router_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02003760 mlxsw_sp_afa_fini(mlxsw_sp);
3761err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02003762 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3763err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003764 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003765err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003766 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003767err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003768 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003769err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003770 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003771err_traps_init:
3772 mlxsw_sp_fids_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003773 return err;
3774}
3775
Jiri Pirkob2f10572016-04-08 19:11:23 +02003776static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003777{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003778 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003779
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003780 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003781 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003782 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003783 mlxsw_sp_span_fini(mlxsw_sp);
Ido Schimmel464dce12016-07-02 11:00:15 +02003784 mlxsw_sp_router_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02003785 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02003786 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003787 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003788 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003789 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003790 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003791 mlxsw_sp_fids_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003792}
3793
Bhumika Goyal159fe882017-08-11 19:10:42 +05303794static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003795 .used_max_vepa_channels = 1,
3796 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003797 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003798 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003799 .used_max_pgt = 1,
3800 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003801 .used_flood_tables = 1,
3802 .used_flood_mode = 1,
3803 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003804 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003805 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003806 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02003807 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003808 .used_max_ib_mc = 1,
3809 .max_ib_mc = 0,
3810 .used_max_pkey = 1,
3811 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003812 .used_kvd_split_data = 1,
3813 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3814 .kvd_hash_single_parts = 2,
3815 .kvd_hash_double_parts = 1,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003816 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003817 .swid_config = {
3818 {
3819 .used_type = 1,
3820 .type = MLXSW_PORT_SWID_TYPE_ETH,
3821 }
3822 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003823 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003824};
3825
3826static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003827 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003828 .priv_size = sizeof(struct mlxsw_sp),
3829 .init = mlxsw_sp_init,
3830 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003831 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003832 .port_split = mlxsw_sp_port_split,
3833 .port_unsplit = mlxsw_sp_port_unsplit,
3834 .sb_pool_get = mlxsw_sp_sb_pool_get,
3835 .sb_pool_set = mlxsw_sp_sb_pool_set,
3836 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3837 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3838 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3839 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3840 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3841 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3842 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3843 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3844 .txhdr_construct = mlxsw_sp_txhdr_construct,
3845 .txhdr_len = MLXSW_TXHDR_LEN,
3846 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003847};
3848
Jiri Pirko22a67762017-02-03 10:29:07 +01003849bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003850{
3851 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3852}
3853
Jiri Pirko1182e532017-03-06 21:25:20 +01003854static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07003855{
Jiri Pirko1182e532017-03-06 21:25:20 +01003856 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07003857 int ret = 0;
3858
3859 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01003860 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07003861 ret = 1;
3862 }
3863
3864 return ret;
3865}
3866
Ido Schimmelc57529e2017-05-26 08:37:31 +02003867struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003868{
Jiri Pirko1182e532017-03-06 21:25:20 +01003869 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003870
3871 if (mlxsw_sp_port_dev_check(dev))
3872 return netdev_priv(dev);
3873
Jiri Pirko1182e532017-03-06 21:25:20 +01003874 mlxsw_sp_port = NULL;
3875 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003876
Jiri Pirko1182e532017-03-06 21:25:20 +01003877 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003878}
3879
Ido Schimmel4724ba562017-03-10 08:53:39 +01003880struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003881{
3882 struct mlxsw_sp_port *mlxsw_sp_port;
3883
3884 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3885 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3886}
3887
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02003888struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003889{
Jiri Pirko1182e532017-03-06 21:25:20 +01003890 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003891
3892 if (mlxsw_sp_port_dev_check(dev))
3893 return netdev_priv(dev);
3894
Jiri Pirko1182e532017-03-06 21:25:20 +01003895 mlxsw_sp_port = NULL;
3896 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
3897 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003898
Jiri Pirko1182e532017-03-06 21:25:20 +01003899 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003900}
3901
3902struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3903{
3904 struct mlxsw_sp_port *mlxsw_sp_port;
3905
3906 rcu_read_lock();
3907 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3908 if (mlxsw_sp_port)
3909 dev_hold(mlxsw_sp_port->dev);
3910 rcu_read_unlock();
3911 return mlxsw_sp_port;
3912}
3913
3914void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3915{
3916 dev_put(mlxsw_sp_port->dev);
3917}
3918
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003919static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003920{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003921 char sldr_pl[MLXSW_REG_SLDR_LEN];
3922
3923 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
3924 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3925}
3926
3927static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
3928{
3929 char sldr_pl[MLXSW_REG_SLDR_LEN];
3930
3931 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
3932 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
3933}
3934
3935static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
3936 u16 lag_id, u8 port_index)
3937{
3938 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3939 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3940
3941 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
3942 lag_id, port_index);
3943 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3944}
3945
3946static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
3947 u16 lag_id)
3948{
3949 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3950 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3951
3952 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
3953 lag_id);
3954 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3955}
3956
3957static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
3958 u16 lag_id)
3959{
3960 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3961 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3962
3963 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
3964 lag_id);
3965 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3966}
3967
3968static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
3969 u16 lag_id)
3970{
3971 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3972 char slcor_pl[MLXSW_REG_SLCOR_LEN];
3973
3974 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
3975 lag_id);
3976 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
3977}
3978
3979static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
3980 struct net_device *lag_dev,
3981 u16 *p_lag_id)
3982{
3983 struct mlxsw_sp_upper *lag;
3984 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003985 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003986 int i;
3987
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003988 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
3989 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003990 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
3991 if (lag->ref_count) {
3992 if (lag->dev == lag_dev) {
3993 *p_lag_id = i;
3994 return 0;
3995 }
3996 } else if (free_lag_id < 0) {
3997 free_lag_id = i;
3998 }
3999 }
4000 if (free_lag_id < 0)
4001 return -EBUSY;
4002 *p_lag_id = free_lag_id;
4003 return 0;
4004}
4005
4006static bool
4007mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4008 struct net_device *lag_dev,
4009 struct netdev_lag_upper_info *lag_upper_info)
4010{
4011 u16 lag_id;
4012
4013 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
4014 return false;
4015 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
4016 return false;
4017 return true;
4018}
4019
4020static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4021 u16 lag_id, u8 *p_port_index)
4022{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004023 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004024 int i;
4025
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004026 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4027 MAX_LAG_MEMBERS);
4028 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004029 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4030 *p_port_index = i;
4031 return 0;
4032 }
4033 }
4034 return -EBUSY;
4035}
4036
4037static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4038 struct net_device *lag_dev)
4039{
4040 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004041 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004042 struct mlxsw_sp_upper *lag;
4043 u16 lag_id;
4044 u8 port_index;
4045 int err;
4046
4047 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4048 if (err)
4049 return err;
4050 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4051 if (!lag->ref_count) {
4052 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4053 if (err)
4054 return err;
4055 lag->dev = lag_dev;
4056 }
4057
4058 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4059 if (err)
4060 return err;
4061 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4062 if (err)
4063 goto err_col_port_add;
4064 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4065 if (err)
4066 goto err_col_port_enable;
4067
4068 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4069 mlxsw_sp_port->local_port);
4070 mlxsw_sp_port->lag_id = lag_id;
4071 mlxsw_sp_port->lagged = 1;
4072 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004073
Ido Schimmelc57529e2017-05-26 08:37:31 +02004074 /* Port is no longer usable as a router interface */
4075 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4076 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004077 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004078
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004079 return 0;
4080
Ido Schimmel51554db2016-05-06 22:18:39 +02004081err_col_port_enable:
4082 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004083err_col_port_add:
4084 if (!lag->ref_count)
4085 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004086 return err;
4087}
4088
Ido Schimmel82e6db02016-06-20 23:04:04 +02004089static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4090 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004091{
4092 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004093 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004094 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004095
4096 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004097 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004098 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4099 WARN_ON(lag->ref_count == 0);
4100
Ido Schimmel82e6db02016-06-20 23:04:04 +02004101 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4102 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004103
Ido Schimmelc57529e2017-05-26 08:37:31 +02004104 /* Any VLANs configured on the port are no longer valid */
4105 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004106
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004107 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004108 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004109
4110 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4111 mlxsw_sp_port->local_port);
4112 mlxsw_sp_port->lagged = 0;
4113 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004114
Ido Schimmelc57529e2017-05-26 08:37:31 +02004115 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4116 /* Make sure untagged frames are allowed to ingress */
4117 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004118}
4119
Jiri Pirko74581202015-12-03 12:12:30 +01004120static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4121 u16 lag_id)
4122{
4123 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4124 char sldr_pl[MLXSW_REG_SLDR_LEN];
4125
4126 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4127 mlxsw_sp_port->local_port);
4128 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4129}
4130
4131static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4132 u16 lag_id)
4133{
4134 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4135 char sldr_pl[MLXSW_REG_SLDR_LEN];
4136
4137 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4138 mlxsw_sp_port->local_port);
4139 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4140}
4141
4142static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4143 bool lag_tx_enabled)
4144{
4145 if (lag_tx_enabled)
4146 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4147 mlxsw_sp_port->lag_id);
4148 else
4149 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4150 mlxsw_sp_port->lag_id);
4151}
4152
4153static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4154 struct netdev_lag_lower_state_info *info)
4155{
4156 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4157}
4158
Jiri Pirko2b94e582017-04-18 16:55:37 +02004159static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4160 bool enable)
4161{
4162 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4163 enum mlxsw_reg_spms_state spms_state;
4164 char *spms_pl;
4165 u16 vid;
4166 int err;
4167
4168 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4169 MLXSW_REG_SPMS_STATE_DISCARDING;
4170
4171 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4172 if (!spms_pl)
4173 return -ENOMEM;
4174 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4175
4176 for (vid = 0; vid < VLAN_N_VID; vid++)
4177 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4178
4179 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4180 kfree(spms_pl);
4181 return err;
4182}
4183
4184static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4185{
4186 int err;
4187
Ido Schimmel4aafc362017-05-26 08:37:25 +02004188 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004189 if (err)
4190 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004191 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4192 if (err)
4193 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004194 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4195 true, false);
4196 if (err)
4197 goto err_port_vlan_set;
4198 return 0;
4199
4200err_port_vlan_set:
4201 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004202err_port_stp_set:
4203 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004204 return err;
4205}
4206
4207static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4208{
4209 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4210 false, false);
4211 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004212 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004213}
4214
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004215static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4216 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004217 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004218{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004219 struct netdev_notifier_changeupper_info *info;
4220 struct mlxsw_sp_port *mlxsw_sp_port;
4221 struct net_device *upper_dev;
4222 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004223 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004224
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004225 mlxsw_sp_port = netdev_priv(dev);
4226 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4227 info = ptr;
4228
4229 switch (event) {
4230 case NETDEV_PRECHANGEUPPER:
4231 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004232 if (!is_vlan_dev(upper_dev) &&
4233 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004234 !netif_is_bridge_master(upper_dev) &&
Jiri Pirko2b94e582017-04-18 16:55:37 +02004235 !netif_is_ovs_master(upper_dev))
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004236 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004237 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004238 break;
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004239 if (netdev_has_any_upper_dev(upper_dev))
4240 return -EINVAL;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004241 if (netif_is_lag_master(upper_dev) &&
4242 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4243 info->upper_info))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004244 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004245 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4246 return -EINVAL;
4247 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4248 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4249 return -EINVAL;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004250 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev))
4251 return -EINVAL;
4252 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev))
4253 return -EINVAL;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004254 break;
4255 case NETDEV_CHANGEUPPER:
4256 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004257 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004258 if (info->linking)
4259 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004260 lower_dev,
Ido Schimmel7117a572016-06-20 23:04:06 +02004261 upper_dev);
4262 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004263 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4264 lower_dev,
4265 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004266 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004267 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004268 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4269 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004270 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004271 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4272 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004273 } else if (netif_is_ovs_master(upper_dev)) {
4274 if (info->linking)
4275 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4276 else
4277 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004278 }
4279 break;
4280 }
4281
Ido Schimmel80bedf12016-06-20 23:03:59 +02004282 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004283}
4284
Jiri Pirko74581202015-12-03 12:12:30 +01004285static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4286 unsigned long event, void *ptr)
4287{
4288 struct netdev_notifier_changelowerstate_info *info;
4289 struct mlxsw_sp_port *mlxsw_sp_port;
4290 int err;
4291
4292 mlxsw_sp_port = netdev_priv(dev);
4293 info = ptr;
4294
4295 switch (event) {
4296 case NETDEV_CHANGELOWERSTATE:
4297 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4298 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4299 info->lower_state_info);
4300 if (err)
4301 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4302 }
4303 break;
4304 }
4305
Ido Schimmel80bedf12016-06-20 23:03:59 +02004306 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004307}
4308
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004309static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4310 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004311 unsigned long event, void *ptr)
4312{
4313 switch (event) {
4314 case NETDEV_PRECHANGEUPPER:
4315 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004316 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4317 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004318 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004319 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4320 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004321 }
4322
Ido Schimmel80bedf12016-06-20 23:03:59 +02004323 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004324}
4325
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004326static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4327 unsigned long event, void *ptr)
4328{
4329 struct net_device *dev;
4330 struct list_head *iter;
4331 int ret;
4332
4333 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4334 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004335 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4336 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004337 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004338 return ret;
4339 }
4340 }
4341
Ido Schimmel80bedf12016-06-20 23:03:59 +02004342 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004343}
4344
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004345static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4346 struct net_device *dev,
4347 unsigned long event, void *ptr,
4348 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004349{
4350 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4351 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004352 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004353 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004354
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004355 switch (event) {
4356 case NETDEV_PRECHANGEUPPER:
4357 upper_dev = info->upper_dev;
Ido Schimmelb1e45522017-04-30 19:47:14 +03004358 if (!netif_is_bridge_master(upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004359 return -EINVAL;
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004360 if (!info->linking)
4361 break;
4362 if (netdev_has_any_upper_dev(upper_dev))
4363 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004364 break;
4365 case NETDEV_CHANGEUPPER:
4366 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004367 if (netif_is_bridge_master(upper_dev)) {
4368 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004369 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4370 vlan_dev,
4371 upper_dev);
Ido Schimmel1f880612017-03-10 08:53:35 +01004372 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004373 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4374 vlan_dev,
4375 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004376 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004377 err = -EINVAL;
4378 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004379 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004380 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004381 }
4382
Ido Schimmel80bedf12016-06-20 23:03:59 +02004383 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004384}
4385
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004386static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4387 struct net_device *lag_dev,
4388 unsigned long event,
4389 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004390{
4391 struct net_device *dev;
4392 struct list_head *iter;
4393 int ret;
4394
4395 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4396 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004397 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4398 event, ptr,
4399 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004400 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004401 return ret;
4402 }
4403 }
4404
Ido Schimmel80bedf12016-06-20 23:03:59 +02004405 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004406}
4407
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004408static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4409 unsigned long event, void *ptr)
4410{
4411 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4412 u16 vid = vlan_dev_vlan_id(vlan_dev);
4413
Ido Schimmel272c4472015-12-15 16:03:47 +01004414 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004415 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4416 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01004417 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004418 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4419 real_dev, event,
4420 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004421
Ido Schimmel80bedf12016-06-20 23:03:59 +02004422 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004423}
4424
Ido Schimmelb1e45522017-04-30 19:47:14 +03004425static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4426{
4427 struct netdev_notifier_changeupper_info *info = ptr;
4428
4429 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4430 return false;
4431 return netif_is_l3_master(info->upper_dev);
4432}
4433
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004434static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4435 unsigned long event, void *ptr)
4436{
4437 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004438 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004439
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004440 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4441 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004442 else if (mlxsw_sp_is_vrf_event(event, ptr))
4443 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004444 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004445 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004446 else if (netif_is_lag_master(dev))
4447 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4448 else if (is_vlan_dev(dev))
4449 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004450
Ido Schimmel80bedf12016-06-20 23:03:59 +02004451 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004452}
4453
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004454static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
4455 .notifier_call = mlxsw_sp_netdevice_event,
4456};
4457
Ido Schimmel99724c12016-07-04 08:23:14 +02004458static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4459 .notifier_call = mlxsw_sp_inetaddr_event,
4460 .priority = 10, /* Must be called before FIB notifier block */
4461};
4462
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004463static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4464 .notifier_call = mlxsw_sp_inet6addr_event,
4465};
4466
Jiri Pirkoe7322632016-09-01 10:37:43 +02004467static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
4468 .notifier_call = mlxsw_sp_router_netevent_event,
4469};
4470
Jiri Pirko1d20d232016-10-27 15:12:59 +02004471static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4472 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4473 {0, },
4474};
4475
4476static struct pci_driver mlxsw_sp_pci_driver = {
4477 .name = mlxsw_sp_driver_name,
4478 .id_table = mlxsw_sp_pci_id_table,
4479};
4480
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004481static int __init mlxsw_sp_module_init(void)
4482{
4483 int err;
4484
4485 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004486 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004487 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004488 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
4489
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004490 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4491 if (err)
4492 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004493
4494 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4495 if (err)
4496 goto err_pci_driver_register;
4497
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004498 return 0;
4499
Jiri Pirko1d20d232016-10-27 15:12:59 +02004500err_pci_driver_register:
4501 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004502err_core_driver_register:
Jiri Pirkoe7322632016-09-01 10:37:43 +02004503 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004504 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004505 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004506 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4507 return err;
4508}
4509
4510static void __exit mlxsw_sp_module_exit(void)
4511{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004512 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004513 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004514 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004515 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004516 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004517 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
4518}
4519
4520module_init(mlxsw_sp_module_init);
4521module_exit(mlxsw_sp_module_exit);
4522
4523MODULE_LICENSE("Dual BSD/GPL");
4524MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4525MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004526MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02004527MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);