blob: e04d2ed34d7ef0e64ab014beac887880843dbe17 [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020056#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020057#include <net/pkt_cls.h>
58#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020059#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010060#include <net/tc_act/tc_sample.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020061
62#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020063#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020064#include "core.h"
65#include "reg.h"
66#include "port.h"
67#include "trap.h"
68#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010069#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020070#include "spectrum_dpipe.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020071#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020072
Yotam Gigi6b742192017-05-23 21:56:29 +020073#define MLXSW_FWREV_MAJOR 13
74#define MLXSW_FWREV_MINOR 1420
75#define MLXSW_FWREV_SUBMINOR 122
76
77static const struct mlxsw_fw_rev mlxsw_sp_supported_fw_rev = {
78 .major = MLXSW_FWREV_MAJOR,
79 .minor = MLXSW_FWREV_MINOR,
80 .subminor = MLXSW_FWREV_SUBMINOR
81};
82
83#define MLXSW_SP_FW_FILENAME \
84 "mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
85 "." __stringify(MLXSW_FWREV_MINOR) \
86 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
87
Jiri Pirko56ade8f2015-10-16 14:01:37 +020088static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
89static const char mlxsw_sp_driver_version[] = "1.0";
90
91/* tx_hdr_version
92 * Tx header version.
93 * Must be set to 1.
94 */
95MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
96
97/* tx_hdr_ctl
98 * Packet control type.
99 * 0 - Ethernet control (e.g. EMADs, LACP)
100 * 1 - Ethernet data
101 */
102MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
103
104/* tx_hdr_proto
105 * Packet protocol type. Must be set to 1 (Ethernet).
106 */
107MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
108
109/* tx_hdr_rx_is_router
110 * Packet is sent from the router. Valid for data packets only.
111 */
112MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
113
114/* tx_hdr_fid_valid
115 * Indicates if the 'fid' field is valid and should be used for
116 * forwarding lookup. Valid for data packets only.
117 */
118MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
119
120/* tx_hdr_swid
121 * Switch partition ID. Must be set to 0.
122 */
123MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
124
125/* tx_hdr_control_tclass
126 * Indicates if the packet should use the control TClass and not one
127 * of the data TClasses.
128 */
129MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
130
131/* tx_hdr_etclass
132 * Egress TClass to be used on the egress device on the egress port.
133 */
134MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
135
136/* tx_hdr_port_mid
137 * Destination local port for unicast packets.
138 * Destination multicast ID for multicast packets.
139 *
140 * Control packets are directed to a specific egress port, while data
141 * packets are transmitted through the CPU port (0) into the switch partition,
142 * where forwarding rules are applied.
143 */
144MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
145
146/* tx_hdr_fid
147 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
148 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
149 * Valid for data packets only.
150 */
151MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
152
153/* tx_hdr_type
154 * 0 - Data packets
155 * 6 - Control packets
156 */
157MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
158
Yotam Gigie5e5c882017-05-23 21:56:27 +0200159struct mlxsw_sp_mlxfw_dev {
160 struct mlxfw_dev mlxfw_dev;
161 struct mlxsw_sp *mlxsw_sp;
162};
163
164static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
165 u16 component_index, u32 *p_max_size,
166 u8 *p_align_bits, u16 *p_max_write_size)
167{
168 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
169 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
170 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
171 char mcqi_pl[MLXSW_REG_MCQI_LEN];
172 int err;
173
174 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
175 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
176 if (err)
177 return err;
178 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
179 p_max_write_size);
180
181 *p_align_bits = max_t(u8, *p_align_bits, 2);
182 *p_max_write_size = min_t(u16, *p_max_write_size,
183 MLXSW_REG_MCDA_MAX_DATA_LEN);
184 return 0;
185}
186
187static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
188{
189 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
190 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
191 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
192 char mcc_pl[MLXSW_REG_MCC_LEN];
193 u8 control_state;
194 int err;
195
196 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
197 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
198 if (err)
199 return err;
200
201 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
202 if (control_state != MLXFW_FSM_STATE_IDLE)
203 return -EBUSY;
204
205 mlxsw_reg_mcc_pack(mcc_pl,
206 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
207 0, *fwhandle, 0);
208 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
209}
210
211static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
212 u32 fwhandle, u16 component_index,
213 u32 component_size)
214{
215 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
216 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
217 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
218 char mcc_pl[MLXSW_REG_MCC_LEN];
219
220 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
221 component_index, fwhandle, component_size);
222 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
223}
224
225static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
226 u32 fwhandle, u8 *data, u16 size,
227 u32 offset)
228{
229 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
230 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
231 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
232 char mcda_pl[MLXSW_REG_MCDA_LEN];
233
234 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
235 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
236}
237
238static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
239 u32 fwhandle, u16 component_index)
240{
241 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
242 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
243 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
244 char mcc_pl[MLXSW_REG_MCC_LEN];
245
246 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
247 component_index, fwhandle, 0);
248 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
249}
250
251static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
252{
253 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
254 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
255 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
256 char mcc_pl[MLXSW_REG_MCC_LEN];
257
258 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
259 fwhandle, 0);
260 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
261}
262
263static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
264 enum mlxfw_fsm_state *fsm_state,
265 enum mlxfw_fsm_state_err *fsm_state_err)
266{
267 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
268 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
269 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
270 char mcc_pl[MLXSW_REG_MCC_LEN];
271 u8 control_state;
272 u8 error_code;
273 int err;
274
275 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
276 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
277 if (err)
278 return err;
279
280 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
281 *fsm_state = control_state;
282 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
283 MLXFW_FSM_STATE_ERR_MAX);
284 return 0;
285}
286
287static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
288{
289 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
290 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
291 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
292 char mcc_pl[MLXSW_REG_MCC_LEN];
293
294 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
295 fwhandle, 0);
296 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
297}
298
299static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
300{
301 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
302 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
303 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
304 char mcc_pl[MLXSW_REG_MCC_LEN];
305
306 mlxsw_reg_mcc_pack(mcc_pl,
307 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
308 fwhandle, 0);
309 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
310}
311
312static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
313 .component_query = mlxsw_sp_component_query,
314 .fsm_lock = mlxsw_sp_fsm_lock,
315 .fsm_component_update = mlxsw_sp_fsm_component_update,
316 .fsm_block_download = mlxsw_sp_fsm_block_download,
317 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
318 .fsm_activate = mlxsw_sp_fsm_activate,
319 .fsm_query_state = mlxsw_sp_fsm_query_state,
320 .fsm_cancel = mlxsw_sp_fsm_cancel,
321 .fsm_release = mlxsw_sp_fsm_release
322};
323
Yotam Gigi6b742192017-05-23 21:56:29 +0200324static bool mlxsw_sp_fw_rev_ge(const struct mlxsw_fw_rev *a,
325 const struct mlxsw_fw_rev *b)
326{
327 if (a->major != b->major)
328 return a->major > b->major;
329 if (a->minor != b->minor)
330 return a->minor > b->minor;
331 return a->subminor >= b->subminor;
332}
333
334static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
335{
336 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
337 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
338 .mlxfw_dev = {
339 .ops = &mlxsw_sp_mlxfw_dev_ops,
340 .psid = mlxsw_sp->bus_info->psid,
341 .psid_size = strlen(mlxsw_sp->bus_info->psid),
342 },
343 .mlxsw_sp = mlxsw_sp
344 };
345 const struct firmware *firmware;
346 int err;
347
348 if (mlxsw_sp_fw_rev_ge(rev, &mlxsw_sp_supported_fw_rev))
349 return 0;
350
351 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d out of data\n",
352 rev->major, rev->minor, rev->subminor);
353 dev_info(mlxsw_sp->bus_info->dev, "Upgrading firmware using file %s\n",
354 MLXSW_SP_FW_FILENAME);
355
356 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
357 mlxsw_sp->bus_info->dev);
358 if (err) {
359 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
360 MLXSW_SP_FW_FILENAME);
361 return err;
362 }
363
364 err = mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
365 release_firmware(firmware);
366 return err;
367}
368
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100369int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
370 unsigned int counter_index, u64 *packets,
371 u64 *bytes)
372{
373 char mgpc_pl[MLXSW_REG_MGPC_LEN];
374 int err;
375
376 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
377 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
378 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
379 if (err)
380 return err;
381 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
382 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
383 return 0;
384}
385
386static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
387 unsigned int counter_index)
388{
389 char mgpc_pl[MLXSW_REG_MGPC_LEN];
390
391 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
392 MLXSW_REG_MGPC_COUNTER_SET_TYPE_PACKETS_BYTES);
393 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
394}
395
396int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
397 unsigned int *p_counter_index)
398{
399 int err;
400
401 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
402 p_counter_index);
403 if (err)
404 return err;
405 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
406 if (err)
407 goto err_counter_clear;
408 return 0;
409
410err_counter_clear:
411 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
412 *p_counter_index);
413 return err;
414}
415
416void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
417 unsigned int counter_index)
418{
419 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
420 counter_index);
421}
422
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200423static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
424 const struct mlxsw_tx_info *tx_info)
425{
426 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
427
428 memset(txhdr, 0, MLXSW_TXHDR_LEN);
429
430 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
431 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
432 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
433 mlxsw_tx_hdr_swid_set(txhdr, 0);
434 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
435 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
436 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
437}
438
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200439int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
440 u8 state)
441{
442 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
443 enum mlxsw_reg_spms_state spms_state;
444 char *spms_pl;
445 int err;
446
447 switch (state) {
448 case BR_STATE_FORWARDING:
449 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
450 break;
451 case BR_STATE_LEARNING:
452 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
453 break;
454 case BR_STATE_LISTENING: /* fall-through */
455 case BR_STATE_DISABLED: /* fall-through */
456 case BR_STATE_BLOCKING:
457 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
458 break;
459 default:
460 BUG();
461 }
462
463 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
464 if (!spms_pl)
465 return -ENOMEM;
466 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
467 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
468
469 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
470 kfree(spms_pl);
471 return err;
472}
473
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200474static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
475{
Elad Raz5b090742016-10-28 21:35:46 +0200476 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200477 int err;
478
479 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
480 if (err)
481 return err;
482 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
483 return 0;
484}
485
Yotam Gigi763b4b72016-07-21 12:03:17 +0200486static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
487{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200488 int i;
489
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200490 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200491 return -EIO;
492
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200493 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
494 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200495 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
496 sizeof(struct mlxsw_sp_span_entry),
497 GFP_KERNEL);
498 if (!mlxsw_sp->span.entries)
499 return -ENOMEM;
500
501 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
502 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
503
504 return 0;
505}
506
507static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
508{
509 int i;
510
511 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
512 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
513
514 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
515 }
516 kfree(mlxsw_sp->span.entries);
517}
518
519static struct mlxsw_sp_span_entry *
520mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
521{
522 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
523 struct mlxsw_sp_span_entry *span_entry;
524 char mpat_pl[MLXSW_REG_MPAT_LEN];
525 u8 local_port = port->local_port;
526 int index;
527 int i;
528 int err;
529
530 /* find a free entry to use */
531 index = -1;
532 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
533 if (!mlxsw_sp->span.entries[i].used) {
534 index = i;
535 span_entry = &mlxsw_sp->span.entries[i];
536 break;
537 }
538 }
539 if (index < 0)
540 return NULL;
541
542 /* create a new port analayzer entry for local_port */
543 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
544 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
545 if (err)
546 return NULL;
547
548 span_entry->used = true;
549 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100550 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200551 span_entry->local_port = local_port;
552 return span_entry;
553}
554
555static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
556 struct mlxsw_sp_span_entry *span_entry)
557{
558 u8 local_port = span_entry->local_port;
559 char mpat_pl[MLXSW_REG_MPAT_LEN];
560 int pa_id = span_entry->id;
561
562 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
563 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
564 span_entry->used = false;
565}
566
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200567static struct mlxsw_sp_span_entry *
568mlxsw_sp_span_entry_find(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200569{
570 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
571 int i;
572
573 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
574 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
575
576 if (curr->used && curr->local_port == port->local_port)
577 return curr;
578 }
579 return NULL;
580}
581
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200582static struct mlxsw_sp_span_entry
583*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200584{
585 struct mlxsw_sp_span_entry *span_entry;
586
587 span_entry = mlxsw_sp_span_entry_find(port);
588 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100589 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200590 span_entry->ref_count++;
591 return span_entry;
592 }
593
594 return mlxsw_sp_span_entry_create(port);
595}
596
597static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
598 struct mlxsw_sp_span_entry *span_entry)
599{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100600 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200601 if (--span_entry->ref_count == 0)
602 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
603 return 0;
604}
605
606static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
607{
608 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
609 struct mlxsw_sp_span_inspected_port *p;
610 int i;
611
612 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
613 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
614
615 list_for_each_entry(p, &curr->bound_ports_list, list)
616 if (p->local_port == port->local_port &&
617 p->type == MLXSW_SP_SPAN_EGRESS)
618 return true;
619 }
620
621 return false;
622}
623
Ido Schimmel18281f22017-03-24 08:02:51 +0100624static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
625 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200626{
Ido Schimmel18281f22017-03-24 08:02:51 +0100627 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200628}
629
630static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
631{
632 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
633 char sbib_pl[MLXSW_REG_SBIB_LEN];
634 int err;
635
636 /* If port is egress mirrored, the shared buffer size should be
637 * updated according to the mtu value
638 */
639 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100640 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
641
642 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200643 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
644 if (err) {
645 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
646 return err;
647 }
648 }
649
650 return 0;
651}
652
653static struct mlxsw_sp_span_inspected_port *
654mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
655 struct mlxsw_sp_span_entry *span_entry)
656{
657 struct mlxsw_sp_span_inspected_port *p;
658
659 list_for_each_entry(p, &span_entry->bound_ports_list, list)
660 if (port->local_port == p->local_port)
661 return p;
662 return NULL;
663}
664
665static int
666mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
667 struct mlxsw_sp_span_entry *span_entry,
668 enum mlxsw_sp_span_type type)
669{
670 struct mlxsw_sp_span_inspected_port *inspected_port;
671 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
672 char mpar_pl[MLXSW_REG_MPAR_LEN];
673 char sbib_pl[MLXSW_REG_SBIB_LEN];
674 int pa_id = span_entry->id;
675 int err;
676
677 /* if it is an egress SPAN, bind a shared buffer to it */
678 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100679 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
680 port->dev->mtu);
681
682 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200683 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
684 if (err) {
685 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
686 return err;
687 }
688 }
689
690 /* bind the port to the SPAN entry */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200691 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
692 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200693 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
694 if (err)
695 goto err_mpar_reg_write;
696
697 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
698 if (!inspected_port) {
699 err = -ENOMEM;
700 goto err_inspected_port_alloc;
701 }
702 inspected_port->local_port = port->local_port;
703 inspected_port->type = type;
704 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
705
706 return 0;
707
708err_mpar_reg_write:
709err_inspected_port_alloc:
710 if (type == MLXSW_SP_SPAN_EGRESS) {
711 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
712 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
713 }
714 return err;
715}
716
717static void
718mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
719 struct mlxsw_sp_span_entry *span_entry,
720 enum mlxsw_sp_span_type type)
721{
722 struct mlxsw_sp_span_inspected_port *inspected_port;
723 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
724 char mpar_pl[MLXSW_REG_MPAR_LEN];
725 char sbib_pl[MLXSW_REG_SBIB_LEN];
726 int pa_id = span_entry->id;
727
728 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
729 if (!inspected_port)
730 return;
731
732 /* remove the inspected port */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200733 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
734 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200735 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
736
737 /* remove the SBIB buffer if it was egress SPAN */
738 if (type == MLXSW_SP_SPAN_EGRESS) {
739 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
740 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
741 }
742
743 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
744
745 list_del(&inspected_port->list);
746 kfree(inspected_port);
747}
748
749static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
750 struct mlxsw_sp_port *to,
751 enum mlxsw_sp_span_type type)
752{
753 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
754 struct mlxsw_sp_span_entry *span_entry;
755 int err;
756
757 span_entry = mlxsw_sp_span_entry_get(to);
758 if (!span_entry)
759 return -ENOENT;
760
761 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
762 span_entry->id);
763
764 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
765 if (err)
766 goto err_port_bind;
767
768 return 0;
769
770err_port_bind:
771 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
772 return err;
773}
774
775static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
776 struct mlxsw_sp_port *to,
777 enum mlxsw_sp_span_type type)
778{
779 struct mlxsw_sp_span_entry *span_entry;
780
781 span_entry = mlxsw_sp_span_entry_find(to);
782 if (!span_entry) {
783 netdev_err(from->dev, "no span entry found\n");
784 return;
785 }
786
787 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
788 span_entry->id);
789 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
790}
791
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100792static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
793 bool enable, u32 rate)
794{
795 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
796 char mpsc_pl[MLXSW_REG_MPSC_LEN];
797
798 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
799 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
800}
801
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200802static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
803 bool is_up)
804{
805 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
806 char paos_pl[MLXSW_REG_PAOS_LEN];
807
808 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
809 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
810 MLXSW_PORT_ADMIN_STATUS_DOWN);
811 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
812}
813
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200814static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
815 unsigned char *addr)
816{
817 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
818 char ppad_pl[MLXSW_REG_PPAD_LEN];
819
820 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
821 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
822 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
823}
824
825static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
826{
827 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
828 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
829
830 ether_addr_copy(addr, mlxsw_sp->base_mac);
831 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
832 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
833}
834
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200835static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
836{
837 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
838 char pmtu_pl[MLXSW_REG_PMTU_LEN];
839 int max_mtu;
840 int err;
841
842 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
843 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
844 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
845 if (err)
846 return err;
847 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
848
849 if (mtu > max_mtu)
850 return -EINVAL;
851
852 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
853 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
854}
855
Ido Schimmelbe945352016-06-09 09:51:39 +0200856static int __mlxsw_sp_port_swid_set(struct mlxsw_sp *mlxsw_sp, u8 local_port,
857 u8 swid)
858{
859 char pspa_pl[MLXSW_REG_PSPA_LEN];
860
861 mlxsw_reg_pspa_pack(pspa_pl, swid, local_port);
862 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
863}
864
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200865static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
866{
867 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200868
Ido Schimmelbe945352016-06-09 09:51:39 +0200869 return __mlxsw_sp_port_swid_set(mlxsw_sp, mlxsw_sp_port->local_port,
870 swid);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200871}
872
873static int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
874 bool enable)
875{
876 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
877 char svpe_pl[MLXSW_REG_SVPE_LEN];
878
879 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
880 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
881}
882
883int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
884 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
885 u16 vid)
886{
887 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
888 char svfa_pl[MLXSW_REG_SVFA_LEN];
889
890 mlxsw_reg_svfa_pack(svfa_pl, mlxsw_sp_port->local_port, mt, valid,
891 fid, vid);
892 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svfa), svfa_pl);
893}
894
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200895int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
896 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200897{
898 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
899 char *spvmlr_pl;
900 int err;
901
902 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
903 if (!spvmlr_pl)
904 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200905 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
906 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200907 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
908 kfree(spvmlr_pl);
909 return err;
910}
911
Ido Schimmelb02eae92017-05-16 19:38:34 +0200912static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
913 u16 vid)
914{
915 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
916 char spvid_pl[MLXSW_REG_SPVID_LEN];
917
918 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
919 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
920}
921
922static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
923 bool allow)
924{
925 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
926 char spaft_pl[MLXSW_REG_SPAFT_LEN];
927
928 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
929 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
930}
931
932int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
933{
934 int err;
935
936 if (!vid) {
937 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
938 if (err)
939 return err;
940 } else {
941 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
942 if (err)
943 return err;
944 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
945 if (err)
946 goto err_port_allow_untagged_set;
947 }
948
949 mlxsw_sp_port->pvid = vid;
950 return 0;
951
952err_port_allow_untagged_set:
953 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
954 return err;
955}
956
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200957static int
958mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
959{
960 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
961 char sspr_pl[MLXSW_REG_SSPR_LEN];
962
963 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
964 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
965}
966
Ido Schimmeld664b412016-06-09 09:51:40 +0200967static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
968 u8 local_port, u8 *p_module,
969 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200970{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200971 char pmlp_pl[MLXSW_REG_PMLP_LEN];
972 int err;
973
Ido Schimmel558c2d52016-02-26 17:32:29 +0100974 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200975 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
976 if (err)
977 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100978 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
979 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200980 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200981 return 0;
982}
983
Ido Schimmel18f1e702016-02-26 17:32:31 +0100984static int mlxsw_sp_port_module_map(struct mlxsw_sp *mlxsw_sp, u8 local_port,
985 u8 module, u8 width, u8 lane)
986{
987 char pmlp_pl[MLXSW_REG_PMLP_LEN];
988 int i;
989
990 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
991 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
992 for (i = 0; i < width; i++) {
993 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
994 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
995 }
996
997 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
998}
999
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01001000static int mlxsw_sp_port_module_unmap(struct mlxsw_sp *mlxsw_sp, u8 local_port)
1001{
1002 char pmlp_pl[MLXSW_REG_PMLP_LEN];
1003
1004 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
1005 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
1006 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1007}
1008
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001009static int mlxsw_sp_port_open(struct net_device *dev)
1010{
1011 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1012 int err;
1013
1014 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1015 if (err)
1016 return err;
1017 netif_start_queue(dev);
1018 return 0;
1019}
1020
1021static int mlxsw_sp_port_stop(struct net_device *dev)
1022{
1023 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1024
1025 netif_stop_queue(dev);
1026 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1027}
1028
1029static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1030 struct net_device *dev)
1031{
1032 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1033 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1034 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1035 const struct mlxsw_tx_info tx_info = {
1036 .local_port = mlxsw_sp_port->local_port,
1037 .is_emad = false,
1038 };
1039 u64 len;
1040 int err;
1041
Jiri Pirko307c2432016-04-08 19:11:22 +02001042 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001043 return NETDEV_TX_BUSY;
1044
1045 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1046 struct sk_buff *skb_orig = skb;
1047
1048 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1049 if (!skb) {
1050 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1051 dev_kfree_skb_any(skb_orig);
1052 return NETDEV_TX_OK;
1053 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +01001054 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001055 }
1056
1057 if (eth_skb_pad(skb)) {
1058 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1059 return NETDEV_TX_OK;
1060 }
1061
1062 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +02001063 /* TX header is consumed by HW on the way so we shouldn't count its
1064 * bytes as being sent.
1065 */
1066 len = skb->len - MLXSW_TXHDR_LEN;
1067
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001068 /* Due to a race we might fail here because of a full queue. In that
1069 * unlikely case we simply drop the packet.
1070 */
Jiri Pirko307c2432016-04-08 19:11:22 +02001071 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001072
1073 if (!err) {
1074 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1075 u64_stats_update_begin(&pcpu_stats->syncp);
1076 pcpu_stats->tx_packets++;
1077 pcpu_stats->tx_bytes += len;
1078 u64_stats_update_end(&pcpu_stats->syncp);
1079 } else {
1080 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1081 dev_kfree_skb_any(skb);
1082 }
1083 return NETDEV_TX_OK;
1084}
1085
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001086static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1087{
1088}
1089
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001090static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1091{
1092 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1093 struct sockaddr *addr = p;
1094 int err;
1095
1096 if (!is_valid_ether_addr(addr->sa_data))
1097 return -EADDRNOTAVAIL;
1098
1099 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1100 if (err)
1101 return err;
1102 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1103 return 0;
1104}
1105
Ido Schimmel18281f22017-03-24 08:02:51 +01001106static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1107 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001108{
Ido Schimmel18281f22017-03-24 08:02:51 +01001109 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001110}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001111
Ido Schimmelf417f042017-03-24 08:02:50 +01001112#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +01001113
1114static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1115 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +01001116{
Ido Schimmel18281f22017-03-24 08:02:51 +01001117 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1118 BITS_PER_BYTE));
1119 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1120 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001121}
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001122
Ido Schimmel18281f22017-03-24 08:02:51 +01001123/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +01001124 * Assumes 100m cable and maximum MTU.
1125 */
Ido Schimmel18281f22017-03-24 08:02:51 +01001126#define MLXSW_SP_PAUSE_DELAY 58752
1127
1128static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1129 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +01001130{
1131 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +01001132 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +01001133 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +01001134 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001135 else
Ido Schimmelf417f042017-03-24 08:02:50 +01001136 return 0;
1137}
1138
1139static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1140 bool lossy)
1141{
1142 if (lossy)
1143 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
1144 else
1145 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1146 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001147}
1148
1149int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001150 u8 *prio_tc, bool pause_en,
1151 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +02001152{
1153 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001154 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1155 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001156 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001157 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001158
1159 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1160 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1161 if (err)
1162 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001163
1164 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1165 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001166 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +01001167 bool lossy;
1168 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001169
1170 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1171 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001172 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001173 configure = true;
1174 break;
1175 }
1176 }
1177
1178 if (!configure)
1179 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +01001180
1181 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +01001182 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1183 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1184 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +01001185 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001186 }
1187
Ido Schimmelff6551e2016-04-06 17:10:03 +02001188 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1189}
1190
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001191static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001192 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001193{
1194 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1195 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001196 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001197 u8 *prio_tc;
1198
1199 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001200 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001201
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001202 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001203 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001204}
1205
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001206static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1207{
1208 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001209 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001210 int err;
1211
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001212 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001213 if (err)
1214 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001215 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1216 if (err)
1217 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001218 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1219 if (err)
1220 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001221 dev->mtu = mtu;
1222 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001223
1224err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001225 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1226err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001227 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +02001228 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001229}
1230
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001231static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001232mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1233 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001234{
1235 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1236 struct mlxsw_sp_port_pcpu_stats *p;
1237 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1238 u32 tx_dropped = 0;
1239 unsigned int start;
1240 int i;
1241
1242 for_each_possible_cpu(i) {
1243 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1244 do {
1245 start = u64_stats_fetch_begin_irq(&p->syncp);
1246 rx_packets = p->rx_packets;
1247 rx_bytes = p->rx_bytes;
1248 tx_packets = p->tx_packets;
1249 tx_bytes = p->tx_bytes;
1250 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1251
1252 stats->rx_packets += rx_packets;
1253 stats->rx_bytes += rx_bytes;
1254 stats->tx_packets += tx_packets;
1255 stats->tx_bytes += tx_bytes;
1256 /* tx_dropped is u32, updated without syncp protection. */
1257 tx_dropped += p->tx_dropped;
1258 }
1259 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001260 return 0;
1261}
1262
Or Gerlitz3df5b3c2016-11-22 23:09:54 +02001263static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001264{
1265 switch (attr_id) {
1266 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1267 return true;
1268 }
1269
1270 return false;
1271}
1272
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001273static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1274 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001275{
1276 switch (attr_id) {
1277 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1278 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1279 }
1280
1281 return -EINVAL;
1282}
1283
1284static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1285 int prio, char *ppcnt_pl)
1286{
1287 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1288 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1289
1290 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1291 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1292}
1293
1294static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1295 struct rtnl_link_stats64 *stats)
1296{
1297 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1298 int err;
1299
1300 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1301 0, ppcnt_pl);
1302 if (err)
1303 goto out;
1304
1305 stats->tx_packets =
1306 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1307 stats->rx_packets =
1308 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1309 stats->tx_bytes =
1310 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1311 stats->rx_bytes =
1312 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1313 stats->multicast =
1314 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1315
1316 stats->rx_crc_errors =
1317 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1318 stats->rx_frame_errors =
1319 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1320
1321 stats->rx_length_errors = (
1322 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1323 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1324 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1325
1326 stats->rx_errors = (stats->rx_crc_errors +
1327 stats->rx_frame_errors + stats->rx_length_errors);
1328
1329out:
1330 return err;
1331}
1332
1333static void update_stats_cache(struct work_struct *work)
1334{
1335 struct mlxsw_sp_port *mlxsw_sp_port =
1336 container_of(work, struct mlxsw_sp_port,
1337 hw_stats.update_dw.work);
1338
1339 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1340 goto out;
1341
1342 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1343 mlxsw_sp_port->hw_stats.cache);
1344
1345out:
1346 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw,
1347 MLXSW_HW_STATS_UPDATE_TIME);
1348}
1349
1350/* Return the stats from a cache that is updated periodically,
1351 * as this function might get called in an atomic context.
1352 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001353static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001354mlxsw_sp_port_get_stats64(struct net_device *dev,
1355 struct rtnl_link_stats64 *stats)
1356{
1357 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1358
1359 memcpy(stats, mlxsw_sp_port->hw_stats.cache, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001360}
1361
Jiri Pirko93cd0812017-04-18 16:55:35 +02001362static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1363 u16 vid_begin, u16 vid_end,
1364 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001365{
1366 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1367 char *spvm_pl;
1368 int err;
1369
1370 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1371 if (!spvm_pl)
1372 return -ENOMEM;
1373
1374 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1375 vid_end, is_member, untagged);
1376 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1377 kfree(spvm_pl);
1378 return err;
1379}
1380
Jiri Pirko93cd0812017-04-18 16:55:35 +02001381int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1382 u16 vid_end, bool is_member, bool untagged)
1383{
1384 u16 vid, vid_e;
1385 int err;
1386
1387 for (vid = vid_begin; vid <= vid_end;
1388 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1389 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1390 vid_end);
1391
1392 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1393 is_member, untagged);
1394 if (err)
1395 return err;
1396 }
1397
1398 return 0;
1399}
1400
Ido Schimmel4aafc362017-05-26 08:37:25 +02001401int mlxsw_sp_port_vp_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001402{
1403 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1404 u16 vid, last_visited_vid;
1405 int err;
1406
1407 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1408 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, true, vid,
1409 vid);
1410 if (err) {
1411 last_visited_vid = vid;
1412 goto err_port_vid_to_fid_set;
1413 }
1414 }
1415
1416 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
1417 if (err) {
1418 last_visited_vid = VLAN_N_VID;
1419 goto err_port_vid_to_fid_set;
1420 }
1421
1422 return 0;
1423
1424err_port_vid_to_fid_set:
1425 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, last_visited_vid)
1426 mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false, vid,
1427 vid);
1428 return err;
1429}
1430
Ido Schimmel4aafc362017-05-26 08:37:25 +02001431int mlxsw_sp_port_vlan_mode_trans(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001432{
1433 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
1434 u16 vid;
1435 int err;
1436
1437 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
1438 if (err)
1439 return err;
1440
1441 for_each_set_bit(vid, mlxsw_sp_port->active_vlans, VLAN_N_VID) {
1442 err = mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_port, mt, false,
1443 vid, vid);
1444 if (err)
1445 return err;
1446 }
1447
1448 return 0;
1449}
1450
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001451static struct mlxsw_sp_port *
Ido Schimmel0355b592016-06-20 23:04:13 +02001452mlxsw_sp_port_vport_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001453{
1454 struct mlxsw_sp_port *mlxsw_sp_vport;
1455
1456 mlxsw_sp_vport = kzalloc(sizeof(*mlxsw_sp_vport), GFP_KERNEL);
1457 if (!mlxsw_sp_vport)
1458 return NULL;
1459
1460 /* dev will be set correctly after the VLAN device is linked
1461 * with the real device. In case of bridge SELF invocation, dev
1462 * will remain as is.
1463 */
1464 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
1465 mlxsw_sp_vport->mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1466 mlxsw_sp_vport->local_port = mlxsw_sp_port->local_port;
1467 mlxsw_sp_vport->stp_state = BR_STATE_FORWARDING;
Ido Schimmel272c4472015-12-15 16:03:47 +01001468 mlxsw_sp_vport->lagged = mlxsw_sp_port->lagged;
1469 mlxsw_sp_vport->lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel0355b592016-06-20 23:04:13 +02001470 mlxsw_sp_vport->vport.vid = vid;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001471
1472 list_add(&mlxsw_sp_vport->vport.list, &mlxsw_sp_port->vports_list);
1473
1474 return mlxsw_sp_vport;
1475}
1476
1477static void mlxsw_sp_port_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_vport)
1478{
1479 list_del(&mlxsw_sp_vport->vport.list);
1480 kfree(mlxsw_sp_vport);
1481}
1482
Ido Schimmel31a08a52017-05-26 08:37:26 +02001483static struct mlxsw_sp_port_vlan *
1484mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1485{
1486 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1487
1488 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1489 if (!mlxsw_sp_port_vlan)
1490 return ERR_PTR(-ENOMEM);
1491
1492 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1493 mlxsw_sp_port_vlan->vid = vid;
1494 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1495
1496 return mlxsw_sp_port_vlan;
1497}
1498
1499static void
1500mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1501{
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001502 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1503
1504 if (fid && !WARN_ON(!fid->leave))
1505 fid->leave(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001506 list_del(&mlxsw_sp_port_vlan->list);
1507 kfree(mlxsw_sp_port_vlan);
1508}
1509
Ido Schimmel05978482016-08-17 16:39:30 +02001510static int mlxsw_sp_port_add_vid(struct net_device *dev,
1511 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001512{
1513 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001514 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001515 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel52697a92016-07-02 11:00:09 +02001516 bool untagged = vid == 1;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001517 int err;
1518
1519 /* VLAN 0 is added to HW filter when device goes up, but it is
1520 * reserved in our case, so simply return.
1521 */
1522 if (!vid)
1523 return 0;
1524
Ido Schimmel31a08a52017-05-26 08:37:26 +02001525 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1526 if (mlxsw_sp_port_vlan)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001527 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001528
Ido Schimmel31a08a52017-05-26 08:37:26 +02001529 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1530 if (IS_ERR(mlxsw_sp_port_vlan))
1531 return PTR_ERR(mlxsw_sp_port_vlan);
1532
Ido Schimmel0355b592016-06-20 23:04:13 +02001533 mlxsw_sp_vport = mlxsw_sp_port_vport_create(mlxsw_sp_port, vid);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001534 if (!mlxsw_sp_vport) {
1535 err = -ENOMEM;
1536 goto err_port_vport_create;
1537 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001538
Ido Schimmel52697a92016-07-02 11:00:09 +02001539 err = mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, true, untagged);
Ido Schimmelfa66d7e2016-08-17 16:39:29 +02001540 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001541 goto err_port_add_vid;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001542
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001543 return 0;
1544
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001545err_port_add_vid:
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001546 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001547err_port_vport_create:
1548 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001549 return err;
1550}
1551
Ido Schimmel32d863f2016-07-02 11:00:10 +02001552static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1553 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001554{
1555 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001556 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001557 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel1c800752016-06-20 23:04:20 +02001558 struct mlxsw_sp_fid *f;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001559
1560 /* VLAN 0 is removed from HW filter when device goes down, but
1561 * it is reserved in our case, so simply return.
1562 */
1563 if (!vid)
1564 return 0;
1565
Ido Schimmel31a08a52017-05-26 08:37:26 +02001566 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1567 if (WARN_ON(!mlxsw_sp_port_vlan))
1568 return 0;
1569
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001570 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel7a355832016-08-17 16:39:28 +02001571 if (WARN_ON(!mlxsw_sp_vport))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001572 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001573
Ido Schimmel7a355832016-08-17 16:39:28 +02001574 mlxsw_sp_port_vlan_set(mlxsw_sp_vport, vid, vid, false, false);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001575
Ido Schimmel1c800752016-06-20 23:04:20 +02001576 /* Drop FID reference. If this was the last reference the
1577 * resources will be freed.
1578 */
1579 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
1580 if (f && !WARN_ON(!f->leave))
Ido Schimmelce95e152017-05-26 08:37:27 +02001581 f->leave(mlxsw_sp_port_vlan);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001582
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001583 mlxsw_sp_port_vport_destroy(mlxsw_sp_vport);
1584
Ido Schimmel31a08a52017-05-26 08:37:26 +02001585 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1586
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001587 return 0;
1588}
1589
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001590static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1591 size_t len)
1592{
1593 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001594 u8 module = mlxsw_sp_port->mapping.module;
1595 u8 width = mlxsw_sp_port->mapping.width;
1596 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001597 int err;
1598
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001599 if (!mlxsw_sp_port->split)
1600 err = snprintf(name, len, "p%d", module + 1);
1601 else
1602 err = snprintf(name, len, "p%ds%d", module + 1,
1603 lane / width);
1604
1605 if (err >= len)
1606 return -EINVAL;
1607
1608 return 0;
1609}
1610
Yotam Gigi763b4b72016-07-21 12:03:17 +02001611static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001612mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1613 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001614 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1615
1616 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1617 if (mall_tc_entry->cookie == cookie)
1618 return mall_tc_entry;
1619
1620 return NULL;
1621}
1622
1623static int
1624mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001625 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001626 const struct tc_action *a,
1627 bool ingress)
1628{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001629 struct net *net = dev_net(mlxsw_sp_port->dev);
1630 enum mlxsw_sp_span_type span_type;
1631 struct mlxsw_sp_port *to_port;
1632 struct net_device *to_dev;
1633 int ifindex;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001634
1635 ifindex = tcf_mirred_ifindex(a);
1636 to_dev = __dev_get_by_index(net, ifindex);
1637 if (!to_dev) {
1638 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1639 return -EINVAL;
1640 }
1641
1642 if (!mlxsw_sp_port_dev_check(to_dev)) {
1643 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001644 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001645 }
1646 to_port = netdev_priv(to_dev);
1647
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001648 mirror->to_local_port = to_port->local_port;
1649 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001650 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001651 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1652}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001653
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001654static void
1655mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1656 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1657{
1658 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1659 enum mlxsw_sp_span_type span_type;
1660 struct mlxsw_sp_port *to_port;
1661
1662 to_port = mlxsw_sp->ports[mirror->to_local_port];
1663 span_type = mirror->ingress ?
1664 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1665 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, to_port, span_type);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001666}
1667
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001668static int
1669mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1670 struct tc_cls_matchall_offload *cls,
1671 const struct tc_action *a,
1672 bool ingress)
1673{
1674 int err;
1675
1676 if (!mlxsw_sp_port->sample)
1677 return -EOPNOTSUPP;
1678 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1679 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1680 return -EEXIST;
1681 }
1682 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1683 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1684 return -EOPNOTSUPP;
1685 }
1686
1687 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1688 tcf_sample_psample_group(a));
1689 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1690 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1691 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1692
1693 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1694 if (err)
1695 goto err_port_sample_set;
1696 return 0;
1697
1698err_port_sample_set:
1699 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1700 return err;
1701}
1702
1703static void
1704mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1705{
1706 if (!mlxsw_sp_port->sample)
1707 return;
1708
1709 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1710 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1711}
1712
Yotam Gigi763b4b72016-07-21 12:03:17 +02001713static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1714 __be16 protocol,
1715 struct tc_cls_matchall_offload *cls,
1716 bool ingress)
1717{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001718 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001719 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001720 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001721 int err;
1722
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001723 if (!tc_single_action(cls->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001724 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001725 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001726 }
1727
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001728 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1729 if (!mall_tc_entry)
1730 return -ENOMEM;
1731 mall_tc_entry->cookie = cls->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001732
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001733 tcf_exts_to_list(cls->exts, &actions);
1734 a = list_first_entry(&actions, struct tc_action, list);
1735
1736 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1737 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1738
1739 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1740 mirror = &mall_tc_entry->mirror;
1741 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1742 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001743 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1744 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1745 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, cls,
1746 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001747 } else {
1748 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001749 }
1750
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001751 if (err)
1752 goto err_add_action;
1753
1754 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001755 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001756
1757err_add_action:
1758 kfree(mall_tc_entry);
1759 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001760}
1761
1762static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1763 struct tc_cls_matchall_offload *cls)
1764{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001765 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001766
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001767 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1768 cls->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001769 if (!mall_tc_entry) {
1770 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1771 return;
1772 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001773 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001774
1775 switch (mall_tc_entry->type) {
1776 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001777 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1778 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001779 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001780 case MLXSW_SP_PORT_MALL_SAMPLE:
1781 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1782 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001783 default:
1784 WARN_ON(1);
1785 }
1786
Yotam Gigi763b4b72016-07-21 12:03:17 +02001787 kfree(mall_tc_entry);
1788}
1789
1790static int mlxsw_sp_setup_tc(struct net_device *dev, u32 handle,
1791 __be16 proto, struct tc_to_netdev *tc)
1792{
1793 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1794 bool ingress = TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS);
1795
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001796 switch (tc->type) {
1797 case TC_SETUP_MATCHALL:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001798 switch (tc->cls_mall->command) {
1799 case TC_CLSMATCHALL_REPLACE:
1800 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port,
1801 proto,
1802 tc->cls_mall,
1803 ingress);
1804 case TC_CLSMATCHALL_DESTROY:
1805 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port,
1806 tc->cls_mall);
1807 return 0;
1808 default:
Or Gerlitzabbdf4b2017-03-17 09:38:01 +01001809 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001810 }
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001811 case TC_SETUP_CLSFLOWER:
1812 switch (tc->cls_flower->command) {
1813 case TC_CLSFLOWER_REPLACE:
1814 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress,
1815 proto, tc->cls_flower);
1816 case TC_CLSFLOWER_DESTROY:
1817 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress,
1818 tc->cls_flower);
1819 return 0;
Arkadi Sharshevsky7c1b8eb2017-03-11 09:42:59 +01001820 case TC_CLSFLOWER_STATS:
1821 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress,
1822 tc->cls_flower);
Jiri Pirko7aa0f5a2017-02-03 10:29:09 +01001823 default:
1824 return -EOPNOTSUPP;
1825 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001826 }
1827
Yotam Gigie915ac62017-01-09 11:25:48 +01001828 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001829}
1830
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001831static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1832 .ndo_open = mlxsw_sp_port_open,
1833 .ndo_stop = mlxsw_sp_port_stop,
1834 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001835 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001836 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001837 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1838 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1839 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001840 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1841 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001842 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1843 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
1844 .ndo_fdb_add = switchdev_port_fdb_add,
1845 .ndo_fdb_del = switchdev_port_fdb_del,
1846 .ndo_fdb_dump = switchdev_port_fdb_dump,
1847 .ndo_bridge_setlink = switchdev_port_bridge_setlink,
1848 .ndo_bridge_getlink = switchdev_port_bridge_getlink,
1849 .ndo_bridge_dellink = switchdev_port_bridge_dellink,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001850 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001851};
1852
1853static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1854 struct ethtool_drvinfo *drvinfo)
1855{
1856 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1857 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1858
1859 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1860 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1861 sizeof(drvinfo->version));
1862 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1863 "%d.%d.%d",
1864 mlxsw_sp->bus_info->fw_rev.major,
1865 mlxsw_sp->bus_info->fw_rev.minor,
1866 mlxsw_sp->bus_info->fw_rev.subminor);
1867 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1868 sizeof(drvinfo->bus_info));
1869}
1870
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001871static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1872 struct ethtool_pauseparam *pause)
1873{
1874 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1875
1876 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1877 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1878}
1879
1880static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1881 struct ethtool_pauseparam *pause)
1882{
1883 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1884
1885 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1886 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1887 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1888
1889 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1890 pfcc_pl);
1891}
1892
1893static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1894 struct ethtool_pauseparam *pause)
1895{
1896 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1897 bool pause_en = pause->tx_pause || pause->rx_pause;
1898 int err;
1899
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001900 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1901 netdev_err(dev, "PFC already enabled on port\n");
1902 return -EINVAL;
1903 }
1904
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001905 if (pause->autoneg) {
1906 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1907 return -EINVAL;
1908 }
1909
1910 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1911 if (err) {
1912 netdev_err(dev, "Failed to configure port's headroom\n");
1913 return err;
1914 }
1915
1916 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1917 if (err) {
1918 netdev_err(dev, "Failed to set PAUSE parameters\n");
1919 goto err_port_pause_configure;
1920 }
1921
1922 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1923 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1924
1925 return 0;
1926
1927err_port_pause_configure:
1928 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1929 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1930 return err;
1931}
1932
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001933struct mlxsw_sp_port_hw_stats {
1934 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001935 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001936 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001937};
1938
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001939static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001940 {
1941 .str = "a_frames_transmitted_ok",
1942 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1943 },
1944 {
1945 .str = "a_frames_received_ok",
1946 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1947 },
1948 {
1949 .str = "a_frame_check_sequence_errors",
1950 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
1951 },
1952 {
1953 .str = "a_alignment_errors",
1954 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
1955 },
1956 {
1957 .str = "a_octets_transmitted_ok",
1958 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
1959 },
1960 {
1961 .str = "a_octets_received_ok",
1962 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
1963 },
1964 {
1965 .str = "a_multicast_frames_xmitted_ok",
1966 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
1967 },
1968 {
1969 .str = "a_broadcast_frames_xmitted_ok",
1970 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
1971 },
1972 {
1973 .str = "a_multicast_frames_received_ok",
1974 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
1975 },
1976 {
1977 .str = "a_broadcast_frames_received_ok",
1978 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
1979 },
1980 {
1981 .str = "a_in_range_length_errors",
1982 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
1983 },
1984 {
1985 .str = "a_out_of_range_length_field",
1986 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
1987 },
1988 {
1989 .str = "a_frame_too_long_errors",
1990 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
1991 },
1992 {
1993 .str = "a_symbol_error_during_carrier",
1994 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
1995 },
1996 {
1997 .str = "a_mac_control_frames_transmitted",
1998 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
1999 },
2000 {
2001 .str = "a_mac_control_frames_received",
2002 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2003 },
2004 {
2005 .str = "a_unsupported_opcodes_received",
2006 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2007 },
2008 {
2009 .str = "a_pause_mac_ctrl_frames_received",
2010 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2011 },
2012 {
2013 .str = "a_pause_mac_ctrl_frames_xmitted",
2014 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2015 },
2016};
2017
2018#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2019
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002020static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2021 {
2022 .str = "rx_octets_prio",
2023 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2024 },
2025 {
2026 .str = "rx_frames_prio",
2027 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2028 },
2029 {
2030 .str = "tx_octets_prio",
2031 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2032 },
2033 {
2034 .str = "tx_frames_prio",
2035 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2036 },
2037 {
2038 .str = "rx_pause_prio",
2039 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2040 },
2041 {
2042 .str = "rx_pause_duration_prio",
2043 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2044 },
2045 {
2046 .str = "tx_pause_prio",
2047 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2048 },
2049 {
2050 .str = "tx_pause_duration_prio",
2051 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2052 },
2053};
2054
2055#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2056
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002057static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2058 {
2059 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01002060 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2061 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002062 },
2063 {
2064 .str = "tc_no_buffer_discard_uc_tc",
2065 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2066 },
2067};
2068
2069#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2070
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002071#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002072 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
2073 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002074 IEEE_8021QAZ_MAX_TCS)
2075
2076static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2077{
2078 int i;
2079
2080 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2081 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2082 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2083 *p += ETH_GSTRING_LEN;
2084 }
2085}
2086
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002087static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2088{
2089 int i;
2090
2091 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2092 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2093 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2094 *p += ETH_GSTRING_LEN;
2095 }
2096}
2097
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002098static void mlxsw_sp_port_get_strings(struct net_device *dev,
2099 u32 stringset, u8 *data)
2100{
2101 u8 *p = data;
2102 int i;
2103
2104 switch (stringset) {
2105 case ETH_SS_STATS:
2106 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2107 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2108 ETH_GSTRING_LEN);
2109 p += ETH_GSTRING_LEN;
2110 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002111
2112 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2113 mlxsw_sp_port_get_prio_strings(&p, i);
2114
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002115 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2116 mlxsw_sp_port_get_tc_strings(&p, i);
2117
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002118 break;
2119 }
2120}
2121
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002122static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2123 enum ethtool_phys_id_state state)
2124{
2125 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2126 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2127 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2128 bool active;
2129
2130 switch (state) {
2131 case ETHTOOL_ID_ACTIVE:
2132 active = true;
2133 break;
2134 case ETHTOOL_ID_INACTIVE:
2135 active = false;
2136 break;
2137 default:
2138 return -EOPNOTSUPP;
2139 }
2140
2141 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2142 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2143}
2144
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002145static int
2146mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2147 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2148{
2149 switch (grp) {
2150 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2151 *p_hw_stats = mlxsw_sp_port_hw_stats;
2152 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2153 break;
2154 case MLXSW_REG_PPCNT_PRIO_CNT:
2155 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2156 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2157 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002158 case MLXSW_REG_PPCNT_TC_CNT:
2159 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2160 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2161 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002162 default:
2163 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002164 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002165 }
2166 return 0;
2167}
2168
2169static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2170 enum mlxsw_reg_ppcnt_grp grp, int prio,
2171 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002172{
Ido Schimmel18281f22017-03-24 08:02:51 +01002173 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2174 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002175 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002176 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002177 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002178 int err;
2179
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002180 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2181 if (err)
2182 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002183 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002184 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002185 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002186 if (!hw_stats[i].cells_bytes)
2187 continue;
2188 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2189 data[data_index + i]);
2190 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002191}
2192
2193static void mlxsw_sp_port_get_stats(struct net_device *dev,
2194 struct ethtool_stats *stats, u64 *data)
2195{
2196 int i, data_index = 0;
2197
2198 /* IEEE 802.3 Counters */
2199 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2200 data, data_index);
2201 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2202
2203 /* Per-Priority Counters */
2204 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2205 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2206 data, data_index);
2207 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2208 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002209
2210 /* Per-TC Counters */
2211 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2212 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2213 data, data_index);
2214 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2215 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002216}
2217
2218static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2219{
2220 switch (sset) {
2221 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002222 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002223 default:
2224 return -EOPNOTSUPP;
2225 }
2226}
2227
2228struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002229 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002230 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002231 u32 speed;
2232};
2233
2234static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2235 {
2236 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002237 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2238 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002239 },
2240 {
2241 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2242 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002243 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2244 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002245 },
2246 {
2247 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002248 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2249 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002250 },
2251 {
2252 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2253 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002254 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2255 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002256 },
2257 {
2258 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2259 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2260 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2261 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002262 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2263 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002264 },
2265 {
2266 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002267 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2268 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002269 },
2270 {
2271 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002272 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2273 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002274 },
2275 {
2276 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002277 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2278 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002279 },
2280 {
2281 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002282 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2283 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002284 },
2285 {
2286 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002287 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2288 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002289 },
2290 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002291 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2292 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2293 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002294 },
2295 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002296 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2297 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2298 .speed = SPEED_25000,
2299 },
2300 {
2301 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2302 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2303 .speed = SPEED_25000,
2304 },
2305 {
2306 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2307 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2308 .speed = SPEED_25000,
2309 },
2310 {
2311 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2312 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2313 .speed = SPEED_50000,
2314 },
2315 {
2316 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2317 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2318 .speed = SPEED_50000,
2319 },
2320 {
2321 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2322 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2323 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002324 },
2325 {
2326 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002327 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2328 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002329 },
2330 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002331 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2332 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2333 .speed = SPEED_56000,
2334 },
2335 {
2336 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2337 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2338 .speed = SPEED_56000,
2339 },
2340 {
2341 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2342 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2343 .speed = SPEED_56000,
2344 },
2345 {
2346 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2347 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2348 .speed = SPEED_100000,
2349 },
2350 {
2351 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2352 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2353 .speed = SPEED_100000,
2354 },
2355 {
2356 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2357 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2358 .speed = SPEED_100000,
2359 },
2360 {
2361 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2362 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2363 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002364 },
2365};
2366
2367#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2368
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002369static void
2370mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2371 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002372{
2373 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2374 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2375 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2376 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2377 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2378 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002379 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002380
2381 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2382 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2383 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2384 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2385 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002386 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002387}
2388
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002389static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002390{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002391 int i;
2392
2393 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2394 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002395 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2396 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002397 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002398}
2399
2400static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002401 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002402{
2403 u32 speed = SPEED_UNKNOWN;
2404 u8 duplex = DUPLEX_UNKNOWN;
2405 int i;
2406
2407 if (!carrier_ok)
2408 goto out;
2409
2410 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2411 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2412 speed = mlxsw_sp_port_link_mode[i].speed;
2413 duplex = DUPLEX_FULL;
2414 break;
2415 }
2416 }
2417out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002418 cmd->base.speed = speed;
2419 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002420}
2421
2422static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2423{
2424 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2425 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2426 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2427 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2428 return PORT_FIBRE;
2429
2430 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2431 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2432 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2433 return PORT_DA;
2434
2435 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2436 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2437 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2438 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2439 return PORT_NONE;
2440
2441 return PORT_OTHER;
2442}
2443
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002444static u32
2445mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002446{
2447 u32 ptys_proto = 0;
2448 int i;
2449
2450 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002451 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2452 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002453 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2454 }
2455 return ptys_proto;
2456}
2457
2458static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2459{
2460 u32 ptys_proto = 0;
2461 int i;
2462
2463 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2464 if (speed == mlxsw_sp_port_link_mode[i].speed)
2465 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2466 }
2467 return ptys_proto;
2468}
2469
Ido Schimmel18f1e702016-02-26 17:32:31 +01002470static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2471{
2472 u32 ptys_proto = 0;
2473 int i;
2474
2475 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2476 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2477 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2478 }
2479 return ptys_proto;
2480}
2481
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002482static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2483 struct ethtool_link_ksettings *cmd)
2484{
2485 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2486 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2487 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2488
2489 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2490 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2491}
2492
2493static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2494 struct ethtool_link_ksettings *cmd)
2495{
2496 if (!autoneg)
2497 return;
2498
2499 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2500 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2501}
2502
2503static void
2504mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2505 struct ethtool_link_ksettings *cmd)
2506{
2507 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2508 return;
2509
2510 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2511 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2512}
2513
2514static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2515 struct ethtool_link_ksettings *cmd)
2516{
2517 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2518 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2519 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2520 char ptys_pl[MLXSW_REG_PTYS_LEN];
2521 u8 autoneg_status;
2522 bool autoneg;
2523 int err;
2524
2525 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002526 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002527 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2528 if (err)
2529 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002530 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2531 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002532
2533 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2534
2535 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2536
2537 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2538 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2539 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2540
2541 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2542 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2543 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2544 cmd);
2545
2546 return 0;
2547}
2548
2549static int
2550mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2551 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002552{
2553 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2554 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2555 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002556 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002557 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002558 int err;
2559
Elad Raz401c8b42016-10-28 21:35:52 +02002560 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002561 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002562 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002563 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002564 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002565
2566 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2567 eth_proto_new = autoneg ?
2568 mlxsw_sp_to_ptys_advert_link(cmd) :
2569 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002570
2571 eth_proto_new = eth_proto_new & eth_proto_cap;
2572 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002573 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002574 return -EINVAL;
2575 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002576
Elad Raz401c8b42016-10-28 21:35:52 +02002577 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2578 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002579 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002580 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002581 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002582
Ido Schimmel6277d462016-07-15 11:14:58 +02002583 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002584 return 0;
2585
Ido Schimmel0c83f882016-09-12 13:26:23 +02002586 mlxsw_sp_port->link.autoneg = autoneg;
2587
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002588 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2589 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002590
2591 return 0;
2592}
2593
2594static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2595 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2596 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002597 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2598 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002599 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002600 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002601 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2602 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002603 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2604 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002605};
2606
Ido Schimmel18f1e702016-02-26 17:32:31 +01002607static int
2608mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2609{
2610 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2611 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2612 char ptys_pl[MLXSW_REG_PTYS_LEN];
2613 u32 eth_proto_admin;
2614
2615 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002616 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2617 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002618 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2619}
2620
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002621int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2622 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2623 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002624{
2625 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2626 char qeec_pl[MLXSW_REG_QEEC_LEN];
2627
2628 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2629 next_index);
2630 mlxsw_reg_qeec_de_set(qeec_pl, true);
2631 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2632 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2633 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2634}
2635
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002636int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2637 enum mlxsw_reg_qeec_hr hr, u8 index,
2638 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002639{
2640 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2641 char qeec_pl[MLXSW_REG_QEEC_LEN];
2642
2643 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2644 next_index);
2645 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2646 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2647 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2648}
2649
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002650int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2651 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002652{
2653 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2654 char qtct_pl[MLXSW_REG_QTCT_LEN];
2655
2656 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2657 tclass);
2658 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2659}
2660
2661static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2662{
2663 int err, i;
2664
2665 /* Setup the elements hierarcy, so that each TC is linked to
2666 * one subgroup, which are all member in the same group.
2667 */
2668 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2669 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2670 0);
2671 if (err)
2672 return err;
2673 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2674 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2675 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2676 0, false, 0);
2677 if (err)
2678 return err;
2679 }
2680 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2681 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2682 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2683 false, 0);
2684 if (err)
2685 return err;
2686 }
2687
2688 /* Make sure the max shaper is disabled in all hierarcies that
2689 * support it.
2690 */
2691 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2692 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2693 MLXSW_REG_QEEC_MAS_DIS);
2694 if (err)
2695 return err;
2696 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2697 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2698 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2699 i, 0,
2700 MLXSW_REG_QEEC_MAS_DIS);
2701 if (err)
2702 return err;
2703 }
2704 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2705 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2706 MLXSW_REG_QEEC_HIERARCY_TC,
2707 i, i,
2708 MLXSW_REG_QEEC_MAS_DIS);
2709 if (err)
2710 return err;
2711 }
2712
2713 /* Map all priorities to traffic class 0. */
2714 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2715 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2716 if (err)
2717 return err;
2718 }
2719
2720 return 0;
2721}
2722
Ido Schimmel05978482016-08-17 16:39:30 +02002723static int mlxsw_sp_port_pvid_vport_create(struct mlxsw_sp_port *mlxsw_sp_port)
2724{
2725 mlxsw_sp_port->pvid = 1;
2726
2727 return mlxsw_sp_port_add_vid(mlxsw_sp_port->dev, 0, 1);
2728}
2729
2730static int mlxsw_sp_port_pvid_vport_destroy(struct mlxsw_sp_port *mlxsw_sp_port)
2731{
2732 return mlxsw_sp_port_kill_vid(mlxsw_sp_port->dev, 0, 1);
2733}
2734
Jiri Pirko67963a32016-10-28 21:35:55 +02002735static int __mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2736 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002737{
2738 struct mlxsw_sp_port *mlxsw_sp_port;
2739 struct net_device *dev;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002740 size_t bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002741 int err;
2742
2743 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
2744 if (!dev)
2745 return -ENOMEM;
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002746 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002747 mlxsw_sp_port = netdev_priv(dev);
2748 mlxsw_sp_port->dev = dev;
2749 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2750 mlxsw_sp_port->local_port = local_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002751 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002752 mlxsw_sp_port->mapping.module = module;
2753 mlxsw_sp_port->mapping.width = width;
2754 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002755 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002756 bytes = DIV_ROUND_UP(VLAN_N_VID, BITS_PER_BYTE);
2757 mlxsw_sp_port->active_vlans = kzalloc(bytes, GFP_KERNEL);
2758 if (!mlxsw_sp_port->active_vlans) {
2759 err = -ENOMEM;
2760 goto err_port_active_vlans_alloc;
2761 }
Elad Razfc1273a2016-01-06 13:01:11 +01002762 mlxsw_sp_port->untagged_vlans = kzalloc(bytes, GFP_KERNEL);
2763 if (!mlxsw_sp_port->untagged_vlans) {
2764 err = -ENOMEM;
2765 goto err_port_untagged_vlans_alloc;
2766 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02002767 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01002768 INIT_LIST_HEAD(&mlxsw_sp_port->vports_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002769 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002770
2771 mlxsw_sp_port->pcpu_stats =
2772 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2773 if (!mlxsw_sp_port->pcpu_stats) {
2774 err = -ENOMEM;
2775 goto err_alloc_stats;
2776 }
2777
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002778 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2779 GFP_KERNEL);
2780 if (!mlxsw_sp_port->sample) {
2781 err = -ENOMEM;
2782 goto err_alloc_sample;
2783 }
2784
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002785 mlxsw_sp_port->hw_stats.cache =
2786 kzalloc(sizeof(*mlxsw_sp_port->hw_stats.cache), GFP_KERNEL);
2787
2788 if (!mlxsw_sp_port->hw_stats.cache) {
2789 err = -ENOMEM;
2790 goto err_alloc_hw_stats;
2791 }
2792 INIT_DELAYED_WORK(&mlxsw_sp_port->hw_stats.update_dw,
2793 &update_stats_cache);
2794
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002795 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2796 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2797
Ido Schimmel3247ff22016-09-08 08:16:02 +02002798 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
2799 if (err) {
2800 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
2801 mlxsw_sp_port->local_port);
2802 goto err_port_swid_set;
2803 }
2804
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002805 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
2806 if (err) {
2807 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
2808 mlxsw_sp_port->local_port);
2809 goto err_dev_addr_init;
2810 }
2811
2812 netif_carrier_off(dev);
2813
2814 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02002815 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
2816 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002817
Jarod Wilsond894be52016-10-20 13:55:16 -04002818 dev->min_mtu = 0;
2819 dev->max_mtu = ETH_MAX_MTU;
2820
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002821 /* Each packet needs to have a Tx header (metadata) on top all other
2822 * headers.
2823 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02002824 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002825
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002826 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
2827 if (err) {
2828 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
2829 mlxsw_sp_port->local_port);
2830 goto err_port_system_port_mapping_set;
2831 }
2832
Ido Schimmel18f1e702016-02-26 17:32:31 +01002833 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
2834 if (err) {
2835 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
2836 mlxsw_sp_port->local_port);
2837 goto err_port_speed_by_width_set;
2838 }
2839
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002840 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
2841 if (err) {
2842 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
2843 mlxsw_sp_port->local_port);
2844 goto err_port_mtu_set;
2845 }
2846
2847 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2848 if (err)
2849 goto err_port_admin_status_set;
2850
2851 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
2852 if (err) {
2853 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
2854 mlxsw_sp_port->local_port);
2855 goto err_port_buffers_init;
2856 }
2857
Ido Schimmel90183b92016-04-06 17:10:08 +02002858 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
2859 if (err) {
2860 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
2861 mlxsw_sp_port->local_port);
2862 goto err_port_ets_init;
2863 }
2864
Ido Schimmelf00817d2016-04-06 17:10:09 +02002865 /* ETS and buffers must be initialized before DCB. */
2866 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
2867 if (err) {
2868 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
2869 mlxsw_sp_port->local_port);
2870 goto err_port_dcb_init;
2871 }
2872
Ido Schimmel45a4a162017-05-16 19:38:35 +02002873 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
2874 if (err) {
2875 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set non-virtual mode\n",
2876 mlxsw_sp_port->local_port);
2877 goto err_port_vp_mode_set;
2878 }
2879
Ido Schimmel05978482016-08-17 16:39:30 +02002880 err = mlxsw_sp_port_pvid_vport_create(mlxsw_sp_port);
2881 if (err) {
2882 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create PVID vPort\n",
2883 mlxsw_sp_port->local_port);
2884 goto err_port_pvid_vport_create;
2885 }
2886
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002887 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02002888 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002889 err = register_netdev(dev);
2890 if (err) {
2891 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
2892 mlxsw_sp_port->local_port);
2893 goto err_register_netdev;
2894 }
2895
Elad Razd808c7e2016-10-28 21:35:57 +02002896 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
2897 mlxsw_sp_port, dev, mlxsw_sp_port->split,
2898 module);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002899 mlxsw_core_schedule_dw(&mlxsw_sp_port->hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002900 return 0;
2901
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002902err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02002903 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002904 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel05978482016-08-17 16:39:30 +02002905 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
2906err_port_pvid_vport_create:
Ido Schimmel45a4a162017-05-16 19:38:35 +02002907err_port_vp_mode_set:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03002908 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002909err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02002910err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002911err_port_buffers_init:
2912err_port_admin_status_set:
2913err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01002914err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002915err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002916err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02002917 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2918err_port_swid_set:
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002919 kfree(mlxsw_sp_port->hw_stats.cache);
2920err_alloc_hw_stats:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002921 kfree(mlxsw_sp_port->sample);
2922err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002923 free_percpu(mlxsw_sp_port->pcpu_stats);
2924err_alloc_stats:
Elad Razfc1273a2016-01-06 13:01:11 +01002925 kfree(mlxsw_sp_port->untagged_vlans);
2926err_port_untagged_vlans_alloc:
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002927 kfree(mlxsw_sp_port->active_vlans);
2928err_port_active_vlans_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002929 free_netdev(dev);
2930 return err;
2931}
2932
Jiri Pirko67963a32016-10-28 21:35:55 +02002933static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2934 bool split, u8 module, u8 width, u8 lane)
2935{
2936 int err;
2937
2938 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2939 if (err) {
2940 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2941 local_port);
2942 return err;
2943 }
Ido Schimmel9a60c902016-12-16 19:29:03 +01002944 err = __mlxsw_sp_port_create(mlxsw_sp, local_port, split,
Jiri Pirko67963a32016-10-28 21:35:55 +02002945 module, width, lane);
2946 if (err)
2947 goto err_port_create;
2948 return 0;
2949
2950err_port_create:
2951 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2952 return err;
2953}
2954
2955static void __mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002956{
2957 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
2958
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002959 cancel_delayed_work_sync(&mlxsw_sp_port->hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02002960 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002961 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02002962 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02002963 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmel05978482016-08-17 16:39:30 +02002964 mlxsw_sp_port_pvid_vport_destroy(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02002965 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01002966 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
2967 mlxsw_sp_port_module_unmap(mlxsw_sp, mlxsw_sp_port->local_port);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002968 kfree(mlxsw_sp_port->hw_stats.cache);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002969 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01002970 free_percpu(mlxsw_sp_port->pcpu_stats);
Elad Razfc1273a2016-01-06 13:01:11 +01002971 kfree(mlxsw_sp_port->untagged_vlans);
Ido Schimmelbd40e9d2015-12-15 16:03:36 +01002972 kfree(mlxsw_sp_port->active_vlans);
Ido Schimmel32d863f2016-07-02 11:00:10 +02002973 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vports_list));
Ido Schimmel31a08a52017-05-26 08:37:26 +02002974 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002975 free_netdev(mlxsw_sp_port->dev);
2976}
2977
Jiri Pirko67963a32016-10-28 21:35:55 +02002978static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2979{
2980 __mlxsw_sp_port_remove(mlxsw_sp, local_port);
2981 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
2982}
2983
Jiri Pirkof83e2102016-10-28 21:35:49 +02002984static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
2985{
2986 return mlxsw_sp->ports[local_port] != NULL;
2987}
2988
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002989static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
2990{
2991 int i;
2992
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002993 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02002994 if (mlxsw_sp_port_created(mlxsw_sp, i))
2995 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01002996 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002997 kfree(mlxsw_sp->ports);
2998}
2999
3000static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3001{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003002 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02003003 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003004 size_t alloc_size;
3005 int i;
3006 int err;
3007
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003008 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003009 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3010 if (!mlxsw_sp->ports)
3011 return -ENOMEM;
3012
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003013 mlxsw_sp->port_to_module = kcalloc(max_ports, sizeof(u8), GFP_KERNEL);
3014 if (!mlxsw_sp->port_to_module) {
3015 err = -ENOMEM;
3016 goto err_port_to_module_alloc;
3017 }
3018
3019 for (i = 1; i < max_ports; i++) {
Ido Schimmel558c2d52016-02-26 17:32:29 +01003020 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003021 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003022 if (err)
3023 goto err_port_module_info_get;
3024 if (!width)
3025 continue;
3026 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003027 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3028 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003029 if (err)
3030 goto err_port_create;
3031 }
3032 return 0;
3033
3034err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003035err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003036 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003037 if (mlxsw_sp_port_created(mlxsw_sp, i))
3038 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003039 kfree(mlxsw_sp->port_to_module);
3040err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003041 kfree(mlxsw_sp->ports);
3042 return err;
3043}
3044
Ido Schimmel18f1e702016-02-26 17:32:31 +01003045static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3046{
3047 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3048
3049 return local_port - offset;
3050}
3051
Ido Schimmelbe945352016-06-09 09:51:39 +02003052static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3053 u8 module, unsigned int count)
3054{
3055 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3056 int err, i;
3057
3058 for (i = 0; i < count; i++) {
3059 err = mlxsw_sp_port_module_map(mlxsw_sp, base_port + i, module,
3060 width, i * width);
3061 if (err)
3062 goto err_port_module_map;
3063 }
3064
3065 for (i = 0; i < count; i++) {
3066 err = __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i, 0);
3067 if (err)
3068 goto err_port_swid_set;
3069 }
3070
3071 for (i = 0; i < count; i++) {
3072 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003073 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003074 if (err)
3075 goto err_port_create;
3076 }
3077
3078 return 0;
3079
3080err_port_create:
3081 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003082 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3083 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003084 i = count;
3085err_port_swid_set:
3086 for (i--; i >= 0; i--)
3087 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i,
3088 MLXSW_PORT_SWID_DISABLED_PORT);
3089 i = count;
3090err_port_module_map:
3091 for (i--; i >= 0; i--)
3092 mlxsw_sp_port_module_unmap(mlxsw_sp, base_port + i);
3093 return err;
3094}
3095
3096static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3097 u8 base_port, unsigned int count)
3098{
3099 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3100 int i;
3101
3102 /* Split by four means we need to re-create two ports, otherwise
3103 * only one.
3104 */
3105 count = count / 2;
3106
3107 for (i = 0; i < count; i++) {
3108 local_port = base_port + i * 2;
3109 module = mlxsw_sp->port_to_module[local_port];
3110
3111 mlxsw_sp_port_module_map(mlxsw_sp, local_port, module, width,
3112 0);
3113 }
3114
3115 for (i = 0; i < count; i++)
3116 __mlxsw_sp_port_swid_set(mlxsw_sp, base_port + i * 2, 0);
3117
3118 for (i = 0; i < count; i++) {
3119 local_port = base_port + i * 2;
3120 module = mlxsw_sp->port_to_module[local_port];
3121
3122 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003123 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003124 }
3125}
3126
Jiri Pirkob2f10572016-04-08 19:11:23 +02003127static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3128 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003129{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003130 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003131 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003132 u8 module, cur_width, base_port;
3133 int i;
3134 int err;
3135
3136 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3137 if (!mlxsw_sp_port) {
3138 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3139 local_port);
3140 return -EINVAL;
3141 }
3142
Ido Schimmeld664b412016-06-09 09:51:40 +02003143 module = mlxsw_sp_port->mapping.module;
3144 cur_width = mlxsw_sp_port->mapping.width;
3145
Ido Schimmel18f1e702016-02-26 17:32:31 +01003146 if (count != 2 && count != 4) {
3147 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3148 return -EINVAL;
3149 }
3150
Ido Schimmel18f1e702016-02-26 17:32:31 +01003151 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3152 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3153 return -EINVAL;
3154 }
3155
3156 /* Make sure we have enough slave (even) ports for the split. */
3157 if (count == 2) {
3158 base_port = local_port;
3159 if (mlxsw_sp->ports[base_port + 1]) {
3160 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3161 return -EINVAL;
3162 }
3163 } else {
3164 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3165 if (mlxsw_sp->ports[base_port + 1] ||
3166 mlxsw_sp->ports[base_port + 3]) {
3167 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3168 return -EINVAL;
3169 }
3170 }
3171
3172 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003173 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3174 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003175
Ido Schimmelbe945352016-06-09 09:51:39 +02003176 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3177 if (err) {
3178 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3179 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003180 }
3181
3182 return 0;
3183
Ido Schimmelbe945352016-06-09 09:51:39 +02003184err_port_split_create:
3185 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003186 return err;
3187}
3188
Jiri Pirkob2f10572016-04-08 19:11:23 +02003189static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003190{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003191 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003192 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003193 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003194 unsigned int count;
3195 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003196
3197 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3198 if (!mlxsw_sp_port) {
3199 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3200 local_port);
3201 return -EINVAL;
3202 }
3203
3204 if (!mlxsw_sp_port->split) {
3205 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3206 return -EINVAL;
3207 }
3208
Ido Schimmeld664b412016-06-09 09:51:40 +02003209 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003210 count = cur_width == 1 ? 4 : 2;
3211
3212 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3213
3214 /* Determine which ports to remove. */
3215 if (count == 2 && local_port >= base_port + 2)
3216 base_port = base_port + 2;
3217
3218 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003219 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3220 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003221
Ido Schimmelbe945352016-06-09 09:51:39 +02003222 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003223
3224 return 0;
3225}
3226
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003227static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3228 char *pude_pl, void *priv)
3229{
3230 struct mlxsw_sp *mlxsw_sp = priv;
3231 struct mlxsw_sp_port *mlxsw_sp_port;
3232 enum mlxsw_reg_pude_oper_status status;
3233 u8 local_port;
3234
3235 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3236 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003237 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003238 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003239
3240 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3241 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3242 netdev_info(mlxsw_sp_port->dev, "link up\n");
3243 netif_carrier_on(mlxsw_sp_port->dev);
3244 } else {
3245 netdev_info(mlxsw_sp_port->dev, "link down\n");
3246 netif_carrier_off(mlxsw_sp_port->dev);
3247 }
3248}
3249
Nogah Frankel14eeda92016-11-25 10:33:32 +01003250static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3251 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003252{
3253 struct mlxsw_sp *mlxsw_sp = priv;
3254 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3255 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3256
3257 if (unlikely(!mlxsw_sp_port)) {
3258 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3259 local_port);
3260 return;
3261 }
3262
3263 skb->dev = mlxsw_sp_port->dev;
3264
3265 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3266 u64_stats_update_begin(&pcpu_stats->syncp);
3267 pcpu_stats->rx_packets++;
3268 pcpu_stats->rx_bytes += skb->len;
3269 u64_stats_update_end(&pcpu_stats->syncp);
3270
3271 skb->protocol = eth_type_trans(skb, skb->dev);
3272 netif_receive_skb(skb);
3273}
3274
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003275static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3276 void *priv)
3277{
3278 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003279 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003280}
3281
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003282static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3283 void *priv)
3284{
3285 struct mlxsw_sp *mlxsw_sp = priv;
3286 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3287 struct psample_group *psample_group;
3288 u32 size;
3289
3290 if (unlikely(!mlxsw_sp_port)) {
3291 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3292 local_port);
3293 goto out;
3294 }
3295 if (unlikely(!mlxsw_sp_port->sample)) {
3296 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3297 local_port);
3298 goto out;
3299 }
3300
3301 size = mlxsw_sp_port->sample->truncate ?
3302 mlxsw_sp_port->sample->trunc_size : skb->len;
3303
3304 rcu_read_lock();
3305 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3306 if (!psample_group)
3307 goto out_unlock;
3308 psample_sample_packet(psample_group, skb, size,
3309 mlxsw_sp_port->dev->ifindex, 0,
3310 mlxsw_sp_port->sample->rate);
3311out_unlock:
3312 rcu_read_unlock();
3313out:
3314 consume_skb(skb);
3315}
3316
Nogah Frankel117b0da2016-11-25 10:33:44 +01003317#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003318 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003319 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003320
Nogah Frankel117b0da2016-11-25 10:33:44 +01003321#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003322 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003323 _is_ctrl, SP_##_trap_group, DISCARD)
3324
3325#define MLXSW_SP_EVENTL(_func, _trap_id) \
3326 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003327
Nogah Frankel45449132016-11-25 10:33:35 +01003328static const struct mlxsw_listener mlxsw_sp_listener[] = {
3329 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003330 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003331 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003332 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3333 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3334 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3335 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3336 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3337 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3338 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3339 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3340 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3341 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3342 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003343 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003344 /* L3 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003345 MLXSW_SP_RXL_NO_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3346 MLXSW_SP_RXL_NO_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3347 MLXSW_SP_RXL_NO_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3348 MLXSW_SP_RXL_MARK(OSPF, TRAP_TO_CPU, OSPF, false),
3349 MLXSW_SP_RXL_NO_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
3350 MLXSW_SP_RXL_NO_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
3351 MLXSW_SP_RXL_NO_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, ARP_MISS, false),
3352 MLXSW_SP_RXL_NO_MARK(BGP_IPV4, TRAP_TO_CPU, BGP_IPV4, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003353 /* PKT Sample trap */
3354 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
3355 false, SP_IP2ME, DISCARD)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003356};
3357
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003358static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3359{
3360 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3361 enum mlxsw_reg_qpcr_ir_units ir_units;
3362 int max_cpu_policers;
3363 bool is_bytes;
3364 u8 burst_size;
3365 u32 rate;
3366 int i, err;
3367
3368 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3369 return -EIO;
3370
3371 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3372
3373 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3374 for (i = 0; i < max_cpu_policers; i++) {
3375 is_bytes = false;
3376 switch (i) {
3377 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3378 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3379 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3380 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3381 rate = 128;
3382 burst_size = 7;
3383 break;
3384 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3385 rate = 16 * 1024;
3386 burst_size = 10;
3387 break;
3388 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3389 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3390 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3391 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3392 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3393 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3394 rate = 1024;
3395 burst_size = 7;
3396 break;
3397 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3398 is_bytes = true;
3399 rate = 4 * 1024;
3400 burst_size = 4;
3401 break;
3402 default:
3403 continue;
3404 }
3405
3406 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3407 burst_size);
3408 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3409 if (err)
3410 return err;
3411 }
3412
3413 return 0;
3414}
3415
Nogah Frankel579c82e2016-11-25 10:33:42 +01003416static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003417{
3418 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003419 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003420 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003421 int max_trap_groups;
3422 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003423 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003424 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003425
3426 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3427 return -EIO;
3428
3429 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003430 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003431
3432 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003433 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003434 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003435 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3436 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3437 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3438 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
3439 priority = 5;
3440 tc = 5;
3441 break;
3442 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP_IPV4:
3443 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3444 priority = 4;
3445 tc = 4;
3446 break;
3447 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3448 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3449 priority = 3;
3450 tc = 3;
3451 break;
3452 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3453 priority = 2;
3454 tc = 2;
3455 break;
3456 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP_MISS:
3457 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3458 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
3459 priority = 1;
3460 tc = 1;
3461 break;
3462 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003463 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3464 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003465 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003466 break;
3467 default:
3468 continue;
3469 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003470
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003471 if (max_cpu_policers <= policer_id &&
3472 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3473 return -EIO;
3474
3475 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003476 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3477 if (err)
3478 return err;
3479 }
3480
3481 return 0;
3482}
3483
3484static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3485{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003486 int i;
3487 int err;
3488
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003489 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3490 if (err)
3491 return err;
3492
Nogah Frankel579c82e2016-11-25 10:33:42 +01003493 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003494 if (err)
3495 return err;
3496
Nogah Frankel45449132016-11-25 10:33:35 +01003497 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003498 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003499 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003500 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003501 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003502 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003503
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003504 }
3505 return 0;
3506
Nogah Frankel45449132016-11-25 10:33:35 +01003507err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003508 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003509 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003510 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003511 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003512 }
3513 return err;
3514}
3515
3516static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3517{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003518 int i;
3519
Nogah Frankel45449132016-11-25 10:33:35 +01003520 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003521 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003522 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003523 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003524 }
3525}
3526
3527static int __mlxsw_sp_flood_init(struct mlxsw_core *mlxsw_core,
3528 enum mlxsw_reg_sfgc_type type,
3529 enum mlxsw_reg_sfgc_bridge_type bridge_type)
3530{
3531 enum mlxsw_flood_table_type table_type;
3532 enum mlxsw_sp_flood_table flood_table;
3533 char sfgc_pl[MLXSW_REG_SFGC_LEN];
3534
Ido Schimmel19ae6122015-12-15 16:03:39 +01003535 if (bridge_type == MLXSW_REG_SFGC_BRIDGE_TYPE_VFID)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003536 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID;
Ido Schimmel19ae6122015-12-15 16:03:39 +01003537 else
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003538 table_type = MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST;
Ido Schimmel19ae6122015-12-15 16:03:39 +01003539
Nogah Frankel71c365b2017-02-09 14:54:46 +01003540 switch (type) {
3541 case MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST:
Ido Schimmel19ae6122015-12-15 16:03:39 +01003542 flood_table = MLXSW_SP_FLOOD_TABLE_UC;
Nogah Frankel71c365b2017-02-09 14:54:46 +01003543 break;
3544 case MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4:
Nogah Frankel71c365b2017-02-09 14:54:46 +01003545 flood_table = MLXSW_SP_FLOOD_TABLE_MC;
3546 break;
3547 default:
3548 flood_table = MLXSW_SP_FLOOD_TABLE_BC;
3549 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003550
3551 mlxsw_reg_sfgc_pack(sfgc_pl, type, bridge_type, table_type,
3552 flood_table);
3553 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(sfgc), sfgc_pl);
3554}
3555
3556static int mlxsw_sp_flood_init(struct mlxsw_sp *mlxsw_sp)
3557{
3558 int type, err;
3559
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003560 for (type = 0; type < MLXSW_REG_SFGC_TYPE_MAX; type++) {
3561 if (type == MLXSW_REG_SFGC_TYPE_RESERVED)
3562 continue;
3563
3564 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3565 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID);
3566 if (err)
3567 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003568
3569 err = __mlxsw_sp_flood_init(mlxsw_sp->core, type,
3570 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID);
3571 if (err)
3572 return err;
3573 }
3574
3575 return 0;
3576}
3577
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003578static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3579{
3580 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003581 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003582
3583 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3584 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3585 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3586 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3587 MLXSW_REG_SLCR_LAG_HASH_SIP |
3588 MLXSW_REG_SLCR_LAG_HASH_DIP |
3589 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3590 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3591 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003592 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3593 if (err)
3594 return err;
3595
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003596 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3597 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003598 return -EIO;
3599
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003600 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003601 sizeof(struct mlxsw_sp_upper),
3602 GFP_KERNEL);
3603 if (!mlxsw_sp->lags)
3604 return -ENOMEM;
3605
3606 return 0;
3607}
3608
3609static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3610{
3611 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003612}
3613
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003614static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3615{
3616 char htgt_pl[MLXSW_REG_HTGT_LEN];
3617
Nogah Frankel579c82e2016-11-25 10:33:42 +01003618 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3619 MLXSW_REG_HTGT_INVALID_POLICER,
3620 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3621 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003622 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3623}
3624
Jiri Pirko202d6f42017-04-18 16:55:33 +02003625static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create);
3626
3627static int mlxsw_sp_dummy_fid_init(struct mlxsw_sp *mlxsw_sp)
3628{
3629 return mlxsw_sp_vfid_op(mlxsw_sp, MLXSW_SP_DUMMY_FID, true);
3630}
3631
3632static void mlxsw_sp_dummy_fid_fini(struct mlxsw_sp *mlxsw_sp)
3633{
3634 mlxsw_sp_vfid_op(mlxsw_sp, MLXSW_SP_DUMMY_FID, false);
3635}
3636
Jiri Pirkob2f10572016-04-08 19:11:23 +02003637static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003638 const struct mlxsw_bus_info *mlxsw_bus_info)
3639{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003640 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003641 int err;
3642
3643 mlxsw_sp->core = mlxsw_core;
3644 mlxsw_sp->bus_info = mlxsw_bus_info;
Ido Schimmel14d39462016-06-20 23:04:15 +02003645 INIT_LIST_HEAD(&mlxsw_sp->fids);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003646 INIT_LIST_HEAD(&mlxsw_sp->vfids.list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003647
Yotam Gigi6b742192017-05-23 21:56:29 +02003648 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3649 if (err) {
3650 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3651 return err;
3652 }
3653
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003654 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3655 if (err) {
3656 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3657 return err;
3658 }
3659
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003660 err = mlxsw_sp_traps_init(mlxsw_sp);
3661 if (err) {
Nogah Frankel45449132016-11-25 10:33:35 +01003662 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3663 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003664 }
3665
3666 err = mlxsw_sp_flood_init(mlxsw_sp);
3667 if (err) {
3668 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize flood tables\n");
3669 goto err_flood_init;
3670 }
3671
3672 err = mlxsw_sp_buffers_init(mlxsw_sp);
3673 if (err) {
3674 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3675 goto err_buffers_init;
3676 }
3677
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003678 err = mlxsw_sp_lag_init(mlxsw_sp);
3679 if (err) {
3680 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3681 goto err_lag_init;
3682 }
3683
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003684 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3685 if (err) {
3686 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3687 goto err_switchdev_init;
3688 }
3689
Ido Schimmel464dce12016-07-02 11:00:15 +02003690 err = mlxsw_sp_router_init(mlxsw_sp);
3691 if (err) {
3692 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3693 goto err_router_init;
3694 }
3695
Yotam Gigi763b4b72016-07-21 12:03:17 +02003696 err = mlxsw_sp_span_init(mlxsw_sp);
3697 if (err) {
3698 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3699 goto err_span_init;
3700 }
3701
Jiri Pirko22a67762017-02-03 10:29:07 +01003702 err = mlxsw_sp_acl_init(mlxsw_sp);
3703 if (err) {
3704 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3705 goto err_acl_init;
3706 }
3707
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003708 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3709 if (err) {
3710 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3711 goto err_counter_pool_init;
3712 }
3713
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003714 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3715 if (err) {
3716 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3717 goto err_dpipe_init;
3718 }
3719
Jiri Pirko202d6f42017-04-18 16:55:33 +02003720 err = mlxsw_sp_dummy_fid_init(mlxsw_sp);
3721 if (err) {
3722 dev_err(mlxsw_sp->bus_info->dev, "Failed to init dummy FID\n");
3723 goto err_dummy_fid_init;
3724 }
3725
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003726 err = mlxsw_sp_ports_create(mlxsw_sp);
3727 if (err) {
3728 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3729 goto err_ports_create;
3730 }
3731
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003732 return 0;
3733
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003734err_ports_create:
Jiri Pirko202d6f42017-04-18 16:55:33 +02003735 mlxsw_sp_dummy_fid_fini(mlxsw_sp);
3736err_dummy_fid_init:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003737 mlxsw_sp_dpipe_fini(mlxsw_sp);
3738err_dpipe_init:
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003739 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3740err_counter_pool_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003741 mlxsw_sp_acl_fini(mlxsw_sp);
3742err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02003743 mlxsw_sp_span_fini(mlxsw_sp);
3744err_span_init:
Ido Schimmel464dce12016-07-02 11:00:15 +02003745 mlxsw_sp_router_fini(mlxsw_sp);
3746err_router_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003747 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003748err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003749 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003750err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003751 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003752err_buffers_init:
3753err_flood_init:
3754 mlxsw_sp_traps_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003755 return err;
3756}
3757
Jiri Pirkob2f10572016-04-08 19:11:23 +02003758static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003759{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003760 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003761
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003762 mlxsw_sp_ports_remove(mlxsw_sp);
Jiri Pirko202d6f42017-04-18 16:55:33 +02003763 mlxsw_sp_dummy_fid_fini(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003764 mlxsw_sp_dpipe_fini(mlxsw_sp);
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +01003765 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003766 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003767 mlxsw_sp_span_fini(mlxsw_sp);
Ido Schimmel464dce12016-07-02 11:00:15 +02003768 mlxsw_sp_router_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003769 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003770 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003771 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003772 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02003773 WARN_ON(!list_empty(&mlxsw_sp->vfids.list));
Ido Schimmel14d39462016-06-20 23:04:15 +02003774 WARN_ON(!list_empty(&mlxsw_sp->fids));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003775}
3776
3777static struct mlxsw_config_profile mlxsw_sp_config_profile = {
3778 .used_max_vepa_channels = 1,
3779 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003780 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003781 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003782 .used_max_pgt = 1,
3783 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003784 .used_flood_tables = 1,
3785 .used_flood_mode = 1,
3786 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003787 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003788 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003789 .max_fid_flood_tables = 3,
Ido Schimmel19ae6122015-12-15 16:03:39 +01003790 .fid_flood_table_size = MLXSW_SP_VFID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003791 .used_max_ib_mc = 1,
3792 .max_ib_mc = 0,
3793 .used_max_pkey = 1,
3794 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003795 .used_kvd_split_data = 1,
3796 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
3797 .kvd_hash_single_parts = 2,
3798 .kvd_hash_double_parts = 1,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003799 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003800 .swid_config = {
3801 {
3802 .used_type = 1,
3803 .type = MLXSW_PORT_SWID_TYPE_ETH,
3804 }
3805 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003806 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003807};
3808
3809static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003810 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003811 .priv_size = sizeof(struct mlxsw_sp),
3812 .init = mlxsw_sp_init,
3813 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003814 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003815 .port_split = mlxsw_sp_port_split,
3816 .port_unsplit = mlxsw_sp_port_unsplit,
3817 .sb_pool_get = mlxsw_sp_sb_pool_get,
3818 .sb_pool_set = mlxsw_sp_sb_pool_set,
3819 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
3820 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
3821 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
3822 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
3823 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
3824 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
3825 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
3826 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
3827 .txhdr_construct = mlxsw_sp_txhdr_construct,
3828 .txhdr_len = MLXSW_TXHDR_LEN,
3829 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003830};
3831
Jiri Pirko22a67762017-02-03 10:29:07 +01003832bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003833{
3834 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
3835}
3836
Jiri Pirko1182e532017-03-06 21:25:20 +01003837static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07003838{
Jiri Pirko1182e532017-03-06 21:25:20 +01003839 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07003840 int ret = 0;
3841
3842 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01003843 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07003844 ret = 1;
3845 }
3846
3847 return ret;
3848}
3849
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003850static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
3851{
Jiri Pirko1182e532017-03-06 21:25:20 +01003852 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003853
3854 if (mlxsw_sp_port_dev_check(dev))
3855 return netdev_priv(dev);
3856
Jiri Pirko1182e532017-03-06 21:25:20 +01003857 mlxsw_sp_port = NULL;
3858 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003859
Jiri Pirko1182e532017-03-06 21:25:20 +01003860 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003861}
3862
Ido Schimmel4724ba562017-03-10 08:53:39 +01003863struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003864{
3865 struct mlxsw_sp_port *mlxsw_sp_port;
3866
3867 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
3868 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
3869}
3870
3871static struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
3872{
Jiri Pirko1182e532017-03-06 21:25:20 +01003873 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003874
3875 if (mlxsw_sp_port_dev_check(dev))
3876 return netdev_priv(dev);
3877
Jiri Pirko1182e532017-03-06 21:25:20 +01003878 mlxsw_sp_port = NULL;
3879 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
3880 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07003881
Jiri Pirko1182e532017-03-06 21:25:20 +01003882 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02003883}
3884
3885struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
3886{
3887 struct mlxsw_sp_port *mlxsw_sp_port;
3888
3889 rcu_read_lock();
3890 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
3891 if (mlxsw_sp_port)
3892 dev_hold(mlxsw_sp_port->dev);
3893 rcu_read_unlock();
3894 return mlxsw_sp_port;
3895}
3896
3897void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
3898{
3899 dev_put(mlxsw_sp_port->dev);
3900}
3901
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003902static bool mlxsw_sp_lag_port_fid_member(struct mlxsw_sp_port *lag_port,
3903 u16 fid)
3904{
3905 if (mlxsw_sp_fid_is_vfid(fid))
3906 return mlxsw_sp_port_vport_find_by_fid(lag_port, fid);
3907 else
3908 return test_bit(fid, lag_port->active_vlans);
3909}
3910
3911static bool mlxsw_sp_port_fdb_should_flush(struct mlxsw_sp_port *mlxsw_sp_port,
3912 u16 fid)
Ido Schimmel039c49a2016-01-27 15:20:18 +01003913{
3914 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003915 u8 local_port = mlxsw_sp_port->local_port;
3916 u16 lag_id = mlxsw_sp_port->lag_id;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003917 u64 max_lag_members;
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003918 int i, count = 0;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003919
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003920 if (!mlxsw_sp_port->lagged)
3921 return true;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003922
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003923 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
3924 MAX_LAG_MEMBERS);
3925 for (i = 0; i < max_lag_members; i++) {
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003926 struct mlxsw_sp_port *lag_port;
3927
3928 lag_port = mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i);
3929 if (!lag_port || lag_port->local_port == local_port)
3930 continue;
3931 if (mlxsw_sp_lag_port_fid_member(lag_port, fid))
3932 count++;
3933 }
3934
3935 return !count;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003936}
3937
3938static int
3939mlxsw_sp_port_fdb_flush_by_port_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3940 u16 fid)
3941{
3942 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3943 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3944
3945 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID);
3946 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3947 mlxsw_reg_sfdf_port_fid_system_port_set(sfdf_pl,
3948 mlxsw_sp_port->local_port);
3949
Ido Schimmel22305372016-06-20 23:04:21 +02003950 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using Port=%d, FID=%d\n",
3951 mlxsw_sp_port->local_port, fid);
3952
Ido Schimmel039c49a2016-01-27 15:20:18 +01003953 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3954}
3955
3956static int
Ido Schimmel039c49a2016-01-27 15:20:18 +01003957mlxsw_sp_port_fdb_flush_by_lag_id_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
3958 u16 fid)
3959{
3960 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3961 char sfdf_pl[MLXSW_REG_SFDF_LEN];
3962
3963 mlxsw_reg_sfdf_pack(sfdf_pl, MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID);
3964 mlxsw_reg_sfdf_fid_set(sfdf_pl, fid);
3965 mlxsw_reg_sfdf_lag_fid_lag_id_set(sfdf_pl, mlxsw_sp_port->lag_id);
3966
Ido Schimmel22305372016-06-20 23:04:21 +02003967 netdev_dbg(mlxsw_sp_port->dev, "FDB flushed using LAG ID=%d, FID=%d\n",
3968 mlxsw_sp_port->lag_id, fid);
3969
Ido Schimmel039c49a2016-01-27 15:20:18 +01003970 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfdf), sfdf_pl);
3971}
3972
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003973int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid)
Ido Schimmel039c49a2016-01-27 15:20:18 +01003974{
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003975 if (!mlxsw_sp_port_fdb_should_flush(mlxsw_sp_port, fid))
3976 return 0;
Ido Schimmel039c49a2016-01-27 15:20:18 +01003977
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003978 if (mlxsw_sp_port->lagged)
3979 return mlxsw_sp_port_fdb_flush_by_lag_id_fid(mlxsw_sp_port,
Ido Schimmel039c49a2016-01-27 15:20:18 +01003980 fid);
3981 else
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02003982 return mlxsw_sp_port_fdb_flush_by_port_fid(mlxsw_sp_port, fid);
Ido Schimmel039c49a2016-01-27 15:20:18 +01003983}
3984
Ido Schimmel701b1862016-07-04 08:23:16 +02003985static void mlxsw_sp_master_bridge_gone_sync(struct mlxsw_sp *mlxsw_sp)
3986{
3987 struct mlxsw_sp_fid *f, *tmp;
3988
3989 list_for_each_entry_safe(f, tmp, &mlxsw_sp->fids, list)
3990 if (--f->ref_count == 0)
3991 mlxsw_sp_fid_destroy(mlxsw_sp, f);
3992 else
3993 WARN_ON_ONCE(1);
3994}
3995
Ido Schimmel7117a572016-06-20 23:04:06 +02003996static bool mlxsw_sp_master_bridge_check(struct mlxsw_sp *mlxsw_sp,
3997 struct net_device *br_dev)
3998{
Ido Schimmel5f6935c2017-05-16 19:38:26 +02003999 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
4000
4001 return !master_bridge->dev || master_bridge->dev == br_dev;
Ido Schimmel7117a572016-06-20 23:04:06 +02004002}
4003
4004static void mlxsw_sp_master_bridge_inc(struct mlxsw_sp *mlxsw_sp,
4005 struct net_device *br_dev)
4006{
Ido Schimmel5f6935c2017-05-16 19:38:26 +02004007 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
4008
4009 master_bridge->dev = br_dev;
4010 master_bridge->ref_count++;
Ido Schimmel7117a572016-06-20 23:04:06 +02004011}
4012
4013static void mlxsw_sp_master_bridge_dec(struct mlxsw_sp *mlxsw_sp)
4014{
Ido Schimmel5f6935c2017-05-16 19:38:26 +02004015 struct mlxsw_sp_upper *master_bridge = mlxsw_sp_master_bridge(mlxsw_sp);
4016
4017 if (--master_bridge->ref_count == 0) {
4018 master_bridge->dev = NULL;
Ido Schimmel701b1862016-07-04 08:23:16 +02004019 /* It's possible upper VLAN devices are still holding
4020 * references to underlying FIDs. Drop the reference
4021 * and release the resources if it was the last one.
4022 * If it wasn't, then something bad happened.
4023 */
4024 mlxsw_sp_master_bridge_gone_sync(mlxsw_sp);
4025 }
Ido Schimmel7117a572016-06-20 23:04:06 +02004026}
4027
4028static int mlxsw_sp_port_bridge_join(struct mlxsw_sp_port *mlxsw_sp_port,
4029 struct net_device *br_dev)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004030{
4031 struct net_device *dev = mlxsw_sp_port->dev;
4032 int err;
4033
4034 /* When port is not bridged untagged packets are tagged with
4035 * PVID=VID=1, thereby creating an implicit VLAN interface in
4036 * the device. Remove it and let bridge code take care of its
4037 * own VLANs.
4038 */
4039 err = mlxsw_sp_port_kill_vid(dev, 0, 1);
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01004040 if (err)
4041 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004042
Ido Schimmel7117a572016-06-20 23:04:06 +02004043 mlxsw_sp_master_bridge_inc(mlxsw_sp_port->mlxsw_sp, br_dev);
4044
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01004045 mlxsw_sp_port->learning = 1;
4046 mlxsw_sp_port->learning_sync = 1;
4047 mlxsw_sp_port->uc_flood = 1;
Nogah Frankel71c365b2017-02-09 14:54:46 +01004048 mlxsw_sp_port->mc_flood = 1;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01004049 mlxsw_sp_port->mc_router = 0;
4050 mlxsw_sp_port->mc_disabled = 1;
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01004051 mlxsw_sp_port->bridged = 1;
4052
4053 return 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004054}
4055
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004056static void mlxsw_sp_port_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004057{
4058 struct net_device *dev = mlxsw_sp_port->dev;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01004059
Ido Schimmel28a01d22016-02-18 11:30:02 +01004060 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
4061
Ido Schimmel7117a572016-06-20 23:04:06 +02004062 mlxsw_sp_master_bridge_dec(mlxsw_sp_port->mlxsw_sp);
4063
Ido Schimmel6c72a3d2016-01-04 10:42:26 +01004064 mlxsw_sp_port->learning = 0;
4065 mlxsw_sp_port->learning_sync = 0;
4066 mlxsw_sp_port->uc_flood = 0;
Nogah Frankel71c365b2017-02-09 14:54:46 +01004067 mlxsw_sp_port->mc_flood = 0;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01004068 mlxsw_sp_port->mc_router = 0;
Ido Schimmel5a8f4522016-01-04 10:42:25 +01004069 mlxsw_sp_port->bridged = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004070
4071 /* Add implicit VLAN interface in the device, so that untagged
4072 * packets will be classified to the default vFID.
4073 */
Ido Schimmel82e6db02016-06-20 23:04:04 +02004074 mlxsw_sp_port_add_vid(dev, 0, 1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004075}
4076
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004077static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004078{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004079 char sldr_pl[MLXSW_REG_SLDR_LEN];
4080
4081 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4082 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4083}
4084
4085static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4086{
4087 char sldr_pl[MLXSW_REG_SLDR_LEN];
4088
4089 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4090 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4091}
4092
4093static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4094 u16 lag_id, u8 port_index)
4095{
4096 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4097 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4098
4099 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4100 lag_id, port_index);
4101 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4102}
4103
4104static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4105 u16 lag_id)
4106{
4107 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4108 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4109
4110 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4111 lag_id);
4112 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4113}
4114
4115static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4116 u16 lag_id)
4117{
4118 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4119 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4120
4121 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4122 lag_id);
4123 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4124}
4125
4126static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4127 u16 lag_id)
4128{
4129 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4130 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4131
4132 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4133 lag_id);
4134 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4135}
4136
4137static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4138 struct net_device *lag_dev,
4139 u16 *p_lag_id)
4140{
4141 struct mlxsw_sp_upper *lag;
4142 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004143 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004144 int i;
4145
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004146 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4147 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004148 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4149 if (lag->ref_count) {
4150 if (lag->dev == lag_dev) {
4151 *p_lag_id = i;
4152 return 0;
4153 }
4154 } else if (free_lag_id < 0) {
4155 free_lag_id = i;
4156 }
4157 }
4158 if (free_lag_id < 0)
4159 return -EBUSY;
4160 *p_lag_id = free_lag_id;
4161 return 0;
4162}
4163
4164static bool
4165mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4166 struct net_device *lag_dev,
4167 struct netdev_lag_upper_info *lag_upper_info)
4168{
4169 u16 lag_id;
4170
4171 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0)
4172 return false;
4173 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
4174 return false;
4175 return true;
4176}
4177
4178static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4179 u16 lag_id, u8 *p_port_index)
4180{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004181 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004182 int i;
4183
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004184 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4185 MAX_LAG_MEMBERS);
4186 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004187 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4188 *p_port_index = i;
4189 return 0;
4190 }
4191 }
4192 return -EBUSY;
4193}
4194
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004195static void
4196mlxsw_sp_port_pvid_vport_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel186962e2017-03-10 08:53:36 +01004197 struct net_device *lag_dev, u16 lag_id)
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004198{
Ido Schimmelce95e152017-05-26 08:37:27 +02004199 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004200 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel11943ff2016-07-02 11:00:12 +02004201 struct mlxsw_sp_fid *f;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004202
4203 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
4204 if (WARN_ON(!mlxsw_sp_vport))
4205 return;
4206
Ido Schimmelce95e152017-05-26 08:37:27 +02004207 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
Ido Schimmel11943ff2016-07-02 11:00:12 +02004208 /* If vPort is assigned a RIF, then leave it since it's no
4209 * longer valid.
4210 */
4211 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4212 if (f)
Ido Schimmelce95e152017-05-26 08:37:27 +02004213 f->leave(mlxsw_sp_port_vlan);
Ido Schimmel11943ff2016-07-02 11:00:12 +02004214
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004215 mlxsw_sp_vport->lag_id = lag_id;
4216 mlxsw_sp_vport->lagged = 1;
Ido Schimmel186962e2017-03-10 08:53:36 +01004217 mlxsw_sp_vport->dev = lag_dev;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004218}
4219
4220static void
4221mlxsw_sp_port_pvid_vport_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4222{
Ido Schimmelce95e152017-05-26 08:37:27 +02004223 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004224 struct mlxsw_sp_port *mlxsw_sp_vport;
Ido Schimmel11943ff2016-07-02 11:00:12 +02004225 struct mlxsw_sp_fid *f;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004226
4227 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, 1);
4228 if (WARN_ON(!mlxsw_sp_vport))
4229 return;
4230
Ido Schimmelce95e152017-05-26 08:37:27 +02004231 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
Ido Schimmel11943ff2016-07-02 11:00:12 +02004232 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
4233 if (f)
Ido Schimmelce95e152017-05-26 08:37:27 +02004234 f->leave(mlxsw_sp_port_vlan);
Ido Schimmel11943ff2016-07-02 11:00:12 +02004235
Ido Schimmel186962e2017-03-10 08:53:36 +01004236 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004237 mlxsw_sp_vport->lagged = 0;
4238}
4239
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004240static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4241 struct net_device *lag_dev)
4242{
4243 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4244 struct mlxsw_sp_upper *lag;
4245 u16 lag_id;
4246 u8 port_index;
4247 int err;
4248
4249 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4250 if (err)
4251 return err;
4252 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4253 if (!lag->ref_count) {
4254 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4255 if (err)
4256 return err;
4257 lag->dev = lag_dev;
4258 }
4259
4260 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4261 if (err)
4262 return err;
4263 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4264 if (err)
4265 goto err_col_port_add;
4266 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4267 if (err)
4268 goto err_col_port_enable;
4269
4270 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4271 mlxsw_sp_port->local_port);
4272 mlxsw_sp_port->lag_id = lag_id;
4273 mlxsw_sp_port->lagged = 1;
4274 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004275
Ido Schimmel186962e2017-03-10 08:53:36 +01004276 mlxsw_sp_port_pvid_vport_lag_join(mlxsw_sp_port, lag_dev, lag_id);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004277
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004278 return 0;
4279
Ido Schimmel51554db2016-05-06 22:18:39 +02004280err_col_port_enable:
4281 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004282err_col_port_add:
4283 if (!lag->ref_count)
4284 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004285 return err;
4286}
4287
Ido Schimmel82e6db02016-06-20 23:04:04 +02004288static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4289 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004290{
4291 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004292 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004293 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004294
4295 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004296 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004297 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4298 WARN_ON(lag->ref_count == 0);
4299
Ido Schimmel82e6db02016-06-20 23:04:04 +02004300 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4301 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004302
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004303 if (mlxsw_sp_port->bridged) {
4304 mlxsw_sp_port_active_vlans_del(mlxsw_sp_port);
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004305 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004306 }
4307
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004308 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004309 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004310
4311 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4312 mlxsw_sp_port->local_port);
4313 mlxsw_sp_port->lagged = 0;
4314 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004315
4316 mlxsw_sp_port_pvid_vport_lag_leave(mlxsw_sp_port);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004317}
4318
Jiri Pirko74581202015-12-03 12:12:30 +01004319static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4320 u16 lag_id)
4321{
4322 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4323 char sldr_pl[MLXSW_REG_SLDR_LEN];
4324
4325 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4326 mlxsw_sp_port->local_port);
4327 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4328}
4329
4330static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4331 u16 lag_id)
4332{
4333 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4334 char sldr_pl[MLXSW_REG_SLDR_LEN];
4335
4336 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4337 mlxsw_sp_port->local_port);
4338 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4339}
4340
4341static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4342 bool lag_tx_enabled)
4343{
4344 if (lag_tx_enabled)
4345 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4346 mlxsw_sp_port->lag_id);
4347 else
4348 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4349 mlxsw_sp_port->lag_id);
4350}
4351
4352static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4353 struct netdev_lag_lower_state_info *info)
4354{
4355 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4356}
4357
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004358static int mlxsw_sp_port_vlan_link(struct mlxsw_sp_port *mlxsw_sp_port,
4359 struct net_device *vlan_dev)
4360{
4361 struct mlxsw_sp_port *mlxsw_sp_vport;
4362 u16 vid = vlan_dev_vlan_id(vlan_dev);
4363
4364 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02004365 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004366 return -EINVAL;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004367
4368 mlxsw_sp_vport->dev = vlan_dev;
4369
4370 return 0;
4371}
4372
Ido Schimmel82e6db02016-06-20 23:04:04 +02004373static void mlxsw_sp_port_vlan_unlink(struct mlxsw_sp_port *mlxsw_sp_port,
4374 struct net_device *vlan_dev)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004375{
4376 struct mlxsw_sp_port *mlxsw_sp_vport;
4377 u16 vid = vlan_dev_vlan_id(vlan_dev);
4378
4379 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel423b9372016-06-20 23:04:03 +02004380 if (WARN_ON(!mlxsw_sp_vport))
Ido Schimmel82e6db02016-06-20 23:04:04 +02004381 return;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004382
4383 mlxsw_sp_vport->dev = mlxsw_sp_port->dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004384}
4385
Jiri Pirko2b94e582017-04-18 16:55:37 +02004386static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4387 bool enable)
4388{
4389 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4390 enum mlxsw_reg_spms_state spms_state;
4391 char *spms_pl;
4392 u16 vid;
4393 int err;
4394
4395 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4396 MLXSW_REG_SPMS_STATE_DISCARDING;
4397
4398 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4399 if (!spms_pl)
4400 return -ENOMEM;
4401 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4402
4403 for (vid = 0; vid < VLAN_N_VID; vid++)
4404 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4405
4406 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4407 kfree(spms_pl);
4408 return err;
4409}
4410
4411static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4412{
4413 int err;
4414
Ido Schimmel4aafc362017-05-26 08:37:25 +02004415 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004416 if (err)
4417 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004418 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4419 if (err)
4420 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004421 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4422 true, false);
4423 if (err)
4424 goto err_port_vlan_set;
4425 return 0;
4426
4427err_port_vlan_set:
4428 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004429err_port_stp_set:
4430 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004431 return err;
4432}
4433
4434static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4435{
4436 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4437 false, false);
4438 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004439 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004440}
4441
Jiri Pirko74581202015-12-03 12:12:30 +01004442static int mlxsw_sp_netdevice_port_upper_event(struct net_device *dev,
4443 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004444{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004445 struct netdev_notifier_changeupper_info *info;
4446 struct mlxsw_sp_port *mlxsw_sp_port;
4447 struct net_device *upper_dev;
4448 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004449 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004450
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004451 mlxsw_sp_port = netdev_priv(dev);
4452 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4453 info = ptr;
4454
4455 switch (event) {
4456 case NETDEV_PRECHANGEUPPER:
4457 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004458 if (!is_vlan_dev(upper_dev) &&
4459 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004460 !netif_is_bridge_master(upper_dev) &&
Jiri Pirko2b94e582017-04-18 16:55:37 +02004461 !netif_is_ovs_master(upper_dev))
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004462 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004463 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004464 break;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004465 /* HW limitation forbids to put ports to multiple bridges. */
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004466 if (netif_is_bridge_master(upper_dev) &&
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004467 !mlxsw_sp_master_bridge_check(mlxsw_sp, upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004468 return -EINVAL;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004469 if (netif_is_lag_master(upper_dev) &&
4470 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
4471 info->upper_info))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004472 return -EINVAL;
Ido Schimmel6ec43902016-06-20 23:04:01 +02004473 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev))
4474 return -EINVAL;
4475 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
4476 !netif_is_lag_master(vlan_dev_real_dev(upper_dev)))
4477 return -EINVAL;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004478 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev))
4479 return -EINVAL;
4480 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev))
4481 return -EINVAL;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004482 break;
4483 case NETDEV_CHANGEUPPER:
4484 upper_dev = info->upper_dev;
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004485 if (is_vlan_dev(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004486 if (info->linking)
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004487 err = mlxsw_sp_port_vlan_link(mlxsw_sp_port,
4488 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004489 else
Jiri Pirkob51df792017-04-18 16:55:31 +02004490 mlxsw_sp_port_vlan_unlink(mlxsw_sp_port,
4491 upper_dev);
Ido Schimmel9589a7b52015-12-15 16:03:43 +01004492 } else if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004493 if (info->linking)
4494 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4495 upper_dev);
4496 else
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004497 mlxsw_sp_port_bridge_leave(mlxsw_sp_port);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004498 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004499 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004500 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4501 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004502 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004503 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4504 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004505 } else if (netif_is_ovs_master(upper_dev)) {
4506 if (info->linking)
4507 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4508 else
4509 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004510 } else {
4511 err = -EINVAL;
4512 WARN_ON(1);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004513 }
4514 break;
4515 }
4516
Ido Schimmel80bedf12016-06-20 23:03:59 +02004517 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004518}
4519
Jiri Pirko74581202015-12-03 12:12:30 +01004520static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4521 unsigned long event, void *ptr)
4522{
4523 struct netdev_notifier_changelowerstate_info *info;
4524 struct mlxsw_sp_port *mlxsw_sp_port;
4525 int err;
4526
4527 mlxsw_sp_port = netdev_priv(dev);
4528 info = ptr;
4529
4530 switch (event) {
4531 case NETDEV_CHANGELOWERSTATE:
4532 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4533 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4534 info->lower_state_info);
4535 if (err)
4536 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4537 }
4538 break;
4539 }
4540
Ido Schimmel80bedf12016-06-20 23:03:59 +02004541 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004542}
4543
4544static int mlxsw_sp_netdevice_port_event(struct net_device *dev,
4545 unsigned long event, void *ptr)
4546{
4547 switch (event) {
4548 case NETDEV_PRECHANGEUPPER:
4549 case NETDEV_CHANGEUPPER:
4550 return mlxsw_sp_netdevice_port_upper_event(dev, event, ptr);
4551 case NETDEV_CHANGELOWERSTATE:
4552 return mlxsw_sp_netdevice_port_lower_event(dev, event, ptr);
4553 }
4554
Ido Schimmel80bedf12016-06-20 23:03:59 +02004555 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004556}
4557
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004558static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4559 unsigned long event, void *ptr)
4560{
4561 struct net_device *dev;
4562 struct list_head *iter;
4563 int ret;
4564
4565 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4566 if (mlxsw_sp_port_dev_check(dev)) {
4567 ret = mlxsw_sp_netdevice_port_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004568 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004569 return ret;
4570 }
4571 }
4572
Ido Schimmel80bedf12016-06-20 23:03:59 +02004573 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004574}
4575
Ido Schimmel701b1862016-07-04 08:23:16 +02004576static int mlxsw_sp_master_bridge_vlan_link(struct mlxsw_sp *mlxsw_sp,
4577 struct net_device *vlan_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004578{
Ido Schimmel701b1862016-07-04 08:23:16 +02004579 u16 fid = vlan_dev_vlan_id(vlan_dev);
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004580 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004581
Ido Schimmel701b1862016-07-04 08:23:16 +02004582 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
4583 if (!f) {
4584 f = mlxsw_sp_fid_create(mlxsw_sp, fid);
4585 if (IS_ERR(f))
4586 return PTR_ERR(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004587 }
4588
Ido Schimmel701b1862016-07-04 08:23:16 +02004589 f->ref_count++;
4590
4591 return 0;
4592}
4593
4594static void mlxsw_sp_master_bridge_vlan_unlink(struct mlxsw_sp *mlxsw_sp,
4595 struct net_device *vlan_dev)
4596{
4597 u16 fid = vlan_dev_vlan_id(vlan_dev);
4598 struct mlxsw_sp_fid *f;
4599
4600 f = mlxsw_sp_fid_find(mlxsw_sp, fid);
Arkadi Sharshevskybf952332017-03-17 09:38:00 +01004601 if (f && f->rif)
4602 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->rif);
Ido Schimmel701b1862016-07-04 08:23:16 +02004603 if (f && --f->ref_count == 0)
4604 mlxsw_sp_fid_destroy(mlxsw_sp, f);
4605}
4606
4607static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
4608 unsigned long event, void *ptr)
4609{
4610 struct netdev_notifier_changeupper_info *info;
4611 struct net_device *upper_dev;
4612 struct mlxsw_sp *mlxsw_sp;
Ido Schimmelb4149702017-03-10 08:53:34 +01004613 int err = 0;
Ido Schimmel701b1862016-07-04 08:23:16 +02004614
4615 mlxsw_sp = mlxsw_sp_lower_get(br_dev);
4616 if (!mlxsw_sp)
4617 return 0;
Ido Schimmel701b1862016-07-04 08:23:16 +02004618
4619 info = ptr;
4620
4621 switch (event) {
Ido Schimmelb4149702017-03-10 08:53:34 +01004622 case NETDEV_PRECHANGEUPPER:
Ido Schimmel701b1862016-07-04 08:23:16 +02004623 upper_dev = info->upper_dev;
Ido Schimmelb1e45522017-04-30 19:47:14 +03004624 if (!is_vlan_dev(upper_dev))
Ido Schimmelb4149702017-03-10 08:53:34 +01004625 return -EINVAL;
4626 if (is_vlan_dev(upper_dev) &&
Ido Schimmel5f6935c2017-05-16 19:38:26 +02004627 br_dev != mlxsw_sp_master_bridge(mlxsw_sp)->dev)
Ido Schimmelb4149702017-03-10 08:53:34 +01004628 return -EINVAL;
4629 break;
4630 case NETDEV_CHANGEUPPER:
4631 upper_dev = info->upper_dev;
4632 if (is_vlan_dev(upper_dev)) {
4633 if (info->linking)
4634 err = mlxsw_sp_master_bridge_vlan_link(mlxsw_sp,
4635 upper_dev);
4636 else
4637 mlxsw_sp_master_bridge_vlan_unlink(mlxsw_sp,
4638 upper_dev);
Ido Schimmel701b1862016-07-04 08:23:16 +02004639 } else {
Ido Schimmelb4149702017-03-10 08:53:34 +01004640 err = -EINVAL;
4641 WARN_ON(1);
Ido Schimmel701b1862016-07-04 08:23:16 +02004642 }
4643 break;
4644 }
4645
Ido Schimmelb4149702017-03-10 08:53:34 +01004646 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004647}
4648
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004649static u16 mlxsw_sp_avail_vfid_get(const struct mlxsw_sp *mlxsw_sp)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004650{
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004651 return find_first_zero_bit(mlxsw_sp->vfids.mapped,
Ido Schimmel99724c12016-07-04 08:23:14 +02004652 MLXSW_SP_VFID_MAX);
4653}
4654
4655static int mlxsw_sp_vfid_op(struct mlxsw_sp *mlxsw_sp, u16 fid, bool create)
4656{
4657 char sfmr_pl[MLXSW_REG_SFMR_LEN];
4658
4659 mlxsw_reg_sfmr_pack(sfmr_pl, !create, fid, 0);
4660 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sfmr), sfmr_pl);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004661}
4662
Ido Schimmelce95e152017-05-26 08:37:27 +02004663static void
4664mlxsw_sp_port_vlan_vfid_leave(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan);
Ido Schimmel1c800752016-06-20 23:04:20 +02004665
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004666static struct mlxsw_sp_fid *mlxsw_sp_vfid_create(struct mlxsw_sp *mlxsw_sp,
4667 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004668{
4669 struct device *dev = mlxsw_sp->bus_info->dev;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004670 struct mlxsw_sp_fid *f;
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004671 u16 vfid, fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004672 int err;
4673
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004674 vfid = mlxsw_sp_avail_vfid_get(mlxsw_sp);
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004675 if (vfid == MLXSW_SP_VFID_MAX) {
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004676 dev_err(dev, "No available vFIDs\n");
4677 return ERR_PTR(-ERANGE);
4678 }
4679
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004680 fid = mlxsw_sp_vfid_to_fid(vfid);
4681 err = mlxsw_sp_vfid_op(mlxsw_sp, fid, true);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004682 if (err) {
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004683 dev_err(dev, "Failed to create FID=%d\n", fid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004684 return ERR_PTR(err);
4685 }
4686
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004687 f = kzalloc(sizeof(*f), GFP_KERNEL);
4688 if (!f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004689 goto err_allocate_vfid;
4690
Ido Schimmelce95e152017-05-26 08:37:27 +02004691 f->leave = mlxsw_sp_port_vlan_vfid_leave;
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004692 f->fid = fid;
4693 f->dev = br_dev;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004694
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004695 list_add(&f->list, &mlxsw_sp->vfids.list);
4696 set_bit(vfid, mlxsw_sp->vfids.mapped);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004697
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004698 return f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004699
4700err_allocate_vfid:
Ido Schimmelc7e920b2016-06-20 23:04:09 +02004701 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004702 return ERR_PTR(-ENOMEM);
4703}
4704
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004705static void mlxsw_sp_vfid_destroy(struct mlxsw_sp *mlxsw_sp,
4706 struct mlxsw_sp_fid *f)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004707{
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004708 u16 vfid = mlxsw_sp_fid_to_vfid(f->fid);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02004709 u16 fid = f->fid;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004710
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004711 clear_bit(vfid, mlxsw_sp->vfids.mapped);
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004712 list_del(&f->list);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004713
Arkadi Sharshevskybf952332017-03-17 09:38:00 +01004714 if (f->rif)
4715 mlxsw_sp_rif_bridge_destroy(mlxsw_sp, f->rif);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004716
Ido Schimmeld0ec8752016-06-20 23:04:12 +02004717 kfree(f);
Ido Schimmel99f44bb2016-07-04 08:23:17 +02004718
4719 mlxsw_sp_vfid_op(mlxsw_sp, fid, false);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004720}
4721
Ido Schimmel99724c12016-07-04 08:23:14 +02004722static int mlxsw_sp_vport_fid_map(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
4723 bool valid)
4724{
4725 enum mlxsw_reg_svfa_mt mt = MLXSW_REG_SVFA_MT_PORT_VID_TO_FID;
4726 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
4727
4728 return mlxsw_sp_port_vid_to_fid_set(mlxsw_sp_vport, mt, valid, fid,
4729 vid);
4730}
4731
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004732static int mlxsw_sp_vport_vfid_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4733 struct net_device *br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004734{
Ido Schimmel4aafc362017-05-26 08:37:25 +02004735 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel0355b592016-06-20 23:04:13 +02004736 struct mlxsw_sp_fid *f;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004737 int err;
4738
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004739 f = mlxsw_sp_vfid_find(mlxsw_sp_vport->mlxsw_sp, br_dev);
Ido Schimmel0355b592016-06-20 23:04:13 +02004740 if (!f) {
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004741 f = mlxsw_sp_vfid_create(mlxsw_sp_vport->mlxsw_sp, br_dev);
Ido Schimmel0355b592016-06-20 23:04:13 +02004742 if (IS_ERR(f))
4743 return PTR_ERR(f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004744 }
4745
Ido Schimmel0355b592016-06-20 23:04:13 +02004746 err = mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, true);
4747 if (err)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004748 goto err_vport_flood_set;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004749
Ido Schimmel0355b592016-06-20 23:04:13 +02004750 err = mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, true);
4751 if (err)
4752 goto err_vport_fid_map;
Ido Schimmel6a9863a2016-02-15 13:19:54 +01004753
Ido Schimmel4aafc362017-05-26 08:37:25 +02004754 mlxsw_sp_port = mlxsw_sp_vport_port(mlxsw_sp_vport);
4755 if (mlxsw_sp_port->nr_port_vid_map++ == 0) {
4756 err = mlxsw_sp_port_vp_mode_trans(mlxsw_sp_port);
4757 if (err)
4758 goto err_port_vp_mode_trans;
4759 }
4760
Ido Schimmel41b996c2016-06-20 23:04:17 +02004761 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, f);
Ido Schimmel0355b592016-06-20 23:04:13 +02004762 f->ref_count++;
Ido Schimmel039c49a2016-01-27 15:20:18 +01004763
Ido Schimmel22305372016-06-20 23:04:21 +02004764 netdev_dbg(mlxsw_sp_vport->dev, "Joined FID=%d\n", f->fid);
4765
Ido Schimmel0355b592016-06-20 23:04:13 +02004766 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004767
Ido Schimmel4aafc362017-05-26 08:37:25 +02004768err_port_vp_mode_trans:
4769 mlxsw_sp_port->nr_port_vid_map--;
4770 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
Ido Schimmel9c4d4422016-06-20 23:04:10 +02004771err_vport_fid_map:
Ido Schimmel0355b592016-06-20 23:04:13 +02004772 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4773err_vport_flood_set:
4774 if (!f->ref_count)
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004775 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
Ido Schimmel0355b592016-06-20 23:04:13 +02004776 return err;
4777}
4778
Ido Schimmelce95e152017-05-26 08:37:27 +02004779static void
4780mlxsw_sp_port_vlan_vfid_leave(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
Ido Schimmel0355b592016-06-20 23:04:13 +02004781{
Ido Schimmelce95e152017-05-26 08:37:27 +02004782 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
4783 struct mlxsw_sp_port *mlxsw_sp_vport;
4784 u16 vid = mlxsw_sp_port_vlan->vid;
4785 struct mlxsw_sp_fid *f;
4786
4787 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
4788 f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel0355b592016-06-20 23:04:13 +02004789
Ido Schimmel22305372016-06-20 23:04:21 +02004790 netdev_dbg(mlxsw_sp_vport->dev, "Left FID=%d\n", f->fid);
4791
Ido Schimmel4aafc362017-05-26 08:37:25 +02004792 mlxsw_sp_vport_fid_set(mlxsw_sp_vport, NULL);
4793 f->ref_count--;
4794
Ido Schimmel4aafc362017-05-26 08:37:25 +02004795 if (mlxsw_sp_port->nr_port_vid_map == 1)
4796 mlxsw_sp_port_vlan_mode_trans(mlxsw_sp_port);
4797 mlxsw_sp_port->nr_port_vid_map--;
4798
Ido Schimmel0355b592016-06-20 23:04:13 +02004799 mlxsw_sp_vport_fid_map(mlxsw_sp_vport, f->fid, false);
4800
4801 mlxsw_sp_vport_flood_set(mlxsw_sp_vport, f->fid, false);
4802
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004803 mlxsw_sp_port_fdb_flush(mlxsw_sp_vport, f->fid);
4804
Ido Schimmel4aafc362017-05-26 08:37:25 +02004805 if (f->ref_count == 0)
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004806 mlxsw_sp_vfid_destroy(mlxsw_sp_vport->mlxsw_sp, f);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004807}
4808
4809static int mlxsw_sp_vport_bridge_join(struct mlxsw_sp_port *mlxsw_sp_vport,
4810 struct net_device *br_dev)
4811{
Ido Schimmel99724c12016-07-04 08:23:14 +02004812 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004813 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
Ido Schimmelce95e152017-05-26 08:37:27 +02004814 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004815 struct net_device *dev = mlxsw_sp_vport->dev;
Ido Schimmelce95e152017-05-26 08:37:27 +02004816 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004817 int err;
4818
Ido Schimmelce95e152017-05-26 08:37:27 +02004819 mlxsw_sp_port = mlxsw_sp_vport_port(mlxsw_sp_vport);
4820 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmel99724c12016-07-04 08:23:14 +02004821 if (f && !WARN_ON(!f->leave))
Ido Schimmelce95e152017-05-26 08:37:27 +02004822 f->leave(mlxsw_sp_port_vlan);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004823
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004824 err = mlxsw_sp_vport_vfid_join(mlxsw_sp_vport, br_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004825 if (err) {
Ido Schimmel0355b592016-06-20 23:04:13 +02004826 netdev_err(dev, "Failed to join vFID\n");
Ido Schimmel99724c12016-07-04 08:23:14 +02004827 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004828 }
4829
4830 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, true);
4831 if (err) {
4832 netdev_err(dev, "Failed to enable learning\n");
4833 goto err_port_vid_learning_set;
4834 }
4835
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004836 mlxsw_sp_vport->learning = 1;
4837 mlxsw_sp_vport->learning_sync = 1;
4838 mlxsw_sp_vport->uc_flood = 1;
Nogah Frankel71c365b2017-02-09 14:54:46 +01004839 mlxsw_sp_vport->mc_flood = 1;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01004840 mlxsw_sp_vport->mc_router = 0;
4841 mlxsw_sp_vport->mc_disabled = 1;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004842 mlxsw_sp_vport->bridged = 1;
4843
4844 return 0;
4845
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004846err_port_vid_learning_set:
Ido Schimmelce95e152017-05-26 08:37:27 +02004847 mlxsw_sp_port_vlan_vfid_leave(mlxsw_sp_port_vlan);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004848 return err;
4849}
4850
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004851static void mlxsw_sp_vport_bridge_leave(struct mlxsw_sp_port *mlxsw_sp_vport)
Ido Schimmel0355b592016-06-20 23:04:13 +02004852{
4853 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_vport);
Ido Schimmelce95e152017-05-26 08:37:27 +02004854 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
4855 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel0355b592016-06-20 23:04:13 +02004856
4857 mlxsw_sp_port_vid_learning_set(mlxsw_sp_vport, vid, false);
4858
Ido Schimmelce95e152017-05-26 08:37:27 +02004859 mlxsw_sp_port = mlxsw_sp_vport_port(mlxsw_sp_vport);
4860 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
4861 mlxsw_sp_port_vlan_vfid_leave(mlxsw_sp_port_vlan);
Ido Schimmel0355b592016-06-20 23:04:13 +02004862
Ido Schimmel0355b592016-06-20 23:04:13 +02004863 mlxsw_sp_vport->learning = 0;
4864 mlxsw_sp_vport->learning_sync = 0;
4865 mlxsw_sp_vport->uc_flood = 0;
Nogah Frankel71c365b2017-02-09 14:54:46 +01004866 mlxsw_sp_vport->mc_flood = 0;
Nogah Frankel8ecd4592017-02-09 14:54:47 +01004867 mlxsw_sp_vport->mc_router = 0;
Ido Schimmel0355b592016-06-20 23:04:13 +02004868 mlxsw_sp_vport->bridged = 0;
4869}
4870
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004871static bool
4872mlxsw_sp_port_master_bridge_check(const struct mlxsw_sp_port *mlxsw_sp_port,
4873 const struct net_device *br_dev)
4874{
4875 struct mlxsw_sp_port *mlxsw_sp_vport;
4876
4877 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
4878 vport.list) {
Ido Schimmel3ba2ebf2016-07-04 08:23:15 +02004879 struct net_device *dev = mlxsw_sp_vport_dev_get(mlxsw_sp_vport);
Ido Schimmel56918b62016-06-20 23:04:18 +02004880
4881 if (dev && dev == br_dev)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004882 return false;
4883 }
4884
4885 return true;
4886}
4887
4888static int mlxsw_sp_netdevice_vport_event(struct net_device *dev,
4889 unsigned long event, void *ptr,
4890 u16 vid)
4891{
4892 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
4893 struct netdev_notifier_changeupper_info *info = ptr;
4894 struct mlxsw_sp_port *mlxsw_sp_vport;
4895 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004896 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004897
4898 mlxsw_sp_vport = mlxsw_sp_port_vport_find(mlxsw_sp_port, vid);
Ido Schimmel1f880612017-03-10 08:53:35 +01004899 if (!mlxsw_sp_vport)
4900 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004901
4902 switch (event) {
4903 case NETDEV_PRECHANGEUPPER:
4904 upper_dev = info->upper_dev;
Ido Schimmelb1e45522017-04-30 19:47:14 +03004905 if (!netif_is_bridge_master(upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004906 return -EINVAL;
Ido Schimmelddbe9932016-06-20 23:04:02 +02004907 if (!info->linking)
4908 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004909 /* We can't have multiple VLAN interfaces configured on
4910 * the same port and being members in the same bridge.
4911 */
Ido Schimmel7179eb52017-03-16 09:08:18 +01004912 if (netif_is_bridge_master(upper_dev) &&
4913 !mlxsw_sp_port_master_bridge_check(mlxsw_sp_port,
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004914 upper_dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004915 return -EINVAL;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004916 break;
4917 case NETDEV_CHANGEUPPER:
4918 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004919 if (netif_is_bridge_master(upper_dev)) {
4920 if (info->linking)
4921 err = mlxsw_sp_vport_bridge_join(mlxsw_sp_vport,
4922 upper_dev);
4923 else
4924 mlxsw_sp_vport_bridge_leave(mlxsw_sp_vport);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004925 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004926 err = -EINVAL;
4927 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004928 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004929 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004930 }
4931
Ido Schimmel80bedf12016-06-20 23:03:59 +02004932 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004933}
4934
Ido Schimmel272c4472015-12-15 16:03:47 +01004935static int mlxsw_sp_netdevice_lag_vport_event(struct net_device *lag_dev,
4936 unsigned long event, void *ptr,
4937 u16 vid)
4938{
4939 struct net_device *dev;
4940 struct list_head *iter;
4941 int ret;
4942
4943 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4944 if (mlxsw_sp_port_dev_check(dev)) {
4945 ret = mlxsw_sp_netdevice_vport_event(dev, event, ptr,
4946 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004947 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004948 return ret;
4949 }
4950 }
4951
Ido Schimmel80bedf12016-06-20 23:03:59 +02004952 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004953}
4954
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004955static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4956 unsigned long event, void *ptr)
4957{
4958 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4959 u16 vid = vlan_dev_vlan_id(vlan_dev);
4960
Ido Schimmel272c4472015-12-15 16:03:47 +01004961 if (mlxsw_sp_port_dev_check(real_dev))
4962 return mlxsw_sp_netdevice_vport_event(real_dev, event, ptr,
4963 vid);
4964 else if (netif_is_lag_master(real_dev))
4965 return mlxsw_sp_netdevice_lag_vport_event(real_dev, event, ptr,
4966 vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004967
Ido Schimmel80bedf12016-06-20 23:03:59 +02004968 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004969}
4970
Ido Schimmelb1e45522017-04-30 19:47:14 +03004971static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4972{
4973 struct netdev_notifier_changeupper_info *info = ptr;
4974
4975 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4976 return false;
4977 return netif_is_l3_master(info->upper_dev);
4978}
4979
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004980static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4981 unsigned long event, void *ptr)
4982{
4983 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004984 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004985
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004986 if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
4987 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004988 else if (mlxsw_sp_is_vrf_event(event, ptr))
4989 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004990 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004991 err = mlxsw_sp_netdevice_port_event(dev, event, ptr);
4992 else if (netif_is_lag_master(dev))
4993 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
Ido Schimmel701b1862016-07-04 08:23:16 +02004994 else if (netif_is_bridge_master(dev))
4995 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004996 else if (is_vlan_dev(dev))
4997 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004998
Ido Schimmel80bedf12016-06-20 23:03:59 +02004999 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01005000}
5001
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005002static struct notifier_block mlxsw_sp_netdevice_nb __read_mostly = {
5003 .notifier_call = mlxsw_sp_netdevice_event,
5004};
5005
Ido Schimmel99724c12016-07-04 08:23:14 +02005006static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
5007 .notifier_call = mlxsw_sp_inetaddr_event,
5008 .priority = 10, /* Must be called before FIB notifier block */
5009};
5010
Jiri Pirkoe7322632016-09-01 10:37:43 +02005011static struct notifier_block mlxsw_sp_router_netevent_nb __read_mostly = {
5012 .notifier_call = mlxsw_sp_router_netevent_event,
5013};
5014
Jiri Pirko1d20d232016-10-27 15:12:59 +02005015static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
5016 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
5017 {0, },
5018};
5019
5020static struct pci_driver mlxsw_sp_pci_driver = {
5021 .name = mlxsw_sp_driver_name,
5022 .id_table = mlxsw_sp_pci_id_table,
5023};
5024
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005025static int __init mlxsw_sp_module_init(void)
5026{
5027 int err;
5028
5029 register_netdevice_notifier(&mlxsw_sp_netdevice_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02005030 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02005031 register_netevent_notifier(&mlxsw_sp_router_netevent_nb);
5032
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005033 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
5034 if (err)
5035 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02005036
5037 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
5038 if (err)
5039 goto err_pci_driver_register;
5040
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005041 return 0;
5042
Jiri Pirko1d20d232016-10-27 15:12:59 +02005043err_pci_driver_register:
5044 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005045err_core_driver_register:
Jiri Pirkoe7322632016-09-01 10:37:43 +02005046 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02005047 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005048 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
5049 return err;
5050}
5051
5052static void __exit mlxsw_sp_module_exit(void)
5053{
Jiri Pirko1d20d232016-10-27 15:12:59 +02005054 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005055 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirkoe7322632016-09-01 10:37:43 +02005056 unregister_netevent_notifier(&mlxsw_sp_router_netevent_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02005057 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005058 unregister_netdevice_notifier(&mlxsw_sp_netdevice_nb);
5059}
5060
5061module_init(mlxsw_sp_module_init);
5062module_exit(mlxsw_sp_module_exit);
5063
5064MODULE_LICENSE("Dual BSD/GPL");
5065MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
5066MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02005067MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02005068MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);