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Daniel Walkerda6df072010-04-23 16:04:20 -07001/* include/linux/msm_mdp.h
2 *
3 * Copyright (C) 2007 Google Incorporated
Pawan Kumarce25d142014-01-29 16:47:35 +05304 * Copyright (c) 2012-2014 The Linux Foundation. All rights reserved.
Daniel Walkerda6df072010-04-23 16:04:20 -07005 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#ifndef _MSM_MDP_H_
16#define _MSM_MDP_H_
17
18#include <linux/types.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070019#include <linux/fb.h>
Daniel Walkerda6df072010-04-23 16:04:20 -070020
21#define MSMFB_IOCTL_MAGIC 'm'
22#define MSMFB_GRP_DISP _IOW(MSMFB_IOCTL_MAGIC, 1, unsigned int)
23#define MSMFB_BLIT _IOW(MSMFB_IOCTL_MAGIC, 2, unsigned int)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070024#define MSMFB_SUSPEND_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 128, unsigned int)
25#define MSMFB_RESUME_SW_REFRESHER _IOW(MSMFB_IOCTL_MAGIC, 129, unsigned int)
26#define MSMFB_CURSOR _IOW(MSMFB_IOCTL_MAGIC, 130, struct fb_cursor)
27#define MSMFB_SET_LUT _IOW(MSMFB_IOCTL_MAGIC, 131, struct fb_cmap)
Carl Vanderlipba093a22011-11-22 13:59:59 -080028#define MSMFB_HISTOGRAM _IOWR(MSMFB_IOCTL_MAGIC, 132, struct mdp_histogram_data)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070029/* new ioctls's for set/get ccs matrix */
30#define MSMFB_GET_CCS_MATRIX _IOWR(MSMFB_IOCTL_MAGIC, 133, struct mdp_ccs)
31#define MSMFB_SET_CCS_MATRIX _IOW(MSMFB_IOCTL_MAGIC, 134, struct mdp_ccs)
32#define MSMFB_OVERLAY_SET _IOWR(MSMFB_IOCTL_MAGIC, 135, \
33 struct mdp_overlay)
34#define MSMFB_OVERLAY_UNSET _IOW(MSMFB_IOCTL_MAGIC, 136, unsigned int)
Kuogee Hsieh586fd162012-02-14 15:24:16 -080035
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070036#define MSMFB_OVERLAY_PLAY _IOW(MSMFB_IOCTL_MAGIC, 137, \
37 struct msmfb_overlay_data)
Kuogee Hsieh586fd162012-02-14 15:24:16 -080038#define MSMFB_OVERLAY_QUEUE MSMFB_OVERLAY_PLAY
39
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070040#define MSMFB_GET_PAGE_PROTECTION _IOR(MSMFB_IOCTL_MAGIC, 138, \
41 struct mdp_page_protection)
42#define MSMFB_SET_PAGE_PROTECTION _IOW(MSMFB_IOCTL_MAGIC, 139, \
43 struct mdp_page_protection)
44#define MSMFB_OVERLAY_GET _IOR(MSMFB_IOCTL_MAGIC, 140, \
45 struct mdp_overlay)
46#define MSMFB_OVERLAY_PLAY_ENABLE _IOW(MSMFB_IOCTL_MAGIC, 141, unsigned int)
47#define MSMFB_OVERLAY_BLT _IOWR(MSMFB_IOCTL_MAGIC, 142, \
48 struct msmfb_overlay_blt)
49#define MSMFB_OVERLAY_BLT_OFFSET _IOW(MSMFB_IOCTL_MAGIC, 143, unsigned int)
Carl Vanderlipba093a22011-11-22 13:59:59 -080050#define MSMFB_HISTOGRAM_START _IOR(MSMFB_IOCTL_MAGIC, 144, \
51 struct mdp_histogram_start_req)
52#define MSMFB_HISTOGRAM_STOP _IOR(MSMFB_IOCTL_MAGIC, 145, unsigned int)
Carl Vanderlip0d6ef4a2013-05-30 11:48:48 -070053#define MSMFB_NOTIFY_UPDATE _IOWR(MSMFB_IOCTL_MAGIC, 146, unsigned int)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070054
55#define MSMFB_OVERLAY_3D _IOWR(MSMFB_IOCTL_MAGIC, 147, \
56 struct msmfb_overlay_3d)
57
kuogee hsieh405dc302011-07-21 15:06:59 -070058#define MSMFB_MIXER_INFO _IOWR(MSMFB_IOCTL_MAGIC, 148, \
59 struct msmfb_mixer_info_req)
Nagamalleswararao Ganji0737d652011-10-14 02:02:33 -070060#define MSMFB_OVERLAY_PLAY_WAIT _IOWR(MSMFB_IOCTL_MAGIC, 149, \
61 struct msmfb_overlay_data)
Vinay Kalia27020d12011-10-14 17:50:29 -070062#define MSMFB_WRITEBACK_INIT _IO(MSMFB_IOCTL_MAGIC, 150)
Vinay Kaliae1ba2702011-12-21 16:24:52 -080063#define MSMFB_WRITEBACK_START _IO(MSMFB_IOCTL_MAGIC, 151)
64#define MSMFB_WRITEBACK_STOP _IO(MSMFB_IOCTL_MAGIC, 152)
Vinay Kalia27020d12011-10-14 17:50:29 -070065#define MSMFB_WRITEBACK_QUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 153, \
66 struct msmfb_data)
67#define MSMFB_WRITEBACK_DEQUEUE_BUFFER _IOW(MSMFB_IOCTL_MAGIC, 154, \
68 struct msmfb_data)
69#define MSMFB_WRITEBACK_TERMINATE _IO(MSMFB_IOCTL_MAGIC, 155)
Pravin Tamkhane02a40682011-11-29 14:17:01 -080070#define MSMFB_MDP_PP _IOWR(MSMFB_IOCTL_MAGIC, 156, struct msmfb_mdp_pp)
Padmanabhan Komanduruf3b0c232012-07-27 20:46:06 +053071#define MSMFB_OVERLAY_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 160, unsigned int)
72#define MSMFB_VSYNC_CTRL _IOW(MSMFB_IOCTL_MAGIC, 161, unsigned int)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053073#define MSMFB_BUFFER_SYNC _IOW(MSMFB_IOCTL_MAGIC, 162, struct mdp_buf_sync)
Kalyan Thota9284a272012-11-02 20:55:30 +053074#define MSMFB_OVERLAY_COMMIT _IO(MSMFB_IOCTL_MAGIC, 163)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053075#define MSMFB_DISPLAY_COMMIT _IOW(MSMFB_IOCTL_MAGIC, 164, \
Ken Zhang4e83b932012-12-02 21:15:47 -050076 struct mdp_display_commit)
Vishnuvardhan Prodduturifeb26292013-02-06 18:23:35 +053077#define MSMFB_METADATA_SET _IOW(MSMFB_IOCTL_MAGIC, 165, struct msmfb_metadata)
Ken Zhang420dd202013-01-08 14:28:20 -050078#define MSMFB_METADATA_GET _IOW(MSMFB_IOCTL_MAGIC, 166, struct msmfb_metadata)
Deva Ramasubramanian166b0982013-01-25 20:11:41 -080079#define MSMFB_WRITEBACK_SET_MIRRORING_HINT _IOW(MSMFB_IOCTL_MAGIC, 167, \
80 unsigned int)
Terence Hampson3e636aa2013-05-08 19:01:51 -040081#define MSMFB_ASYNC_BLIT _IOW(MSMFB_IOCTL_MAGIC, 168, unsigned int)
Adrian Salido-Moreno6b155092014-01-07 17:29:20 -080082#define MSMFB_OVERLAY_PREPARE _IOWR(MSMFB_IOCTL_MAGIC, 169, \
83 struct mdp_overlay_list)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070084#define FB_TYPE_3D_PANEL 0x10101010
85#define MDP_IMGTYPE2_START 0x10000
86#define MSMFB_DRIVER_VERSION 0xF9E8D701
Daniel Walkerda6df072010-04-23 16:04:20 -070087
88enum {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070089 NOTIFY_UPDATE_START,
90 NOTIFY_UPDATE_STOP,
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -070091 NOTIFY_UPDATE_POWER_OFF,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070092};
93
94enum {
Carl Vanderlip0d6ef4a2013-05-30 11:48:48 -070095 NOTIFY_TYPE_NO_UPDATE,
96 NOTIFY_TYPE_SUSPEND,
97 NOTIFY_TYPE_UPDATE,
98};
99
100enum {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700101 MDP_RGB_565, /* RGB 565 planer */
102 MDP_XRGB_8888, /* RGB 888 padded */
103 MDP_Y_CBCR_H2V2, /* Y and CbCr, pseudo planer w/ Cb is in MSB */
Padmanabhan Komandurud9f38b02012-02-02 18:57:03 +0530104 MDP_Y_CBCR_H2V2_ADRENO,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700105 MDP_ARGB_8888, /* ARGB 888 */
106 MDP_RGB_888, /* RGB 888 planer */
107 MDP_Y_CRCB_H2V2, /* Y and CrCb, pseudo planer w/ Cr is in MSB */
108 MDP_YCRYCB_H2V1, /* YCrYCb interleave */
Pawan Kumar42acdef2013-03-21 19:55:49 +0530109 MDP_CBYCRY_H2V1, /* CbYCrY interleave */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700110 MDP_Y_CRCB_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
111 MDP_Y_CBCR_H2V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700112 MDP_Y_CRCB_H1V2,
113 MDP_Y_CBCR_H1V2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700114 MDP_RGBA_8888, /* ARGB 888 */
115 MDP_BGRA_8888, /* ABGR 888 */
116 MDP_RGBX_8888, /* RGBX 888 */
117 MDP_Y_CRCB_H2V2_TILE, /* Y and CrCb, pseudo planer tile */
118 MDP_Y_CBCR_H2V2_TILE, /* Y and CbCr, pseudo planer tile */
119 MDP_Y_CR_CB_H2V2, /* Y, Cr and Cb, planar */
Pradeep Jilagam9b4a6be2011-10-03 17:19:20 +0530120 MDP_Y_CR_CB_GH2V2, /* Y, Cr and Cb, planar aligned to Android YV12 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700121 MDP_Y_CB_CR_H2V2, /* Y, Cb and Cr, planar */
122 MDP_Y_CRCB_H1V1, /* Y and CrCb, pseduo planer w/ Cr is in MSB */
123 MDP_Y_CBCR_H1V1, /* Y and CbCr, pseduo planer w/ Cb is in MSB */
Adrian Salido-Moreno2b410482011-08-15 10:40:40 -0700124 MDP_YCRCB_H1V1, /* YCrCb interleave */
125 MDP_YCBCR_H1V1, /* YCbCr interleave */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700126 MDP_BGR_565, /* BGR 565 planer */
Adrian Salido-Morenod559ef12012-07-12 20:16:14 -0700127 MDP_BGR_888, /* BGR 888 */
Adrian Salido-Moreno330c0bf2012-08-22 14:15:33 -0700128 MDP_Y_CBCR_H2V2_VENUS,
Pawan Kumar79854382013-02-14 15:27:12 +0530129 MDP_BGRX_8888, /* BGRX 8888 */
Shalabh Jainbea586a2013-08-23 12:30:48 -0700130 MDP_RGBA_8888_TILE, /* RGBA 8888 in tile format */
131 MDP_ARGB_8888_TILE, /* ARGB 8888 in tile format */
132 MDP_ABGR_8888_TILE, /* ABGR 8888 in tile format */
133 MDP_BGRA_8888_TILE, /* BGRA 8888 in tile format */
134 MDP_RGBX_8888_TILE, /* RGBX 8888 in tile format */
135 MDP_XRGB_8888_TILE, /* XRGB 8888 in tile format */
136 MDP_XBGR_8888_TILE, /* XBGR 8888 in tile format */
137 MDP_BGRX_8888_TILE, /* BGRX 8888 in tile format */
Ramkumar Radhakrishnan97180fa2013-08-06 20:50:52 -0700138 MDP_YCBYCR_H2V1, /* YCbYCr interleave */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700139 MDP_IMGTYPE_LIMIT,
kuogee hsieh1ce7e4c2012-01-13 14:05:54 -0800140 MDP_RGB_BORDERFILL, /* border fill pipe */
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700141 MDP_FB_FORMAT = MDP_IMGTYPE2_START, /* framebuffer format */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700142 MDP_IMGTYPE_LIMIT2 /* Non valid image type after this enum */
Daniel Walkerda6df072010-04-23 16:04:20 -0700143};
144
145enum {
146 PMEM_IMG,
147 FB_IMG,
148};
149
Liyuan Lid9736632011-11-11 13:47:59 -0800150enum {
151 HSIC_HUE = 0,
152 HSIC_SAT,
153 HSIC_INT,
154 HSIC_CON,
155 NUM_HSIC_PARAM,
156};
157
Adrian Salido-Moreno1857f062012-05-29 17:57:28 -0700158#define MDSS_MDP_ROT_ONLY 0x80
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700159#define MDSS_MDP_RIGHT_MIXER 0x100
Adrian Salido-Moreno6afd7802013-08-05 14:03:25 -0700160#define MDSS_MDP_DUAL_PIPE 0x200
Adrian Salido-Morenoe55fa122012-05-29 15:36:08 -0700161
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700162/* mdp_blit_req flag values */
163#define MDP_ROT_NOP 0
164#define MDP_FLIP_LR 0x1
165#define MDP_FLIP_UD 0x2
166#define MDP_ROT_90 0x4
167#define MDP_ROT_180 (MDP_FLIP_UD|MDP_FLIP_LR)
168#define MDP_ROT_270 (MDP_ROT_90|MDP_FLIP_UD|MDP_FLIP_LR)
169#define MDP_DITHER 0x8
170#define MDP_BLUR 0x10
171#define MDP_BLEND_FG_PREMULT 0x20000
Padmanabhan Komandurudd10bf12012-10-17 20:27:33 +0530172#define MDP_IS_FG 0x40000
Mayank Chopra1d91e092013-12-19 10:46:04 +0530173#define MDP_SOLID_FILL 0x00000020
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700174#define MDP_DEINTERLACE 0x80000000
175#define MDP_SHARPENING 0x40000000
176#define MDP_NO_DMA_BARRIER_START 0x20000000
177#define MDP_NO_DMA_BARRIER_END 0x10000000
178#define MDP_NO_BLIT 0x08000000
179#define MDP_BLIT_WITH_DMA_BARRIERS 0x000
180#define MDP_BLIT_WITH_NO_DMA_BARRIERS \
181 (MDP_NO_DMA_BARRIER_START | MDP_NO_DMA_BARRIER_END)
182#define MDP_BLIT_SRC_GEM 0x04000000
183#define MDP_BLIT_DST_GEM 0x02000000
184#define MDP_BLIT_NON_CACHED 0x01000000
185#define MDP_OV_PIPE_SHARE 0x00800000
186#define MDP_DEINTERLACE_ODD 0x00400000
187#define MDP_OV_PLAY_NOWAIT 0x00200000
188#define MDP_SOURCE_ROTATED_90 0x00100000
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700189#define MDP_OVERLAY_PP_CFG_EN 0x00080000
Ajay Singh Parmar4c7ccb32012-02-21 12:56:04 +0530190#define MDP_BACKEND_COMPOSITION 0x00040000
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800191#define MDP_BORDERFILL_SUPPORTED 0x00010000
192#define MDP_SECURE_OVERLAY_SESSION 0x00008000
Arun Kumar K.R9ce1fd62013-09-24 11:35:08 -0700193#define MDP_SECURE_DISPLAY_OVERLAY_SESSION 0x00002000
Adrian Salido-Moreno9a8485c2013-02-06 14:08:28 -0800194#define MDP_OV_PIPE_FORCE_DMA 0x00004000
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800195#define MDP_MEMORY_ID_TYPE_FB 0x00001000
Sree Sesha Aravind Vadrevu35143132013-03-12 02:32:06 -0700196#define MDP_BWC_EN 0x00000400
Sree Sesha Aravind Vadrevu05d4d222013-04-01 14:31:28 -0700197#define MDP_DECIMATION_EN 0x00000800
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700198#define MDP_TRANSP_NOP 0xffffffff
199#define MDP_ALPHA_NOP 0xff
200
201#define MDP_FB_PAGE_PROTECTION_NONCACHED (0)
202#define MDP_FB_PAGE_PROTECTION_WRITECOMBINE (1)
203#define MDP_FB_PAGE_PROTECTION_WRITETHROUGHCACHE (2)
204#define MDP_FB_PAGE_PROTECTION_WRITEBACKCACHE (3)
205#define MDP_FB_PAGE_PROTECTION_WRITEBACKWACACHE (4)
206/* Sentinel: Don't use! */
207#define MDP_FB_PAGE_PROTECTION_INVALID (5)
208/* Count of the number of MDP_FB_PAGE_PROTECTION_... values. */
209#define MDP_NUM_FB_PAGE_PROTECTION_VALUES (5)
Daniel Walkerda6df072010-04-23 16:04:20 -0700210
211struct mdp_rect {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700212 uint32_t x;
213 uint32_t y;
214 uint32_t w;
215 uint32_t h;
Daniel Walkerda6df072010-04-23 16:04:20 -0700216};
217
218struct mdp_img {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700219 uint32_t width;
220 uint32_t height;
221 uint32_t format;
222 uint32_t offset;
Daniel Walkerda6df072010-04-23 16:04:20 -0700223 int memory_id; /* the file descriptor */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700224 uint32_t priv;
Daniel Walkerda6df072010-04-23 16:04:20 -0700225};
226
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700227/*
228 * {3x3} + {3} ccs matrix
229 */
230
231#define MDP_CCS_RGB2YUV 0
232#define MDP_CCS_YUV2RGB 1
233
234#define MDP_CCS_SIZE 9
235#define MDP_BV_SIZE 3
236
237struct mdp_ccs {
238 int direction; /* MDP_CCS_RGB2YUV or YUV2RGB */
239 uint16_t ccs[MDP_CCS_SIZE]; /* 3x3 color coefficients */
240 uint16_t bv[MDP_BV_SIZE]; /* 1x3 bias vector */
241};
242
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800243struct mdp_csc {
244 int id;
245 uint32_t csc_mv[9];
246 uint32_t csc_pre_bv[3];
247 uint32_t csc_post_bv[3];
248 uint32_t csc_pre_lv[6];
249 uint32_t csc_post_lv[6];
250};
251
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700252/* The version of the mdp_blit_req structure so that
253 * user applications can selectively decide which functionality
254 * to include
255 */
256
257#define MDP_BLIT_REQ_VERSION 2
258
Shivaraj Shetty1bbb3832013-10-22 18:43:17 +0530259struct color {
260 uint32_t r;
261 uint32_t g;
262 uint32_t b;
263 uint32_t alpha;
264};
265
Daniel Walkerda6df072010-04-23 16:04:20 -0700266struct mdp_blit_req {
267 struct mdp_img src;
268 struct mdp_img dst;
269 struct mdp_rect src_rect;
270 struct mdp_rect dst_rect;
Shivaraj Shetty1bbb3832013-10-22 18:43:17 +0530271 struct color const_color;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700272 uint32_t alpha;
273 uint32_t transp_mask;
274 uint32_t flags;
275 int sharpening_strength; /* -127 <--> 127, default 64 */
Daniel Walkerda6df072010-04-23 16:04:20 -0700276};
277
278struct mdp_blit_req_list {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700279 uint32_t count;
Daniel Walkerda6df072010-04-23 16:04:20 -0700280 struct mdp_blit_req req[];
281};
282
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700283#define MSMFB_DATA_VERSION 2
284
285struct msmfb_data {
286 uint32_t offset;
287 int memory_id;
288 int id;
289 uint32_t flags;
290 uint32_t priv;
Vinay Kaliae1ba2702011-12-21 16:24:52 -0800291 uint32_t iova;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700292};
293
294#define MSMFB_NEW_REQUEST -1
295
296struct msmfb_overlay_data {
297 uint32_t id;
298 struct msmfb_data data;
299 uint32_t version_key;
300 struct msmfb_data plane1_data;
301 struct msmfb_data plane2_data;
Adrian Salido-Moreno1857f062012-05-29 17:57:28 -0700302 struct msmfb_data dst_data;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700303};
304
305struct msmfb_img {
306 uint32_t width;
307 uint32_t height;
308 uint32_t format;
309};
310
Vinay Kalia27020d12011-10-14 17:50:29 -0700311#define MSMFB_WRITEBACK_DEQUEUE_BLOCKING 0x1
312struct msmfb_writeback_data {
313 struct msmfb_data buf_info;
314 struct msmfb_img img;
315};
316
Ken Zhang77ce0192012-08-10 11:27:19 -0400317#define MDP_PP_OPS_ENABLE 0x1
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700318#define MDP_PP_OPS_READ 0x2
319#define MDP_PP_OPS_WRITE 0x4
Ken Zhang77ce0192012-08-10 11:27:19 -0400320#define MDP_PP_OPS_DISABLE 0x8
Ken Zhang824758e2012-08-15 11:02:21 -0400321#define MDP_PP_IGC_FLAG_ROM0 0x10
322#define MDP_PP_IGC_FLAG_ROM1 0x20
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700323
Benet Clark477baa02013-10-04 17:21:45 -0700324#define MDP_PP_PA_HUE_ENABLE 0x10
325#define MDP_PP_PA_SAT_ENABLE 0x20
326#define MDP_PP_PA_VAL_ENABLE 0x40
327#define MDP_PP_PA_CONT_ENABLE 0x80
328#define MDP_PP_PA_SIX_ZONE_ENABLE 0x100
329#define MDP_PP_PA_SKIN_ENABLE 0x200
330#define MDP_PP_PA_SKY_ENABLE 0x400
331#define MDP_PP_PA_FOL_ENABLE 0x800
332#define MDP_PP_PA_HUE_MASK 0x1000
333#define MDP_PP_PA_SAT_MASK 0x2000
334#define MDP_PP_PA_VAL_MASK 0x4000
335#define MDP_PP_PA_CONT_MASK 0x8000
336#define MDP_PP_PA_SIX_ZONE_HUE_MASK 0x10000
337#define MDP_PP_PA_SIX_ZONE_SAT_MASK 0x20000
338#define MDP_PP_PA_SIX_ZONE_VAL_MASK 0x40000
339#define MDP_PP_PA_MEM_COL_SKIN_MASK 0x80000
340#define MDP_PP_PA_MEM_COL_SKY_MASK 0x100000
341#define MDP_PP_PA_MEM_COL_FOL_MASK 0x200000
342#define MDP_PP_PA_MEM_PROTECT_EN 0x400000
343#define MDP_PP_PA_SAT_ZERO_EXP_EN 0x800000
344
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700345#define MDSS_PP_DSPP_CFG 0x000
346#define MDSS_PP_SSPP_CFG 0x100
347#define MDSS_PP_LM_CFG 0x200
348#define MDSS_PP_WB_CFG 0x300
Ping Li8231ae42013-01-09 20:39:25 -0500349
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700350#define MDSS_PP_ARG_MASK 0x3C00
351#define MDSS_PP_ARG_NUM 4
Carl Vanderlip793aa582013-03-18 10:18:47 -0700352#define MDSS_PP_ARG_SHIFT 10
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700353#define MDSS_PP_LOCATION_MASK 0x0300
354#define MDSS_PP_LOGICAL_MASK 0x00FF
Ping Li8231ae42013-01-09 20:39:25 -0500355
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700356#define MDSS_PP_ADD_ARG(var, arg) ((var) | (0x1 << (MDSS_PP_ARG_SHIFT + (arg))))
357#define PP_ARG(x, var) ((var) & (0x1 << (MDSS_PP_ARG_SHIFT + (x))))
Ping Li8231ae42013-01-09 20:39:25 -0500358#define PP_LOCAT(var) ((var) & MDSS_PP_LOCATION_MASK)
359#define PP_BLOCK(var) ((var) & MDSS_PP_LOGICAL_MASK)
360
361
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700362struct mdp_qseed_cfg {
363 uint32_t table_num;
364 uint32_t ops;
365 uint32_t len;
366 uint32_t *data;
367};
368
Ping Li87cca832013-01-30 18:27:52 -0500369struct mdp_sharp_cfg {
370 uint32_t flags;
371 uint32_t strength;
372 uint32_t edge_thr;
373 uint32_t smooth_thr;
374 uint32_t noise_thr;
375};
376
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700377struct mdp_qseed_cfg_data {
378 uint32_t block;
379 struct mdp_qseed_cfg qseed_data;
380};
381
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800382#define MDP_OVERLAY_PP_CSC_CFG 0x1
383#define MDP_OVERLAY_PP_QSEED_CFG 0x2
384#define MDP_OVERLAY_PP_PA_CFG 0x4
385#define MDP_OVERLAY_PP_IGC_CFG 0x8
Ping Li87cca832013-01-30 18:27:52 -0500386#define MDP_OVERLAY_PP_SHARP_CFG 0x10
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700387#define MDP_OVERLAY_PP_HIST_CFG 0x20
Carl Vanderlip57027132013-03-18 13:53:16 -0700388#define MDP_OVERLAY_PP_HIST_LUT_CFG 0x40
Benet Clark477baa02013-10-04 17:21:45 -0700389#define MDP_OVERLAY_PP_PA_V2_CFG 0x80
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700390
391#define MDP_CSC_FLAG_ENABLE 0x1
392#define MDP_CSC_FLAG_YUV_IN 0x2
393#define MDP_CSC_FLAG_YUV_OUT 0x4
394
395struct mdp_csc_cfg {
396 /* flags for enable CSC, toggling RGB,YUV input/output */
397 uint32_t flags;
398 uint32_t csc_mv[9];
399 uint32_t csc_pre_bv[3];
400 uint32_t csc_post_bv[3];
401 uint32_t csc_pre_lv[6];
402 uint32_t csc_post_lv[6];
403};
404
405struct mdp_csc_cfg_data {
406 uint32_t block;
407 struct mdp_csc_cfg csc_data;
408};
409
Ping Li58229242012-11-30 14:05:43 -0500410struct mdp_pa_cfg {
411 uint32_t flags;
412 uint32_t hue_adj;
413 uint32_t sat_adj;
414 uint32_t val_adj;
415 uint32_t cont_adj;
416};
417
Benet Clark477baa02013-10-04 17:21:45 -0700418struct mdp_pa_mem_col_cfg {
419 uint32_t color_adjust_p0;
420 uint32_t color_adjust_p1;
421 uint32_t hue_region;
422 uint32_t sat_region;
423 uint32_t val_region;
424};
425
Benet Clark93577da2013-11-19 17:17:01 -0800426#define MDP_SIX_ZONE_LUT_SIZE 384
Carl Vanderlip4ac3a132013-11-19 16:52:52 -0800427
Benet Clark477baa02013-10-04 17:21:45 -0700428struct mdp_pa_v2_data {
429 /* Mask bits for PA features */
430 uint32_t flags;
431 uint32_t global_hue_adj;
432 uint32_t global_sat_adj;
433 uint32_t global_val_adj;
434 uint32_t global_cont_adj;
435 struct mdp_pa_mem_col_cfg skin_cfg;
436 struct mdp_pa_mem_col_cfg sky_cfg;
437 struct mdp_pa_mem_col_cfg fol_cfg;
Benet Clark66955112013-12-04 12:52:22 -0800438 uint32_t six_zone_len;
439 uint32_t six_zone_thresh;
440 uint32_t *six_zone_curve_p0;
441 uint32_t *six_zone_curve_p1;
Benet Clark477baa02013-10-04 17:21:45 -0700442};
443
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800444struct mdp_igc_lut_data {
445 uint32_t block;
446 uint32_t len, ops;
447 uint32_t *c0_c1_data;
448 uint32_t *c2_data;
449};
450
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700451struct mdp_histogram_cfg {
452 uint32_t ops;
453 uint32_t block;
454 uint8_t frame_cnt;
455 uint8_t bit_mask;
456 uint16_t num_bins;
457};
458
Carl Vanderlip57027132013-03-18 13:53:16 -0700459struct mdp_hist_lut_data {
460 uint32_t block;
461 uint32_t ops;
462 uint32_t len;
463 uint32_t *data;
464};
465
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700466struct mdp_overlay_pp_params {
467 uint32_t config_ops;
468 struct mdp_csc_cfg csc_cfg;
469 struct mdp_qseed_cfg qseed_cfg[2];
Ping Li58229242012-11-30 14:05:43 -0500470 struct mdp_pa_cfg pa_cfg;
Benet Clark477baa02013-10-04 17:21:45 -0700471 struct mdp_pa_v2_data pa_v2_cfg;
Carl Vanderlip94d9b782013-01-16 12:13:52 -0800472 struct mdp_igc_lut_data igc_cfg;
Ping Li87cca832013-01-30 18:27:52 -0500473 struct mdp_sharp_cfg sharp_cfg;
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700474 struct mdp_histogram_cfg hist_cfg;
Carl Vanderlip57027132013-03-18 13:53:16 -0700475 struct mdp_hist_lut_data hist_lut_cfg;
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700476};
477
Mayank Chopra29c4ee52013-07-24 12:31:01 +0530478/**
479 * enum mdss_mdp_blend_op - Different blend operations set by userspace
480 *
481 * @BLEND_OP_NOT_DEFINED: No blend operation defined for the layer.
482 * @BLEND_OP_OPAQUE: Apply a constant blend operation. The layer
483 * would appear opaque in case fg plane alpha is
484 * 0xff.
485 * @BLEND_OP_PREMULTIPLIED: Apply source over blend rule. Layer already has
486 * alpha pre-multiplication done. If fg plane alpha
487 * is less than 0xff, apply modulation as well. This
488 * operation is intended on layers having alpha
489 * channel.
490 * @BLEND_OP_COVERAGE: Apply source over blend rule. Layer is not alpha
491 * pre-multiplied. Apply pre-multiplication. If fg
492 * plane alpha is less than 0xff, apply modulation as
493 * well.
494 * @BLEND_OP_MAX: Used to track maximum blend operation possible by
495 * mdp.
496 */
497enum mdss_mdp_blend_op {
498 BLEND_OP_NOT_DEFINED = 0,
499 BLEND_OP_OPAQUE,
500 BLEND_OP_PREMULTIPLIED,
501 BLEND_OP_COVERAGE,
502 BLEND_OP_MAX,
503};
504
Sree Sesha Aravind Vadrevu494961d2013-10-03 12:51:03 -0700505#define MAX_PLANES 4
506struct mdp_scale_data {
507 uint8_t enable_pxl_ext;
508
509 int init_phase_x[MAX_PLANES];
510 int phase_step_x[MAX_PLANES];
511 int init_phase_y[MAX_PLANES];
512 int phase_step_y[MAX_PLANES];
513
514 int num_ext_pxls_left[MAX_PLANES];
515 int num_ext_pxls_right[MAX_PLANES];
516 int num_ext_pxls_top[MAX_PLANES];
517 int num_ext_pxls_btm[MAX_PLANES];
518
519 int left_ftch[MAX_PLANES];
520 int left_rpt[MAX_PLANES];
521 int right_ftch[MAX_PLANES];
522 int right_rpt[MAX_PLANES];
523
524 int top_rpt[MAX_PLANES];
525 int btm_rpt[MAX_PLANES];
526 int top_ftch[MAX_PLANES];
527 int btm_ftch[MAX_PLANES];
528
529 uint32_t roi_w[MAX_PLANES];
530};
531
Adrian Salido-Morenof8da3922013-07-03 15:19:25 -0700532/**
533 * struct mdp_overlay - overlay surface structure
534 * @src: Source image information (width, height, format).
535 * @src_rect: Source crop rectangle, portion of image that will be fetched.
536 * This should always be within boundaries of source image.
537 * @dst_rect: Destination rectangle, the position and size of image on screen.
538 * This should always be within panel boundaries.
539 * @z_order: Blending stage to occupy in display, if multiple layers are
540 * present, highest z_order usually means the top most visible
541 * layer. The range acceptable is from 0-3 to support blending
542 * up to 4 layers.
543 * @is_fg: This flag is used to disable blending of any layers with z_order
544 * less than this overlay. It means that any layers with z_order
545 * less than this layer will not be blended and will be replaced
546 * by the background border color.
547 * @alpha: Used to set plane opacity. The range can be from 0-255, where
548 * 0 means completely transparent and 255 means fully opaque.
549 * @transp_mask: Color used as color key for transparency. Any pixel in fetched
550 * image matching this color will be transparent when blending.
551 * The color should be in same format as the source image format.
552 * @flags: This is used to customize operation of overlay. See MDP flags
553 * for more information.
554 * @user_data: DEPRECATED* Used to store user application specific information.
Adrian Salido-Morenoe21074d2013-07-03 15:41:33 -0700555 * @bg_color: Solid color used to fill the overlay surface when no source
556 * buffer is provided.
Adrian Salido-Morenof8da3922013-07-03 15:19:25 -0700557 * @horz_deci: Horizontal decimation value, this indicates the amount of pixels
558 * dropped for each pixel that is fetched from a line. The value
559 * given should be power of two of decimation amount.
560 * 0: no decimation
561 * 1: decimate by 2 (drop 1 pixel for each pixel fetched)
562 * 2: decimate by 4 (drop 3 pixels for each pixel fetched)
563 * 3: decimate by 8 (drop 7 pixels for each pixel fetched)
564 * 4: decimate by 16 (drop 15 pixels for each pixel fetched)
565 * @vert_deci: Vertical decimation value, this indicates the amount of lines
566 * dropped for each line that is fetched from overlay. The value
567 * given should be power of two of decimation amount.
568 * 0: no decimation
569 * 1: decimation by 2 (drop 1 line for each line fetched)
570 * 2: decimation by 4 (drop 3 lines for each line fetched)
571 * 3: decimation by 8 (drop 7 lines for each line fetched)
572 * 4: decimation by 16 (drop 15 lines for each line fetched)
573 * @overlay_pp_cfg: Overlay post processing configuration, for more information
574 * see struct mdp_overlay_pp_params.
575 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700576struct mdp_overlay {
577 struct msmfb_img src;
578 struct mdp_rect src_rect;
579 struct mdp_rect dst_rect;
580 uint32_t z_order; /* stage number */
581 uint32_t is_fg; /* control alpha & transp */
582 uint32_t alpha;
Mayank Chopra29c4ee52013-07-24 12:31:01 +0530583 uint32_t blend_op;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700584 uint32_t transp_mask;
585 uint32_t flags;
586 uint32_t id;
Adrian Salido-Morenoe21074d2013-07-03 15:41:33 -0700587 uint32_t user_data[6];
588 uint32_t bg_color;
Sree Sesha Aravind Vadrevu05d4d222013-04-01 14:31:28 -0700589 uint8_t horz_deci;
590 uint8_t vert_deci;
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700591 struct mdp_overlay_pp_params overlay_pp_cfg;
Sree Sesha Aravind Vadrevu494961d2013-10-03 12:51:03 -0700592 struct mdp_scale_data scale;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700593};
594
595struct msmfb_overlay_3d {
596 uint32_t is_3d;
597 uint32_t width;
598 uint32_t height;
599};
600
601
602struct msmfb_overlay_blt {
603 uint32_t enable;
604 uint32_t offset;
605 uint32_t width;
606 uint32_t height;
607 uint32_t bpp;
608};
609
610struct mdp_histogram {
611 uint32_t frame_cnt;
612 uint32_t bin_cnt;
613 uint32_t *r;
614 uint32_t *g;
615 uint32_t *b;
616};
617
Mayank Chopra0a8c4762013-07-12 18:19:36 +0530618#define MISR_CRC_BATCH_SIZE 32
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700619enum {
Mayank Chopra0a8c4762013-07-12 18:19:36 +0530620 DISPLAY_MISR_EDP = 0,
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700621 DISPLAY_MISR_DSI0,
622 DISPLAY_MISR_DSI1,
623 DISPLAY_MISR_HDMI,
624 DISPLAY_MISR_LCDC,
Mayank Chopra0a8c4762013-07-12 18:19:36 +0530625 DISPLAY_MISR_MDP,
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700626 DISPLAY_MISR_ATV,
627 DISPLAY_MISR_DSI_CMD,
628 DISPLAY_MISR_MAX
629};
630
631enum {
Mayank Chopra0a8c4762013-07-12 18:19:36 +0530632 MISR_OP_NONE = 0,
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700633 MISR_OP_SFM,
634 MISR_OP_MFM,
635 MISR_OP_BM,
636 MISR_OP_MAX
637};
638
639struct mdp_misr {
640 uint32_t block_id;
641 uint32_t frame_count;
642 uint32_t crc_op_mode;
Mayank Chopra0a8c4762013-07-12 18:19:36 +0530643 uint32_t crc_value[MISR_CRC_BATCH_SIZE];
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700644};
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800645
646/*
647
Ken Zhang6a431632012-08-08 16:46:22 -0400648 mdp_block_type defines the identifiers for pipes in MDP 4.3 and up
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800649
650 MDP_BLOCK_RESERVED is provided for backward compatibility and is
651 deprecated. It corresponds to DMA_P. So MDP_BLOCK_DMA_P should be used
652 instead.
653
Ken Zhang6a431632012-08-08 16:46:22 -0400654 MDP_LOGICAL_BLOCK_DISP_0 identifies the display pipe which fb0 uses,
655 same for others.
656
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800657*/
658
659enum {
660 MDP_BLOCK_RESERVED = 0,
661 MDP_BLOCK_OVERLAY_0,
662 MDP_BLOCK_OVERLAY_1,
663 MDP_BLOCK_VG_1,
664 MDP_BLOCK_VG_2,
665 MDP_BLOCK_RGB_1,
666 MDP_BLOCK_RGB_2,
667 MDP_BLOCK_DMA_P,
668 MDP_BLOCK_DMA_S,
669 MDP_BLOCK_DMA_E,
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700670 MDP_BLOCK_OVERLAY_2,
Carl Vanderlipbf16fdf62013-03-11 13:45:45 -0700671 MDP_LOGICAL_BLOCK_DISP_0 = 0x10,
Ken Zhang6a431632012-08-08 16:46:22 -0400672 MDP_LOGICAL_BLOCK_DISP_1,
673 MDP_LOGICAL_BLOCK_DISP_2,
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800674 MDP_BLOCK_MAX,
675};
676
Carl Vanderlipba093a22011-11-22 13:59:59 -0800677/*
678 * mdp_histogram_start_req is used to provide the parameters for
679 * histogram start request
680 */
681
682struct mdp_histogram_start_req {
683 uint32_t block;
684 uint8_t frame_cnt;
685 uint8_t bit_mask;
Carl Vanderlip16316322012-10-08 16:47:34 -0700686 uint16_t num_bins;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800687};
688
689/*
690 * mdp_histogram_data is used to return the histogram data, once
691 * the histogram is done/stopped/cance
692 */
693
694struct mdp_histogram_data {
695 uint32_t block;
Ken Zhang0f523bd2012-08-23 11:14:03 -0400696 uint32_t bin_cnt;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800697 uint32_t *c0;
698 uint32_t *c1;
699 uint32_t *c2;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800700 uint32_t *extra_info;
Carl Vanderlipba093a22011-11-22 13:59:59 -0800701};
702
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800703struct mdp_pcc_coeff {
704 uint32_t c, r, g, b, rr, gg, bb, rg, gb, rb, rgb_0, rgb_1;
705};
706
707struct mdp_pcc_cfg_data {
708 uint32_t block;
709 uint32_t ops;
710 struct mdp_pcc_coeff r, g, b;
711};
712
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400713#define MDP_GAMUT_TABLE_NUM 8
714
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800715enum {
716 mdp_lut_igc,
717 mdp_lut_pgc,
718 mdp_lut_hist,
719 mdp_lut_max,
720};
721
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800722struct mdp_ar_gc_lut_data {
723 uint32_t x_start;
724 uint32_t slope;
725 uint32_t offset;
726};
727
728struct mdp_pgc_lut_data {
729 uint32_t block;
730 uint32_t flags;
731 uint8_t num_r_stages;
732 uint8_t num_g_stages;
733 uint8_t num_b_stages;
734 struct mdp_ar_gc_lut_data *r_data;
735 struct mdp_ar_gc_lut_data *g_data;
736 struct mdp_ar_gc_lut_data *b_data;
737};
738
739
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800740struct mdp_lut_cfg_data {
741 uint32_t lut_type;
742 union {
743 struct mdp_igc_lut_data igc_lut_data;
744 struct mdp_pgc_lut_data pgc_lut_data;
745 struct mdp_hist_lut_data hist_lut_data;
746 } data;
747};
748
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700749struct mdp_bl_scale_data {
750 uint32_t min_lvl;
751 uint32_t scale;
752};
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700753
Ken Zhang77ce0192012-08-10 11:27:19 -0400754struct mdp_pa_cfg_data {
755 uint32_t block;
Ping Li58229242012-11-30 14:05:43 -0500756 struct mdp_pa_cfg pa_data;
Ken Zhang77ce0192012-08-10 11:27:19 -0400757};
758
Benet Clark477baa02013-10-04 17:21:45 -0700759struct mdp_pa_v2_cfg_data {
760 uint32_t block;
761 struct mdp_pa_v2_data pa_v2_data;
762};
763
Ken Zhang7fb85772012-08-18 14:51:33 -0400764struct mdp_dither_cfg_data {
765 uint32_t block;
766 uint32_t flags;
767 uint32_t g_y_depth;
768 uint32_t r_cr_depth;
769 uint32_t b_cb_depth;
770};
771
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400772struct mdp_gamut_cfg_data {
773 uint32_t block;
774 uint32_t flags;
775 uint32_t gamut_first;
776 uint32_t tbl_size[MDP_GAMUT_TABLE_NUM];
777 uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM];
778 uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM];
779 uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM];
780};
781
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700782struct mdp_calib_config_data {
783 uint32_t ops;
784 uint32_t addr;
785 uint32_t data;
786};
787
Arpita Banerjee676eea22013-06-04 19:43:24 -0700788struct mdp_calib_config_buffer {
789 uint32_t ops;
790 uint32_t size;
791 uint32_t *buffer;
792};
793
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -0700794struct mdp_calib_dcm_state {
795 uint32_t ops;
796 uint32_t dcm_state;
797};
798
799enum {
800 DCM_UNINIT,
801 DCM_UNBLANK,
802 DCM_ENTER,
803 DCM_EXIT,
804 DCM_BLANK,
Dhaval Patel39090532013-12-04 12:11:32 -0800805 DTM_ENTER,
806 DTM_EXIT,
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -0700807};
808
Carl Vanderlip45e042b2013-12-11 13:27:00 -0800809#define MDSS_PP_SPLIT_LEFT_ONLY 0x10000000
810#define MDSS_PP_SPLIT_RIGHT_ONLY 0x20000000
811#define MDSS_PP_SPLIT_MASK 0x30000000
812
Carl Vanderlipe5592b62013-05-16 21:00:03 -0700813#define MDSS_MAX_BL_BRIGHTNESS 255
Benet Clarkc5982d52013-11-08 16:05:58 -0800814#define AD_BL_LIN_LEN 256
Carl Vanderlipe5592b62013-05-16 21:00:03 -0700815
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700816#define MDSS_AD_MODE_AUTO_BL 0x0
817#define MDSS_AD_MODE_AUTO_STR 0x1
818#define MDSS_AD_MODE_TARG_STR 0x3
819#define MDSS_AD_MODE_MAN_STR 0x7
Carl Vanderlip819c5092013-05-19 12:08:33 -0700820#define MDSS_AD_MODE_CALIB 0xF
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700821
822#define MDP_PP_AD_INIT 0x10
823#define MDP_PP_AD_CFG 0x20
824
825struct mdss_ad_init {
826 uint32_t asym_lut[33];
827 uint32_t color_corr_lut[33];
828 uint8_t i_control[2];
829 uint16_t black_lvl;
830 uint16_t white_lvl;
831 uint8_t var;
832 uint8_t limit_ampl;
833 uint8_t i_dither;
834 uint8_t slope_max;
835 uint8_t slope_min;
836 uint8_t dither_ctl;
837 uint8_t format;
838 uint8_t auto_size;
839 uint16_t frame_w;
840 uint16_t frame_h;
841 uint8_t logo_v;
842 uint8_t logo_h;
Carl Vanderlipe5592b62013-05-16 21:00:03 -0700843 uint32_t bl_lin_len;
844 uint32_t *bl_lin;
845 uint32_t *bl_lin_inv;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700846};
847
Carl Vanderlip5e81ced2013-05-23 20:02:14 -0700848#define MDSS_AD_BL_CTRL_MODE_EN 1
849#define MDSS_AD_BL_CTRL_MODE_DIS 0
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700850struct mdss_ad_cfg {
851 uint32_t mode;
852 uint32_t al_calib_lut[33];
853 uint16_t backlight_min;
854 uint16_t backlight_max;
855 uint16_t backlight_scale;
856 uint16_t amb_light_min;
857 uint16_t filter[2];
858 uint16_t calib[4];
859 uint8_t strength_limit;
860 uint8_t t_filter_recursion;
Carl Vanderlip956360e2013-04-04 20:57:17 -0700861 uint16_t stab_itr;
Carl Vanderlip5e81ced2013-05-23 20:02:14 -0700862 uint32_t bl_ctrl_mode;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700863};
864
865/* ops uses standard MDP_PP_* flags */
866struct mdss_ad_init_cfg {
867 uint32_t ops;
868 union {
869 struct mdss_ad_init init;
870 struct mdss_ad_cfg cfg;
871 } params;
872};
873
874/* mode uses MDSS_AD_MODE_* flags */
875struct mdss_ad_input {
876 uint32_t mode;
877 union {
878 uint32_t amb_light;
879 uint32_t strength;
Carl Vanderlip819c5092013-05-19 12:08:33 -0700880 uint32_t calib_bl;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700881 } in;
Carl Vanderlip16e79532013-04-02 11:12:16 -0700882 uint32_t output;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700883};
884
Carl Vanderlipa088b7c2013-05-17 13:52:53 -0700885#define MDSS_CALIB_MODE_BL 0x1
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700886struct mdss_calib_cfg {
887 uint32_t ops;
888 uint32_t calib_mask;
889};
890
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800891enum {
892 mdp_op_pcc_cfg,
893 mdp_op_csc_cfg,
894 mdp_op_lut_cfg,
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700895 mdp_op_qseed_cfg,
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700896 mdp_bl_scale_cfg,
Ken Zhang77ce0192012-08-10 11:27:19 -0400897 mdp_op_pa_cfg,
Benet Clark477baa02013-10-04 17:21:45 -0700898 mdp_op_pa_v2_cfg,
Ken Zhang7fb85772012-08-18 14:51:33 -0400899 mdp_op_dither_cfg,
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400900 mdp_op_gamut_cfg,
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700901 mdp_op_calib_cfg,
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700902 mdp_op_ad_cfg,
903 mdp_op_ad_input,
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700904 mdp_op_calib_mode,
Arpita Banerjee676eea22013-06-04 19:43:24 -0700905 mdp_op_calib_buffer,
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -0700906 mdp_op_calib_dcm_state,
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800907 mdp_op_max,
908};
909
Pawan Kumar9807ea12013-02-14 18:12:02 +0530910enum {
911 WB_FORMAT_NV12,
912 WB_FORMAT_RGB_565,
913 WB_FORMAT_RGB_888,
914 WB_FORMAT_xRGB_8888,
915 WB_FORMAT_ARGB_8888,
Pawan Kumaree811932013-07-09 15:45:01 +0530916 WB_FORMAT_BGRA_8888,
917 WB_FORMAT_BGRX_8888,
Pawan Kumar9807ea12013-02-14 18:12:02 +0530918 WB_FORMAT_ARGB_8888_INPUT_ALPHA /* Need to support */
919};
920
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800921struct msmfb_mdp_pp {
922 uint32_t op;
923 union {
924 struct mdp_pcc_cfg_data pcc_cfg_data;
925 struct mdp_csc_cfg_data csc_cfg_data;
926 struct mdp_lut_cfg_data lut_cfg_data;
Pravin Tamkhane67726da2012-04-13 11:59:11 -0700927 struct mdp_qseed_cfg_data qseed_cfg_data;
Carl Vanderlipf0fd8e72012-05-03 15:08:20 -0700928 struct mdp_bl_scale_data bl_scale_data;
Ken Zhang77ce0192012-08-10 11:27:19 -0400929 struct mdp_pa_cfg_data pa_cfg_data;
Benet Clark477baa02013-10-04 17:21:45 -0700930 struct mdp_pa_v2_cfg_data pa_v2_cfg_data;
Ken Zhang7fb85772012-08-18 14:51:33 -0400931 struct mdp_dither_cfg_data dither_cfg_data;
Ken Zhangbf5fb4c2012-08-19 14:41:01 -0400932 struct mdp_gamut_cfg_data gamut_cfg_data;
Carl Vanderlipe8ed5ec2012-09-28 16:04:10 -0700933 struct mdp_calib_config_data calib_cfg;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700934 struct mdss_ad_init_cfg ad_init_cfg;
Carl Vanderlip95a07e12013-05-17 13:51:38 -0700935 struct mdss_calib_cfg mdss_calib_cfg;
Carl Vanderlip8b493b02013-03-22 13:40:02 -0700936 struct mdss_ad_input ad_input;
Arpita Banerjee676eea22013-06-04 19:43:24 -0700937 struct mdp_calib_config_buffer calib_buffer;
Arpita Banerjeea8b7fbf2013-06-11 19:24:20 -0700938 struct mdp_calib_dcm_state calib_dcm;
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800939 } data;
940};
941
Manoj Raoa8e39d92013-02-16 08:47:21 -0800942#define FB_METADATA_VIDEO_INFO_CODE_SUPPORT 1
Ken Zhang5cf85c02012-08-23 19:32:52 -0700943enum {
944 metadata_op_none,
945 metadata_op_base_blend,
Ken Zhang420dd202013-01-08 14:28:20 -0500946 metadata_op_frame_rate,
Manoj Raoa8e39d92013-02-16 08:47:21 -0800947 metadata_op_vic,
Pawan Kumar9807ea12013-02-14 18:12:02 +0530948 metadata_op_wb_format,
Tatenda Chipeperekwa5dc8c482013-10-25 17:44:37 -0700949 metadata_op_wb_secure,
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800950 metadata_op_get_caps,
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700951 metadata_op_crc,
Ken Zhang5cf85c02012-08-23 19:32:52 -0700952 metadata_op_max
953};
Pravin Tamkhane02a40682011-11-29 14:17:01 -0800954
Ken Zhang5cf85c02012-08-23 19:32:52 -0700955struct mdp_blend_cfg {
956 uint32_t is_premultiplied;
957};
958
Pawan Kumar9807ea12013-02-14 18:12:02 +0530959struct mdp_mixer_cfg {
960 uint32_t writeback_format;
961 uint32_t alpha;
962};
963
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800964struct mdss_hw_caps {
965 uint32_t mdp_rev;
966 uint8_t rgb_pipes;
967 uint8_t vig_pipes;
968 uint8_t dma_pipes;
Sree Sesha Aravind Vadrevu10c4d772013-03-28 13:11:12 -0700969 uint32_t features;
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800970};
971
Ken Zhang5cf85c02012-08-23 19:32:52 -0700972struct msmfb_metadata {
973 uint32_t op;
974 uint32_t flags;
975 union {
Sree Sesha Aravind Vadrevu7bacaaa2013-03-20 11:50:25 -0700976 struct mdp_misr misr_request;
Ken Zhang5cf85c02012-08-23 19:32:52 -0700977 struct mdp_blend_cfg blend_cfg;
Pawan Kumar9807ea12013-02-14 18:12:02 +0530978 struct mdp_mixer_cfg mixer_cfg;
Ken Zhang420dd202013-01-08 14:28:20 -0500979 uint32_t panel_frame_rate;
Manoj Raoa8e39d92013-02-16 08:47:21 -0800980 uint32_t video_info_code;
Adrian Salido-Moreno9bf71f32013-03-05 19:23:44 -0800981 struct mdss_hw_caps caps;
Tatenda Chipeperekwa5dc8c482013-10-25 17:44:37 -0700982 uint8_t secure_en;
Ken Zhang5cf85c02012-08-23 19:32:52 -0700983 } data;
984};
Ken Zhang5295d802012-11-07 18:33:16 -0500985
Adrian Salido-Moreno1a74a492013-05-11 21:24:43 -0700986#define MDP_MAX_FENCE_FD 32
Ken Zhang5295d802012-11-07 18:33:16 -0500987#define MDP_BUF_SYNC_FLAG_WAIT 1
Adrian Salido-Moreno1017e942014-01-10 15:39:49 -0800988#define MDP_BUF_SYNC_FLAG_RETIRE_FENCE 0x10
Ken Zhang5295d802012-11-07 18:33:16 -0500989
990struct mdp_buf_sync {
991 uint32_t flags;
992 uint32_t acq_fen_fd_cnt;
Jayant Shekharf3996992013-08-22 14:28:10 +0530993 uint32_t session_id;
Ken Zhang5295d802012-11-07 18:33:16 -0500994 int *acq_fen_fd;
995 int *rel_fen_fd;
Adrian Salido-Moreno1017e942014-01-10 15:39:49 -0800996 int *retire_fen_fd;
Ken Zhang5295d802012-11-07 18:33:16 -0500997};
998
Terence Hampson3e636aa2013-05-08 19:01:51 -0400999struct mdp_async_blit_req_list {
1000 struct mdp_buf_sync sync;
1001 uint32_t count;
1002 struct mdp_blit_req req[];
1003};
1004
Ken Zhang4e83b932012-12-02 21:15:47 -05001005#define MDP_DISPLAY_COMMIT_OVERLAY 1
1006
1007struct mdp_display_commit {
1008 uint32_t flags;
1009 uint32_t wait_for_finish;
1010 struct fb_var_screeninfo var;
Jeykumar Sankaranb826f332013-09-07 00:58:43 -07001011 struct mdp_rect roi;
Ken Zhang4e83b932012-12-02 21:15:47 -05001012};
1013
Adrian Salido-Moreno6b155092014-01-07 17:29:20 -08001014/**
1015* struct mdp_overlay_list - argument for ioctl MSMFB_OVERLAY_PREPARE
1016* @num_overlays: Number of overlay layers as part of the frame.
1017* @overlay_list: Pointer to a list of overlay structures identifying
1018* the layers as part of the frame
1019* @flags: Flags can be used to extend behavior.
1020* @processed_overlays: Output parameter indicating how many pipes were
1021* successful. If there are no errors this number should
1022* match num_overlays. Otherwise it will indicate the last
1023* successful index for overlay that couldn't be set.
1024*/
1025struct mdp_overlay_list {
1026 uint32_t num_overlays;
1027 struct mdp_overlay **overlay_list;
1028 uint32_t flags;
1029 uint32_t processed_overlays;
1030};
1031
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001032struct mdp_page_protection {
1033 uint32_t page_protection;
1034};
1035
kuogee hsieh405dc302011-07-21 15:06:59 -07001036
1037struct mdp_mixer_info {
1038 int pndx;
1039 int pnum;
1040 int ptype;
1041 int mixer_num;
1042 int z_order;
1043};
1044
1045#define MAX_PIPE_PER_MIXER 4
1046
1047struct msmfb_mixer_info_req {
1048 int mixer_num;
1049 int cnt;
1050 struct mdp_mixer_info info[MAX_PIPE_PER_MIXER];
1051};
1052
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -07001053enum {
1054 DISPLAY_SUBSYSTEM_ID,
1055 ROTATOR_SUBSYSTEM_ID,
1056};
kuogee hsieh405dc302011-07-21 15:06:59 -07001057
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -08001058enum {
1059 MDP_IOMMU_DOMAIN_CP,
1060 MDP_IOMMU_DOMAIN_NS,
1061};
1062
Deva Ramasubramanian166b0982013-01-25 20:11:41 -08001063enum {
1064 MDP_WRITEBACK_MIRROR_OFF,
1065 MDP_WRITEBACK_MIRROR_ON,
1066 MDP_WRITEBACK_MIRROR_PAUSE,
1067 MDP_WRITEBACK_MIRROR_RESUME,
1068};
1069
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001070#ifdef __KERNEL__
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -08001071int msm_fb_get_iommu_domain(struct fb_info *info, int domain);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001072/* get the framebuffer physical address information */
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -07001073int get_fb_phys_info(unsigned long *start, unsigned long *len, int fb_num,
1074 int subsys_id);
Vinay Kalia27020d12011-10-14 17:50:29 -07001075struct fb_info *msm_fb_get_writeback_fb(void);
1076int msm_fb_writeback_init(struct fb_info *info);
Vinay Kaliae1ba2702011-12-21 16:24:52 -08001077int msm_fb_writeback_start(struct fb_info *info);
Vinay Kalia27020d12011-10-14 17:50:29 -07001078int msm_fb_writeback_queue_buffer(struct fb_info *info,
1079 struct msmfb_data *data);
1080int msm_fb_writeback_dequeue_buffer(struct fb_info *info,
1081 struct msmfb_data *data);
Vinay Kaliae1ba2702011-12-21 16:24:52 -08001082int msm_fb_writeback_stop(struct fb_info *info);
Vinay Kalia27020d12011-10-14 17:50:29 -07001083int msm_fb_writeback_terminate(struct fb_info *info);
Adrian Salido-Moreno96d88d42012-12-20 13:01:39 -08001084int msm_fb_writeback_set_secure(struct fb_info *info, int enable);
Pawan Kumarce25d142014-01-29 16:47:35 +05301085int msm_fb_writeback_iommu_ref(struct fb_info *info, int enable);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001086#endif
1087
1088#endif /*_MSM_MDP_H_*/