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gerrit-public.fairphone.software / toolchain / llvm-project / 5ea0a681154c1236430dadc2dd57b06f60ca92e8 / . / llvm / lib / Target / X86 / X86InstrFragmentsSIMD.td
blob: aa005a19016db25be20a24ef5dfdcea19316bbbf [file] [log] [blame]
Jia Liue1d61962012-02-19 02:03:36 +0000[diff] [blame]1//===-- X86InstrFragmentsSIMD.td - x86 SIMD ISA ------------*- tablegen -*-===//
David Greene509be1f2010-02-09 23:52:19 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]7//
David Greene509be1f2010-02-09 23:52:19 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
9//
10// This file provides pattern fragments useful for SIMD instructions.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
Bruno Cardoso Lopese446aef2015-02-05 13:22:50 +0000[diff] [blame]15// MMX specific DAG Nodes.
16//===----------------------------------------------------------------------===//
17
18// Low word of MMX to GPR.
19def MMX_X86movd2w : SDNode<"X86ISD::MMX_MOVD2W", SDTypeProfile<1, 1,
20 [SDTCisVT<0, i32>, SDTCisVT<1, x86mmx>]>>;
Bruno Cardoso Lopesab9ae872015-02-05 13:23:07 +0000[diff] [blame]21// GPR to low word of MMX.
22def MMX_X86movw2d : SDNode<"X86ISD::MMX_MOVW2D", SDTypeProfile<1, 1,
23 [SDTCisVT<0, x86mmx>, SDTCisVT<1, i32>]>>;
Bruno Cardoso Lopese446aef2015-02-05 13:22:50 +0000[diff] [blame]24
25//===----------------------------------------------------------------------===//
David Greene509be1f2010-02-09 23:52:19 +0000[diff] [blame]26// MMX Pattern Fragments
27//===----------------------------------------------------------------------===//
28
Dale Johannesendd224d22010-09-30 23:57:10 +0000[diff] [blame]29def load_mmx : PatFrag<(ops node:$ptr), (x86mmx (load node:$ptr))>;
Bruno Cardoso Lopes9e1c4c12015-02-23 15:23:14 +0000[diff] [blame]30def load_mvmmx : PatFrag<(ops node:$ptr),
31 (x86mmx (MMX_X86movw2d (load node:$ptr)))>;
Dale Johannesendd224d22010-09-30 23:57:10 +0000[diff] [blame]32def bc_mmx : PatFrag<(ops node:$in), (x86mmx (bitconvert node:$in))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]33
34//===----------------------------------------------------------------------===//
35// SSE specific DAG Nodes.
36//===----------------------------------------------------------------------===//
37
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]38def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]39 SDTCisFP<1>, SDTCisVT<3, i8>,
40 SDTCisVec<1>]>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]41
42def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
43def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
Nadav Rotem178250a2012-08-19 13:06:16 +0000[diff] [blame]44
45// Commutative and Associative FMIN and FMAX.
46def X86fminc : SDNode<"X86ISD::FMINC", SDTFPBinOp,
47 [SDNPCommutative, SDNPAssociative]>;
48def X86fmaxc : SDNode<"X86ISD::FMAXC", SDTFPBinOp,
49 [SDNPCommutative, SDNPAssociative]>;
50
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]51def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
52 [SDNPCommutative, SDNPAssociative]>;
53def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
54 [SDNPCommutative, SDNPAssociative]>;
55def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
56 [SDNPCommutative, SDNPAssociative]>;
Benjamin Kramer5bc180c2013-08-04 12:05:16 +0000[diff] [blame]57def X86fandn : SDNode<"X86ISD::FANDN", SDTFPBinOp,
58 [SDNPCommutative, SDNPAssociative]>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]59def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
60def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
Stuart Hastings9f208042011-06-01 04:39:42 +0000[diff] [blame]61def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>;
Duncan Sands0e4fcb82011-09-22 20:15:48 +0000[diff] [blame]62def X86fhadd : SDNode<"X86ISD::FHADD", SDTFPBinOp>;
63def X86fhsub : SDNode<"X86ISD::FHSUB", SDTFPBinOp>;
Craig Topperf984efb2011-11-19 09:02:40 +0000[diff] [blame]64def X86hadd : SDNode<"X86ISD::HADD", SDTIntBinOp>;
65def X86hsub : SDNode<"X86ISD::HSUB", SDTIntBinOp>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]66def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
67def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]68def X86cmps : SDNode<"X86ISD::FSETCC", SDTX86Cmps>;
69//def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>;
Simon Pilgrimcae7b942015-06-16 21:40:28 +0000[diff] [blame]70def X86cvtdq2pd: SDNode<"X86ISD::CVTDQ2PD",
71 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
72 SDTCisVT<1, v4i32>]>>;
Elena Demikhovsky0f370932015-07-13 13:26:20 +0000[diff] [blame]73def X86cvtudq2pd: SDNode<"X86ISD::CVTUDQ2PD",
74 SDTypeProfile<1, 1, [SDTCisVT<0, v2f64>,
75 SDTCisVT<1, v4i32>]>>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]76def X86pshufb : SDNode<"X86ISD::PSHUFB",
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]77 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]78 SDTCisSameAs<0,2>]>>;
Chandler Carruth6ba97302015-05-30 03:20:59 +0000[diff] [blame]79def X86psadbw : SDNode<"X86ISD::PSADBW",
80 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
81 SDTCisSameAs<0,2>]>>;
Igor Bregerf3ded812015-08-31 13:09:30 +0000[diff] [blame]82def X86dbpsadbw : SDNode<"X86ISD::DBPSADBW",
83 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisVec<1>,
84 SDTCisSameAs<1,2>, SDTCisInt<3>]>>;
Bruno Cardoso Lopes7ba479d2011-07-13 21:36:47 +0000[diff] [blame]85def X86andnp : SDNode<"X86ISD::ANDNP",
Bruno Cardoso Lopes9613b642011-07-13 21:36:51 +0000[diff] [blame]86 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
Nate Begeman97b72c92010-12-17 22:55:37 +0000[diff] [blame]87 SDTCisSameAs<0,2>]>>;
Craig Topper81390be2011-11-19 07:33:10 +0000[diff] [blame]88def X86psign : SDNode<"X86ISD::PSIGN",
Craig Topperde6b73b2011-11-19 07:07:26 +0000[diff] [blame]89 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
Nate Begeman97b72c92010-12-17 22:55:37 +0000[diff] [blame]90 SDTCisSameAs<0,2>]>>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]91def X86pextrb : SDNode<"X86ISD::PEXTRB",
92 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
93def X86pextrw : SDNode<"X86ISD::PEXTRW",
94 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
95def X86pinsrb : SDNode<"X86ISD::PINSRB",
96 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
97 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
98def X86pinsrw : SDNode<"X86ISD::PINSRW",
99 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
100 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]101def X86insertps : SDNode<"X86ISD::INSERTPS",
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]102 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]103 SDTCisVT<2, v4f32>, SDTCisVT<3, i8>]>>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]104def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
105 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
Elena Demikhovsky8d7e56c2012-04-22 09:39:03 +0000[diff] [blame]106
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]107def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
Chris Lattner54e53292010-09-22 00:34:38 +0000[diff] [blame]108 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
Michael Liao34107b92012-08-14 21:24:47 +0000[diff] [blame]109
Michael Liao1be96bb2012-10-23 17:34:00 +0000[diff] [blame]110def X86vzext : SDNode<"X86ISD::VZEXT",
111 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]112 SDTCisInt<0>, SDTCisInt<1>,
113 SDTCisOpSmallerThanOp<1, 0>]>>;
Michael Liao1be96bb2012-10-23 17:34:00 +0000[diff] [blame]114
115def X86vsext : SDNode<"X86ISD::VSEXT",
116 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]117 SDTCisInt<0>, SDTCisInt<1>,
118 SDTCisOpSmallerThanOp<1, 0>]>>;
Michael Liao1be96bb2012-10-23 17:34:00 +0000[diff] [blame]119
Igor Breger074a64e2015-07-24 17:24:15 +0000[diff] [blame]120def SDTVtrunc : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
121 SDTCisInt<0>, SDTCisInt<1>,
122 SDTCisOpSmallerThanOp<0, 1>]>;
123
124def X86vtrunc : SDNode<"X86ISD::VTRUNC", SDTVtrunc>;
125def X86vtruncs : SDNode<"X86ISD::VTRUNCS", SDTVtrunc>;
126def X86vtruncus : SDNode<"X86ISD::VTRUNCUS", SDTVtrunc>;
127
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]128def X86trunc : SDNode<"X86ISD::TRUNC",
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]129 SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisInt<1>,
130 SDTCisOpSmallerThanOp<0, 1>]>>;
Michael Liao34107b92012-08-14 21:24:47 +0000[diff] [blame]131def X86vfpext : SDNode<"X86ISD::VFPEXT",
132 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]133 SDTCisFP<0>, SDTCisFP<1>,
134 SDTCisOpSmallerThanOp<1, 0>]>>;
Michael Liaoe999b862012-10-10 16:53:28 +0000[diff] [blame]135def X86vfpround: SDNode<"X86ISD::VFPROUND",
136 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
Craig Topperaefaab62014-01-26 04:59:39 +0000[diff] [blame]137 SDTCisFP<0>, SDTCisFP<1>,
138 SDTCisOpSmallerThanOp<0, 1>]>>;
Michael Liao34107b92012-08-14 21:24:47 +0000[diff] [blame]139
Craig Topper09462642012-01-22 19:15:14 +0000[diff] [blame]140def X86vshldq : SDNode<"X86ISD::VSHLDQ", SDTIntShiftOp>;
141def X86vshrdq : SDNode<"X86ISD::VSRLDQ", SDTIntShiftOp>;
Craig Topper0b7ad762012-01-22 23:36:02 +0000[diff] [blame]142def X86cmpp : SDNode<"X86ISD::CMPP", SDTX86VFCMP>;
Craig Topperbd4884372012-01-22 22:42:16 +0000[diff] [blame]143def X86pcmpeq : SDNode<"X86ISD::PCMPEQ", SDTIntBinOp, [SDNPCommutative]>;
144def X86pcmpgt : SDNode<"X86ISD::PCMPGT", SDTIntBinOp>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]145
Elena Demikhovsky60b1f282013-08-13 13:24:07 +0000[diff] [blame]146def X86IntCmpMask : SDTypeProfile<1, 2,
147 [SDTCisVec<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>]>;
148def X86pcmpeqm : SDNode<"X86ISD::PCMPEQM", X86IntCmpMask, [SDNPCommutative]>;
149def X86pcmpgtm : SDNode<"X86ISD::PCMPGTM", X86IntCmpMask>;
150
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]151def X86CmpMaskCC :
Elena Demikhovsky29792e92015-05-07 11:24:42 +0000[diff] [blame]152 SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCVecEltisVT<0, i1>,
153 SDTCisVec<1>, SDTCisSameAs<2, 1>,
154 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>]>;
155def X86CmpMaskCCRound :
156 SDTypeProfile<1, 4, [SDTCisVec<0>,SDTCVecEltisVT<0, i1>,
157 SDTCisVec<1>, SDTCisSameAs<2, 1>,
158 SDTCisSameNumEltsAs<0, 1>, SDTCisVT<3, i8>,
159 SDTCisInt<4>]>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]160def X86CmpMaskCCScalar :
161 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>;
162
Elena Demikhovsky29792e92015-05-07 11:24:42 +0000[diff] [blame]163def X86cmpm : SDNode<"X86ISD::CMPM", X86CmpMaskCC>;
164def X86cmpmRnd : SDNode<"X86ISD::CMPM_RND", X86CmpMaskCCRound>;
165def X86cmpmu : SDNode<"X86ISD::CMPMU", X86CmpMaskCC>;
166def X86cmpms : SDNode<"X86ISD::FSETCC", X86CmpMaskCCScalar>;
Elena Demikhovsky60b1f282013-08-13 13:24:07 +0000[diff] [blame]167
Craig Topper09462642012-01-22 19:15:14 +0000[diff] [blame]168def X86vshl : SDNode<"X86ISD::VSHL",
169 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
170 SDTCisVec<2>]>>;
171def X86vsrl : SDNode<"X86ISD::VSRL",
172 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
173 SDTCisVec<2>]>>;
174def X86vsra : SDNode<"X86ISD::VSRA",
175 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
176 SDTCisVec<2>]>>;
177
178def X86vshli : SDNode<"X86ISD::VSHLI", SDTIntShiftOp>;
179def X86vsrli : SDNode<"X86ISD::VSRLI", SDTIntShiftOp>;
180def X86vsrai : SDNode<"X86ISD::VSRAI", SDTIntShiftOp>;
181
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]182def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
Bruno Cardoso Lopes91d61df2010-08-10 23:25:42 +0000[diff] [blame]183 SDTCisVec<1>,
184 SDTCisSameAs<2, 1>]>;
Elena Demikhovsky52266382015-05-04 12:35:55 +0000[diff] [blame]185def X86addus : SDNode<"X86ISD::ADDUS", SDTIntBinOp>;
Benjamin Kramerb16ccde2012-12-15 16:47:44 +0000[diff] [blame]186def X86subus : SDNode<"X86ISD::SUBUS", SDTIntBinOp>;
Elena Demikhovsky52266382015-05-04 12:35:55 +0000[diff] [blame]187def X86adds : SDNode<"X86ISD::ADDS", SDTIntBinOp>;
188def X86subs : SDNode<"X86ISD::SUBS", SDTIntBinOp>;
Asaf Badouhc6f3c822015-07-06 14:03:40 +0000[diff] [blame]189def X86mulhrs : SDNode<"X86ISD::MULHRS" , SDTIntBinOp>;
Asaf Badouh81f03c32015-06-18 12:30:53 +0000[diff] [blame]190def X86avg : SDNode<"X86ISD::AVG" , SDTIntBinOp>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]191def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
Bruno Cardoso Lopes91d61df2010-08-10 23:25:42 +0000[diff] [blame]192def X86testp : SDNode<"X86ISD::TESTP", SDTX86CmpPTest>;
Elena Demikhovsky40864b62013-08-05 08:52:21 +0000[diff] [blame]193def X86kortest : SDNode<"X86ISD::KORTEST", SDTX86CmpPTest>;
Igor Breger5ea0a6812015-08-31 13:30:19 +0000[diff] [blame^]194def X86ktest : SDNode<"X86ISD::KTEST", SDTX86CmpPTest>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]195def X86testm : SDNode<"X86ISD::TESTM", SDTypeProfile<1, 2, [SDTCisVec<0>,
Elena Demikhovsky431b81e2015-04-21 13:13:46 +0000[diff] [blame]196 SDTCisVec<1>, SDTCisSameAs<2, 1>,
197 SDTCVecEltisVT<0, i1>,
198 SDTCisSameNumEltsAs<0, 1>]>>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]199def X86testnm : SDNode<"X86ISD::TESTNM", SDTypeProfile<1, 2, [SDTCisVec<0>,
Elena Demikhovsky431b81e2015-04-21 13:13:46 +0000[diff] [blame]200 SDTCisVec<1>, SDTCisSameAs<2, 1>,
201 SDTCVecEltisVT<0, i1>,
202 SDTCisSameNumEltsAs<0, 1>]>>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]203def X86select : SDNode<"X86ISD::SELECT" , SDTSelect>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]204
Craig Topper1d471e32012-02-05 03:14:49 +0000[diff] [blame]205def X86pmuludq : SDNode<"X86ISD::PMULUDQ",
206 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
207 SDTCisSameAs<1,2>]>>;
Benjamin Kramer6d2dff62014-04-26 14:12:19 +0000[diff] [blame]208def X86pmuldq : SDNode<"X86ISD::PMULDQ",
209 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
210 SDTCisSameAs<1,2>]>>;
Craig Topper1d471e32012-02-05 03:14:49 +0000[diff] [blame]211
Simon Pilgrimd85cae32015-07-06 20:46:41 +0000[diff] [blame]212def X86extrqi : SDNode<"X86ISD::EXTRQI",
213 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
214 SDTCisVT<2, i8>, SDTCisVT<3, i8>]>>;
215def X86insertqi : SDNode<"X86ISD::INSERTQI",
216 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
217 SDTCisSameAs<1,2>, SDTCisVT<3, i8>,
218 SDTCisVT<4, i8>]>>;
219
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]220// Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
221// translated into one of the target nodes below during lowering.
222// Note: this is a work in progress...
223def SDTShuff1Op : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
224def SDTShuff2Op : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
225 SDTCisSameAs<0,2>]>;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]226def SDTShuff3Op : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
227 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]228
Chandler Carruth6d5916a2014-09-23 10:08:29 +0000[diff] [blame]229def SDTShuff2OpM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
230 SDTCisVec<2>]>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]231def SDTShuff2OpI : SDTypeProfile<1, 2, [SDTCisVec<0>,
232 SDTCisSameAs<0,1>, SDTCisInt<2>]>;
233def SDTShuff3OpI : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
234 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
Elena Demikhovsky42c96d92015-06-01 06:50:49 +0000[diff] [blame]235def SDTFPBinOpImmRound: SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0,1>,
236 SDTCisSameAs<0,2>, SDTCisInt<3>, SDTCisInt<4>]>;
Asaf Badouha5b2e5e2015-07-22 12:00:43 +0000[diff] [blame]237def SDTFPUnaryOpImmRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
238 SDTCisInt<2>, SDTCisInt<3>]>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]239
Elena Demikhovsky45c54ad2013-08-07 12:34:55 +0000[diff] [blame]240def SDTVBroadcast : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
241def SDTVBroadcastm : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>]>;
242
Nadav Rotem9bc178a2012-04-11 06:40:27 +0000[diff] [blame]243def SDTBlend : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]244 SDTCisSameAs<1,2>, SDTCisVT<3, i8>]>;
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]245
Elena Demikhovsky714f23b2015-02-18 07:59:20 +0000[diff] [blame]246def SDTFPBinOpRound : SDTypeProfile<1, 3, [ // fadd_round, fmul_round, etc.
247 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>, SDTCisInt<3>]>;
248
Asaf Badouh402ebb32015-06-03 13:41:48 +0000[diff] [blame]249def SDTFPUnaryOpRound : SDTypeProfile<1, 2, [ // fsqrt_round, fgetexp_round, etc.
250 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]>;
251
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]252def SDTFma : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
253 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
Elena Demikhovsky7b0dd392015-01-28 10:21:27 +0000[diff] [blame]254def SDTFmaRound : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
255 SDTCisSameAs<1,2>, SDTCisSameAs<1,3>, SDTCisInt<4>]>;
Elena Demikhovskybe8808d2014-11-12 07:31:03 +0000[diff] [blame]256def STDFp1SrcRm : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>,
257 SDTCisVec<0>, SDTCisInt<2>]>;
Elena Demikhovsky905a5a62014-11-26 10:46:49 +0000[diff] [blame]258def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,
259 SDTCisVec<0>, SDTCisInt<3>]>;
Elena Demikhovsky52e81bc2015-02-23 15:12:31 +0000[diff] [blame]260def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,
261 SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;
Bruno Cardoso Lopesbe5e9872011-08-17 02:29:19 +0000[diff] [blame]262
Craig Topper8fb09f02013-01-28 06:48:25 +0000[diff] [blame]263def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;
Adam Nemet2f10cc62014-08-05 17:22:55 +0000[diff] [blame]264def X86VAlign : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;
Elena Demikhovsky5e2f8c42015-06-23 08:19:46 +0000[diff] [blame]265def X86Abs : SDNode<"X86ISD::ABS", SDTIntUnaryOp>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]266
267def X86PShufd : SDNode<"X86ISD::PSHUFD", SDTShuff2OpI>;
268def X86PShufhw : SDNode<"X86ISD::PSHUFHW", SDTShuff2OpI>;
269def X86PShuflw : SDNode<"X86ISD::PSHUFLW", SDTShuff2OpI>;
270
Elena Demikhovsky9e380862015-06-03 10:56:40 +0000[diff] [blame]271def X86Shufp : SDNode<"X86ISD::SHUFP", SDTShuff3OpI>;
272def X86Shuf128 : SDNode<"X86ISD::SHUF128", SDTShuff3OpI>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]273
274def X86Movddup : SDNode<"X86ISD::MOVDDUP", SDTShuff1Op>;
275def X86Movshdup : SDNode<"X86ISD::MOVSHDUP", SDTShuff1Op>;
276def X86Movsldup : SDNode<"X86ISD::MOVSLDUP", SDTShuff1Op>;
277
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]278def X86Movsd : SDNode<"X86ISD::MOVSD", SDTShuff2Op>;
279def X86Movss : SDNode<"X86ISD::MOVSS", SDTShuff2Op>;
280
281def X86Movlhps : SDNode<"X86ISD::MOVLHPS", SDTShuff2Op>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]282def X86Movlhpd : SDNode<"X86ISD::MOVLHPD", SDTShuff2Op>;
Bruno Cardoso Lopes03e4c352010-08-31 21:15:21 +0000[diff] [blame]283def X86Movhlps : SDNode<"X86ISD::MOVHLPS", SDTShuff2Op>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]284
Bruno Cardoso Lopesb3825212010-09-01 05:08:25 +0000[diff] [blame]285def X86Movlps : SDNode<"X86ISD::MOVLPS", SDTShuff2Op>;
286def X86Movlpd : SDNode<"X86ISD::MOVLPD", SDTShuff2Op>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]287
Chandler Carruth8366ceb2014-06-20 01:05:28 +0000[diff] [blame]288def SDTPack : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>;
289def X86Packss : SDNode<"X86ISD::PACKSS", SDTPack>;
290def X86Packus : SDNode<"X86ISD::PACKUS", SDTPack>;
291
Craig Topper8d4ba192011-12-06 08:21:25 +0000[diff] [blame]292def X86Unpckl : SDNode<"X86ISD::UNPCKL", SDTShuff2Op>;
293def X86Unpckh : SDNode<"X86ISD::UNPCKH", SDTShuff2Op>;
Bruno Cardoso Lopes6f3b38a2010-08-20 22:55:05 +0000[diff] [blame]294
Igor Bregerf7fd5472015-07-21 07:11:28 +0000[diff] [blame]295def X86vpmaddubsw : SDNode<"X86ISD::VPMADDUBSW" , SDTPack>;
296def X86vpmaddwd : SDNode<"X86ISD::VPMADDWD" , SDTPack>;
297
Chandler Carruth6d5916a2014-09-23 10:08:29 +0000[diff] [blame]298def X86VPermilpv : SDNode<"X86ISD::VPERMILPV", SDTShuff2OpM>;
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]299def X86VPermilpi : SDNode<"X86ISD::VPERMILPI", SDTShuff2OpI>;
300def X86VPermv : SDNode<"X86ISD::VPERMV", SDTShuff2Op>;
301def X86VPermi : SDNode<"X86ISD::VPERMI", SDTShuff2OpI>;
302def X86VPermv3 : SDNode<"X86ISD::VPERMV3", SDTShuff3Op>;
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]303def X86VPermiv3 : SDNode<"X86ISD::VPERMIV3", SDTShuff3Op>;
Bruno Cardoso Lopesb878caa2011-07-21 01:55:47 +0000[diff] [blame]304
Craig Topper0a672ea2011-11-30 07:47:51 +0000[diff] [blame]305def X86VPerm2x128 : SDNode<"X86ISD::VPERM2X128", SDTShuff3OpI>;
Bruno Cardoso Lopesf15dfe52011-08-12 21:48:26 +0000[diff] [blame]306
Elena Demikhovsky42c96d92015-06-01 06:50:49 +0000[diff] [blame]307def X86VFixupimm : SDNode<"X86ISD::VFIXUPIMM", SDTFPBinOpImmRound>;
Elena Demikhovsky3582eb32015-06-01 11:05:34 +0000[diff] [blame]308def X86VRange : SDNode<"X86ISD::VRANGE", SDTFPBinOpImmRound>;
Asaf Badouha5b2e5e2015-07-22 12:00:43 +0000[diff] [blame]309def X86VReduce : SDNode<"X86ISD::VREDUCE", SDTFPUnaryOpImmRound>;
310def X86VRndScale : SDNode<"X86ISD::VRNDSCALE", SDTFPUnaryOpImmRound>;
Elena Demikhovsky42c96d92015-06-01 06:50:49 +0000[diff] [blame]311
Elena Demikhovskyad9c3962015-05-18 06:42:57 +0000[diff] [blame]312def X86SubVBroadcast : SDNode<"X86ISD::SUBV_BROADCAST",
313 SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
314 SDTCisSubVecOfVec<1, 0>]>, []>;
Bruno Cardoso Lopesbe5e9872011-08-17 02:29:19 +0000[diff] [blame]315def X86VBroadcast : SDNode<"X86ISD::VBROADCAST", SDTVBroadcast>;
Elena Demikhovsky89529742013-09-12 08:55:00 +0000[diff] [blame]316def X86Vinsert : SDNode<"X86ISD::VINSERT", SDTypeProfile<1, 3,
317 [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]318def X86Vextract : SDNode<"X86ISD::VEXTRACT", SDTypeProfile<1, 2,
319 [SDTCisVec<1>, SDTCisPtrTy<2>]>, []>;
Bruno Cardoso Lopesbe5e9872011-08-17 02:29:19 +0000[diff] [blame]320
Elena Demikhovskycd3c1c42012-12-05 09:24:57 +0000[diff] [blame]321def X86Blendi : SDNode<"X86ISD::BLENDI", SDTBlend>;
Chandler Carruth204ad4c2014-09-15 20:09:47 +0000[diff] [blame]322
323def X86Addsub : SDNode<"X86ISD::ADDSUB", SDTFPBinOp>;
324
Elena Demikhovsky714f23b2015-02-18 07:59:20 +0000[diff] [blame]325def X86faddRnd : SDNode<"X86ISD::FADD_RND", SDTFPBinOpRound>;
326def X86fsubRnd : SDNode<"X86ISD::FSUB_RND", SDTFPBinOpRound>;
327def X86fmulRnd : SDNode<"X86ISD::FMUL_RND", SDTFPBinOpRound>;
328def X86fdivRnd : SDNode<"X86ISD::FDIV_RND", SDTFPBinOpRound>;
Elena Demikhovsky0d7e9362015-05-11 06:05:05 +0000[diff] [blame]329def X86fmaxRnd : SDNode<"X86ISD::FMAX_RND", SDTFPBinOpRound>;
Asaf Badouh7ec4b7a2015-06-28 14:30:39 +0000[diff] [blame]330def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
Elena Demikhovsky0d7e9362015-05-11 06:05:05 +0000[diff] [blame]331def X86fminRnd : SDNode<"X86ISD::FMIN_RND", SDTFPBinOpRound>;
Asaf Badouh402ebb32015-06-03 13:41:48 +0000[diff] [blame]332def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
Igor Breger8352a0d2015-07-28 06:53:28 +0000[diff] [blame]333def X86fgetexpRnd : SDNode<"X86ISD::FGETEXP_RND", SDTFPUnaryOpRound>;
334def X86fgetexpRnds : SDNode<"X86ISD::FGETEXP_RND", STDFp2SrcRm>;
Elena Demikhovsky714f23b2015-02-18 07:59:20 +0000[diff] [blame]335
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]336def X86Fmadd : SDNode<"X86ISD::FMADD", SDTFma>;
337def X86Fnmadd : SDNode<"X86ISD::FNMADD", SDTFma>;
338def X86Fmsub : SDNode<"X86ISD::FMSUB", SDTFma>;
339def X86Fnmsub : SDNode<"X86ISD::FNMSUB", SDTFma>;
Craig Toppera999c662012-08-29 07:18:25 +0000[diff] [blame]340def X86Fmaddsub : SDNode<"X86ISD::FMADDSUB", SDTFma>;
341def X86Fmsubadd : SDNode<"X86ISD::FMSUBADD", SDTFma>;
Nadav Rotem9bc178a2012-04-11 06:40:27 +0000[diff] [blame]342
Elena Demikhovsky7b0dd392015-01-28 10:21:27 +0000[diff] [blame]343def X86FmaddRnd : SDNode<"X86ISD::FMADD_RND", SDTFmaRound>;
344def X86FnmaddRnd : SDNode<"X86ISD::FNMADD_RND", SDTFmaRound>;
345def X86FmsubRnd : SDNode<"X86ISD::FMSUB_RND", SDTFmaRound>;
346def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound>;
347def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound>;
348def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound>;
349
Elena Demikhovskybe8808d2014-11-12 07:31:03 +0000[diff] [blame]350def X86rsqrt28 : SDNode<"X86ISD::RSQRT28", STDFp1SrcRm>;
351def X86rcp28 : SDNode<"X86ISD::RCP28", STDFp1SrcRm>;
Elena Demikhovsky905a5a62014-11-26 10:46:49 +0000[diff] [blame]352def X86exp2 : SDNode<"X86ISD::EXP2", STDFp1SrcRm>;
353
354def X86rsqrt28s : SDNode<"X86ISD::RSQRT28", STDFp2SrcRm>;
355def X86rcp28s : SDNode<"X86ISD::RCP28", STDFp2SrcRm>;
Asaf Badouha5b2e5e2015-07-22 12:00:43 +0000[diff] [blame]356def X86RndScales : SDNode<"X86ISD::VRNDSCALE", STDFp3SrcRm>;
357def X86Reduces : SDNode<"X86ISD::VREDUCE", STDFp3SrcRm>;
Elena Demikhovskybe8808d2014-11-12 07:31:03 +0000[diff] [blame]358
Craig Topperab47fe42012-08-06 06:22:36 +0000[diff] [blame]359def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
360 SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,
361 SDTCisVT<4, i8>]>;
362def SDT_PCMPESTRI : SDTypeProfile<2, 5, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
363 SDTCisVT<2, v16i8>, SDTCisVT<3, i32>,
364 SDTCisVT<4, v16i8>, SDTCisVT<5, i32>,
365 SDTCisVT<6, i8>]>;
366
367def X86pcmpistri : SDNode<"X86ISD::PCMPISTRI", SDT_PCMPISTRI>;
368def X86pcmpestri : SDNode<"X86ISD::PCMPESTRI", SDT_PCMPESTRI>;
369
Elena Demikhovskyba5ab322015-06-22 11:16:30 +0000[diff] [blame]370def X86compress: SDNode<"X86ISD::COMPRESS", SDTypeProfile<1, 1,
371 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
372def X86expand : SDNode<"X86ISD::EXPAND", SDTypeProfile<1, 1,
373 [SDTCisSameAs<0, 1>, SDTCisVec<1>]>, []>;
Elena Demikhovsky908dbf42014-12-11 15:02:24 +0000[diff] [blame]374
Igor Bregerabe4a792015-06-14 12:44:55 +0000[diff] [blame]375def SDTintToFPRound: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisFP<0>,
376 SDTCisSameAs<0,1>, SDTCisInt<2>, SDTCisInt<3>]>;
377
Elena Demikhovsky0f370932015-07-13 13:26:20 +0000[diff] [blame]378def SDTDoubleToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
379 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
380def SDTFloatToInt: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>,
381 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
382
383def SDTDoubleToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
384 SDTCisInt<0>, SDTCVecEltisVT<1, f64>]>;
385def SDTFloatToIntRnd: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
386 SDTCisInt<0>, SDTCVecEltisVT<1, f32>]>;
387
388def SDTVintToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
389 SDTCisFP<0>, SDTCVecEltisVT<1, i32>,
390 SDTCisInt<2>]>;
391def SDTVlongToFPRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
392 SDTCisFP<0>, SDTCVecEltisVT<1, i64>,
393 SDTCisInt<2>]>;
394
395def SDTVFPToIntRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
396 SDTCisFP<1>, SDTCVecEltisVT<0, i32>,
397 SDTCisInt<2>]>;
398def SDTVFPToLongRound: SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
399 SDTCisFP<1>, SDTCVecEltisVT<0, i64>,
400 SDTCisInt<2>]>;
401
402// Scalar
403def X86SintToFpRnd : SDNode<"X86ISD::SINT_TO_FP_RND", SDTintToFPRound>;
404def X86UintToFpRnd : SDNode<"X86ISD::UINT_TO_FP_RND", SDTintToFPRound>;
405
406// Vector with rounding mode
407
408// cvtt fp-to-int staff
409def X86VFpToSintRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToIntRound>;
410def X86VFpToUintRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToIntRound>;
411def X86VFpToSlongRnd : SDNode<"ISD::FP_TO_SINT", SDTVFPToLongRound>;
412def X86VFpToUlongRnd : SDNode<"ISD::FP_TO_UINT", SDTVFPToLongRound>;
413
414def X86VSintToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVintToFPRound>;
415def X86VUintToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVintToFPRound>;
416def X86VSlongToFpRnd : SDNode<"ISD::SINT_TO_FP", SDTVlongToFPRound>;
417def X86VUlongToFpRnd : SDNode<"ISD::UINT_TO_FP", SDTVlongToFPRound>;
418
419// cvt fp-to-int staff
420def X86cvtps2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToIntRnd>;
421def X86cvtps2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToIntRnd>;
422def X86cvtpd2IntRnd : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToIntRnd>;
423def X86cvtpd2UIntRnd : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToIntRnd>;
424
425// Vector without rounding mode
426def X86cvtps2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTFloatToInt>;
427def X86cvtps2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTFloatToInt>;
428def X86cvtpd2Int : SDNode<"X86ISD::FP_TO_SINT_RND", SDTDoubleToInt>;
429def X86cvtpd2UInt : SDNode<"X86ISD::FP_TO_UINT_RND", SDTDoubleToInt>;
430
431def X86vfpextRnd : SDNode<"X86ISD::VFPEXT",
432 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
433 SDTCisFP<0>, SDTCisFP<1>,
434 SDTCisOpSmallerThanOp<1, 0>,
435 SDTCisInt<2>]>>;
436def X86vfproundRnd: SDNode<"X86ISD::VFPROUND",
437 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
438 SDTCisFP<0>, SDTCisFP<1>,
439 SDTCVecEltisVT<0, f32>,
440 SDTCVecEltisVT<1, f64>,
441 SDTCisInt<2>]>>;
Igor Bregerabe4a792015-06-14 12:44:55 +0000[diff] [blame]442
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]443//===----------------------------------------------------------------------===//
444// SSE Complex Patterns
445//===----------------------------------------------------------------------===//
446
447// These are 'extloads' from a scalar to the low element of a vector, zeroing
448// the top elements. These are used for the SSE 'ss' and 'sd' instruction
449// forms.
450def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
Chris Lattner0e023ea2010-09-21 20:31:19 +0000[diff] [blame]451 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
452 SDNPWantRoot]>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]453def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
Chris Lattner0e023ea2010-09-21 20:31:19 +0000[diff] [blame]454 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand,
455 SDNPWantRoot]>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]456
457def ssmem : Operand<v4f32> {
458 let PrintMethod = "printf32mem";
459 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
Craig Topper6269f492013-08-26 00:39:04 +0000[diff] [blame]460 let ParserMatchClass = X86Mem32AsmOperand;
Benjamin Kramer9654eef2011-07-14 21:47:22 +0000[diff] [blame]461 let OperandType = "OPERAND_MEMORY";
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]462}
463def sdmem : Operand<v2f64> {
464 let PrintMethod = "printf64mem";
465 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
Craig Topper6269f492013-08-26 00:39:04 +0000[diff] [blame]466 let ParserMatchClass = X86Mem64AsmOperand;
Benjamin Kramer9654eef2011-07-14 21:47:22 +0000[diff] [blame]467 let OperandType = "OPERAND_MEMORY";
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]468}
469
470//===----------------------------------------------------------------------===//
471// SSE pattern fragments
472//===----------------------------------------------------------------------===//
473
Bruno Cardoso Lopes160be292010-08-13 20:39:01 +0000[diff] [blame]474// 128-bit load pattern fragments
Craig Topper0d8e67a2012-01-24 03:03:17 +0000[diff] [blame]475// NOTE: all 128-bit integer vector loads are promoted to v2i64
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]476def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
477def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]478def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
479
Bruno Cardoso Lopes160be292010-08-13 20:39:01 +0000[diff] [blame]480// 256-bit load pattern fragments
Craig Topper0d8e67a2012-01-24 03:03:17 +0000[diff] [blame]481// NOTE: all 256-bit integer vector loads are promoted to v4i64
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]482def loadv8f32 : PatFrag<(ops node:$ptr), (v8f32 (load node:$ptr))>;
483def loadv4f64 : PatFrag<(ops node:$ptr), (v4f64 (load node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]484def loadv4i64 : PatFrag<(ops node:$ptr), (v4i64 (load node:$ptr))>;
485
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]486// 512-bit load pattern fragments
487def loadv16f32 : PatFrag<(ops node:$ptr), (v16f32 (load node:$ptr))>;
488def loadv8f64 : PatFrag<(ops node:$ptr), (v8f64 (load node:$ptr))>;
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]489def loadv64i8 : PatFrag<(ops node:$ptr), (v64i8 (load node:$ptr))>;
490def loadv32i16 : PatFrag<(ops node:$ptr), (v32i16 (load node:$ptr))>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]491def loadv16i32 : PatFrag<(ops node:$ptr), (v16i32 (load node:$ptr))>;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]492def loadv8i64 : PatFrag<(ops node:$ptr), (v8i64 (load node:$ptr))>;
493
494// 128-/256-/512-bit extload pattern fragments
Michael Liao400f7ef2012-09-10 18:33:51 +0000[diff] [blame]495def extloadv2f32 : PatFrag<(ops node:$ptr), (v2f64 (extloadvf32 node:$ptr))>;
496def extloadv4f32 : PatFrag<(ops node:$ptr), (v4f64 (extloadvf32 node:$ptr))>;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]497def extloadv8f32 : PatFrag<(ops node:$ptr), (v8f64 (extloadvf32 node:$ptr))>;
Michael Liao400f7ef2012-09-10 18:33:51 +0000[diff] [blame]498
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]499// These are needed to match a scalar load that is used in a vector-only
500// math instruction such as the FP logical ops: andps, andnps, orps, xorps.
501// The memory operand is required to be a 128-bit load, so it must be converted
502// from a vector to a scalar.
503def loadf32_128 : PatFrag<(ops node:$ptr),
504 (f32 (vector_extract (loadv4f32 node:$ptr), (iPTR 0)))>;
505def loadf64_128 : PatFrag<(ops node:$ptr),
506 (f64 (vector_extract (loadv2f64 node:$ptr), (iPTR 0)))>;
507
Bruno Cardoso Lopes03d60022011-09-13 19:33:03 +0000[diff] [blame]508// Like 'store', but always requires 128-bit vector alignment.
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]509def alignedstore : PatFrag<(ops node:$val, node:$ptr),
510 (store node:$val, node:$ptr), [{
511 return cast<StoreSDNode>(N)->getAlignment() >= 16;
512}]>;
513
Bruno Cardoso Lopes03d60022011-09-13 19:33:03 +0000[diff] [blame]514// Like 'store', but always requires 256-bit vector alignment.
515def alignedstore256 : PatFrag<(ops node:$val, node:$ptr),
516 (store node:$val, node:$ptr), [{
517 return cast<StoreSDNode>(N)->getAlignment() >= 32;
518}]>;
519
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]520// Like 'store', but always requires 512-bit vector alignment.
521def alignedstore512 : PatFrag<(ops node:$val, node:$ptr),
522 (store node:$val, node:$ptr), [{
523 return cast<StoreSDNode>(N)->getAlignment() >= 64;
524}]>;
525
Bruno Cardoso Lopes03d60022011-09-13 19:33:03 +0000[diff] [blame]526// Like 'load', but always requires 128-bit vector alignment.
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]527def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
528 return cast<LoadSDNode>(N)->getAlignment() >= 16;
529}]>;
530
Chad Rosiera281afc2012-03-09 02:00:48 +0000[diff] [blame]531// Like 'X86vzload', but always requires 128-bit vector alignment.
532def alignedX86vzload : PatFrag<(ops node:$ptr), (X86vzload node:$ptr), [{
533 return cast<MemSDNode>(N)->getAlignment() >= 16;
534}]>;
535
Bruno Cardoso Lopes03d60022011-09-13 19:33:03 +0000[diff] [blame]536// Like 'load', but always requires 256-bit vector alignment.
537def alignedload256 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
538 return cast<LoadSDNode>(N)->getAlignment() >= 32;
539}]>;
540
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]541// Like 'load', but always requires 512-bit vector alignment.
542def alignedload512 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
543 return cast<LoadSDNode>(N)->getAlignment() >= 64;
544}]>;
545
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]546def alignedloadfsf32 : PatFrag<(ops node:$ptr),
547 (f32 (alignedload node:$ptr))>;
548def alignedloadfsf64 : PatFrag<(ops node:$ptr),
549 (f64 (alignedload node:$ptr))>;
Bruno Cardoso Lopes160be292010-08-13 20:39:01 +0000[diff] [blame]550
551// 128-bit aligned load pattern fragments
Craig Topper0d8e67a2012-01-24 03:03:17 +0000[diff] [blame]552// NOTE: all 128-bit integer vector loads are promoted to v2i64
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]553def alignedloadv4f32 : PatFrag<(ops node:$ptr),
554 (v4f32 (alignedload node:$ptr))>;
555def alignedloadv2f64 : PatFrag<(ops node:$ptr),
556 (v2f64 (alignedload node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]557def alignedloadv2i64 : PatFrag<(ops node:$ptr),
558 (v2i64 (alignedload node:$ptr))>;
559
Bruno Cardoso Lopes160be292010-08-13 20:39:01 +0000[diff] [blame]560// 256-bit aligned load pattern fragments
Craig Topper0d8e67a2012-01-24 03:03:17 +0000[diff] [blame]561// NOTE: all 256-bit integer vector loads are promoted to v4i64
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]562def alignedloadv8f32 : PatFrag<(ops node:$ptr),
Bruno Cardoso Lopes03d60022011-09-13 19:33:03 +0000[diff] [blame]563 (v8f32 (alignedload256 node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]564def alignedloadv4f64 : PatFrag<(ops node:$ptr),
Bruno Cardoso Lopes03d60022011-09-13 19:33:03 +0000[diff] [blame]565 (v4f64 (alignedload256 node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]566def alignedloadv4i64 : PatFrag<(ops node:$ptr),
Bruno Cardoso Lopes03d60022011-09-13 19:33:03 +0000[diff] [blame]567 (v4i64 (alignedload256 node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]568
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]569// 512-bit aligned load pattern fragments
570def alignedloadv16f32 : PatFrag<(ops node:$ptr),
571 (v16f32 (alignedload512 node:$ptr))>;
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]572def alignedloadv16i32 : PatFrag<(ops node:$ptr),
573 (v16i32 (alignedload512 node:$ptr))>;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]574def alignedloadv8f64 : PatFrag<(ops node:$ptr),
575 (v8f64 (alignedload512 node:$ptr))>;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]576def alignedloadv8i64 : PatFrag<(ops node:$ptr),
577 (v8i64 (alignedload512 node:$ptr))>;
578
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]579// Like 'load', but uses special alignment checks suitable for use in
580// memory operands in most SSE instructions, which are required to
581// be naturally aligned on some targets but not on others. If the subtarget
582// allows unaligned accesses, match any load, though this may require
583// setting a feature bit in the processor (on startup, for example).
584// Opteron 10h and later implement such a feature.
585def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
Sanjay Patelffd039b2015-02-03 17:13:04 +0000[diff] [blame]586 return Subtarget->hasSSEUnalignedMem()
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]587 || cast<LoadSDNode>(N)->getAlignment() >= 16;
588}]>;
589
590def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
591def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
Bruno Cardoso Lopes160be292010-08-13 20:39:01 +0000[diff] [blame]592
593// 128-bit memop pattern fragments
Craig Topper0d8e67a2012-01-24 03:03:17 +0000[diff] [blame]594// NOTE: all 128-bit integer vector loads are promoted to v2i64
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]595def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
596def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]597def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]598
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]599// These are needed to match a scalar memop that is used in a vector-only
600// math instruction such as the FP logical ops: andps, andnps, orps, xorps.
601// The memory operand is required to be a 128-bit load, so it must be converted
602// from a vector to a scalar.
603def memopfsf32_128 : PatFrag<(ops node:$ptr),
604 (f32 (vector_extract (memopv4f32 node:$ptr), (iPTR 0)))>;
605def memopfsf64_128 : PatFrag<(ops node:$ptr),
606 (f64 (vector_extract (memopv2f64 node:$ptr), (iPTR 0)))>;
607
608
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]609// SSSE3 uses MMX registers for some instructions. They aren't aligned on a
610// 16-byte boundary.
611// FIXME: 8 byte alignment for mmx reads is not required
612def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
613 return cast<LoadSDNode>(N)->getAlignment() >= 8;
614}]>;
615
Dale Johannesendd224d22010-09-30 23:57:10 +0000[diff] [blame]616def memopmmx : PatFrag<(ops node:$ptr), (x86mmx (memop64 node:$ptr))>;
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]617
618// MOVNT Support
619// Like 'store', but requires the non-temporal bit to be set
620def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
621 (st node:$val, node:$ptr), [{
622 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
623 return ST->isNonTemporal();
624 return false;
625}]>;
626
627def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
Bill Wendlingea6397f2012-07-19 00:11:40 +0000[diff] [blame]628 (st node:$val, node:$ptr), [{
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]629 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
630 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
631 ST->getAddressingMode() == ISD::UNINDEXED &&
632 ST->getAlignment() >= 16;
633 return false;
634}]>;
635
636def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
Bill Wendlingea6397f2012-07-19 00:11:40 +0000[diff] [blame]637 (st node:$val, node:$ptr), [{
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]638 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
639 return ST->isNonTemporal() &&
640 ST->getAlignment() < 16;
641 return false;
642}]>;
643
Elena Demikhovsky6a1a3572015-06-28 10:53:29 +0000[diff] [blame]644def mgatherv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
645 (masked_gather node:$src1, node:$src2, node:$src3) , [{
646 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
647 return (Mgt->getIndex().getValueType() == MVT::v4i32 ||
648 Mgt->getBasePtr().getValueType() == MVT::v4i32);
649 return false;
650}]>;
651
Elena Demikhovskye1eda8a2015-04-30 08:38:48 +0000[diff] [blame]652def mgatherv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
653 (masked_gather node:$src1, node:$src2, node:$src3) , [{
654 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
655 return (Mgt->getIndex().getValueType() == MVT::v8i32 ||
656 Mgt->getBasePtr().getValueType() == MVT::v8i32);
657 return false;
658}]>;
659
Elena Demikhovsky6a1a3572015-06-28 10:53:29 +0000[diff] [blame]660def mgatherv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
661 (masked_gather node:$src1, node:$src2, node:$src3) , [{
662 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
663 return (Mgt->getIndex().getValueType() == MVT::v2i64 ||
664 Mgt->getBasePtr().getValueType() == MVT::v2i64);
665 return false;
666}]>;
667def mgatherv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
668 (masked_gather node:$src1, node:$src2, node:$src3) , [{
669 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
670 return (Mgt->getIndex().getValueType() == MVT::v4i64 ||
671 Mgt->getBasePtr().getValueType() == MVT::v4i64);
672 return false;
673}]>;
Elena Demikhovskye1eda8a2015-04-30 08:38:48 +0000[diff] [blame]674def mgatherv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
675 (masked_gather node:$src1, node:$src2, node:$src3) , [{
676 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
677 return (Mgt->getIndex().getValueType() == MVT::v8i64 ||
678 Mgt->getBasePtr().getValueType() == MVT::v8i64);
679 return false;
680}]>;
681def mgatherv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
682 (masked_gather node:$src1, node:$src2, node:$src3) , [{
683 if (MaskedGatherSDNode *Mgt = dyn_cast<MaskedGatherSDNode>(N))
684 return (Mgt->getIndex().getValueType() == MVT::v16i32 ||
685 Mgt->getBasePtr().getValueType() == MVT::v16i32);
686 return false;
687}]>;
688
Elena Demikhovsky30bc4ca2015-06-29 12:14:24 +0000[diff] [blame]689def mscatterv2i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
690 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
691 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
692 return (Sc->getIndex().getValueType() == MVT::v2i64 ||
693 Sc->getBasePtr().getValueType() == MVT::v2i64);
694 return false;
695}]>;
696
697def mscatterv4i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
698 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
699 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
700 return (Sc->getIndex().getValueType() == MVT::v4i32 ||
701 Sc->getBasePtr().getValueType() == MVT::v4i32);
702 return false;
703}]>;
704
705def mscatterv4i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
706 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
707 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
708 return (Sc->getIndex().getValueType() == MVT::v4i64 ||
709 Sc->getBasePtr().getValueType() == MVT::v4i64);
710 return false;
711}]>;
712
Elena Demikhovskye1eda8a2015-04-30 08:38:48 +0000[diff] [blame]713def mscatterv8i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
714 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
715 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
716 return (Sc->getIndex().getValueType() == MVT::v8i32 ||
717 Sc->getBasePtr().getValueType() == MVT::v8i32);
718 return false;
719}]>;
720
721def mscatterv8i64 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
722 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
723 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
724 return (Sc->getIndex().getValueType() == MVT::v8i64 ||
725 Sc->getBasePtr().getValueType() == MVT::v8i64);
726 return false;
727}]>;
728def mscatterv16i32 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
729 (masked_scatter node:$src1, node:$src2, node:$src3) , [{
730 if (MaskedScatterSDNode *Sc = dyn_cast<MaskedScatterSDNode>(N))
731 return (Sc->getIndex().getValueType() == MVT::v16i32 ||
732 Sc->getBasePtr().getValueType() == MVT::v16i32);
733 return false;
734}]>;
735
Bruno Cardoso Lopes160be292010-08-13 20:39:01 +0000[diff] [blame]736// 128-bit bitconvert pattern fragments
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]737def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
738def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
739def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
740def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
741def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
742def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
743
Bruno Cardoso Lopes160be292010-08-13 20:39:01 +0000[diff] [blame]744// 256-bit bitconvert pattern fragments
Craig Topper682b8502011-11-02 04:42:13 +0000[diff] [blame]745def bc_v32i8 : PatFrag<(ops node:$in), (v32i8 (bitconvert node:$in))>;
746def bc_v16i16 : PatFrag<(ops node:$in), (v16i16 (bitconvert node:$in))>;
Bruno Cardoso Lopese3acfd42010-07-21 23:53:50 +0000[diff] [blame]747def bc_v8i32 : PatFrag<(ops node:$in), (v8i32 (bitconvert node:$in))>;
Bruno Cardoso Lopes1021b4a2011-07-13 01:15:33 +0000[diff] [blame]748def bc_v4i64 : PatFrag<(ops node:$in), (v4i64 (bitconvert node:$in))>;
Elena Demikhovsky3629b4a2014-01-06 08:45:54 +0000[diff] [blame]749def bc_v8f32 : PatFrag<(ops node:$in), (v8f32 (bitconvert node:$in))>;
Bruno Cardoso Lopese3acfd42010-07-21 23:53:50 +0000[diff] [blame]750
Craig Topper8c929622013-08-16 06:07:34 +0000[diff] [blame]751// 512-bit bitconvert pattern fragments
752def bc_v16i32 : PatFrag<(ops node:$in), (v16i32 (bitconvert node:$in))>;
753def bc_v8i64 : PatFrag<(ops node:$in), (v8i64 (bitconvert node:$in))>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]754def bc_v8f64 : PatFrag<(ops node:$in), (v8f64 (bitconvert node:$in))>;
755def bc_v16f32 : PatFrag<(ops node:$in), (v16f32 (bitconvert node:$in))>;
Craig Topper8c929622013-08-16 06:07:34 +0000[diff] [blame]756
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]757def vzmovl_v2i64 : PatFrag<(ops node:$src),
758 (bitconvert (v2i64 (X86vzmovl
759 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
760def vzmovl_v4i32 : PatFrag<(ops node:$src),
761 (bitconvert (v4i32 (X86vzmovl
762 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
763
764def vzload_v2i64 : PatFrag<(ops node:$src),
765 (bitconvert (v2i64 (X86vzload node:$src)))>;
766
767
768def fp32imm0 : PatLeaf<(f32 fpimm), [{
769 return N->isExactlyValue(+0.0);
770}]>;
771
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]772def I8Imm : SDNodeXForm<imm, [{
773 // Transformation function: get the low 8 bits.
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]774 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]775}]>;
776
777def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;
Adam Nemet50b83f02014-08-14 17:13:26 +0000[diff] [blame]778def FROUND_CURRENT : ImmLeaf<i32, [{
779 return Imm == X86::STATIC_ROUNDING::CUR_DIRECTION;
780}]>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]781
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]782// BYTE_imm - Transform bit immediates into byte immediates.
783def BYTE_imm : SDNodeXForm<imm, [{
784 // Transformation function: imm >> 3
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]785 return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
David Greene03264ef2010-07-12 23:41:28 +0000[diff] [blame]786}]>;
787
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]788// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index
789// to VEXTRACTF128/VEXTRACTI128 imm.
790def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]791 return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));
David Greenec4da1102011-02-03 15:50:00 +0000[diff] [blame]792}]>;
793
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]794// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to
795// VINSERTF128/VINSERTI128 imm.
796def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]797 return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));
David Greene653f1ee2011-02-04 16:08:29 +0000[diff] [blame]798}]>;
799
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]800// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index
801// to VEXTRACTF64x4 imm.
802def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]803 return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]804}]>;
805
806// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to
807// VINSERTF64x4 imm.
808def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000[diff] [blame]809 return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]810}]>;
811
812def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),
David Greenec4da1102011-02-03 15:50:00 +0000[diff] [blame]813 (extract_subvector node:$bigvec,
814 node:$index), [{
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]815 return X86::isVEXTRACT128Index(N);
816}], EXTRACT_get_vextract128_imm>;
David Greene653f1ee2011-02-04 16:08:29 +0000[diff] [blame]817
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]818def vinsert128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
David Greene653f1ee2011-02-04 16:08:29 +0000[diff] [blame]819 node:$index),
820 (insert_subvector node:$bigvec, node:$smallvec,
821 node:$index), [{
Elena Demikhovsky67b05fc2013-07-31 11:35:14 +0000[diff] [blame]822 return X86::isVINSERT128Index(N);
823}], INSERT_get_vinsert128_imm>;
824
825
826def vextract256_extract : PatFrag<(ops node:$bigvec, node:$index),
827 (extract_subvector node:$bigvec,
828 node:$index), [{
829 return X86::isVEXTRACT256Index(N);
830}], EXTRACT_get_vextract256_imm>;
831
832def vinsert256_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
833 node:$index),
834 (insert_subvector node:$bigvec, node:$smallvec,
835 node:$index), [{
836 return X86::isVINSERT256Index(N);
837}], INSERT_get_vinsert256_imm>;
Bruno Cardoso Lopes123dff02011-07-25 23:05:25 +0000[diff] [blame]838
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]839def masked_load_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
840 (masked_load node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]841 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
842 return Load->getAlignment() >= 16;
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]843 return false;
844}]>;
845
846def masked_load_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
847 (masked_load node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]848 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
849 return Load->getAlignment() >= 32;
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]850 return false;
851}]>;
852
853def masked_load_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
854 (masked_load node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]855 if (auto *Load = dyn_cast<MaskedLoadSDNode>(N))
856 return Load->getAlignment() >= 64;
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]857 return false;
858}]>;
859
860def masked_load_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
861 (masked_load node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]862 return isa<MaskedLoadSDNode>(N);
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]863}]>;
864
Igor Breger074a64e2015-07-24 17:24:15 +0000[diff] [blame]865// masked store fragments.
866// X86mstore can't be implemented in core DAG files because some targets
867// doesn't support vector type ( llvm-tblgen will fail)
868def X86mstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
869 (masked_store node:$src1, node:$src2, node:$src3), [{
870 return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();
871}]>;
872
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]873def masked_store_aligned128 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
Igor Breger074a64e2015-07-24 17:24:15 +0000[diff] [blame]874 (X86mstore node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]875 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
876 return Store->getAlignment() >= 16;
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]877 return false;
878}]>;
879
880def masked_store_aligned256 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
Igor Breger074a64e2015-07-24 17:24:15 +0000[diff] [blame]881 (X86mstore node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]882 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
883 return Store->getAlignment() >= 32;
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]884 return false;
885}]>;
886
887def masked_store_aligned512 : PatFrag<(ops node:$src1, node:$src2, node:$src3),
Igor Breger074a64e2015-07-24 17:24:15 +0000[diff] [blame]888 (X86mstore node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]889 if (auto *Store = dyn_cast<MaskedStoreSDNode>(N))
890 return Store->getAlignment() >= 64;
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]891 return false;
892}]>;
893
894def masked_store_unaligned : PatFrag<(ops node:$src1, node:$src2, node:$src3),
Igor Breger074a64e2015-07-24 17:24:15 +0000[diff] [blame]895 (X86mstore node:$src1, node:$src2, node:$src3), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000[diff] [blame]896 return isa<MaskedStoreSDNode>(N);
Elena Demikhovskyd207f172015-03-03 15:03:35 +0000[diff] [blame]897}]>;
898
Igor Breger074a64e2015-07-24 17:24:15 +0000[diff] [blame]899// masked truncstore fragments
900// X86mtruncstore can't be implemented in core DAG files because some targets
901// doesn't support vector type ( llvm-tblgen will fail)
902def X86mtruncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),
903 (masked_store node:$src1, node:$src2, node:$src3), [{
904 return cast<MaskedStoreSDNode>(N)->isTruncatingStore();
905}]>;
906def masked_truncstorevi8 :
907 PatFrag<(ops node:$src1, node:$src2, node:$src3),
908 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
909 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
910}]>;
911def masked_truncstorevi16 :
912 PatFrag<(ops node:$src1, node:$src2, node:$src3),
913 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
914 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
915}]>;
916def masked_truncstorevi32 :
917 PatFrag<(ops node:$src1, node:$src2, node:$src3),
918 (X86mtruncstore node:$src1, node:$src2, node:$src3), [{
919 return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
920}]>;