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Chris Lattnerf3799972005-10-14 23:40:39 +00001//===- PPCInstrInfo.td - The PowerPC Instruction Set -------*- tablegen -*-===//
Misha Brukman5dfe3a92004-06-21 16:55:25 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattner4ee451d2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukman5dfe3a92004-06-21 16:55:25 +00007//
8//===----------------------------------------------------------------------===//
9//
Misha Brukman4ad7d1b2004-08-09 17:24:04 +000010// This file describes the subset of the 32-bit PowerPC instruction set, as used
11// by the PowerPC instruction selector.
Misha Brukman5dfe3a92004-06-21 16:55:25 +000012//
13//===----------------------------------------------------------------------===//
14
Chris Lattnerf3799972005-10-14 23:40:39 +000015include "PPCInstrFormats.td"
Misha Brukman5dfe3a92004-06-21 16:55:25 +000016
Chris Lattnere6115b32005-10-25 20:41:46 +000017//===----------------------------------------------------------------------===//
Chris Lattner51269842006-03-01 05:50:56 +000018// PowerPC specific type constraints.
19//
20def SDT_PPCstfiwx : SDTypeProfile<0, 2, [ // stfiwx
21 SDTCisVT<0, f64>, SDTCisPtrTy<1>
22]>;
Bill Wendlingc69107c2007-11-13 09:19:02 +000023def SDT_PPCCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
24def SDT_PPCCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
25 SDTCisVT<1, i32> ]>;
Chris Lattnerf1d0b2b2006-03-20 01:53:53 +000026def SDT_PPCvperm : SDTypeProfile<1, 3, [
27 SDTCisVT<3, v16i8>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
28]>;
29
Chris Lattnera17b1552006-03-31 05:13:27 +000030def SDT_PPCvcmp : SDTypeProfile<1, 3, [
Chris Lattner6d92cad2006-03-26 10:06:40 +000031 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>
32]>;
33
Chris Lattner90564f22006-04-18 17:59:36 +000034def SDT_PPCcondbr : SDTypeProfile<0, 3, [
Chris Lattner18258c62006-11-17 22:37:34 +000035 SDTCisVT<0, i32>, SDTCisVT<2, OtherVT>
Chris Lattner90564f22006-04-18 17:59:36 +000036]>;
37
Chris Lattnerd9989382006-07-10 20:56:58 +000038def SDT_PPClbrx : SDTypeProfile<1, 3, [
39 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
40]>;
41def SDT_PPCstbrx : SDTypeProfile<0, 4, [
42 SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
43]>;
44
Evan Cheng8608f2e2008-04-19 02:30:38 +000045def SDT_PPClarx : SDTypeProfile<1, 2, [
46 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
Evan Cheng54fc97d2008-04-19 01:30:48 +000047]>;
Evan Cheng8608f2e2008-04-19 02:30:38 +000048def SDT_PPCstcx : SDTypeProfile<0, 3, [
49 SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
Evan Cheng54fc97d2008-04-19 01:30:48 +000050]>;
51def SDT_PPCcmp_unres : SDTypeProfile<0, 3, [
Evan Cheng8608f2e2008-04-19 02:30:38 +000052 SDTCisSameAs<0, 1>, SDTCisInt<1>, SDTCisVT<2, i32>
Evan Cheng54fc97d2008-04-19 01:30:48 +000053]>;
54
Chris Lattner51269842006-03-01 05:50:56 +000055//===----------------------------------------------------------------------===//
Chris Lattnere6115b32005-10-25 20:41:46 +000056// PowerPC specific DAG Nodes.
57//
58
59def PPCfcfid : SDNode<"PPCISD::FCFID" , SDTFPUnaryOp, []>;
60def PPCfctidz : SDNode<"PPCISD::FCTIDZ", SDTFPUnaryOp, []>;
61def PPCfctiwz : SDNode<"PPCISD::FCTIWZ", SDTFPUnaryOp, []>;
Chris Lattnerc8478d82008-01-06 06:44:58 +000062def PPCstfiwx : SDNode<"PPCISD::STFIWX", SDT_PPCstfiwx,
63 [SDNPHasChain, SDNPMayStore]>;
Chris Lattnere6115b32005-10-25 20:41:46 +000064
Dale Johannesen6eaeff22007-10-10 01:01:31 +000065// This sequence is used for long double->int conversions. It changes the
66// bits in the FPSCR which is not modelled.
67def PPCmffs : SDNode<"PPCISD::MFFS", SDTypeProfile<1, 0, [SDTCisVT<0, f64>]>,
68 [SDNPOutFlag]>;
69def PPCmtfsb0 : SDNode<"PPCISD::MTFSB0", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
70 [SDNPInFlag, SDNPOutFlag]>;
71def PPCmtfsb1 : SDNode<"PPCISD::MTFSB1", SDTypeProfile<0, 1, [SDTCisInt<0>]>,
72 [SDNPInFlag, SDNPOutFlag]>;
73def PPCfaddrtz: SDNode<"PPCISD::FADDRTZ", SDTFPBinOp,
74 [SDNPInFlag, SDNPOutFlag]>;
75def PPCmtfsf : SDNode<"PPCISD::MTFSF", SDTypeProfile<1, 3,
76 [SDTCisVT<0, f64>, SDTCisInt<1>, SDTCisVT<2, f64>,
77 SDTCisVT<3, f64>]>,
78 [SDNPInFlag]>;
79
Chris Lattner9c73f092005-10-25 20:55:47 +000080def PPCfsel : SDNode<"PPCISD::FSEL",
81 // Type constraint for fsel.
82 SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,
83 SDTCisFP<0>, SDTCisVT<1, f64>]>, []>;
Chris Lattner47f01f12005-09-08 19:50:41 +000084
Nate Begeman993aeb22005-12-13 22:55:22 +000085def PPChi : SDNode<"PPCISD::Hi", SDTIntBinOp, []>;
86def PPClo : SDNode<"PPCISD::Lo", SDTIntBinOp, []>;
87def PPCvmaddfp : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
88def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
Chris Lattner860e8862005-11-17 07:30:41 +000089
Chris Lattnerf1d0b2b2006-03-20 01:53:53 +000090def PPCvperm : SDNode<"PPCISD::VPERM", SDT_PPCvperm, []>;
Chris Lattnerb2177b92006-03-19 06:55:52 +000091
Chris Lattner4172b102005-12-06 02:10:38 +000092// These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
93// amounts. These nodes are generated by the multi-precision shift code.
Chris Lattneraf8ee842008-03-07 20:18:24 +000094def PPCsrl : SDNode<"PPCISD::SRL" , SDTIntShiftOp>;
95def PPCsra : SDNode<"PPCISD::SRA" , SDTIntShiftOp>;
96def PPCshl : SDNode<"PPCISD::SHL" , SDTIntShiftOp>;
Chris Lattner4172b102005-12-06 02:10:38 +000097
Chris Lattnerecfe55e2006-03-22 05:30:33 +000098def PPCextsw_32 : SDNode<"PPCISD::EXTSW_32" , SDTIntUnaryOp>;
Chris Lattnerc8478d82008-01-06 06:44:58 +000099def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore,
100 [SDNPHasChain, SDNPMayStore]>;
Chris Lattnerecfe55e2006-03-22 05:30:33 +0000101
Chris Lattner937a79d2005-12-04 19:01:59 +0000102// These are target-independent nodes, but have target-specific formats.
Bill Wendlingc69107c2007-11-13 09:19:02 +0000103def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeqStart,
Evan Chengbb7b8442006-08-11 09:03:33 +0000104 [SDNPHasChain, SDNPOutFlag]>;
Bill Wendlingc69107c2007-11-13 09:19:02 +0000105def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeqEnd,
Bill Wendling0f8d9c02007-11-13 00:44:25 +0000106 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Chris Lattner937a79d2005-12-04 19:01:59 +0000107
Chris Lattner2e6b77d2006-06-27 18:36:44 +0000108def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
Nicolas Geoffray63f8fb12007-02-27 13:01:19 +0000109def PPCcall_Macho : SDNode<"PPCISD::CALL_Macho", SDT_PPCCall,
Chris Lattner9f0bc652007-02-25 05:34:32 +0000110 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Nicolas Geoffray63f8fb12007-02-27 13:01:19 +0000111def PPCcall_ELF : SDNode<"PPCISD::CALL_ELF", SDT_PPCCall,
Chris Lattner9a2a4972006-05-17 06:01:33 +0000112 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Chris Lattnerc703a8f2006-05-17 19:00:46 +0000113def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
114 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Chris Lattner48be23c2008-01-15 22:02:54 +0000115def PPCbctrl_Macho : SDNode<"PPCISD::BCTRL_Macho", SDTNone,
Bill Wendling6ef781f2008-02-27 06:33:05 +0000116 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Chris Lattner9f0bc652007-02-25 05:34:32 +0000117
Chris Lattner48be23c2008-01-15 22:02:54 +0000118def PPCbctrl_ELF : SDNode<"PPCISD::BCTRL_ELF", SDTNone,
Bill Wendling6ef781f2008-02-27 06:33:05 +0000119 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
Chris Lattner9a2a4972006-05-17 06:01:33 +0000120
Chris Lattner48be23c2008-01-15 22:02:54 +0000121def retflag : SDNode<"PPCISD::RET_FLAG", SDTNone,
Bill Wendling6ef781f2008-02-27 06:33:05 +0000122 [SDNPHasChain, SDNPOptInFlag]>;
Nate Begeman9e4dd9d2005-12-20 00:26:01 +0000123
Chris Lattnera17b1552006-03-31 05:13:27 +0000124def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
125def PPCvcmp_o : SDNode<"PPCISD::VCMPo", SDT_PPCvcmp, [SDNPOutFlag]>;
Chris Lattner6d92cad2006-03-26 10:06:40 +0000126
Chris Lattner90564f22006-04-18 17:59:36 +0000127def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
128 [SDNPHasChain, SDNPOptInFlag]>;
129
Chris Lattner9b37aaf2008-01-10 05:12:37 +0000130def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx,
131 [SDNPHasChain, SDNPMayLoad]>;
Chris Lattnerc8478d82008-01-06 06:44:58 +0000132def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx,
133 [SDNPHasChain, SDNPMayStore]>;
Chris Lattnerd9989382006-07-10 20:56:58 +0000134
Evan Cheng8608f2e2008-04-19 02:30:38 +0000135def PPClarx : SDNode<"PPCISD::LARX", SDT_PPClarx,
136 [SDNPHasChain, SDNPMayLoad]>;
137def PPCstcx : SDNode<"PPCISD::STCX", SDT_PPCstcx,
138 [SDNPHasChain, SDNPMayStore]>;
Evan Cheng54fc97d2008-04-19 01:30:48 +0000139def PPCcmp_unres : SDNode<"PPCISD::CMP_UNRESERVE", SDT_PPCcmp_unres,
140 [SDNPHasChain]>;
141
Jim Laskey2f616bf2006-11-16 22:43:37 +0000142// Instructions to support dynamic alloca.
143def SDTDynOp : SDTypeProfile<1, 2, []>;
144def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
145
Chris Lattner47f01f12005-09-08 19:50:41 +0000146//===----------------------------------------------------------------------===//
Chris Lattner2eb25172005-09-09 00:39:56 +0000147// PowerPC specific transformation functions and pattern fragments.
148//
Nate Begeman8d948322005-10-19 01:12:32 +0000149
Nate Begeman2d5aff72005-10-19 18:42:01 +0000150def SHL32 : SDNodeXForm<imm, [{
151 // Transformation function: 31 - imm
152 return getI32Imm(31 - N->getValue());
153}]>;
154
Nate Begeman2d5aff72005-10-19 18:42:01 +0000155def SRL32 : SDNodeXForm<imm, [{
156 // Transformation function: 32 - imm
157 return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
158}]>;
159
Chris Lattner2eb25172005-09-09 00:39:56 +0000160def LO16 : SDNodeXForm<imm, [{
161 // Transformation function: get the low 16 bits.
162 return getI32Imm((unsigned short)N->getValue());
163}]>;
164
165def HI16 : SDNodeXForm<imm, [{
166 // Transformation function: shift the immediate value down into the low bits.
167 return getI32Imm((unsigned)N->getValue() >> 16);
168}]>;
Chris Lattner3e63ead2005-09-08 17:33:10 +0000169
Chris Lattner79d0e9f2005-09-28 23:07:13 +0000170def HA16 : SDNodeXForm<imm, [{
171 // Transformation function: shift the immediate value down into the low bits.
172 signed int Val = N->getValue();
173 return getI32Imm((Val - (signed short)Val) >> 16);
174}]>;
Nate Begemanf42f1332006-09-22 05:01:56 +0000175def MB : SDNodeXForm<imm, [{
176 // Transformation function: get the start bit of a mask
177 unsigned mb, me;
178 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
179 return getI32Imm(mb);
180}]>;
Chris Lattner79d0e9f2005-09-28 23:07:13 +0000181
Nate Begemanf42f1332006-09-22 05:01:56 +0000182def ME : SDNodeXForm<imm, [{
183 // Transformation function: get the end bit of a mask
184 unsigned mb, me;
185 (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
186 return getI32Imm(me);
187}]>;
188def maskimm32 : PatLeaf<(imm), [{
189 // maskImm predicate - True if immediate is a run of ones.
190 unsigned mb, me;
191 if (N->getValueType(0) == MVT::i32)
192 return isRunOfOnes((unsigned)N->getValue(), mb, me);
193 else
194 return false;
195}]>;
Chris Lattner79d0e9f2005-09-28 23:07:13 +0000196
Chris Lattner3e63ead2005-09-08 17:33:10 +0000197def immSExt16 : PatLeaf<(imm), [{
198 // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
199 // field. Used by instructions like 'addi'.
Chris Lattner7f7b346e2006-06-20 23:21:20 +0000200 if (N->getValueType(0) == MVT::i32)
201 return (int32_t)N->getValue() == (short)N->getValue();
202 else
203 return (int64_t)N->getValue() == (short)N->getValue();
Chris Lattner3e63ead2005-09-08 17:33:10 +0000204}]>;
Chris Lattnerbfde0802005-09-08 17:40:49 +0000205def immZExt16 : PatLeaf<(imm), [{
206 // immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
207 // field. Used by instructions like 'ori'.
Chris Lattner7f7b346e2006-06-20 23:21:20 +0000208 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
Chris Lattner2eb25172005-09-09 00:39:56 +0000209}], LO16>;
210
Chris Lattner0ea70b22006-06-20 22:34:10 +0000211// imm16Shifted* - These match immediates where the low 16-bits are zero. There
212// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
213// identical in 32-bit mode, but in 64-bit mode, they return true if the
214// immediate fits into a sign/zero extended 32-bit immediate (with the low bits
215// clear).
216def imm16ShiftedZExt : PatLeaf<(imm), [{
217 // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
218 // immediate are set. Used by instructions like 'xoris'.
219 return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
220}], HI16>;
221
222def imm16ShiftedSExt : PatLeaf<(imm), [{
223 // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
224 // immediate are set. Used by instructions like 'addis'. Identical to
225 // imm16ShiftedZExt in 32-bit mode.
Chris Lattnerdd583432006-06-20 21:39:30 +0000226 if (N->getValue() & 0xFFFF) return false;
227 if (N->getValueType(0) == MVT::i32)
228 return true;
229 // For 64-bit, make sure it is sext right.
230 return N->getValue() == (uint64_t)(int)N->getValue();
Chris Lattner2eb25172005-09-09 00:39:56 +0000231}], HI16>;
Chris Lattner3e63ead2005-09-08 17:33:10 +0000232
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000233
Chris Lattner47f01f12005-09-08 19:50:41 +0000234//===----------------------------------------------------------------------===//
235// PowerPC Flag Definitions.
236
Chris Lattner0bdc6f12005-04-19 04:32:54 +0000237class isPPC64 { bit PPC64 = 1; }
Chris Lattner883059f2005-04-19 05:15:18 +0000238class isDOT {
239 list<Register> Defs = [CR0];
240 bit RC = 1;
241}
Chris Lattner0bdc6f12005-04-19 04:32:54 +0000242
Chris Lattner302bf9c2006-11-08 02:13:12 +0000243class RegConstraint<string C> {
244 string Constraints = C;
245}
Chris Lattner8e28b5c2006-11-15 23:24:18 +0000246class NoEncode<string E> {
247 string DisableEncoding = E;
248}
Chris Lattner47f01f12005-09-08 19:50:41 +0000249
250
251//===----------------------------------------------------------------------===//
252// PowerPC Operand Definitions.
Chris Lattner7bb424f2004-08-14 23:27:29 +0000253
Chris Lattner9c61dcf2006-03-25 06:12:06 +0000254def s5imm : Operand<i32> {
255 let PrintMethod = "printS5ImmOperand";
256}
Chris Lattner4345a4a2005-09-14 20:53:05 +0000257def u5imm : Operand<i32> {
Nate Begemanc3306122004-08-21 05:56:39 +0000258 let PrintMethod = "printU5ImmOperand";
259}
Chris Lattner4345a4a2005-09-14 20:53:05 +0000260def u6imm : Operand<i32> {
Nate Begeman07aada82004-08-30 02:28:06 +0000261 let PrintMethod = "printU6ImmOperand";
262}
Chris Lattner4345a4a2005-09-14 20:53:05 +0000263def s16imm : Operand<i32> {
Nate Begemaned428532004-09-04 05:00:00 +0000264 let PrintMethod = "printS16ImmOperand";
265}
Chris Lattner4345a4a2005-09-14 20:53:05 +0000266def u16imm : Operand<i32> {
Chris Lattner97b2a2e2004-08-15 05:20:16 +0000267 let PrintMethod = "printU16ImmOperand";
268}
Chris Lattner841d12d2005-10-18 16:51:22 +0000269def s16immX4 : Operand<i32> { // Multiply imm by 4 before printing.
270 let PrintMethod = "printS16X4ImmOperand";
271}
Chris Lattner1e484782005-12-04 18:42:54 +0000272def target : Operand<OtherVT> {
Nate Begemanb7a8f2c2004-09-02 08:13:00 +0000273 let PrintMethod = "printBranchOperand";
274}
Chris Lattner059ca0f2006-06-16 21:01:35 +0000275def calltarget : Operand<iPTR> {
Chris Lattner3e7f86a2005-11-17 19:16:08 +0000276 let PrintMethod = "printCallOperand";
277}
Chris Lattner059ca0f2006-06-16 21:01:35 +0000278def aaddr : Operand<iPTR> {
Nate Begeman422b0ce2005-11-16 00:48:01 +0000279 let PrintMethod = "printAbsAddrOperand";
280}
Chris Lattner059ca0f2006-06-16 21:01:35 +0000281def piclabel: Operand<iPTR> {
Nate Begemanb7a8f2c2004-09-02 08:13:00 +0000282 let PrintMethod = "printPICLabel";
283}
Nate Begemaned428532004-09-04 05:00:00 +0000284def symbolHi: Operand<i32> {
285 let PrintMethod = "printSymbolHi";
286}
287def symbolLo: Operand<i32> {
288 let PrintMethod = "printSymbolLo";
289}
Nate Begemanadeb43d2005-07-20 22:42:00 +0000290def crbitm: Operand<i8> {
291 let PrintMethod = "printcrbitm";
292}
Nate Begeman7fd1edd2005-12-19 23:25:09 +0000293// Address operands
Chris Lattner059ca0f2006-06-16 21:01:35 +0000294def memri : Operand<iPTR> {
Nate Begeman7fd1edd2005-12-19 23:25:09 +0000295 let PrintMethod = "printMemRegImm";
Chris Lattnerf8e07f42006-11-15 02:43:19 +0000296 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
Nate Begeman7fd1edd2005-12-19 23:25:09 +0000297}
Chris Lattner059ca0f2006-06-16 21:01:35 +0000298def memrr : Operand<iPTR> {
Nate Begeman7fd1edd2005-12-19 23:25:09 +0000299 let PrintMethod = "printMemRegReg";
Chris Lattner66d7ebb2006-06-16 21:29:03 +0000300 let MIOperandInfo = (ops ptr_rc, ptr_rc);
Nate Begeman7fd1edd2005-12-19 23:25:09 +0000301}
Chris Lattner059ca0f2006-06-16 21:01:35 +0000302def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
Chris Lattnerecfe55e2006-03-22 05:30:33 +0000303 let PrintMethod = "printMemRegImmShifted";
Chris Lattner0851b4f2006-11-15 19:55:13 +0000304 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg);
Chris Lattnerecfe55e2006-03-22 05:30:33 +0000305}
Nate Begeman7fd1edd2005-12-19 23:25:09 +0000306
Chris Lattner6fc40072006-11-04 05:42:48 +0000307// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
Chris Lattneraf53a872006-11-04 05:27:39 +0000308// that doesn't matter.
Evan Cheng06aae672007-07-06 23:22:46 +0000309def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
Nate Begemanba8d51c2008-02-13 02:58:33 +0000310 (ops (i32 20), (i32 zero_reg))> {
Chris Lattneraf53a872006-11-04 05:27:39 +0000311 let PrintMethod = "printPredicateOperand";
312}
Chris Lattner0638b262006-11-03 23:53:25 +0000313
Chris Lattnera613d262006-01-12 02:05:36 +0000314// Define PowerPC specific addressing mode.
Evan Chengaf9db752006-10-11 21:03:53 +0000315def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
316def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
317def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
318def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
Chris Lattner97b2a2e2004-08-15 05:20:16 +0000319
Chris Lattner74531e42006-11-16 00:41:37 +0000320/// This is just the offset part of iaddr, used for preinc.
321def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
Chris Lattnerf8e07f42006-11-15 02:43:19 +0000322
Evan Cheng8c75ef92005-12-14 22:07:12 +0000323//===----------------------------------------------------------------------===//
324// PowerPC Instruction Predicate Definitions.
Evan Cheng6a3bfd92005-12-20 20:08:53 +0000325def FPContractions : Predicate<"!NoExcessFPPrecision">;
Evan Cheng152b7e12007-10-23 06:42:42 +0000326def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
327def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
Chris Lattner47f01f12005-09-08 19:50:41 +0000328
Chris Lattner6a5339b2006-11-14 18:44:47 +0000329
Chris Lattner47f01f12005-09-08 19:50:41 +0000330//===----------------------------------------------------------------------===//
331// PowerPC Instruction Definitions.
332
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000333// Pseudo-instructions:
Chris Lattner47f01f12005-09-08 19:50:41 +0000334
Chris Lattner88d211f2006-03-12 09:13:49 +0000335let hasCtrlDep = 1 in {
Evan Cheng071a2792007-09-11 19:55:27 +0000336let Defs = [R1], Uses = [R1] in {
Evan Cheng64d80e32007-07-19 01:14:50 +0000337def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt),
Chris Lattner54689662006-09-27 02:55:21 +0000338 "${:comment} ADJCALLSTACKDOWN",
Evan Cheng071a2792007-09-11 19:55:27 +0000339 [(callseq_start imm:$amt)]>;
Bill Wendling0f8d9c02007-11-13 00:44:25 +0000340def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2),
Chris Lattner54689662006-09-27 02:55:21 +0000341 "${:comment} ADJCALLSTACKUP",
Bill Wendling0f8d9c02007-11-13 00:44:25 +0000342 [(callseq_end imm:$amt1, imm:$amt2)]>;
Evan Cheng071a2792007-09-11 19:55:27 +0000343}
Chris Lattner1877ec92006-03-13 21:52:10 +0000344
Evan Cheng64d80e32007-07-19 01:14:50 +0000345def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
Chris Lattner1877ec92006-03-13 21:52:10 +0000346 "UPDATE_VRSAVE $rD, $rS", []>;
Nate Begemanb816f022004-10-07 22:30:03 +0000347}
Jim Laskey2f616bf2006-11-16 22:43:37 +0000348
Evan Cheng071a2792007-09-11 19:55:27 +0000349let Defs = [R1], Uses = [R1] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000350def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi),
Jim Laskey2f616bf2006-11-16 22:43:37 +0000351 "${:comment} DYNALLOC $result, $negsize, $fpsi",
352 [(set GPRC:$result,
Evan Cheng071a2792007-09-11 19:55:27 +0000353 (PPCdynalloc GPRC:$negsize, iaddr:$fpsi))]>;
Jim Laskey2f616bf2006-11-16 22:43:37 +0000354
Chris Lattner8a2d3ca2005-08-26 21:23:58 +0000355// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
356// scheduler into a branch sequence.
Chris Lattner88d211f2006-03-12 09:13:49 +0000357let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
358 PPC970_Single = 1 in {
Evan Cheng64d80e32007-07-19 01:14:50 +0000359 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
Chris Lattner54689662006-09-27 02:55:21 +0000360 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
361 []>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000362 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
Chris Lattner54689662006-09-27 02:55:21 +0000363 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
364 []>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000365 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
Chris Lattner54689662006-09-27 02:55:21 +0000366 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
367 []>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000368 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
Chris Lattner54689662006-09-27 02:55:21 +0000369 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
370 []>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000371 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
Chris Lattner54689662006-09-27 02:55:21 +0000372 i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
373 []>;
Chris Lattner8a2d3ca2005-08-26 21:23:58 +0000374}
375
Bill Wendling7194aaf2008-03-03 22:19:16 +0000376// SPILL_CR - Indicate that we're dumping the CR register, so we'll need to
377// scavenge a register for it.
378def SPILL_CR : Pseudo<(outs), (ins GPRC:$cond, memri:$F),
379 "${:comment} SPILL_CR $cond $F", []>;
380
Evan Chengffbacca2007-07-21 00:34:19 +0000381let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
Evan Cheng6da8d992006-01-09 18:28:21 +0000382 let isReturn = 1 in
Evan Cheng64d80e32007-07-19 01:14:50 +0000383 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
Chris Lattner6fc40072006-11-04 05:42:48 +0000384 "b${p:cc}lr ${p:reg}", BrB,
385 [(retflag)]>;
Owen Anderson20ab2902007-11-12 07:39:39 +0000386 let isBranch = 1, isIndirectBranch = 1 in
387 def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>;
Chris Lattner47f01f12005-09-08 19:50:41 +0000388}
389
Chris Lattner7a823bd2005-02-15 20:26:49 +0000390let Defs = [LR] in
Evan Cheng64d80e32007-07-19 01:14:50 +0000391 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
Chris Lattner88d211f2006-03-12 09:13:49 +0000392 PPC970_Unit_BRU;
Misha Brukman5dfe3a92004-06-21 16:55:25 +0000393
Evan Chengffbacca2007-07-21 00:34:19 +0000394let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
Chris Lattner594f4c62006-10-13 19:10:34 +0000395 let isBarrier = 1 in {
Evan Cheng64d80e32007-07-19 01:14:50 +0000396 def B : IForm<18, 0, 0, (outs), (ins target:$dst),
Chris Lattner1e484782005-12-04 18:42:54 +0000397 "b $dst", BrB,
398 [(br bb:$dst)]>;
Chris Lattner594f4c62006-10-13 19:10:34 +0000399 }
Chris Lattnerdd998852004-11-22 23:07:01 +0000400
Chris Lattner18258c62006-11-17 22:37:34 +0000401 // BCC represents an arbitrary conditional branch on a predicate.
402 // FIXME: should be able to write a pattern for PPCcondbranch, but can't use
403 // a two-value operand where a dag node expects two operands. :(
Evan Cheng64d80e32007-07-19 01:14:50 +0000404 def BCC : BForm<16, 0, 0, (outs), (ins pred:$cond, target:$dst),
Chris Lattner54e853b2006-11-18 00:32:03 +0000405 "b${cond:cc} ${cond:reg}, $dst"
406 /*[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]*/>;
Misha Brukmanb2edb442004-06-28 18:23:35 +0000407}
408
Chris Lattner9f0bc652007-02-25 05:34:32 +0000409// Macho ABI Calls.
Evan Chengffbacca2007-07-21 00:34:19 +0000410let isCall = 1, PPC970_Unit = 7,
Misha Brukman5fa2b022004-06-29 23:37:36 +0000411 // All calls clobber the non-callee saved registers...
Misha Brukmanc661c302004-06-30 22:00:45 +0000412 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
413 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
Chris Lattnerbe80fc82006-03-16 22:35:59 +0000414 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
Chris Lattner1f24df62005-08-22 22:32:13 +0000415 LR,CTR,
Nicolas Geoffray0404cd92008-03-10 14:12:10 +0000416 CR0,CR1,CR5,CR6,CR7,
417 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
418 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
Misha Brukmanc661c302004-06-30 22:00:45 +0000419 // Convenient aliases for call instructions
Chris Lattner9f0bc652007-02-25 05:34:32 +0000420 def BL_Macho : IForm<18, 0, 1,
Evan Cheng64d80e32007-07-19 01:14:50 +0000421 (outs), (ins calltarget:$func, variable_ops),
Chris Lattner9f0bc652007-02-25 05:34:32 +0000422 "bl $func", BrB, []>; // See Pat patterns below.
423 def BLA_Macho : IForm<18, 1, 1,
Evan Cheng64d80e32007-07-19 01:14:50 +0000424 (outs), (ins aaddr:$func, variable_ops),
Chris Lattner9f0bc652007-02-25 05:34:32 +0000425 "bla $func", BrB, [(PPCcall_Macho (i32 imm:$func))]>;
426 def BCTRL_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
Evan Cheng64d80e32007-07-19 01:14:50 +0000427 (outs), (ins variable_ops),
Chris Lattner9f0bc652007-02-25 05:34:32 +0000428 "bctrl", BrB,
Evan Cheng152b7e12007-10-23 06:42:42 +0000429 [(PPCbctrl_Macho)]>, Requires<[In32BitMode]>;
Chris Lattner9f0bc652007-02-25 05:34:32 +0000430}
431
432// ELF ABI Calls.
Evan Chengffbacca2007-07-21 00:34:19 +0000433let isCall = 1, PPC970_Unit = 7,
Chris Lattner9f0bc652007-02-25 05:34:32 +0000434 // All calls clobber the non-callee saved registers...
435 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
Nicolas Geoffrayef3c0302007-04-03 10:27:07 +0000436 F0,F1,F2,F3,F4,F5,F6,F7,F8,
Chris Lattner9f0bc652007-02-25 05:34:32 +0000437 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
438 LR,CTR,
Nicolas Geoffray0404cd92008-03-10 14:12:10 +0000439 CR0,CR1,CR5,CR6,CR7,
440 CR0LT,CR0GT,CR0EQ,CR0UN,CR1LT,CR1GT,CR1EQ,CR1UN,CR5LT,CR5GT,CR5EQ,
441 CR5UN,CR6LT,CR6GT,CR6EQ,CR6UN,CR7LT,CR7GT,CR7EQ,CR7UN] in {
Chris Lattner9f0bc652007-02-25 05:34:32 +0000442 // Convenient aliases for call instructions
443 def BL_ELF : IForm<18, 0, 1,
Evan Cheng64d80e32007-07-19 01:14:50 +0000444 (outs), (ins calltarget:$func, variable_ops),
Chris Lattner9f0bc652007-02-25 05:34:32 +0000445 "bl $func", BrB, []>; // See Pat patterns below.
446 def BLA_ELF : IForm<18, 1, 1,
Evan Cheng64d80e32007-07-19 01:14:50 +0000447 (outs), (ins aaddr:$func, variable_ops),
Chris Lattner9f0bc652007-02-25 05:34:32 +0000448 "bla $func", BrB,
Nicolas Geoffray63f8fb12007-02-27 13:01:19 +0000449 [(PPCcall_ELF (i32 imm:$func))]>;
Chris Lattner9f0bc652007-02-25 05:34:32 +0000450 def BCTRL_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
Evan Cheng64d80e32007-07-19 01:14:50 +0000451 (outs), (ins variable_ops),
Chris Lattner9f0bc652007-02-25 05:34:32 +0000452 "bctrl", BrB,
Evan Cheng152b7e12007-10-23 06:42:42 +0000453 [(PPCbctrl_ELF)]>, Requires<[In32BitMode]>;
Misha Brukman5fa2b022004-06-29 23:37:36 +0000454}
455
Chris Lattner001db452006-06-06 21:29:23 +0000456// DCB* instructions.
Evan Cheng64d80e32007-07-19 01:14:50 +0000457def DCBA : DCB_Form<758, 0, (outs), (ins memrr:$dst),
Chris Lattnere90c5372006-10-24 01:08:42 +0000458 "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
459 PPC970_DGroup_Single;
Evan Cheng64d80e32007-07-19 01:14:50 +0000460def DCBF : DCB_Form<86, 0, (outs), (ins memrr:$dst),
Chris Lattnere90c5372006-10-24 01:08:42 +0000461 "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
462 PPC970_DGroup_Single;
Evan Cheng64d80e32007-07-19 01:14:50 +0000463def DCBI : DCB_Form<470, 0, (outs), (ins memrr:$dst),
Chris Lattnere90c5372006-10-24 01:08:42 +0000464 "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
465 PPC970_DGroup_Single;
Evan Cheng64d80e32007-07-19 01:14:50 +0000466def DCBST : DCB_Form<54, 0, (outs), (ins memrr:$dst),
Chris Lattnere90c5372006-10-24 01:08:42 +0000467 "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
468 PPC970_DGroup_Single;
Evan Cheng64d80e32007-07-19 01:14:50 +0000469def DCBT : DCB_Form<278, 0, (outs), (ins memrr:$dst),
Chris Lattnere90c5372006-10-24 01:08:42 +0000470 "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
471 PPC970_DGroup_Single;
Evan Cheng64d80e32007-07-19 01:14:50 +0000472def DCBTST : DCB_Form<246, 0, (outs), (ins memrr:$dst),
Chris Lattnere90c5372006-10-24 01:08:42 +0000473 "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
474 PPC970_DGroup_Single;
Evan Cheng64d80e32007-07-19 01:14:50 +0000475def DCBZ : DCB_Form<1014, 0, (outs), (ins memrr:$dst),
Chris Lattnere90c5372006-10-24 01:08:42 +0000476 "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
477 PPC970_DGroup_Single;
Evan Cheng64d80e32007-07-19 01:14:50 +0000478def DCBZL : DCB_Form<1014, 1, (outs), (ins memrr:$dst),
Chris Lattnere90c5372006-10-24 01:08:42 +0000479 "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
480 PPC970_DGroup_Single;
Chris Lattner26e552b2006-11-14 19:19:53 +0000481
Evan Cheng54fc97d2008-04-19 01:30:48 +0000482// Atomic operations.
483def LWARX : Pseudo<(outs GPRC:$rD), (ins memrr:$ptr, i32imm:$label),
484 "\nLa${label}_entry:\n\tlwarx $rD, $ptr",
Evan Cheng8608f2e2008-04-19 02:30:38 +0000485 [(set GPRC:$rD, (PPClarx xoaddr:$ptr, imm:$label))]>;
Evan Cheng54fc97d2008-04-19 01:30:48 +0000486
487let Defs = [CR0] in {
488def STWCX : Pseudo<(outs), (ins GPRC:$rS, memrr:$dst, i32imm:$label),
Evan Cheng8608f2e2008-04-19 02:30:38 +0000489 "stwcx. $rS, $dst\n\tbne- La${label}_entry\nLa${label}_exit:",
490 [(PPCstcx GPRC:$rS, xoaddr:$dst, imm:$label)]>;
Evan Cheng54fc97d2008-04-19 01:30:48 +0000491
492def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm:$label),
493 "cmpw $rA, $rB\n\tbne- La${label}_exit",
494 [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm:$label)]>;
495def CMP_UNRESwi : Pseudo<(outs), (ins GPRC:$rA, s16imm:$imm, i32imm:$label),
496 "cmpwi $rA, $imm\n\tbne- La${label}_exit",
Evan Cheng8608f2e2008-04-19 02:30:38 +0000497 [(PPCcmp_unres GPRC:$rA, immSExt16:$imm, imm:$label)]>;
Evan Cheng54fc97d2008-04-19 01:30:48 +0000498}
499
Chris Lattner26e552b2006-11-14 19:19:53 +0000500//===----------------------------------------------------------------------===//
501// PPC32 Load Instructions.
Nate Begeman07aada82004-08-30 02:28:06 +0000502//
Chris Lattner26e552b2006-11-14 19:19:53 +0000503
Chris Lattnerf8e07f42006-11-15 02:43:19 +0000504// Unindexed (r+i) Loads.
Chris Lattner834f1ce2008-01-06 23:38:27 +0000505let isSimpleLoad = 1, PPC970_Unit = 2 in {
Evan Cheng64d80e32007-07-19 01:14:50 +0000506def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
Nate Begeman7fd1edd2005-12-19 23:25:09 +0000507 "lbz $rD, $src", LdStGeneral,
Evan Cheng466685d2006-10-09 20:57:25 +0000508 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000509def LHA : DForm_1<42, (outs GPRC:$rD), (ins memri:$src),
Nate Begeman7fd1edd2005-12-19 23:25:09 +0000510 "lha $rD, $src", LdStLHA,
Evan Cheng466685d2006-10-09 20:57:25 +0000511 [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
Chris Lattnerfd977342006-03-13 05:15:10 +0000512 PPC970_DGroup_Cracked;
Evan Cheng64d80e32007-07-19 01:14:50 +0000513def LHZ : DForm_1<40, (outs GPRC:$rD), (ins memri:$src),
Nate Begeman7fd1edd2005-12-19 23:25:09 +0000514 "lhz $rD, $src", LdStGeneral,
Evan Cheng466685d2006-10-09 20:57:25 +0000515 [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000516def LWZ : DForm_1<32, (outs GPRC:$rD), (ins memri:$src),
Nate Begeman7fd1edd2005-12-19 23:25:09 +0000517 "lwz $rD, $src", LdStGeneral,
518 [(set GPRC:$rD, (load iaddr:$src))]>;
Chris Lattner302bf9c2006-11-08 02:13:12 +0000519
Evan Cheng64d80e32007-07-19 01:14:50 +0000520def LFS : DForm_1<48, (outs F4RC:$rD), (ins memri:$src),
Chris Lattner4eab7142006-11-10 02:08:47 +0000521 "lfs $rD, $src", LdStLFDU,
522 [(set F4RC:$rD, (load iaddr:$src))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000523def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src),
Chris Lattner4eab7142006-11-10 02:08:47 +0000524 "lfd $rD, $src", LdStLFD,
525 [(set F8RC:$rD, (load iaddr:$src))]>;
526
Chris Lattner4eab7142006-11-10 02:08:47 +0000527
Chris Lattnerf8e07f42006-11-15 02:43:19 +0000528// Unindexed (r+i) Loads with Update (preinc).
Evan Chengcaf778a2007-08-01 23:07:38 +0000529def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
Chris Lattnerf8e07f42006-11-15 02:43:19 +0000530 "lbzu $rD, $addr", LdStGeneral,
Chris Lattner8e28b5c2006-11-15 23:24:18 +0000531 []>, RegConstraint<"$addr.reg = $ea_result">,
532 NoEncode<"$ea_result">;
Chris Lattner4eab7142006-11-10 02:08:47 +0000533
Evan Chengcaf778a2007-08-01 23:07:38 +0000534def LHAU : DForm_1<43, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
Chris Lattnerf8e07f42006-11-15 02:43:19 +0000535 "lhau $rD, $addr", LdStGeneral,
Chris Lattner8e28b5c2006-11-15 23:24:18 +0000536 []>, RegConstraint<"$addr.reg = $ea_result">,
537 NoEncode<"$ea_result">;
Chris Lattner4eab7142006-11-10 02:08:47 +0000538
Evan Chengcaf778a2007-08-01 23:07:38 +0000539def LHZU : DForm_1<41, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
Chris Lattnerf8e07f42006-11-15 02:43:19 +0000540 "lhzu $rD, $addr", LdStGeneral,
Chris Lattner8e28b5c2006-11-15 23:24:18 +0000541 []>, RegConstraint<"$addr.reg = $ea_result">,
542 NoEncode<"$ea_result">;
Chris Lattner4eab7142006-11-10 02:08:47 +0000543
Evan Chengcaf778a2007-08-01 23:07:38 +0000544def LWZU : DForm_1<33, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
Chris Lattnerf8e07f42006-11-15 02:43:19 +0000545 "lwzu $rD, $addr", LdStGeneral,
Chris Lattner8e28b5c2006-11-15 23:24:18 +0000546 []>, RegConstraint<"$addr.reg = $ea_result">,
547 NoEncode<"$ea_result">;
Chris Lattner4eab7142006-11-10 02:08:47 +0000548
Evan Chengcaf778a2007-08-01 23:07:38 +0000549def LFSU : DForm_1<49, (outs F4RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
Chris Lattnerf8e07f42006-11-15 02:43:19 +0000550 "lfs $rD, $addr", LdStLFDU,
Chris Lattner8e28b5c2006-11-15 23:24:18 +0000551 []>, RegConstraint<"$addr.reg = $ea_result">,
552 NoEncode<"$ea_result">;
553
Evan Chengcaf778a2007-08-01 23:07:38 +0000554def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
Chris Lattnerf8e07f42006-11-15 02:43:19 +0000555 "lfd $rD, $addr", LdStLFD,
Chris Lattner8e28b5c2006-11-15 23:24:18 +0000556 []>, RegConstraint<"$addr.reg = $ea_result">,
557 NoEncode<"$ea_result">;
Nate Begemanb816f022004-10-07 22:30:03 +0000558}
Chris Lattner302bf9c2006-11-08 02:13:12 +0000559
Chris Lattnerf8e07f42006-11-15 02:43:19 +0000560// Indexed (r+r) Loads.
Chris Lattner26e552b2006-11-14 19:19:53 +0000561//
Chris Lattner834f1ce2008-01-06 23:38:27 +0000562let isSimpleLoad = 1, PPC970_Unit = 2 in {
Evan Cheng64d80e32007-07-19 01:14:50 +0000563def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
Chris Lattner26e552b2006-11-14 19:19:53 +0000564 "lbzx $rD, $src", LdStGeneral,
565 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000566def LHAX : XForm_1<31, 343, (outs GPRC:$rD), (ins memrr:$src),
Chris Lattner26e552b2006-11-14 19:19:53 +0000567 "lhax $rD, $src", LdStLHA,
568 [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
569 PPC970_DGroup_Cracked;
Evan Cheng64d80e32007-07-19 01:14:50 +0000570def LHZX : XForm_1<31, 279, (outs GPRC:$rD), (ins memrr:$src),
Chris Lattner26e552b2006-11-14 19:19:53 +0000571 "lhzx $rD, $src", LdStGeneral,
572 [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000573def LWZX : XForm_1<31, 23, (outs GPRC:$rD), (ins memrr:$src),
Chris Lattner26e552b2006-11-14 19:19:53 +0000574 "lwzx $rD, $src", LdStGeneral,
575 [(set GPRC:$rD, (load xaddr:$src))]>;
576
577
Evan Cheng64d80e32007-07-19 01:14:50 +0000578def LHBRX : XForm_1<31, 790, (outs GPRC:$rD), (ins memrr:$src),
Chris Lattner26e552b2006-11-14 19:19:53 +0000579 "lhbrx $rD, $src", LdStGeneral,
580 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000581def LWBRX : XForm_1<31, 534, (outs GPRC:$rD), (ins memrr:$src),
Chris Lattner26e552b2006-11-14 19:19:53 +0000582 "lwbrx $rD, $src", LdStGeneral,
583 [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
584
Evan Cheng64d80e32007-07-19 01:14:50 +0000585def LFSX : XForm_25<31, 535, (outs F4RC:$frD), (ins memrr:$src),
Chris Lattner26e552b2006-11-14 19:19:53 +0000586 "lfsx $frD, $src", LdStLFDU,
587 [(set F4RC:$frD, (load xaddr:$src))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000588def LFDX : XForm_25<31, 599, (outs F8RC:$frD), (ins memrr:$src),
Chris Lattner26e552b2006-11-14 19:19:53 +0000589 "lfdx $frD, $src", LdStLFDU,
590 [(set F8RC:$frD, (load xaddr:$src))]>;
591}
592
593//===----------------------------------------------------------------------===//
594// PPC32 Store Instructions.
595//
596
Chris Lattnerf8e07f42006-11-15 02:43:19 +0000597// Unindexed (r+i) Stores.
Chris Lattner9c9fbf82008-01-06 05:53:26 +0000598let PPC970_Unit = 2 in {
Evan Cheng64d80e32007-07-19 01:14:50 +0000599def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
Chris Lattner26e552b2006-11-14 19:19:53 +0000600 "stb $rS, $src", LdStGeneral,
601 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000602def STH : DForm_1<44, (outs), (ins GPRC:$rS, memri:$src),
Chris Lattner26e552b2006-11-14 19:19:53 +0000603 "sth $rS, $src", LdStGeneral,
604 [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000605def STW : DForm_1<36, (outs), (ins GPRC:$rS, memri:$src),
Chris Lattner26e552b2006-11-14 19:19:53 +0000606 "stw $rS, $src", LdStGeneral,
607 [(store GPRC:$rS, iaddr:$src)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000608def STFS : DForm_1<52, (outs), (ins F4RC:$rS, memri:$dst),
Chris Lattner26e552b2006-11-14 19:19:53 +0000609 "stfs $rS, $dst", LdStUX,
610 [(store F4RC:$rS, iaddr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000611def STFD : DForm_1<54, (outs), (ins F8RC:$rS, memri:$dst),
Chris Lattner26e552b2006-11-14 19:19:53 +0000612 "stfd $rS, $dst", LdStUX,
613 [(store F8RC:$rS, iaddr:$dst)]>;
614}
615
Chris Lattnerf8e07f42006-11-15 02:43:19 +0000616// Unindexed (r+i) Stores with Update (preinc).
Chris Lattner9c9fbf82008-01-06 05:53:26 +0000617let PPC970_Unit = 2 in {
Evan Chengd5f181a2007-07-20 00:20:46 +0000618def STBU : DForm_1<39, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
Chris Lattneref20fef2006-11-16 00:33:34 +0000619 symbolLo:$ptroff, ptr_rc:$ptrreg),
620 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
Chris Lattner74531e42006-11-16 00:41:37 +0000621 [(set ptr_rc:$ea_res,
622 (pre_truncsti8 GPRC:$rS, ptr_rc:$ptrreg,
623 iaddroff:$ptroff))]>,
Chris Lattneref20fef2006-11-16 00:33:34 +0000624 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
Evan Chengd5f181a2007-07-20 00:20:46 +0000625def STHU : DForm_1<45, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
Chris Lattneref20fef2006-11-16 00:33:34 +0000626 symbolLo:$ptroff, ptr_rc:$ptrreg),
627 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
Chris Lattner74531e42006-11-16 00:41:37 +0000628 [(set ptr_rc:$ea_res,
629 (pre_truncsti16 GPRC:$rS, ptr_rc:$ptrreg,
630 iaddroff:$ptroff))]>,
Chris Lattneref20fef2006-11-16 00:33:34 +0000631 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
Evan Chengd5f181a2007-07-20 00:20:46 +0000632def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS,
Chris Lattneref20fef2006-11-16 00:33:34 +0000633 symbolLo:$ptroff, ptr_rc:$ptrreg),
634 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
Chris Lattner74531e42006-11-16 00:41:37 +0000635 [(set ptr_rc:$ea_res, (pre_store GPRC:$rS, ptr_rc:$ptrreg,
636 iaddroff:$ptroff))]>,
Chris Lattneref20fef2006-11-16 00:33:34 +0000637 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
Evan Chengd5f181a2007-07-20 00:20:46 +0000638def STFSU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F4RC:$rS,
Chris Lattneref20fef2006-11-16 00:33:34 +0000639 symbolLo:$ptroff, ptr_rc:$ptrreg),
640 "stfsu $rS, $ptroff($ptrreg)", LdStGeneral,
Chris Lattner74531e42006-11-16 00:41:37 +0000641 [(set ptr_rc:$ea_res, (pre_store F4RC:$rS, ptr_rc:$ptrreg,
642 iaddroff:$ptroff))]>,
Chris Lattneref20fef2006-11-16 00:33:34 +0000643 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
Evan Chengd5f181a2007-07-20 00:20:46 +0000644def STFDU : DForm_1<37, (outs ptr_rc:$ea_res), (ins F8RC:$rS,
Chris Lattneref20fef2006-11-16 00:33:34 +0000645 symbolLo:$ptroff, ptr_rc:$ptrreg),
646 "stfdu $rS, $ptroff($ptrreg)", LdStGeneral,
Chris Lattner74531e42006-11-16 00:41:37 +0000647 [(set ptr_rc:$ea_res, (pre_store F8RC:$rS, ptr_rc:$ptrreg,
648 iaddroff:$ptroff))]>,
Chris Lattneref20fef2006-11-16 00:33:34 +0000649 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
Chris Lattnerf8e07f42006-11-15 02:43:19 +0000650}
651
652
Chris Lattner26e552b2006-11-14 19:19:53 +0000653// Indexed (r+r) Stores.
654//
Chris Lattner9c9fbf82008-01-06 05:53:26 +0000655let PPC970_Unit = 2 in {
Evan Cheng64d80e32007-07-19 01:14:50 +0000656def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
Chris Lattner26e552b2006-11-14 19:19:53 +0000657 "stbx $rS, $dst", LdStGeneral,
658 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
659 PPC970_DGroup_Cracked;
Evan Cheng64d80e32007-07-19 01:14:50 +0000660def STHX : XForm_8<31, 407, (outs), (ins GPRC:$rS, memrr:$dst),
Chris Lattner26e552b2006-11-14 19:19:53 +0000661 "sthx $rS, $dst", LdStGeneral,
662 [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
663 PPC970_DGroup_Cracked;
Evan Cheng64d80e32007-07-19 01:14:50 +0000664def STWX : XForm_8<31, 151, (outs), (ins GPRC:$rS, memrr:$dst),
Chris Lattner26e552b2006-11-14 19:19:53 +0000665 "stwx $rS, $dst", LdStGeneral,
666 [(store GPRC:$rS, xaddr:$dst)]>,
667 PPC970_DGroup_Cracked;
Chris Lattner9c9fbf82008-01-06 05:53:26 +0000668
Chris Lattner2e48a702008-01-06 08:36:04 +0000669let mayStore = 1 in {
Evan Cheng64d80e32007-07-19 01:14:50 +0000670def STWUX : XForm_8<31, 183, (outs), (ins GPRC:$rS, GPRC:$rA, GPRC:$rB),
Chris Lattner26e552b2006-11-14 19:19:53 +0000671 "stwux $rS, $rA, $rB", LdStGeneral,
672 []>;
Chris Lattnerc8478d82008-01-06 06:44:58 +0000673}
Evan Cheng64d80e32007-07-19 01:14:50 +0000674def STHBRX: XForm_8<31, 918, (outs), (ins GPRC:$rS, memrr:$dst),
Chris Lattner26e552b2006-11-14 19:19:53 +0000675 "sthbrx $rS, $dst", LdStGeneral,
676 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
677 PPC970_DGroup_Cracked;
Evan Cheng64d80e32007-07-19 01:14:50 +0000678def STWBRX: XForm_8<31, 662, (outs), (ins GPRC:$rS, memrr:$dst),
Chris Lattner26e552b2006-11-14 19:19:53 +0000679 "stwbrx $rS, $dst", LdStGeneral,
680 [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
681 PPC970_DGroup_Cracked;
682
Evan Cheng64d80e32007-07-19 01:14:50 +0000683def STFIWX: XForm_28<31, 983, (outs), (ins F8RC:$frS, memrr:$dst),
Chris Lattner26e552b2006-11-14 19:19:53 +0000684 "stfiwx $frS, $dst", LdStUX,
685 [(PPCstfiwx F8RC:$frS, xoaddr:$dst)]>;
Chris Lattnerc8478d82008-01-06 06:44:58 +0000686
Evan Cheng64d80e32007-07-19 01:14:50 +0000687def STFSX : XForm_28<31, 663, (outs), (ins F4RC:$frS, memrr:$dst),
Chris Lattner26e552b2006-11-14 19:19:53 +0000688 "stfsx $frS, $dst", LdStUX,
689 [(store F4RC:$frS, xaddr:$dst)]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000690def STFDX : XForm_28<31, 727, (outs), (ins F8RC:$frS, memrr:$dst),
Chris Lattner26e552b2006-11-14 19:19:53 +0000691 "stfdx $frS, $dst", LdStUX,
692 [(store F8RC:$frS, xaddr:$dst)]>;
693}
694
695
696//===----------------------------------------------------------------------===//
697// PPC32 Arithmetic Instructions.
698//
Chris Lattner302bf9c2006-11-08 02:13:12 +0000699
Chris Lattner88d211f2006-03-12 09:13:49 +0000700let PPC970_Unit = 1 in { // FXU Operations.
Evan Cheng64d80e32007-07-19 01:14:50 +0000701def ADDI : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
Jim Laskey53842142005-10-19 19:51:16 +0000702 "addi $rD, $rA, $imm", IntGeneral,
Chris Lattner3e63ead2005-09-08 17:33:10 +0000703 [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000704def ADDIC : DForm_2<12, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
Jim Laskey53842142005-10-19 19:51:16 +0000705 "addic $rD, $rA, $imm", IntGeneral,
Chris Lattnerfd977342006-03-13 05:15:10 +0000706 [(set GPRC:$rD, (addc GPRC:$rA, immSExt16:$imm))]>,
707 PPC970_DGroup_Cracked;
Evan Cheng64d80e32007-07-19 01:14:50 +0000708def ADDICo : DForm_2<13, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
Jim Laskey53842142005-10-19 19:51:16 +0000709 "addic. $rD, $rA, $imm", IntGeneral,
Chris Lattner3e63ead2005-09-08 17:33:10 +0000710 []>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000711def ADDIS : DForm_2<15, (outs GPRC:$rD), (ins GPRC:$rA, symbolHi:$imm),
Jim Laskey53842142005-10-19 19:51:16 +0000712 "addis $rD, $rA, $imm", IntGeneral,
Chris Lattner0ea70b22006-06-20 22:34:10 +0000713 [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000714def LA : DForm_2<14, (outs GPRC:$rD), (ins GPRC:$rA, symbolLo:$sym),
Jim Laskey53842142005-10-19 19:51:16 +0000715 "la $rD, $sym($rA)", IntGeneral,
Chris Lattner490ad082005-11-17 17:52:01 +0000716 [(set GPRC:$rD, (add GPRC:$rA,
717 (PPClo tglobaladdr:$sym, 0)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000718def MULLI : DForm_2< 7, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
Jim Laskey53842142005-10-19 19:51:16 +0000719 "mulli $rD, $rA, $imm", IntMulLI,
Chris Lattner3e63ead2005-09-08 17:33:10 +0000720 [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000721def SUBFIC : DForm_2< 8, (outs GPRC:$rD), (ins GPRC:$rA, s16imm:$imm),
Jim Laskey53842142005-10-19 19:51:16 +0000722 "subfic $rD, $rA, $imm", IntGeneral,
Nate Begeman79691bc2006-03-17 22:41:37 +0000723 [(set GPRC:$rD, (subc immSExt16:$imm, GPRC:$rA))]>;
Bill Wendling0f940c92007-12-07 21:42:31 +0000724
Chris Lattnerdd415272008-01-10 05:45:39 +0000725let isReMaterializable = 1 in {
Bill Wendling0f940c92007-12-07 21:42:31 +0000726 def LI : DForm_2_r0<14, (outs GPRC:$rD), (ins symbolLo:$imm),
727 "li $rD, $imm", IntGeneral,
728 [(set GPRC:$rD, immSExt16:$imm)]>;
729 def LIS : DForm_2_r0<15, (outs GPRC:$rD), (ins symbolHi:$imm),
730 "lis $rD, $imm", IntGeneral,
731 [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
732}
Chris Lattner88d211f2006-03-12 09:13:49 +0000733}
Chris Lattner26e552b2006-11-14 19:19:53 +0000734
Chris Lattner88d211f2006-03-12 09:13:49 +0000735let PPC970_Unit = 1 in { // FXU Operations.
Evan Cheng64d80e32007-07-19 01:14:50 +0000736def ANDIo : DForm_4<28, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
Jim Laskey53842142005-10-19 19:51:16 +0000737 "andi. $dst, $src1, $src2", IntGeneral,
Nate Begeman789fd422006-02-12 09:09:52 +0000738 [(set GPRC:$dst, (and GPRC:$src1, immZExt16:$src2))]>,
739 isDOT;
Evan Cheng64d80e32007-07-19 01:14:50 +0000740def ANDISo : DForm_4<29, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
Jim Laskey53842142005-10-19 19:51:16 +0000741 "andis. $dst, $src1, $src2", IntGeneral,
Chris Lattner0ea70b22006-06-20 22:34:10 +0000742 [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
Nate Begeman789fd422006-02-12 09:09:52 +0000743 isDOT;
Evan Cheng64d80e32007-07-19 01:14:50 +0000744def ORI : DForm_4<24, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
Jim Laskey53842142005-10-19 19:51:16 +0000745 "ori $dst, $src1, $src2", IntGeneral,
Chris Lattnerc36d0652005-09-14 18:18:39 +0000746 [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000747def ORIS : DForm_4<25, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
Jim Laskey53842142005-10-19 19:51:16 +0000748 "oris $dst, $src1, $src2", IntGeneral,
Chris Lattner0ea70b22006-06-20 22:34:10 +0000749 [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000750def XORI : DForm_4<26, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
Jim Laskey53842142005-10-19 19:51:16 +0000751 "xori $dst, $src1, $src2", IntGeneral,
Chris Lattnerc36d0652005-09-14 18:18:39 +0000752 [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000753def XORIS : DForm_4<27, (outs GPRC:$dst), (ins GPRC:$src1, u16imm:$src2),
Jim Laskey53842142005-10-19 19:51:16 +0000754 "xoris $dst, $src1, $src2", IntGeneral,
Chris Lattner0ea70b22006-06-20 22:34:10 +0000755 [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000756def NOP : DForm_4_zero<24, (outs), (ins), "nop", IntGeneral,
Nate Begeman09761222005-12-09 23:54:18 +0000757 []>;
Evan Chengcaf778a2007-08-01 23:07:38 +0000758def CMPWI : DForm_5_ext<11, (outs CRRC:$crD), (ins GPRC:$rA, s16imm:$imm),
Jim Laskey53842142005-10-19 19:51:16 +0000759 "cmpwi $crD, $rA, $imm", IntCompare>;
Evan Chengcaf778a2007-08-01 23:07:38 +0000760def CMPLWI : DForm_6_ext<10, (outs CRRC:$dst), (ins GPRC:$src1, u16imm:$src2),
Jim Laskey53842142005-10-19 19:51:16 +0000761 "cmplwi $dst, $src1, $src2", IntCompare>;
Chris Lattner88d211f2006-03-12 09:13:49 +0000762}
Nate Begemaned428532004-09-04 05:00:00 +0000763
Chris Lattnerb22a04d2006-03-25 07:51:43 +0000764
Chris Lattner88d211f2006-03-12 09:13:49 +0000765let PPC970_Unit = 1 in { // FXU Operations.
Evan Cheng64d80e32007-07-19 01:14:50 +0000766def NAND : XForm_6<31, 476, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000767 "nand $rA, $rS, $rB", IntGeneral,
Chris Lattner7cd09cf2005-09-03 00:21:51 +0000768 [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000769def AND : XForm_6<31, 28, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000770 "and $rA, $rS, $rB", IntGeneral,
Chris Lattnerc36d0652005-09-14 18:18:39 +0000771 [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000772def ANDC : XForm_6<31, 60, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000773 "andc $rA, $rS, $rB", IntGeneral,
Chris Lattner7cd09cf2005-09-03 00:21:51 +0000774 [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000775def OR : XForm_6<31, 444, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000776 "or $rA, $rS, $rB", IntGeneral,
Chris Lattnerc36d0652005-09-14 18:18:39 +0000777 [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000778def NOR : XForm_6<31, 124, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000779 "nor $rA, $rS, $rB", IntGeneral,
Chris Lattner7cd09cf2005-09-03 00:21:51 +0000780 [(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000781def ORC : XForm_6<31, 412, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000782 "orc $rA, $rS, $rB", IntGeneral,
Chris Lattner7cd09cf2005-09-03 00:21:51 +0000783 [(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000784def EQV : XForm_6<31, 284, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000785 "eqv $rA, $rS, $rB", IntGeneral,
Chris Lattnerc36d0652005-09-14 18:18:39 +0000786 [(set GPRC:$rA, (not (xor GPRC:$rS, GPRC:$rB)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000787def XOR : XForm_6<31, 316, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000788 "xor $rA, $rS, $rB", IntGeneral,
Chris Lattner4e85e642006-06-20 00:39:56 +0000789 [(set GPRC:$rA, (xor GPRC:$rS, GPRC:$rB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000790def SLW : XForm_6<31, 24, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000791 "slw $rA, $rS, $rB", IntGeneral,
Chris Lattner4172b102005-12-06 02:10:38 +0000792 [(set GPRC:$rA, (PPCshl GPRC:$rS, GPRC:$rB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000793def SRW : XForm_6<31, 536, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000794 "srw $rA, $rS, $rB", IntGeneral,
Chris Lattner4172b102005-12-06 02:10:38 +0000795 [(set GPRC:$rA, (PPCsrl GPRC:$rS, GPRC:$rB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000796def SRAW : XForm_6<31, 792, (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000797 "sraw $rA, $rS, $rB", IntShift,
Chris Lattner4172b102005-12-06 02:10:38 +0000798 [(set GPRC:$rA, (PPCsra GPRC:$rS, GPRC:$rB))]>;
Chris Lattner88d211f2006-03-12 09:13:49 +0000799}
Chris Lattner26e552b2006-11-14 19:19:53 +0000800
Chris Lattner88d211f2006-03-12 09:13:49 +0000801let PPC970_Unit = 1 in { // FXU Operations.
Evan Cheng64d80e32007-07-19 01:14:50 +0000802def SRAWI : XForm_10<31, 824, (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH),
Jim Laskey53842142005-10-19 19:51:16 +0000803 "srawi $rA, $rS, $SH", IntShift,
Chris Lattnerbd059822005-12-05 02:34:05 +0000804 [(set GPRC:$rA, (sra GPRC:$rS, (i32 imm:$SH)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000805def CNTLZW : XForm_11<31, 26, (outs GPRC:$rA), (ins GPRC:$rS),
Jim Laskey53842142005-10-19 19:51:16 +0000806 "cntlzw $rA, $rS", IntGeneral,
Chris Lattner6159fb22005-09-02 22:35:53 +0000807 [(set GPRC:$rA, (ctlz GPRC:$rS))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000808def EXTSB : XForm_11<31, 954, (outs GPRC:$rA), (ins GPRC:$rS),
Jim Laskey53842142005-10-19 19:51:16 +0000809 "extsb $rA, $rS", IntGeneral,
Chris Lattner6159fb22005-09-02 22:35:53 +0000810 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i8))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000811def EXTSH : XForm_11<31, 922, (outs GPRC:$rA), (ins GPRC:$rS),
Jim Laskey53842142005-10-19 19:51:16 +0000812 "extsh $rA, $rS", IntGeneral,
Chris Lattner6159fb22005-09-02 22:35:53 +0000813 [(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
Chris Lattnerecfe55e2006-03-22 05:30:33 +0000814
Evan Cheng64d80e32007-07-19 01:14:50 +0000815def CMPW : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000816 "cmpw $crD, $rA, $rB", IntCompare>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000817def CMPLW : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins GPRC:$rA, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000818 "cmplw $crD, $rA, $rB", IntCompare>;
Chris Lattner88d211f2006-03-12 09:13:49 +0000819}
820let PPC970_Unit = 3 in { // FPU Operations.
Evan Cheng64d80e32007-07-19 01:14:50 +0000821//def FCMPO : XForm_17<63, 32, (outs CRRC:$crD), (ins FPRC:$fA, FPRC:$fB),
Jim Laskey53842142005-10-19 19:51:16 +0000822// "fcmpo $crD, $fA, $fB", FPCompare>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000823def FCMPUS : XForm_17<63, 0, (outs CRRC:$crD), (ins F4RC:$fA, F4RC:$fB),
Jim Laskey53842142005-10-19 19:51:16 +0000824 "fcmpu $crD, $fA, $fB", FPCompare>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000825def FCMPUD : XForm_17<63, 0, (outs CRRC:$crD), (ins F8RC:$fA, F8RC:$fB),
Jim Laskey53842142005-10-19 19:51:16 +0000826 "fcmpu $crD, $fA, $fB", FPCompare>;
Chris Lattner26e552b2006-11-14 19:19:53 +0000827
Evan Cheng64d80e32007-07-19 01:14:50 +0000828def FCTIWZ : XForm_26<63, 15, (outs F8RC:$frD), (ins F8RC:$frB),
Jim Laskey53842142005-10-19 19:51:16 +0000829 "fctiwz $frD, $frB", FPGeneral,
Chris Lattnere6115b32005-10-25 20:41:46 +0000830 [(set F8RC:$frD, (PPCfctiwz F8RC:$frB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000831def FRSP : XForm_26<63, 12, (outs F4RC:$frD), (ins F8RC:$frB),
Jim Laskey53842142005-10-19 19:51:16 +0000832 "frsp $frD, $frB", FPGeneral,
Chris Lattner7cb64912005-10-14 04:55:50 +0000833 [(set F4RC:$frD, (fround F8RC:$frB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000834def FSQRT : XForm_26<63, 22, (outs F8RC:$frD), (ins F8RC:$frB),
Jim Laskey53842142005-10-19 19:51:16 +0000835 "fsqrt $frD, $frB", FPSqrt,
Chris Lattner919c0322005-10-01 01:35:02 +0000836 [(set F8RC:$frD, (fsqrt F8RC:$frB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000837def FSQRTS : XForm_26<59, 22, (outs F4RC:$frD), (ins F4RC:$frB),
Jim Laskey53842142005-10-19 19:51:16 +0000838 "fsqrts $frD, $frB", FPSqrt,
Chris Lattnere0b2e632005-10-15 21:44:15 +0000839 [(set F4RC:$frD, (fsqrt F4RC:$frB))]>;
Chris Lattner88d211f2006-03-12 09:13:49 +0000840}
Chris Lattner919c0322005-10-01 01:35:02 +0000841
842/// FMR is split into 3 versions, one for 4/8 byte FP, and one for extending.
Chris Lattner88d211f2006-03-12 09:13:49 +0000843///
844/// Note that these are defined as pseudo-ops on the PPC970 because they are
Chris Lattner9d5da1d2006-03-24 07:12:19 +0000845/// often coalesced away and we don't want the dispatch group builder to think
Chris Lattner88d211f2006-03-12 09:13:49 +0000846/// that they will fill slots (which could cause the load of a LSU reject to
847/// sneak into a d-group with a store).
Evan Cheng64d80e32007-07-19 01:14:50 +0000848def FMRS : XForm_26<63, 72, (outs F4RC:$frD), (ins F4RC:$frB),
Jim Laskey53842142005-10-19 19:51:16 +0000849 "fmr $frD, $frB", FPGeneral,
Chris Lattner88d211f2006-03-12 09:13:49 +0000850 []>, // (set F4RC:$frD, F4RC:$frB)
851 PPC970_Unit_Pseudo;
Evan Cheng64d80e32007-07-19 01:14:50 +0000852def FMRD : XForm_26<63, 72, (outs F8RC:$frD), (ins F8RC:$frB),
Jim Laskey53842142005-10-19 19:51:16 +0000853 "fmr $frD, $frB", FPGeneral,
Chris Lattner88d211f2006-03-12 09:13:49 +0000854 []>, // (set F8RC:$frD, F8RC:$frB)
855 PPC970_Unit_Pseudo;
Evan Cheng64d80e32007-07-19 01:14:50 +0000856def FMRSD : XForm_26<63, 72, (outs F8RC:$frD), (ins F4RC:$frB),
Jim Laskey53842142005-10-19 19:51:16 +0000857 "fmr $frD, $frB", FPGeneral,
Chris Lattner88d211f2006-03-12 09:13:49 +0000858 [(set F8RC:$frD, (fextend F4RC:$frB))]>,
859 PPC970_Unit_Pseudo;
Chris Lattner919c0322005-10-01 01:35:02 +0000860
Chris Lattner88d211f2006-03-12 09:13:49 +0000861let PPC970_Unit = 3 in { // FPU Operations.
Chris Lattner919c0322005-10-01 01:35:02 +0000862// These are artificially split into two different forms, for 4/8 byte FP.
Evan Cheng64d80e32007-07-19 01:14:50 +0000863def FABSS : XForm_26<63, 264, (outs F4RC:$frD), (ins F4RC:$frB),
Jim Laskey53842142005-10-19 19:51:16 +0000864 "fabs $frD, $frB", FPGeneral,
Chris Lattner919c0322005-10-01 01:35:02 +0000865 [(set F4RC:$frD, (fabs F4RC:$frB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000866def FABSD : XForm_26<63, 264, (outs F8RC:$frD), (ins F8RC:$frB),
Jim Laskey53842142005-10-19 19:51:16 +0000867 "fabs $frD, $frB", FPGeneral,
Chris Lattner919c0322005-10-01 01:35:02 +0000868 [(set F8RC:$frD, (fabs F8RC:$frB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000869def FNABSS : XForm_26<63, 136, (outs F4RC:$frD), (ins F4RC:$frB),
Jim Laskey53842142005-10-19 19:51:16 +0000870 "fnabs $frD, $frB", FPGeneral,
Chris Lattner919c0322005-10-01 01:35:02 +0000871 [(set F4RC:$frD, (fneg (fabs F4RC:$frB)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000872def FNABSD : XForm_26<63, 136, (outs F8RC:$frD), (ins F8RC:$frB),
Jim Laskey53842142005-10-19 19:51:16 +0000873 "fnabs $frD, $frB", FPGeneral,
Chris Lattner919c0322005-10-01 01:35:02 +0000874 [(set F8RC:$frD, (fneg (fabs F8RC:$frB)))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000875def FNEGS : XForm_26<63, 40, (outs F4RC:$frD), (ins F4RC:$frB),
Jim Laskey53842142005-10-19 19:51:16 +0000876 "fneg $frD, $frB", FPGeneral,
Chris Lattner919c0322005-10-01 01:35:02 +0000877 [(set F4RC:$frD, (fneg F4RC:$frB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000878def FNEGD : XForm_26<63, 40, (outs F8RC:$frD), (ins F8RC:$frB),
Jim Laskey53842142005-10-19 19:51:16 +0000879 "fneg $frD, $frB", FPGeneral,
Chris Lattner919c0322005-10-01 01:35:02 +0000880 [(set F8RC:$frD, (fneg F8RC:$frB))]>;
Chris Lattner88d211f2006-03-12 09:13:49 +0000881}
Chris Lattner919c0322005-10-01 01:35:02 +0000882
Nate Begeman6b3dc552004-08-29 22:45:13 +0000883
Nate Begeman07aada82004-08-30 02:28:06 +0000884// XL-Form instructions. condition register logical ops.
885//
Evan Cheng64d80e32007-07-19 01:14:50 +0000886def MCRF : XLForm_3<19, 0, (outs CRRC:$BF), (ins CRRC:$BFA),
Chris Lattner88d211f2006-03-12 09:13:49 +0000887 "mcrf $BF, $BFA", BrMCR>,
888 PPC970_DGroup_First, PPC970_Unit_CRU;
Nate Begeman07aada82004-08-30 02:28:06 +0000889
Nicolas Geoffray0404cd92008-03-10 14:12:10 +0000890def CREQV : XLForm_1<19, 289, (outs CRBITRC:$CRD),
891 (ins CRBITRC:$CRA, CRBITRC:$CRB),
Chris Lattner9f0bc652007-02-25 05:34:32 +0000892 "creqv $CRD, $CRA, $CRB", BrCR,
893 []>;
894
Nicolas Geoffray0404cd92008-03-10 14:12:10 +0000895def CROR : XLForm_1<19, 449, (outs CRBITRC:$CRD),
896 (ins CRBITRC:$CRA, CRBITRC:$CRB),
897 "cror $CRD, $CRA, $CRB", BrCR,
898 []>;
899
900def CRSET : XLForm_1_ext<19, 289, (outs CRBITRC:$dst), (ins),
Chris Lattner9f0bc652007-02-25 05:34:32 +0000901 "creqv $dst, $dst, $dst", BrCR,
902 []>;
903
Chris Lattner88d211f2006-03-12 09:13:49 +0000904// XFX-Form instructions. Instructions that deal with SPRs.
Nate Begeman07aada82004-08-30 02:28:06 +0000905//
Evan Cheng64d80e32007-07-19 01:14:50 +0000906def MFCTR : XFXForm_1_ext<31, 339, 9, (outs GPRC:$rT), (ins),
907 "mfctr $rT", SprMFSPR>,
Chris Lattner88d211f2006-03-12 09:13:49 +0000908 PPC970_DGroup_First, PPC970_Unit_FXU;
Chris Lattnerc703a8f2006-05-17 19:00:46 +0000909let Pattern = [(PPCmtctr GPRC:$rS)] in {
Evan Cheng64d80e32007-07-19 01:14:50 +0000910def MTCTR : XFXForm_7_ext<31, 467, 9, (outs), (ins GPRC:$rS),
911 "mtctr $rS", SprMTSPR>,
Chris Lattner1877ec92006-03-13 21:52:10 +0000912 PPC970_DGroup_First, PPC970_Unit_FXU;
Chris Lattnerc703a8f2006-05-17 19:00:46 +0000913}
Chris Lattner1877ec92006-03-13 21:52:10 +0000914
Evan Cheng64d80e32007-07-19 01:14:50 +0000915def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins GPRC:$rS),
916 "mtlr $rS", SprMTSPR>,
Chris Lattner1877ec92006-03-13 21:52:10 +0000917 PPC970_DGroup_First, PPC970_Unit_FXU;
Evan Cheng64d80e32007-07-19 01:14:50 +0000918def MFLR : XFXForm_1_ext<31, 339, 8, (outs GPRC:$rT), (ins),
919 "mflr $rT", SprMFSPR>,
Chris Lattner88d211f2006-03-12 09:13:49 +0000920 PPC970_DGroup_First, PPC970_Unit_FXU;
Chris Lattner1877ec92006-03-13 21:52:10 +0000921
922// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed like
923// a GPR on the PPC970. As such, copies in and out have the same performance
924// characteristics as an OR instruction.
Evan Cheng64d80e32007-07-19 01:14:50 +0000925def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins GPRC:$rS),
Chris Lattner1877ec92006-03-13 21:52:10 +0000926 "mtspr 256, $rS", IntGeneral>,
Nate Begeman133decd2006-03-15 05:25:05 +0000927 PPC970_DGroup_Single, PPC970_Unit_FXU;
Evan Cheng64d80e32007-07-19 01:14:50 +0000928def MFVRSAVE : XFXForm_1_ext<31, 339, 256, (outs GPRC:$rT), (ins),
Chris Lattner1877ec92006-03-13 21:52:10 +0000929 "mfspr $rT, 256", IntGeneral>,
Nate Begeman133decd2006-03-15 05:25:05 +0000930 PPC970_DGroup_First, PPC970_Unit_FXU;
Chris Lattner1877ec92006-03-13 21:52:10 +0000931
Evan Cheng64d80e32007-07-19 01:14:50 +0000932def MTCRF : XFXForm_5<31, 144, (outs), (ins crbitm:$FXM, GPRC:$rS),
Chris Lattner88d211f2006-03-12 09:13:49 +0000933 "mtcrf $FXM, $rS", BrMCRX>,
934 PPC970_MicroCode, PPC970_Unit_CRU;
Evan Cheng64d80e32007-07-19 01:14:50 +0000935def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), "mfcr $rT", SprMFCR>,
Chris Lattner6d92cad2006-03-26 10:06:40 +0000936 PPC970_MicroCode, PPC970_Unit_CRU;
Evan Cheng64d80e32007-07-19 01:14:50 +0000937def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM),
Chris Lattner88d211f2006-03-12 09:13:49 +0000938 "mfcr $rT, $FXM", SprMFCR>,
939 PPC970_DGroup_First, PPC970_Unit_CRU;
Nate Begeman07aada82004-08-30 02:28:06 +0000940
Dale Johannesen6eaeff22007-10-10 01:01:31 +0000941// Instructions to manipulate FPSCR. Only long double handling uses these.
942// FPSCR is not modelled; we use the SDNode Flag to keep things in order.
943
944def MFFS : XForm_42<63, 583, (outs F8RC:$rT), (ins),
945 "mffs $rT", IntMFFS,
946 [(set F8RC:$rT, (PPCmffs))]>,
947 PPC970_DGroup_Single, PPC970_Unit_FPU;
948def MTFSB0 : XForm_43<63, 70, (outs), (ins u5imm:$FM),
949 "mtfsb0 $FM", IntMTFSB0,
950 [(PPCmtfsb0 (i32 imm:$FM))]>,
951 PPC970_DGroup_Single, PPC970_Unit_FPU;
952def MTFSB1 : XForm_43<63, 38, (outs), (ins u5imm:$FM),
953 "mtfsb1 $FM", IntMTFSB0,
954 [(PPCmtfsb1 (i32 imm:$FM))]>,
955 PPC970_DGroup_Single, PPC970_Unit_FPU;
956def FADDrtz: AForm_2<63, 21,
957 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
958 "fadd $FRT, $FRA, $FRB", FPGeneral,
959 [(set F8RC:$FRT, (PPCfaddrtz F8RC:$FRA, F8RC:$FRB))]>,
960 PPC970_DGroup_Single, PPC970_Unit_FPU;
961// MTFSF does not actually produce an FP result. We pretend it copies
962// input reg B to the output. If we didn't do this it would look like the
963// instruction had no outputs (because we aren't modelling the FPSCR) and
964// it would be deleted.
965def MTFSF : XFLForm<63, 711, (outs F8RC:$FRA),
966 (ins i32imm:$FM, F8RC:$rT, F8RC:$FRB),
967 "mtfsf $FM, $rT", "$FRB = $FRA", IntMTFSB0,
968 [(set F8RC:$FRA, (PPCmtfsf (i32 imm:$FM),
969 F8RC:$rT, F8RC:$FRB))]>,
970 PPC970_DGroup_Single, PPC970_Unit_FPU;
971
Chris Lattner88d211f2006-03-12 09:13:49 +0000972let PPC970_Unit = 1 in { // FXU Operations.
Nate Begeman07aada82004-08-30 02:28:06 +0000973
974// XO-Form instructions. Arithmetic instructions that can set overflow bit
975//
Evan Cheng64d80e32007-07-19 01:14:50 +0000976def ADD4 : XOForm_1<31, 266, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000977 "add $rT, $rA, $rB", IntGeneral,
Chris Lattner218a15d2005-09-02 21:18:00 +0000978 [(set GPRC:$rT, (add GPRC:$rA, GPRC:$rB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000979def ADDC : XOForm_1<31, 10, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000980 "addc $rT, $rA, $rB", IntGeneral,
Chris Lattnerfd977342006-03-13 05:15:10 +0000981 [(set GPRC:$rT, (addc GPRC:$rA, GPRC:$rB))]>,
982 PPC970_DGroup_Cracked;
Evan Cheng64d80e32007-07-19 01:14:50 +0000983def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000984 "adde $rT, $rA, $rB", IntGeneral,
Nate Begeman551bf3f2006-02-17 05:43:56 +0000985 [(set GPRC:$rT, (adde GPRC:$rA, GPRC:$rB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000986def DIVW : XOForm_1<31, 491, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000987 "divw $rT, $rA, $rB", IntDivW,
Chris Lattner88d211f2006-03-12 09:13:49 +0000988 [(set GPRC:$rT, (sdiv GPRC:$rA, GPRC:$rB))]>,
Chris Lattnerfd977342006-03-13 05:15:10 +0000989 PPC970_DGroup_First, PPC970_DGroup_Cracked;
Evan Cheng64d80e32007-07-19 01:14:50 +0000990def DIVWU : XOForm_1<31, 459, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000991 "divwu $rT, $rA, $rB", IntDivW,
Chris Lattner88d211f2006-03-12 09:13:49 +0000992 [(set GPRC:$rT, (udiv GPRC:$rA, GPRC:$rB))]>,
Chris Lattnerfd977342006-03-13 05:15:10 +0000993 PPC970_DGroup_First, PPC970_DGroup_Cracked;
Evan Cheng64d80e32007-07-19 01:14:50 +0000994def MULHW : XOForm_1<31, 75, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000995 "mulhw $rT, $rA, $rB", IntMulHW,
Chris Lattner218a15d2005-09-02 21:18:00 +0000996 [(set GPRC:$rT, (mulhs GPRC:$rA, GPRC:$rB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +0000997def MULHWU : XOForm_1<31, 11, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +0000998 "mulhwu $rT, $rA, $rB", IntMulHWU,
Chris Lattner218a15d2005-09-02 21:18:00 +0000999 [(set GPRC:$rT, (mulhu GPRC:$rA, GPRC:$rB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001000def MULLW : XOForm_1<31, 235, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +00001001 "mullw $rT, $rA, $rB", IntMulHW,
Chris Lattner218a15d2005-09-02 21:18:00 +00001002 [(set GPRC:$rT, (mul GPRC:$rA, GPRC:$rB))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001003def SUBF : XOForm_1<31, 40, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +00001004 "subf $rT, $rA, $rB", IntGeneral,
Chris Lattner218a15d2005-09-02 21:18:00 +00001005 [(set GPRC:$rT, (sub GPRC:$rB, GPRC:$rA))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001006def SUBFC : XOForm_1<31, 8, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +00001007 "subfc $rT, $rA, $rB", IntGeneral,
Chris Lattnerfd977342006-03-13 05:15:10 +00001008 [(set GPRC:$rT, (subc GPRC:$rB, GPRC:$rA))]>,
1009 PPC970_DGroup_Cracked;
Evan Cheng64d80e32007-07-19 01:14:50 +00001010def SUBFE : XOForm_1<31, 136, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
Jim Laskey53842142005-10-19 19:51:16 +00001011 "subfe $rT, $rA, $rB", IntGeneral,
Nate Begeman551bf3f2006-02-17 05:43:56 +00001012 [(set GPRC:$rT, (sube GPRC:$rB, GPRC:$rA))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001013def ADDME : XOForm_3<31, 234, 0, (outs GPRC:$rT), (ins GPRC:$rA),
Jim Laskey53842142005-10-19 19:51:16 +00001014 "addme $rT, $rA", IntGeneral,
Nate Begeman551bf3f2006-02-17 05:43:56 +00001015 [(set GPRC:$rT, (adde GPRC:$rA, immAllOnes))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001016def ADDZE : XOForm_3<31, 202, 0, (outs GPRC:$rT), (ins GPRC:$rA),
Jim Laskey53842142005-10-19 19:51:16 +00001017 "addze $rT, $rA", IntGeneral,
Nate Begeman551bf3f2006-02-17 05:43:56 +00001018 [(set GPRC:$rT, (adde GPRC:$rA, 0))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001019def NEG : XOForm_3<31, 104, 0, (outs GPRC:$rT), (ins GPRC:$rA),
Jim Laskey53842142005-10-19 19:51:16 +00001020 "neg $rT, $rA", IntGeneral,
Chris Lattnerd1cdc702005-09-08 17:01:54 +00001021 [(set GPRC:$rT, (ineg GPRC:$rA))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001022def SUBFME : XOForm_3<31, 232, 0, (outs GPRC:$rT), (ins GPRC:$rA),
Nate Begeman551bf3f2006-02-17 05:43:56 +00001023 "subfme $rT, $rA", IntGeneral,
1024 [(set GPRC:$rT, (sube immAllOnes, GPRC:$rA))]>;
Evan Cheng64d80e32007-07-19 01:14:50 +00001025def SUBFZE : XOForm_3<31, 200, 0, (outs GPRC:$rT), (ins GPRC:$rA),
Jim Laskey53842142005-10-19 19:51:16 +00001026 "subfze $rT, $rA", IntGeneral,
Nate Begeman551bf3f2006-02-17 05:43:56 +00001027 [(set GPRC:$rT, (sube 0, GPRC:$rA))]>;
Chris Lattner88d211f2006-03-12 09:13:49 +00001028}
Nate Begeman07aada82004-08-30 02:28:06 +00001029
1030// A-Form instructions. Most of the instructions executed in the FPU are of
1031// this type.
1032//
Chris Lattner88d211f2006-03-12 09:13:49 +00001033let PPC970_Unit = 3 in { // FPU Operations.
Chris Lattner14522e32005-04-19 05:21:30 +00001034def FMADD : AForm_1<63, 29,
Evan Cheng64d80e32007-07-19 01:14:50 +00001035 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001036 "fmadd $FRT, $FRA, $FRC, $FRB", FPFused,
Chris Lattner919c0322005-10-01 01:35:02 +00001037 [(set F8RC:$FRT, (fadd (fmul F8RC:$FRA, F8RC:$FRC),
Evan Cheng8c75ef92005-12-14 22:07:12 +00001038 F8RC:$FRB))]>,
1039 Requires<[FPContractions]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001040def FMADDS : AForm_1<59, 29,
Evan Cheng64d80e32007-07-19 01:14:50 +00001041 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001042 "fmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
Chris Lattnerdff06f42005-10-02 07:46:28 +00001043 [(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
Evan Cheng8c75ef92005-12-14 22:07:12 +00001044 F4RC:$FRB))]>,
1045 Requires<[FPContractions]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001046def FMSUB : AForm_1<63, 28,
Evan Cheng64d80e32007-07-19 01:14:50 +00001047 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001048 "fmsub $FRT, $FRA, $FRC, $FRB", FPFused,
Chris Lattner919c0322005-10-01 01:35:02 +00001049 [(set F8RC:$FRT, (fsub (fmul F8RC:$FRA, F8RC:$FRC),
Evan Cheng8c75ef92005-12-14 22:07:12 +00001050 F8RC:$FRB))]>,
1051 Requires<[FPContractions]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001052def FMSUBS : AForm_1<59, 28,
Evan Cheng64d80e32007-07-19 01:14:50 +00001053 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001054 "fmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
Chris Lattnerdff06f42005-10-02 07:46:28 +00001055 [(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC),
Evan Cheng8c75ef92005-12-14 22:07:12 +00001056 F4RC:$FRB))]>,
1057 Requires<[FPContractions]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001058def FNMADD : AForm_1<63, 31,
Evan Cheng64d80e32007-07-19 01:14:50 +00001059 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001060 "fnmadd $FRT, $FRA, $FRC, $FRB", FPFused,
Chris Lattner919c0322005-10-01 01:35:02 +00001061 [(set F8RC:$FRT, (fneg (fadd (fmul F8RC:$FRA, F8RC:$FRC),
Nate Begemana07da922005-12-14 22:54:33 +00001062 F8RC:$FRB)))]>,
1063 Requires<[FPContractions]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001064def FNMADDS : AForm_1<59, 31,
Evan Cheng64d80e32007-07-19 01:14:50 +00001065 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001066 "fnmadds $FRT, $FRA, $FRC, $FRB", FPGeneral,
Chris Lattnerdff06f42005-10-02 07:46:28 +00001067 [(set F4RC:$FRT, (fneg (fadd (fmul F4RC:$FRA, F4RC:$FRC),
Nate Begemana07da922005-12-14 22:54:33 +00001068 F4RC:$FRB)))]>,
1069 Requires<[FPContractions]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001070def FNMSUB : AForm_1<63, 30,
Evan Cheng64d80e32007-07-19 01:14:50 +00001071 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001072 "fnmsub $FRT, $FRA, $FRC, $FRB", FPFused,
Chris Lattner919c0322005-10-01 01:35:02 +00001073 [(set F8RC:$FRT, (fneg (fsub (fmul F8RC:$FRA, F8RC:$FRC),
Nate Begemana07da922005-12-14 22:54:33 +00001074 F8RC:$FRB)))]>,
1075 Requires<[FPContractions]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001076def FNMSUBS : AForm_1<59, 30,
Evan Cheng64d80e32007-07-19 01:14:50 +00001077 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001078 "fnmsubs $FRT, $FRA, $FRC, $FRB", FPGeneral,
Chris Lattnerdff06f42005-10-02 07:46:28 +00001079 [(set F4RC:$FRT, (fneg (fsub (fmul F4RC:$FRA, F4RC:$FRC),
Nate Begemana07da922005-12-14 22:54:33 +00001080 F4RC:$FRB)))]>,
1081 Requires<[FPContractions]>;
Chris Lattner43f07a42005-10-02 07:07:49 +00001082// FSEL is artificially split into 4 and 8-byte forms for the result. To avoid
1083// having 4 of these, force the comparison to always be an 8-byte double (code
1084// should use an FMRSD if the input comparison value really wants to be a float)
Chris Lattner867940d2005-10-02 06:58:23 +00001085// and 4/8 byte forms for the result and operand type..
Chris Lattner43f07a42005-10-02 07:07:49 +00001086def FSELD : AForm_1<63, 23,
Evan Cheng64d80e32007-07-19 01:14:50 +00001087 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001088 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
Chris Lattner9c73f092005-10-25 20:55:47 +00001089 [(set F8RC:$FRT, (PPCfsel F8RC:$FRA,F8RC:$FRC,F8RC:$FRB))]>;
Chris Lattner43f07a42005-10-02 07:07:49 +00001090def FSELS : AForm_1<63, 23,
Evan Cheng64d80e32007-07-19 01:14:50 +00001091 (outs F4RC:$FRT), (ins F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001092 "fsel $FRT, $FRA, $FRC, $FRB", FPGeneral,
Chris Lattner9c73f092005-10-25 20:55:47 +00001093 [(set F4RC:$FRT, (PPCfsel F8RC:$FRA,F4RC:$FRC,F4RC:$FRB))]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001094def FADD : AForm_2<63, 21,
Evan Cheng64d80e32007-07-19 01:14:50 +00001095 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001096 "fadd $FRT, $FRA, $FRB", FPGeneral,
Chris Lattner919c0322005-10-01 01:35:02 +00001097 [(set F8RC:$FRT, (fadd F8RC:$FRA, F8RC:$FRB))]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001098def FADDS : AForm_2<59, 21,
Evan Cheng64d80e32007-07-19 01:14:50 +00001099 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001100 "fadds $FRT, $FRA, $FRB", FPGeneral,
Chris Lattnerdff06f42005-10-02 07:46:28 +00001101 [(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001102def FDIV : AForm_2<63, 18,
Evan Cheng64d80e32007-07-19 01:14:50 +00001103 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001104 "fdiv $FRT, $FRA, $FRB", FPDivD,
Chris Lattner919c0322005-10-01 01:35:02 +00001105 [(set F8RC:$FRT, (fdiv F8RC:$FRA, F8RC:$FRB))]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001106def FDIVS : AForm_2<59, 18,
Evan Cheng64d80e32007-07-19 01:14:50 +00001107 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001108 "fdivs $FRT, $FRA, $FRB", FPDivS,
Chris Lattnerdff06f42005-10-02 07:46:28 +00001109 [(set F4RC:$FRT, (fdiv F4RC:$FRA, F4RC:$FRB))]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001110def FMUL : AForm_3<63, 25,
Evan Cheng64d80e32007-07-19 01:14:50 +00001111 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001112 "fmul $FRT, $FRA, $FRB", FPFused,
Chris Lattner919c0322005-10-01 01:35:02 +00001113 [(set F8RC:$FRT, (fmul F8RC:$FRA, F8RC:$FRB))]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001114def FMULS : AForm_3<59, 25,
Evan Cheng64d80e32007-07-19 01:14:50 +00001115 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001116 "fmuls $FRT, $FRA, $FRB", FPGeneral,
Chris Lattnerdff06f42005-10-02 07:46:28 +00001117 [(set F4RC:$FRT, (fmul F4RC:$FRA, F4RC:$FRB))]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001118def FSUB : AForm_2<63, 20,
Evan Cheng64d80e32007-07-19 01:14:50 +00001119 (outs F8RC:$FRT), (ins F8RC:$FRA, F8RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001120 "fsub $FRT, $FRA, $FRB", FPGeneral,
Chris Lattner919c0322005-10-01 01:35:02 +00001121 [(set F8RC:$FRT, (fsub F8RC:$FRA, F8RC:$FRB))]>;
Chris Lattner14522e32005-04-19 05:21:30 +00001122def FSUBS : AForm_2<59, 20,
Evan Cheng64d80e32007-07-19 01:14:50 +00001123 (outs F4RC:$FRT), (ins F4RC:$FRA, F4RC:$FRB),
Jim Laskey53842142005-10-19 19:51:16 +00001124 "fsubs $FRT, $FRA, $FRB", FPGeneral,
Chris Lattnerdff06f42005-10-02 07:46:28 +00001125 [(set F4RC:$FRT, (fsub F4RC:$FRA, F4RC:$FRB))]>;
Chris Lattner88d211f2006-03-12 09:13:49 +00001126}
Nate Begeman07aada82004-08-30 02:28:06 +00001127
Chris Lattner88d211f2006-03-12 09:13:49 +00001128let PPC970_Unit = 1 in { // FXU Operations.
Nate Begemancc8bd9c2004-08-31 02:28:08 +00001129// M-Form instructions. rotate and mask instructions.
1130//
Chris Lattner8e28b5c2006-11-15 23:24:18 +00001131let isCommutable = 1 in {
Chris Lattner043870d2005-09-09 18:17:41 +00001132// RLWIMI can be commuted if the rotate amount is zero.
Chris Lattner14522e32005-04-19 05:21:30 +00001133def RLWIMI : MForm_2<20,
Evan Cheng64d80e32007-07-19 01:14:50 +00001134 (outs GPRC:$rA), (ins GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB,
Jim Laskey53842142005-10-19 19:51:16 +00001135 u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME", IntRotate,
Chris Lattner8e28b5c2006-11-15 23:24:18 +00001136 []>, PPC970_DGroup_Cracked, RegConstraint<"$rSi = $rA">,
1137 NoEncode<"$rSi">;
Nate Begeman2d4c98d2004-10-16 20:43:38 +00001138}
Chris Lattner14522e32005-04-19 05:21:30 +00001139def RLWINM : MForm_2<21,
Evan Cheng64d80e32007-07-19 01:14:50 +00001140 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
Jim Laskey53842142005-10-19 19:51:16 +00001141 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
Nate Begeman2d5aff72005-10-19 18:42:01 +00001142 []>;
Chris Lattner14522e32005-04-19 05:21:30 +00001143def RLWINMo : MForm_2<21,
Evan Cheng64d80e32007-07-19 01:14:50 +00001144 (outs GPRC:$rA), (ins GPRC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
Jim Laskey53842142005-10-19 19:51:16 +00001145 "rlwinm. $rA, $rS, $SH, $MB, $ME", IntGeneral,
Chris Lattnerfd977342006-03-13 05:15:10 +00001146 []>, isDOT, PPC970_DGroup_Cracked;
Chris Lattner14522e32005-04-19 05:21:30 +00001147def RLWNM : MForm_2<23,
Evan Cheng64d80e32007-07-19 01:14:50 +00001148 (outs GPRC:$rA), (ins GPRC:$rS, GPRC:$rB, u5imm:$MB, u5imm:$ME),
Jim Laskey53842142005-10-19 19:51:16 +00001149 "rlwnm $rA, $rS, $rB, $MB, $ME", IntGeneral,
Nate Begeman2d5aff72005-10-19 18:42:01 +00001150 []>;
Chris Lattner88d211f2006-03-12 09:13:49 +00001151}
Nate Begemancc8bd9c2004-08-31 02:28:08 +00001152
Chris Lattner3c0f9cc2006-03-20 06:15:45 +00001153
Chris Lattner2eb25172005-09-09 00:39:56 +00001154//===----------------------------------------------------------------------===//
Jim Laskeyf5395ce2005-12-16 22:45:29 +00001155// DWARF Pseudo Instructions
1156//
1157
Evan Cheng64d80e32007-07-19 01:14:50 +00001158def DWARF_LOC : Pseudo<(outs), (ins i32imm:$line, i32imm:$col, i32imm:$file),
Chris Lattner54689662006-09-27 02:55:21 +00001159 "${:comment} .loc $file, $line, $col",
Jim Laskeyf5395ce2005-12-16 22:45:29 +00001160 [(dwarf_loc (i32 imm:$line), (i32 imm:$col),
Jim Laskeyabf6d172006-01-05 01:25:28 +00001161 (i32 imm:$file))]>;
1162
Jim Laskeyf5395ce2005-12-16 22:45:29 +00001163//===----------------------------------------------------------------------===//
Chris Lattner2eb25172005-09-09 00:39:56 +00001164// PowerPC Instruction Patterns
1165//
1166
Chris Lattner30e21a42005-09-26 22:20:16 +00001167// Arbitrary immediate support. Implement in terms of LIS/ORI.
1168def : Pat<(i32 imm:$imm),
1169 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))>;
Chris Lattner91da8622005-09-28 17:13:15 +00001170
1171// Implement the 'not' operation with the NOR instruction.
1172def NOT : Pat<(not GPRC:$in),
1173 (NOR GPRC:$in, GPRC:$in)>;
1174
Chris Lattner79d0e9f2005-09-28 23:07:13 +00001175// ADD an arbitrary immediate.
1176def : Pat<(add GPRC:$in, imm:$imm),
1177 (ADDIS (ADDI GPRC:$in, (LO16 imm:$imm)), (HA16 imm:$imm))>;
1178// OR an arbitrary immediate.
Chris Lattner2eb25172005-09-09 00:39:56 +00001179def : Pat<(or GPRC:$in, imm:$imm),
1180 (ORIS (ORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
Chris Lattner79d0e9f2005-09-28 23:07:13 +00001181// XOR an arbitrary immediate.
Chris Lattner2eb25172005-09-09 00:39:56 +00001182def : Pat<(xor GPRC:$in, imm:$imm),
1183 (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
Nate Begeman551bf3f2006-02-17 05:43:56 +00001184// SUBFIC
Nate Begeman79691bc2006-03-17 22:41:37 +00001185def : Pat<(sub immSExt16:$imm, GPRC:$in),
Nate Begeman551bf3f2006-02-17 05:43:56 +00001186 (SUBFIC GPRC:$in, imm:$imm)>;
Chris Lattner8be1fa52005-10-19 01:38:02 +00001187
Chris Lattner956f43c2006-06-16 20:22:01 +00001188// SHL/SRL
Chris Lattnerbd059822005-12-05 02:34:05 +00001189def : Pat<(shl GPRC:$in, (i32 imm:$imm)),
Nate Begeman2d5aff72005-10-19 18:42:01 +00001190 (RLWINM GPRC:$in, imm:$imm, 0, (SHL32 imm:$imm))>;
Chris Lattnerbd059822005-12-05 02:34:05 +00001191def : Pat<(srl GPRC:$in, (i32 imm:$imm)),
Nate Begeman2d5aff72005-10-19 18:42:01 +00001192 (RLWINM GPRC:$in, (SRL32 imm:$imm), imm:$imm, 31)>;
Nate Begeman2d5aff72005-10-19 18:42:01 +00001193
Nate Begeman35ef9132006-01-11 21:21:00 +00001194// ROTL
1195def : Pat<(rotl GPRC:$in, GPRC:$sh),
1196 (RLWNM GPRC:$in, GPRC:$sh, 0, 31)>;
1197def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
1198 (RLWINM GPRC:$in, imm:$imm, 0, 31)>;
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001199
Nate Begemanf42f1332006-09-22 05:01:56 +00001200// RLWNM
1201def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
1202 (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
1203
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001204// Calls
Chris Lattner9f0bc652007-02-25 05:34:32 +00001205def : Pat<(PPCcall_Macho (i32 tglobaladdr:$dst)),
1206 (BL_Macho tglobaladdr:$dst)>;
Chris Lattner1fa3d9e2007-02-25 19:20:53 +00001207def : Pat<(PPCcall_Macho (i32 texternalsym:$dst)),
1208 (BL_Macho texternalsym:$dst)>;
Nicolas Geoffray63f8fb12007-02-27 13:01:19 +00001209def : Pat<(PPCcall_ELF (i32 tglobaladdr:$dst)),
Chris Lattner1fa3d9e2007-02-25 19:20:53 +00001210 (BL_ELF tglobaladdr:$dst)>;
Chris Lattner9f0bc652007-02-25 05:34:32 +00001211def : Pat<(PPCcall_ELF (i32 texternalsym:$dst)),
Nicolas Geoffray63f8fb12007-02-27 13:01:19 +00001212 (BL_ELF texternalsym:$dst)>;
Chris Lattnerc703a8f2006-05-17 19:00:46 +00001213
Chris Lattner860e8862005-11-17 07:30:41 +00001214// Hi and Lo for Darwin Global Addresses.
Chris Lattnerd717b192005-12-11 07:45:47 +00001215def : Pat<(PPChi tglobaladdr:$in, 0), (LIS tglobaladdr:$in)>;
1216def : Pat<(PPClo tglobaladdr:$in, 0), (LI tglobaladdr:$in)>;
1217def : Pat<(PPChi tconstpool:$in, 0), (LIS tconstpool:$in)>;
1218def : Pat<(PPClo tconstpool:$in, 0), (LI tconstpool:$in)>;
Nate Begeman37efe672006-04-22 18:53:45 +00001219def : Pat<(PPChi tjumptable:$in, 0), (LIS tjumptable:$in)>;
1220def : Pat<(PPClo tjumptable:$in, 0), (LI tjumptable:$in)>;
Chris Lattner490ad082005-11-17 17:52:01 +00001221def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
1222 (ADDIS GPRC:$in, tglobaladdr:$g)>;
Nate Begeman28a6b022005-12-10 02:36:00 +00001223def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
1224 (ADDIS GPRC:$in, tconstpool:$g)>;
Nate Begeman37efe672006-04-22 18:53:45 +00001225def : Pat<(add GPRC:$in, (PPChi tjumptable:$g, 0)),
1226 (ADDIS GPRC:$in, tjumptable:$g)>;
Chris Lattner860e8862005-11-17 07:30:41 +00001227
Nate Begemana07da922005-12-14 22:54:33 +00001228// Fused negative multiply subtract, alternate pattern
1229def : Pat<(fsub F8RC:$B, (fmul F8RC:$A, F8RC:$C)),
1230 (FNMSUB F8RC:$A, F8RC:$C, F8RC:$B)>,
1231 Requires<[FPContractions]>;
1232def : Pat<(fsub F4RC:$B, (fmul F4RC:$A, F4RC:$C)),
1233 (FNMSUBS F4RC:$A, F4RC:$C, F4RC:$B)>,
1234 Requires<[FPContractions]>;
1235
Chris Lattner4172b102005-12-06 02:10:38 +00001236// Standard shifts. These are represented separately from the real shifts above
1237// so that we can distinguish between shifts that allow 5-bit and 6-bit shift
1238// amounts.
1239def : Pat<(sra GPRC:$rS, GPRC:$rB),
1240 (SRAW GPRC:$rS, GPRC:$rB)>;
1241def : Pat<(srl GPRC:$rS, GPRC:$rB),
1242 (SRW GPRC:$rS, GPRC:$rB)>;
1243def : Pat<(shl GPRC:$rS, GPRC:$rB),
1244 (SLW GPRC:$rS, GPRC:$rB)>;
1245
Evan Cheng466685d2006-10-09 20:57:25 +00001246def : Pat<(zextloadi1 iaddr:$src),
Nate Begeman7fd1edd2005-12-19 23:25:09 +00001247 (LBZ iaddr:$src)>;
Evan Cheng466685d2006-10-09 20:57:25 +00001248def : Pat<(zextloadi1 xaddr:$src),
Nate Begeman7fd1edd2005-12-19 23:25:09 +00001249 (LBZX xaddr:$src)>;
Evan Cheng466685d2006-10-09 20:57:25 +00001250def : Pat<(extloadi1 iaddr:$src),
Nate Begeman7fd1edd2005-12-19 23:25:09 +00001251 (LBZ iaddr:$src)>;
Evan Cheng466685d2006-10-09 20:57:25 +00001252def : Pat<(extloadi1 xaddr:$src),
Nate Begeman7fd1edd2005-12-19 23:25:09 +00001253 (LBZX xaddr:$src)>;
Evan Cheng466685d2006-10-09 20:57:25 +00001254def : Pat<(extloadi8 iaddr:$src),
Nate Begeman7fd1edd2005-12-19 23:25:09 +00001255 (LBZ iaddr:$src)>;
Evan Cheng466685d2006-10-09 20:57:25 +00001256def : Pat<(extloadi8 xaddr:$src),
Nate Begeman7fd1edd2005-12-19 23:25:09 +00001257 (LBZX xaddr:$src)>;
Evan Cheng466685d2006-10-09 20:57:25 +00001258def : Pat<(extloadi16 iaddr:$src),
Nate Begeman7fd1edd2005-12-19 23:25:09 +00001259 (LHZ iaddr:$src)>;
Evan Cheng466685d2006-10-09 20:57:25 +00001260def : Pat<(extloadi16 xaddr:$src),
Nate Begeman7fd1edd2005-12-19 23:25:09 +00001261 (LHZX xaddr:$src)>;
Evan Cheng466685d2006-10-09 20:57:25 +00001262def : Pat<(extloadf32 iaddr:$src),
Nate Begeman7fd1edd2005-12-19 23:25:09 +00001263 (FMRSD (LFS iaddr:$src))>;
Evan Cheng466685d2006-10-09 20:57:25 +00001264def : Pat<(extloadf32 xaddr:$src),
Nate Begeman7fd1edd2005-12-19 23:25:09 +00001265 (FMRSD (LFSX xaddr:$src))>;
1266
Evan Cheng54fc97d2008-04-19 01:30:48 +00001267// Atomic operations
Evan Cheng8608f2e2008-04-19 02:30:38 +00001268def : Pat<(PPCcmp_unres immSExt16:$imm, GPRC:$rA, imm:$label),
1269 (CMP_UNRESwi GPRC:$rA, immSExt16:$imm, imm:$label)>;
Evan Cheng54fc97d2008-04-19 01:30:48 +00001270
Chris Lattnerb22a04d2006-03-25 07:51:43 +00001271include "PPCInstrAltivec.td"
Chris Lattner956f43c2006-06-16 20:22:01 +00001272include "PPCInstr64Bit.td"