blob: 014065af60dcc4a4eae0bac7b72eea267233108c [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_H__
29#define __RADEON_H__
30
Jerome Glisse771fe6b2009-06-05 14:42:42 +020031/* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
34 * related to surface
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
43 */
44
Jerome Glissed39c3b82009-09-28 18:34:43 +020045/* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
61 */
62
Arun Sharma600634972011-07-26 16:09:06 -070063#include <linux/atomic.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020064#include <linux/wait.h>
65#include <linux/list.h>
66#include <linux/kref.h>
67
Jerome Glisse4c788672009-11-20 14:29:23 +010068#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
Thomas Hellstrom147666f2010-11-17 12:38:32 +000072#include <ttm/ttm_execbuf_util.h>
Jerome Glisse4c788672009-11-20 14:29:23 +010073
Dave Airliec2142712009-09-22 08:50:10 +100074#include "radeon_family.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020075#include "radeon_mode.h"
76#include "radeon_reg.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020077
78/*
79 * Modules parameters.
80 */
81extern int radeon_no_wb;
82extern int radeon_modeset;
83extern int radeon_dynclks;
84extern int radeon_r4xx_atom;
85extern int radeon_agpmode;
86extern int radeon_vram_limit;
87extern int radeon_gart_size;
88extern int radeon_benchmarking;
Michel Dänzerecc0b322009-07-21 11:23:57 +020089extern int radeon_testing;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020090extern int radeon_connector_table;
Dave Airlie4ce001a2009-08-13 16:32:14 +100091extern int radeon_tv;
Christian Koenigdafc3bd2009-10-11 23:49:13 +020092extern int radeon_audio;
Alex Deucherf46c0122010-03-31 00:33:27 -040093extern int radeon_disp_priority;
Alex Deuchere2b0a8e2010-03-17 02:07:37 -040094extern int radeon_hw_i2c;
Alex Deucherd42dd572011-01-12 20:05:11 -050095extern int radeon_pcie_gen2;
Alex Deuchera18cee12011-11-01 14:20:30 -040096extern int radeon_msi;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020097
98/*
99 * Copy from radeon_drv.h so we don't have to include both and have conflicting
100 * symbol;
101 */
102#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
Jerome Glisse225758d2010-03-09 14:45:10 +0000103#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
Jerome Glissee8217672010-02-15 21:36:13 +0100104/* RADEON_IB_POOL_SIZE must be a power of 2 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200105#define RADEON_IB_POOL_SIZE 16
Michael Wittenc245cb92011-09-16 20:45:30 +0000106#define RADEON_DEBUGFS_MAX_COMPONENTS 32
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200107#define RADEONFB_CONN_LIMIT 4
Yang Zhaof657c2a2009-09-15 12:21:01 +1000108#define RADEON_BIOS_NUM_SCRATCH 8
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200109
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200110/*
111 * Errata workarounds.
112 */
113enum radeon_pll_errata {
114 CHIP_ERRATA_R300_CG = 0x00000001,
115 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
116 CHIP_ERRATA_PLL_DELAY = 0x00000004
117};
118
119
120struct radeon_device;
121
122
123/*
124 * BIOS.
125 */
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000126#define ATRM_BIOS_PAGE 4096
127
Dave Airlie8edb3812010-03-01 21:50:01 +1100128#if defined(CONFIG_VGA_SWITCHEROO)
Dave Airlie6a9ee8a2010-02-01 15:38:10 +1000129bool radeon_atrm_supported(struct pci_dev *pdev);
130int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
Dave Airlie8edb3812010-03-01 21:50:01 +1100131#else
132static inline bool radeon_atrm_supported(struct pci_dev *pdev)
133{
134 return false;
135}
136
137static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
138 return -EINVAL;
139}
140#endif
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200141bool radeon_get_bios(struct radeon_device *rdev);
142
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000143
144/*
145 * Dummy page
146 */
147struct radeon_dummy_page {
148 struct page *page;
149 dma_addr_t addr;
150};
151int radeon_dummy_page_init(struct radeon_device *rdev);
152void radeon_dummy_page_fini(struct radeon_device *rdev);
153
154
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200155/*
156 * Clocks
157 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200158struct radeon_clock {
159 struct radeon_pll p1pll;
160 struct radeon_pll p2pll;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500161 struct radeon_pll dcpll;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200162 struct radeon_pll spll;
163 struct radeon_pll mpll;
164 /* 10 Khz units */
165 uint32_t default_mclk;
166 uint32_t default_sclk;
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500167 uint32_t default_dispclk;
168 uint32_t dp_extclk;
Alex Deucherb20f9be2011-06-08 13:01:11 -0400169 uint32_t max_pixel_clock;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200170};
171
Rafał Miłecki74338742009-11-03 00:53:02 +0100172/*
173 * Power management
174 */
175int radeon_pm_init(struct radeon_device *rdev);
Alex Deucher29fb52c2010-03-11 10:01:17 -0500176void radeon_pm_fini(struct radeon_device *rdev);
Rafał Miłeckic913e232009-12-22 23:02:16 +0100177void radeon_pm_compute_clocks(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -0400178void radeon_pm_suspend(struct radeon_device *rdev);
179void radeon_pm_resume(struct radeon_device *rdev);
Alex Deucher56278a82009-12-28 13:58:44 -0500180void radeon_combios_get_power_modes(struct radeon_device *rdev);
181void radeon_atombios_get_power_modes(struct radeon_device *rdev);
Alex Deucher8a83ec52011-04-12 14:49:23 -0400182void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
Alex Deucheree4017f2011-06-23 12:19:32 -0400183int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
Alex Deucherf8920342010-06-30 12:02:03 -0400184void rs690_pm_info(struct radeon_device *rdev);
Alex Deucher20d391d2011-02-01 16:12:34 -0500185extern int rv6xx_get_temp(struct radeon_device *rdev);
186extern int rv770_get_temp(struct radeon_device *rdev);
187extern int evergreen_get_temp(struct radeon_device *rdev);
188extern int sumo_get_temp(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000189
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200190/*
191 * Fences.
192 */
193struct radeon_fence_driver {
194 uint32_t scratch_reg;
195 atomic_t seq;
196 uint32_t last_seq;
Jerome Glisse225758d2010-03-09 14:45:10 +0000197 unsigned long last_jiffies;
198 unsigned long last_timeout;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200199 wait_queue_head_t queue;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200200 struct list_head created;
Christian König851a6bd2011-10-24 15:05:29 +0200201 struct list_head emitted;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200202 struct list_head signaled;
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100203 bool initialized;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200204};
205
206struct radeon_fence {
207 struct radeon_device *rdev;
208 struct kref kref;
209 struct list_head list;
210 /* protected by radeon_fence.lock */
211 uint32_t seq;
Christian König851a6bd2011-10-24 15:05:29 +0200212 bool emitted;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200213 bool signaled;
Alex Deucher74652802011-08-25 13:39:48 -0400214 /* RB, DMA, etc. */
215 int ring;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200216};
217
Alex Deucher74652802011-08-25 13:39:48 -0400218int radeon_fence_driver_init(struct radeon_device *rdev, int num_rings);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200219void radeon_fence_driver_fini(struct radeon_device *rdev);
Alex Deucher74652802011-08-25 13:39:48 -0400220int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence, int ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200221int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
Alex Deucher74652802011-08-25 13:39:48 -0400222void radeon_fence_process(struct radeon_device *rdev, int ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200223bool radeon_fence_signaled(struct radeon_fence *fence);
224int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
Alex Deucher74652802011-08-25 13:39:48 -0400225int radeon_fence_wait_next(struct radeon_device *rdev, int ring);
226int radeon_fence_wait_last(struct radeon_device *rdev, int ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200227struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
228void radeon_fence_unref(struct radeon_fence **fence);
Christian König47492a22011-10-20 12:38:09 +0200229int radeon_fence_count_emitted(struct radeon_device *rdev, int ring);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200230
Dave Airliee024e112009-06-24 09:48:08 +1000231/*
Christian König15d33322011-09-15 19:02:22 +0200232 * Semaphores.
233 */
Christian Könige32eb502011-10-23 12:56:27 +0200234struct radeon_ring;
Christian König7b1f2482011-09-23 15:11:23 +0200235
Christian König15d33322011-09-15 19:02:22 +0200236struct radeon_semaphore_driver {
237 rwlock_t lock;
238 struct list_head free;
239};
240
241struct radeon_semaphore {
242 struct radeon_bo *robj;
243 struct list_head list;
244 uint64_t gpu_addr;
245};
246
247void radeon_semaphore_driver_fini(struct radeon_device *rdev);
248int radeon_semaphore_create(struct radeon_device *rdev,
249 struct radeon_semaphore **semaphore);
250void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
251 struct radeon_semaphore *semaphore);
252void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
253 struct radeon_semaphore *semaphore);
254void radeon_semaphore_free(struct radeon_device *rdev,
255 struct radeon_semaphore *semaphore);
256
257/*
Dave Airliee024e112009-06-24 09:48:08 +1000258 * Tiling registers
259 */
260struct radeon_surface_reg {
Jerome Glisse4c788672009-11-20 14:29:23 +0100261 struct radeon_bo *bo;
Dave Airliee024e112009-06-24 09:48:08 +1000262};
263
264#define RADEON_GEM_MAX_SURFACES 8
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200265
266/*
Jerome Glisse4c788672009-11-20 14:29:23 +0100267 * TTM.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200268 */
Jerome Glisse4c788672009-11-20 14:29:23 +0100269struct radeon_mman {
270 struct ttm_bo_global_ref bo_global_ref;
Dave Airlieba4420c2010-03-09 10:56:52 +1000271 struct drm_global_reference mem_global_ref;
Jerome Glisse4c788672009-11-20 14:29:23 +0100272 struct ttm_bo_device bdev;
Jerome Glisse0a0c7592009-12-11 20:36:19 +0100273 bool mem_global_referenced;
274 bool initialized;
Jerome Glisse4c788672009-11-20 14:29:23 +0100275};
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200276
Jerome Glisse4c788672009-11-20 14:29:23 +0100277struct radeon_bo {
278 /* Protected by gem.mutex */
279 struct list_head list;
280 /* Protected by tbo.reserved */
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100281 u32 placements[3];
282 struct ttm_placement placement;
Jerome Glisse4c788672009-11-20 14:29:23 +0100283 struct ttm_buffer_object tbo;
284 struct ttm_bo_kmap_obj kmap;
285 unsigned pin_count;
286 void *kptr;
287 u32 tiling_flags;
288 u32 pitch;
289 int surface_reg;
290 /* Constant after initialization */
291 struct radeon_device *rdev;
Daniel Vetter441921d2011-02-18 17:59:16 +0100292 struct drm_gem_object gem_base;
Jerome Glisse4c788672009-11-20 14:29:23 +0100293};
Daniel Vetter7e4d15d2011-02-18 17:59:17 +0100294#define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
Jerome Glisse4c788672009-11-20 14:29:23 +0100295
296struct radeon_bo_list {
Thomas Hellstrom147666f2010-11-17 12:38:32 +0000297 struct ttm_validate_buffer tv;
Jerome Glisse4c788672009-11-20 14:29:23 +0100298 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200299 uint64_t gpu_offset;
300 unsigned rdomain;
301 unsigned wdomain;
Jerome Glisse4c788672009-11-20 14:29:23 +0100302 u32 tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200303};
304
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200305/*
306 * GEM objects.
307 */
308struct radeon_gem {
Jerome Glisse4c788672009-11-20 14:29:23 +0100309 struct mutex mutex;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200310 struct list_head objects;
311};
312
313int radeon_gem_init(struct radeon_device *rdev);
314void radeon_gem_fini(struct radeon_device *rdev);
315int radeon_gem_object_create(struct radeon_device *rdev, int size,
Jerome Glisse4c788672009-11-20 14:29:23 +0100316 int alignment, int initial_domain,
317 bool discardable, bool kernel,
318 struct drm_gem_object **obj);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200319int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
320 uint64_t *gpu_addr);
321void radeon_gem_object_unpin(struct drm_gem_object *obj);
322
Dave Airlieff72145b2011-02-07 12:16:14 +1000323int radeon_mode_dumb_create(struct drm_file *file_priv,
324 struct drm_device *dev,
325 struct drm_mode_create_dumb *args);
326int radeon_mode_dumb_mmap(struct drm_file *filp,
327 struct drm_device *dev,
328 uint32_t handle, uint64_t *offset_p);
329int radeon_mode_dumb_destroy(struct drm_file *file_priv,
330 struct drm_device *dev,
331 uint32_t handle);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200332
333/*
334 * GART structures, functions & helpers
335 */
336struct radeon_mc;
337
Matt Turnera77f1712009-10-14 00:34:41 -0400338#define RADEON_GPU_PAGE_SIZE 4096
Jerome Glissed594e462010-02-17 21:54:29 +0000339#define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
Alex Deucher003cefe2011-09-16 12:04:08 -0400340#define RADEON_GPU_PAGE_SHIFT 12
Matt Turnera77f1712009-10-14 00:34:41 -0400341
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200342struct radeon_gart {
343 dma_addr_t table_addr;
Jerome Glissec9a1be92011-11-03 11:16:49 -0400344 struct radeon_bo *robj;
345 void *ptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200346 unsigned num_gpu_pages;
347 unsigned num_cpu_pages;
348 unsigned table_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200349 struct page **pages;
350 dma_addr_t *pages_addr;
351 bool ready;
352};
353
354int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
355void radeon_gart_table_ram_free(struct radeon_device *rdev);
356int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
357void radeon_gart_table_vram_free(struct radeon_device *rdev);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400358int radeon_gart_table_vram_pin(struct radeon_device *rdev);
359void radeon_gart_table_vram_unpin(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200360int radeon_gart_init(struct radeon_device *rdev);
361void radeon_gart_fini(struct radeon_device *rdev);
362void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
363 int pages);
364int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
Konrad Rzeszutek Wilkc39d3512010-12-02 11:04:29 -0500365 int pages, struct page **pagelist,
366 dma_addr_t *dma_addr);
Jerome Glissec9a1be92011-11-03 11:16:49 -0400367void radeon_gart_restore(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200368
369
370/*
371 * GPU MC structures, functions & helpers
372 */
373struct radeon_mc {
374 resource_size_t aper_size;
375 resource_size_t aper_base;
376 resource_size_t agp_base;
Dave Airlie7a50f012009-07-21 20:39:30 +1000377 /* for some chips with <= 32MB we need to lie
378 * about vram size near mc fb location */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000379 u64 mc_vram_size;
Jerome Glissed594e462010-02-17 21:54:29 +0000380 u64 visible_vram_size;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000381 u64 gtt_size;
382 u64 gtt_start;
383 u64 gtt_end;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000384 u64 vram_start;
385 u64 vram_end;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200386 unsigned vram_width;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000387 u64 real_vram_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200388 int vram_mtrr;
389 bool vram_is_ddr;
Jerome Glissed594e462010-02-17 21:54:29 +0000390 bool igp_sideport_enabled;
Alex Deucher8d369bb2010-07-15 10:51:10 -0400391 u64 gtt_base_align;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200392};
393
Alex Deucher06b64762010-01-05 11:27:29 -0500394bool radeon_combios_sideport_present(struct radeon_device *rdev);
395bool radeon_atombios_sideport_present(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200396
397/*
398 * GPU scratch registers structures, functions & helpers
399 */
400struct radeon_scratch {
401 unsigned num_reg;
Alex Deucher724c80e2010-08-27 18:25:25 -0400402 uint32_t reg_base;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200403 bool free[32];
404 uint32_t reg[32];
405};
406
407int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
408void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
409
410
411/*
412 * IRQS.
413 */
Alex Deucher6f34be52010-11-21 10:59:01 -0500414
415struct radeon_unpin_work {
416 struct work_struct work;
417 struct radeon_device *rdev;
418 int crtc_id;
419 struct radeon_fence *fence;
420 struct drm_pending_vblank_event *event;
421 struct radeon_bo *old_rbo;
422 u64 new_crtc_base;
423};
424
425struct r500_irq_stat_regs {
426 u32 disp_int;
427};
428
429struct r600_irq_stat_regs {
430 u32 disp_int;
431 u32 disp_int_cont;
432 u32 disp_int_cont2;
433 u32 d1grph_int;
434 u32 d2grph_int;
435};
436
437struct evergreen_irq_stat_regs {
438 u32 disp_int;
439 u32 disp_int_cont;
440 u32 disp_int_cont2;
441 u32 disp_int_cont3;
442 u32 disp_int_cont4;
443 u32 disp_int_cont5;
444 u32 d1grph_int;
445 u32 d2grph_int;
446 u32 d3grph_int;
447 u32 d4grph_int;
448 u32 d5grph_int;
449 u32 d6grph_int;
450};
451
452union radeon_irq_stat_regs {
453 struct r500_irq_stat_regs r500;
454 struct r600_irq_stat_regs r600;
455 struct evergreen_irq_stat_regs evergreen;
456};
457
Ilija Hadzic54bd52062011-10-26 15:43:58 -0400458#define RADEON_MAX_HPD_PINS 6
459#define RADEON_MAX_CRTCS 6
460#define RADEON_MAX_HDMI_BLOCKS 2
461
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200462struct radeon_irq {
463 bool installed;
464 bool sw_int;
Ilija Hadzic54bd52062011-10-26 15:43:58 -0400465 bool crtc_vblank_int[RADEON_MAX_CRTCS];
466 bool pflip[RADEON_MAX_CRTCS];
Rafał Miłecki73a6d3f2010-01-08 00:22:47 +0100467 wait_queue_head_t vblank_queue;
Ilija Hadzic54bd52062011-10-26 15:43:58 -0400468 bool hpd[RADEON_MAX_HPD_PINS];
Alex Deucher2031f772010-04-22 12:52:11 -0400469 bool gui_idle;
470 bool gui_idle_acked;
471 wait_queue_head_t idle_queue;
Ilija Hadzic54bd52062011-10-26 15:43:58 -0400472 bool hdmi[RADEON_MAX_HDMI_BLOCKS];
Dave Airlie1614f8b2009-12-01 16:04:56 +1000473 spinlock_t sw_lock;
474 int sw_refcount;
Alex Deucher6f34be52010-11-21 10:59:01 -0500475 union radeon_irq_stat_regs stat_regs;
Ilija Hadzic54bd52062011-10-26 15:43:58 -0400476 spinlock_t pflip_lock[RADEON_MAX_CRTCS];
477 int pflip_refcount[RADEON_MAX_CRTCS];
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200478};
479
480int radeon_irq_kms_init(struct radeon_device *rdev);
481void radeon_irq_kms_fini(struct radeon_device *rdev);
Dave Airlie1614f8b2009-12-01 16:04:56 +1000482void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
483void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -0500484void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
485void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200486
487/*
Christian Könige32eb502011-10-23 12:56:27 +0200488 * CP & rings.
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200489 */
Alex Deucher74652802011-08-25 13:39:48 -0400490
491/* max number of rings */
492#define RADEON_NUM_RINGS 3
493
494/* internal ring indices */
495/* r1xx+ has gfx CP ring */
496#define RADEON_RING_TYPE_GFX_INDEX 0
497
498/* cayman has 2 compute CP rings */
499#define CAYMAN_RING_TYPE_CP1_INDEX 1
500#define CAYMAN_RING_TYPE_CP2_INDEX 2
501
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200502struct radeon_ib {
503 struct list_head list;
Jerome Glissee8217672010-02-15 21:36:13 +0100504 unsigned idx;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200505 uint64_t gpu_addr;
506 struct radeon_fence *fence;
Jerome Glissee8217672010-02-15 21:36:13 +0100507 uint32_t *ptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200508 uint32_t length_dw;
Jerome Glissee8217672010-02-15 21:36:13 +0100509 bool free;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200510};
511
Dave Airlieecb114a2009-09-15 11:12:56 +1000512/*
513 * locking -
514 * mutex protects scheduled_ibs, ready, alloc_bm
515 */
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200516struct radeon_ib_pool {
517 struct mutex mutex;
Jerome Glisse4c788672009-11-20 14:29:23 +0100518 struct radeon_bo *robj;
Jerome Glisse9f93ed32010-01-28 18:22:31 +0100519 struct list_head bogus_ib;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200520 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
521 bool ready;
Jerome Glissee8217672010-02-15 21:36:13 +0100522 unsigned head_id;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200523};
524
Christian Könige32eb502011-10-23 12:56:27 +0200525struct radeon_ring {
Jerome Glisse4c788672009-11-20 14:29:23 +0100526 struct radeon_bo *ring_obj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200527 volatile uint32_t *ring;
528 unsigned rptr;
Christian König5596a9d2011-10-13 12:48:45 +0200529 unsigned rptr_offs;
530 unsigned rptr_reg;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200531 unsigned wptr;
532 unsigned wptr_old;
Christian König5596a9d2011-10-13 12:48:45 +0200533 unsigned wptr_reg;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200534 unsigned ring_size;
535 unsigned ring_free_dw;
536 int count_dw;
537 uint64_t gpu_addr;
538 uint32_t align_mask;
539 uint32_t ptr_mask;
540 struct mutex mutex;
541 bool ready;
542};
543
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500544/*
545 * R6xx+ IH ring
546 */
547struct r600_ih {
Jerome Glisse4c788672009-11-20 14:29:23 +0100548 struct radeon_bo *ring_obj;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500549 volatile uint32_t *ring;
550 unsigned rptr;
Christian Königbf852792011-10-13 13:19:22 +0200551 unsigned rptr_offs;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500552 unsigned wptr;
553 unsigned wptr_old;
554 unsigned ring_size;
555 uint64_t gpu_addr;
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500556 uint32_t ptr_mask;
557 spinlock_t lock;
558 bool enabled;
559};
560
Ilija Hadzic8eec9d62011-10-12 23:29:40 -0400561struct r600_blit_cp_primitives {
562 void (*set_render_target)(struct radeon_device *rdev, int format,
563 int w, int h, u64 gpu_addr);
564 void (*cp_set_surface_sync)(struct radeon_device *rdev,
565 u32 sync_type, u32 size,
566 u64 mc_addr);
567 void (*set_shaders)(struct radeon_device *rdev);
568 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
569 void (*set_tex_resource)(struct radeon_device *rdev,
570 int format, int w, int h, int pitch,
Alex Deucher9bb77032011-10-22 10:07:09 -0400571 u64 gpu_addr, u32 size);
Ilija Hadzic8eec9d62011-10-12 23:29:40 -0400572 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
573 int x2, int y2);
574 void (*draw_auto)(struct radeon_device *rdev);
575 void (*set_default_state)(struct radeon_device *rdev);
576};
577
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000578struct r600_blit {
Jerome Glisseff82f052010-01-22 15:19:00 +0100579 struct mutex mutex;
Jerome Glisse4c788672009-11-20 14:29:23 +0100580 struct radeon_bo *shader_obj;
Ilija Hadzic8eec9d62011-10-12 23:29:40 -0400581 struct r600_blit_cp_primitives primitives;
582 int max_dim;
583 int ring_size_common;
584 int ring_size_per_loop;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000585 u64 shader_gpu_addr;
586 u32 vs_offset, ps_offset;
587 u32 state_offset;
588 u32 state_len;
589 u32 vb_used, vb_total;
590 struct radeon_ib *vb_ib;
591};
592
Alex Deucher6ddddfe2011-10-14 10:51:22 -0400593void r600_blit_suspend(struct radeon_device *rdev);
594
Christian König7b1f2482011-09-23 15:11:23 +0200595int radeon_ib_get(struct radeon_device *rdev, int ring, struct radeon_ib **ib);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200596void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
597int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
598int radeon_ib_pool_init(struct radeon_device *rdev);
599void radeon_ib_pool_fini(struct radeon_device *rdev);
600int radeon_ib_test(struct radeon_device *rdev);
Jerome Glisse9f93ed32010-01-28 18:22:31 +0100601extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200602/* Ring access between begin & end cannot sleep */
Christian Könige32eb502011-10-23 12:56:27 +0200603int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *cp);
604void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp);
605int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
606int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw);
607void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp);
608void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp);
609void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp);
610int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
611int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size,
Christian König5596a9d2011-10-13 12:48:45 +0200612 unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg);
Christian Könige32eb502011-10-23 12:56:27 +0200613void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200614
615
616/*
617 * CS.
618 */
619struct radeon_cs_reloc {
620 struct drm_gem_object *gobj;
Jerome Glisse4c788672009-11-20 14:29:23 +0100621 struct radeon_bo *robj;
622 struct radeon_bo_list lobj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200623 uint32_t handle;
624 uint32_t flags;
625};
626
627struct radeon_cs_chunk {
628 uint32_t chunk_id;
629 uint32_t length_dw;
Dave Airlie513bcb42009-09-23 16:56:27 +1000630 int kpage_idx[2];
631 uint32_t *kpage[2];
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200632 uint32_t *kdata;
Dave Airlie513bcb42009-09-23 16:56:27 +1000633 void __user *user_ptr;
634 int last_copied_page;
635 int last_page_index;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200636};
637
638struct radeon_cs_parser {
Jerome Glissec8c15ff2010-01-18 13:01:36 +0100639 struct device *dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200640 struct radeon_device *rdev;
641 struct drm_file *filp;
642 /* chunks */
643 unsigned nchunks;
644 struct radeon_cs_chunk *chunks;
645 uint64_t *chunks_array;
646 /* IB */
647 unsigned idx;
648 /* relocations */
649 unsigned nrelocs;
650 struct radeon_cs_reloc *relocs;
651 struct radeon_cs_reloc **relocs_ptr;
652 struct list_head validated;
653 /* indices of various chunks */
654 int chunk_ib_idx;
655 int chunk_relocs_idx;
656 struct radeon_ib *ib;
657 void *track;
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000658 unsigned family;
Marek Olšáke70f2242011-10-25 01:38:45 +0200659 int parser_error;
660 bool keep_tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200661};
662
Dave Airlie513bcb42009-09-23 16:56:27 +1000663extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
664extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
Andi Kleence580fa2011-10-13 16:08:47 -0700665extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
Dave Airlie513bcb42009-09-23 16:56:27 +1000666
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200667struct radeon_cs_packet {
668 unsigned idx;
669 unsigned type;
670 unsigned reg;
671 unsigned opcode;
672 int count;
673 unsigned one_reg_wr;
674};
675
676typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
677 struct radeon_cs_packet *pkt,
678 unsigned idx, unsigned reg);
679typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
680 struct radeon_cs_packet *pkt);
681
682
683/*
684 * AGP
685 */
686int radeon_agp_init(struct radeon_device *rdev);
Dave Airlie0ebf1712009-11-05 15:39:10 +1000687void radeon_agp_resume(struct radeon_device *rdev);
Jerome Glisse10b06122010-05-21 18:48:54 +0200688void radeon_agp_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200689void radeon_agp_fini(struct radeon_device *rdev);
690
691
692/*
693 * Writeback
694 */
695struct radeon_wb {
Jerome Glisse4c788672009-11-20 14:29:23 +0100696 struct radeon_bo *wb_obj;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200697 volatile uint32_t *wb;
698 uint64_t gpu_addr;
Alex Deucher724c80e2010-08-27 18:25:25 -0400699 bool enabled;
Alex Deucherd0f8a852010-09-04 05:04:34 -0400700 bool use_event;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200701};
702
Alex Deucher724c80e2010-08-27 18:25:25 -0400703#define RADEON_WB_SCRATCH_OFFSET 0
704#define RADEON_WB_CP_RPTR_OFFSET 1024
Alex Deucher0c88a022011-03-02 20:07:31 -0500705#define RADEON_WB_CP1_RPTR_OFFSET 1280
706#define RADEON_WB_CP2_RPTR_OFFSET 1536
Alex Deucher724c80e2010-08-27 18:25:25 -0400707#define R600_WB_IH_WPTR_OFFSET 2048
Alex Deucherd0f8a852010-09-04 05:04:34 -0400708#define R600_WB_EVENT_OFFSET 3072
Alex Deucher724c80e2010-08-27 18:25:25 -0400709
Jerome Glissec93bb852009-07-13 21:04:08 +0200710/**
711 * struct radeon_pm - power management datas
712 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
713 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
714 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
715 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
716 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
717 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
718 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
719 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
720 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300721 * @sclk: GPU clock Mhz (core bandwidth depends of this clock)
Jerome Glissec93bb852009-07-13 21:04:08 +0200722 * @needed_bandwidth: current bandwidth needs
723 *
724 * It keeps track of various data needed to take powermanagement decision.
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300725 * Bandwidth need is used to determine minimun clock of the GPU and memory.
Jerome Glissec93bb852009-07-13 21:04:08 +0200726 * Equation between gpu/memory clock and available bandwidth is hw dependent
727 * (type of memory, bus size, efficiency, ...)
728 */
Alex Deucherce8f5372010-05-07 15:10:16 -0400729
730enum radeon_pm_method {
731 PM_METHOD_PROFILE,
732 PM_METHOD_DYNPM,
Rafał Miłeckic913e232009-12-22 23:02:16 +0100733};
Alex Deucherce8f5372010-05-07 15:10:16 -0400734
735enum radeon_dynpm_state {
736 DYNPM_STATE_DISABLED,
737 DYNPM_STATE_MINIMUM,
738 DYNPM_STATE_PAUSED,
Rafael J. Wysocki3f53eb62010-06-17 23:02:27 +0000739 DYNPM_STATE_ACTIVE,
740 DYNPM_STATE_SUSPENDED,
Alex Deucherce8f5372010-05-07 15:10:16 -0400741};
742enum radeon_dynpm_action {
743 DYNPM_ACTION_NONE,
744 DYNPM_ACTION_MINIMUM,
745 DYNPM_ACTION_DOWNCLOCK,
746 DYNPM_ACTION_UPCLOCK,
747 DYNPM_ACTION_DEFAULT
Rafał Miłeckic913e232009-12-22 23:02:16 +0100748};
Alex Deucher56278a82009-12-28 13:58:44 -0500749
750enum radeon_voltage_type {
751 VOLTAGE_NONE = 0,
752 VOLTAGE_GPIO,
753 VOLTAGE_VDDC,
754 VOLTAGE_SW
755};
756
Alex Deucher0ec0e742009-12-23 13:21:58 -0500757enum radeon_pm_state_type {
758 POWER_STATE_TYPE_DEFAULT,
759 POWER_STATE_TYPE_POWERSAVE,
760 POWER_STATE_TYPE_BATTERY,
761 POWER_STATE_TYPE_BALANCED,
762 POWER_STATE_TYPE_PERFORMANCE,
763};
764
Alex Deucherce8f5372010-05-07 15:10:16 -0400765enum radeon_pm_profile_type {
766 PM_PROFILE_DEFAULT,
767 PM_PROFILE_AUTO,
768 PM_PROFILE_LOW,
Alex Deucherc9e75b22010-06-02 17:56:01 -0400769 PM_PROFILE_MID,
Alex Deucherce8f5372010-05-07 15:10:16 -0400770 PM_PROFILE_HIGH,
771};
772
773#define PM_PROFILE_DEFAULT_IDX 0
774#define PM_PROFILE_LOW_SH_IDX 1
Alex Deucherc9e75b22010-06-02 17:56:01 -0400775#define PM_PROFILE_MID_SH_IDX 2
776#define PM_PROFILE_HIGH_SH_IDX 3
777#define PM_PROFILE_LOW_MH_IDX 4
778#define PM_PROFILE_MID_MH_IDX 5
779#define PM_PROFILE_HIGH_MH_IDX 6
780#define PM_PROFILE_MAX 7
Alex Deucherce8f5372010-05-07 15:10:16 -0400781
782struct radeon_pm_profile {
783 int dpms_off_ps_idx;
784 int dpms_on_ps_idx;
785 int dpms_off_cm_idx;
786 int dpms_on_cm_idx;
Alex Deucher516d0e42009-12-23 14:28:05 -0500787};
788
Alex Deucher21a81222010-07-02 12:58:16 -0400789enum radeon_int_thermal_type {
790 THERMAL_TYPE_NONE,
791 THERMAL_TYPE_RV6XX,
792 THERMAL_TYPE_RV770,
793 THERMAL_TYPE_EVERGREEN,
Alex Deuchere33df252010-11-22 17:56:32 -0500794 THERMAL_TYPE_SUMO,
Alex Deucher4fddba12011-01-06 21:19:22 -0500795 THERMAL_TYPE_NI,
Alex Deucher21a81222010-07-02 12:58:16 -0400796};
797
Alex Deucher56278a82009-12-28 13:58:44 -0500798struct radeon_voltage {
799 enum radeon_voltage_type type;
800 /* gpio voltage */
801 struct radeon_gpio_rec gpio;
802 u32 delay; /* delay in usec from voltage drop to sclk change */
803 bool active_high; /* voltage drop is active when bit is high */
804 /* VDDC voltage */
805 u8 vddc_id; /* index into vddc voltage table */
806 u8 vddci_id; /* index into vddci voltage table */
807 bool vddci_enabled;
808 /* r6xx+ sw */
Alex Deucher2feea492011-04-12 14:49:24 -0400809 u16 voltage;
810 /* evergreen+ vddci */
811 u16 vddci;
Alex Deucher56278a82009-12-28 13:58:44 -0500812};
813
Alex Deucherd7311172010-05-03 01:13:14 -0400814/* clock mode flags */
815#define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
816
Alex Deucher56278a82009-12-28 13:58:44 -0500817struct radeon_pm_clock_info {
818 /* memory clock */
819 u32 mclk;
820 /* engine clock */
821 u32 sclk;
822 /* voltage info */
823 struct radeon_voltage voltage;
Alex Deucherd7311172010-05-03 01:13:14 -0400824 /* standardized clock flags */
Alex Deucher56278a82009-12-28 13:58:44 -0500825 u32 flags;
826};
827
Alex Deuchera48b9b42010-04-22 14:03:55 -0400828/* state flags */
Alex Deucherd7311172010-05-03 01:13:14 -0400829#define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
Alex Deuchera48b9b42010-04-22 14:03:55 -0400830
Alex Deucher56278a82009-12-28 13:58:44 -0500831struct radeon_power_state {
Alex Deucher0ec0e742009-12-23 13:21:58 -0500832 enum radeon_pm_state_type type;
Alex Deucher8f3f1c92011-11-04 10:09:43 -0400833 struct radeon_pm_clock_info *clock_info;
Alex Deucher56278a82009-12-28 13:58:44 -0500834 /* number of valid clock modes in this power state */
835 int num_clock_modes;
Alex Deucher56278a82009-12-28 13:58:44 -0500836 struct radeon_pm_clock_info *default_clock_mode;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400837 /* standardized state flags */
838 u32 flags;
Alex Deucher79daedc2010-04-22 14:25:19 -0400839 u32 misc; /* vbios specific flags */
840 u32 misc2; /* vbios specific flags */
841 int pcie_lanes; /* pcie lanes */
Alex Deucher56278a82009-12-28 13:58:44 -0500842};
843
Rafał Miłecki27459322010-02-11 22:16:36 +0000844/*
845 * Some modes are overclocked by very low value, accept them
846 */
847#define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
848
Jerome Glissec93bb852009-07-13 21:04:08 +0200849struct radeon_pm {
Rafał Miłeckic913e232009-12-22 23:02:16 +0100850 struct mutex mutex;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400851 u32 active_crtcs;
852 int active_crtc_count;
Rafał Miłeckic913e232009-12-22 23:02:16 +0100853 int req_vblank;
Rafał Miłecki839461d2010-03-02 22:06:51 +0100854 bool vblank_sync;
Alex Deucher2031f772010-04-22 12:52:11 -0400855 bool gui_idle;
Jerome Glissec93bb852009-07-13 21:04:08 +0200856 fixed20_12 max_bandwidth;
857 fixed20_12 igp_sideport_mclk;
858 fixed20_12 igp_system_mclk;
859 fixed20_12 igp_ht_link_clk;
860 fixed20_12 igp_ht_link_width;
861 fixed20_12 k8_bandwidth;
862 fixed20_12 sideport_bandwidth;
863 fixed20_12 ht_bandwidth;
864 fixed20_12 core_bandwidth;
865 fixed20_12 sclk;
Alex Deucherf47299c2010-03-16 20:54:38 -0400866 fixed20_12 mclk;
Jerome Glissec93bb852009-07-13 21:04:08 +0200867 fixed20_12 needed_bandwidth;
Alex Deucher0975b162011-02-02 18:42:03 -0500868 struct radeon_power_state *power_state;
Alex Deucher56278a82009-12-28 13:58:44 -0500869 /* number of valid power states */
870 int num_power_states;
Alex Deuchera48b9b42010-04-22 14:03:55 -0400871 int current_power_state_index;
872 int current_clock_mode_index;
873 int requested_power_state_index;
874 int requested_clock_mode_index;
875 int default_power_state_index;
876 u32 current_sclk;
877 u32 current_mclk;
Alex Deucher2feea492011-04-12 14:49:24 -0400878 u16 current_vddc;
879 u16 current_vddci;
Alex Deucher9ace9f72011-01-06 21:19:26 -0500880 u32 default_sclk;
881 u32 default_mclk;
Alex Deucher2feea492011-04-12 14:49:24 -0400882 u16 default_vddc;
883 u16 default_vddci;
Alex Deucher29fb52c2010-03-11 10:01:17 -0500884 struct radeon_i2c_chan *i2c_bus;
Alex Deucherce8f5372010-05-07 15:10:16 -0400885 /* selected pm method */
886 enum radeon_pm_method pm_method;
887 /* dynpm power management */
888 struct delayed_work dynpm_idle_work;
889 enum radeon_dynpm_state dynpm_state;
890 enum radeon_dynpm_action dynpm_planned_action;
891 unsigned long dynpm_action_timeout;
892 bool dynpm_can_upclock;
893 bool dynpm_can_downclock;
894 /* profile-based power management */
895 enum radeon_pm_profile_type profile;
896 int profile_index;
897 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
Alex Deucher21a81222010-07-02 12:58:16 -0400898 /* internal thermal controller on rv6xx+ */
899 enum radeon_int_thermal_type int_thermal_type;
900 struct device *int_hwmon_dev;
Jerome Glissec93bb852009-07-13 21:04:08 +0200901};
902
Alex Deuchera4c9e2e2011-11-04 10:09:41 -0400903int radeon_pm_get_type_index(struct radeon_device *rdev,
904 enum radeon_pm_state_type ps_type,
905 int instance);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200906
907/*
908 * Benchmarking
909 */
Ilija Hadzic638dd7d2011-10-12 23:29:39 -0400910void radeon_benchmark(struct radeon_device *rdev, int test_number);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200911
912
913/*
Michel Dänzerecc0b322009-07-21 11:23:57 +0200914 * Testing
915 */
916void radeon_test_moves(struct radeon_device *rdev);
Christian König60a7e392011-09-27 12:31:00 +0200917void radeon_test_ring_sync(struct radeon_device *rdev,
Christian Könige32eb502011-10-23 12:56:27 +0200918 struct radeon_ring *cpA,
919 struct radeon_ring *cpB);
Christian König60a7e392011-09-27 12:31:00 +0200920void radeon_test_syncing(struct radeon_device *rdev);
Michel Dänzerecc0b322009-07-21 11:23:57 +0200921
922
923/*
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200924 * Debugfs
925 */
Christian König4d8bf9a2011-10-24 14:54:54 +0200926struct radeon_debugfs {
927 struct drm_info_list *files;
928 unsigned num_files;
929};
930
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200931int radeon_debugfs_add_files(struct radeon_device *rdev,
932 struct drm_info_list *files,
933 unsigned nfiles);
934int radeon_debugfs_fence_init(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200935
936
937/*
938 * ASIC specific functions.
939 */
940struct radeon_asic {
Jerome Glisse068a1172009-06-17 13:28:30 +0200941 int (*init)(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000942 void (*fini)(struct radeon_device *rdev);
943 int (*resume)(struct radeon_device *rdev);
944 int (*suspend)(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000945 void (*vga_set_state)(struct radeon_device *rdev, bool state);
Christian Könige32eb502011-10-23 12:56:27 +0200946 bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glissea2d07b72010-03-09 14:45:11 +0000947 int (*asic_reset)(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200948 void (*gart_tlb_flush)(struct radeon_device *rdev);
949 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
950 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
951 void (*cp_fini)(struct radeon_device *rdev);
952 void (*cp_disable)(struct radeon_device *rdev);
953 void (*ring_start)(struct radeon_device *rdev);
Christian König4c87bc22011-10-19 19:02:21 +0200954
955 struct {
956 void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
957 void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence);
Christian Könige32eb502011-10-23 12:56:27 +0200958 void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
Christian König4c87bc22011-10-19 19:02:21 +0200959 struct radeon_semaphore *semaphore, bool emit_wait);
960 } ring[RADEON_NUM_RINGS];
961
Christian Könige32eb502011-10-23 12:56:27 +0200962 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200963 int (*irq_set)(struct radeon_device *rdev);
964 int (*irq_process)(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200965 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200966 int (*cs_parse)(struct radeon_cs_parser *p);
967 int (*copy_blit)(struct radeon_device *rdev,
968 uint64_t src_offset,
969 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400970 unsigned num_gpu_pages,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200971 struct radeon_fence *fence);
972 int (*copy_dma)(struct radeon_device *rdev,
973 uint64_t src_offset,
974 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400975 unsigned num_gpu_pages,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200976 struct radeon_fence *fence);
977 int (*copy)(struct radeon_device *rdev,
978 uint64_t src_offset,
979 uint64_t dst_offset,
Alex Deucher003cefe2011-09-16 12:04:08 -0400980 unsigned num_gpu_pages,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200981 struct radeon_fence *fence);
Rafał Miłecki74338742009-11-03 00:53:02 +0100982 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200983 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki74338742009-11-03 00:53:02 +0100984 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200985 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
Alex Deucherc836a412009-12-23 10:07:50 -0500986 int (*get_pcie_lanes)(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200987 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
988 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
Dave Airliee024e112009-06-24 09:48:08 +1000989 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
990 uint32_t tiling_flags, uint32_t pitch,
991 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000992 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
Jerome Glissec93bb852009-07-13 21:04:08 +0200993 void (*bandwidth_update)(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500994 void (*hpd_init)(struct radeon_device *rdev);
995 void (*hpd_fini)(struct radeon_device *rdev);
996 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
997 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
Jerome Glisse062b3892010-02-04 20:36:39 +0100998 /* ioctl hw specific callback. Some hw might want to perform special
999 * operation on specific ioctl. For instance on wait idle some hw
1000 * might want to perform and HDP flush through MMIO as it seems that
1001 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
1002 * through ring.
1003 */
1004 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
Alex Deucherdef9ba92010-04-22 12:39:58 -04001005 bool (*gui_idle)(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -04001006 /* power management */
Alex Deucher49e02b72010-04-23 17:57:27 -04001007 void (*pm_misc)(struct radeon_device *rdev);
1008 void (*pm_prepare)(struct radeon_device *rdev);
1009 void (*pm_finish)(struct radeon_device *rdev);
Alex Deucherce8f5372010-05-07 15:10:16 -04001010 void (*pm_init_profile)(struct radeon_device *rdev);
1011 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
Alex Deucher6f34be52010-11-21 10:59:01 -05001012 /* pageflipping */
1013 void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
1014 u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
1015 void (*post_page_flip)(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001016};
1017
Jerome Glisse21f9a432009-09-11 15:55:33 +02001018/*
1019 * Asic structures
1020 */
Jerome Glisse225758d2010-03-09 14:45:10 +00001021struct r100_gpu_lockup {
1022 unsigned long last_jiffies;
1023 u32 last_cp_rptr;
1024};
1025
Dave Airlie551ebd82009-09-01 15:25:57 +10001026struct r100_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001027 const unsigned *reg_safe_bm;
1028 unsigned reg_safe_bm_size;
1029 u32 hdp_cntl;
1030 struct r100_gpu_lockup lockup;
Dave Airlie551ebd82009-09-01 15:25:57 +10001031};
1032
Jerome Glisse21f9a432009-09-11 15:55:33 +02001033struct r300_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001034 const unsigned *reg_safe_bm;
1035 unsigned reg_safe_bm_size;
1036 u32 resync_scratch;
1037 u32 hdp_cntl;
1038 struct r100_gpu_lockup lockup;
Jerome Glisse21f9a432009-09-11 15:55:33 +02001039};
1040
1041struct r600_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001042 unsigned max_pipes;
1043 unsigned max_tile_pipes;
1044 unsigned max_simds;
1045 unsigned max_backends;
1046 unsigned max_gprs;
1047 unsigned max_threads;
1048 unsigned max_stack_entries;
1049 unsigned max_hw_contexts;
1050 unsigned max_gs_threads;
1051 unsigned sx_max_export_size;
1052 unsigned sx_max_export_pos_size;
1053 unsigned sx_max_export_smx_size;
1054 unsigned sq_num_cf_insts;
1055 unsigned tiling_nbanks;
1056 unsigned tiling_npipes;
1057 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001058 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001059 unsigned backend_map;
Jerome Glisse225758d2010-03-09 14:45:10 +00001060 struct r100_gpu_lockup lockup;
Jerome Glisse21f9a432009-09-11 15:55:33 +02001061};
1062
1063struct rv770_asic {
Jerome Glisse225758d2010-03-09 14:45:10 +00001064 unsigned max_pipes;
1065 unsigned max_tile_pipes;
1066 unsigned max_simds;
1067 unsigned max_backends;
1068 unsigned max_gprs;
1069 unsigned max_threads;
1070 unsigned max_stack_entries;
1071 unsigned max_hw_contexts;
1072 unsigned max_gs_threads;
1073 unsigned sx_max_export_size;
1074 unsigned sx_max_export_pos_size;
1075 unsigned sx_max_export_smx_size;
1076 unsigned sq_num_cf_insts;
1077 unsigned sx_num_of_sets;
1078 unsigned sc_prim_fifo_size;
1079 unsigned sc_hiz_tile_fifo_size;
1080 unsigned sc_earlyz_tile_fifo_fize;
1081 unsigned tiling_nbanks;
1082 unsigned tiling_npipes;
1083 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001084 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001085 unsigned backend_map;
Jerome Glisse225758d2010-03-09 14:45:10 +00001086 struct r100_gpu_lockup lockup;
Jerome Glisse21f9a432009-09-11 15:55:33 +02001087};
1088
Alex Deucher32fcdbf2010-03-24 13:33:47 -04001089struct evergreen_asic {
1090 unsigned num_ses;
1091 unsigned max_pipes;
1092 unsigned max_tile_pipes;
1093 unsigned max_simds;
1094 unsigned max_backends;
1095 unsigned max_gprs;
1096 unsigned max_threads;
1097 unsigned max_stack_entries;
1098 unsigned max_hw_contexts;
1099 unsigned max_gs_threads;
1100 unsigned sx_max_export_size;
1101 unsigned sx_max_export_pos_size;
1102 unsigned sx_max_export_smx_size;
1103 unsigned sq_num_cf_insts;
1104 unsigned sx_num_of_sets;
1105 unsigned sc_prim_fifo_size;
1106 unsigned sc_hiz_tile_fifo_size;
1107 unsigned sc_earlyz_tile_fifo_size;
1108 unsigned tiling_nbanks;
1109 unsigned tiling_npipes;
1110 unsigned tiling_group_size;
Alex Deuchere7aeeba2010-06-04 13:10:12 -04001111 unsigned tile_config;
Alex Deuchere55b9422011-07-15 19:53:52 +00001112 unsigned backend_map;
Alex Deucher17db7042010-12-21 16:05:39 -05001113 struct r100_gpu_lockup lockup;
Alex Deucher32fcdbf2010-03-24 13:33:47 -04001114};
1115
Alex Deucherfecf1d02011-03-02 20:07:29 -05001116struct cayman_asic {
1117 unsigned max_shader_engines;
1118 unsigned max_pipes_per_simd;
1119 unsigned max_tile_pipes;
1120 unsigned max_simds_per_se;
1121 unsigned max_backends_per_se;
1122 unsigned max_texture_channel_caches;
1123 unsigned max_gprs;
1124 unsigned max_threads;
1125 unsigned max_gs_threads;
1126 unsigned max_stack_entries;
1127 unsigned sx_num_of_sets;
1128 unsigned sx_max_export_size;
1129 unsigned sx_max_export_pos_size;
1130 unsigned sx_max_export_smx_size;
1131 unsigned max_hw_contexts;
1132 unsigned sq_num_cf_insts;
1133 unsigned sc_prim_fifo_size;
1134 unsigned sc_hiz_tile_fifo_size;
1135 unsigned sc_earlyz_tile_fifo_size;
1136
1137 unsigned num_shader_engines;
1138 unsigned num_shader_pipes_per_simd;
1139 unsigned num_tile_pipes;
1140 unsigned num_simds_per_se;
1141 unsigned num_backends_per_se;
1142 unsigned backend_disable_mask_per_asic;
1143 unsigned backend_map;
1144 unsigned num_texture_channel_caches;
1145 unsigned mem_max_burst_length_bytes;
1146 unsigned mem_row_size_in_kb;
1147 unsigned shader_engine_tile_size;
1148 unsigned num_gpus;
1149 unsigned multi_gpu_tile_size;
1150
1151 unsigned tile_config;
1152 struct r100_gpu_lockup lockup;
1153};
1154
Jerome Glisse068a1172009-06-17 13:28:30 +02001155union radeon_asic_config {
1156 struct r300_asic r300;
Dave Airlie551ebd82009-09-01 15:25:57 +10001157 struct r100_asic r100;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001158 struct r600_asic r600;
1159 struct rv770_asic rv770;
Alex Deucher32fcdbf2010-03-24 13:33:47 -04001160 struct evergreen_asic evergreen;
Alex Deucherfecf1d02011-03-02 20:07:29 -05001161 struct cayman_asic cayman;
Jerome Glisse068a1172009-06-17 13:28:30 +02001162};
1163
Daniel Vetter0a10c852010-03-11 21:19:14 +00001164/*
1165 * asic initizalization from radeon_asic.c
1166 */
1167void radeon_agp_disable(struct radeon_device *rdev);
1168int radeon_asic_init(struct radeon_device *rdev);
1169
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001170
1171/*
1172 * IOCTL.
1173 */
1174int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1175 struct drm_file *filp);
1176int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1177 struct drm_file *filp);
1178int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1179 struct drm_file *file_priv);
1180int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1181 struct drm_file *file_priv);
1182int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1183 struct drm_file *file_priv);
1184int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1185 struct drm_file *file_priv);
1186int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1187 struct drm_file *filp);
1188int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1189 struct drm_file *filp);
1190int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1191 struct drm_file *filp);
1192int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1193 struct drm_file *filp);
1194int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
Dave Airliee024e112009-06-24 09:48:08 +10001195int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1196 struct drm_file *filp);
1197int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1198 struct drm_file *filp);
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001199
Alex Deucher16cdf042011-10-28 10:30:02 -04001200/* VRAM scratch page for HDP bug, default vram page */
1201struct r600_vram_scratch {
Alex Deucher87cbf8f2010-08-27 13:59:54 -04001202 struct radeon_bo *robj;
1203 volatile uint32_t *ptr;
Alex Deucher16cdf042011-10-28 10:30:02 -04001204 u64 gpu_addr;
Alex Deucher87cbf8f2010-08-27 13:59:54 -04001205};
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001206
Michel Dänzer7a1619b2011-11-10 18:57:26 +01001207
1208/*
1209 * Mutex which allows recursive locking from the same process.
1210 */
1211struct radeon_mutex {
1212 struct mutex mutex;
1213 struct task_struct *owner;
1214 int level;
1215};
1216
1217static inline void radeon_mutex_init(struct radeon_mutex *mutex)
1218{
1219 mutex_init(&mutex->mutex);
1220 mutex->owner = NULL;
1221 mutex->level = 0;
1222}
1223
1224static inline void radeon_mutex_lock(struct radeon_mutex *mutex)
1225{
1226 if (mutex_trylock(&mutex->mutex)) {
1227 /* The mutex was unlocked before, so it's ours now */
1228 mutex->owner = current;
1229 } else if (mutex->owner != current) {
1230 /* Another process locked the mutex, take it */
1231 mutex_lock(&mutex->mutex);
1232 mutex->owner = current;
1233 }
1234 /* Otherwise the mutex was already locked by this process */
1235
1236 mutex->level++;
1237}
1238
1239static inline void radeon_mutex_unlock(struct radeon_mutex *mutex)
1240{
1241 if (--mutex->level > 0)
1242 return;
1243
1244 mutex->owner = NULL;
1245 mutex_unlock(&mutex->mutex);
1246}
1247
1248
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001249/*
1250 * Core structure, functions and helpers.
1251 */
1252typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1253typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1254
1255struct radeon_device {
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001256 struct device *dev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001257 struct drm_device *ddev;
1258 struct pci_dev *pdev;
1259 /* ASIC */
Jerome Glisse068a1172009-06-17 13:28:30 +02001260 union radeon_asic_config config;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001261 enum radeon_family family;
1262 unsigned long flags;
1263 int usec_timeout;
1264 enum radeon_pll_errata pll_errata;
1265 int num_gb_pipes;
Alex Deucherf779b3e2009-08-19 19:11:39 -04001266 int num_z_pipes;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001267 int disp_priority;
1268 /* BIOS */
1269 uint8_t *bios;
1270 bool is_atom_bios;
1271 uint16_t bios_header_start;
Jerome Glisse4c788672009-11-20 14:29:23 +01001272 struct radeon_bo *stollen_vga_memory;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001273 /* Register mmio */
Dave Airlie4c9bc752009-06-29 18:29:12 +10001274 resource_size_t rmmio_base;
1275 resource_size_t rmmio_size;
Benjamin Herrenschmidta0533fb2011-07-13 06:28:12 +00001276 void __iomem *rmmio;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001277 radeon_rreg_t mc_rreg;
1278 radeon_wreg_t mc_wreg;
1279 radeon_rreg_t pll_rreg;
1280 radeon_wreg_t pll_wreg;
Dave Airliede1b2892009-08-12 18:43:14 +10001281 uint32_t pcie_reg_mask;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001282 radeon_rreg_t pciep_rreg;
1283 radeon_wreg_t pciep_wreg;
Alex Deucher351a52a2010-06-30 11:52:50 -04001284 /* io port */
1285 void __iomem *rio_mem;
1286 resource_size_t rio_mem_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001287 struct radeon_clock clock;
1288 struct radeon_mc mc;
1289 struct radeon_gart gart;
1290 struct radeon_mode_info mode_info;
1291 struct radeon_scratch scratch;
1292 struct radeon_mman mman;
Alex Deucher74652802011-08-25 13:39:48 -04001293 rwlock_t fence_lock;
1294 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
Christian König15d33322011-09-15 19:02:22 +02001295 struct radeon_semaphore_driver semaphore_drv;
Christian Könige32eb502011-10-23 12:56:27 +02001296 struct radeon_ring ring[RADEON_NUM_RINGS];
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001297 struct radeon_ib_pool ib_pool;
1298 struct radeon_irq irq;
1299 struct radeon_asic *asic;
1300 struct radeon_gem gem;
Jerome Glissec93bb852009-07-13 21:04:08 +02001301 struct radeon_pm pm;
Yang Zhaof657c2a2009-09-15 12:21:01 +10001302 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
Michel Dänzer7a1619b2011-11-10 18:57:26 +01001303 struct radeon_mutex cs_mutex;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001304 struct radeon_wb wb;
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001305 struct radeon_dummy_page dummy_page;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001306 bool gpu_lockup;
1307 bool shutdown;
1308 bool suspend;
Dave Airliead49f502009-07-10 22:36:26 +10001309 bool need_dma32;
Jerome Glisse733289c2009-09-16 15:24:21 +02001310 bool accel_working;
Dave Airliee024e112009-06-24 09:48:08 +10001311 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001312 const struct firmware *me_fw; /* all family ME firmware */
1313 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001314 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
Alex Deucher0af62b02011-01-06 21:19:31 -05001315 const struct firmware *mc_fw; /* NI MC firmware */
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001316 struct r600_blit r600_blit;
Alex Deucher16cdf042011-10-28 10:30:02 -04001317 struct r600_vram_scratch vram_scratch;
Alex Deucher3e5cb982009-10-16 12:21:24 -04001318 int msi_enabled; /* msi enabled */
Alex Deucherd8f60cf2009-12-01 13:43:46 -05001319 struct r600_ih ih; /* r6/700 interrupt ring */
Alex Deucherd4877cf2009-12-04 16:56:37 -05001320 struct work_struct hotplug_work;
Alex Deucher18917b62010-02-01 16:02:25 -05001321 int num_crtc; /* number of crtcs */
Alex Deucher40bacf12009-12-23 03:23:21 -05001322 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
Matthew Garrett5876dd22010-04-26 15:52:20 -04001323 struct mutex vram_mutex;
Christian Koenigdafc3bd2009-10-11 23:49:13 +02001324
1325 /* audio stuff */
Rafał Miłecki7eea7e92010-06-19 12:24:56 +02001326 bool audio_enabled;
Christian Koenigdafc3bd2009-10-11 23:49:13 +02001327 struct timer_list audio_timer;
1328 int audio_channels;
1329 int audio_rate;
1330 int audio_bits_per_sample;
1331 uint8_t audio_status_bits;
1332 uint8_t audio_category_code;
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001333
Alex Deucherce8f5372010-05-07 15:10:16 -04001334 struct notifier_block acpi_nb;
Marek Olšák9eba4a92011-01-05 05:46:48 +01001335 /* only one userspace can use Hyperz features or CMASK at a time */
Dave Airlieab9e1f52010-07-13 11:11:11 +10001336 struct drm_file *hyperz_filp;
Marek Olšák9eba4a92011-01-05 05:46:48 +01001337 struct drm_file *cmask_filp;
Alex Deucherf376b942010-08-05 21:21:16 -04001338 /* i2c buses */
1339 struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
Christian König4d8bf9a2011-10-24 14:54:54 +02001340 /* debugfs */
1341 struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS];
1342 unsigned debugfs_count;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001343};
1344
1345int radeon_device_init(struct radeon_device *rdev,
1346 struct drm_device *ddev,
1347 struct pci_dev *pdev,
1348 uint32_t flags);
1349void radeon_device_fini(struct radeon_device *rdev);
1350int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1351
Andi Kleen6fcbef72011-10-13 16:08:42 -07001352uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1353void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1354u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1355void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
Alex Deucher351a52a2010-06-30 11:52:50 -04001356
Jerome Glisse4c788672009-11-20 14:29:23 +01001357/*
1358 * Cast helper
1359 */
1360#define to_radeon_fence(p) ((struct radeon_fence *)(p))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001361
1362/*
1363 * Registers read & write functions.
1364 */
Benjamin Herrenschmidta0533fb2011-07-13 06:28:12 +00001365#define RREG8(reg) readb((rdev->rmmio) + (reg))
1366#define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1367#define RREG16(reg) readw((rdev->rmmio) + (reg))
1368#define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
Dave Airliede1b2892009-08-12 18:43:14 +10001369#define RREG32(reg) r100_mm_rreg(rdev, (reg))
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001370#define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
Dave Airliede1b2892009-08-12 18:43:14 +10001371#define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001372#define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1373#define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1374#define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1375#define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1376#define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1377#define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
Dave Airliede1b2892009-08-12 18:43:14 +10001378#define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1379#define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
Rafał Miłeckiaa5120d2010-02-18 20:24:28 +00001380#define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1381#define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001382#define WREG32_P(reg, val, mask) \
1383 do { \
1384 uint32_t tmp_ = RREG32(reg); \
1385 tmp_ &= (mask); \
1386 tmp_ |= ((val) & ~(mask)); \
1387 WREG32(reg, tmp_); \
1388 } while (0)
1389#define WREG32_PLL_P(reg, val, mask) \
1390 do { \
1391 uint32_t tmp_ = RREG32_PLL(reg); \
1392 tmp_ &= (mask); \
1393 tmp_ |= ((val) & ~(mask)); \
1394 WREG32_PLL(reg, tmp_); \
1395 } while (0)
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001396#define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
Alex Deucher351a52a2010-06-30 11:52:50 -04001397#define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1398#define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001399
Dave Airliede1b2892009-08-12 18:43:14 +10001400/*
1401 * Indirect registers accessor
1402 */
1403static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1404{
1405 uint32_t r;
1406
1407 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1408 r = RREG32(RADEON_PCIE_DATA);
1409 return r;
1410}
1411
1412static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1413{
1414 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1415 WREG32(RADEON_PCIE_DATA, (v));
1416}
1417
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001418void r100_pll_errata_after_index(struct radeon_device *rdev);
1419
1420
1421/*
1422 * ASICs helpers.
1423 */
Dave Airlieb995e432009-07-14 02:02:32 +10001424#define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1425 (rdev->pdev->device == 0x5969))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001426#define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1427 (rdev->family == CHIP_RV200) || \
1428 (rdev->family == CHIP_RS100) || \
1429 (rdev->family == CHIP_RS200) || \
1430 (rdev->family == CHIP_RV250) || \
1431 (rdev->family == CHIP_RV280) || \
1432 (rdev->family == CHIP_RS300))
1433#define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1434 (rdev->family == CHIP_RV350) || \
1435 (rdev->family == CHIP_R350) || \
1436 (rdev->family == CHIP_RV380) || \
1437 (rdev->family == CHIP_R420) || \
1438 (rdev->family == CHIP_R423) || \
1439 (rdev->family == CHIP_RV410) || \
1440 (rdev->family == CHIP_RS400) || \
1441 (rdev->family == CHIP_RS480))
Alex Deucher3313e3d2011-01-06 18:49:34 -05001442#define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1443 (rdev->ddev->pdev->device == 0x9443) || \
1444 (rdev->ddev->pdev->device == 0x944B) || \
1445 (rdev->ddev->pdev->device == 0x9506) || \
1446 (rdev->ddev->pdev->device == 0x9509) || \
1447 (rdev->ddev->pdev->device == 0x950F) || \
1448 (rdev->ddev->pdev->device == 0x689C) || \
1449 (rdev->ddev->pdev->device == 0x689D))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001450#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
Alex Deucher99999aa2010-11-16 12:09:41 -05001451#define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \
1452 (rdev->family == CHIP_RS690) || \
1453 (rdev->family == CHIP_RS740) || \
1454 (rdev->family >= CHIP_R600))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001455#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1456#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
Alex Deucherbcc1c2a2010-01-12 17:54:34 -05001457#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
Alex Deucher633b9162011-01-06 21:19:11 -05001458#define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1459 (rdev->flags & RADEON_IS_IGP))
Alex Deucher1fe18302011-01-06 21:19:12 -05001460#define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001461
1462/*
1463 * BIOS helpers.
1464 */
1465#define RBIOS8(i) (rdev->bios[i])
1466#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1467#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1468
1469int radeon_combios_init(struct radeon_device *rdev);
1470void radeon_combios_fini(struct radeon_device *rdev);
1471int radeon_atombios_init(struct radeon_device *rdev);
1472void radeon_atombios_fini(struct radeon_device *rdev);
1473
1474
1475/*
1476 * RING helpers.
1477 */
Andi Kleence580fa2011-10-13 16:08:47 -07001478#if DRM_DEBUG_CODE == 0
Christian Könige32eb502011-10-23 12:56:27 +02001479static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001480{
Christian Könige32eb502011-10-23 12:56:27 +02001481 ring->ring[ring->wptr++] = v;
1482 ring->wptr &= ring->ptr_mask;
1483 ring->count_dw--;
1484 ring->ring_free_dw--;
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001485}
Andi Kleence580fa2011-10-13 16:08:47 -07001486#else
1487/* With debugging this is just too big to inline */
Christian Könige32eb502011-10-23 12:56:27 +02001488void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
Andi Kleence580fa2011-10-13 16:08:47 -07001489#endif
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001490
1491/*
1492 * ASICs macro.
1493 */
Jerome Glisse068a1172009-06-17 13:28:30 +02001494#define radeon_init(rdev) (rdev)->asic->init((rdev))
Jerome Glisse3ce0a232009-09-08 10:10:24 +10001495#define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1496#define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1497#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001498#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
Dave Airlie28d52042009-09-21 14:33:58 +10001499#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
Christian König7b1f2482011-09-23 15:11:23 +02001500#define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp))
Jerome Glissea2d07b72010-03-09 14:45:11 +00001501#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001502#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1503#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001504#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
Christian König7b1f2482011-09-23 15:11:23 +02001505#define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp))
Christian König4c87bc22011-10-19 19:02:21 +02001506#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001507#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1508#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
Michel Dänzer7ed220d2009-08-13 11:10:51 +02001509#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
Christian König4c87bc22011-10-19 19:02:21 +02001510#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1511#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001512#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1513#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1514#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
Rafał Miłecki74338742009-11-03 00:53:02 +01001515#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001516#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
Rafał Miłecki74338742009-11-03 00:53:02 +01001517#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
Rafał Miłecki93e7de72009-11-04 23:34:10 +01001518#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
Alex Deucherc836a412009-12-23 10:07:50 -05001519#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001520#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1521#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
Dave Airliee024e112009-06-24 09:48:08 +10001522#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1523#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
Jerome Glissec93bb852009-07-13 21:04:08 +02001524#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
Alex Deucher429770b2009-12-04 15:26:55 -05001525#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1526#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1527#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1528#define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
Alex Deucherdef9ba92010-04-22 12:39:58 -04001529#define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
Alex Deuchera4248162010-04-24 14:50:23 -04001530#define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1531#define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1532#define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
Alex Deucherce8f5372010-05-07 15:10:16 -04001533#define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1534#define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
Alex Deucher6f34be52010-11-21 10:59:01 -05001535#define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1536#define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1537#define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001538
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02001539/* Common functions */
Jerome Glisse700a0cc2010-01-13 15:16:38 +01001540/* AGP */
Jerome Glisse90aca4d2010-03-09 14:45:12 +00001541extern int radeon_gpu_reset(struct radeon_device *rdev);
Jerome Glisse700a0cc2010-01-13 15:16:38 +01001542extern void radeon_agp_disable(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001543extern int radeon_modeset_init(struct radeon_device *rdev);
1544extern void radeon_modeset_fini(struct radeon_device *rdev);
Jerome Glisse9f022dd2009-09-11 15:35:22 +02001545extern bool radeon_card_posted(struct radeon_device *rdev);
Alex Deucherf47299c2010-03-16 20:54:38 -04001546extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
Alex Deucherf46c0122010-03-31 00:33:27 -04001547extern void radeon_update_display_priority(struct radeon_device *rdev);
Dave Airlie72542d72009-12-01 14:06:31 +10001548extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001549extern void radeon_scratch_init(struct radeon_device *rdev);
Alex Deucher724c80e2010-08-27 18:25:25 -04001550extern void radeon_wb_fini(struct radeon_device *rdev);
1551extern int radeon_wb_init(struct radeon_device *rdev);
1552extern void radeon_wb_disable(struct radeon_device *rdev);
Jerome Glisse21f9a432009-09-11 15:55:33 +02001553extern void radeon_surface_init(struct radeon_device *rdev);
1554extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
Jerome Glisseca6ffc62009-10-01 10:20:52 +02001555extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
Jerome Glissed39c3b82009-09-28 18:34:43 +02001556extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
Jerome Glisse312ea8d2009-12-07 15:52:58 +01001557extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
Jerome Glissed03d8582009-12-14 21:02:09 +01001558extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
Jerome Glissed594e462010-02-17 21:54:29 +00001559extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1560extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
Dave Airlie6a9ee8a2010-02-01 15:38:10 +10001561extern int radeon_resume_kms(struct drm_device *dev);
1562extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
Dave Airlie53595332011-03-14 09:47:24 +10001563extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
Jerome Glisse6cf8a3f2009-09-10 21:46:48 +02001564
Daniel Vetter3574dda2011-02-18 17:59:19 +01001565/*
Alex Deucher16cdf042011-10-28 10:30:02 -04001566 * R600 vram scratch functions
1567 */
1568int r600_vram_scratch_init(struct radeon_device *rdev);
1569void r600_vram_scratch_fini(struct radeon_device *rdev);
1570
1571/*
Daniel Vetter3574dda2011-02-18 17:59:19 +01001572 * r600 functions used by radeon_encoder.c
1573 */
Rafał Miłecki2cd6218c2010-03-08 22:14:01 +00001574extern void r600_hdmi_enable(struct drm_encoder *encoder);
1575extern void r600_hdmi_disable(struct drm_encoder *encoder);
Christian Koenigdafc3bd2009-10-11 23:49:13 +02001576extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
Alex Deucherfe251e22010-03-24 13:36:43 -04001577
Alex Deucher0af62b02011-01-06 21:19:31 -05001578extern int ni_init_microcode(struct radeon_device *rdev);
Alex Deucher755d8192011-03-02 20:07:34 -05001579extern int ni_mc_load_microcode(struct radeon_device *rdev);
Alex Deucher0af62b02011-01-06 21:19:31 -05001580
Alberto Miloned7a29522010-07-06 11:40:24 -04001581/* radeon_acpi.c */
1582#if defined(CONFIG_ACPI)
1583extern int radeon_acpi_init(struct radeon_device *rdev);
1584#else
1585static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1586#endif
1587
Jerome Glisse4c788672009-11-20 14:29:23 +01001588#include "radeon_object.h"
1589
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001590#endif