blob: 54c7d9202e814cefe36e6c914b2be8baaaa7a09d [file] [log] [blame]
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001/*
2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.c
Jiri Pirko22a67762017-02-03 10:29:07 +01003 * Copyright (c) 2015-2017 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2017 Jiri Pirko <jiri@mellanox.com>
Jiri Pirko56ade8f2015-10-16 14:01:37 +02005 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 *
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
19 *
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/types.h>
Jiri Pirko1d20d232016-10-27 15:12:59 +020040#include <linux/pci.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020041#include <linux/netdevice.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/slab.h>
45#include <linux/device.h>
46#include <linux/skbuff.h>
47#include <linux/if_vlan.h>
48#include <linux/if_bridge.h>
49#include <linux/workqueue.h>
50#include <linux/jiffies.h>
51#include <linux/bitops.h>
Ido Schimmel7f71eb42015-12-15 16:03:37 +010052#include <linux/list.h>
Ido Schimmel80bedf12016-06-20 23:03:59 +020053#include <linux/notifier.h>
Ido Schimmel90183b92016-04-06 17:10:08 +020054#include <linux/dcbnl.h>
Ido Schimmel99724c12016-07-04 08:23:14 +020055#include <linux/inetdevice.h>
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +020056#include <linux/netlink.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020057#include <net/switchdev.h>
Yotam Gigi763b4b72016-07-21 12:03:17 +020058#include <net/pkt_cls.h>
59#include <net/tc_act/tc_mirred.h>
Jiri Pirkoe7322632016-09-01 10:37:43 +020060#include <net/netevent.h>
Yotam Gigi98d0f7b2017-01-23 11:07:11 +010061#include <net/tc_act/tc_sample.h>
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +020062#include <net/addrconf.h>
Jiri Pirko56ade8f2015-10-16 14:01:37 +020063
64#include "spectrum.h"
Jiri Pirko1d20d232016-10-27 15:12:59 +020065#include "pci.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020066#include "core.h"
67#include "reg.h"
68#include "port.h"
69#include "trap.h"
70#include "txheader.h"
Arkadi Sharshevskyff7b0d22017-03-11 09:42:51 +010071#include "spectrum_cnt.h"
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +020072#include "spectrum_dpipe.h"
Yotam Gigid3b939b2017-09-19 10:00:09 +020073#include "spectrum_acl_flex_actions.h"
Yotam Gigie5e5c882017-05-23 21:56:27 +020074#include "../mlxfw/mlxfw.h"
Jiri Pirko56ade8f2015-10-16 14:01:37 +020075
Yotam Gigi6b742192017-05-23 21:56:29 +020076#define MLXSW_FWREV_MAJOR 13
Shalom Toledo2f53fbd2017-11-12 09:01:24 +010077#define MLXSW_FWREV_MINOR 1530
78#define MLXSW_FWREV_SUBMINOR 152
Yotam Gigi6b742192017-05-23 21:56:29 +020079
80static const struct mlxsw_fw_rev mlxsw_sp_supported_fw_rev = {
81 .major = MLXSW_FWREV_MAJOR,
82 .minor = MLXSW_FWREV_MINOR,
83 .subminor = MLXSW_FWREV_SUBMINOR
84};
85
86#define MLXSW_SP_FW_FILENAME \
Yotam Gigia4e1ce22017-06-04 16:49:58 +020087 "mellanox/mlxsw_spectrum-" __stringify(MLXSW_FWREV_MAJOR) \
Yotam Gigi6b742192017-05-23 21:56:29 +020088 "." __stringify(MLXSW_FWREV_MINOR) \
89 "." __stringify(MLXSW_FWREV_SUBMINOR) ".mfa2"
90
Jiri Pirko56ade8f2015-10-16 14:01:37 +020091static const char mlxsw_sp_driver_name[] = "mlxsw_spectrum";
92static const char mlxsw_sp_driver_version[] = "1.0";
93
94/* tx_hdr_version
95 * Tx header version.
96 * Must be set to 1.
97 */
98MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
99
100/* tx_hdr_ctl
101 * Packet control type.
102 * 0 - Ethernet control (e.g. EMADs, LACP)
103 * 1 - Ethernet data
104 */
105MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
106
107/* tx_hdr_proto
108 * Packet protocol type. Must be set to 1 (Ethernet).
109 */
110MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
111
112/* tx_hdr_rx_is_router
113 * Packet is sent from the router. Valid for data packets only.
114 */
115MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
116
117/* tx_hdr_fid_valid
118 * Indicates if the 'fid' field is valid and should be used for
119 * forwarding lookup. Valid for data packets only.
120 */
121MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
122
123/* tx_hdr_swid
124 * Switch partition ID. Must be set to 0.
125 */
126MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
127
128/* tx_hdr_control_tclass
129 * Indicates if the packet should use the control TClass and not one
130 * of the data TClasses.
131 */
132MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
133
134/* tx_hdr_etclass
135 * Egress TClass to be used on the egress device on the egress port.
136 */
137MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
138
139/* tx_hdr_port_mid
140 * Destination local port for unicast packets.
141 * Destination multicast ID for multicast packets.
142 *
143 * Control packets are directed to a specific egress port, while data
144 * packets are transmitted through the CPU port (0) into the switch partition,
145 * where forwarding rules are applied.
146 */
147MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
148
149/* tx_hdr_fid
150 * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
151 * set, otherwise calculated based on the packet's VID using VID to FID mapping.
152 * Valid for data packets only.
153 */
154MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
155
156/* tx_hdr_type
157 * 0 - Data packets
158 * 6 - Control packets
159 */
160MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
161
Yotam Gigie5e5c882017-05-23 21:56:27 +0200162struct mlxsw_sp_mlxfw_dev {
163 struct mlxfw_dev mlxfw_dev;
164 struct mlxsw_sp *mlxsw_sp;
165};
166
167static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
168 u16 component_index, u32 *p_max_size,
169 u8 *p_align_bits, u16 *p_max_write_size)
170{
171 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
172 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
173 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
174 char mcqi_pl[MLXSW_REG_MCQI_LEN];
175 int err;
176
177 mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
178 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
179 if (err)
180 return err;
181 mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
182 p_max_write_size);
183
184 *p_align_bits = max_t(u8, *p_align_bits, 2);
185 *p_max_write_size = min_t(u16, *p_max_write_size,
186 MLXSW_REG_MCDA_MAX_DATA_LEN);
187 return 0;
188}
189
190static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
191{
192 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
193 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
194 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
195 char mcc_pl[MLXSW_REG_MCC_LEN];
196 u8 control_state;
197 int err;
198
199 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
200 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
201 if (err)
202 return err;
203
204 mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
205 if (control_state != MLXFW_FSM_STATE_IDLE)
206 return -EBUSY;
207
208 mlxsw_reg_mcc_pack(mcc_pl,
209 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
210 0, *fwhandle, 0);
211 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
212}
213
214static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
215 u32 fwhandle, u16 component_index,
216 u32 component_size)
217{
218 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
219 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
220 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
221 char mcc_pl[MLXSW_REG_MCC_LEN];
222
223 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
224 component_index, fwhandle, component_size);
225 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
226}
227
228static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
229 u32 fwhandle, u8 *data, u16 size,
230 u32 offset)
231{
232 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
233 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
234 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
235 char mcda_pl[MLXSW_REG_MCDA_LEN];
236
237 mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
238 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
239}
240
241static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
242 u32 fwhandle, u16 component_index)
243{
244 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
245 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
246 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
247 char mcc_pl[MLXSW_REG_MCC_LEN];
248
249 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
250 component_index, fwhandle, 0);
251 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
252}
253
254static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
255{
256 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
257 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
258 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
259 char mcc_pl[MLXSW_REG_MCC_LEN];
260
261 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
262 fwhandle, 0);
263 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
264}
265
266static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
267 enum mlxfw_fsm_state *fsm_state,
268 enum mlxfw_fsm_state_err *fsm_state_err)
269{
270 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
271 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
272 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
273 char mcc_pl[MLXSW_REG_MCC_LEN];
274 u8 control_state;
275 u8 error_code;
276 int err;
277
278 mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
279 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
280 if (err)
281 return err;
282
283 mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
284 *fsm_state = control_state;
285 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
286 MLXFW_FSM_STATE_ERR_MAX);
287 return 0;
288}
289
290static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
291{
292 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
293 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
294 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
295 char mcc_pl[MLXSW_REG_MCC_LEN];
296
297 mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
298 fwhandle, 0);
299 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
300}
301
302static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
303{
304 struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
305 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
306 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
307 char mcc_pl[MLXSW_REG_MCC_LEN];
308
309 mlxsw_reg_mcc_pack(mcc_pl,
310 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
311 fwhandle, 0);
312 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
313}
314
315static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
316 .component_query = mlxsw_sp_component_query,
317 .fsm_lock = mlxsw_sp_fsm_lock,
318 .fsm_component_update = mlxsw_sp_fsm_component_update,
319 .fsm_block_download = mlxsw_sp_fsm_block_download,
320 .fsm_component_verify = mlxsw_sp_fsm_component_verify,
321 .fsm_activate = mlxsw_sp_fsm_activate,
322 .fsm_query_state = mlxsw_sp_fsm_query_state,
323 .fsm_cancel = mlxsw_sp_fsm_cancel,
324 .fsm_release = mlxsw_sp_fsm_release
325};
326
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300327static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
328 const struct firmware *firmware)
329{
330 struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
331 .mlxfw_dev = {
332 .ops = &mlxsw_sp_mlxfw_dev_ops,
333 .psid = mlxsw_sp->bus_info->psid,
334 .psid_size = strlen(mlxsw_sp->bus_info->psid),
335 },
336 .mlxsw_sp = mlxsw_sp
337 };
338
339 return mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev, firmware);
340}
341
Yotam Gigi6b742192017-05-23 21:56:29 +0200342static bool mlxsw_sp_fw_rev_ge(const struct mlxsw_fw_rev *a,
343 const struct mlxsw_fw_rev *b)
344{
345 if (a->major != b->major)
346 return a->major > b->major;
347 if (a->minor != b->minor)
348 return a->minor > b->minor;
349 return a->subminor >= b->subminor;
350}
351
352static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
353{
354 const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
Yotam Gigi6b742192017-05-23 21:56:29 +0200355 const struct firmware *firmware;
356 int err;
357
358 if (mlxsw_sp_fw_rev_ge(rev, &mlxsw_sp_supported_fw_rev))
359 return 0;
360
Ido Schimmeld016e132018-01-10 14:56:54 +0100361 dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is out of date\n",
Yotam Gigi6b742192017-05-23 21:56:29 +0200362 rev->major, rev->minor, rev->subminor);
363 dev_info(mlxsw_sp->bus_info->dev, "Upgrading firmware using file %s\n",
364 MLXSW_SP_FW_FILENAME);
365
366 err = request_firmware_direct(&firmware, MLXSW_SP_FW_FILENAME,
367 mlxsw_sp->bus_info->dev);
368 if (err) {
369 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
370 MLXSW_SP_FW_FILENAME);
371 return err;
372 }
373
Yotam Gigice6ef68f2017-06-01 16:26:46 +0300374 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
Yotam Gigi6b742192017-05-23 21:56:29 +0200375 release_firmware(firmware);
376 return err;
377}
378
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100379int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
380 unsigned int counter_index, u64 *packets,
381 u64 *bytes)
382{
383 char mgpc_pl[MLXSW_REG_MGPC_LEN];
384 int err;
385
386 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200387 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100388 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
389 if (err)
390 return err;
Arkadi Sharshevsky7cfcbc72017-08-24 08:40:08 +0200391 if (packets)
392 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
393 if (bytes)
394 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100395 return 0;
396}
397
398static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
399 unsigned int counter_index)
400{
401 char mgpc_pl[MLXSW_REG_MGPC_LEN];
402
403 mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
Arkadi Sharshevsky6bba7e22017-08-24 08:40:07 +0200404 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
Arkadi Sharshevsky1abcbcc2017-03-11 09:42:53 +0100405 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
406}
407
408int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
409 unsigned int *p_counter_index)
410{
411 int err;
412
413 err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
414 p_counter_index);
415 if (err)
416 return err;
417 err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
418 if (err)
419 goto err_counter_clear;
420 return 0;
421
422err_counter_clear:
423 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
424 *p_counter_index);
425 return err;
426}
427
428void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
429 unsigned int counter_index)
430{
431 mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
432 counter_index);
433}
434
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200435static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
436 const struct mlxsw_tx_info *tx_info)
437{
438 char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
439
440 memset(txhdr, 0, MLXSW_TXHDR_LEN);
441
442 mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
443 mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
444 mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
445 mlxsw_tx_hdr_swid_set(txhdr, 0);
446 mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
447 mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
448 mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
449}
450
Ido Schimmelfe9ccc72017-05-16 19:38:31 +0200451int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
452 u8 state)
453{
454 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
455 enum mlxsw_reg_spms_state spms_state;
456 char *spms_pl;
457 int err;
458
459 switch (state) {
460 case BR_STATE_FORWARDING:
461 spms_state = MLXSW_REG_SPMS_STATE_FORWARDING;
462 break;
463 case BR_STATE_LEARNING:
464 spms_state = MLXSW_REG_SPMS_STATE_LEARNING;
465 break;
466 case BR_STATE_LISTENING: /* fall-through */
467 case BR_STATE_DISABLED: /* fall-through */
468 case BR_STATE_BLOCKING:
469 spms_state = MLXSW_REG_SPMS_STATE_DISCARDING;
470 break;
471 default:
472 BUG();
473 }
474
475 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
476 if (!spms_pl)
477 return -ENOMEM;
478 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
479 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
480
481 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
482 kfree(spms_pl);
483 return err;
484}
485
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200486static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
487{
Elad Raz5b090742016-10-28 21:35:46 +0200488 char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200489 int err;
490
491 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
492 if (err)
493 return err;
494 mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
495 return 0;
496}
497
Yotam Gigi763b4b72016-07-21 12:03:17 +0200498static int mlxsw_sp_span_init(struct mlxsw_sp *mlxsw_sp)
499{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200500 int i;
501
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200502 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_SPAN))
Yotam Gigi763b4b72016-07-21 12:03:17 +0200503 return -EIO;
504
Jiri Pirkoc1a38312016-10-21 16:07:23 +0200505 mlxsw_sp->span.entries_count = MLXSW_CORE_RES_GET(mlxsw_sp->core,
506 MAX_SPAN);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200507 mlxsw_sp->span.entries = kcalloc(mlxsw_sp->span.entries_count,
508 sizeof(struct mlxsw_sp_span_entry),
509 GFP_KERNEL);
510 if (!mlxsw_sp->span.entries)
511 return -ENOMEM;
512
513 for (i = 0; i < mlxsw_sp->span.entries_count; i++)
514 INIT_LIST_HEAD(&mlxsw_sp->span.entries[i].bound_ports_list);
515
516 return 0;
517}
518
519static void mlxsw_sp_span_fini(struct mlxsw_sp *mlxsw_sp)
520{
521 int i;
522
523 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
524 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
525
526 WARN_ON_ONCE(!list_empty(&curr->bound_ports_list));
527 }
528 kfree(mlxsw_sp->span.entries);
529}
530
531static struct mlxsw_sp_span_entry *
532mlxsw_sp_span_entry_create(struct mlxsw_sp_port *port)
533{
534 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
535 struct mlxsw_sp_span_entry *span_entry;
536 char mpat_pl[MLXSW_REG_MPAT_LEN];
537 u8 local_port = port->local_port;
538 int index;
539 int i;
540 int err;
541
542 /* find a free entry to use */
543 index = -1;
544 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
545 if (!mlxsw_sp->span.entries[i].used) {
546 index = i;
547 span_entry = &mlxsw_sp->span.entries[i];
548 break;
549 }
550 }
551 if (index < 0)
552 return NULL;
553
554 /* create a new port analayzer entry for local_port */
555 mlxsw_reg_mpat_pack(mpat_pl, index, local_port, true);
556 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
557 if (err)
558 return NULL;
559
560 span_entry->used = true;
561 span_entry->id = index;
Yotam Gigi2d644d42016-11-11 16:34:25 +0100562 span_entry->ref_count = 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200563 span_entry->local_port = local_port;
564 return span_entry;
565}
566
567static void mlxsw_sp_span_entry_destroy(struct mlxsw_sp *mlxsw_sp,
568 struct mlxsw_sp_span_entry *span_entry)
569{
570 u8 local_port = span_entry->local_port;
571 char mpat_pl[MLXSW_REG_MPAT_LEN];
572 int pa_id = span_entry->id;
573
574 mlxsw_reg_mpat_pack(mpat_pl, pa_id, local_port, false);
575 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpat), mpat_pl);
576 span_entry->used = false;
577}
578
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200579static struct mlxsw_sp_span_entry *
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200580mlxsw_sp_span_entry_find(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200581{
Yotam Gigi763b4b72016-07-21 12:03:17 +0200582 int i;
583
584 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
585 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
586
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200587 if (curr->used && curr->local_port == local_port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200588 return curr;
589 }
590 return NULL;
591}
592
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200593static struct mlxsw_sp_span_entry
594*mlxsw_sp_span_entry_get(struct mlxsw_sp_port *port)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200595{
596 struct mlxsw_sp_span_entry *span_entry;
597
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200598 span_entry = mlxsw_sp_span_entry_find(port->mlxsw_sp,
599 port->local_port);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200600 if (span_entry) {
Yotam Gigi2d644d42016-11-11 16:34:25 +0100601 /* Already exists, just take a reference */
Yotam Gigi763b4b72016-07-21 12:03:17 +0200602 span_entry->ref_count++;
603 return span_entry;
604 }
605
606 return mlxsw_sp_span_entry_create(port);
607}
608
609static int mlxsw_sp_span_entry_put(struct mlxsw_sp *mlxsw_sp,
610 struct mlxsw_sp_span_entry *span_entry)
611{
Yotam Gigi2d644d42016-11-11 16:34:25 +0100612 WARN_ON(!span_entry->ref_count);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200613 if (--span_entry->ref_count == 0)
614 mlxsw_sp_span_entry_destroy(mlxsw_sp, span_entry);
615 return 0;
616}
617
618static bool mlxsw_sp_span_is_egress_mirror(struct mlxsw_sp_port *port)
619{
620 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
621 struct mlxsw_sp_span_inspected_port *p;
622 int i;
623
624 for (i = 0; i < mlxsw_sp->span.entries_count; i++) {
625 struct mlxsw_sp_span_entry *curr = &mlxsw_sp->span.entries[i];
626
627 list_for_each_entry(p, &curr->bound_ports_list, list)
628 if (p->local_port == port->local_port &&
629 p->type == MLXSW_SP_SPAN_EGRESS)
630 return true;
631 }
632
633 return false;
634}
635
Ido Schimmel18281f22017-03-24 08:02:51 +0100636static int mlxsw_sp_span_mtu_to_buffsize(const struct mlxsw_sp *mlxsw_sp,
637 int mtu)
Yotam Gigi763b4b72016-07-21 12:03:17 +0200638{
Ido Schimmel18281f22017-03-24 08:02:51 +0100639 return mlxsw_sp_bytes_cells(mlxsw_sp, mtu * 5 / 2) + 1;
Yotam Gigi763b4b72016-07-21 12:03:17 +0200640}
641
642static int mlxsw_sp_span_port_mtu_update(struct mlxsw_sp_port *port, u16 mtu)
643{
644 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
645 char sbib_pl[MLXSW_REG_SBIB_LEN];
646 int err;
647
648 /* If port is egress mirrored, the shared buffer size should be
649 * updated according to the mtu value
650 */
651 if (mlxsw_sp_span_is_egress_mirror(port)) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100652 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp, mtu);
653
654 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200655 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
656 if (err) {
657 netdev_err(port->dev, "Could not update shared buffer for mirroring\n");
658 return err;
659 }
660 }
661
662 return 0;
663}
664
665static struct mlxsw_sp_span_inspected_port *
666mlxsw_sp_span_entry_bound_port_find(struct mlxsw_sp_port *port,
667 struct mlxsw_sp_span_entry *span_entry)
668{
669 struct mlxsw_sp_span_inspected_port *p;
670
671 list_for_each_entry(p, &span_entry->bound_ports_list, list)
672 if (port->local_port == p->local_port)
673 return p;
674 return NULL;
675}
676
677static int
678mlxsw_sp_span_inspected_port_bind(struct mlxsw_sp_port *port,
679 struct mlxsw_sp_span_entry *span_entry,
680 enum mlxsw_sp_span_type type)
681{
682 struct mlxsw_sp_span_inspected_port *inspected_port;
683 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
684 char mpar_pl[MLXSW_REG_MPAR_LEN];
685 char sbib_pl[MLXSW_REG_SBIB_LEN];
686 int pa_id = span_entry->id;
687 int err;
688
689 /* if it is an egress SPAN, bind a shared buffer to it */
690 if (type == MLXSW_SP_SPAN_EGRESS) {
Ido Schimmel18281f22017-03-24 08:02:51 +0100691 u32 buffsize = mlxsw_sp_span_mtu_to_buffsize(mlxsw_sp,
692 port->dev->mtu);
693
694 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, buffsize);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200695 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
696 if (err) {
697 netdev_err(port->dev, "Could not create shared buffer for mirroring\n");
698 return err;
699 }
700 }
701
702 /* bind the port to the SPAN entry */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200703 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
704 (enum mlxsw_reg_mpar_i_e) type, true, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200705 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
706 if (err)
707 goto err_mpar_reg_write;
708
709 inspected_port = kzalloc(sizeof(*inspected_port), GFP_KERNEL);
710 if (!inspected_port) {
711 err = -ENOMEM;
712 goto err_inspected_port_alloc;
713 }
714 inspected_port->local_port = port->local_port;
715 inspected_port->type = type;
716 list_add_tail(&inspected_port->list, &span_entry->bound_ports_list);
717
718 return 0;
719
720err_mpar_reg_write:
721err_inspected_port_alloc:
722 if (type == MLXSW_SP_SPAN_EGRESS) {
723 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
724 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
725 }
726 return err;
727}
728
729static void
730mlxsw_sp_span_inspected_port_unbind(struct mlxsw_sp_port *port,
731 struct mlxsw_sp_span_entry *span_entry,
732 enum mlxsw_sp_span_type type)
733{
734 struct mlxsw_sp_span_inspected_port *inspected_port;
735 struct mlxsw_sp *mlxsw_sp = port->mlxsw_sp;
736 char mpar_pl[MLXSW_REG_MPAR_LEN];
737 char sbib_pl[MLXSW_REG_SBIB_LEN];
738 int pa_id = span_entry->id;
739
740 inspected_port = mlxsw_sp_span_entry_bound_port_find(port, span_entry);
741 if (!inspected_port)
742 return;
743
744 /* remove the inspected port */
Ido Schimmel1a9234e662016-09-19 08:29:26 +0200745 mlxsw_reg_mpar_pack(mpar_pl, port->local_port,
746 (enum mlxsw_reg_mpar_i_e) type, false, pa_id);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200747 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpar), mpar_pl);
748
749 /* remove the SBIB buffer if it was egress SPAN */
750 if (type == MLXSW_SP_SPAN_EGRESS) {
751 mlxsw_reg_sbib_pack(sbib_pl, port->local_port, 0);
752 mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sbib), sbib_pl);
753 }
754
755 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
756
757 list_del(&inspected_port->list);
758 kfree(inspected_port);
759}
760
761static int mlxsw_sp_span_mirror_add(struct mlxsw_sp_port *from,
762 struct mlxsw_sp_port *to,
763 enum mlxsw_sp_span_type type)
764{
765 struct mlxsw_sp *mlxsw_sp = from->mlxsw_sp;
766 struct mlxsw_sp_span_entry *span_entry;
767 int err;
768
769 span_entry = mlxsw_sp_span_entry_get(to);
770 if (!span_entry)
771 return -ENOENT;
772
773 netdev_dbg(from->dev, "Adding inspected port to SPAN entry %d\n",
774 span_entry->id);
775
776 err = mlxsw_sp_span_inspected_port_bind(from, span_entry, type);
777 if (err)
778 goto err_port_bind;
779
780 return 0;
781
782err_port_bind:
783 mlxsw_sp_span_entry_put(mlxsw_sp, span_entry);
784 return err;
785}
786
787static void mlxsw_sp_span_mirror_remove(struct mlxsw_sp_port *from,
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200788 u8 destination_port,
Yotam Gigi763b4b72016-07-21 12:03:17 +0200789 enum mlxsw_sp_span_type type)
790{
791 struct mlxsw_sp_span_entry *span_entry;
792
Yuval Mintz6399ebc2017-09-12 08:50:53 +0200793 span_entry = mlxsw_sp_span_entry_find(from->mlxsw_sp,
794 destination_port);
Yotam Gigi763b4b72016-07-21 12:03:17 +0200795 if (!span_entry) {
796 netdev_err(from->dev, "no span entry found\n");
797 return;
798 }
799
800 netdev_dbg(from->dev, "removing inspected port from SPAN entry %d\n",
801 span_entry->id);
802 mlxsw_sp_span_inspected_port_unbind(from, span_entry, type);
803}
804
Yotam Gigi98d0f7b2017-01-23 11:07:11 +0100805static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
806 bool enable, u32 rate)
807{
808 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
809 char mpsc_pl[MLXSW_REG_MPSC_LEN];
810
811 mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
812 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
813}
814
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200815static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
816 bool is_up)
817{
818 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
819 char paos_pl[MLXSW_REG_PAOS_LEN];
820
821 mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
822 is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
823 MLXSW_PORT_ADMIN_STATUS_DOWN);
824 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
825}
826
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200827static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
828 unsigned char *addr)
829{
830 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
831 char ppad_pl[MLXSW_REG_PPAD_LEN];
832
833 mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
834 mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
835 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
836}
837
838static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
839{
840 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
841 unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
842
843 ether_addr_copy(addr, mlxsw_sp->base_mac);
844 addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
845 return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
846}
847
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200848static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
849{
850 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
851 char pmtu_pl[MLXSW_REG_PMTU_LEN];
852 int max_mtu;
853 int err;
854
855 mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
856 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
857 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
858 if (err)
859 return err;
860 max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
861
862 if (mtu > max_mtu)
863 return -EINVAL;
864
865 mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
866 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
867}
868
869static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
870{
871 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel5b153852017-06-08 08:47:44 +0200872 char pspa_pl[MLXSW_REG_PSPA_LEN];
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200873
Ido Schimmel5b153852017-06-08 08:47:44 +0200874 mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
875 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200876}
877
Ido Schimmela1107482017-05-26 08:37:39 +0200878int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200879{
880 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
881 char svpe_pl[MLXSW_REG_SVPE_LEN];
882
883 mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
884 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
885}
886
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200887int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
888 bool learn_enable)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200889{
890 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
891 char *spvmlr_pl;
892 int err;
893
894 spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
895 if (!spvmlr_pl)
896 return -ENOMEM;
Ido Schimmel7cbc4272017-05-16 19:38:33 +0200897 mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
898 learn_enable);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200899 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
900 kfree(spvmlr_pl);
901 return err;
902}
903
Ido Schimmelb02eae92017-05-16 19:38:34 +0200904static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
905 u16 vid)
906{
907 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
908 char spvid_pl[MLXSW_REG_SPVID_LEN];
909
910 mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
911 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
912}
913
914static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
915 bool allow)
916{
917 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
918 char spaft_pl[MLXSW_REG_SPAFT_LEN];
919
920 mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
921 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
922}
923
924int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
925{
926 int err;
927
928 if (!vid) {
929 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
930 if (err)
931 return err;
932 } else {
933 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
934 if (err)
935 return err;
936 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
937 if (err)
938 goto err_port_allow_untagged_set;
939 }
940
941 mlxsw_sp_port->pvid = vid;
942 return 0;
943
944err_port_allow_untagged_set:
945 __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
946 return err;
947}
948
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200949static int
950mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
951{
952 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
953 char sspr_pl[MLXSW_REG_SSPR_LEN];
954
955 mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
956 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
957}
958
Ido Schimmeld664b412016-06-09 09:51:40 +0200959static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
960 u8 local_port, u8 *p_module,
961 u8 *p_width, u8 *p_lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200962{
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200963 char pmlp_pl[MLXSW_REG_PMLP_LEN];
964 int err;
965
Ido Schimmel558c2d52016-02-26 17:32:29 +0100966 mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200967 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
968 if (err)
969 return err;
Ido Schimmel558c2d52016-02-26 17:32:29 +0100970 *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
971 *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
Ido Schimmel2bf9a582016-04-05 10:20:04 +0200972 *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +0200973 return 0;
974}
975
Ido Schimmel2e915e02017-06-08 08:47:45 +0200976static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel18f1e702016-02-26 17:32:31 +0100977 u8 module, u8 width, u8 lane)
978{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200979 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel18f1e702016-02-26 17:32:31 +0100980 char pmlp_pl[MLXSW_REG_PMLP_LEN];
981 int i;
982
Ido Schimmel2e915e02017-06-08 08:47:45 +0200983 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel18f1e702016-02-26 17:32:31 +0100984 mlxsw_reg_pmlp_width_set(pmlp_pl, width);
985 for (i = 0; i < width; i++) {
986 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
987 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i); /* Rx & Tx */
988 }
989
990 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
991}
992
Ido Schimmel2e915e02017-06-08 08:47:45 +0200993static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100994{
Ido Schimmel2e915e02017-06-08 08:47:45 +0200995 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100996 char pmlp_pl[MLXSW_REG_PMLP_LEN];
997
Ido Schimmel2e915e02017-06-08 08:47:45 +0200998 mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +0100999 mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
1000 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
1001}
1002
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001003static int mlxsw_sp_port_open(struct net_device *dev)
1004{
1005 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1006 int err;
1007
1008 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1009 if (err)
1010 return err;
1011 netif_start_queue(dev);
1012 return 0;
1013}
1014
1015static int mlxsw_sp_port_stop(struct net_device *dev)
1016{
1017 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1018
1019 netif_stop_queue(dev);
1020 return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1021}
1022
1023static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
1024 struct net_device *dev)
1025{
1026 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1027 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1028 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
1029 const struct mlxsw_tx_info tx_info = {
1030 .local_port = mlxsw_sp_port->local_port,
1031 .is_emad = false,
1032 };
1033 u64 len;
1034 int err;
1035
Jiri Pirko307c2432016-04-08 19:11:22 +02001036 if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001037 return NETDEV_TX_BUSY;
1038
1039 if (unlikely(skb_headroom(skb) < MLXSW_TXHDR_LEN)) {
1040 struct sk_buff *skb_orig = skb;
1041
1042 skb = skb_realloc_headroom(skb, MLXSW_TXHDR_LEN);
1043 if (!skb) {
1044 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1045 dev_kfree_skb_any(skb_orig);
1046 return NETDEV_TX_OK;
1047 }
Arkadi Sharshevsky36bf38d2017-01-12 09:10:37 +01001048 dev_consume_skb_any(skb_orig);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001049 }
1050
1051 if (eth_skb_pad(skb)) {
1052 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1053 return NETDEV_TX_OK;
1054 }
1055
1056 mlxsw_sp_txhdr_construct(skb, &tx_info);
Nogah Frankel63dcdd32016-06-17 15:09:05 +02001057 /* TX header is consumed by HW on the way so we shouldn't count its
1058 * bytes as being sent.
1059 */
1060 len = skb->len - MLXSW_TXHDR_LEN;
1061
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001062 /* Due to a race we might fail here because of a full queue. In that
1063 * unlikely case we simply drop the packet.
1064 */
Jiri Pirko307c2432016-04-08 19:11:22 +02001065 err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001066
1067 if (!err) {
1068 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
1069 u64_stats_update_begin(&pcpu_stats->syncp);
1070 pcpu_stats->tx_packets++;
1071 pcpu_stats->tx_bytes += len;
1072 u64_stats_update_end(&pcpu_stats->syncp);
1073 } else {
1074 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
1075 dev_kfree_skb_any(skb);
1076 }
1077 return NETDEV_TX_OK;
1078}
1079
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001080static void mlxsw_sp_set_rx_mode(struct net_device *dev)
1081{
1082}
1083
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001084static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
1085{
1086 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1087 struct sockaddr *addr = p;
1088 int err;
1089
1090 if (!is_valid_ether_addr(addr->sa_data))
1091 return -EADDRNOTAVAIL;
1092
1093 err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
1094 if (err)
1095 return err;
1096 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1097 return 0;
1098}
1099
Ido Schimmel18281f22017-03-24 08:02:51 +01001100static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
1101 int mtu)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001102{
Ido Schimmel18281f22017-03-24 08:02:51 +01001103 return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001104}
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001105
Ido Schimmelf417f042017-03-24 08:02:50 +01001106#define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
Ido Schimmel18281f22017-03-24 08:02:51 +01001107
1108static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1109 u16 delay)
Ido Schimmelf417f042017-03-24 08:02:50 +01001110{
Ido Schimmel18281f22017-03-24 08:02:51 +01001111 delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
1112 BITS_PER_BYTE));
1113 return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
1114 mtu);
Ido Schimmelf417f042017-03-24 08:02:50 +01001115}
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001116
Ido Schimmel18281f22017-03-24 08:02:51 +01001117/* Maximum delay buffer needed in case of PAUSE frames, in bytes.
Ido Schimmelf417f042017-03-24 08:02:50 +01001118 * Assumes 100m cable and maximum MTU.
1119 */
Ido Schimmel18281f22017-03-24 08:02:51 +01001120#define MLXSW_SP_PAUSE_DELAY 58752
1121
1122static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
1123 u16 delay, bool pfc, bool pause)
Ido Schimmelf417f042017-03-24 08:02:50 +01001124{
1125 if (pfc)
Ido Schimmel18281f22017-03-24 08:02:51 +01001126 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
Ido Schimmelf417f042017-03-24 08:02:50 +01001127 else if (pause)
Ido Schimmel18281f22017-03-24 08:02:51 +01001128 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001129 else
Ido Schimmelf417f042017-03-24 08:02:50 +01001130 return 0;
1131}
1132
1133static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
1134 bool lossy)
1135{
1136 if (lossy)
1137 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
1138 else
1139 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
1140 thres);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001141}
1142
1143int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001144 u8 *prio_tc, bool pause_en,
1145 struct ieee_pfc *my_pfc)
Ido Schimmelff6551e2016-04-06 17:10:03 +02001146{
1147 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001148 u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
1149 u16 delay = !!my_pfc ? my_pfc->delay : 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001150 char pbmc_pl[MLXSW_REG_PBMC_LEN];
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001151 int i, j, err;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001152
1153 mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
1154 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1155 if (err)
1156 return err;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001157
1158 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1159 bool configure = false;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001160 bool pfc = false;
Ido Schimmelf417f042017-03-24 08:02:50 +01001161 bool lossy;
1162 u16 thres;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001163
1164 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
1165 if (prio_tc[j] == i) {
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001166 pfc = pfc_en & BIT(j);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001167 configure = true;
1168 break;
1169 }
1170 }
1171
1172 if (!configure)
1173 continue;
Ido Schimmelf417f042017-03-24 08:02:50 +01001174
1175 lossy = !(pfc || pause_en);
Ido Schimmel18281f22017-03-24 08:02:51 +01001176 thres = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
1177 delay = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay, pfc,
1178 pause_en);
Ido Schimmelf417f042017-03-24 08:02:50 +01001179 mlxsw_sp_pg_buf_pack(pbmc_pl, i, thres + delay, thres, lossy);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001180 }
1181
Ido Schimmelff6551e2016-04-06 17:10:03 +02001182 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
1183}
1184
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001185static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001186 int mtu, bool pause_en)
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001187{
1188 u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
1189 bool dcb_en = !!mlxsw_sp_port->dcb.ets;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001190 struct ieee_pfc *my_pfc;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001191 u8 *prio_tc;
1192
1193 prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001194 my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001195
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001196 return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001197 pause_en, my_pfc);
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02001198}
1199
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001200static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
1201{
1202 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001203 bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001204 int err;
1205
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001206 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001207 if (err)
1208 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001209 err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
1210 if (err)
1211 goto err_span_port_mtu_update;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001212 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
1213 if (err)
1214 goto err_port_mtu_set;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001215 dev->mtu = mtu;
1216 return 0;
Ido Schimmelff6551e2016-04-06 17:10:03 +02001217
1218err_port_mtu_set:
Yotam Gigi763b4b72016-07-21 12:03:17 +02001219 mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1220err_span_port_mtu_update:
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001221 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
Ido Schimmelff6551e2016-04-06 17:10:03 +02001222 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001223}
1224
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001225static int
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001226mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1227 struct rtnl_link_stats64 *stats)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001228{
1229 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1230 struct mlxsw_sp_port_pcpu_stats *p;
1231 u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1232 u32 tx_dropped = 0;
1233 unsigned int start;
1234 int i;
1235
1236 for_each_possible_cpu(i) {
1237 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1238 do {
1239 start = u64_stats_fetch_begin_irq(&p->syncp);
1240 rx_packets = p->rx_packets;
1241 rx_bytes = p->rx_bytes;
1242 tx_packets = p->tx_packets;
1243 tx_bytes = p->tx_bytes;
1244 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1245
1246 stats->rx_packets += rx_packets;
1247 stats->rx_bytes += rx_bytes;
1248 stats->tx_packets += tx_packets;
1249 stats->tx_bytes += tx_bytes;
1250 /* tx_dropped is u32, updated without syncp protection. */
1251 tx_dropped += p->tx_dropped;
1252 }
1253 stats->tx_dropped = tx_dropped;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001254 return 0;
1255}
1256
Or Gerlitz3df5b3c2016-11-22 23:09:54 +02001257static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001258{
1259 switch (attr_id) {
1260 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1261 return true;
1262 }
1263
1264 return false;
1265}
1266
Or Gerlitz4bdcc6c2016-09-20 08:14:08 +03001267static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1268 void *sp)
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001269{
1270 switch (attr_id) {
1271 case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1272 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1273 }
1274
1275 return -EINVAL;
1276}
1277
1278static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1279 int prio, char *ppcnt_pl)
1280{
1281 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1282 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1283
1284 mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1285 return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1286}
1287
1288static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1289 struct rtnl_link_stats64 *stats)
1290{
1291 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1292 int err;
1293
1294 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1295 0, ppcnt_pl);
1296 if (err)
1297 goto out;
1298
1299 stats->tx_packets =
1300 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1301 stats->rx_packets =
1302 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1303 stats->tx_bytes =
1304 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1305 stats->rx_bytes =
1306 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1307 stats->multicast =
1308 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1309
1310 stats->rx_crc_errors =
1311 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1312 stats->rx_frame_errors =
1313 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1314
1315 stats->rx_length_errors = (
1316 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1317 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1318 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1319
1320 stats->rx_errors = (stats->rx_crc_errors +
1321 stats->rx_frame_errors + stats->rx_length_errors);
1322
1323out:
1324 return err;
1325}
1326
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001327static void
1328mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1329 struct mlxsw_sp_port_xstats *xstats)
1330{
1331 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1332 int err, i;
1333
1334 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1335 ppcnt_pl);
1336 if (!err)
1337 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1338
1339 for (i = 0; i < TC_MAX_QUEUE; i++) {
1340 err = mlxsw_sp_port_get_stats_raw(dev,
1341 MLXSW_REG_PPCNT_TC_CONG_TC,
1342 i, ppcnt_pl);
1343 if (!err)
1344 xstats->wred_drop[i] =
1345 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1346
1347 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1348 i, ppcnt_pl);
1349 if (err)
1350 continue;
1351
1352 xstats->backlog[i] =
1353 mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1354 xstats->tail_drop[i] =
1355 mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1356 }
1357}
1358
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001359static void update_stats_cache(struct work_struct *work)
1360{
1361 struct mlxsw_sp_port *mlxsw_sp_port =
1362 container_of(work, struct mlxsw_sp_port,
Nogah Frankel9deef432017-10-26 10:55:32 +02001363 periodic_hw_stats.update_dw.work);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001364
1365 if (!netif_carrier_ok(mlxsw_sp_port->dev))
1366 goto out;
1367
1368 mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
Nogah Frankel9deef432017-10-26 10:55:32 +02001369 &mlxsw_sp_port->periodic_hw_stats.stats);
Nogah Frankel075ab8a2017-11-06 07:23:47 +01001370 mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1371 &mlxsw_sp_port->periodic_hw_stats.xstats);
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001372
1373out:
Nogah Frankel9deef432017-10-26 10:55:32 +02001374 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001375 MLXSW_HW_STATS_UPDATE_TIME);
1376}
1377
1378/* Return the stats from a cache that is updated periodically,
1379 * as this function might get called in an atomic context.
1380 */
stephen hemmingerbc1f4472017-01-06 19:12:52 -08001381static void
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001382mlxsw_sp_port_get_stats64(struct net_device *dev,
1383 struct rtnl_link_stats64 *stats)
1384{
1385 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1386
Nogah Frankel9deef432017-10-26 10:55:32 +02001387 memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001388}
1389
Jiri Pirko93cd0812017-04-18 16:55:35 +02001390static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1391 u16 vid_begin, u16 vid_end,
1392 bool is_member, bool untagged)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001393{
1394 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1395 char *spvm_pl;
1396 int err;
1397
1398 spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1399 if (!spvm_pl)
1400 return -ENOMEM;
1401
1402 mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1403 vid_end, is_member, untagged);
1404 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1405 kfree(spvm_pl);
1406 return err;
1407}
1408
Jiri Pirko93cd0812017-04-18 16:55:35 +02001409int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1410 u16 vid_end, bool is_member, bool untagged)
1411{
1412 u16 vid, vid_e;
1413 int err;
1414
1415 for (vid = vid_begin; vid <= vid_end;
1416 vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1417 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1418 vid_end);
1419
1420 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1421 is_member, untagged);
1422 if (err)
1423 return err;
1424 }
1425
1426 return 0;
1427}
1428
Ido Schimmelc57529e2017-05-26 08:37:31 +02001429static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port)
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001430{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001431 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001432
Ido Schimmelc57529e2017-05-26 08:37:31 +02001433 list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1434 &mlxsw_sp_port->vlans_list, list)
1435 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel7f71eb42015-12-15 16:03:37 +01001436}
1437
Ido Schimmel31a08a52017-05-26 08:37:26 +02001438static struct mlxsw_sp_port_vlan *
1439mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1440{
1441 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001442 bool untagged = vid == 1;
1443 int err;
1444
1445 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1446 if (err)
1447 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001448
1449 mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001450 if (!mlxsw_sp_port_vlan) {
1451 err = -ENOMEM;
1452 goto err_port_vlan_alloc;
1453 }
Ido Schimmel31a08a52017-05-26 08:37:26 +02001454
1455 mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1456 mlxsw_sp_port_vlan->vid = vid;
1457 list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1458
1459 return mlxsw_sp_port_vlan;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001460
1461err_port_vlan_alloc:
1462 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1463 return ERR_PTR(err);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001464}
1465
1466static void
1467mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1468{
Ido Schimmelc57529e2017-05-26 08:37:31 +02001469 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1470 u16 vid = mlxsw_sp_port_vlan->vid;
Ido Schimmel7cbecf22017-05-26 08:37:28 +02001471
Ido Schimmel31a08a52017-05-26 08:37:26 +02001472 list_del(&mlxsw_sp_port_vlan->list);
1473 kfree(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001474 mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1475}
1476
1477struct mlxsw_sp_port_vlan *
1478mlxsw_sp_port_vlan_get(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1479{
1480 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1481
1482 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1483 if (mlxsw_sp_port_vlan)
1484 return mlxsw_sp_port_vlan;
1485
1486 return mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid);
1487}
1488
1489void mlxsw_sp_port_vlan_put(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1490{
Ido Schimmela1107482017-05-26 08:37:39 +02001491 struct mlxsw_sp_fid *fid = mlxsw_sp_port_vlan->fid;
1492
Ido Schimmelc57529e2017-05-26 08:37:31 +02001493 if (mlxsw_sp_port_vlan->bridge_port)
1494 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
Ido Schimmela1107482017-05-26 08:37:39 +02001495 else if (fid)
1496 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001497
1498 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001499}
1500
Ido Schimmel05978482016-08-17 16:39:30 +02001501static int mlxsw_sp_port_add_vid(struct net_device *dev,
1502 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001503{
1504 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001505
1506 /* VLAN 0 is added to HW filter when device goes up, but it is
1507 * reserved in our case, so simply return.
1508 */
1509 if (!vid)
1510 return 0;
1511
Ido Schimmelc57529e2017-05-26 08:37:31 +02001512 return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_get(mlxsw_sp_port, vid));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001513}
1514
Ido Schimmel32d863f2016-07-02 11:00:10 +02001515static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1516 __be16 __always_unused proto, u16 vid)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001517{
1518 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001519 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001520
1521 /* VLAN 0 is removed from HW filter when device goes down, but
1522 * it is reserved in our case, so simply return.
1523 */
1524 if (!vid)
1525 return 0;
1526
Ido Schimmel31a08a52017-05-26 08:37:26 +02001527 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
Ido Schimmelc57529e2017-05-26 08:37:31 +02001528 if (!mlxsw_sp_port_vlan)
Ido Schimmel31a08a52017-05-26 08:37:26 +02001529 return 0;
Ido Schimmelc57529e2017-05-26 08:37:31 +02001530 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
Ido Schimmel31a08a52017-05-26 08:37:26 +02001531
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001532 return 0;
1533}
1534
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001535static int mlxsw_sp_port_get_phys_port_name(struct net_device *dev, char *name,
1536 size_t len)
1537{
1538 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmeld664b412016-06-09 09:51:40 +02001539 u8 module = mlxsw_sp_port->mapping.module;
1540 u8 width = mlxsw_sp_port->mapping.width;
1541 u8 lane = mlxsw_sp_port->mapping.lane;
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001542 int err;
1543
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001544 if (!mlxsw_sp_port->split)
1545 err = snprintf(name, len, "p%d", module + 1);
1546 else
1547 err = snprintf(name, len, "p%ds%d", module + 1,
1548 lane / width);
1549
1550 if (err >= len)
1551 return -EINVAL;
1552
1553 return 0;
1554}
1555
Yotam Gigi763b4b72016-07-21 12:03:17 +02001556static struct mlxsw_sp_port_mall_tc_entry *
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001557mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1558 unsigned long cookie) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001559 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1560
1561 list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1562 if (mall_tc_entry->cookie == cookie)
1563 return mall_tc_entry;
1564
1565 return NULL;
1566}
1567
1568static int
1569mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001570 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001571 const struct tc_action *a,
1572 bool ingress)
1573{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001574 enum mlxsw_sp_span_type span_type;
1575 struct mlxsw_sp_port *to_port;
1576 struct net_device *to_dev;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001577
Cong Wang9f8a7392017-12-05 16:17:26 -08001578 to_dev = tcf_mirred_dev(a);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001579 if (!to_dev) {
1580 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1581 return -EINVAL;
1582 }
1583
1584 if (!mlxsw_sp_port_dev_check(to_dev)) {
1585 netdev_err(mlxsw_sp_port->dev, "Cannot mirror to a non-spectrum port");
Yotam Gigie915ac62017-01-09 11:25:48 +01001586 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001587 }
1588 to_port = netdev_priv(to_dev);
1589
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001590 mirror->to_local_port = to_port->local_port;
1591 mirror->ingress = ingress;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001592 span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001593 return mlxsw_sp_span_mirror_add(mlxsw_sp_port, to_port, span_type);
1594}
Yotam Gigi763b4b72016-07-21 12:03:17 +02001595
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001596static void
1597mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1598 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1599{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001600 enum mlxsw_sp_span_type span_type;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001601
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001602 span_type = mirror->ingress ?
1603 MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
Yuval Mintz6399ebc2017-09-12 08:50:53 +02001604 mlxsw_sp_span_mirror_remove(mlxsw_sp_port, mirror->to_local_port,
1605 span_type);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001606}
1607
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001608static int
1609mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1610 struct tc_cls_matchall_offload *cls,
1611 const struct tc_action *a,
1612 bool ingress)
1613{
1614 int err;
1615
1616 if (!mlxsw_sp_port->sample)
1617 return -EOPNOTSUPP;
1618 if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1619 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1620 return -EEXIST;
1621 }
1622 if (tcf_sample_rate(a) > MLXSW_REG_MPSC_RATE_MAX) {
1623 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1624 return -EOPNOTSUPP;
1625 }
1626
1627 rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1628 tcf_sample_psample_group(a));
1629 mlxsw_sp_port->sample->truncate = tcf_sample_truncate(a);
1630 mlxsw_sp_port->sample->trunc_size = tcf_sample_trunc_size(a);
1631 mlxsw_sp_port->sample->rate = tcf_sample_rate(a);
1632
1633 err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, tcf_sample_rate(a));
1634 if (err)
1635 goto err_port_sample_set;
1636 return 0;
1637
1638err_port_sample_set:
1639 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1640 return err;
1641}
1642
1643static void
1644mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1645{
1646 if (!mlxsw_sp_port->sample)
1647 return;
1648
1649 mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1650 RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1651}
1652
Yotam Gigi763b4b72016-07-21 12:03:17 +02001653static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001654 struct tc_cls_matchall_offload *f,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001655 bool ingress)
1656{
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001657 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001658 __be16 protocol = f->common.protocol;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001659 const struct tc_action *a;
WANG Cong22dc13c2016-08-13 22:35:00 -07001660 LIST_HEAD(actions);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001661 int err;
1662
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001663 if (!tcf_exts_has_one_action(f->exts)) {
Yotam Gigi763b4b72016-07-21 12:03:17 +02001664 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
Yotam Gigie915ac62017-01-09 11:25:48 +01001665 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001666 }
1667
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001668 mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1669 if (!mall_tc_entry)
1670 return -ENOMEM;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001671 mall_tc_entry->cookie = f->cookie;
Ido Schimmel86cb13e2016-07-25 13:12:33 +03001672
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001673 tcf_exts_to_list(f->exts, &actions);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001674 a = list_first_entry(&actions, struct tc_action, list);
1675
1676 if (is_tcf_mirred_egress_mirror(a) && protocol == htons(ETH_P_ALL)) {
1677 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1678
1679 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1680 mirror = &mall_tc_entry->mirror;
1681 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1682 mirror, a, ingress);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001683 } else if (is_tcf_sample(a) && protocol == htons(ETH_P_ALL)) {
1684 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001685 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001686 a, ingress);
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001687 } else {
1688 err = -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001689 }
1690
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001691 if (err)
1692 goto err_add_action;
1693
1694 list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001695 return 0;
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001696
1697err_add_action:
1698 kfree(mall_tc_entry);
1699 return err;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001700}
1701
1702static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001703 struct tc_cls_matchall_offload *f)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001704{
Yotam Gigi763b4b72016-07-21 12:03:17 +02001705 struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001706
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001707 mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
Jiri Pirko9cbf14e2017-08-07 10:15:25 +02001708 f->cookie);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001709 if (!mall_tc_entry) {
1710 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1711 return;
1712 }
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001713 list_del(&mall_tc_entry->list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001714
1715 switch (mall_tc_entry->type) {
1716 case MLXSW_SP_PORT_MALL_MIRROR:
Yotam Gigi65acb5d2017-01-09 11:25:46 +01001717 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1718 &mall_tc_entry->mirror);
Yotam Gigi763b4b72016-07-21 12:03:17 +02001719 break;
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01001720 case MLXSW_SP_PORT_MALL_SAMPLE:
1721 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1722 break;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001723 default:
1724 WARN_ON(1);
1725 }
1726
Yotam Gigi763b4b72016-07-21 12:03:17 +02001727 kfree(mall_tc_entry);
1728}
1729
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001730static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001731 struct tc_cls_matchall_offload *f,
1732 bool ingress)
Yotam Gigi763b4b72016-07-21 12:03:17 +02001733{
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001734 if (f->common.chain_index)
Jiri Pirkoa5fcf8a2017-06-06 17:00:16 +02001735 return -EOPNOTSUPP;
1736
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001737 switch (f->command) {
1738 case TC_CLSMATCHALL_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001739 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001740 ingress);
1741 case TC_CLSMATCHALL_DESTROY:
1742 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1743 return 0;
1744 default:
1745 return -EOPNOTSUPP;
1746 }
1747}
1748
1749static int
1750mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_port *mlxsw_sp_port,
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001751 struct tc_cls_flower_offload *f,
1752 bool ingress)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001753{
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001754 switch (f->command) {
1755 case TC_CLSFLOWER_REPLACE:
Jiri Pirko5fd9fc42017-08-07 10:15:29 +02001756 return mlxsw_sp_flower_replace(mlxsw_sp_port, ingress, f);
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001757 case TC_CLSFLOWER_DESTROY:
1758 mlxsw_sp_flower_destroy(mlxsw_sp_port, ingress, f);
1759 return 0;
1760 case TC_CLSFLOWER_STATS:
1761 return mlxsw_sp_flower_stats(mlxsw_sp_port, ingress, f);
1762 default:
1763 return -EOPNOTSUPP;
1764 }
1765}
1766
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001767static int mlxsw_sp_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
1768 void *cb_priv, bool ingress)
1769{
1770 struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1771
Jiri Pirko44ae12a2017-11-01 11:47:39 +01001772 if (!tc_can_offload(mlxsw_sp_port->dev))
1773 return -EOPNOTSUPP;
1774
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001775 switch (type) {
1776 case TC_SETUP_CLSMATCHALL:
1777 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1778 ingress);
1779 case TC_SETUP_CLSFLOWER:
1780 return mlxsw_sp_setup_tc_cls_flower(mlxsw_sp_port, type_data,
1781 ingress);
1782 default:
1783 return -EOPNOTSUPP;
1784 }
1785}
1786
1787static int mlxsw_sp_setup_tc_block_cb_ig(enum tc_setup_type type,
1788 void *type_data, void *cb_priv)
1789{
1790 return mlxsw_sp_setup_tc_block_cb(type, type_data, cb_priv, true);
1791}
1792
1793static int mlxsw_sp_setup_tc_block_cb_eg(enum tc_setup_type type,
1794 void *type_data, void *cb_priv)
1795{
1796 return mlxsw_sp_setup_tc_block_cb(type, type_data, cb_priv, false);
1797}
1798
1799static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1800 struct tc_block_offload *f)
1801{
1802 tc_setup_cb_t *cb;
1803
1804 if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
1805 cb = mlxsw_sp_setup_tc_block_cb_ig;
1806 else if (f->binder_type == TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS)
1807 cb = mlxsw_sp_setup_tc_block_cb_eg;
1808 else
1809 return -EOPNOTSUPP;
1810
1811 switch (f->command) {
1812 case TC_BLOCK_BIND:
1813 return tcf_block_cb_register(f->block, cb, mlxsw_sp_port,
1814 mlxsw_sp_port);
1815 case TC_BLOCK_UNBIND:
1816 tcf_block_cb_unregister(f->block, cb, mlxsw_sp_port);
1817 return 0;
1818 default:
1819 return -EOPNOTSUPP;
1820 }
1821}
1822
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001823static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
Jiri Pirkode4784c2017-08-07 10:15:32 +02001824 void *type_data)
Jiri Pirkofd33f1d2017-08-07 10:15:24 +02001825{
1826 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1827
Jiri Pirko2572ac52017-08-07 10:15:17 +02001828 switch (type) {
Jiri Pirkoeb49cfa2017-10-19 15:50:37 +02001829 case TC_SETUP_BLOCK:
1830 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
Nogah Frankel96f17e02017-11-06 07:23:45 +01001831 case TC_SETUP_QDISC_RED:
1832 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
Jiri Pirko2572ac52017-08-07 10:15:17 +02001833 default:
1834 return -EOPNOTSUPP;
Yotam Gigi763b4b72016-07-21 12:03:17 +02001835 }
Yotam Gigi763b4b72016-07-21 12:03:17 +02001836}
1837
Jiri Pirko9454d932017-12-06 09:41:12 +01001838
1839static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1840{
1841 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1842
1843 if (!enable && (mlxsw_sp_port->acl_rule_count ||
1844 !list_empty(&mlxsw_sp_port->mall_tc_list))) {
1845 netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1846 return -EINVAL;
1847 }
1848 return 0;
1849}
1850
1851typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1852
1853static int mlxsw_sp_handle_feature(struct net_device *dev,
1854 netdev_features_t wanted_features,
1855 netdev_features_t feature,
1856 mlxsw_sp_feature_handler feature_handler)
1857{
1858 netdev_features_t changes = wanted_features ^ dev->features;
1859 bool enable = !!(wanted_features & feature);
1860 int err;
1861
1862 if (!(changes & feature))
1863 return 0;
1864
1865 err = feature_handler(dev, enable);
1866 if (err) {
1867 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1868 enable ? "Enable" : "Disable", &feature, err);
1869 return err;
1870 }
1871
1872 if (enable)
1873 dev->features |= feature;
1874 else
1875 dev->features &= ~feature;
1876
1877 return 0;
1878}
1879static int mlxsw_sp_set_features(struct net_device *dev,
1880 netdev_features_t features)
1881{
1882 return mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1883 mlxsw_sp_feature_hw_tc);
1884}
1885
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001886static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1887 .ndo_open = mlxsw_sp_port_open,
1888 .ndo_stop = mlxsw_sp_port_stop,
1889 .ndo_start_xmit = mlxsw_sp_port_xmit,
Yotam Gigi763b4b72016-07-21 12:03:17 +02001890 .ndo_setup_tc = mlxsw_sp_setup_tc,
Jiri Pirkoc5b9b512015-12-03 12:12:22 +01001891 .ndo_set_rx_mode = mlxsw_sp_set_rx_mode,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001892 .ndo_set_mac_address = mlxsw_sp_port_set_mac_address,
1893 .ndo_change_mtu = mlxsw_sp_port_change_mtu,
1894 .ndo_get_stats64 = mlxsw_sp_port_get_stats64,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02001895 .ndo_has_offload_stats = mlxsw_sp_port_has_offload_stats,
1896 .ndo_get_offload_stats = mlxsw_sp_port_get_offload_stats,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001897 .ndo_vlan_rx_add_vid = mlxsw_sp_port_add_vid,
1898 .ndo_vlan_rx_kill_vid = mlxsw_sp_port_kill_vid,
Ido Schimmel2bf9a582016-04-05 10:20:04 +02001899 .ndo_get_phys_port_name = mlxsw_sp_port_get_phys_port_name,
Jiri Pirko9454d932017-12-06 09:41:12 +01001900 .ndo_set_features = mlxsw_sp_set_features,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001901};
1902
1903static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1904 struct ethtool_drvinfo *drvinfo)
1905{
1906 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1907 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1908
1909 strlcpy(drvinfo->driver, mlxsw_sp_driver_name, sizeof(drvinfo->driver));
1910 strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1911 sizeof(drvinfo->version));
1912 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1913 "%d.%d.%d",
1914 mlxsw_sp->bus_info->fw_rev.major,
1915 mlxsw_sp->bus_info->fw_rev.minor,
1916 mlxsw_sp->bus_info->fw_rev.subminor);
1917 strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1918 sizeof(drvinfo->bus_info));
1919}
1920
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001921static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1922 struct ethtool_pauseparam *pause)
1923{
1924 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1925
1926 pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1927 pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1928}
1929
1930static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1931 struct ethtool_pauseparam *pause)
1932{
1933 char pfcc_pl[MLXSW_REG_PFCC_LEN];
1934
1935 mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1936 mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1937 mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1938
1939 return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1940 pfcc_pl);
1941}
1942
1943static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1944 struct ethtool_pauseparam *pause)
1945{
1946 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1947 bool pause_en = pause->tx_pause || pause->rx_pause;
1948 int err;
1949
Ido Schimmeld81a6bd2016-04-06 17:10:16 +02001950 if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1951 netdev_err(dev, "PFC already enabled on port\n");
1952 return -EINVAL;
1953 }
1954
Ido Schimmel9f7ec052016-04-06 17:10:14 +02001955 if (pause->autoneg) {
1956 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1957 return -EINVAL;
1958 }
1959
1960 err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1961 if (err) {
1962 netdev_err(dev, "Failed to configure port's headroom\n");
1963 return err;
1964 }
1965
1966 err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1967 if (err) {
1968 netdev_err(dev, "Failed to set PAUSE parameters\n");
1969 goto err_port_pause_configure;
1970 }
1971
1972 mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1973 mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1974
1975 return 0;
1976
1977err_port_pause_configure:
1978 pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
1979 mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1980 return err;
1981}
1982
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001983struct mlxsw_sp_port_hw_stats {
1984 char str[ETH_GSTRING_LEN];
Jiri Pirko412791d2016-10-21 16:07:19 +02001985 u64 (*getter)(const char *payload);
Ido Schimmel18281f22017-03-24 08:02:51 +01001986 bool cells_bytes;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001987};
1988
Ido Schimmel7ed674b2016-07-19 15:35:53 +02001989static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02001990 {
1991 .str = "a_frames_transmitted_ok",
1992 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
1993 },
1994 {
1995 .str = "a_frames_received_ok",
1996 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
1997 },
1998 {
1999 .str = "a_frame_check_sequence_errors",
2000 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
2001 },
2002 {
2003 .str = "a_alignment_errors",
2004 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
2005 },
2006 {
2007 .str = "a_octets_transmitted_ok",
2008 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
2009 },
2010 {
2011 .str = "a_octets_received_ok",
2012 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
2013 },
2014 {
2015 .str = "a_multicast_frames_xmitted_ok",
2016 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
2017 },
2018 {
2019 .str = "a_broadcast_frames_xmitted_ok",
2020 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
2021 },
2022 {
2023 .str = "a_multicast_frames_received_ok",
2024 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
2025 },
2026 {
2027 .str = "a_broadcast_frames_received_ok",
2028 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
2029 },
2030 {
2031 .str = "a_in_range_length_errors",
2032 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
2033 },
2034 {
2035 .str = "a_out_of_range_length_field",
2036 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
2037 },
2038 {
2039 .str = "a_frame_too_long_errors",
2040 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
2041 },
2042 {
2043 .str = "a_symbol_error_during_carrier",
2044 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
2045 },
2046 {
2047 .str = "a_mac_control_frames_transmitted",
2048 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
2049 },
2050 {
2051 .str = "a_mac_control_frames_received",
2052 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2053 },
2054 {
2055 .str = "a_unsupported_opcodes_received",
2056 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2057 },
2058 {
2059 .str = "a_pause_mac_ctrl_frames_received",
2060 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2061 },
2062 {
2063 .str = "a_pause_mac_ctrl_frames_xmitted",
2064 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2065 },
2066};
2067
2068#define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2069
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002070static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2071 {
2072 .str = "rx_octets_prio",
2073 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2074 },
2075 {
2076 .str = "rx_frames_prio",
2077 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2078 },
2079 {
2080 .str = "tx_octets_prio",
2081 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2082 },
2083 {
2084 .str = "tx_frames_prio",
2085 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2086 },
2087 {
2088 .str = "rx_pause_prio",
2089 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2090 },
2091 {
2092 .str = "rx_pause_duration_prio",
2093 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2094 },
2095 {
2096 .str = "tx_pause_prio",
2097 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2098 },
2099 {
2100 .str = "tx_pause_duration_prio",
2101 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2102 },
2103};
2104
2105#define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2106
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002107static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2108 {
2109 .str = "tc_transmit_queue_tc",
Ido Schimmel18281f22017-03-24 08:02:51 +01002110 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2111 .cells_bytes = true,
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002112 },
2113 {
2114 .str = "tc_no_buffer_discard_uc_tc",
2115 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2116 },
2117};
2118
2119#define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2120
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002121#define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002122 (MLXSW_SP_PORT_HW_PRIO_STATS_LEN + \
2123 MLXSW_SP_PORT_HW_TC_STATS_LEN) * \
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002124 IEEE_8021QAZ_MAX_TCS)
2125
2126static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2127{
2128 int i;
2129
2130 for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2131 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2132 mlxsw_sp_port_hw_prio_stats[i].str, prio);
2133 *p += ETH_GSTRING_LEN;
2134 }
2135}
2136
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002137static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2138{
2139 int i;
2140
2141 for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2142 snprintf(*p, ETH_GSTRING_LEN, "%s_%d",
2143 mlxsw_sp_port_hw_tc_stats[i].str, tc);
2144 *p += ETH_GSTRING_LEN;
2145 }
2146}
2147
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002148static void mlxsw_sp_port_get_strings(struct net_device *dev,
2149 u32 stringset, u8 *data)
2150{
2151 u8 *p = data;
2152 int i;
2153
2154 switch (stringset) {
2155 case ETH_SS_STATS:
2156 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2157 memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2158 ETH_GSTRING_LEN);
2159 p += ETH_GSTRING_LEN;
2160 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002161
2162 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2163 mlxsw_sp_port_get_prio_strings(&p, i);
2164
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002165 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2166 mlxsw_sp_port_get_tc_strings(&p, i);
2167
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002168 break;
2169 }
2170}
2171
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002172static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2173 enum ethtool_phys_id_state state)
2174{
2175 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2176 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2177 char mlcr_pl[MLXSW_REG_MLCR_LEN];
2178 bool active;
2179
2180 switch (state) {
2181 case ETHTOOL_ID_ACTIVE:
2182 active = true;
2183 break;
2184 case ETHTOOL_ID_INACTIVE:
2185 active = false;
2186 break;
2187 default:
2188 return -EOPNOTSUPP;
2189 }
2190
2191 mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2192 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2193}
2194
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002195static int
2196mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2197 int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2198{
2199 switch (grp) {
2200 case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2201 *p_hw_stats = mlxsw_sp_port_hw_stats;
2202 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2203 break;
2204 case MLXSW_REG_PPCNT_PRIO_CNT:
2205 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2206 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2207 break;
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002208 case MLXSW_REG_PPCNT_TC_CNT:
2209 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2210 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2211 break;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002212 default:
2213 WARN_ON(1);
Yotam Gigie915ac62017-01-09 11:25:48 +01002214 return -EOPNOTSUPP;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002215 }
2216 return 0;
2217}
2218
2219static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2220 enum mlxsw_reg_ppcnt_grp grp, int prio,
2221 u64 *data, int data_index)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002222{
Ido Schimmel18281f22017-03-24 08:02:51 +01002223 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2224 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002225 struct mlxsw_sp_port_hw_stats *hw_stats;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002226 char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002227 int i, len;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002228 int err;
2229
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002230 err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2231 if (err)
2232 return;
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002233 mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002234 for (i = 0; i < len; i++) {
Colin Ian Kingfaac0ff2016-09-23 12:02:45 +01002235 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
Ido Schimmel18281f22017-03-24 08:02:51 +01002236 if (!hw_stats[i].cells_bytes)
2237 continue;
2238 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2239 data[data_index + i]);
2240 }
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002241}
2242
2243static void mlxsw_sp_port_get_stats(struct net_device *dev,
2244 struct ethtool_stats *stats, u64 *data)
2245{
2246 int i, data_index = 0;
2247
2248 /* IEEE 802.3 Counters */
2249 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2250 data, data_index);
2251 data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2252
2253 /* Per-Priority Counters */
2254 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2255 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2256 data, data_index);
2257 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2258 }
Ido Schimmeldf4750e2016-07-19 15:35:54 +02002259
2260 /* Per-TC Counters */
2261 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2262 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2263 data, data_index);
2264 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2265 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002266}
2267
2268static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2269{
2270 switch (sset) {
2271 case ETH_SS_STATS:
Ido Schimmel7ed674b2016-07-19 15:35:53 +02002272 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002273 default:
2274 return -EOPNOTSUPP;
2275 }
2276}
2277
2278struct mlxsw_sp_port_link_mode {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002279 enum ethtool_link_mode_bit_indices mask_ethtool;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002280 u32 mask;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002281 u32 speed;
2282};
2283
2284static const struct mlxsw_sp_port_link_mode mlxsw_sp_port_link_mode[] = {
2285 {
2286 .mask = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002287 .mask_ethtool = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2288 .speed = SPEED_100,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002289 },
2290 {
2291 .mask = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2292 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002293 .mask_ethtool = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2294 .speed = SPEED_1000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002295 },
2296 {
2297 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002298 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2299 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002300 },
2301 {
2302 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2303 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002304 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2305 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002306 },
2307 {
2308 .mask = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2309 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2310 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2311 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002312 .mask_ethtool = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2313 .speed = SPEED_10000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002314 },
2315 {
2316 .mask = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002317 .mask_ethtool = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2318 .speed = SPEED_20000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002319 },
2320 {
2321 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002322 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2323 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002324 },
2325 {
2326 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002327 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2328 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002329 },
2330 {
2331 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002332 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2333 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002334 },
2335 {
2336 .mask = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002337 .mask_ethtool = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2338 .speed = SPEED_40000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002339 },
2340 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002341 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2342 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2343 .speed = SPEED_25000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002344 },
2345 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002346 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2347 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2348 .speed = SPEED_25000,
2349 },
2350 {
2351 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2352 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2353 .speed = SPEED_25000,
2354 },
2355 {
2356 .mask = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2357 .mask_ethtool = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2358 .speed = SPEED_25000,
2359 },
2360 {
2361 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2362 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2363 .speed = SPEED_50000,
2364 },
2365 {
2366 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2367 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2368 .speed = SPEED_50000,
2369 },
2370 {
2371 .mask = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2372 .mask_ethtool = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2373 .speed = SPEED_50000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002374 },
2375 {
2376 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002377 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT,
2378 .speed = SPEED_56000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002379 },
2380 {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002381 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2382 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT,
2383 .speed = SPEED_56000,
2384 },
2385 {
2386 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2387 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT,
2388 .speed = SPEED_56000,
2389 },
2390 {
2391 .mask = MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4,
2392 .mask_ethtool = ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT,
2393 .speed = SPEED_56000,
2394 },
2395 {
2396 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2397 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2398 .speed = SPEED_100000,
2399 },
2400 {
2401 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2402 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2403 .speed = SPEED_100000,
2404 },
2405 {
2406 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2407 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2408 .speed = SPEED_100000,
2409 },
2410 {
2411 .mask = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2412 .mask_ethtool = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2413 .speed = SPEED_100000,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002414 },
2415};
2416
2417#define MLXSW_SP_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp_port_link_mode)
2418
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002419static void
2420mlxsw_sp_from_ptys_supported_port(u32 ptys_eth_proto,
2421 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002422{
2423 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2424 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2425 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2426 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2427 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2428 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002429 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002430
2431 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2432 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2433 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2434 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2435 MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002436 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002437}
2438
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002439static void mlxsw_sp_from_ptys_link(u32 ptys_eth_proto, unsigned long *mode)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002440{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002441 int i;
2442
2443 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2444 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask)
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002445 __set_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2446 mode);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002447 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002448}
2449
2450static void mlxsw_sp_from_ptys_speed_duplex(bool carrier_ok, u32 ptys_eth_proto,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002451 struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002452{
2453 u32 speed = SPEED_UNKNOWN;
2454 u8 duplex = DUPLEX_UNKNOWN;
2455 int i;
2456
2457 if (!carrier_ok)
2458 goto out;
2459
2460 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2461 if (ptys_eth_proto & mlxsw_sp_port_link_mode[i].mask) {
2462 speed = mlxsw_sp_port_link_mode[i].speed;
2463 duplex = DUPLEX_FULL;
2464 break;
2465 }
2466 }
2467out:
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002468 cmd->base.speed = speed;
2469 cmd->base.duplex = duplex;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002470}
2471
2472static u8 mlxsw_sp_port_connector_port(u32 ptys_eth_proto)
2473{
2474 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2475 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2476 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2477 MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2478 return PORT_FIBRE;
2479
2480 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2481 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2482 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4))
2483 return PORT_DA;
2484
2485 if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2486 MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2487 MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2488 MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4))
2489 return PORT_NONE;
2490
2491 return PORT_OTHER;
2492}
2493
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002494static u32
2495mlxsw_sp_to_ptys_advert_link(const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002496{
2497 u32 ptys_proto = 0;
2498 int i;
2499
2500 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002501 if (test_bit(mlxsw_sp_port_link_mode[i].mask_ethtool,
2502 cmd->link_modes.advertising))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002503 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2504 }
2505 return ptys_proto;
2506}
2507
2508static u32 mlxsw_sp_to_ptys_speed(u32 speed)
2509{
2510 u32 ptys_proto = 0;
2511 int i;
2512
2513 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2514 if (speed == mlxsw_sp_port_link_mode[i].speed)
2515 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2516 }
2517 return ptys_proto;
2518}
2519
Ido Schimmel18f1e702016-02-26 17:32:31 +01002520static u32 mlxsw_sp_to_ptys_upper_speed(u32 upper_speed)
2521{
2522 u32 ptys_proto = 0;
2523 int i;
2524
2525 for (i = 0; i < MLXSW_SP_PORT_LINK_MODE_LEN; i++) {
2526 if (mlxsw_sp_port_link_mode[i].speed <= upper_speed)
2527 ptys_proto |= mlxsw_sp_port_link_mode[i].mask;
2528 }
2529 return ptys_proto;
2530}
2531
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002532static void mlxsw_sp_port_get_link_supported(u32 eth_proto_cap,
2533 struct ethtool_link_ksettings *cmd)
2534{
2535 ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
2536 ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
2537 ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
2538
2539 mlxsw_sp_from_ptys_supported_port(eth_proto_cap, cmd);
2540 mlxsw_sp_from_ptys_link(eth_proto_cap, cmd->link_modes.supported);
2541}
2542
2543static void mlxsw_sp_port_get_link_advertise(u32 eth_proto_admin, bool autoneg,
2544 struct ethtool_link_ksettings *cmd)
2545{
2546 if (!autoneg)
2547 return;
2548
2549 ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
2550 mlxsw_sp_from_ptys_link(eth_proto_admin, cmd->link_modes.advertising);
2551}
2552
2553static void
2554mlxsw_sp_port_get_link_lp_advertise(u32 eth_proto_lp, u8 autoneg_status,
2555 struct ethtool_link_ksettings *cmd)
2556{
2557 if (autoneg_status != MLXSW_REG_PTYS_AN_STATUS_OK || !eth_proto_lp)
2558 return;
2559
2560 ethtool_link_ksettings_add_link_mode(cmd, lp_advertising, Autoneg);
2561 mlxsw_sp_from_ptys_link(eth_proto_lp, cmd->link_modes.lp_advertising);
2562}
2563
2564static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
2565 struct ethtool_link_ksettings *cmd)
2566{
2567 u32 eth_proto_cap, eth_proto_admin, eth_proto_oper, eth_proto_lp;
2568 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2569 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2570 char ptys_pl[MLXSW_REG_PTYS_LEN];
2571 u8 autoneg_status;
2572 bool autoneg;
2573 int err;
2574
2575 autoneg = mlxsw_sp_port->link.autoneg;
Elad Raz401c8b42016-10-28 21:35:52 +02002576 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002577 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2578 if (err)
2579 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002580 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, &eth_proto_admin,
2581 &eth_proto_oper);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002582
2583 mlxsw_sp_port_get_link_supported(eth_proto_cap, cmd);
2584
2585 mlxsw_sp_port_get_link_advertise(eth_proto_admin, autoneg, cmd);
2586
2587 eth_proto_lp = mlxsw_reg_ptys_eth_proto_lp_advertise_get(ptys_pl);
2588 autoneg_status = mlxsw_reg_ptys_an_status_get(ptys_pl);
2589 mlxsw_sp_port_get_link_lp_advertise(eth_proto_lp, autoneg_status, cmd);
2590
2591 cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
2592 cmd->base.port = mlxsw_sp_port_connector_port(eth_proto_oper);
2593 mlxsw_sp_from_ptys_speed_duplex(netif_carrier_ok(dev), eth_proto_oper,
2594 cmd);
2595
2596 return 0;
2597}
2598
2599static int
2600mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
2601 const struct ethtool_link_ksettings *cmd)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002602{
2603 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2604 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2605 char ptys_pl[MLXSW_REG_PTYS_LEN];
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002606 u32 eth_proto_cap, eth_proto_new;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002607 bool autoneg;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002608 int err;
2609
Elad Raz401c8b42016-10-28 21:35:52 +02002610 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002611 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002612 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002613 return err;
Elad Raz401c8b42016-10-28 21:35:52 +02002614 mlxsw_reg_ptys_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002615
2616 autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
2617 eth_proto_new = autoneg ?
2618 mlxsw_sp_to_ptys_advert_link(cmd) :
2619 mlxsw_sp_to_ptys_speed(cmd->base.speed);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002620
2621 eth_proto_new = eth_proto_new & eth_proto_cap;
2622 if (!eth_proto_new) {
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002623 netdev_err(dev, "No supported speed requested\n");
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002624 return -EINVAL;
2625 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002626
Elad Raz401c8b42016-10-28 21:35:52 +02002627 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2628 eth_proto_new);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002629 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002630 if (err)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002631 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002632
Ido Schimmel6277d462016-07-15 11:14:58 +02002633 if (!netif_running(dev))
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002634 return 0;
2635
Ido Schimmel0c83f882016-09-12 13:26:23 +02002636 mlxsw_sp_port->link.autoneg = autoneg;
2637
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002638 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
2639 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002640
2641 return 0;
2642}
2643
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002644static int mlxsw_sp_flash_device(struct net_device *dev,
2645 struct ethtool_flash *flash)
2646{
2647 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2648 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2649 const struct firmware *firmware;
2650 int err;
2651
2652 if (flash->region != ETHTOOL_FLASH_ALL_REGIONS)
2653 return -EOPNOTSUPP;
2654
2655 dev_hold(dev);
2656 rtnl_unlock();
2657
2658 err = request_firmware_direct(&firmware, flash->data, &dev->dev);
2659 if (err)
2660 goto out;
2661 err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware);
2662 release_firmware(firmware);
2663out:
2664 rtnl_lock();
2665 dev_put(dev);
2666 return err;
2667}
2668
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002669#define MLXSW_SP_I2C_ADDR_LOW 0x50
2670#define MLXSW_SP_I2C_ADDR_HIGH 0x51
2671#define MLXSW_SP_EEPROM_PAGE_LENGTH 256
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002672
2673static int mlxsw_sp_query_module_eeprom(struct mlxsw_sp_port *mlxsw_sp_port,
2674 u16 offset, u16 size, void *data,
2675 unsigned int *p_read_size)
2676{
2677 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2678 char eeprom_tmp[MLXSW_SP_REG_MCIA_EEPROM_SIZE];
2679 char mcia_pl[MLXSW_REG_MCIA_LEN];
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002680 u16 i2c_addr;
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002681 int status;
2682 int err;
2683
2684 size = min_t(u16, size, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002685
2686 if (offset < MLXSW_SP_EEPROM_PAGE_LENGTH &&
2687 offset + size > MLXSW_SP_EEPROM_PAGE_LENGTH)
2688 /* Cross pages read, read until offset 256 in low page */
2689 size = MLXSW_SP_EEPROM_PAGE_LENGTH - offset;
2690
2691 i2c_addr = MLXSW_SP_I2C_ADDR_LOW;
2692 if (offset >= MLXSW_SP_EEPROM_PAGE_LENGTH) {
2693 i2c_addr = MLXSW_SP_I2C_ADDR_HIGH;
2694 offset -= MLXSW_SP_EEPROM_PAGE_LENGTH;
2695 }
2696
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002697 mlxsw_reg_mcia_pack(mcia_pl, mlxsw_sp_port->mapping.module,
Arkadi Sharshevsky44000812017-09-11 09:42:26 +02002698 0, 0, offset, size, i2c_addr);
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002699
2700 err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcia), mcia_pl);
2701 if (err)
2702 return err;
2703
2704 status = mlxsw_reg_mcia_status_get(mcia_pl);
2705 if (status)
2706 return -EIO;
2707
2708 mlxsw_reg_mcia_eeprom_memcpy_from(mcia_pl, eeprom_tmp);
2709 memcpy(data, eeprom_tmp, size);
2710 *p_read_size = size;
2711
2712 return 0;
2713}
2714
2715enum mlxsw_sp_eeprom_module_info_rev_id {
2716 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
2717 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
2718 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
2719};
2720
2721enum mlxsw_sp_eeprom_module_info_id {
2722 MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP = 0x03,
2723 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
2724 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
2725 MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
2726};
2727
2728enum mlxsw_sp_eeprom_module_info {
2729 MLXSW_SP_EEPROM_MODULE_INFO_ID,
2730 MLXSW_SP_EEPROM_MODULE_INFO_REV_ID,
2731 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2732};
2733
2734static int mlxsw_sp_get_module_info(struct net_device *netdev,
2735 struct ethtool_modinfo *modinfo)
2736{
2737 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2738 u8 module_info[MLXSW_SP_EEPROM_MODULE_INFO_SIZE];
2739 u8 module_rev_id, module_id;
2740 unsigned int read_size;
2741 int err;
2742
2743 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, 0,
2744 MLXSW_SP_EEPROM_MODULE_INFO_SIZE,
2745 module_info, &read_size);
2746 if (err)
2747 return err;
2748
2749 if (read_size < MLXSW_SP_EEPROM_MODULE_INFO_SIZE)
2750 return -EIO;
2751
2752 module_rev_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_REV_ID];
2753 module_id = module_info[MLXSW_SP_EEPROM_MODULE_INFO_ID];
2754
2755 switch (module_id) {
2756 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP:
2757 modinfo->type = ETH_MODULE_SFF_8436;
2758 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2759 break;
2760 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP_PLUS:
2761 case MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28:
2762 if (module_id == MLXSW_SP_EEPROM_MODULE_INFO_ID_QSFP28 ||
2763 module_rev_id >= MLXSW_SP_EEPROM_MODULE_INFO_REV_ID_8636) {
2764 modinfo->type = ETH_MODULE_SFF_8636;
2765 modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
2766 } else {
2767 modinfo->type = ETH_MODULE_SFF_8436;
2768 modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
2769 }
2770 break;
2771 case MLXSW_SP_EEPROM_MODULE_INFO_ID_SFP:
2772 modinfo->type = ETH_MODULE_SFF_8472;
2773 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2774 break;
2775 default:
2776 return -EINVAL;
2777 }
2778
2779 return 0;
2780}
2781
2782static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
2783 struct ethtool_eeprom *ee,
2784 u8 *data)
2785{
2786 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
2787 int offset = ee->offset;
2788 unsigned int read_size;
2789 int i = 0;
2790 int err;
2791
2792 if (!ee->len)
2793 return -EINVAL;
2794
2795 memset(data, 0, ee->len);
2796
2797 while (i < ee->len) {
2798 err = mlxsw_sp_query_module_eeprom(mlxsw_sp_port, offset,
2799 ee->len - i, data + i,
2800 &read_size);
2801 if (err) {
2802 netdev_err(mlxsw_sp_port->dev, "Eeprom query failed\n");
2803 return err;
2804 }
2805
2806 i += read_size;
2807 offset += read_size;
2808 }
2809
2810 return 0;
2811}
2812
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002813static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
2814 .get_drvinfo = mlxsw_sp_port_get_drvinfo,
2815 .get_link = ethtool_op_get_link,
Ido Schimmel9f7ec052016-04-06 17:10:14 +02002816 .get_pauseparam = mlxsw_sp_port_get_pauseparam,
2817 .set_pauseparam = mlxsw_sp_port_set_pauseparam,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002818 .get_strings = mlxsw_sp_port_get_strings,
Ido Schimmel3a66ee32015-11-27 13:45:55 +01002819 .set_phys_id = mlxsw_sp_port_set_phys_id,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002820 .get_ethtool_stats = mlxsw_sp_port_get_stats,
2821 .get_sset_count = mlxsw_sp_port_get_sset_count,
Ido Schimmelb9d66a32016-09-12 13:26:27 +02002822 .get_link_ksettings = mlxsw_sp_port_get_link_ksettings,
2823 .set_link_ksettings = mlxsw_sp_port_set_link_ksettings,
Yotam Gigice6ef68f2017-06-01 16:26:46 +03002824 .flash_device = mlxsw_sp_flash_device,
Arkadi Sharshevsky2ea10902017-06-14 09:27:40 +02002825 .get_module_info = mlxsw_sp_get_module_info,
2826 .get_module_eeprom = mlxsw_sp_get_module_eeprom,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002827};
2828
Ido Schimmel18f1e702016-02-26 17:32:31 +01002829static int
2830mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
2831{
2832 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2833 u32 upper_speed = MLXSW_SP_PORT_BASE_SPEED * width;
2834 char ptys_pl[MLXSW_REG_PTYS_LEN];
2835 u32 eth_proto_admin;
2836
2837 eth_proto_admin = mlxsw_sp_to_ptys_upper_speed(upper_speed);
Elad Raz401c8b42016-10-28 21:35:52 +02002838 mlxsw_reg_ptys_eth_pack(ptys_pl, mlxsw_sp_port->local_port,
2839 eth_proto_admin);
Ido Schimmel18f1e702016-02-26 17:32:31 +01002840 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
2841}
2842
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002843int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
2844 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
2845 bool dwrr, u8 dwrr_weight)
Ido Schimmel90183b92016-04-06 17:10:08 +02002846{
2847 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2848 char qeec_pl[MLXSW_REG_QEEC_LEN];
2849
2850 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2851 next_index);
2852 mlxsw_reg_qeec_de_set(qeec_pl, true);
2853 mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
2854 mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
2855 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2856}
2857
Ido Schimmelcc7cf512016-04-06 17:10:11 +02002858int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
2859 enum mlxsw_reg_qeec_hr hr, u8 index,
2860 u8 next_index, u32 maxrate)
Ido Schimmel90183b92016-04-06 17:10:08 +02002861{
2862 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2863 char qeec_pl[MLXSW_REG_QEEC_LEN];
2864
2865 mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
2866 next_index);
2867 mlxsw_reg_qeec_mase_set(qeec_pl, true);
2868 mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
2869 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
2870}
2871
Ido Schimmel8e8dfe92016-04-06 17:10:10 +02002872int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
2873 u8 switch_prio, u8 tclass)
Ido Schimmel90183b92016-04-06 17:10:08 +02002874{
2875 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2876 char qtct_pl[MLXSW_REG_QTCT_LEN];
2877
2878 mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
2879 tclass);
2880 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
2881}
2882
2883static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
2884{
2885 int err, i;
2886
2887 /* Setup the elements hierarcy, so that each TC is linked to
2888 * one subgroup, which are all member in the same group.
2889 */
2890 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2891 MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
2892 0);
2893 if (err)
2894 return err;
2895 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2896 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2897 MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
2898 0, false, 0);
2899 if (err)
2900 return err;
2901 }
2902 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2903 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
2904 MLXSW_REG_QEEC_HIERARCY_TC, i, i,
2905 false, 0);
2906 if (err)
2907 return err;
2908 }
2909
2910 /* Make sure the max shaper is disabled in all hierarcies that
2911 * support it.
2912 */
2913 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2914 MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
2915 MLXSW_REG_QEEC_MAS_DIS);
2916 if (err)
2917 return err;
2918 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2919 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2920 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2921 i, 0,
2922 MLXSW_REG_QEEC_MAS_DIS);
2923 if (err)
2924 return err;
2925 }
2926 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2927 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
2928 MLXSW_REG_QEEC_HIERARCY_TC,
2929 i, i,
2930 MLXSW_REG_QEEC_MAS_DIS);
2931 if (err)
2932 return err;
2933 }
2934
2935 /* Map all priorities to traffic class 0. */
2936 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2937 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
2938 if (err)
2939 return err;
2940 }
2941
2942 return 0;
2943}
2944
Ido Schimmel5b153852017-06-08 08:47:44 +02002945static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2946 bool split, u8 module, u8 width, u8 lane)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002947{
Ido Schimmelc57529e2017-05-26 08:37:31 +02002948 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002949 struct mlxsw_sp_port *mlxsw_sp_port;
2950 struct net_device *dev;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002951 int err;
2952
Ido Schimmel5b153852017-06-08 08:47:44 +02002953 err = mlxsw_core_port_init(mlxsw_sp->core, local_port);
2954 if (err) {
2955 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
2956 local_port);
2957 return err;
2958 }
2959
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002960 dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
Ido Schimmel5b153852017-06-08 08:47:44 +02002961 if (!dev) {
2962 err = -ENOMEM;
2963 goto err_alloc_etherdev;
2964 }
Jiri Pirkof20a91f2016-10-27 15:13:00 +02002965 SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002966 mlxsw_sp_port = netdev_priv(dev);
2967 mlxsw_sp_port->dev = dev;
2968 mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
2969 mlxsw_sp_port->local_port = local_port;
Ido Schimmelc57529e2017-05-26 08:37:31 +02002970 mlxsw_sp_port->pvid = 1;
Ido Schimmel18f1e702016-02-26 17:32:31 +01002971 mlxsw_sp_port->split = split;
Ido Schimmeld664b412016-06-09 09:51:40 +02002972 mlxsw_sp_port->mapping.module = module;
2973 mlxsw_sp_port->mapping.width = width;
2974 mlxsw_sp_port->mapping.lane = lane;
Ido Schimmel0c83f882016-09-12 13:26:23 +02002975 mlxsw_sp_port->link.autoneg = 1;
Ido Schimmel31a08a52017-05-26 08:37:26 +02002976 INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
Yotam Gigi763b4b72016-07-21 12:03:17 +02002977 INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002978
2979 mlxsw_sp_port->pcpu_stats =
2980 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
2981 if (!mlxsw_sp_port->pcpu_stats) {
2982 err = -ENOMEM;
2983 goto err_alloc_stats;
2984 }
2985
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01002986 mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
2987 GFP_KERNEL);
2988 if (!mlxsw_sp_port->sample) {
2989 err = -ENOMEM;
2990 goto err_alloc_sample;
2991 }
2992
Nogah Frankel9deef432017-10-26 10:55:32 +02002993 INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
Nogah Frankelfc1bbb02016-09-16 15:05:38 +02002994 &update_stats_cache);
2995
Jiri Pirko56ade8f2015-10-16 14:01:37 +02002996 dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
2997 dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
2998
Ido Schimmel2e915e02017-06-08 08:47:45 +02002999 err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
Ido Schimmel5b153852017-06-08 08:47:44 +02003000 if (err) {
3001 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
3002 mlxsw_sp_port->local_port);
3003 goto err_port_module_map;
3004 }
3005
Ido Schimmel3247ff22016-09-08 08:16:02 +02003006 err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
3007 if (err) {
3008 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
3009 mlxsw_sp_port->local_port);
3010 goto err_port_swid_set;
3011 }
3012
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003013 err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
3014 if (err) {
3015 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
3016 mlxsw_sp_port->local_port);
3017 goto err_dev_addr_init;
3018 }
3019
3020 netif_carrier_off(dev);
3021
3022 dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
Yotam Gigi763b4b72016-07-21 12:03:17 +02003023 NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
3024 dev->hw_features |= NETIF_F_HW_TC;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003025
Jarod Wilsond894be52016-10-20 13:55:16 -04003026 dev->min_mtu = 0;
3027 dev->max_mtu = ETH_MAX_MTU;
3028
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003029 /* Each packet needs to have a Tx header (metadata) on top all other
3030 * headers.
3031 */
Yotam Gigifeb7d382016-10-04 09:46:04 +02003032 dev->needed_headroom = MLXSW_TXHDR_LEN;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003033
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003034 err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
3035 if (err) {
3036 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
3037 mlxsw_sp_port->local_port);
3038 goto err_port_system_port_mapping_set;
3039 }
3040
Ido Schimmel18f1e702016-02-26 17:32:31 +01003041 err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
3042 if (err) {
3043 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
3044 mlxsw_sp_port->local_port);
3045 goto err_port_speed_by_width_set;
3046 }
3047
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003048 err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3049 if (err) {
3050 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3051 mlxsw_sp_port->local_port);
3052 goto err_port_mtu_set;
3053 }
3054
3055 err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3056 if (err)
3057 goto err_port_admin_status_set;
3058
3059 err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3060 if (err) {
3061 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3062 mlxsw_sp_port->local_port);
3063 goto err_port_buffers_init;
3064 }
3065
Ido Schimmel90183b92016-04-06 17:10:08 +02003066 err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3067 if (err) {
3068 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3069 mlxsw_sp_port->local_port);
3070 goto err_port_ets_init;
3071 }
3072
Ido Schimmelf00817d2016-04-06 17:10:09 +02003073 /* ETS and buffers must be initialized before DCB. */
3074 err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3075 if (err) {
3076 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3077 mlxsw_sp_port->local_port);
3078 goto err_port_dcb_init;
3079 }
3080
Ido Schimmela1107482017-05-26 08:37:39 +02003081 err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
Ido Schimmel45a4a162017-05-16 19:38:35 +02003082 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003083 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
Ido Schimmel45a4a162017-05-16 19:38:35 +02003084 mlxsw_sp_port->local_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003085 goto err_port_fids_init;
Ido Schimmel45a4a162017-05-16 19:38:35 +02003086 }
3087
Nogah Frankel371b4372018-01-10 14:59:57 +01003088 err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3089 if (err) {
3090 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3091 mlxsw_sp_port->local_port);
3092 goto err_port_qdiscs_init;
3093 }
3094
Ido Schimmelc57529e2017-05-26 08:37:31 +02003095 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
3096 if (IS_ERR(mlxsw_sp_port_vlan)) {
3097 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
Ido Schimmel05978482016-08-17 16:39:30 +02003098 mlxsw_sp_port->local_port);
Wei Yongjund86fd112017-11-06 11:11:28 +00003099 err = PTR_ERR(mlxsw_sp_port_vlan);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003100 goto err_port_vlan_get;
Ido Schimmel05978482016-08-17 16:39:30 +02003101 }
3102
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003103 mlxsw_sp_port_switchdev_init(mlxsw_sp_port);
Ido Schimmel2f258442016-08-17 16:39:31 +02003104 mlxsw_sp->ports[local_port] = mlxsw_sp_port;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003105 err = register_netdev(dev);
3106 if (err) {
3107 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3108 mlxsw_sp_port->local_port);
3109 goto err_register_netdev;
3110 }
3111
Elad Razd808c7e2016-10-28 21:35:57 +02003112 mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3113 mlxsw_sp_port, dev, mlxsw_sp_port->split,
3114 module);
Nogah Frankel9deef432017-10-26 10:55:32 +02003115 mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003116 return 0;
3117
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003118err_register_netdev:
Ido Schimmel2f258442016-08-17 16:39:31 +02003119 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003120 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003121 mlxsw_sp_port_vlan_put(mlxsw_sp_port_vlan);
3122err_port_vlan_get:
Nogah Frankel371b4372018-01-10 14:59:57 +01003123 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3124err_port_qdiscs_init:
Ido Schimmela1107482017-05-26 08:37:39 +02003125 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3126err_port_fids_init:
Ido Schimmel4de34eb2016-08-04 17:36:22 +03003127 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003128err_port_dcb_init:
Ido Schimmel90183b92016-04-06 17:10:08 +02003129err_port_ets_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003130err_port_buffers_init:
3131err_port_admin_status_set:
3132err_port_mtu_set:
Ido Schimmel18f1e702016-02-26 17:32:31 +01003133err_port_speed_by_width_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003134err_port_system_port_mapping_set:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003135err_dev_addr_init:
Ido Schimmel3247ff22016-09-08 08:16:02 +02003136 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3137err_port_swid_set:
Ido Schimmel2e915e02017-06-08 08:47:45 +02003138 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Ido Schimmel5b153852017-06-08 08:47:44 +02003139err_port_module_map:
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003140 kfree(mlxsw_sp_port->sample);
3141err_alloc_sample:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003142 free_percpu(mlxsw_sp_port->pcpu_stats);
3143err_alloc_stats:
3144 free_netdev(dev);
Ido Schimmel5b153852017-06-08 08:47:44 +02003145err_alloc_etherdev:
Jiri Pirko67963a32016-10-28 21:35:55 +02003146 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3147 return err;
3148}
3149
Ido Schimmel5b153852017-06-08 08:47:44 +02003150static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003151{
3152 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3153
Nogah Frankel9deef432017-10-26 10:55:32 +02003154 cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
Jiri Pirko67963a32016-10-28 21:35:55 +02003155 mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003156 unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
Ido Schimmel2f258442016-08-17 16:39:31 +02003157 mlxsw_sp->ports[local_port] = NULL;
Ido Schimmel05832722016-08-17 16:39:35 +02003158 mlxsw_sp_port_switchdev_fini(mlxsw_sp_port);
Ido Schimmelc57529e2017-05-26 08:37:31 +02003159 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Nogah Frankel371b4372018-01-10 14:59:57 +01003160 mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
Ido Schimmela1107482017-05-26 08:37:39 +02003161 mlxsw_sp_port_fids_fini(mlxsw_sp_port);
Ido Schimmelf00817d2016-04-06 17:10:09 +02003162 mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
Ido Schimmel3e9b27b2016-02-26 17:32:28 +01003163 mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
Ido Schimmel2e915e02017-06-08 08:47:45 +02003164 mlxsw_sp_port_module_unmap(mlxsw_sp_port);
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003165 kfree(mlxsw_sp_port->sample);
Yotam Gigi136f1442017-01-09 11:25:47 +01003166 free_percpu(mlxsw_sp_port->pcpu_stats);
Ido Schimmel31a08a52017-05-26 08:37:26 +02003167 WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003168 free_netdev(mlxsw_sp_port->dev);
Jiri Pirko67963a32016-10-28 21:35:55 +02003169 mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3170}
3171
Jiri Pirkof83e2102016-10-28 21:35:49 +02003172static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3173{
3174 return mlxsw_sp->ports[local_port] != NULL;
3175}
3176
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003177static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3178{
3179 int i;
3180
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003181 for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003182 if (mlxsw_sp_port_created(mlxsw_sp, i))
3183 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003184 kfree(mlxsw_sp->port_to_module);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003185 kfree(mlxsw_sp->ports);
3186}
3187
3188static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3189{
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003190 unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
Ido Schimmeld664b412016-06-09 09:51:40 +02003191 u8 module, width, lane;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003192 size_t alloc_size;
3193 int i;
3194 int err;
3195
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003196 alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003197 mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3198 if (!mlxsw_sp->ports)
3199 return -ENOMEM;
3200
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003201 mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3202 GFP_KERNEL);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003203 if (!mlxsw_sp->port_to_module) {
3204 err = -ENOMEM;
3205 goto err_port_to_module_alloc;
3206 }
3207
3208 for (i = 1; i < max_ports; i++) {
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003209 /* Mark as invalid */
3210 mlxsw_sp->port_to_module[i] = -1;
3211
Ido Schimmel558c2d52016-02-26 17:32:29 +01003212 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003213 &width, &lane);
Ido Schimmel558c2d52016-02-26 17:32:29 +01003214 if (err)
3215 goto err_port_module_info_get;
3216 if (!width)
3217 continue;
3218 mlxsw_sp->port_to_module[i] = module;
Jiri Pirko67963a32016-10-28 21:35:55 +02003219 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3220 module, width, lane);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003221 if (err)
3222 goto err_port_create;
3223 }
3224 return 0;
3225
3226err_port_create:
Ido Schimmel558c2d52016-02-26 17:32:29 +01003227err_port_module_info_get:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003228 for (i--; i >= 1; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003229 if (mlxsw_sp_port_created(mlxsw_sp, i))
3230 mlxsw_sp_port_remove(mlxsw_sp, i);
Ido Schimmel5ec2ee72017-03-24 08:02:48 +01003231 kfree(mlxsw_sp->port_to_module);
3232err_port_to_module_alloc:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003233 kfree(mlxsw_sp->ports);
3234 return err;
3235}
3236
Ido Schimmel18f1e702016-02-26 17:32:31 +01003237static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3238{
3239 u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3240
3241 return local_port - offset;
3242}
3243
Ido Schimmelbe945352016-06-09 09:51:39 +02003244static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
3245 u8 module, unsigned int count)
3246{
3247 u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
3248 int err, i;
3249
3250 for (i = 0; i < count; i++) {
Ido Schimmelbe945352016-06-09 09:51:39 +02003251 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i, true,
Ido Schimmeld664b412016-06-09 09:51:40 +02003252 module, width, i * width);
Ido Schimmelbe945352016-06-09 09:51:39 +02003253 if (err)
3254 goto err_port_create;
3255 }
3256
3257 return 0;
3258
3259err_port_create:
3260 for (i--; i >= 0; i--)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003261 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3262 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmelbe945352016-06-09 09:51:39 +02003263 return err;
3264}
3265
3266static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
3267 u8 base_port, unsigned int count)
3268{
3269 u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
3270 int i;
3271
3272 /* Split by four means we need to re-create two ports, otherwise
3273 * only one.
3274 */
3275 count = count / 2;
3276
3277 for (i = 0; i < count; i++) {
3278 local_port = base_port + i * 2;
Ido Schimmelbf4e9f22017-11-21 09:42:21 +01003279 if (mlxsw_sp->port_to_module[local_port] < 0)
3280 continue;
Ido Schimmelbe945352016-06-09 09:51:39 +02003281 module = mlxsw_sp->port_to_module[local_port];
3282
Ido Schimmelbe945352016-06-09 09:51:39 +02003283 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
Ido Schimmeld664b412016-06-09 09:51:40 +02003284 width, 0);
Ido Schimmelbe945352016-06-09 09:51:39 +02003285 }
3286}
3287
Jiri Pirkob2f10572016-04-08 19:11:23 +02003288static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
3289 unsigned int count)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003290{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003291 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003292 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003293 u8 module, cur_width, base_port;
3294 int i;
3295 int err;
3296
3297 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3298 if (!mlxsw_sp_port) {
3299 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3300 local_port);
3301 return -EINVAL;
3302 }
3303
Ido Schimmeld664b412016-06-09 09:51:40 +02003304 module = mlxsw_sp_port->mapping.module;
3305 cur_width = mlxsw_sp_port->mapping.width;
3306
Ido Schimmel18f1e702016-02-26 17:32:31 +01003307 if (count != 2 && count != 4) {
3308 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
3309 return -EINVAL;
3310 }
3311
Ido Schimmel18f1e702016-02-26 17:32:31 +01003312 if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
3313 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
3314 return -EINVAL;
3315 }
3316
3317 /* Make sure we have enough slave (even) ports for the split. */
3318 if (count == 2) {
3319 base_port = local_port;
3320 if (mlxsw_sp->ports[base_port + 1]) {
3321 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3322 return -EINVAL;
3323 }
3324 } else {
3325 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3326 if (mlxsw_sp->ports[base_port + 1] ||
3327 mlxsw_sp->ports[base_port + 3]) {
3328 netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
3329 return -EINVAL;
3330 }
3331 }
3332
3333 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003334 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3335 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003336
Ido Schimmelbe945352016-06-09 09:51:39 +02003337 err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count);
3338 if (err) {
3339 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
3340 goto err_port_split_create;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003341 }
3342
3343 return 0;
3344
Ido Schimmelbe945352016-06-09 09:51:39 +02003345err_port_split_create:
3346 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003347 return err;
3348}
3349
Jiri Pirkob2f10572016-04-08 19:11:23 +02003350static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port)
Ido Schimmel18f1e702016-02-26 17:32:31 +01003351{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003352 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003353 struct mlxsw_sp_port *mlxsw_sp_port;
Ido Schimmeld664b412016-06-09 09:51:40 +02003354 u8 cur_width, base_port;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003355 unsigned int count;
3356 int i;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003357
3358 mlxsw_sp_port = mlxsw_sp->ports[local_port];
3359 if (!mlxsw_sp_port) {
3360 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
3361 local_port);
3362 return -EINVAL;
3363 }
3364
3365 if (!mlxsw_sp_port->split) {
3366 netdev_err(mlxsw_sp_port->dev, "Port wasn't split\n");
3367 return -EINVAL;
3368 }
3369
Ido Schimmeld664b412016-06-09 09:51:40 +02003370 cur_width = mlxsw_sp_port->mapping.width;
Ido Schimmel18f1e702016-02-26 17:32:31 +01003371 count = cur_width == 1 ? 4 : 2;
3372
3373 base_port = mlxsw_sp_cluster_base_port_get(local_port);
3374
3375 /* Determine which ports to remove. */
3376 if (count == 2 && local_port >= base_port + 2)
3377 base_port = base_port + 2;
3378
3379 for (i = 0; i < count; i++)
Jiri Pirkof83e2102016-10-28 21:35:49 +02003380 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i))
3381 mlxsw_sp_port_remove(mlxsw_sp, base_port + i);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003382
Ido Schimmelbe945352016-06-09 09:51:39 +02003383 mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
Ido Schimmel18f1e702016-02-26 17:32:31 +01003384
3385 return 0;
3386}
3387
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003388static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
3389 char *pude_pl, void *priv)
3390{
3391 struct mlxsw_sp *mlxsw_sp = priv;
3392 struct mlxsw_sp_port *mlxsw_sp_port;
3393 enum mlxsw_reg_pude_oper_status status;
3394 u8 local_port;
3395
3396 local_port = mlxsw_reg_pude_local_port_get(pude_pl);
3397 mlxsw_sp_port = mlxsw_sp->ports[local_port];
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003398 if (!mlxsw_sp_port)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003399 return;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003400
3401 status = mlxsw_reg_pude_oper_status_get(pude_pl);
3402 if (status == MLXSW_PORT_OPER_STATUS_UP) {
3403 netdev_info(mlxsw_sp_port->dev, "link up\n");
3404 netif_carrier_on(mlxsw_sp_port->dev);
3405 } else {
3406 netdev_info(mlxsw_sp_port->dev, "link down\n");
3407 netif_carrier_off(mlxsw_sp_port->dev);
3408 }
3409}
3410
Nogah Frankel14eeda92016-11-25 10:33:32 +01003411static void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
3412 u8 local_port, void *priv)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003413{
3414 struct mlxsw_sp *mlxsw_sp = priv;
3415 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3416 struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
3417
3418 if (unlikely(!mlxsw_sp_port)) {
3419 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
3420 local_port);
3421 return;
3422 }
3423
3424 skb->dev = mlxsw_sp_port->dev;
3425
3426 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
3427 u64_stats_update_begin(&pcpu_stats->syncp);
3428 pcpu_stats->rx_packets++;
3429 pcpu_stats->rx_bytes += skb->len;
3430 u64_stats_update_end(&pcpu_stats->syncp);
3431
3432 skb->protocol = eth_type_trans(skb, skb->dev);
3433 netif_receive_skb(skb);
3434}
3435
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003436static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
3437 void *priv)
3438{
3439 skb->offload_fwd_mark = 1;
Nogah Frankel14eeda92016-11-25 10:33:32 +01003440 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
Ido Schimmel1c6c6d22016-08-25 18:42:40 +02003441}
3442
Yotam Gigia0040c82017-10-03 09:58:10 +02003443static void mlxsw_sp_rx_listener_mr_mark_func(struct sk_buff *skb,
3444 u8 local_port, void *priv)
3445{
3446 skb->offload_mr_fwd_mark = 1;
3447 skb->offload_fwd_mark = 1;
3448 return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
3449}
3450
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003451static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
3452 void *priv)
3453{
3454 struct mlxsw_sp *mlxsw_sp = priv;
3455 struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3456 struct psample_group *psample_group;
3457 u32 size;
3458
3459 if (unlikely(!mlxsw_sp_port)) {
3460 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
3461 local_port);
3462 goto out;
3463 }
3464 if (unlikely(!mlxsw_sp_port->sample)) {
3465 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
3466 local_port);
3467 goto out;
3468 }
3469
3470 size = mlxsw_sp_port->sample->truncate ?
3471 mlxsw_sp_port->sample->trunc_size : skb->len;
3472
3473 rcu_read_lock();
3474 psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
3475 if (!psample_group)
3476 goto out_unlock;
3477 psample_sample_packet(psample_group, skb, size,
3478 mlxsw_sp_port->dev->ifindex, 0,
3479 mlxsw_sp_port->sample->rate);
3480out_unlock:
3481 rcu_read_unlock();
3482out:
3483 consume_skb(skb);
3484}
3485
Nogah Frankel117b0da2016-11-25 10:33:44 +01003486#define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel0fb78a42016-11-25 10:33:39 +01003487 MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003488 _is_ctrl, SP_##_trap_group, DISCARD)
Ido Schimmel93393b32016-08-25 18:42:38 +02003489
Nogah Frankel117b0da2016-11-25 10:33:44 +01003490#define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
Nogah Frankel14eeda92016-11-25 10:33:32 +01003491 MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action, \
Nogah Frankel117b0da2016-11-25 10:33:44 +01003492 _is_ctrl, SP_##_trap_group, DISCARD)
3493
Yotam Gigia0040c82017-10-03 09:58:10 +02003494#define MLXSW_SP_RXL_MR_MARK(_trap_id, _action, _trap_group, _is_ctrl) \
3495 MLXSW_RXL(mlxsw_sp_rx_listener_mr_mark_func, _trap_id, _action, \
3496 _is_ctrl, SP_##_trap_group, DISCARD)
3497
Nogah Frankel117b0da2016-11-25 10:33:44 +01003498#define MLXSW_SP_EVENTL(_func, _trap_id) \
3499 MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
Nogah Frankel14eeda92016-11-25 10:33:32 +01003500
Nogah Frankel45449132016-11-25 10:33:35 +01003501static const struct mlxsw_listener mlxsw_sp_listener[] = {
3502 /* Events */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003503 MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
Nogah Frankelee4a60d2016-11-25 10:33:29 +01003504 /* L2 traps */
Nogah Frankel117b0da2016-11-25 10:33:44 +01003505 MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
3506 MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
3507 MLXSW_SP_RXL_NO_MARK(LLDP, TRAP_TO_CPU, LLDP, true),
3508 MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
3509 MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
3510 MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
3511 MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
3512 MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
3513 MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
3514 MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
3515 MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
Jiri Pirko9d41acc2017-04-18 16:55:38 +02003516 MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003517 MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
3518 false),
3519 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3520 false),
3521 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
3522 false),
3523 MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
3524 false),
Ido Schimmel93393b32016-08-25 18:42:38 +02003525 /* L3 traps */
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003526 MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3527 MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
3528 MLXSW_SP_RXL_MARK(LBERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003529 MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003530 MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
3531 false),
3532 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
3533 MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
3534 MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
3535 MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
3536 false),
3537 MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
3538 MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
3539 MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
Ido Schimmel0fcc4842017-07-17 14:15:29 +02003540 MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003541 MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
3542 MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
3543 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3544 false),
3545 MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3546 false),
3547 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
3548 false),
3549 MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
3550 false),
3551 MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
3552 MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
3553 false),
3554 MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
3555 MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
Ido Schimmel7607dd32017-07-17 14:15:30 +02003556 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003557 MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
Petr Machata86484de2017-09-02 23:49:27 +02003558 MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
Yotam Gigi98d0f7b2017-01-23 11:07:11 +01003559 /* PKT Sample trap */
3560 MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
Jiri Pirko0db7b382017-06-06 14:12:05 +02003561 false, SP_IP2ME, DISCARD),
3562 /* ACL trap */
3563 MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
Yotam Gigib48cfc82017-09-19 10:00:20 +02003564 /* Multicast Router Traps */
3565 MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
3566 MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
3567 MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
Yotam Gigia0040c82017-10-03 09:58:10 +02003568 MLXSW_SP_RXL_MR_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003569};
3570
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003571static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
3572{
3573 char qpcr_pl[MLXSW_REG_QPCR_LEN];
3574 enum mlxsw_reg_qpcr_ir_units ir_units;
3575 int max_cpu_policers;
3576 bool is_bytes;
3577 u8 burst_size;
3578 u32 rate;
3579 int i, err;
3580
3581 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
3582 return -EIO;
3583
3584 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
3585
3586 ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
3587 for (i = 0; i < max_cpu_policers; i++) {
3588 is_bytes = false;
3589 switch (i) {
3590 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3591 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3592 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3593 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003594 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
3595 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003596 rate = 128;
3597 burst_size = 7;
3598 break;
3599 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003600 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003601 rate = 16 * 1024;
3602 burst_size = 10;
3603 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003604 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003605 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
3606 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003607 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003608 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3609 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003610 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003611 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003612 rate = 1024;
3613 burst_size = 7;
3614 break;
3615 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
3616 is_bytes = true;
3617 rate = 4 * 1024;
3618 burst_size = 4;
3619 break;
3620 default:
3621 continue;
3622 }
3623
3624 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
3625 burst_size);
3626 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
3627 if (err)
3628 return err;
3629 }
3630
3631 return 0;
3632}
3633
Nogah Frankel579c82e2016-11-25 10:33:42 +01003634static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003635{
3636 char htgt_pl[MLXSW_REG_HTGT_LEN];
Nogah Frankel117b0da2016-11-25 10:33:44 +01003637 enum mlxsw_reg_htgt_trap_group i;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003638 int max_cpu_policers;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003639 int max_trap_groups;
3640 u8 priority, tc;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003641 u16 policer_id;
Nogah Frankel117b0da2016-11-25 10:33:44 +01003642 int err;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003643
3644 if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
3645 return -EIO;
3646
3647 max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003648 max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003649
3650 for (i = 0; i < max_trap_groups; i++) {
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003651 policer_id = i;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003652 switch (i) {
Nogah Frankel117b0da2016-11-25 10:33:44 +01003653 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
3654 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
3655 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
3656 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003657 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003658 priority = 5;
3659 tc = 5;
3660 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003661 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003662 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
3663 priority = 4;
3664 tc = 4;
3665 break;
3666 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
3667 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
Arkadi Sharshevsky588823f2017-07-17 14:15:31 +02003668 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003669 priority = 3;
3670 tc = 3;
3671 break;
3672 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003673 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003674 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003675 priority = 2;
3676 tc = 2;
3677 break;
Arkadi Sharshevsky8d548142017-07-18 10:10:11 +02003678 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003679 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
3680 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
Yotam Gigib48cfc82017-09-19 10:00:20 +02003681 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
Nogah Frankel117b0da2016-11-25 10:33:44 +01003682 priority = 1;
3683 tc = 1;
3684 break;
3685 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
Nogah Frankel579c82e2016-11-25 10:33:42 +01003686 priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
3687 tc = MLXSW_REG_HTGT_DEFAULT_TC;
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003688 policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
Nogah Frankel579c82e2016-11-25 10:33:42 +01003689 break;
3690 default:
3691 continue;
3692 }
Nogah Frankel117b0da2016-11-25 10:33:44 +01003693
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003694 if (max_cpu_policers <= policer_id &&
3695 policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
3696 return -EIO;
3697
3698 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
Nogah Frankel579c82e2016-11-25 10:33:42 +01003699 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3700 if (err)
3701 return err;
3702 }
3703
3704 return 0;
3705}
3706
3707static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
3708{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003709 int i;
3710 int err;
3711
Nogah Frankel9148e7c2016-11-25 10:33:47 +01003712 err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
3713 if (err)
3714 return err;
3715
Nogah Frankel579c82e2016-11-25 10:33:42 +01003716 err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003717 if (err)
3718 return err;
3719
Nogah Frankel45449132016-11-25 10:33:35 +01003720 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003721 err = mlxsw_core_trap_register(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003722 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003723 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003724 if (err)
Nogah Frankel45449132016-11-25 10:33:35 +01003725 goto err_listener_register;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003726
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003727 }
3728 return 0;
3729
Nogah Frankel45449132016-11-25 10:33:35 +01003730err_listener_register:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003731 for (i--; i >= 0; i--) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003732 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003733 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003734 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003735 }
3736 return err;
3737}
3738
3739static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
3740{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003741 int i;
3742
Nogah Frankel45449132016-11-25 10:33:35 +01003743 for (i = 0; i < ARRAY_SIZE(mlxsw_sp_listener); i++) {
Nogah Frankel14eeda92016-11-25 10:33:32 +01003744 mlxsw_core_trap_unregister(mlxsw_sp->core,
Nogah Frankel45449132016-11-25 10:33:35 +01003745 &mlxsw_sp_listener[i],
Nogah Frankel14eeda92016-11-25 10:33:32 +01003746 mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003747 }
3748}
3749
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003750static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
3751{
3752 char slcr_pl[MLXSW_REG_SLCR_LEN];
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003753 int err;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003754
3755 mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
3756 MLXSW_REG_SLCR_LAG_HASH_DMAC |
3757 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
3758 MLXSW_REG_SLCR_LAG_HASH_VLANID |
3759 MLXSW_REG_SLCR_LAG_HASH_SIP |
3760 MLXSW_REG_SLCR_LAG_HASH_DIP |
3761 MLXSW_REG_SLCR_LAG_HASH_SPORT |
3762 MLXSW_REG_SLCR_LAG_HASH_DPORT |
3763 MLXSW_REG_SLCR_LAG_HASH_IPPROTO);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003764 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
3765 if (err)
3766 return err;
3767
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003768 if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
3769 !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003770 return -EIO;
3771
Jiri Pirkoc1a38312016-10-21 16:07:23 +02003772 mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003773 sizeof(struct mlxsw_sp_upper),
3774 GFP_KERNEL);
3775 if (!mlxsw_sp->lags)
3776 return -ENOMEM;
3777
3778 return 0;
3779}
3780
3781static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
3782{
3783 kfree(mlxsw_sp->lags);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003784}
3785
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003786static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
3787{
3788 char htgt_pl[MLXSW_REG_HTGT_LEN];
3789
Nogah Frankel579c82e2016-11-25 10:33:42 +01003790 mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3791 MLXSW_REG_HTGT_INVALID_POLICER,
3792 MLXSW_REG_HTGT_DEFAULT_PRIORITY,
3793 MLXSW_REG_HTGT_DEFAULT_TC);
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003794 return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
3795}
3796
Petr Machatac30f5d02017-10-16 16:26:35 +02003797static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
3798 unsigned long event, void *ptr);
3799
Jiri Pirkob2f10572016-04-08 19:11:23 +02003800static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003801 const struct mlxsw_bus_info *mlxsw_bus_info)
3802{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003803 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003804 int err;
3805
3806 mlxsw_sp->core = mlxsw_core;
3807 mlxsw_sp->bus_info = mlxsw_bus_info;
3808
Yotam Gigi6b742192017-05-23 21:56:29 +02003809 err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
3810 if (err) {
3811 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
3812 return err;
3813 }
3814
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003815 err = mlxsw_sp_base_mac_get(mlxsw_sp);
3816 if (err) {
3817 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
3818 return err;
3819 }
3820
Ido Schimmela875a2e2017-10-22 23:11:44 +02003821 err = mlxsw_sp_kvdl_init(mlxsw_sp);
3822 if (err) {
3823 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
3824 return err;
3825 }
3826
Ido Schimmela1107482017-05-26 08:37:39 +02003827 err = mlxsw_sp_fids_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003828 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003829 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
Ido Schimmela875a2e2017-10-22 23:11:44 +02003830 goto err_fids_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003831 }
3832
Ido Schimmela1107482017-05-26 08:37:39 +02003833 err = mlxsw_sp_traps_init(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003834 if (err) {
Ido Schimmela1107482017-05-26 08:37:39 +02003835 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
3836 goto err_traps_init;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003837 }
3838
3839 err = mlxsw_sp_buffers_init(mlxsw_sp);
3840 if (err) {
3841 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
3842 goto err_buffers_init;
3843 }
3844
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003845 err = mlxsw_sp_lag_init(mlxsw_sp);
3846 if (err) {
3847 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
3848 goto err_lag_init;
3849 }
3850
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003851 err = mlxsw_sp_switchdev_init(mlxsw_sp);
3852 if (err) {
3853 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
3854 goto err_switchdev_init;
3855 }
3856
Yotam Gigie2b2d352017-09-19 10:00:08 +02003857 err = mlxsw_sp_counter_pool_init(mlxsw_sp);
3858 if (err) {
3859 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
3860 goto err_counter_pool_init;
3861 }
3862
Yotam Gigid3b939b2017-09-19 10:00:09 +02003863 err = mlxsw_sp_afa_init(mlxsw_sp);
3864 if (err) {
3865 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
3866 goto err_afa_init;
3867 }
3868
Ido Schimmel464dce12016-07-02 11:00:15 +02003869 err = mlxsw_sp_router_init(mlxsw_sp);
3870 if (err) {
3871 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
3872 goto err_router_init;
3873 }
3874
Petr Machatac30f5d02017-10-16 16:26:35 +02003875 /* Initialize netdevice notifier after router is initialized, so that
3876 * the event handler can use router structures.
3877 */
3878 mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
3879 err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3880 if (err) {
3881 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
3882 goto err_netdev_notifier;
3883 }
3884
Yotam Gigi763b4b72016-07-21 12:03:17 +02003885 err = mlxsw_sp_span_init(mlxsw_sp);
3886 if (err) {
3887 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
3888 goto err_span_init;
3889 }
3890
Jiri Pirko22a67762017-02-03 10:29:07 +01003891 err = mlxsw_sp_acl_init(mlxsw_sp);
3892 if (err) {
3893 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
3894 goto err_acl_init;
3895 }
3896
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003897 err = mlxsw_sp_dpipe_init(mlxsw_sp);
3898 if (err) {
3899 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
3900 goto err_dpipe_init;
3901 }
3902
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003903 err = mlxsw_sp_ports_create(mlxsw_sp);
3904 if (err) {
3905 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
3906 goto err_ports_create;
3907 }
3908
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003909 return 0;
3910
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003911err_ports_create:
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003912 mlxsw_sp_dpipe_fini(mlxsw_sp);
3913err_dpipe_init:
Jiri Pirko22a67762017-02-03 10:29:07 +01003914 mlxsw_sp_acl_fini(mlxsw_sp);
3915err_acl_init:
Yotam Gigi763b4b72016-07-21 12:03:17 +02003916 mlxsw_sp_span_fini(mlxsw_sp);
3917err_span_init:
Petr Machatac30f5d02017-10-16 16:26:35 +02003918 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
3919err_netdev_notifier:
Ido Schimmel464dce12016-07-02 11:00:15 +02003920 mlxsw_sp_router_fini(mlxsw_sp);
3921err_router_init:
Yotam Gigid3b939b2017-09-19 10:00:09 +02003922 mlxsw_sp_afa_fini(mlxsw_sp);
3923err_afa_init:
Yotam Gigie2b2d352017-09-19 10:00:08 +02003924 mlxsw_sp_counter_pool_fini(mlxsw_sp);
3925err_counter_pool_init:
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003926 mlxsw_sp_switchdev_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003927err_switchdev_init:
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003928 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01003929err_lag_init:
Jiri Pirko0f433fa2016-04-14 18:19:24 +02003930 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003931err_buffers_init:
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003932 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003933err_traps_init:
3934 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003935err_fids_init:
3936 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003937 return err;
3938}
3939
Jiri Pirkob2f10572016-04-08 19:11:23 +02003940static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003941{
Jiri Pirkob2f10572016-04-08 19:11:23 +02003942 struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003943
Ido Schimmelbbf2a472016-07-02 11:00:14 +02003944 mlxsw_sp_ports_remove(mlxsw_sp);
Arkadi Sharshevsky230ead02017-03-28 17:24:12 +02003945 mlxsw_sp_dpipe_fini(mlxsw_sp);
Jiri Pirko22a67762017-02-03 10:29:07 +01003946 mlxsw_sp_acl_fini(mlxsw_sp);
Yotam Gigi763b4b72016-07-21 12:03:17 +02003947 mlxsw_sp_span_fini(mlxsw_sp);
Petr Machatac30f5d02017-10-16 16:26:35 +02003948 unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
Ido Schimmel464dce12016-07-02 11:00:15 +02003949 mlxsw_sp_router_fini(mlxsw_sp);
Yotam Gigid3b939b2017-09-19 10:00:09 +02003950 mlxsw_sp_afa_fini(mlxsw_sp);
Yotam Gigie2b2d352017-09-19 10:00:08 +02003951 mlxsw_sp_counter_pool_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003952 mlxsw_sp_switchdev_fini(mlxsw_sp);
Nogah Frankelce0bd2b2016-09-20 11:16:50 +02003953 mlxsw_sp_lag_fini(mlxsw_sp);
Jiri Pirko5113bfd2016-05-06 22:20:59 +02003954 mlxsw_sp_buffers_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003955 mlxsw_sp_traps_fini(mlxsw_sp);
Ido Schimmela1107482017-05-26 08:37:39 +02003956 mlxsw_sp_fids_fini(mlxsw_sp);
Ido Schimmela875a2e2017-10-22 23:11:44 +02003957 mlxsw_sp_kvdl_fini(mlxsw_sp);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003958}
3959
Bhumika Goyal159fe882017-08-11 19:10:42 +05303960static const struct mlxsw_config_profile mlxsw_sp_config_profile = {
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003961 .used_max_vepa_channels = 1,
3962 .max_vepa_channels = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003963 .used_max_mid = 1,
Elad Raz53ae6282016-01-10 21:06:26 +01003964 .max_mid = MLXSW_SP_MID_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003965 .used_max_pgt = 1,
3966 .max_pgt = 0,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003967 .used_flood_tables = 1,
3968 .used_flood_mode = 1,
3969 .flood_mode = 3,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003970 .max_fid_offset_flood_tables = 3,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003971 .fid_offset_flood_table_size = VLAN_N_VID - 1,
Nogah Frankel71c365b2017-02-09 14:54:46 +01003972 .max_fid_flood_tables = 3,
Ido Schimmela1107482017-05-26 08:37:39 +02003973 .fid_flood_table_size = MLXSW_SP_FID_8021D_MAX,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003974 .used_max_ib_mc = 1,
3975 .max_ib_mc = 0,
3976 .used_max_pkey = 1,
3977 .max_pkey = 0,
Nogah Frankel403547d2016-09-20 11:16:52 +02003978 .used_kvd_split_data = 1,
3979 .kvd_hash_granularity = MLXSW_SP_KVD_GRANULARITY,
Ido Schimmelf11fbaf2017-10-22 23:11:49 +02003980 .kvd_hash_single_parts = 59,
3981 .kvd_hash_double_parts = 41,
Jiri Pirkoc6022422016-07-05 11:27:46 +02003982 .kvd_linear_size = MLXSW_SP_KVD_LINEAR_SIZE,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003983 .swid_config = {
3984 {
3985 .used_type = 1,
3986 .type = MLXSW_PORT_SWID_TYPE_ETH,
3987 }
3988 },
Nogah Frankel57d316b2016-07-21 12:03:09 +02003989 .resource_query_enable = 1,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02003990};
3991
3992static struct mlxsw_driver mlxsw_sp_driver = {
Jiri Pirko1d20d232016-10-27 15:12:59 +02003993 .kind = mlxsw_sp_driver_name,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003994 .priv_size = sizeof(struct mlxsw_sp),
3995 .init = mlxsw_sp_init,
3996 .fini = mlxsw_sp_fini,
Nogah Frankel9d87fce2016-11-25 10:33:40 +01003997 .basic_trap_groups_set = mlxsw_sp_basic_trap_groups_set,
Jiri Pirko2d0ed392016-04-14 18:19:30 +02003998 .port_split = mlxsw_sp_port_split,
3999 .port_unsplit = mlxsw_sp_port_unsplit,
4000 .sb_pool_get = mlxsw_sp_sb_pool_get,
4001 .sb_pool_set = mlxsw_sp_sb_pool_set,
4002 .sb_port_pool_get = mlxsw_sp_sb_port_pool_get,
4003 .sb_port_pool_set = mlxsw_sp_sb_port_pool_set,
4004 .sb_tc_pool_bind_get = mlxsw_sp_sb_tc_pool_bind_get,
4005 .sb_tc_pool_bind_set = mlxsw_sp_sb_tc_pool_bind_set,
4006 .sb_occ_snapshot = mlxsw_sp_sb_occ_snapshot,
4007 .sb_occ_max_clear = mlxsw_sp_sb_occ_max_clear,
4008 .sb_occ_port_pool_get = mlxsw_sp_sb_occ_port_pool_get,
4009 .sb_occ_tc_port_bind_get = mlxsw_sp_sb_occ_tc_port_bind_get,
4010 .txhdr_construct = mlxsw_sp_txhdr_construct,
4011 .txhdr_len = MLXSW_TXHDR_LEN,
4012 .profile = &mlxsw_sp_config_profile,
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004013};
4014
Jiri Pirko22a67762017-02-03 10:29:07 +01004015bool mlxsw_sp_port_dev_check(const struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004016{
4017 return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
4018}
4019
Jiri Pirko1182e532017-03-06 21:25:20 +01004020static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
David Aherndd823642016-10-17 19:15:49 -07004021{
Jiri Pirko1182e532017-03-06 21:25:20 +01004022 struct mlxsw_sp_port **p_mlxsw_sp_port = data;
David Aherndd823642016-10-17 19:15:49 -07004023 int ret = 0;
4024
4025 if (mlxsw_sp_port_dev_check(lower_dev)) {
Jiri Pirko1182e532017-03-06 21:25:20 +01004026 *p_mlxsw_sp_port = netdev_priv(lower_dev);
David Aherndd823642016-10-17 19:15:49 -07004027 ret = 1;
4028 }
4029
4030 return ret;
4031}
4032
Ido Schimmelc57529e2017-05-26 08:37:31 +02004033struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004034{
Jiri Pirko1182e532017-03-06 21:25:20 +01004035 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004036
4037 if (mlxsw_sp_port_dev_check(dev))
4038 return netdev_priv(dev);
4039
Jiri Pirko1182e532017-03-06 21:25:20 +01004040 mlxsw_sp_port = NULL;
4041 netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004042
Jiri Pirko1182e532017-03-06 21:25:20 +01004043 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004044}
4045
Ido Schimmel4724ba562017-03-10 08:53:39 +01004046struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004047{
4048 struct mlxsw_sp_port *mlxsw_sp_port;
4049
4050 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
4051 return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
4052}
4053
Arkadi Sharshevskyaf0613782017-06-08 08:44:20 +02004054struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004055{
Jiri Pirko1182e532017-03-06 21:25:20 +01004056 struct mlxsw_sp_port *mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004057
4058 if (mlxsw_sp_port_dev_check(dev))
4059 return netdev_priv(dev);
4060
Jiri Pirko1182e532017-03-06 21:25:20 +01004061 mlxsw_sp_port = NULL;
4062 netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
4063 &mlxsw_sp_port);
David Aherndd823642016-10-17 19:15:49 -07004064
Jiri Pirko1182e532017-03-06 21:25:20 +01004065 return mlxsw_sp_port;
Jiri Pirko7ce856a2016-07-04 08:23:12 +02004066}
4067
4068struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
4069{
4070 struct mlxsw_sp_port *mlxsw_sp_port;
4071
4072 rcu_read_lock();
4073 mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
4074 if (mlxsw_sp_port)
4075 dev_hold(mlxsw_sp_port->dev);
4076 rcu_read_unlock();
4077 return mlxsw_sp_port;
4078}
4079
4080void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
4081{
4082 dev_put(mlxsw_sp_port->dev);
4083}
4084
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004085static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004086{
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004087 char sldr_pl[MLXSW_REG_SLDR_LEN];
4088
4089 mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
4090 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4091}
4092
4093static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
4094{
4095 char sldr_pl[MLXSW_REG_SLDR_LEN];
4096
4097 mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
4098 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4099}
4100
4101static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4102 u16 lag_id, u8 port_index)
4103{
4104 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4105 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4106
4107 mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
4108 lag_id, port_index);
4109 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4110}
4111
4112static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4113 u16 lag_id)
4114{
4115 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4116 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4117
4118 mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
4119 lag_id);
4120 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4121}
4122
4123static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
4124 u16 lag_id)
4125{
4126 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4127 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4128
4129 mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
4130 lag_id);
4131 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4132}
4133
4134static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
4135 u16 lag_id)
4136{
4137 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4138 char slcor_pl[MLXSW_REG_SLCOR_LEN];
4139
4140 mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
4141 lag_id);
4142 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
4143}
4144
4145static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4146 struct net_device *lag_dev,
4147 u16 *p_lag_id)
4148{
4149 struct mlxsw_sp_upper *lag;
4150 int free_lag_id = -1;
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004151 u64 max_lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004152 int i;
4153
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004154 max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
4155 for (i = 0; i < max_lag; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004156 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
4157 if (lag->ref_count) {
4158 if (lag->dev == lag_dev) {
4159 *p_lag_id = i;
4160 return 0;
4161 }
4162 } else if (free_lag_id < 0) {
4163 free_lag_id = i;
4164 }
4165 }
4166 if (free_lag_id < 0)
4167 return -EBUSY;
4168 *p_lag_id = free_lag_id;
4169 return 0;
4170}
4171
4172static bool
4173mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
4174 struct net_device *lag_dev,
David Aherne58376e2017-10-04 17:48:51 -07004175 struct netdev_lag_upper_info *lag_upper_info,
4176 struct netlink_ext_ack *extack)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004177{
4178 u16 lag_id;
4179
David Aherne58376e2017-10-04 17:48:51 -07004180 if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
4181 NL_SET_ERR_MSG(extack,
4182 "spectrum: Exceeded number of supported LAG devices");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004183 return false;
David Aherne58376e2017-10-04 17:48:51 -07004184 }
4185 if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
4186 NL_SET_ERR_MSG(extack,
4187 "spectrum: LAG device using unsupported Tx type");
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004188 return false;
David Aherne58376e2017-10-04 17:48:51 -07004189 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004190 return true;
4191}
4192
4193static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
4194 u16 lag_id, u8 *p_port_index)
4195{
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004196 u64 max_lag_members;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004197 int i;
4198
Jiri Pirkoc1a38312016-10-21 16:07:23 +02004199 max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
4200 MAX_LAG_MEMBERS);
4201 for (i = 0; i < max_lag_members; i++) {
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004202 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
4203 *p_port_index = i;
4204 return 0;
4205 }
4206 }
4207 return -EBUSY;
4208}
4209
4210static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
4211 struct net_device *lag_dev)
4212{
4213 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004214 struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004215 struct mlxsw_sp_upper *lag;
4216 u16 lag_id;
4217 u8 port_index;
4218 int err;
4219
4220 err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
4221 if (err)
4222 return err;
4223 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4224 if (!lag->ref_count) {
4225 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
4226 if (err)
4227 return err;
4228 lag->dev = lag_dev;
4229 }
4230
4231 err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
4232 if (err)
4233 return err;
4234 err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
4235 if (err)
4236 goto err_col_port_add;
4237 err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port, lag_id);
4238 if (err)
4239 goto err_col_port_enable;
4240
4241 mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
4242 mlxsw_sp_port->local_port);
4243 mlxsw_sp_port->lag_id = lag_id;
4244 mlxsw_sp_port->lagged = 1;
4245 lag->ref_count++;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004246
Ido Schimmelc57529e2017-05-26 08:37:31 +02004247 /* Port is no longer usable as a router interface */
4248 mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, 1);
4249 if (mlxsw_sp_port_vlan->fid)
Ido Schimmela1107482017-05-26 08:37:39 +02004250 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004251
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004252 return 0;
4253
Ido Schimmel51554db2016-05-06 22:18:39 +02004254err_col_port_enable:
4255 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004256err_col_port_add:
4257 if (!lag->ref_count)
4258 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004259 return err;
4260}
4261
Ido Schimmel82e6db02016-06-20 23:04:04 +02004262static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
4263 struct net_device *lag_dev)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004264{
4265 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004266 u16 lag_id = mlxsw_sp_port->lag_id;
Ido Schimmel1c800752016-06-20 23:04:20 +02004267 struct mlxsw_sp_upper *lag;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004268
4269 if (!mlxsw_sp_port->lagged)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004270 return;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004271 lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
4272 WARN_ON(lag->ref_count == 0);
4273
Ido Schimmel82e6db02016-06-20 23:04:04 +02004274 mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, lag_id);
4275 mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004276
Ido Schimmelc57529e2017-05-26 08:37:31 +02004277 /* Any VLANs configured on the port are no longer valid */
4278 mlxsw_sp_port_vlan_flush(mlxsw_sp_port);
Ido Schimmel4dc236c2016-01-27 15:20:16 +01004279
Ido Schimmelfe3f6d12016-06-20 23:04:19 +02004280 if (lag->ref_count == 1)
Ido Schimmel82e6db02016-06-20 23:04:04 +02004281 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004282
4283 mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
4284 mlxsw_sp_port->local_port);
4285 mlxsw_sp_port->lagged = 0;
4286 lag->ref_count--;
Ido Schimmel86bf95b2016-07-02 11:00:11 +02004287
Ido Schimmelc57529e2017-05-26 08:37:31 +02004288 mlxsw_sp_port_vlan_get(mlxsw_sp_port, 1);
4289 /* Make sure untagged frames are allowed to ingress */
4290 mlxsw_sp_port_pvid_set(mlxsw_sp_port, 1);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004291}
4292
Jiri Pirko74581202015-12-03 12:12:30 +01004293static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
4294 u16 lag_id)
4295{
4296 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4297 char sldr_pl[MLXSW_REG_SLDR_LEN];
4298
4299 mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
4300 mlxsw_sp_port->local_port);
4301 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4302}
4303
4304static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
4305 u16 lag_id)
4306{
4307 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4308 char sldr_pl[MLXSW_REG_SLDR_LEN];
4309
4310 mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
4311 mlxsw_sp_port->local_port);
4312 return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
4313}
4314
4315static int mlxsw_sp_port_lag_tx_en_set(struct mlxsw_sp_port *mlxsw_sp_port,
4316 bool lag_tx_enabled)
4317{
4318 if (lag_tx_enabled)
4319 return mlxsw_sp_lag_dist_port_add(mlxsw_sp_port,
4320 mlxsw_sp_port->lag_id);
4321 else
4322 return mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
4323 mlxsw_sp_port->lag_id);
4324}
4325
4326static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
4327 struct netdev_lag_lower_state_info *info)
4328{
4329 return mlxsw_sp_port_lag_tx_en_set(mlxsw_sp_port, info->tx_enabled);
4330}
4331
Jiri Pirko2b94e582017-04-18 16:55:37 +02004332static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
4333 bool enable)
4334{
4335 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4336 enum mlxsw_reg_spms_state spms_state;
4337 char *spms_pl;
4338 u16 vid;
4339 int err;
4340
4341 spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
4342 MLXSW_REG_SPMS_STATE_DISCARDING;
4343
4344 spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
4345 if (!spms_pl)
4346 return -ENOMEM;
4347 mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
4348
4349 for (vid = 0; vid < VLAN_N_VID; vid++)
4350 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
4351
4352 err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
4353 kfree(spms_pl);
4354 return err;
4355}
4356
4357static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
4358{
Yuval Mintzfccff082017-12-15 08:44:21 +01004359 u16 vid = 1;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004360 int err;
4361
Ido Schimmel4aafc362017-05-26 08:37:25 +02004362 err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004363 if (err)
4364 return err;
Ido Schimmel4aafc362017-05-26 08:37:25 +02004365 err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
4366 if (err)
4367 goto err_port_stp_set;
Jiri Pirko2b94e582017-04-18 16:55:37 +02004368 err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4369 true, false);
4370 if (err)
4371 goto err_port_vlan_set;
Yuval Mintzfccff082017-12-15 08:44:21 +01004372
4373 for (; vid <= VLAN_N_VID - 1; vid++) {
4374 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4375 vid, false);
4376 if (err)
4377 goto err_vid_learning_set;
4378 }
4379
Jiri Pirko2b94e582017-04-18 16:55:37 +02004380 return 0;
4381
Yuval Mintzfccff082017-12-15 08:44:21 +01004382err_vid_learning_set:
4383 for (vid--; vid >= 1; vid--)
4384 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004385err_port_vlan_set:
4386 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004387err_port_stp_set:
4388 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004389 return err;
4390}
4391
4392static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
4393{
Yuval Mintzfccff082017-12-15 08:44:21 +01004394 u16 vid;
4395
4396 for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
4397 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
4398 vid, true);
4399
Jiri Pirko2b94e582017-04-18 16:55:37 +02004400 mlxsw_sp_port_vlan_set(mlxsw_sp_port, 2, VLAN_N_VID - 1,
4401 false, false);
4402 mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
Ido Schimmel4aafc362017-05-26 08:37:25 +02004403 mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004404}
4405
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004406static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
4407 struct net_device *dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004408 unsigned long event, void *ptr)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004409{
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004410 struct netdev_notifier_changeupper_info *info;
4411 struct mlxsw_sp_port *mlxsw_sp_port;
David Aherne58376e2017-10-04 17:48:51 -07004412 struct netlink_ext_ack *extack;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004413 struct net_device *upper_dev;
4414 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004415 int err = 0;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004416
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004417 mlxsw_sp_port = netdev_priv(dev);
4418 mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
4419 info = ptr;
David Aherne58376e2017-10-04 17:48:51 -07004420 extack = netdev_notifier_info_to_extack(&info->info);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004421
4422 switch (event) {
4423 case NETDEV_PRECHANGEUPPER:
4424 upper_dev = info->upper_dev;
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004425 if (!is_vlan_dev(upper_dev) &&
4426 !netif_is_lag_master(upper_dev) &&
Ido Schimmel7179eb52017-03-16 09:08:18 +01004427 !netif_is_bridge_master(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004428 !netif_is_ovs_master(upper_dev)) {
4429 NL_SET_ERR_MSG(extack,
4430 "spectrum: Unknown upper device type");
Ido Schimmel59fe9b32016-06-20 23:04:00 +02004431 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004432 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004433 if (!info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004434 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004435 if (netdev_has_any_upper_dev(upper_dev) &&
4436 (!netif_is_bridge_master(upper_dev) ||
4437 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4438 upper_dev))) {
David Aherne58376e2017-10-04 17:48:51 -07004439 NL_SET_ERR_MSG(extack,
4440 "spectrum: Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004441 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004442 }
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004443 if (netif_is_lag_master(upper_dev) &&
4444 !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
David Aherne58376e2017-10-04 17:48:51 -07004445 info->upper_info, extack))
Ido Schimmel80bedf12016-06-20 23:03:59 +02004446 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004447 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
4448 NL_SET_ERR_MSG(extack,
4449 "spectrum: Master device is a LAG master and this device has a VLAN");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004450 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004451 }
Ido Schimmel6ec43902016-06-20 23:04:01 +02004452 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
David Aherne58376e2017-10-04 17:48:51 -07004453 !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
4454 NL_SET_ERR_MSG(extack,
4455 "spectrum: Can not put a VLAN on a LAG port");
Ido Schimmel6ec43902016-06-20 23:04:01 +02004456 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004457 }
4458 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
4459 NL_SET_ERR_MSG(extack,
4460 "spectrum: Master device is an OVS master and this device has a VLAN");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004461 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004462 }
4463 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
4464 NL_SET_ERR_MSG(extack,
4465 "spectrum: Can not put a VLAN on an OVS port");
Jiri Pirko2b94e582017-04-18 16:55:37 +02004466 return -EINVAL;
David Aherne58376e2017-10-04 17:48:51 -07004467 }
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004468 break;
4469 case NETDEV_CHANGEUPPER:
4470 upper_dev = info->upper_dev;
Ido Schimmelc57529e2017-05-26 08:37:31 +02004471 if (netif_is_bridge_master(upper_dev)) {
Ido Schimmel7117a572016-06-20 23:04:06 +02004472 if (info->linking)
4473 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004474 lower_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004475 upper_dev,
4476 extack);
Ido Schimmel7117a572016-06-20 23:04:06 +02004477 else
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004478 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4479 lower_dev,
4480 upper_dev);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004481 } else if (netif_is_lag_master(upper_dev)) {
Ido Schimmel80bedf12016-06-20 23:03:59 +02004482 if (info->linking)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004483 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
4484 upper_dev);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004485 else
Ido Schimmel82e6db02016-06-20 23:04:04 +02004486 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
4487 upper_dev);
Jiri Pirko2b94e582017-04-18 16:55:37 +02004488 } else if (netif_is_ovs_master(upper_dev)) {
4489 if (info->linking)
4490 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
4491 else
4492 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004493 }
4494 break;
4495 }
4496
Ido Schimmel80bedf12016-06-20 23:03:59 +02004497 return err;
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004498}
4499
Jiri Pirko74581202015-12-03 12:12:30 +01004500static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
4501 unsigned long event, void *ptr)
4502{
4503 struct netdev_notifier_changelowerstate_info *info;
4504 struct mlxsw_sp_port *mlxsw_sp_port;
4505 int err;
4506
4507 mlxsw_sp_port = netdev_priv(dev);
4508 info = ptr;
4509
4510 switch (event) {
4511 case NETDEV_CHANGELOWERSTATE:
4512 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
4513 err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
4514 info->lower_state_info);
4515 if (err)
4516 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
4517 }
4518 break;
4519 }
4520
Ido Schimmel80bedf12016-06-20 23:03:59 +02004521 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004522}
4523
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004524static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
4525 struct net_device *port_dev,
Jiri Pirko74581202015-12-03 12:12:30 +01004526 unsigned long event, void *ptr)
4527{
4528 switch (event) {
4529 case NETDEV_PRECHANGEUPPER:
4530 case NETDEV_CHANGEUPPER:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004531 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
4532 event, ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004533 case NETDEV_CHANGELOWERSTATE:
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004534 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
4535 ptr);
Jiri Pirko74581202015-12-03 12:12:30 +01004536 }
4537
Ido Schimmel80bedf12016-06-20 23:03:59 +02004538 return 0;
Jiri Pirko74581202015-12-03 12:12:30 +01004539}
4540
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004541static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
4542 unsigned long event, void *ptr)
4543{
4544 struct net_device *dev;
4545 struct list_head *iter;
4546 int ret;
4547
4548 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4549 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004550 ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
4551 ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004552 if (ret)
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004553 return ret;
4554 }
4555 }
4556
Ido Schimmel80bedf12016-06-20 23:03:59 +02004557 return 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004558}
4559
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004560static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
4561 struct net_device *dev,
4562 unsigned long event, void *ptr,
4563 u16 vid)
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004564{
4565 struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
Ido Schimmel90045fc2017-12-25 09:05:33 +01004566 struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004567 struct netdev_notifier_changeupper_info *info = ptr;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004568 struct netlink_ext_ack *extack;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004569 struct net_device *upper_dev;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004570 int err = 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004571
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004572 extack = netdev_notifier_info_to_extack(&info->info);
4573
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004574 switch (event) {
4575 case NETDEV_PRECHANGEUPPER:
4576 upper_dev = info->upper_dev;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004577 if (!netif_is_bridge_master(upper_dev)) {
4578 NL_SET_ERR_MSG(extack, "spectrum: VLAN devices only support bridge and VRF uppers");
Ido Schimmel80bedf12016-06-20 23:03:59 +02004579 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004580 }
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004581 if (!info->linking)
4582 break;
Ido Schimmel90045fc2017-12-25 09:05:33 +01004583 if (netdev_has_any_upper_dev(upper_dev) &&
4584 (!netif_is_bridge_master(upper_dev) ||
4585 !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
4586 upper_dev))) {
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004587 NL_SET_ERR_MSG(extack, "spectrum: Enslaving a port to a device that already has an upper device is not supported");
Ido Schimmel25cc72a2017-09-01 10:52:31 +02004588 return -EINVAL;
Ido Schimmelc1f2c6d2017-10-08 11:57:55 +02004589 }
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004590 break;
4591 case NETDEV_CHANGEUPPER:
4592 upper_dev = info->upper_dev;
Ido Schimmel1f880612017-03-10 08:53:35 +01004593 if (netif_is_bridge_master(upper_dev)) {
4594 if (info->linking)
Ido Schimmelc57529e2017-05-26 08:37:31 +02004595 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
4596 vlan_dev,
Ido Schimmel9b63ef882017-10-08 11:57:56 +02004597 upper_dev,
4598 extack);
Ido Schimmel1f880612017-03-10 08:53:35 +01004599 else
Ido Schimmelc57529e2017-05-26 08:37:31 +02004600 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
4601 vlan_dev,
4602 upper_dev);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004603 } else {
Ido Schimmel1f880612017-03-10 08:53:35 +01004604 err = -EINVAL;
4605 WARN_ON(1);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004606 }
Ido Schimmel1f880612017-03-10 08:53:35 +01004607 break;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004608 }
4609
Ido Schimmel80bedf12016-06-20 23:03:59 +02004610 return err;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004611}
4612
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004613static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
4614 struct net_device *lag_dev,
4615 unsigned long event,
4616 void *ptr, u16 vid)
Ido Schimmel272c4472015-12-15 16:03:47 +01004617{
4618 struct net_device *dev;
4619 struct list_head *iter;
4620 int ret;
4621
4622 netdev_for_each_lower_dev(lag_dev, dev, iter) {
4623 if (mlxsw_sp_port_dev_check(dev)) {
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004624 ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
4625 event, ptr,
4626 vid);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004627 if (ret)
Ido Schimmel272c4472015-12-15 16:03:47 +01004628 return ret;
4629 }
4630 }
4631
Ido Schimmel80bedf12016-06-20 23:03:59 +02004632 return 0;
Ido Schimmel272c4472015-12-15 16:03:47 +01004633}
4634
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004635static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
4636 unsigned long event, void *ptr)
4637{
4638 struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
4639 u16 vid = vlan_dev_vlan_id(vlan_dev);
4640
Ido Schimmel272c4472015-12-15 16:03:47 +01004641 if (mlxsw_sp_port_dev_check(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004642 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
4643 event, ptr, vid);
Ido Schimmel272c4472015-12-15 16:03:47 +01004644 else if (netif_is_lag_master(real_dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004645 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
4646 real_dev, event,
4647 ptr, vid);
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004648
Ido Schimmel80bedf12016-06-20 23:03:59 +02004649 return 0;
Ido Schimmel26f0e7f2015-12-15 16:03:44 +01004650}
4651
Ido Schimmelb1e45522017-04-30 19:47:14 +03004652static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
4653{
4654 struct netdev_notifier_changeupper_info *info = ptr;
4655
4656 if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
4657 return false;
4658 return netif_is_l3_master(info->upper_dev);
4659}
4660
Petr Machata00635872017-10-16 16:26:37 +02004661static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004662 unsigned long event, void *ptr)
4663{
4664 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
Petr Machata00635872017-10-16 16:26:37 +02004665 struct mlxsw_sp *mlxsw_sp;
Ido Schimmel80bedf12016-06-20 23:03:59 +02004666 int err = 0;
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004667
Petr Machata00635872017-10-16 16:26:37 +02004668 mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
Petr Machata796ec772017-11-03 10:03:29 +01004669 if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
4670 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
4671 event, ptr);
Petr Machata61481f22017-11-03 10:03:41 +01004672 else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
4673 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
4674 event, ptr);
Petr Machata00635872017-10-16 16:26:37 +02004675 else if (event == NETDEV_CHANGEADDR || event == NETDEV_CHANGEMTU)
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004676 err = mlxsw_sp_netdevice_router_port_event(dev);
Ido Schimmelb1e45522017-04-30 19:47:14 +03004677 else if (mlxsw_sp_is_vrf_event(event, ptr))
4678 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
Ido Schimmel6e095fd2016-07-04 08:23:13 +02004679 else if (mlxsw_sp_port_dev_check(dev))
Ido Schimmelf0cebd82017-05-26 08:37:29 +02004680 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
Ido Schimmel80bedf12016-06-20 23:03:59 +02004681 else if (netif_is_lag_master(dev))
4682 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
4683 else if (is_vlan_dev(dev))
4684 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004685
Ido Schimmel80bedf12016-06-20 23:03:59 +02004686 return notifier_from_errno(err);
Jiri Pirko0d65fc12015-12-03 12:12:28 +01004687}
4688
David Ahern89d5dd22017-10-18 09:56:55 -07004689static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
4690 .notifier_call = mlxsw_sp_inetaddr_valid_event,
4691};
4692
Ido Schimmel99724c12016-07-04 08:23:14 +02004693static struct notifier_block mlxsw_sp_inetaddr_nb __read_mostly = {
4694 .notifier_call = mlxsw_sp_inetaddr_event,
David Ahern89d5dd22017-10-18 09:56:55 -07004695};
4696
4697static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
4698 .notifier_call = mlxsw_sp_inet6addr_valid_event,
Ido Schimmel99724c12016-07-04 08:23:14 +02004699};
4700
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004701static struct notifier_block mlxsw_sp_inet6addr_nb __read_mostly = {
4702 .notifier_call = mlxsw_sp_inet6addr_event,
4703};
4704
Jiri Pirko1d20d232016-10-27 15:12:59 +02004705static const struct pci_device_id mlxsw_sp_pci_id_table[] = {
4706 {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
4707 {0, },
4708};
4709
4710static struct pci_driver mlxsw_sp_pci_driver = {
4711 .name = mlxsw_sp_driver_name,
4712 .id_table = mlxsw_sp_pci_id_table,
4713};
4714
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004715static int __init mlxsw_sp_module_init(void)
4716{
4717 int err;
4718
David Ahern89d5dd22017-10-18 09:56:55 -07004719 register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004720 register_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004721 register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004722 register_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
Jiri Pirkoe7322632016-09-01 10:37:43 +02004723
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004724 err = mlxsw_core_driver_register(&mlxsw_sp_driver);
4725 if (err)
4726 goto err_core_driver_register;
Jiri Pirko1d20d232016-10-27 15:12:59 +02004727
4728 err = mlxsw_pci_driver_register(&mlxsw_sp_pci_driver);
4729 if (err)
4730 goto err_pci_driver_register;
4731
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004732 return 0;
4733
Jiri Pirko1d20d232016-10-27 15:12:59 +02004734err_pci_driver_register:
4735 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004736err_core_driver_register:
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004737 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004738 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Jiri Pirkode7d6292016-09-01 10:37:42 +02004739 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004740 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004741 return err;
4742}
4743
4744static void __exit mlxsw_sp_module_exit(void)
4745{
Jiri Pirko1d20d232016-10-27 15:12:59 +02004746 mlxsw_pci_driver_unregister(&mlxsw_sp_pci_driver);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004747 mlxsw_core_driver_unregister(&mlxsw_sp_driver);
Arkadi Sharshevsky5ea12372017-07-18 10:10:13 +02004748 unregister_inet6addr_notifier(&mlxsw_sp_inet6addr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004749 unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
Ido Schimmel99724c12016-07-04 08:23:14 +02004750 unregister_inetaddr_notifier(&mlxsw_sp_inetaddr_nb);
David Ahern89d5dd22017-10-18 09:56:55 -07004751 unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
Jiri Pirko56ade8f2015-10-16 14:01:37 +02004752}
4753
4754module_init(mlxsw_sp_module_init);
4755module_exit(mlxsw_sp_module_exit);
4756
4757MODULE_LICENSE("Dual BSD/GPL");
4758MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
4759MODULE_DESCRIPTION("Mellanox Spectrum driver");
Jiri Pirko1d20d232016-10-27 15:12:59 +02004760MODULE_DEVICE_TABLE(pci, mlxsw_sp_pci_id_table);
Yotam Gigi6b742192017-05-23 21:56:29 +02004761MODULE_FIRMWARE(MLXSW_SP_FW_FILENAME);